diff --git a/.github/ISSUE_TEMPLATE.md b/.github/ISSUE_TEMPLATE.md new file mode 100644 index 0000000000..5b85dc2d0f --- /dev/null +++ b/.github/ISSUE_TEMPLATE.md @@ -0,0 +1,3 @@ + + + diff --git a/.github/workflows/action.yml b/.github/workflows/action.yml index ecbc19cca9..2959a63c07 100644 --- a/.github/workflows/action.yml +++ b/.github/workflows/action.yml @@ -82,6 +82,7 @@ jobs: - {RTT_BSP: "stm32/stm32f401-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32f405-smdz-breadfruit", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32f407-atk-explorer", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32f407-robomaster-c", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32f407-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32f410-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32f411-atk-nano", RTT_TOOL_CHAIN: "sourcery-arm"} @@ -149,10 +150,10 @@ jobs: if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-arm' && success() }} shell: bash run: | - wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/arm-2017q2-v6/gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 - sudo tar xjf gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 -C /opt - /opt/gcc-arm-none-eabi-6-2017-q2-update/bin/arm-none-eabi-gcc --version - echo "RTT_EXEC_PATH=/opt/gcc-arm-none-eabi-6-2017-q2-update/bin" >> $GITHUB_ENV + wget -q https://developer.arm.com/-/media/Files/downloads/gnu-rm/10-2020q4/gcc-arm-none-eabi-10-2020-q4-major-x86_64-linux.tar.bz2 + sudo tar xjf gcc-arm-none-eabi-10-2020-q4-major-x86_64-linux.tar.bz2 -C /opt + /opt/gcc-arm-none-eabi-10-2020-q4-major/bin/arm-none-eabi-gcc --version + echo "RTT_EXEC_PATH=/opt/gcc-arm-none-eabi-10-2020-q4-major/bin" >> $GITHUB_ENV - name: Install Mips ToolChains if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-mips' && success() }} diff --git a/.github/workflows/action_utest.yml b/.github/workflows/action_utest.yml index b8fea056e1..7d0e2c44d8 100644 --- a/.github/workflows/action_utest.yml +++ b/.github/workflows/action_utest.yml @@ -11,33 +11,60 @@ jobs: fail-fast: false matrix: legs: - - {UTEST: "kernel/ipc", RTT_BSP: "bsp/qemu-vexpress-a9", QEMU_ARCH: "vexpress-a9", CONFIG_FILE: "examples/utest/configs/utest_self/config.h"} - - {UTEST: "components/utest", RTT_BSP: "bsp/qemu-vexpress-a9", QEMU_ARCH: "vexpress-a9", CONFIG_FILE: "examples/utest/configs/utest_self/config.h"} - + - {UTEST: "kernel/mem", RTT_BSP: "bsp/qemu-vexpress-a9", QEMU_ARCH: "arm", QEMU_MACHINE: "vexpress-a9", CONFIG_FILE: "kernel/mem.conf", SD_FILE: "sd.bin"} + - {UTEST: "components/utest", RTT_BSP: "bsp/qemu-vexpress-a9", QEMU_ARCH: "arm", QEMU_MACHINE: "vexpress-a9", CONFIG_FILE: "utest_self/self.conf", SD_FILE: "sd.bin"} + - {UTEST: "kernel/mem/riscv64", RTT_BSP: "bsp/qemu-riscv-virt64", QEMU_ARCH: "riscv64", QEMU_MACHINE: "virt", CONFIG_FILE: "kernel/mem.conf", SD_FILE: "None"} env: + TEST_QEMU_ARCH: ${{ matrix.legs.QEMU_ARCH }} + TEST_QEMU_MACHINE: ${{ matrix.legs.QEMU_MACHINE }} TEST_BSP_ROOT: ${{ matrix.legs.RTT_BSP }} TEST_CONFIG_FILE: ${{ matrix.legs.CONFIG_FILE }} + TEST_SD_FILE: ${{ matrix.legs.SD_FILE }} steps: - uses: actions/checkout@v1 - - name: Prepare env + + - name: Install Tools + shell: bash run: | - sudo apt-get update > /dev/null - sudo apt-get -yqq install scons qemu-system-arm git - wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/arm-2017q2-v6/gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 - sudo tar xjf gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 -C /opt - - name: Build bsp + sudo apt-get update + sudo apt-get -yqq install scons qemu-system git + + - name: Install Arm ToolChains + if: ${{ matrix.legs.QEMU_ARCH == 'arm' && success() }} + shell: bash run: | - export RTT_EXEC_PATH=/opt/gcc-arm-none-eabi-6-2017-q2-update/bin - /opt/gcc-arm-none-eabi-6-2017-q2-update/bin/arm-none-eabi-gcc --version - cp $TEST_CONFIG_FILE $TEST_BSP_ROOT/rtconfig.h + wget -q https://developer.arm.com/-/media/Files/downloads/gnu-rm/10-2020q4/gcc-arm-none-eabi-10-2020-q4-major-x86_64-linux.tar.bz2 + sudo tar xjf gcc-arm-none-eabi-10-2020-q4-major-x86_64-linux.tar.bz2 -C /opt + /opt/gcc-arm-none-eabi-10-2020-q4-major/bin/arm-none-eabi-gcc --version + echo "RTT_EXEC_PATH=/opt/gcc-arm-none-eabi-10-2020-q4-major/bin" >> $GITHUB_ENV + + - name: Install RISC-V ToolChains + if: ${{ matrix.legs.QEMU_ARCH == 'riscv64' && success() }} + run: | + wget -q https://static.dev.sifive.com/dev-tools/freedom-tools/v2020.12/riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14.tar.gz + sudo tar zxvf riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14.tar.gz -C /opt + /opt/riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14/bin/riscv64-unknown-elf-gcc --version + echo "RTT_EXEC_PATH=/opt/riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14/bin" >> $GITHUB_ENV + + - name: Build BSP + run: | + echo CONFIG_RT_USING_UTESTCASES=y >> $TEST_BSP_ROOT/.config + cat examples/utest/configs/$TEST_CONFIG_FILE >> $TEST_BSP_ROOT/.config + scons --pyconfig-silent -C $TEST_BSP_ROOT scons -j$(nproc) -C $TEST_BSP_ROOT - - name: Start test + + - name: Start Test + if: ${{ success() }} run: | git clone https://github.com/armink/UtestRunner.git pushd $TEST_BSP_ROOT dd if=/dev/zero of=sd.bin bs=1024 count=65536 popd pushd UtestRunner - python3 qemu_runner.py --elf ../$TEST_BSP_ROOT/rtthread.elf --sd ../$TEST_BSP_ROOT/sd.bin + if [ $TEST_SD_FILE != "None" ]; then + python3 qemu_runner.py --system $TEST_QEMU_ARCH --machine $TEST_QEMU_MACHINE --elf ../$TEST_BSP_ROOT/rtthread.elf --sd ../$TEST_BSP_ROOT/$TEST_SD_FILE + else + python3 qemu_runner.py --system $TEST_QEMU_ARCH --machine $TEST_QEMU_MACHINE --elf ../$TEST_BSP_ROOT/rtthread.elf + fi cat rtt_console.log - popd + popd \ No newline at end of file diff --git a/.ignore_format.yml b/.ignore_format.yml index 5af47eedd4..1aa68c35d1 100644 --- a/.ignore_format.yml +++ b/.ignore_format.yml @@ -9,4 +9,5 @@ dir_path: - tools - components/net/lwip-1.4.1 - components/net/lwip-2.0.2 +- components/net/lwip-2.0.3 - components/net/lwip-2.1.2 \ No newline at end of file diff --git a/bsp/CME_M7/rtconfig.h b/bsp/CME_M7/rtconfig.h index a16dddf4d9..81d7c22eb4 100644 --- a/bsp/CME_M7/rtconfig.h +++ b/bsp/CME_M7/rtconfig.h @@ -91,6 +91,7 @@ /* SECTION: lwip, a lighwight TCP/IP protocol stack */ #define RT_USING_LWIP +#define RT_USING_LWIP203 /* Enable ICMP protocol*/ #define RT_LWIP_ICMP /* Enable UDP protocol*/ diff --git a/bsp/bluetrum/ab32vg1-ab-prougen/.config b/bsp/bluetrum/ab32vg1-ab-prougen/.config index 097f9df54c..898a04fc6b 100644 --- a/bsp/bluetrum/ab32vg1-ab-prougen/.config +++ b/bsp/bluetrum/ab32vg1-ab-prougen/.config @@ -122,6 +122,8 @@ CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 # CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set # CONFIG_RT_SERIAL_USING_DMA is not set CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_CAN is not set @@ -197,6 +199,7 @@ CONFIG_RT_LIBC_FIXED_TIMEZONE=8 # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_RT_LINK is not set # # RT-Thread Utestcases @@ -320,6 +323,8 @@ CONFIG_RT_LIBC_FIXED_TIMEZONE=8 # CONFIG_PKG_USING_AZUREGUIX is not set # CONFIG_PKG_USING_TOUCHGFX2RTT is not set # CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set # # tools packages @@ -328,6 +333,7 @@ CONFIG_RT_LIBC_FIXED_TIMEZONE=8 # CONFIG_PKG_USING_EASYFLASH is not set # CONFIG_PKG_USING_EASYLOGGER is not set # CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set # CONFIG_PKG_USING_RDB is not set # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_ULOG_EASYFLASH is not set @@ -365,6 +371,24 @@ CONFIG_RT_LIBC_FIXED_TIMEZONE=8 # # system packages # + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set # CONFIG_PKG_USING_GUIENGINE is not set # CONFIG_PKG_USING_CAIRO is not set # CONFIG_PKG_USING_PIXMAN is not set @@ -389,23 +413,9 @@ CONFIG_RT_LIBC_FIXED_TIMEZONE=8 # CONFIG_PKG_USING_RAMDISK is not set # CONFIG_PKG_USING_MININI is not set # CONFIG_PKG_USING_QBOOT is not set - -# -# Micrium: Micrium software products porting for RT-Thread -# -# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set -# CONFIG_PKG_USING_UCOSII_WRAPPER is not set -# CONFIG_PKG_USING_UC_CRC is not set -# CONFIG_PKG_USING_UC_CLK is not set -# CONFIG_PKG_USING_UC_COMMON is not set -# CONFIG_PKG_USING_UC_MODBUS is not set # CONFIG_PKG_USING_PPOOL is not set # CONFIG_PKG_USING_OPENAMP is not set # CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set -# CONFIG_PKG_USING_RT_MEMCPY_CM is not set -# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set -# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set -# CONFIG_PKG_USING_QFPLIB_M3 is not set # CONFIG_PKG_USING_LPM is not set # CONFIG_PKG_USING_TLSF is not set # CONFIG_PKG_USING_EVENT_RECORDER is not set @@ -433,7 +443,6 @@ CONFIG_RT_LIBC_FIXED_TIMEZONE=8 # CONFIG_PKG_USING_WM_LIBRARIES is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set # CONFIG_PKG_USING_INFRARED is not set -# CONFIG_PKG_USING_ROSSERIAL is not set # CONFIG_PKG_USING_AGILE_BUTTON is not set # CONFIG_PKG_USING_AGILE_LED is not set # CONFIG_PKG_USING_AT24CXX is not set @@ -477,6 +486,9 @@ CONFIG_RT_LIBC_FIXED_TIMEZONE=8 # CONFIG_PKG_USING_MFOC is not set # CONFIG_PKG_USING_TMC51XX is not set # CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set # # AI packages diff --git a/bsp/bluetrum/ab32vg1-ab-prougen/applications/mnt.c b/bsp/bluetrum/ab32vg1-ab-prougen/applications/mnt.c index 18793cb967..e719cd6c52 100644 --- a/bsp/bluetrum/ab32vg1-ab-prougen/applications/mnt.c +++ b/bsp/bluetrum/ab32vg1-ab-prougen/applications/mnt.c @@ -10,7 +10,7 @@ #include -#ifdef BSP_USING_SDIO +#if defined (BSP_USING_SDCARD) #include #include @@ -58,4 +58,23 @@ int ab32_sdcard_mount(void) return RT_EOK; } INIT_APP_EXPORT(ab32_sdcard_mount); +#elif defined (RT_USING_DFS_ROMFS) + +#include +#include "dfs_romfs.h" + +int ab32_romfs_mount(void) +{ + if (dfs_mount(RT_NULL, "/", "rom", 0, &(romfs_root)) == 0) + { + rt_kprintf("ROM file system initializated!\n"); + } + else + { + rt_kprintf("ROM file system initializate failed!\n"); + } + + return 0; +} +INIT_ENV_EXPORT(ab32_romfs_mount); #endif diff --git a/bsp/bluetrum/ab32vg1-ab-prougen/board/ports/audio/drv_sound.c b/bsp/bluetrum/ab32vg1-ab-prougen/board/ports/audio/drv_sound.c index e2ba236512..e9b4496894 100644 --- a/bsp/bluetrum/ab32vg1-ab-prougen/board/ports/audio/drv_sound.c +++ b/bsp/bluetrum/ab32vg1-ab-prougen/board/ports/audio/drv_sound.c @@ -388,8 +388,6 @@ static rt_err_t sound_stop(struct rt_audio_device *audio, int stream) if (stream == AUDIO_STREAM_REPLAY) { - DACDIGCON0 = 0; - AUBUFCON &= ~BIT(4); LOG_D("close sound device"); } diff --git a/bsp/bluetrum/ab32vg1-ab-prougen/link.lds b/bsp/bluetrum/ab32vg1-ab-prougen/link.lds index 82e8906080..b12f648d48 100644 --- a/bsp/bluetrum/ab32vg1-ab-prougen/link.lds +++ b/bsp/bluetrum/ab32vg1-ab-prougen/link.lds @@ -34,8 +34,8 @@ SECTIONS } > init .ram1 __ram1_vma : { - . = ALIGN(4); /* section information for initial */ + . = ALIGN(4); __rt_init_start = .; KEEP(*(SORT(.rti_fn*))) __rt_init_end = .; @@ -75,7 +75,6 @@ SECTIONS KEEP(*(.vector)) *(.irq.cache) *(.irq*) - *components*src**.o (.text* .rodata*) *ab32vg1_hal**.o (.text* .rodata*) *drv_gpio.o (.text* .rodata*) *drv_usart.o (.rodata*) diff --git a/bsp/bluetrum/ab32vg1-ab-prougen/rtconfig.h b/bsp/bluetrum/ab32vg1-ab-prougen/rtconfig.h index 7451b8f1c0..4d37e2598b 100644 --- a/bsp/bluetrum/ab32vg1-ab-prougen/rtconfig.h +++ b/bsp/bluetrum/ab32vg1-ab-prougen/rtconfig.h @@ -81,6 +81,7 @@ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 #define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_PIN @@ -145,6 +146,8 @@ /* system packages */ +/* acceleration: Assembly language or algorithmic acceleration packages */ + /* Micrium: Micrium software products porting for RT-Thread */ diff --git a/bsp/bluetrum/libraries/hal_drivers/drv_rtc.c b/bsp/bluetrum/libraries/hal_drivers/drv_rtc.c index ccbaac1909..9107107ab0 100644 --- a/bsp/bluetrum/libraries/hal_drivers/drv_rtc.c +++ b/bsp/bluetrum/libraries/hal_drivers/drv_rtc.c @@ -189,27 +189,27 @@ static rt_err_t ab32_rtc_control(rt_device_t dev, int cmd, void *args) switch (cmd) { case RT_DEVICE_CTRL_RTC_GET_TIME: - *(rt_uint32_t *)args = get_rtc_time_stamp(); - LOG_D("RTC: get rtc_time %x", *(rt_uint32_t *)args); + *(time_t *)args = get_rtc_time_stamp(); + LOG_D("RTC: get rtc_time %x", *(time_t *)args); break; case RT_DEVICE_CTRL_RTC_SET_TIME: - if (set_rtc_time_stamp(*(rt_uint32_t *)args)) + if (set_rtc_time_stamp(*(time_t *)args)) { result = -RT_ERROR; } - LOG_D("RTC: set rtc_time %x", *(rt_uint32_t *)args); + LOG_D("RTC: set rtc_time %x", *(time_t *)args); break; case RT_DEVICE_CTRL_RTC_SET_ALARM: - if (set_rtc_alarm_stamp(*(rt_uint32_t *)args)) + if (set_rtc_alarm_stamp(*(time_t *)args)) { result = -RT_ERROR; } - LOG_D("RTC: set alarm_stamp %x", *(rt_uint32_t *)args); + LOG_D("RTC: set alarm_stamp %x", *(time_t *)args); break; case RT_DEVICE_CTRL_RTC_GET_ALARM: - *(rt_uint32_t *)args = get_rtc_alarm_stamp(); - LOG_D("RTC: get alarm_stamp %x", *(rt_uint32_t *)args); + *(time_t *)args = get_rtc_alarm_stamp(); + LOG_D("RTC: get alarm_stamp %x", *(time_t *)args); break; } diff --git a/bsp/efm32/drv_rtc.c b/bsp/efm32/drv_rtc.c index 75713fe3b4..9972d3c631 100644 --- a/bsp/efm32/drv_rtc.c +++ b/bsp/efm32/drv_rtc.c @@ -24,6 +24,8 @@ ******************************************************************************/ /* Includes ------------------------------------------------------------------*/ + +#include #include "board.h" #include "hdl_interrupt.h" #include "drv_rtc.h" diff --git a/bsp/essemi/es32f0654/.config b/bsp/essemi/es32f0654/.config index 3a014cefdd..cab1975d8a 100644 --- a/bsp/essemi/es32f0654/.config +++ b/bsp/essemi/es32f0654/.config @@ -19,7 +19,7 @@ CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_IDLE_THREAD_STACK_SIZE=512 # CONFIG_RT_USING_TIMER_SOFT is not set CONFIG_RT_DEBUG=y CONFIG_RT_DEBUG_COLOR=y @@ -114,26 +114,26 @@ CONFIG_RT_PIPE_BUFSZ=512 CONFIG_RT_USING_SERIAL=y # CONFIG_RT_SERIAL_USING_DMA is not set CONFIG_RT_SERIAL_RB_BUFSZ=64 -CONFIG_RT_USING_CAN=y +# CONFIG_RT_USING_CAN is not set # CONFIG_RT_CAN_USING_HDR is not set -CONFIG_RT_USING_HWTIMER=y +# CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set -CONFIG_RT_USING_I2C=y +# CONFIG_RT_USING_I2C is not set # CONFIG_RT_I2C_DEBUG is not set -CONFIG_RT_USING_I2C_BITOPS=y +# CONFIG_RT_USING_I2C_BITOPS is not set # CONFIG_RT_I2C_BITOPS_DEBUG is not set CONFIG_RT_USING_PIN=y -CONFIG_RT_USING_ADC=y +# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_DAC is not set -CONFIG_RT_USING_PWM=y +# CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set -CONFIG_RT_USING_PM=y -CONFIG_RT_USING_RTC=y +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_ALARM is not set # CONFIG_RT_USING_SOFT_RTC is not set # CONFIG_RT_USING_SDIO is not set -CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_SPI is not set # CONFIG_RT_USING_QSPI is not set # CONFIG_RT_USING_SPI_MSD is not set # CONFIG_RT_USING_SFUD is not set @@ -159,7 +159,8 @@ CONFIG_RT_USING_SPI=y # # CONFIG_RT_USING_LIBC is not set # CONFIG_RT_USING_PTHREADS is not set -# CONFIG_RT_LIBC_USING_TIME is not set +CONFIG_RT_LIBC_USING_TIME=y +CONFIG_RT_LIBC_FIXED_TIMEZONE=8 # # Network @@ -468,6 +469,8 @@ CONFIG_BSP_USING_GPIO=y # CONFIG_BSP_USING_UART1 is not set CONFIG_BSP_USING_UART2=y # CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_USART0 is not set +# CONFIG_BSP_USING_USART1 is not set # # SPI Drivers @@ -484,23 +487,26 @@ CONFIG_BSP_USING_UART2=y # # CAN Drivers # -# CONFIG_BSP_USING_CAN is not set +# CONFIG_BSP_USING_CAN0 is not set # # PWM Drivers # -# CONFIG_BSP_USING_PWM0 is not set -# CONFIG_BSP_USING_PWM1 is not set -# CONFIG_BSP_USING_PWM2 is not set -# CONFIG_BSP_USING_PWM3 is not set +# CONFIG_BSP_USING_AD16C4T0_PWM is not set +# CONFIG_BSP_USING_GP16C4T0_PWM is not set +# CONFIG_BSP_USING_GP16C2T0_PWM is not set +# CONFIG_BSP_USING_GP16C2T1_PWM is not set # # HWtimer Drivers # -# CONFIG_BSP_USING_HWTIMER0 is not set -# CONFIG_BSP_USING_HWTIMER1 is not set -# CONFIG_BSP_USING_HWTIMER2 is not set -# CONFIG_BSP_USING_HWTIMER3 is not set +# CONFIG_BSP_USING_AD16C4T0_HWTIMER is not set +# CONFIG_BSP_USING_GP16C4T0_HWTIMER is not set +# CONFIG_BSP_USING_GP16C2T0_HWTIMER is not set +# CONFIG_BSP_USING_GP16C2T1_HWTIMER is not set +# CONFIG_BSP_USING_BS16T0_HWTIMER is not set +# CONFIG_BSP_USING_BS16T2_HWTIMER is not set +# CONFIG_BSP_USING_BS16T3_HWTIMER is not set # # RTC Drivers @@ -515,7 +521,7 @@ CONFIG_BSP_USING_UART2=y # # ADC Drivers # -# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_ADC0 is not set # # Onboard Peripheral Drivers @@ -532,6 +538,7 @@ CONFIG_BSP_USING_UART2=y # CONFIG_BSP_USING_EXAMPLE_ADC_VOL is not set # CONFIG_BSP_USING_EXAMPLE_HWTIMER is not set # CONFIG_BSP_USING_EXAMPLE_I2C is not set +# CONFIG_BSP_USING_EXAMPLE_I2C_E2PROM is not set # CONFIG_BSP_USING_EXAMPLE_LED_BLINK is not set # CONFIG_BSP_USING_EXAMPLE_PIN_BEEP is not set # CONFIG_BSP_USING_EXAMPLE_PWM_LED is not set diff --git a/bsp/essemi/es32f0654/drivers/ES/Kconfig b/bsp/essemi/es32f0654/drivers/ES/Kconfig new file mode 100644 index 0000000000..1f3b0a4e96 --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/ES/Kconfig @@ -0,0 +1,160 @@ +menu "UART Drivers" + + config BSP_USING_UART0 + bool "Register UART0" + select RT_USING_SERIAL + default n + + config BSP_USING_UART1 + bool "Register UART1" + select RT_USING_SERIAL + default n + + config BSP_USING_UART2 + bool "Register UART2" + select RT_USING_SERIAL + default y + + config BSP_USING_UART3 + bool "Register UART3" + select RT_USING_SERIAL + default n + + config BSP_USING_USART0 + bool "Register USART0" + select RT_USING_SERIAL + default n + + config BSP_USING_USART1 + bool "Register USART1" + select RT_USING_SERIAL + default n +endmenu + +menu "SPI Drivers" + + config BSP_USING_SPI0 + bool "Register SPI0" + select RT_USING_SPI + select RT_USING_PIN + default n + + config BSP_USING_SPI1 + bool "Register SPI1" + select RT_USING_SPI + select RT_USING_PIN + default n +endmenu + +menu "I2C Drivers" + config BSP_USING_I2C0 + bool "Register I2C0" + select RT_USING_I2C + default n + + config BSP_USING_I2C1 + bool "Register I2C1" + select RT_USING_I2C + default n +endmenu + +menu "CAN Drivers" + config BSP_USING_CAN0 + bool "Register CAN0" + select RT_USING_CAN + select RT_CAN_USING_HDR + default n +endmenu + +menu "PWM Drivers" + config BSP_USING_AD16C4T0_PWM + bool "Register pwm0" + select RT_USING_PWM + default n + + config BSP_USING_GP16C4T0_PWM + bool "Register pwm1" + select RT_USING_PWM + default n + + config BSP_USING_GP16C2T0_PWM + bool "Register pwm2" + select RT_USING_PWM + default n + + config BSP_USING_GP16C2T1_PWM + bool "Register pwm3" + select RT_USING_PWM + default n +endmenu + +menu "HWtimer Drivers" + config BSP_USING_AD16C4T0_HWTIMER + bool "Register timer0" + select RT_USING_HWTIMER + default n + depends on !BSP_USING_AD16C4T0_PWM + + config BSP_USING_GP16C4T0_HWTIMER + bool "Register timer1" + select RT_USING_HWTIMER + default n + depends on !BSP_USING_GP16C4T0_PWM + + config BSP_USING_GP16C2T0_HWTIMER + bool "Register timer2" + select RT_USING_HWTIMER + default n + depends on !BSP_USING_GP16C2T0_PWM + + config BSP_USING_GP16C2T1_HWTIMER + bool "Register timer3" + select RT_USING_HWTIMER + default n + depends on !BSP_USING_GP16C2T1_PWM + + config BSP_USING_BS16T0_HWTIMER + bool "Register timer4" + select RT_USING_HWTIMER + default n + + config BSP_USING_BS16T1_HWTIMER + bool "Register timer5" + select RT_USING_HWTIMER + default n + depends on !BSP_USING_UART2 + + config BSP_USING_BS16T2_HWTIMER + bool "Register timer6" + select RT_USING_HWTIMER + default n + depends on !BSP_USING_UART3 + + config BSP_USING_BS16T3_HWTIMER + bool "Register timer7" + select RT_USING_HWTIMER + default n +endmenu + +menu "RTC Drivers" + config BSP_USING_RTC + bool "Register RTC" + select RT_USING_RTC + default n +endmenu + +menu "PM Drivers" + config BSP_USING_PM + bool "Using PM" + select RT_USING_PM + default n +endmenu + +menu "ADC Drivers" + config BSP_USING_ADC0 + bool "Using ADC" + select RT_USING_ADC + select BSP_USING_ADC + default n +endmenu + diff --git a/bsp/essemi/es32f0654/drivers/ES/es_conf_info_adc.h b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_adc.h new file mode 100644 index 0000000000..772f7a0df0 --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_adc.h @@ -0,0 +1,97 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_ADC_H__ +#define __ES_CONF_INFO_ADC_H__ + +#include "es_conf_info_map.h" + +#include + + +#define ES_C_ADC_CLK_DIV_1 ADC_CKDIV_1 +#define ES_C_ADC_CLK_DIV_2 ADC_CKDIV_2 +#define ES_C_ADC_CLK_DIV_4 ADC_CKDIV_4 +#define ES_C_ADC_CLK_DIV_8 ADC_CKDIV_8 +#define ES_C_ADC_CLK_DIV_16 ADC_CKDIV_16 +#define ES_C_ADC_CLK_DIV_32 ADC_CKDIV_32 +#define ES_C_ADC_CLK_DIV_64 ADC_CKDIV_64 +#define ES_C_ADC_CLK_DIV_128 ADC_CKDIV_128 + +#define ES_C_ADC_ALIGN_RIGHT ADC_DATAALIGN_RIGHT +#define ES_C_ADC_ALIGN_LEFT ADC_DATAALIGN_LEFT + +#define ES_C_ADC_CONV_BIT_6 ADC_CONV_BIT_6 +#define ES_C_ADC_CONV_BIT_8 ADC_CONV_BIT_8 +#define ES_C_ADC_CONV_BIT_10 ADC_CONV_BIT_10 +#define ES_C_ADC_CONV_BIT_12 ADC_CONV_BIT_12 + +#define ES_C_ADC_SAMPLE_TIME_1 ADC_SAMPLETIME_1 +#define ES_C_ADC_SAMPLE_TIME_2 ADC_SAMPLETIME_2 +#define ES_C_ADC_SAMPLE_TIME_4 ADC_SAMPLETIME_4 +#define ES_C_ADC_SAMPLE_TIME_15 ADC_SAMPLETIME_15 + +/* ADC 配置 */ + +/* codes_main */ + + +#define ES_ADC0_ALIGN ES_C_ADC_ALIGN_RIGHT +#define ES_ADC1_ALIGN ES_C_ADC_ALIGN_RIGHT +#define ES_ADC1_DATA_BIT ES_C_ADC_CONV_BIT_12 +#define ES_ADC0_DATA_BIT ES_C_ADC_CONV_BIT_12 + +#ifndef ES_DEVICE_NAME_ADC0 +#define ES_DEVICE_NAME_ADC0 "adc0" +#endif +#ifndef ES_DEVICE_NAME_ADC1 +#define ES_DEVICE_NAME_ADC1 "adc1" +#endif + +#ifndef ES_ADC0_CLK_DIV +#define ES_ADC0_CLK_DIV ES_C_ADC_CLK_DIV_128 +#endif +#ifndef ES_ADC0_ALIGN +#define ES_ADC0_ALIGN ES_C_ADC_ALIGN_RIGHT +#endif +#ifndef ES_ADC0_DATA_BIT +#define ES_ADC0_DATA_BIT ES_C_ADC_CONV_BIT_12 +#endif +#ifndef ES_ADC0_NCH_SAMPLETIME +#define ES_ADC0_NCH_SAMPLETIME ES_C_ADC_SAMPLE_TIME_4 +#endif + +#ifndef ES_ADC1_CLK_DIV +#define ES_ADC1_CLK_DIV ES_C_ADC_CLK_DIV_128 +#endif +#ifndef ES_ADC1_ALIGN +#define ES_ADC1_ALIGN ES_C_ADC_ALIGN_RIGHT +#endif +#ifndef ES_ADC1_DATA_BIT +#define ES_ADC1_DATA_BIT ES_C_ADC_CONV_BIT_12 +#endif +#ifndef ES_ADC1_NCH_SAMPLETIME +#define ES_ADC1_NCH_SAMPLETIME ES_C_ADC_SAMPLE_TIME_4 +#endif + +#endif diff --git a/bsp/essemi/es32f0654/drivers/ES/es_conf_info_can.h b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_can.h new file mode 100644 index 0000000000..46df1ed054 --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_can.h @@ -0,0 +1,73 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_CAN_H__ +#define __ES_CONF_INFO_CAN_H__ + +#include "es_conf_info_map.h" +#include +#include + + +/*默认的CAN硬件过滤器的编号 0 */ +#define ES_C_CAN_DEFAULT_FILTER_NUMBER 0 + +/*硬件过滤器，过滤帧类型*/ +#define ES_C_CAN_FILTER_FRAME_TYPE 0 + + +#define ES_C_CAN_SJW_NUM_1 CAN_SJW_1 +#define ES_C_CAN_SJW_NUM_2 CAN_SJW_2 +#define ES_C_CAN_SJW_NUM_3 CAN_SJW_3 +#define ES_C_CAN_SJW_NUM_4 CAN_SJW_4 + + + +/* CAN 配置 */ + +/* codes_main */ + + + +#ifndef ES_DEVICE_NAME_CAN0 +#define ES_DEVICE_NAME_CAN0 "can0" +#endif + +#ifndef ES_CAN0_AUTO_BAN_RE_T +#define ES_CAN0_AUTO_BAN_RE_T ES_C_ENABLE +#endif +#ifndef ES_CAN0_SPEED +#define ES_CAN0_SPEED 1000000 +#endif +#ifndef ES_CAN0_SJW +#define ES_CAN0_SJW ES_C_CAN_SJW_NUM_4 +#endif + +#define ES_CAN0_CONFIG \ +{ \ + ES_CAN0_SPEED, \ + RT_CANMSG_BOX_SZ, \ + RT_CANSND_BOX_NUM, \ + RT_CAN_MODE_NORMAL, \ +}; +#endif diff --git a/bsp/essemi/es32f0654/drivers/ES/es_conf_info_cmu.h b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_cmu.h new file mode 100644 index 0000000000..f82c1d2b6b --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_cmu.h @@ -0,0 +1,87 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_CMU_H__ +#define __ES_CONF_INFO_CMU_H__ + + +#include + + +/* 时钟树 配置 */ + +#define ES_C_MUL_9 CMU_PLL1_OUTPUT_36M +#define ES_C_MUL_12 CMU_PLL1_OUTPUT_48M + +#define ES_C_DIV_1 CMU_DIV_1 +#define ES_C_DIV_2 CMU_DIV_2 +#define ES_C_DIV_4 CMU_DIV_4 +#define ES_C_DIV_8 CMU_DIV_8 +#define ES_C_DIV_16 CMU_DIV_16 +#define ES_C_DIV_32 CMU_DIV_32 +#define ES_C_DIV_64 CMU_DIV_64 +#define ES_C_DIV_128 CMU_DIV_128 +#define ES_C_DIV_256 CMU_DIV_256 +#define ES_C_DIV_512 CMU_DIV_512 +#define ES_C_DIV_1024 CMU_DIV_1024 +#define ES_C_DIV_2048 CMU_DIV_2048 +#define ES_C_DIV_4096 CMU_DIV_4096 + +#define ES_C_HOSC_DIV_1 CMU_PLL1_INPUT_HOSC +#define ES_C_HOSC_DIV_2 CMU_PLL1_INPUT_HOSC_2 +#define ES_C_HOSC_DIV_3 CMU_PLL1_INPUT_HOSC_3 +#define ES_C_HOSC_DIV_4 CMU_PLL1_INPUT_HOSC_4 +#define ES_C_HOSC_DIV_5 CMU_PLL1_INPUT_HOSC_5 +#define ES_C_HOSC_DIV_6 CMU_PLL1_INPUT_HOSC_6 +#define ES_C_HRC_DIV_6 CMU_PLL1_INPUT_HRC_6 + + + + + +#define ES_PLL1_REFER_CLK ES_C_HOSC_DIV_3 +#define ES_PLL1_OUT_CLK ES_C_MUL_12 +#define ES_CMU_PLL1_EN ES_C_ENABLE +#define ES_CMU_PLL1_SAFE_EN ES_C_DISABLE +#define ES_CMU_LOSC_EN ES_C_ENABLE +#define ES_CMU_LRC_EN ES_C_ENABLE +#define ES_CMU_HOSC_EN ES_C_ENABLE +#define ES_CMU_HRC_EN ES_C_ENABLE +#define ES_CMU_SYS_DIV ES_C_DIV_1 +#define ES_CMU_HCLK_1_DIV ES_C_DIV_1 +#define ES_CMU_PCLK_1_DIV ES_C_DIV_1 +#define ES_CMU_PCLK_2_DIV ES_C_DIV_1 +#define ES_SYS_CLK_SOURSE CMU_CLOCK_PLL1 +#define ES_PLL_CLK 48000000 +#define ES_SYS_SOURCE_CLK 48000000 +#define ES_SYS_CLK 48000000 +#define ES_PCLK1_CLK 48000000 +#define ES_PCLK2_CLK 48000000 +#define ES_HCLK1_CLK 48000000 +#define ES_CMU_EXTERN_CLK_LOSC 32768 +#define ES_CMU_EXTERN_CLK_HOSC 12000000 + + + + +#endif diff --git a/bsp/essemi/es32f0654/drivers/ES/es_conf_info_gpio.h b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_gpio.h new file mode 100644 index 0000000000..dc3fde3020 --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_gpio.h @@ -0,0 +1,5158 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_GPIO_H__ +#define __ES_CONF_INFO_GPIO_H__ + +#include "es_conf_info_map.h" + +#include +#include +#include + +/* GPIO 配置 */ + +typedef struct { + uint8_t pin; + uint8_t pin_mode; + uint8_t pin_level; + uint8_t irq_en; + uint8_t irq_mode; + void (*callback)(void *arg); +} gpio_conf_t; + +/*参数的定义*/ + +#define ES_C_GPIO_LEVEL_HIGH PIN_HIGH +#define ES_C_GPIO_LEVEL_LOW PIN_LOW + +#define ES_C_GPIO_MODE_OUTPUT PIN_MODE_OUTPUT +#define ES_C_GPIO_MODE_INPUT PIN_MODE_INPUT +#define ES_C_GPIO_MODE_INPUT_PULLUP PIN_MODE_INPUT_PULLUP +#define ES_C_GPIO_MODE_INPUT_PULLDOWN PIN_MODE_INPUT_PULLDOWN +#define ES_C_GPIO_MODE_OUTPUT_OD PIN_MODE_OUTPUT_OD + +#define ES_C_GPIO_IRQ_ENABLE PIN_IRQ_ENABLE +#define ES_C_GPIO_IRQ_DISABLE PIN_IRQ_DISABLE + +#define ES_C_GPIO_IRQ_MODE_FALL PIN_IRQ_MODE_FALLING +#define ES_C_GPIO_IRQ_MODE_RISE PIN_IRQ_MODE_RISING +#define ES_C_GPIO_IRQ_MODE_R_F PIN_IRQ_MODE_RISING_FALLING + + + + + +/* codes_main */ +//#define ES_INIT_PIN_GPIO_C_8 +//#define ES_INIT_GPIO_C_8_IRQ_EN ES_C_GPIO_IRQ_ENABLE + + + +#ifndef ES_DEVICE_NAME_PIN +#define ES_DEVICE_NAME_PIN "pin" +#endif + +/*GPIO外部中断回调函数控制需要，补充是否中断*/ +#if 11111 + +#ifndef ES_INIT_GPIO_A_0_IRQ_EN +#define ES_INIT_GPIO_A_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_1_IRQ_EN +#define ES_INIT_GPIO_A_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_2_IRQ_EN +#define ES_INIT_GPIO_A_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_3_IRQ_EN +#define ES_INIT_GPIO_A_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_4_IRQ_EN +#define ES_INIT_GPIO_A_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_5_IRQ_EN +#define ES_INIT_GPIO_A_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_6_IRQ_EN +#define ES_INIT_GPIO_A_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_7_IRQ_EN +#define ES_INIT_GPIO_A_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_8_IRQ_EN +#define ES_INIT_GPIO_A_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_9_IRQ_EN +#define ES_INIT_GPIO_A_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_10_IRQ_EN +#define ES_INIT_GPIO_A_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_11_IRQ_EN +#define ES_INIT_GPIO_A_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_12_IRQ_EN +#define ES_INIT_GPIO_A_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_13_IRQ_EN +#define ES_INIT_GPIO_A_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_14_IRQ_EN +#define ES_INIT_GPIO_A_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_15_IRQ_EN +#define ES_INIT_GPIO_A_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_0_IRQ_EN +#define ES_INIT_GPIO_B_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_1_IRQ_EN +#define ES_INIT_GPIO_B_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_2_IRQ_EN +#define ES_INIT_GPIO_B_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_3_IRQ_EN +#define ES_INIT_GPIO_B_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_4_IRQ_EN +#define ES_INIT_GPIO_B_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_5_IRQ_EN +#define ES_INIT_GPIO_B_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_6_IRQ_EN +#define ES_INIT_GPIO_B_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_7_IRQ_EN +#define ES_INIT_GPIO_B_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_8_IRQ_EN +#define ES_INIT_GPIO_B_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_9_IRQ_EN +#define ES_INIT_GPIO_B_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_10_IRQ_EN +#define ES_INIT_GPIO_B_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_11_IRQ_EN +#define ES_INIT_GPIO_B_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_12_IRQ_EN +#define ES_INIT_GPIO_B_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_13_IRQ_EN +#define ES_INIT_GPIO_B_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_14_IRQ_EN +#define ES_INIT_GPIO_B_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_15_IRQ_EN +#define ES_INIT_GPIO_B_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_0_IRQ_EN +#define ES_INIT_GPIO_C_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_1_IRQ_EN +#define ES_INIT_GPIO_C_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_2_IRQ_EN +#define ES_INIT_GPIO_C_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_3_IRQ_EN +#define ES_INIT_GPIO_C_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_4_IRQ_EN +#define ES_INIT_GPIO_C_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_5_IRQ_EN +#define ES_INIT_GPIO_C_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_6_IRQ_EN +#define ES_INIT_GPIO_C_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_7_IRQ_EN +#define ES_INIT_GPIO_C_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_8_IRQ_EN +#define ES_INIT_GPIO_C_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_9_IRQ_EN +#define ES_INIT_GPIO_C_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_10_IRQ_EN +#define ES_INIT_GPIO_C_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_11_IRQ_EN +#define ES_INIT_GPIO_C_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_12_IRQ_EN +#define ES_INIT_GPIO_C_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_13_IRQ_EN +#define ES_INIT_GPIO_C_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_14_IRQ_EN +#define ES_INIT_GPIO_C_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_15_IRQ_EN +#define ES_INIT_GPIO_C_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_0_IRQ_EN +#define ES_INIT_GPIO_D_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_1_IRQ_EN +#define ES_INIT_GPIO_D_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_2_IRQ_EN +#define ES_INIT_GPIO_D_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_3_IRQ_EN +#define ES_INIT_GPIO_D_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_4_IRQ_EN +#define ES_INIT_GPIO_D_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_5_IRQ_EN +#define ES_INIT_GPIO_D_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_6_IRQ_EN +#define ES_INIT_GPIO_D_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_7_IRQ_EN +#define ES_INIT_GPIO_D_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_8_IRQ_EN +#define ES_INIT_GPIO_D_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_9_IRQ_EN +#define ES_INIT_GPIO_D_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_10_IRQ_EN +#define ES_INIT_GPIO_D_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_11_IRQ_EN +#define ES_INIT_GPIO_D_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_12_IRQ_EN +#define ES_INIT_GPIO_D_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_13_IRQ_EN +#define ES_INIT_GPIO_D_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_14_IRQ_EN +#define ES_INIT_GPIO_D_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_15_IRQ_EN +#define ES_INIT_GPIO_D_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_0_IRQ_EN +#define ES_INIT_GPIO_E_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_1_IRQ_EN +#define ES_INIT_GPIO_E_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_2_IRQ_EN +#define ES_INIT_GPIO_E_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_3_IRQ_EN +#define ES_INIT_GPIO_E_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_4_IRQ_EN +#define ES_INIT_GPIO_E_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_5_IRQ_EN +#define ES_INIT_GPIO_E_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_6_IRQ_EN +#define ES_INIT_GPIO_E_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_7_IRQ_EN +#define ES_INIT_GPIO_E_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_8_IRQ_EN +#define ES_INIT_GPIO_E_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_9_IRQ_EN +#define ES_INIT_GPIO_E_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_10_IRQ_EN +#define ES_INIT_GPIO_E_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_11_IRQ_EN +#define ES_INIT_GPIO_E_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_12_IRQ_EN +#define ES_INIT_GPIO_E_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_13_IRQ_EN +#define ES_INIT_GPIO_E_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_14_IRQ_EN +#define ES_INIT_GPIO_E_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_15_IRQ_EN +#define ES_INIT_GPIO_E_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_0_IRQ_EN +#define ES_INIT_GPIO_F_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_1_IRQ_EN +#define ES_INIT_GPIO_F_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_2_IRQ_EN +#define ES_INIT_GPIO_F_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_3_IRQ_EN +#define ES_INIT_GPIO_F_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_4_IRQ_EN +#define ES_INIT_GPIO_F_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_5_IRQ_EN +#define ES_INIT_GPIO_F_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_6_IRQ_EN +#define ES_INIT_GPIO_F_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_7_IRQ_EN +#define ES_INIT_GPIO_F_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_8_IRQ_EN +#define ES_INIT_GPIO_F_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_9_IRQ_EN +#define ES_INIT_GPIO_F_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_10_IRQ_EN +#define ES_INIT_GPIO_F_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_11_IRQ_EN +#define ES_INIT_GPIO_F_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_12_IRQ_EN +#define ES_INIT_GPIO_F_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_13_IRQ_EN +#define ES_INIT_GPIO_F_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_14_IRQ_EN +#define ES_INIT_GPIO_F_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_15_IRQ_EN +#define ES_INIT_GPIO_F_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_0_IRQ_EN +#define ES_INIT_GPIO_G_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_1_IRQ_EN +#define ES_INIT_GPIO_G_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_2_IRQ_EN +#define ES_INIT_GPIO_G_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_3_IRQ_EN +#define ES_INIT_GPIO_G_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_4_IRQ_EN +#define ES_INIT_GPIO_G_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_5_IRQ_EN +#define ES_INIT_GPIO_G_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_6_IRQ_EN +#define ES_INIT_GPIO_G_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_7_IRQ_EN +#define ES_INIT_GPIO_G_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_8_IRQ_EN +#define ES_INIT_GPIO_G_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_9_IRQ_EN +#define ES_INIT_GPIO_G_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_10_IRQ_EN +#define ES_INIT_GPIO_G_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_11_IRQ_EN +#define ES_INIT_GPIO_G_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_12_IRQ_EN +#define ES_INIT_GPIO_G_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_13_IRQ_EN +#define ES_INIT_GPIO_G_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_14_IRQ_EN +#define ES_INIT_GPIO_G_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_15_IRQ_EN +#define ES_INIT_GPIO_G_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_0_IRQ_EN +#define ES_INIT_GPIO_H_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_1_IRQ_EN +#define ES_INIT_GPIO_H_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_2_IRQ_EN +#define ES_INIT_GPIO_H_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_3_IRQ_EN +#define ES_INIT_GPIO_H_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_4_IRQ_EN +#define ES_INIT_GPIO_H_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_5_IRQ_EN +#define ES_INIT_GPIO_H_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_6_IRQ_EN +#define ES_INIT_GPIO_H_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_7_IRQ_EN +#define ES_INIT_GPIO_H_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_8_IRQ_EN +#define ES_INIT_GPIO_H_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_9_IRQ_EN +#define ES_INIT_GPIO_H_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_10_IRQ_EN +#define ES_INIT_GPIO_H_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_11_IRQ_EN +#define ES_INIT_GPIO_H_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_12_IRQ_EN +#define ES_INIT_GPIO_H_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_13_IRQ_EN +#define ES_INIT_GPIO_H_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_14_IRQ_EN +#define ES_INIT_GPIO_H_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_15_IRQ_EN +#define ES_INIT_GPIO_H_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#endif //11111 + + + +/*是否需要 GPIO外部中断回调函数 （控制函数本体+声明）*/ +#if 11111 + +#if (ES_INIT_GPIO_A_0_IRQ_EN)||(ES_INIT_GPIO_B_0_IRQ_EN)||(ES_INIT_GPIO_C_0_IRQ_EN)||(ES_INIT_GPIO_D_0_IRQ_EN)|| \ + (ES_INIT_GPIO_E_0_IRQ_EN)||(ES_INIT_GPIO_F_0_IRQ_EN)||(ES_INIT_GPIO_G_0_IRQ_EN)||(ES_INIT_GPIO_H_0_IRQ_EN) +#define ES_CONF_EXTI_IRQ_0 +#endif + +#if (ES_INIT_GPIO_A_1_IRQ_EN)||(ES_INIT_GPIO_B_1_IRQ_EN)||(ES_INIT_GPIO_C_1_IRQ_EN)||(ES_INIT_GPIO_D_1_IRQ_EN)|| \ + (ES_INIT_GPIO_E_1_IRQ_EN)||(ES_INIT_GPIO_F_1_IRQ_EN)||(ES_INIT_GPIO_G_1_IRQ_EN)||(ES_INIT_GPIO_H_1_IRQ_EN) +#define ES_CONF_EXTI_IRQ_1 +#endif + +#if (ES_INIT_GPIO_A_2_IRQ_EN)||(ES_INIT_GPIO_B_2_IRQ_EN)||(ES_INIT_GPIO_C_2_IRQ_EN)||(ES_INIT_GPIO_D_2_IRQ_EN)|| \ + (ES_INIT_GPIO_E_2_IRQ_EN)||(ES_INIT_GPIO_F_2_IRQ_EN)||(ES_INIT_GPIO_G_2_IRQ_EN)||(ES_INIT_GPIO_H_2_IRQ_EN) +#define ES_CONF_EXTI_IRQ_2 +#endif + +#if (ES_INIT_GPIO_A_3_IRQ_EN)||(ES_INIT_GPIO_B_3_IRQ_EN)||(ES_INIT_GPIO_C_3_IRQ_EN)||(ES_INIT_GPIO_D_3_IRQ_EN)|| \ + (ES_INIT_GPIO_E_3_IRQ_EN)||(ES_INIT_GPIO_F_3_IRQ_EN)||(ES_INIT_GPIO_G_3_IRQ_EN)||(ES_INIT_GPIO_H_3_IRQ_EN) +#define ES_CONF_EXTI_IRQ_3 +#endif + +#if (ES_INIT_GPIO_A_4_IRQ_EN)||(ES_INIT_GPIO_B_4_IRQ_EN)||(ES_INIT_GPIO_C_4_IRQ_EN)||(ES_INIT_GPIO_D_4_IRQ_EN)|| \ + (ES_INIT_GPIO_E_4_IRQ_EN)||(ES_INIT_GPIO_F_4_IRQ_EN)||(ES_INIT_GPIO_G_4_IRQ_EN)||(ES_INIT_GPIO_H_4_IRQ_EN) +#define ES_CONF_EXTI_IRQ_4 +#endif + +#if (ES_INIT_GPIO_A_5_IRQ_EN)||(ES_INIT_GPIO_B_5_IRQ_EN)||(ES_INIT_GPIO_C_5_IRQ_EN)||(ES_INIT_GPIO_D_5_IRQ_EN)|| \ + (ES_INIT_GPIO_E_5_IRQ_EN)||(ES_INIT_GPIO_F_5_IRQ_EN)||(ES_INIT_GPIO_G_5_IRQ_EN)||(ES_INIT_GPIO_H_5_IRQ_EN) +#define ES_CONF_EXTI_IRQ_5 +#endif + +#if (ES_INIT_GPIO_A_6_IRQ_EN)||(ES_INIT_GPIO_B_6_IRQ_EN)||(ES_INIT_GPIO_C_6_IRQ_EN)||(ES_INIT_GPIO_D_6_IRQ_EN)|| \ + (ES_INIT_GPIO_E_6_IRQ_EN)||(ES_INIT_GPIO_F_6_IRQ_EN)||(ES_INIT_GPIO_G_6_IRQ_EN)||(ES_INIT_GPIO_H_6_IRQ_EN) +#define ES_CONF_EXTI_IRQ_6 +#endif + +#if (ES_INIT_GPIO_A_7_IRQ_EN)||(ES_INIT_GPIO_B_7_IRQ_EN)||(ES_INIT_GPIO_C_7_IRQ_EN)||(ES_INIT_GPIO_D_7_IRQ_EN)|| \ + (ES_INIT_GPIO_E_7_IRQ_EN)||(ES_INIT_GPIO_F_7_IRQ_EN)||(ES_INIT_GPIO_G_7_IRQ_EN)||(ES_INIT_GPIO_H_7_IRQ_EN) +#define ES_CONF_EXTI_IRQ_7 +#endif + +#if (ES_INIT_GPIO_A_8_IRQ_EN)||(ES_INIT_GPIO_B_8_IRQ_EN)||(ES_INIT_GPIO_C_8_IRQ_EN)||(ES_INIT_GPIO_D_8_IRQ_EN)|| \ + (ES_INIT_GPIO_E_8_IRQ_EN)||(ES_INIT_GPIO_F_8_IRQ_EN)||(ES_INIT_GPIO_G_8_IRQ_EN)||(ES_INIT_GPIO_H_8_IRQ_EN) +#define ES_CONF_EXTI_IRQ_8 +#endif + +#if (ES_INIT_GPIO_A_9_IRQ_EN)||(ES_INIT_GPIO_B_9_IRQ_EN)||(ES_INIT_GPIO_C_9_IRQ_EN)||(ES_INIT_GPIO_D_9_IRQ_EN)|| \ + (ES_INIT_GPIO_E_9_IRQ_EN)||(ES_INIT_GPIO_F_9_IRQ_EN)||(ES_INIT_GPIO_G_9_IRQ_EN)||(ES_INIT_GPIO_H_9_IRQ_EN) +#define ES_CONF_EXTI_IRQ_9 +#endif + +#if (ES_INIT_GPIO_A_10_IRQ_EN)||(ES_INIT_GPIO_B_10_IRQ_EN)||(ES_INIT_GPIO_C_10_IRQ_EN)||(ES_INIT_GPIO_D_10_IRQ_EN)|| \ + (ES_INIT_GPIO_E_10_IRQ_EN)||(ES_INIT_GPIO_F_10_IRQ_EN)||(ES_INIT_GPIO_G_10_IRQ_EN)||(ES_INIT_GPIO_H_10_IRQ_EN) +#define ES_CONF_EXTI_IRQ_10 +#endif + +#if (ES_INIT_GPIO_A_11_IRQ_EN)||(ES_INIT_GPIO_B_11_IRQ_EN)||(ES_INIT_GPIO_C_11_IRQ_EN)||(ES_INIT_GPIO_D_11_IRQ_EN)|| \ + (ES_INIT_GPIO_E_11_IRQ_EN)||(ES_INIT_GPIO_F_11_IRQ_EN)||(ES_INIT_GPIO_G_11_IRQ_EN)||(ES_INIT_GPIO_H_11_IRQ_EN) +#define ES_CONF_EXTI_IRQ_11 +#endif + +#if (ES_INIT_GPIO_A_12_IRQ_EN)||(ES_INIT_GPIO_B_12_IRQ_EN)||(ES_INIT_GPIO_C_12_IRQ_EN)||(ES_INIT_GPIO_D_12_IRQ_EN)|| \ + (ES_INIT_GPIO_E_12_IRQ_EN)||(ES_INIT_GPIO_F_12_IRQ_EN)||(ES_INIT_GPIO_G_12_IRQ_EN)||(ES_INIT_GPIO_H_12_IRQ_EN) +#define ES_CONF_EXTI_IRQ_12 +#endif + +#if (ES_INIT_GPIO_A_13_IRQ_EN)||(ES_INIT_GPIO_B_13_IRQ_EN)||(ES_INIT_GPIO_C_13_IRQ_EN)||(ES_INIT_GPIO_D_13_IRQ_EN)|| \ + (ES_INIT_GPIO_E_13_IRQ_EN)||(ES_INIT_GPIO_F_13_IRQ_EN)||(ES_INIT_GPIO_G_13_IRQ_EN)||(ES_INIT_GPIO_H_13_IRQ_EN) +#define ES_CONF_EXTI_IRQ_13 +#endif + +#if (ES_INIT_GPIO_A_14_IRQ_EN)||(ES_INIT_GPIO_B_14_IRQ_EN)||(ES_INIT_GPIO_C_14_IRQ_EN)||(ES_INIT_GPIO_D_14_IRQ_EN)|| \ + (ES_INIT_GPIO_E_14_IRQ_EN)||(ES_INIT_GPIO_F_14_IRQ_EN)||(ES_INIT_GPIO_G_14_IRQ_EN)||(ES_INIT_GPIO_H_14_IRQ_EN) +#define ES_CONF_EXTI_IRQ_14 +#endif + +#if (ES_INIT_GPIO_A_15_IRQ_EN)||(ES_INIT_GPIO_B_15_IRQ_EN)||(ES_INIT_GPIO_C_15_IRQ_EN)||(ES_INIT_GPIO_D_15_IRQ_EN)|| \ + (ES_INIT_GPIO_E_15_IRQ_EN)||(ES_INIT_GPIO_F_15_IRQ_EN)||(ES_INIT_GPIO_G_15_IRQ_EN)||(ES_INIT_GPIO_H_15_IRQ_EN) +#define ES_CONF_EXTI_IRQ_15 +#endif + +#endif //11111 + + +/*GPIO外部中断 声明*/ +#if 11111 + +#ifdef ES_CONF_EXTI_IRQ_0 +void irq_pin0_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_1 +void irq_pin1_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_2 +void irq_pin2_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_3 +void irq_pin3_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_4 +void irq_pin4_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_5 +void irq_pin5_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_6 +void irq_pin6_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_7 +void irq_pin7_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_8 +void irq_pin8_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_9 +void irq_pin9_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_10 +void irq_pin10_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_11 +void irq_pin11_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_12 +void irq_pin12_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_13 +void irq_pin13_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_14 +void irq_pin14_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_15 +void irq_pin15_callback(void* arg); +#endif + + +#endif //11111 + + + + +/*是否有配置的管脚*/ +#if defined(ES_INIT_PIN_GPIO_A_0) || defined(ES_INIT_PIN_GPIO_A_1) || defined(ES_INIT_PIN_GPIO_A_2) || defined(ES_INIT_PIN_GPIO_A_3) || \ + defined(ES_INIT_PIN_GPIO_A_4) || defined(ES_INIT_PIN_GPIO_A_5) || defined(ES_INIT_PIN_GPIO_A_6) || defined(ES_INIT_PIN_GPIO_A_7) || \ + defined(ES_INIT_PIN_GPIO_A_8) || defined(ES_INIT_PIN_GPIO_A_9) || defined(ES_INIT_PIN_GPIO_A_10) || defined(ES_INIT_PIN_GPIO_A_11) || \ + defined(ES_INIT_PIN_GPIO_A_12) || defined(ES_INIT_PIN_GPIO_A_13) || defined(ES_INIT_PIN_GPIO_A_14) || defined(ES_INIT_PIN_GPIO_A_15) || \ + defined(ES_INIT_PIN_GPIO_B_0) || defined(ES_INIT_PIN_GPIO_B_1) || defined(ES_INIT_PIN_GPIO_B_2) || defined(ES_INIT_PIN_GPIO_B_3) || \ + defined(ES_INIT_PIN_GPIO_B_4) || defined(ES_INIT_PIN_GPIO_B_5) || defined(ES_INIT_PIN_GPIO_B_6) || defined(ES_INIT_PIN_GPIO_B_7) || \ + defined(ES_INIT_PIN_GPIO_B_8) || defined(ES_INIT_PIN_GPIO_B_9) || defined(ES_INIT_PIN_GPIO_B_10) || defined(ES_INIT_PIN_GPIO_B_11) || \ + defined(ES_INIT_PIN_GPIO_B_12) || defined(ES_INIT_PIN_GPIO_B_13) || defined(ES_INIT_PIN_GPIO_B_14) || defined(ES_INIT_PIN_GPIO_B_15) || \ + defined(ES_INIT_PIN_GPIO_C_0) || defined(ES_INIT_PIN_GPIO_C_1) || defined(ES_INIT_PIN_GPIO_C_2) || defined(ES_INIT_PIN_GPIO_C_3) || \ + defined(ES_INIT_PIN_GPIO_C_4) || defined(ES_INIT_PIN_GPIO_C_5) || defined(ES_INIT_PIN_GPIO_C_6) || defined(ES_INIT_PIN_GPIO_C_7) || \ + defined(ES_INIT_PIN_GPIO_C_8) || defined(ES_INIT_PIN_GPIO_C_9) || defined(ES_INIT_PIN_GPIO_C_10) || defined(ES_INIT_PIN_GPIO_C_11) || \ + defined(ES_INIT_PIN_GPIO_C_12) || defined(ES_INIT_PIN_GPIO_C_13) || defined(ES_INIT_PIN_GPIO_C_14) || defined(ES_INIT_PIN_GPIO_C_15) || \ + defined(ES_INIT_PIN_GPIO_D_0) || defined(ES_INIT_PIN_GPIO_D_1) || defined(ES_INIT_PIN_GPIO_D_2) || defined(ES_INIT_PIN_GPIO_D_3) || \ + defined(ES_INIT_PIN_GPIO_D_4) || defined(ES_INIT_PIN_GPIO_D_5) || defined(ES_INIT_PIN_GPIO_D_6) || defined(ES_INIT_PIN_GPIO_D_7) || \ + defined(ES_INIT_PIN_GPIO_D_8) || defined(ES_INIT_PIN_GPIO_D_9) || defined(ES_INIT_PIN_GPIO_D_10) || defined(ES_INIT_PIN_GPIO_D_11) || \ + defined(ES_INIT_PIN_GPIO_D_12) || defined(ES_INIT_PIN_GPIO_D_13) || defined(ES_INIT_PIN_GPIO_D_14) || defined(ES_INIT_PIN_GPIO_D_15) || \ + defined(ES_INIT_PIN_GPIO_E_0) || defined(ES_INIT_PIN_GPIO_E_1) || defined(ES_INIT_PIN_GPIO_E_2) || defined(ES_INIT_PIN_GPIO_E_3) || \ + defined(ES_INIT_PIN_GPIO_E_4) || defined(ES_INIT_PIN_GPIO_E_5) || defined(ES_INIT_PIN_GPIO_E_6) || defined(ES_INIT_PIN_GPIO_E_7) || \ + defined(ES_INIT_PIN_GPIO_E_8) || defined(ES_INIT_PIN_GPIO_E_9) || defined(ES_INIT_PIN_GPIO_E_10) || defined(ES_INIT_PIN_GPIO_E_11) || \ + defined(ES_INIT_PIN_GPIO_E_12) || defined(ES_INIT_PIN_GPIO_E_13) || defined(ES_INIT_PIN_GPIO_E_14) || defined(ES_INIT_PIN_GPIO_E_15) || \ + defined(ES_INIT_PIN_GPIO_F_0) || defined(ES_INIT_PIN_GPIO_F_1) || defined(ES_INIT_PIN_GPIO_F_2) || defined(ES_INIT_PIN_GPIO_F_3) || \ + defined(ES_INIT_PIN_GPIO_F_4) || defined(ES_INIT_PIN_GPIO_F_5) || defined(ES_INIT_PIN_GPIO_F_6) || defined(ES_INIT_PIN_GPIO_F_7) || \ + defined(ES_INIT_PIN_GPIO_F_8) || defined(ES_INIT_PIN_GPIO_F_9) || defined(ES_INIT_PIN_GPIO_F_10) || defined(ES_INIT_PIN_GPIO_F_11) || \ + defined(ES_INIT_PIN_GPIO_F_12) || defined(ES_INIT_PIN_GPIO_F_13) || defined(ES_INIT_PIN_GPIO_F_14) || defined(ES_INIT_PIN_GPIO_F_15) || \ + defined(ES_INIT_PIN_GPIO_G_0) || defined(ES_INIT_PIN_GPIO_G_1) || defined(ES_INIT_PIN_GPIO_G_2) || defined(ES_INIT_PIN_GPIO_G_3) || \ + defined(ES_INIT_PIN_GPIO_G_4) || defined(ES_INIT_PIN_GPIO_G_5) || defined(ES_INIT_PIN_GPIO_G_6) || defined(ES_INIT_PIN_GPIO_G_7) || \ + defined(ES_INIT_PIN_GPIO_G_8) || defined(ES_INIT_PIN_GPIO_G_9) || defined(ES_INIT_PIN_GPIO_G_10) || defined(ES_INIT_PIN_GPIO_G_11) || \ + defined(ES_INIT_PIN_GPIO_G_12) || defined(ES_INIT_PIN_GPIO_G_13) || defined(ES_INIT_PIN_GPIO_G_14) || defined(ES_INIT_PIN_GPIO_G_15) || \ + defined(ES_INIT_PIN_GPIO_H_0) || defined(ES_INIT_PIN_GPIO_H_1) || defined(ES_INIT_PIN_GPIO_H_2) || defined(ES_INIT_PIN_GPIO_H_3) || \ + defined(ES_INIT_PIN_GPIO_H_4) || defined(ES_INIT_PIN_GPIO_H_5) || defined(ES_INIT_PIN_GPIO_H_6) || defined(ES_INIT_PIN_GPIO_H_7) || \ + defined(ES_INIT_PIN_GPIO_H_8) || defined(ES_INIT_PIN_GPIO_H_9) || defined(ES_INIT_PIN_GPIO_H_10) || defined(ES_INIT_PIN_GPIO_H_11) || \ + defined(ES_INIT_PIN_GPIO_H_12) || defined(ES_INIT_PIN_GPIO_H_13) || defined(ES_INIT_PIN_GPIO_H_14) || defined(ES_INIT_PIN_GPIO_H_15) + +#define ES_INIT_GPIOS + +#endif + + +#ifdef ES_INIT_GPIOS + +static gpio_conf_t gpio_conf_all[] = +{ + +#ifdef ES_INIT_PIN_GPIO_A_0 + + { + ES_PIN_GPIO_A_0 , + +#ifdef ES_INIT_GPIO_A_0_MODE + ES_INIT_GPIO_A_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_0_LEVEL + ES_INIT_GPIO_A_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_0_IRQ_MODE + ES_INIT_GPIO_A_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_1 + + { + ES_PIN_GPIO_A_1 , + +#ifdef ES_INIT_GPIO_A_1_MODE + ES_INIT_GPIO_A_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_1_LEVEL + ES_INIT_GPIO_A_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_1_IRQ_MODE + ES_INIT_GPIO_A_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_2 + + { + ES_PIN_GPIO_A_2 , + +#ifdef ES_INIT_GPIO_A_2_MODE + ES_INIT_GPIO_A_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_2_LEVEL + ES_INIT_GPIO_A_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_2_IRQ_MODE + ES_INIT_GPIO_A_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_3 + + { + ES_PIN_GPIO_A_3 , + +#ifdef ES_INIT_GPIO_A_3_MODE + ES_INIT_GPIO_A_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_3_LEVEL + ES_INIT_GPIO_A_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_3_IRQ_MODE + ES_INIT_GPIO_A_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_4 + + { + ES_PIN_GPIO_A_4 , + +#ifdef ES_INIT_GPIO_A_4_MODE + ES_INIT_GPIO_A_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_4_LEVEL + ES_INIT_GPIO_A_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_4_IRQ_MODE + ES_INIT_GPIO_A_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_5 + + { + ES_PIN_GPIO_A_5 , + +#ifdef ES_INIT_GPIO_A_5_MODE + ES_INIT_GPIO_A_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_5_LEVEL + ES_INIT_GPIO_A_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_5_IRQ_MODE + ES_INIT_GPIO_A_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_6 + + { + ES_PIN_GPIO_A_6 , + +#ifdef ES_INIT_GPIO_A_6_MODE + ES_INIT_GPIO_A_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_6_LEVEL + ES_INIT_GPIO_A_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_6_IRQ_MODE + ES_INIT_GPIO_A_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_7 + + { + ES_PIN_GPIO_A_7 , + +#ifdef ES_INIT_GPIO_A_7_MODE + ES_INIT_GPIO_A_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_7_LEVEL + ES_INIT_GPIO_A_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_7_IRQ_MODE + ES_INIT_GPIO_A_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_8 + + { + ES_PIN_GPIO_A_8 , + +#ifdef ES_INIT_GPIO_A_8_MODE + ES_INIT_GPIO_A_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_8_LEVEL + ES_INIT_GPIO_A_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_8_IRQ_MODE + ES_INIT_GPIO_A_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_9 + + { + ES_PIN_GPIO_A_9 , + +#ifdef ES_INIT_GPIO_A_9_MODE + ES_INIT_GPIO_A_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_9_LEVEL + ES_INIT_GPIO_A_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_9_IRQ_MODE + ES_INIT_GPIO_A_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_10 + + { + ES_PIN_GPIO_A_10 , + +#ifdef ES_INIT_GPIO_A_10_MODE + ES_INIT_GPIO_A_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_10_LEVEL + ES_INIT_GPIO_A_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_10_IRQ_MODE + ES_INIT_GPIO_A_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_11 + + { + ES_PIN_GPIO_A_11 , + +#ifdef ES_INIT_GPIO_A_11_MODE + ES_INIT_GPIO_A_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_11_LEVEL + ES_INIT_GPIO_A_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_11_IRQ_MODE + ES_INIT_GPIO_A_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_12 + + { + ES_PIN_GPIO_A_12 , + +#ifdef ES_INIT_GPIO_A_12_MODE + ES_INIT_GPIO_A_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_12_LEVEL + ES_INIT_GPIO_A_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_12_IRQ_MODE + ES_INIT_GPIO_A_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_13 + + { + ES_PIN_GPIO_A_13 , + +#ifdef ES_INIT_GPIO_A_13_MODE + ES_INIT_GPIO_A_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_13_LEVEL + ES_INIT_GPIO_A_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_13_IRQ_MODE + ES_INIT_GPIO_A_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_14 + + { + ES_PIN_GPIO_A_14 , + +#ifdef ES_INIT_GPIO_A_14_MODE + ES_INIT_GPIO_A_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_14_LEVEL + ES_INIT_GPIO_A_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_14_IRQ_MODE + ES_INIT_GPIO_A_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_15 + + { + ES_PIN_GPIO_A_15 , + +#ifdef ES_INIT_GPIO_A_15_MODE + ES_INIT_GPIO_A_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_15_LEVEL + ES_INIT_GPIO_A_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_15_IRQ_MODE + ES_INIT_GPIO_A_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_0 + + { + ES_PIN_GPIO_B_0 , + +#ifdef ES_INIT_GPIO_B_0_MODE + ES_INIT_GPIO_B_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_0_LEVEL + ES_INIT_GPIO_B_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_0_IRQ_MODE + ES_INIT_GPIO_B_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_1 + + { + ES_PIN_GPIO_B_1 , + +#ifdef ES_INIT_GPIO_B_1_MODE + ES_INIT_GPIO_B_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_1_LEVEL + ES_INIT_GPIO_B_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_1_IRQ_MODE + ES_INIT_GPIO_B_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_2 + + { + ES_PIN_GPIO_B_2 , + +#ifdef ES_INIT_GPIO_B_2_MODE + ES_INIT_GPIO_B_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_2_LEVEL + ES_INIT_GPIO_B_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_2_IRQ_MODE + ES_INIT_GPIO_B_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_3 + + { + ES_PIN_GPIO_B_3 , + +#ifdef ES_INIT_GPIO_B_3_MODE + ES_INIT_GPIO_B_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_3_LEVEL + ES_INIT_GPIO_B_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_3_IRQ_MODE + ES_INIT_GPIO_B_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_4 + + { + ES_PIN_GPIO_B_4 , + +#ifdef ES_INIT_GPIO_B_4_MODE + ES_INIT_GPIO_B_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_4_LEVEL + ES_INIT_GPIO_B_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_4_IRQ_MODE + ES_INIT_GPIO_B_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_5 + + { + ES_PIN_GPIO_B_5 , + +#ifdef ES_INIT_GPIO_B_5_MODE + ES_INIT_GPIO_B_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_5_LEVEL + ES_INIT_GPIO_B_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_5_IRQ_MODE + ES_INIT_GPIO_B_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_6 + + { + ES_PIN_GPIO_B_6 , + +#ifdef ES_INIT_GPIO_B_6_MODE + ES_INIT_GPIO_B_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_6_LEVEL + ES_INIT_GPIO_B_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_6_IRQ_MODE + ES_INIT_GPIO_B_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_7 + + { + ES_PIN_GPIO_B_7 , + +#ifdef ES_INIT_GPIO_B_7_MODE + ES_INIT_GPIO_B_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_7_LEVEL + ES_INIT_GPIO_B_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_7_IRQ_MODE + ES_INIT_GPIO_B_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_8 + + { + ES_PIN_GPIO_B_8 , + +#ifdef ES_INIT_GPIO_B_8_MODE + ES_INIT_GPIO_B_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_8_LEVEL + ES_INIT_GPIO_B_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_8_IRQ_MODE + ES_INIT_GPIO_B_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_9 + + { + ES_PIN_GPIO_B_9 , + +#ifdef ES_INIT_GPIO_B_9_MODE + ES_INIT_GPIO_B_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_9_LEVEL + ES_INIT_GPIO_B_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_9_IRQ_MODE + ES_INIT_GPIO_B_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_10 + + { + ES_PIN_GPIO_B_10 , + +#ifdef ES_INIT_GPIO_B_10_MODE + ES_INIT_GPIO_B_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_10_LEVEL + ES_INIT_GPIO_B_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_10_IRQ_MODE + ES_INIT_GPIO_B_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_11 + + { + ES_PIN_GPIO_B_11 , + +#ifdef ES_INIT_GPIO_B_11_MODE + ES_INIT_GPIO_B_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_11_LEVEL + ES_INIT_GPIO_B_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_11_IRQ_MODE + ES_INIT_GPIO_B_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_12 + + { + ES_PIN_GPIO_B_12 , + +#ifdef ES_INIT_GPIO_B_12_MODE + ES_INIT_GPIO_B_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_12_LEVEL + ES_INIT_GPIO_B_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_12_IRQ_MODE + ES_INIT_GPIO_B_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_13 + + { + ES_PIN_GPIO_B_13 , + +#ifdef ES_INIT_GPIO_B_13_MODE + ES_INIT_GPIO_B_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_13_LEVEL + ES_INIT_GPIO_B_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_13_IRQ_MODE + ES_INIT_GPIO_B_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_14 + + { + ES_PIN_GPIO_B_14 , + +#ifdef ES_INIT_GPIO_B_14_MODE + ES_INIT_GPIO_B_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_14_LEVEL + ES_INIT_GPIO_B_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_14_IRQ_MODE + ES_INIT_GPIO_B_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_15 + + { + ES_PIN_GPIO_B_15 , + +#ifdef ES_INIT_GPIO_B_15_MODE + ES_INIT_GPIO_B_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_15_LEVEL + ES_INIT_GPIO_B_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_15_IRQ_MODE + ES_INIT_GPIO_B_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_0 + + { + ES_PIN_GPIO_C_0 , + +#ifdef ES_INIT_GPIO_C_0_MODE + ES_INIT_GPIO_C_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_0_LEVEL + ES_INIT_GPIO_C_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_0_IRQ_MODE + ES_INIT_GPIO_C_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_1 + + { + ES_PIN_GPIO_C_1 , + +#ifdef ES_INIT_GPIO_C_1_MODE + ES_INIT_GPIO_C_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_1_LEVEL + ES_INIT_GPIO_C_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_1_IRQ_MODE + ES_INIT_GPIO_C_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_2 + + { + ES_PIN_GPIO_C_2 , + +#ifdef ES_INIT_GPIO_C_2_MODE + ES_INIT_GPIO_C_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_2_LEVEL + ES_INIT_GPIO_C_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_2_IRQ_MODE + ES_INIT_GPIO_C_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_3 + + { + ES_PIN_GPIO_C_3 , + +#ifdef ES_INIT_GPIO_C_3_MODE + ES_INIT_GPIO_C_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_3_LEVEL + ES_INIT_GPIO_C_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_3_IRQ_MODE + ES_INIT_GPIO_C_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_4 + + { + ES_PIN_GPIO_C_4 , + +#ifdef ES_INIT_GPIO_C_4_MODE + ES_INIT_GPIO_C_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_4_LEVEL + ES_INIT_GPIO_C_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_4_IRQ_MODE + ES_INIT_GPIO_C_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_5 + + { + ES_PIN_GPIO_C_5 , + +#ifdef ES_INIT_GPIO_C_5_MODE + ES_INIT_GPIO_C_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_5_LEVEL + ES_INIT_GPIO_C_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_5_IRQ_MODE + ES_INIT_GPIO_C_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_6 + + { + ES_PIN_GPIO_C_6 , + +#ifdef ES_INIT_GPIO_C_6_MODE + ES_INIT_GPIO_C_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_6_LEVEL + ES_INIT_GPIO_C_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_6_IRQ_MODE + ES_INIT_GPIO_C_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_7 + + { + ES_PIN_GPIO_C_7 , + +#ifdef ES_INIT_GPIO_C_7_MODE + ES_INIT_GPIO_C_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_7_LEVEL + ES_INIT_GPIO_C_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_7_IRQ_MODE + ES_INIT_GPIO_C_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_8 + + { + ES_PIN_GPIO_C_8 , + +#ifdef ES_INIT_GPIO_C_8_MODE + ES_INIT_GPIO_C_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_8_LEVEL + ES_INIT_GPIO_C_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_8_IRQ_MODE + ES_INIT_GPIO_C_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_9 + + { + ES_PIN_GPIO_C_9 , + +#ifdef ES_INIT_GPIO_C_9_MODE + ES_INIT_GPIO_C_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_9_LEVEL + ES_INIT_GPIO_C_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_9_IRQ_MODE + ES_INIT_GPIO_C_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_10 + + { + ES_PIN_GPIO_C_10 , + +#ifdef ES_INIT_GPIO_C_10_MODE + ES_INIT_GPIO_C_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_10_LEVEL + ES_INIT_GPIO_C_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_10_IRQ_MODE + ES_INIT_GPIO_C_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_11 + + { + ES_PIN_GPIO_C_11 , + +#ifdef ES_INIT_GPIO_C_11_MODE + ES_INIT_GPIO_C_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_11_LEVEL + ES_INIT_GPIO_C_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_11_IRQ_MODE + ES_INIT_GPIO_C_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_12 + + { + ES_PIN_GPIO_C_12 , + +#ifdef ES_INIT_GPIO_C_12_MODE + ES_INIT_GPIO_C_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_12_LEVEL + ES_INIT_GPIO_C_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_12_IRQ_MODE + ES_INIT_GPIO_C_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_13 + + { + ES_PIN_GPIO_C_13 , + +#ifdef ES_INIT_GPIO_C_13_MODE + ES_INIT_GPIO_C_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_13_LEVEL + ES_INIT_GPIO_C_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_13_IRQ_MODE + ES_INIT_GPIO_C_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_14 + + { + ES_PIN_GPIO_C_14 , + +#ifdef ES_INIT_GPIO_C_14_MODE + ES_INIT_GPIO_C_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_14_LEVEL + ES_INIT_GPIO_C_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_14_IRQ_MODE + ES_INIT_GPIO_C_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_15 + + { + ES_PIN_GPIO_C_15 , + +#ifdef ES_INIT_GPIO_C_15_MODE + ES_INIT_GPIO_C_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_15_LEVEL + ES_INIT_GPIO_C_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_15_IRQ_MODE + ES_INIT_GPIO_C_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_0 + + { + ES_PIN_GPIO_D_0 , + +#ifdef ES_INIT_GPIO_D_0_MODE + ES_INIT_GPIO_D_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_0_LEVEL + ES_INIT_GPIO_D_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_0_IRQ_MODE + ES_INIT_GPIO_D_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_1 + + { + ES_PIN_GPIO_D_1 , + +#ifdef ES_INIT_GPIO_D_1_MODE + ES_INIT_GPIO_D_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_1_LEVEL + ES_INIT_GPIO_D_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_1_IRQ_MODE + ES_INIT_GPIO_D_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_2 + + { + ES_PIN_GPIO_D_2 , + +#ifdef ES_INIT_GPIO_D_2_MODE + ES_INIT_GPIO_D_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_2_LEVEL + ES_INIT_GPIO_D_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_2_IRQ_MODE + ES_INIT_GPIO_D_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_3 + + { + ES_PIN_GPIO_D_3 , + +#ifdef ES_INIT_GPIO_D_3_MODE + ES_INIT_GPIO_D_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_3_LEVEL + ES_INIT_GPIO_D_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_3_IRQ_MODE + ES_INIT_GPIO_D_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_4 + + { + ES_PIN_GPIO_D_4 , + +#ifdef ES_INIT_GPIO_D_4_MODE + ES_INIT_GPIO_D_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_4_LEVEL + ES_INIT_GPIO_D_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_4_IRQ_MODE + ES_INIT_GPIO_D_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_5 + + { + ES_PIN_GPIO_D_5 , + +#ifdef ES_INIT_GPIO_D_5_MODE + ES_INIT_GPIO_D_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_5_LEVEL + ES_INIT_GPIO_D_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_5_IRQ_MODE + ES_INIT_GPIO_D_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_6 + + { + ES_PIN_GPIO_D_6 , + +#ifdef ES_INIT_GPIO_D_6_MODE + ES_INIT_GPIO_D_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_6_LEVEL + ES_INIT_GPIO_D_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_6_IRQ_MODE + ES_INIT_GPIO_D_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_7 + + { + ES_PIN_GPIO_D_7 , + +#ifdef ES_INIT_GPIO_D_7_MODE + ES_INIT_GPIO_D_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_7_LEVEL + ES_INIT_GPIO_D_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_7_IRQ_MODE + ES_INIT_GPIO_D_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_8 + + { + ES_PIN_GPIO_D_8 , + +#ifdef ES_INIT_GPIO_D_8_MODE + ES_INIT_GPIO_D_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_8_LEVEL + ES_INIT_GPIO_D_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_8_IRQ_MODE + ES_INIT_GPIO_D_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_9 + + { + ES_PIN_GPIO_D_9 , + +#ifdef ES_INIT_GPIO_D_9_MODE + ES_INIT_GPIO_D_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_9_LEVEL + ES_INIT_GPIO_D_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_9_IRQ_MODE + ES_INIT_GPIO_D_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_10 + + { + ES_PIN_GPIO_D_10 , + +#ifdef ES_INIT_GPIO_D_10_MODE + ES_INIT_GPIO_D_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_10_LEVEL + ES_INIT_GPIO_D_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_10_IRQ_MODE + ES_INIT_GPIO_D_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_11 + + { + ES_PIN_GPIO_D_11 , + +#ifdef ES_INIT_GPIO_D_11_MODE + ES_INIT_GPIO_D_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_11_LEVEL + ES_INIT_GPIO_D_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_11_IRQ_MODE + ES_INIT_GPIO_D_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_12 + + { + ES_PIN_GPIO_D_12 , + +#ifdef ES_INIT_GPIO_D_12_MODE + ES_INIT_GPIO_D_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_12_LEVEL + ES_INIT_GPIO_D_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_12_IRQ_MODE + ES_INIT_GPIO_D_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_13 + + { + ES_PIN_GPIO_D_13 , + +#ifdef ES_INIT_GPIO_D_13_MODE + ES_INIT_GPIO_D_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_13_LEVEL + ES_INIT_GPIO_D_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_13_IRQ_MODE + ES_INIT_GPIO_D_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_14 + + { + ES_PIN_GPIO_D_14 , + +#ifdef ES_INIT_GPIO_D_14_MODE + ES_INIT_GPIO_D_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_14_LEVEL + ES_INIT_GPIO_D_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_14_IRQ_MODE + ES_INIT_GPIO_D_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_15 + + { + ES_PIN_GPIO_D_15 , + +#ifdef ES_INIT_GPIO_D_15_MODE + ES_INIT_GPIO_D_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_15_LEVEL + ES_INIT_GPIO_D_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_15_IRQ_MODE + ES_INIT_GPIO_D_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_0 + + { + ES_PIN_GPIO_E_0 , + +#ifdef ES_INIT_GPIO_E_0_MODE + ES_INIT_GPIO_E_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_0_LEVEL + ES_INIT_GPIO_E_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_0_IRQ_MODE + ES_INIT_GPIO_E_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_1 + + { + ES_PIN_GPIO_E_1 , + +#ifdef ES_INIT_GPIO_E_1_MODE + ES_INIT_GPIO_E_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_1_LEVEL + ES_INIT_GPIO_E_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_1_IRQ_MODE + ES_INIT_GPIO_E_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_2 + + { + ES_PIN_GPIO_E_2 , + +#ifdef ES_INIT_GPIO_E_2_MODE + ES_INIT_GPIO_E_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_2_LEVEL + ES_INIT_GPIO_E_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_2_IRQ_MODE + ES_INIT_GPIO_E_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_3 + + { + ES_PIN_GPIO_E_3 , + +#ifdef ES_INIT_GPIO_E_3_MODE + ES_INIT_GPIO_E_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_3_LEVEL + ES_INIT_GPIO_E_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_3_IRQ_MODE + ES_INIT_GPIO_E_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_4 + + { + ES_PIN_GPIO_E_4 , + +#ifdef ES_INIT_GPIO_E_4_MODE + ES_INIT_GPIO_E_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_4_LEVEL + ES_INIT_GPIO_E_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_4_IRQ_MODE + ES_INIT_GPIO_E_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_5 + + { + ES_PIN_GPIO_E_5 , + +#ifdef ES_INIT_GPIO_E_5_MODE + ES_INIT_GPIO_E_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_5_LEVEL + ES_INIT_GPIO_E_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_5_IRQ_MODE + ES_INIT_GPIO_E_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_6 + + { + ES_PIN_GPIO_E_6 , + +#ifdef ES_INIT_GPIO_E_6_MODE + ES_INIT_GPIO_E_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_6_LEVEL + ES_INIT_GPIO_E_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_6_IRQ_MODE + ES_INIT_GPIO_E_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_7 + + { + ES_PIN_GPIO_E_7 , + +#ifdef ES_INIT_GPIO_E_7_MODE + ES_INIT_GPIO_E_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_7_LEVEL + ES_INIT_GPIO_E_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_7_IRQ_MODE + ES_INIT_GPIO_E_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_8 + + { + ES_PIN_GPIO_E_8 , + +#ifdef ES_INIT_GPIO_E_8_MODE + ES_INIT_GPIO_E_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_8_LEVEL + ES_INIT_GPIO_E_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_8_IRQ_MODE + ES_INIT_GPIO_E_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_9 + + { + ES_PIN_GPIO_E_9 , + +#ifdef ES_INIT_GPIO_E_9_MODE + ES_INIT_GPIO_E_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_9_LEVEL + ES_INIT_GPIO_E_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_9_IRQ_MODE + ES_INIT_GPIO_E_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_10 + + { + ES_PIN_GPIO_E_10 , + +#ifdef ES_INIT_GPIO_E_10_MODE + ES_INIT_GPIO_E_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_10_LEVEL + ES_INIT_GPIO_E_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_10_IRQ_MODE + ES_INIT_GPIO_E_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_11 + + { + ES_PIN_GPIO_E_11 , + +#ifdef ES_INIT_GPIO_E_11_MODE + ES_INIT_GPIO_E_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_11_LEVEL + ES_INIT_GPIO_E_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_11_IRQ_MODE + ES_INIT_GPIO_E_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_12 + + { + ES_PIN_GPIO_E_12 , + +#ifdef ES_INIT_GPIO_E_12_MODE + ES_INIT_GPIO_E_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_12_LEVEL + ES_INIT_GPIO_E_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_12_IRQ_MODE + ES_INIT_GPIO_E_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_13 + + { + ES_PIN_GPIO_E_13 , + +#ifdef ES_INIT_GPIO_E_13_MODE + ES_INIT_GPIO_E_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_13_LEVEL + ES_INIT_GPIO_E_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_13_IRQ_MODE + ES_INIT_GPIO_E_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_14 + + { + ES_PIN_GPIO_E_14 , + +#ifdef ES_INIT_GPIO_E_14_MODE + ES_INIT_GPIO_E_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_14_LEVEL + ES_INIT_GPIO_E_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_14_IRQ_MODE + ES_INIT_GPIO_E_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_15 + + { + ES_PIN_GPIO_E_15 , + +#ifdef ES_INIT_GPIO_E_15_MODE + ES_INIT_GPIO_E_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_15_LEVEL + ES_INIT_GPIO_E_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_15_IRQ_MODE + ES_INIT_GPIO_E_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_0 + + { + ES_PIN_GPIO_F_0 , + +#ifdef ES_INIT_GPIO_F_0_MODE + ES_INIT_GPIO_F_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_0_LEVEL + ES_INIT_GPIO_F_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_0_IRQ_MODE + ES_INIT_GPIO_F_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_1 + + { + ES_PIN_GPIO_F_1 , + +#ifdef ES_INIT_GPIO_F_1_MODE + ES_INIT_GPIO_F_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_1_LEVEL + ES_INIT_GPIO_F_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_1_IRQ_MODE + ES_INIT_GPIO_F_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_2 + + { + ES_PIN_GPIO_F_2 , + +#ifdef ES_INIT_GPIO_F_2_MODE + ES_INIT_GPIO_F_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_2_LEVEL + ES_INIT_GPIO_F_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_2_IRQ_MODE + ES_INIT_GPIO_F_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_3 + + { + ES_PIN_GPIO_F_3 , + +#ifdef ES_INIT_GPIO_F_3_MODE + ES_INIT_GPIO_F_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_3_LEVEL + ES_INIT_GPIO_F_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_3_IRQ_MODE + ES_INIT_GPIO_F_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_4 + + { + ES_PIN_GPIO_F_4 , + +#ifdef ES_INIT_GPIO_F_4_MODE + ES_INIT_GPIO_F_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_4_LEVEL + ES_INIT_GPIO_F_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_4_IRQ_MODE + ES_INIT_GPIO_F_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_5 + + { + ES_PIN_GPIO_F_5 , + +#ifdef ES_INIT_GPIO_F_5_MODE + ES_INIT_GPIO_F_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_5_LEVEL + ES_INIT_GPIO_F_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_5_IRQ_MODE + ES_INIT_GPIO_F_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_6 + + { + ES_PIN_GPIO_F_6 , + +#ifdef ES_INIT_GPIO_F_6_MODE + ES_INIT_GPIO_F_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_6_LEVEL + ES_INIT_GPIO_F_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_6_IRQ_MODE + ES_INIT_GPIO_F_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_7 + + { + ES_PIN_GPIO_F_7 , + +#ifdef ES_INIT_GPIO_F_7_MODE + ES_INIT_GPIO_F_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_7_LEVEL + ES_INIT_GPIO_F_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_7_IRQ_MODE + ES_INIT_GPIO_F_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_8 + + { + ES_PIN_GPIO_F_8 , + +#ifdef ES_INIT_GPIO_F_8_MODE + ES_INIT_GPIO_F_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_8_LEVEL + ES_INIT_GPIO_F_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_8_IRQ_MODE + ES_INIT_GPIO_F_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_9 + + { + ES_PIN_GPIO_F_9 , + +#ifdef ES_INIT_GPIO_F_9_MODE + ES_INIT_GPIO_F_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_9_LEVEL + ES_INIT_GPIO_F_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_9_IRQ_MODE + ES_INIT_GPIO_F_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_10 + + { + ES_PIN_GPIO_F_10 , + +#ifdef ES_INIT_GPIO_F_10_MODE + ES_INIT_GPIO_F_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_10_LEVEL + ES_INIT_GPIO_F_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_10_IRQ_MODE + ES_INIT_GPIO_F_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_11 + + { + ES_PIN_GPIO_F_11 , + +#ifdef ES_INIT_GPIO_F_11_MODE + ES_INIT_GPIO_F_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_11_LEVEL + ES_INIT_GPIO_F_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_11_IRQ_MODE + ES_INIT_GPIO_F_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_12 + + { + ES_PIN_GPIO_F_12 , + +#ifdef ES_INIT_GPIO_F_12_MODE + ES_INIT_GPIO_F_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_12_LEVEL + ES_INIT_GPIO_F_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_12_IRQ_MODE + ES_INIT_GPIO_F_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_13 + + { + ES_PIN_GPIO_F_13 , + +#ifdef ES_INIT_GPIO_F_13_MODE + ES_INIT_GPIO_F_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_13_LEVEL + ES_INIT_GPIO_F_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_13_IRQ_MODE + ES_INIT_GPIO_F_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_14 + + { + ES_PIN_GPIO_F_14 , + +#ifdef ES_INIT_GPIO_F_14_MODE + ES_INIT_GPIO_F_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_14_LEVEL + ES_INIT_GPIO_F_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_14_IRQ_MODE + ES_INIT_GPIO_F_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_15 + + { + ES_PIN_GPIO_F_15 , + +#ifdef ES_INIT_GPIO_F_15_MODE + ES_INIT_GPIO_F_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_15_LEVEL + ES_INIT_GPIO_F_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_15_IRQ_MODE + ES_INIT_GPIO_F_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_0 + + { + ES_PIN_GPIO_G_0 , + +#ifdef ES_INIT_GPIO_G_0_MODE + ES_INIT_GPIO_G_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_0_LEVEL + ES_INIT_GPIO_G_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_0_IRQ_MODE + ES_INIT_GPIO_G_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_1 + + { + ES_PIN_GPIO_G_1 , + +#ifdef ES_INIT_GPIO_G_1_MODE + ES_INIT_GPIO_G_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_1_LEVEL + ES_INIT_GPIO_G_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_1_IRQ_MODE + ES_INIT_GPIO_G_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_2 + + { + ES_PIN_GPIO_G_2 , + +#ifdef ES_INIT_GPIO_G_2_MODE + ES_INIT_GPIO_G_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_2_LEVEL + ES_INIT_GPIO_G_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_2_IRQ_MODE + ES_INIT_GPIO_G_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_3 + + { + ES_PIN_GPIO_G_3 , + +#ifdef ES_INIT_GPIO_G_3_MODE + ES_INIT_GPIO_G_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_3_LEVEL + ES_INIT_GPIO_G_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_3_IRQ_MODE + ES_INIT_GPIO_G_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_4 + + { + ES_PIN_GPIO_G_4 , + +#ifdef ES_INIT_GPIO_G_4_MODE + ES_INIT_GPIO_G_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_4_LEVEL + ES_INIT_GPIO_G_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_4_IRQ_MODE + ES_INIT_GPIO_G_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_5 + + { + ES_PIN_GPIO_G_5 , + +#ifdef ES_INIT_GPIO_G_5_MODE + ES_INIT_GPIO_G_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_5_LEVEL + ES_INIT_GPIO_G_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_5_IRQ_MODE + ES_INIT_GPIO_G_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_6 + + { + ES_PIN_GPIO_G_6 , + +#ifdef ES_INIT_GPIO_G_6_MODE + ES_INIT_GPIO_G_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_6_LEVEL + ES_INIT_GPIO_G_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_6_IRQ_MODE + ES_INIT_GPIO_G_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_7 + + { + ES_PIN_GPIO_G_7 , + +#ifdef ES_INIT_GPIO_G_7_MODE + ES_INIT_GPIO_G_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_7_LEVEL + ES_INIT_GPIO_G_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_7_IRQ_MODE + ES_INIT_GPIO_G_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_8 + + { + ES_PIN_GPIO_G_8 , + +#ifdef ES_INIT_GPIO_G_8_MODE + ES_INIT_GPIO_G_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_8_LEVEL + ES_INIT_GPIO_G_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_8_IRQ_MODE + ES_INIT_GPIO_G_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_9 + + { + ES_PIN_GPIO_G_9 , + +#ifdef ES_INIT_GPIO_G_9_MODE + ES_INIT_GPIO_G_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_9_LEVEL + ES_INIT_GPIO_G_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_9_IRQ_MODE + ES_INIT_GPIO_G_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_10 + + { + ES_PIN_GPIO_G_10 , + +#ifdef ES_INIT_GPIO_G_10_MODE + ES_INIT_GPIO_G_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_10_LEVEL + ES_INIT_GPIO_G_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_10_IRQ_MODE + ES_INIT_GPIO_G_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_11 + + { + ES_PIN_GPIO_G_11 , + +#ifdef ES_INIT_GPIO_G_11_MODE + ES_INIT_GPIO_G_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_11_LEVEL + ES_INIT_GPIO_G_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_11_IRQ_MODE + ES_INIT_GPIO_G_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_12 + + { + ES_PIN_GPIO_G_12 , + +#ifdef ES_INIT_GPIO_G_12_MODE + ES_INIT_GPIO_G_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_12_LEVEL + ES_INIT_GPIO_G_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_12_IRQ_MODE + ES_INIT_GPIO_G_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_13 + + { + ES_PIN_GPIO_G_13 , + +#ifdef ES_INIT_GPIO_G_13_MODE + ES_INIT_GPIO_G_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_13_LEVEL + ES_INIT_GPIO_G_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_13_IRQ_MODE + ES_INIT_GPIO_G_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_14 + + { + ES_PIN_GPIO_G_14 , + +#ifdef ES_INIT_GPIO_G_14_MODE + ES_INIT_GPIO_G_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_14_LEVEL + ES_INIT_GPIO_G_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_14_IRQ_MODE + ES_INIT_GPIO_G_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_15 + + { + ES_PIN_GPIO_G_15 , + +#ifdef ES_INIT_GPIO_G_15_MODE + ES_INIT_GPIO_G_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_15_LEVEL + ES_INIT_GPIO_G_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_15_IRQ_MODE + ES_INIT_GPIO_G_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_0 + + { + ES_PIN_GPIO_H_0 , + +#ifdef ES_INIT_GPIO_H_0_MODE + ES_INIT_GPIO_H_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_0_LEVEL + ES_INIT_GPIO_H_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_0_IRQ_MODE + ES_INIT_GPIO_H_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_1 + + { + ES_PIN_GPIO_H_1 , + +#ifdef ES_INIT_GPIO_H_1_MODE + ES_INIT_GPIO_H_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_1_LEVEL + ES_INIT_GPIO_H_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_1_IRQ_MODE + ES_INIT_GPIO_H_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_2 + + { + ES_PIN_GPIO_H_2 , + +#ifdef ES_INIT_GPIO_H_2_MODE + ES_INIT_GPIO_H_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_2_LEVEL + ES_INIT_GPIO_H_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_2_IRQ_MODE + ES_INIT_GPIO_H_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_3 + + { + ES_PIN_GPIO_H_3 , + +#ifdef ES_INIT_GPIO_H_3_MODE + ES_INIT_GPIO_H_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_3_LEVEL + ES_INIT_GPIO_H_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_3_IRQ_MODE + ES_INIT_GPIO_H_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_4 + + { + ES_PIN_GPIO_H_4 , + +#ifdef ES_INIT_GPIO_H_4_MODE + ES_INIT_GPIO_H_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_4_LEVEL + ES_INIT_GPIO_H_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_4_IRQ_MODE + ES_INIT_GPIO_H_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_5 + + { + ES_PIN_GPIO_H_5 , + +#ifdef ES_INIT_GPIO_H_5_MODE + ES_INIT_GPIO_H_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_5_LEVEL + ES_INIT_GPIO_H_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_5_IRQ_MODE + ES_INIT_GPIO_H_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_6 + + { + ES_PIN_GPIO_H_6 , + +#ifdef ES_INIT_GPIO_H_6_MODE + ES_INIT_GPIO_H_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_6_LEVEL + ES_INIT_GPIO_H_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_6_IRQ_MODE + ES_INIT_GPIO_H_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_7 + + { + ES_PIN_GPIO_H_7 , + +#ifdef ES_INIT_GPIO_H_7_MODE + ES_INIT_GPIO_H_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_7_LEVEL + ES_INIT_GPIO_H_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_7_IRQ_MODE + ES_INIT_GPIO_H_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_8 + + { + ES_PIN_GPIO_H_8 , + +#ifdef ES_INIT_GPIO_H_8_MODE + ES_INIT_GPIO_H_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_8_LEVEL + ES_INIT_GPIO_H_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_8_IRQ_MODE + ES_INIT_GPIO_H_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_9 + + { + ES_PIN_GPIO_H_9 , + +#ifdef ES_INIT_GPIO_H_9_MODE + ES_INIT_GPIO_H_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_9_LEVEL + ES_INIT_GPIO_H_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_9_IRQ_MODE + ES_INIT_GPIO_H_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_10 + + { + ES_PIN_GPIO_H_10 , + +#ifdef ES_INIT_GPIO_H_10_MODE + ES_INIT_GPIO_H_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_10_LEVEL + ES_INIT_GPIO_H_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_10_IRQ_MODE + ES_INIT_GPIO_H_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_11 + + { + ES_PIN_GPIO_H_11 , + +#ifdef ES_INIT_GPIO_H_11_MODE + ES_INIT_GPIO_H_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_11_LEVEL + ES_INIT_GPIO_H_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_11_IRQ_MODE + ES_INIT_GPIO_H_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_12 + + { + ES_PIN_GPIO_H_12 , + +#ifdef ES_INIT_GPIO_H_12_MODE + ES_INIT_GPIO_H_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_12_LEVEL + ES_INIT_GPIO_H_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_12_IRQ_MODE + ES_INIT_GPIO_H_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_13 + + { + ES_PIN_GPIO_H_13 , + +#ifdef ES_INIT_GPIO_H_13_MODE + ES_INIT_GPIO_H_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_13_LEVEL + ES_INIT_GPIO_H_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_13_IRQ_MODE + ES_INIT_GPIO_H_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_14 + + { + ES_PIN_GPIO_H_14 , + +#ifdef ES_INIT_GPIO_H_14_MODE + ES_INIT_GPIO_H_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_14_LEVEL + ES_INIT_GPIO_H_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_14_IRQ_MODE + ES_INIT_GPIO_H_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_15 + + { + ES_PIN_GPIO_H_15 , + +#ifdef ES_INIT_GPIO_H_15_MODE + ES_INIT_GPIO_H_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_15_LEVEL + ES_INIT_GPIO_H_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_15_IRQ_MODE + ES_INIT_GPIO_H_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + + + +}; + +#endif + + + +#endif diff --git a/bsp/essemi/es32f0654/drivers/ES/es_conf_info_hwtimer.h b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_hwtimer.h new file mode 100644 index 0000000000..d829c68f93 --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_hwtimer.h @@ -0,0 +1,103 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_HWTIMER_H__ +#define __ES_CONF_INFO_HWTIMER_H__ + +#include +#include + +#define ES_C_HWTIMER_MODE_UP HWTIMER_CNTMODE_UP +#define ES_C_HWTIMER_MODE_DOWN HWTIMER_CNTMODE_DW + +/* HWTIMER 配置 */ + +/* codes_main */ + + + +#ifndef ES_AD16C4T0_HWTIMER_MODE +#define ES_AD16C4T0_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif + +#ifndef ES_GP16C4T0_HWTIMER_MODE +#define ES_GP16C4T0_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_GP16C2T0_HWTIMER_MODE +#define ES_GP16C2T0_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_GP1624T1_HWTIMER_MODE +#define ES_GP16C2T1_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_BS16T0_HWTIMER_MODE +#define ES_BS16T0_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_BS16T1_HWTIMER_MODE +#define ES_BS16T1_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_BS16T2_HWTIMER_MODE +#define ES_BS16T2_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_BS16T3_HWTIMER_MODE +#define ES_BS16T3_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif + + + + +#define ES_AD16C4T0_HWTIMER_PRES 1 +#define ES_GP16C4T0_HWTIMER_PRES 1 +#define ES_GP16C2T0_HWTIMER_PRES 1 +#define ES_GP16C2T1_HWTIMER_PRES 1 +#define ES_BS16T0_HWTIMER_PRES 1 +#define ES_BS16T1_HWTIMER_PRES 1 +#define ES_BS16T2_HWTIMER_PRES 1 +#define ES_BS16T3_HWTIMER_PRES 1 + +#ifndef ES_DEVICE_NAME_AD16C4T0_HWTIMER +#define ES_DEVICE_NAME_AD16C4T0_HWTIMER "timer0" +#endif +#ifndef ES_DEVICE_NAME_GP16C4T0_HWTIMER +#define ES_DEVICE_NAME_GP16C4T0_HWTIMER "timer1" +#endif +#ifndef ES_DEVICE_NAME_GP16C2T0_HWTIMER +#define ES_DEVICE_NAME_GP16C2T0_HWTIMER "timer2" +#endif +#ifndef ES_DEVICE_NAME_GP16C2T1_HWTIMER +#define ES_DEVICE_NAME_GP16C2T1_HWTIMER "timer3" +#endif +#ifndef ES_DEVICE_NAME_BS16T0_HWTIMER +#define ES_DEVICE_NAME_BS16T0_HWTIMER "timer4" +#endif +#ifndef ES_DEVICE_NAME_BS16T1_HWTIMER +#define ES_DEVICE_NAME_BS16T1_HWTIMER "timer5" +#endif +#ifndef ES_DEVICE_NAME_BS16T2_HWTIMER +#define ES_DEVICE_NAME_BS16T2_HWTIMER "timer6" +#endif +#ifndef ES_DEVICE_NAME_BS16T3_HWTIMER +#define ES_DEVICE_NAME_BS16T3_HWTIMER "timer7" +#endif + + +#endif diff --git a/bsp/essemi/es32f0654/drivers/ES/es_conf_info_i2c.h b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_i2c.h new file mode 100644 index 0000000000..65310fce01 --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_i2c.h @@ -0,0 +1,95 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_I2C_H__ +#define __ES_CONF_INFO_I2C_H__ + +#include "es_conf_info_map.h" +#include +#include +#include + +#define ES_C_I2C_STRETCH I2C_NOSTRETCH_DISABLE +#define ES_C_I2C_NO_STRETCH I2C_NOSTRETCH_ENABLE + +#define ES_C_I2C_GENERALCALL I2C_GENERALCALL_ENABLE +#define ES_C_I2C_NO_GENERALCALL I2C_GENERALCALL_DISABLE + + +#define ES_C_I2C_ADDR_7_MODE I2C_ADDR_7BIT +#define ES_C_I2C_ADDR_10_MODE I2C_ADDR_10BIT + + +/* I2C 配置 */ + + + +/* codes_main */ + + + + + +#ifndef ES_DEVICE_NAME_I2C0 +#define ES_DEVICE_NAME_I2C0 "i2c0" +#endif + +#ifndef ES_DEVICE_NAME_I2C1 +#define ES_DEVICE_NAME_I2C1 "i2c1" +#endif + +#ifndef ES_I2C0_CLK_SPEED +#define ES_I2C0_CLK_SPEED 100000 +#endif +#ifndef ES_I2C0_OWN_ADDR1 +#define ES_I2C0_OWN_ADDR1 0x20 +#endif +#ifndef ES_I2C0_GENERAL_CALL +#define ES_I2C0_GENERAL_CALL ES_C_I2C_NO_GENERALCALL +#endif +#ifndef ES_I2C0_STRETCH +#define ES_I2C0_STRETCH ES_C_I2C_STRETCH +#endif +#ifndef ES_I2C0_ADDR_MODE +#define ES_I2C0_ADDR_MODE ES_C_I2C_ADDR_7_MODE +#endif + +#ifndef ES_I2C1_CLK_SPEED +#define ES_I2C1_CLK_SPEED 100000 +#endif +#ifndef ES_I2C1_OWN_ADDR1 +#define ES_I2C1_OWN_ADDR1 0x20 +#endif +#ifndef ES_I2C1_GENERAL_CALL +#define ES_I2C1_GENERAL_CALL ES_C_I2C_NO_GENERALCALL +#endif +#ifndef ES_I2C1_STRETCH +#define ES_I2C1_STRETCH ES_C_I2C_STRETCH +#endif +#ifndef ES_I2C1_ADDR_MODE +#define ES_I2C1_ADDR_MODE ES_C_I2C_ADDR_7_MODE +#endif + + + +#endif diff --git a/bsp/essemi/es32f0654/drivers/ES/es_conf_info_map.h b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_map.h new file mode 100644 index 0000000000..62274d122f --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_map.h @@ -0,0 +1,2691 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __es_conf_info_map_H__ +#define __es_conf_info_map_H__ + +#include + + +#define __ES_PIN(index, gpio, gpio_index) {index, GPIO##gpio, GPIO_PIN_##gpio_index} +#define __ES_PIN_DEFAULT {-1, 0, 0} + +struct pin_index +{ + int index; + GPIO_TypeDef *gpio; + uint32_t pin; +}; + +static const struct pin_index pins[] = +{ + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, + __ES_PIN(2, C, 13), + __ES_PIN(3, C, 14), + __ES_PIN(4, C, 15), + __ES_PIN(5, H, 0), + __ES_PIN(6, H, 1), + __ES_PIN_DEFAULT, + __ES_PIN(8, C, 0), + __ES_PIN(9, C, 1), + __ES_PIN(10, C, 2), + __ES_PIN(11, C, 3), + __ES_PIN(12, H, 3), + __ES_PIN(13, H, 4), + __ES_PIN(14, A, 0), + __ES_PIN(15, A, 1), + __ES_PIN(16, A, 2), + __ES_PIN(17, A, 3), + __ES_PIN(18, F, 0), + __ES_PIN(19, F, 1), + __ES_PIN(20, A, 4), + __ES_PIN(21, A, 5), + __ES_PIN(22, A, 6), + __ES_PIN(23, A, 7), + __ES_PIN(24, C, 4), + __ES_PIN(25, C, 5), + __ES_PIN(26, B, 0), + __ES_PIN(27, B, 1), + __ES_PIN(28, B, 2), + __ES_PIN(29, B, 10), + __ES_PIN(30, B, 11), + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, + __ES_PIN(33, B, 12), + __ES_PIN(34, B, 13), + __ES_PIN(35, B, 14), + __ES_PIN(36, B, 15), + __ES_PIN(37, C, 6), + __ES_PIN(38, C, 7), + __ES_PIN(39, C, 8), + __ES_PIN(40, C, 9), + __ES_PIN(41, A, 8), + __ES_PIN(42, A, 9), + __ES_PIN(43, A, 10), + __ES_PIN(44, A, 11), + __ES_PIN(45, A, 12), + __ES_PIN(46, A, 13), + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, + __ES_PIN(49, A, 14), + __ES_PIN(50, A, 15), + __ES_PIN(51, C, 10), + __ES_PIN(52, C, 11), + __ES_PIN(53, C, 12), + __ES_PIN(54, D, 2), + __ES_PIN(55, B, 3), + __ES_PIN(56, B, 4), + __ES_PIN(57, B, 5), + __ES_PIN(58, B, 6), + __ES_PIN(59, B, 7), + __ES_PIN(60, H, 2), + __ES_PIN(61, B, 8), + __ES_PIN(62, B, 9), + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, +}; + +#define ES_GPIO_ADC_CH0_GPIO GPIOC +#define ES_GPIO_ADC_CH1_GPIO GPIOC +#define ES_GPIO_ADC_CH2_GPIO GPIOC +#define ES_GPIO_ADC_CH3_GPIO GPIOC +#define ES_GPIO_ADC_CH4_GPIO GPIOA +#define ES_GPIO_ADC_CH5_GPIO GPIOA +#define ES_GPIO_ADC_CH6_GPIO GPIOA +#define ES_GPIO_ADC_CH7_GPIO GPIOA +#define ES_GPIO_ADC_CH8_GPIO GPIOA +#define ES_GPIO_ADC_CH9_GPIO GPIOA +#define ES_GPIO_ADC_CH10_GPIO GPIOA +#define ES_GPIO_ADC_CH11_GPIO GPIOA +#define ES_GPIO_ADC_CH12_GPIO GPIOC +#define ES_GPIO_ADC_CH13_GPIO GPIOC +#define ES_GPIO_ADC_CH14_GPIO GPIOB +#define ES_GPIO_ADC_CH15_GPIO GPIOB + +#define ES_GPIO_ADC_CH0_PIN GPIO_PIN_0 +#define ES_GPIO_ADC_CH1_PIN GPIO_PIN_1 +#define ES_GPIO_ADC_CH2_PIN GPIO_PIN_2 +#define ES_GPIO_ADC_CH3_PIN GPIO_PIN_3 +#define ES_GPIO_ADC_CH4_PIN GPIO_PIN_0 +#define ES_GPIO_ADC_CH5_PIN GPIO_PIN_1 +#define ES_GPIO_ADC_CH6_PIN GPIO_PIN_2 +#define ES_GPIO_ADC_CH7_PIN GPIO_PIN_3 +#define ES_GPIO_ADC_CH8_PIN GPIO_PIN_4 +#define ES_GPIO_ADC_CH9_PIN GPIO_PIN_5 +#define ES_GPIO_ADC_CH10_PIN GPIO_PIN_6 +#define ES_GPIO_ADC_CH11_PIN GPIO_PIN_7 +#define ES_GPIO_ADC_CH12_PIN GPIO_PIN_4 +#define ES_GPIO_ADC_CH13_PIN GPIO_PIN_5 +#define ES_GPIO_ADC_CH14_PIN GPIO_PIN_0 +#define ES_GPIO_ADC_CH15_PIN GPIO_PIN_1 + + + + +#define ES_PIN_GPIO_C_13 2 +#define ES_PIN_GPIO_C_14 3 +#define ES_PIN_GPIO_C_15 4 +#define ES_PIN_GPIO_H_0 5 +#define ES_PIN_GPIO_H_1 6 +#define ES_PIN_GPIO_C_0 8 +#define ES_PIN_GPIO_C_1 9 +#define ES_PIN_GPIO_C_2 10 +#define ES_PIN_GPIO_C_3 11 +#define ES_PIN_GPIO_H_3 12 +#define ES_PIN_GPIO_H_4 13 +#define ES_PIN_GPIO_A_0 14 +#define ES_PIN_GPIO_A_1 15 +#define ES_PIN_GPIO_A_2 16 +#define ES_PIN_GPIO_A_3 17 +#define ES_PIN_GPIO_F_0 18 +#define ES_PIN_GPIO_F_1 19 +#define ES_PIN_GPIO_A_4 20 +#define ES_PIN_GPIO_A_5 21 +#define ES_PIN_GPIO_A_6 22 +#define ES_PIN_GPIO_A_7 23 +#define ES_PIN_GPIO_C_4 24 +#define ES_PIN_GPIO_C_5 25 +#define ES_PIN_GPIO_B_0 26 +#define ES_PIN_GPIO_B_1 27 +#define ES_PIN_GPIO_B_2 28 +#define ES_PIN_GPIO_B_10 29 +#define ES_PIN_GPIO_B_11 30 +#define ES_PIN_GPIO_B_12 33 +#define ES_PIN_GPIO_B_13 34 +#define ES_PIN_GPIO_B_14 35 +#define ES_PIN_GPIO_B_15 36 +#define ES_PIN_GPIO_C_6 37 +#define ES_PIN_GPIO_C_7 38 +#define ES_PIN_GPIO_C_8 39 +#define ES_PIN_GPIO_C_9 40 +#define ES_PIN_GPIO_A_8 41 +#define ES_PIN_GPIO_A_9 42 +#define ES_PIN_GPIO_A_10 43 +#define ES_PIN_GPIO_A_11 44 +#define ES_PIN_GPIO_A_12 45 +#define ES_PIN_GPIO_A_13 46 +#define ES_PIN_GPIO_A_14 49 +#define ES_PIN_GPIO_A_15 50 +#define ES_PIN_GPIO_C_10 51 +#define ES_PIN_GPIO_C_11 52 +#define ES_PIN_GPIO_C_12 53 +#define ES_PIN_GPIO_D_2 54 +#define ES_PIN_GPIO_B_3 55 +#define ES_PIN_GPIO_B_4 56 +#define ES_PIN_GPIO_B_5 57 +#define ES_PIN_GPIO_B_6 58 +#define ES_PIN_GPIO_B_7 59 +#define ES_PIN_GPIO_H_2 60 +#define ES_PIN_GPIO_B_8 61 +#define ES_PIN_GPIO_B_9 62 + + + +/* UART_TX */ + + +#ifndef ES_UART0_TX_GPIO_FUNC +#define ES_UART0_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART0_TX_GPIO_PORT +#define ES_UART0_TX_GPIO_PORT GPIOB +#endif +#ifndef ES_UART0_TX_GPIO_PIN +#define ES_UART0_TX_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_UART0_TX_PIN +#ifdef ES_PIN_GPIO_B_10 +#define ES_UART0_TX_PIN ES_PIN_GPIO_B_10 +#endif +#endif + +#ifndef ES_UART0_TX_GPIO_FUNC +#define ES_UART0_TX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART0_TX_GPIO_PORT +#define ES_UART0_TX_GPIO_PORT GPIOA +#endif +#ifndef ES_UART0_TX_GPIO_PIN +#define ES_UART0_TX_GPIO_PIN GPIO_PIN_9 +#endif + +#ifndef ES_UART0_TX_PIN +#ifdef ES_PIN_GPIO_A_9 +#define ES_UART0_TX_PIN ES_PIN_GPIO_A_9 +#endif +#endif + +#ifndef ES_UART0_TX_GPIO_FUNC +#define ES_UART0_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART0_TX_GPIO_PORT +#define ES_UART0_TX_GPIO_PORT GPIOH +#endif +#ifndef ES_UART0_TX_GPIO_PIN +#define ES_UART0_TX_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_UART0_TX_PIN +#ifdef ES_PIN_GPIO_H_0 +#define ES_UART0_TX_PIN ES_PIN_GPIO_H_0 +#endif +#endif + +#ifndef ES_UART0_TX_GPIO_FUNC +#define ES_UART0_TX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART0_TX_GPIO_PORT +#define ES_UART0_TX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART0_TX_GPIO_PIN +#define ES_UART0_TX_GPIO_PIN GPIO_PIN_8 +#endif + +#ifndef ES_UART0_TX_PIN +#ifdef ES_PIN_GPIO_D_8 +#define ES_UART0_TX_PIN ES_PIN_GPIO_D_8 +#endif +#endif + +#ifndef ES_UART1_TX_GPIO_FUNC +#define ES_UART1_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_TX_GPIO_PORT +#define ES_UART1_TX_GPIO_PORT GPIOC +#endif +#ifndef ES_UART1_TX_GPIO_PIN +#define ES_UART1_TX_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_UART1_TX_PIN +#ifdef ES_PIN_GPIO_C_0 +#define ES_UART1_TX_PIN ES_PIN_GPIO_C_0 +#endif +#endif + +#ifndef ES_UART1_TX_GPIO_FUNC +#define ES_UART1_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_TX_GPIO_PORT +#define ES_UART1_TX_GPIO_PORT GPIOC +#endif +#ifndef ES_UART1_TX_GPIO_PIN +#define ES_UART1_TX_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_UART1_TX_PIN +#ifdef ES_PIN_GPIO_C_10 +#define ES_UART1_TX_PIN ES_PIN_GPIO_C_10 +#endif +#endif + +#ifndef ES_UART1_TX_GPIO_FUNC +#define ES_UART1_TX_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_UART1_TX_GPIO_PORT +#define ES_UART1_TX_GPIO_PORT GPIOA +#endif +#ifndef ES_UART1_TX_GPIO_PIN +#define ES_UART1_TX_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_UART1_TX_PIN +#ifdef ES_PIN_GPIO_A_13 +#define ES_UART1_TX_PIN ES_PIN_GPIO_A_13 +#endif +#endif + +#ifndef ES_UART1_TX_GPIO_FUNC +#define ES_UART1_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_TX_GPIO_PORT +#define ES_UART1_TX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART1_TX_GPIO_PIN +#define ES_UART1_TX_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_UART1_TX_PIN +#ifdef ES_PIN_GPIO_D_5 +#define ES_UART1_TX_PIN ES_PIN_GPIO_D_5 +#endif +#endif + +#ifndef ES_UART2_TX_GPIO_FUNC +#define ES_UART2_TX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART2_TX_GPIO_PORT +#define ES_UART2_TX_GPIO_PORT GPIOC +#endif +#ifndef ES_UART2_TX_GPIO_PIN +#define ES_UART2_TX_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_UART2_TX_PIN +#ifdef ES_PIN_GPIO_C_12 +#define ES_UART2_TX_PIN ES_PIN_GPIO_C_12 +#endif +#endif + +#ifndef ES_UART2_TX_GPIO_FUNC +#define ES_UART2_TX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART2_TX_GPIO_PORT +#define ES_UART2_TX_GPIO_PORT GPIOB +#endif +#ifndef ES_UART2_TX_GPIO_PIN +#define ES_UART2_TX_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_UART2_TX_PIN +#ifdef ES_PIN_GPIO_B_3 +#define ES_UART2_TX_PIN ES_PIN_GPIO_B_3 +#endif +#endif + +#ifndef ES_UART2_TX_GPIO_FUNC +#define ES_UART2_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART2_TX_GPIO_PORT +#define ES_UART2_TX_GPIO_PORT GPIOE +#endif +#ifndef ES_UART2_TX_GPIO_PIN +#define ES_UART2_TX_GPIO_PIN GPIO_PIN_2 +#endif + +#ifndef ES_UART2_TX_PIN +#ifdef ES_PIN_GPIO_E_2 +#define ES_UART2_TX_PIN ES_PIN_GPIO_E_2 +#endif +#endif + +#ifndef ES_UART3_TX_GPIO_FUNC +#define ES_UART3_TX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART3_TX_GPIO_PORT +#define ES_UART3_TX_GPIO_PORT GPIOC +#endif +#ifndef ES_UART3_TX_GPIO_PIN +#define ES_UART3_TX_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_UART3_TX_PIN +#ifdef ES_PIN_GPIO_C_4 +#define ES_UART3_TX_PIN ES_PIN_GPIO_C_4 +#endif +#endif + +#ifndef ES_UART3_TX_GPIO_FUNC +#define ES_UART3_TX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART3_TX_GPIO_PORT +#define ES_UART3_TX_GPIO_PORT GPIOE +#endif +#ifndef ES_UART3_TX_GPIO_PIN +#define ES_UART3_TX_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_UART3_TX_PIN +#ifdef ES_PIN_GPIO_E_10 +#define ES_UART3_TX_PIN ES_PIN_GPIO_E_10 +#endif +#endif + +#ifndef ES_UART3_TX_GPIO_FUNC +#define ES_UART3_TX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART3_TX_GPIO_PORT +#define ES_UART3_TX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART3_TX_GPIO_PIN +#define ES_UART3_TX_GPIO_PIN GPIO_PIN_14 +#endif + +#ifndef ES_UART3_TX_PIN +#ifdef ES_PIN_GPIO_D_14 +#define ES_UART3_TX_PIN ES_PIN_GPIO_D_14 +#endif +#endif + + +/* UART_RX */ + + +#ifndef ES_UART0_RX_GPIO_FUNC +#define ES_UART0_RX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART0_RX_GPIO_PORT +#define ES_UART0_RX_GPIO_PORT GPIOA +#endif +#ifndef ES_UART0_RX_GPIO_PIN +#define ES_UART0_RX_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_UART0_RX_PIN +#ifdef ES_PIN_GPIO_A_10 +#define ES_UART0_RX_PIN ES_PIN_GPIO_A_10 +#endif +#endif + +#ifndef ES_UART0_RX_GPIO_FUNC +#define ES_UART0_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART0_RX_GPIO_PORT +#define ES_UART0_RX_GPIO_PORT GPIOH +#endif +#ifndef ES_UART0_RX_GPIO_PIN +#define ES_UART0_RX_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_UART0_RX_PIN +#ifdef ES_PIN_GPIO_H_1 +#define ES_UART0_RX_PIN ES_PIN_GPIO_H_1 +#endif +#endif + +#ifndef ES_UART0_RX_GPIO_FUNC +#define ES_UART0_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART0_RX_GPIO_PORT +#define ES_UART0_RX_GPIO_PORT GPIOB +#endif +#ifndef ES_UART0_RX_GPIO_PIN +#define ES_UART0_RX_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_UART0_RX_PIN +#ifdef ES_PIN_GPIO_B_11 +#define ES_UART0_RX_PIN ES_PIN_GPIO_B_11 +#endif +#endif + +#ifndef ES_UART0_RX_GPIO_FUNC +#define ES_UART0_RX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART0_RX_GPIO_PORT +#define ES_UART0_RX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART0_RX_GPIO_PIN +#define ES_UART0_RX_GPIO_PIN GPIO_PIN_9 +#endif + +#ifndef ES_UART0_RX_PIN +#ifdef ES_PIN_GPIO_D_9 +#define ES_UART0_RX_PIN ES_PIN_GPIO_D_9 +#endif +#endif + +#ifndef ES_UART1_RX_GPIO_FUNC +#define ES_UART1_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_RX_GPIO_PORT +#define ES_UART1_RX_GPIO_PORT GPIOC +#endif +#ifndef ES_UART1_RX_GPIO_PIN +#define ES_UART1_RX_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_UART1_RX_PIN +#ifdef ES_PIN_GPIO_C_11 +#define ES_UART1_RX_PIN ES_PIN_GPIO_C_11 +#endif +#endif + +#ifndef ES_UART1_RX_GPIO_FUNC +#define ES_UART1_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_RX_GPIO_PORT +#define ES_UART1_RX_GPIO_PORT GPIOC +#endif +#ifndef ES_UART1_RX_GPIO_PIN +#define ES_UART1_RX_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_UART1_RX_PIN +#ifdef ES_PIN_GPIO_C_1 +#define ES_UART1_RX_PIN ES_PIN_GPIO_C_1 +#endif +#endif + +#ifndef ES_UART1_RX_GPIO_FUNC +#define ES_UART1_RX_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_UART1_RX_GPIO_PORT +#define ES_UART1_RX_GPIO_PORT GPIOA +#endif +#ifndef ES_UART1_RX_GPIO_PIN +#define ES_UART1_RX_GPIO_PIN GPIO_PIN_14 +#endif + +#ifndef ES_UART1_RX_PIN +#ifdef ES_PIN_GPIO_A_14 +#define ES_UART1_RX_PIN ES_PIN_GPIO_A_14 +#endif +#endif + +#ifndef ES_UART1_RX_GPIO_FUNC +#define ES_UART1_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_RX_GPIO_PORT +#define ES_UART1_RX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART1_RX_GPIO_PIN +#define ES_UART1_RX_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_UART1_RX_PIN +#ifdef ES_PIN_GPIO_D_6 +#define ES_UART1_RX_PIN ES_PIN_GPIO_D_6 +#endif +#endif + +#ifndef ES_UART2_RX_GPIO_FUNC +#define ES_UART2_RX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART2_RX_GPIO_PORT +#define ES_UART2_RX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART2_RX_GPIO_PIN +#define ES_UART2_RX_GPIO_PIN GPIO_PIN_2 +#endif + +#ifndef ES_UART2_RX_PIN +#ifdef ES_PIN_GPIO_D_2 +#define ES_UART2_RX_PIN ES_PIN_GPIO_D_2 +#endif +#endif + +#ifndef ES_UART2_RX_GPIO_FUNC +#define ES_UART2_RX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART2_RX_GPIO_PORT +#define ES_UART2_RX_GPIO_PORT GPIOB +#endif +#ifndef ES_UART2_RX_GPIO_PIN +#define ES_UART2_RX_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_UART2_RX_PIN +#ifdef ES_PIN_GPIO_B_4 +#define ES_UART2_RX_PIN ES_PIN_GPIO_B_4 +#endif +#endif + +#ifndef ES_UART2_RX_GPIO_FUNC +#define ES_UART2_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART2_RX_GPIO_PORT +#define ES_UART2_RX_GPIO_PORT GPIOE +#endif +#ifndef ES_UART2_RX_GPIO_PIN +#define ES_UART2_RX_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_UART2_RX_PIN +#ifdef ES_PIN_GPIO_E_3 +#define ES_UART2_RX_PIN ES_PIN_GPIO_E_3 +#endif +#endif + +#ifndef ES_UART3_RX_GPIO_FUNC +#define ES_UART3_RX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART3_RX_GPIO_PORT +#define ES_UART3_RX_GPIO_PORT GPIOC +#endif +#ifndef ES_UART3_RX_GPIO_PIN +#define ES_UART3_RX_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_UART3_RX_PIN +#ifdef ES_PIN_GPIO_C_5 +#define ES_UART3_RX_PIN ES_PIN_GPIO_C_5 +#endif +#endif + +#ifndef ES_UART3_RX_GPIO_FUNC +#define ES_UART3_RX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART3_RX_GPIO_PORT +#define ES_UART3_RX_GPIO_PORT GPIOE +#endif +#ifndef ES_UART3_RX_GPIO_PIN +#define ES_UART3_RX_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_UART3_RX_PIN +#ifdef ES_PIN_GPIO_E_11 +#define ES_UART3_RX_PIN ES_PIN_GPIO_E_11 +#endif +#endif + +#ifndef ES_UART3_RX_GPIO_FUNC +#define ES_UART3_RX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART3_RX_GPIO_PORT +#define ES_UART3_RX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART3_RX_GPIO_PIN +#define ES_UART3_RX_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_UART3_RX_PIN +#ifdef ES_PIN_GPIO_D_13 +#define ES_UART3_RX_PIN ES_PIN_GPIO_D_13 +#endif +#endif + + +/* UART_RTS */ + + +#ifndef ES_UART0_RTS_GPIO_FUNC +#define ES_UART0_RTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART0_RTS_GPIO_PORT +#define ES_UART0_RTS_GPIO_PORT GPIOB +#endif +#ifndef ES_UART0_RTS_GPIO_PIN +#define ES_UART0_RTS_GPIO_PIN GPIO_PIN_14 +#endif + +#ifndef ES_UART0_RTS_PIN +#ifdef ES_PIN_GPIO_B_14 +#define ES_UART0_RTS_PIN ES_PIN_GPIO_B_14 +#endif +#endif + +#ifndef ES_UART0_RTS_GPIO_FUNC +#define ES_UART0_RTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART0_RTS_GPIO_PORT +#define ES_UART0_RTS_GPIO_PORT GPIOA +#endif +#ifndef ES_UART0_RTS_GPIO_PIN +#define ES_UART0_RTS_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_UART0_RTS_PIN +#ifdef ES_PIN_GPIO_A_12 +#define ES_UART0_RTS_PIN ES_PIN_GPIO_A_12 +#endif +#endif + +#ifndef ES_UART0_RTS_GPIO_FUNC +#define ES_UART0_RTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART0_RTS_GPIO_PORT +#define ES_UART0_RTS_GPIO_PORT GPIOD +#endif +#ifndef ES_UART0_RTS_GPIO_PIN +#define ES_UART0_RTS_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_UART0_RTS_PIN +#ifdef ES_PIN_GPIO_D_12 +#define ES_UART0_RTS_PIN ES_PIN_GPIO_D_12 +#endif +#endif + +#ifndef ES_UART1_RTS_GPIO_FUNC +#define ES_UART1_RTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_RTS_GPIO_PORT +#define ES_UART1_RTS_GPIO_PORT GPIOC +#endif +#ifndef ES_UART1_RTS_GPIO_PIN +#define ES_UART1_RTS_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_UART1_RTS_PIN +#ifdef ES_PIN_GPIO_C_12 +#define ES_UART1_RTS_PIN ES_PIN_GPIO_C_12 +#endif +#endif + +#ifndef ES_UART1_RTS_GPIO_FUNC +#define ES_UART1_RTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_RTS_GPIO_PORT +#define ES_UART1_RTS_GPIO_PORT GPIOC +#endif +#ifndef ES_UART1_RTS_GPIO_PIN +#define ES_UART1_RTS_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_UART1_RTS_PIN +#ifdef ES_PIN_GPIO_C_3 +#define ES_UART1_RTS_PIN ES_PIN_GPIO_C_3 +#endif +#endif + +#ifndef ES_UART2_RTS_GPIO_FUNC +#define ES_UART2_RTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART2_RTS_GPIO_PORT +#define ES_UART2_RTS_GPIO_PORT GPIOC +#endif +#ifndef ES_UART2_RTS_GPIO_PIN +#define ES_UART2_RTS_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_UART2_RTS_PIN +#ifdef ES_PIN_GPIO_C_10 +#define ES_UART2_RTS_PIN ES_PIN_GPIO_C_10 +#endif +#endif + +#ifndef ES_UART2_RTS_GPIO_FUNC +#define ES_UART2_RTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART2_RTS_GPIO_PORT +#define ES_UART2_RTS_GPIO_PORT GPIOE +#endif +#ifndef ES_UART2_RTS_GPIO_PIN +#define ES_UART2_RTS_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_UART2_RTS_PIN +#ifdef ES_PIN_GPIO_E_5 +#define ES_UART2_RTS_PIN ES_PIN_GPIO_E_5 +#endif +#endif + +#ifndef ES_UART3_RTS_GPIO_FUNC +#define ES_UART3_RTS_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART3_RTS_GPIO_PORT +#define ES_UART3_RTS_GPIO_PORT GPIOB +#endif +#ifndef ES_UART3_RTS_GPIO_PIN +#define ES_UART3_RTS_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_UART3_RTS_PIN +#ifdef ES_PIN_GPIO_B_1 +#define ES_UART3_RTS_PIN ES_PIN_GPIO_B_1 +#endif +#endif + +#ifndef ES_UART3_RTS_GPIO_FUNC +#define ES_UART3_RTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART3_RTS_GPIO_PORT +#define ES_UART3_RTS_GPIO_PORT GPIOE +#endif +#ifndef ES_UART3_RTS_GPIO_PIN +#define ES_UART3_RTS_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_UART3_RTS_PIN +#ifdef ES_PIN_GPIO_E_13 +#define ES_UART3_RTS_PIN ES_PIN_GPIO_E_13 +#endif +#endif + + +/* UART_CTS */ + + +#ifndef ES_UART0_CTS_GPIO_FUNC +#define ES_UART0_CTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART0_CTS_GPIO_PORT +#define ES_UART0_CTS_GPIO_PORT GPIOB +#endif +#ifndef ES_UART0_CTS_GPIO_PIN +#define ES_UART0_CTS_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_UART0_CTS_PIN +#ifdef ES_PIN_GPIO_B_13 +#define ES_UART0_CTS_PIN ES_PIN_GPIO_B_13 +#endif +#endif + +#ifndef ES_UART0_CTS_GPIO_FUNC +#define ES_UART0_CTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART0_CTS_GPIO_PORT +#define ES_UART0_CTS_GPIO_PORT GPIOA +#endif +#ifndef ES_UART0_CTS_GPIO_PIN +#define ES_UART0_CTS_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_UART0_CTS_PIN +#ifdef ES_PIN_GPIO_A_11 +#define ES_UART0_CTS_PIN ES_PIN_GPIO_A_11 +#endif +#endif + +#ifndef ES_UART0_CTS_GPIO_FUNC +#define ES_UART0_CTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART0_CTS_GPIO_PORT +#define ES_UART0_CTS_GPIO_PORT GPIOD +#endif +#ifndef ES_UART0_CTS_GPIO_PIN +#define ES_UART0_CTS_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_UART0_CTS_PIN +#ifdef ES_PIN_GPIO_D_11 +#define ES_UART0_CTS_PIN ES_PIN_GPIO_D_11 +#endif +#endif + +#ifndef ES_UART1_CTS_GPIO_FUNC +#define ES_UART1_CTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_CTS_GPIO_PORT +#define ES_UART1_CTS_GPIO_PORT GPIOC +#endif +#ifndef ES_UART1_CTS_GPIO_PIN +#define ES_UART1_CTS_GPIO_PIN GPIO_PIN_2 +#endif + +#ifndef ES_UART1_CTS_PIN +#ifdef ES_PIN_GPIO_C_2 +#define ES_UART1_CTS_PIN ES_PIN_GPIO_C_2 +#endif +#endif + +#ifndef ES_UART1_CTS_GPIO_FUNC +#define ES_UART1_CTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_CTS_GPIO_PORT +#define ES_UART1_CTS_GPIO_PORT GPIOD +#endif +#ifndef ES_UART1_CTS_GPIO_PIN +#define ES_UART1_CTS_GPIO_PIN GPIO_PIN_2 +#endif + +#ifndef ES_UART1_CTS_PIN +#ifdef ES_PIN_GPIO_D_2 +#define ES_UART1_CTS_PIN ES_PIN_GPIO_D_2 +#endif +#endif + +#ifndef ES_UART2_CTS_GPIO_FUNC +#define ES_UART2_CTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART2_CTS_GPIO_PORT +#define ES_UART2_CTS_GPIO_PORT GPIOC +#endif +#ifndef ES_UART2_CTS_GPIO_PIN +#define ES_UART2_CTS_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_UART2_CTS_PIN +#ifdef ES_PIN_GPIO_C_11 +#define ES_UART2_CTS_PIN ES_PIN_GPIO_C_11 +#endif +#endif + +#ifndef ES_UART2_CTS_GPIO_FUNC +#define ES_UART2_CTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART2_CTS_GPIO_PORT +#define ES_UART2_CTS_GPIO_PORT GPIOE +#endif +#ifndef ES_UART2_CTS_GPIO_PIN +#define ES_UART2_CTS_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_UART2_CTS_PIN +#ifdef ES_PIN_GPIO_E_4 +#define ES_UART2_CTS_PIN ES_PIN_GPIO_E_4 +#endif +#endif + +#ifndef ES_UART3_CTS_GPIO_FUNC +#define ES_UART3_CTS_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART3_CTS_GPIO_PORT +#define ES_UART3_CTS_GPIO_PORT GPIOB +#endif +#ifndef ES_UART3_CTS_GPIO_PIN +#define ES_UART3_CTS_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_UART3_CTS_PIN +#ifdef ES_PIN_GPIO_B_0 +#define ES_UART3_CTS_PIN ES_PIN_GPIO_B_0 +#endif +#endif + +#ifndef ES_UART3_CTS_GPIO_FUNC +#define ES_UART3_CTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART3_CTS_GPIO_PORT +#define ES_UART3_CTS_GPIO_PORT GPIOE +#endif +#ifndef ES_UART3_CTS_GPIO_PIN +#define ES_UART3_CTS_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_UART3_CTS_PIN +#ifdef ES_PIN_GPIO_E_12 +#define ES_UART3_CTS_PIN ES_PIN_GPIO_E_12 +#endif +#endif + + +/* UART_CK */ + + + +/* USART_TX */ + + +#ifndef ES_USART0_TX_GPIO_FUNC +#define ES_USART0_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_USART0_TX_GPIO_PORT +#define ES_USART0_TX_GPIO_PORT GPIOB +#endif +#ifndef ES_USART0_TX_GPIO_PIN +#define ES_USART0_TX_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_USART0_TX_PIN +#ifdef ES_PIN_GPIO_B_6 +#define ES_USART0_TX_PIN ES_PIN_GPIO_B_6 +#endif +#endif + +#ifndef ES_USART0_TX_GPIO_FUNC +#define ES_USART0_TX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_USART0_TX_GPIO_PORT +#define ES_USART0_TX_GPIO_PORT GPIOE +#endif +#ifndef ES_USART0_TX_GPIO_PIN +#define ES_USART0_TX_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_USART0_TX_PIN +#ifdef ES_PIN_GPIO_E_10 +#define ES_USART0_TX_PIN ES_PIN_GPIO_E_10 +#endif +#endif + +#ifndef ES_USART1_TX_GPIO_FUNC +#define ES_USART1_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_USART1_TX_GPIO_PORT +#define ES_USART1_TX_GPIO_PORT GPIOA +#endif +#ifndef ES_USART1_TX_GPIO_PIN +#define ES_USART1_TX_GPIO_PIN GPIO_PIN_2 +#endif + +#ifndef ES_USART1_TX_PIN +#ifdef ES_PIN_GPIO_A_2 +#define ES_USART1_TX_PIN ES_PIN_GPIO_A_2 +#endif +#endif + +#ifndef ES_USART1_TX_GPIO_FUNC +#define ES_USART1_TX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_USART1_TX_GPIO_PORT +#define ES_USART1_TX_GPIO_PORT GPIOB +#endif +#ifndef ES_USART1_TX_GPIO_PIN +#define ES_USART1_TX_GPIO_PIN GPIO_PIN_9 +#endif + +#ifndef ES_USART1_TX_PIN +#ifdef ES_PIN_GPIO_B_9 +#define ES_USART1_TX_PIN ES_PIN_GPIO_B_9 +#endif +#endif + +#ifndef ES_USART1_TX_GPIO_FUNC +#define ES_USART1_TX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_USART1_TX_GPIO_PORT +#define ES_USART1_TX_GPIO_PORT GPIOD +#endif +#ifndef ES_USART1_TX_GPIO_PIN +#define ES_USART1_TX_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_USART1_TX_PIN +#ifdef ES_PIN_GPIO_D_5 +#define ES_USART1_TX_PIN ES_PIN_GPIO_D_5 +#endif +#endif + + +/* USART_RX */ + + +#ifndef ES_USART0_RX_GPIO_FUNC +#define ES_USART0_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_USART0_RX_GPIO_PORT +#define ES_USART0_RX_GPIO_PORT GPIOB +#endif +#ifndef ES_USART0_RX_GPIO_PIN +#define ES_USART0_RX_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_USART0_RX_PIN +#ifdef ES_PIN_GPIO_B_7 +#define ES_USART0_RX_PIN ES_PIN_GPIO_B_7 +#endif +#endif + +#ifndef ES_USART0_RX_GPIO_FUNC +#define ES_USART0_RX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_USART0_RX_GPIO_PORT +#define ES_USART0_RX_GPIO_PORT GPIOE +#endif +#ifndef ES_USART0_RX_GPIO_PIN +#define ES_USART0_RX_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_USART0_RX_PIN +#ifdef ES_PIN_GPIO_E_11 +#define ES_USART0_RX_PIN ES_PIN_GPIO_E_11 +#endif +#endif + +#ifndef ES_USART1_RX_GPIO_FUNC +#define ES_USART1_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_USART1_RX_GPIO_PORT +#define ES_USART1_RX_GPIO_PORT GPIOA +#endif +#ifndef ES_USART1_RX_GPIO_PIN +#define ES_USART1_RX_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_USART1_RX_PIN +#ifdef ES_PIN_GPIO_A_3 +#define ES_USART1_RX_PIN ES_PIN_GPIO_A_3 +#endif +#endif + +#ifndef ES_USART1_RX_GPIO_FUNC +#define ES_USART1_RX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_USART1_RX_GPIO_PORT +#define ES_USART1_RX_GPIO_PORT GPIOD +#endif +#ifndef ES_USART1_RX_GPIO_PIN +#define ES_USART1_RX_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_USART1_RX_PIN +#ifdef ES_PIN_GPIO_D_6 +#define ES_USART1_RX_PIN ES_PIN_GPIO_D_6 +#endif +#endif + +#ifndef ES_USART1_RX_GPIO_FUNC +#define ES_USART1_RX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_USART1_RX_GPIO_PORT +#define ES_USART1_RX_GPIO_PORT GPIOB +#endif +#ifndef ES_USART1_RX_GPIO_PIN +#define ES_USART1_RX_GPIO_PIN GPIO_PIN_8 +#endif + +#ifndef ES_USART1_RX_PIN +#ifdef ES_PIN_GPIO_B_8 +#define ES_USART1_RX_PIN ES_PIN_GPIO_B_8 +#endif +#endif + + +/* USART_RTS */ + + +#ifndef ES_USART0_RTS_GPIO_FUNC +#define ES_USART0_RTS_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_USART0_RTS_GPIO_PORT +#define ES_USART0_RTS_GPIO_PORT GPIOE +#endif +#ifndef ES_USART0_RTS_GPIO_PIN +#define ES_USART0_RTS_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_USART0_RTS_PIN +#ifdef ES_PIN_GPIO_E_13 +#define ES_USART0_RTS_PIN ES_PIN_GPIO_E_13 +#endif +#endif + +#ifndef ES_USART0_RTS_GPIO_FUNC +#define ES_USART0_RTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_USART0_RTS_GPIO_PORT +#define ES_USART0_RTS_GPIO_PORT GPIOE +#endif +#ifndef ES_USART0_RTS_GPIO_PIN +#define ES_USART0_RTS_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_USART0_RTS_PIN +#ifdef ES_PIN_GPIO_E_1 +#define ES_USART0_RTS_PIN ES_PIN_GPIO_E_1 +#endif +#endif + +#ifndef ES_USART1_RTS_GPIO_FUNC +#define ES_USART1_RTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_USART1_RTS_GPIO_PORT +#define ES_USART1_RTS_GPIO_PORT GPIOA +#endif +#ifndef ES_USART1_RTS_GPIO_PIN +#define ES_USART1_RTS_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_USART1_RTS_PIN +#ifdef ES_PIN_GPIO_A_1 +#define ES_USART1_RTS_PIN ES_PIN_GPIO_A_1 +#endif +#endif + +#ifndef ES_USART1_RTS_GPIO_FUNC +#define ES_USART1_RTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_USART1_RTS_GPIO_PORT +#define ES_USART1_RTS_GPIO_PORT GPIOD +#endif +#ifndef ES_USART1_RTS_GPIO_PIN +#define ES_USART1_RTS_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_USART1_RTS_PIN +#ifdef ES_PIN_GPIO_D_4 +#define ES_USART1_RTS_PIN ES_PIN_GPIO_D_4 +#endif +#endif + + +/* USART_CTS */ + + +#ifndef ES_USART0_CTS_GPIO_FUNC +#define ES_USART0_CTS_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_USART0_CTS_GPIO_PORT +#define ES_USART0_CTS_GPIO_PORT GPIOE +#endif +#ifndef ES_USART0_CTS_GPIO_PIN +#define ES_USART0_CTS_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_USART0_CTS_PIN +#ifdef ES_PIN_GPIO_E_12 +#define ES_USART0_CTS_PIN ES_PIN_GPIO_E_12 +#endif +#endif + +#ifndef ES_USART0_CTS_GPIO_FUNC +#define ES_USART0_CTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_USART0_CTS_GPIO_PORT +#define ES_USART0_CTS_GPIO_PORT GPIOE +#endif +#ifndef ES_USART0_CTS_GPIO_PIN +#define ES_USART0_CTS_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_USART0_CTS_PIN +#ifdef ES_PIN_GPIO_E_0 +#define ES_USART0_CTS_PIN ES_PIN_GPIO_E_0 +#endif +#endif + +#ifndef ES_USART1_CTS_GPIO_FUNC +#define ES_USART1_CTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_USART1_CTS_GPIO_PORT +#define ES_USART1_CTS_GPIO_PORT GPIOF +#endif +#ifndef ES_USART1_CTS_GPIO_PIN +#define ES_USART1_CTS_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_USART1_CTS_PIN +#ifdef ES_PIN_GPIO_F_7 +#define ES_USART1_CTS_PIN ES_PIN_GPIO_F_7 +#endif +#endif + +#ifndef ES_USART1_CTS_GPIO_FUNC +#define ES_USART1_CTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_USART1_CTS_GPIO_PORT +#define ES_USART1_CTS_GPIO_PORT GPIOD +#endif +#ifndef ES_USART1_CTS_GPIO_PIN +#define ES_USART1_CTS_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_USART1_CTS_PIN +#ifdef ES_PIN_GPIO_D_3 +#define ES_USART1_CTS_PIN ES_PIN_GPIO_D_3 +#endif +#endif + + +/* USART_CK */ + + +#ifndef ES_USART0_CK_GPIO_FUNC +#define ES_USART0_CK_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_USART0_CK_GPIO_PORT +#define ES_USART0_CK_GPIO_PORT GPIOA +#endif +#ifndef ES_USART0_CK_GPIO_PIN +#define ES_USART0_CK_GPIO_PIN GPIO_PIN_8 +#endif + +#ifndef ES_USART0_CK_PIN +#ifdef ES_PIN_GPIO_A_8 +#define ES_USART0_CK_PIN ES_PIN_GPIO_A_8 +#endif +#endif + +#ifndef ES_USART0_CK_GPIO_FUNC +#define ES_USART0_CK_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_USART0_CK_GPIO_PORT +#define ES_USART0_CK_GPIO_PORT GPIOE +#endif +#ifndef ES_USART0_CK_GPIO_PIN +#define ES_USART0_CK_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_USART0_CK_PIN +#ifdef ES_PIN_GPIO_E_6 +#define ES_USART0_CK_PIN ES_PIN_GPIO_E_6 +#endif +#endif + +#ifndef ES_USART0_CK_GPIO_FUNC +#define ES_USART0_CK_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_USART0_CK_GPIO_PORT +#define ES_USART0_CK_GPIO_PORT GPIOE +#endif +#ifndef ES_USART0_CK_GPIO_PIN +#define ES_USART0_CK_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_USART0_CK_PIN +#ifdef ES_PIN_GPIO_E_7 +#define ES_USART0_CK_PIN ES_PIN_GPIO_E_7 +#endif +#endif + +#ifndef ES_USART1_CK_GPIO_FUNC +#define ES_USART1_CK_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_USART1_CK_GPIO_PORT +#define ES_USART1_CK_GPIO_PORT GPIOA +#endif +#ifndef ES_USART1_CK_GPIO_PIN +#define ES_USART1_CK_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_USART1_CK_PIN +#ifdef ES_PIN_GPIO_A_4 +#define ES_USART1_CK_PIN ES_PIN_GPIO_A_4 +#endif +#endif + +#ifndef ES_USART1_CK_GPIO_FUNC +#define ES_USART1_CK_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_USART1_CK_GPIO_PORT +#define ES_USART1_CK_GPIO_PORT GPIOD +#endif +#ifndef ES_USART1_CK_GPIO_PIN +#define ES_USART1_CK_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_USART1_CK_PIN +#ifdef ES_PIN_GPIO_D_7 +#define ES_USART1_CK_PIN ES_PIN_GPIO_D_7 +#endif +#endif + +#ifndef ES_USART1_CK_GPIO_FUNC +#define ES_USART1_CK_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_USART1_CK_GPIO_PORT +#define ES_USART1_CK_GPIO_PORT GPIOE +#endif +#ifndef ES_USART1_CK_GPIO_PIN +#define ES_USART1_CK_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_USART1_CK_PIN +#ifdef ES_PIN_GPIO_E_0 +#define ES_USART1_CK_PIN ES_PIN_GPIO_E_0 +#endif +#endif + + +/* I2C_SCL */ + + +#ifndef ES_I2C0_SCL_GPIO_FUNC +#define ES_I2C0_SCL_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C0_SCL_GPIO_PORT +#define ES_I2C0_SCL_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C0_SCL_GPIO_PIN +#define ES_I2C0_SCL_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_I2C0_SCL_PIN +#ifdef ES_PIN_GPIO_B_6 +#define ES_I2C0_SCL_PIN ES_PIN_GPIO_B_6 +#endif +#endif + +#ifndef ES_I2C0_SCL_GPIO_FUNC +#define ES_I2C0_SCL_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C0_SCL_GPIO_PORT +#define ES_I2C0_SCL_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C0_SCL_GPIO_PIN +#define ES_I2C0_SCL_GPIO_PIN GPIO_PIN_8 +#endif + +#ifndef ES_I2C0_SCL_PIN +#ifdef ES_PIN_GPIO_B_8 +#define ES_I2C0_SCL_PIN ES_PIN_GPIO_B_8 +#endif +#endif + +#ifndef ES_I2C1_SCL_GPIO_FUNC +#define ES_I2C1_SCL_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C1_SCL_GPIO_PORT +#define ES_I2C1_SCL_GPIO_PORT GPIOA +#endif +#ifndef ES_I2C1_SCL_GPIO_PIN +#define ES_I2C1_SCL_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_I2C1_SCL_PIN +#ifdef ES_PIN_GPIO_A_5 +#define ES_I2C1_SCL_PIN ES_PIN_GPIO_A_5 +#endif +#endif + +#ifndef ES_I2C1_SCL_GPIO_FUNC +#define ES_I2C1_SCL_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C1_SCL_GPIO_PORT +#define ES_I2C1_SCL_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C1_SCL_GPIO_PIN +#define ES_I2C1_SCL_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_I2C1_SCL_PIN +#ifdef ES_PIN_GPIO_B_10 +#define ES_I2C1_SCL_PIN ES_PIN_GPIO_B_10 +#endif +#endif + +#ifndef ES_I2C1_SCL_GPIO_FUNC +#define ES_I2C1_SCL_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C1_SCL_GPIO_PORT +#define ES_I2C1_SCL_GPIO_PORT GPIOH +#endif +#ifndef ES_I2C1_SCL_GPIO_PIN +#define ES_I2C1_SCL_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_I2C1_SCL_PIN +#ifdef ES_PIN_GPIO_H_0 +#define ES_I2C1_SCL_PIN ES_PIN_GPIO_H_0 +#endif +#endif + + +/* I2C_SDA */ + + +#ifndef ES_I2C0_SDA_GPIO_FUNC +#define ES_I2C0_SDA_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C0_SDA_GPIO_PORT +#define ES_I2C0_SDA_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C0_SDA_GPIO_PIN +#define ES_I2C0_SDA_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_I2C0_SDA_PIN +#ifdef ES_PIN_GPIO_B_7 +#define ES_I2C0_SDA_PIN ES_PIN_GPIO_B_7 +#endif +#endif + +#ifndef ES_I2C0_SDA_GPIO_FUNC +#define ES_I2C0_SDA_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C0_SDA_GPIO_PORT +#define ES_I2C0_SDA_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C0_SDA_GPIO_PIN +#define ES_I2C0_SDA_GPIO_PIN GPIO_PIN_9 +#endif + +#ifndef ES_I2C0_SDA_PIN +#ifdef ES_PIN_GPIO_B_9 +#define ES_I2C0_SDA_PIN ES_PIN_GPIO_B_9 +#endif +#endif + +#ifndef ES_I2C1_SDA_GPIO_FUNC +#define ES_I2C1_SDA_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C1_SDA_GPIO_PORT +#define ES_I2C1_SDA_GPIO_PORT GPIOA +#endif +#ifndef ES_I2C1_SDA_GPIO_PIN +#define ES_I2C1_SDA_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_I2C1_SDA_PIN +#ifdef ES_PIN_GPIO_A_6 +#define ES_I2C1_SDA_PIN ES_PIN_GPIO_A_6 +#endif +#endif + +#ifndef ES_I2C1_SDA_GPIO_FUNC +#define ES_I2C1_SDA_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C1_SDA_GPIO_PORT +#define ES_I2C1_SDA_GPIO_PORT GPIOH +#endif +#ifndef ES_I2C1_SDA_GPIO_PIN +#define ES_I2C1_SDA_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_I2C1_SDA_PIN +#ifdef ES_PIN_GPIO_H_1 +#define ES_I2C1_SDA_PIN ES_PIN_GPIO_H_1 +#endif +#endif + +#ifndef ES_I2C1_SDA_GPIO_FUNC +#define ES_I2C1_SDA_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C1_SDA_GPIO_PORT +#define ES_I2C1_SDA_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C1_SDA_GPIO_PIN +#define ES_I2C1_SDA_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_I2C1_SDA_PIN +#ifdef ES_PIN_GPIO_B_11 +#define ES_I2C1_SDA_PIN ES_PIN_GPIO_B_11 +#endif +#endif + + +/* SPI_MISO */ + + +#ifndef ES_SPI0_MISO_GPIO_FUNC +#define ES_SPI0_MISO_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_MISO_GPIO_PORT +#define ES_SPI0_MISO_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI0_MISO_GPIO_PIN +#define ES_SPI0_MISO_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_SPI0_MISO_PIN +#ifdef ES_PIN_GPIO_B_4 +#define ES_SPI0_MISO_PIN ES_PIN_GPIO_B_4 +#endif +#endif + +#ifndef ES_SPI0_MISO_GPIO_FUNC +#define ES_SPI0_MISO_GPIO_FUNC GPIO_FUNC_6 +#endif +#ifndef ES_SPI0_MISO_GPIO_PORT +#define ES_SPI0_MISO_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI0_MISO_GPIO_PIN +#define ES_SPI0_MISO_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_SPI0_MISO_PIN +#ifdef ES_PIN_GPIO_A_6 +#define ES_SPI0_MISO_PIN ES_PIN_GPIO_A_6 +#endif +#endif + +#ifndef ES_SPI0_MISO_GPIO_FUNC +#define ES_SPI0_MISO_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_MISO_GPIO_PORT +#define ES_SPI0_MISO_GPIO_PORT GPIOD +#endif +#ifndef ES_SPI0_MISO_GPIO_PIN +#define ES_SPI0_MISO_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_SPI0_MISO_PIN +#ifdef ES_PIN_GPIO_D_4 +#define ES_SPI0_MISO_PIN ES_PIN_GPIO_D_4 +#endif +#endif + +#ifndef ES_SPI1_MISO_GPIO_FUNC +#define ES_SPI1_MISO_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_MISO_GPIO_PORT +#define ES_SPI1_MISO_GPIO_PORT GPIOC +#endif +#ifndef ES_SPI1_MISO_GPIO_PIN +#define ES_SPI1_MISO_GPIO_PIN GPIO_PIN_2 +#endif + +#ifndef ES_SPI1_MISO_PIN +#ifdef ES_PIN_GPIO_C_2 +#define ES_SPI1_MISO_PIN ES_PIN_GPIO_C_2 +#endif +#endif + +#ifndef ES_SPI1_MISO_GPIO_FUNC +#define ES_SPI1_MISO_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_MISO_GPIO_PORT +#define ES_SPI1_MISO_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI1_MISO_GPIO_PIN +#define ES_SPI1_MISO_GPIO_PIN GPIO_PIN_14 +#endif + +#ifndef ES_SPI1_MISO_PIN +#ifdef ES_PIN_GPIO_B_14 +#define ES_SPI1_MISO_PIN ES_PIN_GPIO_B_14 +#endif +#endif + + +/* SPI_MOSI */ + + +#ifndef ES_SPI0_MOSI_GPIO_FUNC +#define ES_SPI0_MOSI_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_MOSI_GPIO_PORT +#define ES_SPI0_MOSI_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI0_MOSI_GPIO_PIN +#define ES_SPI0_MOSI_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_SPI0_MOSI_PIN +#ifdef ES_PIN_GPIO_B_5 +#define ES_SPI0_MOSI_PIN ES_PIN_GPIO_B_5 +#endif +#endif + +#ifndef ES_SPI0_MOSI_GPIO_FUNC +#define ES_SPI0_MOSI_GPIO_FUNC GPIO_FUNC_6 +#endif +#ifndef ES_SPI0_MOSI_GPIO_PORT +#define ES_SPI0_MOSI_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI0_MOSI_GPIO_PIN +#define ES_SPI0_MOSI_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_SPI0_MOSI_PIN +#ifdef ES_PIN_GPIO_A_7 +#define ES_SPI0_MOSI_PIN ES_PIN_GPIO_A_7 +#endif +#endif + + +#ifndef ES_SPI0_MOSI_GPIO_FUNC +#define ES_SPI0_MOSI_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_MOSI_GPIO_PORT +#define ES_SPI0_MOSI_GPIO_PORT GPIOD +#endif +#ifndef ES_SPI0_MOSI_GPIO_PIN +#define ES_SPI0_MOSI_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_SPI0_MOSI_PIN +#ifdef ES_PIN_GPIO_D_7 +#define ES_SPI0_MOSI_PIN ES_PIN_GPIO_D_7 +#endif +#endif + +#ifndef ES_SPI1_MOSI_GPIO_FUNC +#define ES_SPI1_MOSI_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_MOSI_GPIO_PORT +#define ES_SPI1_MOSI_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI1_MOSI_GPIO_PIN +#define ES_SPI1_MOSI_GPIO_PIN GPIO_PIN_15 +#endif + +#ifndef ES_SPI1_MOSI_PIN +#ifdef ES_PIN_GPIO_B_15 +#define ES_SPI1_MOSI_PIN ES_PIN_GPIO_B_15 +#endif +#endif + +#ifndef ES_SPI1_MOSI_GPIO_FUNC +#define ES_SPI1_MOSI_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_MOSI_GPIO_PORT +#define ES_SPI1_MOSI_GPIO_PORT GPIOC +#endif +#ifndef ES_SPI1_MOSI_GPIO_PIN +#define ES_SPI1_MOSI_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_SPI1_MOSI_PIN +#ifdef ES_PIN_GPIO_C_3 +#define ES_SPI1_MOSI_PIN ES_PIN_GPIO_C_3 +#endif +#endif + + +/* SPI_SCK */ + + +#ifndef ES_SPI0_SCK_GPIO_FUNC +#define ES_SPI0_SCK_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_SCK_GPIO_PORT +#define ES_SPI0_SCK_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI0_SCK_GPIO_PIN +#define ES_SPI0_SCK_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_SPI0_SCK_PIN +#ifdef ES_PIN_GPIO_B_3 +#define ES_SPI0_SCK_PIN ES_PIN_GPIO_B_3 +#endif +#endif + +#ifndef ES_SPI0_SCK_GPIO_FUNC +#define ES_SPI0_SCK_GPIO_FUNC GPIO_FUNC_6 +#endif +#ifndef ES_SPI0_SCK_GPIO_PORT +#define ES_SPI0_SCK_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI0_SCK_GPIO_PIN +#define ES_SPI0_SCK_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_SPI0_SCK_PIN +#ifdef ES_PIN_GPIO_A_5 +#define ES_SPI0_SCK_PIN ES_PIN_GPIO_A_5 +#endif +#endif + +#ifndef ES_SPI0_SCK_GPIO_FUNC +#define ES_SPI0_SCK_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_SCK_GPIO_PORT +#define ES_SPI0_SCK_GPIO_PORT GPIOD +#endif +#ifndef ES_SPI0_SCK_GPIO_PIN +#define ES_SPI0_SCK_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_SPI0_SCK_PIN +#ifdef ES_PIN_GPIO_D_3 +#define ES_SPI0_SCK_PIN ES_PIN_GPIO_D_3 +#endif +#endif + +#ifndef ES_SPI1_SCK_GPIO_FUNC +#define ES_SPI1_SCK_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_SCK_GPIO_PORT +#define ES_SPI1_SCK_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI1_SCK_GPIO_PIN +#define ES_SPI1_SCK_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_SPI1_SCK_PIN +#ifdef ES_PIN_GPIO_B_13 +#define ES_SPI1_SCK_PIN ES_PIN_GPIO_B_13 +#endif +#endif + +#ifndef ES_SPI1_SCK_GPIO_FUNC +#define ES_SPI1_SCK_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_SCK_GPIO_PORT +#define ES_SPI1_SCK_GPIO_PORT GPIOC +#endif +#ifndef ES_SPI1_SCK_GPIO_PIN +#define ES_SPI1_SCK_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_SPI1_SCK_PIN +#ifdef ES_PIN_GPIO_C_1 +#define ES_SPI1_SCK_PIN ES_PIN_GPIO_C_1 +#endif +#endif + + +/* SPI_NSS */ + + +#ifndef ES_SPI0_NSS_GPIO_FUNC +#define ES_SPI0_NSS_GPIO_FUNC GPIO_FUNC_6 +#endif +#ifndef ES_SPI0_NSS_GPIO_PORT +#define ES_SPI0_NSS_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI0_NSS_GPIO_PIN +#define ES_SPI0_NSS_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_SPI0_NSS_PIN +#ifdef ES_PIN_GPIO_A_4 +#define ES_SPI0_NSS_PIN ES_PIN_GPIO_A_4 +#endif +#endif + +#ifndef ES_SPI0_NSS_GPIO_FUNC +#define ES_SPI0_NSS_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_NSS_GPIO_PORT +#define ES_SPI0_NSS_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI0_NSS_GPIO_PIN +#define ES_SPI0_NSS_GPIO_PIN GPIO_PIN_15 +#endif + +#ifndef ES_SPI0_NSS_PIN +#ifdef ES_PIN_GPIO_A_15 +#define ES_SPI0_NSS_PIN ES_PIN_GPIO_A_15 +#endif +#endif + +#ifndef ES_SPI1_NSS_GPIO_FUNC +#define ES_SPI1_NSS_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_NSS_GPIO_PORT +#define ES_SPI1_NSS_GPIO_PORT GPIOC +#endif +#ifndef ES_SPI1_NSS_GPIO_PIN +#define ES_SPI1_NSS_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_SPI1_NSS_PIN +#ifdef ES_PIN_GPIO_C_0 +#define ES_SPI1_NSS_PIN ES_PIN_GPIO_C_0 +#endif +#endif + +#ifndef ES_SPI1_NSS_GPIO_FUNC +#define ES_SPI1_NSS_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_NSS_GPIO_PORT +#define ES_SPI1_NSS_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI1_NSS_GPIO_PIN +#define ES_SPI1_NSS_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_SPI1_NSS_PIN +#ifdef ES_PIN_GPIO_B_12 +#define ES_SPI1_NSS_PIN ES_PIN_GPIO_B_12 +#endif +#endif + + +/* CAN_TX */ + + +#ifndef ES_CAN0_TX_GPIO_FUNC +#define ES_CAN0_TX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_CAN0_TX_GPIO_PORT +#define ES_CAN0_TX_GPIO_PORT GPIOA +#endif +#ifndef ES_CAN0_TX_GPIO_PIN +#define ES_CAN0_TX_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_CAN0_TX_PIN +#ifdef ES_PIN_GPIO_A_12 +#define ES_CAN0_TX_PIN ES_PIN_GPIO_A_12 +#endif +#endif + +#ifndef ES_CAN0_TX_GPIO_FUNC +#define ES_CAN0_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_CAN0_TX_GPIO_PORT +#define ES_CAN0_TX_GPIO_PORT GPIOB +#endif +#ifndef ES_CAN0_TX_GPIO_PIN +#define ES_CAN0_TX_GPIO_PIN GPIO_PIN_9 +#endif + +#ifndef ES_CAN0_TX_PIN +#ifdef ES_PIN_GPIO_B_9 +#define ES_CAN0_TX_PIN ES_PIN_GPIO_B_9 +#endif +#endif + + +/* CAN_RX */ + + +#ifndef ES_CAN0_RX_GPIO_FUNC +#define ES_CAN0_RX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_CAN0_RX_GPIO_PORT +#define ES_CAN0_RX_GPIO_PORT GPIOA +#endif +#ifndef ES_CAN0_RX_GPIO_PIN +#define ES_CAN0_RX_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_CAN0_RX_PIN +#ifdef ES_PIN_GPIO_A_11 +#define ES_CAN0_RX_PIN ES_PIN_GPIO_A_11 +#endif +#endif + +#ifndef ES_CAN0_RX_GPIO_FUNC +#define ES_CAN0_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_CAN0_RX_GPIO_PORT +#define ES_CAN0_RX_GPIO_PORT GPIOB +#endif +#ifndef ES_CAN0_RX_GPIO_PIN +#define ES_CAN0_RX_GPIO_PIN GPIO_PIN_8 +#endif + +#ifndef ES_CAN0_RX_PIN +#ifdef ES_PIN_GPIO_B_8 +#define ES_CAN0_RX_PIN ES_PIN_GPIO_B_8 +#endif +#endif + + +/* AD16C4T_CH1 */ + + +#ifndef ES_AD16C4T0_CH1_GPIO_FUNC +#define ES_AD16C4T0_CH1_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH1_GPIO_PORT +#define ES_AD16C4T0_CH1_GPIO_PORT GPIOA +#endif +#ifndef ES_AD16C4T0_CH1_GPIO_PIN +#define ES_AD16C4T0_CH1_GPIO_PIN GPIO_PIN_8 +#endif + +#ifndef ES_AD16C4T0_CH1_PIN +#ifdef ES_PIN_GPIO_A_8 +#define ES_AD16C4T0_CH1_PIN ES_PIN_GPIO_A_8 +#endif +#endif + +#ifndef ES_AD16C4T0_CH1_GPIO_FUNC +#define ES_AD16C4T0_CH1_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH1_GPIO_PORT +#define ES_AD16C4T0_CH1_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_CH1_GPIO_PIN +#define ES_AD16C4T0_CH1_GPIO_PIN GPIO_PIN_9 +#endif + +#ifndef ES_AD16C4T0_CH1_PIN +#ifdef ES_PIN_GPIO_E_9 +#define ES_AD16C4T0_CH1_PIN ES_PIN_GPIO_E_9 +#endif +#endif + + +/* AD16C4T_CH2 */ + + +#ifndef ES_AD16C4T0_CH2_GPIO_FUNC +#define ES_AD16C4T0_CH2_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH2_GPIO_PORT +#define ES_AD16C4T0_CH2_GPIO_PORT GPIOA +#endif +#ifndef ES_AD16C4T0_CH2_GPIO_PIN +#define ES_AD16C4T0_CH2_GPIO_PIN GPIO_PIN_9 +#endif + +#ifndef ES_AD16C4T0_CH2_PIN +#ifdef ES_PIN_GPIO_A_9 +#define ES_AD16C4T0_CH2_PIN ES_PIN_GPIO_A_9 +#endif +#endif + +#ifndef ES_AD16C4T0_CH2_GPIO_FUNC +#define ES_AD16C4T0_CH2_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH2_GPIO_PORT +#define ES_AD16C4T0_CH2_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_CH2_GPIO_PIN +#define ES_AD16C4T0_CH2_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_AD16C4T0_CH2_PIN +#ifdef ES_PIN_GPIO_E_11 +#define ES_AD16C4T0_CH2_PIN ES_PIN_GPIO_E_11 +#endif +#endif + + +/* AD16C4T_CH3 */ + + +#ifndef ES_AD16C4T0_CH3_GPIO_FUNC +#define ES_AD16C4T0_CH3_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH3_GPIO_PORT +#define ES_AD16C4T0_CH3_GPIO_PORT GPIOA +#endif +#ifndef ES_AD16C4T0_CH3_GPIO_PIN +#define ES_AD16C4T0_CH3_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_AD16C4T0_CH3_PIN +#ifdef ES_PIN_GPIO_A_10 +#define ES_AD16C4T0_CH3_PIN ES_PIN_GPIO_A_10 +#endif +#endif + +#ifndef ES_AD16C4T0_CH3_GPIO_FUNC +#define ES_AD16C4T0_CH3_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH3_GPIO_PORT +#define ES_AD16C4T0_CH3_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_CH3_GPIO_PIN +#define ES_AD16C4T0_CH3_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_AD16C4T0_CH3_PIN +#ifdef ES_PIN_GPIO_E_13 +#define ES_AD16C4T0_CH3_PIN ES_PIN_GPIO_E_13 +#endif +#endif + + +/* AD16C4T_CH4 */ + + +#ifndef ES_AD16C4T0_CH4_GPIO_FUNC +#define ES_AD16C4T0_CH4_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH4_GPIO_PORT +#define ES_AD16C4T0_CH4_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_CH4_GPIO_PIN +#define ES_AD16C4T0_CH4_GPIO_PIN GPIO_PIN_14 +#endif + +#ifndef ES_AD16C4T0_CH4_PIN +#ifdef ES_PIN_GPIO_E_14 +#define ES_AD16C4T0_CH4_PIN ES_PIN_GPIO_E_14 +#endif +#endif + +#ifndef ES_AD16C4T0_CH4_GPIO_FUNC +#define ES_AD16C4T0_CH4_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH4_GPIO_PORT +#define ES_AD16C4T0_CH4_GPIO_PORT GPIOA +#endif +#ifndef ES_AD16C4T0_CH4_GPIO_PIN +#define ES_AD16C4T0_CH4_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_AD16C4T0_CH4_PIN +#ifdef ES_PIN_GPIO_A_11 +#define ES_AD16C4T0_CH4_PIN ES_PIN_GPIO_A_11 +#endif +#endif + + +/* AD16C4T_CH1N */ + + +#ifndef ES_AD16C4T0_CH1N_GPIO_FUNC +#define ES_AD16C4T0_CH1N_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_AD16C4T0_CH1N_GPIO_PORT +#define ES_AD16C4T0_CH1N_GPIO_PORT GPIOA +#endif +#ifndef ES_AD16C4T0_CH1N_GPIO_PIN +#define ES_AD16C4T0_CH1N_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_AD16C4T0_CH1N_PIN +#ifdef ES_PIN_GPIO_A_7 +#define ES_AD16C4T0_CH1N_PIN ES_PIN_GPIO_A_7 +#endif +#endif + +#ifndef ES_AD16C4T0_CH1N_GPIO_FUNC +#define ES_AD16C4T0_CH1N_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH1N_GPIO_PORT +#define ES_AD16C4T0_CH1N_GPIO_PORT GPIOB +#endif +#ifndef ES_AD16C4T0_CH1N_GPIO_PIN +#define ES_AD16C4T0_CH1N_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_AD16C4T0_CH1N_PIN +#ifdef ES_PIN_GPIO_B_13 +#define ES_AD16C4T0_CH1N_PIN ES_PIN_GPIO_B_13 +#endif +#endif + +#ifndef ES_AD16C4T0_CH1N_GPIO_FUNC +#define ES_AD16C4T0_CH1N_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH1N_GPIO_PORT +#define ES_AD16C4T0_CH1N_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_CH1N_GPIO_PIN +#define ES_AD16C4T0_CH1N_GPIO_PIN GPIO_PIN_8 +#endif + +#ifndef ES_AD16C4T0_CH1N_PIN +#ifdef ES_PIN_GPIO_E_8 +#define ES_AD16C4T0_CH1N_PIN ES_PIN_GPIO_E_8 +#endif +#endif + + +/* AD16C4T_CH2N */ + + +#ifndef ES_AD16C4T0_CH2N_GPIO_FUNC +#define ES_AD16C4T0_CH2N_GPIO_FUNC GPIO_FUNC_6 +#endif +#ifndef ES_AD16C4T0_CH2N_GPIO_PORT +#define ES_AD16C4T0_CH2N_GPIO_PORT GPIOB +#endif +#ifndef ES_AD16C4T0_CH2N_GPIO_PIN +#define ES_AD16C4T0_CH2N_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_AD16C4T0_CH2N_PIN +#ifdef ES_PIN_GPIO_B_0 +#define ES_AD16C4T0_CH2N_PIN ES_PIN_GPIO_B_0 +#endif +#endif + +#ifndef ES_AD16C4T0_CH2N_GPIO_FUNC +#define ES_AD16C4T0_CH2N_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH2N_GPIO_PORT +#define ES_AD16C4T0_CH2N_GPIO_PORT GPIOB +#endif +#ifndef ES_AD16C4T0_CH2N_GPIO_PIN +#define ES_AD16C4T0_CH2N_GPIO_PIN GPIO_PIN_14 +#endif + +#ifndef ES_AD16C4T0_CH2N_PIN +#ifdef ES_PIN_GPIO_B_14 +#define ES_AD16C4T0_CH2N_PIN ES_PIN_GPIO_B_14 +#endif +#endif + +#ifndef ES_AD16C4T0_CH2N_GPIO_FUNC +#define ES_AD16C4T0_CH2N_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH2N_GPIO_PORT +#define ES_AD16C4T0_CH2N_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_CH2N_GPIO_PIN +#define ES_AD16C4T0_CH2N_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_AD16C4T0_CH2N_PIN +#ifdef ES_PIN_GPIO_E_10 +#define ES_AD16C4T0_CH2N_PIN ES_PIN_GPIO_E_10 +#endif +#endif + + +/* AD16C4T_CH3N */ + + +#ifndef ES_AD16C4T0_CH3N_GPIO_FUNC +#define ES_AD16C4T0_CH3N_GPIO_FUNC GPIO_FUNC_6 +#endif +#ifndef ES_AD16C4T0_CH3N_GPIO_PORT +#define ES_AD16C4T0_CH3N_GPIO_PORT GPIOB +#endif +#ifndef ES_AD16C4T0_CH3N_GPIO_PIN +#define ES_AD16C4T0_CH3N_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_AD16C4T0_CH3N_PIN +#ifdef ES_PIN_GPIO_B_1 +#define ES_AD16C4T0_CH3N_PIN ES_PIN_GPIO_B_1 +#endif +#endif + +#ifndef ES_AD16C4T0_CH3N_GPIO_FUNC +#define ES_AD16C4T0_CH3N_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH3N_GPIO_PORT +#define ES_AD16C4T0_CH3N_GPIO_PORT GPIOB +#endif +#ifndef ES_AD16C4T0_CH3N_GPIO_PIN +#define ES_AD16C4T0_CH3N_GPIO_PIN GPIO_PIN_15 +#endif + +#ifndef ES_AD16C4T0_CH3N_PIN +#ifdef ES_PIN_GPIO_B_15 +#define ES_AD16C4T0_CH3N_PIN ES_PIN_GPIO_B_15 +#endif +#endif + +#ifndef ES_AD16C4T0_CH3N_GPIO_FUNC +#define ES_AD16C4T0_CH3N_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH3N_GPIO_PORT +#define ES_AD16C4T0_CH3N_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_CH3N_GPIO_PIN +#define ES_AD16C4T0_CH3N_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_AD16C4T0_CH3N_PIN +#ifdef ES_PIN_GPIO_E_12 +#define ES_AD16C4T0_CH3N_PIN ES_PIN_GPIO_E_12 +#endif +#endif + + +/* AD16C4T_CH4N */ + + + +/* AD16C4T_ET */ + + +#ifndef ES_AD16C4T0_ET_GPIO_FUNC +#define ES_AD16C4T0_ET_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_ET_GPIO_PORT +#define ES_AD16C4T0_ET_GPIO_PORT GPIOA +#endif +#ifndef ES_AD16C4T0_ET_GPIO_PIN +#define ES_AD16C4T0_ET_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_AD16C4T0_ET_PIN +#ifdef ES_PIN_GPIO_A_12 +#define ES_AD16C4T0_ET_PIN ES_PIN_GPIO_A_12 +#endif +#endif + +#ifndef ES_AD16C4T0_ET_GPIO_FUNC +#define ES_AD16C4T0_ET_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_ET_GPIO_PORT +#define ES_AD16C4T0_ET_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_ET_GPIO_PIN +#define ES_AD16C4T0_ET_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_AD16C4T0_ET_PIN +#ifdef ES_PIN_GPIO_E_7 +#define ES_AD16C4T0_ET_PIN ES_PIN_GPIO_E_7 +#endif +#endif + + +/* GP32C4T_CH1 */ + + + +/* GP32C4T_CH2 */ + + + +/* GP32C4T_CH3 */ + + + +/* GP32C4T_CH4 */ + + + +/* GP32C4T_ET */ + + + +/* GP16C4T_CH1 */ + + +#ifndef ES_GP16C4T0_CH1_GPIO_FUNC +#define ES_GP16C4T0_CH1_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH1_GPIO_PORT +#define ES_GP16C4T0_CH1_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C4T0_CH1_GPIO_PIN +#define ES_GP16C4T0_CH1_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_GP16C4T0_CH1_PIN +#ifdef ES_PIN_GPIO_B_6 +#define ES_GP16C4T0_CH1_PIN ES_PIN_GPIO_B_6 +#endif +#endif + +#ifndef ES_GP16C4T0_CH1_GPIO_FUNC +#define ES_GP16C4T0_CH1_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH1_GPIO_PORT +#define ES_GP16C4T0_CH1_GPIO_PORT GPIOD +#endif +#ifndef ES_GP16C4T0_CH1_GPIO_PIN +#define ES_GP16C4T0_CH1_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_GP16C4T0_CH1_PIN +#ifdef ES_PIN_GPIO_D_12 +#define ES_GP16C4T0_CH1_PIN ES_PIN_GPIO_D_12 +#endif +#endif + + +/* GP16C4T_CH2 */ + + +#ifndef ES_GP16C4T0_CH2_GPIO_FUNC +#define ES_GP16C4T0_CH2_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH2_GPIO_PORT +#define ES_GP16C4T0_CH2_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C4T0_CH2_GPIO_PIN +#define ES_GP16C4T0_CH2_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_GP16C4T0_CH2_PIN +#ifdef ES_PIN_GPIO_B_7 +#define ES_GP16C4T0_CH2_PIN ES_PIN_GPIO_B_7 +#endif +#endif + +#ifndef ES_GP16C4T0_CH2_GPIO_FUNC +#define ES_GP16C4T0_CH2_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH2_GPIO_PORT +#define ES_GP16C4T0_CH2_GPIO_PORT GPIOD +#endif +#ifndef ES_GP16C4T0_CH2_GPIO_PIN +#define ES_GP16C4T0_CH2_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_GP16C4T0_CH2_PIN +#ifdef ES_PIN_GPIO_D_13 +#define ES_GP16C4T0_CH2_PIN ES_PIN_GPIO_D_13 +#endif +#endif + + +/* GP16C4T_CH3 */ + + +#ifndef ES_GP16C4T0_CH3_GPIO_FUNC +#define ES_GP16C4T0_CH3_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH3_GPIO_PORT +#define ES_GP16C4T0_CH3_GPIO_PORT GPIOD +#endif +#ifndef ES_GP16C4T0_CH3_GPIO_PIN +#define ES_GP16C4T0_CH3_GPIO_PIN GPIO_PIN_14 +#endif + +#ifndef ES_GP16C4T0_CH3_PIN +#ifdef ES_PIN_GPIO_D_14 +#define ES_GP16C4T0_CH3_PIN ES_PIN_GPIO_D_14 +#endif +#endif + +#ifndef ES_GP16C4T0_CH3_GPIO_FUNC +#define ES_GP16C4T0_CH3_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH3_GPIO_PORT +#define ES_GP16C4T0_CH3_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C4T0_CH3_GPIO_PIN +#define ES_GP16C4T0_CH3_GPIO_PIN GPIO_PIN_8 +#endif + +#ifndef ES_GP16C4T0_CH3_PIN +#ifdef ES_PIN_GPIO_B_8 +#define ES_GP16C4T0_CH3_PIN ES_PIN_GPIO_B_8 +#endif +#endif + + +/* GP16C4T_CH4 */ + + +#ifndef ES_GP16C4T0_CH4_GPIO_FUNC +#define ES_GP16C4T0_CH4_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH4_GPIO_PORT +#define ES_GP16C4T0_CH4_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C4T0_CH4_GPIO_PIN +#define ES_GP16C4T0_CH4_GPIO_PIN GPIO_PIN_9 +#endif + +#ifndef ES_GP16C4T0_CH4_PIN +#ifdef ES_PIN_GPIO_B_9 +#define ES_GP16C4T0_CH4_PIN ES_PIN_GPIO_B_9 +#endif +#endif + +#ifndef ES_GP16C4T0_CH4_GPIO_FUNC +#define ES_GP16C4T0_CH4_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH4_GPIO_PORT +#define ES_GP16C4T0_CH4_GPIO_PORT GPIOD +#endif +#ifndef ES_GP16C4T0_CH4_GPIO_PIN +#define ES_GP16C4T0_CH4_GPIO_PIN GPIO_PIN_15 +#endif + +#ifndef ES_GP16C4T0_CH4_PIN +#ifdef ES_PIN_GPIO_D_15 +#define ES_GP16C4T0_CH4_PIN ES_PIN_GPIO_D_15 +#endif +#endif + + +/* GP16C4T_ET */ + + +#ifndef ES_GP16C4T0_ET_GPIO_FUNC +#define ES_GP16C4T0_ET_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_ET_GPIO_PORT +#define ES_GP16C4T0_ET_GPIO_PORT GPIOE +#endif +#ifndef ES_GP16C4T0_ET_GPIO_PIN +#define ES_GP16C4T0_ET_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_GP16C4T0_ET_PIN +#ifdef ES_PIN_GPIO_E_0 +#define ES_GP16C4T0_ET_PIN ES_PIN_GPIO_E_0 +#endif +#endif + + +/* GP16C2T_CH1 */ + + +#ifndef ES_GP16C2T0_CH1_GPIO_FUNC +#define ES_GP16C2T0_CH1_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C2T0_CH1_GPIO_PORT +#define ES_GP16C2T0_CH1_GPIO_PORT GPIOA +#endif +#ifndef ES_GP16C2T0_CH1_GPIO_PIN +#define ES_GP16C2T0_CH1_GPIO_PIN GPIO_PIN_15 +#endif + +#ifndef ES_GP16C2T0_CH1_PIN +#ifdef ES_PIN_GPIO_A_15 +#define ES_GP16C2T0_CH1_PIN ES_PIN_GPIO_A_15 +#endif +#endif + +#ifndef ES_GP16C2T0_CH1_GPIO_FUNC +#define ES_GP16C2T0_CH1_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C2T0_CH1_GPIO_PORT +#define ES_GP16C2T0_CH1_GPIO_PORT GPIOF +#endif +#ifndef ES_GP16C2T0_CH1_GPIO_PIN +#define ES_GP16C2T0_CH1_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_GP16C2T0_CH1_PIN +#ifdef ES_PIN_GPIO_F_7 +#define ES_GP16C2T0_CH1_PIN ES_PIN_GPIO_F_7 +#endif +#endif + +#ifndef ES_GP16C2T1_CH1_GPIO_FUNC +#define ES_GP16C2T1_CH1_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_GP16C2T1_CH1_GPIO_PORT +#define ES_GP16C2T1_CH1_GPIO_PORT GPIOA +#endif +#ifndef ES_GP16C2T1_CH1_GPIO_PIN +#define ES_GP16C2T1_CH1_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_GP16C2T1_CH1_PIN +#ifdef ES_PIN_GPIO_A_6 +#define ES_GP16C2T1_CH1_PIN ES_PIN_GPIO_A_6 +#endif +#endif + +#ifndef ES_GP16C2T1_CH1_GPIO_FUNC +#define ES_GP16C2T1_CH1_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_GP16C2T1_CH1_GPIO_PORT +#define ES_GP16C2T1_CH1_GPIO_PORT GPIOC +#endif +#ifndef ES_GP16C2T1_CH1_GPIO_PIN +#define ES_GP16C2T1_CH1_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_GP16C2T1_CH1_PIN +#ifdef ES_PIN_GPIO_C_6 +#define ES_GP16C2T1_CH1_PIN ES_PIN_GPIO_C_6 +#endif +#endif + +#ifndef ES_GP16C2T1_CH1_GPIO_FUNC +#define ES_GP16C2T1_CH1_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C2T1_CH1_GPIO_PORT +#define ES_GP16C2T1_CH1_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C2T1_CH1_GPIO_PIN +#define ES_GP16C2T1_CH1_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_GP16C2T1_CH1_PIN +#ifdef ES_PIN_GPIO_B_4 +#define ES_GP16C2T1_CH1_PIN ES_PIN_GPIO_B_4 +#endif +#endif + + +/* GP16C2T_CH2 */ + + +#ifndef ES_GP16C2T0_CH2_GPIO_FUNC +#define ES_GP16C2T0_CH2_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C2T0_CH2_GPIO_PORT +#define ES_GP16C2T0_CH2_GPIO_PORT GPIOA +#endif +#ifndef ES_GP16C2T0_CH2_GPIO_PIN +#define ES_GP16C2T0_CH2_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_GP16C2T0_CH2_PIN +#ifdef ES_PIN_GPIO_A_1 +#define ES_GP16C2T0_CH2_PIN ES_PIN_GPIO_A_1 +#endif +#endif + +#ifndef ES_GP16C2T0_CH2_GPIO_FUNC +#define ES_GP16C2T0_CH2_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C2T0_CH2_GPIO_PORT +#define ES_GP16C2T0_CH2_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C2T0_CH2_GPIO_PIN +#define ES_GP16C2T0_CH2_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_GP16C2T0_CH2_PIN +#ifdef ES_PIN_GPIO_B_3 +#define ES_GP16C2T0_CH2_PIN ES_PIN_GPIO_B_3 +#endif +#endif + +#ifndef ES_GP16C2T1_CH2_GPIO_FUNC +#define ES_GP16C2T1_CH2_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_GP16C2T1_CH2_GPIO_PORT +#define ES_GP16C2T1_CH2_GPIO_PORT GPIOA +#endif +#ifndef ES_GP16C2T1_CH2_GPIO_PIN +#define ES_GP16C2T1_CH2_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_GP16C2T1_CH2_PIN +#ifdef ES_PIN_GPIO_A_7 +#define ES_GP16C2T1_CH2_PIN ES_PIN_GPIO_A_7 +#endif +#endif + +#ifndef ES_GP16C2T1_CH2_GPIO_FUNC +#define ES_GP16C2T1_CH2_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_GP16C2T1_CH2_GPIO_PORT +#define ES_GP16C2T1_CH2_GPIO_PORT GPIOC +#endif +#ifndef ES_GP16C2T1_CH2_GPIO_PIN +#define ES_GP16C2T1_CH2_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_GP16C2T1_CH2_PIN +#ifdef ES_PIN_GPIO_C_7 +#define ES_GP16C2T1_CH2_PIN ES_PIN_GPIO_C_7 +#endif +#endif + +#ifndef ES_GP16C2T1_CH2_GPIO_FUNC +#define ES_GP16C2T1_CH2_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C2T1_CH2_GPIO_PORT +#define ES_GP16C2T1_CH2_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C2T1_CH2_GPIO_PIN +#define ES_GP16C2T1_CH2_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_GP16C2T1_CH2_PIN +#ifdef ES_PIN_GPIO_B_5 +#define ES_GP16C2T1_CH2_PIN ES_PIN_GPIO_B_5 +#endif +#endif + + +/* GP16C2T_CH1N */ + + +#ifndef ES_GP16C2T0_CH1N_GPIO_FUNC +#define ES_GP16C2T0_CH1N_GPIO_FUNC GPIO_FUNC_6 +#endif +#ifndef ES_GP16C2T0_CH1N_GPIO_PORT +#define ES_GP16C2T0_CH1N_GPIO_PORT GPIOA +#endif +#ifndef ES_GP16C2T0_CH1N_GPIO_PIN +#define ES_GP16C2T0_CH1N_GPIO_PIN GPIO_PIN_2 +#endif + +#ifndef ES_GP16C2T0_CH1N_PIN +#ifdef ES_PIN_GPIO_A_2 +#define ES_GP16C2T0_CH1N_PIN ES_PIN_GPIO_A_2 +#endif +#endif + +#ifndef ES_GP16C2T0_CH1N_GPIO_FUNC +#define ES_GP16C2T0_CH1N_GPIO_FUNC GPIO_FUNC_6 +#endif +#ifndef ES_GP16C2T0_CH1N_GPIO_PORT +#define ES_GP16C2T0_CH1N_GPIO_PORT GPIOC +#endif +#ifndef ES_GP16C2T0_CH1N_GPIO_PIN +#define ES_GP16C2T0_CH1N_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_GP16C2T0_CH1N_PIN +#ifdef ES_PIN_GPIO_C_10 +#define ES_GP16C2T0_CH1N_PIN ES_PIN_GPIO_C_10 +#endif +#endif + +#ifndef ES_GP16C2T1_CH1N_GPIO_FUNC +#define ES_GP16C2T1_CH1N_GPIO_FUNC GPIO_FUNC_6 +#endif +#ifndef ES_GP16C2T1_CH1N_GPIO_PORT +#define ES_GP16C2T1_CH1N_GPIO_PORT GPIOC +#endif +#ifndef ES_GP16C2T1_CH1N_GPIO_PIN +#define ES_GP16C2T1_CH1N_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_GP16C2T1_CH1N_PIN +#ifdef ES_PIN_GPIO_C_4 +#define ES_GP16C2T1_CH1N_PIN ES_PIN_GPIO_C_4 +#endif +#endif + +#ifndef ES_GP16C2T1_CH1N_GPIO_FUNC +#define ES_GP16C2T1_CH1N_GPIO_FUNC GPIO_FUNC_6 +#endif +#ifndef ES_GP16C2T1_CH1N_GPIO_PORT +#define ES_GP16C2T1_CH1N_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C2T1_CH1N_GPIO_PIN +#define ES_GP16C2T1_CH1N_GPIO_PIN GPIO_PIN_8 +#endif + +#ifndef ES_GP16C2T1_CH1N_PIN +#ifdef ES_PIN_GPIO_B_8 +#define ES_GP16C2T1_CH1N_PIN ES_PIN_GPIO_B_8 +#endif +#endif + + +/* GP16C2T_CH2N */ + + + + +#endif diff --git a/bsp/essemi/es32f0654/drivers/ES/es_conf_info_pm.h b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_pm.h new file mode 100644 index 0000000000..580268312c --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_pm.h @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_PM_H__ +#define __ES_CONF_INFO_PM_H__ + +#include +#include + +#define ES_PMU_SAVE_LOAD_UART + +/* PM 配置 */ + + + +#endif diff --git a/bsp/essemi/es32f0654/drivers/ES/es_conf_info_pwm.h b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_pwm.h new file mode 100644 index 0000000000..bb0c034da9 --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_pwm.h @@ -0,0 +1,72 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_PWM_H__ +#define __ES_CONF_INFO_PWM_H__ + +#include "es_conf_info_map.h" +#include +#include +#include + + +#define ES_C_PWM_OC_POL_HIGH TIMER_OC_POLARITY_HIGH +#define ES_C_PWM_OC_POL_LOW TIMER_OC_POLARITY_LOW + +#define ES_C_PWM_OC_MODE_PWM1 TIMER_OC_MODE_PWM1 +#define ES_C_PWM_OC_MODE_PWM2 TIMER_OC_MODE_PWM2 + + + +/* PWM 配置 */ + + +/* codes_main */ + + + +#define ES_PWM_OC_POLARITY ES_C_PWM_OC_POL_HIGH +#define ES_PWM_OC_MODE ES_C_PWM_OC_MODE_PWM1 + +#ifndef ES_PWM_OC_POLARITY +#define ES_PWM_OC_POLARITY ES_C_PWM_OC_POL_HIGH +#endif +#ifndef ES_PWM_OC_MODE +#define ES_PWM_OC_MODE ES_C_PWM_OC_MODE_PWM2 +#endif + +#ifndef ES_DEVICE_NAME_AD16C4T0_PWM +#define ES_DEVICE_NAME_AD16C4T0_PWM "pwm0" +#endif +#ifndef ES_DEVICE_NAME_GP16C4T0_PWM +#define ES_DEVICE_NAME_GP16C4T0_PWM "pwm1" +#endif +#ifndef ES_DEVICE_NAME_GP16C2T0_PWM +#define ES_DEVICE_NAME_GP16C2T0_PWM "pwm2" +#endif +#ifndef ES_DEVICE_NAME_GP16C2T1_PWM +#define ES_DEVICE_NAME_GP16C2T1_PWM "pwm3" +#endif + + +#endif diff --git a/bsp/essemi/es32f0654/drivers/ES/es_conf_info_rtc.h b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_rtc.h new file mode 100644 index 0000000000..2aa8faf9d7 --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_rtc.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_RTC_H__ +#define __ES_CONF_INFO_RTC_H__ + +#include +#include + +/* RTC 配置 */ + +#define ES_C_RTC_SOURCE_LRC RTC_SOURCE_LRC +#define ES_C_RTC_SOURCE_LOSC RTC_SOURCE_LOSC + +#define ES_RTC_CLK_SOURCE ES_C_RTC_SOURCE_LOSC + + + + +/* codes_main */ + + +#ifndef ES_DEVICE_NAME_RTC +#define ES_DEVICE_NAME_RTC "rtc" +#endif + +#endif diff --git a/bsp/essemi/es32f0654/drivers/ES/es_conf_info_select.h b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_select.h new file mode 100644 index 0000000000..47ac7c4e6a --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_select.h @@ -0,0 +1,44 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_SELECT_H__ +#define __ES_CONF_INFO_SELECT_H__ + + +#define ES_C_ENABLE 1 +#define ES_C_DISABLE 0 + + +/* codes_main */ +//#define ES_USE_ASSERT ES_C_ENABLE + +#ifndef ES_USE_ASSERT +#define ES_USE_ASSERT ES_C_DISABLE +#endif + + +#if ES_USE_ASSERT + #define USE_ASSERT +#endif + +#endif diff --git a/bsp/essemi/es32f0654/drivers/ES/es_conf_info_spi.h b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_spi.h new file mode 100644 index 0000000000..182bc4c44c --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_spi.h @@ -0,0 +1,132 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_SPI_H__ +#define __ES_CONF_INFO_SPI_H__ + +#include "es_conf_info_map.h" +#include +#include +#include + +/* SPI 配置 */ + +#define SPI_BUS_CONFIG(_CONF_,_I_) do{_CONF_.mode = 0U; \ + _CONF_.mode |= ( ES_SPI##_I_##_MASTER_SLAVE | \ + ES_SPI##_I_##_WIRE_3_4 | \ + ES_SPI##_I_##_CPHA_1_2 | \ + ES_SPI##_I_##_CPOL_H_L | \ + ES_SPI##_I_##_CS | \ + ES_SPI##_I_##_M_L_SB ); \ + _CONF_.data_width = ES_SPI##_I_##_DATA_W; \ + _CONF_.max_hz = ES_SPI##_I_##_MAX_HZ; \ + }while(0) + + +// spi_config.mode &= ~RT_SPI_SLAVE; /* 主机模式 */ +// spi_config.mode &= ~RT_SPI_3WIRE; /* 4线，双向传输 */ +// spi_config.mode |= RT_SPI_CPHA; /* 第二边沿采样 */ +// spi_config.mode |= RT_SPI_CPOL; /* 空闲高电平 */ +// spi_config.mode |= RT_SPI_NO_CS; /* 禁用软件从机选择管理 */ +// spi_config.mode |= RT_SPI_MSB; /* 高位在前 */ +// spi_config.data_width = 8; /* 数据长度：8 */ +// spi_config.max_hz = 2000000; /* 最快时钟频率 */ + +#define ES_C_SPI_CLK_POL_HIGH RT_SPI_CPOL +#define ES_C_SPI_CLK_POL_LOW !RT_SPI_CPOL + +#define ES_C_SPI_CLK_PHA_FIRST !RT_SPI_CPHA +#define ES_C_SPI_CLK_PHA_SECOND RT_SPI_CPHA + +#define ES_C_SPI_MSB RT_SPI_MSB +#define ES_C_SPI_LSB RT_SPI_LSB + +#define ES_C_SPI_CS_LOW_LEVEL 0 +#define ES_C_SPI_CS_HIGH_LEVEL 1 + +/* codes_main */ + + +#ifndef ES_DEVICE_NAME_SPI0_BUS +#define ES_DEVICE_NAME_SPI0_BUS "spi0" +#endif +#ifndef ES_DEVICE_NAME_SPI0_DEV0 +#define ES_DEVICE_NAME_SPI0_DEV0 "spi00" +#endif + +#ifndef ES_DEVICE_NAME_SPI1_BUS +#define ES_DEVICE_NAME_SPI1_BUS "spi1" +#endif +#ifndef ES_DEVICE_NAME_SPI1_DEV0 +#define ES_DEVICE_NAME_SPI1_DEV0 "spi10" +#endif + + +#define ES_SPI_CS_LEVEL ES_C_SPI_CS_LOW_LEVEL + +#ifndef ES_SPI0_CPHA_1_2 +#define ES_SPI0_CPHA_1_2 ES_C_SPI_CLK_PHA_SECOND +#endif +#ifndef ES_SPI0_CPOL_H_L +#define ES_SPI0_CPOL_H_L ES_C_SPI_CLK_POL_HIGH +#endif +#ifndef ES_SPI0_M_L_SB +#define ES_SPI0_M_L_SB RT_SPI_MSB +#endif +#ifndef ES_SPI0_MAX_HZ +#define ES_SPI0_MAX_HZ 2000000 +#endif +#ifndef ES_SPI0_NSS_PIN +#define ES_SPI0_NSS_PIN 0xFFFFFFFF +#endif + +#ifndef ES_SPI1_CPHA_1_2 +#define ES_SPI1_CPHA_1_2 ES_C_SPI_CLK_PHA_SECOND +#endif +#ifndef ES_SPI1_CPOL_H_L +#define ES_SPI1_CPOL_H_L ES_C_SPI_CLK_POL_HIGH +#endif +#ifndef ES_SPI1_M_L_SB +#define ES_SPI1_M_L_SB RT_SPI_MSB +#endif +#ifndef ES_SPI1_MAX_HZ +#define ES_SPI1_MAX_HZ 2000000 +#endif +#ifndef ES_SPI1_NSS_PIN +#define ES_SPI1_NSS_PIN 0xFFFFFFFF +#endif + + + +#define ES_SPI0_MASTER_SLAVE !RT_SPI_SLAVE +#define ES_SPI0_WIRE_3_4 !RT_SPI_3WIRE +#define ES_SPI0_CS RT_SPI_NO_CS +#define ES_SPI0_DATA_W 8 + +#define ES_SPI1_MASTER_SLAVE !RT_SPI_SLAVE +#define ES_SPI1_WIRE_3_4 !RT_SPI_3WIRE +#define ES_SPI1_CS RT_SPI_NO_CS +#define ES_SPI1_DATA_W 8 + + +#endif diff --git a/bsp/essemi/es32f0654/drivers/ES/es_conf_info_uart.h b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_uart.h new file mode 100644 index 0000000000..2dd32aa220 --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_uart.h @@ -0,0 +1,206 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_UART_H__ +#define __ES_CONF_INFO_UART_H__ + +#include "es_conf_info_map.h" +#include +#include +#include +#include + + + +#define ES_C_UART_PARITY_NONE PARITY_NONE +#define ES_C_UART_PARITY_ODD PARITY_ODD +#define ES_C_UART_PARITY_EVEN PARITY_EVEN + +#define ES_C_UART_STOP_1 STOP_BITS_1 +#define ES_C_UART_STOP_2 STOP_BITS_2 + + +/* UART 配置 */ + +/* codes_main */ + + + +#ifndef ES_DEVICE_NAME_UART0 +#define ES_DEVICE_NAME_UART0 "uart0" +#endif +#ifndef ES_DEVICE_NAME_UART1 +#define ES_DEVICE_NAME_UART1 "uart1" +#endif +#ifndef ES_DEVICE_NAME_UART2 +#define ES_DEVICE_NAME_UART2 "uart2" +#endif +#ifndef ES_DEVICE_NAME_UART3 +#define ES_DEVICE_NAME_UART3 "uart3" +#endif +#ifndef ES_DEVICE_NAME_USART0 +#define ES_DEVICE_NAME_USART0 "usart0" +#endif +#ifndef ES_DEVICE_NAME_USART1 +#define ES_DEVICE_NAME_USART1 "usart1" +#endif + +#ifndef ES_CONF_UART0_BAUD_RATE +#define ES_CONF_UART0_BAUD_RATE 115200 +#endif +#ifndef ES_CONF_UART0_PARITY +#define ES_CONF_UART0_PARITY ES_C_UART_PARITY_NONE +#endif +#ifndef ES_CONF_UART0_STOP_BITS +#define ES_CONF_UART0_STOP_BITS ES_C_UART_STOP_1 +#endif + +#ifndef ES_CONF_UART1_BAUD_RATE +#define ES_CONF_UART1_BAUD_RATE 115200 +#endif +#ifndef ES_CONF_UART1_PARITY +#define ES_CONF_UART1_PARITY ES_C_UART_PARITY_NONE +#endif +#ifndef ES_CONF_UART1_STOP_BITS +#define ES_CONF_UART1_STOP_BITS ES_C_UART_STOP_1 +#endif + +#ifndef ES_CONF_UART2_BAUD_RATE +#define ES_CONF_UART2_BAUD_RATE 115200 +#endif +#ifndef ES_CONF_UART2_PARITY +#define ES_CONF_UART2_PARITY ES_C_UART_PARITY_NONE +#endif +#ifndef ES_CONF_UART2_STOP_BITS +#define ES_CONF_UART2_STOP_BITS ES_C_UART_STOP_1 +#endif + +#ifndef ES_CONF_UART3_BAUD_RATE +#define ES_CONF_UART3_BAUD_RATE 115200 +#endif +#ifndef ES_CONF_UART3_PARITY +#define ES_CONF_UART3_PARITY ES_C_UART_PARITY_NONE +#endif +#ifndef ES_CONF_UART3_STOP_BITS +#define ES_CONF_UART3_STOP_BITS ES_C_UART_STOP_1 +#endif + +#ifndef ES_CONF_USART0_BAUD_RATE +#define ES_CONF_USART0_BAUD_RATE 115200 +#endif +#ifndef ES_CONF_USART0_PARITY +#define ES_CONF_USART0_PARITY ES_C_UART_PARITY_NONE +#endif +#ifndef ES_CONF_USART0_STOP_BITS +#define ES_CONF_USART0_STOP_BITS ES_C_UART_STOP_1 +#endif + +#ifndef ES_CONF_USART1_BAUD_RATE +#define ES_CONF_USART1_BAUD_RATE 115200 +#endif +#ifndef ES_CONF_USART1_PARITY +#define ES_CONF_USART1_PARITY ES_C_UART_PARITY_NONE +#endif +#ifndef ES_CONF_USART1_STOP_BITS +#define ES_CONF_USART1_STOP_BITS ES_C_UART_STOP_1 +#endif + + +#define ES_UART0_CONFIG \ +{ \ + ES_CONF_UART0_BAUD_RATE, \ + DATA_BITS_8, \ + ES_CONF_UART0_STOP_BITS, \ + ES_CONF_UART0_PARITY, \ + BIT_ORDER_LSB, \ + NRZ_NORMAL, \ + RT_SERIAL_RB_BUFSZ, \ + 0 \ +} + + +#define ES_UART1_CONFIG \ +{ \ + ES_CONF_UART1_BAUD_RATE, \ + DATA_BITS_8, \ + ES_CONF_UART1_STOP_BITS, \ + ES_CONF_UART1_PARITY, \ + BIT_ORDER_LSB, \ + NRZ_NORMAL, \ + RT_SERIAL_RB_BUFSZ, \ + 0 \ +} + + +#define ES_UART2_CONFIG \ +{ \ + ES_CONF_UART2_BAUD_RATE, \ + DATA_BITS_8, \ + ES_CONF_UART2_STOP_BITS, \ + ES_CONF_UART2_PARITY, \ + BIT_ORDER_LSB, \ + NRZ_NORMAL, \ + RT_SERIAL_RB_BUFSZ, \ + 0 \ +} + + +#define ES_UART3_CONFIG \ +{ \ + ES_CONF_UART3_BAUD_RATE, \ + DATA_BITS_8, \ + ES_CONF_UART3_STOP_BITS, \ + ES_CONF_UART3_PARITY, \ + BIT_ORDER_LSB, \ + NRZ_NORMAL, \ + RT_SERIAL_RB_BUFSZ, \ + 0 \ +} + + +#define ES_USART0_CONFIG \ +{ \ + ES_CONF_USART0_BAUD_RATE, \ + DATA_BITS_8, \ + ES_CONF_USART0_STOP_BITS, \ + ES_CONF_USART0_PARITY, \ + BIT_ORDER_LSB, \ + NRZ_NORMAL, \ + RT_SERIAL_RB_BUFSZ, \ + 0 \ +} + + +#define ES_USART1_CONFIG \ +{ \ + ES_CONF_USART1_BAUD_RATE, \ + DATA_BITS_8, \ + ES_CONF_USART1_STOP_BITS, \ + ES_CONF_USART1_PARITY, \ + BIT_ORDER_LSB, \ + NRZ_NORMAL, \ + RT_SERIAL_RB_BUFSZ, \ + 0 \ +} + +#endif diff --git a/bsp/essemi/es32f0654/drivers/Kconfig b/bsp/essemi/es32f0654/drivers/Kconfig index 3c3cf9e9e5..75d678805d 100644 --- a/bsp/essemi/es32f0654/drivers/Kconfig +++ b/bsp/essemi/es32f0654/drivers/Kconfig @@ -6,129 +6,7 @@ menu "Hardware Drivers Config" select RT_USING_PIN default y - menu "UART Drivers" - config BSP_USING_UART0 - bool "Enable UART0 PB10/PB11(T/R)" - select RT_USING_SERIAL - default n - - config BSP_USING_UART1 - bool "Enable UART1 PC10/PC11(T/R)" - select RT_USING_SERIAL - default n - - config BSP_USING_UART2 - bool "Enable UART2 PC12/PD02(T/R)" - select RT_USING_SERIAL - default y - depends on !BSP_USING_HWTIMER1 - - config BSP_USING_UART3 - bool "Enable UART3 PC04/PC05(T/R)" - select RT_USING_SERIAL - default n - depends on !BSP_USING_HWTIMER2 - endmenu - - menu "SPI Drivers" - config BSP_USING_SPI0 - bool "Enable SPI0 BUS PB03/PB04/PB05(CLK/MISO/MOSI)" - select RT_USING_SPI - select RT_USING_PIN - default n - - config BSP_USING_SPI1 - bool "Enable SPI1 BUS PB13/PB14/PB15(CLK/MISO/MOSI)" - select RT_USING_SPI - select RT_USING_PIN - default n - endmenu - - menu "I2C Drivers" - config BSP_USING_I2C0 - bool "Enable I2C0 BUS PB08/PB09(SCL/SDA)" - select RT_USING_I2C - default n - - config BSP_USING_I2C1 - bool "Enable I2C1 BUS PB10/PB11(SCL/SDA)" - select RT_USING_I2C - default n - endmenu - - menu "CAN Drivers" - config BSP_USING_CAN - bool "Enable CAN BUS PA11/PA12(RX/TX)" - select RT_USING_CAN - default n - endmenu - - menu "PWM Drivers" - config BSP_USING_PWM0 - bool "Using PWM0 PA08/PA09/PA10/PA11" - select RT_USING_PWM - default n - - config BSP_USING_PWM1 - bool "Using PWM1 PB06/PB07/PB08/PB09" - select RT_USING_PWM - default n - - config BSP_USING_PWM2 - bool "Using PWM2 PA00/PA01" - select RT_USING_PWM - default n - - config BSP_USING_PWM3 - bool "Using PWM3 PC06/PC07" - select RT_USING_PWM - default n - endmenu - - menu "HWtimer Drivers" - config BSP_USING_HWTIMER0 - bool "Using timer0" - select RT_USING_HWTIMER - default n - - config BSP_USING_HWTIMER1 - bool "Using timer1" - select RT_USING_HWTIMER - default n - depends on !BSP_USING_UART2 - - config BSP_USING_HWTIMER2 - bool "Using timer2" - select RT_USING_HWTIMER - default n - depends on !BSP_USING_UART3 - - config BSP_USING_HWTIMER3 - bool "Using timer3" - select RT_USING_HWTIMER - default n - endmenu - - menu "RTC Drivers" - config BSP_USING_RTC - bool "Using RTC" - select RT_USING_RTC - default n - endmenu - - menu "PM Drivers" - config BSP_USING_PM - bool "Using PM" - select RT_USING_PM - default n - endmenu - - menu "ADC Drivers" - config BSP_USING_ADC - bool "Using ADC" - select RT_USING_ADC - default n - endmenu + source "drivers/ES/Kconfig" endmenu @@ -137,11 +15,21 @@ menu "Hardware Drivers Config" config BSP_USING_SPI_FLASH bool "Enable SPI FLASH (W25Q64 spi0)" select BSP_USING_SPI - select BSP_USING_SPI0 select RT_USING_SFUD select RT_SFUD_USING_SFDP default n +if BSP_USING_SPI_FLASH + + config ES_DEVICE_NAME_SPI_DEV + string "The name of spi device (registered)" + default "spi00" + + config ES_DEVICE_NAME_SPI_FALSH_DEV + string "The name of spi flash device" + default "W25Q64" +endif + endmenu menu "Offboard Peripheral Drivers" @@ -163,13 +51,17 @@ menu "Hardware Drivers Config" bool "BSP_USING_EXAMPLE_I2C" default n + config BSP_USING_EXAMPLE_I2C_E2PROM + bool "BSP_USING_EXAMPLE_I2C_E2PROM" + default n + config BSP_USING_EXAMPLE_LED_BLINK bool "BSP_USING_EXAMPLE_LED_BLINK" - default y + default n config BSP_USING_EXAMPLE_PIN_BEEP bool "BSP_USING_EXAMPLE_PIN_BEEP" - default y + default n config BSP_USING_EXAMPLE_PWM_LED bool "BSP_USING_EXAMPLE_PWM_LED" @@ -185,7 +77,7 @@ menu "Hardware Drivers Config" config BSP_USING_EXAMPLE_UART bool "BSP_USING_EXAMPLE_UART" - default y + default n config BSP_USING_EXAMPLE_CAN bool "BSP_USING_EXAMPLE_CAN" diff --git a/bsp/essemi/es32f0654/drivers/SConscript b/bsp/essemi/es32f0654/drivers/SConscript index 280c6f5c90..0e34f50b2f 100644 --- a/bsp/essemi/es32f0654/drivers/SConscript +++ b/bsp/essemi/es32f0654/drivers/SConscript @@ -14,7 +14,10 @@ if GetDepend('RT_USING_PIN'): src += ['drv_gpio.c'] # add serial driver code -if GetDepend('BSP_USING_UART0') or GetDepend('BSP_USING_UART1') or GetDepend('BSP_USING_UART2') or GetDepend('BSP_USING_UART3'): +if GetDepend('BSP_USING_UART0') or GetDepend('BSP_USING_UART1') or GetDepend('BSP_USING_UART2') or GetDepend('BSP_USING_UART3') or \ + GetDepend('BSP_USING_UART4') or GetDepend('BSP_USING_UART5') or \ + GetDepend('BSP_USING_USART0') or GetDepend('BSP_USING_USART1') or GetDepend('BSP_USING_USART2') or GetDepend('BSP_USING_USART3') or \ + GetDepend('BSP_USING_USART4') or GetDepend('BSP_USING_USART5'): src += ['drv_uart.c'] # add spi driver code @@ -26,40 +29,50 @@ if GetDepend('BSP_USING_I2C0') or GetDepend('BSP_USING_I2C1'): src += ['drv_i2c.c'] # add can driver code -if GetDepend('BSP_USING_CAN'): +if GetDepend('BSP_USING_CAN') or GetDepend('BSP_USING_CAN0') or GetDepend('RT_USING_CAN'): src += ['drv_can.c'] -# add spi flash driver code -if GetDepend('BSP_USING_SPI_FLASH'): - src += ['drv_spiflash.c'] -# add pwm driver code -if GetDepend('BSP_USING_PWM0') or GetDepend('BSP_USING_PWM1') or GetDepend('BSP_USING_PWM2') or GetDepend('BSP_USING_PWM3'): - src += ['drv_pwm.c'] - -# add hwtimer driver code -if GetDepend('BSP_USING_HWTIMER0') or GetDepend('BSP_USING_HWTIMER1') or GetDepend('BSP_USING_HWTIMER2') or GetDepend('BSP_USING_HWTIMER3'): - src += ['drv_hwtimer.c'] +# add adc driver code +if GetDepend(['BSP_USING_ADC0']) or GetDepend('BSP_USING_ADC'): + src += ['drv_adc.c'] # add rtc driver code if GetDepend(['BSP_USING_RTC']): src += ['drv_rtc.c'] +# add spi flash driver code +if GetDepend('BSP_USING_SPI_FLASH'): + src += ['drv_spiflash.c'] + +# add hwtimer driver code +if GetDepend('BSP_USING_AD16C4T0_HWTIMER') or GetDepend('BSP_USING_AD16C4T1_HWTIMER') or \ + GetDepend('BSP_USING_GP32C4T0_HWTIMER') or GetDepend('BSP_USING_GP32C4T1_HWTIMER') or \ + GetDepend('BSP_USING_GP16C4T0_HWTIMER') or GetDepend('BSP_USING_GP16C4T1_HWTIMER') or \ + GetDepend('BSP_USING_GP16C2T0_HWTIMER') or GetDepend('BSP_USING_GP16C2T1_HWTIMER') or \ + GetDepend('BSP_USING_GP16C4T0_HWTIMER') or GetDepend('BSP_USING_GP16C4T1_HWTIMER') or \ + GetDepend('BSP_USING_BS16T0_HWTIMER') or GetDepend('BSP_USING_BS16T1_HWTIMERIMER') or \ + GetDepend('BSP_USING_BS16T2_HWTIMER') or GetDepend('BSP_USING_BS16T3_HWTIMER'): + src += ['drv_hwtimer.c'] + +# add pwm driver code +if GetDepend('BSP_USING_AD16C4T0_PWM') or GetDepend('BSP_USING_AD16C4T1_PWM') or \ + GetDepend('BSP_USING_GP16C4T0_PWM') or GetDepend('BSP_USING_GP16C4T1_PWM') or \ + GetDepend('BSP_USING_GP16C2T0__PWM') or GetDepend('BSP_USING_GP16C2T1_PWM') or \ + GetDepend('BSP_USING_GP32C4T0_PWM') or GetDepend('BSP_USING_GP32C4T1_PWM') or \ + GetDepend('BSP_USING_GP16C4T0_PWM') or GetDepend('BSP_USING_GP16C4T1_PWM'): + src += ['drv_pwm.c'] + # add pm driver code if GetDepend(['BSP_USING_PM']): src += ['drv_pm.c'] - -# add adc driver code -if GetDepend(['BSP_USING_ADC']): - src += ['drv_adc.c'] - CPPPATH = [cwd] group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) objs = objs + group src = [] cwd = GetCurrentDir() -include_path = [cwd] +include_path = [cwd + '/ES'] if GetDepend('BSP_USING_EXAMPLE_ADC_VOL'): src += ['bsp_driver_example/adc_vol_sample.c'] @@ -70,6 +83,9 @@ if GetDepend('BSP_USING_EXAMPLE_HWTIMER'): if GetDepend('BSP_USING_EXAMPLE_I2C'): src += ['bsp_driver_example/i2c_sample.c'] +if GetDepend('BSP_USING_EXAMPLE_I2C_E2PROM'): + src += ['bsp_driver_example/i2c_e2_sample.c'] + if GetDepend('BSP_USING_EXAMPLE_LED_BLINK'): src += ['bsp_driver_example/led_blink_sample.c'] diff --git a/bsp/essemi/es32f0654/drivers/board.c b/bsp/essemi/es32f0654/drivers/board.c index 94b259e485..7411168324 100644 --- a/bsp/essemi/es32f0654/drivers/board.c +++ b/bsp/essemi/es32f0654/drivers/board.c @@ -1,12 +1,25 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes * 2019-01-23 wangyq the first version - * 2019-11-01 wangyq update libraries + * 2019-11-01 wangyq update libraries + * 2021-04-20 liuhy the second version */ #include @@ -14,7 +27,6 @@ #include "board.h" #include "drv_uart.h" #include "drv_gpio.h" -#include #include /** @@ -43,11 +55,65 @@ void NVIC_Configuration(void) *******************************************************************************/ void SystemClock_Config(void) { - /* hosc 12MHz, from hosc/3 pll to 48MHz */ - ald_cmu_pll1_config(CMU_PLL1_INPUT_HOSC_3, CMU_PLL1_OUTPUT_48M); + SYSCFG_UNLOCK(); +#if ES_CMU_LRC_EN + SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); +#else + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); +#endif /*ES_CMU_LRC_EN*/ + +#if ES_CMU_LOSC_EN + SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); +#else + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); +#endif /*ES_CMU_LOSC_EN*/ + +#if ES_CMU_HRC_EN + SET_BIT(CMU->CLKENR, CMU_CLKENR_HRCEN_MSK); +#else + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_HRCEN_MSK); +#endif /*ES_CMU_HRC_EN*/ + +#if ES_CMU_HOSC_EN + SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK); +#else + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK); +#endif /*ES_CMU_HOSC_EN*/ - /* MCLK 48MHz*/ - ald_cmu_clock_config(CMU_CLOCK_PLL1, 48000000); + SYSCFG_LOCK(); + +#if ES_CMU_PLL1_EN + /*PLL的源必须是4M*/ + ald_cmu_pll1_config(ES_PLL1_REFER_CLK, ES_PLL1_OUT_CLK); + + #if ES_CMU_PLL1_SAFE_EN + ald_cmu_pll_safe_config(ENABLE); + #else + ald_cmu_pll_safe_config(DISABLE); + #endif + +#else + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_PLL1EN_MSK); +#endif /*ES_CMU_PLL1_EN*/ + + ald_cmu_clock_config(ES_SYS_CLK_SOURSE, ES_SYS_CLK); + + ald_cmu_div_config(CMU_SYS,ES_CMU_SYS_DIV); + ald_cmu_div_config(CMU_HCLK_1,ES_CMU_HCLK_1_DIV); + ald_cmu_div_config(CMU_PCLK_1,ES_CMU_PCLK_1_DIV); + ald_cmu_div_config(CMU_PCLK_2,ES_CMU_PCLK_2_DIV); + + ald_cmu_perh_clock_config(CMU_PERH_ALL, ENABLE); + +/*低功耗时钟使能*/ +#ifdef RT_USING_PM + SYSCFG_UNLOCK(); + SET_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK); + SET_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK); + SET_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK); + SET_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK); + SYSCFG_LOCK(); +#endif } /******************************************************************************* @@ -71,13 +137,22 @@ void SysTick_Handler(void) { /* enter interrupt */ rt_interrupt_enter(); - + ald_inc_tick(); rt_tick_increase(); /* leave interrupt */ rt_interrupt_leave(); } +/** + * This is the cmu interrupt service. + * + */ +void CMU_Handler(void) +{ + ald_cmu_irq_handler(); +} + /*@}*/ /** * This function will initial ES32F0 board. diff --git a/bsp/essemi/es32f0654/drivers/board.h b/bsp/essemi/es32f0654/drivers/board.h index 5b969142ac..a6fdd9e909 100644 --- a/bsp/essemi/es32f0654/drivers/board.h +++ b/bsp/essemi/es32f0654/drivers/board.h @@ -1,11 +1,24 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes - * 2019-01-23 wangyq the first version + * 2019-01-23 wangyq the first version + * 2021-04-20 liuhy the second version */ // <<< Use Configuration Wizard in Context Menu >>> @@ -13,6 +26,7 @@ #define __BOARD_H__ #include +#include "es_conf_info_cmu.h" #define ES32F0_SRAM_SIZE 0x8000 #define ES32F0_SRAM_END (0x20000000 + ES32F0_SRAM_SIZE) diff --git a/bsp/essemi/es32f0654/drivers/bsp_driver_example/adc_vol_sample.c b/bsp/essemi/es32f0654/drivers/bsp_driver_example/adc_vol_sample.c index 19eed3f35d..7d67c94070 100644 --- a/bsp/essemi/es32f0654/drivers/bsp_driver_example/adc_vol_sample.c +++ b/bsp/essemi/es32f0654/drivers/bsp_driver_example/adc_vol_sample.c @@ -18,6 +18,9 @@ #include #include + +#ifdef RT_USING_ADC + #define ADC_DEV_NAME "adc0" /* ADC 设备名称 */ #define ADC_DEV_CHANNEL 5 /* PA1 ADC 通道 */ #define REFER_VOLTAGE 330 /* 参考电压 3.3V,数据精度乘以100保留2位小数*/ @@ -55,3 +58,5 @@ static int adc_vol_sample(int argc, char *argv[]) } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(adc_vol_sample, adc voltage convert sample); + +#endif diff --git a/bsp/essemi/es32f0654/drivers/bsp_driver_example/can_sample.c b/bsp/essemi/es32f0654/drivers/bsp_driver_example/can_sample.c index 4c16d1d555..17f8f2007f 100644 --- a/bsp/essemi/es32f0654/drivers/bsp_driver_example/can_sample.c +++ b/bsp/essemi/es32f0654/drivers/bsp_driver_example/can_sample.c @@ -18,7 +18,9 @@ #include #include "rtdevice.h" -#define CAN_DEV_NAME "can" /* CAN 设备名称 */ +#ifdef RT_USING_CAN + +#define CAN_DEV_NAME "can0" /* CAN 设备名称 */ static struct rt_semaphore rx_sem; /* 用于接收消息的信号量 */ static rt_device_t can_dev; /* CAN 设备句柄 */ @@ -142,3 +144,5 @@ int can_sample(int argc, char *argv[]) } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(can_sample, can device sample); + +#endif diff --git a/bsp/essemi/es32f0654/drivers/bsp_driver_example/hwtimer_sample.c b/bsp/essemi/es32f0654/drivers/bsp_driver_example/hwtimer_sample.c index e2e39664f3..cc0b790643 100644 --- a/bsp/essemi/es32f0654/drivers/bsp_driver_example/hwtimer_sample.c +++ b/bsp/essemi/es32f0654/drivers/bsp_driver_example/hwtimer_sample.c @@ -17,7 +17,9 @@ #include #include -#define HWTIMER_DEV_NAME "timer0" /* 定时器名称 */ +#ifdef RT_USING_HWTIMER + +#define HWTIMER_DEV_NAME "timer1" /* 定时器名称 */ /* 定时器超时回调函数 */ static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size) @@ -83,3 +85,5 @@ static int hwtimer_sample(int argc, char *argv[]) } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(hwtimer_sample, hwtimer sample); + +#endif diff --git a/bsp/essemi/es32f0654/drivers/bsp_driver_example/i2c_e2_sample.c b/bsp/essemi/es32f0654/drivers/bsp_driver_example/i2c_e2_sample.c new file mode 100644 index 0000000000..3bfd005e67 --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/bsp_driver_example/i2c_e2_sample.c @@ -0,0 +1,109 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Change Logs: + * Date Author Notes + * 2020-12-15 liuhy first implementation. + */ +/* + * 程序清单：这是一个 I2C 设备使用例程 + * 例程导出了 i2c_e2_sample 命令到控制终端 + * 命令调用格式：i2c_e2_sample + * 命令解释：使用默认的I2C总线设备i2c0 + * 程序功能：通过 I2C 设备写读e2prom，ST24C04WP。 +*/ + +/*ST24C04WP 有2个Block ：Block0 的从机地址为：0x50,Block1 的从机地址为：0x51 + 一个Block有 256字节，一页16字节,写只可在一页内(超过一页的范围后,会回到页的开始),读无页限制*/ +#include +#include + +#ifdef RT_USING_I2C + +#define I2C_BUS_NAME "i2c0" /*I2C总线设备名称 */ +#define SLAVE_ADDR 0x50 /*从机地址*/ +#define MEM_ADDR 0x00 /*从机的起始储存地址,范围：0x00到0xEF(例程写读范围：2页)*/ +#define ADDR_LEN 1 /*定义从机储存地址的长度，默认8位,1字节*/ +#define STR_LEN 16 /*接收发送的页数据长度 ,最大16*/ + +static rt_uint8_t mem_addr,rx_buffer[33] = { 0U }; /*读两页,需要32字节，字符串结束'\0'*/ +/*第一个字节' '用来放 E2PROM 的内存地址,最后一个字节'\0'作为子串的结束，不存入e2prom*/ +static rt_uint8_t tx_buffer1[STR_LEN + ADDR_LEN + 1] = " e2prom example !\0"; +static rt_uint8_t tx_buffer2[STR_LEN + ADDR_LEN + 1] = " ABCDEFGH12345678\0"; + +static void i2c_e2_sample(int argc, char *argv[]) +{ + struct rt_i2c_bus_device *i2c_bus = RT_NULL; /* I2C总线设备句柄 */ + struct rt_i2c_msg i2c_msg[2]; /* I2C消息 */ + rt_size_t s_stat; + + i2c_bus = (struct rt_i2c_bus_device *)rt_device_find(I2C_BUS_NAME); /* 通过名字获取I2C总线设备的句柄 */ + + if( i2c_bus == RT_NULL) + { + rt_kprintf("can't find i2c device :%s !\n",I2C_BUS_NAME); + return; + } + + /*写T24C04WP + 如果 (MEM_ADDR & 0x0F) + STR_LEN <= 16, 写的范围为：(MEM_ADDR , MEM_ADDR + STR_LEN ) + (0x10 + MEM_ADDR , 0x10 + MEM_ADDR + STR_LEN ) + 如果 (MEM_ADDR & 0x0F) + STR_LEN > 16, 超出范围的部分会在页内循环写。*/ + tx_buffer1[0] = MEM_ADDR; + + /*初始化消息*/ + i2c_msg[0].addr = SLAVE_ADDR; /* 从机地址 */ + i2c_msg[0].len = ADDR_LEN + STR_LEN ; /* 写入的长度，地址+数据 */ + i2c_msg[0].buf = tx_buffer1; /* 待写入第一段数据 */ + i2c_msg[0].flags = RT_I2C_WR; /* I2C写 */ + s_stat = rt_i2c_transfer(i2c_bus,i2c_msg,1); /* 写入第一段数据 */ + + if( s_stat == 1 )rt_kprintf("write successful. \nmessage: %s\n",&tx_buffer1[1]); + else rt_kprintf("device %s write fail \n",I2C_BUS_NAME); + + tx_buffer2[0] = MEM_ADDR + 0x10; /*加一页*/ + i2c_msg[0].buf = tx_buffer2; /* 待写入第二段数据 */ + s_stat = rt_i2c_transfer(i2c_bus,i2c_msg,1); /* 写入第二段数据 */ + + if( s_stat == 1 )rt_kprintf("write successful. \nmessage: %s\n",&tx_buffer2[1]); + else rt_kprintf("device %s write fail \n",I2C_BUS_NAME); + + /*读T24C04WP 读2页的数据。读数据需要2条消息：第一条消息：发送读取的地址。 + 第二条消息：读取具体的数据。*/ + + mem_addr = MEM_ADDR & 0xF0; /*从页的开始读*/ + + i2c_msg[0].len = ADDR_LEN; + i2c_msg[0].buf = &mem_addr; + + i2c_msg[1].addr = SLAVE_ADDR; /* 从机地址 */ + i2c_msg[1].len = 32; /* 读取的数据长度：2*16 */ + i2c_msg[1].buf = rx_buffer; /* 数据存放地址 */ + i2c_msg[1].flags = RT_I2C_RD; /* I2C读 */ + s_stat = rt_i2c_transfer(i2c_bus,i2c_msg,2); /* 读已写的2页 */ + + if( s_stat == 2 )rt_kprintf(" read successful \n messege : %s \n",rx_buffer); + else + rt_kprintf("read fail \n"); + + return; + +} +/* 导出到 msh 命令列表中 */ +MSH_CMD_EXPORT(i2c_e2_sample, i2c e2prom sample); + +#endif diff --git a/bsp/essemi/es32f0654/drivers/bsp_driver_example/i2c_sample.c b/bsp/essemi/es32f0654/drivers/bsp_driver_example/i2c_sample.c index 2d386433c6..c8a666609d 100644 --- a/bsp/essemi/es32f0654/drivers/bsp_driver_example/i2c_sample.c +++ b/bsp/essemi/es32f0654/drivers/bsp_driver_example/i2c_sample.c @@ -1,7 +1,19 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes @@ -11,14 +23,16 @@ * 程序清单：这是一个 I2C 设备使用例程 * 例程导出了 i2c_io_sample 命令到控制终端 * 命令调用格式：i2c_io_sample - * 命令解释：使用默认的I2C总线设备 + * 命令解释：使用默认的I2C总线设备i2c0 * 程序功能：通过 I2C 设备接收数据并打印，然后将接收的字符加1输出。 */ #include #include -#define I2C_BUS_NAME "i2c1" /* I2C总线设备名称 */ +#ifdef RT_USING_I2C + +#define I2C_BUS_NAME "i2c0" /* I2C总线设备名称 */ #define SLAVE_ADDR 0x2D /* 从机地址 */ #define STR_LEN 16 /* 接收发送的数据长度 */ @@ -95,3 +109,5 @@ static void i2c_io_sample(int argc, char *argv[]) } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(i2c_io_sample, i2c io sample); + +#endif diff --git a/bsp/essemi/es32f0654/drivers/bsp_driver_example/pm_sample.c b/bsp/essemi/es32f0654/drivers/bsp_driver_example/pm_sample.c index f7287e36ac..78358e421c 100644 --- a/bsp/essemi/es32f0654/drivers/bsp_driver_example/pm_sample.c +++ b/bsp/essemi/es32f0654/drivers/bsp_driver_example/pm_sample.c @@ -1,7 +1,19 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes @@ -11,15 +23,18 @@ * 程序清单：这是一个 pm睡眠唤醒的使用例程 * 例程导出了 pm_sample 命令到控制终端 * 命令调用格式：pm_sample - * 命令解释：进入不同的睡眠模式，然后用按键唤醒 + * 命令解释：进入不同的睡眠模式，然后用按键唤醒。 * 程序功能：通过串口输出字符串，告知进入睡眠和唤醒睡眠的情况。 + * 注意：进入睡眠前，如果有中断挂起（SYSTICK、UART、EXTI等），睡眠将被瞬间唤醒。 */ #include #include + +#ifdef RT_USING_PM #define PM_NAME "pm" /* 设备名称 */ -#define WAKE_UP_PIN 18 /* 唤醒源 */ +#define WAKE_UP_PIN 19 /* 唤醒源 */ #define SLEEP_TIMES 12 /* 进入睡眠次数，轮流进入不同的睡眠模式，包括无睡眠模式 */ @@ -65,8 +80,9 @@ void sleep_in_out_callback(rt_uint8_t event, rt_uint8_t mode, void *data) break; /*睡眠唤醒后*/ case RT_PM_EXIT_SLEEP: g_pm_data.flag = 0; /*睡眠唤醒后*/ + /*从深睡眠唤醒后，等待UART时钟未恢复稳定，输出可能丢失*/ rt_kprintf("\n\rEXIT\n\r"); - rt_pm_release(mode); /*释放休眠模式*/ + rt_pm_request(PM_SLEEP_MODE_NONE); /*进无休眠模式*/ return; default: break; @@ -125,6 +141,9 @@ static void pm_test(void *parameter) g_pm_data.flag = 2; } + + /*彻底释放无休眠模式*/ + rt_pm_release_all(PM_SLEEP_MODE_NONE); /*请求选择的休眠模式*/ rt_pm_request(in_mode[i%6]); @@ -137,15 +156,21 @@ static void pm_test(void *parameter) rt_thread_mdelay(500); } - /*释放选择的休眠模式*/ - rt_pm_release(in_mode[i%6]); + /*释放选择的休眠模式 ，彻底释放*/ + rt_pm_release_all(in_mode[i%6]); i++; } - /*清除回调函数和私有数据*/ + + /*切换为无睡眠模式*/ + rt_pm_request(PM_SLEEP_MODE_NONE); + + /*清除回调函数和私有数据*/ rt_pm_notify_set(RT_NULL,RT_NULL); - rt_kprintf("thread pm_test close\n\r"); + + rt_kprintf("thread pm_test close\n\r"); + } /*按键唤醒的回调函数*/ @@ -181,3 +206,5 @@ static int pm_sample(int argc, char *argv[]) } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(pm_sample, pm sample); + +#endif diff --git a/bsp/essemi/es32f0654/drivers/bsp_driver_example/pwm_led_sample.c b/bsp/essemi/es32f0654/drivers/bsp_driver_example/pwm_led_sample.c index ce1573aa55..23ecfd227e 100644 --- a/bsp/essemi/es32f0654/drivers/bsp_driver_example/pwm_led_sample.c +++ b/bsp/essemi/es32f0654/drivers/bsp_driver_example/pwm_led_sample.c @@ -17,9 +17,12 @@ #include #include + +#ifdef RT_USING_PWM + #define LED_PIN_NUM 16 /* LED PIN脚编号，查看驱动文件drv_gpio.c确定 */ #define PWM_DEV_NAME "pwm1" /* PWM设备名称 */ -#define PWM_DEV_CHANNEL 4 /* PB9 PWM通道 */ +#define PWM_DEV_CHANNEL 1 /* PA8 PWM通道 */ struct rt_device_pwm *pwm_dev; /* PWM设备句柄 */ @@ -70,3 +73,6 @@ static int pwm_led_sample(int argc, char *argv[]) } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(pwm_led_sample, pwm sample); + +#endif + diff --git a/bsp/essemi/es32f0654/drivers/bsp_driver_example/rtc_sample.c b/bsp/essemi/es32f0654/drivers/bsp_driver_example/rtc_sample.c index 711a3a0ebb..6f732806f5 100644 --- a/bsp/essemi/es32f0654/drivers/bsp_driver_example/rtc_sample.c +++ b/bsp/essemi/es32f0654/drivers/bsp_driver_example/rtc_sample.c @@ -17,6 +17,8 @@ #include #include +#ifdef RT_USING_RTC + static int rtc_sample(int argc, char *argv[]) { rt_err_t ret = RT_EOK; @@ -49,3 +51,5 @@ static int rtc_sample(int argc, char *argv[]) } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(rtc_sample, rtc sample); + +#endif diff --git a/bsp/essemi/es32f0654/drivers/bsp_driver_example/spi_sample.c b/bsp/essemi/es32f0654/drivers/bsp_driver_example/spi_sample.c index 994888cdb0..6f6e730288 100644 --- a/bsp/essemi/es32f0654/drivers/bsp_driver_example/spi_sample.c +++ b/bsp/essemi/es32f0654/drivers/bsp_driver_example/spi_sample.c @@ -1,7 +1,19 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes @@ -17,13 +29,14 @@ #include #include +#ifdef RT_USING_SPI + #define SPI_DEVICE_NAME "spi00" #define BUF_LEN 16 static void spi_io_sample(int argc, char *argv[]) { struct rt_spi_device * spi_dev; /* spi设备的句柄 */ - struct rt_spi_configuration spi_config; rt_uint8_t i,buffer[BUF_LEN] = { 0U }; rt_err_t s_stat; rt_err_t result; @@ -37,23 +50,8 @@ static void spi_io_sample(int argc, char *argv[]) return; } - - /* 清空配置结构体 */ - rt_memset(&spi_config,0,sizeof(struct rt_spi_configuration)); - - spi_config.mode &= ~RT_SPI_SLAVE; /* 主机模式 */ - spi_config.mode &= ~RT_SPI_3WIRE; /* 4线，双向传输 */ - spi_config.mode |= RT_SPI_CPHA; /* 第二边沿采样 */ - spi_config.mode |= RT_SPI_CPOL; /* 空闲高电平 */ - spi_config.mode |= RT_SPI_NO_CS; /* 禁用软件从机选择管理 */ - spi_config.mode |= RT_SPI_MSB; /* 高位在前 */ - - spi_config.data_width = 8; /* 数据长度：8 */ - - spi_config.max_hz = 2000000; /* 最快时钟频率 */ - /* 配置SPI设备 */ - s_stat = rt_spi_configure(spi_dev,&spi_config); + s_stat = rt_spi_configure(spi_dev,&(spi_dev->config)); if(s_stat != RT_EOK) { @@ -150,3 +148,5 @@ static void spi_io_sample(int argc, char *argv[]) } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(spi_io_sample, spi sample); + +#endif diff --git a/bsp/essemi/es32f0654/drivers/drv_adc.c b/bsp/essemi/es32f0654/drivers/drv_adc.c index bc26b05802..bb1575c4a0 100644 --- a/bsp/essemi/es32f0654/drivers/drv_adc.c +++ b/bsp/essemi/es32f0654/drivers/drv_adc.c @@ -1,12 +1,25 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes * 2019-04-03 wangyq the first version * 2019-11-01 wangyq update libraries + * 2021-04-20 liuhy the second version */ #include @@ -59,77 +72,69 @@ static adc_channel_t es32f0_adc_get_channel(rt_uint32_t channel) { case 0: es32f0_channel = ADC_CHANNEL_0; - ald_gpio_init(GPIOC, GPIO_PIN_0, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH0_GPIO, ES_GPIO_ADC_CH0_PIN, &gpio_initstruct); break; case 1: es32f0_channel = ADC_CHANNEL_1; - ald_gpio_init(GPIOC, GPIO_PIN_1, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH1_GPIO, ES_GPIO_ADC_CH1_PIN, &gpio_initstruct); break; case 2: es32f0_channel = ADC_CHANNEL_2; - ald_gpio_init(GPIOC, GPIO_PIN_2, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH2_GPIO, ES_GPIO_ADC_CH2_PIN, &gpio_initstruct); break; case 3: es32f0_channel = ADC_CHANNEL_3; - ald_gpio_init(GPIOC, GPIO_PIN_3, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH3_GPIO, ES_GPIO_ADC_CH3_PIN, &gpio_initstruct); break; case 4: es32f0_channel = ADC_CHANNEL_4; - ald_gpio_init(GPIOA, GPIO_PIN_0, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH4_GPIO, ES_GPIO_ADC_CH4_PIN, &gpio_initstruct); break; case 5: es32f0_channel = ADC_CHANNEL_5; - ald_gpio_init(GPIOA, GPIO_PIN_1, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH5_GPIO, ES_GPIO_ADC_CH5_PIN, &gpio_initstruct); break; case 6: es32f0_channel = ADC_CHANNEL_6; - ald_gpio_init(GPIOA, GPIO_PIN_2, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH6_GPIO, ES_GPIO_ADC_CH6_PIN, &gpio_initstruct); break; case 7: es32f0_channel = ADC_CHANNEL_7; - ald_gpio_init(GPIOA, GPIO_PIN_3, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH7_GPIO, ES_GPIO_ADC_CH7_PIN, &gpio_initstruct); break; case 8: es32f0_channel = ADC_CHANNEL_8; - ald_gpio_init(GPIOA, GPIO_PIN_4, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH8_GPIO, ES_GPIO_ADC_CH8_PIN, &gpio_initstruct); break; case 9: es32f0_channel = ADC_CHANNEL_9; - ald_gpio_init(GPIOA, GPIO_PIN_5, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH9_GPIO, ES_GPIO_ADC_CH9_PIN, &gpio_initstruct); break; case 10: es32f0_channel = ADC_CHANNEL_10; - ald_gpio_init(GPIOA, GPIO_PIN_6, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH10_GPIO, ES_GPIO_ADC_CH10_PIN, &gpio_initstruct); break; case 11: es32f0_channel = ADC_CHANNEL_11; - ald_gpio_init(GPIOA, GPIO_PIN_7, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH11_GPIO, ES_GPIO_ADC_CH11_PIN, &gpio_initstruct); break; case 12: es32f0_channel = ADC_CHANNEL_12; - ald_gpio_init(GPIOC, GPIO_PIN_4, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH12_GPIO, ES_GPIO_ADC_CH12_PIN, &gpio_initstruct); break; case 13: es32f0_channel = ADC_CHANNEL_13; - ald_gpio_init(GPIOC, GPIO_PIN_5, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH13_GPIO, ES_GPIO_ADC_CH13_PIN, &gpio_initstruct); break; case 14: es32f0_channel = ADC_CHANNEL_14; - ald_gpio_init(GPIOB, GPIO_PIN_0, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH14_GPIO, ES_GPIO_ADC_CH14_PIN, &gpio_initstruct); break; case 15: es32f0_channel = ADC_CHANNEL_15; - ald_gpio_init(GPIOB, GPIO_PIN_1, &gpio_initstruct); - break; - case 16: - es32f0_channel = ADC_CHANNEL_16; - break; - case 17: - es32f0_channel = ADC_CHANNEL_17; - break; - case 18: - es32f0_channel = ADC_CHANNEL_18; + ald_gpio_init(ES_GPIO_ADC_CH15_GPIO, ES_GPIO_ADC_CH15_PIN, &gpio_initstruct); break; + default: break; } @@ -148,6 +153,9 @@ static rt_err_t es32f0_get_adc_value(struct rt_adc_device *device, rt_uint32_t c /* config adc channel */ nm_config.ch = es32f0_adc_get_channel(channel); nm_config.idx = ADC_NCH_IDX_1; + +/*aaabbbccc*/ + nm_config.samp = ES_ADC0_NCH_SAMPLETIME; nm_config.samp = ADC_SAMPLETIME_4; ald_adc_normal_channel_config(_hadc, &nm_config); @@ -168,24 +176,34 @@ static const struct rt_adc_ops es32f0_adc_ops = int rt_hw_adc_init(void) { int result = RT_EOK; + + adc_handle_t _h_adc; + + _h_adc.init.scan = DISABLE; + _h_adc.init.cont = DISABLE; + _h_adc.init.disc = ADC_ALL_DISABLE; + _h_adc.init.disc_nr = ADC_DISC_NR_1; + _h_adc.init.nche_sel = ADC_NCHESEL_MODE_ALL; + _h_adc.init.n_ref = ADC_NEG_REF_VSS; + _h_adc.init.p_ref = ADC_POS_REF_VDD; + _h_adc.init.nch_nr = ADC_NCH_NR_16; + +#ifdef BSP_USING_ADC0 + static adc_handle_t _h_adc0; - - /* adc function initialization */ + + _h_adc0.init = _h_adc.init; + _h_adc0.perh = ADC0; - _h_adc0.init.align = ADC_DATAALIGN_RIGHT; - _h_adc0.init.scan = DISABLE; - _h_adc0.init.cont = DISABLE; - _h_adc0.init.disc = ADC_ALL_DISABLE; - _h_adc0.init.disc_nr = ADC_DISC_NR_1; - _h_adc0.init.data_bit = ADC_CONV_BIT_12; - _h_adc0.init.div = ADC_CKDIV_128; - _h_adc0.init.nche_sel = ADC_NCHESEL_MODE_ALL; - _h_adc0.init.n_ref = ADC_NEG_REF_VSS; - _h_adc0.init.p_ref = ADC_POS_REF_VDD; + _h_adc0.init.align = ES_ADC0_ALIGN; + _h_adc0.init.data_bit = ES_ADC0_DATA_BIT; + _h_adc0.init.div = ES_ADC0_CLK_DIV; ald_adc_init(&_h_adc0); - - rt_hw_adc_register(&_device_adc0, "adc0", &es32f0_adc_ops, &_h_adc0); - + + result = rt_hw_adc_register(&_device_adc0, ES_DEVICE_NAME_ADC0, &es32f0_adc_ops, &_h_adc0); + +#endif /*BSP_USING_ADC0*/ + return result; } INIT_BOARD_EXPORT(rt_hw_adc_init); diff --git a/bsp/essemi/es32f0654/drivers/drv_adc.h b/bsp/essemi/es32f0654/drivers/drv_adc.h index eaddd67407..fa51cdbb21 100644 --- a/bsp/essemi/es32f0654/drivers/drv_adc.h +++ b/bsp/essemi/es32f0654/drivers/drv_adc.h @@ -3,14 +3,29 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes * 2019-04-03 wangyq the first version + * 2021-04-20 liuhy the second version */ #ifndef DRV_ADC_H__ #define DRV_ADC_H__ +#include "es_conf_info_adc.h" + int rt_hw_adc_init(void); #endif diff --git a/bsp/essemi/es32f0654/drivers/drv_can.c b/bsp/essemi/es32f0654/drivers/drv_can.c index cefddd997c..7c73acd0cf 100644 --- a/bsp/essemi/es32f0654/drivers/drv_can.c +++ b/bsp/essemi/es32f0654/drivers/drv_can.c @@ -1,51 +1,94 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes - * 2019-11-09 wangyq the first version + * 2019-11-09 wangyq the first version + * 2021-04-20 liuhy the second version */ #include "drv_can.h" -#ifdef BSP_USING_CAN +#ifdef RT_USING_CAN + static struct es32f0_can can; -/* attention !!! baud calculation example: Pclk / ((sjw + seg1 + seg2) * psc) 48 / ((1 + 3 + 2) * 8) = 1MHz */ -static const struct es32f0_baud_rate_tab can_baud_rate_tab[] = -{ - {CAN1MBaud, 8}, - {CAN800kBaud, 10}, - {CAN500kBaud, 16}, - {CAN250kBaud, 32}, - {CAN125kBaud, 64}, - {CAN100kBaud, 80}, - {CAN50kBaud, 160}, - {CAN20kBaud, 400}, - {CAN10kBaud, 800} -}; -static rt_uint32_t get_can_baud_index(rt_uint32_t baud) -{ - rt_uint32_t len, index; - - len = sizeof(can_baud_rate_tab) / sizeof(can_baud_rate_tab[0]); - for (index = 0; index < len; index++) +static rt_uint32_t get_can_baud_index(rt_uint32_t baud,can_init_t * init) +{ +/* attention !!! baud calculation example: Pclk / ((1 + seg1 + seg2) * psc) Pclk=48 / ((1 + seg1=3 + seg2=2) * 8) = 1MHz */ + double target,temp,min; + uint32_t i,j,j_max,near = 0; + target = (double)(ald_cmu_get_pclk1_clock()); + target/= baud; /*1*/ + + min = 0xFFFFFFFF; + + for(i = 1 + 16 + 8 ;i > 2;i--) /*SYNC_SEG + SEG1 + SEG2*/ { - if (can_baud_rate_tab[index].baud_rate == baud) - return index; + j_max = target/i/(0.98) + 1; /*СΧ*/ + j_max = (j_max > 1024) ? (1024) : (j_max); + + for(j = target/i/1.02 ;j < j_max;j++) + { + temp = target/i/j; /*2*/ + temp = (temp > 1) ? (temp - 1) : (1 - temp); + temp+= ((1.0 * i * j) / 0xFFFFFFFF) ; + + if(temp < min) + { + if(temp > 0.000001) + { + near = (i<<16) + j; + min = temp; + } + else + { + init->seg1 = (can_seg1_t)((i - 1)*2/3-1); + init->seg2 = (can_seg2_t)(i - init->seg1 - 1 - 1 - 1); + init->psc = j; + + return 0; + } + } + } } - return 0; /* default baud is CAN1MBaud */ + if(min < 0.01) + { + i = near>>16; + j = near % (1<<16); + init->seg1 = (can_seg1_t)((i - 1)*2/3-1); + init->seg2 = (can_seg2_t)(i - init->seg1 - 1 - 1 - 1); + init->psc = j; + + return 0; + } + else + { + return 1; + } } + static rt_err_t _can_config(struct rt_can_device *can_device, struct can_configure *cfg) { struct es32f0_can *drv_can; - rt_uint32_t baud_index; RT_ASSERT(can_device); RT_ASSERT(cfg); @@ -56,7 +99,7 @@ static rt_err_t _can_config(struct rt_can_device *can_device, struct can_configu drv_can->CanHandle.init.ttcm = DISABLE; drv_can->CanHandle.init.abom = ENABLE; drv_can->CanHandle.init.awk = DISABLE; - drv_can->CanHandle.init.artx = DISABLE; + drv_can->CanHandle.init.artx = (type_func_t)ES_CAN0_AUTO_BAN_RE_T; drv_can->CanHandle.init.rfom = DISABLE; drv_can->CanHandle.init.txmp = ENABLE; @@ -75,12 +118,20 @@ static rt_err_t _can_config(struct rt_can_device *can_device, struct can_configu drv_can->CanHandle.init.mode = CAN_MODE_SILENT_LOOPBACK; break; } + /*ò*/ + if(get_can_baud_index(cfg->baud_rate,&(drv_can->CanHandle.init))) + { + return -RT_ERROR; + } + drv_can->CanHandle.init.sjw = (can_sjw_t)(cfg->reserved); + + /* init can */ - baud_index = get_can_baud_index(cfg->baud_rate); - drv_can->CanHandle.init.sjw = CAN_SJW_1; - drv_can->CanHandle.init.seg1 = CAN_SEG1_3; - drv_can->CanHandle.init.seg2 = CAN_SEG2_2; - drv_can->CanHandle.init.psc = can_baud_rate_tab[baud_index].config_data; + // baud_index = get_can_baud_index(cfg->baud_rate); + //drv_can->CanHandle.init.sjw = CAN_SJW_1; + // drv_can->CanHandle.init.seg1 = CAN_SEG1_3; + // drv_can->CanHandle.init.seg2 = CAN_SEG2_2; + // drv_can->CanHandle.init.psc = can_baud_rate_tab[baud_index].config_data; /* init can */ if (ald_can_init(&drv_can->CanHandle) != OK) { @@ -96,7 +147,10 @@ static rt_err_t _can_control(struct rt_can_device *can_device, int cmd, void *ar { rt_uint32_t argval; struct es32f0_can *drv_can; + +#ifdef RT_CAN_USING_HDR struct rt_can_filter_config *filter_cfg; +#endif RT_ASSERT(can_device != RT_NULL); drv_can = (struct es32f0_can *)can_device->parent.user_data; @@ -108,8 +162,12 @@ static rt_err_t _can_control(struct rt_can_device *can_device, int cmd, void *ar argval = (rt_uint32_t) arg; if (argval == RT_DEVICE_FLAG_INT_RX) { - ald_can_interrupt_config(&drv_can->CanHandle, (can_it_t)(CAN_IT_FP0 | CAN_IT_FF0 | CAN_IT_FOV0 | - CAN_IT_FP1 | CAN_IT_FF1 | CAN_IT_FOV1), DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FP0, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FF0, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FOV0, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FP1, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FF1, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FOV1, DISABLE); } else if (argval == RT_DEVICE_FLAG_INT_TX) { @@ -117,8 +175,11 @@ static rt_err_t _can_control(struct rt_can_device *can_device, int cmd, void *ar } else if (argval == RT_DEVICE_CAN_INT_ERR) { - ald_can_interrupt_config(&drv_can->CanHandle, (can_it_t)(CAN_IT_WARN | CAN_IT_PERR | CAN_IT_BOF | - CAN_IT_PRERR | CAN_IT_ERR), DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_WARN, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_PERR, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_BOF, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_PRERR, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_ERR, DISABLE); } break; case RT_DEVICE_CTRL_SET_INT: @@ -127,8 +188,14 @@ static rt_err_t _can_control(struct rt_can_device *can_device, int cmd, void *ar { NVIC_SetPriority(CAN0_IRQn, 1); NVIC_EnableIRQ(CAN0_IRQn); - - ald_can_interrupt_config(&drv_can->CanHandle, (can_it_t)(CAN_IT_FP0 | CAN_IT_FP1), ENABLE); + + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FP0, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FF0, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FOV0, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FP1, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FF1, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FOV1, ENABLE); + } else if (argval == RT_DEVICE_FLAG_INT_TX) { @@ -141,11 +208,16 @@ static rt_err_t _can_control(struct rt_can_device *can_device, int cmd, void *ar { NVIC_SetPriority(CAN0_IRQn, 1); NVIC_EnableIRQ(CAN0_IRQn); - - ald_can_interrupt_config(&drv_can->CanHandle, (can_it_t)(CAN_IT_WARN | CAN_IT_PERR | CAN_IT_BOF | - CAN_IT_PRERR | CAN_IT_ERR), ENABLE); + + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_WARN, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_PERR, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_BOF, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_PRERR, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_ERR, ENABLE); + } break; +#ifdef RT_CAN_USING_HDR case RT_CAN_CMD_SET_FILTER: if (RT_NULL == arg) { @@ -157,8 +229,55 @@ static rt_err_t _can_control(struct rt_can_device *can_device, int cmd, void *ar filter_cfg = (struct rt_can_filter_config *)arg; /* get default filter */ for (int i = 0; i < filter_cfg->count; i++) - { - drv_can->FilterConfig.number = filter_cfg->items[i].hdr; + { + + /*ĬϹ˱ж*/ + if(filter_cfg->items[i].hdr < drv_can->device.config.maxhdr) + drv_can->FilterConfig.number = filter_cfg->items[i].hdr; + else + drv_can->FilterConfig.number = ES_C_CAN_DEFAULT_FILTER_NUMBER; + + if(filter_cfg->items[i].mode) + { + /*ʶбģʽ ƥ idƥΪյid = õid + = õmask ͨ*/ + /*չ֡*/ + if(filter_cfg->items[i].ide) + { +// filter_cfg->items[i].id = filter_cfg->items[i].id ; /*id 29 λ*/ + filter_cfg->items[i].mask = ((filter_cfg->items[i].mask << 3) | + (filter_cfg->items[i].ide << 2) | + (filter_cfg->items[i].rtr << 1)); + } + else /*׼֡*/ + { + filter_cfg->items[i].id = (filter_cfg->items[i].id << 18); + filter_cfg->items[i].mask = ((filter_cfg->items[i].mask << 21) | + (filter_cfg->items[i].ide << 2) | + (filter_cfg->items[i].rtr << 1)); + } + } + else + { + /*ʶģʽ*/ + /*չ֡*/ + if(filter_cfg->items[i].ide) + { + filter_cfg->items[i].mask = (filter_cfg->items[i].mask)<<3; + } + else /*׼֡*/ + { + filter_cfg->items[i].id = (filter_cfg->items[i].id)<<18; + filter_cfg->items[i].mask = (filter_cfg->items[i].mask)<<21; + } + +#if ES_C_CAN_FILTER_FRAME_TYPE + /*ƥ*/ + filter_cfg->items[i].mask |= 0x6; +#endif + + } + drv_can->FilterConfig.id_high = (filter_cfg->items[i].id >> 13) & 0xFFFF; drv_can->FilterConfig.id_low = ((filter_cfg->items[i].id << 3) | (filter_cfg->items[i].ide << 2) | @@ -171,6 +290,8 @@ static rt_err_t _can_control(struct rt_can_device *can_device, int cmd, void *ar } } break; + +#endif case RT_CAN_CMD_SET_MODE: argval = (rt_uint32_t) arg; if (argval != RT_CAN_MODE_NORMAL && @@ -188,18 +309,7 @@ static rt_err_t _can_control(struct rt_can_device *can_device, int cmd, void *ar break; case RT_CAN_CMD_SET_BAUD: argval = (rt_uint32_t) arg; - if (argval != CAN1MBaud && - argval != CAN800kBaud && - argval != CAN500kBaud && - argval != CAN250kBaud && - argval != CAN125kBaud && - argval != CAN100kBaud && - argval != CAN50kBaud && - argval != CAN20kBaud && - argval != CAN10kBaud) - { - return -RT_ERROR; - } + if (argval != drv_can->device.config.baud_rate) { drv_can->device.config.baud_rate = argval; @@ -423,8 +533,11 @@ static void _can_rx_isr(struct rt_can_device *can, rt_uint32_t fifo) /* RX interrupt */ else { + if(CAN_RX_MSG_PENDING(h_can, CAN_RX_FIFO0) != 0) + { /* save to user list */ rt_hw_can_isr(can, RT_CAN_EVENT_RX_IND | fifo << 8); + } /* Clear FIFO0 rx Flag */ SET_BIT(h_can->perh->RXF0, CAN_RXF0_FREE_MSK); @@ -441,8 +554,11 @@ static void _can_rx_isr(struct rt_can_device *can, rt_uint32_t fifo) /* RX interrupt */ else { + if(CAN_RX_MSG_PENDING(h_can, CAN_RX_FIFO1) != 0) + { /* save to user list */ rt_hw_can_isr(can, RT_CAN_EVENT_RX_IND | fifo << 8); + } /* Clear FIFO0 rx Flag */ SET_BIT(h_can->perh->RXF1, CAN_RXF1_FREE_MSK); @@ -549,20 +665,12 @@ void CAN0_Handler(void) can.device.status.errcode = errtype & 0x07; h_can->perh->IFC |= CAN_IFC_ERRIFC_MSK; } - rt_interrupt_leave(); } int rt_hw_can_init(void) { gpio_init_t h_gpio; - struct can_configure config = CANDEFAULTCONFIG; - - config.privmode = RT_CAN_MODE_NOPRIV; - config.ticks = 50; -#ifdef RT_CAN_USING_HDR - config.maxhdr = 14; -#endif /* Initialize can common pin */ h_gpio.odos = GPIO_PUSH_PULL; @@ -570,15 +678,22 @@ int rt_hw_can_init(void) h_gpio.odrv = GPIO_OUT_DRIVE_NORMAL; h_gpio.flt = GPIO_FILTER_DISABLE; h_gpio.type = GPIO_TYPE_TTL; - h_gpio.func = GPIO_FUNC_4; +#if defined(ES_CAN0_RX_GPIO_FUNC)&&defined(ES_CAN0_RX_GPIO_PORT)&&defined(ES_CAN0_RX_GPIO_PIN) /* Initialize can rx pin */ - h_gpio.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOA, GPIO_PIN_11, &h_gpio); - + h_gpio.mode = GPIO_MODE_INPUT; + h_gpio.func = ES_CAN0_RX_GPIO_FUNC; + ald_gpio_init(ES_CAN0_RX_GPIO_PORT, ES_CAN0_RX_GPIO_PIN, &h_gpio); +#endif + + +#if defined(ES_CAN0_TX_GPIO_FUNC)&&defined(ES_CAN0_TX_GPIO_PORT)&&defined(ES_CAN0_TX_GPIO_PIN) /* Initialize can tx pin */ - h_gpio.mode = GPIO_MODE_OUTPUT; - ald_gpio_init(GPIOA, GPIO_PIN_12, &h_gpio); + h_gpio.mode = GPIO_MODE_OUTPUT; + h_gpio.func = ES_CAN0_TX_GPIO_FUNC; + ald_gpio_init(ES_CAN0_TX_GPIO_PORT, ES_CAN0_TX_GPIO_PIN, &h_gpio); +#endif + /* config default filter */ can_filter_t filter = {0}; @@ -587,15 +702,21 @@ int rt_hw_can_init(void) filter.mask_id_high = 0x0000; filter.mask_id_low = 0x0000; filter.fifo = CAN_FILTER_FIFO0; - filter.number = 0; + filter.number = ES_C_CAN_DEFAULT_FILTER_NUMBER; filter.mode = CAN_FILTER_MODE_MASK; filter.scale = CAN_FILTER_SCALE_32; filter.active = ENABLE; can.FilterConfig = filter; - can.device.config = config; + can.device.config = (struct can_configure)ES_CAN0_CONFIG; +#ifdef RT_CAN_USING_HDR + can.device.config.maxhdr = 14; +#endif + can.device.config.privmode = RT_CAN_MODE_NOPRIV; + can.device.config.ticks = 50; + can.device.config.reserved = ES_CAN0_SJW; /* register CAN1 device */ - rt_hw_can_register(&can.device, "can", &_can_ops, &can); + rt_hw_can_register(&can.device, ES_DEVICE_NAME_CAN0, &_can_ops, &can); return 0; } diff --git a/bsp/essemi/es32f0654/drivers/drv_can.h b/bsp/essemi/es32f0654/drivers/drv_can.h index 798a3a8653..c89f2bb2ae 100644 --- a/bsp/essemi/es32f0654/drivers/drv_can.h +++ b/bsp/essemi/es32f0654/drivers/drv_can.h @@ -3,9 +3,22 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes - * 2019-11-09 wangyq the first version + * 2019-11-09 wangyq the first version + * 2021-04-20 liuhy the second version */ #ifndef DRV_CAN_H__ @@ -14,16 +27,9 @@ #include #include #include +#include "es_conf_info_can.h" -#include -#include - -struct es32f0_baud_rate_tab -{ - rt_uint32_t baud_rate; - rt_uint32_t config_data; -}; - +#ifdef RT_USING_CAN /* es32f0 can device */ struct es32f0_can { @@ -34,4 +40,5 @@ struct es32f0_can int rt_hw_can_init(void); +#endif #endif /*DRV_CAN_H__ */ diff --git a/bsp/essemi/es32f0654/drivers/drv_gpio.c b/bsp/essemi/es32f0654/drivers/drv_gpio.c index 142fcce7fc..00050866e5 100644 --- a/bsp/essemi/es32f0654/drivers/drv_gpio.c +++ b/bsp/essemi/es32f0654/drivers/drv_gpio.c @@ -1,103 +1,34 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes * 2019-01-23 wangyq the first version - * 2019-11-01 wangyq update libraries + * 2019-11-01 wangyq update libraries + * 2021-04-20 liuhy the second version */ -#include -#include #include "board.h" #include "drv_gpio.h" -#include -#include + +/*管脚映射在 es_conf_info_map.h 的 pins[] 中*/ #ifdef RT_USING_PIN -#define __ES32F0_PIN(index, gpio, gpio_index) {index, GPIO##gpio, GPIO_PIN_##gpio_index} -#define __ES32F0_PIN_DEFAULT {-1, 0, 0} - -/* ES32F0 GPIO driver */ -struct pin_index -{ - int index; - GPIO_TypeDef *gpio; - uint32_t pin; -}; - -static const struct pin_index pins[] = -{ - __ES32F0_PIN_DEFAULT, - __ES32F0_PIN_DEFAULT, - __ES32F0_PIN(2, C, 13), - __ES32F0_PIN(3, C, 14), - __ES32F0_PIN(4, C, 15), - __ES32F0_PIN(5, H, 0), - __ES32F0_PIN(6, H, 1), - __ES32F0_PIN_DEFAULT, - __ES32F0_PIN(8, C, 0), - __ES32F0_PIN(9, C, 1), - __ES32F0_PIN(10, C, 2), - __ES32F0_PIN(11, C, 3), - __ES32F0_PIN(12, H, 3), - __ES32F0_PIN(13, H, 4), - __ES32F0_PIN(14, A, 0), - __ES32F0_PIN(15, A, 1), - __ES32F0_PIN(16, A, 2), - __ES32F0_PIN(17, A, 3), - __ES32F0_PIN(18, F, 0), - __ES32F0_PIN(19, F, 1), - __ES32F0_PIN(20, A, 4), - __ES32F0_PIN(21, A, 5), - __ES32F0_PIN(22, A, 6), - __ES32F0_PIN(23, A, 7), - __ES32F0_PIN(24, C, 4), - __ES32F0_PIN(25, C, 5), - __ES32F0_PIN(26, B, 0), - __ES32F0_PIN(27, B, 1), - __ES32F0_PIN(28, B, 2), - __ES32F0_PIN(29, B, 10), - __ES32F0_PIN(30, B, 11), - __ES32F0_PIN_DEFAULT, - __ES32F0_PIN_DEFAULT, - __ES32F0_PIN(33, B, 12), - __ES32F0_PIN(34, B, 13), - __ES32F0_PIN(35, B, 14), - __ES32F0_PIN(36, B, 15), - __ES32F0_PIN(37, C, 6), - __ES32F0_PIN(38, C, 7), - __ES32F0_PIN(39, C, 8), - __ES32F0_PIN(40, C, 9), - __ES32F0_PIN(41, A, 8), - __ES32F0_PIN(42, A, 9), - __ES32F0_PIN(43, A, 10), - __ES32F0_PIN(44, A, 11), - __ES32F0_PIN(45, A, 12), - __ES32F0_PIN(46, A, 13), - __ES32F0_PIN_DEFAULT, - __ES32F0_PIN_DEFAULT, - __ES32F0_PIN(49, A, 14), - __ES32F0_PIN(50, A, 15), - __ES32F0_PIN(51, C, 10), - __ES32F0_PIN(52, C, 11), - __ES32F0_PIN(53, C, 12), - __ES32F0_PIN(54, D, 2), - __ES32F0_PIN(55, B, 3), - __ES32F0_PIN(56, B, 4), - __ES32F0_PIN(57, B, 5), - __ES32F0_PIN(58, B, 6), - __ES32F0_PIN(59, B, 7), - __ES32F0_PIN(60, H, 2), - __ES32F0_PIN(61, B, 8), - __ES32F0_PIN(62, B, 9), - __ES32F0_PIN_DEFAULT, - __ES32F0_PIN_DEFAULT, -}; - struct pin_irq_map { rt_uint16_t pinbit; @@ -143,6 +74,150 @@ struct rt_pin_irq_hdr pin_irq_hdr_tab[] = { -1, 0, RT_NULL, RT_NULL}, }; +#ifdef ES_CONF_EXTI_IRQ_0 + +RT_WEAK void irq_pin0_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 0\r\n"); +} +#endif + +#ifdef ES_CONF_EXTI_IRQ_1 + +RT_WEAK void irq_pin1_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 1\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_2 + + RT_WEAK void irq_pin2_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 2\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_3 + +RT_WEAK void irq_pin3_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 3\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_4 + +RT_WEAK void irq_pin4_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 4\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_5 + +RT_WEAK void irq_pin5_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 5\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_6 + +RT_WEAK void irq_pin6_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 6\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_7 + +RT_WEAK void irq_pin7_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 7\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_8 + +RT_WEAK void irq_pin8_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 8\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_9 + +RT_WEAK void irq_pin9_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 9\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_10 + +RT_WEAK void irq_pin10_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 10\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_11 + +RT_WEAK void irq_pin11_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 11\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_12 + +RT_WEAK void irq_pin12_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 12\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_13 + +RT_WEAK void irq_pin13_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 13\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_14 + +RT_WEAK void irq_pin14_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 14\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_15 + +RT_WEAK void irq_pin15_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 15\r\n"); +} + +#endif + + #define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) const struct pin_index *get_pin(uint8_t pin) { @@ -408,18 +483,9 @@ const static struct rt_pin_ops _es32f0_pin_ops = es32f0_pin_attach_irq, es32f0_pin_detach_irq, es32f0_pin_irq_enable, - RT_NULL, + /*RT_NULL,*/ }; -int rt_hw_pin_init(void) -{ - int result; - ald_cmu_perh_clock_config(CMU_PERH_GPIO, ENABLE); - result = rt_device_pin_register("pin", &_es32f0_pin_ops, RT_NULL); - return result; -} -INIT_BOARD_EXPORT(rt_hw_pin_init); - rt_inline void pin_irq_hdr(uint16_t GPIO_Pin) { uint16_t irqno; @@ -488,4 +554,44 @@ void EXTI12_15_Handler(void) rt_interrupt_leave(); } +int rt_hw_pin_init(void) +{ + int result; + + +#ifdef ES_INIT_GPIOS + + rt_size_t i,gpio_conf_num = sizeof(gpio_conf_all) / sizeof(gpio_conf_t); + +#endif + + ald_cmu_perh_clock_config(CMU_PERH_GPIO, ENABLE); + + result = rt_device_pin_register(ES_DEVICE_NAME_PIN, &_es32f0_pin_ops, RT_NULL); + + if(result != RT_EOK)return result; + +#ifdef ES_INIT_GPIOS + + for(i = 0;i < gpio_conf_num;i++) + { + rt_pin_mode( gpio_conf_all[i].pin,gpio_conf_all[i].pin_mode); + + if((gpio_conf_all[i].pin_mode == ES_C_GPIO_MODE_OUTPUT)||(gpio_conf_all[i].pin_mode == ES_C_GPIO_MODE_OUTPUT_OD)) + rt_pin_write(gpio_conf_all[i].pin,gpio_conf_all[i].pin_level); + + if(!gpio_conf_all[i].irq_en)continue; + + rt_pin_attach_irq(gpio_conf_all[i].pin, gpio_conf_all[i].irq_mode, gpio_conf_all[i].callback, RT_NULL); + rt_pin_irq_enable(gpio_conf_all[i].pin, gpio_conf_all[i].irq_en); + } + +#endif + + + + return result; +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + #endif diff --git a/bsp/essemi/es32f0654/drivers/drv_gpio.h b/bsp/essemi/es32f0654/drivers/drv_gpio.h index 3032af51ba..b0b68714d3 100644 --- a/bsp/essemi/es32f0654/drivers/drv_gpio.h +++ b/bsp/essemi/es32f0654/drivers/drv_gpio.h @@ -3,14 +3,29 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes * 2019-01-23 wangyq the first version + * 2021-04-20 liuhy the second version */ #ifndef DRV_GPIO_H__ #define DRV_GPIO_H__ +#include "es_conf_info_gpio.h" + int rt_hw_pin_init(void); #endif diff --git a/bsp/essemi/es32f0654/drivers/drv_hwtimer.c b/bsp/essemi/es32f0654/drivers/drv_hwtimer.c index 4d7614a323..83d3d9c87a 100644 --- a/bsp/essemi/es32f0654/drivers/drv_hwtimer.c +++ b/bsp/essemi/es32f0654/drivers/drv_hwtimer.c @@ -1,21 +1,33 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes * 2019-3-19 wangyq the first version * 2019-11-01 wangyq update libraries + * 2021-04-20 liuhy the second version */ #include #include #include #include -#include -#include -#include +#include + #ifdef RT_USING_HWTIMER @@ -26,93 +38,172 @@ struct es32f0_hwtimer_dev IRQn_Type IRQn; }; -#ifdef BSP_USING_HWTIMER0 -static struct es32f0_hwtimer_dev hwtimer0; +#ifdef BSP_USING_AD16C4T0_HWTIMER +static struct es32f0_hwtimer_dev ad16c4t0_hwtimer; + +static struct rt_hwtimer_info ad16c4t0_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_AD16C4T0_HWTIMER_MODE +}; + +void AD16C4T0_BRK_UP_TRIG_COM_Handler(void) +{ + ald_timer_clear_flag_status(ad16c4t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&ad16c4t0_hwtimer.parent); +} + +#endif + +#ifdef BSP_USING_GP16C4T0_HWTIMER + +static struct es32f0_hwtimer_dev gp16c4t0_hwtimer; + +static struct rt_hwtimer_info gp16c4t0_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_GP16C4T0_HWTIMER_MODE +}; + +void GP16C4T0_LCD_Handler(void) +{ + ald_timer_clear_flag_status(gp16c4t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&gp16c4t0_hwtimer.parent); +} + +#endif + +#ifdef BSP_USING_GP16C2T0_HWTIMER + +static struct es32f0_hwtimer_dev gp16c2t0_hwtimer; + +static struct rt_hwtimer_info gp16c2t0_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_GP16C2T0_HWTIMER_MODE +}; + +void GP16C2T0_Handler(void) +{ + ald_timer_clear_flag_status(gp16c2t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&gp16c2t0_hwtimer.parent); +} + +#endif + +#ifdef BSP_USING_GP16C2T1_HWTIMER + +static struct es32f0_hwtimer_dev gp16c2t1_hwtimer; + +static struct rt_hwtimer_info gp16c2t1_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_GP16C2T1_HWTIMER_MODE +}; + +void GP16C2T1_Handler(void) +{ + ald_timer_clear_flag_status(gp16c2t1_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&gp16c2t1_hwtimer.parent); +} + +#endif + +#ifdef BSP_USING_BS16T0_HWTIMER + +static struct es32f0_hwtimer_dev bs16t0_hwtimer; + +static struct rt_hwtimer_info bs16t0_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_BS16T0_HWTIMER_MODE +}; void BS16T0_Handler(void) { - ald_timer_clear_flag_status(hwtimer0.hwtimer_periph, TIMER_FLAG_UPDATE); - rt_device_hwtimer_isr(&hwtimer0.parent); - - if (HWTIMER_MODE_ONESHOT == hwtimer0.parent.mode) - { - ald_timer_base_stop(hwtimer0.hwtimer_periph); - } + ald_timer_clear_flag_status(bs16t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&bs16t0_hwtimer.parent); } + #endif -#ifdef BSP_USING_HWTIMER1 -static struct es32f0_hwtimer_dev hwtimer1; -/* can not use when UART2 Handler is enabled */ +#ifdef BSP_USING_BS16T1_HWTIMER + +static struct es32f0_hwtimer_dev bs16t1_hwtimer; + +static struct rt_hwtimer_info bs16t1_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_BS16T1_HWTIMER_MODE +}; + void BS16T1_UART2_Handler(void) { - /* if BS16T1 it */ - if (ald_timer_get_it_status(hwtimer1.hwtimer_periph, TIMER_IT_UPDATE) && - ald_timer_get_flag_status(hwtimer1.hwtimer_periph, TIMER_FLAG_UPDATE)) - { - ald_timer_clear_flag_status(hwtimer1.hwtimer_periph, TIMER_FLAG_UPDATE); - rt_device_hwtimer_isr(&hwtimer1.parent); - - if (HWTIMER_MODE_ONESHOT == hwtimer1.parent.mode) - { - ald_timer_base_stop(hwtimer1.hwtimer_periph); - } - } + ald_timer_clear_flag_status(bs16t1_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&bs16t1_hwtimer.parent); } + #endif -#ifdef BSP_USING_HWTIMER2 -static struct es32f0_hwtimer_dev hwtimer2; -/* can not use when UART3 Handler is enabled */ +#ifdef BSP_USING_BS16T2_HWTIMER + +static struct es32f0_hwtimer_dev bs16t2_hwtimer; + +static struct rt_hwtimer_info bs16t2_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_BS16T2_HWTIMER_MODE +}; + void BS16T2_UART3_Handler(void) { - /* if BS16T2 it */ - if (ald_timer_get_it_status(hwtimer2.hwtimer_periph, TIMER_IT_UPDATE) && - ald_timer_get_flag_status(hwtimer2.hwtimer_periph, TIMER_FLAG_UPDATE)) - { - ald_timer_clear_flag_status(hwtimer2.hwtimer_periph, TIMER_FLAG_UPDATE); - rt_device_hwtimer_isr(&hwtimer2.parent); - - if (HWTIMER_MODE_ONESHOT == hwtimer2.parent.mode) - { - ald_timer_base_stop(hwtimer2.hwtimer_periph); - } - } + ald_timer_clear_flag_status(bs16t2_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&bs16t2_hwtimer.parent); } + #endif -#ifdef BSP_USING_HWTIMER3 -static struct es32f0_hwtimer_dev hwtimer3; -/* can not use when DAC0 Handler is enabled */ +#ifdef BSP_USING_BS16T3_HWTIMER + +static struct es32f0_hwtimer_dev bs16t3_hwtimer; + +static struct rt_hwtimer_info bs16t3_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_BS16T3_HWTIMER_MODE +}; + void BS16T3_DAC0_Handler(void) { - /* if BS16T3 it */ - if (ald_timer_get_it_status(hwtimer3.hwtimer_periph, TIMER_IT_UPDATE) && - ald_timer_get_flag_status(hwtimer3.hwtimer_periph, TIMER_FLAG_UPDATE)) - { - ald_timer_clear_flag_status(hwtimer3.hwtimer_periph, TIMER_FLAG_UPDATE); - rt_device_hwtimer_isr(&hwtimer3.parent); - - if (HWTIMER_MODE_ONESHOT == hwtimer3.parent.mode) - { - ald_timer_base_stop(hwtimer3.hwtimer_periph); - } - } + ald_timer_clear_flag_status(bs16t3_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&bs16t3_hwtimer.parent); } -#endif -static struct rt_hwtimer_info es32f0_hwtimer_info = -{ - 48000000, /* maximum count frequency */ - 1, /* minimum count frequency */ - 65535, /* counter maximum value */ - HWTIMER_CNTMODE_UP -}; +#endif static void es32f0_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) { struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data; + struct rt_hwtimer_info *hwtimer_info = (struct rt_hwtimer_info *)timer->info; + + RT_ASSERT(hwtimer != RT_NULL); if (1 == state) @@ -121,9 +212,10 @@ static void es32f0_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) ald_timer_interrupt_config(hwtimer->hwtimer_periph, TIMER_IT_UPDATE, ENABLE); NVIC_EnableIRQ(hwtimer->IRQn); } - hwtimer->parent.freq = ald_cmu_get_pclk1_clock(); - es32f0_hwtimer_info.maxfreq = ald_cmu_get_pclk1_clock(); - es32f0_hwtimer_info.minfreq = ald_cmu_get_pclk1_clock(); + + hwtimer->parent.freq = ald_cmu_get_pclk1_clock()/((hwtimer->hwtimer_periph->perh->PRES & 0xFFFF)+1); + hwtimer_info->maxfreq = hwtimer->parent.freq; + hwtimer_info->minfreq = (hwtimer->parent.freq)/0xFFFF; } static rt_err_t es32f0_hwtimer_start(rt_hwtimer_t *timer, @@ -175,10 +267,37 @@ static rt_err_t es32f0_hwtimer_control(rt_hwtimer_t *timer, { case HWTIMER_CTRL_FREQ_SET: freq = *(rt_uint32_t *)args; - if (freq != ald_cmu_get_pclk1_clock()) - { - ret = -RT_ERROR; + + ret = -RT_ERROR; + + if(freq) + { + double temp,target; + temp = (double)ald_cmu_get_pclk1_clock(); + target = temp/freq; + + if(target < 0x10001) /*Ƶ = max(PRES)+1*/ + { + temp = target - (int)(target); + + if((temp > 0.998)&&(target < 0x10000)) + { + hwtimer->hwtimer_periph->perh->PRES = (uint32_t)target; + ret = RT_EOK; + } + if((temp < 0.002)&&(target >= 0x1)) + { + hwtimer->hwtimer_periph->perh->PRES = (uint32_t)target - 1; + ret = RT_EOK; + } + + } + + if(ret == RT_EOK) /*Ϣ*/ + hwtimer->parent.freq = ald_cmu_get_pclk1_clock()/((hwtimer->hwtimer_periph->perh->PRES & 0xFFFF)+1); + } + break; case HWTIMER_CTRL_STOP: @@ -206,46 +325,127 @@ int rt_hw_hwtimer_init(void) { rt_err_t ret = RT_EOK; -#ifdef BSP_USING_HWTIMER0 - static timer_handle_t _hwtimer_periph0; - _hwtimer_periph0.perh = BS16T0; - hwtimer0.IRQn = BS16T0_IRQn; - hwtimer0.hwtimer_periph = &_hwtimer_periph0; - hwtimer0.parent.info = &es32f0_hwtimer_info; - hwtimer0.parent.ops = &es32f0_hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer0.parent, "timer0", &hwtimer0); +#ifdef BSP_USING_AD16C4T0_HWTIMER + static timer_handle_t ad16c4t0_hwtimer_periph; + + ad16c4t0_hwtimer_periph.perh = AD16C4T0; + ad16c4t0_hwtimer.IRQn = AD16C4T0_BRK_UP_TRIG_COM_IRQn; + + ad16c4t0_hwtimer_periph.init.prescaler = ES_AD16C4T0_HWTIMER_PRES - 1; + ad16c4t0_hwtimer_periph.init.mode = ( ES_AD16C4T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + ad16c4t0_hwtimer.hwtimer_periph = &ad16c4t0_hwtimer_periph; + + ad16c4t0_hwtimer.parent.info = &ad16c4t0_info; + ad16c4t0_hwtimer.parent.ops = &es32f0_hwtimer_ops; + ret = rt_device_hwtimer_register(&ad16c4t0_hwtimer.parent, ES_DEVICE_NAME_AD16C4T0_HWTIMER, &ad16c4t0_hwtimer); #endif -#ifdef BSP_USING_HWTIMER1 - static timer_handle_t _hwtimer_periph1; - _hwtimer_periph1.perh = BS16T1; - hwtimer1.IRQn = BS16T1_UART2_IRQn; - hwtimer1.hwtimer_periph = &_hwtimer_periph1; - hwtimer1.parent.info = &es32f0_hwtimer_info; - hwtimer1.parent.ops = &es32f0_hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer1.parent, "timer1", &hwtimer1); +#ifdef BSP_USING_GP16C4T0_HWTIMER + static timer_handle_t gp16c4t0_hwtimer_periph; + + gp16c4t0_hwtimer_periph.perh = GP16C4T0; + gp16c4t0_hwtimer.IRQn = GP16C4T0_LCD_IRQn; + + gp16c4t0_hwtimer_periph.init.prescaler = ES_GP16C4T0_HWTIMER_PRES - 1; + gp16c4t0_hwtimer_periph.init.mode = ( ES_GP16C4T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + gp16c4t0_hwtimer.hwtimer_periph = &gp16c4t0_hwtimer_periph; + + gp16c4t0_hwtimer.parent.info = &gp16c4t0_info; + gp16c4t0_hwtimer.parent.ops = &es32f0_hwtimer_ops; + ret = rt_device_hwtimer_register(&gp16c4t0_hwtimer.parent, ES_DEVICE_NAME_GP16C4T0_HWTIMER, &gp16c4t0_hwtimer); #endif -#ifdef BSP_USING_HWTIMER2 - static timer_handle_t _hwtimer_periph2; - _hwtimer_periph2.perh = BS16T2; - hwtimer2.IRQn = BS16T2_UART3_IRQn; - hwtimer2.hwtimer_periph = &_hwtimer_periph2; - hwtimer2.parent.info = &es32f0_hwtimer_info; - hwtimer2.parent.ops = &es32f0_hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer2.parent, "timer2", &hwtimer2); +#ifdef BSP_USING_GP16C2T0_HWTIMER + static timer_handle_t gp16c2t0_hwtimer_periph; + + gp16c2t0_hwtimer_periph.perh = GP16C2T0; + gp16c2t0_hwtimer.IRQn = GP16C2T0_IRQn; + + gp16c2t0_hwtimer_periph.init.prescaler = ES_GP16C2T0_HWTIMER_PRES - 1; + gp16c2t0_hwtimer_periph.init.mode = ( ES_GP16C2T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + gp16c2t0_hwtimer.hwtimer_periph = &gp16c2t0_hwtimer_periph; + + gp16c2t0_hwtimer.parent.info = &gp16c2t0_info; + gp16c2t0_hwtimer.parent.ops = &es32f0_hwtimer_ops; + ret = rt_device_hwtimer_register(&gp16c2t0_hwtimer.parent, ES_DEVICE_NAME_GP16C2T0_HWTIMER, &gp16c2t0_hwtimer); #endif -#ifdef BSP_USING_HWTIMER3 - static timer_handle_t _hwtimer_periph3; - _hwtimer_periph3.perh = BS16T3; - hwtimer3.IRQn = BS16T3_DAC0_IRQn; - hwtimer3.hwtimer_periph = &_hwtimer_periph3; - hwtimer3.parent.info = &es32f0_hwtimer_info; - hwtimer3.parent.ops = &es32f0_hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer3.parent, "timer3", &hwtimer3); +#ifdef BSP_USING_GP16C2T1_HWTIMER + static timer_handle_t gp16c2t1_hwtimer_periph; + + gp16c2t1_hwtimer_periph.perh = GP16C2T1; + gp16c2t1_hwtimer.IRQn = GP16C2T1_IRQn; + + gp16c2t1_hwtimer_periph.init.prescaler = ES_GP16C2T1_HWTIMER_PRES - 1; + gp16c2t1_hwtimer_periph.init.mode = ( ES_GP16C2T1_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + gp16c2t1_hwtimer.hwtimer_periph = &gp16c2t1_hwtimer_periph; + + gp16c2t1_hwtimer.parent.info = &gp16c2t1_info; + gp16c2t1_hwtimer.parent.ops = &es32f0_hwtimer_ops; + ret = rt_device_hwtimer_register(&gp16c2t1_hwtimer.parent, ES_DEVICE_NAME_GP16C2T1_HWTIMER, &gp16c2t1_hwtimer); #endif +#ifdef BSP_USING_BS16T0_HWTIMER + static timer_handle_t bs16t0_hwtimer_periph; + + bs16t0_hwtimer_periph.perh = BS16T0; + bs16t0_hwtimer.IRQn = BS16T0_IRQn; + + bs16t0_hwtimer_periph.init.prescaler = ES_BS16T0_HWTIMER_PRES - 1; + bs16t0_hwtimer_periph.init.mode = ( ES_BS16T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + bs16t0_hwtimer.hwtimer_periph = &bs16t0_hwtimer_periph; + + bs16t0_hwtimer.parent.info = &bs16t0_info; + bs16t0_hwtimer.parent.ops = &es32f0_hwtimer_ops; + ret = rt_device_hwtimer_register(&bs16t0_hwtimer.parent, ES_DEVICE_NAME_BS16T0_HWTIMER, &bs16t0_hwtimer); +#endif + +#ifdef BSP_USING_BS16T1_HWTIMER + static timer_handle_t bs16t1_hwtimer_periph; + + bs16t1_hwtimer_periph.perh = BS16T1; + bs16t1_hwtimer.IRQn = BS16T1_UART2_IRQn; + + bs16t1_hwtimer_periph.init.prescaler = ES_BS16T1_HWTIMER_PRES - 1; + bs16t1_hwtimer_periph.init.mode = ( ES_BS16T1_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + bs16t1_hwtimer.hwtimer_periph = &bs16t1_hwtimer_periph; + + bs16t1_hwtimer.parent.info = &bs16t1_info; + bs16t1_hwtimer.parent.ops = &es32f0_hwtimer_ops; + ret = rt_device_hwtimer_register(&bs16t1_hwtimer.parent, ES_DEVICE_NAME_BS16T1_HWTIMER, &bs16t1_hwtimer); +#endif + +#ifdef BSP_USING_BS16T2_HWTIMER + static timer_handle_t bs16t2_hwtimer_periph; + + bs16t2_hwtimer_periph.perh = BS16T2; + bs16t2_hwtimer.IRQn = BS16T2_UART3_IRQn; + + bs16t2_hwtimer_periph.init.prescaler = ES_BS16T2_HWTIMER_PRES - 1; + bs16t2_hwtimer_periph.init.mode = ( ES_BS16T2_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + bs16t2_hwtimer.hwtimer_periph = &bs16t2_hwtimer_periph; + + bs16t2_hwtimer.parent.info = &bs16t2_info; + bs16t2_hwtimer.parent.ops = &es32f0_hwtimer_ops; + ret = rt_device_hwtimer_register(&bs16t2_hwtimer.parent, ES_DEVICE_NAME_BS16T2_HWTIMER, &bs16t2_hwtimer); +#endif + +#ifdef BSP_USING_BS16T3_HWTIMER + static timer_handle_t bs16t3_hwtimer_periph; + + bs16t3_hwtimer_periph.perh = BS16T3; + bs16t3_hwtimer.IRQn = BS16T3_DAC0_IRQn; + + bs16t3_hwtimer_periph.init.prescaler = ES_BS16T3_HWTIMER_PRES - 1; + bs16t3_hwtimer_periph.init.mode = ( ES_BS16T3_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + bs16t3_hwtimer.hwtimer_periph = &bs16t3_hwtimer_periph; + + bs16t3_hwtimer.parent.info = &bs16t3_info; + bs16t3_hwtimer.parent.ops = &es32f0_hwtimer_ops; + ret = rt_device_hwtimer_register(&bs16t3_hwtimer.parent, ES_DEVICE_NAME_BS16T3_HWTIMER, &bs16t3_hwtimer); +#endif + + return ret; } INIT_BOARD_EXPORT(rt_hw_hwtimer_init); diff --git a/bsp/essemi/es32f0654/drivers/drv_hwtimer.h b/bsp/essemi/es32f0654/drivers/drv_hwtimer.h index e18d580fbd..46e307a5c3 100644 --- a/bsp/essemi/es32f0654/drivers/drv_hwtimer.h +++ b/bsp/essemi/es32f0654/drivers/drv_hwtimer.h @@ -3,14 +3,28 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes - * 2019-3-19 wangyq the first version + * 2019-3-19 wangyq the first version + * 2021-04-20 liuhy the second version */ #ifndef DRV_HWTIMER_H__ #define DRV_HWTIMER_H__ +#include "es_conf_info_hwtimer.h" int rt_hw_hwtimer_init(void); #endif diff --git a/bsp/essemi/es32f0654/drivers/drv_i2c.c b/bsp/essemi/es32f0654/drivers/drv_i2c.c index 399e1427ef..1109b7f641 100644 --- a/bsp/essemi/es32f0654/drivers/drv_i2c.c +++ b/bsp/essemi/es32f0654/drivers/drv_i2c.c @@ -1,8 +1,19 @@ /* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes * 2019-01-24 wangyq the first version @@ -10,19 +21,24 @@ * 2020-12-15 liuhy update libraries */ +#include #include #include -#include #include "board.h" #include "drv_i2c.h" -#include -#include + #ifdef RT_USING_I2C #define TIMEOUT 0x0FFF /* I2C struct definition */ -static i2c_handle_t _h_i2c0, _h_i2c1; +#ifdef BSP_USING_I2C0 + static i2c_handle_t _h_i2c0; +#endif + +#ifdef BSP_USING_I2C1 + static i2c_handle_t _h_i2c1; +#endif static void _i2c_init(void) { @@ -38,35 +54,55 @@ static void _i2c_init(void) gpio_instruct.func = GPIO_FUNC_5; #ifdef BSP_USING_I2C0 + +#if defined(ES_I2C0_SCL_GPIO_FUNC)&&defined(ES_I2C0_SCL_GPIO_PORT)&&defined(ES_I2C0_SCL_GPIO_PIN) + gpio_instruct.func = ES_I2C0_SCL_GPIO_FUNC; + ald_gpio_init(ES_I2C0_SCL_GPIO_PORT, ES_I2C0_SCL_GPIO_PIN, &gpio_instruct); +#endif + +#if defined(ES_I2C0_SDA_GPIO_FUNC)&&defined(ES_I2C0_SDA_GPIO_PORT)&&defined(ES_I2C0_SDA_GPIO_PIN) + gpio_instruct.func = ES_I2C0_SDA_GPIO_FUNC; + ald_gpio_init(ES_I2C0_SDA_GPIO_PORT, ES_I2C0_SDA_GPIO_PIN, &gpio_instruct); +#endif + /* Initialize I2C Function */ _h_i2c0.perh = I2C0; - _h_i2c0.init.clk_speed = 100000; _h_i2c0.init.duty = I2C_DUTYCYCLE_2; - _h_i2c0.init.own_addr1 = 0x0A; - _h_i2c0.init.addr_mode = I2C_ADDR_7BIT; - _h_i2c0.init.general_call = I2C_GENERALCALL_DISABLE; - _h_i2c0.init.no_stretch = I2C_NOSTRETCH_ENABLE; + _h_i2c0.init.clk_speed = ES_I2C0_CLK_SPEED; + _h_i2c0.init.own_addr1 = ES_I2C0_OWN_ADDR1; + _h_i2c0.init.addr_mode = ES_I2C0_ADDR_MODE; + _h_i2c0.init.general_call = ES_I2C0_GENERAL_CALL; + _h_i2c0.init.no_stretch = ES_I2C0_STRETCH; ald_i2c_reset(&_h_i2c0); ald_i2c_init(&_h_i2c0); - /* I2C0_SCL->PB8, I2C0_SDA->PB9 */ - ald_gpio_init(GPIOB, GPIO_PIN_8 | GPIO_PIN_9, &gpio_instruct); + #endif #ifdef BSP_USING_I2C1 + +#if defined(ES_I2C1_SDA_GPIO_FUNC)&&defined(ES_I2C1_SDA_GPIO_PORT)&&defined(ES_I2C1_SDA_GPIO_PIN) + gpio_instruct.func = ES_I2C1_SDA_GPIO_FUNC; + ald_gpio_init(ES_I2C1_SDA_GPIO_PORT, ES_I2C1_SDA_GPIO_PIN, &gpio_instruct); +#endif + +#if defined(ES_I2C1_SDA_GPIO_FUNC)&&defined(ES_I2C1_SDA_GPIO_PORT)&&defined(ES_I2C1_SDA_GPIO_PIN) + gpio_instruct.func = ES_I2C1_SDA_GPIO_FUNC; + ald_gpio_init(ES_I2C1_SDA_GPIO_PORT, ES_I2C1_SDA_GPIO_PIN, &gpio_instruct); +#endif + /* Initialize i2c function */ _h_i2c1.perh = I2C1; - _h_i2c1.init.clk_speed = 100000; - _h_i2c1.init.duty = I2C_DUTYCYCLE_2; - _h_i2c1.init.own_addr1 = 0xA0; - _h_i2c1.init.addr_mode = I2C_ADDR_7BIT; - _h_i2c1.init.general_call = I2C_GENERALCALL_DISABLE; - _h_i2c1.init.no_stretch = I2C_NOSTRETCH_ENABLE; - + _h_i2c1.init.duty = I2C_DUTYCYCLE_2; + _h_i2c1.init.clk_speed = ES_I2C1_CLK_SPEED; + _h_i2c1.init.own_addr1 = ES_I2C1_OWN_ADDR1; + _h_i2c1.init.addr_mode = ES_I2C1_ADDR_MODE; + _h_i2c1.init.general_call = ES_I2C1_GENERAL_CALL; + _h_i2c1.init.no_stretch = ES_I2C1_STRETCH; + ald_i2c_reset(&_h_i2c1); ald_i2c_init(&_h_i2c1); - /* I2C1_SCL->PB10, I2C1_SDA->PB11 */ - ald_gpio_init(GPIOB, GPIO_PIN_10 | GPIO_PIN_11, &gpio_instruct); + #endif } @@ -116,6 +152,8 @@ const struct rt_i2c_bus_device_ops es32f0_i2c_ops = int rt_hw_i2c_init(void) { + int result = RT_EOK; + _i2c_init(); #ifdef BSP_USING_I2C0 @@ -124,16 +162,25 @@ int rt_hw_i2c_init(void) rt_memset((void *)&_i2c_device0, 0, sizeof(struct rt_i2c_bus_device)); _i2c_device0.ops = &es32f0_i2c_ops; _i2c_device0.priv = &_h_i2c0; - rt_i2c_bus_device_register(&_i2c_device0, "i2c0"); + result = rt_i2c_bus_device_register(&_i2c_device0, ES_DEVICE_NAME_I2C0); + if (result != RT_EOK) + { + return result; + } #endif #ifdef BSP_USING_I2C1 /* define i2c Instance */ static struct rt_i2c_bus_device _i2c_device1; rt_memset((void *)&_i2c_device1, 0, sizeof(struct rt_i2c_bus_device)); + _i2c_device1.ops = &es32f0_i2c_ops; _i2c_device1.priv = &_h_i2c1; - rt_i2c_bus_device_register(&_i2c_device1, "i2c1"); + rt_i2c_bus_device_register(&_i2c_device1, ES_DEVICE_NAME_I2C1); + if (result != RT_EOK) + { + return result; + } #endif return RT_EOK; diff --git a/bsp/essemi/es32f0654/drivers/drv_i2c.h b/bsp/essemi/es32f0654/drivers/drv_i2c.h index 84c32561c8..b5cc316ee7 100644 --- a/bsp/essemi/es32f0654/drivers/drv_i2c.h +++ b/bsp/essemi/es32f0654/drivers/drv_i2c.h @@ -1,16 +1,31 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes - * 2019-01-24 wangyq the first version + * 2019-01-24 wangyq the first version + * 2021-04-20 liuhy the second version */ #ifndef DRV_I2C_H__ #define DRV_I2C_H__ +#include "es_conf_info_i2c.h" + int rt_hw_i2c_init(void); #endif diff --git a/bsp/essemi/es32f0654/drivers/drv_pm.c b/bsp/essemi/es32f0654/drivers/drv_pm.c index 669514c7b8..c1b4c41237 100644 --- a/bsp/essemi/es32f0654/drivers/drv_pm.c +++ b/bsp/essemi/es32f0654/drivers/drv_pm.c @@ -3,20 +3,30 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes * 2019-04-08 wangyq the first version * 2019-11-01 wangyq adapt to the new power management interface + * 2020-12-15 liuhy the first version */ -#include -#include -#include -#include -#include +#include "drv_pm.h" #ifdef RT_USING_PM + static void uart_console_reconfig(void) { struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; @@ -24,26 +34,14 @@ static void uart_console_reconfig(void) rt_device_control(rt_console_get_device(), RT_DEVICE_CTRL_CONFIG, &config); } -static void delay(void) -{ - long i; - rt_base_t level; - - level = rt_hw_interrupt_disable(); - i = 0; - do{ - i++; - } - while (i < 10000); - - rt_hw_interrupt_enable(level); -} - /** - * This function will put ES32F033x into sleep mode. + * This function will put ES32F065x into sleep mode. * * @param pm pointer to power manage structure */ + + +/* 注意：进入睡眠前，如果有中断挂起（SYSTICK、PENDSV、UART、EXTI等），睡眠将被瞬间唤醒。*/ static void sleep(struct rt_pm *pm, uint8_t mode) { switch (mode) @@ -52,31 +50,26 @@ static void sleep(struct rt_pm *pm, uint8_t mode) break; case PM_SLEEP_MODE_IDLE: - //__WFI(); break; case PM_SLEEP_MODE_LIGHT: /* Enter SLEEP Mode, Main regulator is ON */ ald_pmu_stop1_enter(); - delay(); break; - case PM_SLEEP_MODE_DEEP: - /* Enter STOP 2 mode */ + case PM_SLEEP_MODE_DEEP: + /* Enter STOP 2 mode */ ald_pmu_stop2_enter(); - delay(); break; case PM_SLEEP_MODE_STANDBY: - /* Enter STANDBY mode */ + /* Enter STANDBY mode */ ald_pmu_stop2_enter(); - delay(); break; case PM_SLEEP_MODE_SHUTDOWN: - /* Enter SHUTDOWNN mode */ + /* Enter SHUTDOWNN mode */ ald_pmu_stop2_enter(); - delay(); break; default: diff --git a/bsp/essemi/es32f0654/drivers/drv_pm.h b/bsp/essemi/es32f0654/drivers/drv_pm.h index a4f6cc84ee..e43ba09c26 100644 --- a/bsp/essemi/es32f0654/drivers/drv_pm.h +++ b/bsp/essemi/es32f0654/drivers/drv_pm.h @@ -3,7 +3,20 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: + * Date Author Notes * 2019-04-01 wangyq the first version */ @@ -11,6 +24,12 @@ #ifndef DRV_PM_H__ #define DRV_PM_H__ +#include +#include +#include +#include "es_conf_info_pm.h" +#include + int rt_hw_pm_init(void); #endif diff --git a/bsp/essemi/es32f0654/drivers/drv_pwm.c b/bsp/essemi/es32f0654/drivers/drv_pwm.c index d324e2bbbb..59e8494241 100644 --- a/bsp/essemi/es32f0654/drivers/drv_pwm.c +++ b/bsp/essemi/es32f0654/drivers/drv_pwm.c @@ -3,28 +3,33 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes * 2019-03-11 wangyq the first version * 2019-11-01 wangyq update libraries + * 2021-04-20 liuhy the second version */ #include #include #include #include -#include -#include -#include +#include "es_conf_info_pwm.h" -static void pwm_set_freq(timer_handle_t *timer_initstruct, uint32_t ns) -{ - uint64_t _arr = (uint64_t)ald_cmu_get_pclk1_clock() * ns / 1000000000 / - (timer_initstruct->init.prescaler + 1); - WRITE_REG(timer_initstruct->perh->AR, (uint32_t)_arr); - timer_initstruct->init.period = (uint32_t)_arr; -} +#ifdef RT_USING_PWM static void pwm_set_duty(timer_handle_t *timer_initstruct, timer_channel_t ch, uint32_t ns) { @@ -44,7 +49,8 @@ static void pwm_set_duty(timer_handle_t *timer_initstruct, timer_channel_t ch, u static rt_err_t es32f0_pwm_control(struct rt_device_pwm *device, int cmd, void *arg) { rt_err_t ret = RT_EOK; - uint32_t _ccep; + uint64_t _arr,bus_speed,tmp; + uint32_t _maxcnt,_ccep_ch_en = 0U; timer_channel_t pwm_channel; timer_oc_init_t tim_ocinit; timer_handle_t *timer_initstruct = (timer_handle_t *)device->parent.user_data; @@ -52,39 +58,30 @@ static rt_err_t es32f0_pwm_control(struct rt_device_pwm *device, int cmd, void * RT_ASSERT(timer_initstruct != RT_NULL); - tim_ocinit.oc_mode = TIMER_OC_MODE_PWM1; - tim_ocinit.oc_polarity = TIMER_OC_POLARITY_HIGH; - tim_ocinit.oc_fast_en = DISABLE; - tim_ocinit.ocn_polarity = TIMER_OCN_POLARITY_HIGH; - tim_ocinit.ocn_idle = TIMER_OCN_IDLE_RESET; - tim_ocinit.oc_idle = TIMER_OC_IDLE_RESET; - /* select pwm output channel */ if (1 == cfg->channel) { pwm_channel = TIMER_CHANNEL_1; + _ccep_ch_en = timer_initstruct->perh->CCEP & TIMER_CCEP_CC1EN_MSK; } - else if (2 == cfg->channel) + else if (2 == cfg->channel) { pwm_channel = TIMER_CHANNEL_2; + _ccep_ch_en = timer_initstruct->perh->CCEP & TIMER_CCEP_CC2EN_MSK; } - else if (3 == cfg->channel) + else if (3 == cfg->channel) { - if (timer_initstruct->perh == GP16C2T0 || timer_initstruct->perh == GP16C2T1) - return RT_EINVAL; pwm_channel = TIMER_CHANNEL_3; + _ccep_ch_en = timer_initstruct->perh->CCEP & TIMER_CCEP_CC3EN_MSK; } - else if (4 == cfg->channel) + else if (4 == cfg->channel) { - if (timer_initstruct->perh == GP16C2T0 || timer_initstruct->perh == GP16C2T1) - return RT_EINVAL; pwm_channel = TIMER_CHANNEL_4; + _ccep_ch_en = timer_initstruct->perh->CCEP & TIMER_CCEP_CC4EN_MSK; } else - { return RT_EINVAL; - } - + switch (cmd) { case PWM_CMD_ENABLE: @@ -96,19 +93,44 @@ static rt_err_t es32f0_pwm_control(struct rt_device_pwm *device, int cmd, void * break; case PWM_CMD_SET: - _ccep = timer_initstruct->perh->CCEP; - /* count registers max 0xFFFF, auto adjust prescaler */ + + /*当通道没开的时候：关通道，设置输出模式和极性，初始化通道*/ + if(!_ccep_ch_en) + { + tim_ocinit.oc_mode = ES_PWM_OC_MODE; + tim_ocinit.oc_polarity = ES_PWM_OC_POLARITY; + tim_ocinit.oc_fast_en = DISABLE; + tim_ocinit.ocn_polarity = TIMER_OCN_POLARITY_HIGH; + tim_ocinit.ocn_idle = TIMER_OCN_IDLE_RESET; + tim_ocinit.oc_idle = TIMER_OC_IDLE_RESET; + ald_timer_oc_config_channel(timer_initstruct, &tim_ocinit, pwm_channel); + } + + bus_speed = (uint64_t)ald_cmu_get_pclk1_clock(); + + /*外设的计数器最大值*/ + _maxcnt = 0xFFFF; + + /*当最大分频 <= _maxcnt时：估计大概的分频，加快速度 */ + tmp = bus_speed * (cfg->period)/1000000000/_maxcnt; + timer_initstruct->init.prescaler = (tmp > 2U) ? (tmp - 2U) : 0U ; /*bus_speed < 500000000*/ + + /* count registers max , auto adjust prescaler */ do { - pwm_set_freq(timer_initstruct, cfg->period); - timer_initstruct->init.prescaler ++; + _arr = bus_speed * (cfg->period) / 1000000000 /(++timer_initstruct->init.prescaler); + } - while (timer_initstruct->init.period > 0xFFFF); + while (_arr > _maxcnt); + + WRITE_REG(timer_initstruct->perh->AR, (uint32_t)_arr); + timer_initstruct->init.period = (uint32_t)_arr; + /* update prescaler */ WRITE_REG(timer_initstruct->perh->PRES, --timer_initstruct->init.prescaler); - ald_timer_oc_config_channel(timer_initstruct, &tim_ocinit, pwm_channel); + pwm_set_duty(timer_initstruct, pwm_channel, cfg->pulse); - timer_initstruct->perh->CCEP = _ccep; + break; case PWM_CMD_GET: @@ -139,74 +161,124 @@ int rt_hw_pwm_init(void) gpio_initstructure.flt = GPIO_FILTER_DISABLE; gpio_initstructure.type = GPIO_TYPE_TTL; -#ifdef BSP_USING_PWM0 /* 4 channels */ - static struct rt_device_pwm pwm_dev0; - static timer_handle_t timer_initstruct0; +#ifdef BSP_USING_AD16C4T0_PWM /* 4 channels */ + static struct rt_device_pwm ad16c4t0_pwm_dev; + static timer_handle_t ad16c4t0_timer_initstruct; - timer_initstruct0.perh = AD16C4T0; - ald_timer_pwm_init(&timer_initstruct0); + ad16c4t0_timer_initstruct.perh = AD16C4T0; + ald_timer_pwm_init(&ad16c4t0_timer_initstruct); /* gpio initialization */ - gpio_initstructure.func = GPIO_FUNC_2; - ald_gpio_init(GPIOA, GPIO_PIN_8, &gpio_initstructure); - ald_gpio_init(GPIOA, GPIO_PIN_9, &gpio_initstructure); - ald_gpio_init(GPIOA, GPIO_PIN_10, &gpio_initstructure); - ald_gpio_init(GPIOA, GPIO_PIN_11, &gpio_initstructure); - ret = rt_device_pwm_register(&pwm_dev0, "pwm0", &es32f0_pwm_ops, - &timer_initstruct0); +#if defined(ES_AD16C4T0_CH1_GPIO_FUNC)&&defined(ES_AD16C4T0_CH1_GPIO_PORT)&&defined(ES_AD16C4T0_CH1_GPIO_PIN) + gpio_initstructure.func = ES_AD16C4T0_CH1_GPIO_FUNC; + ald_gpio_init(ES_AD16C4T0_CH1_GPIO_PORT, ES_AD16C4T0_CH1_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_AD16C4T0_CH2_GPIO_FUNC)&&defined(ES_AD16C4T0_CH2_GPIO_PORT)&&defined(ES_AD16C4T0_CH2_GPIO_PIN) + gpio_initstructure.func = ES_AD16C4T0_CH2_GPIO_FUNC; + ald_gpio_init(ES_AD16C4T0_CH2_GPIO_PORT, ES_AD16C4T0_CH2_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_AD16C4T0_CH3_GPIO_FUNC)&&defined(ES_AD16C4T0_CH3_GPIO_PORT)&&defined(ES_AD16C4T0_CH3_GPIO_FUNC) + gpio_initstructure.func = ES_AD16C4T0_CH3_GPIO_FUNC; + ald_gpio_init(ES_AD16C4T0_CH3_GPIO_PORT, ES_AD16C4T0_CH3_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_AD16C4T0_CH4_GPIO_FUNC)&&defined(ES_AD16C4T0_CH4_GPIO_PORT)&&defined(ES_AD16C4T0_CH4_GPIO_PIN) + gpio_initstructure.func = ES_AD16C4T0_CH4_GPIO_FUNC; + ald_gpio_init(ES_AD16C4T0_CH4_GPIO_PORT, ES_AD16C4T0_CH4_GPIO_PIN, &gpio_initstructure); +#endif + + ret = rt_device_pwm_register(&ad16c4t0_pwm_dev, ES_DEVICE_NAME_AD16C4T0_PWM, &es32f0_pwm_ops, + &ad16c4t0_timer_initstruct); #endif -#ifdef BSP_USING_PWM1 /* 4 channels */ - static struct rt_device_pwm pwm_dev1; - static timer_handle_t timer_initstruct1; +#ifdef BSP_USING_GP16C4T0_PWM /* 4 channels */ + static struct rt_device_pwm gp16c4t0_pwm_dev; + static timer_handle_t gp16c4t0_timer_initstruct; - timer_initstruct1.perh = GP16C4T0; - ald_timer_pwm_init(&timer_initstruct1); + gp16c4t0_timer_initstruct.perh = GP16C4T0; + ald_timer_pwm_init(&gp16c4t0_timer_initstruct); /* gpio initialization */ - gpio_initstructure.func = GPIO_FUNC_2; - ald_gpio_init(GPIOB, GPIO_PIN_6, &gpio_initstructure); - ald_gpio_init(GPIOB, GPIO_PIN_7, &gpio_initstructure); - ald_gpio_init(GPIOB, GPIO_PIN_8, &gpio_initstructure); - ald_gpio_init(GPIOB, GPIO_PIN_9, &gpio_initstructure); + +#if defined(ES_GP16C4T0_CH1_GPIO_FUNC)&&defined(ES_GP16C4T0_CH1_GPIO_PORT)&&defined(ES_GP16C4T0_CH1_GPIO_PIN) + gpio_initstructure.func = ES_GP16C4T0_CH1_GPIO_FUNC; + ald_gpio_init(ES_GP16C4T0_CH1_GPIO_PORT, ES_GP16C4T0_CH1_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP16C4T0_CH2_GPIO_FUNC)&&defined(ES_GP16C4T0_CH2_GPIO_PORT)&&defined(ES_GP16C4T0_CH2_GPIO_PIN) + gpio_initstructure.func = ES_GP16C4T0_CH2_GPIO_FUNC; + ald_gpio_init(ES_GP16C4T0_CH2_GPIO_PORT, ES_GP16C4T0_CH2_GPIO_PIN, &gpio_initstructure); +#endif - ret = rt_device_pwm_register(&pwm_dev1, "pwm1", &es32f0_pwm_ops, - &timer_initstruct1); +#if defined(ES_GP16C4T0_CH3_GPIO_FUNC)&&defined(ES_GP16C4T0_CH3_GPIO_PORT)&&defined(ES_GP16C4T0_CH3_GPIO_PIN) + gpio_initstructure.func = ES_GP16C4T0_CH3_GPIO_FUNC; + ald_gpio_init(ES_GP16C4T0_CH3_GPIO_PORT, ES_GP16C4T0_CH3_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP16C4T0_CH4_GPIO_FUNC)&&defined(ES_GP16C4T0_CH4_GPIO_PORT)&&defined(ES_GP16C4T0_CH4_GPIO_PIN) + gpio_initstructure.func = ES_GP16C4T0_CH4_GPIO_FUNC; + ald_gpio_init(ES_GP16C4T0_CH4_GPIO_PORT, ES_GP16C4T0_CH4_GPIO_PIN, &gpio_initstructure); +#endif + + ret = rt_device_pwm_register(&gp16c4t0_pwm_dev, ES_DEVICE_NAME_GP16C4T0_PWM, &es32f0_pwm_ops, + &gp16c4t0_timer_initstruct); #endif -#ifdef BSP_USING_PWM2 /* 2 channels */ - static struct rt_device_pwm pwm_dev2; - static timer_handle_t timer_initstruct2; - timer_initstruct2.perh = GP16C2T0; - ald_timer_pwm_init(&timer_initstruct2); +#ifdef BSP_USING_GP16C2T0_PWM /* 2 channels */ + static struct rt_device_pwm gp16c2t0_pwm_dev; + static timer_handle_t gp16c2t0_timer_initstruct; + + gp16c2t0_timer_initstruct.perh = GP16C2T0; + ald_timer_pwm_init(&gp16c2t0_timer_initstruct); /* gpio initialization */ - gpio_initstructure.func = GPIO_FUNC_2; - ald_gpio_init(GPIOA, GPIO_PIN_0, &gpio_initstructure); - ald_gpio_init(GPIOA, GPIO_PIN_1, &gpio_initstructure); + +#if defined(ES_GP16C2T0_CH1_GPIO_FUNC)&&defined(ES_GP16C2T0_CH1_GPIO_PORT)&&defined(ES_GP16C2T0_CH1_GPIO_PIN) + gpio_initstructure.func = ES_GP16C2T0_CH1_GPIO_FUNC; + ald_gpio_init(ES_GP16C2T0_CH1_GPIO_PORT, ES_GP16C2T0_CH1_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP16C2T0_CH2_GPIO_FUNC)&&defined(ES_GP16C2T0_CH2_GPIO_PORT)&&defined(ES_GP16C2T0_CH2_GPIO_PIN) + gpio_initstructure.func = ES_GP16C2T0_CH2_GPIO_FUNC; + ald_gpio_init(ES_GP16C2T0_CH2_GPIO_PORT, ES_GP16C2T0_CH2_GPIO_PIN, &gpio_initstructure); +#endif - ret = rt_device_pwm_register(&pwm_dev2, "pwm2", &es32f0_pwm_ops, - &timer_initstruct2); + ret = rt_device_pwm_register(&gp16c2t0_pwm_dev, ES_DEVICE_NAME_GP16C2T0_PWM, &es32f0_pwm_ops, + &gp16c2t0_timer_initstruct); #endif -#ifdef BSP_USING_PWM3 /* 2 channels */ - static struct rt_device_pwm pwm_dev3; - static timer_handle_t timer_initstruct3; - timer_initstruct3.perh = GP16C2T1; - ald_timer_pwm_init(&timer_initstruct3); +#ifdef BSP_USING_GP16C2T1_PWM /* 2 channels */ + static struct rt_device_pwm gp16c2t1_pwm_dev; + static timer_handle_t gp16c2t1_timer_initstruct; + + gp16c2t1_timer_initstruct.perh = GP16C2T1; + ald_timer_pwm_init(&gp16c2t1_timer_initstruct); /* gpio initialization */ - gpio_initstructure.func = GPIO_FUNC_3; - ald_gpio_init(GPIOC, GPIO_PIN_6, &gpio_initstructure); - ald_gpio_init(GPIOC, GPIO_PIN_7, &gpio_initstructure); + +#if defined(ES_GP16C2T1_CH1_GPIO_FUNC)&&defined(ES_GP16C2T1_CH1_GPIO_PORT)&&defined(ES_GP16C2T1_CH1_GPIO_PIN) + gpio_initstructure.func = ES_GP16C2T1_CH1_GPIO_FUNC; + ald_gpio_init(ES_GP16C2T1_CH1_GPIO_PORT, ES_GP16C2T1_CH1_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP16C2T1_CH2_GPIO_FUNC)&&defined(ES_GP16C2T1_CH2_GPIO_PORT)&&defined(ES_GP16C2T1_CH2_GPIO_PIN) + gpio_initstructure.func = ES_GP16C2T1_CH2_GPIO_FUNC; + ald_gpio_init(ES_GP16C2T1_CH2_GPIO_PORT, ES_GP16C2T1_CH2_GPIO_PIN, &gpio_initstructure); +#endif - ret = rt_device_pwm_register(&pwm_dev3, "pwm3", &es32f0_pwm_ops, - &timer_initstruct3); + ret = rt_device_pwm_register(&gp16c2t1_pwm_dev, ES_DEVICE_NAME_GP16C2T1_PWM, &es32f0_pwm_ops, + &gp16c2t1_timer_initstruct); #endif + + return ret; } INIT_DEVICE_EXPORT(rt_hw_pwm_init); + +#endif diff --git a/bsp/essemi/es32f0654/drivers/drv_pwm.h b/bsp/essemi/es32f0654/drivers/drv_pwm.h index f4fcfe7cff..3383e7ba1c 100644 --- a/bsp/essemi/es32f0654/drivers/drv_pwm.h +++ b/bsp/essemi/es32f0654/drivers/drv_pwm.h @@ -3,6 +3,18 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes * 2019-03-11 wangyq the first version diff --git a/bsp/essemi/es32f0654/drivers/drv_rtc.c b/bsp/essemi/es32f0654/drivers/drv_rtc.c index cab5b8b61b..ee7589090b 100644 --- a/bsp/essemi/es32f0654/drivers/drv_rtc.c +++ b/bsp/essemi/es32f0654/drivers/drv_rtc.c @@ -3,26 +3,38 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes * 2019-03-22 wangyq the first version * 2019-11-01 wangyq update libraries + * 2021-04-20 liuhy the second version */ #include #include -#include +#include #include #include #include "board.h" -#include "drv_rtc.h" -#include -#include +#include "drv_rtc.h" #ifdef RT_USING_RTC static void __rtc_init(rtc_init_t *init) { + assert_param(IS_RTC_HOUR_FORMAT(init->hour_format)); assert_param(IS_RTC_OUTPUT_SEL(init->output)); assert_param(IS_RTC_OUTPUT_POLARITY(init->output_polarity)); @@ -117,10 +129,16 @@ int rt_hw_rtc_init(void) rt_err_t ret = RT_EOK; static struct rt_device rtc_dev; rtc_init_t rtc_initstruct; + + /* enable clk */ + ald_rtc_source_select(ES_RTC_CLK_SOURCE); - /* enable external 32.768kHz */ - CMU_LOSC_ENABLE(); - ald_cmu_losc_safe_config(ENABLE); + if(ES_RTC_CLK_SOURCE == ES_C_RTC_SOURCE_LOSC) + { + CMU_LOSC_ENABLE(); + ald_cmu_losc_safe_config(ENABLE); + } + /* set default time */ RTC_UNLOCK(); WRITE_REG(RTC->TIME, 0x134251); @@ -131,6 +149,8 @@ int rt_hw_rtc_init(void) rtc_initstruct.asynch_pre_div = 0; rtc_initstruct.synch_pre_div = 32767; rtc_initstruct.output = RTC_OUTPUT_DISABLE; + rtc_initstruct.output_polarity = RTC_OUTPUT_POLARITY_HIGH; + __rtc_init(&rtc_initstruct); rtc_dev.type = RT_Device_Class_RTC; @@ -150,7 +170,7 @@ int rt_hw_rtc_init(void) rtc_dev.user_data = RTC; - ret = rt_device_register(&rtc_dev, "rtc", RT_DEVICE_FLAG_RDWR); + ret = rt_device_register(&rtc_dev, ES_DEVICE_NAME_RTC, RT_DEVICE_FLAG_RDWR); return ret; } diff --git a/bsp/essemi/es32f0654/drivers/drv_rtc.h b/bsp/essemi/es32f0654/drivers/drv_rtc.h index fe0264fb51..76e5b24d85 100644 --- a/bsp/essemi/es32f0654/drivers/drv_rtc.h +++ b/bsp/essemi/es32f0654/drivers/drv_rtc.h @@ -3,14 +3,28 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes - * 2019-03-22 wangyq the first version + * 2019-03-22 wangyq the first version + * 2021-04-20 liuhy the second version */ #ifndef DRV_RTC_H__ #define DRV_RTC_H__ +#include "es_conf_info_rtc.h" int rt_hw_rtc_init(void); #endif diff --git a/bsp/essemi/es32f0654/drivers/drv_spi.c b/bsp/essemi/es32f0654/drivers/drv_spi.c index dd37691125..6ea5c1a705 100644 --- a/bsp/essemi/es32f0654/drivers/drv_spi.c +++ b/bsp/essemi/es32f0654/drivers/drv_spi.c @@ -3,11 +3,23 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes * 2019-01-24 wangyq the first version * 2019-11-01 wangyq update libraries - * 2020-12-15 liuhy update libraries + * 2021-04-20 liuhy the second version */ #include @@ -16,9 +28,7 @@ #include #include "board.h" #include "drv_spi.h" -#include -#include -#include + #ifdef RT_USING_SPI @@ -30,6 +40,9 @@ rt_err_t spi_configure(struct rt_spi_device *device, spi_handle_t *hspi; hspi = (spi_handle_t *)device->bus->parent.user_data; + hspi->init.ss_en = DISABLE; + hspi->init.crc_calc = DISABLE; + /* config spi mode */ if (cfg->mode & RT_SPI_SLAVE) { @@ -64,6 +77,16 @@ rt_err_t spi_configure(struct rt_spi_device *device, { hspi->init.phase = SPI_CPHA_FIRST; } + + if (cfg->mode & RT_SPI_MSB) + { + hspi->init.first_bit = SPI_FIRSTBIT_MSB; + } + else + { + hspi->init.first_bit = SPI_FIRSTBIT_LSB; + } + if (cfg->mode & RT_SPI_CPOL) { hspi->init.polarity = SPI_CPOL_HIGH; @@ -72,6 +95,7 @@ rt_err_t spi_configure(struct rt_spi_device *device, { hspi->init.polarity = SPI_CPOL_LOW; } + if (cfg->mode & RT_SPI_NO_CS) { hspi->init.ss_en = DISABLE; @@ -150,74 +174,54 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message * hspi = (spi_handle_t *)device->bus->parent.user_data; cs = device->parent.user_data; + + if (message->cs_take) + { + rt_pin_write(cs->pin, ES_SPI_CS_LEVEL); + } if(message->send_buf != RT_NULL || message->recv_buf != RT_NULL) { /* send & receive */ if ((message->send_buf != RT_NULL) && (message->recv_buf != RT_NULL)) { - if (message->cs_take) - { - rt_pin_write(cs->pin, 0); - } res = ald_spi_send_recv(hspi, (rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, SPITIMEOUT); - if (message->cs_release) - { - rt_pin_write(cs->pin, 1); - } - if (res != RT_EOK) - return RT_ERROR; } else { /* only send data */ if (message->recv_buf == RT_NULL) { - if (message->cs_take) - { - rt_pin_write(cs->pin, 0); - } res = ald_spi_send(hspi, (rt_uint8_t *)message->send_buf, (rt_int32_t)message->length, SPITIMEOUT); - if (message->cs_release) - { - rt_pin_write(cs->pin, 1); - } - if (res != RT_EOK) - return RT_ERROR; } /* only receive data */ if (message->send_buf == RT_NULL) { - if (message->cs_take) - { - rt_pin_write(cs->pin, 0); - } res = ald_spi_recv(hspi, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, SPITIMEOUT); - if (message->cs_release) - { - rt_pin_write(cs->pin, 1); - } - if (res != RT_EOK) - return RT_ERROR; } } - + + if (message->cs_release) + { + rt_pin_write(cs->pin, !ES_SPI_CS_LEVEL); + } + + if (res != RT_EOK) + return RT_ERROR; + else + return message->length; + } else { - if (message->cs_take) - { - rt_pin_write(cs->pin, 0); - } - + if (message->cs_release) { - rt_pin_write(cs->pin, 1); + rt_pin_write(cs->pin, !ES_SPI_CS_LEVEL); } return RT_EOK; } - return message->length; } @@ -230,6 +234,7 @@ const struct rt_spi_ops es32f0_spi_ops = rt_err_t es32f0_spi_device_attach(rt_uint32_t pin, const char *bus_name, const char *device_name) { + int result; /* define spi Instance */ struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); RT_ASSERT(spi_device != RT_NULL); @@ -238,7 +243,17 @@ rt_err_t es32f0_spi_device_attach(rt_uint32_t pin, const char *bus_name, const c cs_pin->pin = pin; rt_pin_mode(pin, PIN_MODE_OUTPUT); rt_pin_write(pin, 1); - return rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); + + result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); + +#ifdef BSP_USING_SPI0 + if(!(strcmp(bus_name,ES_DEVICE_NAME_SPI0_BUS)))SPI_BUS_CONFIG(spi_device->config,0); +#endif +#ifdef BSP_USING_SPI1 + if(!(strcmp(bus_name,ES_DEVICE_NAME_SPI1_BUS)))SPI_BUS_CONFIG(spi_device->config,1); +#endif + + return result; } #ifdef BSP_USING_SPI0 @@ -259,77 +274,84 @@ int rt_hw_spi_init(void) spi_handle_t *spi; gpio_init_t gpio_instruct; + gpio_instruct.odos = GPIO_PUSH_PULL; + gpio_instruct.type = GPIO_TYPE_CMOS; + gpio_instruct.flt = GPIO_FILTER_DISABLE; + gpio_instruct.odrv = GPIO_OUT_DRIVE_NORMAL; #ifdef BSP_USING_SPI0 _spi0.perh = SPI0; spi_bus = &_spi_bus0; spi = &_spi0; - rt_device_t spi_bus_dev0; /* SPI0 gpio init */ - gpio_instruct.mode = GPIO_MODE_OUTPUT; - gpio_instruct.odos = GPIO_PUSH_PULL; - gpio_instruct.func = GPIO_FUNC_4; - gpio_instruct.type = GPIO_TYPE_CMOS; - gpio_instruct.flt = GPIO_FILTER_DISABLE; + gpio_instruct.mode = GPIO_MODE_OUTPUT; - /* PB3->SPI0_SCK, PB5->SPI0_MOSI */ - ald_gpio_init(GPIOB, GPIO_PIN_3 | GPIO_PIN_5, &gpio_instruct); +#if defined(ES_SPI0_SCK_GPIO_FUNC)&&defined(ES_SPI0_SCK_GPIO_PORT)&&defined(ES_SPI0_SCK_GPIO_PIN) + gpio_instruct.func = ES_SPI0_SCK_GPIO_FUNC; + ald_gpio_init(ES_SPI0_SCK_GPIO_PORT, ES_SPI0_SCK_GPIO_PIN, &gpio_instruct); +#endif - /* PB4->SPI0_MISO */ - gpio_instruct.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOB, GPIO_PIN_4, &gpio_instruct); +#if defined(ES_SPI0_MOSI_GPIO_FUNC)&&defined(ES_SPI0_MOSI_GPIO_PORT)&&defined(ES_SPI0_MOSI_GPIO_PIN) + gpio_instruct.func = ES_SPI0_MOSI_GPIO_FUNC; + ald_gpio_init(ES_SPI0_MOSI_GPIO_PORT, ES_SPI0_MOSI_GPIO_PIN, &gpio_instruct); +#endif + + gpio_instruct.mode = GPIO_MODE_INPUT; + +#if defined(ES_SPI0_MISO_GPIO_FUNC)&&defined(ES_SPI0_MISO_GPIO_PORT)&&defined(ES_SPI0_MISO_GPIO_PIN) + gpio_instruct.func = ES_SPI0_MISO_GPIO_FUNC; + ald_gpio_init(ES_SPI0_MISO_GPIO_PORT, ES_SPI0_MISO_GPIO_PIN, &gpio_instruct); +#endif spi_bus->parent.user_data = spi; - result = rt_spi_bus_register(spi_bus, "spi0", &es32f0_spi_ops); + result = rt_spi_bus_register(spi_bus, ES_DEVICE_NAME_SPI0_BUS, &es32f0_spi_ops); if (result != RT_EOK) { return result; } - rt_device_register(spi_bus_dev0, "spi00", RT_DEVICE_FLAG_RDWR); - - /* SPI0_NSS = PA15 = PIN 50 */ - result = es32f0_spi_device_attach(50, "spi0", "spi00"); + result = es32f0_spi_device_attach(ES_SPI0_NSS_PIN, ES_DEVICE_NAME_SPI0_BUS, ES_DEVICE_NAME_SPI0_DEV0); if (result != RT_EOK) { return result; } - + #endif #ifdef BSP_USING_SPI1 _spi1.perh = SPI1; spi_bus = &_spi_bus1; spi = &_spi1; - rt_device_t spi_bus_dev0; /* SPI1 gpio init */ - gpio_instruct.mode = GPIO_MODE_OUTPUT; - gpio_instruct.odos = GPIO_PUSH_PULL; - gpio_instruct.func = GPIO_FUNC_4; - gpio_instruct.type = GPIO_TYPE_CMOS; - gpio_instruct.flt = GPIO_FILTER_DISABLE; - - /* PB13->SPI1_SCK, PB15->SPI1_MOSI */ - ald_gpio_init(GPIOB, GPIO_PIN_13 | GPIO_PIN_15, &gpio_instruct); - - /* PB14->SPI1_MISO */ - gpio_instruct.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOB, GPIO_PIN_14, &gpio_instruct); + gpio_instruct.mode = GPIO_MODE_OUTPUT; + +#if defined(ES_SPI1_SCK_GPIO_FUNC)&&defined(ES_SPI1_SCK_GPIO_PORT)&&defined(ES_SPI1_SCK_GPIO_PIN) + gpio_instruct.func = ES_SPI1_SCK_GPIO_FUNC; + ald_gpio_init(ES_SPI1_SCK_GPIO_PORT, ES_SPI1_SCK_GPIO_PIN, &gpio_instruct); +#endif + +#if defined(ES_SPI1_MOSI_GPIO_FUNC)&&defined(ES_SPI1_MOSI_GPIO_PORT)&&defined(ES_SPI1_MOSI_GPIO_PIN) + gpio_instruct.func = ES_SPI1_MOSI_GPIO_FUNC; + ald_gpio_init(ES_SPI1_MOSI_GPIO_PORT, ES_SPI1_MOSI_GPIO_PIN, &gpio_instruct); +#endif + + gpio_instruct.mode = GPIO_MODE_INPUT; + +#if defined(ES_SPI1_MISO_GPIO_FUNC)&&defined(ES_SPI1_MISO_GPIO_PORT)&&defined(ES_SPI1_MISO_GPIO_PIN) + gpio_instruct.func = ES_SPI1_MISO_GPIO_FUNC; + ald_gpio_init(ES_SPI1_MISO_GPIO_PORT, ES_SPI1_MISO_GPIO_PIN, &gpio_instruct); +#endif spi_bus->parent.user_data = spi; - result = rt_spi_bus_register(spi_bus, "spi1", &es32f0_spi_ops); + result = rt_spi_bus_register(spi_bus, ES_DEVICE_NAME_SPI1_BUS, &es32f0_spi_ops); if (result != RT_EOK) { return result; } - rt_device_register(spi_bus_dev0, "spi10", RT_DEVICE_FLAG_RDWR); - - /* SPI1_NSS = PC00 = PIN 8 */ - result = es32f0_spi_device_attach(8, "spi1", "spi10"); - + result = es32f0_spi_device_attach((ES_SPI1_NSS_PIN, ES_DEVICE_NAME_SPI1_BUS, ES_DEVICE_NAME_SPI1_DEV0); if (result != RT_EOK) { return result; diff --git a/bsp/essemi/es32f0654/drivers/drv_spi.h b/bsp/essemi/es32f0654/drivers/drv_spi.h index 991ff35c7a..df7932d570 100644 --- a/bsp/essemi/es32f0654/drivers/drv_spi.h +++ b/bsp/essemi/es32f0654/drivers/drv_spi.h @@ -3,9 +3,22 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes - * 2019-01-24 wangyq the first version + * 2019-01-24 wangyq the first version + * 2021-04-20 liuhy the second version */ #ifndef DRV_SPI_H__ @@ -14,6 +27,8 @@ #include #include #include + +#include "es_conf_info_spi.h" struct es32f0_hw_spi_cs { diff --git a/bsp/essemi/es32f0654/drivers/drv_spiflash.c b/bsp/essemi/es32f0654/drivers/drv_spiflash.c index c84fe1be78..d8176257d1 100644 --- a/bsp/essemi/es32f0654/drivers/drv_spiflash.c +++ b/bsp/essemi/es32f0654/drivers/drv_spiflash.c @@ -9,18 +9,20 @@ * 2019-11-01 wangyq update libraries */ +#include "board.h" #include + +#if defined(BSP_USING_SPI_FLASH) + #include "spi_flash.h" #include "drv_spiflash.h" #include "spi_flash_sfud.h" #include "drv_spi.h" -#if defined(BSP_USING_SPI_FLASH) int rt_hw_spi_flash_init(void) { - es32f0_spi_device_attach(50, "spi0", "spi00"); - - if (RT_NULL == rt_sfud_flash_probe("W25Q64", "spi00")) + + if (RT_NULL == rt_sfud_flash_probe(ES_DEVICE_NAME_SPI_FALSH_DEV, ES_DEVICE_NAME_SPI_DEV)) { return -RT_ERROR; }; diff --git a/bsp/essemi/es32f0654/drivers/drv_uart.c b/bsp/essemi/es32f0654/drivers/drv_uart.c index 4ebd18f826..45f42eed78 100644 --- a/bsp/essemi/es32f0654/drivers/drv_uart.c +++ b/bsp/essemi/es32f0654/drivers/drv_uart.c @@ -3,19 +3,30 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes * 2019-01-23 wangyq the first version - * 2019-11-01 wangyq update libraries + * 2019-11-01 wangyq update libraries + * 2021-04-20 liuhy the second version */ #include #include #include #include "board.h" -#include "drv_uart.h" -#include -#include +#include "es_conf_info_uart.h" #ifdef RT_USING_SERIAL @@ -24,151 +35,13 @@ struct es32_uart { uart_handle_t huart; IRQn_Type irq; -}; +}; -static rt_err_t es32f0x_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +/* es32 usart driver */ +struct es32_usart { - gpio_init_t gpio_initstructure; - struct es32_uart *uart; - RT_ASSERT(serial != RT_NULL); - RT_ASSERT(cfg != RT_NULL); - uart = (struct es32_uart *)serial->parent.user_data; - - /* Initialize tx pin */ - gpio_initstructure.mode = GPIO_MODE_OUTPUT; - gpio_initstructure.odos = GPIO_PUSH_PULL; - gpio_initstructure.pupd = GPIO_PUSH_UP; - gpio_initstructure.odrv = GPIO_OUT_DRIVE_NORMAL; - gpio_initstructure.flt = GPIO_FILTER_DISABLE; - gpio_initstructure.type = GPIO_TYPE_TTL; - -#ifdef BSP_USING_UART0 - gpio_initstructure.func = GPIO_FUNC_3; - ald_gpio_init(GPIOB, GPIO_PIN_10, &gpio_initstructure); - - /* Initialize rx pin ,the same as txpin except mode */ - gpio_initstructure.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOB, GPIO_PIN_11, &gpio_initstructure); -#endif /* uart0 gpio init */ - -#ifdef BSP_USING_UART1 - gpio_initstructure.func = GPIO_FUNC_3; - ald_gpio_init(GPIOC, GPIO_PIN_10, &gpio_initstructure); - - /* Initialize rx pin ,the same as txpin except mode */ - gpio_initstructure.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOC, GPIO_PIN_11, &gpio_initstructure); -#endif /* uart1 gpio init */ - -#ifdef BSP_USING_UART2 - gpio_initstructure.func = GPIO_FUNC_5; - ald_gpio_init(GPIOC, GPIO_PIN_12, &gpio_initstructure); - - /* Initialize rx pin ,the same as txpin except mode */ - gpio_initstructure.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOD, GPIO_PIN_2, &gpio_initstructure); -#endif /* uart2 gpio init */ - -#ifdef BSP_USING_UART3 - gpio_initstructure.func = GPIO_FUNC_4; - ald_gpio_init(GPIOC, GPIO_PIN_4, &gpio_initstructure); - - /* Initialize rx pin ,the same as txpin except mode */ - gpio_initstructure.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOC, GPIO_PIN_5, &gpio_initstructure); -#endif /* uart3 gpio init */ - - uart->huart.init.mode = UART_MODE_UART; - uart->huart.init.baud = cfg->baud_rate; - uart->huart.init.word_length = (uart_word_length_t)(cfg->data_bits - 5); - uart->huart.init.parity = (uart_parity_t)(cfg->parity == PARITY_EVEN ? UART_PARITY_EVEN : cfg->parity); - uart->huart.init.fctl = UART_HW_FLOW_CTL_DISABLE; - ald_uart_init(&uart->huart); - - if (cfg->bit_order == BIT_ORDER_MSB) - { - UART_MSB_FIRST_ENABLE(&uart->huart); - } - else - { - UART_MSB_FIRST_DISABLE(&uart->huart); - } - - if (cfg->invert == NRZ_INVERTED) - { - UART_DATA_INV_ENABLE(&uart->huart); - } - else - { - UART_DATA_INV_DISABLE(&uart->huart); - } - - /* enable rx int */ - ald_uart_interrupt_config(&uart->huart, UART_IT_RXRD, ENABLE); - - return RT_EOK; -} - -static rt_err_t es32f0x_control(struct rt_serial_device *serial, int cmd, void *arg) -{ - struct es32_uart *uart; - RT_ASSERT(serial != RT_NULL); - - uart = (struct es32_uart *)serial->parent.user_data; - switch (cmd) - { - case RT_DEVICE_CTRL_CLR_INT: - /* disable rx irq */ - NVIC_DisableIRQ(uart->irq); - /* disable interrupt */ - ald_uart_interrupt_config(&uart->huart, UART_IT_RXRD, DISABLE); - break; - - case RT_DEVICE_CTRL_SET_INT: - /* enable rx irq */ - NVIC_EnableIRQ(uart->irq); - /* enable interrupt */ - ald_uart_interrupt_config(&uart->huart, UART_IT_RXRD, ENABLE); - break; - } - - return RT_EOK; -} - -static int es32f0x_putc(struct rt_serial_device *serial, char c) -{ - struct es32_uart *uart; - RT_ASSERT(serial != RT_NULL); - uart = (struct es32_uart *)serial->parent.user_data; - - while (!(uart->huart.perh->SR & 0x40)) ; - WRITE_REG(uart->huart.perh->TBR, c); - - return 1; -} - -static int es32f0x_getc(struct rt_serial_device *serial) -{ - int ch = -1; - struct es32_uart *uart; - - RT_ASSERT(serial != RT_NULL); - uart = (struct es32_uart *)serial->parent.user_data; - - if (uart->huart.perh->SR & 0x01) - { - ch = (uint8_t)(uart->huart.perh->RBR & 0xFF); - } - - return ch; -} - -static const struct rt_uart_ops es32f0x_uart_ops = -{ - es32f0x_configure, - es32f0x_control, - es32f0x_putc, - es32f0x_getc, + usart_handle_t huart; + IRQn_Type irq; }; #ifdef BSP_USING_UART0 @@ -266,19 +139,380 @@ void BS16T2_UART3_Handler(void) rt_interrupt_leave(); } #endif /* BSP_USING_UART3 */ + +#ifdef BSP_USING_USART0 +/* USART0 device driver structure */ +struct es32_usart usart0 = +{ + {USART0}, + USART0_IRQn +}; + +struct rt_serial_device serial4; + +void USART0_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + if (USART0->STAT & USART_FLAG_RXNE) + { + rt_hw_serial_isr(&serial4, RT_SERIAL_EVENT_RX_IND); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_USART0 */ + +#ifdef BSP_USING_USART1 +/* USART1 device driver structure */ +struct es32_usart usart1 = +{ + {USART1}, + USART1_IRQn +}; + +struct rt_serial_device serial5; + +void USART1_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + if (USART1->STAT & USART_FLAG_RXNE) + { + rt_hw_serial_isr(&serial5, RT_SERIAL_EVENT_RX_IND); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_USART1 */ + +static rt_err_t es32f0x_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + gpio_init_t gpio_initstructure; + struct es32_uart *uart; + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + uart = (struct es32_uart *)serial->parent.user_data; + + /* Initialize tx pin */ + gpio_initstructure.mode = GPIO_MODE_OUTPUT; + gpio_initstructure.odos = GPIO_PUSH_PULL; + gpio_initstructure.pupd = GPIO_PUSH_UP; + gpio_initstructure.odrv = GPIO_OUT_DRIVE_NORMAL; + gpio_initstructure.flt = GPIO_FILTER_DISABLE; + gpio_initstructure.type = GPIO_TYPE_TTL; + + if((uint32_t)(uart->huart.perh) > (uint32_t)UART3) /*根据外设物理地址区分UART和USART*/ + { + /*USART*/ + struct es32_usart *usart= (struct es32_usart *)serial->parent.user_data; + +#ifdef BSP_USING_USART0 + if(usart == (&usart0)) + { +#if defined(ES_USART0_TX_GPIO_FUNC)&&defined(ES_USART0_TX_GPIO_PORT)&&defined(ES_USART0_TX_GPIO_PIN) + gpio_initstructure.func = ES_USART0_TX_GPIO_FUNC; + ald_gpio_init(ES_USART0_TX_GPIO_PORT, ES_USART0_TX_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_USART0_RX_GPIO_FUNC)&&defined(ES_USART0_RX_GPIO_PORT)&&defined(ES_USART0_RX_GPIO_PIN) + /* Initialize rx pin ,the same as txpin except mode */ + gpio_initstructure.mode = GPIO_MODE_INPUT; + gpio_initstructure.func = ES_USART0_RX_GPIO_FUNC; + ald_gpio_init(ES_USART0_RX_GPIO_PORT, ES_USART0_RX_GPIO_PIN, &gpio_initstructure); +#endif + ald_cmu_perh_clock_config(CMU_PERH_USART0, ENABLE); + } + +#endif /* usart0 gpio init */ + +#ifdef BSP_USING_USART1 + if(usart == (&usart1)) + { +#if defined(ES_USART1_TX_GPIO_FUNC)&&defined(ES_USART1_TX_GPIO_PORT)&&defined(ES_USART1_TX_GPIO_PIN) + gpio_initstructure.func = ES_USART1_TX_GPIO_FUNC; + ald_gpio_init(ES_USART1_TX_GPIO_PORT, ES_USART1_TX_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_USART1_RX_GPIO_FUNC)&&defined(ES_USART1_RX_GPIO_PORT)&&defined(ES_USART1_RX_GPIO_PIN) + /* Initialize rx pin ,the same as txpin except mode */ + gpio_initstructure.mode = GPIO_MODE_INPUT; + gpio_initstructure.func = ES_USART1_RX_GPIO_FUNC; + ald_gpio_init(ES_USART1_RX_GPIO_PORT, ES_USART1_RX_GPIO_PIN, &gpio_initstructure); +#endif + + ald_cmu_perh_clock_config(CMU_PERH_USART1, ENABLE); + } +#endif /* usart1 gpio init */ + + usart->huart.init.mode = USART_MODE_TX_RX; + usart->huart.init.baud = cfg->baud_rate; + usart->huart.init.word_length = (usart_word_length_t)(cfg->data_bits - 8); + usart->huart.init.stop_bits = ((cfg->stop_bits == STOP_BITS_1) ? USART_STOP_BITS_1 : USART_STOP_BITS_2); + usart->huart.init.parity = (usart_parity_t)(cfg->parity == PARITY_NONE ? cfg->parity : (4 - cfg->parity) ); + usart->huart.init.fctl = USART_HW_FLOW_CTL_NONE; + + ald_usart_init(&usart->huart); + + /* + BIT_ORDER_LSB BIT_ORDER_MSB + NRZ_NORMAL NRZ_INVERTED + 无相关寄存器*/ + + /* enable rx int */ + ald_usart_interrupt_config(&usart->huart, USART_IT_RXNE, ENABLE); + + } + else + { + /*UART*/ + +#ifdef BSP_USING_UART0 + if(uart == (&uart0)) + { +#if defined(ES_UART0_TX_GPIO_FUNC)&&defined(ES_UART0_TX_GPIO_PORT)&&defined(ES_UART0_TX_GPIO_PIN) + gpio_initstructure.func = ES_UART0_TX_GPIO_FUNC; + ald_gpio_init(ES_UART0_TX_GPIO_PORT, ES_UART0_TX_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_UART0_RX_GPIO_FUNC)&&defined(ES_UART0_RX_GPIO_PORT)&&defined(ES_UART0_RX_GPIO_PIN) + /* Initialize rx pin ,the same as txpin except mode */ + gpio_initstructure.mode = GPIO_MODE_INPUT; + gpio_initstructure.func = ES_UART0_RX_GPIO_FUNC; + ald_gpio_init(ES_UART0_RX_GPIO_PORT, ES_UART0_RX_GPIO_PIN, &gpio_initstructure); +#endif + ald_cmu_perh_clock_config(CMU_PERH_UART0, ENABLE); + } + +#endif /* uart0 gpio init */ + +#ifdef BSP_USING_UART1 + if(uart == (&uart1)) + { +#if defined(ES_UART1_TX_GPIO_FUNC)&&defined(ES_UART1_TX_GPIO_PORT)&&defined(ES_UART1_TX_GPIO_PIN) + gpio_initstructure.func = ES_UART1_TX_GPIO_FUNC; + ald_gpio_init(ES_UART1_TX_GPIO_PORT, ES_UART1_TX_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_UART1_RX_GPIO_FUNC)&&defined(ES_UART1_RX_GPIO_PORT)&&defined(ES_UART1_RX_GPIO_PIN) + /* Initialize rx pin ,the same as txpin except mode */ + gpio_initstructure.mode = GPIO_MODE_INPUT; + gpio_initstructure.func = ES_UART1_RX_GPIO_FUNC; + ald_gpio_init(ES_UART1_RX_GPIO_PORT, ES_UART1_RX_GPIO_PIN, &gpio_initstructure); +#endif + + ald_cmu_perh_clock_config(CMU_PERH_UART1, ENABLE); + } +#endif /* uart1 gpio init */ + +#ifdef BSP_USING_UART2 + if(uart == (&uart2)) + { +#if defined(ES_UART2_TX_GPIO_FUNC)&&defined(ES_UART2_TX_GPIO_PORT)&&defined(ES_UART2_TX_GPIO_PIN) + gpio_initstructure.func = ES_UART2_TX_GPIO_FUNC; + ald_gpio_init(ES_UART2_TX_GPIO_PORT, ES_UART2_TX_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_UART2_RX_GPIO_FUNC)&&defined(ES_UART2_RX_GPIO_PORT)&&defined(ES_UART2_RX_GPIO_PIN) + /* Initialize rx pin ,the same as txpin except mode */ + gpio_initstructure.mode = GPIO_MODE_INPUT; + gpio_initstructure.func = ES_UART2_RX_GPIO_FUNC; + ald_gpio_init(ES_UART2_RX_GPIO_PORT, ES_UART2_RX_GPIO_PIN, &gpio_initstructure); +#endif + + ald_cmu_perh_clock_config(CMU_PERH_UART2, ENABLE); + } +#endif /* uart2 gpio init */ + +#ifdef BSP_USING_UART3 + if(uart == (&uart3)) + { +#if defined(ES_UART3_TX_GPIO_FUNC)&&defined(ES_UART3_TX_GPIO_PORT)&&defined(ES_UART3_TX_GPIO_PIN) + gpio_initstructure.func = ES_UART3_TX_GPIO_FUNC; + ald_gpio_init(ES_UART3_TX_GPIO_PORT, ES_UART3_TX_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_UART3_RX_GPIO_FUNC)&&defined(ES_UART3_RX_GPIO_PORT)&&defined(ES_UART3_RX_GPIO_PIN) + /* Initialize rx pin ,the same as txpin except mode */ + gpio_initstructure.mode = GPIO_MODE_INPUT; + gpio_initstructure.func = ES_UART3_RX_GPIO_FUNC; + ald_gpio_init(ES_UART3_RX_GPIO_PORT, ES_UART3_RX_GPIO_PIN, &gpio_initstructure); +#endif + + ald_cmu_perh_clock_config(CMU_PERH_UART3, ENABLE); + } +#endif /* uart3 gpio init */ + + uart->huart.init.mode = UART_MODE_UART; + uart->huart.init.baud = cfg->baud_rate; + uart->huart.init.word_length = (uart_word_length_t)(cfg->data_bits - 5); + uart->huart.init.stop_bits = (uart_stop_bits_t)cfg->stop_bits; + uart->huart.init.parity = (uart_parity_t)(cfg->parity == PARITY_EVEN ? UART_PARITY_EVEN : cfg->parity); + uart->huart.init.fctl = UART_HW_FLOW_CTL_DISABLE; + + ald_uart_init(&uart->huart); + + if (cfg->bit_order == BIT_ORDER_MSB) + { + UART_MSB_FIRST_ENABLE(&uart->huart); + } + else + { + UART_MSB_FIRST_DISABLE(&uart->huart); + } + + if (cfg->invert == NRZ_INVERTED) + { + UART_DATA_INV_ENABLE(&uart->huart); + } + else + { + UART_DATA_INV_DISABLE(&uart->huart); + } + + /* enable rx int */ + ald_uart_interrupt_config(&uart->huart, UART_IT_RXRD, ENABLE); + + } + + + return RT_EOK; +} + +static rt_err_t es32f0x_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct es32_uart *uart; + RT_ASSERT(serial != RT_NULL); + + uart = (struct es32_uart *)serial->parent.user_data; + + if((uint32_t)(uart->huart.perh) > (uint32_t)UART3) /*根据外设物理地址区分UART和USART*/ + { + /*USART*/ + struct es32_usart *usart= (struct es32_usart *)serial->parent.user_data; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + NVIC_DisableIRQ(usart->irq); + /* disable interrupt */ + ald_usart_interrupt_config(&usart->huart, USART_IT_RXNE, DISABLE); + break; + + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + NVIC_EnableIRQ(usart->irq); + /* enable interrupt */ + ald_usart_interrupt_config(&usart->huart, USART_IT_RXNE, ENABLE); + break; + } + + } + else + { + /*UART*/ + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + NVIC_DisableIRQ(uart->irq); + /* disable interrupt */ + ald_uart_interrupt_config(&uart->huart, UART_IT_RXRD, DISABLE); + break; + + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + NVIC_EnableIRQ(uart->irq); + /* enable interrupt */ + ald_uart_interrupt_config(&uart->huart, UART_IT_RXRD, ENABLE); + break; + } + } + + + return RT_EOK; +} + +static int es32f0x_putc(struct rt_serial_device *serial, char c) +{ + struct es32_uart *uart; + RT_ASSERT(serial != RT_NULL); + uart = (struct es32_uart *)serial->parent.user_data; + + if((uint32_t)(uart->huart.perh) > (uint32_t)UART3) /*根据外设物理地址区分UART和USART*/ + { + /*USART*/ + struct es32_usart *usart= (struct es32_usart *)serial->parent.user_data; + while (!(usart->huart.perh->STAT & USART_STAT_TXEMPIF_MSK)) ; + WRITE_REG(usart->huart.perh->DATA, c); + } + else + { + /*UART*/ + while (!(uart->huart.perh->SR & 0x40)) ; + WRITE_REG(uart->huart.perh->TBR, c); + } + + return 1; +} + +static int es32f0x_getc(struct rt_serial_device *serial) +{ + int ch = -1; + struct es32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct es32_uart *)serial->parent.user_data; + + if((uint32_t)(uart->huart.perh) > (uint32_t)UART3) /*根据外设物理地址区分UART和USART*/ + { + /*USART*/ + struct es32_usart *usart= (struct es32_usart *)serial->parent.user_data; + if (usart->huart.perh->STAT & USART_STAT_RXNEIF_MSK) + { + ch = (uint8_t)(usart->huart.perh->DATA & 0xFF); + } + } + else + { + /*UART*/ + if (uart->huart.perh->SR & 0x01) + { + ch = (uint8_t)(uart->huart.perh->RBR & 0xFF); + } + } + + return ch; +} + +static const struct rt_uart_ops es32f0x_uart_ops = +{ + es32f0x_configure, + es32f0x_control, + es32f0x_putc, + es32f0x_getc, +}; int rt_hw_uart_init(void) { +#if (defined(BSP_USING_UART0)||defined(BSP_USING_UART1)||defined(BSP_USING_UART2)||defined(BSP_USING_UART3)) struct es32_uart *uart; - struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; +#endif +#if (defined(BSP_USING_USART0)||defined(BSP_USING_USART1)) + struct es32_usart *usart; +#endif #ifdef BSP_USING_UART0 uart = &uart0; serial0.ops = &es32f0x_uart_ops; - serial0.config = config; + serial0.config = (struct serial_configure)ES_UART0_CONFIG; /* register UART0 device */ - rt_hw_serial_register(&serial0, "uart0", + rt_hw_serial_register(&serial0, ES_DEVICE_NAME_UART0, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); #endif /* BSP_USING_UART0 */ @@ -286,10 +520,10 @@ int rt_hw_uart_init(void) #ifdef BSP_USING_UART1 uart = &uart1; serial1.ops = &es32f0x_uart_ops; - serial1.config = config; + serial1.config = (struct serial_configure)ES_UART1_CONFIG; /* register UART1 device */ - rt_hw_serial_register(&serial1, "uart1", + rt_hw_serial_register(&serial1, ES_DEVICE_NAME_UART1, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); #endif /* BSP_USING_UART1 */ @@ -297,10 +531,10 @@ int rt_hw_uart_init(void) #ifdef BSP_USING_UART2 uart = &uart2; serial2.ops = &es32f0x_uart_ops; - serial2.config = config; + serial2.config = (struct serial_configure)ES_UART2_CONFIG; /* register UART2 device */ - rt_hw_serial_register(&serial2, "uart2", + rt_hw_serial_register(&serial2, ES_DEVICE_NAME_UART2, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); #endif /* BSP_USING_UART2 */ @@ -308,14 +542,35 @@ int rt_hw_uart_init(void) #ifdef BSP_USING_UART3 uart = &uart3; serial3.ops = &es32f0x_uart_ops; - serial3.config = config; + serial3.config = (struct serial_configure)ES_UART3_CONFIG; /* register UART3 device */ - rt_hw_serial_register(&serial3, "uart3", + rt_hw_serial_register(&serial3, ES_DEVICE_NAME_UART3, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); #endif /* BSP_USING_UART3 */ + +#ifdef BSP_USING_USART0 + usart = &usart0; + serial4.ops = &es32f0x_uart_ops; + serial4.config = (struct serial_configure)ES_USART0_CONFIG; + /* register USART0 device */ + rt_hw_serial_register(&serial4, ES_DEVICE_NAME_USART0, + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + usart); +#endif /* BSP_USING_USART0 */ + +#ifdef BSP_USING_USART1 + usart = &usart1; + serial5.ops = &es32f0x_uart_ops; + serial5.config = (struct serial_configure)ES_USART1_CONFIG; + + /* register USART1 device */ + rt_hw_serial_register(&serial5, ES_DEVICE_NAME_USART1, + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + usart); +#endif /* BSP_USING_USART1 */ return 0; } INIT_BOARD_EXPORT(rt_hw_uart_init); diff --git a/bsp/essemi/es32f0654/drivers/drv_uart.h b/bsp/essemi/es32f0654/drivers/drv_uart.h index e68d67ca1e..a7eb0de41d 100644 --- a/bsp/essemi/es32f0654/drivers/drv_uart.h +++ b/bsp/essemi/es32f0654/drivers/drv_uart.h @@ -3,6 +3,18 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes * 2019-01-23 wangyq the first version diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_acmp.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_acmp.h index 2bbe7437d0..535d7c2770 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_acmp.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_acmp.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_adc.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_adc.h index b5f9532f8d..efad62ab26 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_adc.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_adc.h @@ -9,6 +9,20 @@ * @note * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ****************************************************************************** */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_bkpc.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_bkpc.h index cbaa1c88f8..038ddf635b 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_bkpc.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_bkpc.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_calc.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_calc.h index 283417d843..870c5b536d 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_calc.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_calc.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_can.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_can.h index 196094eaaa..04a5d5ef5e 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_can.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_can.h @@ -10,6 +10,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ****************************************************************************** */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_cmu.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_cmu.h index 648b3c2b50..314c585a8a 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_cmu.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_cmu.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_conf.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_conf.h index 2a91282ab6..673782173a 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_conf.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_conf.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crc.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crc.h index 3ea24ea927..d40e22fcf9 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crc.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crc.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crypt.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crypt.h index 483c15a31e..00be4131f3 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crypt.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crypt.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dbgc.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dbgc.h index 3f695b7e8f..a4e2d75621 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dbgc.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dbgc.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dma.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dma.h index 1fbebd56bf..4d7f6b9787 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dma.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dma.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_flash.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_flash.h index 8858b8b707..ad3148382f 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_flash.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_flash.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_gpio.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_gpio.h index 336c90f977..01df5fd138 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_gpio.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_gpio.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_i2c.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_i2c.h index f421ff168e..27527104ba 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_i2c.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_i2c.h @@ -10,6 +10,20 @@ * @note * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ******************************************************************************** */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_iap.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_iap.h index a777fca4a9..2fa6a4f6ec 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_iap.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_iap.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pis.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pis.h index c17b03cfd9..5b63193f46 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pis.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pis.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pmu.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pmu.h index 264c185b81..be93e204ba 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pmu.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pmu.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rmu.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rmu.h index 164ebb5e3f..6cc63fab8a 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rmu.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rmu.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rtc.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rtc.h index dd5d8ad7ee..fbb6799c17 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rtc.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rtc.h @@ -10,6 +10,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_smartcard.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_smartcard.h index 74401fecc1..291908e6d5 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_smartcard.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_smartcard.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_spi.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_spi.h index 1a7c7c7e5e..5820deadf2 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_spi.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_spi.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_syscfg.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_syscfg.h index 35844c887e..3df2492432 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_syscfg.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_syscfg.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_timer.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_timer.h index 538fc0ca0b..e6f4986947 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_timer.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_timer.h @@ -12,6 +12,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_trng.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_trng.h index 635cb1a90a..202e6f2af8 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_trng.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_trng.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_tsense.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_tsense.h index 410dcb7ff6..dc78ce56cc 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_tsense.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_tsense.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_uart.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_uart.h index 10a351ca19..a240a91b36 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_uart.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_uart.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_usart.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_usart.h index 4f30e2c2a4..b3cd4bf421 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_usart.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_usart.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_wdt.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_wdt.h index 619f777324..2473a8ebb2 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_wdt.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_wdt.h @@ -10,6 +10,20 @@ * @note * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ******************************************************************************** */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/type.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/type.h index 54082f3f21..a892c69bd4 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/type.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/type.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ @@ -22,6 +36,7 @@ extern "C" { #endif #include +#include "es_conf_info_select.h" #if defined (__CC_ARM) diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/utils.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/utils.h index 5ad1dc36a7..165cec6306 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/utils.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/utils.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_acmp.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_acmp.c index e480de1697..cec11372c3 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_acmp.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_acmp.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_adc.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_adc.c index 7f1f522c7a..bf0215740b 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_adc.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_adc.c @@ -24,6 +24,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_bkpc.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_bkpc.c index a3852bdb22..b459fba045 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_bkpc.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_bkpc.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_calc.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_calc.c index ec2400453d..2196ffb99f 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_calc.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_calc.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_can.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_can.c index fb551abdf1..b665165077 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_can.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_can.c @@ -14,6 +14,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** * @verbatim ============================================================================== diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_cmu.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_cmu.c index e43b12c7d1..b6473dc432 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_cmu.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_cmu.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* * @verbatim ============================================================================== diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crc.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crc.c index bf6fde037c..2a69489158 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crc.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crc.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crypt.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crypt.c index ff8f92d9d5..1381bd416f 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crypt.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crypt.c @@ -12,6 +12,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_dma.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_dma.c index f3c125578d..080dff3045 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_dma.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_dma.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* * @verbatim ============================================================================== diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash.c index 44d25a7f76..224843cb01 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash.c @@ -10,6 +10,20 @@ * @note * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. */ #include "ald_flash.h" diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash_ext.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash_ext.c index 44e8fe7d9c..4087b71b01 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash_ext.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash_ext.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* * ********************************************************************************* diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_gpio.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_gpio.c index 08366e9350..153a21d8a6 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_gpio.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_gpio.c @@ -16,6 +16,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* * @verbatim ============================================================================== diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_i2c.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_i2c.c index 82faa31502..a442d73428 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_i2c.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_i2c.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * @verbatim ============================================================================== ##### How to use this driver ##### diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_iap.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_iap.c index ccb9b5170b..61cee32739 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_iap.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_iap.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pis.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pis.c index d9067499ea..c83907e0c2 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pis.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pis.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pmu.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pmu.c index f8b4b94e27..976bae4334 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pmu.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pmu.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rmu.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rmu.c index 2b04f2719c..ec2ec312b6 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rmu.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rmu.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rtc.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rtc.c index 7391045a62..4863178005 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rtc.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rtc.c @@ -18,6 +18,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** * @verbatim ============================================================================== diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_smartcard.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_smartcard.c index 2b3552ab77..5a18e4ed27 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_smartcard.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_smartcard.c @@ -16,6 +16,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* * @verbatim ============================================================================== diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_spi.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_spi.c index f756f6785d..fd154c6c73 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_spi.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_spi.c @@ -17,6 +17,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* @verbatim ============================================================================== diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_timer.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_timer.c index dc0a285368..77d3b14c8f 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_timer.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_timer.c @@ -12,6 +12,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_trng.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_trng.c index 8e4d13a4d0..81a62e6127 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_trng.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_trng.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_tsense.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_tsense.c index 5fcd8311f1..9200f5a33f 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_tsense.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_tsense.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_uart.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_uart.c index 59c2489bfa..3a13a5ea04 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_uart.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_uart.c @@ -17,6 +17,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* * @verbatim ============================================================================== diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_usart.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_usart.c index 1e9ed5c501..8c9c2ef8f1 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_usart.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_usart.c @@ -17,6 +17,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* * @verbatim ============================================================================== diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_wdt.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_wdt.c index d19a0397ab..fe21244fe7 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_wdt.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_wdt.c @@ -10,6 +10,20 @@ * @note * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/utils.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/utils.c index e406c53afc..e74f9d3f7f 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/utils.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/utils.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/project.uvprojx b/bsp/essemi/es32f0654/project.uvprojx index 70c93b4c8e..569397deb8 100644 --- a/bsp/essemi/es32f0654/project.uvprojx +++ b/bsp/essemi/es32f0654/project.uvprojx @@ -336,9 +336,9 @@ 0 - ES32F065x + ES32F065x, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND - applications;.;drivers;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m0;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\spi;..\..\..\components\drivers\include;..\..\..\components\drivers\include;drivers;..\..\..\components\finsh;.;..\..\..\include;libraries\CMSIS\Device\EastSoft\ES32F065x\Include;libraries\CMSIS\Include;libraries\ES32F065x_ALD_StdPeriph_Driver\Include + applications;.;drivers\ES;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m0;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;drivers;..\..\..\components\finsh;.;..\..\..\include;..\..\..\components\libc\compilers\common;libraries\CMSIS\Device\EastSoft\ES32F065x\Include;libraries\CMSIS\Include;libraries\ES32F065x_ALD_StdPeriph_Driver\Include @@ -390,8 +390,13 @@ - cpu + CPU + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + backtrace.c 1 @@ -403,168 +408,34 @@ ..\..\..\libcpu\arm\common\div0.c - showmem.c - 1 - ..\..\..\libcpu\arm\common\showmem.c + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m0\context_rvds.S cpuport.c 1 ..\..\..\libcpu\arm\cortex-m0\cpuport.c - - context_rvds.S - 2 - ..\..\..\libcpu\arm\cortex-m0\context_rvds.S - DeviceDrivers - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 0 - - - - 2 - 0 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 0 - 2 - 2 - 2 - 2 - 2 - 0 - 0 - 2 - 2 - 2 - 2 - 2 - - - - - - - - - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - - - - - - - - - - - can.c - 1 - ..\..\..\components\drivers\can\can.c - - - hwtimer.c - 1 - ..\..\..\components\drivers\hwtimer\hwtimer.c - - - i2c_core.c - 1 - ..\..\..\components\drivers\i2c\i2c_core.c - - - i2c_dev.c - 1 - ..\..\..\components\drivers\i2c\i2c_dev.c - - - i2c-bit-ops.c - 1 - ..\..\..\components\drivers\i2c\i2c-bit-ops.c - pin.c 1 ..\..\..\components\drivers\misc\pin.c - - adc.c - 1 - ..\..\..\components\drivers\misc\adc.c - - - rt_drv_pwm.c - 1 - ..\..\..\components\drivers\misc\rt_drv_pwm.c - - - pm.c - 1 - ..\..\..\components\drivers\pm\pm.c - - - rtc.c - 1 - ..\..\..\components\drivers\rtc\rtc.c - serial.c 1 ..\..\..\components\drivers\serial\serial.c - spi_core.c + waitqueue.c 1 - ..\..\..\components\drivers\spi\spi_core.c - - - spi_dev.c - 1 - ..\..\..\components\drivers\spi\spi_dev.c - - - completion.c - 1 - ..\..\..\components\drivers\src\completion.c - - - dataqueue.c - 1 - ..\..\..\components\drivers\src\dataqueue.c + ..\..\..\components\drivers\src\waitqueue.c pipe.c @@ -572,9 +443,9 @@ ..\..\..\components\drivers\src\pipe.c - ringblk_buf.c + dataqueue.c 1 - ..\..\..\components\drivers\src\ringblk_buf.c + ..\..\..\components\drivers\src\dataqueue.c ringbuffer.c @@ -582,25 +453,25 @@ ..\..\..\components\drivers\src\ringbuffer.c - waitqueue.c + ringblk_buf.c 1 - ..\..\..\components\drivers\src\waitqueue.c + ..\..\..\components\drivers\src\ringblk_buf.c workqueue.c 1 ..\..\..\components\drivers\src\workqueue.c + + completion.c + 1 + ..\..\..\components\drivers\src\completion.c + Drivers - - board.c - 1 - drivers\board.c - drv_gpio.c 1 @@ -611,6 +482,11 @@ 1 drivers\drv_uart.c + + board.c + 1 + drivers\board.c + @@ -621,30 +497,25 @@ 1 ..\..\..\components\finsh\shell.c - - cmd.c - 1 - ..\..\..\components\finsh\cmd.c - msh.c 1 ..\..\..\components\finsh\msh.c + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + Kernel - clock.c + ipc.c 1 - ..\..\..\src\clock.c - - - components.c - 1 - ..\..\..\src\components.c + ..\..\..\src\ipc.c device.c @@ -652,19 +523,9 @@ ..\..\..\src\device.c - idle.c + object.c 1 - ..\..\..\src\idle.c - - - ipc.c - 1 - ..\..\..\src\ipc.c - - - irq.c - 1 - ..\..\..\src\irq.c + ..\..\..\src\object.c kservice.c @@ -672,9 +533,29 @@ ..\..\..\src\kservice.c - mem.c + scheduler.c 1 - ..\..\..\src\mem.c + ..\..\..\src\scheduler.c + + + idle.c + 1 + ..\..\..\src\idle.c + + + irq.c + 1 + ..\..\..\src\irq.c + + + components.c + 1 + ..\..\..\src\components.c + + + timer.c + 1 + ..\..\..\src\timer.c mempool.c @@ -682,19 +563,9 @@ ..\..\..\src\mempool.c - object.c + mem.c 1 - ..\..\..\src\object.c - - - scheduler.c - 1 - ..\..\..\src\scheduler.c - - - signal.c - 1 - ..\..\..\src\signal.c + ..\..\..\src\mem.c thread.c @@ -702,20 +573,155 @@ ..\..\..\src\thread.c - timer.c + clock.c 1 - ..\..\..\src\timer.c + ..\..\..\src\clock.c + + + + + libc + + + time.c + 1 + ..\..\..\components\libc\compilers\common\time.c Libraries + + ald_dma.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_dma.c + + + ald_crc.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_crc.c + + + utils.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\utils.c + + + ald_flash_ext.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_flash_ext.c + + + ald_trng.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_trng.c + + + ald_pmu.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_pmu.c + + + ald_i2c.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_i2c.c + + + ald_can.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_can.c + + + ald_crypt.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_crypt.c + + + ald_spi.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_spi.c + + + ald_rtc.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_rtc.c + + + ald_iap.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_iap.c + + + startup_es32f065x.s + 2 + libraries\CMSIS\Device\EastSoft\ES32F065x\Startup\keil\startup_es32f065x.s + + + ald_usart.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_usart.c + + + ald_uart.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_uart.c + + + ald_tsense.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_tsense.c + + + ald_wdt.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_wdt.c + + + ald_flash.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_flash.c + + + ald_smartcard.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_smartcard.c + + + ald_pis.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_pis.c + + + ald_cmu.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_cmu.c + + + ald_rmu.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_rmu.c + ald_acmp.c 1 libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_acmp.c + + ald_calc.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_calc.c + + + ald_gpio.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_gpio.c + + + ald_timer.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_timer.c + ald_adc.c 1 @@ -726,131 +732,6 @@ 1 libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_bkpc.c - - ald_calc.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_calc.c - - - ald_can.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_can.c - - - ald_cmu.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_cmu.c - - - ald_crc.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_crc.c - - - ald_crypt.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_crypt.c - - - ald_dma.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_dma.c - - - ald_flash.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_flash.c - - - ald_flash_ext.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_flash_ext.c - - - ald_gpio.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_gpio.c - - - ald_i2c.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_i2c.c - - - ald_iap.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_iap.c - - - ald_pis.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_pis.c - - - ald_pmu.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_pmu.c - - - ald_rmu.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_rmu.c - - - ald_rtc.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_rtc.c - - - ald_smartcard.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_smartcard.c - - - ald_spi.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_spi.c - - - ald_timer.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_timer.c - - - ald_trng.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_trng.c - - - ald_tsense.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_tsense.c - - - ald_uart.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_uart.c - - - ald_usart.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_usart.c - - - ald_wdt.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_wdt.c - - - utils.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\utils.c - - - startup_es32f065x.s - 2 - libraries\CMSIS\Device\EastSoft\ES32F065x\Startup\keil\startup_es32f065x.s - diff --git a/bsp/essemi/es32f0654/rtconfig.h b/bsp/essemi/es32f0654/rtconfig.h index 3a173aaa59..9b50643265 100644 --- a/bsp/essemi/es32f0654/rtconfig.h +++ b/bsp/essemi/es32f0654/rtconfig.h @@ -76,16 +76,7 @@ #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL #define RT_SERIAL_RB_BUFSZ 64 -#define RT_USING_CAN -#define RT_USING_HWTIMER -#define RT_USING_I2C -#define RT_USING_I2C_BITOPS #define RT_USING_PIN -#define RT_USING_ADC -#define RT_USING_PWM -#define RT_USING_PM -#define RT_USING_RTC -#define RT_USING_SPI /* Using USB */ diff --git a/bsp/essemi/es32f369x/.config b/bsp/essemi/es32f369x/.config index af456dc765..5e47c69c47 100644 --- a/bsp/essemi/es32f369x/.config +++ b/bsp/essemi/es32f369x/.config @@ -19,8 +19,9 @@ CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_IDLE_THREAD_STACK_SIZE=512 # CONFIG_RT_USING_TIMER_SOFT is not set +# CONFIG_RT_KSERVICE_USING_STDLIB is not set CONFIG_RT_DEBUG=y CONFIG_RT_DEBUG_COLOR=y # CONFIG_RT_DEBUG_INIT_CONFIG is not set @@ -42,7 +43,7 @@ CONFIG_RT_USING_MUTEX=y CONFIG_RT_USING_EVENT=y CONFIG_RT_USING_MAILBOX=y CONFIG_RT_USING_MESSAGEQUEUE=y -# CONFIG_RT_USING_SIGNALS is not set +CONFIG_RT_USING_SIGNALS=y # # Memory Management @@ -52,6 +53,7 @@ CONFIG_RT_USING_MEMPOOL=y # CONFIG_RT_USING_NOHEAP is not set CONFIG_RT_USING_SMALL_MEM=y # CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_USERHEAP is not set # CONFIG_RT_USING_MEMTRACE is not set CONFIG_RT_USING_HEAP=y @@ -114,31 +116,21 @@ CONFIG_RT_PIPE_BUFSZ=512 CONFIG_RT_USING_SERIAL=y # CONFIG_RT_SERIAL_USING_DMA is not set CONFIG_RT_SERIAL_RB_BUFSZ=64 -CONFIG_RT_USING_CAN=y -# CONFIG_RT_CAN_USING_HDR is not set -CONFIG_RT_USING_HWTIMER=y +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set -CONFIG_RT_USING_I2C=y -# CONFIG_RT_I2C_DEBUG is not set -CONFIG_RT_USING_I2C_BITOPS=y -# CONFIG_RT_I2C_BITOPS_DEBUG is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y -CONFIG_RT_USING_ADC=y +# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_DAC is not set -CONFIG_RT_USING_PWM=y +# CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set -CONFIG_RT_USING_PM=y -CONFIG_RT_USING_RTC=y -# CONFIG_RT_USING_ALARM is not set -# CONFIG_RT_USING_SOFT_RTC is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set -CONFIG_RT_USING_SPI=y -# CONFIG_RT_USING_QSPI is not set -# CONFIG_RT_USING_SPI_MSD is not set -# CONFIG_RT_USING_SFUD is not set -# CONFIG_RT_USING_ENC28J60 is not set -# CONFIG_RT_USING_SPI_WIFI is not set +# CONFIG_RT_USING_SPI is not set # CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set @@ -159,7 +151,7 @@ CONFIG_RT_USING_SPI=y # # CONFIG_RT_USING_LIBC is not set # CONFIG_RT_USING_PTHREADS is not set -# CONFIG_RT_LIBC_USING_TIME is not set +CONFIG_RT_LIBC_USING_TIME=y # # Network @@ -305,6 +297,8 @@ CONFIG_RT_USING_SPI=y # CONFIG_PKG_USING_WAVPLAYER is not set # CONFIG_PKG_USING_TJPGD is not set # CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set # # tools packages @@ -319,6 +313,7 @@ CONFIG_RT_USING_SPI=y # CONFIG_PKG_USING_ADBD is not set # CONFIG_PKG_USING_COREMARK is not set # CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set # CONFIG_PKG_USING_NR_MICRO_SHELL is not set # CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set # CONFIG_PKG_USING_LUNAR_CALENDAR is not set @@ -326,6 +321,10 @@ CONFIG_RT_USING_SPI=y # CONFIG_PKG_USING_GPS_RMC is not set # CONFIG_PKG_USING_URLENCODE is not set # CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set # # system packages @@ -352,7 +351,16 @@ CONFIG_RT_USING_SPI=y # CONFIG_PKG_USING_RAMDISK is not set # CONFIG_PKG_USING_MININI is not set # CONFIG_PKG_USING_QBOOT is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# # CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set # CONFIG_PKG_USING_PPOOL is not set # @@ -408,6 +416,10 @@ CONFIG_RT_USING_SPI=y # CONFIG_PKG_USING_WK2124 is not set # CONFIG_PKG_USING_LY68L6400 is not set # CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set # # miscellaneous packages @@ -417,6 +429,7 @@ CONFIG_RT_USING_SPI=y # CONFIG_PKG_USING_FASTLZ is not set # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set # CONFIG_PKG_USING_MULTIBUTTON is not set # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set @@ -437,17 +450,23 @@ CONFIG_RT_USING_SPI=y # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set # CONFIG_PKG_USING_HELLO is not set # CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set # CONFIG_PKG_USING_NNOM is not set # CONFIG_PKG_USING_LIBANN is not set # CONFIG_PKG_USING_ELAPACK is not set # CONFIG_PKG_USING_ARMv7M_DWT is not set # CONFIG_PKG_USING_VT100 is not set -# CONFIG_PKG_USING_TETRIS is not set # CONFIG_PKG_USING_ULAPACK is not set # CONFIG_PKG_USING_UKAL is not set # CONFIG_PKG_USING_CRCLIB is not set + +# +# games: games run on RT-Thread console +# # CONFIG_PKG_USING_THREES is not set # CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set # CONFIG_PKG_USING_LWGPS is not set # CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set CONFIG_SOC_ES32F3696LT=y @@ -487,12 +506,13 @@ CONFIG_BSP_USING_UART0=y # # CAN Drivers # -# CONFIG_BSP_USING_CAN is not set +# CONFIG_BSP_USING_CAN0 is not set # # ADC Drivers # -# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_ADC0 is not set +# CONFIG_BSP_USING_ADC1 is not set # # RTC Drivers @@ -500,16 +520,26 @@ CONFIG_BSP_USING_UART0=y # CONFIG_BSP_USING_RTC is not set # -# HWtimer Drivers +# HWTIMER Drivers # -# CONFIG_BSP_USING_HWTIMER0 is not set -# CONFIG_BSP_USING_HWTIMER1 is not set +# CONFIG_BSP_USING_AD16C4T0_HWTIMER is not set +# CONFIG_BSP_USING_AD16C4T1_HWTIMER is not set +# CONFIG_BSP_USING_GP32C4T0_HWTIMER is not set +# CONFIG_BSP_USING_GP32C4T1_HWTIMER is not set +# CONFIG_BSP_USING_GP16C4T0_HWTIMER is not set +# CONFIG_BSP_USING_GP16C4T1_HWTIMER is not set +# CONFIG_BSP_USING_BS16T0_HWTIMER is not set +# CONFIG_BSP_USING_BS16T1_HWTIMER is not set # # PWM Drivers # -# CONFIG_BSP_USING_PWM0 is not set -# CONFIG_BSP_USING_PWM1 is not set +# CONFIG_BSP_USING_AD16C4T0_PWM is not set +# CONFIG_BSP_USING_AD16C4T1_PWM is not set +# CONFIG_BSP_USING_GP32C4T0_PWM is not set +# CONFIG_BSP_USING_GP32C4T1_PWM is not set +# CONFIG_BSP_USING_GP16C4T0_PWM is not set +# CONFIG_BSP_USING_GP16C4T1_PWM is not set # # PM Drivers diff --git a/bsp/essemi/es32f369x/drivers/ES/Kconfig b/bsp/essemi/es32f369x/drivers/ES/Kconfig new file mode 100644 index 0000000000..9ba55d110e --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/ES/Kconfig @@ -0,0 +1,197 @@ +menu "UART Drivers" + + config BSP_USING_UART0 + bool "Register UART0 " + select RT_USING_SERIAL + default y + + config BSP_USING_UART1 + bool "Register UART1 " + select RT_USING_SERIAL + default n + + config BSP_USING_UART2 + bool "Register UART2 " + select RT_USING_SERIAL + default n + + config BSP_USING_UART3 + bool "Register UART3 " + select RT_USING_SERIAL + default n + + config BSP_USING_UART4 + bool "Register UART4 " + select RT_USING_SERIAL + default n + + config BSP_USING_UART5 + bool "Register UART5 " + select RT_USING_SERIAL + default n + +endmenu + +menu "SPI Drivers" + + config BSP_USING_SPI0 + bool "Register SPI0 " + select RT_USING_SPI + select RT_USING_PIN + default n + + config BSP_USING_SPI1 + bool "Register SPI1 " + select RT_USING_SPI + select RT_USING_PIN + default n + + config BSP_USING_SPI2 + bool "Register SPI2 " + select RT_USING_SPI + select RT_USING_PIN + default n + +endmenu + +menu "I2C Drivers" + + config BSP_USING_I2C0 + bool "Register I2C0 " + select RT_USING_I2C + default n + + config BSP_USING_I2C1 + bool "Register I2C1 " + select RT_USING_I2C + default n + +endmenu + +menu "CAN Drivers" + + config BSP_USING_CAN0 + bool "Register CAN0 " + select RT_USING_CAN + select RT_CAN_USING_HDR + select BSP_USING_CAN + default n + +endmenu + +menu "ADC Drivers" + + config BSP_USING_ADC0 + bool "Register ADC0 " + select RT_USING_ADC + default n + + config BSP_USING_ADC1 + bool "Register ADC1 " + select RT_USING_ADC + default n + +endmenu + +menu "RTC Drivers" + + config BSP_USING_RTC + bool "Register RTC " + select RT_USING_RTC + default n + +endmenu + +menu "HWTIMER Drivers" + + config BSP_USING_AD16C4T0_HWTIMER + bool "Register HWTIMER0 " + select RT_USING_HWTIMER + default n + + config BSP_USING_AD16C4T1_HWTIMER + bool "Register HWTIMER1 " + select RT_USING_HWTIMER + default n + + config BSP_USING_GP32C4T0_HWTIMER + bool "Register HWTIMER2 " + select RT_USING_HWTIMER + default n + + config BSP_USING_GP32C4T1_HWTIMER + bool "Register HWTIMER3 " + select RT_USING_HWTIMER + default n + + config BSP_USING_GP16C4T0_HWTIMER + bool "Register HWTIMER4 " + select RT_USING_HWTIMER + default n + + config BSP_USING_GP16C4T1_HWTIMER + bool "Register HWTIMER5 " + select RT_USING_HWTIMER + default n + + config BSP_USING_BS16T0_HWTIMER + bool "Register HWTIMER6 " + select RT_USING_HWTIMER + default n + + config BSP_USING_BS16T1_HWTIMER + bool "Register HWTIMER7 " + select RT_USING_HWTIMER + default n + +endmenu + +menu "PWM Drivers" + + config BSP_USING_AD16C4T0_PWM + bool "Register PWM0 " + select RT_USING_PWM + default n + depends on !BSP_USING_AD16C4T0_HWTIMER + + config BSP_USING_AD16C4T1_PWM + bool "Register PWM1 " + select RT_USING_PWM + default n + depends on !BSP_USING_AD16C4T1_HWTIMER + + config BSP_USING_GP32C4T0_PWM + bool "Register PWM2 " + select RT_USING_PWM + default n + depends on !BSP_USING_GP32C4T0_HWTIMER + + config BSP_USING_GP32C4T1_PWM + bool "Register PWM3 " + select RT_USING_PWM + default n + depends on !BSP_USING_GP32C4T1_HWTIMER + + config BSP_USING_GP16C4T0_PWM + bool "Register PWM4 " + select RT_USING_PWM + default n + depends on !BSP_USING_GP16C4T0_HWTIMER + + config BSP_USING_GP16C4T1_PWM + bool "Register PWM5 " + select RT_USING_PWM + default n + depends on !BSP_USING_GP16C4T1_HWTIMER + +endmenu + +menu "PM Drivers" + + config BSP_USING_PM + bool "Register PM " + select RT_USING_PM + default n + +endmenu + diff --git a/bsp/essemi/es32f369x/drivers/ES/es_conf_info_adc.h b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_adc.h new file mode 100644 index 0000000000..772f7a0df0 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_adc.h @@ -0,0 +1,97 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_ADC_H__ +#define __ES_CONF_INFO_ADC_H__ + +#include "es_conf_info_map.h" + +#include + + +#define ES_C_ADC_CLK_DIV_1 ADC_CKDIV_1 +#define ES_C_ADC_CLK_DIV_2 ADC_CKDIV_2 +#define ES_C_ADC_CLK_DIV_4 ADC_CKDIV_4 +#define ES_C_ADC_CLK_DIV_8 ADC_CKDIV_8 +#define ES_C_ADC_CLK_DIV_16 ADC_CKDIV_16 +#define ES_C_ADC_CLK_DIV_32 ADC_CKDIV_32 +#define ES_C_ADC_CLK_DIV_64 ADC_CKDIV_64 +#define ES_C_ADC_CLK_DIV_128 ADC_CKDIV_128 + +#define ES_C_ADC_ALIGN_RIGHT ADC_DATAALIGN_RIGHT +#define ES_C_ADC_ALIGN_LEFT ADC_DATAALIGN_LEFT + +#define ES_C_ADC_CONV_BIT_6 ADC_CONV_BIT_6 +#define ES_C_ADC_CONV_BIT_8 ADC_CONV_BIT_8 +#define ES_C_ADC_CONV_BIT_10 ADC_CONV_BIT_10 +#define ES_C_ADC_CONV_BIT_12 ADC_CONV_BIT_12 + +#define ES_C_ADC_SAMPLE_TIME_1 ADC_SAMPLETIME_1 +#define ES_C_ADC_SAMPLE_TIME_2 ADC_SAMPLETIME_2 +#define ES_C_ADC_SAMPLE_TIME_4 ADC_SAMPLETIME_4 +#define ES_C_ADC_SAMPLE_TIME_15 ADC_SAMPLETIME_15 + +/* ADC 配置 */ + +/* codes_main */ + + +#define ES_ADC0_ALIGN ES_C_ADC_ALIGN_RIGHT +#define ES_ADC1_ALIGN ES_C_ADC_ALIGN_RIGHT +#define ES_ADC1_DATA_BIT ES_C_ADC_CONV_BIT_12 +#define ES_ADC0_DATA_BIT ES_C_ADC_CONV_BIT_12 + +#ifndef ES_DEVICE_NAME_ADC0 +#define ES_DEVICE_NAME_ADC0 "adc0" +#endif +#ifndef ES_DEVICE_NAME_ADC1 +#define ES_DEVICE_NAME_ADC1 "adc1" +#endif + +#ifndef ES_ADC0_CLK_DIV +#define ES_ADC0_CLK_DIV ES_C_ADC_CLK_DIV_128 +#endif +#ifndef ES_ADC0_ALIGN +#define ES_ADC0_ALIGN ES_C_ADC_ALIGN_RIGHT +#endif +#ifndef ES_ADC0_DATA_BIT +#define ES_ADC0_DATA_BIT ES_C_ADC_CONV_BIT_12 +#endif +#ifndef ES_ADC0_NCH_SAMPLETIME +#define ES_ADC0_NCH_SAMPLETIME ES_C_ADC_SAMPLE_TIME_4 +#endif + +#ifndef ES_ADC1_CLK_DIV +#define ES_ADC1_CLK_DIV ES_C_ADC_CLK_DIV_128 +#endif +#ifndef ES_ADC1_ALIGN +#define ES_ADC1_ALIGN ES_C_ADC_ALIGN_RIGHT +#endif +#ifndef ES_ADC1_DATA_BIT +#define ES_ADC1_DATA_BIT ES_C_ADC_CONV_BIT_12 +#endif +#ifndef ES_ADC1_NCH_SAMPLETIME +#define ES_ADC1_NCH_SAMPLETIME ES_C_ADC_SAMPLE_TIME_4 +#endif + +#endif diff --git a/bsp/essemi/es32f369x/drivers/ES/es_conf_info_can.h b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_can.h new file mode 100644 index 0000000000..46df1ed054 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_can.h @@ -0,0 +1,73 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_CAN_H__ +#define __ES_CONF_INFO_CAN_H__ + +#include "es_conf_info_map.h" +#include +#include + + +/*默认的CAN硬件过滤器的编号 0 */ +#define ES_C_CAN_DEFAULT_FILTER_NUMBER 0 + +/*硬件过滤器，过滤帧类型*/ +#define ES_C_CAN_FILTER_FRAME_TYPE 0 + + +#define ES_C_CAN_SJW_NUM_1 CAN_SJW_1 +#define ES_C_CAN_SJW_NUM_2 CAN_SJW_2 +#define ES_C_CAN_SJW_NUM_3 CAN_SJW_3 +#define ES_C_CAN_SJW_NUM_4 CAN_SJW_4 + + + +/* CAN 配置 */ + +/* codes_main */ + + + +#ifndef ES_DEVICE_NAME_CAN0 +#define ES_DEVICE_NAME_CAN0 "can0" +#endif + +#ifndef ES_CAN0_AUTO_BAN_RE_T +#define ES_CAN0_AUTO_BAN_RE_T ES_C_ENABLE +#endif +#ifndef ES_CAN0_SPEED +#define ES_CAN0_SPEED 1000000 +#endif +#ifndef ES_CAN0_SJW +#define ES_CAN0_SJW ES_C_CAN_SJW_NUM_4 +#endif + +#define ES_CAN0_CONFIG \ +{ \ + ES_CAN0_SPEED, \ + RT_CANMSG_BOX_SZ, \ + RT_CANSND_BOX_NUM, \ + RT_CAN_MODE_NORMAL, \ +}; +#endif diff --git a/bsp/essemi/es32f369x/drivers/ES/es_conf_info_cmu.h b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_cmu.h new file mode 100644 index 0000000000..1c5e6a829a --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_cmu.h @@ -0,0 +1,89 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_CMU_H__ +#define __ES_CONF_INFO_CMU_H__ + + +#include + + +/* 时钟树 配置 */ + +#define ES_C_MUL_9 CMU_PLL1_OUTPUT_36M +#define ES_C_MUL_12 CMU_PLL1_OUTPUT_48M +#define ES_C_MUL_18 CMU_PLL1_OUTPUT_72M +#define ES_C_MUL_24 CMU_PLL1_OUTPUT_96M + +#define ES_C_DIV_1 CMU_DIV_1 +#define ES_C_DIV_2 CMU_DIV_2 +#define ES_C_DIV_4 CMU_DIV_4 +#define ES_C_DIV_8 CMU_DIV_8 +#define ES_C_DIV_16 CMU_DIV_16 +#define ES_C_DIV_32 CMU_DIV_32 +#define ES_C_DIV_64 CMU_DIV_64 +#define ES_C_DIV_128 CMU_DIV_128 +#define ES_C_DIV_256 CMU_DIV_256 +#define ES_C_DIV_512 CMU_DIV_512 +#define ES_C_DIV_1024 CMU_DIV_1024 +#define ES_C_DIV_2048 CMU_DIV_2048 +#define ES_C_DIV_4096 CMU_DIV_4096 + +#define ES_C_HOSC_DIV_1 CMU_PLL1_INPUT_HOSC +#define ES_C_HOSC_DIV_2 CMU_PLL1_INPUT_HOSC_2 +#define ES_C_HOSC_DIV_3 CMU_PLL1_INPUT_HOSC_3 +#define ES_C_HOSC_DIV_4 CMU_PLL1_INPUT_HOSC_4 +#define ES_C_HOSC_DIV_5 CMU_PLL1_INPUT_HOSC_5 +#define ES_C_HOSC_DIV_6 CMU_PLL1_INPUT_HOSC_6 +#define ES_C_HRC_DIV_6 CMU_PLL1_INPUT_HRC_6 + + + + + +#define ES_PLL1_REFER_CLK ES_C_HOSC_DIV_3 +#define ES_PLL1_OUT_CLK ES_C_MUL_18 +#define ES_CMU_PLL1_EN ES_C_ENABLE +#define ES_CMU_PLL1_SAFE_EN ES_C_DISABLE +#define ES_CMU_LOSC_EN ES_C_ENABLE +#define ES_CMU_LRC_EN ES_C_ENABLE +#define ES_CMU_HOSC_EN ES_C_ENABLE +#define ES_CMU_HRC_EN ES_C_ENABLE +#define ES_CMU_SYS_DIV ES_C_DIV_1 +#define ES_CMU_HCLK_1_DIV ES_C_DIV_2 +#define ES_CMU_HCLK_2_DIV ES_C_DIV_2 +#define ES_CMU_PCLK_1_DIV ES_C_DIV_2 +#define ES_CMU_PCLK_2_DIV ES_C_DIV_4 +#define ES_SYS_CLK_SOURSE CMU_CLOCK_PLL1 +#define ES_PLL_CLK 72000000 +#define ES_SYS_SOURCE_CLK 72000000 +#define ES_SYS_CLK 72000000 +#define ES_PCLK1_CLK 36000000 +#define ES_PCLK2_CLK 18000000 +#define ES_HCLK1_CLK 36000000 +#define ES_HCLK2_CLK 36000000 +#define ES_CMU_EXTERN_CLK_LOSC 32768 +#define ES_CMU_EXTERN_CLK_HOSC 12000000 + + +#endif diff --git a/bsp/essemi/es32f369x/drivers/ES/es_conf_info_gpio.h b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_gpio.h new file mode 100644 index 0000000000..7748e5fda2 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_gpio.h @@ -0,0 +1,5157 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_GPIO_H__ +#define __ES_CONF_INFO_GPIO_H__ + +#include "es_conf_info_map.h" + +#include +#include +#include + +/* GPIO 配置 */ + +typedef struct { + uint8_t pin; + uint8_t pin_mode; + uint8_t pin_level; + uint8_t irq_en; + uint8_t irq_mode; + void (*callback)(void *arg); +} gpio_conf_t; + +/*参数的定义*/ + +#define ES_C_GPIO_LEVEL_HIGH PIN_HIGH +#define ES_C_GPIO_LEVEL_LOW PIN_LOW + +#define ES_C_GPIO_MODE_OUTPUT PIN_MODE_OUTPUT +#define ES_C_GPIO_MODE_INPUT PIN_MODE_INPUT +#define ES_C_GPIO_MODE_INPUT_PULLUP PIN_MODE_INPUT_PULLUP +#define ES_C_GPIO_MODE_INPUT_PULLDOWN PIN_MODE_INPUT_PULLDOWN +#define ES_C_GPIO_MODE_OUTPUT_OD PIN_MODE_OUTPUT_OD + +#define ES_C_GPIO_IRQ_ENABLE PIN_IRQ_ENABLE +#define ES_C_GPIO_IRQ_DISABLE PIN_IRQ_DISABLE + +#define ES_C_GPIO_IRQ_MODE_FALL PIN_IRQ_MODE_FALLING +#define ES_C_GPIO_IRQ_MODE_RISE PIN_IRQ_MODE_RISING +#define ES_C_GPIO_IRQ_MODE_R_F PIN_IRQ_MODE_RISING_FALLING + + + + + +/* codes_main */ + + + + +#ifndef ES_DEVICE_NAME_PIN +#define ES_DEVICE_NAME_PIN "pin" +#endif + +/*GPIO外部中断回调函数控制需要，补充是否中断*/ +#if 11111 + +#ifndef ES_INIT_GPIO_A_0_IRQ_EN +#define ES_INIT_GPIO_A_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_1_IRQ_EN +#define ES_INIT_GPIO_A_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_2_IRQ_EN +#define ES_INIT_GPIO_A_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_3_IRQ_EN +#define ES_INIT_GPIO_A_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_4_IRQ_EN +#define ES_INIT_GPIO_A_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_5_IRQ_EN +#define ES_INIT_GPIO_A_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_6_IRQ_EN +#define ES_INIT_GPIO_A_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_7_IRQ_EN +#define ES_INIT_GPIO_A_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_8_IRQ_EN +#define ES_INIT_GPIO_A_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_9_IRQ_EN +#define ES_INIT_GPIO_A_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_10_IRQ_EN +#define ES_INIT_GPIO_A_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_11_IRQ_EN +#define ES_INIT_GPIO_A_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_12_IRQ_EN +#define ES_INIT_GPIO_A_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_13_IRQ_EN +#define ES_INIT_GPIO_A_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_14_IRQ_EN +#define ES_INIT_GPIO_A_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_15_IRQ_EN +#define ES_INIT_GPIO_A_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_0_IRQ_EN +#define ES_INIT_GPIO_B_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_1_IRQ_EN +#define ES_INIT_GPIO_B_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_2_IRQ_EN +#define ES_INIT_GPIO_B_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_3_IRQ_EN +#define ES_INIT_GPIO_B_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_4_IRQ_EN +#define ES_INIT_GPIO_B_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_5_IRQ_EN +#define ES_INIT_GPIO_B_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_6_IRQ_EN +#define ES_INIT_GPIO_B_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_7_IRQ_EN +#define ES_INIT_GPIO_B_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_8_IRQ_EN +#define ES_INIT_GPIO_B_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_9_IRQ_EN +#define ES_INIT_GPIO_B_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_10_IRQ_EN +#define ES_INIT_GPIO_B_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_11_IRQ_EN +#define ES_INIT_GPIO_B_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_12_IRQ_EN +#define ES_INIT_GPIO_B_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_13_IRQ_EN +#define ES_INIT_GPIO_B_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_14_IRQ_EN +#define ES_INIT_GPIO_B_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_15_IRQ_EN +#define ES_INIT_GPIO_B_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_0_IRQ_EN +#define ES_INIT_GPIO_C_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_1_IRQ_EN +#define ES_INIT_GPIO_C_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_2_IRQ_EN +#define ES_INIT_GPIO_C_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_3_IRQ_EN +#define ES_INIT_GPIO_C_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_4_IRQ_EN +#define ES_INIT_GPIO_C_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_5_IRQ_EN +#define ES_INIT_GPIO_C_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_6_IRQ_EN +#define ES_INIT_GPIO_C_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_7_IRQ_EN +#define ES_INIT_GPIO_C_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_8_IRQ_EN +#define ES_INIT_GPIO_C_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_9_IRQ_EN +#define ES_INIT_GPIO_C_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_10_IRQ_EN +#define ES_INIT_GPIO_C_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_11_IRQ_EN +#define ES_INIT_GPIO_C_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_12_IRQ_EN +#define ES_INIT_GPIO_C_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_13_IRQ_EN +#define ES_INIT_GPIO_C_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_14_IRQ_EN +#define ES_INIT_GPIO_C_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_15_IRQ_EN +#define ES_INIT_GPIO_C_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_0_IRQ_EN +#define ES_INIT_GPIO_D_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_1_IRQ_EN +#define ES_INIT_GPIO_D_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_2_IRQ_EN +#define ES_INIT_GPIO_D_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_3_IRQ_EN +#define ES_INIT_GPIO_D_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_4_IRQ_EN +#define ES_INIT_GPIO_D_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_5_IRQ_EN +#define ES_INIT_GPIO_D_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_6_IRQ_EN +#define ES_INIT_GPIO_D_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_7_IRQ_EN +#define ES_INIT_GPIO_D_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_8_IRQ_EN +#define ES_INIT_GPIO_D_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_9_IRQ_EN +#define ES_INIT_GPIO_D_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_10_IRQ_EN +#define ES_INIT_GPIO_D_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_11_IRQ_EN +#define ES_INIT_GPIO_D_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_12_IRQ_EN +#define ES_INIT_GPIO_D_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_13_IRQ_EN +#define ES_INIT_GPIO_D_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_14_IRQ_EN +#define ES_INIT_GPIO_D_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_15_IRQ_EN +#define ES_INIT_GPIO_D_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_0_IRQ_EN +#define ES_INIT_GPIO_E_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_1_IRQ_EN +#define ES_INIT_GPIO_E_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_2_IRQ_EN +#define ES_INIT_GPIO_E_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_3_IRQ_EN +#define ES_INIT_GPIO_E_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_4_IRQ_EN +#define ES_INIT_GPIO_E_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_5_IRQ_EN +#define ES_INIT_GPIO_E_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_6_IRQ_EN +#define ES_INIT_GPIO_E_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_7_IRQ_EN +#define ES_INIT_GPIO_E_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_8_IRQ_EN +#define ES_INIT_GPIO_E_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_9_IRQ_EN +#define ES_INIT_GPIO_E_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_10_IRQ_EN +#define ES_INIT_GPIO_E_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_11_IRQ_EN +#define ES_INIT_GPIO_E_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_12_IRQ_EN +#define ES_INIT_GPIO_E_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_13_IRQ_EN +#define ES_INIT_GPIO_E_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_14_IRQ_EN +#define ES_INIT_GPIO_E_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_15_IRQ_EN +#define ES_INIT_GPIO_E_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_0_IRQ_EN +#define ES_INIT_GPIO_F_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_1_IRQ_EN +#define ES_INIT_GPIO_F_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_2_IRQ_EN +#define ES_INIT_GPIO_F_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_3_IRQ_EN +#define ES_INIT_GPIO_F_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_4_IRQ_EN +#define ES_INIT_GPIO_F_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_5_IRQ_EN +#define ES_INIT_GPIO_F_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_6_IRQ_EN +#define ES_INIT_GPIO_F_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_7_IRQ_EN +#define ES_INIT_GPIO_F_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_8_IRQ_EN +#define ES_INIT_GPIO_F_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_9_IRQ_EN +#define ES_INIT_GPIO_F_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_10_IRQ_EN +#define ES_INIT_GPIO_F_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_11_IRQ_EN +#define ES_INIT_GPIO_F_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_12_IRQ_EN +#define ES_INIT_GPIO_F_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_13_IRQ_EN +#define ES_INIT_GPIO_F_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_14_IRQ_EN +#define ES_INIT_GPIO_F_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_15_IRQ_EN +#define ES_INIT_GPIO_F_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_0_IRQ_EN +#define ES_INIT_GPIO_G_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_1_IRQ_EN +#define ES_INIT_GPIO_G_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_2_IRQ_EN +#define ES_INIT_GPIO_G_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_3_IRQ_EN +#define ES_INIT_GPIO_G_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_4_IRQ_EN +#define ES_INIT_GPIO_G_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_5_IRQ_EN +#define ES_INIT_GPIO_G_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_6_IRQ_EN +#define ES_INIT_GPIO_G_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_7_IRQ_EN +#define ES_INIT_GPIO_G_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_8_IRQ_EN +#define ES_INIT_GPIO_G_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_9_IRQ_EN +#define ES_INIT_GPIO_G_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_10_IRQ_EN +#define ES_INIT_GPIO_G_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_11_IRQ_EN +#define ES_INIT_GPIO_G_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_12_IRQ_EN +#define ES_INIT_GPIO_G_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_13_IRQ_EN +#define ES_INIT_GPIO_G_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_14_IRQ_EN +#define ES_INIT_GPIO_G_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_15_IRQ_EN +#define ES_INIT_GPIO_G_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_0_IRQ_EN +#define ES_INIT_GPIO_H_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_1_IRQ_EN +#define ES_INIT_GPIO_H_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_2_IRQ_EN +#define ES_INIT_GPIO_H_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_3_IRQ_EN +#define ES_INIT_GPIO_H_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_4_IRQ_EN +#define ES_INIT_GPIO_H_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_5_IRQ_EN +#define ES_INIT_GPIO_H_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_6_IRQ_EN +#define ES_INIT_GPIO_H_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_7_IRQ_EN +#define ES_INIT_GPIO_H_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_8_IRQ_EN +#define ES_INIT_GPIO_H_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_9_IRQ_EN +#define ES_INIT_GPIO_H_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_10_IRQ_EN +#define ES_INIT_GPIO_H_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_11_IRQ_EN +#define ES_INIT_GPIO_H_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_12_IRQ_EN +#define ES_INIT_GPIO_H_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_13_IRQ_EN +#define ES_INIT_GPIO_H_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_14_IRQ_EN +#define ES_INIT_GPIO_H_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_15_IRQ_EN +#define ES_INIT_GPIO_H_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#endif //11111 + + + +/*是否需要 GPIO外部中断回调函数 （控制函数本体+声明）*/ +#if 11111 + +#if (ES_INIT_GPIO_A_0_IRQ_EN)||(ES_INIT_GPIO_B_0_IRQ_EN)||(ES_INIT_GPIO_C_0_IRQ_EN)||(ES_INIT_GPIO_D_0_IRQ_EN)|| \ + (ES_INIT_GPIO_E_0_IRQ_EN)||(ES_INIT_GPIO_F_0_IRQ_EN)||(ES_INIT_GPIO_G_0_IRQ_EN)||(ES_INIT_GPIO_H_0_IRQ_EN) +#define ES_CONF_EXTI_IRQ_0 +#endif + +#if (ES_INIT_GPIO_A_1_IRQ_EN)||(ES_INIT_GPIO_B_1_IRQ_EN)||(ES_INIT_GPIO_C_1_IRQ_EN)||(ES_INIT_GPIO_D_1_IRQ_EN)|| \ + (ES_INIT_GPIO_E_1_IRQ_EN)||(ES_INIT_GPIO_F_1_IRQ_EN)||(ES_INIT_GPIO_G_1_IRQ_EN)||(ES_INIT_GPIO_H_1_IRQ_EN) +#define ES_CONF_EXTI_IRQ_1 +#endif + +#if (ES_INIT_GPIO_A_2_IRQ_EN)||(ES_INIT_GPIO_B_2_IRQ_EN)||(ES_INIT_GPIO_C_2_IRQ_EN)||(ES_INIT_GPIO_D_2_IRQ_EN)|| \ + (ES_INIT_GPIO_E_2_IRQ_EN)||(ES_INIT_GPIO_F_2_IRQ_EN)||(ES_INIT_GPIO_G_2_IRQ_EN)||(ES_INIT_GPIO_H_2_IRQ_EN) +#define ES_CONF_EXTI_IRQ_2 +#endif + +#if (ES_INIT_GPIO_A_3_IRQ_EN)||(ES_INIT_GPIO_B_3_IRQ_EN)||(ES_INIT_GPIO_C_3_IRQ_EN)||(ES_INIT_GPIO_D_3_IRQ_EN)|| \ + (ES_INIT_GPIO_E_3_IRQ_EN)||(ES_INIT_GPIO_F_3_IRQ_EN)||(ES_INIT_GPIO_G_3_IRQ_EN)||(ES_INIT_GPIO_H_3_IRQ_EN) +#define ES_CONF_EXTI_IRQ_3 +#endif + +#if (ES_INIT_GPIO_A_4_IRQ_EN)||(ES_INIT_GPIO_B_4_IRQ_EN)||(ES_INIT_GPIO_C_4_IRQ_EN)||(ES_INIT_GPIO_D_4_IRQ_EN)|| \ + (ES_INIT_GPIO_E_4_IRQ_EN)||(ES_INIT_GPIO_F_4_IRQ_EN)||(ES_INIT_GPIO_G_4_IRQ_EN)||(ES_INIT_GPIO_H_4_IRQ_EN) +#define ES_CONF_EXTI_IRQ_4 +#endif + +#if (ES_INIT_GPIO_A_5_IRQ_EN)||(ES_INIT_GPIO_B_5_IRQ_EN)||(ES_INIT_GPIO_C_5_IRQ_EN)||(ES_INIT_GPIO_D_5_IRQ_EN)|| \ + (ES_INIT_GPIO_E_5_IRQ_EN)||(ES_INIT_GPIO_F_5_IRQ_EN)||(ES_INIT_GPIO_G_5_IRQ_EN)||(ES_INIT_GPIO_H_5_IRQ_EN) +#define ES_CONF_EXTI_IRQ_5 +#endif + +#if (ES_INIT_GPIO_A_6_IRQ_EN)||(ES_INIT_GPIO_B_6_IRQ_EN)||(ES_INIT_GPIO_C_6_IRQ_EN)||(ES_INIT_GPIO_D_6_IRQ_EN)|| \ + (ES_INIT_GPIO_E_6_IRQ_EN)||(ES_INIT_GPIO_F_6_IRQ_EN)||(ES_INIT_GPIO_G_6_IRQ_EN)||(ES_INIT_GPIO_H_6_IRQ_EN) +#define ES_CONF_EXTI_IRQ_6 +#endif + +#if (ES_INIT_GPIO_A_7_IRQ_EN)||(ES_INIT_GPIO_B_7_IRQ_EN)||(ES_INIT_GPIO_C_7_IRQ_EN)||(ES_INIT_GPIO_D_7_IRQ_EN)|| \ + (ES_INIT_GPIO_E_7_IRQ_EN)||(ES_INIT_GPIO_F_7_IRQ_EN)||(ES_INIT_GPIO_G_7_IRQ_EN)||(ES_INIT_GPIO_H_7_IRQ_EN) +#define ES_CONF_EXTI_IRQ_7 +#endif + +#if (ES_INIT_GPIO_A_8_IRQ_EN)||(ES_INIT_GPIO_B_8_IRQ_EN)||(ES_INIT_GPIO_C_8_IRQ_EN)||(ES_INIT_GPIO_D_8_IRQ_EN)|| \ + (ES_INIT_GPIO_E_8_IRQ_EN)||(ES_INIT_GPIO_F_8_IRQ_EN)||(ES_INIT_GPIO_G_8_IRQ_EN)||(ES_INIT_GPIO_H_8_IRQ_EN) +#define ES_CONF_EXTI_IRQ_8 +#endif + +#if (ES_INIT_GPIO_A_9_IRQ_EN)||(ES_INIT_GPIO_B_9_IRQ_EN)||(ES_INIT_GPIO_C_9_IRQ_EN)||(ES_INIT_GPIO_D_9_IRQ_EN)|| \ + (ES_INIT_GPIO_E_9_IRQ_EN)||(ES_INIT_GPIO_F_9_IRQ_EN)||(ES_INIT_GPIO_G_9_IRQ_EN)||(ES_INIT_GPIO_H_9_IRQ_EN) +#define ES_CONF_EXTI_IRQ_9 +#endif + +#if (ES_INIT_GPIO_A_10_IRQ_EN)||(ES_INIT_GPIO_B_10_IRQ_EN)||(ES_INIT_GPIO_C_10_IRQ_EN)||(ES_INIT_GPIO_D_10_IRQ_EN)|| \ + (ES_INIT_GPIO_E_10_IRQ_EN)||(ES_INIT_GPIO_F_10_IRQ_EN)||(ES_INIT_GPIO_G_10_IRQ_EN)||(ES_INIT_GPIO_H_10_IRQ_EN) +#define ES_CONF_EXTI_IRQ_10 +#endif + +#if (ES_INIT_GPIO_A_11_IRQ_EN)||(ES_INIT_GPIO_B_11_IRQ_EN)||(ES_INIT_GPIO_C_11_IRQ_EN)||(ES_INIT_GPIO_D_11_IRQ_EN)|| \ + (ES_INIT_GPIO_E_11_IRQ_EN)||(ES_INIT_GPIO_F_11_IRQ_EN)||(ES_INIT_GPIO_G_11_IRQ_EN)||(ES_INIT_GPIO_H_11_IRQ_EN) +#define ES_CONF_EXTI_IRQ_11 +#endif + +#if (ES_INIT_GPIO_A_12_IRQ_EN)||(ES_INIT_GPIO_B_12_IRQ_EN)||(ES_INIT_GPIO_C_12_IRQ_EN)||(ES_INIT_GPIO_D_12_IRQ_EN)|| \ + (ES_INIT_GPIO_E_12_IRQ_EN)||(ES_INIT_GPIO_F_12_IRQ_EN)||(ES_INIT_GPIO_G_12_IRQ_EN)||(ES_INIT_GPIO_H_12_IRQ_EN) +#define ES_CONF_EXTI_IRQ_12 +#endif + +#if (ES_INIT_GPIO_A_13_IRQ_EN)||(ES_INIT_GPIO_B_13_IRQ_EN)||(ES_INIT_GPIO_C_13_IRQ_EN)||(ES_INIT_GPIO_D_13_IRQ_EN)|| \ + (ES_INIT_GPIO_E_13_IRQ_EN)||(ES_INIT_GPIO_F_13_IRQ_EN)||(ES_INIT_GPIO_G_13_IRQ_EN)||(ES_INIT_GPIO_H_13_IRQ_EN) +#define ES_CONF_EXTI_IRQ_13 +#endif + +#if (ES_INIT_GPIO_A_14_IRQ_EN)||(ES_INIT_GPIO_B_14_IRQ_EN)||(ES_INIT_GPIO_C_14_IRQ_EN)||(ES_INIT_GPIO_D_14_IRQ_EN)|| \ + (ES_INIT_GPIO_E_14_IRQ_EN)||(ES_INIT_GPIO_F_14_IRQ_EN)||(ES_INIT_GPIO_G_14_IRQ_EN)||(ES_INIT_GPIO_H_14_IRQ_EN) +#define ES_CONF_EXTI_IRQ_14 +#endif + +#if (ES_INIT_GPIO_A_15_IRQ_EN)||(ES_INIT_GPIO_B_15_IRQ_EN)||(ES_INIT_GPIO_C_15_IRQ_EN)||(ES_INIT_GPIO_D_15_IRQ_EN)|| \ + (ES_INIT_GPIO_E_15_IRQ_EN)||(ES_INIT_GPIO_F_15_IRQ_EN)||(ES_INIT_GPIO_G_15_IRQ_EN)||(ES_INIT_GPIO_H_15_IRQ_EN) +#define ES_CONF_EXTI_IRQ_15 +#endif + +#endif //11111 + + +/*GPIO外部中断 声明*/ +#if 11111 + +#ifdef ES_CONF_EXTI_IRQ_0 +void irq_pin0_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_1 +void irq_pin1_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_2 +void irq_pin2_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_3 +void irq_pin3_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_4 +void irq_pin4_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_5 +void irq_pin5_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_6 +void irq_pin6_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_7 +void irq_pin7_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_8 +void irq_pin8_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_9 +void irq_pin9_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_10 +void irq_pin10_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_11 +void irq_pin11_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_12 +void irq_pin12_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_13 +void irq_pin13_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_14 +void irq_pin14_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_15 +void irq_pin15_callback(void* arg); +#endif + + +#endif //11111 + + + + +/*是否有配置的管脚*/ +#if defined(ES_INIT_PIN_GPIO_A_0) || defined(ES_INIT_PIN_GPIO_A_1) || defined(ES_INIT_PIN_GPIO_A_2) || defined(ES_INIT_PIN_GPIO_A_3) || \ + defined(ES_INIT_PIN_GPIO_A_4) || defined(ES_INIT_PIN_GPIO_A_5) || defined(ES_INIT_PIN_GPIO_A_6) || defined(ES_INIT_PIN_GPIO_A_7) || \ + defined(ES_INIT_PIN_GPIO_A_8) || defined(ES_INIT_PIN_GPIO_A_9) || defined(ES_INIT_PIN_GPIO_A_10) || defined(ES_INIT_PIN_GPIO_A_11) || \ + defined(ES_INIT_PIN_GPIO_A_12) || defined(ES_INIT_PIN_GPIO_A_13) || defined(ES_INIT_PIN_GPIO_A_14) || defined(ES_INIT_PIN_GPIO_A_15) || \ + defined(ES_INIT_PIN_GPIO_B_0) || defined(ES_INIT_PIN_GPIO_B_1) || defined(ES_INIT_PIN_GPIO_B_2) || defined(ES_INIT_PIN_GPIO_B_3) || \ + defined(ES_INIT_PIN_GPIO_B_4) || defined(ES_INIT_PIN_GPIO_B_5) || defined(ES_INIT_PIN_GPIO_B_6) || defined(ES_INIT_PIN_GPIO_B_7) || \ + defined(ES_INIT_PIN_GPIO_B_8) || defined(ES_INIT_PIN_GPIO_B_9) || defined(ES_INIT_PIN_GPIO_B_10) || defined(ES_INIT_PIN_GPIO_B_11) || \ + defined(ES_INIT_PIN_GPIO_B_12) || defined(ES_INIT_PIN_GPIO_B_13) || defined(ES_INIT_PIN_GPIO_B_14) || defined(ES_INIT_PIN_GPIO_B_15) || \ + defined(ES_INIT_PIN_GPIO_C_0) || defined(ES_INIT_PIN_GPIO_C_1) || defined(ES_INIT_PIN_GPIO_C_2) || defined(ES_INIT_PIN_GPIO_C_3) || \ + defined(ES_INIT_PIN_GPIO_C_4) || defined(ES_INIT_PIN_GPIO_C_5) || defined(ES_INIT_PIN_GPIO_C_6) || defined(ES_INIT_PIN_GPIO_C_7) || \ + defined(ES_INIT_PIN_GPIO_C_8) || defined(ES_INIT_PIN_GPIO_C_9) || defined(ES_INIT_PIN_GPIO_C_10) || defined(ES_INIT_PIN_GPIO_C_11) || \ + defined(ES_INIT_PIN_GPIO_C_12) || defined(ES_INIT_PIN_GPIO_C_13) || defined(ES_INIT_PIN_GPIO_C_14) || defined(ES_INIT_PIN_GPIO_C_15) || \ + defined(ES_INIT_PIN_GPIO_D_0) || defined(ES_INIT_PIN_GPIO_D_1) || defined(ES_INIT_PIN_GPIO_D_2) || defined(ES_INIT_PIN_GPIO_D_3) || \ + defined(ES_INIT_PIN_GPIO_D_4) || defined(ES_INIT_PIN_GPIO_D_5) || defined(ES_INIT_PIN_GPIO_D_6) || defined(ES_INIT_PIN_GPIO_D_7) || \ + defined(ES_INIT_PIN_GPIO_D_8) || defined(ES_INIT_PIN_GPIO_D_9) || defined(ES_INIT_PIN_GPIO_D_10) || defined(ES_INIT_PIN_GPIO_D_11) || \ + defined(ES_INIT_PIN_GPIO_D_12) || defined(ES_INIT_PIN_GPIO_D_13) || defined(ES_INIT_PIN_GPIO_D_14) || defined(ES_INIT_PIN_GPIO_D_15) || \ + defined(ES_INIT_PIN_GPIO_E_0) || defined(ES_INIT_PIN_GPIO_E_1) || defined(ES_INIT_PIN_GPIO_E_2) || defined(ES_INIT_PIN_GPIO_E_3) || \ + defined(ES_INIT_PIN_GPIO_E_4) || defined(ES_INIT_PIN_GPIO_E_5) || defined(ES_INIT_PIN_GPIO_E_6) || defined(ES_INIT_PIN_GPIO_E_7) || \ + defined(ES_INIT_PIN_GPIO_E_8) || defined(ES_INIT_PIN_GPIO_E_9) || defined(ES_INIT_PIN_GPIO_E_10) || defined(ES_INIT_PIN_GPIO_E_11) || \ + defined(ES_INIT_PIN_GPIO_E_12) || defined(ES_INIT_PIN_GPIO_E_13) || defined(ES_INIT_PIN_GPIO_E_14) || defined(ES_INIT_PIN_GPIO_E_15) || \ + defined(ES_INIT_PIN_GPIO_F_0) || defined(ES_INIT_PIN_GPIO_F_1) || defined(ES_INIT_PIN_GPIO_F_2) || defined(ES_INIT_PIN_GPIO_F_3) || \ + defined(ES_INIT_PIN_GPIO_F_4) || defined(ES_INIT_PIN_GPIO_F_5) || defined(ES_INIT_PIN_GPIO_F_6) || defined(ES_INIT_PIN_GPIO_F_7) || \ + defined(ES_INIT_PIN_GPIO_F_8) || defined(ES_INIT_PIN_GPIO_F_9) || defined(ES_INIT_PIN_GPIO_F_10) || defined(ES_INIT_PIN_GPIO_F_11) || \ + defined(ES_INIT_PIN_GPIO_F_12) || defined(ES_INIT_PIN_GPIO_F_13) || defined(ES_INIT_PIN_GPIO_F_14) || defined(ES_INIT_PIN_GPIO_F_15) || \ + defined(ES_INIT_PIN_GPIO_G_0) || defined(ES_INIT_PIN_GPIO_G_1) || defined(ES_INIT_PIN_GPIO_G_2) || defined(ES_INIT_PIN_GPIO_G_3) || \ + defined(ES_INIT_PIN_GPIO_G_4) || defined(ES_INIT_PIN_GPIO_G_5) || defined(ES_INIT_PIN_GPIO_G_6) || defined(ES_INIT_PIN_GPIO_G_7) || \ + defined(ES_INIT_PIN_GPIO_G_8) || defined(ES_INIT_PIN_GPIO_G_9) || defined(ES_INIT_PIN_GPIO_G_10) || defined(ES_INIT_PIN_GPIO_G_11) || \ + defined(ES_INIT_PIN_GPIO_G_12) || defined(ES_INIT_PIN_GPIO_G_13) || defined(ES_INIT_PIN_GPIO_G_14) || defined(ES_INIT_PIN_GPIO_G_15) || \ + defined(ES_INIT_PIN_GPIO_H_0) || defined(ES_INIT_PIN_GPIO_H_1) || defined(ES_INIT_PIN_GPIO_H_2) || defined(ES_INIT_PIN_GPIO_H_3) || \ + defined(ES_INIT_PIN_GPIO_H_4) || defined(ES_INIT_PIN_GPIO_H_5) || defined(ES_INIT_PIN_GPIO_H_6) || defined(ES_INIT_PIN_GPIO_H_7) || \ + defined(ES_INIT_PIN_GPIO_H_8) || defined(ES_INIT_PIN_GPIO_H_9) || defined(ES_INIT_PIN_GPIO_H_10) || defined(ES_INIT_PIN_GPIO_H_11) || \ + defined(ES_INIT_PIN_GPIO_H_12) || defined(ES_INIT_PIN_GPIO_H_13) || defined(ES_INIT_PIN_GPIO_H_14) || defined(ES_INIT_PIN_GPIO_H_15) + +#define ES_INIT_GPIOS + +#endif + + +#ifdef ES_INIT_GPIOS + +static gpio_conf_t gpio_conf_all[] = +{ + +#ifdef ES_INIT_PIN_GPIO_A_0 + + { + ES_PIN_GPIO_A_0 , + +#ifdef ES_INIT_GPIO_A_0_MODE + ES_INIT_GPIO_A_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_0_LEVEL + ES_INIT_GPIO_A_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_0_IRQ_MODE + ES_INIT_GPIO_A_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_1 + + { + ES_PIN_GPIO_A_1 , + +#ifdef ES_INIT_GPIO_A_1_MODE + ES_INIT_GPIO_A_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_1_LEVEL + ES_INIT_GPIO_A_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_1_IRQ_MODE + ES_INIT_GPIO_A_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_2 + + { + ES_PIN_GPIO_A_2 , + +#ifdef ES_INIT_GPIO_A_2_MODE + ES_INIT_GPIO_A_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_2_LEVEL + ES_INIT_GPIO_A_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_2_IRQ_MODE + ES_INIT_GPIO_A_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_3 + + { + ES_PIN_GPIO_A_3 , + +#ifdef ES_INIT_GPIO_A_3_MODE + ES_INIT_GPIO_A_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_3_LEVEL + ES_INIT_GPIO_A_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_3_IRQ_MODE + ES_INIT_GPIO_A_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_4 + + { + ES_PIN_GPIO_A_4 , + +#ifdef ES_INIT_GPIO_A_4_MODE + ES_INIT_GPIO_A_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_4_LEVEL + ES_INIT_GPIO_A_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_4_IRQ_MODE + ES_INIT_GPIO_A_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_5 + + { + ES_PIN_GPIO_A_5 , + +#ifdef ES_INIT_GPIO_A_5_MODE + ES_INIT_GPIO_A_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_5_LEVEL + ES_INIT_GPIO_A_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_5_IRQ_MODE + ES_INIT_GPIO_A_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_6 + + { + ES_PIN_GPIO_A_6 , + +#ifdef ES_INIT_GPIO_A_6_MODE + ES_INIT_GPIO_A_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_6_LEVEL + ES_INIT_GPIO_A_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_6_IRQ_MODE + ES_INIT_GPIO_A_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_7 + + { + ES_PIN_GPIO_A_7 , + +#ifdef ES_INIT_GPIO_A_7_MODE + ES_INIT_GPIO_A_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_7_LEVEL + ES_INIT_GPIO_A_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_7_IRQ_MODE + ES_INIT_GPIO_A_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_8 + + { + ES_PIN_GPIO_A_8 , + +#ifdef ES_INIT_GPIO_A_8_MODE + ES_INIT_GPIO_A_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_8_LEVEL + ES_INIT_GPIO_A_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_8_IRQ_MODE + ES_INIT_GPIO_A_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_9 + + { + ES_PIN_GPIO_A_9 , + +#ifdef ES_INIT_GPIO_A_9_MODE + ES_INIT_GPIO_A_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_9_LEVEL + ES_INIT_GPIO_A_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_9_IRQ_MODE + ES_INIT_GPIO_A_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_10 + + { + ES_PIN_GPIO_A_10 , + +#ifdef ES_INIT_GPIO_A_10_MODE + ES_INIT_GPIO_A_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_10_LEVEL + ES_INIT_GPIO_A_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_10_IRQ_MODE + ES_INIT_GPIO_A_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_11 + + { + ES_PIN_GPIO_A_11 , + +#ifdef ES_INIT_GPIO_A_11_MODE + ES_INIT_GPIO_A_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_11_LEVEL + ES_INIT_GPIO_A_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_11_IRQ_MODE + ES_INIT_GPIO_A_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_12 + + { + ES_PIN_GPIO_A_12 , + +#ifdef ES_INIT_GPIO_A_12_MODE + ES_INIT_GPIO_A_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_12_LEVEL + ES_INIT_GPIO_A_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_12_IRQ_MODE + ES_INIT_GPIO_A_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_13 + + { + ES_PIN_GPIO_A_13 , + +#ifdef ES_INIT_GPIO_A_13_MODE + ES_INIT_GPIO_A_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_13_LEVEL + ES_INIT_GPIO_A_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_13_IRQ_MODE + ES_INIT_GPIO_A_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_14 + + { + ES_PIN_GPIO_A_14 , + +#ifdef ES_INIT_GPIO_A_14_MODE + ES_INIT_GPIO_A_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_14_LEVEL + ES_INIT_GPIO_A_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_14_IRQ_MODE + ES_INIT_GPIO_A_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_15 + + { + ES_PIN_GPIO_A_15 , + +#ifdef ES_INIT_GPIO_A_15_MODE + ES_INIT_GPIO_A_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_15_LEVEL + ES_INIT_GPIO_A_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_15_IRQ_MODE + ES_INIT_GPIO_A_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_0 + + { + ES_PIN_GPIO_B_0 , + +#ifdef ES_INIT_GPIO_B_0_MODE + ES_INIT_GPIO_B_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_0_LEVEL + ES_INIT_GPIO_B_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_0_IRQ_MODE + ES_INIT_GPIO_B_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_1 + + { + ES_PIN_GPIO_B_1 , + +#ifdef ES_INIT_GPIO_B_1_MODE + ES_INIT_GPIO_B_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_1_LEVEL + ES_INIT_GPIO_B_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_1_IRQ_MODE + ES_INIT_GPIO_B_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_2 + + { + ES_PIN_GPIO_B_2 , + +#ifdef ES_INIT_GPIO_B_2_MODE + ES_INIT_GPIO_B_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_2_LEVEL + ES_INIT_GPIO_B_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_2_IRQ_MODE + ES_INIT_GPIO_B_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_3 + + { + ES_PIN_GPIO_B_3 , + +#ifdef ES_INIT_GPIO_B_3_MODE + ES_INIT_GPIO_B_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_3_LEVEL + ES_INIT_GPIO_B_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_3_IRQ_MODE + ES_INIT_GPIO_B_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_4 + + { + ES_PIN_GPIO_B_4 , + +#ifdef ES_INIT_GPIO_B_4_MODE + ES_INIT_GPIO_B_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_4_LEVEL + ES_INIT_GPIO_B_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_4_IRQ_MODE + ES_INIT_GPIO_B_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_5 + + { + ES_PIN_GPIO_B_5 , + +#ifdef ES_INIT_GPIO_B_5_MODE + ES_INIT_GPIO_B_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_5_LEVEL + ES_INIT_GPIO_B_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_5_IRQ_MODE + ES_INIT_GPIO_B_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_6 + + { + ES_PIN_GPIO_B_6 , + +#ifdef ES_INIT_GPIO_B_6_MODE + ES_INIT_GPIO_B_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_6_LEVEL + ES_INIT_GPIO_B_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_6_IRQ_MODE + ES_INIT_GPIO_B_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_7 + + { + ES_PIN_GPIO_B_7 , + +#ifdef ES_INIT_GPIO_B_7_MODE + ES_INIT_GPIO_B_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_7_LEVEL + ES_INIT_GPIO_B_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_7_IRQ_MODE + ES_INIT_GPIO_B_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_8 + + { + ES_PIN_GPIO_B_8 , + +#ifdef ES_INIT_GPIO_B_8_MODE + ES_INIT_GPIO_B_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_8_LEVEL + ES_INIT_GPIO_B_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_8_IRQ_MODE + ES_INIT_GPIO_B_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_9 + + { + ES_PIN_GPIO_B_9 , + +#ifdef ES_INIT_GPIO_B_9_MODE + ES_INIT_GPIO_B_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_9_LEVEL + ES_INIT_GPIO_B_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_9_IRQ_MODE + ES_INIT_GPIO_B_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_10 + + { + ES_PIN_GPIO_B_10 , + +#ifdef ES_INIT_GPIO_B_10_MODE + ES_INIT_GPIO_B_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_10_LEVEL + ES_INIT_GPIO_B_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_10_IRQ_MODE + ES_INIT_GPIO_B_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_11 + + { + ES_PIN_GPIO_B_11 , + +#ifdef ES_INIT_GPIO_B_11_MODE + ES_INIT_GPIO_B_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_11_LEVEL + ES_INIT_GPIO_B_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_11_IRQ_MODE + ES_INIT_GPIO_B_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_12 + + { + ES_PIN_GPIO_B_12 , + +#ifdef ES_INIT_GPIO_B_12_MODE + ES_INIT_GPIO_B_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_12_LEVEL + ES_INIT_GPIO_B_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_12_IRQ_MODE + ES_INIT_GPIO_B_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_13 + + { + ES_PIN_GPIO_B_13 , + +#ifdef ES_INIT_GPIO_B_13_MODE + ES_INIT_GPIO_B_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_13_LEVEL + ES_INIT_GPIO_B_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_13_IRQ_MODE + ES_INIT_GPIO_B_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_14 + + { + ES_PIN_GPIO_B_14 , + +#ifdef ES_INIT_GPIO_B_14_MODE + ES_INIT_GPIO_B_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_14_LEVEL + ES_INIT_GPIO_B_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_14_IRQ_MODE + ES_INIT_GPIO_B_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_15 + + { + ES_PIN_GPIO_B_15 , + +#ifdef ES_INIT_GPIO_B_15_MODE + ES_INIT_GPIO_B_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_15_LEVEL + ES_INIT_GPIO_B_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_15_IRQ_MODE + ES_INIT_GPIO_B_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_0 + + { + ES_PIN_GPIO_C_0 , + +#ifdef ES_INIT_GPIO_C_0_MODE + ES_INIT_GPIO_C_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_0_LEVEL + ES_INIT_GPIO_C_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_0_IRQ_MODE + ES_INIT_GPIO_C_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_1 + + { + ES_PIN_GPIO_C_1 , + +#ifdef ES_INIT_GPIO_C_1_MODE + ES_INIT_GPIO_C_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_1_LEVEL + ES_INIT_GPIO_C_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_1_IRQ_MODE + ES_INIT_GPIO_C_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_2 + + { + ES_PIN_GPIO_C_2 , + +#ifdef ES_INIT_GPIO_C_2_MODE + ES_INIT_GPIO_C_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_2_LEVEL + ES_INIT_GPIO_C_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_2_IRQ_MODE + ES_INIT_GPIO_C_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_3 + + { + ES_PIN_GPIO_C_3 , + +#ifdef ES_INIT_GPIO_C_3_MODE + ES_INIT_GPIO_C_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_3_LEVEL + ES_INIT_GPIO_C_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_3_IRQ_MODE + ES_INIT_GPIO_C_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_4 + + { + ES_PIN_GPIO_C_4 , + +#ifdef ES_INIT_GPIO_C_4_MODE + ES_INIT_GPIO_C_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_4_LEVEL + ES_INIT_GPIO_C_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_4_IRQ_MODE + ES_INIT_GPIO_C_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_5 + + { + ES_PIN_GPIO_C_5 , + +#ifdef ES_INIT_GPIO_C_5_MODE + ES_INIT_GPIO_C_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_5_LEVEL + ES_INIT_GPIO_C_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_5_IRQ_MODE + ES_INIT_GPIO_C_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_6 + + { + ES_PIN_GPIO_C_6 , + +#ifdef ES_INIT_GPIO_C_6_MODE + ES_INIT_GPIO_C_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_6_LEVEL + ES_INIT_GPIO_C_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_6_IRQ_MODE + ES_INIT_GPIO_C_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_7 + + { + ES_PIN_GPIO_C_7 , + +#ifdef ES_INIT_GPIO_C_7_MODE + ES_INIT_GPIO_C_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_7_LEVEL + ES_INIT_GPIO_C_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_7_IRQ_MODE + ES_INIT_GPIO_C_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_8 + + { + ES_PIN_GPIO_C_8 , + +#ifdef ES_INIT_GPIO_C_8_MODE + ES_INIT_GPIO_C_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_8_LEVEL + ES_INIT_GPIO_C_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_8_IRQ_MODE + ES_INIT_GPIO_C_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_9 + + { + ES_PIN_GPIO_C_9 , + +#ifdef ES_INIT_GPIO_C_9_MODE + ES_INIT_GPIO_C_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_9_LEVEL + ES_INIT_GPIO_C_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_9_IRQ_MODE + ES_INIT_GPIO_C_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_10 + + { + ES_PIN_GPIO_C_10 , + +#ifdef ES_INIT_GPIO_C_10_MODE + ES_INIT_GPIO_C_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_10_LEVEL + ES_INIT_GPIO_C_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_10_IRQ_MODE + ES_INIT_GPIO_C_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_11 + + { + ES_PIN_GPIO_C_11 , + +#ifdef ES_INIT_GPIO_C_11_MODE + ES_INIT_GPIO_C_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_11_LEVEL + ES_INIT_GPIO_C_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_11_IRQ_MODE + ES_INIT_GPIO_C_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_12 + + { + ES_PIN_GPIO_C_12 , + +#ifdef ES_INIT_GPIO_C_12_MODE + ES_INIT_GPIO_C_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_12_LEVEL + ES_INIT_GPIO_C_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_12_IRQ_MODE + ES_INIT_GPIO_C_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_13 + + { + ES_PIN_GPIO_C_13 , + +#ifdef ES_INIT_GPIO_C_13_MODE + ES_INIT_GPIO_C_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_13_LEVEL + ES_INIT_GPIO_C_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_13_IRQ_MODE + ES_INIT_GPIO_C_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_14 + + { + ES_PIN_GPIO_C_14 , + +#ifdef ES_INIT_GPIO_C_14_MODE + ES_INIT_GPIO_C_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_14_LEVEL + ES_INIT_GPIO_C_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_14_IRQ_MODE + ES_INIT_GPIO_C_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_15 + + { + ES_PIN_GPIO_C_15 , + +#ifdef ES_INIT_GPIO_C_15_MODE + ES_INIT_GPIO_C_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_15_LEVEL + ES_INIT_GPIO_C_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_15_IRQ_MODE + ES_INIT_GPIO_C_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_0 + + { + ES_PIN_GPIO_D_0 , + +#ifdef ES_INIT_GPIO_D_0_MODE + ES_INIT_GPIO_D_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_0_LEVEL + ES_INIT_GPIO_D_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_0_IRQ_MODE + ES_INIT_GPIO_D_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_1 + + { + ES_PIN_GPIO_D_1 , + +#ifdef ES_INIT_GPIO_D_1_MODE + ES_INIT_GPIO_D_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_1_LEVEL + ES_INIT_GPIO_D_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_1_IRQ_MODE + ES_INIT_GPIO_D_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_2 + + { + ES_PIN_GPIO_D_2 , + +#ifdef ES_INIT_GPIO_D_2_MODE + ES_INIT_GPIO_D_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_2_LEVEL + ES_INIT_GPIO_D_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_2_IRQ_MODE + ES_INIT_GPIO_D_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_3 + + { + ES_PIN_GPIO_D_3 , + +#ifdef ES_INIT_GPIO_D_3_MODE + ES_INIT_GPIO_D_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_3_LEVEL + ES_INIT_GPIO_D_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_3_IRQ_MODE + ES_INIT_GPIO_D_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_4 + + { + ES_PIN_GPIO_D_4 , + +#ifdef ES_INIT_GPIO_D_4_MODE + ES_INIT_GPIO_D_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_4_LEVEL + ES_INIT_GPIO_D_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_4_IRQ_MODE + ES_INIT_GPIO_D_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_5 + + { + ES_PIN_GPIO_D_5 , + +#ifdef ES_INIT_GPIO_D_5_MODE + ES_INIT_GPIO_D_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_5_LEVEL + ES_INIT_GPIO_D_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_5_IRQ_MODE + ES_INIT_GPIO_D_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_6 + + { + ES_PIN_GPIO_D_6 , + +#ifdef ES_INIT_GPIO_D_6_MODE + ES_INIT_GPIO_D_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_6_LEVEL + ES_INIT_GPIO_D_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_6_IRQ_MODE + ES_INIT_GPIO_D_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_7 + + { + ES_PIN_GPIO_D_7 , + +#ifdef ES_INIT_GPIO_D_7_MODE + ES_INIT_GPIO_D_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_7_LEVEL + ES_INIT_GPIO_D_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_7_IRQ_MODE + ES_INIT_GPIO_D_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_8 + + { + ES_PIN_GPIO_D_8 , + +#ifdef ES_INIT_GPIO_D_8_MODE + ES_INIT_GPIO_D_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_8_LEVEL + ES_INIT_GPIO_D_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_8_IRQ_MODE + ES_INIT_GPIO_D_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_9 + + { + ES_PIN_GPIO_D_9 , + +#ifdef ES_INIT_GPIO_D_9_MODE + ES_INIT_GPIO_D_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_9_LEVEL + ES_INIT_GPIO_D_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_9_IRQ_MODE + ES_INIT_GPIO_D_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_10 + + { + ES_PIN_GPIO_D_10 , + +#ifdef ES_INIT_GPIO_D_10_MODE + ES_INIT_GPIO_D_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_10_LEVEL + ES_INIT_GPIO_D_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_10_IRQ_MODE + ES_INIT_GPIO_D_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_11 + + { + ES_PIN_GPIO_D_11 , + +#ifdef ES_INIT_GPIO_D_11_MODE + ES_INIT_GPIO_D_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_11_LEVEL + ES_INIT_GPIO_D_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_11_IRQ_MODE + ES_INIT_GPIO_D_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_12 + + { + ES_PIN_GPIO_D_12 , + +#ifdef ES_INIT_GPIO_D_12_MODE + ES_INIT_GPIO_D_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_12_LEVEL + ES_INIT_GPIO_D_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_12_IRQ_MODE + ES_INIT_GPIO_D_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_13 + + { + ES_PIN_GPIO_D_13 , + +#ifdef ES_INIT_GPIO_D_13_MODE + ES_INIT_GPIO_D_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_13_LEVEL + ES_INIT_GPIO_D_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_13_IRQ_MODE + ES_INIT_GPIO_D_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_14 + + { + ES_PIN_GPIO_D_14 , + +#ifdef ES_INIT_GPIO_D_14_MODE + ES_INIT_GPIO_D_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_14_LEVEL + ES_INIT_GPIO_D_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_14_IRQ_MODE + ES_INIT_GPIO_D_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_15 + + { + ES_PIN_GPIO_D_15 , + +#ifdef ES_INIT_GPIO_D_15_MODE + ES_INIT_GPIO_D_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_15_LEVEL + ES_INIT_GPIO_D_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_15_IRQ_MODE + ES_INIT_GPIO_D_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_0 + + { + ES_PIN_GPIO_E_0 , + +#ifdef ES_INIT_GPIO_E_0_MODE + ES_INIT_GPIO_E_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_0_LEVEL + ES_INIT_GPIO_E_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_0_IRQ_MODE + ES_INIT_GPIO_E_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_1 + + { + ES_PIN_GPIO_E_1 , + +#ifdef ES_INIT_GPIO_E_1_MODE + ES_INIT_GPIO_E_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_1_LEVEL + ES_INIT_GPIO_E_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_1_IRQ_MODE + ES_INIT_GPIO_E_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_2 + + { + ES_PIN_GPIO_E_2 , + +#ifdef ES_INIT_GPIO_E_2_MODE + ES_INIT_GPIO_E_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_2_LEVEL + ES_INIT_GPIO_E_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_2_IRQ_MODE + ES_INIT_GPIO_E_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_3 + + { + ES_PIN_GPIO_E_3 , + +#ifdef ES_INIT_GPIO_E_3_MODE + ES_INIT_GPIO_E_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_3_LEVEL + ES_INIT_GPIO_E_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_3_IRQ_MODE + ES_INIT_GPIO_E_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_4 + + { + ES_PIN_GPIO_E_4 , + +#ifdef ES_INIT_GPIO_E_4_MODE + ES_INIT_GPIO_E_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_4_LEVEL + ES_INIT_GPIO_E_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_4_IRQ_MODE + ES_INIT_GPIO_E_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_5 + + { + ES_PIN_GPIO_E_5 , + +#ifdef ES_INIT_GPIO_E_5_MODE + ES_INIT_GPIO_E_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_5_LEVEL + ES_INIT_GPIO_E_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_5_IRQ_MODE + ES_INIT_GPIO_E_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_6 + + { + ES_PIN_GPIO_E_6 , + +#ifdef ES_INIT_GPIO_E_6_MODE + ES_INIT_GPIO_E_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_6_LEVEL + ES_INIT_GPIO_E_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_6_IRQ_MODE + ES_INIT_GPIO_E_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_7 + + { + ES_PIN_GPIO_E_7 , + +#ifdef ES_INIT_GPIO_E_7_MODE + ES_INIT_GPIO_E_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_7_LEVEL + ES_INIT_GPIO_E_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_7_IRQ_MODE + ES_INIT_GPIO_E_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_8 + + { + ES_PIN_GPIO_E_8 , + +#ifdef ES_INIT_GPIO_E_8_MODE + ES_INIT_GPIO_E_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_8_LEVEL + ES_INIT_GPIO_E_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_8_IRQ_MODE + ES_INIT_GPIO_E_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_9 + + { + ES_PIN_GPIO_E_9 , + +#ifdef ES_INIT_GPIO_E_9_MODE + ES_INIT_GPIO_E_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_9_LEVEL + ES_INIT_GPIO_E_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_9_IRQ_MODE + ES_INIT_GPIO_E_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_10 + + { + ES_PIN_GPIO_E_10 , + +#ifdef ES_INIT_GPIO_E_10_MODE + ES_INIT_GPIO_E_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_10_LEVEL + ES_INIT_GPIO_E_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_10_IRQ_MODE + ES_INIT_GPIO_E_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_11 + + { + ES_PIN_GPIO_E_11 , + +#ifdef ES_INIT_GPIO_E_11_MODE + ES_INIT_GPIO_E_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_11_LEVEL + ES_INIT_GPIO_E_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_11_IRQ_MODE + ES_INIT_GPIO_E_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_12 + + { + ES_PIN_GPIO_E_12 , + +#ifdef ES_INIT_GPIO_E_12_MODE + ES_INIT_GPIO_E_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_12_LEVEL + ES_INIT_GPIO_E_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_12_IRQ_MODE + ES_INIT_GPIO_E_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_13 + + { + ES_PIN_GPIO_E_13 , + +#ifdef ES_INIT_GPIO_E_13_MODE + ES_INIT_GPIO_E_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_13_LEVEL + ES_INIT_GPIO_E_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_13_IRQ_MODE + ES_INIT_GPIO_E_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_14 + + { + ES_PIN_GPIO_E_14 , + +#ifdef ES_INIT_GPIO_E_14_MODE + ES_INIT_GPIO_E_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_14_LEVEL + ES_INIT_GPIO_E_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_14_IRQ_MODE + ES_INIT_GPIO_E_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_15 + + { + ES_PIN_GPIO_E_15 , + +#ifdef ES_INIT_GPIO_E_15_MODE + ES_INIT_GPIO_E_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_15_LEVEL + ES_INIT_GPIO_E_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_15_IRQ_MODE + ES_INIT_GPIO_E_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_0 + + { + ES_PIN_GPIO_F_0 , + +#ifdef ES_INIT_GPIO_F_0_MODE + ES_INIT_GPIO_F_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_0_LEVEL + ES_INIT_GPIO_F_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_0_IRQ_MODE + ES_INIT_GPIO_F_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_1 + + { + ES_PIN_GPIO_F_1 , + +#ifdef ES_INIT_GPIO_F_1_MODE + ES_INIT_GPIO_F_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_1_LEVEL + ES_INIT_GPIO_F_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_1_IRQ_MODE + ES_INIT_GPIO_F_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_2 + + { + ES_PIN_GPIO_F_2 , + +#ifdef ES_INIT_GPIO_F_2_MODE + ES_INIT_GPIO_F_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_2_LEVEL + ES_INIT_GPIO_F_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_2_IRQ_MODE + ES_INIT_GPIO_F_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_3 + + { + ES_PIN_GPIO_F_3 , + +#ifdef ES_INIT_GPIO_F_3_MODE + ES_INIT_GPIO_F_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_3_LEVEL + ES_INIT_GPIO_F_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_3_IRQ_MODE + ES_INIT_GPIO_F_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_4 + + { + ES_PIN_GPIO_F_4 , + +#ifdef ES_INIT_GPIO_F_4_MODE + ES_INIT_GPIO_F_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_4_LEVEL + ES_INIT_GPIO_F_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_4_IRQ_MODE + ES_INIT_GPIO_F_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_5 + + { + ES_PIN_GPIO_F_5 , + +#ifdef ES_INIT_GPIO_F_5_MODE + ES_INIT_GPIO_F_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_5_LEVEL + ES_INIT_GPIO_F_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_5_IRQ_MODE + ES_INIT_GPIO_F_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_6 + + { + ES_PIN_GPIO_F_6 , + +#ifdef ES_INIT_GPIO_F_6_MODE + ES_INIT_GPIO_F_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_6_LEVEL + ES_INIT_GPIO_F_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_6_IRQ_MODE + ES_INIT_GPIO_F_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_7 + + { + ES_PIN_GPIO_F_7 , + +#ifdef ES_INIT_GPIO_F_7_MODE + ES_INIT_GPIO_F_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_7_LEVEL + ES_INIT_GPIO_F_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_7_IRQ_MODE + ES_INIT_GPIO_F_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_8 + + { + ES_PIN_GPIO_F_8 , + +#ifdef ES_INIT_GPIO_F_8_MODE + ES_INIT_GPIO_F_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_8_LEVEL + ES_INIT_GPIO_F_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_8_IRQ_MODE + ES_INIT_GPIO_F_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_9 + + { + ES_PIN_GPIO_F_9 , + +#ifdef ES_INIT_GPIO_F_9_MODE + ES_INIT_GPIO_F_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_9_LEVEL + ES_INIT_GPIO_F_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_9_IRQ_MODE + ES_INIT_GPIO_F_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_10 + + { + ES_PIN_GPIO_F_10 , + +#ifdef ES_INIT_GPIO_F_10_MODE + ES_INIT_GPIO_F_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_10_LEVEL + ES_INIT_GPIO_F_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_10_IRQ_MODE + ES_INIT_GPIO_F_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_11 + + { + ES_PIN_GPIO_F_11 , + +#ifdef ES_INIT_GPIO_F_11_MODE + ES_INIT_GPIO_F_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_11_LEVEL + ES_INIT_GPIO_F_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_11_IRQ_MODE + ES_INIT_GPIO_F_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_12 + + { + ES_PIN_GPIO_F_12 , + +#ifdef ES_INIT_GPIO_F_12_MODE + ES_INIT_GPIO_F_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_12_LEVEL + ES_INIT_GPIO_F_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_12_IRQ_MODE + ES_INIT_GPIO_F_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_13 + + { + ES_PIN_GPIO_F_13 , + +#ifdef ES_INIT_GPIO_F_13_MODE + ES_INIT_GPIO_F_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_13_LEVEL + ES_INIT_GPIO_F_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_13_IRQ_MODE + ES_INIT_GPIO_F_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_14 + + { + ES_PIN_GPIO_F_14 , + +#ifdef ES_INIT_GPIO_F_14_MODE + ES_INIT_GPIO_F_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_14_LEVEL + ES_INIT_GPIO_F_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_14_IRQ_MODE + ES_INIT_GPIO_F_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_15 + + { + ES_PIN_GPIO_F_15 , + +#ifdef ES_INIT_GPIO_F_15_MODE + ES_INIT_GPIO_F_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_15_LEVEL + ES_INIT_GPIO_F_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_15_IRQ_MODE + ES_INIT_GPIO_F_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_0 + + { + ES_PIN_GPIO_G_0 , + +#ifdef ES_INIT_GPIO_G_0_MODE + ES_INIT_GPIO_G_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_0_LEVEL + ES_INIT_GPIO_G_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_0_IRQ_MODE + ES_INIT_GPIO_G_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_1 + + { + ES_PIN_GPIO_G_1 , + +#ifdef ES_INIT_GPIO_G_1_MODE + ES_INIT_GPIO_G_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_1_LEVEL + ES_INIT_GPIO_G_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_1_IRQ_MODE + ES_INIT_GPIO_G_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_2 + + { + ES_PIN_GPIO_G_2 , + +#ifdef ES_INIT_GPIO_G_2_MODE + ES_INIT_GPIO_G_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_2_LEVEL + ES_INIT_GPIO_G_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_2_IRQ_MODE + ES_INIT_GPIO_G_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_3 + + { + ES_PIN_GPIO_G_3 , + +#ifdef ES_INIT_GPIO_G_3_MODE + ES_INIT_GPIO_G_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_3_LEVEL + ES_INIT_GPIO_G_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_3_IRQ_MODE + ES_INIT_GPIO_G_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_4 + + { + ES_PIN_GPIO_G_4 , + +#ifdef ES_INIT_GPIO_G_4_MODE + ES_INIT_GPIO_G_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_4_LEVEL + ES_INIT_GPIO_G_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_4_IRQ_MODE + ES_INIT_GPIO_G_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_5 + + { + ES_PIN_GPIO_G_5 , + +#ifdef ES_INIT_GPIO_G_5_MODE + ES_INIT_GPIO_G_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_5_LEVEL + ES_INIT_GPIO_G_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_5_IRQ_MODE + ES_INIT_GPIO_G_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_6 + + { + ES_PIN_GPIO_G_6 , + +#ifdef ES_INIT_GPIO_G_6_MODE + ES_INIT_GPIO_G_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_6_LEVEL + ES_INIT_GPIO_G_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_6_IRQ_MODE + ES_INIT_GPIO_G_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_7 + + { + ES_PIN_GPIO_G_7 , + +#ifdef ES_INIT_GPIO_G_7_MODE + ES_INIT_GPIO_G_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_7_LEVEL + ES_INIT_GPIO_G_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_7_IRQ_MODE + ES_INIT_GPIO_G_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_8 + + { + ES_PIN_GPIO_G_8 , + +#ifdef ES_INIT_GPIO_G_8_MODE + ES_INIT_GPIO_G_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_8_LEVEL + ES_INIT_GPIO_G_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_8_IRQ_MODE + ES_INIT_GPIO_G_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_9 + + { + ES_PIN_GPIO_G_9 , + +#ifdef ES_INIT_GPIO_G_9_MODE + ES_INIT_GPIO_G_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_9_LEVEL + ES_INIT_GPIO_G_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_9_IRQ_MODE + ES_INIT_GPIO_G_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_10 + + { + ES_PIN_GPIO_G_10 , + +#ifdef ES_INIT_GPIO_G_10_MODE + ES_INIT_GPIO_G_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_10_LEVEL + ES_INIT_GPIO_G_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_10_IRQ_MODE + ES_INIT_GPIO_G_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_11 + + { + ES_PIN_GPIO_G_11 , + +#ifdef ES_INIT_GPIO_G_11_MODE + ES_INIT_GPIO_G_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_11_LEVEL + ES_INIT_GPIO_G_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_11_IRQ_MODE + ES_INIT_GPIO_G_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_12 + + { + ES_PIN_GPIO_G_12 , + +#ifdef ES_INIT_GPIO_G_12_MODE + ES_INIT_GPIO_G_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_12_LEVEL + ES_INIT_GPIO_G_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_12_IRQ_MODE + ES_INIT_GPIO_G_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_13 + + { + ES_PIN_GPIO_G_13 , + +#ifdef ES_INIT_GPIO_G_13_MODE + ES_INIT_GPIO_G_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_13_LEVEL + ES_INIT_GPIO_G_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_13_IRQ_MODE + ES_INIT_GPIO_G_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_14 + + { + ES_PIN_GPIO_G_14 , + +#ifdef ES_INIT_GPIO_G_14_MODE + ES_INIT_GPIO_G_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_14_LEVEL + ES_INIT_GPIO_G_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_14_IRQ_MODE + ES_INIT_GPIO_G_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_15 + + { + ES_PIN_GPIO_G_15 , + +#ifdef ES_INIT_GPIO_G_15_MODE + ES_INIT_GPIO_G_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_15_LEVEL + ES_INIT_GPIO_G_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_15_IRQ_MODE + ES_INIT_GPIO_G_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_0 + + { + ES_PIN_GPIO_H_0 , + +#ifdef ES_INIT_GPIO_H_0_MODE + ES_INIT_GPIO_H_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_0_LEVEL + ES_INIT_GPIO_H_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_0_IRQ_MODE + ES_INIT_GPIO_H_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_1 + + { + ES_PIN_GPIO_H_1 , + +#ifdef ES_INIT_GPIO_H_1_MODE + ES_INIT_GPIO_H_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_1_LEVEL + ES_INIT_GPIO_H_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_1_IRQ_MODE + ES_INIT_GPIO_H_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_2 + + { + ES_PIN_GPIO_H_2 , + +#ifdef ES_INIT_GPIO_H_2_MODE + ES_INIT_GPIO_H_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_2_LEVEL + ES_INIT_GPIO_H_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_2_IRQ_MODE + ES_INIT_GPIO_H_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_3 + + { + ES_PIN_GPIO_H_3 , + +#ifdef ES_INIT_GPIO_H_3_MODE + ES_INIT_GPIO_H_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_3_LEVEL + ES_INIT_GPIO_H_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_3_IRQ_MODE + ES_INIT_GPIO_H_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_4 + + { + ES_PIN_GPIO_H_4 , + +#ifdef ES_INIT_GPIO_H_4_MODE + ES_INIT_GPIO_H_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_4_LEVEL + ES_INIT_GPIO_H_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_4_IRQ_MODE + ES_INIT_GPIO_H_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_5 + + { + ES_PIN_GPIO_H_5 , + +#ifdef ES_INIT_GPIO_H_5_MODE + ES_INIT_GPIO_H_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_5_LEVEL + ES_INIT_GPIO_H_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_5_IRQ_MODE + ES_INIT_GPIO_H_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_6 + + { + ES_PIN_GPIO_H_6 , + +#ifdef ES_INIT_GPIO_H_6_MODE + ES_INIT_GPIO_H_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_6_LEVEL + ES_INIT_GPIO_H_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_6_IRQ_MODE + ES_INIT_GPIO_H_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_7 + + { + ES_PIN_GPIO_H_7 , + +#ifdef ES_INIT_GPIO_H_7_MODE + ES_INIT_GPIO_H_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_7_LEVEL + ES_INIT_GPIO_H_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_7_IRQ_MODE + ES_INIT_GPIO_H_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_8 + + { + ES_PIN_GPIO_H_8 , + +#ifdef ES_INIT_GPIO_H_8_MODE + ES_INIT_GPIO_H_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_8_LEVEL + ES_INIT_GPIO_H_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_8_IRQ_MODE + ES_INIT_GPIO_H_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_9 + + { + ES_PIN_GPIO_H_9 , + +#ifdef ES_INIT_GPIO_H_9_MODE + ES_INIT_GPIO_H_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_9_LEVEL + ES_INIT_GPIO_H_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_9_IRQ_MODE + ES_INIT_GPIO_H_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_10 + + { + ES_PIN_GPIO_H_10 , + +#ifdef ES_INIT_GPIO_H_10_MODE + ES_INIT_GPIO_H_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_10_LEVEL + ES_INIT_GPIO_H_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_10_IRQ_MODE + ES_INIT_GPIO_H_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_11 + + { + ES_PIN_GPIO_H_11 , + +#ifdef ES_INIT_GPIO_H_11_MODE + ES_INIT_GPIO_H_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_11_LEVEL + ES_INIT_GPIO_H_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_11_IRQ_MODE + ES_INIT_GPIO_H_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_12 + + { + ES_PIN_GPIO_H_12 , + +#ifdef ES_INIT_GPIO_H_12_MODE + ES_INIT_GPIO_H_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_12_LEVEL + ES_INIT_GPIO_H_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_12_IRQ_MODE + ES_INIT_GPIO_H_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_13 + + { + ES_PIN_GPIO_H_13 , + +#ifdef ES_INIT_GPIO_H_13_MODE + ES_INIT_GPIO_H_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_13_LEVEL + ES_INIT_GPIO_H_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_13_IRQ_MODE + ES_INIT_GPIO_H_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_14 + + { + ES_PIN_GPIO_H_14 , + +#ifdef ES_INIT_GPIO_H_14_MODE + ES_INIT_GPIO_H_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_14_LEVEL + ES_INIT_GPIO_H_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_14_IRQ_MODE + ES_INIT_GPIO_H_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_15 + + { + ES_PIN_GPIO_H_15 , + +#ifdef ES_INIT_GPIO_H_15_MODE + ES_INIT_GPIO_H_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_15_LEVEL + ES_INIT_GPIO_H_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_15_IRQ_MODE + ES_INIT_GPIO_H_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + + + +}; + +#endif + + + +#endif diff --git a/bsp/essemi/es32f369x/drivers/ES/es_conf_info_hwtimer.h b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_hwtimer.h new file mode 100644 index 0000000000..f71afb3b95 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_hwtimer.h @@ -0,0 +1,102 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_HWTIMER_H__ +#define __ES_CONF_INFO_HWTIMER_H__ + +#include +#include + +#define ES_C_HWTIMER_MODE_UP HWTIMER_CNTMODE_UP +#define ES_C_HWTIMER_MODE_DOWN HWTIMER_CNTMODE_DW + +/* HWTIMER 配置 */ + +/* codes_main */ + + + +#ifndef ES_AD16C4T0_HWTIMER_MODE +#define ES_AD16C4T0_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_AD16C4T1_HWTIMER_MODE +#define ES_AD16C4T1_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_GP32C4T0_HWTIMER_MODE +#define ES_GP32C4T0_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_GP32C4T1_HWTIMER_MODE +#define ES_GP32C4T1_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_GP16C4T0_HWTIMER_MODE +#define ES_GP16C4T0_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_GP16C4T1_HWTIMER_MODE +#define ES_GP16C4T1_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_BS16T0_HWTIMER_MODE +#define ES_BS16T0_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_BS16T1_HWTIMER_MODE +#define ES_BS16T1_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif + + + + +#define ES_AD16C4T0_HWTIMER_PRES 1 +#define ES_AD16C4T1_HWTIMER_PRES 1 +#define ES_GP16C4T0_HWTIMER_PRES 1 +#define ES_GP16C4T1_HWTIMER_PRES 1 +#define ES_GP32C4T0_HWTIMER_PRES 1 +#define ES_GP32C4T1_HWTIMER_PRES 1 +#define ES_BS16T0_HWTIMER_PRES 1 +#define ES_BS16T1_HWTIMER_PRES 1 + +#ifndef ES_DEVICE_NAME_AD16C4T0_HWTIMER +#define ES_DEVICE_NAME_AD16C4T0_HWTIMER "timer0" +#endif +#ifndef ES_DEVICE_NAME_AD16C4T1_HWTIMER +#define ES_DEVICE_NAME_AD16C4T1_HWTIMER "timer1" +#endif +#ifndef ES_DEVICE_NAME_GP32C4T0_HWTIMER +#define ES_DEVICE_NAME_GP32C4T0_HWTIMER "timer2" +#endif +#ifndef ES_DEVICE_NAME_GP32C4T1_HWTIMER +#define ES_DEVICE_NAME_GP32C4T1_HWTIMER "timer3" +#endif +#ifndef ES_DEVICE_NAME_GP16C4T0_HWTIMER +#define ES_DEVICE_NAME_GP16C4T0_HWTIMER "timer4" +#endif +#ifndef ES_DEVICE_NAME_GP16C4T1_HWTIMER +#define ES_DEVICE_NAME_GP16C4T1_HWTIMER "timer5" +#endif +#ifndef ES_DEVICE_NAME_BS16T0_HWTIMER +#define ES_DEVICE_NAME_BS16T0_HWTIMER "timer6" +#endif +#ifndef ES_DEVICE_NAME_BS16T1_HWTIMER +#define ES_DEVICE_NAME_BS16T1_HWTIMER "timer7" +#endif + + +#endif diff --git a/bsp/essemi/es32f369x/drivers/ES/es_conf_info_i2c.h b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_i2c.h new file mode 100644 index 0000000000..65310fce01 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_i2c.h @@ -0,0 +1,95 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_I2C_H__ +#define __ES_CONF_INFO_I2C_H__ + +#include "es_conf_info_map.h" +#include +#include +#include + +#define ES_C_I2C_STRETCH I2C_NOSTRETCH_DISABLE +#define ES_C_I2C_NO_STRETCH I2C_NOSTRETCH_ENABLE + +#define ES_C_I2C_GENERALCALL I2C_GENERALCALL_ENABLE +#define ES_C_I2C_NO_GENERALCALL I2C_GENERALCALL_DISABLE + + +#define ES_C_I2C_ADDR_7_MODE I2C_ADDR_7BIT +#define ES_C_I2C_ADDR_10_MODE I2C_ADDR_10BIT + + +/* I2C 配置 */ + + + +/* codes_main */ + + + + + +#ifndef ES_DEVICE_NAME_I2C0 +#define ES_DEVICE_NAME_I2C0 "i2c0" +#endif + +#ifndef ES_DEVICE_NAME_I2C1 +#define ES_DEVICE_NAME_I2C1 "i2c1" +#endif + +#ifndef ES_I2C0_CLK_SPEED +#define ES_I2C0_CLK_SPEED 100000 +#endif +#ifndef ES_I2C0_OWN_ADDR1 +#define ES_I2C0_OWN_ADDR1 0x20 +#endif +#ifndef ES_I2C0_GENERAL_CALL +#define ES_I2C0_GENERAL_CALL ES_C_I2C_NO_GENERALCALL +#endif +#ifndef ES_I2C0_STRETCH +#define ES_I2C0_STRETCH ES_C_I2C_STRETCH +#endif +#ifndef ES_I2C0_ADDR_MODE +#define ES_I2C0_ADDR_MODE ES_C_I2C_ADDR_7_MODE +#endif + +#ifndef ES_I2C1_CLK_SPEED +#define ES_I2C1_CLK_SPEED 100000 +#endif +#ifndef ES_I2C1_OWN_ADDR1 +#define ES_I2C1_OWN_ADDR1 0x20 +#endif +#ifndef ES_I2C1_GENERAL_CALL +#define ES_I2C1_GENERAL_CALL ES_C_I2C_NO_GENERALCALL +#endif +#ifndef ES_I2C1_STRETCH +#define ES_I2C1_STRETCH ES_C_I2C_STRETCH +#endif +#ifndef ES_I2C1_ADDR_MODE +#define ES_I2C1_ADDR_MODE ES_C_I2C_ADDR_7_MODE +#endif + + + +#endif diff --git a/bsp/essemi/es32f369x/drivers/ES/es_conf_info_map.h b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_map.h new file mode 100644 index 0000000000..f25123227b --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_map.h @@ -0,0 +1,2876 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __es_conf_info_map_H__ +#define __es_conf_info_map_H__ + +#include + + + +#define __ES_PIN(index, gpio, gpio_index) {index, GPIO##gpio, GPIO_PIN_##gpio_index} +#define __ES_PIN_DEFAULT {-1, 0, 0} + +struct pin_index +{ + int index; + GPIO_TypeDef *gpio; + uint32_t pin; +}; + + +#define ES_GPIO_ADC_CH0_GPIO GPIOC +#define ES_GPIO_ADC_CH1_GPIO GPIOC +#define ES_GPIO_ADC_CH2_GPIO GPIOC +#define ES_GPIO_ADC_CH3_GPIO GPIOC +#define ES_GPIO_ADC_CH4_GPIO GPIOA +#define ES_GPIO_ADC_CH5_GPIO GPIOA +#define ES_GPIO_ADC_CH6_GPIO GPIOA +#define ES_GPIO_ADC_CH7_GPIO GPIOA +#define ES_GPIO_ADC_CH8_GPIO GPIOA +#define ES_GPIO_ADC_CH9_GPIO GPIOA +#define ES_GPIO_ADC_CH10_GPIO GPIOA +#define ES_GPIO_ADC_CH11_GPIO GPIOA +#define ES_GPIO_ADC_CH12_GPIO GPIOC +#define ES_GPIO_ADC_CH13_GPIO GPIOC +#define ES_GPIO_ADC_CH14_GPIO GPIOB +#define ES_GPIO_ADC_CH15_GPIO GPIOB + +#define ES_GPIO_ADC_CH0_PIN GPIO_PIN_0 +#define ES_GPIO_ADC_CH1_PIN GPIO_PIN_1 +#define ES_GPIO_ADC_CH2_PIN GPIO_PIN_2 +#define ES_GPIO_ADC_CH3_PIN GPIO_PIN_3 +#define ES_GPIO_ADC_CH4_PIN GPIO_PIN_0 +#define ES_GPIO_ADC_CH5_PIN GPIO_PIN_1 +#define ES_GPIO_ADC_CH6_PIN GPIO_PIN_2 +#define ES_GPIO_ADC_CH7_PIN GPIO_PIN_3 +#define ES_GPIO_ADC_CH8_PIN GPIO_PIN_4 +#define ES_GPIO_ADC_CH9_PIN GPIO_PIN_5 +#define ES_GPIO_ADC_CH10_PIN GPIO_PIN_6 +#define ES_GPIO_ADC_CH11_PIN GPIO_PIN_7 +#define ES_GPIO_ADC_CH12_PIN GPIO_PIN_4 +#define ES_GPIO_ADC_CH13_PIN GPIO_PIN_5 +#define ES_GPIO_ADC_CH14_PIN GPIO_PIN_0 +#define ES_GPIO_ADC_CH15_PIN GPIO_PIN_1 + + + +static const struct pin_index pins[] = +{ + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, + __ES_PIN(2, C, 13), + __ES_PIN(3, C, 14), + __ES_PIN(4, C, 15), + __ES_PIN(5, H, 0), + __ES_PIN(6, H, 1), + __ES_PIN_DEFAULT, + __ES_PIN(8, C, 0), + __ES_PIN(9, C, 1), + __ES_PIN(10, C, 2), + __ES_PIN(11, C, 3), + __ES_PIN(12, H, 3), + __ES_PIN(13, H, 4), + __ES_PIN(14, A, 0), + __ES_PIN(15, A, 1), + __ES_PIN(16, A, 2), + __ES_PIN(17, A, 3), + __ES_PIN(18, F, 0), + __ES_PIN(19, F, 1), + __ES_PIN(20, A, 4), + __ES_PIN(21, A, 5), + __ES_PIN(22, A, 6), + __ES_PIN(23, A, 7), + __ES_PIN(24, C, 4), + __ES_PIN(25, C, 5), + __ES_PIN(26, B, 0), + __ES_PIN(27, B, 1), + __ES_PIN(28, B, 2), + __ES_PIN(29, B, 10), + __ES_PIN(30, B, 11), + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, + __ES_PIN(33, B, 12), + __ES_PIN(34, B, 13), + __ES_PIN(35, B, 14), + __ES_PIN(36, B, 15), + __ES_PIN(37, C, 6), + __ES_PIN(38, C, 7), + __ES_PIN(39, C, 8), + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, + __ES_PIN(46, A, 13), + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, + __ES_PIN(49, A, 14), + __ES_PIN(50, A, 15), + __ES_PIN(51, C, 10), + __ES_PIN(52, C, 11), + __ES_PIN(53, C, 12), + __ES_PIN(54, D, 2), + __ES_PIN(55, B, 3), + __ES_PIN(56, B, 4), + __ES_PIN(57, B, 5), + __ES_PIN(58, B, 6), + __ES_PIN(59, B, 7), + __ES_PIN(60, H, 2), + __ES_PIN(61, B, 8), + __ES_PIN(62, B, 9), + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, +}; + +#define ES_PIN_GPIO_C_13 2 +#define ES_PIN_GPIO_C_14 3 +#define ES_PIN_GPIO_C_15 4 +#define ES_PIN_GPIO_H_0 5 +#define ES_PIN_GPIO_H_1 6 +#define ES_PIN_GPIO_C_0 8 +#define ES_PIN_GPIO_C_1 9 +#define ES_PIN_GPIO_C_2 10 +#define ES_PIN_GPIO_C_3 11 +#define ES_PIN_GPIO_H_3 12 +#define ES_PIN_GPIO_H_4 13 +#define ES_PIN_GPIO_A_0 14 +#define ES_PIN_GPIO_A_1 15 +#define ES_PIN_GPIO_A_2 16 +#define ES_PIN_GPIO_A_3 17 +#define ES_PIN_GPIO_F_0 18 +#define ES_PIN_GPIO_F_1 19 +#define ES_PIN_GPIO_A_4 20 +#define ES_PIN_GPIO_A_5 21 +#define ES_PIN_GPIO_A_6 22 +#define ES_PIN_GPIO_A_7 23 +#define ES_PIN_GPIO_C_4 24 +#define ES_PIN_GPIO_C_5 25 +#define ES_PIN_GPIO_B_0 26 +#define ES_PIN_GPIO_B_1 27 +#define ES_PIN_GPIO_B_2 28 +#define ES_PIN_GPIO_B_10 29 +#define ES_PIN_GPIO_B_11 30 +#define ES_PIN_GPIO_B_12 33 +#define ES_PIN_GPIO_B_13 34 +#define ES_PIN_GPIO_B_14 35 +#define ES_PIN_GPIO_B_15 36 +#define ES_PIN_GPIO_C_6 37 +#define ES_PIN_GPIO_C_7 38 +#define ES_PIN_GPIO_C_8 39 +#define ES_PIN_GPIO_A_13 46 +#define ES_PIN_GPIO_A_14 49 +#define ES_PIN_GPIO_A_15 50 +#define ES_PIN_GPIO_C_10 51 +#define ES_PIN_GPIO_C_11 52 +#define ES_PIN_GPIO_C_12 53 +#define ES_PIN_GPIO_D_2 54 +#define ES_PIN_GPIO_B_3 55 +#define ES_PIN_GPIO_B_4 56 +#define ES_PIN_GPIO_B_5 57 +#define ES_PIN_GPIO_B_6 58 +#define ES_PIN_GPIO_B_7 59 +#define ES_PIN_GPIO_H_2 60 +#define ES_PIN_GPIO_B_8 61 +#define ES_PIN_GPIO_B_9 62 + + + +/* UART_TX */ + + +#ifndef ES_UART0_TX_GPIO_FUNC +#define ES_UART0_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART0_TX_GPIO_PORT +#define ES_UART0_TX_GPIO_PORT GPIOB +#endif +#ifndef ES_UART0_TX_GPIO_PIN +#define ES_UART0_TX_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_UART0_TX_PIN +#ifdef ES_PIN_GPIO_B_10 +#define ES_UART0_TX_PIN ES_PIN_GPIO_B_10 +#endif +#endif + +#ifndef ES_UART0_TX_GPIO_FUNC +#define ES_UART0_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART0_TX_GPIO_PORT +#define ES_UART0_TX_GPIO_PORT GPIOH +#endif +#ifndef ES_UART0_TX_GPIO_PIN +#define ES_UART0_TX_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_UART0_TX_PIN +#ifdef ES_PIN_GPIO_H_0 +#define ES_UART0_TX_PIN ES_PIN_GPIO_H_0 +#endif +#endif + +#ifndef ES_UART0_TX_GPIO_FUNC +#define ES_UART0_TX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART0_TX_GPIO_PORT +#define ES_UART0_TX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART0_TX_GPIO_PIN +#define ES_UART0_TX_GPIO_PIN GPIO_PIN_8 +#endif + +#ifndef ES_UART0_TX_PIN +#ifdef ES_PIN_GPIO_D_8 +#define ES_UART0_TX_PIN ES_PIN_GPIO_D_8 +#endif +#endif + +#ifndef ES_UART1_TX_GPIO_FUNC +#define ES_UART1_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_TX_GPIO_PORT +#define ES_UART1_TX_GPIO_PORT GPIOC +#endif +#ifndef ES_UART1_TX_GPIO_PIN +#define ES_UART1_TX_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_UART1_TX_PIN +#ifdef ES_PIN_GPIO_C_0 +#define ES_UART1_TX_PIN ES_PIN_GPIO_C_0 +#endif +#endif + +#ifndef ES_UART1_TX_GPIO_FUNC +#define ES_UART1_TX_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_UART1_TX_GPIO_PORT +#define ES_UART1_TX_GPIO_PORT GPIOA +#endif +#ifndef ES_UART1_TX_GPIO_PIN +#define ES_UART1_TX_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_UART1_TX_PIN +#ifdef ES_PIN_GPIO_A_13 +#define ES_UART1_TX_PIN ES_PIN_GPIO_A_13 +#endif +#endif + +#ifndef ES_UART1_TX_GPIO_FUNC +#define ES_UART1_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_TX_GPIO_PORT +#define ES_UART1_TX_GPIO_PORT GPIOC +#endif +#ifndef ES_UART1_TX_GPIO_PIN +#define ES_UART1_TX_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_UART1_TX_PIN +#ifdef ES_PIN_GPIO_C_10 +#define ES_UART1_TX_PIN ES_PIN_GPIO_C_10 +#endif +#endif + +#ifndef ES_UART1_TX_GPIO_FUNC +#define ES_UART1_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_TX_GPIO_PORT +#define ES_UART1_TX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART1_TX_GPIO_PIN +#define ES_UART1_TX_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_UART1_TX_PIN +#ifdef ES_PIN_GPIO_D_5 +#define ES_UART1_TX_PIN ES_PIN_GPIO_D_5 +#endif +#endif + +#ifndef ES_UART2_TX_GPIO_FUNC +#define ES_UART2_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART2_TX_GPIO_PORT +#define ES_UART2_TX_GPIO_PORT GPIOE +#endif +#ifndef ES_UART2_TX_GPIO_PIN +#define ES_UART2_TX_GPIO_PIN GPIO_PIN_2 +#endif + +#ifndef ES_UART2_TX_PIN +#ifdef ES_PIN_GPIO_E_2 +#define ES_UART2_TX_PIN ES_PIN_GPIO_E_2 +#endif +#endif + +#ifndef ES_UART2_TX_GPIO_FUNC +#define ES_UART2_TX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART2_TX_GPIO_PORT +#define ES_UART2_TX_GPIO_PORT GPIOC +#endif +#ifndef ES_UART2_TX_GPIO_PIN +#define ES_UART2_TX_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_UART2_TX_PIN +#ifdef ES_PIN_GPIO_C_12 +#define ES_UART2_TX_PIN ES_PIN_GPIO_C_12 +#endif +#endif + +#ifndef ES_UART2_TX_GPIO_FUNC +#define ES_UART2_TX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART2_TX_GPIO_PORT +#define ES_UART2_TX_GPIO_PORT GPIOB +#endif +#ifndef ES_UART2_TX_GPIO_PIN +#define ES_UART2_TX_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_UART2_TX_PIN +#ifdef ES_PIN_GPIO_B_3 +#define ES_UART2_TX_PIN ES_PIN_GPIO_B_3 +#endif +#endif + +#ifndef ES_UART3_TX_GPIO_FUNC +#define ES_UART3_TX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART3_TX_GPIO_PORT +#define ES_UART3_TX_GPIO_PORT GPIOC +#endif +#ifndef ES_UART3_TX_GPIO_PIN +#define ES_UART3_TX_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_UART3_TX_PIN +#ifdef ES_PIN_GPIO_C_4 +#define ES_UART3_TX_PIN ES_PIN_GPIO_C_4 +#endif +#endif + +#ifndef ES_UART3_TX_GPIO_FUNC +#define ES_UART3_TX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART3_TX_GPIO_PORT +#define ES_UART3_TX_GPIO_PORT GPIOE +#endif +#ifndef ES_UART3_TX_GPIO_PIN +#define ES_UART3_TX_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_UART3_TX_PIN +#ifdef ES_PIN_GPIO_E_10 +#define ES_UART3_TX_PIN ES_PIN_GPIO_E_10 +#endif +#endif + +#ifndef ES_UART3_TX_GPIO_FUNC +#define ES_UART3_TX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART3_TX_GPIO_PORT +#define ES_UART3_TX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART3_TX_GPIO_PIN +#define ES_UART3_TX_GPIO_PIN GPIO_PIN_14 +#endif + +#ifndef ES_UART3_TX_PIN +#ifdef ES_PIN_GPIO_D_14 +#define ES_UART3_TX_PIN ES_PIN_GPIO_D_14 +#endif +#endif + +#ifndef ES_UART4_TX_GPIO_FUNC +#define ES_UART4_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART4_TX_GPIO_PORT +#define ES_UART4_TX_GPIO_PORT GPIOB +#endif +#ifndef ES_UART4_TX_GPIO_PIN +#define ES_UART4_TX_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_UART4_TX_PIN +#ifdef ES_PIN_GPIO_B_6 +#define ES_UART4_TX_PIN ES_PIN_GPIO_B_6 +#endif +#endif + +#ifndef ES_UART4_TX_GPIO_FUNC +#define ES_UART4_TX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART4_TX_GPIO_PORT +#define ES_UART4_TX_GPIO_PORT GPIOE +#endif +#ifndef ES_UART4_TX_GPIO_PIN +#define ES_UART4_TX_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_UART4_TX_PIN +#ifdef ES_PIN_GPIO_E_10 +#define ES_UART4_TX_PIN ES_PIN_GPIO_E_10 +#endif +#endif + +#ifndef ES_UART5_TX_GPIO_FUNC +#define ES_UART5_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART5_TX_GPIO_PORT +#define ES_UART5_TX_GPIO_PORT GPIOA +#endif +#ifndef ES_UART5_TX_GPIO_PIN +#define ES_UART5_TX_GPIO_PIN GPIO_PIN_2 +#endif + +#ifndef ES_UART5_TX_PIN +#ifdef ES_PIN_GPIO_A_2 +#define ES_UART5_TX_PIN ES_PIN_GPIO_A_2 +#endif +#endif + +#ifndef ES_UART5_TX_GPIO_FUNC +#define ES_UART5_TX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART5_TX_GPIO_PORT +#define ES_UART5_TX_GPIO_PORT GPIOB +#endif +#ifndef ES_UART5_TX_GPIO_PIN +#define ES_UART5_TX_GPIO_PIN GPIO_PIN_9 +#endif + +#ifndef ES_UART5_TX_PIN +#ifdef ES_PIN_GPIO_B_9 +#define ES_UART5_TX_PIN ES_PIN_GPIO_B_9 +#endif +#endif + +#ifndef ES_UART5_TX_GPIO_FUNC +#define ES_UART5_TX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART5_TX_GPIO_PORT +#define ES_UART5_TX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART5_TX_GPIO_PIN +#define ES_UART5_TX_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_UART5_TX_PIN +#ifdef ES_PIN_GPIO_D_5 +#define ES_UART5_TX_PIN ES_PIN_GPIO_D_5 +#endif +#endif + + +/* UART_RX */ + + +#ifndef ES_UART0_RX_GPIO_FUNC +#define ES_UART0_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART0_RX_GPIO_PORT +#define ES_UART0_RX_GPIO_PORT GPIOB +#endif +#ifndef ES_UART0_RX_GPIO_PIN +#define ES_UART0_RX_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_UART0_RX_PIN +#ifdef ES_PIN_GPIO_B_11 +#define ES_UART0_RX_PIN ES_PIN_GPIO_B_11 +#endif +#endif + +#ifndef ES_UART0_RX_GPIO_FUNC +#define ES_UART0_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART0_RX_GPIO_PORT +#define ES_UART0_RX_GPIO_PORT GPIOH +#endif +#ifndef ES_UART0_RX_GPIO_PIN +#define ES_UART0_RX_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_UART0_RX_PIN +#ifdef ES_PIN_GPIO_H_1 +#define ES_UART0_RX_PIN ES_PIN_GPIO_H_1 +#endif +#endif + +#ifndef ES_UART0_RX_GPIO_FUNC +#define ES_UART0_RX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART0_RX_GPIO_PORT +#define ES_UART0_RX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART0_RX_GPIO_PIN +#define ES_UART0_RX_GPIO_PIN GPIO_PIN_9 +#endif + +#ifndef ES_UART0_RX_PIN +#ifdef ES_PIN_GPIO_D_9 +#define ES_UART0_RX_PIN ES_PIN_GPIO_D_9 +#endif +#endif + +#ifndef ES_UART1_RX_GPIO_FUNC +#define ES_UART1_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_RX_GPIO_PORT +#define ES_UART1_RX_GPIO_PORT GPIOC +#endif +#ifndef ES_UART1_RX_GPIO_PIN +#define ES_UART1_RX_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_UART1_RX_PIN +#ifdef ES_PIN_GPIO_C_1 +#define ES_UART1_RX_PIN ES_PIN_GPIO_C_1 +#endif +#endif + +#ifndef ES_UART1_RX_GPIO_FUNC +#define ES_UART1_RX_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_UART1_RX_GPIO_PORT +#define ES_UART1_RX_GPIO_PORT GPIOA +#endif +#ifndef ES_UART1_RX_GPIO_PIN +#define ES_UART1_RX_GPIO_PIN GPIO_PIN_14 +#endif + +#ifndef ES_UART1_RX_PIN +#ifdef ES_PIN_GPIO_A_14 +#define ES_UART1_RX_PIN ES_PIN_GPIO_A_14 +#endif +#endif + +#ifndef ES_UART1_RX_GPIO_FUNC +#define ES_UART1_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_RX_GPIO_PORT +#define ES_UART1_RX_GPIO_PORT GPIOC +#endif +#ifndef ES_UART1_RX_GPIO_PIN +#define ES_UART1_RX_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_UART1_RX_PIN +#ifdef ES_PIN_GPIO_C_11 +#define ES_UART1_RX_PIN ES_PIN_GPIO_C_11 +#endif +#endif + +#ifndef ES_UART1_RX_GPIO_FUNC +#define ES_UART1_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_RX_GPIO_PORT +#define ES_UART1_RX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART1_RX_GPIO_PIN +#define ES_UART1_RX_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_UART1_RX_PIN +#ifdef ES_PIN_GPIO_D_6 +#define ES_UART1_RX_PIN ES_PIN_GPIO_D_6 +#endif +#endif + +#ifndef ES_UART2_RX_GPIO_FUNC +#define ES_UART2_RX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART2_RX_GPIO_PORT +#define ES_UART2_RX_GPIO_PORT GPIOB +#endif +#ifndef ES_UART2_RX_GPIO_PIN +#define ES_UART2_RX_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_UART2_RX_PIN +#ifdef ES_PIN_GPIO_B_4 +#define ES_UART2_RX_PIN ES_PIN_GPIO_B_4 +#endif +#endif + +#ifndef ES_UART2_RX_GPIO_FUNC +#define ES_UART2_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART2_RX_GPIO_PORT +#define ES_UART2_RX_GPIO_PORT GPIOE +#endif +#ifndef ES_UART2_RX_GPIO_PIN +#define ES_UART2_RX_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_UART2_RX_PIN +#ifdef ES_PIN_GPIO_E_3 +#define ES_UART2_RX_PIN ES_PIN_GPIO_E_3 +#endif +#endif + +#ifndef ES_UART2_RX_GPIO_FUNC +#define ES_UART2_RX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART2_RX_GPIO_PORT +#define ES_UART2_RX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART2_RX_GPIO_PIN +#define ES_UART2_RX_GPIO_PIN GPIO_PIN_2 +#endif + +#ifndef ES_UART2_RX_PIN +#ifdef ES_PIN_GPIO_D_2 +#define ES_UART2_RX_PIN ES_PIN_GPIO_D_2 +#endif +#endif + +#ifndef ES_UART3_RX_GPIO_FUNC +#define ES_UART3_RX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART3_RX_GPIO_PORT +#define ES_UART3_RX_GPIO_PORT GPIOC +#endif +#ifndef ES_UART3_RX_GPIO_PIN +#define ES_UART3_RX_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_UART3_RX_PIN +#ifdef ES_PIN_GPIO_C_5 +#define ES_UART3_RX_PIN ES_PIN_GPIO_C_5 +#endif +#endif + +#ifndef ES_UART3_RX_GPIO_FUNC +#define ES_UART3_RX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART3_RX_GPIO_PORT +#define ES_UART3_RX_GPIO_PORT GPIOE +#endif +#ifndef ES_UART3_RX_GPIO_PIN +#define ES_UART3_RX_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_UART3_RX_PIN +#ifdef ES_PIN_GPIO_E_11 +#define ES_UART3_RX_PIN ES_PIN_GPIO_E_11 +#endif +#endif + +#ifndef ES_UART3_RX_GPIO_FUNC +#define ES_UART3_RX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART3_RX_GPIO_PORT +#define ES_UART3_RX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART3_RX_GPIO_PIN +#define ES_UART3_RX_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_UART3_RX_PIN +#ifdef ES_PIN_GPIO_D_13 +#define ES_UART3_RX_PIN ES_PIN_GPIO_D_13 +#endif +#endif + +#ifndef ES_UART4_RX_GPIO_FUNC +#define ES_UART4_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART4_RX_GPIO_PORT +#define ES_UART4_RX_GPIO_PORT GPIOB +#endif +#ifndef ES_UART4_RX_GPIO_PIN +#define ES_UART4_RX_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_UART4_RX_PIN +#ifdef ES_PIN_GPIO_B_7 +#define ES_UART4_RX_PIN ES_PIN_GPIO_B_7 +#endif +#endif + +#ifndef ES_UART4_RX_GPIO_FUNC +#define ES_UART4_RX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART4_RX_GPIO_PORT +#define ES_UART4_RX_GPIO_PORT GPIOE +#endif +#ifndef ES_UART4_RX_GPIO_PIN +#define ES_UART4_RX_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_UART4_RX_PIN +#ifdef ES_PIN_GPIO_E_11 +#define ES_UART4_RX_PIN ES_PIN_GPIO_E_11 +#endif +#endif + +#ifndef ES_UART5_RX_GPIO_FUNC +#define ES_UART5_RX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART5_RX_GPIO_PORT +#define ES_UART5_RX_GPIO_PORT GPIOB +#endif +#ifndef ES_UART5_RX_GPIO_PIN +#define ES_UART5_RX_GPIO_PIN GPIO_PIN_8 +#endif + +#ifndef ES_UART5_RX_PIN +#ifdef ES_PIN_GPIO_B_8 +#define ES_UART5_RX_PIN ES_PIN_GPIO_B_8 +#endif +#endif + +#ifndef ES_UART5_RX_GPIO_FUNC +#define ES_UART5_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART5_RX_GPIO_PORT +#define ES_UART5_RX_GPIO_PORT GPIOA +#endif +#ifndef ES_UART5_RX_GPIO_PIN +#define ES_UART5_RX_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_UART5_RX_PIN +#ifdef ES_PIN_GPIO_A_3 +#define ES_UART5_RX_PIN ES_PIN_GPIO_A_3 +#endif +#endif + +#ifndef ES_UART5_RX_GPIO_FUNC +#define ES_UART5_RX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART5_RX_GPIO_PORT +#define ES_UART5_RX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART5_RX_GPIO_PIN +#define ES_UART5_RX_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_UART5_RX_PIN +#ifdef ES_PIN_GPIO_D_6 +#define ES_UART5_RX_PIN ES_PIN_GPIO_D_6 +#endif +#endif + + +/* UART_RTS */ + + +#ifndef ES_UART0_RTS_GPIO_FUNC +#define ES_UART0_RTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART0_RTS_GPIO_PORT +#define ES_UART0_RTS_GPIO_PORT GPIOB +#endif +#ifndef ES_UART0_RTS_GPIO_PIN +#define ES_UART0_RTS_GPIO_PIN GPIO_PIN_14 +#endif + +#ifndef ES_UART0_RTS_PIN +#ifdef ES_PIN_GPIO_B_14 +#define ES_UART0_RTS_PIN ES_PIN_GPIO_B_14 +#endif +#endif + +#ifndef ES_UART0_RTS_GPIO_FUNC +#define ES_UART0_RTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART0_RTS_GPIO_PORT +#define ES_UART0_RTS_GPIO_PORT GPIOD +#endif +#ifndef ES_UART0_RTS_GPIO_PIN +#define ES_UART0_RTS_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_UART0_RTS_PIN +#ifdef ES_PIN_GPIO_D_12 +#define ES_UART0_RTS_PIN ES_PIN_GPIO_D_12 +#endif +#endif + +#ifndef ES_UART1_RTS_GPIO_FUNC +#define ES_UART1_RTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_RTS_GPIO_PORT +#define ES_UART1_RTS_GPIO_PORT GPIOC +#endif +#ifndef ES_UART1_RTS_GPIO_PIN +#define ES_UART1_RTS_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_UART1_RTS_PIN +#ifdef ES_PIN_GPIO_C_3 +#define ES_UART1_RTS_PIN ES_PIN_GPIO_C_3 +#endif +#endif + +#ifndef ES_UART1_RTS_GPIO_FUNC +#define ES_UART1_RTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_RTS_GPIO_PORT +#define ES_UART1_RTS_GPIO_PORT GPIOC +#endif +#ifndef ES_UART1_RTS_GPIO_PIN +#define ES_UART1_RTS_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_UART1_RTS_PIN +#ifdef ES_PIN_GPIO_C_12 +#define ES_UART1_RTS_PIN ES_PIN_GPIO_C_12 +#endif +#endif + +#ifndef ES_UART2_RTS_GPIO_FUNC +#define ES_UART2_RTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART2_RTS_GPIO_PORT +#define ES_UART2_RTS_GPIO_PORT GPIOE +#endif +#ifndef ES_UART2_RTS_GPIO_PIN +#define ES_UART2_RTS_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_UART2_RTS_PIN +#ifdef ES_PIN_GPIO_E_5 +#define ES_UART2_RTS_PIN ES_PIN_GPIO_E_5 +#endif +#endif + +#ifndef ES_UART2_RTS_GPIO_FUNC +#define ES_UART2_RTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART2_RTS_GPIO_PORT +#define ES_UART2_RTS_GPIO_PORT GPIOC +#endif +#ifndef ES_UART2_RTS_GPIO_PIN +#define ES_UART2_RTS_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_UART2_RTS_PIN +#ifdef ES_PIN_GPIO_C_10 +#define ES_UART2_RTS_PIN ES_PIN_GPIO_C_10 +#endif +#endif + +#ifndef ES_UART3_RTS_GPIO_FUNC +#define ES_UART3_RTS_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART3_RTS_GPIO_PORT +#define ES_UART3_RTS_GPIO_PORT GPIOB +#endif +#ifndef ES_UART3_RTS_GPIO_PIN +#define ES_UART3_RTS_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_UART3_RTS_PIN +#ifdef ES_PIN_GPIO_B_1 +#define ES_UART3_RTS_PIN ES_PIN_GPIO_B_1 +#endif +#endif + +#ifndef ES_UART3_RTS_GPIO_FUNC +#define ES_UART3_RTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART3_RTS_GPIO_PORT +#define ES_UART3_RTS_GPIO_PORT GPIOE +#endif +#ifndef ES_UART3_RTS_GPIO_PIN +#define ES_UART3_RTS_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_UART3_RTS_PIN +#ifdef ES_PIN_GPIO_E_13 +#define ES_UART3_RTS_PIN ES_PIN_GPIO_E_13 +#endif +#endif + +#ifndef ES_UART4_RTS_GPIO_FUNC +#define ES_UART4_RTS_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART4_RTS_GPIO_PORT +#define ES_UART4_RTS_GPIO_PORT GPIOE +#endif +#ifndef ES_UART4_RTS_GPIO_PIN +#define ES_UART4_RTS_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_UART4_RTS_PIN +#ifdef ES_PIN_GPIO_E_13 +#define ES_UART4_RTS_PIN ES_PIN_GPIO_E_13 +#endif +#endif + +#ifndef ES_UART4_RTS_GPIO_FUNC +#define ES_UART4_RTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART4_RTS_GPIO_PORT +#define ES_UART4_RTS_GPIO_PORT GPIOE +#endif +#ifndef ES_UART4_RTS_GPIO_PIN +#define ES_UART4_RTS_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_UART4_RTS_PIN +#ifdef ES_PIN_GPIO_E_1 +#define ES_UART4_RTS_PIN ES_PIN_GPIO_E_1 +#endif +#endif + +#ifndef ES_UART5_RTS_GPIO_FUNC +#define ES_UART5_RTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART5_RTS_GPIO_PORT +#define ES_UART5_RTS_GPIO_PORT GPIOA +#endif +#ifndef ES_UART5_RTS_GPIO_PIN +#define ES_UART5_RTS_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_UART5_RTS_PIN +#ifdef ES_PIN_GPIO_A_1 +#define ES_UART5_RTS_PIN ES_PIN_GPIO_A_1 +#endif +#endif + +#ifndef ES_UART5_RTS_GPIO_FUNC +#define ES_UART5_RTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART5_RTS_GPIO_PORT +#define ES_UART5_RTS_GPIO_PORT GPIOD +#endif +#ifndef ES_UART5_RTS_GPIO_PIN +#define ES_UART5_RTS_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_UART5_RTS_PIN +#ifdef ES_PIN_GPIO_D_4 +#define ES_UART5_RTS_PIN ES_PIN_GPIO_D_4 +#endif +#endif + + +/* UART_CTS */ + + +#ifndef ES_UART0_CTS_GPIO_FUNC +#define ES_UART0_CTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART0_CTS_GPIO_PORT +#define ES_UART0_CTS_GPIO_PORT GPIOB +#endif +#ifndef ES_UART0_CTS_GPIO_PIN +#define ES_UART0_CTS_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_UART0_CTS_PIN +#ifdef ES_PIN_GPIO_B_13 +#define ES_UART0_CTS_PIN ES_PIN_GPIO_B_13 +#endif +#endif + +#ifndef ES_UART0_CTS_GPIO_FUNC +#define ES_UART0_CTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART0_CTS_GPIO_PORT +#define ES_UART0_CTS_GPIO_PORT GPIOD +#endif +#ifndef ES_UART0_CTS_GPIO_PIN +#define ES_UART0_CTS_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_UART0_CTS_PIN +#ifdef ES_PIN_GPIO_D_11 +#define ES_UART0_CTS_PIN ES_PIN_GPIO_D_11 +#endif +#endif + +#ifndef ES_UART1_CTS_GPIO_FUNC +#define ES_UART1_CTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_CTS_GPIO_PORT +#define ES_UART1_CTS_GPIO_PORT GPIOC +#endif +#ifndef ES_UART1_CTS_GPIO_PIN +#define ES_UART1_CTS_GPIO_PIN GPIO_PIN_2 +#endif + +#ifndef ES_UART1_CTS_PIN +#ifdef ES_PIN_GPIO_C_2 +#define ES_UART1_CTS_PIN ES_PIN_GPIO_C_2 +#endif +#endif + +#ifndef ES_UART1_CTS_GPIO_FUNC +#define ES_UART1_CTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_CTS_GPIO_PORT +#define ES_UART1_CTS_GPIO_PORT GPIOD +#endif +#ifndef ES_UART1_CTS_GPIO_PIN +#define ES_UART1_CTS_GPIO_PIN GPIO_PIN_2 +#endif + +#ifndef ES_UART1_CTS_PIN +#ifdef ES_PIN_GPIO_D_2 +#define ES_UART1_CTS_PIN ES_PIN_GPIO_D_2 +#endif +#endif + +#ifndef ES_UART2_CTS_GPIO_FUNC +#define ES_UART2_CTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART2_CTS_GPIO_PORT +#define ES_UART2_CTS_GPIO_PORT GPIOE +#endif +#ifndef ES_UART2_CTS_GPIO_PIN +#define ES_UART2_CTS_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_UART2_CTS_PIN +#ifdef ES_PIN_GPIO_E_4 +#define ES_UART2_CTS_PIN ES_PIN_GPIO_E_4 +#endif +#endif + +#ifndef ES_UART2_CTS_GPIO_FUNC +#define ES_UART2_CTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART2_CTS_GPIO_PORT +#define ES_UART2_CTS_GPIO_PORT GPIOC +#endif +#ifndef ES_UART2_CTS_GPIO_PIN +#define ES_UART2_CTS_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_UART2_CTS_PIN +#ifdef ES_PIN_GPIO_C_11 +#define ES_UART2_CTS_PIN ES_PIN_GPIO_C_11 +#endif +#endif + +#ifndef ES_UART3_CTS_GPIO_FUNC +#define ES_UART3_CTS_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART3_CTS_GPIO_PORT +#define ES_UART3_CTS_GPIO_PORT GPIOB +#endif +#ifndef ES_UART3_CTS_GPIO_PIN +#define ES_UART3_CTS_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_UART3_CTS_PIN +#ifdef ES_PIN_GPIO_B_0 +#define ES_UART3_CTS_PIN ES_PIN_GPIO_B_0 +#endif +#endif + +#ifndef ES_UART3_CTS_GPIO_FUNC +#define ES_UART3_CTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART3_CTS_GPIO_PORT +#define ES_UART3_CTS_GPIO_PORT GPIOE +#endif +#ifndef ES_UART3_CTS_GPIO_PIN +#define ES_UART3_CTS_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_UART3_CTS_PIN +#ifdef ES_PIN_GPIO_E_12 +#define ES_UART3_CTS_PIN ES_PIN_GPIO_E_12 +#endif +#endif + +#ifndef ES_UART4_CTS_GPIO_FUNC +#define ES_UART4_CTS_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART4_CTS_GPIO_PORT +#define ES_UART4_CTS_GPIO_PORT GPIOE +#endif +#ifndef ES_UART4_CTS_GPIO_PIN +#define ES_UART4_CTS_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_UART4_CTS_PIN +#ifdef ES_PIN_GPIO_E_12 +#define ES_UART4_CTS_PIN ES_PIN_GPIO_E_12 +#endif +#endif + +#ifndef ES_UART4_CTS_GPIO_FUNC +#define ES_UART4_CTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART4_CTS_GPIO_PORT +#define ES_UART4_CTS_GPIO_PORT GPIOE +#endif +#ifndef ES_UART4_CTS_GPIO_PIN +#define ES_UART4_CTS_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_UART4_CTS_PIN +#ifdef ES_PIN_GPIO_E_0 +#define ES_UART4_CTS_PIN ES_PIN_GPIO_E_0 +#endif +#endif + +#ifndef ES_UART5_CTS_GPIO_FUNC +#define ES_UART5_CTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART5_CTS_GPIO_PORT +#define ES_UART5_CTS_GPIO_PORT GPIOA +#endif +#ifndef ES_UART5_CTS_GPIO_PIN +#define ES_UART5_CTS_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_UART5_CTS_PIN +#ifdef ES_PIN_GPIO_A_0 +#define ES_UART5_CTS_PIN ES_PIN_GPIO_A_0 +#endif +#endif + +#ifndef ES_UART5_CTS_GPIO_FUNC +#define ES_UART5_CTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART5_CTS_GPIO_PORT +#define ES_UART5_CTS_GPIO_PORT GPIOD +#endif +#ifndef ES_UART5_CTS_GPIO_PIN +#define ES_UART5_CTS_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_UART5_CTS_PIN +#ifdef ES_PIN_GPIO_D_3 +#define ES_UART5_CTS_PIN ES_PIN_GPIO_D_3 +#endif +#endif + + +/* UART_CK */ + + +#ifndef ES_UART4_CK_GPIO_FUNC +#define ES_UART4_CK_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART4_CK_GPIO_PORT +#define ES_UART4_CK_GPIO_PORT GPIOE +#endif +#ifndef ES_UART4_CK_GPIO_PIN +#define ES_UART4_CK_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_UART4_CK_PIN +#ifdef ES_PIN_GPIO_E_6 +#define ES_UART4_CK_PIN ES_PIN_GPIO_E_6 +#endif +#endif + +#ifndef ES_UART4_CK_GPIO_FUNC +#define ES_UART4_CK_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART4_CK_GPIO_PORT +#define ES_UART4_CK_GPIO_PORT GPIOE +#endif +#ifndef ES_UART4_CK_GPIO_PIN +#define ES_UART4_CK_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_UART4_CK_PIN +#ifdef ES_PIN_GPIO_E_7 +#define ES_UART4_CK_PIN ES_PIN_GPIO_E_7 +#endif +#endif + +#ifndef ES_UART5_CK_GPIO_FUNC +#define ES_UART5_CK_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART5_CK_GPIO_PORT +#define ES_UART5_CK_GPIO_PORT GPIOA +#endif +#ifndef ES_UART5_CK_GPIO_PIN +#define ES_UART5_CK_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_UART5_CK_PIN +#ifdef ES_PIN_GPIO_A_4 +#define ES_UART5_CK_PIN ES_PIN_GPIO_A_4 +#endif +#endif + +#ifndef ES_UART5_CK_GPIO_FUNC +#define ES_UART5_CK_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART5_CK_GPIO_PORT +#define ES_UART5_CK_GPIO_PORT GPIOD +#endif +#ifndef ES_UART5_CK_GPIO_PIN +#define ES_UART5_CK_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_UART5_CK_PIN +#ifdef ES_PIN_GPIO_D_7 +#define ES_UART5_CK_PIN ES_PIN_GPIO_D_7 +#endif +#endif + +#ifndef ES_UART5_CK_GPIO_FUNC +#define ES_UART5_CK_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART5_CK_GPIO_PORT +#define ES_UART5_CK_GPIO_PORT GPIOE +#endif +#ifndef ES_UART5_CK_GPIO_PIN +#define ES_UART5_CK_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_UART5_CK_PIN +#ifdef ES_PIN_GPIO_E_0 +#define ES_UART5_CK_PIN ES_PIN_GPIO_E_0 +#endif +#endif + + +/* USART_TX */ + + + +/* USART_RX */ + + + +/* USART_RTS */ + + + +/* USART_CTS */ + + + +/* USART_CK */ + + + +/* I2C_SCL */ + + +#ifndef ES_I2C0_SCL_GPIO_FUNC +#define ES_I2C0_SCL_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C0_SCL_GPIO_PORT +#define ES_I2C0_SCL_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C0_SCL_GPIO_PIN +#define ES_I2C0_SCL_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_I2C0_SCL_PIN +#ifdef ES_PIN_GPIO_B_6 +#define ES_I2C0_SCL_PIN ES_PIN_GPIO_B_6 +#endif +#endif + +#ifndef ES_I2C0_SCL_GPIO_FUNC +#define ES_I2C0_SCL_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C0_SCL_GPIO_PORT +#define ES_I2C0_SCL_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C0_SCL_GPIO_PIN +#define ES_I2C0_SCL_GPIO_PIN GPIO_PIN_8 +#endif + +#ifndef ES_I2C0_SCL_PIN +#ifdef ES_PIN_GPIO_B_8 +#define ES_I2C0_SCL_PIN ES_PIN_GPIO_B_8 +#endif +#endif + +#ifndef ES_I2C1_SCL_GPIO_FUNC +#define ES_I2C1_SCL_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C1_SCL_GPIO_PORT +#define ES_I2C1_SCL_GPIO_PORT GPIOA +#endif +#ifndef ES_I2C1_SCL_GPIO_PIN +#define ES_I2C1_SCL_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_I2C1_SCL_PIN +#ifdef ES_PIN_GPIO_A_5 +#define ES_I2C1_SCL_PIN ES_PIN_GPIO_A_5 +#endif +#endif + +#ifndef ES_I2C1_SCL_GPIO_FUNC +#define ES_I2C1_SCL_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C1_SCL_GPIO_PORT +#define ES_I2C1_SCL_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C1_SCL_GPIO_PIN +#define ES_I2C1_SCL_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_I2C1_SCL_PIN +#ifdef ES_PIN_GPIO_B_10 +#define ES_I2C1_SCL_PIN ES_PIN_GPIO_B_10 +#endif +#endif + +#ifndef ES_I2C1_SCL_GPIO_FUNC +#define ES_I2C1_SCL_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C1_SCL_GPIO_PORT +#define ES_I2C1_SCL_GPIO_PORT GPIOH +#endif +#ifndef ES_I2C1_SCL_GPIO_PIN +#define ES_I2C1_SCL_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_I2C1_SCL_PIN +#ifdef ES_PIN_GPIO_H_0 +#define ES_I2C1_SCL_PIN ES_PIN_GPIO_H_0 +#endif +#endif + + +/* I2C_SDA */ + + +#ifndef ES_I2C0_SDA_GPIO_FUNC +#define ES_I2C0_SDA_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C0_SDA_GPIO_PORT +#define ES_I2C0_SDA_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C0_SDA_GPIO_PIN +#define ES_I2C0_SDA_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_I2C0_SDA_PIN +#ifdef ES_PIN_GPIO_B_7 +#define ES_I2C0_SDA_PIN ES_PIN_GPIO_B_7 +#endif +#endif + +#ifndef ES_I2C0_SDA_GPIO_FUNC +#define ES_I2C0_SDA_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C0_SDA_GPIO_PORT +#define ES_I2C0_SDA_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C0_SDA_GPIO_PIN +#define ES_I2C0_SDA_GPIO_PIN GPIO_PIN_9 +#endif + +#ifndef ES_I2C0_SDA_PIN +#ifdef ES_PIN_GPIO_B_9 +#define ES_I2C0_SDA_PIN ES_PIN_GPIO_B_9 +#endif +#endif + +#ifndef ES_I2C1_SDA_GPIO_FUNC +#define ES_I2C1_SDA_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C1_SDA_GPIO_PORT +#define ES_I2C1_SDA_GPIO_PORT GPIOA +#endif +#ifndef ES_I2C1_SDA_GPIO_PIN +#define ES_I2C1_SDA_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_I2C1_SDA_PIN +#ifdef ES_PIN_GPIO_A_6 +#define ES_I2C1_SDA_PIN ES_PIN_GPIO_A_6 +#endif +#endif + +#ifndef ES_I2C1_SDA_GPIO_FUNC +#define ES_I2C1_SDA_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C1_SDA_GPIO_PORT +#define ES_I2C1_SDA_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C1_SDA_GPIO_PIN +#define ES_I2C1_SDA_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_I2C1_SDA_PIN +#ifdef ES_PIN_GPIO_B_11 +#define ES_I2C1_SDA_PIN ES_PIN_GPIO_B_11 +#endif +#endif + +#ifndef ES_I2C1_SDA_GPIO_FUNC +#define ES_I2C1_SDA_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C1_SDA_GPIO_PORT +#define ES_I2C1_SDA_GPIO_PORT GPIOH +#endif +#ifndef ES_I2C1_SDA_GPIO_PIN +#define ES_I2C1_SDA_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_I2C1_SDA_PIN +#ifdef ES_PIN_GPIO_H_1 +#define ES_I2C1_SDA_PIN ES_PIN_GPIO_H_1 +#endif +#endif + + +/* SPI_MISO */ + + +#ifndef ES_SPI0_MISO_GPIO_FUNC +#define ES_SPI0_MISO_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_MISO_GPIO_PORT +#define ES_SPI0_MISO_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI0_MISO_GPIO_PIN +#define ES_SPI0_MISO_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_SPI0_MISO_PIN +#ifdef ES_PIN_GPIO_B_4 +#define ES_SPI0_MISO_PIN ES_PIN_GPIO_B_4 +#endif +#endif + +#ifndef ES_SPI0_MISO_GPIO_FUNC +#define ES_SPI0_MISO_GPIO_FUNC GPIO_FUNC_6 +#endif +#ifndef ES_SPI0_MISO_GPIO_PORT +#define ES_SPI0_MISO_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI0_MISO_GPIO_PIN +#define ES_SPI0_MISO_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_SPI0_MISO_PIN +#ifdef ES_PIN_GPIO_A_6 +#define ES_SPI0_MISO_PIN ES_PIN_GPIO_A_6 +#endif +#endif + +#ifndef ES_SPI0_MISO_GPIO_FUNC +#define ES_SPI0_MISO_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_MISO_GPIO_PORT +#define ES_SPI0_MISO_GPIO_PORT GPIOD +#endif +#ifndef ES_SPI0_MISO_GPIO_PIN +#define ES_SPI0_MISO_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_SPI0_MISO_PIN +#ifdef ES_PIN_GPIO_D_4 +#define ES_SPI0_MISO_PIN ES_PIN_GPIO_D_4 +#endif +#endif + +#ifndef ES_SPI1_MISO_GPIO_FUNC +#define ES_SPI1_MISO_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_MISO_GPIO_PORT +#define ES_SPI1_MISO_GPIO_PORT GPIOC +#endif +#ifndef ES_SPI1_MISO_GPIO_PIN +#define ES_SPI1_MISO_GPIO_PIN GPIO_PIN_2 +#endif + +#ifndef ES_SPI1_MISO_PIN +#ifdef ES_PIN_GPIO_C_2 +#define ES_SPI1_MISO_PIN ES_PIN_GPIO_C_2 +#endif +#endif + +#ifndef ES_SPI1_MISO_GPIO_FUNC +#define ES_SPI1_MISO_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_MISO_GPIO_PORT +#define ES_SPI1_MISO_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI1_MISO_GPIO_PIN +#define ES_SPI1_MISO_GPIO_PIN GPIO_PIN_14 +#endif + +#ifndef ES_SPI1_MISO_PIN +#ifdef ES_PIN_GPIO_B_14 +#define ES_SPI1_MISO_PIN ES_PIN_GPIO_B_14 +#endif +#endif + +#ifndef ES_SPI2_MISO_GPIO_FUNC +#define ES_SPI2_MISO_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_SPI2_MISO_GPIO_PORT +#define ES_SPI2_MISO_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI2_MISO_GPIO_PIN +#define ES_SPI2_MISO_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_SPI2_MISO_PIN +#ifdef ES_PIN_GPIO_B_4 +#define ES_SPI2_MISO_PIN ES_PIN_GPIO_B_4 +#endif +#endif + +#ifndef ES_SPI2_MISO_GPIO_FUNC +#define ES_SPI2_MISO_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_SPI2_MISO_GPIO_PORT +#define ES_SPI2_MISO_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI2_MISO_GPIO_PIN +#define ES_SPI2_MISO_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_SPI2_MISO_PIN +#ifdef ES_PIN_GPIO_B_0 +#define ES_SPI2_MISO_PIN ES_PIN_GPIO_B_0 +#endif +#endif + + +/* SPI_MOSI */ + + +#ifndef ES_SPI0_MOSI_GPIO_FUNC +#define ES_SPI0_MOSI_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_MOSI_GPIO_PORT +#define ES_SPI0_MOSI_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI0_MOSI_GPIO_PIN +#define ES_SPI0_MOSI_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_SPI0_MOSI_PIN +#ifdef ES_PIN_GPIO_B_5 +#define ES_SPI0_MOSI_PIN ES_PIN_GPIO_B_5 +#endif +#endif + +#ifndef ES_SPI0_MOSI_GPIO_FUNC +#define ES_SPI0_MOSI_GPIO_FUNC GPIO_FUNC_6 +#endif +#ifndef ES_SPI0_MOSI_GPIO_PORT +#define ES_SPI0_MOSI_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI0_MOSI_GPIO_PIN +#define ES_SPI0_MOSI_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_SPI0_MOSI_PIN +#ifdef ES_PIN_GPIO_A_7 +#define ES_SPI0_MOSI_PIN ES_PIN_GPIO_A_7 +#endif +#endif + +#ifndef ES_SPI0_MOSI_GPIO_FUNC +#define ES_SPI0_MOSI_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_MOSI_GPIO_PORT +#define ES_SPI0_MOSI_GPIO_PORT GPIOD +#endif +#ifndef ES_SPI0_MOSI_GPIO_PIN +#define ES_SPI0_MOSI_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_SPI0_MOSI_PIN +#ifdef ES_PIN_GPIO_D_7 +#define ES_SPI0_MOSI_PIN ES_PIN_GPIO_D_7 +#endif +#endif + +#ifndef ES_SPI1_MOSI_GPIO_FUNC +#define ES_SPI1_MOSI_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_MOSI_GPIO_PORT +#define ES_SPI1_MOSI_GPIO_PORT GPIOC +#endif +#ifndef ES_SPI1_MOSI_GPIO_PIN +#define ES_SPI1_MOSI_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_SPI1_MOSI_PIN +#ifdef ES_PIN_GPIO_C_3 +#define ES_SPI1_MOSI_PIN ES_PIN_GPIO_C_3 +#endif +#endif + +#ifndef ES_SPI1_MOSI_GPIO_FUNC +#define ES_SPI1_MOSI_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_MOSI_GPIO_PORT +#define ES_SPI1_MOSI_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI1_MOSI_GPIO_PIN +#define ES_SPI1_MOSI_GPIO_PIN GPIO_PIN_15 +#endif + +#ifndef ES_SPI1_MOSI_PIN +#ifdef ES_PIN_GPIO_B_15 +#define ES_SPI1_MOSI_PIN ES_PIN_GPIO_B_15 +#endif +#endif + +#ifndef ES_SPI2_MOSI_GPIO_FUNC +#define ES_SPI2_MOSI_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_SPI2_MOSI_GPIO_PORT +#define ES_SPI2_MOSI_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI2_MOSI_GPIO_PIN +#define ES_SPI2_MOSI_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_SPI2_MOSI_PIN +#ifdef ES_PIN_GPIO_B_5 +#define ES_SPI2_MOSI_PIN ES_PIN_GPIO_B_5 +#endif +#endif + +#ifndef ES_SPI2_MOSI_GPIO_FUNC +#define ES_SPI2_MOSI_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_SPI2_MOSI_GPIO_PORT +#define ES_SPI2_MOSI_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI2_MOSI_GPIO_PIN +#define ES_SPI2_MOSI_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_SPI2_MOSI_PIN +#ifdef ES_PIN_GPIO_B_1 +#define ES_SPI2_MOSI_PIN ES_PIN_GPIO_B_1 +#endif +#endif + + +/* SPI_SCK */ + + +#ifndef ES_SPI0_SCK_GPIO_FUNC +#define ES_SPI0_SCK_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_SCK_GPIO_PORT +#define ES_SPI0_SCK_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI0_SCK_GPIO_PIN +#define ES_SPI0_SCK_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_SPI0_SCK_PIN +#ifdef ES_PIN_GPIO_B_3 +#define ES_SPI0_SCK_PIN ES_PIN_GPIO_B_3 +#endif +#endif + +#ifndef ES_SPI0_SCK_GPIO_FUNC +#define ES_SPI0_SCK_GPIO_FUNC GPIO_FUNC_6 +#endif +#ifndef ES_SPI0_SCK_GPIO_PORT +#define ES_SPI0_SCK_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI0_SCK_GPIO_PIN +#define ES_SPI0_SCK_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_SPI0_SCK_PIN +#ifdef ES_PIN_GPIO_A_5 +#define ES_SPI0_SCK_PIN ES_PIN_GPIO_A_5 +#endif +#endif + +#ifndef ES_SPI0_SCK_GPIO_FUNC +#define ES_SPI0_SCK_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_SCK_GPIO_PORT +#define ES_SPI0_SCK_GPIO_PORT GPIOD +#endif +#ifndef ES_SPI0_SCK_GPIO_PIN +#define ES_SPI0_SCK_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_SPI0_SCK_PIN +#ifdef ES_PIN_GPIO_D_3 +#define ES_SPI0_SCK_PIN ES_PIN_GPIO_D_3 +#endif +#endif + +#ifndef ES_SPI1_SCK_GPIO_FUNC +#define ES_SPI1_SCK_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_SCK_GPIO_PORT +#define ES_SPI1_SCK_GPIO_PORT GPIOC +#endif +#ifndef ES_SPI1_SCK_GPIO_PIN +#define ES_SPI1_SCK_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_SPI1_SCK_PIN +#ifdef ES_PIN_GPIO_C_1 +#define ES_SPI1_SCK_PIN ES_PIN_GPIO_C_1 +#endif +#endif + +#ifndef ES_SPI1_SCK_GPIO_FUNC +#define ES_SPI1_SCK_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_SCK_GPIO_PORT +#define ES_SPI1_SCK_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI1_SCK_GPIO_PIN +#define ES_SPI1_SCK_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_SPI1_SCK_PIN +#ifdef ES_PIN_GPIO_B_13 +#define ES_SPI1_SCK_PIN ES_PIN_GPIO_B_13 +#endif +#endif + +#ifndef ES_SPI2_SCK_GPIO_FUNC +#define ES_SPI2_SCK_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_SPI2_SCK_GPIO_PORT +#define ES_SPI2_SCK_GPIO_PORT GPIOC +#endif +#ifndef ES_SPI2_SCK_GPIO_PIN +#define ES_SPI2_SCK_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_SPI2_SCK_PIN +#ifdef ES_PIN_GPIO_C_5 +#define ES_SPI2_SCK_PIN ES_PIN_GPIO_C_5 +#endif +#endif + +#ifndef ES_SPI2_SCK_GPIO_FUNC +#define ES_SPI2_SCK_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_SPI2_SCK_GPIO_PORT +#define ES_SPI2_SCK_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI2_SCK_GPIO_PIN +#define ES_SPI2_SCK_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_SPI2_SCK_PIN +#ifdef ES_PIN_GPIO_B_3 +#define ES_SPI2_SCK_PIN ES_PIN_GPIO_B_3 +#endif +#endif + + +/* SPI_NSS */ + + +#ifndef ES_SPI0_NSS_GPIO_FUNC +#define ES_SPI0_NSS_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_NSS_GPIO_PORT +#define ES_SPI0_NSS_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI0_NSS_GPIO_PIN +#define ES_SPI0_NSS_GPIO_PIN GPIO_PIN_15 +#endif + +#ifndef ES_SPI0_NSS_PIN +#ifdef ES_PIN_GPIO_A_15 +#define ES_SPI0_NSS_PIN ES_PIN_GPIO_A_15 +#endif +#endif + +#ifndef ES_SPI0_NSS_GPIO_FUNC +#define ES_SPI0_NSS_GPIO_FUNC GPIO_FUNC_6 +#endif +#ifndef ES_SPI0_NSS_GPIO_PORT +#define ES_SPI0_NSS_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI0_NSS_GPIO_PIN +#define ES_SPI0_NSS_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_SPI0_NSS_PIN +#ifdef ES_PIN_GPIO_A_4 +#define ES_SPI0_NSS_PIN ES_PIN_GPIO_A_4 +#endif +#endif + +#ifndef ES_SPI1_NSS_GPIO_FUNC +#define ES_SPI1_NSS_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_NSS_GPIO_PORT +#define ES_SPI1_NSS_GPIO_PORT GPIOC +#endif +#ifndef ES_SPI1_NSS_GPIO_PIN +#define ES_SPI1_NSS_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_SPI1_NSS_PIN +#ifdef ES_PIN_GPIO_C_0 +#define ES_SPI1_NSS_PIN ES_PIN_GPIO_C_0 +#endif +#endif + +#ifndef ES_SPI1_NSS_GPIO_FUNC +#define ES_SPI1_NSS_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_NSS_GPIO_PORT +#define ES_SPI1_NSS_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI1_NSS_GPIO_PIN +#define ES_SPI1_NSS_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_SPI1_NSS_PIN +#ifdef ES_PIN_GPIO_B_12 +#define ES_SPI1_NSS_PIN ES_PIN_GPIO_B_12 +#endif +#endif + +#ifndef ES_SPI2_NSS_GPIO_FUNC +#define ES_SPI2_NSS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_SPI2_NSS_GPIO_PORT +#define ES_SPI2_NSS_GPIO_PORT GPIOC +#endif +#ifndef ES_SPI2_NSS_GPIO_PIN +#define ES_SPI2_NSS_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_SPI2_NSS_PIN +#ifdef ES_PIN_GPIO_C_4 +#define ES_SPI2_NSS_PIN ES_PIN_GPIO_C_4 +#endif +#endif + +#ifndef ES_SPI2_NSS_GPIO_FUNC +#define ES_SPI2_NSS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_SPI2_NSS_GPIO_PORT +#define ES_SPI2_NSS_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI2_NSS_GPIO_PIN +#define ES_SPI2_NSS_GPIO_PIN GPIO_PIN_15 +#endif + +#ifndef ES_SPI2_NSS_PIN +#ifdef ES_PIN_GPIO_A_15 +#define ES_SPI2_NSS_PIN ES_PIN_GPIO_A_15 +#endif +#endif + + +/* CAN_TX */ + + +#ifndef ES_CAN0_TX_GPIO_FUNC +#define ES_CAN0_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_CAN0_TX_GPIO_PORT +#define ES_CAN0_TX_GPIO_PORT GPIOB +#endif +#ifndef ES_CAN0_TX_GPIO_PIN +#define ES_CAN0_TX_GPIO_PIN GPIO_PIN_9 +#endif + +#ifndef ES_CAN0_TX_PIN +#ifdef ES_PIN_GPIO_B_9 +#define ES_CAN0_TX_PIN ES_PIN_GPIO_B_9 +#endif +#endif + + +/* CAN_RX */ + + +#ifndef ES_CAN0_RX_GPIO_FUNC +#define ES_CAN0_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_CAN0_RX_GPIO_PORT +#define ES_CAN0_RX_GPIO_PORT GPIOB +#endif +#ifndef ES_CAN0_RX_GPIO_PIN +#define ES_CAN0_RX_GPIO_PIN GPIO_PIN_8 +#endif + +#ifndef ES_CAN0_RX_PIN +#ifdef ES_PIN_GPIO_B_8 +#define ES_CAN0_RX_PIN ES_PIN_GPIO_B_8 +#endif +#endif + + +/* AD16C4T_CH1 */ + + +#ifndef ES_AD16C4T0_CH1_GPIO_FUNC +#define ES_AD16C4T0_CH1_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_AD16C4T0_CH1_GPIO_PORT +#define ES_AD16C4T0_CH1_GPIO_PORT GPIOA +#endif +#ifndef ES_AD16C4T0_CH1_GPIO_PIN +#define ES_AD16C4T0_CH1_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_AD16C4T0_CH1_PIN +#ifdef ES_PIN_GPIO_A_7 +#define ES_AD16C4T0_CH1_PIN ES_PIN_GPIO_A_7 +#endif +#endif + +#ifndef ES_AD16C4T0_CH1_GPIO_FUNC +#define ES_AD16C4T0_CH1_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH1_GPIO_PORT +#define ES_AD16C4T0_CH1_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_CH1_GPIO_PIN +#define ES_AD16C4T0_CH1_GPIO_PIN GPIO_PIN_9 +#endif + +#ifndef ES_AD16C4T0_CH1_PIN +#ifdef ES_PIN_GPIO_E_9 +#define ES_AD16C4T0_CH1_PIN ES_PIN_GPIO_E_9 +#endif +#endif + +#ifndef ES_AD16C4T1_CH1_GPIO_FUNC +#define ES_AD16C4T1_CH1_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T1_CH1_GPIO_PORT +#define ES_AD16C4T1_CH1_GPIO_PORT GPIOC +#endif +#ifndef ES_AD16C4T1_CH1_GPIO_PIN +#define ES_AD16C4T1_CH1_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_AD16C4T1_CH1_PIN +#ifdef ES_PIN_GPIO_C_6 +#define ES_AD16C4T1_CH1_PIN ES_PIN_GPIO_C_6 +#endif +#endif + + +/* AD16C4T_CH2 */ + + +#ifndef ES_AD16C4T0_CH2_GPIO_FUNC +#define ES_AD16C4T0_CH2_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH2_GPIO_PORT +#define ES_AD16C4T0_CH2_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_CH2_GPIO_PIN +#define ES_AD16C4T0_CH2_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_AD16C4T0_CH2_PIN +#ifdef ES_PIN_GPIO_E_11 +#define ES_AD16C4T0_CH2_PIN ES_PIN_GPIO_E_11 +#endif +#endif + +#ifndef ES_AD16C4T1_CH2_GPIO_FUNC +#define ES_AD16C4T1_CH2_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T1_CH2_GPIO_PORT +#define ES_AD16C4T1_CH2_GPIO_PORT GPIOC +#endif +#ifndef ES_AD16C4T1_CH2_GPIO_PIN +#define ES_AD16C4T1_CH2_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_AD16C4T1_CH2_PIN +#ifdef ES_PIN_GPIO_C_7 +#define ES_AD16C4T1_CH2_PIN ES_PIN_GPIO_C_7 +#endif +#endif + + +/* AD16C4T_CH3 */ + + +#ifndef ES_AD16C4T0_CH3_GPIO_FUNC +#define ES_AD16C4T0_CH3_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH3_GPIO_PORT +#define ES_AD16C4T0_CH3_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_CH3_GPIO_PIN +#define ES_AD16C4T0_CH3_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_AD16C4T0_CH3_PIN +#ifdef ES_PIN_GPIO_E_13 +#define ES_AD16C4T0_CH3_PIN ES_PIN_GPIO_E_13 +#endif +#endif + +#ifndef ES_AD16C4T1_CH3_GPIO_FUNC +#define ES_AD16C4T1_CH3_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T1_CH3_GPIO_PORT +#define ES_AD16C4T1_CH3_GPIO_PORT GPIOC +#endif +#ifndef ES_AD16C4T1_CH3_GPIO_PIN +#define ES_AD16C4T1_CH3_GPIO_PIN GPIO_PIN_8 +#endif + +#ifndef ES_AD16C4T1_CH3_PIN +#ifdef ES_PIN_GPIO_C_8 +#define ES_AD16C4T1_CH3_PIN ES_PIN_GPIO_C_8 +#endif +#endif + + +/* AD16C4T_CH4 */ + + +#ifndef ES_AD16C4T0_CH4_GPIO_FUNC +#define ES_AD16C4T0_CH4_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH4_GPIO_PORT +#define ES_AD16C4T0_CH4_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_CH4_GPIO_PIN +#define ES_AD16C4T0_CH4_GPIO_PIN GPIO_PIN_14 +#endif + +#ifndef ES_AD16C4T0_CH4_PIN +#ifdef ES_PIN_GPIO_E_14 +#define ES_AD16C4T0_CH4_PIN ES_PIN_GPIO_E_14 +#endif +#endif + + +/* AD16C4T_CH1N */ + + +#ifndef ES_AD16C4T0_CH1N_GPIO_FUNC +#define ES_AD16C4T0_CH1N_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH1N_GPIO_PORT +#define ES_AD16C4T0_CH1N_GPIO_PORT GPIOB +#endif +#ifndef ES_AD16C4T0_CH1N_GPIO_PIN +#define ES_AD16C4T0_CH1N_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_AD16C4T0_CH1N_PIN +#ifdef ES_PIN_GPIO_B_13 +#define ES_AD16C4T0_CH1N_PIN ES_PIN_GPIO_B_13 +#endif +#endif + +#ifndef ES_AD16C4T0_CH1N_GPIO_FUNC +#define ES_AD16C4T0_CH1N_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH1N_GPIO_PORT +#define ES_AD16C4T0_CH1N_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_CH1N_GPIO_PIN +#define ES_AD16C4T0_CH1N_GPIO_PIN GPIO_PIN_8 +#endif + +#ifndef ES_AD16C4T0_CH1N_PIN +#ifdef ES_PIN_GPIO_E_8 +#define ES_AD16C4T0_CH1N_PIN ES_PIN_GPIO_E_8 +#endif +#endif + +#ifndef ES_AD16C4T1_CH1N_GPIO_FUNC +#define ES_AD16C4T1_CH1N_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T1_CH1N_GPIO_PORT +#define ES_AD16C4T1_CH1N_GPIO_PORT GPIOA +#endif +#ifndef ES_AD16C4T1_CH1N_GPIO_PIN +#define ES_AD16C4T1_CH1N_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_AD16C4T1_CH1N_PIN +#ifdef ES_PIN_GPIO_A_7 +#define ES_AD16C4T1_CH1N_PIN ES_PIN_GPIO_A_7 +#endif +#endif + + +/* AD16C4T_CH2N */ + + +#ifndef ES_AD16C4T0_CH2N_GPIO_FUNC +#define ES_AD16C4T0_CH2N_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH2N_GPIO_PORT +#define ES_AD16C4T0_CH2N_GPIO_PORT GPIOB +#endif +#ifndef ES_AD16C4T0_CH2N_GPIO_PIN +#define ES_AD16C4T0_CH2N_GPIO_PIN GPIO_PIN_14 +#endif + +#ifndef ES_AD16C4T0_CH2N_PIN +#ifdef ES_PIN_GPIO_B_14 +#define ES_AD16C4T0_CH2N_PIN ES_PIN_GPIO_B_14 +#endif +#endif + +#ifndef ES_AD16C4T0_CH2N_GPIO_FUNC +#define ES_AD16C4T0_CH2N_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH2N_GPIO_PORT +#define ES_AD16C4T0_CH2N_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_CH2N_GPIO_PIN +#define ES_AD16C4T0_CH2N_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_AD16C4T0_CH2N_PIN +#ifdef ES_PIN_GPIO_E_10 +#define ES_AD16C4T0_CH2N_PIN ES_PIN_GPIO_E_10 +#endif +#endif + +#ifndef ES_AD16C4T1_CH2N_GPIO_FUNC +#define ES_AD16C4T1_CH2N_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_AD16C4T1_CH2N_GPIO_PORT +#define ES_AD16C4T1_CH2N_GPIO_PORT GPIOB +#endif +#ifndef ES_AD16C4T1_CH2N_GPIO_PIN +#define ES_AD16C4T1_CH2N_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_AD16C4T1_CH2N_PIN +#ifdef ES_PIN_GPIO_B_0 +#define ES_AD16C4T1_CH2N_PIN ES_PIN_GPIO_B_0 +#endif +#endif + + +/* AD16C4T_CH3N */ + + +#ifndef ES_AD16C4T0_CH3N_GPIO_FUNC +#define ES_AD16C4T0_CH3N_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH3N_GPIO_PORT +#define ES_AD16C4T0_CH3N_GPIO_PORT GPIOB +#endif +#ifndef ES_AD16C4T0_CH3N_GPIO_PIN +#define ES_AD16C4T0_CH3N_GPIO_PIN GPIO_PIN_15 +#endif + +#ifndef ES_AD16C4T0_CH3N_PIN +#ifdef ES_PIN_GPIO_B_15 +#define ES_AD16C4T0_CH3N_PIN ES_PIN_GPIO_B_15 +#endif +#endif + +#ifndef ES_AD16C4T0_CH3N_GPIO_FUNC +#define ES_AD16C4T0_CH3N_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH3N_GPIO_PORT +#define ES_AD16C4T0_CH3N_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_CH3N_GPIO_PIN +#define ES_AD16C4T0_CH3N_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_AD16C4T0_CH3N_PIN +#ifdef ES_PIN_GPIO_E_12 +#define ES_AD16C4T0_CH3N_PIN ES_PIN_GPIO_E_12 +#endif +#endif + +#ifndef ES_AD16C4T1_CH3N_GPIO_FUNC +#define ES_AD16C4T1_CH3N_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_AD16C4T1_CH3N_GPIO_PORT +#define ES_AD16C4T1_CH3N_GPIO_PORT GPIOB +#endif +#ifndef ES_AD16C4T1_CH3N_GPIO_PIN +#define ES_AD16C4T1_CH3N_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_AD16C4T1_CH3N_PIN +#ifdef ES_PIN_GPIO_B_1 +#define ES_AD16C4T1_CH3N_PIN ES_PIN_GPIO_B_1 +#endif +#endif + + +/* AD16C4T_CH4N */ + + + +/* AD16C4T_ET */ + + +#ifndef ES_AD16C4T0_ET_GPIO_FUNC +#define ES_AD16C4T0_ET_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_ET_GPIO_PORT +#define ES_AD16C4T0_ET_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_ET_GPIO_PIN +#define ES_AD16C4T0_ET_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_AD16C4T0_ET_PIN +#ifdef ES_PIN_GPIO_E_7 +#define ES_AD16C4T0_ET_PIN ES_PIN_GPIO_E_7 +#endif +#endif + +#ifndef ES_AD16C4T1_ET_GPIO_FUNC +#define ES_AD16C4T1_ET_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_AD16C4T1_ET_GPIO_PORT +#define ES_AD16C4T1_ET_GPIO_PORT GPIOA +#endif +#ifndef ES_AD16C4T1_ET_GPIO_PIN +#define ES_AD16C4T1_ET_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_AD16C4T1_ET_PIN +#ifdef ES_PIN_GPIO_A_0 +#define ES_AD16C4T1_ET_PIN ES_PIN_GPIO_A_0 +#endif +#endif + + +/* GP32C4T_CH1 */ + + +#ifndef ES_GP32C4T0_CH1_GPIO_FUNC +#define ES_GP32C4T0_CH1_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T0_CH1_GPIO_PORT +#define ES_GP32C4T0_CH1_GPIO_PORT GPIOA +#endif +#ifndef ES_GP32C4T0_CH1_GPIO_PIN +#define ES_GP32C4T0_CH1_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_GP32C4T0_CH1_PIN +#ifdef ES_PIN_GPIO_A_0 +#define ES_GP32C4T0_CH1_PIN ES_PIN_GPIO_A_0 +#endif +#endif + +#ifndef ES_GP32C4T0_CH1_GPIO_FUNC +#define ES_GP32C4T0_CH1_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T0_CH1_GPIO_PORT +#define ES_GP32C4T0_CH1_GPIO_PORT GPIOA +#endif +#ifndef ES_GP32C4T0_CH1_GPIO_PIN +#define ES_GP32C4T0_CH1_GPIO_PIN GPIO_PIN_15 +#endif + +#ifndef ES_GP32C4T0_CH1_PIN +#ifdef ES_PIN_GPIO_A_15 +#define ES_GP32C4T0_CH1_PIN ES_PIN_GPIO_A_15 +#endif +#endif + +#ifndef ES_GP32C4T1_CH1_GPIO_FUNC +#define ES_GP32C4T1_CH1_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_GP32C4T1_CH1_GPIO_PORT +#define ES_GP32C4T1_CH1_GPIO_PORT GPIOA +#endif +#ifndef ES_GP32C4T1_CH1_GPIO_PIN +#define ES_GP32C4T1_CH1_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_GP32C4T1_CH1_PIN +#ifdef ES_PIN_GPIO_A_6 +#define ES_GP32C4T1_CH1_PIN ES_PIN_GPIO_A_6 +#endif +#endif + +#ifndef ES_GP32C4T1_CH1_GPIO_FUNC +#define ES_GP32C4T1_CH1_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_GP32C4T1_CH1_GPIO_PORT +#define ES_GP32C4T1_CH1_GPIO_PORT GPIOC +#endif +#ifndef ES_GP32C4T1_CH1_GPIO_PIN +#define ES_GP32C4T1_CH1_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_GP32C4T1_CH1_PIN +#ifdef ES_PIN_GPIO_C_6 +#define ES_GP32C4T1_CH1_PIN ES_PIN_GPIO_C_6 +#endif +#endif + +#ifndef ES_GP32C4T1_CH1_GPIO_FUNC +#define ES_GP32C4T1_CH1_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T1_CH1_GPIO_PORT +#define ES_GP32C4T1_CH1_GPIO_PORT GPIOB +#endif +#ifndef ES_GP32C4T1_CH1_GPIO_PIN +#define ES_GP32C4T1_CH1_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_GP32C4T1_CH1_PIN +#ifdef ES_PIN_GPIO_B_4 +#define ES_GP32C4T1_CH1_PIN ES_PIN_GPIO_B_4 +#endif +#endif + + +/* GP32C4T_CH2 */ + + +#ifndef ES_GP32C4T0_CH2_GPIO_FUNC +#define ES_GP32C4T0_CH2_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T0_CH2_GPIO_PORT +#define ES_GP32C4T0_CH2_GPIO_PORT GPIOA +#endif +#ifndef ES_GP32C4T0_CH2_GPIO_PIN +#define ES_GP32C4T0_CH2_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_GP32C4T0_CH2_PIN +#ifdef ES_PIN_GPIO_A_1 +#define ES_GP32C4T0_CH2_PIN ES_PIN_GPIO_A_1 +#endif +#endif + +#ifndef ES_GP32C4T0_CH2_GPIO_FUNC +#define ES_GP32C4T0_CH2_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T0_CH2_GPIO_PORT +#define ES_GP32C4T0_CH2_GPIO_PORT GPIOB +#endif +#ifndef ES_GP32C4T0_CH2_GPIO_PIN +#define ES_GP32C4T0_CH2_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_GP32C4T0_CH2_PIN +#ifdef ES_PIN_GPIO_B_3 +#define ES_GP32C4T0_CH2_PIN ES_PIN_GPIO_B_3 +#endif +#endif + +#ifndef ES_GP32C4T1_CH2_GPIO_FUNC +#define ES_GP32C4T1_CH2_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T1_CH2_GPIO_PORT +#define ES_GP32C4T1_CH2_GPIO_PORT GPIOB +#endif +#ifndef ES_GP32C4T1_CH2_GPIO_PIN +#define ES_GP32C4T1_CH2_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_GP32C4T1_CH2_PIN +#ifdef ES_PIN_GPIO_B_5 +#define ES_GP32C4T1_CH2_PIN ES_PIN_GPIO_B_5 +#endif +#endif + +#ifndef ES_GP32C4T1_CH2_GPIO_FUNC +#define ES_GP32C4T1_CH2_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_GP32C4T1_CH2_GPIO_PORT +#define ES_GP32C4T1_CH2_GPIO_PORT GPIOA +#endif +#ifndef ES_GP32C4T1_CH2_GPIO_PIN +#define ES_GP32C4T1_CH2_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_GP32C4T1_CH2_PIN +#ifdef ES_PIN_GPIO_A_7 +#define ES_GP32C4T1_CH2_PIN ES_PIN_GPIO_A_7 +#endif +#endif + +#ifndef ES_GP32C4T1_CH2_GPIO_FUNC +#define ES_GP32C4T1_CH2_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_GP32C4T1_CH2_GPIO_PORT +#define ES_GP32C4T1_CH2_GPIO_PORT GPIOC +#endif +#ifndef ES_GP32C4T1_CH2_GPIO_PIN +#define ES_GP32C4T1_CH2_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_GP32C4T1_CH2_PIN +#ifdef ES_PIN_GPIO_C_7 +#define ES_GP32C4T1_CH2_PIN ES_PIN_GPIO_C_7 +#endif +#endif + + +/* GP32C4T_CH3 */ + + +#ifndef ES_GP32C4T0_CH3_GPIO_FUNC +#define ES_GP32C4T0_CH3_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T0_CH3_GPIO_PORT +#define ES_GP32C4T0_CH3_GPIO_PORT GPIOA +#endif +#ifndef ES_GP32C4T0_CH3_GPIO_PIN +#define ES_GP32C4T0_CH3_GPIO_PIN GPIO_PIN_2 +#endif + +#ifndef ES_GP32C4T0_CH3_PIN +#ifdef ES_PIN_GPIO_A_2 +#define ES_GP32C4T0_CH3_PIN ES_PIN_GPIO_A_2 +#endif +#endif + +#ifndef ES_GP32C4T0_CH3_GPIO_FUNC +#define ES_GP32C4T0_CH3_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T0_CH3_GPIO_PORT +#define ES_GP32C4T0_CH3_GPIO_PORT GPIOB +#endif +#ifndef ES_GP32C4T0_CH3_GPIO_PIN +#define ES_GP32C4T0_CH3_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_GP32C4T0_CH3_PIN +#ifdef ES_PIN_GPIO_B_10 +#define ES_GP32C4T0_CH3_PIN ES_PIN_GPIO_B_10 +#endif +#endif + +#ifndef ES_GP32C4T1_CH3_GPIO_FUNC +#define ES_GP32C4T1_CH3_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T1_CH3_GPIO_PORT +#define ES_GP32C4T1_CH3_GPIO_PORT GPIOB +#endif +#ifndef ES_GP32C4T1_CH3_GPIO_PIN +#define ES_GP32C4T1_CH3_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_GP32C4T1_CH3_PIN +#ifdef ES_PIN_GPIO_B_0 +#define ES_GP32C4T1_CH3_PIN ES_PIN_GPIO_B_0 +#endif +#endif + +#ifndef ES_GP32C4T1_CH3_GPIO_FUNC +#define ES_GP32C4T1_CH3_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_GP32C4T1_CH3_GPIO_PORT +#define ES_GP32C4T1_CH3_GPIO_PORT GPIOC +#endif +#ifndef ES_GP32C4T1_CH3_GPIO_PIN +#define ES_GP32C4T1_CH3_GPIO_PIN GPIO_PIN_8 +#endif + +#ifndef ES_GP32C4T1_CH3_PIN +#ifdef ES_PIN_GPIO_C_8 +#define ES_GP32C4T1_CH3_PIN ES_PIN_GPIO_C_8 +#endif +#endif + + +/* GP32C4T_CH4 */ + + +#ifndef ES_GP32C4T0_CH4_GPIO_FUNC +#define ES_GP32C4T0_CH4_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T0_CH4_GPIO_PORT +#define ES_GP32C4T0_CH4_GPIO_PORT GPIOB +#endif +#ifndef ES_GP32C4T0_CH4_GPIO_PIN +#define ES_GP32C4T0_CH4_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_GP32C4T0_CH4_PIN +#ifdef ES_PIN_GPIO_B_11 +#define ES_GP32C4T0_CH4_PIN ES_PIN_GPIO_B_11 +#endif +#endif + +#ifndef ES_GP32C4T0_CH4_GPIO_FUNC +#define ES_GP32C4T0_CH4_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T0_CH4_GPIO_PORT +#define ES_GP32C4T0_CH4_GPIO_PORT GPIOA +#endif +#ifndef ES_GP32C4T0_CH4_GPIO_PIN +#define ES_GP32C4T0_CH4_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_GP32C4T0_CH4_PIN +#ifdef ES_PIN_GPIO_A_3 +#define ES_GP32C4T0_CH4_PIN ES_PIN_GPIO_A_3 +#endif +#endif + +#ifndef ES_GP32C4T1_CH4_GPIO_FUNC +#define ES_GP32C4T1_CH4_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T1_CH4_GPIO_PORT +#define ES_GP32C4T1_CH4_GPIO_PORT GPIOB +#endif +#ifndef ES_GP32C4T1_CH4_GPIO_PIN +#define ES_GP32C4T1_CH4_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_GP32C4T1_CH4_PIN +#ifdef ES_PIN_GPIO_B_1 +#define ES_GP32C4T1_CH4_PIN ES_PIN_GPIO_B_1 +#endif +#endif + + +/* GP32C4T_ET */ + + +#ifndef ES_GP32C4T0_ET_GPIO_FUNC +#define ES_GP32C4T0_ET_GPIO_FUNC GPIO_FUNC_6 +#endif +#ifndef ES_GP32C4T0_ET_GPIO_PORT +#define ES_GP32C4T0_ET_GPIO_PORT GPIOA +#endif +#ifndef ES_GP32C4T0_ET_GPIO_PIN +#define ES_GP32C4T0_ET_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_GP32C4T0_ET_PIN +#ifdef ES_PIN_GPIO_A_0 +#define ES_GP32C4T0_ET_PIN ES_PIN_GPIO_A_0 +#endif +#endif + +#ifndef ES_GP32C4T0_ET_GPIO_FUNC +#define ES_GP32C4T0_ET_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_GP32C4T0_ET_GPIO_PORT +#define ES_GP32C4T0_ET_GPIO_PORT GPIOA +#endif +#ifndef ES_GP32C4T0_ET_GPIO_PIN +#define ES_GP32C4T0_ET_GPIO_PIN GPIO_PIN_15 +#endif + +#ifndef ES_GP32C4T0_ET_PIN +#ifdef ES_PIN_GPIO_A_15 +#define ES_GP32C4T0_ET_PIN ES_PIN_GPIO_A_15 +#endif +#endif + +#ifndef ES_GP32C4T1_ET_GPIO_FUNC +#define ES_GP32C4T1_ET_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T1_ET_GPIO_PORT +#define ES_GP32C4T1_ET_GPIO_PORT GPIOD +#endif +#ifndef ES_GP32C4T1_ET_GPIO_PIN +#define ES_GP32C4T1_ET_GPIO_PIN GPIO_PIN_2 +#endif + +#ifndef ES_GP32C4T1_ET_PIN +#ifdef ES_PIN_GPIO_D_2 +#define ES_GP32C4T1_ET_PIN ES_PIN_GPIO_D_2 +#endif +#endif + + +/* GP16C4T_CH1 */ + + +#ifndef ES_GP16C4T0_CH1_GPIO_FUNC +#define ES_GP16C4T0_CH1_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH1_GPIO_PORT +#define ES_GP16C4T0_CH1_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C4T0_CH1_GPIO_PIN +#define ES_GP16C4T0_CH1_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_GP16C4T0_CH1_PIN +#ifdef ES_PIN_GPIO_B_6 +#define ES_GP16C4T0_CH1_PIN ES_PIN_GPIO_B_6 +#endif +#endif + +#ifndef ES_GP16C4T0_CH1_GPIO_FUNC +#define ES_GP16C4T0_CH1_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH1_GPIO_PORT +#define ES_GP16C4T0_CH1_GPIO_PORT GPIOD +#endif +#ifndef ES_GP16C4T0_CH1_GPIO_PIN +#define ES_GP16C4T0_CH1_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_GP16C4T0_CH1_PIN +#ifdef ES_PIN_GPIO_D_12 +#define ES_GP16C4T0_CH1_PIN ES_PIN_GPIO_D_12 +#endif +#endif + +#ifndef ES_GP16C4T1_CH1_GPIO_FUNC +#define ES_GP16C4T1_CH1_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_GP16C4T1_CH1_GPIO_PORT +#define ES_GP16C4T1_CH1_GPIO_PORT GPIOA +#endif +#ifndef ES_GP16C4T1_CH1_GPIO_PIN +#define ES_GP16C4T1_CH1_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_GP16C4T1_CH1_PIN +#ifdef ES_PIN_GPIO_A_0 +#define ES_GP16C4T1_CH1_PIN ES_PIN_GPIO_A_0 +#endif +#endif + + +/* GP16C4T_CH2 */ + + +#ifndef ES_GP16C4T0_CH2_GPIO_FUNC +#define ES_GP16C4T0_CH2_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH2_GPIO_PORT +#define ES_GP16C4T0_CH2_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C4T0_CH2_GPIO_PIN +#define ES_GP16C4T0_CH2_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_GP16C4T0_CH2_PIN +#ifdef ES_PIN_GPIO_B_7 +#define ES_GP16C4T0_CH2_PIN ES_PIN_GPIO_B_7 +#endif +#endif + +#ifndef ES_GP16C4T0_CH2_GPIO_FUNC +#define ES_GP16C4T0_CH2_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH2_GPIO_PORT +#define ES_GP16C4T0_CH2_GPIO_PORT GPIOD +#endif +#ifndef ES_GP16C4T0_CH2_GPIO_PIN +#define ES_GP16C4T0_CH2_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_GP16C4T0_CH2_PIN +#ifdef ES_PIN_GPIO_D_13 +#define ES_GP16C4T0_CH2_PIN ES_PIN_GPIO_D_13 +#endif +#endif + +#ifndef ES_GP16C4T1_CH2_GPIO_FUNC +#define ES_GP16C4T1_CH2_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_GP16C4T1_CH2_GPIO_PORT +#define ES_GP16C4T1_CH2_GPIO_PORT GPIOA +#endif +#ifndef ES_GP16C4T1_CH2_GPIO_PIN +#define ES_GP16C4T1_CH2_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_GP16C4T1_CH2_PIN +#ifdef ES_PIN_GPIO_A_1 +#define ES_GP16C4T1_CH2_PIN ES_PIN_GPIO_A_1 +#endif +#endif + + +/* GP16C4T_CH3 */ + + +#ifndef ES_GP16C4T0_CH3_GPIO_FUNC +#define ES_GP16C4T0_CH3_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH3_GPIO_PORT +#define ES_GP16C4T0_CH3_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C4T0_CH3_GPIO_PIN +#define ES_GP16C4T0_CH3_GPIO_PIN GPIO_PIN_8 +#endif + +#ifndef ES_GP16C4T0_CH3_PIN +#ifdef ES_PIN_GPIO_B_8 +#define ES_GP16C4T0_CH3_PIN ES_PIN_GPIO_B_8 +#endif +#endif + +#ifndef ES_GP16C4T0_CH3_GPIO_FUNC +#define ES_GP16C4T0_CH3_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH3_GPIO_PORT +#define ES_GP16C4T0_CH3_GPIO_PORT GPIOD +#endif +#ifndef ES_GP16C4T0_CH3_GPIO_PIN +#define ES_GP16C4T0_CH3_GPIO_PIN GPIO_PIN_14 +#endif + +#ifndef ES_GP16C4T0_CH3_PIN +#ifdef ES_PIN_GPIO_D_14 +#define ES_GP16C4T0_CH3_PIN ES_PIN_GPIO_D_14 +#endif +#endif + +#ifndef ES_GP16C4T1_CH3_GPIO_FUNC +#define ES_GP16C4T1_CH3_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_GP16C4T1_CH3_GPIO_PORT +#define ES_GP16C4T1_CH3_GPIO_PORT GPIOA +#endif +#ifndef ES_GP16C4T1_CH3_GPIO_PIN +#define ES_GP16C4T1_CH3_GPIO_PIN GPIO_PIN_2 +#endif + +#ifndef ES_GP16C4T1_CH3_PIN +#ifdef ES_PIN_GPIO_A_2 +#define ES_GP16C4T1_CH3_PIN ES_PIN_GPIO_A_2 +#endif +#endif + + +/* GP16C4T_CH4 */ + + +#ifndef ES_GP16C4T0_CH4_GPIO_FUNC +#define ES_GP16C4T0_CH4_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH4_GPIO_PORT +#define ES_GP16C4T0_CH4_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C4T0_CH4_GPIO_PIN +#define ES_GP16C4T0_CH4_GPIO_PIN GPIO_PIN_9 +#endif + +#ifndef ES_GP16C4T0_CH4_PIN +#ifdef ES_PIN_GPIO_B_9 +#define ES_GP16C4T0_CH4_PIN ES_PIN_GPIO_B_9 +#endif +#endif + +#ifndef ES_GP16C4T0_CH4_GPIO_FUNC +#define ES_GP16C4T0_CH4_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH4_GPIO_PORT +#define ES_GP16C4T0_CH4_GPIO_PORT GPIOD +#endif +#ifndef ES_GP16C4T0_CH4_GPIO_PIN +#define ES_GP16C4T0_CH4_GPIO_PIN GPIO_PIN_15 +#endif + +#ifndef ES_GP16C4T0_CH4_PIN +#ifdef ES_PIN_GPIO_D_15 +#define ES_GP16C4T0_CH4_PIN ES_PIN_GPIO_D_15 +#endif +#endif + +#ifndef ES_GP16C4T1_CH4_GPIO_FUNC +#define ES_GP16C4T1_CH4_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_GP16C4T1_CH4_GPIO_PORT +#define ES_GP16C4T1_CH4_GPIO_PORT GPIOA +#endif +#ifndef ES_GP16C4T1_CH4_GPIO_PIN +#define ES_GP16C4T1_CH4_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_GP16C4T1_CH4_PIN +#ifdef ES_PIN_GPIO_A_3 +#define ES_GP16C4T1_CH4_PIN ES_PIN_GPIO_A_3 +#endif +#endif + + +/* GP16C4T_ET */ + + +#ifndef ES_GP16C4T0_ET_GPIO_FUNC +#define ES_GP16C4T0_ET_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_ET_GPIO_PORT +#define ES_GP16C4T0_ET_GPIO_PORT GPIOE +#endif +#ifndef ES_GP16C4T0_ET_GPIO_PIN +#define ES_GP16C4T0_ET_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_GP16C4T0_ET_PIN +#ifdef ES_PIN_GPIO_E_0 +#define ES_GP16C4T0_ET_PIN ES_PIN_GPIO_E_0 +#endif +#endif + +#ifndef ES_GP16C4T1_ET_GPIO_FUNC +#define ES_GP16C4T1_ET_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T1_ET_GPIO_PORT +#define ES_GP16C4T1_ET_GPIO_PORT GPIOD +#endif +#ifndef ES_GP16C4T1_ET_GPIO_PIN +#define ES_GP16C4T1_ET_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_GP16C4T1_ET_PIN +#ifdef ES_PIN_GPIO_D_3 +#define ES_GP16C4T1_ET_PIN ES_PIN_GPIO_D_3 +#endif +#endif + + +/* GP16C2T_CH1 */ + + + +/* GP16C2T_CH2 */ + + + +/* GP16C2T_CH1N */ + + + +/* GP16C2T_CH2N */ + + + +#endif diff --git a/bsp/essemi/es32f369x/drivers/ES/es_conf_info_pm.h b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_pm.h new file mode 100644 index 0000000000..580268312c --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_pm.h @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_PM_H__ +#define __ES_CONF_INFO_PM_H__ + +#include +#include + +#define ES_PMU_SAVE_LOAD_UART + +/* PM 配置 */ + + + +#endif diff --git a/bsp/essemi/es32f369x/drivers/ES/es_conf_info_pwm.h b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_pwm.h new file mode 100644 index 0000000000..86010a80ce --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_pwm.h @@ -0,0 +1,78 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_PWM_H__ +#define __ES_CONF_INFO_PWM_H__ + +#include "es_conf_info_map.h" +#include +#include +#include + + +#define ES_C_PWM_OC_POL_HIGH TIMER_OC_POLARITY_HIGH +#define ES_C_PWM_OC_POL_LOW TIMER_OC_POLARITY_LOW + +#define ES_C_PWM_OC_MODE_PWM1 TIMER_OC_MODE_PWM1 +#define ES_C_PWM_OC_MODE_PWM2 TIMER_OC_MODE_PWM2 + + + +/* PWM 配置 */ + + +/* codes_main */ + + + +#define ES_PWM_OC_POLARITY ES_C_PWM_OC_POL_HIGH +#define ES_PWM_OC_MODE ES_C_PWM_OC_MODE_PWM2 + +#ifndef ES_PWM_OC_POLARITY +#define ES_PWM_OC_POLARITY ES_C_PWM_OC_POL_HIGH +#endif +#ifndef ES_PWM_OC_MODE +#define ES_PWM_OC_MODE ES_C_PWM_OC_MODE_PWM2 +#endif + +#ifndef ES_DEVICE_NAME_AD16C4T0_PWM +#define ES_DEVICE_NAME_AD16C4T0_PWM "pwm0" +#endif +#ifndef ES_DEVICE_NAME_AD16C4T1_PWM +#define ES_DEVICE_NAME_AD16C4T1_PWM "pwm1" +#endif +#ifndef ES_DEVICE_NAME_GP32C4T0_PWM +#define ES_DEVICE_NAME_GP32C4T0_PWM "pwm2" +#endif +#ifndef ES_DEVICE_NAME_GP32C4T1_PWM +#define ES_DEVICE_NAME_GP32C4T1_PWM "pwm3" +#endif +#ifndef ES_DEVICE_NAME_GP16C4T0_PWM +#define ES_DEVICE_NAME_GP16C4T0_PWM "pwm4" +#endif +#ifndef ES_DEVICE_NAME_GP16C4T1_PWM +#define ES_DEVICE_NAME_GP16C4T1_PWM "pwm5" +#endif + + +#endif diff --git a/bsp/essemi/es32f369x/drivers/ES/es_conf_info_rtc.h b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_rtc.h new file mode 100644 index 0000000000..2aa8faf9d7 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_rtc.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_RTC_H__ +#define __ES_CONF_INFO_RTC_H__ + +#include +#include + +/* RTC 配置 */ + +#define ES_C_RTC_SOURCE_LRC RTC_SOURCE_LRC +#define ES_C_RTC_SOURCE_LOSC RTC_SOURCE_LOSC + +#define ES_RTC_CLK_SOURCE ES_C_RTC_SOURCE_LOSC + + + + +/* codes_main */ + + +#ifndef ES_DEVICE_NAME_RTC +#define ES_DEVICE_NAME_RTC "rtc" +#endif + +#endif diff --git a/bsp/essemi/es32f369x/drivers/ES/es_conf_info_select.h b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_select.h new file mode 100644 index 0000000000..06a28d6fd0 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_select.h @@ -0,0 +1,43 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_SELECT_H__ +#define __ES_CONF_INFO_SELECT_H__ + + +#define ES_C_ENABLE 1 +#define ES_C_DISABLE 0 + + +/* codes_main */ + +#ifndef ES_USE_ASSERT +#define ES_USE_ASSERT ES_C_DISABLE +#endif + + +#if ES_USE_ASSERT + #define USE_ASSERT +#endif + +#endif diff --git a/bsp/essemi/es32f369x/drivers/ES/es_conf_info_spi.h b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_spi.h new file mode 100644 index 0000000000..c9cf895aeb --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_spi.h @@ -0,0 +1,159 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_SPI_H__ +#define __ES_CONF_INFO_SPI_H__ + +#include "es_conf_info_map.h" +#include +#include +#include + +/* SPI 配置 */ + +#define SPI_BUS_CONFIG(_CONF_,_I_) do{_CONF_.mode = 0U; \ + _CONF_.mode |= ( ES_SPI##_I_##_MASTER_SLAVE | \ + ES_SPI##_I_##_WIRE_3_4 | \ + ES_SPI##_I_##_CPHA_1_2 | \ + ES_SPI##_I_##_CPOL_H_L | \ + ES_SPI##_I_##_CS | \ + ES_SPI##_I_##_M_L_SB ); \ + _CONF_.data_width = ES_SPI##_I_##_DATA_W; \ + _CONF_.max_hz = ES_SPI##_I_##_MAX_HZ; \ + }while(0) + + +// spi_config.mode &= ~RT_SPI_SLAVE; /* 主机模式 */ +// spi_config.mode &= ~RT_SPI_3WIRE; /* 4线，双向传输 */ +// spi_config.mode |= RT_SPI_CPHA; /* 第二边沿采样 */ +// spi_config.mode |= RT_SPI_CPOL; /* 空闲高电平 */ +// spi_config.mode |= RT_SPI_NO_CS; /* 禁用软件从机选择管理 */ +// spi_config.mode |= RT_SPI_MSB; /* 高位在前 */ +// spi_config.data_width = 8; /* 数据长度：8 */ +// spi_config.max_hz = 2000000; /* 最快时钟频率 */ + +#define ES_C_SPI_CLK_POL_HIGH RT_SPI_CPOL +#define ES_C_SPI_CLK_POL_LOW !RT_SPI_CPOL + +#define ES_C_SPI_CLK_PHA_FIRST !RT_SPI_CPHA +#define ES_C_SPI_CLK_PHA_SECOND RT_SPI_CPHA + +#define ES_C_SPI_MSB RT_SPI_MSB +#define ES_C_SPI_LSB RT_SPI_LSB + +#define ES_C_SPI_CS_LOW_LEVEL 0 +#define ES_C_SPI_CS_HIGH_LEVEL 1 + +/* codes_main */ + + +#ifndef ES_DEVICE_NAME_SPI0_BUS +#define ES_DEVICE_NAME_SPI0_BUS "spi0" +#endif +#ifndef ES_DEVICE_NAME_SPI0_DEV0 +#define ES_DEVICE_NAME_SPI0_DEV0 "spi00" +#endif + +#ifndef ES_DEVICE_NAME_SPI1_BUS +#define ES_DEVICE_NAME_SPI1_BUS "spi1" +#endif +#ifndef ES_DEVICE_NAME_SPI1_DEV0 +#define ES_DEVICE_NAME_SPI1_DEV0 "spi10" +#endif + +#ifndef ES_DEVICE_NAME_SPI2_BUS +#define ES_DEVICE_NAME_SPI2_BUS "spi2" +#endif +#ifndef ES_DEVICE_NAME_SPI2_DEV0 +#define ES_DEVICE_NAME_SPI2_DEV0 "spi20" +#endif + + +#define ES_SPI_CS_LEVEL ES_C_SPI_CS_LOW_LEVEL + +#ifndef ES_SPI0_CPHA_1_2 +#define ES_SPI0_CPHA_1_2 ES_C_SPI_CLK_PHA_SECOND +#endif +#ifndef ES_SPI0_CPOL_H_L +#define ES_SPI0_CPOL_H_L ES_C_SPI_CLK_POL_HIGH +#endif +#ifndef ES_SPI0_M_L_SB +#define ES_SPI0_M_L_SB RT_SPI_MSB +#endif +#ifndef ES_SPI0_MAX_HZ +#define ES_SPI0_MAX_HZ 2000000 +#endif +#ifndef ES_SPI0_NSS_PIN +#define ES_SPI0_NSS_PIN 0xFFFFFFFF +#endif + +#ifndef ES_SPI1_CPHA_1_2 +#define ES_SPI1_CPHA_1_2 ES_C_SPI_CLK_PHA_SECOND +#endif +#ifndef ES_SPI1_CPOL_H_L +#define ES_SPI1_CPOL_H_L ES_C_SPI_CLK_POL_HIGH +#endif +#ifndef ES_SPI1_M_L_SB +#define ES_SPI1_M_L_SB RT_SPI_MSB +#endif +#ifndef ES_SPI1_MAX_HZ +#define ES_SPI1_MAX_HZ 2000000 +#endif +#ifndef ES_SPI1_NSS_PIN +#define ES_SPI1_NSS_PIN 0xFFFFFFFF +#endif + +#ifndef ES_SPI2_CPHA_1_2 +#define ES_SPI2_CPHA_1_2 ES_C_SPI_CLK_PHA_SECOND +#endif +#ifndef ES_SPI2_CPOL_H_L +#define ES_SPI2_CPOL_H_L ES_C_SPI_CLK_POL_HIGH +#endif +#ifndef ES_SPI2_M_L_SB +#define ES_SPI2_M_L_SB RT_SPI_MSB +#endif +#ifndef ES_SPI2_MAX_HZ +#define ES_SPI2_MAX_HZ 2000000 +#endif +#ifndef ES_SPI2_NSS_PIN +#define ES_SPI2_NSS_PIN 0xFFFFFFFF +#endif + + +#define ES_SPI0_MASTER_SLAVE !RT_SPI_SLAVE +#define ES_SPI0_WIRE_3_4 !RT_SPI_3WIRE +#define ES_SPI0_CS RT_SPI_NO_CS +#define ES_SPI0_DATA_W 8 + +#define ES_SPI1_MASTER_SLAVE !RT_SPI_SLAVE +#define ES_SPI1_WIRE_3_4 !RT_SPI_3WIRE +#define ES_SPI1_CS RT_SPI_NO_CS +#define ES_SPI1_DATA_W 8 + +#define ES_SPI2_MASTER_SLAVE !RT_SPI_SLAVE +#define ES_SPI2_WIRE_3_4 !RT_SPI_3WIRE +#define ES_SPI2_CS RT_SPI_NO_CS +#define ES_SPI2_DATA_W 8 + + +#endif diff --git a/bsp/essemi/es32f369x/drivers/ES/es_conf_info_uart.h b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_uart.h new file mode 100644 index 0000000000..430cb9f599 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_uart.h @@ -0,0 +1,205 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_UART_H__ +#define __ES_CONF_INFO_UART_H__ + +#include "es_conf_info_map.h" +#include +#include +#include + + + +#define ES_C_UART_PARITY_NONE PARITY_NONE +#define ES_C_UART_PARITY_ODD PARITY_ODD +#define ES_C_UART_PARITY_EVEN PARITY_EVEN + +#define ES_C_UART_STOP_1 STOP_BITS_1 +#define ES_C_UART_STOP_2 STOP_BITS_2 + + +/* UART 配置 */ + +/* codes_main */ + + + +#ifndef ES_DEVICE_NAME_UART0 +#define ES_DEVICE_NAME_UART0 "uart0" +#endif +#ifndef ES_DEVICE_NAME_UART1 +#define ES_DEVICE_NAME_UART1 "uart1" +#endif +#ifndef ES_DEVICE_NAME_UART2 +#define ES_DEVICE_NAME_UART2 "uart2" +#endif +#ifndef ES_DEVICE_NAME_UART3 +#define ES_DEVICE_NAME_UART3 "uart3" +#endif +#ifndef ES_DEVICE_NAME_UART4 +#define ES_DEVICE_NAME_UART4 "uart4" +#endif +#ifndef ES_DEVICE_NAME_UART5 +#define ES_DEVICE_NAME_UART5 "uart5" +#endif + +#ifndef ES_CONF_UART0_BAUD_RATE +#define ES_CONF_UART0_BAUD_RATE 115200 +#endif +#ifndef ES_CONF_UART0_PARITY +#define ES_CONF_UART0_PARITY ES_C_UART_PARITY_NONE +#endif +#ifndef ES_CONF_UART0_STOP_BITS +#define ES_CONF_UART0_STOP_BITS ES_C_UART_STOP_1 +#endif + +#ifndef ES_CONF_UART1_BAUD_RATE +#define ES_CONF_UART1_BAUD_RATE 115200 +#endif +#ifndef ES_CONF_UART1_PARITY +#define ES_CONF_UART1_PARITY ES_C_UART_PARITY_NONE +#endif +#ifndef ES_CONF_UART1_STOP_BITS +#define ES_CONF_UART1_STOP_BITS ES_C_UART_STOP_1 +#endif + +#ifndef ES_CONF_UART2_BAUD_RATE +#define ES_CONF_UART2_BAUD_RATE 115200 +#endif +#ifndef ES_CONF_UART2_PARITY +#define ES_CONF_UART2_PARITY ES_C_UART_PARITY_NONE +#endif +#ifndef ES_CONF_UART2_STOP_BITS +#define ES_CONF_UART2_STOP_BITS ES_C_UART_STOP_1 +#endif + +#ifndef ES_CONF_UART3_BAUD_RATE +#define ES_CONF_UART3_BAUD_RATE 115200 +#endif +#ifndef ES_CONF_UART3_PARITY +#define ES_CONF_UART3_PARITY ES_C_UART_PARITY_NONE +#endif +#ifndef ES_CONF_UART3_STOP_BITS +#define ES_CONF_UART3_STOP_BITS ES_C_UART_STOP_1 +#endif + +#ifndef ES_CONF_UART4_BAUD_RATE +#define ES_CONF_UART4_BAUD_RATE 115200 +#endif +#ifndef ES_CONF_UART4_PARITY +#define ES_CONF_UART4_PARITY ES_C_UART_PARITY_NONE +#endif +#ifndef ES_CONF_UART4_STOP_BITS +#define ES_CONF_UART4_STOP_BITS ES_C_UART_STOP_1 +#endif + +#ifndef ES_CONF_UART5_BAUD_RATE +#define ES_CONF_UART5_BAUD_RATE 115200 +#endif +#ifndef ES_CONF_UART5_PARITY +#define ES_CONF_UART5_PARITY ES_C_UART_PARITY_NONE +#endif +#ifndef ES_CONF_UART5_STOP_BITS +#define ES_CONF_UART5_STOP_BITS ES_C_UART_STOP_1 +#endif + + +#define ES_UART0_CONFIG \ +{ \ + ES_CONF_UART0_BAUD_RATE, \ + DATA_BITS_8, \ + ES_CONF_UART0_STOP_BITS, \ + ES_CONF_UART0_PARITY, \ + BIT_ORDER_LSB, \ + NRZ_NORMAL, \ + RT_SERIAL_RB_BUFSZ, \ + 0 \ +} + + +#define ES_UART1_CONFIG \ +{ \ + ES_CONF_UART1_BAUD_RATE, \ + DATA_BITS_8, \ + ES_CONF_UART1_STOP_BITS, \ + ES_CONF_UART1_PARITY, \ + BIT_ORDER_LSB, \ + NRZ_NORMAL, \ + RT_SERIAL_RB_BUFSZ, \ + 0 \ +} + + +#define ES_UART2_CONFIG \ +{ \ + ES_CONF_UART2_BAUD_RATE, \ + DATA_BITS_8, \ + ES_CONF_UART2_STOP_BITS, \ + ES_CONF_UART2_PARITY, \ + BIT_ORDER_LSB, \ + NRZ_NORMAL, \ + RT_SERIAL_RB_BUFSZ, \ + 0 \ +} + + +#define ES_UART3_CONFIG \ +{ \ + ES_CONF_UART3_BAUD_RATE, \ + DATA_BITS_8, \ + ES_CONF_UART3_STOP_BITS, \ + ES_CONF_UART3_PARITY, \ + BIT_ORDER_LSB, \ + NRZ_NORMAL, \ + RT_SERIAL_RB_BUFSZ, \ + 0 \ +} + + +#define ES_UART4_CONFIG \ +{ \ + ES_CONF_UART4_BAUD_RATE, \ + DATA_BITS_8, \ + ES_CONF_UART4_STOP_BITS, \ + ES_CONF_UART4_PARITY, \ + BIT_ORDER_LSB, \ + NRZ_NORMAL, \ + RT_SERIAL_RB_BUFSZ, \ + 0 \ +} + + +#define ES_UART5_CONFIG \ +{ \ + ES_CONF_UART5_BAUD_RATE, \ + DATA_BITS_8, \ + ES_CONF_UART5_STOP_BITS, \ + ES_CONF_UART5_PARITY, \ + BIT_ORDER_LSB, \ + NRZ_NORMAL, \ + RT_SERIAL_RB_BUFSZ, \ + 0 \ +} + +#endif diff --git a/bsp/essemi/es32f369x/drivers/Kconfig b/bsp/essemi/es32f369x/drivers/Kconfig index 4b42e7e074..75cb7bd164 100644 --- a/bsp/essemi/es32f369x/drivers/Kconfig +++ b/bsp/essemi/es32f369x/drivers/Kconfig @@ -1,139 +1,37 @@ menu "Hardware Drivers Config" + + menu "On-chip Peripheral Drivers" config BSP_USING_GPIO bool "Enable GPIO" select RT_USING_PIN default y - menu "UART Drivers" - config BSP_USING_UART0 - bool "Enable UART0 PB10/PB11(T/R)" - select RT_USING_SERIAL - default n - - config BSP_USING_UART1 - bool "Enable UART1 PC10/PC11(T/R)" - select RT_USING_SERIAL - default n - - config BSP_USING_UART2 - bool "Enable UART2 PC12/PD02(T/R)" - select RT_USING_SERIAL - default y - - config BSP_USING_UART3 - bool "Enable UART3 PC04/PC05(T/R)" - select RT_USING_SERIAL - default n - depends on !BSP_USING_SPI2 - - config BSP_USING_UART4 - bool "Enable UART4 PB06/PB07(T/R)" - select RT_USING_SERIAL - default n - depends on !BSP_USING_I2C0 - depends on !BSP_USING_PWM0 - - config BSP_USING_UART5 - bool "Enable UART5 PB09/PB08(T/R)" - select RT_USING_SERIAL - default n - depends on !BSP_USING_PWM0 - endmenu - - menu "SPI Drivers" - config BSP_USING_SPI0 - bool "Enable SPI0 BUS PB03/PB04/PB05(CLK/MISO/MOSI)" - select RT_USING_SPI - select RT_USING_PIN - default n - - config BSP_USING_SPI1 - bool "Enable SPI1 BUS PC01/PC02/PC03(CLK/MISO/MOSI)" - select RT_USING_SPI - select RT_USING_PIN - default n - - config BSP_USING_SPI2 - bool "Enable SPI2 BUS PC05/PB00/PB01(CLK/MISO/MOSI)" - select RT_USING_SPI - select RT_USING_PIN - default n - depends on !BSP_USING_UART3 - endmenu - - menu "I2C Drivers" - config BSP_USING_I2C0 - bool "Enable I2C0 BUS PB06/PB07(SCL/SDA)" - select RT_USING_I2C - default n - depends on !BSP_USING_PWM0 - - config BSP_USING_I2C1 - bool "Enable I2C1 BUS PA05/PA06(SCL/SDA)" - select RT_USING_I2C - default n - endmenu - - menu "CAN Drivers" - config BSP_USING_CAN - bool "Enable CAN BUS PB08/PB09(RX/TX)" - select RT_USING_CAN - default n - endmenu - - menu "ADC Drivers" - config BSP_USING_ADC - bool "Using ADC" - select RT_USING_ADC - default n - endmenu - - menu "RTC Drivers" - config BSP_USING_RTC - bool "Using RTC" - select RT_USING_RTC - default n - endmenu - - menu "HWtimer Drivers" - config BSP_USING_HWTIMER0 - bool "Using timer0" - select RT_USING_HWTIMER - default n - - config BSP_USING_HWTIMER1 - bool "Using timer1" - select RT_USING_HWTIMER - default n - endmenu - - menu "PWM Drivers" - config BSP_USING_PWM0 - bool "Using PWM0 PB06/PB07/PB08/PB09" - select RT_USING_PWM - default n - depends on !BSP_USING_CAN - depends on !BSP_USING_I2C0 - - config BSP_USING_PWM1 - bool "Using PWM1 PA00/PA01/PA02/PA03" - select RT_USING_PWM - default n - endmenu - - menu "PM Drivers" - config BSP_USING_PM - bool "Using PM" - select RT_USING_PM - default n - endmenu + source "drivers/ES/Kconfig" endmenu menu "Onboard Peripheral Drivers" + config BSP_USING_SPI_FLASH + bool "Enable SPI FLASH (W25Q64 spi0)" + select BSP_USING_SPI + select RT_USING_SFUD + select RT_SFUD_USING_SFDP + default n + +if BSP_USING_SPI_FLASH + + config ES_DEVICE_NAME_SPI_DEV + string "The name of spi device (registered)" + default "spi00" + + config ES_DEVICE_NAME_SPI_FALSH_DEV + string "The name of spi flash device" + default "W25Q64" +endif + endmenu menu "Offboard Peripheral Drivers" @@ -155,13 +53,17 @@ menu "Hardware Drivers Config" bool "BSP_USING_EXAMPLE_I2C" default n + config BSP_USING_EXAMPLE_I2C_E2PROM + bool "BSP_USING_EXAMPLE_I2C_E2PROM" + default n + config BSP_USING_EXAMPLE_LED_BLINK bool "BSP_USING_EXAMPLE_LED_BLINK" - default y + default n config BSP_USING_EXAMPLE_PIN_BEEP bool "BSP_USING_EXAMPLE_PIN_BEEP" - default y + default n config BSP_USING_EXAMPLE_PWM_LED bool "BSP_USING_EXAMPLE_PWM_LED" @@ -177,7 +79,7 @@ menu "Hardware Drivers Config" config BSP_USING_EXAMPLE_UART bool "BSP_USING_EXAMPLE_UART" - default y + default n config BSP_USING_EXAMPLE_CAN bool "BSP_USING_EXAMPLE_CAN" diff --git a/bsp/essemi/es32f369x/drivers/SConscript b/bsp/essemi/es32f369x/drivers/SConscript index 735ebb37be..b39d545e35 100644 --- a/bsp/essemi/es32f369x/drivers/SConscript +++ b/bsp/essemi/es32f369x/drivers/SConscript @@ -15,7 +15,9 @@ if GetDepend('RT_USING_PIN'): # add serial driver code if GetDepend('BSP_USING_UART0') or GetDepend('BSP_USING_UART1') or GetDepend('BSP_USING_UART2') or GetDepend('BSP_USING_UART3') or \ - GetDepend('BSP_USING_UART4') or GetDepend('BSP_USING_UART5'): + GetDepend('BSP_USING_UART4') or GetDepend('BSP_USING_UART5') or \ + GetDepend('BSP_USING_USART0') or GetDepend('BSP_USING_USART1') or GetDepend('BSP_USING_USART2') or GetDepend('BSP_USING_USART3') or \ + GetDepend('BSP_USING_USART4') or GetDepend('BSP_USING_USART5'): src += ['drv_uart.c'] # add spi driver code @@ -27,23 +29,32 @@ if GetDepend('BSP_USING_I2C0') or GetDepend('BSP_USING_I2C1'): src += ['drv_i2c.c'] # add can driver code -if GetDepend('BSP_USING_CAN'): +if GetDepend('BSP_USING_CAN') or GetDepend('BSP_USING_CAN0') or GetDepend('RT_USING_CAN'): src += ['drv_can.c'] # add adc driver code -if GetDepend(['BSP_USING_ADC']): +if GetDepend(['BSP_USING_ADC0']) or GetDepend('BSP_USING_ADC1'): src += ['drv_adc.c'] # add rtc driver code if GetDepend(['BSP_USING_RTC']): src += ['drv_rtc.c'] +# add spi flash driver code +if GetDepend('BSP_USING_SPI_FLASH'): + src += ['drv_spiflash.c'] + # add hwtimer driver code -if GetDepend('BSP_USING_HWTIMER0') or GetDepend('BSP_USING_HWTIMER1'): +if GetDepend('BSP_USING_AD16C4T0_HWTIMER') or GetDepend('BSP_USING_AD16C4T1_HWTIMER') or \ + GetDepend('BSP_USING_GP32C4T0_HWTIMER') or GetDepend('BSP_USING_GP32C4T1_HWTIMER') or \ + GetDepend('BSP_USING_GP16C4T0_HWTIMER') or GetDepend('BSP_USING_GP16C4T1_HWTIMER') or \ + GetDepend('BSP_USING_BS16T0_HWTIMER') or GetDepend('BSP_USING_BS16T1_HWTIMER'): src += ['drv_hwtimer.c'] # add pwm driver code -if GetDepend('BSP_USING_PWM0') or GetDepend('BSP_USING_PWM1'): +if GetDepend('BSP_USING_AD16C4T0_PWM') or GetDepend('BSP_USING_AD16C4T1_PWM') or \ + GetDepend('BSP_USING_GP32C4T0_PWM') or GetDepend('BSP_USING_GP32C4T1_PWM') or \ + GetDepend('BSP_USING_GP16C4T0_PWM') or GetDepend('BSP_USING_GP16C4T1_PWM'): src += ['drv_pwm.c'] # add pm driver code @@ -56,7 +67,7 @@ objs = objs + group src = [] cwd = GetCurrentDir() -include_path = [cwd] +include_path = [cwd + '/ES'] if GetDepend('BSP_USING_EXAMPLE_ADC_VOL'): src += ['bsp_driver_example/adc_vol_sample.c'] @@ -67,6 +78,9 @@ if GetDepend('BSP_USING_EXAMPLE_HWTIMER'): if GetDepend('BSP_USING_EXAMPLE_I2C'): src += ['bsp_driver_example/i2c_sample.c'] +if GetDepend('BSP_USING_EXAMPLE_I2C_E2PROM'): + src += ['bsp_driver_example/i2c_e2_sample.c'] + if GetDepend('BSP_USING_EXAMPLE_LED_BLINK'): src += ['bsp_driver_example/led_blink_sample.c'] diff --git a/bsp/essemi/es32f369x/drivers/board.c b/bsp/essemi/es32f369x/drivers/board.c index 1c2b834177..ea42df63dc 100644 --- a/bsp/essemi/es32f369x/drivers/board.c +++ b/bsp/essemi/es32f369x/drivers/board.c @@ -1,11 +1,24 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes - * 2020-01-14 wangyq the first version + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version */ #include @@ -13,7 +26,6 @@ #include "board.h" #include "drv_uart.h" #include "drv_gpio.h" -#include #include /** @@ -42,11 +54,68 @@ void NVIC_Configuration(void) *******************************************************************************/ void SystemClock_Config(void) { - /* hosc 12MHz, from hosc/3 pll to 96MHz */ - ald_cmu_pll1_config(CMU_PLL1_INPUT_HOSC_3, CMU_PLL1_OUTPUT_96M); - /* SYSCLK 96MHz */ - ald_cmu_clock_config(CMU_CLOCK_PLL1, 96000000); + + SYSCFG_UNLOCK(); +#if ES_CMU_LRC_EN + SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); +#else + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); +#endif /*ES_CMU_LRC_EN*/ + +#if ES_CMU_LOSC_EN + SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); +#else + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); +#endif /*ES_CMU_LOSC_EN*/ + +#if ES_CMU_HRC_EN + SET_BIT(CMU->CLKENR, CMU_CLKENR_HRCEN_MSK); +#else + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_HRCEN_MSK); +#endif /*ES_CMU_HRC_EN*/ + +#if ES_CMU_HOSC_EN + SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK); +#else + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK); +#endif /*ES_CMU_HOSC_EN*/ + + SYSCFG_LOCK(); + +#if ES_CMU_PLL1_EN + /*PLL的源必须是4M*/ + ald_cmu_pll1_config(ES_PLL1_REFER_CLK, ES_PLL1_OUT_CLK); + + #if ES_CMU_PLL1_SAFE_EN + ald_cmu_pll_safe_config(ENABLE); + #else + ald_cmu_pll_safe_config(DISABLE); + #endif + +#else + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_PLL1EN_MSK); +#endif /*ES_CMU_PLL1_EN*/ + + ald_cmu_clock_config(ES_SYS_CLK_SOURSE, ES_SYS_CLK); + + ald_cmu_div_config(CMU_SYS,ES_CMU_SYS_DIV); + ald_cmu_div_config(CMU_HCLK_1,ES_CMU_HCLK_1_DIV); + ald_cmu_div_config(CMU_HCLK_2,ES_CMU_HCLK_2_DIV); + ald_cmu_div_config(CMU_PCLK_1,ES_CMU_PCLK_1_DIV); + ald_cmu_div_config(CMU_PCLK_2,ES_CMU_PCLK_2_DIV); + ald_cmu_perh_clock_config(CMU_PERH_ALL, ENABLE); + +/*低功耗时钟使能*/ +#ifdef RT_USING_PM + SYSCFG_UNLOCK(); + SET_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK); + SET_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK); + SET_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK); + SET_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK); + SYSCFG_LOCK(); +#endif + } /******************************************************************************* @@ -70,11 +139,21 @@ void SysTick_Handler(void) { /* enter interrupt */ rt_interrupt_enter(); + ald_inc_tick(); rt_tick_increase(); /* leave interrupt */ rt_interrupt_leave(); } +/** + * This is the cmu interrupt service. + * + */ +void CMU_Handler(void) +{ + ald_cmu_irq_handler(); +} + /*@}*/ /** * This function will initial ES32F3 board. diff --git a/bsp/essemi/es32f369x/drivers/board.h b/bsp/essemi/es32f369x/drivers/board.h index 628c2f87fd..640cf44864 100644 --- a/bsp/essemi/es32f369x/drivers/board.h +++ b/bsp/essemi/es32f369x/drivers/board.h @@ -1,11 +1,24 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes - * 2020-01-14 wangyq the first version + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version */ // <<< Use Configuration Wizard in Context Menu >>> @@ -13,6 +26,7 @@ #define __BOARD_H__ #include +#include "es_conf_info_cmu.h" #define ES32F3_SRAM_SIZE 0x18000 #define ES32F3_SRAM_END (0x20000000 + ES32F3_SRAM_SIZE) diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/adc_vol_sample.c b/bsp/essemi/es32f369x/drivers/bsp_driver_example/adc_vol_sample.c index f9444982d4..9576736bcd 100644 --- a/bsp/essemi/es32f369x/drivers/bsp_driver_example/adc_vol_sample.c +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/adc_vol_sample.c @@ -18,11 +18,15 @@ #include #include + +#ifdef RT_USING_ADC + #define ADC_DEV_NAME "adc0" /* ADC 设备名称 */ #define ADC_DEV_CHANNEL 5 /* ADC 通道 5 PA1*/ #define REFER_VOLTAGE 330 /* 参考电压 3.3V,数据精度乘以100保留2位小数*/ #define CONVERT_BITS (1 << 12) /* 转换位数为12位 */ + static int adc_vol_sample(int argc, char *argv[]) { rt_adc_device_t adc_dev; @@ -55,3 +59,5 @@ static int adc_vol_sample(int argc, char *argv[]) } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(adc_vol_sample, adc voltage convert sample); + +#endif diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/can_sample.c b/bsp/essemi/es32f369x/drivers/bsp_driver_example/can_sample.c index bfbd50095e..1133ad8d2b 100644 --- a/bsp/essemi/es32f369x/drivers/bsp_driver_example/can_sample.c +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/can_sample.c @@ -18,7 +18,9 @@ #include #include "rtdevice.h" -#define CAN_DEV_NAME "can" /* CAN 设备名称 */ +#ifdef RT_USING_CAN + +#define CAN_DEV_NAME "can0" /* CAN 设备名称 */ static struct rt_semaphore rx_sem; /* 用于接收消息的信号量 */ static rt_device_t can_dev; /* CAN 设备句柄 */ @@ -142,3 +144,5 @@ int can_sample(int argc, char *argv[]) } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(can_sample, can device sample); + +#endif diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/hwtimer_sample.c b/bsp/essemi/es32f369x/drivers/bsp_driver_example/hwtimer_sample.c index e2e39664f3..025b4f26c0 100644 --- a/bsp/essemi/es32f369x/drivers/bsp_driver_example/hwtimer_sample.c +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/hwtimer_sample.c @@ -17,6 +17,8 @@ #include #include +#ifdef RT_USING_HWTIMER + #define HWTIMER_DEV_NAME "timer0" /* 定时器名称 */ /* 定时器超时回调函数 */ @@ -83,3 +85,5 @@ static int hwtimer_sample(int argc, char *argv[]) } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(hwtimer_sample, hwtimer sample); + +#endif diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/i2c_e2_sample.c b/bsp/essemi/es32f369x/drivers/bsp_driver_example/i2c_e2_sample.c new file mode 100644 index 0000000000..3bfd005e67 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/i2c_e2_sample.c @@ -0,0 +1,109 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Change Logs: + * Date Author Notes + * 2020-12-15 liuhy first implementation. + */ +/* + * 程序清单：这是一个 I2C 设备使用例程 + * 例程导出了 i2c_e2_sample 命令到控制终端 + * 命令调用格式：i2c_e2_sample + * 命令解释：使用默认的I2C总线设备i2c0 + * 程序功能：通过 I2C 设备写读e2prom，ST24C04WP。 +*/ + +/*ST24C04WP 有2个Block ：Block0 的从机地址为：0x50,Block1 的从机地址为：0x51 + 一个Block有 256字节，一页16字节,写只可在一页内(超过一页的范围后,会回到页的开始),读无页限制*/ +#include +#include + +#ifdef RT_USING_I2C + +#define I2C_BUS_NAME "i2c0" /*I2C总线设备名称 */ +#define SLAVE_ADDR 0x50 /*从机地址*/ +#define MEM_ADDR 0x00 /*从机的起始储存地址,范围：0x00到0xEF(例程写读范围：2页)*/ +#define ADDR_LEN 1 /*定义从机储存地址的长度，默认8位,1字节*/ +#define STR_LEN 16 /*接收发送的页数据长度 ,最大16*/ + +static rt_uint8_t mem_addr,rx_buffer[33] = { 0U }; /*读两页,需要32字节，字符串结束'\0'*/ +/*第一个字节' '用来放 E2PROM 的内存地址,最后一个字节'\0'作为子串的结束，不存入e2prom*/ +static rt_uint8_t tx_buffer1[STR_LEN + ADDR_LEN + 1] = " e2prom example !\0"; +static rt_uint8_t tx_buffer2[STR_LEN + ADDR_LEN + 1] = " ABCDEFGH12345678\0"; + +static void i2c_e2_sample(int argc, char *argv[]) +{ + struct rt_i2c_bus_device *i2c_bus = RT_NULL; /* I2C总线设备句柄 */ + struct rt_i2c_msg i2c_msg[2]; /* I2C消息 */ + rt_size_t s_stat; + + i2c_bus = (struct rt_i2c_bus_device *)rt_device_find(I2C_BUS_NAME); /* 通过名字获取I2C总线设备的句柄 */ + + if( i2c_bus == RT_NULL) + { + rt_kprintf("can't find i2c device :%s !\n",I2C_BUS_NAME); + return; + } + + /*写T24C04WP + 如果 (MEM_ADDR & 0x0F) + STR_LEN <= 16, 写的范围为：(MEM_ADDR , MEM_ADDR + STR_LEN ) + (0x10 + MEM_ADDR , 0x10 + MEM_ADDR + STR_LEN ) + 如果 (MEM_ADDR & 0x0F) + STR_LEN > 16, 超出范围的部分会在页内循环写。*/ + tx_buffer1[0] = MEM_ADDR; + + /*初始化消息*/ + i2c_msg[0].addr = SLAVE_ADDR; /* 从机地址 */ + i2c_msg[0].len = ADDR_LEN + STR_LEN ; /* 写入的长度，地址+数据 */ + i2c_msg[0].buf = tx_buffer1; /* 待写入第一段数据 */ + i2c_msg[0].flags = RT_I2C_WR; /* I2C写 */ + s_stat = rt_i2c_transfer(i2c_bus,i2c_msg,1); /* 写入第一段数据 */ + + if( s_stat == 1 )rt_kprintf("write successful. \nmessage: %s\n",&tx_buffer1[1]); + else rt_kprintf("device %s write fail \n",I2C_BUS_NAME); + + tx_buffer2[0] = MEM_ADDR + 0x10; /*加一页*/ + i2c_msg[0].buf = tx_buffer2; /* 待写入第二段数据 */ + s_stat = rt_i2c_transfer(i2c_bus,i2c_msg,1); /* 写入第二段数据 */ + + if( s_stat == 1 )rt_kprintf("write successful. \nmessage: %s\n",&tx_buffer2[1]); + else rt_kprintf("device %s write fail \n",I2C_BUS_NAME); + + /*读T24C04WP 读2页的数据。读数据需要2条消息：第一条消息：发送读取的地址。 + 第二条消息：读取具体的数据。*/ + + mem_addr = MEM_ADDR & 0xF0; /*从页的开始读*/ + + i2c_msg[0].len = ADDR_LEN; + i2c_msg[0].buf = &mem_addr; + + i2c_msg[1].addr = SLAVE_ADDR; /* 从机地址 */ + i2c_msg[1].len = 32; /* 读取的数据长度：2*16 */ + i2c_msg[1].buf = rx_buffer; /* 数据存放地址 */ + i2c_msg[1].flags = RT_I2C_RD; /* I2C读 */ + s_stat = rt_i2c_transfer(i2c_bus,i2c_msg,2); /* 读已写的2页 */ + + if( s_stat == 2 )rt_kprintf(" read successful \n messege : %s \n",rx_buffer); + else + rt_kprintf("read fail \n"); + + return; + +} +/* 导出到 msh 命令列表中 */ +MSH_CMD_EXPORT(i2c_e2_sample, i2c e2prom sample); + +#endif diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/i2c_sample.c b/bsp/essemi/es32f369x/drivers/bsp_driver_example/i2c_sample.c index 4fd42baf41..c8a666609d 100644 --- a/bsp/essemi/es32f369x/drivers/bsp_driver_example/i2c_sample.c +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/i2c_sample.c @@ -1,7 +1,19 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes @@ -18,6 +30,8 @@ #include #include +#ifdef RT_USING_I2C + #define I2C_BUS_NAME "i2c0" /* I2C总线设备名称 */ #define SLAVE_ADDR 0x2D /* 从机地址 */ #define STR_LEN 16 /* 接收发送的数据长度 */ @@ -95,3 +109,5 @@ static void i2c_io_sample(int argc, char *argv[]) } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(i2c_io_sample, i2c io sample); + +#endif diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/pm_sample.c b/bsp/essemi/es32f369x/drivers/bsp_driver_example/pm_sample.c index b886876108..731dca4115 100644 --- a/bsp/essemi/es32f369x/drivers/bsp_driver_example/pm_sample.c +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/pm_sample.c @@ -1,7 +1,19 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes @@ -11,18 +23,26 @@ * 程序清单：这是一个 pm睡眠唤醒的使用例程 * 例程导出了 pm_sample 命令到控制终端 * 命令调用格式：pm_sample - * 命令解释：进入不同的睡眠模式，然后用按键唤醒 + * 命令解释：进入不同的睡眠模式，然后用按键唤醒。 * 程序功能：通过串口输出字符串，告知进入睡眠和唤醒睡眠的情况。 + * 注意：进入睡眠前，如果有中断挂起（SYSTICK、UART、EXTI等），睡眠将被瞬间唤醒。 */ #include #include -#include "drv_pm.h" +#include "drv_pm.h" +#include "ald_gpio.h" + + +#ifdef RT_USING_PM #define PM_NAME "pm" /* 设备名称 */ #define WAKE_UP_PIN 51 /* 唤醒源 */ #define SLEEP_TIMES 12 /* 进入睡眠次数，轮流进入不同的睡眠模式，包括无睡眠模式 */ +/*部分芯片进入深度睡眠后，部分外设的部分寄存器可能会丢失*/ +#define SAVE_REG UART0 +#define SAVE_REG_TYPE UART_TypeDef struct pm_callback_t { @@ -64,14 +84,15 @@ void sleep_in_out_callback(rt_uint8_t event, rt_uint8_t mode, void *data) /*进入睡眠前*/ case RT_PM_ENTER_SLEEP: g_pm_data.flag = 1; rt_kprintf("\n\r##%d : ENTER ",g_pm_data.in_fun_times); - save_register(UART0,sizeof(UART_TypeDef),save_load_mem); /*备份寄存器的值*/ + /*进入深度睡眠后，部分外设的部分寄存器可能会丢失*/ + save_register(SAVE_REG,sizeof(SAVE_REG_TYPE),save_load_mem); /*备份寄存器的值*/ g_pm_data.in_fun_times++; /*进入睡眠次数+1*/ break; /*睡眠唤醒后*/ case RT_PM_EXIT_SLEEP: g_pm_data.flag = 0; /*睡眠唤醒后*/ - load_register(UART0,sizeof(UART_TypeDef),save_load_mem); /*还原寄存器的值*/ + load_register(SAVE_REG,sizeof(SAVE_REG_TYPE),save_load_mem); /*还原寄存器的值*/ rt_kprintf("\n\rEXIT\n\r"); - rt_pm_release(mode); /*释放休眠模式*/ + rt_pm_request(PM_SLEEP_MODE_NONE); /*进无休眠模式*/ return; default: break; @@ -118,7 +139,7 @@ static void pm_test(void *parameter) /*设置回调函数和私有数据*/ rt_pm_notify_set(sleep_in_out_callback,RT_NULL); - + while(i < SLEEP_TIMES) { @@ -130,9 +151,12 @@ static void pm_test(void *parameter) g_pm_data.flag = 2; } + + /*彻底释放无休眠模式*/ + rt_pm_release_all(PM_SLEEP_MODE_NONE); /*请求选择的休眠模式*/ - rt_pm_request(in_mode[i%6]); + rt_pm_request(in_mode[i%6]); rt_thread_mdelay(500); @@ -142,14 +166,19 @@ static void pm_test(void *parameter) rt_thread_mdelay(500); } - /*释放选择的休眠模式*/ - rt_pm_release(in_mode[i%6]); + /*释放选择的休眠模式 ，彻底释放*/ + rt_pm_release_all(in_mode[i%6]); i++; } - /*清除回调函数和私有数据*/ + + /*切换为无睡眠模式*/ + rt_pm_request(PM_SLEEP_MODE_NONE); + + /*清除回调函数和私有数据*/ rt_pm_notify_set(RT_NULL,RT_NULL); + rt_kprintf("thread pm_test close\n\r"); } @@ -187,3 +216,5 @@ static int pm_sample(int argc, char *argv[]) } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(pm_sample, pm sample); + +#endif diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/pwm_led_sample.c b/bsp/essemi/es32f369x/drivers/bsp_driver_example/pwm_led_sample.c index df82c1b41c..8d12b74e15 100644 --- a/bsp/essemi/es32f369x/drivers/bsp_driver_example/pwm_led_sample.c +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/pwm_led_sample.c @@ -17,9 +17,12 @@ #include #include -#define LED_PIN_NUM 19 /* PF1 LED PIN脚编号，查看驱动文件drv_gpio.c确定 */ + +#ifdef RT_USING_PWM + +#define LED_PIN_NUM 37 /* PF1 LED PIN脚编号，查看驱动文件drv_gpio.c确定 */ #define PWM_DEV_NAME "pwm1" /* PWM设备名称 */ -#define PWM_DEV_CHANNEL 2 /* PA1 PWM通道 */ +#define PWM_DEV_CHANNEL 1 /* PWM通道 */ struct rt_device_pwm *pwm_dev; /* PWM设备句柄 */ @@ -70,3 +73,5 @@ static int pwm_led_sample(int argc, char *argv[]) } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(pwm_led_sample, pwm sample); + +#endif diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/rtc_sample.c b/bsp/essemi/es32f369x/drivers/bsp_driver_example/rtc_sample.c index 711a3a0ebb..d66b9db9df 100644 --- a/bsp/essemi/es32f369x/drivers/bsp_driver_example/rtc_sample.c +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/rtc_sample.c @@ -17,6 +17,8 @@ #include #include +#ifdef RT_USING_RTC + static int rtc_sample(int argc, char *argv[]) { rt_err_t ret = RT_EOK; @@ -39,7 +41,7 @@ static int rtc_sample(int argc, char *argv[]) } /* 延时3秒 */ - rt_thread_mdelay(3000); + rt_thread_mdelay(3000); /* 获取时间 */ now = time(RT_NULL); @@ -49,3 +51,5 @@ static int rtc_sample(int argc, char *argv[]) } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(rtc_sample, rtc sample); + +#endif diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/spi_sample.c b/bsp/essemi/es32f369x/drivers/bsp_driver_example/spi_sample.c index 994888cdb0..6f6e730288 100644 --- a/bsp/essemi/es32f369x/drivers/bsp_driver_example/spi_sample.c +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/spi_sample.c @@ -1,7 +1,19 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes @@ -17,13 +29,14 @@ #include #include +#ifdef RT_USING_SPI + #define SPI_DEVICE_NAME "spi00" #define BUF_LEN 16 static void spi_io_sample(int argc, char *argv[]) { struct rt_spi_device * spi_dev; /* spi设备的句柄 */ - struct rt_spi_configuration spi_config; rt_uint8_t i,buffer[BUF_LEN] = { 0U }; rt_err_t s_stat; rt_err_t result; @@ -37,23 +50,8 @@ static void spi_io_sample(int argc, char *argv[]) return; } - - /* 清空配置结构体 */ - rt_memset(&spi_config,0,sizeof(struct rt_spi_configuration)); - - spi_config.mode &= ~RT_SPI_SLAVE; /* 主机模式 */ - spi_config.mode &= ~RT_SPI_3WIRE; /* 4线，双向传输 */ - spi_config.mode |= RT_SPI_CPHA; /* 第二边沿采样 */ - spi_config.mode |= RT_SPI_CPOL; /* 空闲高电平 */ - spi_config.mode |= RT_SPI_NO_CS; /* 禁用软件从机选择管理 */ - spi_config.mode |= RT_SPI_MSB; /* 高位在前 */ - - spi_config.data_width = 8; /* 数据长度：8 */ - - spi_config.max_hz = 2000000; /* 最快时钟频率 */ - /* 配置SPI设备 */ - s_stat = rt_spi_configure(spi_dev,&spi_config); + s_stat = rt_spi_configure(spi_dev,&(spi_dev->config)); if(s_stat != RT_EOK) { @@ -150,3 +148,5 @@ static void spi_io_sample(int argc, char *argv[]) } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(spi_io_sample, spi sample); + +#endif diff --git a/bsp/essemi/es32f369x/drivers/drv_adc.c b/bsp/essemi/es32f369x/drivers/drv_adc.c index 79afc06123..716fddcfa4 100644 --- a/bsp/essemi/es32f369x/drivers/drv_adc.c +++ b/bsp/essemi/es32f369x/drivers/drv_adc.c @@ -1,26 +1,44 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes * 2019-04-03 wangyq the first version - * 2019-11-01 wangyq update libraries + * 2019-11-01 wangyq update libraries + * 2021-04-20 liuhy the second version */ #include #include #include #include "board.h" -#include "drv_adc.h" -#include -#include +#include "drv_adc.h" #ifdef RT_USING_ADC /* define adc instance */ + +#ifdef BSP_USING_ADC0 static struct rt_adc_device _device_adc0; +#endif /*BSP_USING_ADC0*/ + +#ifdef BSP_USING_ADC1 +static struct rt_adc_device _device_adc1; +#endif /*BSP_USING_ADC1*/ /* enable or disable adc */ static rt_err_t es32f3_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled) @@ -48,7 +66,8 @@ static adc_channel_t es32f3_adc_get_channel(rt_uint32_t channel) /* Initialize ADC pin */ gpio_initstruct.mode = GPIO_MODE_INPUT; - gpio_initstruct.pupd = GPIO_FLOATING; + gpio_initstruct.pupd = GPIO_FLOATING; + gpio_initstruct.odos = GPIO_OPEN_DRAIN; gpio_initstruct.podrv = GPIO_OUT_DRIVE_1; gpio_initstruct.nodrv = GPIO_OUT_DRIVE_1; gpio_initstruct.flt = GPIO_FILTER_DISABLE; @@ -60,77 +79,69 @@ static adc_channel_t es32f3_adc_get_channel(rt_uint32_t channel) { case 0: es32f3_channel = ADC_CHANNEL_0; - ald_gpio_init(GPIOC, GPIO_PIN_0, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH0_GPIO, ES_GPIO_ADC_CH0_PIN, &gpio_initstruct); break; case 1: es32f3_channel = ADC_CHANNEL_1; - ald_gpio_init(GPIOC, GPIO_PIN_1, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH1_GPIO, ES_GPIO_ADC_CH1_PIN, &gpio_initstruct); break; case 2: es32f3_channel = ADC_CHANNEL_2; - ald_gpio_init(GPIOC, GPIO_PIN_2, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH2_GPIO, ES_GPIO_ADC_CH2_PIN, &gpio_initstruct); break; case 3: es32f3_channel = ADC_CHANNEL_3; - ald_gpio_init(GPIOC, GPIO_PIN_3, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH3_GPIO, ES_GPIO_ADC_CH3_PIN, &gpio_initstruct); break; case 4: es32f3_channel = ADC_CHANNEL_4; - ald_gpio_init(GPIOA, GPIO_PIN_0, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH4_GPIO, ES_GPIO_ADC_CH4_PIN, &gpio_initstruct); break; case 5: es32f3_channel = ADC_CHANNEL_5; - ald_gpio_init(GPIOA, GPIO_PIN_1, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH5_GPIO, ES_GPIO_ADC_CH5_PIN, &gpio_initstruct); break; case 6: es32f3_channel = ADC_CHANNEL_6; - ald_gpio_init(GPIOA, GPIO_PIN_2, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH6_GPIO, ES_GPIO_ADC_CH6_PIN, &gpio_initstruct); break; case 7: es32f3_channel = ADC_CHANNEL_7; - ald_gpio_init(GPIOA, GPIO_PIN_3, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH7_GPIO, ES_GPIO_ADC_CH7_PIN, &gpio_initstruct); break; case 8: es32f3_channel = ADC_CHANNEL_8; - ald_gpio_init(GPIOA, GPIO_PIN_4, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH8_GPIO, ES_GPIO_ADC_CH8_PIN, &gpio_initstruct); break; case 9: es32f3_channel = ADC_CHANNEL_9; - ald_gpio_init(GPIOA, GPIO_PIN_5, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH9_GPIO, ES_GPIO_ADC_CH9_PIN, &gpio_initstruct); break; case 10: es32f3_channel = ADC_CHANNEL_10; - ald_gpio_init(GPIOA, GPIO_PIN_6, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH10_GPIO, ES_GPIO_ADC_CH10_PIN, &gpio_initstruct); break; case 11: es32f3_channel = ADC_CHANNEL_11; - ald_gpio_init(GPIOA, GPIO_PIN_7, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH11_GPIO, ES_GPIO_ADC_CH11_PIN, &gpio_initstruct); break; case 12: es32f3_channel = ADC_CHANNEL_12; - ald_gpio_init(GPIOC, GPIO_PIN_4, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH12_GPIO, ES_GPIO_ADC_CH12_PIN, &gpio_initstruct); break; case 13: es32f3_channel = ADC_CHANNEL_13; - ald_gpio_init(GPIOC, GPIO_PIN_5, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH13_GPIO, ES_GPIO_ADC_CH13_PIN, &gpio_initstruct); break; case 14: es32f3_channel = ADC_CHANNEL_14; - ald_gpio_init(GPIOB, GPIO_PIN_0, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH14_GPIO, ES_GPIO_ADC_CH14_PIN, &gpio_initstruct); break; case 15: es32f3_channel = ADC_CHANNEL_15; - ald_gpio_init(GPIOB, GPIO_PIN_1, &gpio_initstruct); - break; - case 16: - es32f3_channel = ADC_CHANNEL_16; - break; - case 17: - es32f3_channel = ADC_CHANNEL_17; - break; - case 18: - es32f3_channel = ADC_CHANNEL_18; + ald_gpio_init(ES_GPIO_ADC_CH15_GPIO, ES_GPIO_ADC_CH15_PIN, &gpio_initstruct); break; + default: break; } @@ -149,7 +160,7 @@ static rt_err_t es32f3_get_adc_value(struct rt_adc_device *device, rt_uint32_t c /* config adc channel */ nm_config.ch = es32f3_adc_get_channel(channel); nm_config.idx = ADC_NCH_IDX_1; - nm_config.samp = ADC_SAMPLETIME_4; + nm_config.samp = ES_ADC0_NCH_SAMPLETIME; ald_adc_normal_channel_config(_hadc, &nm_config); ald_adc_normal_start(_hadc); @@ -169,23 +180,51 @@ static const struct rt_adc_ops es32f3_adc_ops = int rt_hw_adc_init(void) { int result = RT_EOK; - static adc_handle_t _h_adc0; + adc_handle_t _h_adc; /* adc function initialization */ - _h_adc0.perh = ADC0; - _h_adc0.init.align = ADC_DATAALIGN_RIGHT; - _h_adc0.init.scan = DISABLE; - _h_adc0.init.cont = DISABLE; - _h_adc0.init.disc = ADC_ALL_DISABLE; - _h_adc0.init.disc_nr = ADC_DISC_NR_1; - _h_adc0.init.data_bit = ADC_CONV_BIT_12; - _h_adc0.init.div = ADC_CKDIV_128; - _h_adc0.init.nche_sel = ADC_NCHESEL_MODE_ALL; - _h_adc0.init.n_ref = ADC_NEG_REF_VSS; - _h_adc0.init.p_ref = ADC_POS_REF_VDD; - ald_adc_init(&_h_adc0); + _h_adc.init.scan = DISABLE; + _h_adc.init.cont = DISABLE; + _h_adc.init.disc = ADC_ALL_DISABLE; + _h_adc.init.disc_nr = ADC_DISC_NR_1; + _h_adc.init.nch_nr = ADC_NCH_NR_16; + _h_adc.init.nche_sel = ADC_NCHESEL_MODE_ALL; + _h_adc.init.cont = DISABLE; + _h_adc.init.n_ref = ADC_NEG_REF_VSS; + _h_adc.init.p_ref = ADC_POS_REF_VDD; - rt_hw_adc_register(&_device_adc0, "adc0", &es32f3_adc_ops, &_h_adc0); +#ifdef BSP_USING_ADC0 + + static adc_handle_t _h_adc0; + + _h_adc0.init = _h_adc.init; + + _h_adc0.perh = ADC0; + _h_adc0.init.align = ES_ADC0_ALIGN; + _h_adc0.init.data_bit = ES_ADC0_DATA_BIT; + _h_adc0.init.div = ES_ADC0_CLK_DIV; + ald_adc_init(&_h_adc0); + + rt_hw_adc_register(&_device_adc0, ES_DEVICE_NAME_ADC0, &es32f3_adc_ops, &_h_adc0); + +#endif /*BSP_USING_ADC0*/ + +#ifdef BSP_USING_ADC1 + + static adc_handle_t _h_adc1; + + _h_adc1.init = _h_adc.init; + + _h_adc1.perh = ADC1; + _h_adc1.init.align = ES_ADC1_ALIGN; + _h_adc1.init.data_bit = ES_ADC1_DATA_BIT; + _h_adc1.init.div = ES_ADC1_CLK_DIV; + ald_adc_init(&_h_adc1); + + rt_hw_adc_register(&_device_adc1, ES_DEVICE_NAME_ADC1, &es32f3_adc_ops, &_h_adc1); + +#endif /*BSP_USING_ADC1*/ + return result; } diff --git a/bsp/essemi/es32f369x/drivers/drv_adc.h b/bsp/essemi/es32f369x/drivers/drv_adc.h index eaddd67407..6585b44cf0 100644 --- a/bsp/essemi/es32f369x/drivers/drv_adc.h +++ b/bsp/essemi/es32f369x/drivers/drv_adc.h @@ -3,14 +3,29 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes - * 2019-04-03 wangyq the first version + * 2019-04-03 wangyq the first version + * 2021-04-20 liuhy the second version */ #ifndef DRV_ADC_H__ #define DRV_ADC_H__ +#include "es_conf_info_adc.h" + int rt_hw_adc_init(void); #endif diff --git a/bsp/essemi/es32f369x/drivers/drv_can.c b/bsp/essemi/es32f369x/drivers/drv_can.c index 04f4f161d7..6e7456b9b6 100644 --- a/bsp/essemi/es32f369x/drivers/drv_can.c +++ b/bsp/essemi/es32f369x/drivers/drv_can.c @@ -1,51 +1,93 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes - * 2020-01-14 wangyq the first version + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version */ #include "drv_can.h" -#ifdef BSP_USING_CAN +#ifdef RT_USING_CAN static struct es32f3_can can; -/* attention !!! baud calculation example: Pclk / ((sjw + seg1 + seg2) * psc) 48 / ((1 + 3 + 2) * 8) = 1MHz */ -static const struct es32f3_baud_rate_tab can_baud_rate_tab[] = -{ - {CAN1MBaud, 8}, - {CAN800kBaud, 10}, - {CAN500kBaud, 16}, - {CAN250kBaud, 32}, - {CAN125kBaud, 64}, - {CAN100kBaud, 80}, - {CAN50kBaud, 160}, - {CAN20kBaud, 400}, - {CAN10kBaud, 800} -}; -static rt_uint32_t get_can_baud_index(rt_uint32_t baud) -{ - rt_uint32_t len, index; - - len = sizeof(can_baud_rate_tab) / sizeof(can_baud_rate_tab[0]); - for (index = 0; index < len; index++) +static rt_uint32_t get_can_baud_index(rt_uint32_t baud,can_init_t * init) +{ +/* attention !!! baud calculation example: Pclk / ((1 + seg1 + seg2) * psc) Pclk=48 / ((1 + seg1=3 + seg2=2) * 8) = 1MHz */ + double target,temp,min; + uint32_t i,j,j_max,near = 0; + target = (double)(ald_cmu_get_pclk1_clock()); + target/= baud; /*计算误差1*/ + + min = 0xFFFFFFFF; + + for(i = 1 + 16 + 8 ;i > 2;i--) /*SYNC_SEG + SEG1 + SEG2*/ { - if (can_baud_rate_tab[index].baud_rate == baud) - return index; + j_max = target/i/(0.98) + 1; /*缩小范围*/ + j_max = (j_max > 1024) ? (1024) : (j_max); + + for(j = target/i/1.02 ;j < j_max;j++) + { + temp = target/i/j; /*计算误差2*/ + temp = (temp > 1) ? (temp - 1) : (1 - temp); + temp+= ((1.0 * i * j) / 0xFFFFFFFF) ; + + if(temp < min) + { + if(temp > 0.000001) + { + near = (i<<16) + j; + min = temp; + } + else + { + init->seg1 = (can_seg1_t)((i - 1)*2/3-1); + init->seg2 = (can_seg2_t)(i - init->seg1 - 1 - 1 - 1); + init->psc = j; + + return 0; + } + } + } } - return 0; /* default baud is CAN1MBaud */ + if(min < 0.01) + { + i = near>>16; + j = near % (1<<16); + init->seg1 = (can_seg1_t)((i - 1)*2/3-1); + init->seg2 = (can_seg2_t)(i - init->seg1 - 1 - 1 - 1); + init->psc = j; + + return 0; + } + else + { + return 1; + } } + static rt_err_t _can_config(struct rt_can_device *can_device, struct can_configure *cfg) { struct es32f3_can *drv_can; - rt_uint32_t baud_index; RT_ASSERT(can_device); RT_ASSERT(cfg); @@ -56,7 +98,7 @@ static rt_err_t _can_config(struct rt_can_device *can_device, struct can_configu drv_can->CanHandle.init.ttcm = DISABLE; drv_can->CanHandle.init.abom = ENABLE; drv_can->CanHandle.init.awk = DISABLE; - drv_can->CanHandle.init.artx = DISABLE; + drv_can->CanHandle.init.artx = (type_func_t)ES_CAN0_AUTO_BAN_RE_T; drv_can->CanHandle.init.rfom = DISABLE; drv_can->CanHandle.init.txmp = ENABLE; @@ -75,12 +117,13 @@ static rt_err_t _can_config(struct rt_can_device *can_device, struct can_configu drv_can->CanHandle.init.mode = CAN_MODE_SILENT_LOOPBACK; break; } - - baud_index = get_can_baud_index(cfg->baud_rate); - drv_can->CanHandle.init.sjw = CAN_SJW_1; - drv_can->CanHandle.init.seg1 = CAN_SEG1_3; - drv_can->CanHandle.init.seg2 = CAN_SEG2_2; - drv_can->CanHandle.init.psc = can_baud_rate_tab[baud_index].config_data; + /*配置参数*/ + if(get_can_baud_index(cfg->baud_rate,&(drv_can->CanHandle.init))) + { + return -RT_ERROR; + } + drv_can->CanHandle.init.sjw = (can_sjw_t)(cfg->reserved); + /* init can */ if (ald_can_init(&drv_can->CanHandle) != OK) { @@ -95,8 +138,12 @@ static rt_err_t _can_config(struct rt_can_device *can_device, struct can_configu static rt_err_t _can_control(struct rt_can_device *can_device, int cmd, void *arg) { rt_uint32_t argval; + struct es32f3_can *drv_can; + +#ifdef RT_CAN_USING_HDR struct rt_can_filter_config *filter_cfg; +#endif RT_ASSERT(can_device != RT_NULL); drv_can = (struct es32f3_can *)can_device->parent.user_data; @@ -108,17 +155,24 @@ static rt_err_t _can_control(struct rt_can_device *can_device, int cmd, void *ar argval = (rt_uint32_t) arg; if (argval == RT_DEVICE_FLAG_INT_RX) { - ald_can_interrupt_config(&drv_can->CanHandle, (can_it_t)(CAN_IT_FP0 | CAN_IT_FF0 | CAN_IT_FOV0 | - CAN_IT_FP1 | CAN_IT_FF1 | CAN_IT_FOV1), DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FP0, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FF0, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FOV0, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FP1, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FF1, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FOV1, DISABLE); } else if (argval == RT_DEVICE_FLAG_INT_TX) { ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_TXM, DISABLE); } else if (argval == RT_DEVICE_CAN_INT_ERR) - { - ald_can_interrupt_config(&drv_can->CanHandle, (can_it_t)(CAN_IT_WARN | CAN_IT_PERR | CAN_IT_BOF | - CAN_IT_PRERR | CAN_IT_ERR), DISABLE); + { + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_WARN, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_PERR, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_BOF, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_PRERR, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_ERR, DISABLE); } break; case RT_DEVICE_CTRL_SET_INT: @@ -127,29 +181,36 @@ static rt_err_t _can_control(struct rt_can_device *can_device, int cmd, void *ar { NVIC_SetPriority(CAN0_RX0_IRQn, 1); NVIC_EnableIRQ(CAN0_RX0_IRQn); - - NVIC_SetPriority(CAN0_RX0_IRQn, 1); - NVIC_EnableIRQ(CAN0_RX0_IRQn); - - ald_can_interrupt_config(&drv_can->CanHandle, (can_it_t)(CAN_IT_FP0 | CAN_IT_FF0 | CAN_IT_FOV0 | - CAN_IT_FP1 | CAN_IT_FF1 | CAN_IT_FOV1), ENABLE); + + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FP0, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FF0, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FOV0, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FP1, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FF1, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FOV1, ENABLE); + } else if (argval == RT_DEVICE_FLAG_INT_TX) { NVIC_SetPriority(CAN0_TX_IRQn, 1); NVIC_EnableIRQ(CAN0_TX_IRQn); - + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_TXM, ENABLE); } else if (argval == RT_DEVICE_CAN_INT_ERR) { NVIC_SetPriority(CAN0_EXCEPTION_IRQn, 1); NVIC_EnableIRQ(CAN0_EXCEPTION_IRQn); - - ald_can_interrupt_config(&drv_can->CanHandle, (can_it_t)(CAN_IT_WARN | CAN_IT_PERR | CAN_IT_BOF | - CAN_IT_PRERR | CAN_IT_ERR), ENABLE); + + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_WARN, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_PERR, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_BOF, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_PRERR, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_ERR, ENABLE); + } break; +#ifdef RT_CAN_USING_HDR case RT_CAN_CMD_SET_FILTER: if (RT_NULL == arg) { @@ -161,20 +222,70 @@ static rt_err_t _can_control(struct rt_can_device *can_device, int cmd, void *ar filter_cfg = (struct rt_can_filter_config *)arg; /* get default filter */ for (int i = 0; i < filter_cfg->count; i++) - { - drv_can->FilterConfig.number = filter_cfg->items[i].hdr; + { + + /*默认过滤表判断*/ + if(filter_cfg->items[i].hdr < drv_can->device.config.maxhdr) + drv_can->FilterConfig.number = filter_cfg->items[i].hdr; + else + drv_can->FilterConfig.number = ES_C_CAN_DEFAULT_FILTER_NUMBER; + + if(filter_cfg->items[i].mode) + { + /*标识符列表模式： 类型匹配 ，id匹配为：接收的id = 配置的id + 或者 = 配置的mask ，通过*/ + /*扩展帧*/ + if(filter_cfg->items[i].ide) + { +// filter_cfg->items[i].id = filter_cfg->items[i].id ; /*id 29 位*/ + filter_cfg->items[i].mask = ((filter_cfg->items[i].mask << 3) | + (filter_cfg->items[i].ide << 2) | + (filter_cfg->items[i].rtr << 1)); + } + else /*标准帧*/ + { + filter_cfg->items[i].id = (filter_cfg->items[i].id << 18); + filter_cfg->items[i].mask = ((filter_cfg->items[i].mask << 21) | + (filter_cfg->items[i].ide << 2) | + (filter_cfg->items[i].rtr << 1)); + } + } + else + { + /*标识符掩码模式*/ + /*扩展帧*/ + if(filter_cfg->items[i].ide) + { + filter_cfg->items[i].mask = (filter_cfg->items[i].mask)<<3; + } + else /*标准帧*/ + { + filter_cfg->items[i].id = (filter_cfg->items[i].id)<<18; + filter_cfg->items[i].mask = (filter_cfg->items[i].mask)<<21; + } + +#if ES_C_CAN_FILTER_FRAME_TYPE + /*匹配类型*/ + filter_cfg->items[i].mask |= 0x6; +#endif + + } + drv_can->FilterConfig.id_high = (filter_cfg->items[i].id >> 13) & 0xFFFF; drv_can->FilterConfig.id_low = ((filter_cfg->items[i].id << 3) | (filter_cfg->items[i].ide << 2) | (filter_cfg->items[i].rtr << 1)) & 0xFFFF; drv_can->FilterConfig.mask_id_high = (filter_cfg->items[i].mask >> 16) & 0xFFFF; drv_can->FilterConfig.mask_id_low = filter_cfg->items[i].mask & 0xFFFF; + drv_can->FilterConfig.mode = (can_filter_mode_t)filter_cfg->items[i].mode; /* Filter conf */ ald_can_filter_config(&drv_can->CanHandle, &drv_can->FilterConfig); } } break; + +#endif case RT_CAN_CMD_SET_MODE: argval = (rt_uint32_t) arg; if (argval != RT_CAN_MODE_NORMAL && @@ -192,18 +303,7 @@ static rt_err_t _can_control(struct rt_can_device *can_device, int cmd, void *ar break; case RT_CAN_CMD_SET_BAUD: argval = (rt_uint32_t) arg; - if (argval != CAN1MBaud && - argval != CAN800kBaud && - argval != CAN500kBaud && - argval != CAN250kBaud && - argval != CAN125kBaud && - argval != CAN100kBaud && - argval != CAN50kBaud && - argval != CAN20kBaud && - argval != CAN10kBaud) - { - return -RT_ERROR; - } + if (argval != drv_can->device.config.baud_rate) { drv_can->device.config.baud_rate = argval; @@ -312,6 +412,7 @@ static int _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t } /* clear TIR */ h_can->perh->TxMailBox[box_num].TXID &= CAN_TXID0_TXMREQ_MSK; + /* Set up the Id */ if (RT_CAN_STDID == pmsg->ide) { @@ -336,7 +437,7 @@ static int _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t ((uint32_t)pmsg->data[0] << CAN_TXDL0_BYTE0_POSS)); /* Request transmission */ SET_BIT(h_can->perh->TxMailBox[box_num].TXID, CAN_TXID0_TXMREQ_MSK); - + return RT_EOK; } else @@ -346,6 +447,8 @@ static int _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t return -RT_ERROR; } + + } static int _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo) @@ -427,8 +530,12 @@ static void _can_rx_isr(struct rt_can_device *can, rt_uint32_t fifo) /* RX interrupt */ else { + if(CAN_RX_MSG_PENDING(h_can, CAN_RX_FIFO0) != 0) + { /* save to user list */ rt_hw_can_isr(can, RT_CAN_EVENT_RX_IND | fifo << 8); + } + /* Clear FIFO0 rx Flag */ SET_BIT(h_can->perh->RXF0, CAN_RXF0_FREE_MSK); } @@ -444,8 +551,12 @@ static void _can_rx_isr(struct rt_can_device *can, rt_uint32_t fifo) /* RX interrupt */ else { + if(CAN_RX_MSG_PENDING(h_can, CAN_RX_FIFO1) != 0) + { /* save to user list */ rt_hw_can_isr(can, RT_CAN_EVENT_RX_IND | fifo << 8); + } + /* Clear FIFO0 rx Flag */ SET_BIT(h_can->perh->RXF1, CAN_RXF1_FREE_MSK); } @@ -575,30 +686,30 @@ void CAN0_EXCEPTION_Handler(void) int rt_hw_can_init(void) { gpio_init_t h_gpio; - struct can_configure config = CANDEFAULTCONFIG; - - config.privmode = RT_CAN_MODE_NOPRIV; - config.ticks = 50; -#ifdef RT_CAN_USING_HDR - config.maxhdr = 14; -#endif /* Initialize can common pin */ h_gpio.odos = GPIO_PUSH_PULL; h_gpio.pupd = GPIO_PUSH_UP; - h_gpio.podrv = GPIO_OUT_DRIVE_1; - h_gpio.nodrv = GPIO_OUT_DRIVE_0_1; + h_gpio.podrv = GPIO_OUT_DRIVE_6; + h_gpio.nodrv = GPIO_OUT_DRIVE_6; h_gpio.flt = GPIO_FILTER_DISABLE; h_gpio.type = GPIO_TYPE_TTL; - h_gpio.func = GPIO_FUNC_3; +#if defined(ES_CAN0_RX_GPIO_FUNC)&&defined(ES_CAN0_RX_GPIO_PORT)&&defined(ES_CAN0_RX_GPIO_PIN) /* Initialize can rx pin */ - h_gpio.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOB, GPIO_PIN_8, &h_gpio); - + h_gpio.mode = GPIO_MODE_INPUT; + h_gpio.func = ES_CAN0_RX_GPIO_FUNC; + ald_gpio_init(ES_CAN0_RX_GPIO_PORT, ES_CAN0_RX_GPIO_PIN, &h_gpio); +#endif + + +#if defined(ES_CAN0_TX_GPIO_FUNC)&&defined(ES_CAN0_TX_GPIO_PORT)&&defined(ES_CAN0_TX_GPIO_PIN) /* Initialize can tx pin */ - h_gpio.mode = GPIO_MODE_OUTPUT; - ald_gpio_init(GPIOB, GPIO_PIN_9, &h_gpio); + h_gpio.mode = GPIO_MODE_OUTPUT; + h_gpio.func = ES_CAN0_TX_GPIO_FUNC; + ald_gpio_init(ES_CAN0_TX_GPIO_PORT, ES_CAN0_TX_GPIO_PIN, &h_gpio); +#endif + /* config default filter */ can_filter_t filter = {0}; @@ -607,15 +718,21 @@ int rt_hw_can_init(void) filter.mask_id_high = 0x0000; filter.mask_id_low = 0x0000; filter.fifo = CAN_FILTER_FIFO0; - filter.number = 0; + filter.number = ES_C_CAN_DEFAULT_FILTER_NUMBER; filter.mode = CAN_FILTER_MODE_MASK; filter.scale = CAN_FILTER_SCALE_32; filter.active = ENABLE; can.FilterConfig = filter; - can.device.config = config; + can.device.config = (struct can_configure)ES_CAN0_CONFIG; +#ifdef RT_CAN_USING_HDR + can.device.config.maxhdr = 14; +#endif + can.device.config.privmode = RT_CAN_MODE_NOPRIV; + can.device.config.ticks = 50; + can.device.config.reserved = ES_CAN0_SJW; /* register CAN1 device */ - rt_hw_can_register(&can.device, "can", &_can_ops, &can); + rt_hw_can_register(&can.device, ES_DEVICE_NAME_CAN0, &_can_ops, &can); return 0; } diff --git a/bsp/essemi/es32f369x/drivers/drv_can.h b/bsp/essemi/es32f369x/drivers/drv_can.h index cffe4b81b0..d7eeb859aa 100644 --- a/bsp/essemi/es32f369x/drivers/drv_can.h +++ b/bsp/essemi/es32f369x/drivers/drv_can.h @@ -3,9 +3,22 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes - * 2020-01-14 wangyq the first version + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version */ #ifndef DRV_CAN_H__ @@ -14,16 +27,9 @@ #include #include #include +#include "es_conf_info_can.h" -#include -#include - -struct es32f3_baud_rate_tab -{ - rt_uint32_t baud_rate; - rt_uint32_t config_data; -}; - +#ifdef RT_USING_CAN /* es32f3 can device */ struct es32f3_can { @@ -34,4 +40,5 @@ struct es32f3_can int rt_hw_can_init(void); +#endif #endif /*DRV_CAN_H__ */ diff --git a/bsp/essemi/es32f369x/drivers/drv_gpio.c b/bsp/essemi/es32f369x/drivers/drv_gpio.c index fa39a31ea5..8ce6ab7aa8 100644 --- a/bsp/essemi/es32f369x/drivers/drv_gpio.c +++ b/bsp/essemi/es32f369x/drivers/drv_gpio.c @@ -1,107 +1,40 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes - * 2020-01-14 wangyq the first version + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version */ -#include -#include #include "board.h" #include "drv_gpio.h" -#include -#include + +/*管脚映射在 es_conf_info_map.h 的 pins[] 中*/ #ifdef RT_USING_PIN -#define __ES32F3_PIN(index, gpio, gpio_index) {index, GPIO##gpio, GPIO_PIN_##gpio_index} -#define __ES32F3_PIN_DEFAULT {-1, 0, 0} - -/* ES32F3 GPIO driver */ -struct pin_index -{ - int index; - GPIO_TypeDef *gpio; - uint32_t pin; -}; - -static const struct pin_index pins[] = -{ - __ES32F3_PIN_DEFAULT, - __ES32F3_PIN_DEFAULT, - __ES32F3_PIN(2, C, 13), - __ES32F3_PIN(3, C, 14), - __ES32F3_PIN(4, C, 15), - __ES32F3_PIN(5, H, 0), - __ES32F3_PIN(6, H, 1), - __ES32F3_PIN_DEFAULT, - __ES32F3_PIN(8, C, 0), - __ES32F3_PIN(9, C, 1), - __ES32F3_PIN(10, C, 2), - __ES32F3_PIN(11, C, 3), - __ES32F3_PIN(12, H, 3), - __ES32F3_PIN(13, H, 4), - __ES32F3_PIN(14, A, 0), - __ES32F3_PIN(15, A, 1), - __ES32F3_PIN(16, A, 2), - __ES32F3_PIN(17, A, 3), - __ES32F3_PIN(18, F, 0), - __ES32F3_PIN(19, F, 1), - __ES32F3_PIN(20, A, 4), - __ES32F3_PIN(21, A, 5), - __ES32F3_PIN(22, A, 6), - __ES32F3_PIN(23, A, 7), - __ES32F3_PIN(24, C, 4), - __ES32F3_PIN(25, C, 5), - __ES32F3_PIN(26, B, 0), - __ES32F3_PIN(27, B, 1), - __ES32F3_PIN(28, B, 2), - __ES32F3_PIN(29, B, 10), - __ES32F3_PIN(30, B, 11), - __ES32F3_PIN_DEFAULT, - __ES32F3_PIN_DEFAULT, - __ES32F3_PIN(33, B, 12), - __ES32F3_PIN(34, B, 13), - __ES32F3_PIN(35, B, 14), - __ES32F3_PIN(36, B, 15), - __ES32F3_PIN(37, C, 6), - __ES32F3_PIN(38, C, 7), - __ES32F3_PIN(39, C, 8), - __ES32F3_PIN_DEFAULT, - __ES32F3_PIN_DEFAULT, - __ES32F3_PIN_DEFAULT, - __ES32F3_PIN_DEFAULT, - __ES32F3_PIN_DEFAULT, - __ES32F3_PIN_DEFAULT, - __ES32F3_PIN(46, A, 13), - __ES32F3_PIN_DEFAULT, - __ES32F3_PIN_DEFAULT, - __ES32F3_PIN(49, A, 14), - __ES32F3_PIN(50, A, 15), - __ES32F3_PIN(51, C, 10), - __ES32F3_PIN(52, C, 11), - __ES32F3_PIN(53, C, 12), - __ES32F3_PIN(54, D, 2), - __ES32F3_PIN(55, B, 3), - __ES32F3_PIN(56, B, 4), - __ES32F3_PIN(57, B, 5), - __ES32F3_PIN(58, B, 6), - __ES32F3_PIN(59, B, 7), - __ES32F3_PIN(60, H, 2), - __ES32F3_PIN(61, B, 8), - __ES32F3_PIN(62, B, 9), - __ES32F3_PIN_DEFAULT, - __ES32F3_PIN_DEFAULT, -}; struct pin_irq_map { rt_uint16_t pinbit; IRQn_Type irqno; }; + static const struct pin_irq_map pin_irq_map[] = { {GPIO_PIN_0, EXTI0_IRQn}, @@ -140,7 +73,151 @@ struct rt_pin_irq_hdr pin_irq_hdr_tab[] = { -1, 0, RT_NULL, RT_NULL}, { -1, 0, RT_NULL, RT_NULL}, { -1, 0, RT_NULL, RT_NULL}, -}; +}; + +#ifdef ES_CONF_EXTI_IRQ_0 + +RT_WEAK void irq_pin0_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 0\r\n"); +} +#endif + +#ifdef ES_CONF_EXTI_IRQ_1 + +RT_WEAK void irq_pin1_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 1\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_2 + + RT_WEAK void irq_pin2_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 2\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_3 + +RT_WEAK void irq_pin3_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 3\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_4 + +RT_WEAK void irq_pin4_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 4\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_5 + +RT_WEAK void irq_pin5_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 5\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_6 + +RT_WEAK void irq_pin6_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 6\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_7 + +RT_WEAK void irq_pin7_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 7\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_8 + +RT_WEAK void irq_pin8_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 8\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_9 + +RT_WEAK void irq_pin9_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 9\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_10 + +RT_WEAK void irq_pin10_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 10\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_11 + +RT_WEAK void irq_pin11_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 11\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_12 + +RT_WEAK void irq_pin12_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 12\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_13 + +RT_WEAK void irq_pin13_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 13\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_14 + +RT_WEAK void irq_pin14_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 14\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_15 + +RT_WEAK void irq_pin15_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 15\r\n"); +} + +#endif + #define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) const struct pin_index *get_pin(uint8_t pin) @@ -200,8 +277,8 @@ void es32f3_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) gpio_initstruct.podrv = GPIO_OUT_DRIVE_1; gpio_initstruct.nodrv = GPIO_OUT_DRIVE_0_1; gpio_initstruct.type = GPIO_TYPE_CMOS; - gpio_initstruct.pupd = GPIO_FLOATING; - gpio_initstruct.odos = GPIO_PUSH_PULL; + gpio_initstruct.odos = GPIO_PUSH_PULL; + gpio_initstruct.flt = GPIO_FILTER_DISABLE; if (mode == PIN_MODE_OUTPUT) { @@ -364,7 +441,11 @@ rt_err_t es32f3_pin_irq_enable(struct rt_device *device, rt_base_t pin, ald_gpio_exti_init(index->gpio, index->pin, &exti_initstruct); /* Configure GPIO_InitStructure */ gpio_initstruct.mode = GPIO_MODE_INPUT; - gpio_initstruct.func = GPIO_FUNC_1; + gpio_initstruct.odos = GPIO_PUSH_PULL; + gpio_initstruct.podrv = GPIO_OUT_DRIVE_1; + gpio_initstruct.nodrv = GPIO_OUT_DRIVE_1; + gpio_initstruct.func = GPIO_FUNC_1; + gpio_initstruct.flt = GPIO_FILTER_DISABLE; switch (pin_irq_hdr_tab[irqindex].mode) { case PIN_IRQ_MODE_RISING: @@ -408,18 +489,9 @@ const static struct rt_pin_ops _es32f3_pin_ops = es32f3_pin_attach_irq, es32f3_pin_detach_irq, es32f3_pin_irq_enable, - RT_NULL, + /*RT_NULL,*/ }; -int rt_hw_pin_init(void) -{ - int result; - ald_cmu_perh_clock_config(CMU_PERH_GPIO, ENABLE); - result = rt_device_pin_register("pin", &_es32f3_pin_ops, RT_NULL); - return result; -} -INIT_BOARD_EXPORT(rt_hw_pin_init); - rt_inline void pin_irq_hdr(uint16_t GPIO_Pin) { uint16_t irqno; @@ -560,4 +632,44 @@ void EXTI15_Handler(void) rt_interrupt_leave(); } +int rt_hw_pin_init(void) +{ + int result; + + +#ifdef ES_INIT_GPIOS + + rt_size_t i,gpio_conf_num = sizeof(gpio_conf_all) / sizeof(gpio_conf_t); + +#endif + + ald_cmu_perh_clock_config(CMU_PERH_GPIO, ENABLE); + + result = rt_device_pin_register(ES_DEVICE_NAME_PIN, &_es32f3_pin_ops, RT_NULL); + + if(result != RT_EOK)return result; + +#ifdef ES_INIT_GPIOS + + for(i = 0;i < gpio_conf_num;i++) + { + rt_pin_mode( gpio_conf_all[i].pin,gpio_conf_all[i].pin_mode); + + if((gpio_conf_all[i].pin_mode == ES_C_GPIO_MODE_OUTPUT)||(gpio_conf_all[i].pin_mode == ES_C_GPIO_MODE_OUTPUT_OD)) + rt_pin_write(gpio_conf_all[i].pin,gpio_conf_all[i].pin_level); + + if(!gpio_conf_all[i].irq_en)continue; + + rt_pin_attach_irq(gpio_conf_all[i].pin, gpio_conf_all[i].irq_mode, gpio_conf_all[i].callback, RT_NULL); + rt_pin_irq_enable(gpio_conf_all[i].pin, gpio_conf_all[i].irq_en); + } + +#endif + + + + return result; +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + #endif diff --git a/bsp/essemi/es32f369x/drivers/drv_gpio.h b/bsp/essemi/es32f369x/drivers/drv_gpio.h index fef8fb8487..8489e625d5 100644 --- a/bsp/essemi/es32f369x/drivers/drv_gpio.h +++ b/bsp/essemi/es32f369x/drivers/drv_gpio.h @@ -3,14 +3,29 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes - * 2020-01-14 wangyq the first version + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version */ #ifndef DRV_GPIO_H__ #define DRV_GPIO_H__ +#include "es_conf_info_gpio.h" + int rt_hw_pin_init(void); #endif diff --git a/bsp/essemi/es32f369x/drivers/drv_hwtimer.c b/bsp/essemi/es32f369x/drivers/drv_hwtimer.c index f693137ae7..e0fd46a36b 100644 --- a/bsp/essemi/es32f369x/drivers/drv_hwtimer.c +++ b/bsp/essemi/es32f369x/drivers/drv_hwtimer.c @@ -1,21 +1,33 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes * 2019-3-19 wangyq the first version - * 2019-11-01 wangyq update libraries + * 2019-11-01 wangyq update libraries + * 2021-04-20 liuhy the second version */ #include #include #include #include -#include -#include -#include +#include + #ifdef RT_USING_HWTIMER @@ -26,53 +38,167 @@ struct es32f3_hwtimer_dev IRQn_Type IRQn; }; -#ifdef BSP_USING_HWTIMER0 -static struct es32f3_hwtimer_dev hwtimer0; +#ifdef BSP_USING_AD16C4T0_HWTIMER +static struct es32f3_hwtimer_dev ad16c4t0_hwtimer; + +static struct rt_hwtimer_info ad16c4t0_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_AD16C4T0_HWTIMER_MODE +}; + +void AD16C4T0_UP_Handler(void) +{ + ald_timer_clear_flag_status(ad16c4t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&ad16c4t0_hwtimer.parent); +} + +#endif + +#ifdef BSP_USING_AD16C4T1_HWTIMER + +static struct es32f3_hwtimer_dev ad16c4t1_hwtimer; + +static struct rt_hwtimer_info ad16c4t1_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_AD16C4T1_HWTIMER_MODE +}; + +void AD16C4T1_UP_Handler(void) +{ + ald_timer_clear_flag_status(ad16c4t1_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&ad16c4t1_hwtimer.parent); +} + +#endif +#ifdef BSP_USING_GP32C4T0_HWTIMER + +static struct es32f3_hwtimer_dev gp32c4t0_hwtimer; + +static struct rt_hwtimer_info gp32c4t0_info = +{ + + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV , /* maximum count frequency */ + ( ES_SYS_CLK >> ES_CMU_PCLK_1_DIV )/(1U<<16), /* minimum count frequency */ + 0xFFFFFFFF, /* counter maximum value */ + ES_GP32C4T0_HWTIMER_MODE +}; + +void GP32C4T0_Handler(void) +{ + ald_timer_clear_flag_status(gp32c4t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&gp32c4t0_hwtimer.parent); +} + +#endif +#ifdef BSP_USING_GP32C4T1_HWTIMER + +static struct es32f3_hwtimer_dev gp32c4t1_hwtimer; + +static struct rt_hwtimer_info gp32c4t1_info = +{ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV ), /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV )/(1U<<16), /* minimum count frequency */ + 0xFFFFFFFF, /* counter maximum value */ + ES_GP32C4T1_HWTIMER_MODE +}; + +void GP32C4T1_Handler(void) +{ + ald_timer_clear_flag_status(gp32c4t1_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&gp32c4t1_hwtimer.parent); +} + +#endif +#ifdef BSP_USING_GP16C4T0_HWTIMER + +static struct es32f3_hwtimer_dev gp16c4t0_hwtimer; + +static struct rt_hwtimer_info gp16c4t0_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_GP16C4T0_HWTIMER_MODE +}; + +void GP16C4T0_Handler(void) +{ + ald_timer_clear_flag_status(gp16c4t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&gp16c4t0_hwtimer.parent); +} + +#endif +#ifdef BSP_USING_GP16C4T1_HWTIMER + +static struct es32f3_hwtimer_dev gp16c4t1_hwtimer; + +static struct rt_hwtimer_info gp16c4t1_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_GP16C4T1_HWTIMER_MODE +}; + +void GP16C4T1_Handler(void) +{ + ald_timer_clear_flag_status(gp16c4t1_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&gp16c4t1_hwtimer.parent); +} + +#endif +#ifdef BSP_USING_BS16T0_HWTIMER + +static struct es32f3_hwtimer_dev bs16t0_hwtimer; + +static struct rt_hwtimer_info bs16t0_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_BS16T0_HWTIMER_MODE +}; void BS16T0_Handler(void) { - ald_timer_clear_flag_status(hwtimer0.hwtimer_periph, TIMER_FLAG_UPDATE); - rt_device_hwtimer_isr(&hwtimer0.parent); - - if (HWTIMER_MODE_ONESHOT == hwtimer0.parent.mode) - { - ald_timer_base_stop(hwtimer0.hwtimer_periph); - } + ald_timer_clear_flag_status(bs16t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&bs16t0_hwtimer.parent); } -#endif -#ifdef BSP_USING_HWTIMER1 -static struct es32f3_hwtimer_dev hwtimer1; -/* can not use when UART2 Handler is enabled */ +#endif +#ifdef BSP_USING_BS16T1_HWTIMER + +static struct es32f3_hwtimer_dev bs16t1_hwtimer; + +static struct rt_hwtimer_info bs16t1_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_BS16T1_HWTIMER_MODE +}; + void BS16T1_Handler(void) { - /* if BS16T1 it */ - if (ald_timer_get_it_status(hwtimer1.hwtimer_periph, TIMER_IT_UPDATE) && - ald_timer_get_flag_status(hwtimer1.hwtimer_periph, TIMER_FLAG_UPDATE)) - { - ald_timer_clear_flag_status(hwtimer1.hwtimer_periph, TIMER_FLAG_UPDATE); - rt_device_hwtimer_isr(&hwtimer1.parent); - - if (HWTIMER_MODE_ONESHOT == hwtimer1.parent.mode) - { - ald_timer_base_stop(hwtimer1.hwtimer_periph); - } - } + ald_timer_clear_flag_status(bs16t1_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&bs16t1_hwtimer.parent); } -#endif -static struct rt_hwtimer_info es32f3_hwtimer_info = -{ - 96000000, /* maximum count frequency */ - 1, /* minimum count frequency */ - 65535, /* counter maximum value */ - HWTIMER_CNTMODE_UP -}; +#endif static void es32f3_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) { struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data; + struct rt_hwtimer_info *hwtimer_info = (struct rt_hwtimer_info *)timer->info; + + RT_ASSERT(hwtimer != RT_NULL); if (1 == state) @@ -81,19 +207,21 @@ static void es32f3_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) ald_timer_interrupt_config(hwtimer->hwtimer_periph, TIMER_IT_UPDATE, ENABLE); NVIC_EnableIRQ(hwtimer->IRQn); } - hwtimer->parent.freq = ald_cmu_get_pclk1_clock(); - es32f3_hwtimer_info.maxfreq = ald_cmu_get_pclk1_clock(); - es32f3_hwtimer_info.minfreq = ald_cmu_get_pclk1_clock(); + + hwtimer->parent.freq = ald_cmu_get_pclk1_clock()/((hwtimer->hwtimer_periph->perh->PRES & 0xFFFF)+1); + hwtimer_info->maxfreq = hwtimer->parent.freq; + hwtimer_info->minfreq = (hwtimer->parent.freq)/0xFFFF; + } static rt_err_t es32f3_hwtimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t mode) { - struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data; + struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data; RT_ASSERT(hwtimer != RT_NULL); - + WRITE_REG(hwtimer->hwtimer_periph->perh->AR, cnt); ald_timer_base_start(hwtimer->hwtimer_periph); @@ -135,10 +263,37 @@ static rt_err_t es32f3_hwtimer_control(rt_hwtimer_t *timer, { case HWTIMER_CTRL_FREQ_SET: freq = *(rt_uint32_t *)args; - if (freq != ald_cmu_get_pclk1_clock()) - { - ret = -RT_ERROR; + + ret = -RT_ERROR; + + if(freq) + { + double temp,target; + temp = (double)ald_cmu_get_pclk1_clock(); + target = temp/freq; + + if(target < 0x10001) /*最大分频 = max(PRES)+1*/ + { + temp = target - (int)(target); + + if((temp > 0.998)&&(target < 0x10000)) + { + hwtimer->hwtimer_periph->perh->PRES = (uint32_t)target; + ret = RT_EOK; + } + if((temp < 0.002)&&(target >= 0x1)) + { + hwtimer->hwtimer_periph->perh->PRES = (uint32_t)target - 1; + ret = RT_EOK; + } + + } + + if(ret == RT_EOK) /*更新信息*/ + hwtimer->parent.freq = ald_cmu_get_pclk1_clock()/((hwtimer->hwtimer_periph->perh->PRES & 0xFFFF)+1); + } + break; case HWTIMER_CTRL_STOP: @@ -166,24 +321,124 @@ int rt_hw_hwtimer_init(void) { rt_err_t ret = RT_EOK; -#ifdef BSP_USING_HWTIMER0 - static timer_handle_t _hwtimer_periph0; - _hwtimer_periph0.perh = BS16T0; - hwtimer0.IRQn = BS16T0_IRQn; - hwtimer0.hwtimer_periph = &_hwtimer_periph0; - hwtimer0.parent.info = &es32f3_hwtimer_info; - hwtimer0.parent.ops = &es32f3_hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer0.parent, "timer0", &hwtimer0); +#ifdef BSP_USING_AD16C4T0_HWTIMER + static timer_handle_t ad16c4t0_hwtimer_periph; + + ad16c4t0_hwtimer_periph.perh = AD16C4T0; + ad16c4t0_hwtimer.IRQn = AD16C4T0_UP_IRQn; + + ad16c4t0_hwtimer_periph.init.prescaler = ES_AD16C4T0_HWTIMER_PRES - 1; + ad16c4t0_hwtimer_periph.init.mode = ( ES_AD16C4T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + ad16c4t0_hwtimer.hwtimer_periph = &ad16c4t0_hwtimer_periph; + + ad16c4t0_hwtimer.parent.info = &ad16c4t0_info; + ad16c4t0_hwtimer.parent.ops = &es32f3_hwtimer_ops; + ret = rt_device_hwtimer_register(&ad16c4t0_hwtimer.parent, ES_DEVICE_NAME_AD16C4T0_HWTIMER, &ad16c4t0_hwtimer); #endif -#ifdef BSP_USING_HWTIMER1 - static timer_handle_t _hwtimer_periph1; - _hwtimer_periph1.perh = BS16T1; - hwtimer1.IRQn = BS16T1_IRQn; - hwtimer1.hwtimer_periph = &_hwtimer_periph1; - hwtimer1.parent.info = &es32f3_hwtimer_info; - hwtimer1.parent.ops = &es32f3_hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer1.parent, "timer1", &hwtimer1); +#ifdef BSP_USING_AD16C4T1_HWTIMER + static timer_handle_t ad16c4t1_hwtimer_periph; + + ad16c4t1_hwtimer_periph.perh = AD16C4T1; + ad16c4t1_hwtimer.IRQn = AD16C4T1_UP_IRQn; + + ad16c4t1_hwtimer_periph.init.prescaler = ES_AD16C4T1_HWTIMER_PRES - 1; + ad16c4t1_hwtimer_periph.init.mode = ( ES_AD16C4T1_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + ad16c4t1_hwtimer.hwtimer_periph = &ad16c4t1_hwtimer_periph; + + ad16c4t1_hwtimer.parent.info = &ad16c4t1_info; + ad16c4t1_hwtimer.parent.ops = &es32f3_hwtimer_ops; + ret = rt_device_hwtimer_register(&ad16c4t1_hwtimer.parent, ES_DEVICE_NAME_AD16C4T1_HWTIMER, &ad16c4t1_hwtimer); +#endif + +#ifdef BSP_USING_GP32C4T0_HWTIMER + static timer_handle_t gp32c4t0_hwtimer_periph; + + gp32c4t0_hwtimer_periph.perh = GP32C4T0; + gp32c4t0_hwtimer.IRQn = GP32C4T0_IRQn; + + gp32c4t0_hwtimer_periph.init.prescaler = ES_GP32C4T0_HWTIMER_PRES - 1; + gp32c4t0_hwtimer_periph.init.mode = ( ES_GP32C4T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + gp32c4t0_hwtimer.hwtimer_periph = &gp32c4t0_hwtimer_periph; + + gp32c4t0_hwtimer.parent.info = &gp32c4t0_info; + gp32c4t0_hwtimer.parent.ops = &es32f3_hwtimer_ops; + ret = rt_device_hwtimer_register(&gp32c4t0_hwtimer.parent, ES_DEVICE_NAME_GP32C4T0_HWTIMER, &gp32c4t0_hwtimer); +#endif + +#ifdef BSP_USING_GP32C4T1_HWTIMER + static timer_handle_t gp32c4t1_hwtimer_periph; + + gp32c4t1_hwtimer_periph.perh = GP32C4T1; + gp32c4t1_hwtimer.IRQn = GP32C4T1_IRQn; + + gp32c4t1_hwtimer_periph.init.prescaler = ES_GP32C4T1_HWTIMER_PRES - 1; + gp32c4t1_hwtimer_periph.init.mode = ( ES_GP32C4T1_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + gp32c4t1_hwtimer.hwtimer_periph = &gp32c4t1_hwtimer_periph; + + gp32c4t1_hwtimer.parent.info = &gp32c4t1_info; + gp32c4t1_hwtimer.parent.ops = &es32f3_hwtimer_ops; + ret = rt_device_hwtimer_register(&gp32c4t1_hwtimer.parent, ES_DEVICE_NAME_GP32C4T1_HWTIMER, &gp32c4t1_hwtimer); +#endif + +#ifdef BSP_USING_GP16C4T0_HWTIMER + static timer_handle_t gp16c4t0_hwtimer_periph; + + gp16c4t0_hwtimer_periph.perh = GP16C4T0; + gp16c4t0_hwtimer.IRQn = GP16C4T0_IRQn; + + gp16c4t0_hwtimer_periph.init.prescaler = ES_GP16C4T0_HWTIMER_PRES - 1; + gp16c4t0_hwtimer_periph.init.mode = ( ES_GP16C4T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + gp16c4t0_hwtimer.hwtimer_periph = &gp16c4t0_hwtimer_periph; + + gp16c4t0_hwtimer.parent.info = &gp16c4t0_info; + gp16c4t0_hwtimer.parent.ops = &es32f3_hwtimer_ops; + ret = rt_device_hwtimer_register(&gp16c4t0_hwtimer.parent, ES_DEVICE_NAME_GP16C4T0_HWTIMER, &gp16c4t0_hwtimer); +#endif + +#ifdef BSP_USING_GP16C4T1_HWTIMER + static timer_handle_t gp16c4t1_hwtimer_periph; + + gp16c4t1_hwtimer_periph.perh = GP16C4T1; + gp16c4t1_hwtimer.IRQn = GP16C4T1_IRQn; + + gp16c4t1_hwtimer_periph.init.prescaler = ES_GP16C4T1_HWTIMER_PRES - 1; + gp16c4t1_hwtimer_periph.init.mode = ( ES_GP16C4T1_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + gp16c4t1_hwtimer.hwtimer_periph = &gp16c4t1_hwtimer_periph; + + gp16c4t1_hwtimer.parent.info = &gp16c4t1_info; + gp16c4t1_hwtimer.parent.ops = &es32f3_hwtimer_ops; + ret = rt_device_hwtimer_register(&gp16c4t1_hwtimer.parent, ES_DEVICE_NAME_GP16C4T1_HWTIMER, &gp16c4t1_hwtimer); +#endif + +#ifdef BSP_USING_BS16T0_HWTIMER + static timer_handle_t bs16t0_hwtimer_periph; + + bs16t0_hwtimer_periph.perh = BS16T0; + bs16t0_hwtimer.IRQn = BS16T0_IRQn; + + bs16t0_hwtimer_periph.init.prescaler = ES_BS16T0_HWTIMER_PRES - 1; + bs16t0_hwtimer_periph.init.mode = ( ES_BS16T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + bs16t0_hwtimer.hwtimer_periph = &bs16t0_hwtimer_periph; + + bs16t0_hwtimer.parent.info = &bs16t0_info; + bs16t0_hwtimer.parent.ops = &es32f3_hwtimer_ops; + ret = rt_device_hwtimer_register(&bs16t0_hwtimer.parent, ES_DEVICE_NAME_BS16T0_HWTIMER, &bs16t0_hwtimer); +#endif + +#ifdef BSP_USING_BS16T1_HWTIMER + static timer_handle_t bs16t1_hwtimer_periph; + + bs16t1_hwtimer_periph.perh = BS16T1; + bs16t1_hwtimer.IRQn = BS16T1_IRQn; + + bs16t1_hwtimer_periph.init.prescaler = ES_BS16T1_HWTIMER_PRES - 1; + bs16t1_hwtimer_periph.init.mode = ( ES_BS16T1_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + bs16t1_hwtimer.hwtimer_periph = &bs16t1_hwtimer_periph; + + bs16t1_hwtimer.parent.info = &bs16t1_info; + bs16t1_hwtimer.parent.ops = &es32f3_hwtimer_ops; + ret = rt_device_hwtimer_register(&bs16t1_hwtimer.parent, ES_DEVICE_NAME_BS16T1_HWTIMER, &bs16t1_hwtimer); #endif return ret; diff --git a/bsp/essemi/es32f369x/drivers/drv_hwtimer.h b/bsp/essemi/es32f369x/drivers/drv_hwtimer.h index e18d580fbd..46e307a5c3 100644 --- a/bsp/essemi/es32f369x/drivers/drv_hwtimer.h +++ b/bsp/essemi/es32f369x/drivers/drv_hwtimer.h @@ -3,14 +3,28 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes - * 2019-3-19 wangyq the first version + * 2019-3-19 wangyq the first version + * 2021-04-20 liuhy the second version */ #ifndef DRV_HWTIMER_H__ #define DRV_HWTIMER_H__ +#include "es_conf_info_hwtimer.h" int rt_hw_hwtimer_init(void); #endif diff --git a/bsp/essemi/es32f369x/drivers/drv_i2c.c b/bsp/essemi/es32f369x/drivers/drv_i2c.c index 207890a6d4..c398d5ab45 100644 --- a/bsp/essemi/es32f369x/drivers/drv_i2c.c +++ b/bsp/essemi/es32f369x/drivers/drv_i2c.c @@ -1,12 +1,24 @@ /* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: - * Date Author Notes - * 2020-01-14 wangyq the first version - * 2019-11-01 wangyq update libraries + * Date Author Notes + * 2019-11-01 wangyq update libraries + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version */ #include @@ -14,9 +26,7 @@ #include #include "board.h" #include "drv_i2c.h" -#include -#include -#include + #ifdef RT_USING_I2C @@ -43,36 +53,58 @@ static void _i2c_init(void) gpio_instruct.nodrv = GPIO_OUT_DRIVE_0_1; gpio_instruct.flt = GPIO_FILTER_DISABLE; gpio_instruct.type = GPIO_TYPE_CMOS; - gpio_instruct.func = GPIO_FUNC_5; + + +#ifdef BSP_USING_I2C0 + +#if defined(ES_I2C0_SCL_GPIO_FUNC)&&defined(ES_I2C0_SCL_GPIO_PORT)&&defined(ES_I2C0_SCL_GPIO_PIN) + gpio_instruct.func = ES_I2C0_SCL_GPIO_FUNC; + ald_gpio_init(ES_I2C0_SCL_GPIO_PORT, ES_I2C0_SCL_GPIO_PIN, &gpio_instruct); +#endif + +#if defined(ES_I2C0_SDA_GPIO_FUNC)&&defined(ES_I2C0_SDA_GPIO_PORT)&&defined(ES_I2C0_SDA_GPIO_PIN) + gpio_instruct.func = ES_I2C0_SDA_GPIO_FUNC; + ald_gpio_init(ES_I2C0_SDA_GPIO_PORT, ES_I2C0_SDA_GPIO_PIN, &gpio_instruct); +#endif -#ifdef BSP_USING_I2C0 /* Initialize I2C Function */ - _h_i2c0.perh = I2C0; - _h_i2c0.init.clk_speed = 100000; - _h_i2c0.init.own_addr1 = 0x0A; - _h_i2c0.init.addr_mode = I2C_ADDR_7BIT; - _h_i2c0.init.general_call = I2C_GENERALCALL_DISABLE; - _h_i2c0.init.no_stretch = I2C_NOSTRETCH_ENABLE; + _h_i2c0.perh = I2C0; + _h_i2c0.init.module = I2C_MODULE_MASTER; + _h_i2c0.init.clk_speed = ES_I2C0_CLK_SPEED; + _h_i2c0.init.own_addr1 = ES_I2C0_OWN_ADDR1; + _h_i2c0.init.addr_mode = ES_I2C0_ADDR_MODE; + _h_i2c0.init.general_call = ES_I2C0_GENERAL_CALL; + _h_i2c0.init.no_stretch = ES_I2C0_STRETCH; ald_i2c_reset(&_h_i2c0); ald_i2c_init(&_h_i2c0); - /* PB06->I2C0_SCL, PB07->I2C0_SDA */ - ald_gpio_init(GPIOB, GPIO_PIN_6 | GPIO_PIN_7, &gpio_instruct); + #endif -#ifdef BSP_USING_I2C1 +#ifdef BSP_USING_I2C1 + +#if defined(ES_I2C1_SDA_GPIO_FUNC)&&defined(ES_I2C1_SDA_GPIO_PORT)&&defined(ES_I2C1_SDA_GPIO_PIN) + gpio_instruct.func = ES_I2C1_SDA_GPIO_FUNC; + ald_gpio_init(ES_I2C1_SDA_GPIO_PORT, ES_I2C1_SDA_GPIO_PIN, &gpio_instruct); +#endif + +#if defined(ES_I2C1_SDA_GPIO_FUNC)&&defined(ES_I2C1_SDA_GPIO_PORT)&&defined(ES_I2C1_SDA_GPIO_PIN) + gpio_instruct.func = ES_I2C1_SDA_GPIO_FUNC; + ald_gpio_init(ES_I2C1_SDA_GPIO_PORT, ES_I2C1_SDA_GPIO_PIN, &gpio_instruct); +#endif + /* Initialize i2c function */ - _h_i2c1.perh = I2C1; - _h_i2c1.init.clk_speed = 100000; - _h_i2c1.init.own_addr1 = 0xA0; - _h_i2c1.init.addr_mode = I2C_ADDR_7BIT; - _h_i2c1.init.general_call = I2C_GENERALCALL_DISABLE; - _h_i2c1.init.no_stretch = I2C_NOSTRETCH_ENABLE; + _h_i2c1.perh = I2C1; + _h_i2c1.init.module = I2C_MODULE_MASTER; + _h_i2c1.init.clk_speed = ES_I2C1_CLK_SPEED; + _h_i2c1.init.own_addr1 = ES_I2C1_OWN_ADDR1; + _h_i2c1.init.addr_mode = ES_I2C1_ADDR_MODE; + _h_i2c1.init.general_call = ES_I2C1_GENERAL_CALL; + _h_i2c1.init.no_stretch = ES_I2C1_STRETCH; ald_i2c_reset(&_h_i2c1); ald_i2c_init(&_h_i2c1); - /* PA05->I2C1_SCL, PA06->I2C1_SDA */ - ald_gpio_init(GPIOA, GPIO_PIN_5 | GPIO_PIN_6, &gpio_instruct); + #endif } @@ -133,7 +165,7 @@ int rt_hw_i2c_init(void) _i2c_device0.ops = &es32f3_i2c_ops; _i2c_device0.priv = &_h_i2c0; - result = rt_i2c_bus_device_register(&_i2c_device0, "i2c0"); + result = rt_i2c_bus_device_register(&_i2c_device0, ES_DEVICE_NAME_I2C0); if (result != RT_EOK) { return result; @@ -147,7 +179,7 @@ int rt_hw_i2c_init(void) _i2c_device1.ops = &es32f3_i2c_ops; _i2c_device1.priv = &_h_i2c1; - rt_i2c_bus_device_register(&_i2c_device1, "i2c1"); + rt_i2c_bus_device_register(&_i2c_device1, ES_DEVICE_NAME_I2C1); if (result != RT_EOK) { return result; diff --git a/bsp/essemi/es32f369x/drivers/drv_i2c.h b/bsp/essemi/es32f369x/drivers/drv_i2c.h index d7c2410682..16bfa324d3 100644 --- a/bsp/essemi/es32f369x/drivers/drv_i2c.h +++ b/bsp/essemi/es32f369x/drivers/drv_i2c.h @@ -1,16 +1,31 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes - * 2020-01-14 wangyq the first version + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version */ #ifndef DRV_I2C_H__ #define DRV_I2C_H__ +#include "es_conf_info_i2c.h" + int rt_hw_i2c_init(void); #endif diff --git a/bsp/essemi/es32f369x/drivers/drv_pm.c b/bsp/essemi/es32f369x/drivers/drv_pm.c index ffe46ff6f3..5ec1c8c701 100644 --- a/bsp/essemi/es32f369x/drivers/drv_pm.c +++ b/bsp/essemi/es32f369x/drivers/drv_pm.c @@ -3,16 +3,27 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes * 2020-12-15 liuhy the first version */ -#include "drv_pm.h" +#include "drv_pm.h" #ifdef RT_USING_PM -//uint32_t save_mem[1024] __attribute__ ((aligned(4))); void save_register(void *p_head,uint32_t size,void *p_save) { @@ -21,15 +32,17 @@ void save_register(void *p_head,uint32_t size,void *p_save) void load_register(void *p_head,uint32_t size,void *p_load) { - uint32_t tmp; memcpy(p_head,p_load,size); - + +#ifdef ES_PMU_SAVE_LOAD_UART + if((p_head == UART0) || (p_head == UART1) || (p_head == UART2) || (p_head == UART3) || (p_head == UART4) || (p_head == UART5) ) { - tmp = ((UART_TypeDef*)p_load)->IVS; - ((UART_TypeDef*)p_head)->IER = tmp; + ((UART_TypeDef*)p_head)->IER = ((UART_TypeDef*)p_load)->IVS; } +#endif + } static void uart_console_reconfig(void) @@ -39,36 +52,14 @@ static void uart_console_reconfig(void) rt_device_control(rt_console_get_device(), RT_DEVICE_CTRL_CONFIG, &config); } -static void delay(void) -{ - long i; - rt_base_t level; - - level = rt_hw_interrupt_disable(); - i = 0; - do{ - i++; - } - while (i < 4000000); - - rt_hw_interrupt_enable(level); -} - /** * This function will put ES32F369x into sleep mode. * * @param pm pointer to power manage structure */ -struct pm_callback_t -{ - volatile int in_fun_times; /*进入函数的次数*/ - volatile char flag; /*标志*/ - volatile int mode; /*需要打印的模式*/ -}; - -extern volatile struct pm_callback_t g_pm_data; +/* 注意：进入睡眠前，如果有中断挂起（SYSTICK、PENDSV、UART、EXTI等），睡眠将被瞬间唤醒。*/ static void sleep(struct rt_pm *pm, uint8_t mode) { @@ -83,26 +74,21 @@ static void sleep(struct rt_pm *pm, uint8_t mode) case PM_SLEEP_MODE_LIGHT: /* Enter SLEEP Mode, Main regulator is ON */ ald_pmu_stop1_enter(); - delay(); - break; case PM_SLEEP_MODE_DEEP: - /* Enter STOP 2 mode */ + /* Enter STOP 2 mode */ ald_pmu_stop2_enter(); - delay(); break; case PM_SLEEP_MODE_STANDBY: - /* Enter STANDBY mode */ + /* Enter STANDBY mode */ ald_pmu_stop2_enter(); - delay(); break; case PM_SLEEP_MODE_SHUTDOWN: - /* Enter SHUTDOWNN mode */ + /* Enter SHUTDOWNN mode */ ald_pmu_stop2_enter(); - delay(); break; default: diff --git a/bsp/essemi/es32f369x/drivers/drv_pm.h b/bsp/essemi/es32f369x/drivers/drv_pm.h index 56de29eef5..874f86ed08 100644 --- a/bsp/essemi/es32f369x/drivers/drv_pm.h +++ b/bsp/essemi/es32f369x/drivers/drv_pm.h @@ -3,9 +3,22 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes - * 2019-04-01 wangyq the first version + * 2019-04-01 wangyq the first version + * 2021-04-20 liuhy the second version */ #ifndef DRV_PM_H__ @@ -14,9 +27,8 @@ #include #include #include -#include -#include -#include "shell.h" +#include "es_conf_info_pm.h" +#include int rt_hw_pm_init(void); diff --git a/bsp/essemi/es32f369x/drivers/drv_pwm.c b/bsp/essemi/es32f369x/drivers/drv_pwm.c index e033e47cec..b61e363633 100644 --- a/bsp/essemi/es32f369x/drivers/drv_pwm.c +++ b/bsp/essemi/es32f369x/drivers/drv_pwm.c @@ -3,28 +3,33 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes * 2019-03-11 wangyq the first version - * 2019-11-01 wangyq update libraries + * 2019-11-01 wangyq update libraries + * 2021-04-20 liuhy the second version */ #include #include #include #include -#include -#include -#include +#include "es_conf_info_pwm.h" -static void pwm_set_freq(timer_handle_t *timer_initstruct, uint32_t ns) -{ - uint64_t _arr = (uint64_t)ald_cmu_get_pclk1_clock() * ns / 1000000000 / - (timer_initstruct->init.prescaler + 1); - WRITE_REG(timer_initstruct->perh->AR, (uint32_t)_arr); - timer_initstruct->init.period = (uint32_t)_arr; -} +#ifdef RT_USING_PWM static void pwm_set_duty(timer_handle_t *timer_initstruct, timer_channel_t ch, uint32_t ns) { @@ -44,37 +49,40 @@ static void pwm_set_duty(timer_handle_t *timer_initstruct, timer_channel_t ch, u static rt_err_t es32f3_pwm_control(struct rt_device_pwm *device, int cmd, void *arg) { rt_err_t ret = RT_EOK; - uint32_t _ccep; + uint64_t _arr,bus_speed,tmp; + uint32_t _maxcnt,_ccep_ch_en = 0U; timer_channel_t pwm_channel; timer_oc_init_t tim_ocinit; timer_handle_t *timer_initstruct = (timer_handle_t *)device->parent.user_data; struct rt_pwm_configuration *cfg = (struct rt_pwm_configuration *)arg; RT_ASSERT(timer_initstruct != RT_NULL); - - tim_ocinit.oc_mode = TIMER_OC_MODE_PWM1; - tim_ocinit.oc_polarity = TIMER_OC_POLARITY_HIGH; - tim_ocinit.oc_fast_en = DISABLE; - tim_ocinit.ocn_polarity = TIMER_OCN_POLARITY_HIGH; - tim_ocinit.ocn_idle = TIMER_OCN_IDLE_RESET; - tim_ocinit.oc_idle = TIMER_OC_IDLE_RESET; - + + /* select pwm output channel */ if (1 == cfg->channel) + { pwm_channel = TIMER_CHANNEL_1; - - else if (2 == cfg->channel) + _ccep_ch_en = timer_initstruct->perh->CCEP & TIMER_CCEP_CC1EN_MSK; + } + else if (2 == cfg->channel) + { pwm_channel = TIMER_CHANNEL_2; - - else if (3 == cfg->channel) + _ccep_ch_en = timer_initstruct->perh->CCEP & TIMER_CCEP_CC2EN_MSK; + } + else if (3 == cfg->channel) + { pwm_channel = TIMER_CHANNEL_3; - - else if (4 == cfg->channel) + _ccep_ch_en = timer_initstruct->perh->CCEP & TIMER_CCEP_CC3EN_MSK; + } + else if (4 == cfg->channel) + { pwm_channel = TIMER_CHANNEL_4; - + _ccep_ch_en = timer_initstruct->perh->CCEP & TIMER_CCEP_CC4EN_MSK; + } else return RT_EINVAL; - + switch (cmd) { case PWM_CMD_ENABLE: @@ -86,19 +94,53 @@ static rt_err_t es32f3_pwm_control(struct rt_device_pwm *device, int cmd, void * break; case PWM_CMD_SET: - _ccep = timer_initstruct->perh->CCEP; - /* count registers max 0xFFFF, auto adjust prescaler */ + + /*当通道没开的时候：关通道，设置输出模式和极性，初始化通道*/ + if(!_ccep_ch_en) + { + tim_ocinit.oc_mode = ES_PWM_OC_MODE; + tim_ocinit.oc_polarity = ES_PWM_OC_POLARITY; + tim_ocinit.oc_fast_en = DISABLE; + tim_ocinit.ocn_polarity = TIMER_OCN_POLARITY_HIGH; + tim_ocinit.ocn_idle = TIMER_OCN_IDLE_RESET; + tim_ocinit.oc_idle = TIMER_OC_IDLE_RESET; + + ald_timer_oc_config_channel(timer_initstruct, &tim_ocinit, pwm_channel); + } + + bus_speed = (uint64_t)ald_cmu_get_pclk1_clock(); + + /*判断外设的计数器最大值*/ +#ifdef ES32F36xx + if((timer_initstruct->perh == GP32C4T0)||(timer_initstruct->perh == GP32C4T1)) + { + _maxcnt = 0xFFFFFFFF; + } + else _maxcnt = 0xFFFF; +#else + _maxcnt = 0xFFFF; +#endif + + /*当最大分频 <= _maxcnt时：估计大概的分频，加快速度 */ + tmp = bus_speed * (cfg->period)/1000000000/_maxcnt; + timer_initstruct->init.prescaler = (tmp > 2U) ? (tmp - 2U) : 0U ; /*bus_speed < 500000000*/ + + /* count registers max , auto adjust prescaler */ do { - pwm_set_freq(timer_initstruct, cfg->period); - timer_initstruct->init.prescaler ++; + _arr = bus_speed * (cfg->period) / 1000000000 /(++timer_initstruct->init.prescaler); + } - while (timer_initstruct->init.period > 0xFFFF); + while (_arr > _maxcnt); + + WRITE_REG(timer_initstruct->perh->AR, (uint32_t)_arr); + timer_initstruct->init.period = (uint32_t)_arr; + /* update prescaler */ WRITE_REG(timer_initstruct->perh->PRES, --timer_initstruct->init.prescaler); - ald_timer_oc_config_channel(timer_initstruct, &tim_ocinit, pwm_channel); + pwm_set_duty(timer_initstruct, pwm_channel, cfg->pulse); - timer_initstruct->perh->CCEP = _ccep; + break; case PWM_CMD_GET: @@ -130,42 +172,210 @@ int rt_hw_pwm_init(void) gpio_initstructure.flt = GPIO_FILTER_DISABLE; gpio_initstructure.type = GPIO_TYPE_TTL; -#ifdef BSP_USING_PWM0 /* 4 channels */ - static struct rt_device_pwm pwm_dev0; - static timer_handle_t timer_initstruct0; +#ifdef BSP_USING_AD16C4T0_PWM /* 4 channels */ + static struct rt_device_pwm ad16c4t0_pwm_dev; + static timer_handle_t ad16c4t0_timer_initstruct; - timer_initstruct0.perh = GP16C4T0; - ald_timer_pwm_init(&timer_initstruct0); + ad16c4t0_timer_initstruct.perh = AD16C4T0; + ald_timer_pwm_init(&ad16c4t0_timer_initstruct); /* gpio initialization */ - gpio_initstructure.func = GPIO_FUNC_2; - ald_gpio_init(GPIOB, GPIO_PIN_6, &gpio_initstructure); - ald_gpio_init(GPIOB, GPIO_PIN_7, &gpio_initstructure); - ald_gpio_init(GPIOB, GPIO_PIN_8, &gpio_initstructure); - ald_gpio_init(GPIOB, GPIO_PIN_9, &gpio_initstructure); - ret = rt_device_pwm_register(&pwm_dev0, "pwm0", &es32f3_pwm_ops, - &timer_initstruct0); +#if defined(ES_AD16C4T0_CH1_GPIO_FUNC)&&defined(ES_AD16C4T0_CH1_GPIO_PORT)&&defined(ES_AD16C4T0_CH1_GPIO_PIN) + gpio_initstructure.func = ES_AD16C4T0_CH1_GPIO_FUNC; + ald_gpio_init(ES_AD16C4T0_CH1_GPIO_PORT, ES_AD16C4T0_CH1_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_AD16C4T0_CH2_GPIO_FUNC)&&defined(ES_AD16C4T0_CH2_GPIO_PORT)&&defined(ES_AD16C4T0_CH2_GPIO_PIN) + gpio_initstructure.func = ES_AD16C4T0_CH2_GPIO_FUNC; + ald_gpio_init(ES_AD16C4T0_CH2_GPIO_PORT, ES_AD16C4T0_CH2_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_AD16C4T0_CH3_GPIO_FUNC)&&defined(ES_AD16C4T0_CH3_GPIO_PORT)&&defined(ES_AD16C4T0_CH3_GPIO_FUNC) + gpio_initstructure.func = ES_AD16C4T0_CH3_GPIO_FUNC; + ald_gpio_init(ES_AD16C4T0_CH3_GPIO_PORT, ES_AD16C4T0_CH3_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_AD16C4T0_CH4_GPIO_FUNC)&&defined(ES_AD16C4T0_CH4_GPIO_PORT)&&defined(ES_AD16C4T0_CH4_GPIO_PIN) + gpio_initstructure.func = ES_AD16C4T0_CH4_GPIO_FUNC; + ald_gpio_init(ES_AD16C4T0_CH4_GPIO_PORT, ES_AD16C4T0_CH4_GPIO_PIN, &gpio_initstructure); +#endif + + ret = rt_device_pwm_register(&ad16c4t0_pwm_dev, ES_DEVICE_NAME_AD16C4T0_PWM, &es32f3_pwm_ops, + &ad16c4t0_timer_initstruct); #endif -#ifdef BSP_USING_PWM1 /* 4 channels */ - static struct rt_device_pwm pwm_dev1; - static timer_handle_t timer_initstruct1; +#ifdef BSP_USING_AD16C4T1_PWM /* 4 channels */ + static struct rt_device_pwm ad16c4t1_pwm_dev; + static timer_handle_t ad16c4t1_timer_initstruct; - timer_initstruct1.perh = GP16C4T1; - ald_timer_pwm_init(&timer_initstruct1); + ad16c4t1_timer_initstruct.perh = AD16C4T1; + ald_timer_pwm_init(&ad16c4t1_timer_initstruct); /* gpio initialization */ - gpio_initstructure.func = GPIO_FUNC_5; - ald_gpio_init(GPIOA, GPIO_PIN_0, &gpio_initstructure); - ald_gpio_init(GPIOA, GPIO_PIN_1, &gpio_initstructure); - ald_gpio_init(GPIOA, GPIO_PIN_2, &gpio_initstructure); - ald_gpio_init(GPIOA, GPIO_PIN_3, &gpio_initstructure); + +#if defined(ES_AD16C4T1_CH1_GPIO_FUNC)&&defined(ES_AD16C4T1_CH1_GPIO_PORT)&&defined(ES_AD16C4T1_CH1_GPIO_PIN) + gpio_initstructure.func = ES_AD16C4T1_CH1_GPIO_FUNC; + ald_gpio_init(ES_AD16C4T1_CH1_GPIO_PORT, ES_AD16C4T1_CH1_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_AD16C4T1_CH2_GPIO_FUNC)&&defined(ES_AD16C4T1_CH2_GPIO_PORT)&&defined(ES_AD16C4T1_CH2_GPIO_PIN) + gpio_initstructure.func = ES_AD16C4T1_CH2_GPIO_FUNC; + ald_gpio_init(ES_AD16C4T1_CH2_GPIO_PORT, ES_AD16C4T1_CH2_GPIO_PIN, &gpio_initstructure); +#endif - ret = rt_device_pwm_register(&pwm_dev1, "pwm1", &es32f3_pwm_ops, - &timer_initstruct1); +#if defined(ES_AD16C4T1_CH3_GPIO_FUNC)&&defined(ES_AD16C4T1_CH3_GPIO_PORT)&&defined(ES_AD16C4T1_CH3_GPIO_PIN) + gpio_initstructure.func = ES_AD16C4T1_CH3_GPIO_FUNC; + ald_gpio_init(ES_AD16C4T1_CH3_GPIO_PORT, ES_AD16C4T1_CH3_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_AD16C4T1_CH4_GPIO_FUNC)&&defined(ES_AD16C4T1_CH4_GPIO_PORT)&&defined(ES_AD16C4T1_CH4_GPIO_PIN) + gpio_initstructure.func = ES_AD16C4T1_CH4_GPIO_FUNC; + ald_gpio_init(ES_AD16C4T1_CH4_GPIO_PORT, ES_AD16C4T1_CH4_GPIO_PIN, &gpio_initstructure); +#endif + + ret = rt_device_pwm_register(&ad16c4t1_pwm_dev, ES_DEVICE_NAME_AD16C4T1_PWM, &es32f3_pwm_ops, + &ad16c4t1_timer_initstruct); +#endif + + +#ifdef BSP_USING_GP32C4T0_PWM /* 4 channels */ + static struct rt_device_pwm gp32c4t0_pwm_dev; + static timer_handle_t gp32c4t0_timer_initstruct; + + gp32c4t0_timer_initstruct.perh = GP32C4T0; + ald_timer_pwm_init(&gp32c4t0_timer_initstruct); + + /* gpio initialization */ + +#if defined(ES_GP32C4T0_CH1_GPIO_FUNC)&&defined(ES_GP32C4T0_CH1_GPIO_PORT)&&defined(ES_GP32C4T0_CH1_GPIO_PIN) + gpio_initstructure.func = ES_GP32C4T0_CH1_GPIO_FUNC; + ald_gpio_init(ES_GP32C4T0_CH1_GPIO_PORT, ES_GP32C4T0_CH1_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP32C4T0_CH2_GPIO_FUNC)&&defined(ES_GP32C4T0_CH2_GPIO_PORT)&&defined(ES_GP32C4T0_CH2_GPIO_PIN) + gpio_initstructure.func = ES_GP32C4T0_CH2_GPIO_FUNC; + ald_gpio_init(ES_GP32C4T0_CH2_GPIO_PORT, ES_GP32C4T0_CH2_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP32C4T0_CH3_GPIO_FUNC)&&defined(ES_GP32C4T0_CH3_GPIO_PORT)&&defined(ES_GP32C4T0_CH3_GPIO_PIN) + gpio_initstructure.func = ES_GP32C4T0_CH3_GPIO_FUNC; + ald_gpio_init(ES_GP32C4T0_CH3_GPIO_PORT, ES_GP32C4T0_CH3_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP32C4T0_CH4_GPIO_FUNC)&&defined(ES_GP32C4T0_CH4_GPIO_PORT)&&defined(ES_GP32C4T0_CH4_GPIO_PIN) + gpio_initstructure.func = ES_GP32C4T0_CH4_GPIO_FUNC; + ald_gpio_init(ES_GP32C4T0_CH4_GPIO_PORT, ES_GP32C4T0_CH4_GPIO_PIN, &gpio_initstructure); +#endif + + ret = rt_device_pwm_register(&gp32c4t0_pwm_dev, ES_DEVICE_NAME_AD16C4T1_PWM, &es32f3_pwm_ops, + &gp32c4t0_timer_initstruct); +#endif + + +#ifdef BSP_USING_GP32C4T1_PWM /* 4 channels */ + static struct rt_device_pwm gp32c4t1_pwm_dev; + static timer_handle_t gp32c4t1_timer_initstruct; + + gp32c4t1_timer_initstruct.perh = GP32C4T1; + ald_timer_pwm_init(&gp32c4t1_timer_initstruct); + + /* gpio initialization */ + +#if defined(ES_GP32C4T1_CH1_GPIO_FUNC)&&defined(ES_GP32C4T1_CH1_GPIO_PORT)&&defined(ES_GP32C4T1_CH1_GPIO_PIN) + gpio_initstructure.func = ES_GP32C4T1_CH1_GPIO_FUNC; + ald_gpio_init(ES_GP32C4T1_CH1_GPIO_PORT, ES_GP32C4T1_CH1_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP32C4T1_CH2_GPIO_FUNC)&&defined(ES_GP32C4T1_CH2_GPIO_PORT)&&defined(ES_GP32C4T1_CH2_GPIO_PIN) + gpio_initstructure.func = ES_GP32C4T1_CH2_GPIO_FUNC; + ald_gpio_init(ES_GP32C4T1_CH2_GPIO_PORT, ES_GP32C4T1_CH2_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP32C4T1_CH3_GPIO_FUNC)&&defined(ES_GP32C4T1_CH3_GPIO_PORT)&&defined(ES_GP32C4T1_CH3_GPIO_PIN) + gpio_initstructure.func = ES_GP32C4T1_CH3_GPIO_FUNC; + ald_gpio_init(ES_GP32C4T1_CH3_GPIO_PORT, ES_GP32C4T1_CH3_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP32C4T1_CH4_GPIO_FUNC)&&defined(ES_GP32C4T1_CH4_GPIO_PORT)&&defined(ES_GP32C4T1_CH4_GPIO_PIN) + gpio_initstructure.func = ES_GP32C4T1_CH4_GPIO_FUNC; + ald_gpio_init(ES_GP32C4T1_CH4_GPIO_PORT, ES_GP32C4T1_CH4_GPIO_PIN, &gpio_initstructure); +#endif + + ret = rt_device_pwm_register(&gp32c4t1_pwm_dev, ES_DEVICE_NAME_GP32C4T1_PWM, &es32f3_pwm_ops, + &gp32c4t1_timer_initstruct); +#endif + + +#ifdef BSP_USING_GP16C4T0_PWM /* 4 channels */ + static struct rt_device_pwm gp16c4t0_pwm_dev; + static timer_handle_t gp16c4t0_timer_initstruct; + + gp16c4t0_timer_initstruct.perh = GP16C4T0; + ald_timer_pwm_init(&gp16c4t0_timer_initstruct); + + /* gpio initialization */ + +#if defined(ES_GP16C4T0_CH1_GPIO_FUNC)&&defined(ES_GP16C4T0_CH1_GPIO_PORT)&&defined(ES_GP16C4T0_CH1_GPIO_PIN) + gpio_initstructure.func = ES_GP16C4T0_CH1_GPIO_FUNC; + ald_gpio_init(ES_GP16C4T0_CH1_GPIO_PORT, ES_GP16C4T0_CH1_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP16C4T0_CH2_GPIO_FUNC)&&defined(ES_GP16C4T0_CH2_GPIO_PORT)&&defined(ES_GP16C4T0_CH2_GPIO_PIN) + gpio_initstructure.func = ES_GP16C4T0_CH2_GPIO_FUNC; + ald_gpio_init(ES_GP16C4T0_CH2_GPIO_PORT, ES_GP16C4T0_CH2_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP16C4T0_CH3_GPIO_FUNC)&&defined(ES_GP16C4T0_CH3_GPIO_PORT)&&defined(ES_GP16C4T0_CH3_GPIO_PIN) + gpio_initstructure.func = ES_GP16C4T0_CH3_GPIO_FUNC; + ald_gpio_init(ES_GP16C4T0_CH3_GPIO_PORT, ES_GP16C4T0_CH3_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP16C4T0_CH4_GPIO_FUNC)&&defined(ES_GP16C4T0_CH4_GPIO_PORT)&&defined(ES_GP16C4T0_CH4_GPIO_PIN) + gpio_initstructure.func = ES_GP16C4T0_CH4_GPIO_FUNC; + ald_gpio_init(ES_GP16C4T0_CH4_GPIO_PORT, ES_GP16C4T0_CH4_GPIO_PIN, &gpio_initstructure); +#endif + + ret = rt_device_pwm_register(&gp16c4t0_pwm_dev, ES_DEVICE_NAME_GP16C4T0_PWM, &es32f3_pwm_ops, + &gp16c4t0_timer_initstruct); +#endif + + +#ifdef BSP_USING_GP16C4T1_PWM /* 4 channels */ + static struct rt_device_pwm gp16c4t1_pwm_dev; + static timer_handle_t gp16c4t1_timer_initstruct; + + gp16c4t1_timer_initstruct.perh = GP16C4T1; + ald_timer_pwm_init(&gp16c4t1_timer_initstruct); + + /* gpio initialization */ + +#if defined(ES_GP16C4T1_CH1_GPIO_FUNC)&&defined(ES_GP16C4T1_CH1_GPIO_PORT)&&defined(ES_GP16C4T1_CH1_GPIO_PIN) + gpio_initstructure.func = ES_GP16C4T1_CH1_GPIO_FUNC; + ald_gpio_init(ES_GP16C4T1_CH1_GPIO_PORT, ES_GP16C4T1_CH1_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP16C4T1_CH2_GPIO_FUNC)&&defined(ES_GP16C4T1_CH2_GPIO_PORT)&&defined(ES_GP16C4T1_CH2_GPIO_PIN) + gpio_initstructure.func = ES_GP16C4T1_CH2_GPIO_FUNC; + ald_gpio_init(ES_GP16C4T1_CH2_GPIO_PORT, ES_GP16C4T1_CH2_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP16C4T1_CH3_GPIO_FUNC)&&defined(ES_GP16C4T1_CH3_GPIO_PORT)&&defined(ES_GP16C4T1_CH3_GPIO_PIN) + gpio_initstructure.func = ES_GP16C4T1_CH3_GPIO_FUNC; + ald_gpio_init(ES_GP16C4T1_CH3_GPIO_PORT, ES_GP16C4T1_CH3_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP16C4T1_CH4_GPIO_FUNC)&&defined(ES_GP16C4T1_CH4_GPIO_PORT)&&defined(ES_GP16C4T1_CH4_GPIO_PIN) + gpio_initstructure.func = ES_GP16C4T1_CH4_GPIO_FUNC; + ald_gpio_init(ES_GP16C4T1_CH4_GPIO_PORT, ES_GP16C4T1_CH4_GPIO_PIN, &gpio_initstructure); +#endif + + ret = rt_device_pwm_register(&gp16c4t1_pwm_dev, ES_DEVICE_NAME_GP16C4T1_PWM, &es32f3_pwm_ops, + &gp16c4t1_timer_initstruct); #endif return ret; } INIT_DEVICE_EXPORT(rt_hw_pwm_init); + +#endif diff --git a/bsp/essemi/es32f369x/drivers/drv_rtc.c b/bsp/essemi/es32f369x/drivers/drv_rtc.c index cab5b8b61b..13b0fc9a24 100644 --- a/bsp/essemi/es32f369x/drivers/drv_rtc.c +++ b/bsp/essemi/es32f369x/drivers/drv_rtc.c @@ -3,21 +3,32 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes * 2019-03-22 wangyq the first version - * 2019-11-01 wangyq update libraries + * 2019-11-01 wangyq update libraries + * 2021-04-20 liuhy the second version */ #include #include -#include +#include #include #include #include "board.h" -#include "drv_rtc.h" -#include -#include +#include "drv_rtc.h" #ifdef RT_USING_RTC @@ -117,20 +128,28 @@ int rt_hw_rtc_init(void) rt_err_t ret = RT_EOK; static struct rt_device rtc_dev; rtc_init_t rtc_initstruct; + + /* enable clk */ + ald_rtc_source_select(ES_RTC_CLK_SOURCE); - /* enable external 32.768kHz */ - CMU_LOSC_ENABLE(); - ald_cmu_losc_safe_config(ENABLE); + if(ES_RTC_CLK_SOURCE == ES_C_RTC_SOURCE_LOSC) + { + CMU_LOSC_ENABLE(); + ald_cmu_losc_safe_config(ENABLE); + } + /* set default time */ RTC_UNLOCK(); WRITE_REG(RTC->TIME, 0x134251); WRITE_REG(RTC->DATE, 0x1190401); RTC_LOCK(); + /* RTC function initialization */ rtc_initstruct.hour_format = RTC_HOUR_FORMAT_24; rtc_initstruct.asynch_pre_div = 0; rtc_initstruct.synch_pre_div = 32767; - rtc_initstruct.output = RTC_OUTPUT_DISABLE; + rtc_initstruct.output = RTC_OUTPUT_DISABLE; + rtc_initstruct.output_polarity = RTC_OUTPUT_POLARITY_HIGH; __rtc_init(&rtc_initstruct); rtc_dev.type = RT_Device_Class_RTC; @@ -150,7 +169,7 @@ int rt_hw_rtc_init(void) rtc_dev.user_data = RTC; - ret = rt_device_register(&rtc_dev, "rtc", RT_DEVICE_FLAG_RDWR); + ret = rt_device_register(&rtc_dev, ES_DEVICE_NAME_RTC, RT_DEVICE_FLAG_RDWR); return ret; } diff --git a/bsp/essemi/es32f369x/drivers/drv_rtc.h b/bsp/essemi/es32f369x/drivers/drv_rtc.h index fe0264fb51..76e5b24d85 100644 --- a/bsp/essemi/es32f369x/drivers/drv_rtc.h +++ b/bsp/essemi/es32f369x/drivers/drv_rtc.h @@ -3,14 +3,28 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes - * 2019-03-22 wangyq the first version + * 2019-03-22 wangyq the first version + * 2021-04-20 liuhy the second version */ #ifndef DRV_RTC_H__ #define DRV_RTC_H__ +#include "es_conf_info_rtc.h" int rt_hw_rtc_init(void); #endif diff --git a/bsp/essemi/es32f369x/drivers/drv_spi.c b/bsp/essemi/es32f369x/drivers/drv_spi.c index 9bf7e4e4b5..aae178f78e 100644 --- a/bsp/essemi/es32f369x/drivers/drv_spi.c +++ b/bsp/essemi/es32f369x/drivers/drv_spi.c @@ -3,10 +3,23 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: - * Date Author Notes - * 2020-01-14 wangyq the first version - * 2019-11-01 wangyq update libraries + * Date Author Notes + * 2019-11-01 wangyq update libraries + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version */ #include @@ -15,9 +28,7 @@ #include #include "board.h" #include "drv_spi.h" -#include -#include -#include + #ifdef RT_USING_SPI @@ -31,6 +42,7 @@ rt_err_t spi_configure(struct rt_spi_device *device, hspi->init.ss_en = DISABLE; hspi->init.crc_calc = DISABLE; + hspi->init.frame = SPI_FRAME_MOTOROLA; /* config spi mode */ if (cfg->mode & RT_SPI_SLAVE) @@ -163,73 +175,54 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message * hspi = (spi_handle_t *)device->bus->parent.user_data; cs = device->parent.user_data; + if (message->cs_take) + { + rt_pin_write(cs->pin, ES_SPI_CS_LEVEL); + } + if(message->send_buf != RT_NULL || message->recv_buf != RT_NULL) { /* send & receive */ if ((message->send_buf != RT_NULL) && (message->recv_buf != RT_NULL)) { - if (message->cs_take) - { - rt_pin_write(cs->pin, 0); - } res = ald_spi_send_recv(hspi, (rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, SPITIMEOUT); - if (message->cs_release) - { - rt_pin_write(cs->pin, 1); - } - if (res != RT_EOK) - return RT_ERROR; } else { /* only send data */ if (message->recv_buf == RT_NULL) { - if (message->cs_take) - { - rt_pin_write(cs->pin, 0); - } res = ald_spi_send(hspi, (rt_uint8_t *)message->send_buf, (rt_int32_t)message->length, SPITIMEOUT); - if (message->cs_release) - { - rt_pin_write(cs->pin, 1); - } - if (res != RT_EOK) - return RT_ERROR; } /* only receive data */ if (message->send_buf == RT_NULL) { - if (message->cs_take) - { - rt_pin_write(cs->pin, 0); - } res = ald_spi_recv(hspi, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, SPITIMEOUT); - if (message->cs_release) - { - rt_pin_write(cs->pin, 1); - } - if (res != RT_EOK) - return RT_ERROR; } } - + + if (message->cs_release) + { + rt_pin_write(cs->pin, !ES_SPI_CS_LEVEL); + } + + if (res != RT_EOK) + return RT_ERROR; + else + return message->length; + } else { - if (message->cs_take) - { - rt_pin_write(cs->pin, 0); - } - + if (message->cs_release) { - rt_pin_write(cs->pin, 1); + rt_pin_write(cs->pin, !ES_SPI_CS_LEVEL); } return RT_EOK; } - return message->length; + } const struct rt_spi_ops es32f3_spi_ops = @@ -240,6 +233,7 @@ const struct rt_spi_ops es32f3_spi_ops = rt_err_t es32f3_spi_device_attach(rt_uint32_t pin, const char *bus_name, const char *device_name) { + int result; /* define spi Instance */ struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); RT_ASSERT(spi_device != RT_NULL); @@ -248,7 +242,20 @@ rt_err_t es32f3_spi_device_attach(rt_uint32_t pin, const char *bus_name, const c cs_pin->pin = pin; rt_pin_mode(pin, PIN_MODE_OUTPUT); rt_pin_write(pin, 1); - return rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); + + result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); + +#ifdef BSP_USING_SPI0 + if(!(strcmp(bus_name,ES_DEVICE_NAME_SPI0_BUS)))SPI_BUS_CONFIG(spi_device->config,0); +#endif +#ifdef BSP_USING_SPI1 + if(!(strcmp(bus_name,ES_DEVICE_NAME_SPI1_BUS)))SPI_BUS_CONFIG(spi_device->config,1); +#endif +#ifdef BSP_USING_SPI2 + if(!(strcmp(bus_name,ES_DEVICE_NAME_SPI2_BUS)))SPI_BUS_CONFIG(spi_device->config,2); +#endif + + return result; } #ifdef BSP_USING_SPI0 @@ -273,40 +280,47 @@ int rt_hw_spi_init(void) struct rt_spi_bus *spi_bus; spi_handle_t *spi; gpio_init_t gpio_instruct; - + + gpio_instruct.pupd = GPIO_PUSH_UP_DOWN; + gpio_instruct.odos = GPIO_PUSH_PULL; + gpio_instruct.podrv = GPIO_OUT_DRIVE_1; + gpio_instruct.nodrv = GPIO_OUT_DRIVE_1; + gpio_instruct.type = GPIO_TYPE_TTL; + gpio_instruct.flt = GPIO_FILTER_DISABLE; + #ifdef BSP_USING_SPI0 _spi0.perh = SPI0; spi_bus = &_spi_bus0; spi = &_spi0; - rt_device_t spi_bus_dev0; /* SPI0 gpio init */ gpio_instruct.mode = GPIO_MODE_OUTPUT; - gpio_instruct.odos = GPIO_PUSH_PULL; - gpio_instruct.podrv = GPIO_OUT_DRIVE_1; - gpio_instruct.nodrv = GPIO_OUT_DRIVE_1; - gpio_instruct.func = GPIO_FUNC_4; - gpio_instruct.type = GPIO_TYPE_TTL; - gpio_instruct.flt = GPIO_FILTER_DISABLE; - /* PB3->SPI0_SCK, PB5->SPI0_MOSI */ - ald_gpio_init(GPIOB, GPIO_PIN_3 | GPIO_PIN_5, &gpio_instruct); +#if defined(ES_SPI0_SCK_GPIO_FUNC)&&defined(ES_SPI0_SCK_GPIO_PORT)&&defined(ES_SPI0_SCK_GPIO_PIN) + gpio_instruct.func = ES_SPI0_SCK_GPIO_FUNC; + ald_gpio_init(ES_SPI0_SCK_GPIO_PORT, ES_SPI0_SCK_GPIO_PIN, &gpio_instruct); +#endif - /* PB4->SPI0_MISO */ +#if defined(ES_SPI0_MOSI_GPIO_FUNC)&&defined(ES_SPI0_MOSI_GPIO_PORT)&&defined(ES_SPI0_MOSI_GPIO_PIN) + gpio_instruct.func = ES_SPI0_MOSI_GPIO_FUNC; + ald_gpio_init(ES_SPI0_MOSI_GPIO_PORT, ES_SPI0_MOSI_GPIO_PIN, &gpio_instruct); +#endif + gpio_instruct.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOB, GPIO_PIN_4, &gpio_instruct); + +#if defined(ES_SPI0_MISO_GPIO_FUNC)&&defined(ES_SPI0_MISO_GPIO_PORT)&&defined(ES_SPI0_MISO_GPIO_PIN) + gpio_instruct.func = ES_SPI0_MISO_GPIO_FUNC; + ald_gpio_init(ES_SPI0_MISO_GPIO_PORT, ES_SPI0_MISO_GPIO_PIN, &gpio_instruct); +#endif spi_bus->parent.user_data = spi; - result = rt_spi_bus_register(spi_bus, "spi0", &es32f3_spi_ops); + result = rt_spi_bus_register(spi_bus, ES_DEVICE_NAME_SPI0_BUS, &es32f3_spi_ops); if (result != RT_EOK) { return result; } - rt_device_register(spi_bus_dev0, "spi00", RT_DEVICE_FLAG_RDWR); - - /* SPI0_NSS = PA15 = PIN 50 */ - result = es32f3_spi_device_attach(50, "spi0", "spi00"); + result = es32f3_spi_device_attach(ES_SPI0_NSS_PIN, ES_DEVICE_NAME_SPI0_BUS, ES_DEVICE_NAME_SPI0_DEV0); if (result != RT_EOK) { @@ -319,35 +333,35 @@ int rt_hw_spi_init(void) _spi1.perh = SPI1; spi_bus = &_spi_bus1; spi = &_spi1; - rt_device_t spi_bus_dev0; /* SPI1 gpio init */ gpio_instruct.mode = GPIO_MODE_OUTPUT; - gpio_instruct.odos = GPIO_PUSH_PULL; - gpio_instruct.podrv = GPIO_OUT_DRIVE_1; - gpio_instruct.nodrv = GPIO_OUT_DRIVE_1; - gpio_instruct.func = GPIO_FUNC_4; - gpio_instruct.type = GPIO_TYPE_TTL; - gpio_instruct.flt = GPIO_FILTER_DISABLE; - - /* PC01->SPI1_SCK, PC03->SPI1_MOSI */ - ald_gpio_init(GPIOC, GPIO_PIN_1 | GPIO_PIN_3, &gpio_instruct); - - /* PC02->SPI1_MISO */ + +#if defined(ES_SPI1_SCK_GPIO_FUNC)&&defined(ES_SPI1_SCK_GPIO_PORT)&&defined(ES_SPI1_SCK_GPIO_PIN) + gpio_instruct.func = ES_SPI1_SCK_GPIO_FUNC; + ald_gpio_init(ES_SPI1_SCK_GPIO_PORT, ES_SPI1_SCK_GPIO_PIN, &gpio_instruct); +#endif + +#if defined(ES_SPI1_MOSI_GPIO_FUNC)&&defined(ES_SPI1_MOSI_GPIO_PORT)&&defined(ES_SPI1_MOSI_GPIO_PIN) + gpio_instruct.func = ES_SPI1_MOSI_GPIO_FUNC; + ald_gpio_init(ES_SPI1_MOSI_GPIO_PORT, ES_SPI1_MOSI_GPIO_PIN, &gpio_instruct); +#endif + gpio_instruct.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOC, GPIO_PIN_2, &gpio_instruct); + +#if defined(ES_SPI1_MISO_GPIO_FUNC)&&defined(ES_SPI1_MISO_GPIO_PORT)&&defined(ES_SPI1_MISO_GPIO_PIN) + gpio_instruct.func = ES_SPI1_MISO_GPIO_FUNC; + ald_gpio_init(ES_SPI1_MISO_GPIO_PORT, ES_SPI1_MISO_GPIO_PIN, &gpio_instruct); +#endif spi_bus->parent.user_data = spi; - result = rt_spi_bus_register(spi_bus, "spi1", &es32f3_spi_ops); + result = rt_spi_bus_register(spi_bus, ES_DEVICE_NAME_SPI1_BUS, &es32f3_spi_ops); if (result != RT_EOK) { return result; } - rt_device_register(spi_bus_dev0, "spi10", RT_DEVICE_FLAG_RDWR); - - /* SPI1_NSS = PC00 = PIN 8 */ - result = es32f3_spi_device_attach(8, "spi1", "spi10"); + result = es32f3_spi_device_attach(ES_SPI1_NSS_PIN, ES_DEVICE_NAME_SPI1_BUS, ES_DEVICE_NAME_SPI1_DEV0); if (result != RT_EOK) { @@ -357,38 +371,38 @@ int rt_hw_spi_init(void) #endif #ifdef BSP_USING_SPI2 - _spi1.perh = SPI2; + _spi2.perh = SPI2; spi_bus = &_spi_bus2; spi = &_spi2; - rt_device_t spi_bus_dev0; /* SPI2 gpio init */ gpio_instruct.mode = GPIO_MODE_OUTPUT; - gpio_instruct.odos = GPIO_PUSH_PULL; - gpio_instruct.podrv = GPIO_OUT_DRIVE_1; - gpio_instruct.nodrv = GPIO_OUT_DRIVE_1; - gpio_instruct.func = GPIO_FUNC_5; - gpio_instruct.type = GPIO_TYPE_TTL; - gpio_instruct.flt = GPIO_FILTER_DISABLE; - - /* PC05->SPI1_SCK, PB01->SPI1_MOSI */ - ald_gpio_init(GPIOC, GPIO_PIN_5 | GPIO_PIN_1, &gpio_instruct); - - /* PB00->SPI1_MISO */ + +#if defined(ES_SPI2_SCK_GPIO_FUNC)&&defined(ES_SPI2_SCK_GPIO_PORT)&&defined(ES_SPI2_SCK_GPIO_PIN) + gpio_instruct.func = ES_SPI2_SCK_GPIO_FUNC; + ald_gpio_init(ES_SPI2_SCK_GPIO_PORT, ES_SPI2_SCK_GPIO_PIN, &gpio_instruct); +#endif + +#if defined(ES_SPI2_MOSI_GPIO_FUNC)&&defined(ES_SPI2_MOSI_GPIO_PORT)&&defined(ES_SPI2_MOSI_GPIO_PIN) + gpio_instruct.func = ES_SPI2_MOSI_GPIO_FUNC; + ald_gpio_init(ES_SPI2_MOSI_GPIO_PORT, ES_SPI2_MOSI_GPIO_PIN, &gpio_instruct); +#endif + gpio_instruct.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOB, GPIO_PIN_0, &gpio_instruct); + +#if defined(ES_SPI2_MISO_GPIO_FUNC)&&defined(ES_SPI2_MISO_GPIO_PORT)&&defined(ES_SPI2_MISO_GPIO_PIN) + gpio_instruct.func = ES_SPI2_MISO_GPIO_FUNC; + ald_gpio_init(ES_SPI2_MISO_GPIO_PORT, ES_SPI2_MISO_GPIO_PIN, &gpio_instruct); +#endif spi_bus->parent.user_data = spi; - result = rt_spi_bus_register(spi_bus, "spi2", &es32f3_spi_ops); + result = rt_spi_bus_register(spi_bus, ES_DEVICE_NAME_SPI2_BUS, &es32f3_spi_ops); if (result != RT_EOK) { return result; } - rt_device_register(spi_bus_dev0, "spi20", RT_DEVICE_FLAG_RDWR); - - /* SPI2_NSS = PC04 = PIN 24 */ - result = es32f3_spi_device_attach(39, "spi2", "spi20"); + result = es32f3_spi_device_attach(ES_SPI2_NSS_PIN, ES_DEVICE_NAME_SPI2_BUS, ES_DEVICE_NAME_SPI1_DEV0); if (result != RT_EOK) { diff --git a/bsp/essemi/es32f369x/drivers/drv_spi.h b/bsp/essemi/es32f369x/drivers/drv_spi.h index 832d1a58b1..32eab04cc5 100644 --- a/bsp/essemi/es32f369x/drivers/drv_spi.h +++ b/bsp/essemi/es32f369x/drivers/drv_spi.h @@ -3,9 +3,22 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes - * 2020-01-14 wangyq the first version + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version */ #ifndef DRV_SPI_H__ @@ -14,6 +27,8 @@ #include #include #include + +#include "es_conf_info_spi.h" struct es32f3_hw_spi_cs { diff --git a/bsp/essemi/es32f369x/drivers/drv_spiflash.c b/bsp/essemi/es32f369x/drivers/drv_spiflash.c new file mode 100644 index 0000000000..d8176257d1 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/drv_spiflash.c @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-02-15 wangyq the first version + * 2019-11-01 wangyq update libraries + */ + +#include "board.h" +#include + +#if defined(BSP_USING_SPI_FLASH) + +#include "spi_flash.h" +#include "drv_spiflash.h" +#include "spi_flash_sfud.h" +#include "drv_spi.h" + +int rt_hw_spi_flash_init(void) +{ + + if (RT_NULL == rt_sfud_flash_probe(ES_DEVICE_NAME_SPI_FALSH_DEV, ES_DEVICE_NAME_SPI_DEV)) + { + return -RT_ERROR; + }; + + return RT_EOK; +} +INIT_COMPONENT_EXPORT(rt_hw_spi_flash_init); + +#endif diff --git a/bsp/essemi/es32f369x/drivers/drv_spiflash.h b/bsp/essemi/es32f369x/drivers/drv_spiflash.h new file mode 100644 index 0000000000..6ef31852bb --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/drv_spiflash.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-02-15 wangyq the first version + * 2021-04-20 liuhy the second version + */ + +#ifndef DRV_NOR_FLASH_H__ +#define DRV_NOR_FLASH_H__ + +#include "es_conf_info_spi.h" + +int rt_hw_spi_flash_init(void); + +#endif diff --git a/bsp/essemi/es32f369x/drivers/drv_uart.c b/bsp/essemi/es32f369x/drivers/drv_uart.c index b6a8b7a453..5ca5085c54 100644 --- a/bsp/essemi/es32f369x/drivers/drv_uart.c +++ b/bsp/essemi/es32f369x/drivers/drv_uart.c @@ -3,19 +3,29 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes - * 2020-01-14 wangyq the first version + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version */ #include #include #include #include "board.h" -#include "drv_uart.h" -#include -#include -#include +#include "es_conf_info_uart.h" #ifdef RT_USING_SERIAL @@ -26,183 +36,6 @@ struct es32_uart IRQn_Type irq; }; -static rt_err_t es32f3x_configure(struct rt_serial_device *serial, struct serial_configure *cfg) -{ - gpio_init_t gpio_initstructure; - struct es32_uart *uart; - RT_ASSERT(serial != RT_NULL); - RT_ASSERT(cfg != RT_NULL); - uart = (struct es32_uart *)serial->parent.user_data; - - /* Initialize tx pin */ - gpio_initstructure.mode = GPIO_MODE_OUTPUT; - gpio_initstructure.odos = GPIO_PUSH_PULL; - gpio_initstructure.pupd = GPIO_PUSH_UP; - gpio_initstructure.podrv = GPIO_OUT_DRIVE_1; - gpio_initstructure.nodrv = GPIO_OUT_DRIVE_1; - gpio_initstructure.flt = GPIO_FILTER_DISABLE; - gpio_initstructure.type = GPIO_TYPE_TTL; - -#ifdef BSP_USING_UART0 - gpio_initstructure.func = GPIO_FUNC_3; - ald_gpio_init(GPIOB, GPIO_PIN_10, &gpio_initstructure); - - /* Initialize rx pin ,the same as txpin except mode */ - gpio_initstructure.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOB, GPIO_PIN_11, &gpio_initstructure); - - ald_cmu_perh_clock_config(CMU_PERH_UART0, ENABLE); -#endif /* uart0 gpio init */ - -#ifdef BSP_USING_UART1 - gpio_initstructure.func = GPIO_FUNC_3; - ald_gpio_init(GPIOC, GPIO_PIN_10, &gpio_initstructure); - - /* Initialize rx pin ,the same as txpin except mode */ - gpio_initstructure.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOC, GPIO_PIN_11, &gpio_initstructure); - - ald_cmu_perh_clock_config(CMU_PERH_UART1, ENABLE); -#endif /* uart1 gpio init */ - -#ifdef BSP_USING_UART2 - gpio_initstructure.func = GPIO_FUNC_5; - ald_gpio_init(GPIOC, GPIO_PIN_12, &gpio_initstructure); - - /* Initialize rx pin ,the same as txpin except mode */ - gpio_initstructure.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOD, GPIO_PIN_2, &gpio_initstructure); - - ald_cmu_perh_clock_config(CMU_PERH_UART2, ENABLE); -#endif /* uart2 gpio init */ - -#ifdef BSP_USING_UART3 - gpio_initstructure.func = GPIO_FUNC_4; - ald_gpio_init(GPIOC, GPIO_PIN_4, &gpio_initstructure); - - /* Initialize rx pin ,the same as txpin except mode */ - gpio_initstructure.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOC, GPIO_PIN_5, &gpio_initstructure); - - ald_cmu_perh_clock_config(CMU_PERH_UART3, ENABLE); -#endif /* uart3 gpio init */ - -#ifdef BSP_USING_UART4 - gpio_initstructure.func = GPIO_FUNC_3; - ald_gpio_init(GPIOB, GPIO_PIN_6, &gpio_initstructure); - - /* Initialize rx pin ,the same as txpin except mode */ - gpio_initstructure.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOB, GPIO_PIN_7, &gpio_initstructure); - - ald_cmu_perh_clock_config(CMU_PERH_UART4, ENABLE); -#endif /* uart4 gpio init */ - -#ifdef BSP_USING_UART5 - gpio_initstructure.func = GPIO_FUNC_4; - ald_gpio_init(GPIOB, GPIO_PIN_9, &gpio_initstructure); - - /* Initialize rx pin ,the same as txpin except mode */ - gpio_initstructure.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOB, GPIO_PIN_8, &gpio_initstructure); - - ald_cmu_perh_clock_config(CMU_PERH_UART5, ENABLE); -#endif /* uart5 gpio init */ - - ald_uart_tx_fifo_config(&uart->huart, UART_TXFIFO_EMPTY); - ald_uart_rx_fifo_config(&uart->huart, UART_RXFIFO_1BYTE); - - uart->huart.init.mode = UART_MODE_UART; - uart->huart.init.baud = cfg->baud_rate; - uart->huart.init.word_length = (uart_word_length_t)(8 - cfg->data_bits); - uart->huart.init.parity = (uart_parity_t)(cfg->parity == PARITY_EVEN ? UART_PARITY_EVEN : cfg->parity); - uart->huart.init.fctl = UART_HW_FLOW_CTL_DISABLE; - ald_uart_init(&uart->huart); - - if (cfg->bit_order == BIT_ORDER_MSB) - { - UART_MSB_FIRST_ENABLE(&uart->huart); - } - else - { - UART_MSB_FIRST_DISABLE(&uart->huart); - } - - if (cfg->invert == NRZ_INVERTED) - { - UART_DATA_INV_ENABLE(&uart->huart); - } - else - { - UART_DATA_INV_DISABLE(&uart->huart); - } - - return RT_EOK; -} - -static rt_err_t es32f3x_control(struct rt_serial_device *serial, int cmd, void *arg) -{ - struct es32_uart *uart; - RT_ASSERT(serial != RT_NULL); - - uart = (struct es32_uart *)serial->parent.user_data; - switch (cmd) - { - case RT_DEVICE_CTRL_CLR_INT: - /* disable rx irq */ - NVIC_DisableIRQ(uart->irq); - /* disable interrupt */ - ald_uart_interrupt_config(&uart->huart, UART_IT_RFTH, DISABLE); - break; - - case RT_DEVICE_CTRL_SET_INT: - /* enable rx irq */ - NVIC_EnableIRQ(uart->irq); - /* enable interrupt */ - ald_uart_interrupt_config(&uart->huart, UART_IT_RFTH, ENABLE); - break; - } - - return RT_EOK; -} - -static int es32f3x_putc(struct rt_serial_device *serial, char c) -{ - struct es32_uart *uart; - RT_ASSERT(serial != RT_NULL); - uart = (struct es32_uart *)serial->parent.user_data; - - while (ald_uart_get_status(&uart->huart, UART_STATUS_TFEMPTY) == RESET) - ; - WRITE_REG(uart->huart.perh->TXBUF, c); - - return 1; -} - -static int es32f3x_getc(struct rt_serial_device *serial) -{ - int ch = -1; - struct es32_uart *uart; - - RT_ASSERT(serial != RT_NULL); - uart = (struct es32_uart *)serial->parent.user_data; - - if (ald_uart_get_status(&uart->huart, UART_STATUS_RFTH)) - { - ch = (uint8_t)(uart->huart.perh->RXBUF & 0xFF); - } - - return ch; -} - -static const struct rt_uart_ops es32f3x_uart_ops = -{ - es32f3x_configure, - es32f3x_control, - es32f3x_putc, - es32f3x_getc, -}; - #ifdef BSP_USING_UART0 /* UART0 device driver structure */ struct es32_uart uart0 = @@ -353,18 +186,243 @@ void UART5_Handler(void) } #endif /* BSP_USING_UART5 */ +static rt_err_t es32f3x_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + gpio_init_t gpio_initstructure; + struct es32_uart *uart; + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + uart = (struct es32_uart *)serial->parent.user_data; + + /* Initialize tx pin */ + gpio_initstructure.mode = GPIO_MODE_OUTPUT; + gpio_initstructure.odos = GPIO_PUSH_PULL; + gpio_initstructure.pupd = GPIO_PUSH_UP; + gpio_initstructure.podrv = GPIO_OUT_DRIVE_1; + gpio_initstructure.nodrv = GPIO_OUT_DRIVE_1; + gpio_initstructure.flt = GPIO_FILTER_DISABLE; + gpio_initstructure.type = GPIO_TYPE_TTL; + +#ifdef BSP_USING_UART0 + if(uart == (&uart0)) + { +#if defined(ES_UART0_TX_GPIO_FUNC)&&defined(ES_UART0_TX_GPIO_PORT)&&defined(ES_UART0_TX_GPIO_PIN) + gpio_initstructure.func = ES_UART0_TX_GPIO_FUNC; + ald_gpio_init(ES_UART0_TX_GPIO_PORT, ES_UART0_TX_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_UART0_RX_GPIO_FUNC)&&defined(ES_UART0_RX_GPIO_PORT)&&defined(ES_UART0_RX_GPIO_PIN) + /* Initialize rx pin ,the same as txpin except mode */ + gpio_initstructure.mode = GPIO_MODE_INPUT; + gpio_initstructure.func = ES_UART0_RX_GPIO_FUNC; + ald_gpio_init(ES_UART0_RX_GPIO_PORT, ES_UART0_RX_GPIO_PIN, &gpio_initstructure); +#endif + ald_cmu_perh_clock_config(CMU_PERH_UART0, ENABLE); + } + +#endif /* uart0 gpio init */ + +#ifdef BSP_USING_UART1 + if(uart == (&uart1)) + { +#if defined(ES_UART1_TX_GPIO_FUNC)&&defined(ES_UART1_TX_GPIO_PORT)&&defined(ES_UART1_TX_GPIO_PIN) + gpio_initstructure.func = ES_UART1_TX_GPIO_FUNC; + ald_gpio_init(ES_UART1_TX_GPIO_PORT, ES_UART1_TX_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_UART1_RX_GPIO_FUNC)&&defined(ES_UART1_RX_GPIO_PORT)&&defined(ES_UART1_RX_GPIO_PIN) + /* Initialize rx pin ,the same as txpin except mode */ + gpio_initstructure.mode = GPIO_MODE_INPUT; + gpio_initstructure.func = ES_UART1_RX_GPIO_FUNC; + ald_gpio_init(ES_UART1_RX_GPIO_PORT, ES_UART1_RX_GPIO_PIN, &gpio_initstructure); +#endif + + ald_cmu_perh_clock_config(CMU_PERH_UART1, ENABLE); + } +#endif /* uart1 gpio init */ + +#ifdef BSP_USING_UART2 + if(uart == (&uart2)) + { +#if defined(ES_UART2_TX_GPIO_FUNC)&&defined(ES_UART2_TX_GPIO_PORT)&&defined(ES_UART2_TX_GPIO_PIN) + gpio_initstructure.func = ES_UART2_TX_GPIO_FUNC; + ald_gpio_init(ES_UART2_TX_GPIO_PORT, ES_UART2_TX_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_UART2_RX_GPIO_FUNC)&&defined(ES_UART2_RX_GPIO_PORT)&&defined(ES_UART2_RX_GPIO_PIN) + /* Initialize rx pin ,the same as txpin except mode */ + gpio_initstructure.mode = GPIO_MODE_INPUT; + gpio_initstructure.func = ES_UART2_RX_GPIO_FUNC; + ald_gpio_init(ES_UART2_RX_GPIO_PORT, ES_UART2_RX_GPIO_PIN, &gpio_initstructure); +#endif + + ald_cmu_perh_clock_config(CMU_PERH_UART2, ENABLE); + } +#endif /* uart2 gpio init */ + +#ifdef BSP_USING_UART3 + if(uart == (&uart3)) + { +#if defined(ES_UART3_TX_GPIO_FUNC)&&defined(ES_UART3_TX_GPIO_PORT)&&defined(ES_UART3_TX_GPIO_PIN) + gpio_initstructure.func = ES_UART3_TX_GPIO_FUNC; + ald_gpio_init(ES_UART3_TX_GPIO_PORT, ES_UART3_TX_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_UART3_RX_GPIO_FUNC)&&defined(ES_UART3_RX_GPIO_PORT)&&defined(ES_UART3_RX_GPIO_PIN) + /* Initialize rx pin ,the same as txpin except mode */ + gpio_initstructure.mode = GPIO_MODE_INPUT; + gpio_initstructure.func = ES_UART3_RX_GPIO_FUNC; + ald_gpio_init(ES_UART3_RX_GPIO_PORT, ES_UART3_RX_GPIO_PIN, &gpio_initstructure); +#endif + + ald_cmu_perh_clock_config(CMU_PERH_UART3, ENABLE); + } +#endif /* uart3 gpio init */ + +#ifdef BSP_USING_UART4 + if(uart == (&uart4)) + { +#if defined(ES_UART4_TX_GPIO_FUNC)&&defined(ES_UART4_TX_GPIO_PORT)&&defined(ES_UART4_TX_GPIO_PIN) + gpio_initstructure.func = ES_UART4_TX_GPIO_FUNC; + ald_gpio_init(ES_UART4_TX_GPIO_PORT, ES_UART4_TX_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_UART4_RX_GPIO_FUNC)&&defined(ES_UART4_RX_GPIO_PORT)&&defined(ES_UART4_RX_GPIO_PIN) + /* Initialize rx pin ,the same as txpin except mode */ + gpio_initstructure.mode = GPIO_MODE_INPUT; + gpio_initstructure.func = ES_UART4_RX_GPIO_FUNC; + ald_gpio_init(ES_UART4_RX_GPIO_PORT, ES_UART4_RX_GPIO_PIN, &gpio_initstructure); +#endif + + ald_cmu_perh_clock_config(CMU_PERH_UART4, ENABLE); + } +#endif /* uart4 gpio init */ + +#ifdef BSP_USING_UART5 + if(uart == (&uart5)) + { +#if defined(ES_UART5_TX_GPIO_FUNC)&&defined(ES_UART5_TX_GPIO_PORT)&&defined(ES_UART5_TX_GPIO_PIN) + gpio_initstructure.func = ES_UART5_TX_GPIO_FUNC; + ald_gpio_init(ES_UART5_TX_GPIO_PORT, ES_UART5_TX_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_UART5_RX_GPIO_FUNC)&&defined(ES_UART5_RX_GPIO_PORT)&&defined(ES_UART5_RX_GPIO_PIN) + /* Initialize rx pin ,the same as txpin except mode */ + gpio_initstructure.mode = GPIO_MODE_INPUT; + gpio_initstructure.func = ES_UART5_RX_GPIO_FUNC; + ald_gpio_init(ES_UART5_RX_GPIO_PORT, ES_UART5_RX_GPIO_PIN, &gpio_initstructure); +#endif + + ald_cmu_perh_clock_config(CMU_PERH_UART5, ENABLE); + } +#endif /* uart5 gpio init */ + + ald_uart_tx_fifo_config(&uart->huart, UART_TXFIFO_EMPTY); + ald_uart_rx_fifo_config(&uart->huart, UART_RXFIFO_1BYTE); + + uart->huart.init.mode = UART_MODE_UART; + uart->huart.init.baud = cfg->baud_rate; + uart->huart.init.word_length = (uart_word_length_t)(8 - cfg->data_bits); + uart->huart.init.parity = (uart_parity_t)(cfg->parity == PARITY_EVEN ? UART_PARITY_EVEN : cfg->parity); + uart->huart.init.fctl = UART_HW_FLOW_CTL_DISABLE; + uart->huart.init.stop_bits = UART_STOP_BITS_1; + ald_uart_init(&uart->huart); + + if (cfg->bit_order == BIT_ORDER_MSB) + { + UART_MSB_FIRST_ENABLE(&uart->huart); + } + else + { + UART_MSB_FIRST_DISABLE(&uart->huart); + } + + if (cfg->invert == NRZ_INVERTED) + { + UART_DATA_INV_ENABLE(&uart->huart); + } + else + { + UART_DATA_INV_DISABLE(&uart->huart); + } + + return RT_EOK; +} + +static rt_err_t es32f3x_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct es32_uart *uart; + RT_ASSERT(serial != RT_NULL); + + uart = (struct es32_uart *)serial->parent.user_data; + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + NVIC_DisableIRQ(uart->irq); + /* disable interrupt */ + ald_uart_interrupt_config(&uart->huart, UART_IT_RFTH, DISABLE); + break; + + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + NVIC_EnableIRQ(uart->irq); + /* enable interrupt */ + ald_uart_interrupt_config(&uart->huart, UART_IT_RFTH, ENABLE); + break; + } + + return RT_EOK; +} + +static int es32f3x_putc(struct rt_serial_device *serial, char c) +{ + struct es32_uart *uart; + RT_ASSERT(serial != RT_NULL); + uart = (struct es32_uart *)serial->parent.user_data; + + while (ald_uart_get_status(&uart->huart, UART_STATUS_TFEMPTY) == RESET) + ; + WRITE_REG(uart->huart.perh->TXBUF, c); + + return 1; +} + +static int es32f3x_getc(struct rt_serial_device *serial) +{ + int ch = -1; + struct es32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct es32_uart *)serial->parent.user_data; + + if (ald_uart_get_status(&uart->huart, UART_STATUS_RFTH)) + { + ch = (uint8_t)(uart->huart.perh->RXBUF & 0xFF); + } + + return ch; +} + +static const struct rt_uart_ops es32f3x_uart_ops = +{ + es32f3x_configure, + es32f3x_control, + es32f3x_putc, + es32f3x_getc, +}; + int rt_hw_uart_init(void) { struct es32_uart *uart; - struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; #ifdef BSP_USING_UART0 uart = &uart0; serial0.ops = &es32f3x_uart_ops; - serial0.config = config; + serial0.config = (struct serial_configure)ES_UART0_CONFIG; /* register UART0 device */ - rt_hw_serial_register(&serial0, "uart0", + rt_hw_serial_register(&serial0, ES_DEVICE_NAME_UART0, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); #endif /* BSP_USING_UART0 */ @@ -372,10 +430,10 @@ int rt_hw_uart_init(void) #ifdef BSP_USING_UART1 uart = &uart1; serial1.ops = &es32f3x_uart_ops; - serial1.config = config; + serial1.config = (struct serial_configure)ES_UART1_CONFIG; /* register UART1 device */ - rt_hw_serial_register(&serial1, "uart1", + rt_hw_serial_register(&serial1, ES_DEVICE_NAME_UART1, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); #endif /* BSP_USING_UART1 */ @@ -383,10 +441,10 @@ int rt_hw_uart_init(void) #ifdef BSP_USING_UART2 uart = &uart2; serial2.ops = &es32f3x_uart_ops; - serial2.config = config; + serial2.config = (struct serial_configure)ES_UART2_CONFIG; /* register UART2 device */ - rt_hw_serial_register(&serial2, "uart2", + rt_hw_serial_register(&serial2, ES_DEVICE_NAME_UART2, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); #endif /* BSP_USING_UART2 */ @@ -394,10 +452,10 @@ int rt_hw_uart_init(void) #ifdef BSP_USING_UART3 uart = &uart3; serial3.ops = &es32f3x_uart_ops; - serial3.config = config; + serial3.config = (struct serial_configure)ES_UART3_CONFIG; /* register UART3 device */ - rt_hw_serial_register(&serial3, "uart3", + rt_hw_serial_register(&serial3, ES_DEVICE_NAME_UART3, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); #endif /* BSP_USING_UART3 */ @@ -405,10 +463,10 @@ int rt_hw_uart_init(void) #ifdef BSP_USING_UART4 uart = &uart4; serial4.ops = &es32f3x_uart_ops; - serial4.config = config; + serial4.config = (struct serial_configure)ES_UART4_CONFIG; /* register UART4 device */ - rt_hw_serial_register(&serial4, "uart4", + rt_hw_serial_register(&serial4, ES_DEVICE_NAME_UART4, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); #endif /* BSP_USING_UART4 */ @@ -416,10 +474,10 @@ int rt_hw_uart_init(void) #ifdef BSP_USING_UART5 uart = &uart5; serial5.ops = &es32f3x_uart_ops; - serial5.config = config; + serial5.config = (struct serial_configure)ES_UART5_CONFIG; /* register UART5 device */ - rt_hw_serial_register(&serial5, "uart5", + rt_hw_serial_register(&serial5, ES_DEVICE_NAME_UART5, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); #endif /* BSP_USING_UART5 */ diff --git a/bsp/essemi/es32f369x/drivers/drv_uart.h b/bsp/essemi/es32f369x/drivers/drv_uart.h index fed3184080..6e9b7703e0 100644 --- a/bsp/essemi/es32f369x/drivers/drv_uart.h +++ b/bsp/essemi/es32f369x/drivers/drv_uart.h @@ -3,6 +3,18 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes * 2020-01-14 wangyq the first version diff --git a/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Include/es32f36xx.h b/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Include/es32f36xx.h index 2e29a0d583..71e4e83261 100644 --- a/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Include/es32f36xx.h +++ b/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Include/es32f36xx.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/gcc/startup_es32f36xx.S b/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/gcc/startup_es32f36xx.S new file mode 100644 index 0000000000..4e34d42c1d --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/gcc/startup_es32f36xx.S @@ -0,0 +1,438 @@ +/** + ****************************************************************************** + * @file startup_es32f36xx.s + * @author AE Team + * @brief ES32F36xx devices vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + */ + + .syntax unified + .arch armv7-m + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/*bl __libc_init_array + + bl main */ + bl entry + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack /* 0, load top of stack */ + .word Reset_Handler /* 1, reset handler */ + .word NMI_Handler /* 2, nmi handler */ + .word HardFault_Handler /* 3, hard fault handler */ + .word MemManage_Handler /* 4, MPU Fault Handler */ + .word BusFault_Handler /* 5, Bus Fault Handler */ + .word UsageFault_Handler /* 6, Usage Fault Handler */ + .word 0 /* 7, Reserved */ + .word 0 /* 8, Reserved */ + .word 0 /* 9, Reserved */ + .word 0 /* 10, Reserved */ + .word SVC_Handler /* 11, svcall handler */ + .word DebugMon_Handler /* 12, Debug Monitor Handler */ + .word 0 /* 13, Reserved */ + .word PendSV_Handler /* 14, pendsv handler */ + .word SysTick_Handler /* 15, systick handler */ + .word WWDG_Handler /* 16, irq0 WWDG handler */ + .word IWDG_Handler /* 17, irq1 IWDG handler */ + .word LVD_Handler /* 18, irq2 LVD handler */ + .word RTC_Handler /* 19, irq3 RTC handler */ + .word 0 /* 20, irq4 Reserved */ + .word 0 /* 21, irq5 Reserved */ + .word CMU_Handler /* 22, irq6 CMU handler */ + .word ADC0_Handler /* 23, irq7 ADC0 handler */ + .word CAN0_TX_Handler /* 24, irq8 CAN0_TX handler */ + .word CAN0_RX0_Handler /* 25, irq9 CAN0_RX0 handler */ + .word CAN0_RX1_Handler /* 26, irq10 CAN0_RX1 handler */ + .word CAN0_EXCEPTION_Handler /* 27, irq11 CAN0_EXCEPTION handler */ + .word AD16C4T0_BRK_Handler /* 28, irq12 AD16C4T0_BRK handler */ + .word AD16C4T0_UP_Handler /* 29, irq13 AD16C4T0_UP handler */ + .word AD16C4T0_TRIG_COM_Handler /* 30, irq14 AD16C4T0_TRIG_COM handler */ + .word AD16C4T0_CC_Handler /* 31, irq15 AD16C4T0_CC handler */ + .word AD16C4T1_BRK_Handler /* 32, irq16 AD16C4T1_BRK handler */ + .word AD16C4T1_UP_Handler /* 33, irq17 AD16C4T1_UP handler */ + .word AD16C4T1_TRIG_COM_Handler /* 34, irq18 AD16C4T1_TRIG_COM handler */ + .word AD16C4T1_CC_Handler /* 35, irq19 AD16C4T1_CC handler */ + .word GP32C4T0_Handler /* 36, irq20 GP32C4T0 handler */ + .word GP32C4T1_Handler /* 37, irq21 GP32C4T1 handler */ + .word BS16T0_Handler /* 38, irq22 BS16T0 handler */ + .word BS16T1_Handler /* 39, irq23 BS16T1 handler */ + .word GP16C4T0_Handler /* 40, irq24 GP16C4T0 handler */ + .word GP16C4T1_Handler /* 41, irq25 GP16C4T1 handler */ + .word 0 /* 42, irq26 Reserved */ + .word DAC0_CH0_Handler /* 43, irq27 DAC0_CH0 handler */ + .word I2C0_EV_Handler /* 44, irq28 I2C0_EV handler */ + .word I2C0_ERR_Handler /* 45, irq29 I2C0_ERR handler */ + .word I2C1_EV_Handler /* 46 irq30 I2C1_EV handler */ + .word I2C1_ERR_Handler /* 47, irq31 I2C1_ERR handler */ + .word SPI0_I2S0_Handler /* 48, irq32 SPI0_I2S0 handler */ + .word SPI1_I2S1_Handler /* 49, irq33 SPI1_I2S1 handler */ + .word UART0_Handler /* 50, irq34 UART0 handler */ + .word UART1_Handler /* 51, irq35 UART1 handler */ + .word UART2_Handler /* 52, irq36 UART2 handler */ + .word UART3_Handler /* 53, irq37 UART3 handler */ + .word UART4_Handler /* 54, irq38 UART4 handler */ + .word UART5_Handler /* 55, irq39 UART5 handler */ + .word 0 /* 56, irq40 Reserved */ + .word 0 /* 57, irq41 Reserved */ + .word CRYPT_Handler /* 58, irq42 CRYPT handler */ + .word ACMP0_Handler /* 59, irq43 ACMP0 handler */ + .word ACMP1_Handler /* 60, irq44 ACMP1 handler */ + .word SPI2_I2S2_Handler /* 61, irq45 SPI2_I2S2 handler */ + .word 0 /* 62, irq46 Reserved */ + .word EBI_Handler /* 63, irq47 EBI handler */ + .word TRNG_Handler /* 64, irq48 TRNG handler */ + .word TSENSE_Handler /* 65, irq49 TSENSE handler */ + .word EXTI0_Handler /* 66, irq50 EXTI0 handler */ + .word EXTI1_Handler /* 67, irq51 EXTI1 handler */ + .word EXTI2_Handler /* 68, irq52 EXTI2 handler */ + .word EXTI3_Handler /* 69, irq53 EXTI3 handler */ + .word EXTI4_Handler /* 70, irq54 EXTI4 handler */ + .word EXTI5_Handler /* 71, irq55 EXTI5 handler */ + .word EXTI6_Handler /* 72, irq56 EXTI6 handler */ + .word EXTI7_Handler /* 73, irq57 EXTI7 handler */ + .word EXTI8_Handler /* 74, irq58 EXTI8 handler */ + .word EXTI9_Handler /* 75, irq59 EXTI9 handler */ + .word EXTI10_Handler /* 76, irq60 EXTI10 handler */ + .word EXTI11_Handler /* 77, irq61 EXTI11 handler */ + .word EXTI12_Handler /* 78, irq62 EXTI12 handler */ + .word EXTI13_Handler /* 79, irq63 EXTI13 handler */ + .word EXTI14_Handler /* 80, irq64 EXTI14 handler */ + .word EXTI15_Handler /* 81, irq65 EXTI15 handler */ + .word DMA_Handler /* 82, irq66 DMA handler */ + .word ADC1_Handler /* 83, irq67 ADC1 handler */ + .word DAC0_CH1_Handler /* 84, irq68 DAC0_CH1 handler */ + .word QSPI_Handler /* 85, irq69 QSPI handler */ + .word USB_INT_Handler /* 86, irq70 USB_INT handler */ + .word USB_DMA_Handler /* 87, irq71 USB_DMA handler */ + .word ACMP2_Handler /* 88, irq72 ACMP2 handler */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_Handler + .thumb_set WWDG_Handler,Default_Handler + + .weak IWDG_Handler + .thumb_set IWDG_Handler,Default_Handler + + .weak LVD_Handler + .thumb_set LVD_Handler,Default_Handler + + .weak RTC_Handler + .thumb_set RTC_Handler,Default_Handler + + .weak CMU_Handler + .thumb_set CMU_Handler,Default_Handler + + .weak ADC0_Handler + .thumb_set ADC0_Handler,Default_Handler + + .weak CAN0_TX_Handler + .thumb_set CAN0_TX_Handler,Default_Handler + + .weak CAN0_RX0_Handler + .thumb_set CAN0_RX0_Handler,Default_Handler + + .weak CAN0_RX1_Handler + .thumb_set CAN0_RX1_Handler,Default_Handler + + .weak CAN0_EXCEPTION_Handler + .thumb_set CAN0_EXCEPTION_Handler,Default_Handler + + .weak AD16C4T0_BRK_Handler + .thumb_set AD16C4T0_BRK_Handler,Default_Handler + + .weak AD16C4T0_UP_Handler + .thumb_set AD16C4T0_UP_Handler,Default_Handler + + .weak AD16C4T0_TRIG_COM_Handler + .thumb_set AD16C4T0_TRIG_COM_Handler,Default_Handler + + .weak AD16C4T0_CC_Handler + .thumb_set AD16C4T0_CC_Handler,Default_Handler + + .weak AD16C4T1_BRK_Handler + .thumb_set AD16C4T1_BRK_Handler,Default_Handler + + .weak AD16C4T1_UP_Handler + .thumb_set AD16C4T1_UP_Handler,Default_Handler + + .weak AD16C4T1_TRIG_COM_Handler + .thumb_set AD16C4T1_TRIG_COM_Handler,Default_Handler + + .weak AD16C4T1_CC_Handler + .thumb_set AD16C4T1_CC_Handler,Default_Handler + + .weak GP32C4T0_Handler + .thumb_set GP32C4T0_Handler,Default_Handler + + .weak GP32C4T1_Handler + .thumb_set GP32C4T1_Handler,Default_Handler + + .weak BS16T0_Handler + .thumb_set BS16T0_Handler,Default_Handler + + .weak BS16T1_Handler + .thumb_set BS16T1_Handler,Default_Handler + + .weak GP16C4T0_Handler + .thumb_set GP16C4T0_Handler,Default_Handler + + .weak GP16C4T1_Handler + .thumb_set GP16C4T1_Handler,Default_Handler + + .weak DAC0_CH0_Handler + .thumb_set DAC0_CH0_Handler,Default_Handler + + .weak I2C0_EV_Handler + .thumb_set I2C0_EV_Handler,Default_Handler + + .weak I2C0_ERR_Handler + .thumb_set I2C0_ERR_Handler,Default_Handler + + .weak I2C1_EV_Handler + .thumb_set I2C1_EV_Handler,Default_Handler + + .weak I2C1_ERR_Handler + .thumb_set I2C1_ERR_Handler,Default_Handler + + .weak SPI0_I2S0_Handler + .thumb_set SPI0_I2S0_Handler,Default_Handler + + .weak SPI1_I2S1_Handler + .thumb_set SPI1_I2S1_Handler,Default_Handler + + .weak UART0_Handler + .thumb_set UART0_Handler,Default_Handler + + .weak UART1_Handler + .thumb_set UART1_Handler,Default_Handler + + .weak UART2_Handler + .thumb_set UART2_Handler,Default_Handler + + .weak UART3_Handler + .thumb_set UART3_Handler,Default_Handler + + .weak UART4_Handler + .thumb_set UART4_Handler,Default_Handler + + .weak UART5_Handler + .thumb_set UART5_Handler,Default_Handler + + .weak CRYPT_Handler + .thumb_set CRYPT_Handler,Default_Handler + + .weak ACMP0_Handler + .thumb_set ACMP0_Handler,Default_Handler + + .weak ACMP1_Handler + .thumb_set ACMP1_Handler,Default_Handler + + .weak SPI2_I2S2_Handler + .thumb_set SPI2_I2S2_Handler,Default_Handler + + .weak EBI_Handler + .thumb_set EBI_Handler,Default_Handler + + .weak TRNG_Handler + .thumb_set TRNG_Handler,Default_Handler + + .weak TSENSE_Handler + .thumb_set TSENSE_Handler,Default_Handler + + .weak EXTI0_Handler + .thumb_set EXTI0_Handler,Default_Handler + + .weak EXTI1_Handler + .thumb_set EXTI1_Handler,Default_Handler + + .weak EXTI2_Handler + .thumb_set EXTI2_Handler,Default_Handler + + .weak EXTI3_Handler + .thumb_set EXTI3_Handler,Default_Handler + + .weak EXTI4_Handler + .thumb_set EXTI4_Handler,Default_Handler + + .weak EXTI5_Handler + .thumb_set EXTI5_Handler,Default_Handler + + .weak EXTI6_Handler + .thumb_set EXTI6_Handler,Default_Handler + + .weak EXTI7_Handler + .thumb_set EXTI7_Handler,Default_Handler + + .weak EXTI8_Handler + .thumb_set EXTI8_Handler,Default_Handler + + .weak EXTI9_Handler + .thumb_set EXTI9_Handler,Default_Handler + + .weak EXTI10_Handler + .thumb_set EXTI10_Handler,Default_Handler + + .weak EXTI11_Handler + .thumb_set EXTI11_Handler,Default_Handler + + .weak EXTI12_Handler + .thumb_set EXTI12_Handler,Default_Handler + + .weak EXTI13_Handler + .thumb_set EXTI13_Handler,Default_Handler + + .weak EXTI14_Handler + .thumb_set EXTI14_Handler,Default_Handler + + .weak EXTI15_Handler + .thumb_set EXTI15_Handler,Default_Handler + + .weak DMA_Handler + .thumb_set DMA_Handler,Default_Handler + + .weak ADC1_Handler + .thumb_set ADC1_Handler,Default_Handler + + .weak DAC0_CH1_Handler + .thumb_set DAC0_CH1_Handler,Default_Handler + + .weak QSPI_Handler + .thumb_set QSPI_Handler,Default_Handler + + .weak USB_INT_Handler + .thumb_set USB_INT_Handler,Default_Handler + + .weak USB_DMA_Handler + .thumb_set USB_DMA_Handler,Default_Handler + + .weak ACMP2_Handler + .thumb_set ACMP2_Handler,Default_Handler + diff --git a/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/keil/startup_es32f36xx.s b/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/keil/startup_es32f36xx.s index 362c8483fe..c8aaf3ed69 100644 --- a/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/keil/startup_es32f36xx.s +++ b/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/keil/startup_es32f36xx.s @@ -4,6 +4,20 @@ ; author : AE Team ; data : 23 Jan 2019 ; Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. +; +; SPDX-License-Identifier: Apache-2.0 +; +; Licensed under the Apache License, Version 2.0 (the License); you may +; not use this file except in compliance with the License. +; You may obtain a copy of the License at +; +; www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an AS IS BASIS, WITHOUT +; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. ;******************************************************************************* ;Stack Configuration------------------------------------------------------------ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_acmp.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_acmp.h index 7fbb68e655..60877098d6 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_acmp.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_acmp.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_adc.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_adc.h index 2638e139fd..e88c16d10b 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_adc.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_adc.h @@ -9,6 +9,20 @@ * @note * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ****************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_bkpc.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_bkpc.h index ce23ba73e9..246f6397d3 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_bkpc.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_bkpc.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_calc.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_calc.h index bd861b2d04..e14ff7851e 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_calc.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_calc.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_can.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_can.h index 196094eaaa..04a5d5ef5e 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_can.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_can.h @@ -10,6 +10,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ****************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_cmu.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_cmu.h index 400551ae45..55d713ed38 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_cmu.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_cmu.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_conf.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_conf.h index 1ee5597055..4953ab4f14 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_conf.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_conf.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_crc.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_crc.h index dcd6761acb..4e0f3cc152 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_crc.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_crc.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_crypt.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_crypt.h index f72cb06fc7..36a4d41387 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_crypt.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_crypt.h @@ -9,7 +9,21 @@ * @author AE Team * @note * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dac.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dac.h index d086905826..0e71f3e7e0 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dac.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dac.h @@ -9,6 +9,20 @@ * @note * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ****************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dbgc.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dbgc.h index 4d72f6cb2b..c6471b2c2c 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dbgc.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dbgc.h @@ -10,6 +10,21 @@ * @note * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dma.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dma.h index efd366889c..6f29a0cc7b 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dma.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dma.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_ebi.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_ebi.h index a4c0f372d6..d3ed85d97a 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_ebi.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_ebi.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_flash.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_flash.h index 3a1dfac113..8899ca4326 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_flash.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_flash.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_gpio.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_gpio.h index 4731c34a67..517330ce32 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_gpio.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_gpio.h @@ -9,7 +9,21 @@ * @author AE Team * @note * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_i2c.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_i2c.h index 7219542d60..c520c3d41a 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_i2c.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_i2c.h @@ -10,6 +10,20 @@ * @note * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ******************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_i2s.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_i2s.h index 46d0c36c8e..e6a811aae3 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_i2s.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_i2s.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_iap.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_iap.h index 900cc43086..cb1e0bf023 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_iap.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_iap.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_nand.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_nand.h index bf08b7de80..89d8d5875b 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_nand.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_nand.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_nor_lcd.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_nor_lcd.h index 83a200b34e..9815aa6ebc 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_nor_lcd.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_nor_lcd.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_pis.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_pis.h index 992b3790f0..39f481a5be 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_pis.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_pis.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_pmu.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_pmu.h index d58c34db24..f400be8a9f 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_pmu.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_pmu.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_qspi.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_qspi.h index a8e80b09d8..f4e2642dcd 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_qspi.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_qspi.h @@ -7,6 +7,20 @@ * @note * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rmu.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rmu.h index 07319306b0..bb3ec3df89 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rmu.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rmu.h @@ -9,7 +9,21 @@ * @author AE Team * @note * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ******************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rtc.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rtc.h index 4c31312e84..3234aa7d6e 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rtc.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rtc.h @@ -10,6 +10,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rtchw.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rtchw.h index 55cbbfec47..6faecf5145 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rtchw.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rtchw.h @@ -10,6 +10,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_spi.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_spi.h index 63a4a01f56..ebda1db3a7 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_spi.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_spi.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_sram.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_sram.h index 2743b83535..aff23692a3 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_sram.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_sram.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_syscfg.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_syscfg.h index c541c714ed..35063a28a1 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_syscfg.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_syscfg.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_timer.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_timer.h index 1805c3f95a..dcbc884368 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_timer.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_timer.h @@ -12,6 +12,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_trng.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_trng.h index ff86dbbcbf..267a7db0da 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_trng.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_trng.h @@ -9,7 +9,21 @@ * @author AE Team * @note * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ******************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_tsense.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_tsense.h index 6aff4435b1..cceb2587ec 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_tsense.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_tsense.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_uart.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_uart.h index a525f59783..56c1b5b94d 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_uart.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_uart.h @@ -9,7 +9,21 @@ * @author AE Team * @note * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_usb.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_usb.h index 38c991a757..d319f7a575 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_usb.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_usb.h @@ -9,7 +9,21 @@ * @author AE Team * @note * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ******************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_wdt.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_wdt.h index 5629fafaa3..805be32d50 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_wdt.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_wdt.h @@ -9,7 +9,21 @@ * @author AE Team * @note * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ******************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/type.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/type.h index ea5bd88970..a8db397a97 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/type.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/type.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ @@ -22,7 +36,7 @@ extern "C" { #endif #include - +#include "es_conf_info_select.h" #if defined (__CC_ARM) #define __INLINE__ __inline diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/utils.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/utils.h index 1c6b1b942f..b5589ce07a 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/utils.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/utils.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_acmp.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_acmp.c index 75c53bda13..2e2dbe74d5 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_acmp.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_acmp.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_adc.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_adc.c index c239d074b2..6870742cc0 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_adc.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_adc.c @@ -24,6 +24,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_bkpc.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_bkpc.c index c0a5e86f8a..568f7cec0e 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_bkpc.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_bkpc.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_calc.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_calc.c index 7a00c641fb..a49d150e32 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_calc.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_calc.c @@ -9,7 +9,21 @@ * @author AE Team * @note * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_can.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_can.c index 24cabd8cef..ec9ec28260 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_can.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_can.c @@ -14,6 +14,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** * @verbatim ============================================================================== diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_cmu.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_cmu.c index 76c6e516be..8beb08de5b 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_cmu.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_cmu.c @@ -9,7 +9,21 @@ * @author AE Team * @note * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ********************************************************************************* * @verbatim diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_crc.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_crc.c index ad0199a486..ea64ad1245 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_crc.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_crc.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_crypt.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_crypt.c index 4d17afca3b..04a0fa19de 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_crypt.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_crypt.c @@ -12,6 +12,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_dac.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_dac.c index ba07048b07..7f98ce0b88 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_dac.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_dac.c @@ -10,6 +10,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_dma.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_dma.c index a314e72b29..eae14f80c3 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_dma.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_dma.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* * @verbatim ============================================================================== diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_ebi.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_ebi.c index 5fc69ba3f9..d58acdfc9b 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_ebi.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_ebi.c @@ -10,6 +10,20 @@ * @note * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. ****************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_flash.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_flash.c index 48c7fe0228..33b114fa55 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_flash.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_flash.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* * ********************************************************************************* diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_flash_ext.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_flash_ext.c index 0c8f94b3a2..07d7dc5f60 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_flash_ext.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_flash_ext.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* * ********************************************************************************* diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_gpio.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_gpio.c index 686bb601d2..255c569463 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_gpio.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_gpio.c @@ -16,6 +16,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* * @verbatim ============================================================================== @@ -185,7 +199,7 @@ void ald_gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, gpio_init_t *init) for (i = 0; i < 16; ++i) { if (((pin >> i) & 0x1) == 0) continue; - + /* Get position and 2-bits mask */ pos = i << 1; mask = 0x3 << pos; diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_i2c.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_i2c.c index 419bb25481..37ec31d67d 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_i2c.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_i2c.c @@ -10,6 +10,20 @@ * @note * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * @verbatim ============================================================================== diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_i2s.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_i2s.c index 9570ddf8f7..c018037845 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_i2s.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_i2s.c @@ -17,6 +17,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* @verbatim ============================================================================== diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_iap.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_iap.c index e350c0a3ac..a2265bc1dc 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_iap.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_iap.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_nand.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_nand.c index 1595d520e6..cc178feb7f 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_nand.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_nand.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* * @verbatim ============================================================================== diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_nor_lcd.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_nor_lcd.c index 4d52faee86..ca28cbf091 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_nor_lcd.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_nor_lcd.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_pis.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_pis.c index e26037fcfc..3546c0b3be 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_pis.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_pis.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_pmu.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_pmu.c index bb588747db..0d411b0bbd 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_pmu.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_pmu.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_qspi.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_qspi.c index d0c0ecb3ac..b8bd90ffc1 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_qspi.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_qspi.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ #include "ald_qspi.h" diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rmu.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rmu.c index c5bd06b325..55869f621b 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rmu.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rmu.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rtc.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rtc.c index c0fd24b64f..baf3e5d205 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rtc.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rtc.c @@ -18,6 +18,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** * @verbatim ============================================================================== diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rtchw.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rtchw.c index c423f657cb..684e1eb5e8 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rtchw.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rtchw.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_spi.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_spi.c index ce78e605a7..470167d65e 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_spi.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_spi.c @@ -17,6 +17,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* @verbatim ============================================================================== diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_sram.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_sram.c index 31f7491679..384175d117 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_sram.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_sram.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ #include "ald_sram.h" diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_timer.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_timer.c index 49e8ccee2c..7860499237 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_timer.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_timer.c @@ -12,6 +12,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_trng.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_trng.c index 200f8db8bc..54496cec18 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_trng.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_trng.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_tsense.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_tsense.c index b5bbc8534b..90c341c864 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_tsense.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_tsense.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_uart.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_uart.c index f747967e32..84c96348c6 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_uart.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_uart.c @@ -17,6 +17,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* * @verbatim ============================================================================== diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_usb.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_usb.c index 26605cd791..3524853e37 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_usb.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_usb.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_wdt.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_wdt.c index 1e69e95d8f..2077cdabed 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_wdt.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_wdt.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ #include "ald_conf.h" diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/utils.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/utils.c index bd247fc055..d2c5bfecb6 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/utils.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/utils.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/project.uvoptx b/bsp/essemi/es32f369x/project.uvoptx index 9820d88eaa..2ee2601b40 100644 --- a/bsp/essemi/es32f369x/project.uvoptx +++ b/bsp/essemi/es32f369x/project.uvoptx @@ -73,7 +73,7 @@ 0 - 1 + 0 0 1 @@ -176,7 +176,7 @@ Applications - 1 + 0 0 0 0 @@ -195,7 +195,7 @@ - cpu + CPU 0 0 0 @@ -275,66 +275,6 @@ 0 0 0 - ..\..\..\components\drivers\can\can.c - can.c - 0 - 0 - - - 3 - 8 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\hwtimer\hwtimer.c - hwtimer.c - 0 - 0 - - - 3 - 9 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\i2c\i2c_core.c - i2c_core.c - 0 - 0 - - - 3 - 10 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\i2c\i2c_dev.c - i2c_dev.c - 0 - 0 - - - 3 - 11 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\i2c\i2c-bit-ops.c - i2c-bit-ops.c - 0 - 0 - - - 3 - 12 - 1 - 0 - 0 - 0 ..\..\..\components\drivers\misc\pin.c pin.c 0 @@ -342,55 +282,7 @@ 3 - 13 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\misc\adc.c - adc.c - 0 - 0 - - - 3 - 14 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\misc\rt_drv_pwm.c - rt_drv_pwm.c - 0 - 0 - - - 3 - 15 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\pm\pm.c - pm.c - 0 - 0 - - - 3 - 16 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\rtc\rtc.c - rtc.c - 0 - 0 - - - 3 - 17 + 8 1 0 0 @@ -402,43 +294,7 @@ 3 - 18 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\spi\spi_core.c - spi_core.c - 0 - 0 - - - 3 - 19 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\spi\spi_dev.c - spi_dev.c - 0 - 0 - - - 3 - 20 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\src\completion.c - completion.c - 0 - 0 - - - 3 - 21 + 9 1 0 0 @@ -450,7 +306,7 @@ 3 - 22 + 10 1 0 0 @@ -462,7 +318,31 @@ 3 - 23 + 11 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\workqueue.c + workqueue.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\completion.c + completion.c + 0 + 0 + + + 3 + 13 1 0 0 @@ -474,7 +354,7 @@ 3 - 24 + 14 1 0 0 @@ -486,7 +366,7 @@ 3 - 25 + 15 1 0 0 @@ -496,18 +376,6 @@ 0 0 - - 3 - 26 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\src\workqueue.c - workqueue.c - 0 - 0 - @@ -518,19 +386,7 @@ 0 4 - 27 - 1 - 0 - 0 - 0 - drivers\board.c - board.c - 0 - 0 - - - 4 - 28 + 16 1 0 0 @@ -542,7 +398,7 @@ 4 - 29 + 17 1 0 0 @@ -552,6 +408,18 @@ 0 0 + + 4 + 18 + 1 + 0 + 0 + 0 + drivers\board.c + board.c + 0 + 0 + @@ -562,7 +430,7 @@ 0 5 - 30 + 19 1 0 0 @@ -574,19 +442,7 @@ 5 - 31 - 1 - 0 - 0 - 0 - ..\..\..\components\finsh\cmd.c - cmd.c - 0 - 0 - - - 5 - 32 + 20 1 0 0 @@ -596,6 +452,18 @@ 0 0 + + 5 + 21 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\cmd.c + cmd.c + 0 + 0 + @@ -604,6 +472,138 @@ 0 0 0 + + 6 + 22 + 1 + 0 + 0 + 0 + ..\..\..\src\mem.c + mem.c + 0 + 0 + + + 6 + 23 + 1 + 0 + 0 + 0 + ..\..\..\src\irq.c + irq.c + 0 + 0 + + + 6 + 24 + 1 + 0 + 0 + 0 + ..\..\..\src\timer.c + timer.c + 0 + 0 + + + 6 + 25 + 1 + 0 + 0 + 0 + ..\..\..\src\object.c + object.c + 0 + 0 + + + 6 + 26 + 1 + 0 + 0 + 0 + ..\..\..\src\kservice.c + kservice.c + 0 + 0 + + + 6 + 27 + 1 + 0 + 0 + 0 + ..\..\..\src\signal.c + signal.c + 0 + 0 + + + 6 + 28 + 1 + 0 + 0 + 0 + ..\..\..\src\mempool.c + mempool.c + 0 + 0 + + + 6 + 29 + 1 + 0 + 0 + 0 + ..\..\..\src\thread.c + thread.c + 0 + 0 + + + 6 + 30 + 1 + 0 + 0 + 0 + ..\..\..\src\ipc.c + ipc.c + 0 + 0 + + + 6 + 31 + 1 + 0 + 0 + 0 + ..\..\..\src\idle.c + idle.c + 0 + 0 + + + 6 + 32 + 1 + 0 + 0 + 0 + ..\..\..\src\scheduler.c + scheduler.c + 0 + 0 + 6 33 @@ -611,8 +611,8 @@ 0 0 0 - ..\..\..\src\clock.c - clock.c + ..\..\..\src\device.c + device.c 0 0 @@ -635,140 +635,28 @@ 0 0 0 - ..\..\..\src\device.c - device.c + ..\..\..\src\clock.c + clock.c 0 0 + + + + libc + 0 + 0 + 0 + 0 - 6 + 7 36 1 0 0 0 - ..\..\..\src\idle.c - idle.c - 0 - 0 - - - 6 - 37 - 1 - 0 - 0 - 0 - ..\..\..\src\ipc.c - ipc.c - 0 - 0 - - - 6 - 38 - 1 - 0 - 0 - 0 - ..\..\..\src\irq.c - irq.c - 0 - 0 - - - 6 - 39 - 1 - 0 - 0 - 0 - ..\..\..\src\kservice.c - kservice.c - 0 - 0 - - - 6 - 40 - 1 - 0 - 0 - 0 - ..\..\..\src\mem.c - mem.c - 0 - 0 - - - 6 - 41 - 1 - 0 - 0 - 0 - ..\..\..\src\mempool.c - mempool.c - 0 - 0 - - - 6 - 42 - 1 - 0 - 0 - 0 - ..\..\..\src\object.c - object.c - 0 - 0 - - - 6 - 43 - 1 - 0 - 0 - 0 - ..\..\..\src\scheduler.c - scheduler.c - 0 - 0 - - - 6 - 44 - 1 - 0 - 0 - 0 - ..\..\..\src\signal.c - signal.c - 0 - 0 - - - 6 - 45 - 1 - 0 - 0 - 0 - ..\..\..\src\thread.c - thread.c - 0 - 0 - - - 6 - 46 - 1 - 0 - 0 - 0 - ..\..\..\src\timer.c - timer.c + ..\..\..\components\libc\compilers\common\time.c + time.c 0 0 @@ -781,176 +669,8 @@ 0 0 - 7 - 47 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_acmp.c - ald_acmp.c - 0 - 0 - - - 7 - 48 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_adc.c - ald_adc.c - 0 - 0 - - - 7 - 49 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_bkpc.c - ald_bkpc.c - 0 - 0 - - - 7 - 50 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_calc.c - ald_calc.c - 0 - 0 - - - 7 - 51 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_can.c - ald_can.c - 0 - 0 - - - 7 - 52 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_cmu.c - ald_cmu.c - 0 - 0 - - - 7 - 53 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crc.c - ald_crc.c - 0 - 0 - - - 7 - 54 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crypt.c - ald_crypt.c - 0 - 0 - - - 7 - 55 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dac.c - ald_dac.c - 0 - 0 - - - 7 - 56 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dma.c - ald_dma.c - 0 - 0 - - - 7 - 57 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_ebi.c - ald_ebi.c - 0 - 0 - - - 7 - 58 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash.c - ald_flash.c - 0 - 0 - - - 7 - 59 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash_ext.c - ald_flash_ext.c - 0 - 0 - - - 7 - 60 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_gpio.c - ald_gpio.c - 0 - 0 - - - 7 - 61 + 8 + 37 1 0 0 @@ -961,44 +681,44 @@ 0 - 7 - 62 + 8 + 38 1 0 0 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2s.c - ald_i2s.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_ebi.c + ald_ebi.c 0 0 - 7 - 63 + 8 + 39 1 0 0 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_iap.c - ald_iap.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtc.c + ald_rtc.c 0 0 - 7 - 64 + 8 + 40 1 0 0 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nand.c - ald_nand.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_can.c + ald_can.c 0 0 - 7 - 65 + 8 + 41 1 0 0 @@ -1009,8 +729,20 @@ 0 - 7 - 66 + 8 + 42 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_cmu.c + ald_cmu.c + 0 + 0 + + + 8 + 43 1 0 0 @@ -1021,7 +753,283 @@ 0 - 7 + 8 + 44 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_timer.c + ald_timer.c + 0 + 0 + + + 8 + 45 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_sram.c + ald_sram.c + 0 + 0 + + + 8 + 46 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_iap.c + ald_iap.c + 0 + 0 + + + 8 + 47 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_wdt.c + ald_wdt.c + 0 + 0 + + + 8 + 48 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtchw.c + ald_rtchw.c + 0 + 0 + + + 8 + 49 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dac.c + ald_dac.c + 0 + 0 + + + 8 + 50 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_acmp.c + ald_acmp.c + 0 + 0 + + + 8 + 51 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_gpio.c + ald_gpio.c + 0 + 0 + + + 8 + 52 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_tsense.c + ald_tsense.c + 0 + 0 + + + 8 + 53 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dma.c + ald_dma.c + 0 + 0 + + + 8 + 54 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rmu.c + ald_rmu.c + 0 + 0 + + + 8 + 55 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_trng.c + ald_trng.c + 0 + 0 + + + 8 + 56 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_spi.c + ald_spi.c + 0 + 0 + + + 8 + 57 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crc.c + ald_crc.c + 0 + 0 + + + 8 + 58 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_usb.c + ald_usb.c + 0 + 0 + + + 8 + 59 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_calc.c + ald_calc.c + 0 + 0 + + + 8 + 60 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\utils.c + utils.c + 0 + 0 + + + 8 + 61 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_qspi.c + ald_qspi.c + 0 + 0 + + + 8 + 62 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash.c + ald_flash.c + 0 + 0 + + + 8 + 63 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nand.c + ald_nand.c + 0 + 0 + + + 8 + 64 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_adc.c + ald_adc.c + 0 + 0 + + + 8 + 65 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crypt.c + ald_crypt.c + 0 + 0 + + + 8 + 66 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_uart.c + ald_uart.c + 0 + 0 + + + 8 67 1 0 @@ -1033,164 +1041,32 @@ 0 - 7 + 8 68 1 0 0 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_qspi.c - ald_qspi.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_bkpc.c + ald_bkpc.c 0 0 - 7 + 8 69 1 0 0 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rmu.c - ald_rmu.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash_ext.c + ald_flash_ext.c 0 0 - 7 + 8 70 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtc.c - ald_rtc.c - 0 - 0 - - - 7 - 71 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtchw.c - ald_rtchw.c - 0 - 0 - - - 7 - 72 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_spi.c - ald_spi.c - 0 - 0 - - - 7 - 73 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_sram.c - ald_sram.c - 0 - 0 - - - 7 - 74 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_timer.c - ald_timer.c - 0 - 0 - - - 7 - 75 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_trng.c - ald_trng.c - 0 - 0 - - - 7 - 76 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_tsense.c - ald_tsense.c - 0 - 0 - - - 7 - 77 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_uart.c - ald_uart.c - 0 - 0 - - - 7 - 78 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_usb.c - ald_usb.c - 0 - 0 - - - 7 - 79 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_wdt.c - ald_wdt.c - 0 - 0 - - - 7 - 80 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\utils.c - utils.c - 0 - 0 - - - 7 - 81 2 0 0 @@ -1200,6 +1076,18 @@ 0 0 + + 8 + 71 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2s.c + ald_i2s.c + 0 + 0 + diff --git a/bsp/essemi/es32f369x/project.uvprojx b/bsp/essemi/es32f369x/project.uvprojx index bca6765ef1..5fc8ec68b0 100644 --- a/bsp/essemi/es32f369x/project.uvprojx +++ b/bsp/essemi/es32f369x/project.uvprojx @@ -336,9 +336,9 @@ 0 - ES32F36xx + ES32F36xx, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND - applications;.;drivers;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\spi;..\..\..\components\drivers\include;..\..\..\components\drivers\include;drivers;..\..\..\components\finsh;.;..\..\..\include;libraries\CMSIS\Device\EastSoft\ES32F36xx\Include;libraries\CMSIS\Include;libraries\ES32F36xx_ALD_StdPeriph_Driver\Include + applications;.;drivers\ES;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;drivers;..\..\..\components\finsh;.;..\..\..\include;..\..\..\components\libc\compilers\common;libraries\CMSIS\Device\EastSoft\ES32F36xx\Include;libraries\CMSIS\Include;libraries\ES32F36xx_ALD_StdPeriph_Driver\Include @@ -390,7 +390,7 @@ - cpu + CPU backtrace.c @@ -421,146 +421,17 @@ DeviceDrivers - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 0 - - - - 2 - 0 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 0 - 2 - 2 - 2 - 2 - 2 - 0 - 0 - 2 - 2 - 2 - 2 - 2 - - - - - - - - - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - - - - - - - - - - - can.c - 1 - ..\..\..\components\drivers\can\can.c - - - hwtimer.c - 1 - ..\..\..\components\drivers\hwtimer\hwtimer.c - - - i2c_core.c - 1 - ..\..\..\components\drivers\i2c\i2c_core.c - - - i2c_dev.c - 1 - ..\..\..\components\drivers\i2c\i2c_dev.c - - - i2c-bit-ops.c - 1 - ..\..\..\components\drivers\i2c\i2c-bit-ops.c - pin.c 1 ..\..\..\components\drivers\misc\pin.c - - adc.c - 1 - ..\..\..\components\drivers\misc\adc.c - - - rt_drv_pwm.c - 1 - ..\..\..\components\drivers\misc\rt_drv_pwm.c - - - pm.c - 1 - ..\..\..\components\drivers\pm\pm.c - - - rtc.c - 1 - ..\..\..\components\drivers\rtc\rtc.c - serial.c 1 ..\..\..\components\drivers\serial\serial.c - - spi_core.c - 1 - ..\..\..\components\drivers\spi\spi_core.c - - - spi_dev.c - 1 - ..\..\..\components\drivers\spi\spi_dev.c - - - completion.c - 1 - ..\..\..\components\drivers\src\completion.c - dataqueue.c 1 @@ -571,6 +442,16 @@ 1 ..\..\..\components\drivers\src\pipe.c + + workqueue.c + 1 + ..\..\..\components\drivers\src\workqueue.c + + + completion.c + 1 + ..\..\..\components\drivers\src\completion.c + ringblk_buf.c 1 @@ -586,21 +467,11 @@ 1 ..\..\..\components\drivers\src\waitqueue.c - - workqueue.c - 1 - ..\..\..\components\drivers\src\workqueue.c - Drivers - - board.c - 1 - drivers\board.c - drv_gpio.c 1 @@ -611,6 +482,11 @@ 1 drivers\drv_uart.c + + board.c + 1 + drivers\board.c + @@ -621,45 +497,25 @@ 1 ..\..\..\components\finsh\shell.c - - cmd.c - 1 - ..\..\..\components\finsh\cmd.c - msh.c 1 ..\..\..\components\finsh\msh.c + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + Kernel - clock.c + mem.c 1 - ..\..\..\src\clock.c - - - components.c - 1 - ..\..\..\src\components.c - - - device.c - 1 - ..\..\..\src\device.c - - - idle.c - 1 - ..\..\..\src\idle.c - - - ipc.c - 1 - ..\..\..\src\ipc.c + ..\..\..\src\mem.c irq.c @@ -667,19 +523,9 @@ ..\..\..\src\irq.c - kservice.c + timer.c 1 - ..\..\..\src\kservice.c - - - mem.c - 1 - ..\..\..\src\mem.c - - - mempool.c - 1 - ..\..\..\src\mempool.c + ..\..\..\src\timer.c object.c @@ -687,24 +533,64 @@ ..\..\..\src\object.c - scheduler.c + kservice.c 1 - ..\..\..\src\scheduler.c + ..\..\..\src\kservice.c signal.c 1 ..\..\..\src\signal.c + + mempool.c + 1 + ..\..\..\src\mempool.c + thread.c 1 ..\..\..\src\thread.c - timer.c + ipc.c 1 - ..\..\..\src\timer.c + ..\..\..\src\ipc.c + + + idle.c + 1 + ..\..\..\src\idle.c + + + scheduler.c + 1 + ..\..\..\src\scheduler.c + + + device.c + 1 + ..\..\..\src\device.c + + + components.c + 1 + ..\..\..\src\components.c + + + clock.c + 1 + ..\..\..\src\clock.c + + + + + libc + + + time.c + 1 + ..\..\..\components\libc\compilers\common\time.c @@ -712,54 +598,9 @@ Libraries - ald_acmp.c + ald_i2c.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_acmp.c - - - ald_adc.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_adc.c - - - ald_bkpc.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_bkpc.c - - - ald_calc.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_calc.c - - - ald_can.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_can.c - - - ald_cmu.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_cmu.c - - - ald_crc.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crc.c - - - ald_crypt.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crypt.c - - - ald_dac.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dac.c - - - ald_dma.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dma.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2c.c ald_ebi.c @@ -767,125 +608,170 @@ libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_ebi.c - ald_flash.c + ald_rtc.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtc.c - ald_flash_ext.c + ald_can.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash_ext.c - - - ald_gpio.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_gpio.c - - - ald_i2c.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2c.c - - - ald_i2s.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2s.c - - - ald_iap.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_iap.c - - - ald_nand.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nand.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_can.c ald_nor_lcd.c 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nor_lcd.c + + ald_cmu.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_cmu.c + ald_pis.c 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pis.c - - ald_pmu.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pmu.c - - - ald_qspi.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_qspi.c - - - ald_rmu.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rmu.c - - - ald_rtc.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtc.c - - - ald_rtchw.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtchw.c - - - ald_spi.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_spi.c - - - ald_sram.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_sram.c - ald_timer.c 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_timer.c - ald_trng.c + ald_sram.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_trng.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_sram.c - ald_tsense.c + ald_iap.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_tsense.c - - - ald_uart.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_uart.c - - - ald_usb.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_usb.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_iap.c ald_wdt.c 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_wdt.c + + ald_rtchw.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtchw.c + + + ald_dac.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dac.c + + + ald_acmp.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_acmp.c + + + ald_gpio.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_gpio.c + + + ald_tsense.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_tsense.c + + + ald_dma.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dma.c + + + ald_rmu.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rmu.c + + + ald_trng.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_trng.c + + + ald_spi.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_spi.c + + + ald_crc.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crc.c + + + ald_usb.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_usb.c + + + ald_calc.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_calc.c + utils.c 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\utils.c + + ald_qspi.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_qspi.c + + + ald_flash.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash.c + + + ald_nand.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nand.c + + + ald_adc.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_adc.c + + + ald_crypt.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crypt.c + + + ald_uart.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_uart.c + + + ald_pmu.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pmu.c + + + ald_bkpc.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_bkpc.c + + + ald_flash_ext.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash_ext.c + startup_es32f36xx.s 2 libraries\CMSIS\Device\EastSoft\ES32F36xx\Startup\keil\startup_es32f36xx.s + + ald_i2s.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2s.c + diff --git a/bsp/essemi/es32f369x/rtconfig.h b/bsp/essemi/es32f369x/rtconfig.h index 54bd07901b..819056462c 100644 --- a/bsp/essemi/es32f369x/rtconfig.h +++ b/bsp/essemi/es32f369x/rtconfig.h @@ -15,7 +15,7 @@ #define RT_USING_HOOK #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 256 +#define IDLE_THREAD_STACK_SIZE 512 #define RT_DEBUG #define RT_DEBUG_COLOR @@ -26,6 +26,7 @@ #define RT_USING_EVENT #define RT_USING_MAILBOX #define RT_USING_MESSAGEQUEUE +#define RT_USING_SIGNALS /* Memory Management */ @@ -76,22 +77,14 @@ #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL #define RT_SERIAL_RB_BUFSZ 64 -#define RT_USING_CAN -#define RT_USING_HWTIMER -#define RT_USING_I2C -#define RT_USING_I2C_BITOPS #define RT_USING_PIN -#define RT_USING_ADC -#define RT_USING_PWM -#define RT_USING_PM -#define RT_USING_RTC -#define RT_USING_SPI /* Using USB */ /* POSIX layer and C standard library */ +#define RT_LIBC_USING_TIME /* Network */ @@ -144,6 +137,9 @@ /* system packages */ +/* Micrium: Micrium software products porting for RT-Thread */ + + /* peripheral libraries and drivers */ @@ -152,6 +148,9 @@ /* samples: kernel and components samples */ + +/* games: games run on RT-Thread console */ + #define SOC_ES32F3696LT /* Hardware Drivers Config */ @@ -179,7 +178,7 @@ /* RTC Drivers */ -/* HWtimer Drivers */ +/* HWTIMER Drivers */ /* PWM Drivers */ diff --git a/bsp/essemi/es32f369x/template.uvoptx b/bsp/essemi/es32f369x/template.uvoptx index 8d3f54f7f5..8e6583c22c 100644 --- a/bsp/essemi/es32f369x/template.uvoptx +++ b/bsp/essemi/es32f369x/template.uvoptx @@ -101,7 +101,9 @@ 0 0 1 - 2 + 0 + 0 + 3 @@ -165,6 +167,10 @@ + + + + diff --git a/bsp/essemi/es32f369x/template.uvprojx b/bsp/essemi/es32f369x/template.uvprojx index ad28753eb3..df9bb4e30c 100644 --- a/bsp/essemi/es32f369x/template.uvprojx +++ b/bsp/essemi/es32f369x/template.uvprojx @@ -10,11 +10,13 @@ rt-thread 0x4 ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 ES32F3696LT Eastsoft - Eastsoft.ES32_DFP.1.0.5 + Eastsoft.ES32_DFP.7.2350 http://www.essemi.com IRAM(0x20000000,0x00018000) IROM(0x00000000,0x00080000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE @@ -182,6 +184,7 @@ 0 0 0 + 0 0 0 8 @@ -322,6 +325,7 @@ 0 0 1 + 0 0 1 1 diff --git a/bsp/frdm-k64f/rtconfig.h b/bsp/frdm-k64f/rtconfig.h index 6338b39edb..81b5b29f8c 100644 --- a/bsp/frdm-k64f/rtconfig.h +++ b/bsp/frdm-k64f/rtconfig.h @@ -103,6 +103,7 @@ /* SECTION: lwip, a lighwight TCP/IP protocol stack */ #define RT_USING_LWIP +#define RT_USING_LWIP203 /* Enable LwIP debug output */ //#define RT_LWIP_DEBUG /* Enable ICMP protocol*/ diff --git a/bsp/gd32303e-eval/cconfig.h b/bsp/gd32303e-eval/cconfig.h deleted file mode 100644 index fb19b36e8e..0000000000 --- a/bsp/gd32303e-eval/cconfig.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef CCONFIG_H__ -#define CCONFIG_H__ -/* Automatically generated file; DO NOT EDIT. */ -/* compiler configure file for RT-Thread in GCC*/ - -#define HAVE_NEWLIB_H 1 -#define LIBC_VERSION "newlib 2.4.0" - -#define HAVE_SYS_SIGNAL_H 1 -#define HAVE_SYS_SELECT_H 1 -#define HAVE_PTHREAD_H 1 - -#define HAVE_FDSET 1 -#define HAVE_SIGACTION 1 -#define GCC_VERSION "5.4.1 20160919 (release) [ARM/embedded-5-branch revision 240496]" -#define STDC "2011" - -#endif diff --git a/bsp/gd32350r-eval/.config b/bsp/gd32350r-eval/.config new file mode 100644 index 0000000000..cba7e2b0bd --- /dev/null +++ b/bsp/gd32350r-eval/.config @@ -0,0 +1,555 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_COLOR is not set +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart" +CONFIG_RT_VER_NUM=0x40004 +# CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +# CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +# CONFIG_RT_USING_DFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +# CONFIG_RT_USING_LIBC is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_LIBC_USING_TIME is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_RT_LINK is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set + +# +# system packages +# + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set +CONFIG_SOC_GD32350R=y +CONFIG_BSP_USING_UART0=y +# CONFIG_BSP_USING_UART1 is not set diff --git a/bsp/gd32350r-eval/EventRecorderStub.scvd b/bsp/gd32350r-eval/EventRecorderStub.scvd new file mode 100644 index 0000000000..2956b29683 --- /dev/null +++ b/bsp/gd32350r-eval/EventRecorderStub.scvd @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/bsp/gd32350r-eval/Kconfig b/bsp/gd32350r-eval/Kconfig new file mode 100644 index 0000000000..907bfe3b87 --- /dev/null +++ b/bsp/gd32350r-eval/Kconfig @@ -0,0 +1,37 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +# you can change the RTT_ROOT default: "rt-thread" +# example : default "F:/git_repositories/rt-thread" + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config SOC_GD32350R + bool + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +config BSP_USING_UART0 + bool "using uart0" + select RT_USING_SERIAL + default n +config BSP_USING_UART1 + bool "using uart1" + select RT_USING_SERIAL + default n diff --git a/bsp/gd32350r-eval/Libraries/CMSIS/GD/GD32F3x0/Include/gd32f3x0.h b/bsp/gd32350r-eval/Libraries/CMSIS/GD/GD32F3x0/Include/gd32f3x0.h new file mode 100644 index 0000000000..9121b966b6 --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/CMSIS/GD/GD32F3x0/Include/gd32f3x0.h @@ -0,0 +1,242 @@ +/*! + \file gd32f3x0.h + \brief general definitions for gd32f3x0 + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F3X0_H +#define GD32F3X0_H + +#ifdef cplusplus + extern "C" { +#endif + +/* define GD32F3x0 */ +#if !defined (GD32F3x0) + #define GD32F3x0 +#endif /* define GD32F3x0 */ +#if !defined (GD32F3x0) + #error "Please select the target GD32F3x0 device used in your application (in gd32f3x0.h file)" +#endif /* undefine GD32F3x0 tip */ + +/* define GD32F3x0 device category */ +#if (!defined (GD32F330))&&(!defined (GD32F350)) + #error "Please select GD32F3x0 device category( GD32F330 or GD32F350 )" +#endif /* undefine GD32F330 or GD32F350 tip */ +#if (defined (GD32F330))&&(defined (GD32F350)) + #error "Please select one GD32F3x0 device category( GD32F330 or GD32F350 )" +#endif /* define GD32F330 and GD32F350 tip */ + +/* define value of high speed crystal oscillator (HXTAL) in Hz */ +#if !defined (HXTAL_VALUE) +#define HXTAL_VALUE ((uint32_t)8000000) +#endif /* high speed crystal oscillator value */ + +/* define startup timeout value of high speed crystal oscillator (HXTAL) */ +#if !defined (HXTAL_STARTUP_TIMEOUT) +#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0x0800) +#endif /* high speed crystal oscillator startup timeout */ + +/* define value of internal 8MHz RC oscillator (IRC8M) in Hz */ +#if !defined (IRC8M_VALUE) +#define IRC8M_VALUE ((uint32_t)8000000) +#endif /* internal 8MHz RC oscillator value */ + +/* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */ +#if !defined (IRC8M_STARTUP_TIMEOUT) +#define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500) +#endif /* internal 8MHz RC oscillator startup timeout */ + +/* define value of internal RC oscillator for ADC in Hz */ +#if !defined (IRC28M_VALUE) +#define IRC28M_VALUE ((uint32_t)28000000) +#endif /* IRC28M_VALUE */ + +#if !defined (IRC48M_VALUE) +#define IRC48M_VALUE ((uint32_t)48000000) +#endif /* IRC48M_VALUE */ + +/* define value of internal 40KHz RC oscillator(IRC40K) in Hz */ +#if !defined (IRC40K_VALUE) +#define IRC40K_VALUE ((uint32_t)40000) +#endif /* internal 40KHz RC oscillator value */ + +/* define value of low speed crystal oscillator (LXTAL)in Hz */ +#if !defined (LXTAL_VALUE) +#define LXTAL_VALUE ((uint32_t)32768) +#endif /* low speed crystal oscillator value */ + +/* GD32F3x0 firmware library version number V1.0 */ +#define __GD32F3x0_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __GD32F3x0_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ +#define __GD32F3x0_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __GD32F3x0_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __GD32F3x0_STDPERIPH_VERSION ((__GD32F3x0_STDPERIPH_VERSION_MAIN << 24)\ + |(__GD32F3x0_STDPERIPH_VERSION_SUB1 << 16)\ + |(__GD32F3x0_STDPERIPH_VERSION_SUB2 << 8)\ + |(__GD32F3x0_STDPERIPH_VERSION_RC)) + +/* configuration of the Cortex-M4 processor and core peripherals */ +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0U /*!< GD32F3x0 do not provide MPU */ +#define __NVIC_PRIO_BITS 4U /*!< GD32F3x0 uses 4 bits for the priority levels */ +#define __Vendor_SysTickConfig 0U /*!< set to 1 if different sysTick config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ + +/* define interrupt number */ +typedef enum IRQn +{ + /* Cortex-M4 processor exceptions numbers */ + NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 memory management interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 bus fault interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 usage fault interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV call interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 debug monitor interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 pend SV interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 system tick interrupt */ + /* interruput numbers */ + WWDGT_IRQn = 0, /*!< window watchdog timer interrupt */ + LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */ + RCU_CTC_IRQn = 2, /*!< RTC and CTC interrupt */ + FMC_IRQn = 3, /*!< FMC interrupt */ + RCU_IRQn = 4, /*!< RCU interrupt */ + EXTI0_1_IRQn = 5, /*!< EXTI line 0 and 1 interrupts */ + EXTI2_3_IRQn = 6, /*!< EXTI line 2 and 3 interrupts */ + EXTI4_15_IRQn = 7, /*!< EXTI line 4 to 15 interrupts */ + TSI_IRQn = 8, /*!< TSI Interrupt */ + DMA_Channel0_IRQn = 9, /*!< DMA channel 0 interrupt */ + DMA_Channel1_2_IRQn = 10, /*!< DMA channel 1 and channel 2 interrupts */ + DMA_Channel3_4_IRQn = 11, /*!< DMA channel 3 and channel 4 interrupts */ + ADC_CMP_IRQn = 12, /*!< ADC, CMP0 and CMP1 interrupts */ + TIMER0_BRK_UP_TRG_COM_IRQn = 13, /*!< TIMER0 break, update, trigger and commutation interrupts */ + TIMER0_Channel_IRQn = 14, /*!< TIMER0 channel capture compare interrupts */ + TIMER1_IRQn = 15, /*!< TIMER1 interrupt */ + TIMER2_IRQn = 16, /*!< TIMER2 interrupt */ +#ifdef GD32F350 + TIMER5_DAC_IRQn = 17, /*!< TIMER5 and DAC interrupts */ +#endif /* GD32F350 */ + TIMER13_IRQn = 19, /*!< TIMER13 interrupt */ + TIMER14_IRQn = 20, /*!< TIMER14 interrupt */ + TIMER15_IRQn = 21, /*!< TIMER15 interrupt */ + TIMER16_IRQn = 22, /*!< TIMER16 interrupt */ + I2C0_EV_IRQn = 23, /*!< I2C0 event interrupt */ + I2C1_EV_IRQn = 24, /*!< I2C1 event interrupt */ + SPI0_IRQn = 25, /*!< SPI0 interrupt */ + SPI1_IRQn = 26, /*!< SPI1 interrupt */ + USART0_IRQn = 27, /*!< USART0 interrupt */ + USART1_IRQn = 28, /*!< USART1 interrupt */ +#ifdef GD32F350 + CEC_IRQn = 30, /*!< CEC interrupt */ +#endif /* GD32F350 */ + I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ + I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ + DMA_Channel5_6_IRQn = 48, /*!< DMA channel 5 and channel 6 interrupts */ +#ifdef GD32F350 + USBFS_WKUP_IRQn = 42, /*!< USBFS wakeup interrupt */ + USBFS_IRQn = 67, /*!< USBFS global interrupt */ +#endif /* GD32F350 */ +} IRQn_Type; + +/* includes */ +#include "core_cm4.h" +#include "system_gd32f3x0.h" +#include + +/* enum definitions */ +typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; +typedef enum {FALSE = 0, TRUE = !FALSE} bool; +typedef enum {RESET = 0, SET = !RESET} FlagStatus; +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; + +/* bit operations */ +#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr)) +#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) +#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) +#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) +#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) +#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) + +/* main flash and SRAM memory map */ +#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */ +#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address */ +/* SRAM and peripheral base bit-band region */ +#define SRAM_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM bit-band base address */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< peripheral bit-band base address */ +/* peripheral memory map */ +#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */ +#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */ +#define AHB1_BUS_BASE ((uint32_t)0x40020000U) /*!< ahb1 base address */ +#define AHB2_BUS_BASE ((uint32_t)0x48000000U) /*!< ahb2 base address */ +/* advanced peripheral bus 1 memory map */ +#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */ +#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */ +#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */ +#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */ +#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */ +#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */ +#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */ +#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */ +#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */ +#define CEC_BASE (APB1_BUS_BASE + 0x00007800U) /*!< CEC base address */ +#define CTC_BASE (APB1_BUS_BASE + 0x0000C800U) /*!< CTC base address */ +/* advanced peripheral bus 2 memory map */ +#define SYSCFG_BASE (APB2_BUS_BASE + 0x00000000U) /*!< SYSCFG base address */ +#define CMP_BASE (APB2_BUS_BASE + 0x0000001CU) /*!< CMP base address */ +#define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */ +#define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */ +/* advanced high performance bus 1 memory map */ +#define DMA_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< DMA base address */ +#define DMA_CHANNEL_BASE (DMA_BASE + 0x00000008U) /*!< DMA channel base address */ +#define RCU_BASE (AHB1_BUS_BASE + 0x00001000U) /*!< RCU base address */ +#define FMC_BASE (AHB1_BUS_BASE + 0x00002000U) /*!< FMC base address */ +#define CRC_BASE (AHB1_BUS_BASE + 0x00003000U) /*!< CRC base address */ +#define TSI_BASE (AHB1_BUS_BASE + 0x00004000U) /*!< TSI base address */ +#define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE0000U) /*!< USBFS base address */ +/* advanced high performance bus 2 memory map */ +#define GPIO_BASE (AHB2_BUS_BASE + 0x00000000U) /*!< GPIO base address */ +/* option byte and debug memory map */ +#define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */ +#define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */ + +/* define marco USE_STDPERIPH_DRIVER */ +#if !defined USE_STDPERIPH_DRIVER +#define USE_STDPERIPH_DRIVER +#endif +#ifdef USE_STDPERIPH_DRIVER +#include "gd32f3x0_libopt.h" +#endif /* USE_STDPERIPH_DRIVER */ + +#ifdef cplusplus +} +#endif +#endif diff --git a/bsp/gd32350r-eval/Libraries/CMSIS/GD/GD32F3x0/Include/system_gd32f3x0.h b/bsp/gd32350r-eval/Libraries/CMSIS/GD/GD32F3x0/Include/system_gd32f3x0.h new file mode 100644 index 0000000000..c2e466587a --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/CMSIS/GD/GD32F3x0/Include/system_gd32f3x0.h @@ -0,0 +1,58 @@ +/*! + \file system_gd32f3x0.h + \brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for + GD32F3x0 Device Series +*/ + +/* Copyright (c) 2012 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ + +#ifndef SYSTEM_GD32F3X0_H +#define SYSTEM_GD32F3X0_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* system clock frequency (core clock) */ +extern uint32_t SystemCoreClock; + +/* function declarations */ +/* initialize the system and update the SystemCoreClock variable */ +extern void SystemInit (void); +/* update the SystemCoreClock with current core clock retrieved from cpu registers */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_GD32F3X0_H */ diff --git a/bsp/gd32350r-eval/Libraries/CMSIS/GD/GD32F3x0/Source/ARM/startup_gd32f3x0.s b/bsp/gd32350r-eval/Libraries/CMSIS/GD/GD32F3x0/Source/ARM/startup_gd32f3x0.s new file mode 100644 index 0000000000..d9930d2455 --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/CMSIS/GD/GD32F3x0/Source/ARM/startup_gd32f3x0.s @@ -0,0 +1,318 @@ +;/*! +; \file startup_gd32f3x0.s +; \brief start up file +; +; \version 2017-06-06, V1.0.0, firmware for GD32F3x0 +; \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +;*/ +; +;/* +; Copyright (c) 2019, GigaDevice Semiconductor Inc. +; +; Redistribution and use in source and binary forms, with or without modification, +;are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, this +; list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +;OF SUCH DAMAGE. +;*/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +; /* reset Vector Mapped to at Address 0 */ + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + +; /* external interrupts handler */ + DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer + DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect + DCD RTC_IRQHandler ; 18:RTC through EXTI Line + DCD FMC_IRQHandler ; 19:FMC + DCD RCU_CTC_IRQHandler ; 20:RCU and CTC + DCD EXTI0_1_IRQHandler ; 21:EXTI Line 0 and EXTI Line 1 + DCD EXTI2_3_IRQHandler ; 22:EXTI Line 2 and EXTI Line 3 + DCD EXTI4_15_IRQHandler ; 23:EXTI Line 4 to EXTI Line 15 + DCD TSI_IRQHandler ; 24:TSI + DCD DMA_Channel0_IRQHandler ; 25:DMA Channel 0 + DCD DMA_Channel1_2_IRQHandler ; 26:DMA Channel 1 and DMA Channel 2 + DCD DMA_Channel3_4_IRQHandler ; 27:DMA Channel 3 and DMA Channel 4 + DCD ADC_CMP_IRQHandler ; 28:ADC and Comparator 0-1 + DCD TIMER0_BRK_UP_TRG_COM_IRQHandler ; 29:TIMER0 Break,Update,Trigger and Commutation + DCD TIMER0_Channel_IRQHandler ; 30:TIMER0 Channel Capture Compare + DCD TIMER1_IRQHandler ; 31:TIMER1 + DCD TIMER2_IRQHandler ; 32:TIMER2 + DCD TIMER5_DAC_IRQHandler ; 33:TIMER5 and DAC + DCD 0 ; Reserved + DCD TIMER13_IRQHandler ; 35:TIMER13 + DCD TIMER14_IRQHandler ; 36:TIMER14 + DCD TIMER15_IRQHandler ; 37:TIMER15 + DCD TIMER16_IRQHandler ; 38:TIMER16 + DCD I2C0_EV_IRQHandler ; 39:I2C0 Event + DCD I2C1_EV_IRQHandler ; 40:I2C1 Event + DCD SPI0_IRQHandler ; 41:SPI0 + DCD SPI1_IRQHandler ; 42:SPI1 + DCD USART0_IRQHandler ; 43:USART0 + DCD USART1_IRQHandler ; 44:USART1 + DCD 0 ; Reserved + DCD CEC_IRQHandler ; 46:CEC + DCD 0 ; Reserved + DCD I2C0_ER_IRQHandler ; 48:I2C0 Error + DCD 0 ; Reserved + DCD I2C1_ER_IRQHandler ; 50:I2C1 Error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA_Channel5_6_IRQHandler ; 64:DMA Channel5 and Channel6 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD USBFS_IRQHandler ; 83:USBFS +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +;/* reset Handler */ +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +;/* dummy Exception Handlers */ +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC +; /* external interrupts handler */ + EXPORT WWDGT_IRQHandler [WEAK] + EXPORT LVD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT RCU_CTC_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT TSI_IRQHandler [WEAK] + EXPORT DMA_Channel0_IRQHandler [WEAK] + EXPORT DMA_Channel1_2_IRQHandler [WEAK] + EXPORT DMA_Channel3_4_IRQHandler [WEAK] + EXPORT ADC_CMP_IRQHandler [WEAK] + EXPORT TIMER0_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIMER0_Channel_IRQHandler [WEAK] + EXPORT TIMER1_IRQHandler [WEAK] + EXPORT TIMER2_IRQHandler [WEAK] + EXPORT TIMER5_DAC_IRQHandler [WEAK] + EXPORT TIMER13_IRQHandler [WEAK] + EXPORT TIMER14_IRQHandler [WEAK] + EXPORT TIMER15_IRQHandler [WEAK] + EXPORT TIMER16_IRQHandler [WEAK] + EXPORT I2C0_EV_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT I2C0_ER_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT USBFS_WKUP_IRQHandler [WEAK] + EXPORT DMA_Channel5_6_IRQHandler [WEAK] + EXPORT USBFS_IRQHandler [WEAK] + +;/* external interrupts handler */ +WWDGT_IRQHandler +LVD_IRQHandler +RTC_IRQHandler +FMC_IRQHandler +RCU_CTC_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +TSI_IRQHandler +DMA_Channel0_IRQHandler +DMA_Channel1_2_IRQHandler +DMA_Channel3_4_IRQHandler +ADC_CMP_IRQHandler +TIMER0_BRK_UP_TRG_COM_IRQHandler +TIMER0_Channel_IRQHandler +TIMER1_IRQHandler +TIMER2_IRQHandler +TIMER5_DAC_IRQHandler +TIMER13_IRQHandler +TIMER14_IRQHandler +TIMER15_IRQHandler +TIMER16_IRQHandler +I2C0_EV_IRQHandler +I2C1_EV_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +CEC_IRQHandler +I2C0_ER_IRQHandler +I2C1_ER_IRQHandler +USBFS_WKUP_IRQHandler +DMA_Channel5_6_IRQHandler +USBFS_IRQHandler + + B . + ENDP + + ALIGN + +; user Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + END diff --git a/bsp/gd32350r-eval/Libraries/CMSIS/GD/GD32F3x0/Source/IAR/startup_gd32f3x0.s b/bsp/gd32350r-eval/Libraries/CMSIS/GD/GD32F3x0/Source/IAR/startup_gd32f3x0.s new file mode 100644 index 0000000000..2d7c70dc4a --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/CMSIS/GD/GD32F3x0/Source/IAR/startup_gd32f3x0.s @@ -0,0 +1,366 @@ +;/*! +; \file startup_gd32f3x0.s +; \brief start up file +; +; \version 2017-06-06, V1.0.0, firmware for GD32F3x0 +; \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +;*/ +; +;/* +; Copyright (c) 2019, GigaDevice Semiconductor Inc. +; +; Redistribution and use in source and binary forms, with or without modification, +;are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, this +; list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +;OF SUCH DAMAGE. +;*/ + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) ; top of stack + DCD Reset_Handler ; Vector Number 1,Reset Handler + + DCD NMI_Handler ; Vector Number 2,NMI Handler + DCD HardFault_Handler ; Vector Number 3,Hard Fault Handler + DCD MemManage_Handler ; Vector Number 4,MPU Fault Handler + DCD BusFault_Handler ; Vector Number 5,Bus Fault Handler + DCD UsageFault_Handler ; Vector Number 6,Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; Vector Number 11,SVCall Handler + DCD DebugMon_Handler ; Vector Number 12,Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; Vector Number 14,PendSV Handler + DCD SysTick_Handler ; Vector Number 15,SysTick Handler + + ; External Interrupts + DCD WWDGT_IRQHandler ; Vector Number 16,Window watchdog timer + DCD LVD_IRQHandler ; Vector Number 17,LVD through EXTI Line detect + DCD RTC_IRQHandler ; Vector Number 18,RTC through EXTI Line + DCD FMC_IRQHandler ; Vector Number 19,FMC + DCD RCU_CTC_IRQHandler ; Vector Number 20,RCU and CTC + DCD EXTI0_1_IRQHandler ; Vector Number 21,EXTI Line 0 and EXTI Line 1 + DCD EXTI2_3_IRQHandler ; Vector Number 22,EXTI Line 2 and EXTI Line 3 + DCD EXTI4_15_IRQHandler ; Vector Number 23,EXTI Line 4 to EXTI Line 15 + DCD TSI_IRQHandler ; Vector Number 24,TSI + DCD DMA_Channel0_IRQHandler ; Vector Number 25,DMA Channel 0 + DCD DMA_Channel1_2_IRQHandler ; Vector Number 26,DMA Channel 1 and DMA Channel 2 + DCD DMA_Channel3_4_IRQHandler ; Vector Number 27,DMA Channel 3 and DMA Channel 4 + DCD ADC_CMP_IRQHandler ; Vector Number 28,ADC and Comparator 1-2 + DCD TIMER0_BRK_UP_TRG_COM_IRQHandler ; Vector Number 29,TIMER0 Break, Update, Trigger and Commutation + DCD TIMER0_Channel_IRQHandler ; Vector Number 30,TIMER0 Channel Capture Compare + DCD TIMER1_IRQHandler ; Vector Number 31,TIMER1 + DCD TIMER2_IRQHandler ; Vector Number 32,TIMER2 + DCD TIMER5_DAC_IRQHandler ; Vector Number 33,TIMER5 and DAC + DCD 0 ; Reserved + DCD TIMER13_IRQHandler ; Vector Number 35,TIMER13 + DCD TIMER14_IRQHandler ; Vector Number 36,TIMER14 + DCD TIMER15_IRQHandler ; Vector Number 37,TIMER15 + DCD TIMER16_IRQHandler ; Vector Number 38,TIMER16 + DCD I2C0_EV_IRQHandler ; Vector Number 39,I2C0 Event + DCD I2C1_EV_IRQHandler ; Vector Number 40,I2C1 Event + DCD SPI0_IRQHandler ; Vector Number 41,SPI0 + DCD SPI1_IRQHandler ; Vector Number 42,SPI1 + DCD USART0_IRQHandler ; Vector Number 43,USART0 + DCD USART1_IRQHandler ; Vector Number 44,USART1 + DCD 0 ; Reserved + DCD CEC_IRQHandler ; Vector Number 46,CEC + DCD 0 ; Reserved + DCD I2C0_ER_IRQHandler ; Vector Number 48,I2C0 Error + DCD 0 ; Reserved + DCD I2C1_ER_IRQHandler ; Vector Number 50,I2C1 Error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD USBFS_WKUP_IRQHandler ; Vector Number 58,USBFS Wakeup + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA_Channel5_6_IRQHandler ; Vector Number 64,DMA Channel5 and Channel6 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD USBFS_IRQHandler ; Vector Number 83,USBFS + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDGT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDGT_IRQHandler + B WWDGT_IRQHandler + + PUBWEAK LVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LVD_IRQHandler + B LVD_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK RCU_CTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCU_CTC_IRQHandler + B RCU_CTC_IRQHandler + + PUBWEAK EXTI0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_1_IRQHandler + B EXTI0_1_IRQHandler + + PUBWEAK EXTI2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_3_IRQHandler + B EXTI2_3_IRQHandler + + PUBWEAK EXTI4_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_15_IRQHandler + B EXTI4_15_IRQHandler + + PUBWEAK TSI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TSI_IRQHandler + B TSI_IRQHandler + + PUBWEAK DMA_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_Channel0_IRQHandler + B DMA_Channel0_IRQHandler + + PUBWEAK DMA_Channel1_2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_Channel1_2_IRQHandler + B DMA_Channel1_2_IRQHandler + + PUBWEAK DMA_Channel3_4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_Channel3_4_IRQHandler + B DMA_Channel3_4_IRQHandler + + PUBWEAK ADC_CMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC_CMP_IRQHandler + B ADC_CMP_IRQHandler + + PUBWEAK TIMER0_BRK_UP_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_BRK_UP_TRG_COM_IRQHandler + B TIMER0_BRK_UP_TRG_COM_IRQHandler + + PUBWEAK TIMER0_Channel_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_Channel_IRQHandler + B TIMER0_Channel_IRQHandler + + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER1_IRQHandler + B TIMER1_IRQHandler + + PUBWEAK TIMER2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER2_IRQHandler + B TIMER2_IRQHandler + + PUBWEAK TIMER5_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER5_DAC_IRQHandler + B TIMER5_DAC_IRQHandler + + PUBWEAK TIMER13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER13_IRQHandler + B TIMER13_IRQHandler + + PUBWEAK TIMER14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER14_IRQHandler + B TIMER14_IRQHandler + + PUBWEAK TIMER15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER15_IRQHandler + B TIMER15_IRQHandler + + PUBWEAK TIMER16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER16_IRQHandler + B TIMER16_IRQHandler + + PUBWEAK I2C0_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C0_EV_IRQHandler + B I2C0_EV_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK SPI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI0_IRQHandler + B SPI0_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK USART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART0_IRQHandler + B USART0_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK CEC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler + + PUBWEAK I2C0_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C0_ER_IRQHandler + B I2C0_ER_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK USBFS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBFS_WKUP_IRQHandler + B USBFS_WKUP_IRQHandler + + PUBWEAK DMA_Channel5_6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_Channel5_6_IRQHandler + B DMA_Channel5_6_IRQHandler + + PUBWEAK USBFS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBFS_IRQHandler + B USBFS_IRQHandler + + END diff --git a/bsp/gd32350r-eval/Libraries/CMSIS/GD/GD32F3x0/Source/system_gd32f3x0.c b/bsp/gd32350r-eval/Libraries/CMSIS/GD/GD32F3x0/Source/system_gd32f3x0.c new file mode 100644 index 0000000000..d8bb8bc727 --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/CMSIS/GD/GD32F3x0/Source/system_gd32f3x0.c @@ -0,0 +1,783 @@ +/*! + \file system_gd32f3x0.c + \brief CMSIS Cortex-M4 Device Peripheral Access Layer Source File for + GD32F3x0 Device Series +*/ + +/* Copyright (c) 2012 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ + +#include "gd32f3x0.h" + +/* system frequency define */ +#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */ +#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */ +#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */ + +#define VECT_TAB_OFFSET (uint32_t)0x00 /* vector table base offset */ + +/* select a system clock by uncommenting the following line */ +#if defined (GD32F330) +//#define __SYSTEM_CLOCK_8M_HXTAL (__HXTAL) +//#define __SYSTEM_CLOCK_8M_IRC8M (__IRC8M) +//#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000) +//#define __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2 (uint32_t)(72000000) +//#define __SYSTEM_CLOCK_72M_PLL_IRC48M_DIV2 (uint32_t)(72000000) +#define __SYSTEM_CLOCK_84M_PLL_HXTAL (uint32_t)(84000000) +//#define __SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2 (uint32_t)(84000000) +#endif /* GD32F330 */ + +#if defined (GD32F350) +//#define __SYSTEM_CLOCK_8M_HXTAL (__HXTAL) +//#define __SYSTEM_CLOCK_8M_IRC8M (__IRC8M) +//#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000) +//#define __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2 (uint32_t)(72000000) +//#define __SYSTEM_CLOCK_84M_PLL_HXTAL (uint32_t)(84000000) +//#define __SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2 (uint32_t)(84000000) +//#define __SYSTEM_CLOCK_96M_PLL_HXTAL (uint32_t)(96000000) +//#define __SYSTEM_CLOCK_96M_PLL_IRC8M_DIV2 (uint32_t)(96000000) +//#define __SYSTEM_CLOCK_96M_PLL_IRC48M_DIV2 (uint32_t)(96000000) +#define __SYSTEM_CLOCK_108M_PLL_HXTAL (uint32_t)(108000000) +//#define __SYSTEM_CLOCK_108M_PLL_IRC8M_DIV2 (uint32_t)(108000000) +#endif /* GD32F350 */ + +#define SEL_IRC8M 0x00 +#define SEL_HXTAL 0x01 +#define SEL_PLL 0x02 + +/* set the system clock frequency and declare the system clock configuration function */ +#ifdef __SYSTEM_CLOCK_8M_HXTAL +uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_HXTAL; +static void system_clock_8m_hxtal(void); + +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL; +static void system_clock_72m_hxtal(void); + +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2; +static void system_clock_72m_irc8m(void); + +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC48M_DIV2) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC48M_DIV2; +static void system_clock_72m_irc48m(void); + +#elif defined (__SYSTEM_CLOCK_84M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_84M_PLL_HXTAL; +static void system_clock_84m_hxtal(void); + +#elif defined (__SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2; +static void system_clock_84m_irc8m(void); + +#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_96M_PLL_HXTAL; +static void system_clock_96m_hxtal(void); + +#elif defined (__SYSTEM_CLOCK_96M_PLL_IRC8M_DIV2) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_96M_PLL_IRC8M_DIV2; +static void system_clock_96m_irc8m(void); + +#elif defined (__SYSTEM_CLOCK_96M_PLL_IRC48M_DIV2) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_96M_PLL_IRC48M_DIV2; +static void system_clock_96m_irc48m(void); + +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_HXTAL; +static void system_clock_108m_hxtal(void); + +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M_DIV2) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_IRC8M_DIV2; +static void system_clock_108m_irc8m(void); + +#else +uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_IRC8M; +static void system_clock_8m_irc8m(void); +#endif /* __SYSTEM_CLOCK_8M_HXTAL */ + +/* configure the system clock */ +static void system_clock_config(void); + +/*! + \brief setup the microcontroller system, initialize the system + \param[in] none + \param[out] none + \retval none +*/ +void SystemInit (void) +{ +#if (defined(GD32F350)) + RCU_APB2EN = BIT(0); + CMP_CS |= (CMP_CS_CMP1MSEL | CMP_CS_CMP0MSEL); +#endif /* GD32F350 */ + + /* FPU settings */ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ +#endif + /* enable IRC8M */ + RCU_CTL0 |= RCU_CTL0_IRC8MEN; + while(0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)){ + } + /* reset RCU */ + RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |\ + RCU_CFG0_ADCPSC | RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV); + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV); +#if (defined(GD32F350)) + RCU_CFG0 &= ~(RCU_CFG0_USBFSPSC); + RCU_CFG2 &= ~(RCU_CFG2_CECSEL | RCU_CFG2_USBFSPSC2); +#endif /* GD32F350 */ + RCU_CTL0 &= ~(RCU_CTL0_HXTALEN | RCU_CTL0_CKMEN | RCU_CTL0_PLLEN | RCU_CTL0_HXTALBPS); + RCU_CFG1 &= ~(RCU_CFG1_PREDV | RCU_CFG1_PLLMF5 | RCU_CFG1_PLLPRESEL); + RCU_CFG2 &= ~(RCU_CFG2_USART0SEL | RCU_CFG2_ADCSEL); + RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV; + RCU_CFG2 &= ~RCU_CFG2_ADCPSC2; + RCU_CTL1 &= ~RCU_CTL1_IRC28MEN; + RCU_ADDCTL &= ~RCU_ADDCTL_IRC48MEN; + RCU_INT = 0x00000000U; + RCU_ADDINT = 0x00000000U; + + /* configure system clock */ + system_clock_config(); + +#ifdef VECT_TAB_SRAM + nvic_vector_table_set(NVIC_VECTTAB_RAM,VECT_TAB_OFFSET); +#else + nvic_vector_table_set(NVIC_VECTTAB_FLASH,VECT_TAB_OFFSET); +#endif +} + +/*! + \brief configure the system clock + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_config(void) +{ +#ifdef __SYSTEM_CLOCK_8M_HXTAL + system_clock_8m_hxtal(); +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) + system_clock_72m_hxtal(); +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2) + system_clock_72m_irc8m(); +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC48M_DIV2) + system_clock_72m_irc48m(); +#elif defined (__SYSTEM_CLOCK_84M_PLL_HXTAL) + system_clock_84m_hxtal(); +#elif defined (__SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2) + system_clock_84m_irc8m(); +#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) + system_clock_96m_hxtal(); +#elif defined (__SYSTEM_CLOCK_96M_PLL_IRC8M_DIV2) + system_clock_96m_irc8m(); +#elif defined (__SYSTEM_CLOCK_96M_PLL_IRC48M_DIV2) + system_clock_96m_irc48m(); +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) + system_clock_108m_hxtal(); +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M_DIV2) + system_clock_108m_irc8m(); +#else + system_clock_8m_irc8m(); +#endif /* __SYSTEM_CLOCK_8M_HXTAL */ +} + +#ifdef __SYSTEM_CLOCK_8M_HXTAL +/*! + \brief configure the system clock to 8M by HXTAL + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_8m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL0 |= RCU_CTL0_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB); + } + while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + /* if fail */ + if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){ + return; + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV1; + + /* select HXTAL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_HXTAL; + + /* wait until HXTAL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_HXTAL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) +/*! + \brief configure the system clock to 72M by PLL which selects HXTAL as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_72m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL0 |= RCU_CTL0_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB); + } + while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + /* if fail */ + if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){ + return; + } + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* PLL = HXTAL * 9 = 72 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLDV); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL9); + + /* enable PLL */ + RCU_CTL0 |= RCU_CTL0_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + + +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2) +/*! + \brief configure the system clock to 72M by PLL which selects IRC8M/2 as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_72m_irc8m(void) +{ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + /* PLL = (IRC8M/2) * 18 = 72 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF); + RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL18); + + /* enable PLL */ + RCU_CTL0 |= RCU_CTL0_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC48M_DIV2) +/*! + \brief configure the system clock to 72M by PLL which selects IRC48M/2 as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_72m_irc48m(void) +{ + /* enable IRC48M */ + RCU_ADDCTL |= RCU_ADDCTL_IRC48MEN; + + /* wait until IRC48M is stable*/ + while(0U == (RCU_ADDCTL & RCU_ADDCTL_IRC48MSTB)){ + } + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + /* PLL = (IRC48M/2) * 3 = 96 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV); + RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PLLMF5); + RCU_CFG1 |= (RCU_PLL_PREDV2 |RCU_PLLPRESEL_IRC48M); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL3); + + /* enable PLL */ + RCU_CTL0 |= RCU_CTL0_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_84M_PLL_HXTAL) +/*! + \brief configure the system clock to 84M by PLL which selects HXTAL as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_84m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + /* enable HXTAL */ + RCU_CTL0 |= RCU_CTL0_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB); + } + while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + /* if fail */ + if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){ + return; + } + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* PLL = HXTAL /2 * 21 = 84 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV); + RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PLLMF5); + RCU_CFG1 |= RCU_PLL_PREDV2; + RCU_CFG0 |= (RCU_CFG0_PLLSEL | RCU_PLL_MUL21); + + /* enable PLL */ + RCU_CTL0 |= RCU_CTL0_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2) +/*! + \brief configure the system clock to 84M by PLL which selects IRC8M/2 as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_84m_irc8m(void) +{ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + /* PLL = (IRC8M/2) * 21 = 84 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF); + RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL21); + + /* enable PLL */ + RCU_CTL0 |= RCU_CTL0_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) +/*! + \brief configure the system clock to 96M by PLL which selects HXTAL as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_96m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + /* enable HXTAL */ + RCU_CTL0 |= RCU_CTL0_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB); + } + while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + /* if fail */ + if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){ + return; + } + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* PLL = HXTAL /2 * 24 = 96 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV); + RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PLLMF5); + RCU_CFG1 |= RCU_PLL_PREDV2; + RCU_CFG0 |= (RCU_CFG0_PLLSEL | RCU_PLL_MUL24); + + /* enable PLL */ + RCU_CTL0 |= RCU_CTL0_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_96M_PLL_IRC8M_DIV2) +/*! + \brief configure the system clock to 96M by PLL which selects IRC8M/2 as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_96m_irc8m(void) +{ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + /* PLL = (IRC8M/2) * 24 = 96 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF); + RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL24); + + /* enable PLL */ + RCU_CTL0 |= RCU_CTL0_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_96M_PLL_IRC48M_DIV2) +/*! + \brief configure the system clock to 96M by PLL which selects IRC48M/2 as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_96m_irc48m(void) +{ + /* enable IRC48M */ + RCU_ADDCTL |= RCU_ADDCTL_IRC48MEN; + + /* wait until IRC48M is stable*/ + while(0U == (RCU_ADDCTL & RCU_ADDCTL_IRC48MSTB)){ + } + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + /* PLL = (IRC48M/2) * 4 = 96 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV); + RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PLLMF5); + RCU_CFG1 |= (RCU_PLL_PREDV2 |RCU_PLLPRESEL_IRC48M); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL4); + + /* enable PLL */ + RCU_CTL0 |= RCU_CTL0_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) +/*! + \brief configure the system clock to 84M by PLL which selects HXTAL as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_108m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL0 |= RCU_CTL0_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB); + } + while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + /* if fail */ + if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){ + return; + } + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* PLL = HXTAL /2 * 27 = 108 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV); + RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PLLMF5); + RCU_CFG1 |= RCU_PLL_PREDV2; + RCU_CFG0 |= (RCU_CFG0_PLLSEL | RCU_PLL_MUL27); + + /* enable PLL */ + RCU_CTL0 |= RCU_CTL0_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M_DIV2) +/*! + \brief configure the system clock to 108M by PLL which selects IRC8M/2 as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_108m_irc8m(void) +{ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + /* PLL = (IRC8M/2) * 27 = 108 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF); + RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL27); + + /* enable PLL */ + RCU_CTL0 |= RCU_CTL0_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#else +/*! + \brief configure the system clock to 8M by IRC8M + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_8m_irc8m(void) +{ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV1; + + /* select IRC8M as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_IRC8M; + + /* wait until IRC8M is selected as system clock */ + while(0U != (RCU_CFG0 & RCU_SCSS_IRC8M)){ + } +} +#endif /* __SYSTEM_CLOCK_8M_HXTAL */ + +/*! + \brief update the SystemCoreClock with current core clock retrieved from cpu registers + \param[in] none + \param[out] none + \retval none +*/ +void SystemCoreClockUpdate (void) +{ + uint32_t sws = 0U; + uint32_t pllmf = 0U, pllmf4 = 0U, pllmf5 = 0U, pllsel = 0U, pllpresel = 0U, prediv = 0U, idx = 0U, clk_exp = 0U; + /* exponent of AHB clock divider */ + const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + + sws = GET_BITS(RCU_CFG0, 2, 3); + switch(sws){ + /* IRC8M is selected as CK_SYS */ + case SEL_IRC8M: + SystemCoreClock = IRC8M_VALUE; + break; + /* HXTAL is selected as CK_SYS */ + case SEL_HXTAL: + SystemCoreClock = HXTAL_VALUE; + break; + /* PLL is selected as CK_SYS */ + case SEL_PLL: + /* get the value of PLLMF[3:0] */ + pllmf = GET_BITS(RCU_CFG0, 18, 21); + pllmf4 = GET_BITS(RCU_CFG0, 27, 27); + pllmf5 = GET_BITS(RCU_CFG1, 31, 31); + /* high 16 bits */ + if(1U == pllmf4){ + pllmf += 17U; + }else{ + pllmf += 2U; + } + if(1U == pllmf5){ + pllmf += 31U; + } + /* PLL clock source selection, HXTAL or IRC8M/2 */ + pllsel = GET_BITS(RCU_CFG0, 16, 16); + if(0U != pllsel){ + prediv = (GET_BITS(RCU_CFG1, 0, 3) + 1U); + if(0U == pllpresel){ + SystemCoreClock = (HXTAL_VALUE / prediv) * pllmf; + }else{ + SystemCoreClock = (IRC48M_VALUE / prediv) * pllmf; + } + }else{ + SystemCoreClock = (IRC8M_VALUE >> 1) * pllmf; + } + break; + /* IRC8M is selected as CK_SYS */ + default: + SystemCoreClock = IRC8M_VALUE; + break; + } + /* calculate AHB clock frequency */ + idx = GET_BITS(RCU_CFG0, 4, 7); + clk_exp = ahb_exp[idx]; + SystemCoreClock >>= clk_exp; +} diff --git a/bsp/gd32350r-eval/Libraries/CMSIS/core_cm4.h b/bsp/gd32350r-eval/Libraries/CMSIS/core_cm4.h new file mode 100644 index 0000000000..d82841442c --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/CMSIS/core_cm4.h @@ -0,0 +1,1790 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V3.30 + * @date 17. February 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) /* Cosmic */ + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ +#include /* Compiler specific SIMD Intrinsics */ + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000 + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0 + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ +/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ + NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/bsp/gd32350r-eval/Libraries/CMSIS/core_cm4_simd.h b/bsp/gd32350r-eval/Libraries/CMSIS/core_cm4_simd.h new file mode 100644 index 0000000000..f9bceff1e5 --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/CMSIS/core_cm4_simd.h @@ -0,0 +1,697 @@ +/**************************************************************************//** + * @file core_cm4_simd.h + * @brief CMSIS Cortex-M4 SIMD Header File + * @version V3.30 + * @date 17. February 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM4_SIMD_H +#define __CORE_CM4_SIMD_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32) ) >> 32)) + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* not yet supported */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_SIMD_H */ diff --git a/bsp/gd32350r-eval/Libraries/CMSIS/core_cmFunc.h b/bsp/gd32350r-eval/Libraries/CMSIS/core_cmFunc.h new file mode 100644 index 0000000000..3c932e0d6e --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/CMSIS/core_cmFunc.h @@ -0,0 +1,616 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V3.01 + * @date 06. March 2012 + * + * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) ); +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) ); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) ); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +#endif /* __CORE_CMFUNC_H */ diff --git a/bsp/gd32350r-eval/Libraries/CMSIS/core_cmInstr.h b/bsp/gd32350r-eval/Libraries/CMSIS/core_cmInstr.h new file mode 100644 index 0000000000..597e64df04 --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/CMSIS/core_cmInstr.h @@ -0,0 +1,618 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V3.01 + * @date 06. March 2012 + * + * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + +#endif /* (__CORTEX_M >= 0x03) */ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ + uint32_t result; + + __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + + __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) ); + return(op1); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint8_t result; + + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint16_t result; + + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +{ + uint8_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_adc.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_adc.h new file mode 100644 index 0000000000..f184578579 --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_adc.h @@ -0,0 +1,365 @@ +/*! + \file gd32f3x0_adc.h + \brief definitions for the ADC + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F3X0_ADC_H +#define GD32F3X0_ADC_H + +#include "gd32f3x0.h" + +/* ADC definitions */ +#define ADC ADC_BASE + +/* registers definitions */ +#define ADC_STAT REG32(ADC + 0x00000000U) /*!< ADC status register */ +#define ADC_CTL0 REG32(ADC + 0x00000004U) /*!< ADC control register 0 */ +#define ADC_CTL1 REG32(ADC + 0x00000008U) /*!< ADC control register 1 */ +#define ADC_SAMPT0 REG32(ADC + 0x0000000CU) /*!< ADC sampling time register 0 */ +#define ADC_SAMPT1 REG32(ADC + 0x00000010U) /*!< ADC sampling time register 1 */ +#define ADC_IOFF0 REG32(ADC + 0x00000014U) /*!< ADC inserted channel data offset register 0 */ +#define ADC_IOFF1 REG32(ADC + 0x00000018U) /*!< ADC inserted channel data offset register 1 */ +#define ADC_IOFF2 REG32(ADC + 0x0000001CU) /*!< ADC inserted channel data offset register 2 */ +#define ADC_IOFF3 REG32(ADC + 0x00000020U) /*!< ADC inserted channel data offset register 3 */ +#define ADC_WDHT REG32(ADC + 0x00000024U) /*!< ADC watchdog high threshold register */ +#define ADC_WDLT REG32(ADC + 0x00000028U) /*!< ADC watchdog low threshold register */ +#define ADC_RSQ0 REG32(ADC + 0x0000002CU) /*!< ADC regular sequence register 0 */ +#define ADC_RSQ1 REG32(ADC + 0x00000030U) /*!< ADC regular sequence register 1 */ +#define ADC_RSQ2 REG32(ADC + 0x00000034U) /*!< ADC regular sequence register 2 */ +#define ADC_ISQ REG32(ADC + 0x00000038U) /*!< ADC inserted sequence register */ +#define ADC_IDATA0 REG32(ADC + 0x0000003CU) /*!< ADC inserted data register 0 */ +#define ADC_IDATA1 REG32(ADC + 0x00000040U) /*!< ADC inserted data register 1 */ +#define ADC_IDATA2 REG32(ADC + 0x00000044U) /*!< ADC inserted data register 2 */ +#define ADC_IDATA3 REG32(ADC + 0x00000048U) /*!< ADC inserted data register 3 */ +#define ADC_RDATA REG32(ADC + 0x0000004CU) /*!< ADC regular data register */ +#define ADC_OVSAMPCTL REG32(ADC + 0x00000080U) /*!< ADC oversampling control register */ + +/* bits definitions */ +/* ADC_STAT */ +#define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */ +#define ADC_STAT_EOC BIT(1) /*!< end of conversion flag */ +#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion flag */ +#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */ +#define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */ + +/* ADC_CTL0 */ +#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */ +#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */ +#define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */ +#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */ +#define ADC_CTL0_SM BIT(8) /*!< scan mode */ +#define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */ +#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */ +#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */ +#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */ +#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */ +#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */ +#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */ +#define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */ + +/* ADC_CTL1 */ +#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */ +#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */ +#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */ +#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ +#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */ +#define ADC_CTL1_DAL BIT(11) /*!< data alignment */ +#define ADC_CTL1_ETSIC BITS(12,14) /*!< external trigger select for inserted channel */ +#define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */ +#define ADC_CTL1_ETSRC BITS(17,19) /*!< external trigger select for regular channel */ +#define ADC_CTL1_ETERC BIT(20) /*!< external trigger enable for regular channel */ +#define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */ +#define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */ +#define ADC_CTL1_TSVREN BIT(23) /*!< enable channel 16 and 17 */ +#define ADC_CTL1_VBETEN BIT(24) /*!< VBAT enable */ + +/* ADC_SAMPTx x=0,1 */ +#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel n(n=0..18) sample time selection */ + +/* ADC_IOFFx x=0..3 */ +#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */ + +/* ADC_WDHT */ +#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */ + +/* ADC_WDLT */ +#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */ + +/* ADC_RSQx x=0..2 */ +#define ADC_RSQX_RSQN BITS(0,4) /*!< n conversion in regular sequence */ +#define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */ + +/* ADC_ISQ */ +#define ADC_ISQ_ISQN BITS(0,4) /*!< n conversion in regular sequence */ +#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */ + +/* ADC_IDATAx x=0..3*/ +#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted channel x conversion data */ + +/* ADC_RDATA */ +#define ADC_RDATA_RDATA BITS(0,15) /*!< regular channel data */ + +/* ADC_OVSAMPCTL */ +#define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */ +#define ADC_OVSAMPCTL_OVSR BITS(2,4) /*!< oversampling ratio */ +#define ADC_OVSAMPCTL_OVSS BITS(5,8) /*!< oversampling shift */ +#define ADC_OVSAMPCTL_TOVS BIT(9) /*!< triggered oversampling */ + +/* constants definitions */ +/* ADC flag definitions */ +#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */ +#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion flag */ +#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted channel group conversion flag */ +#define ADC_FLAG_STIC ADC_STAT_STIC /*!< start flag of inserted channel group */ +#define ADC_FLAG_STRC ADC_STAT_STRC /*!< start flag of regular channel group */ + +/* adc_ctl0 register value */ +#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< number of conversions in discontinuous mode */ + +/* ADC special function */ +#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */ +#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */ +#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */ + +/* ADC data alignment */ +#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< right alignment */ +#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< left alignment */ + +/* external trigger select for regular channel */ +#define CTL1_ETSRC(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) +#define ADC_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< TIMER0 CH0 event select */ +#define ADC_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< TIMER0 CH1 event select */ +#define ADC_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< TIMER0 CH2 event select */ +#define ADC_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3) /*!< TIMER1 CH1 event select */ +#define ADC_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(4) /*!< TIMER2 TRGO event select */ +#define ADC_EXTTRIG_REGULAR_T14_CH0 CTL1_ETSRC(5) /*!< TIMER14 CH0 event select */ +#define ADC_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(6) /*!< external interrupt line 11 */ +#define ADC_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7) /*!< software trigger */ + +/* external trigger select for inserted channel */ +#define CTL1_ETSIC(regval) (BITS(12,14) & ((uint32_t)(regval) << 12)) +#define ADC_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< TIMER0 TRGO event select */ +#define ADC_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< TIMER0 CH3 event select */ +#define ADC_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(2) /*!< TIMER1 TRGO event select */ +#define ADC_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(3) /*!< TIMER1 CH0 event select */ +#define ADC_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(4) /*!< TIMER2 CH3 event select */ +#define ADC_EXTTRIG_INSERTED_T14_TRGO CTL1_ETSIC(5) /*!< TIMER14 TRGO event select */ +#define ADC_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(6) /*!< external interrupt line 15 */ +#define ADC_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7) /*!< software trigger */ + +/* adc_samptx register value */ +#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) +#define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0) /*!< 1.5 sampling cycles */ +#define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1) /*!< 7.5 sampling cycles */ +#define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2) /*!< 13.5 sampling cycles */ +#define ADC_SAMPLETIME_28POINT5 SAMPTX_SPT(3) /*!< 28.5 sampling cycles */ +#define ADC_SAMPLETIME_41POINT5 SAMPTX_SPT(4) /*!< 41.5 sampling cycles */ +#define ADC_SAMPLETIME_55POINT5 SAMPTX_SPT(5) /*!< 55.5 sampling cycles */ +#define ADC_SAMPLETIME_71POINT5 SAMPTX_SPT(6) /*!< 71.5 sampling cycles */ +#define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7) /*!< 239.5 sampling cycles */ + +/* ADC data offset for inserted channel x*/ +#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) + +/* ADC analog watchdog high threshold */ +#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) + +/* ADC analog watchdog low threshold */ +#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) + +/* ADC regular channel group length */ +#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) + +/* ADC inserted channel group length */ +#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) + +/* ADC resolution definitions */ +#define CTL0_DRES(regval) (BITS(24,25) & ((regval) << 24)) /*!< ADC resolution */ +#define ADC_RESOLUTION_12B CTL0_DRES(0) /*!< 12-bit ADC resolution */ +#define ADC_RESOLUTION_10B CTL0_DRES(1) /*!< 10-bit ADC resolution */ +#define ADC_RESOLUTION_8B CTL0_DRES(2) /*!< 8-bit ADC resolution */ +#define ADC_RESOLUTION_6B CTL0_DRES(3) /*!< 6-bit ADC resolution */ + +/* ADC oversampling shift */ +#define OVSAMPCTL_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) +#define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0) /*!< no oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1) /*!< 1-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2) /*!< 2-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_3B OVSAMPCTL_OVSS(3) /*!< 3-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_4B OVSAMPCTL_OVSS(4) /*!< 4-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_5B OVSAMPCTL_OVSS(5) /*!< 5-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_6B OVSAMPCTL_OVSS(6) /*!< 6-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_7B OVSAMPCTL_OVSS(7) /*!< 7-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8) /*!< 8-bit oversampling shift */ + +/* ADC oversampling ratio */ +#define OVSAMPCTL_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) +#define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0) /*!< oversampling ratio multiple 2 */ +#define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1) /*!< oversampling ratio multiple 4 */ +#define ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2) /*!< oversampling ratio multiple 8 */ +#define ADC_OVERSAMPLING_RATIO_MUL16 OVSAMPCTL_OVSR(3) /*!< oversampling ratio multiple 16 */ +#define ADC_OVERSAMPLING_RATIO_MUL32 OVSAMPCTL_OVSR(4) /*!< oversampling ratio multiple 32 */ +#define ADC_OVERSAMPLING_RATIO_MUL64 OVSAMPCTL_OVSR(5) /*!< oversampling ratio multiple 64 */ +#define ADC_OVERSAMPLING_RATIO_MUL128 OVSAMPCTL_OVSR(6) /*!< oversampling ratio multiple 128 */ +#define ADC_OVERSAMPLING_RATIO_MUL256 OVSAMPCTL_OVSR(7) /*!< oversampling ratio multiple 256 */ + +/* ADC triggered oversampling */ +#define ADC_OVERSAMPLING_ALL_CONVERT 0U /*!< all oversampled conversions for a channel are done consecutively after a trigger */ +#define ADC_OVERSAMPLING_ONE_CONVERT 1U /*!< each oversampled conversion for a channel needs a trigger */ + +/* ADC channel group definitions */ +#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< ADC regular channel group */ +#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< ADC inserted channel group */ +#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */ +#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */ + +/* ADC inserted channel definitions */ +#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC inserted channel 0 */ +#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC inserted channel 1 */ +#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC inserted channel 2 */ +#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC inserted channel 3 */ + +/* ADC channel definitions */ +#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */ +#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */ +#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */ +#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */ +#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */ +#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */ +#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */ +#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */ +#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */ +#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */ +#define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */ +#define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */ +#define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */ +#define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */ +#define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */ +#define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */ +#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */ +#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */ +#define ADC_CHANNEL_18 ((uint8_t)0x12U) /*!< ADC channel 18 */ + +/* ADC interrupt definitions */ +#define ADC_INT_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */ +#define ADC_INT_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */ +#define ADC_INT_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */ + +/* ADC interrupt flag */ +#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt flag */ +#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt flag */ +#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt flag */ + +/* function declarations */ +/* reset ADC */ +void adc_deinit(void); +/* enable ADC interface */ +void adc_enable(void); +/* disable ADC interface */ +void adc_disable(void); + +/* ADC calibration and reset calibration */ +void adc_calibration_enable(void); +/* enable DMA request */ +void adc_dma_mode_enable(void); +/* disable DMA request */ +void adc_dma_mode_disable(void); + +/* enable the temperature sensor and Vrefint channel */ +void adc_tempsensor_vrefint_enable(void); +/* disable the temperature sensor and Vrefint channel */ +void adc_tempsensor_vrefint_disable(void); +/* enable the vbat channel */ +void adc_vbat_enable(void); +/* disable the vbat channel */ +void adc_vbat_disable(void); + +/* configure ADC discontinuous mode */ +void adc_discontinuous_mode_config(uint8_t channel_group, uint8_t length); +/* configure ADC special function */ +void adc_special_function_config(uint32_t function, ControlStatus newvalue); + +/* configure ADC data alignment */ +void adc_data_alignment_config(uint32_t data_alignment); +/* configure the length of regular channel group or inserted channel group */ +void adc_channel_length_config(uint8_t channel_group, uint32_t length); +/* configure ADC regular channel */ +void adc_regular_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time); +/* configure ADC inserted channel */ +void adc_inserted_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time); +/* configure ADC inserted channel offset */ +void adc_inserted_channel_offset_config(uint8_t inserted_channel, uint16_t offset); +/* enable ADC external trigger */ +void adc_external_trigger_config(uint8_t channel_group, ControlStatus newvalue); +/* configure ADC external trigger source */ +void adc_external_trigger_source_config(uint8_t channel_group, uint32_t external_trigger_source); +/* enable ADC software trigger */ +void adc_software_trigger_enable(uint8_t channel_group); + +/* read ADC regular group data register */ +uint16_t adc_regular_data_read(void); +/* read ADC inserted group data register */ +uint16_t adc_inserted_data_read(uint8_t inserted_channel); + +/* get the ADC flag bits */ +FlagStatus adc_flag_get(uint32_t flag); +/* clear the ADC flag bits */ +void adc_flag_clear(uint32_t flag); +/* get the ADC interrupt bits */ +FlagStatus adc_interrupt_flag_get(uint32_t flag); +/* clear the ADC flag */ +void adc_interrupt_flag_clear(uint32_t flag); +/* enable ADC interrupt */ +void adc_interrupt_enable(uint32_t interrupt); +/* disable ADC interrupt */ +void adc_interrupt_disable(uint32_t interrupt); + +/* configure ADC analog watchdog single channel */ +void adc_watchdog_single_channel_enable(uint8_t channel); +/* configure ADC analog watchdog group channel */ +void adc_watchdog_group_channel_enable(uint8_t channel_group); +/* disable ADC analog watchdog */ +void adc_watchdog_disable(void); +/* configure ADC analog watchdog threshold */ +void adc_watchdog_threshold_config(uint16_t low_threshold, uint16_t high_threshold); + +/* configure ADC resolution */ +void adc_resolution_config(uint32_t resolution); +/* configure ADC oversample mode */ +void adc_oversample_mode_config(uint8_t mode, uint16_t shift, uint8_t ratio); +/* enable ADC oversample mode */ +void adc_oversample_mode_enable(void); +/* disable ADC oversample mode */ +void adc_oversample_mode_disable(void); + +#endif /* GD32F3X0_ADC_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_cec.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_cec.h new file mode 100644 index 0000000000..304c53437b --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_cec.h @@ -0,0 +1,250 @@ +/*! + \file gd32f3x0_cec.h + \brief definitions for the CEC + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifdef GD32F350 + +#ifndef GD32F3X0_CEC_H +#define GD32F3X0_CEC_H + +#include "gd32f3x0.h" + +/* CEC definitions */ +#define CEC CEC_BASE /*!< CEC base address */ + +/* registers definitions */ +#define CEC_CTL REG32(CEC + 0x00000000U) /*!< CEC control register */ +#define CEC_CFG REG32(CEC + 0x00000004U) /*!< CEC configuration register */ +#define CEC_TDATA REG32(CEC + 0x00000008U) /*!< CEC transmit data register */ +#define CEC_RDATA REG32(CEC + 0x0000000CU) /*!< CEC receive data register */ +#define CEC_INTF REG32(CEC + 0x00000010U) /*!< CEC interrupt flag Register */ +#define CEC_INTEN REG32(CEC + 0x00000014U) /*!< CEC interrupt enable register */ + +/* bits definitions */ +/* CEC_CTL */ +#define CEC_CTL_CECEN BIT(0) /*!< enable or disable HDMI-CEC controller bit */ +#define CEC_CTL_STAOM BIT(1) /*!< start of sending a message. */ +#define CEC_CTL_ENDOM BIT(2) /*!< ENDOM bit value in the next frame in Tx mode */ + +/* CEC_CFG */ +#define CEC_CFG_SFT BITS(0,2) /*!< signal free time */ +#define CEC_CFG_RTOL BIT(3) /*!< reception bit timing tolerance */ +#define CEC_CFG_BRES BIT(4) /*!< whether stop receive message when detected BRE */ +#define CEC_CFG_BREG BIT(5) /*!< generate Error-bit when detected BRE in singlecast */ +#define CEC_CFG_BPLEG BIT(6) /*!< generate Error-bit when detected BPLE in singlecast */ +#define CEC_CFG_BCNG BIT(7) /*!< do not generate Error-bit in broadcast message */ +#define CEC_CFG_SFTOPT BIT(8) /*!< the SFT start option bit */ +#define CEC_CFG_OWN_ADDRESS BITS(16,30) /*!< own address */ +#define CEC_CFG_LMEN BIT(31) /*!< listen mode enable bit */ + +/* CEC_TDATA */ +#define CEC_TDATA_TDATA BITS(0,7) /*!< Tx data register */ + +/* CEC_RDATA */ +#define CEC_RDATA_RDATA BITS(0,7) /*!< Rx data register */ + +/* CEC_INTF */ +#define CEC_INTF_BR BIT(0) /*!< Rx-byte data received */ +#define CEC_INTF_REND BIT(1) /*!< end of reception */ +#define CEC_INTF_RO BIT(2) /*!< Rx overrun */ +#define CEC_INTF_BRE BIT(3) /*!< bit rising error */ +#define CEC_INTF_BPSE BIT(4) /*!< short bit period error */ +#define CEC_INTF_BPLE BIT(5) /*!< long bit period error */ +#define CEC_INTF_RAE BIT(6) /*!< Rx ACK error */ +#define CEC_INTF_ARBF BIT(7) /*!< arbitration fail */ +#define CEC_INTF_TBR BIT(8) /*!< Tx-byte data request */ +#define CEC_INTF_TEND BIT(9) /*!< transmission successfully end */ +#define CEC_INTF_TU BIT(10) /*!< Tx data buffer underrun */ +#define CEC_INTF_TERR BIT(11) /*!< Tx-error */ +#define CEC_INTF_TAERR BIT(12) /*!< Tx ACK error flag */ + +/* CEC_INTEN */ +#define CEC_INTEN_BRIE BIT(0) /*!< BR interrupt enable */ +#define CEC_INTEN_RENDIE BIT(1) /*!< REND interrupt enable */ +#define CEC_INTEN_ROIE BIT(2) /*!< RO interrupt enable */ +#define CEC_INTEN_BREIE BIT(3) /*!< BRE interrupt enable. */ +#define CEC_INTEN_BPSEIE BIT(4) /*!< BPSE interrupt enable */ +#define CEC_INTEN_BPLEIE BIT(5) /*!< BPLE interrupt enable. */ +#define CEC_INTEN_RAEIE BIT(6) /*!< RAE interrupt enable */ +#define CEC_INTEN_ARBFIE BIT(7) /*!< ARBF interrupt enable */ +#define CEC_INTEN_TBRIE BIT(8) /*!< TBR interrupt enable */ +#define CEC_INTEN_TENDIE BIT(9) /*!< TEND interrupt enable */ +#define CEC_INTEN_TUIE BIT(10) /*!< TU interrupt enable */ +#define CEC_INTEN_TERRIE BIT(11) /*!< TE interrupt enable */ +#define CEC_INTEN_TAERRIE BIT(12) /*!< TAE interrupt enable */ + +/* constants definitions */ +/* signal free time */ +#define CFG_SFT(regval) (BITS(0, 2) & ((regval) << 0U)) +#define CEC_SFT_PROTOCOL_PERIOD CFG_SFT(0) /*!< the signal free time will perform as HDMI-CEC protocol description */ +#define CEC_SFT_1POINT5_PERIOD CFG_SFT(1) /*!< 1.5 nominal data bit periods */ +#define CEC_SFT_2POINT5_PERIOD CFG_SFT(2) /*!< 2.5 nominal data bit periods */ +#define CEC_SFT_3POINT5_PERIOD CFG_SFT(3) /*!< 3.5 nominal data bit periods */ +#define CEC_SFT_4POINT5_PERIOD CFG_SFT(4) /*!< 4.5 nominal data bit periods */ +#define CEC_SFT_5POINT5_PERIOD CFG_SFT(5) /*!< 5.5 nominal data bit periods */ +#define CEC_SFT_6POINT5_PERIOD CFG_SFT(6) /*!< 6.5 nominal data bit periods */ +#define CEC_SFT_7POINT5_PERIOD CFG_SFT(7) /*!< 7.5 nominal data bit periods */ + +/* signal free time start option */ +#define CEC_SFT_START_STAOM ((uint32_t)0x00000000U) /*!< signal free time counter starts counting when STAOM is asserted */ +#define CEC_SFT_START_LAST CEC_CFG_SFTOPT /*!< signal free time counter starts automatically after transmission/reception end */ + +/* own address */ +#define CEC_OWN_ADDRESS_CLEAR ((uint32_t)0x00000000U) /*!< own address is cleared */ +#define CEC_OWN_ADDRESS0 BIT(16) /*!< own address is 0 */ +#define CEC_OWN_ADDRESS1 BIT(17) /*!< own address is 1 */ +#define CEC_OWN_ADDRESS2 BIT(18) /*!< own address is 2 */ +#define CEC_OWN_ADDRESS3 BIT(19) /*!< own address is 3 */ +#define CEC_OWN_ADDRESS4 BIT(20) /*!< own address is 4 */ +#define CEC_OWN_ADDRESS5 BIT(21) /*!< own address is 5 */ +#define CEC_OWN_ADDRESS6 BIT(22) /*!< own address is 6 */ +#define CEC_OWN_ADDRESS7 BIT(23) /*!< own address is 7 */ +#define CEC_OWN_ADDRESS8 BIT(24) /*!< own address is 8 */ +#define CEC_OWN_ADDRESS9 BIT(25) /*!< own address is 9 */ +#define CEC_OWN_ADDRESS10 BIT(26) /*!< own address is 10 */ +#define CEC_OWN_ADDRESS11 BIT(27) /*!< own address is 11 */ +#define CEC_OWN_ADDRESS12 BIT(28) /*!< own address is 12 */ +#define CEC_OWN_ADDRESS13 BIT(29) /*!< own address is 13 */ +#define CEC_OWN_ADDRESS14 BIT(30) /*!< own address is 14 */ + +/* error-bit generate */ +#define CEC_BROADCAST_ERROR_BIT_ON ((uint32_t)0x00000000U) /*!< generate Error-bit in broadcast */ +#define CEC_BROADCAST_ERROR_BIT_OFF CEC_CFG_BCNG /*!< do not generate Error-bit in broadcast */ +#define CEC_LONG_PERIOD_ERROR_BIT_OFF ((uint32_t)0x00000000U) /*!< generate Error-bit on long bit period error */ +#define CEC_LONG_PERIOD_ERROR_BIT_ON CEC_CFG_BPLEG /*!< do not generate Error-bit on long bit period error */ +#define CEC_RISING_PERIOD_ERROR_BIT_OFF ((uint32_t)0x00000000U) /*!< generate Error-bit on bit rising error */ +#define CEC_RISING_PERIOD_ERROR_BIT_ON CEC_CFG_BREG /*!< do not generate Error-bit on bit rising error */ + +/* whether stop receive message when detected bit rising error */ +#define CEC_STOP_RISING_ERROR_BIT_ON ((uint32_t)0x00000000U) /*!< stop reception when detected bit rising error */ +#define CEC_STOP_RISING_ERROR_BIT_OFF ((uint32_t)0x00000001U) /*!< do not stop reception when detected bit rising error */ + +/* flag bits */ +#define CEC_FLAG_BR CEC_INTF_BR /*!< RX-byte data received */ +#define CEC_FLAG_REND CEC_INTF_REND /*!< end of reception */ +#define CEC_FLAG_RO CEC_INTF_RO /*!< RX overrun */ +#define CEC_FLAG_BRE CEC_INTF_BRE /*!< bit rising error */ +#define CEC_FLAG_BPSE CEC_INTF_BPSE /*!< short bit period error */ +#define CEC_FLAG_BPLE CEC_INTF_BPLE /*!< long bit period error */ +#define CEC_FLAG_RAE CEC_INTF_RAE /*!< RX ACK error */ +#define CEC_FLAG_ARBF CEC_INTF_ARBF /*!< arbitration lost */ +#define CEC_FLAG_TBR CEC_INTF_TBR /*!< TX-byte data request */ +#define CEC_FLAG_TEND CEC_INTF_TEND /*!< transmission successfully end */ +#define CEC_FLAG_TU CEC_INTF_TU /*!< TX data buffer underrun */ +#define CEC_FLAG_TERR CEC_INTF_TERR /*!< TX-error */ +#define CEC_FLAG_TAERR CEC_INTF_TAERR /*!< TX ACK error flag */ + +/* interrupt flag bits */ +#define CEC_INT_FLAG_BR CEC_INTF_BR /*!< RX-byte data received */ +#define CEC_INT_FLAG_REND CEC_INTF_REND /*!< end of reception */ +#define CEC_INT_FLAG_RO CEC_INTF_RO /*!< RX overrun */ +#define CEC_INT_FLAG_BRE CEC_INTF_BRE /*!< bit rising error */ +#define CEC_INT_FLAG_BPSE CEC_INTF_BPSE /*!< short bit period error */ +#define CEC_INT_FLAG_BPLE CEC_INTF_BPLE /*!< long bit period error */ +#define CEC_INT_FLAG_RAE CEC_INTF_RAE /*!< RX ACK error */ +#define CEC_INT_FLAG_ARBF CEC_INTF_ARBF /*!< arbitration lost */ +#define CEC_INT_FLAG_TBR CEC_INTF_TBR /*!< TX-byte data request */ +#define CEC_INT_FLAG_TEND CEC_INTF_TEND /*!< transmission successfully end */ +#define CEC_INT_FLAG_TU CEC_INTF_TU /*!< TX data buffer underrun */ +#define CEC_INT_FLAG_TERR CEC_INTF_TERR /*!< TX-error */ +#define CEC_INT_FLAG_TAERR CEC_INTF_TAERR /*!< TX ACK error flag */ + +/* interrupt enable bits */ +#define CEC_INT_BR CEC_INTEN_BRIE /*!< RBR interrupt enable */ +#define CEC_INT_REND CEC_INTEN_RENDIE /*!< REND interrupt enable */ +#define CEC_INT_RO CEC_INTEN_ROIE /*!< RO interrupt enable */ +#define CEC_INT_BRE CEC_INTEN_BREIE /*!< RBRE interrupt enable. */ +#define CEC_INT_BPSE CEC_INTEN_BPSEIE /*!< RSBPE interrupt enable */ +#define CEC_INT_BPLE CEC_INTEN_BPLEIE /*!< RLBPE interrupt enable. */ +#define CEC_INT_RAE CEC_INTEN_RAEIE /*!< RAE interrupt enable */ +#define CEC_INT_ARBF CEC_INTEN_ARBFIE /*!< ALRLST interrupt enable */ +#define CEC_INT_TBR CEC_INTEN_TBRIE /*!< TBR interrupt enable */ +#define CEC_INT_TEND CEC_INTEN_TENDIE /*!< TEND interrupt enable */ +#define CEC_INT_TU CEC_INTEN_TUIE /*!< TU interrupt enable */ +#define CEC_INT_TERR CEC_INTEN_TERRIE /*!< TE interrupt enable */ +#define CEC_INT_TAERR CEC_INTEN_TAERRIE /*!< TAE interrupt enable */ + +/* function declarations */ +/* reset HDMI-CEC controller */ +void cec_deinit(void); +/* configure signal free time,the signal free time counter start option,own address */ +void cec_init(uint32_t sftmopt, uint32_t sft, uint32_t address); +/* configure generate Error-bit, whether stop receive message when detected bit rising error */ +void cec_error_config(uint32_t broadcast, uint32_t singlecast_lbpe, uint32_t singlecast_bre, uint32_t rxbrestp); +/* enable HDMI-CEC controller */ +void cec_enable(void); +/* disable HDMI-CEC controller */ +void cec_disable(void); + +/* start CEC message transmission */ +void cec_transmission_start(void); +/* end CEC message transmission */ +void cec_transmission_end(void); +/* enable CEC listen mode */ +void cec_listen_mode_enable(void); +/* disable CEC listen mode */ +void cec_listen_mode_disable(void); +/* configure and clear own address */ +void cec_own_address_config(uint32_t address); +/* configure signal free time and the signal free time counter start option */ +void cec_sft_config(uint32_t sftmopt,uint32_t sft); +/* configure generate Error-bit when detected some abnormal situation or not */ +void cec_generate_errorbit_config(uint32_t broadcast, uint32_t singlecast_lbpe, uint32_t singlecast_bre); +/* whether stop receive message when detected bit rising error */ +void cec_stop_receive_bre_config(uint32_t rxbrestp); +/* enable reception bit timing tolerance */ +void cec_reception_tolerance_enable(void); +/* disable reception bit timing tolerance */ +void cec_reception_tolerance_disable(void); +/* send a data by the CEC peripheral */ +void cec_data_send(uint8_t data); +/* receive a data by the CEC peripheral */ +uint8_t cec_data_receive(void); + +/* enable interrupt */ +void cec_interrupt_enable(uint32_t flag); +/* disable interrupt */ +void cec_interrupt_disable(uint32_t flag); +/* get CEC status */ +FlagStatus cec_flag_get(uint32_t flag); +/* clear CEC status */ +void cec_flag_clear(uint32_t flag); +/* get CEC int flag and status */ +FlagStatus cec_interrupt_flag_get(uint32_t flag); +/* clear CEC int flag and status */ +void cec_interrupt_flag_clear(uint32_t flag); + +#endif /* GD32F3X0_CEC_H */ + +#endif /* GD32F350 */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_cmp.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_cmp.h new file mode 100644 index 0000000000..19f64e03e7 --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_cmp.h @@ -0,0 +1,219 @@ +/*! + \file gd32f3x0_cmp.h + \brief definitions for the CMP + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F3X0_CMP_H +#define GD32F3X0_CMP_H + +#include "gd32f3x0.h" + +/* CMP definitions */ +#define CMP CMP_BASE /*!< CMP base address */ + +/* registers definitions */ +#define CMP_CS REG32((CMP) + 0x00000000U) /*!< CMP control and status register */ + +/* CMP_CS bits definitions */ +#define CMP_CS_CMP0EN BIT(0) /*!< CMP0 enable */ +#define CMP_CS_CMP0SW BIT(1) /*!< CMP0 switch */ +#define CMP_CS_CMP0M BITS(2,3) /*!< CMP0 mode */ +#define CMP_CS_CMP0MSEL BITS(4,6) /*!< COMP0_M input selection */ +#define CMP_CS_CMP0OSEL BITS(8,10) /*!< CMP0 output selection */ +#define CMP_CS_CMP0PL BIT(11) /*!< polarity of CMP0 output */ +#define CMP_CS_CMP0HST BITS(12,13) /*!< CMP0 hysteresis */ +#define CMP_CS_CMP0O BIT(14) /*!< CMP0 output */ +#define CMP_CS_CMP0LK BIT(15) /*!< CMP0 lock */ +#define CMP_CS_CMP1EN BIT(16) /*!< CMP1 enable */ +#define CMP_CS_CMP1M BITS(18,19) /*!< CMP1 mode */ +#define CMP_CS_CMP1MSEL BITS(20,22) /*!< CMP1_M input selection */ +#define CMP_CS_WNDEN BIT(23) /*!< window mode enable */ +#define CMP_CS_CMP1OSEL BITS(24,26) /*!< CMP1 output selection */ +#define CMP_CS_CMP1PL BIT(27) /*!< polarity of CMP1 output */ +#define CMP_CS_CMP1HST BITS(28,29) /*!< CMP1 hysteresis */ +#define CMP_CS_CMP1O BIT(30) /*!< CMP1 output */ +#define CMP_CS_CMP1LK BIT(31) /*!< CMP1 lock */ + +/* consts definitions */ +/* operating mode */ +typedef enum{ + CMP_HIGHSPEED = 0, /*!< high speed mode */ + CMP_MIDDLESPEED, /*!< medium speed mode */ + CMP_LOWSPEED, /*!< low speed mode */ + CMP_VERYLOWSPEED /*!< very-low speed mode */ +}operating_mode_enum; + +/* inverting input */ +typedef enum{ + CMP_1_4VREFINT = 0, /*!< VREFINT /4 input */ + CMP_1_2VREFINT, /*!< VREFINT /2 input */ + CMP_3_4VREFINT, /*!< VREFINT *3/4 input */ + CMP_VREFINT, /*!< VREFINT input */ + CMP_DAC, /*!< PA4 (DAC) input */ + CMP_PA5, /*!< PA5 input */ + CMP_PA_0_2 /*!< PA0 or PA2 input */ +}inverting_input_enum; + +/* hysteresis */ +typedef enum{ + CMP_HYSTERESIS_NO = 0, /*!< output no hysteresis */ + CMP_HYSTERESIS_LOW, /*!< output low hysteresis */ + CMP_HYSTERESIS_MIDDLE, /*!< output middle hysteresis */ + CMP_HYSTERESIS_HIGH /*!< output high hysteresis */ +}cmp_hysteresis_enum; + +/* output */ +typedef enum{ + CMP_OUTPUT_NONE = 0, /*!< output no selection */ + CMP_OUTPUT_TIMER0BKIN, /*!< TIMER 0 break input */ + CMP_OUTPUT_TIMER0IC0, /*!< TIMER 0 channel0 input capture */ + CMP_OUTPUT_TIMER0OCPRECLR, /*!< TIMER 0 OCPRE_CLR input */ + CMP_OUTPUT_TIMER1IC3, /*!< TIMER 1 channel3 input capture */ + CMP_OUTPUT_TIMER1OCPRECLR, /*!< TIMER 1 OCPRE_CLR input */ + CMP_OUTPUT_TIMER2IC0, /*!< TIMER 2 channel0 input capture */ + CMP_OUTPUT_TIMER2OCPRECLR /*!< TIMER 2 OCPRE_CLR input */ +}cmp_output_enum; + +/* CMP0 mode */ +#define CS_CMP0M(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) +#define CS_CMP0M_HIGHSPEED CS_CMP0M(0) /*!< CMP0 mode high speed */ +#define CS_CMP0M_MIDDLESPEED CS_CMP0M(1) /*!< CMP0 mode middle speed */ +#define CS_CMP0M_LOWSPEED CS_CMP0M(2) /*!< CMP0 mode low speed */ +#define CS_CMP0M_VERYLOWSPEED CS_CMP0M(3) /*!< CMP0 mode very low speed */ + +/* comparator 0 inverting input */ +#define CS_CMP0MSEL(regval) (BITS(4,6) & ((uint32_t)(regval) << 4)) +#define CS_CMP0MSEL_1_4VREFINT CS_CMP0MSEL(0) /*!< CMP0 inverting input 1/4 Vrefint */ +#define CS_CMP0MSEL_1_2VREFINT CS_CMP0MSEL(1) /*!< CMP0 inverting input 1/2 Vrefint */ +#define CS_CMP0MSEL_3_4VREFINT CS_CMP0MSEL(2) /*!< CMP0 inverting input 3/4 Vrefint */ +#define CS_CMP0MSEL_VREFINT CS_CMP0MSEL(3) /*!< CMP0 inverting input Vrefint */ +#define CS_CMP0MSEL_DAC CS_CMP0MSEL(4) /*!< CMP0 inverting input DAC*/ +#define CS_CMP0MSEL_PA5 CS_CMP0MSEL(5) /*!< CMP0 inverting input PA5*/ +#define CS_CMP0MSEL_PA0 CS_CMP0MSEL(6) /*!< CMP0 inverting input PA0*/ + +/* CMP0 output */ +#define CS_CMP0OSEL(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) +#define CS_CMP0OSEL_OUTPUT_NONE CS_CMP0OSEL(0) /*!< CMP0 output none */ +#define CS_CMP0OSEL_OUTPUT_TIMER0BKIN CS_CMP0OSEL(1) /*!< CMP0 output TIMER 0 break input */ +#define CS_CMP0OSEL_OUTPUT_TIMER0IC0 CS_CMP0OSEL(2) /*!< CMP0 output TIMER 0 channel 0 input capture */ +#define CS_CMP0OSEL_OUTPUT_TIMER0OCPRECLR CS_CMP0OSEL(3) /*!< CMP0 output TIMER 0 ocpreclear input */ +#define CS_CMP0OSEL_OUTPUT_TIMER1IC3 CS_CMP0OSEL(4) /*!< CMP0 output TIMER 1 channel 3 input capture */ +#define CS_CMP0OSEL_OUTPUT_TIMER1OCPRECLR CS_CMP0OSEL(5) /*!< CMP0 output TIMER 1 ocpreclear input */ +#define CS_CMP0OSEL_OUTPUT_TIMER2IC0 CS_CMP0OSEL(6) /*!< CMP0 output TIMER 2 channle 0 input capture */ +#define CS_CMP0OSEL_OUTPUT_TIMER2OCPRECLR CS_CMP0OSEL(7) /*!< CMP0 output TIMER 2 ocpreclear input */ + +/* CMP0 hysteresis */ +#define CS_CMP0HST(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) +#define CS_CMP0HST_HYSTERESIS_NO CS_CMP0HST(0) /*!< CMP0 output no hysteresis */ +#define CS_CMP0HST_HYSTERESIS_LOW CS_CMP0HST(1) /*!< CMP0 output low hysteresis */ +#define CS_CMP0HST_HYSTERESIS_MIDDLE CS_CMP0HST(2) /*!< CMP0 output middle hysteresis */ +#define CS_CMP0HST_HYSTERESIS_HIGH CS_CMP0HST(3) /*!< CMP0 output high hysteresis */ + +/* CMP1 mode */ +#define CS_CMP1M(regval) (BITS(18,19) & ((uint32_t)(regval) << 18)) +#define CS_CMP1M_HIGHSPEED CS_CMP1M(0) /*!< CMP1 mode high speed */ +#define CS_CMP1M_MIDDLESPEED CS_CMP1M(1) /*!< CMP1 mode middle speed */ +#define CS_CMP1M_LOWSPEED CS_CMP1M(2) /*!< CMP1 mode low speed */ +#define CS_CMP1M_VERYLOWSPEED CS_CMP1M(3) /*!< CMP1 mode very low speed */ + +/* CMP1 inverting input */ +#define CS_CMP1MSEL(regval) (BITS(20,22) & ((uint32_t)(regval) << 20)) +#define CS_CMP1MSEL_1_4VREFINT CS_CMP1MSEL(0) /*!< CMP1 inverting input 1/4 Vrefint */ +#define CS_CMP1MSEL_1_2VREFINT CS_CMP1MSEL(1) /*!< CMP1 inverting input 1/2 Vrefint */ +#define CS_CMP1MSEL_3_4VREFINT CS_CMP1MSEL(2) /*!< CMP1 inverting input 3/4 Vrefint */ +#define CS_CMP1MSEL_VREFINT CS_CMP1MSEL(3) /*!< CMP1 inverting input Vrefint */ +#define CS_CMP1MSEL_DAC CS_CMP1MSEL(4) /*!< CMP1 inverting input DAC */ +#define CS_CMP1MSEL_PA5 CS_CMP1MSEL(5) /*!< CMP1 inverting input PA5 */ +#define CS_CMP1MSEL_PA2 CS_CMP1MSEL(6) /*!< CMP1 inverting input PA2 */ + +/* CMP1 output */ +#define CS_CMP1OSEL(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) +#define CS_CMP1OSEL_OUTPUT_NONE CS_CMP1OSEL(0) /*!< CMP1 output none */ +#define CS_CMP1OSEL_OUTPUT_TIMER0BKIN CS_CMP1OSEL(1) /*!< CMP1 output TIMER 0 break input */ +#define CS_CMP1OSEL_OUTPUT_TIMER0IC0 CS_CMP1OSEL(2) /*!< CMP1 output TIMER 0 channel 0 input capture */ +#define CS_CMP1OSEL_OUTPUT_TIMER0OCPRECLR CS_CMP1OSEL(3) /*!< CMP1 output TIMER 0 ocpreclear input */ +#define CS_CMP1OSEL_OUTPUT_TIMER1IC3 CS_CMP1OSEL(4) /*!< CMP1 output TIMER 1 channel 3 input capture */ +#define CS_CMP1OSEL_OUTPUT_TIMER1OCPRECLR CS_CMP1OSEL(5) /*!< CMP1 output TIMER 1 ocpreclear input */ +#define CS_CMP1OSEL_OUTPUT_TIMER2IC0 CS_CMP1OSEL(6) /*!< CMP1 output TIMER 2 channle 0 input capture */ +#define CS_CMP1OSEL_OUTPUT_TIMER2OCPRECLR CS_CMP1OSEL(7) /*!< CMP1 output TIMER 2 ocpreclear input */ + +/* CMP1 hysteresis */ +#define CS_CMP1HST(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) +#define CS_CMP1HST_HSTHYSTERESIS_NO CS_CMP1HST(0) /*!< CMP1 output no hysteresis */ +#define CS_CMP1HST_HYSTERESIS_LOW CS_CMP1HST(1) /*!< CMP1 output low hysteresis */ +#define CS_CMP1HST_HYSTERESIS_MIDDLE CS_CMP1HST(2) /*!< CMP1 output middle hysteresis */ +#define CS_CMP1HST_HYSTERESIS_HIGH CS_CMP1HST(3) /*!< CMP1 output high hysteresis */ + +/* comparator x definitions */ +#define CMP0 ((uint32_t)0x00000000) /*!< comparator 0 */ +#define CMP1 ((uint32_t)0x00000010) /*!< comparator 1 */ + +/* comparator output level */ +#define CMP_OUTPUTLEVEL_HIGH ((uint32_t)0x00000001) /*!< comparator output high */ +#define CMP_OUTPUTLEVEL_LOW ((uint32_t)0x00000000) /*!< comparator output low */ + +/* output polarity of comparator */ +#define CMP_OUTPUT_POLARITY_INVERTED ((uint32_t)0x00000001) /*!< output is inverted */ +#define CMP_OUTPUT_POLARITY_NOINVERTED ((uint32_t)0x00000000) /*!< output is not inverted */ + +/* function declarations */ + +/* initialization functions */ +/* CMP deinit */ +void cmp_deinit(void); +/* CMP mode init */ +void cmp_mode_init(uint32_t cmp_periph, operating_mode_enum operating_mode, inverting_input_enum inverting_input, cmp_hysteresis_enum output_hysteresis); +/* CMP output init */ +void cmp_output_init(uint32_t cmp_periph, cmp_output_enum output_slection, uint32_t output_polarity); + +/* enable functions */ +/* enable CMP */ +void cmp_enable(uint32_t cmp_periph); +/* disable CMP */ +void cmp_disable(uint32_t cmp_periph); +/* enable CMP switch */ +void cmp_switch_enable(void); +/* disable CMP switch */ +void cmp_switch_disable(void); +/* enable the window mode */ +void cmp_window_enable(void); +/* disable the window mode */ +void cmp_window_disable(void); +/* lock the CMP */ +void cmp_lock_enable(uint32_t cmp_periph); + +/* output functions */ +/* get output level */ +uint32_t cmp_output_level_get(uint32_t cmp_periph); + +#endif /* GD32F3X0_CMP_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_crc.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_crc.h new file mode 100644 index 0000000000..398af82238 --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_crc.h @@ -0,0 +1,119 @@ +/*! + \file gd32f3x0_crc.h + \brief definitions for the CRC + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F3X0_CRC_H +#define GD32F3X0_CRC_H + +#include "gd32f3x0.h" + +/* CRC definitions */ +#define CRC CRC_BASE + +/* registers definitions */ +#define CRC_DATA REG32(CRC + 0x00000000U) /*!< CRC data register */ +#define CRC_FDATA REG32(CRC + 0x00000004U) /*!< CRC free data register */ +#define CRC_CTL REG32(CRC + 0x00000008U) /*!< CRC control register */ +#define CRC_IDATA REG32(CRC + 0x00000010U) /*!< CRC initialization data register */ +#define CRC_POLY REG32(CRC + 0x00000014U) /*!< CRC polynomial register */ + +/* bits definitions */ +/* CRC_DATA */ +#define CRC_DATA_DATA BITS(0,31) /*!< CRC data bits */ + +/* CRC_FDATA */ +#define CRC_FDATA_FDATA BITS(0,7) /*!< CRC free data bits */ + +/* CRC_CTL */ +#define CRC_CTL_RST BIT(0) /*!< CRC reset bit */ +#define CRC_CTL_PS BITS(3,4) /*!< size of polynomial function bits */ +#define CRC_CTL_REV_I BITS(5,6) /*!< input data reverse function bits */ +#define CRC_CTL_REV_O BIT(7) /*!< output data reverse function bit */ + +/* CRC_INIT */ +#define CRC_IDATA_IDATA BITS(0,31) /*!< CRC initialization data bits */ + +/* CRC_POLY */ +#define CRC_POLY_POLY BITS(0,31) /*!< CRC polynomial value bits */ + +/* constants definitions */ +/* size of polynomial function */ +#define CTL_PS(regval) (BITS(3, 4) & ((regval) << 3)) +#define CRC_CTL_PS_32 CTL_PS(0) /*!< 32-bit polynomial for CRC calculation */ +#define CRC_CTL_PS_16 CTL_PS(1) /*!< 16-bit polynomial for CRC calculation */ +#define CRC_CTL_PS_8 CTL_PS(2) /*!< 8-bit polynomial for CRC calculation */ +#define CRC_CTL_PS_7 CTL_PS(3) /*!< 7-bit polynomial for CRC calculation */ + +/* input data reverse function */ +#define CTL_REV_I(regval) (BITS(5, 6) & ((regval) << 5)) +#define CRC_INPUT_DATA_NOT CTL_REV_I(0) /*!< input data not reverse */ +#define CRC_INPUT_DATA_BYTE CTL_REV_I(1) /*!< input data reversed by byte type */ +#define CRC_INPUT_DATA_HALFWORD CTL_REV_I(2) /*!< input data reversed by half-word type */ +#define CRC_INPUT_DATA_WORD CTL_REV_I(3) /*!< input data reversed by word type */ + +/* function declarations */ +/* deinit CRC calculation unit */ +void crc_deinit(void); + +/* enable the reverse operation of output data */ +void crc_reverse_output_data_enable(void); +/* disable the reverse operation of output data */ +void crc_reverse_output_data_disable(void); + +/* reset data register to the value of initializaiton data register */ +void crc_data_register_reset(void); +/* read the data register */ +uint32_t crc_data_register_read(void); + +/* read the free data register */ +uint8_t crc_free_data_register_read(void); +/* write the free data register */ +void crc_free_data_register_write(uint8_t free_data); + +/* write the initial value register */ +void crc_init_data_register_write(uint32_t init_data); +/* configure the CRC input data function */ +void crc_input_data_reverse_config(uint32_t data_reverse); + +/* configure the CRC size of polynomial function */ +void crc_polynomial_size_set(uint32_t poly_size); +/* configure the CRC polynomial value function */ +void crc_polynomial_set(uint32_t poly); + +/* CRC calculate a 32-bit data */ +uint32_t crc_single_data_calculate(uint32_t sdata); +/* CRC calculate a 32-bit data array */ +uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size); + +#endif /* GD32F3X0_CRC_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_ctc.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_ctc.h new file mode 100644 index 0000000000..2c8ff14e08 --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_ctc.h @@ -0,0 +1,191 @@ +/*! + \file gd32f3x0_ctc.h + \brief definitions for the CTC + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F3X0_CTC_H +#define GD32F3X0_CTC_H + +#include "gd32f3x0.h" + +/* CTC definitions */ +#define CTC CTC_BASE + +/* registers definitions */ +#define CTC_CTL0 REG32(CTC + 0x00000000U) /*!< CTC control register 0 */ +#define CTC_CTL1 REG32(CTC + 0x00000004U) /*!< CTC control register 1 */ +#define CTC_STAT REG32(CTC + 0x00000008U) /*!< CTC status register */ +#define CTC_INTC REG32(CTC + 0x0000000CU) /*!< CTC interrupt clear register */ + +/* bits definitions */ +/* CTC_CTL0 */ +#define CTC_CTL0_CKOKIE BIT(0) /*!< clock trim OK(CKOKIF) interrupt enable */ +#define CTC_CTL0_CKWARNIE BIT(1) /*!< clock trim warning(CKWARNIF) interrupt enable */ +#define CTC_CTL0_ERRIE BIT(2) /*!< error(ERRIF) interrupt enable */ +#define CTC_CTL0_EREFIE BIT(3) /*!< EREFIF interrupt enable */ +#define CTC_CTL0_CNTEN BIT(5) /*!< CTC counter enable */ +#define CTC_CTL0_AUTOTRIM BIT(6) /*!< hardware automatically trim mode */ +#define CTC_CTL0_SWREFPUL BIT(7) /*!< software reference source sync pulse */ +#define CTC_CTL0_TRIMVALUE BITS(8,13) /*!< IRC48M trim value */ + +/* CTC_CTL1 */ +#define CTC_CTL1_RLVALUE BITS(0,15) /*!< CTC counter reload value */ +#define CTC_CTL1_CKLIM BITS(16,23) /*!< clock trim base limit value */ +#define CTC_CTL1_REFPSC BITS(24,26) /*!< reference signal source prescaler */ +#define CTC_CTL1_REFSEL BITS(28,29) /*!< reference signal source selection */ +#define CTC_CTL1_REFPOL BIT(31) /*!< reference signal source polarity */ + +/* CTC_STAT */ +#define CTC_STAT_CKOKIF BIT(0) /*!< clock trim OK interrupt flag */ +#define CTC_STAT_CKWARNIF BIT(1) /*!< clock trim warning interrupt flag */ +#define CTC_STAT_ERRIF BIT(2) /*!< error interrupt flag */ +#define CTC_STAT_EREFIF BIT(3) /*!< expect reference interrupt flag */ +#define CTC_STAT_CKERR BIT(8) /*!< clock trim error bit */ +#define CTC_STAT_REFMISS BIT(9) /*!< reference sync pulse miss */ +#define CTC_STAT_TRIMERR BIT(10) /*!< trim value error bit */ +#define CTC_STAT_REFDIR BIT(15) /*!< CTC trim counter direction when reference sync pulse occurred */ +#define CTC_STAT_REFCAP BITS(16,31) /*!< CTC counter capture when reference sync pulse occurred */ + +/* CTC_INTC */ +#define CTC_INTC_CKOKIC BIT(0) /*!< CKOKIF interrupt clear bit */ +#define CTC_INTC_CKWARNIC BIT(1) /*!< CKWARNIF interrupt clear bit */ +#define CTC_INTC_ERRIC BIT(2) /*!< ERRIF interrupt clear bit */ +#define CTC_INTC_EREFIC BIT(3) /*!< EREFIF interrupt clear bit */ + +/* constants definitions */ +#define CTL0_TRIMVALUE(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) +#define CTL1_CKLIM(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) +#define GET_STAT_REFCAP(regval) GET_BITS((regval),16,31) +#define GET_CTL0_TRIMVALUE(regval) GET_BITS((regval),8,13) + +/* hardware automatically trim mode definitions */ +#define CTC_HARDWARE_TRIM_MODE_ENABLE CTC_CTL0_AUTOTRIM /*!< hardware automatically trim mode enable*/ +#define CTC_HARDWARE_TRIM_MODE_DISABLE ((uint32_t)0x00000000U) /*!< hardware automatically trim mode disable*/ + +/* reference signal source polarity definitions */ +#define CTC_REFSOURCE_POLARITY_FALLING CTC_CTL1_REFPOL /*!< reference signal source polarity is falling edge*/ +#define CTC_REFSOURCE_POLARITY_RISING ((uint32_t)0x00000000U) /*!< reference signal source polarity is rising edge*/ + +/* reference signal source selection definitions */ +#define CTL1_REFSEL(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) +#define CTC_REFSOURCE_GPIO CTL1_REFSEL(0) /*!< GPIO is selected */ +#define CTC_REFSOURCE_LXTAL CTL1_REFSEL(1) /*!< LXTAL is clock selected */ +#define CTC_REFSOURCE_USBSOF CTL1_REFSEL(2) /*!< USBFSSOF selected */ + +/* reference signal source prescaler definitions */ +#define CTL1_REFPSC(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) +#define CTC_REFSOURCE_PSC_OFF CTL1_REFPSC(0) /*!< reference signal not divided */ +#define CTC_REFSOURCE_PSC_DIV2 CTL1_REFPSC(1) /*!< reference signal divided by 2 */ +#define CTC_REFSOURCE_PSC_DIV4 CTL1_REFPSC(2) /*!< reference signal divided by 4 */ +#define CTC_REFSOURCE_PSC_DIV8 CTL1_REFPSC(3) /*!< reference signal divided by 8 */ +#define CTC_REFSOURCE_PSC_DIV16 CTL1_REFPSC(4) /*!< reference signal divided by 16 */ +#define CTC_REFSOURCE_PSC_DIV32 CTL1_REFPSC(5) /*!< reference signal divided by 32 */ +#define CTC_REFSOURCE_PSC_DIV64 CTL1_REFPSC(6) /*!< reference signal divided by 64 */ +#define CTC_REFSOURCE_PSC_DIV128 CTL1_REFPSC(7) /*!< reference signal divided by 128 */ + +/* CTC interrupt enable definitions */ +#define CTC_INT_CKOK CTC_CTL0_CKOKIE /*!< clock trim OK interrupt enable */ +#define CTC_INT_CKWARN CTC_CTL0_CKWARNIE /*!< clock trim warning interrupt enable */ +#define CTC_INT_ERR CTC_CTL0_ERRIE /*!< error interrupt enable */ +#define CTC_INT_EREF CTC_CTL0_EREFIE /*!< expect reference interrupt enable */ + +/* CTC interrupt source definitions */ +#define CTC_INT_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK interrupt flag */ +#define CTC_INT_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning interrupt flag */ +#define CTC_INT_FLAG_ERR CTC_STAT_ERRIF /*!< error interrupt flag */ +#define CTC_INT_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference interrupt flag */ +#define CTC_INT_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */ +#define CTC_INT_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */ +#define CTC_INT_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error */ + +/* CTC flag definitions */ +#define CTC_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK flag */ +#define CTC_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning flag */ +#define CTC_FLAG_ERR CTC_STAT_ERRIF /*!< error flag */ +#define CTC_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference flag */ +#define CTC_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */ +#define CTC_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */ +#define CTC_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error bit */ + +/* function declarations */ +/* initialization functions */ +/* reset ctc clock trim controller */ +void ctc_deinit(void); +/* configure reference signal source polarity */ +void ctc_refsource_polarity_config(uint32_t polarity); +/* select reference signal source */ +void ctc_refsource_signal_select(uint32_t refs); +/* configure reference signal source prescaler */ +void ctc_refsource_prescaler_config(uint32_t prescaler); +/* configure clock trim base limit value */ +void ctc_clock_limit_value_config(uint8_t limit_value); +/* configure CTC counter reload value */ +void ctc_counter_reload_value_config(uint16_t reload_value); +/* enable CTC trim counter */ +void ctc_counter_enable(void); +/* disable CTC trim counter */ +void ctc_counter_disable(void); + +/* function configuration */ +/* configure the IRC48M trim value */ +void ctc_irc48m_trim_value_config(uint8_t trim_value); +/* generate software reference source sync pulse */ +void ctc_software_refsource_pulse_generate(void); +/* configure hardware automatically trim mode */ +void ctc_hardware_trim_mode_config(uint32_t hardmode); + +/* reading functions */ +/* read CTC counter capture value when reference sync pulse occurred */ +uint16_t ctc_counter_capture_value_read(void); +/* read CTC trim counter direction when reference sync pulse occurred */ +FlagStatus ctc_counter_direction_read(void); +/* read CTC counter reload value */ +uint16_t ctc_counter_reload_value_read(void); +/* read the IRC48M trim value */ +uint8_t ctc_irc48m_trim_value_read(void); + +/* interrupt & flag functions */ +/* enable the CTC interrupt */ +void ctc_interrupt_enable(uint32_t interrupt); +/* disable the CTC interrupt */ +void ctc_interrupt_disable(uint32_t interrupt); +/* get CTC flag */ +FlagStatus ctc_flag_get(uint32_t flag); +/* clear CTC flag */ +void ctc_flag_clear(uint32_t flag); +/* get CTC interrupt flag */ +FlagStatus ctc_interrupt_flag_get(uint32_t interrupt); +/* clear CTC interrupt flag */ +void ctc_interrupt_flag_clear(uint32_t interrupt); + +#endif /* GD32F3X0_CTC_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_dac.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_dac.h new file mode 100644 index 0000000000..5975f7724c --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_dac.h @@ -0,0 +1,204 @@ +/*! + \file gd32f3x0_dac.h + \brief definitions for the DAC + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifdef GD32F350 +#ifndef GD32F3X0_DAC_H +#define GD32F3X0_DAC_H + +#include "gd32f3x0.h" + +/* DAC definitions */ +#define DAC DAC_BASE + +/* registers definitions */ +#define DAC_CTL REG32(DAC + (0x00000000U)) /*!< DAC control register */ +#define DAC_SWT REG32(DAC + (0x00000004U)) /*!< DAC software trigger register */ +#define DAC_R12DH REG32(DAC + (0x00000008U)) /*!< DAC 12-bit right-aligned data holding register */ +#define DAC_L12DH REG32(DAC + (0x0000000CU)) /*!< DAC 12-bit left-aligned data holding register */ +#define DAC_R8DH REG32(DAC + (0x00000010U)) /*!< DAC 8-bit right-aligned data holding register */ +#define DAC_DO REG32(DAC + (0x0000002CU)) /*!< DAC output data register */ +#define DAC_STAT REG32(DAC + (0x00000034U)) /*!< DAC status register */ + +/* bits definitions */ +/* DAC_CTL */ +#define DAC_CTL_DEN BIT(0) /*!< DAC enable/disable bit */ +#define DAC_CTL_DBOFF BIT(1) /*!< DAC output buffer turn on/turn off bit */ +#define DAC_CTL_DTEN BIT(2) /*!< DAC trigger enable/disable bit */ +#define DAC_CTL_DTSEL BITS(3,5) /*!< DAC trigger source selection enable/disable bits */ +#define DAC_CTL_DWM BITS(6,7) /*!< DAC noise wave mode */ +#define DAC_CTL_DWBW BITS(8,11) /*!< DAC noise wave bit width */ +#define DAC_CTL_DDMAEN BIT(12) /*!< DAC DMA enable/disable bit */ +#define DAC_CTL_DDUDRIE BIT(13) /*!< DAC DMA underrun interrupt enable/disable bit */ + +/* DAC_SWT */ +#define DAC_SWT_SWTR BIT(0) /*!< DAC software trigger bit,cleared by hardware */ + +/* DAC_R12DH */ +#define DAC_R12DH_DAC_DH BITS(0,11) /*!< DAC 12-bit right-aligned data bits */ + +/* DAC_L12DH */ +#define DAC_L12DH_DAC_DH BITS(4,15) /*!< DAC 12-bit left-aligned data bits */ + +/* DAC_R8DH */ +#define DAC_R8DH_DAC_DH BITS(0,7) /*!< DAC 8-bit right-aligned data bits */ + +/* DAC_DO */ +#define DAC_DO_DAC_DO BITS(0,11) /*!< DAC 12-bit output data bits */ + +/* DAC_STAT */ +#define DAC_STAT_DDUDR BIT(13) /*!< DAC DMA underrun flag */ + +/* constants definitions */ +/* DAC trigger source */ +#define CTL_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) +#define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */ +#define DAC_TRIGGER_T2_TRGO CTL_DTSEL(1) /*!< TIMER2 TRGO */ +#define DAC_TRIGGER_T14_TRGO CTL_DTSEL(3) /*!< TIMER14 TRGO */ +#define DAC_TRIGGER_T1_TRGO CTL_DTSEL(4) /*!< TIMER1 TRGO */ +#define DAC_TRIGGER_EXTI_9 CTL_DTSEL(6) /*!< EXTI interrupt line9 event */ +#define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7) /*!< software trigger */ + +/* DAC noise wave mode */ +#define CTL_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) +#define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disable */ +#define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */ +#define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */ + +/* DAC noise wave bit width */ +#define DWBW(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) +#define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */ +#define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */ +#define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */ +#define DAC_WAVE_BIT_WIDTH_4 DWBW(3) /*!< bit width of the wave signal is 4 */ +#define DAC_WAVE_BIT_WIDTH_5 DWBW(4) /*!< bit width of the wave signal is 5 */ +#define DAC_WAVE_BIT_WIDTH_6 DWBW(5) /*!< bit width of the wave signal is 6 */ +#define DAC_WAVE_BIT_WIDTH_7 DWBW(6) /*!< bit width of the wave signal is 7 */ +#define DAC_WAVE_BIT_WIDTH_8 DWBW(7) /*!< bit width of the wave signal is 8 */ +#define DAC_WAVE_BIT_WIDTH_9 DWBW(8) /*!< bit width of the wave signal is 9 */ +#define DAC_WAVE_BIT_WIDTH_10 DWBW(9) /*!< bit width of the wave signal is 10 */ +#define DAC_WAVE_BIT_WIDTH_11 DWBW(10) /*!< bit width of the wave signal is 11 */ +#define DAC_WAVE_BIT_WIDTH_12 DWBW(11) /*!< bit width of the wave signal is 12 */ + +/* unmask LFSR bits in DAC LFSR noise mode */ +#define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1 /*!< unmask the LFSR bit0 */ +#define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2 /*!< unmask the LFSR bits[1:0] */ +#define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3 /*!< unmask the LFSR bits[2:0] */ +#define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4 /*!< unmask the LFSR bits[3:0] */ +#define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5 /*!< unmask the LFSR bits[4:0] */ +#define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6 /*!< unmask the LFSR bits[5:0] */ +#define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7 /*!< unmask the LFSR bits[6:0] */ +#define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8 /*!< unmask the LFSR bits[7:0] */ +#define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9 /*!< unmask the LFSR bits[8:0] */ +#define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */ +#define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */ +#define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */ + +/* triangle amplitude in DAC triangle noise mode */ +#define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1 /*!< triangle amplitude is 1 */ +#define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2 /*!< triangle amplitude is 3 */ +#define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3 /*!< triangle amplitude is 7 */ +#define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4 /*!< triangle amplitude is 15 */ +#define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5 /*!< triangle amplitude is 31 */ +#define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6 /*!< triangle amplitude is 63 */ +#define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7 /*!< triangle amplitude is 127 */ +#define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8 /*!< triangle amplitude is 255 */ +#define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9 /*!< triangle amplitude is 511 */ +#define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */ +#define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */ +#define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */ + +/* DAC data alignment */ +#define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< data right 12b alignment */ +#define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< data left 12b alignment */ +#define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< data right 8b alignment */ + +/* function declarations */ +/* deinitialize DAC */ +void dac_deinit(void); + +/* enable DAC */ +void dac_enable(void); +/* disable DAC */ +void dac_disable(void); +/* enable DAC DMA */ +void dac_dma_enable(void); +/* disable DAC DMA */ +void dac_dma_disable(void); +/* enable DAC output buffer */ +void dac_output_buffer_enable(void); +/* disable DAC output buffer */ +void dac_output_buffer_disable(void); +/* enable DAC trigger */ +void dac_trigger_enable(void); +/* disable DAC trigger */ +void dac_trigger_disable(void); +/* enable DAC software trigger */ +void dac_software_trigger_enable(void); +/* disable DAC software trigger */ +void dac_software_trigger_disable(void); +/* enable DAC interrupt(DAC DMA underrun interrupt) */ +void dac_interrupt_enable(void); +/* disable DAC interrupt(DAC DMA underrun interrupt) */ +void dac_interrupt_disable(void); + +/* configure DAC trigger source */ +void dac_trigger_source_config(uint32_t triggersource); +/* configure DAC wave mode */ +void dac_wave_mode_config(uint32_t wave_mode); +/* configure DAC wave bit width */ +void dac_wave_bit_width_config(uint32_t bit_width); +/* configure DAC LFSR noise mode */ +void dac_lfsr_noise_config(uint32_t unmask_bits); +/* configure DAC triangle noise mode */ +void dac_triangle_noise_config(uint32_t amplitude); +/* get the last data output value */ +uint16_t dac_output_value_get(void); + +/* get the specified DAC flag(DAC DMA underrun flag) */ +FlagStatus dac_flag_get(void); +/* clear the specified DAC flag(DAC DMA underrun flag) */ +void dac_flag_clear(void); +/* get the specified DAC interrupt flag(DAC DMA underrun interrupt flag) */ +FlagStatus dac_interrupt_flag_get(void); +/* clear the specified DAC interrupt flag(DAC DMA underrun interrupt flag) */ +void dac_interrupt_flag_clear(void); + +/* set DAC data holding register value */ +void dac_data_set(uint32_t dac_align, uint16_t data); + +#endif /* GD32F3X0_DAC_H */ + +#endif /* GD32F350 */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_dbg.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_dbg.h new file mode 100644 index 0000000000..9492753345 --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_dbg.h @@ -0,0 +1,128 @@ +/*! + \file gd32f3x0_dbg.h + \brief definitions for the DBG + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F3X0_DBG_H +#define GD32F3X0_DBG_H + +#include "gd32f3x0.h" + +/* DBG definitions */ +#define DBG DBG_BASE + +/* registers definitions */ +#define DBG_ID REG32(DBG + 0x00000000U) /*!< DBG_ID code register */ +#define DBG_CTL0 REG32(DBG + 0x00000004U) /*!< DBG control register 0 */ +#define DBG_CTL1 REG32(DBG + 0x00000008U) /*!< DBG control register 1 */ + +/* bits definitions */ +/* DBG_ID */ +#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */ + +/* DBG_CTL0 */ +#define DBG_CTL0_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */ +#define DBG_CTL0_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */ +#define DBG_CTL0_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */ +#define DBG_CTL0_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halted */ +#define DBG_CTL0_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halted */ +#define DBG_CTL0_TIMER0_HOLD BIT(10) /*!< hold TIMER0 counter when core is halted */ +#define DBG_CTL0_TIMER1_HOLD BIT(11) /*!< hold TIMER1 counter when core is halted */ +#define DBG_CTL0_TIMER2_HOLD BIT(12) /*!< hold TIMER2 counter when core is halted */ +#define DBG_CTL0_I2C0_HOLD BIT(15) /*!< hold I2C0 smbus when core is halted */ +#define DBG_CTL0_I2C1_HOLD BIT(16) /*!< hold I2C1 smbus when core is halted */ +#ifdef GD32F350 +#define DBG_CTL0_TIMER5_HOLD BIT(19) /*!< hold TIMER5 counter when core is halted */ +#endif /* GD32F350 */ +#define DBG_CTL0_TIMER13_HOLD BIT(27) /*!< hold TIMER13 counter when core is halted */ + +/* DBG_CTL1 */ +#define DBG_CTL1_RTC_HOLD BIT(10) /*!< hold RTC calendar and wakeup counter when core is halted */ +#define DBG_CTL1_TIMER14_HOLD BIT(16) /*!< hold TIMER14 counter when core is halted */ +#define DBG_CTL1_TIMER15_HOLD BIT(17) /*!< hold TIMER15 counter when core is halted */ +#define DBG_CTL1_TIMER16_HOLD BIT(18) /*!< hold TIMER16 counter when core is halted */ + +/* constants definitions */ +#define DBG_LOW_POWER_SLEEP DBG_CTL0_SLP_HOLD /*!< keep debugger connection during sleep mode */ +#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */ +#define DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD /*!< keep debugger connection during standby mode */ + +/* define the peripheral debug hold bit position and its register index offset */ +#define DBG_REGIDX_BIT(regidx, bitpos) (((regidx) << 6) | (bitpos)) +#define DBG_REG_VAL(periph) (REG32(DBG + ((uint32_t)(periph) >> 6))) +#define DBG_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU) + +/* register index */ +typedef enum +{ + DBG_IDX_CTL0 = 0x04U, /*!< DBG control register 0 offset */ + DBG_IDX_CTL1 = 0x08U, /*!< DBG control register 1 offset */ +}dbg_reg_idx; + +/* peripherals hold bit */ +typedef enum +{ + DBG_FWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 8U), /*!< debug FWDGT kept when core is halted */ + DBG_WWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 9U), /*!< debug WWDGT kept when core is halted */ + DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 10U), /*!< hold TIMER0 counter when core is halted */ + DBG_TIMER1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 11U), /*!< hold TIMER1 counter when core is halted */ + DBG_TIMER2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 12U), /*!< hold TIMER2 counter when core is halted */ +#ifdef GD32F350 + DBG_TIMER5_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 19U), /*!< hold TIMER5 counter when core is halted */ +#endif /* GD32F350 */ + DBG_TIMER13_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 27U), /*!< hold TIMER13 counter when core is halted */ + DBG_TIMER14_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 16U), /*!< hold TIMER14 counter when core is halted */ + DBG_TIMER15_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 17U), /*!< hold TIMER15 counter when core is halted */ + DBG_TIMER16_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 18U), /*!< hold TIMER16 counter when core is halted */ + DBG_I2C0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 15U), /*!< hold I2C0 smbus when core is halted */ + DBG_I2C1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 16U), /*!< hold I2C1 smbus when core is halted */ + DBG_RTC_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 10U), /*!< hold RTC calendar and wakeup counter when core is halted */ +}dbg_periph_enum; + +/* function declarations */ +/* deinitialize the DBG */ +void dbg_deinit(void); +/* read DBG_ID code register */ +uint32_t dbg_id_get(void); + +/* enable low power behavior when the MCU is in debug mode */ +void dbg_low_power_enable(uint32_t dbg_low_power); +/* disable low power behavior when the MCU is in debug mode */ +void dbg_low_power_disable(uint32_t dbg_low_power); + +/* enable peripheral behavior when the MCU is in debug mode */ +void dbg_periph_enable(dbg_periph_enum dbg_periph); +/* disable peripheral behavior when the MCU is in debug mode */ +void dbg_periph_disable(dbg_periph_enum dbg_periph); + +#endif /* GD32F3X0_DBG_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_dma.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_dma.h new file mode 100644 index 0000000000..9c24dca1dd --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_dma.h @@ -0,0 +1,273 @@ +/*! + \file gd32f3x0_dma.h + \brief definitions for the DMA + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F3X0_DMA_H +#define GD32F3X0_DMA_H + +#include "gd32f3x0.h" + +/* DMA definitions */ +#define DMA DMA_BASE /*!< DMA base address */ + +/* registers definitions */ +#define DMA_INTF REG32(DMA + 0x00000000U) /*!< DMA interrupt flag register */ +#define DMA_INTC REG32(DMA + 0x00000004U) /*!< DMA interrupt flag clear register */ +#define DMA_CH0CTL REG32(DMA + 0x00000008U) /*!< DMA channel 0 control register */ +#define DMA_CH0CNT REG32(DMA + 0x0000000CU) /*!< DMA channel 0 counter register */ +#define DMA_CH0PADDR REG32(DMA + 0x00000010U) /*!< DMA channel 0 peripheral base address register */ +#define DMA_CH0MADDR REG32(DMA + 0x00000014U) /*!< DMA channel 0 memory base address register */ +#define DMA_CH1CTL REG32(DMA + 0x0000001CU) /*!< DMA channel 1 control register */ +#define DMA_CH1CNT REG32(DMA + 0x00000020U) /*!< DMA channel 1 counter register */ +#define DMA_CH1PADDR REG32(DMA + 0x00000024U) /*!< DMA channel 1 peripheral base address register */ +#define DMA_CH1MADDR REG32(DMA + 0x00000028U) /*!< DMA channel 1 memory base address register */ +#define DMA_CH2CTL REG32(DMA + 0x00000030U) /*!< DMA channel 2 control register */ +#define DMA_CH2CNT REG32(DMA + 0x00000034U) /*!< DMA channel 2 counter register */ +#define DMA_CH2PADDR REG32(DMA + 0x00000038U) /*!< DMA channel 2 peripheral base address register */ +#define DMA_CH2MADDR REG32(DMA + 0x0000003CU) /*!< DMA channel 2 memory base address register */ +#define DMA_CH3CTL REG32(DMA + 0x00000044U) /*!< DMA channel 3 control register */ +#define DMA_CH3CNT REG32(DMA + 0x00000048U) /*!< DMA channel 3 counter register */ +#define DMA_CH3PADDR REG32(DMA + 0x0000004CU) /*!< DMA channel 3 peripheral base address register */ +#define DMA_CH3MADDR REG32(DMA + 0x00000050U) /*!< DMA channel 3 memory base address register */ +#define DMA_CH4CTL REG32(DMA + 0x00000058U) /*!< DMA channel 4 control register */ +#define DMA_CH4CNT REG32(DMA + 0x0000005CU) /*!< DMA channel 4 counter register */ +#define DMA_CH4PADDR REG32(DMA + 0x00000060U) /*!< DMA channel 4 peripheral base address register */ +#define DMA_CH4MADDR REG32(DMA + 0x00000064U) /*!< DMA channel 4 memory base address register */ +#define DMA_CH5CTL REG32(DMA + 0x0000006CU) /*!< DMA channel 5 control register */ +#define DMA_CH5CNT REG32(DMA + 0x00000070U) /*!< DMA channel 5 counter register */ +#define DMA_CH5PADDR REG32(DMA + 0x00000074U) /*!< DMA channel 5 peripheral base address register */ +#define DMA_CH5MADDR REG32(DMA + 0x00000078U) /*!< DMA channel 5 memory base address register */ +#define DMA_CH6CTL REG32(DMA + 0x00000080U) /*!< DMA channel 6 control register */ +#define DMA_CH6CNT REG32(DMA + 0x00000084U) /*!< DMA channel 6 counter register */ +#define DMA_CH6PADDR REG32(DMA + 0x00000088U) /*!< DMA channel 6 peripheral base address register */ +#define DMA_CH6MADDR REG32(DMA + 0x0000008CU) /*!< DMA channel 6 memory base address register */ + +/* bits definitions */ +/* DMA_INTF */ +#define DMA_INTF_GIF BIT(0) /*!< global interrupt flag of channel */ +#define DMA_INTF_FTFIF BIT(1) /*!< full transfer finish flag of channel */ +#define DMA_INTF_HTFIF BIT(2) /*!< half transfer finish flag of channel */ +#define DMA_INTF_ERRIF BIT(3) /*!< error flag of channel */ + +/* DMA_INTC */ +#define DMA_INTC_GIFC BIT(0) /*!< clear global interrupt flag of channel */ +#define DMA_INTC_FTFIFC BIT(1) /*!< clear transfer finish flag of channel */ +#define DMA_INTC_HTFIFC BIT(2) /*!< clear half transfer finish flag of channel */ +#define DMA_INTC_ERRIFC BIT(3) /*!< clear error flag of channel */ + +/* DMA_CHxCTL,x=0..6 */ +#define DMA_CHXCTL_CHEN BIT(0) /*!< channel x enable */ +#define DMA_CHXCTL_FTFIE BIT(1) /*!< enable bit for channel x transfer complete interrupt */ +#define DMA_CHXCTL_HTFIE BIT(2) /*!< enable bit for channel x transfer half complete interrupt */ +#define DMA_CHXCTL_ERRIE BIT(3) /*!< enable bit for channel x error interrupt */ +#define DMA_CHXCTL_DIR BIT(4) /*!< direction of the data transfer on the channel */ +#define DMA_CHXCTL_CMEN BIT(5) /*!< circulation mode */ +#define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */ +#define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */ +#define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data size of peripheral */ +#define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data size of memory */ +#define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level of channelx */ +#define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */ + +/* DMA_CHxCNT,x=0..6 */ +#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */ + +/* DMA_CHxPADDR,x=0..6 */ +#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */ + +/* DMA_CHxMADDR,x=0..6 */ +#define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */ + +/* constants definitions */ +/* DMA channel select */ +typedef enum +{ + DMA_CH0 = 0, /*!< DMA Channel0 */ + DMA_CH1, /*!< DMA Channel1 */ + DMA_CH2, /*!< DMA Channel2 */ + DMA_CH3, /*!< DMA Channel3 */ + DMA_CH4, /*!< DMA Channel4 */ + DMA_CH5, /*!< DMA Channel5 */ + DMA_CH6 /*!< DMA Channel6 */ +} dma_channel_enum; + +/* DMA initialize struct */ +typedef struct +{ + uint32_t periph_addr; /*!< peripheral base address */ + uint32_t periph_width; /*!< transfer data size of peripheral */ + uint8_t periph_inc; /*!< peripheral increasing mode */ + uint32_t memory_addr; /*!< memory base address */ + uint32_t memory_width; /*!< transfer data size of memory */ + uint8_t memory_inc; /*!< memory increasing mode */ + uint8_t direction; /*!< channel data transfer direction */ + uint32_t number; /*!< channel transfer number */ + uint32_t priority; /*!< channel priority level */ +} dma_parameter_struct; + +/* DMA reset value */ +#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */ +#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */ +#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */ +#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */ +#define DMA_CHINTF_RESET_VALUE (DMA_INTF_GIF | DMA_INTF_FTFIF | \ + DMA_INTF_HTFIF | DMA_INTF_ERRIF) + +#define DMA_FLAG_ADD(flag,shift) ((flag) << ((uint32_t)(shift) * 4U)) /*!< DMA channel flag shift */ + +/* DMA_CHCTL base address */ +#define DMA_CHXCTL_BASE (DMA + (uint32_t)0x00000008U) /*!< the base address of DMA channel CHXCTL register */ +#define DMA_CHXCNT_BASE (DMA + (uint32_t)0x0000000CU) /*!< the base address of DMA channel CHXCNT register */ +#define DMA_CHXPADDR_BASE (DMA + (uint32_t)0x00000010U) /*!< the base address of DMA channel CHXPADDR register */ +#define DMA_CHXMADDR_BASE (DMA + (uint32_t)0x00000014U) /*!< the base address of DMA channel CHXMADDR register */ + +/* DMA channel shift bit */ +#define DMA_CHCTL(channel) REG32(DMA_CHXCTL_BASE + (uint32_t)0x0000014U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCTL register */ +#define DMA_CHCNT(channel) REG32(DMA_CHXCNT_BASE + (uint32_t)0x0000014U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCNT register */ +#define DMA_CHPADDR(channel) REG32(DMA_CHXPADDR_BASE + (uint32_t)0x0000014U * (uint32_t)(channel)) /*!< the address of DMA channel CHXPADDR register */ +#define DMA_CHMADDR(channel) REG32(DMA_CHXMADDR_BASE + (uint32_t)0x0000014U * (uint32_t)(channel)) /*!< the address of DMA channel CHXMADDR register */ + +/* DMA_INTF register */ +/* interrupt flag bits */ +#define DMA_INT_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ +#define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish interrupt flag of channel */ +#define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish interrupt flag of channel */ +#define DMA_INT_FLAG_ERR DMA_INTF_ERRIF /*!< error interrupt flag of channel */ + +/* flag bits */ +#define DMA_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ +#define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag of channel */ +#define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag of channel */ +#define DMA_FLAG_ERR DMA_INTF_ERRIF /*!< error flag of channel */ + +/* DMA_CHxCTL register */ +/* interrupt enable bits */ +#define DMA_INT_FTF DMA_CHXCTL_FTFIE /*!< enable bit for channel full transfer finish interrupt */ +#define DMA_INT_HTF DMA_CHXCTL_HTFIE /*!< enable bit for channel half transfer finish interrupt */ +#define DMA_INT_ERR DMA_CHXCTL_ERRIE /*!< enable bit for channel error interrupt */ + +/* transfer direction */ +#define DMA_PERIPHERAL_TO_MEMORY ((uint32_t)0x00000000U) /*!< read from peripheral and write to memory */ +#define DMA_MEMORY_TO_PERIPHERAL ((uint32_t)0x00000001U) /*!< read from memory and write to peripheral */ + +/* peripheral increasing mode */ +#define DMA_PERIPH_INCREASE_DISABLE ((uint32_t)0x00000000U) /*!< next address of peripheral is fixed address mode */ +#define DMA_PERIPH_INCREASE_ENABLE ((uint32_t)0x00000001U) /*!< next address of peripheral is increasing address mode */ + +/* memory increasing mode */ +#define DMA_MEMORY_INCREASE_DISABLE ((uint32_t)0x00000000U) /*!< next address of memory is fixed address mode */ +#define DMA_MEMORY_INCREASE_ENABLE ((uint32_t)0x00000001U) /*!< next address of memory is increasing address mode */ + +/* transfer data size of peripheral */ +#define CHCTL_PWIDTH(regval) (BITS(8,9) & ((regval) << 8)) /*!< transfer data size of peripheral */ +#define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0) /*!< transfer data size of peripheral is 8-bit */ +#define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1) /*!< transfer data size of peripheral is 16-bit */ +#define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2) /*!< transfer data size of peripheral is 32-bit */ + +/* transfer data size of memory */ +#define CHCTL_MWIDTH(regval) (BITS(10,11) & ((regval) << 10)) /*!< transfer data size of memory */ +#define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0) /*!< transfer data size of memory is 8-bit */ +#define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1) /*!< transfer data size of memory is 16-bit */ +#define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2) /*!< transfer data size of memory is 32-bit */ + +/* channel priority level */ +#define CHCTL_PRIO(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) /*!< DMA channel priority level */ +#define DMA_PRIORITY_LOW CHCTL_PRIO(0) /*!< low priority */ +#define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1) /*!< medium priority */ +#define DMA_PRIORITY_HIGH CHCTL_PRIO(2) /*!< high priority */ +#define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3) /*!< ultra high priority */ + +/* DMA_CHxCNT register */ +/* transfer counter */ +#define DMA_CHANNEL_CNT_MASK DMA_CHXCNT_CNT + +/* function declarations */ +/* deinitialize DMA a channel registers */ +void dma_deinit(dma_channel_enum channelx); +/* initialize the parameters of DMA struct with the default values */ +void dma_struct_para_init(dma_parameter_struct* init_struct); +/* initialize DMA channel */ +void dma_init(dma_channel_enum channelx, dma_parameter_struct* init_struct); +/* enable DMA circulation mode */ +void dma_circulation_enable(dma_channel_enum channelx); +/* disable DMA circulation mode */ +void dma_circulation_disable(dma_channel_enum channelx); +/* enable memory to memory mode */ +void dma_memory_to_memory_enable(dma_channel_enum channelx); +/* disable memory to memory mode */ +void dma_memory_to_memory_disable(dma_channel_enum channelx); +/* enable DMA channel */ +void dma_channel_enable(dma_channel_enum channelx); +/* disable DMA channel */ +void dma_channel_disable(dma_channel_enum channelx); + +/* set DMA peripheral base address */ +void dma_periph_address_config(dma_channel_enum channelx, uint32_t address); +/* set DMA memory base address */ +void dma_memory_address_config(dma_channel_enum channelx, uint32_t address); +/* set the number of remaining data to be transferred by the DMA */ +void dma_transfer_number_config(dma_channel_enum channelx, uint32_t number); +/* get the number of remaining data to be transferred by the DMA */ +uint32_t dma_transfer_number_get(dma_channel_enum channelx); +/* configure priority level of DMA channel */ +void dma_priority_config(dma_channel_enum channelx, uint32_t priority); +/* configure transfer data size of memory */ +void dma_memory_width_config (dma_channel_enum channelx, uint32_t mwidth); +/* configure transfer data size of peripheral */ +void dma_periph_width_config (dma_channel_enum channelx, uint32_t pwidth); +/* enable next address increasement algorithm of memory */ +void dma_memory_increase_enable(dma_channel_enum channelx); +/* disable next address increasement algorithm of memory */ +void dma_memory_increase_disable(dma_channel_enum channelx); +/* enable next address increasement algorithm of peripheral */ +void dma_periph_increase_enable(dma_channel_enum channelx); +/* disable next address increasement algorithm of peripheral */ +void dma_periph_increase_disable(dma_channel_enum channelx); +/* configure the direction of data transfer on the channel */ +void dma_transfer_direction_config(dma_channel_enum channelx, uint32_t direction); + +/* check DMA flag is set or not */ +FlagStatus dma_flag_get(dma_channel_enum channelx, uint32_t flag); +/* clear DMA a channel flag */ +void dma_flag_clear(dma_channel_enum channelx, uint32_t flag); +/* check DMA flag and interrupt enable bit is set or not */ +FlagStatus dma_interrupt_flag_get(dma_channel_enum channelx, uint32_t flag); +/* clear DMA a channel flag */ +void dma_interrupt_flag_clear(dma_channel_enum channelx, uint32_t flag); +/* enable DMA interrupt */ +void dma_interrupt_enable(dma_channel_enum channelx, uint32_t source); +/* disable DMA interrupt */ +void dma_interrupt_disable(dma_channel_enum channelx, uint32_t source); + +#endif /* GD32F3X0_DMA_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_exti.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_exti.h new file mode 100644 index 0000000000..3e17ff3c57 --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_exti.h @@ -0,0 +1,285 @@ +/*! + \file gd32f3x0_exti.h + \brief definitions for the EXTI + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F3X0_EXTI_H +#define GD32F3X0_EXTI_H + +#include "gd32f3x0.h" + +/* EXTI definitions */ +#define EXTI EXTI_BASE + +/* registers definitions */ +#define EXTI_INTEN REG32(EXTI + 0x00000000U)/*!< interrupt enable register */ +#define EXTI_EVEN REG32(EXTI + 0x00000004U)/*!< event enable register */ +#define EXTI_RTEN REG32(EXTI + 0x00000008U)/*!< rising edge trigger enable register */ +#define EXTI_FTEN REG32(EXTI + 0x0000000CU)/*!< falling trigger enable register */ +#define EXTI_SWIEV REG32(EXTI + 0x00000010U)/*!< software interrupt event register */ +#define EXTI_PD REG32(EXTI + 0x00000014U)/*!< pending register */ + +/* bits definitions */ +/* EXTI_INTEN */ +#define EXTI_INTEN_INTEN0 BIT(0) /*!< interrupt from line 0 */ +#define EXTI_INTEN_INTEN1 BIT(1) /*!< interrupt from line 1 */ +#define EXTI_INTEN_INTEN2 BIT(2) /*!< interrupt from line 2 */ +#define EXTI_INTEN_INTEN3 BIT(3) /*!< interrupt from line 3 */ +#define EXTI_INTEN_INTEN4 BIT(4) /*!< interrupt from line 4 */ +#define EXTI_INTEN_INTEN5 BIT(5) /*!< interrupt from line 5 */ +#define EXTI_INTEN_INTEN6 BIT(6) /*!< interrupt from line 6 */ +#define EXTI_INTEN_INTEN7 BIT(7) /*!< interrupt from line 7 */ +#define EXTI_INTEN_INTEN8 BIT(8) /*!< interrupt from line 8 */ +#define EXTI_INTEN_INTEN9 BIT(9) /*!< interrupt from line 9 */ +#define EXTI_INTEN_INTEN10 BIT(10) /*!< interrupt from line 10 */ +#define EXTI_INTEN_INTEN11 BIT(11) /*!< interrupt from line 11 */ +#define EXTI_INTEN_INTEN12 BIT(12) /*!< interrupt from line 12 */ +#define EXTI_INTEN_INTEN13 BIT(13) /*!< interrupt from line 13 */ +#define EXTI_INTEN_INTEN14 BIT(14) /*!< interrupt from line 14 */ +#define EXTI_INTEN_INTEN15 BIT(15) /*!< interrupt from line 15 */ +#define EXTI_INTEN_INTEN16 BIT(16) /*!< interrupt from line 16 */ +#define EXTI_INTEN_INTEN17 BIT(17) /*!< interrupt from line 17 */ +#define EXTI_INTEN_INTEN18 BIT(18) /*!< interrupt from line 18 */ +#define EXTI_INTEN_INTEN19 BIT(19) /*!< interrupt from line 19 */ +#define EXTI_INTEN_INTEN20 BIT(20) /*!< interrupt from line 20 */ +#define EXTI_INTEN_INTEN21 BIT(21) /*!< interrupt from line 21 */ +#define EXTI_INTEN_INTEN22 BIT(22) /*!< interrupt from line 22 */ +#define EXTI_INTEN_INTEN23 BIT(23) /*!< interrupt from line 23 */ +#define EXTI_INTEN_INTEN24 BIT(24) /*!< interrupt from line 24 */ +#define EXTI_INTEN_INTEN25 BIT(25) /*!< interrupt from line 25 */ +#define EXTI_INTEN_INTEN26 BIT(26) /*!< interrupt from line 26 */ +#define EXTI_INTEN_INTEN27 BIT(27) /*!< interrupt from line 27 */ + +/* EXTI_EVEN */ +#define EXTI_EVEN_EVEN0 BIT(0) /*!< event from line 0 */ +#define EXTI_EVEN_EVEN1 BIT(1) /*!< event from line 1 */ +#define EXTI_EVEN_EVEN2 BIT(2) /*!< event from line 2 */ +#define EXTI_EVEN_EVEN3 BIT(3) /*!< event from line 3 */ +#define EXTI_EVEN_EVEN4 BIT(4) /*!< event from line 4 */ +#define EXTI_EVEN_EVEN5 BIT(5) /*!< event from line 5 */ +#define EXTI_EVEN_EVEN6 BIT(6) /*!< event from line 6 */ +#define EXTI_EVEN_EVEN7 BIT(7) /*!< event from line 7 */ +#define EXTI_EVEN_EVEN8 BIT(8) /*!< event from line 8 */ +#define EXTI_EVEN_EVEN9 BIT(9) /*!< event from line 9 */ +#define EXTI_EVEN_EVEN10 BIT(10) /*!< event from line 10 */ +#define EXTI_EVEN_EVEN11 BIT(11) /*!< event from line 11 */ +#define EXTI_EVEN_EVEN12 BIT(12) /*!< event from line 12 */ +#define EXTI_EVEN_EVEN13 BIT(13) /*!< event from line 13 */ +#define EXTI_EVEN_EVEN14 BIT(14) /*!< event from line 14 */ +#define EXTI_EVEN_EVEN15 BIT(15) /*!< event from line 15 */ +#define EXTI_EVEN_EVEN16 BIT(16) /*!< event from line 16 */ +#define EXTI_EVEN_EVEN17 BIT(17) /*!< event from line 17 */ +#define EXTI_EVEN_EVEN18 BIT(18) /*!< event from line 18 */ +#define EXTI_EVEN_EVEN19 BIT(19) /*!< event from line 19 */ +#define EXTI_EVEN_EVEN20 BIT(20) /*!< event from line 20 */ +#define EXTI_EVEN_EVEN21 BIT(21) /*!< event from line 21 */ +#define EXTI_EVEN_EVEN22 BIT(22) /*!< event from line 22 */ +#define EXTI_EVEN_EVEN23 BIT(23) /*!< event from line 23 */ +#define EXTI_EVEN_EVEN24 BIT(24) /*!< event from line 24 */ +#define EXTI_EVEN_EVEN25 BIT(25) /*!< event from line 25 */ +#define EXTI_EVEN_EVEN26 BIT(26) /*!< event from line 26 */ +#define EXTI_EVEN_EVEN27 BIT(27) /*!< event from line 27 */ + +/* EXTI_RTEN */ +#define EXTI_RTEN_RTEN0 BIT(0) /*!< rising edge from line 0 */ +#define EXTI_RTEN_RTEN1 BIT(1) /*!< rising edge from line 1 */ +#define EXTI_RTEN_RTEN2 BIT(2) /*!< rising edge from line 2 */ +#define EXTI_RTEN_RTEN3 BIT(3) /*!< rising edge from line 3 */ +#define EXTI_RTEN_RTEN4 BIT(4) /*!< rising edge from line 4 */ +#define EXTI_RTEN_RTEN5 BIT(5) /*!< rising edge from line 5 */ +#define EXTI_RTEN_RTEN6 BIT(6) /*!< rising edge from line 6 */ +#define EXTI_RTEN_RTEN7 BIT(7) /*!< rising edge from line 7 */ +#define EXTI_RTEN_RTEN8 BIT(8) /*!< rising edge from line 8 */ +#define EXTI_RTEN_RTEN9 BIT(9) /*!< rising edge from line 9 */ +#define EXTI_RTEN_RTEN10 BIT(10) /*!< rising edge from line 10 */ +#define EXTI_RTEN_RTEN11 BIT(11) /*!< rising edge from line 11 */ +#define EXTI_RTEN_RTEN12 BIT(12) /*!< rising edge from line 12 */ +#define EXTI_RTEN_RTEN13 BIT(13) /*!< rising edge from line 13 */ +#define EXTI_RTEN_RTEN14 BIT(14) /*!< rising edge from line 14 */ +#define EXTI_RTEN_RTEN15 BIT(15) /*!< rising edge from line 15 */ +#define EXTI_RTEN_RTEN16 BIT(16) /*!< rising edge from line 16 */ +#define EXTI_RTEN_RTEN17 BIT(17) /*!< rising edge from line 17 */ +#define EXTI_RTEN_RTEN18 BIT(18) /*!< rising edge from line 18 */ +#define EXTI_RTEN_RTEN19 BIT(19) /*!< rising edge from line 19 */ +#define EXTI_RTEN_RTEN21 BIT(21) /*!< rising edge from line 21 */ +#define EXTI_RTEN_RTEN22 BIT(22) /*!< rising edge from line 22 */ + +/* EXTI_FTEN */ +#define EXTI_FTEN_FTEN0 BIT(0) /*!< falling edge from line 0 */ +#define EXTI_FTEN_FTEN1 BIT(1) /*!< falling edge from line 1 */ +#define EXTI_FTEN_FTEN2 BIT(2) /*!< falling edge from line 2 */ +#define EXTI_FTEN_FTEN3 BIT(3) /*!< falling edge from line 3 */ +#define EXTI_FTEN_FTEN4 BIT(4) /*!< falling edge from line 4 */ +#define EXTI_FTEN_FTEN5 BIT(5) /*!< falling edge from line 5 */ +#define EXTI_FTEN_FTEN6 BIT(6) /*!< falling edge from line 6 */ +#define EXTI_FTEN_FTEN7 BIT(7) /*!< falling edge from line 7 */ +#define EXTI_FTEN_FTEN8 BIT(8) /*!< falling edge from line 8 */ +#define EXTI_FTEN_FTEN9 BIT(9) /*!< falling edge from line 9 */ +#define EXTI_FTEN_FTEN10 BIT(10) /*!< falling edge from line 10 */ +#define EXTI_FTEN_FTEN11 BIT(11) /*!< falling edge from line 11 */ +#define EXTI_FTEN_FTEN12 BIT(12) /*!< falling edge from line 12 */ +#define EXTI_FTEN_FTEN13 BIT(13) /*!< falling edge from line 13 */ +#define EXTI_FTEN_FTEN14 BIT(14) /*!< falling edge from line 14 */ +#define EXTI_FTEN_FTEN15 BIT(15) /*!< falling edge from line 15 */ +#define EXTI_FTEN_FTEN16 BIT(16) /*!< falling edge from line 16 */ +#define EXTI_FTEN_FTEN17 BIT(17) /*!< falling edge from line 17 */ +#define EXTI_FTEN_FTEN18 BIT(18) /*!< falling edge from line 18 */ +#define EXTI_FTEN_FTEN19 BIT(19) /*!< falling edge from line 19 */ +#define EXTI_FTEN_FTEN21 BIT(21) /*!< falling edge from line 21 */ +#define EXTI_FTEN_FTEN22 BIT(22) /*!< falling edge from line 22 */ + +/* EXTI_SWIEV */ +#define EXTI_SWIEV_SWIEV0 BIT(0) /*!< software interrupt/event request from line 0 */ +#define EXTI_SWIEV_SWIEV1 BIT(1) /*!< software interrupt/event request from line 1 */ +#define EXTI_SWIEV_SWIEV2 BIT(2) /*!< software interrupt/event request from line 2 */ +#define EXTI_SWIEV_SWIEV3 BIT(3) /*!< software interrupt/event request from line 3 */ +#define EXTI_SWIEV_SWIEV4 BIT(4) /*!< software interrupt/event request from line 4 */ +#define EXTI_SWIEV_SWIEV5 BIT(5) /*!< software interrupt/event request from line 5 */ +#define EXTI_SWIEV_SWIEV6 BIT(6) /*!< software interrupt/event request from line 6 */ +#define EXTI_SWIEV_SWIEV7 BIT(7) /*!< software interrupt/event request from line 7 */ +#define EXTI_SWIEV_SWIEV8 BIT(8) /*!< software interrupt/event request from line 8 */ +#define EXTI_SWIEV_SWIEV9 BIT(9) /*!< software interrupt/event request from line 9 */ +#define EXTI_SWIEV_SWIEV10 BIT(10) /*!< software interrupt/event request from line 10 */ +#define EXTI_SWIEV_SWIEV11 BIT(11) /*!< software interrupt/event request from line 11 */ +#define EXTI_SWIEV_SWIEV12 BIT(12) /*!< software interrupt/event request from line 12 */ +#define EXTI_SWIEV_SWIEV13 BIT(13) /*!< software interrupt/event request from line 13 */ +#define EXTI_SWIEV_SWIEV14 BIT(14) /*!< software interrupt/event request from line 14 */ +#define EXTI_SWIEV_SWIEV15 BIT(15) /*!< software interrupt/event request from line 15 */ +#define EXTI_SWIEV_SWIEV16 BIT(16) /*!< software interrupt/event request from line 16 */ +#define EXTI_SWIEV_SWIEV17 BIT(17) /*!< software interrupt/event request from line 17 */ +#define EXTI_SWIEV_SWIEV18 BIT(18) /*!< software interrupt/event request from line 18 */ +#define EXTI_SWIEV_SWIEV19 BIT(19) /*!< software interrupt/event request from line 19 */ +#define EXTI_SWIEV_SWIEV21 BIT(21) /*!< software interrupt/event request from line 21 */ +#define EXTI_SWIEV_SWIEV22 BIT(22) /*!< software interrupt/event request from line 22 */ + +/* EXTI_PD */ +#define EXTI_PD_PD0 BIT(0) /*!< interrupt/event pending status from line 0 */ +#define EXTI_PD_PD1 BIT(1) /*!< interrupt/event pending status from line 1 */ +#define EXTI_PD_PD2 BIT(2) /*!< interrupt/event pending status from line 2 */ +#define EXTI_PD_PD3 BIT(3) /*!< interrupt/event pending status from line 3 */ +#define EXTI_PD_PD4 BIT(4) /*!< interrupt/event pending status from line 4 */ +#define EXTI_PD_PD5 BIT(5) /*!< interrupt/event pending status from line 5 */ +#define EXTI_PD_PD6 BIT(6) /*!< interrupt/event pending status from line 6 */ +#define EXTI_PD_PD7 BIT(7) /*!< interrupt/event pending status from line 7 */ +#define EXTI_PD_PD8 BIT(8) /*!< interrupt/event pending status from line 8 */ +#define EXTI_PD_PD9 BIT(9) /*!< interrupt/event pending status from line 9 */ +#define EXTI_PD_PD10 BIT(10) /*!< interrupt/event pending status from line 10 */ +#define EXTI_PD_PD11 BIT(11) /*!< interrupt/event pending status from line 11 */ +#define EXTI_PD_PD12 BIT(12) /*!< interrupt/event pending status from line 12 */ +#define EXTI_PD_PD13 BIT(13) /*!< interrupt/event pending status from line 13 */ +#define EXTI_PD_PD14 BIT(14) /*!< interrupt/event pending status from line 14 */ +#define EXTI_PD_PD15 BIT(15) /*!< interrupt/event pending status from line 15 */ +#define EXTI_PD_PD16 BIT(16) /*!< interrupt/event pending status from line 16 */ +#define EXTI_PD_PD17 BIT(17) /*!< interrupt/event pending status from line 17 */ +#define EXTI_PD_PD18 BIT(18) /*!< interrupt/event pending status from line 18 */ +#define EXTI_PD_PD19 BIT(19) /*!< interrupt/event pending status from line 19 */ +#define EXTI_PD_PD21 BIT(21) /*!< interrupt/event pending status from line 21 */ +#define EXTI_PD_PD22 BIT(22) /*!< interrupt/event pending status from line 22 */ + +/* constants definitions */ +/* EXTI line number */ +typedef enum +{ + EXTI_0 = BIT(0), /*!< EXTI line 0 */ + EXTI_1 = BIT(1), /*!< EXTI line 1 */ + EXTI_2 = BIT(2), /*!< EXTI line 2 */ + EXTI_3 = BIT(3), /*!< EXTI line 3 */ + EXTI_4 = BIT(4), /*!< EXTI line 4 */ + EXTI_5 = BIT(5), /*!< EXTI line 5 */ + EXTI_6 = BIT(6), /*!< EXTI line 6 */ + EXTI_7 = BIT(7), /*!< EXTI line 7 */ + EXTI_8 = BIT(8), /*!< EXTI line 8 */ + EXTI_9 = BIT(9), /*!< EXTI line 9 */ + EXTI_10 = BIT(10), /*!< EXTI line 10 */ + EXTI_11 = BIT(11), /*!< EXTI line 11 */ + EXTI_12 = BIT(12), /*!< EXTI line 12 */ + EXTI_13 = BIT(13), /*!< EXTI line 13 */ + EXTI_14 = BIT(14), /*!< EXTI line 14 */ + EXTI_15 = BIT(15), /*!< EXTI line 15 */ + EXTI_16 = BIT(16), /*!< EXTI line 16 */ + EXTI_17 = BIT(17), /*!< EXTI line 17 */ + EXTI_18 = BIT(18), /*!< EXTI line 18 */ + EXTI_19 = BIT(19), /*!< EXTI line 19 */ + EXTI_20 = BIT(20), /*!< EXTI line 20 */ + EXTI_21 = BIT(21), /*!< EXTI line 21 */ + EXTI_22 = BIT(22), /*!< EXTI line 22 */ + EXTI_23 = BIT(23), /*!< EXTI line 23 */ + EXTI_24 = BIT(24), /*!< EXTI line 24 */ + EXTI_25 = BIT(25), /*!< EXTI line 25 */ + EXTI_26 = BIT(26), /*!< EXTI line 26 */ + EXTI_27 = BIT(27), /*!< EXTI line 27 */ +}exti_line_enum; + +/* external interrupt and event */ +typedef enum +{ + EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */ + EXTI_EVENT /*!< EXTI event mode */ +}exti_mode_enum; + +/* interrupt trigger mode */ +typedef enum +{ + EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */ + EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */ + EXTI_TRIG_BOTH /*!< EXTI rising and falling edge trigger */ +}exti_trig_type_enum; + +/* function declarations */ +/* deinitialize the EXTI */ +void exti_deinit(void); +/* initialize the EXTI, enable the configuration of EXTI initialize */ +void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type); +/* enable the interrupts from EXTI line x */ +void exti_interrupt_enable(exti_line_enum linex); +/* disable the interrupts from EXTI line x */ +void exti_interrupt_disable(exti_line_enum linex); +/* enable the events from EXTI line x */ +void exti_event_enable(exti_line_enum linex); +/* disable the events from EXTI line x */ +void exti_event_disable(exti_line_enum linex); + +/* enable EXTI software interrupt event */ +void exti_software_interrupt_enable(exti_line_enum linex); +/* disable EXTI software interrupt event */ +void exti_software_interrupt_disable(exti_line_enum linex); +/* get EXTI line x pending flag */ +FlagStatus exti_flag_get(exti_line_enum linex); +/* clear EXTI line x pending flag */ +void exti_flag_clear(exti_line_enum linex); +/* get EXTI line x flag when the interrupt flag is set */ +FlagStatus exti_interrupt_flag_get(exti_line_enum linex); +/* clear EXTI line x pending flag */ +void exti_interrupt_flag_clear(exti_line_enum linex); + +#endif /* GD32F3X0_EXTI_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_fmc.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_fmc.h new file mode 100644 index 0000000000..9e49e73dc9 --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_fmc.h @@ -0,0 +1,258 @@ +/*! + \file gd32f3x0_fmc.h + \brief definitions for the FMC + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + +#ifndef GD32F3X0_FMC_H +#define GD32F3X0_FMC_H + +#include "gd32f3x0.h" + +/* FMC and option byte definition */ +#define FMC FMC_BASE /*!< FMC register base address */ +#define OB OB_BASE /*!< option byte base address */ + +/* registers definitions */ +#define FMC_WS REG32(FMC + 0x00000000U) /*!< FMC wait state register */ +#define FMC_KEY REG32(FMC + 0x00000004U) /*!< FMC unlock key register */ +#define FMC_OBKEY REG32(FMC + 0x00000008U) /*!< FMC option bytes unlock key register */ +#define FMC_STAT REG32(FMC + 0x0000000CU) /*!< FMC status register */ +#define FMC_CTL REG32(FMC + 0x00000010U) /*!< FMC control register */ +#define FMC_ADDR REG32(FMC + 0x00000014U) /*!< FMC address register */ +#define FMC_OBSTAT REG32(FMC + 0x0000001CU) /*!< FMC option bytes status register */ +#define FMC_WP REG32(FMC + 0x00000020U) /*!< FMC write protection register */ +#define FMC_WSEN REG32(FMC + 0x000000FCU) /*!< FMC wait state enable register */ +#define FMC_PID REG32(FMC + 0x00000100U) /*!< FMC product ID register */ + +#define OB_SPC REG16(OB + 0x00000000U) /*!< option byte security protection value */ +#define OB_USER REG16(OB + 0x00000002U) /*!< option byte user value*/ +#define OB_DATA0 REG16(OB + 0x00000004U) /*!< option byte data bit[7:0] value*/ +#define OB_DATA1 REG16(OB + 0x00000006U) /*!< option byte data bit[15:8] value*/ +#define OB_WP0 REG16(OB + 0x00000008U) /*!< option byte write protection 0 */ +#define OB_WP1 REG16(OB + 0x0000000AU) /*!< option byte write protection 1 */ + +/* bits definitions */ +/* FMC_WS */ +#define FMC_WS_WSCNT BITS(0,2) /*!< wait state counter */ + +/* FMC_KEY */ +#define FMC_KEY_KEY BITS(0,31) /*!< FMC main flash unlock key bits */ + +/* FMC_OBKEY */ +#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option bytes unlock key bits */ + +/* FMC_STAT */ +#define FMC_STAT_BUSY BIT(0) /*!< flash busy flag bit */ +#define FMC_STAT_PGERR BIT(2) /*!< flash program error flag bit */ +#define FMC_STAT_WPERR BIT(4) /*!< flash write protection error flag bit */ +#define FMC_STAT_ENDF BIT(5) /*!< end of operation flag bit */ + +/* FMC_CTL */ +#define FMC_CTL_PG BIT(0) /*!< main flash program command bit */ +#define FMC_CTL_PER BIT(1) /*!< main flash page erase bit */ +#define FMC_CTL_MER BIT(2) /*!< main flash mass erase bit */ +#define FMC_CTL_OBPG BIT(4) /*!< option bytes program command bit */ +#define FMC_CTL_OBER BIT(5) /*!< option bytes erase command bit */ +#define FMC_CTL_START BIT(6) /*!< send erase command to FMC bit */ +#define FMC_CTL_LK BIT(7) /*!< flash lock bit */ +#define FMC_CTL_OBWEN BIT(9) /*!< option bytes erase/program enable bit */ +#define FMC_CTL_ERRIE BIT(10) /*!< error interrupt enable bit */ +#define FMC_CTL_ENDIE BIT(12) /*!< end of operation interrupt enable bit */ +#define FMC_CTL_OBRLD BIT(13) /*!< option bytes reload bit */ + +/* FMC_ADDR */ +#define FMC_ADDR_ADDR BITS(0,31) /*!< flash command address bits */ + +/* FMC_OBSTAT */ +#define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error bit */ +#define FMC_OBSTAT_PLEVEL_BIT0 BIT(1) /*!< protection level bit 0 */ +#define FMC_OBSTAT_PLEVEL_BIT1 BIT(2) /*!< protection level bit 1 */ +#define FMC_OBSTAT_USER BITS(8,15) /*!< option bytes user bits */ +#define FMC_OBSTAT_DATA BITS(16,31) /*!< option byte data bits */ + +/* FMC_WSEN */ +#define FMC_WSEN_WSEN BIT(0) /*!< FMC wait state enable bit */ +#define FMC_WSEN_BPEN BIT(1) /*!< FMC bit program enable bit */ + +/* FMC_PID */ +#define FMC_PID_PID BITS(0,31) /*!< product ID bits */ + +/* constants definitions */ +/* fmc state */ +typedef enum +{ + FMC_READY, /*!< the operation has been completed */ + FMC_BUSY, /*!< the operation is in progress */ + FMC_PGERR, /*!< program error */ + FMC_WPERR, /*!< erase/program protection error */ + FMC_TOERR, /*!< timeout error */ + FMC_OB_HSPC /*!< option byte security protection code high */ +}fmc_state_enum; + +/* option byte parameter */ +typedef struct +{ + uint8_t spc; /*!< option byte parameter spc */ + uint8_t user; /*!< option byte parameter user */ + uint8_t data0; /*!< option byte parameter data0 */ + uint8_t data1; /*!< option byte parameter data1 */ + uint8_t wp0; /*!< option byte parameter wp0 */ + uint8_t wp1; /*!< option byte parameter wp1 */ +}ob_parm_struct; + +/* unlock key */ +#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */ +#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */ + +/* wait state counter value */ +#define WS_WSCNT_0 ((uint8_t)0x00U) /*!< 0 wait state added */ +#define WS_WSCNT_1 ((uint8_t)0x01U) /*!< 1 wait state added */ +#define WS_WSCNT_2 ((uint8_t)0x02U) /*!< 2 wait state added */ + +/* read protect configure */ +#define FMC_NSPC ((uint8_t)0xA5U) /*!< no security protection */ +#define FMC_LSPC ((uint8_t)0xBBU) /*!< low security protection, any value except 0xA5 or 0xCC */ +#define FMC_HSPC ((uint8_t)0xCCU) /*!< high security protection */ + +/* option byte write protection */ +#define OB_LWP ((uint32_t)0x000000FFU) /*!< write protection low bits */ +#define OB_HWP ((uint32_t)0x0000FF00U) /*!< write protection high bits */ + +#define OB_FWDGT_HW ((uint8_t)(~BIT(0))) /*!< hardware free watchdog timer */ +#define OB_DEEPSLEEP_RST ((uint8_t)(~BIT(1))) /*!< generate a reset instead of entering deepsleep mode */ +#define OB_STDBY_RST ((uint8_t)(~BIT(2))) /*!< generate a reset instead of entering standby mode */ +#define OB_BOOT1_SET_1 ((uint8_t)(~BIT(4))) /*!< BOOT1 bit is 1 */ +#define OB_VDDA_DISABLE ((uint8_t)(~BIT(5))) /*!< disable VDDA monitor */ +#define OB_SRAM_PARITY_ENABLE ((uint8_t)(~BIT(6))) /*!< enable SRAM parity check */ + +/* option byte security protection level in FMC_OBSTAT register */ +#define OB_OBSTAT_PLEVEL_NO ((uint32_t)0x00000000U) /*!< no security protection */ +#define OB_OBSTAT_PLEVEL_LOW ((uint32_t)0x00000002U) /*!< low security protection */ +#define OB_OBSTAT_PLEVEL_HIGH ((uint32_t)0x00000006U) /*!< high security protection */ + +#define OB_USER_DEFAULT ((uint8_t)0xDFU) /*!< OB_USER default value */ + +/* option byte parameter address */ +#define OB_SPC_ADDR (uint32_t)(OB + 0x00000000U)/*!< option byte spc address */ +#define OB_USER_ADDR (uint32_t)(OB + 0x00000002U)/*!< option byte user address */ +#define OB_DATA_ADDR0 (uint32_t)(OB + 0x00000004U)/*!< option byte data address 0 */ +#define OB_DATA_ADDR1 (uint32_t)(OB + 0x00000006U)/*!< option byte data address 1 */ +#define OB_WP_ADDR0 (uint32_t)(OB + 0x00000008U)/*!< option byte wp address 0 */ +#define OB_WP_ADDR1 (uint32_t)(OB + 0x0000000AU)/*!< option byte wp address 1 */ + +/* FMC flags */ +#define FMC_FLAG_BUSY FMC_STAT_BUSY /*!< FMC busy flag */ +#define FMC_FLAG_PGERR FMC_STAT_PGERR /*!< FMC programming error flag */ +#define FMC_FLAG_WPERR FMC_STAT_WPERR /*!< FMC write protection error flag */ +#define FMC_FLAG_END FMC_STAT_ENDF /*!< FMC end of programming flag */ + +/* FMC interrupt enable */ +#define FMC_INTEN_END FMC_CTL_ENDIE /*!< enable FMC end of operation interrupt */ +#define FMC_INTEN_ERR FMC_CTL_ERRIE /*!< enable FMC error interrupt */ + +/* FMC time out */ +#define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000U) /*!< count to judge of FMC timeout */ + +/* function declarations */ +/* FMC main memory programming functions */ +/* unlock the main FMC operation */ +void fmc_unlock(void); +/* lock the main FMC operation */ +void fmc_lock(void); +/* set the wait state counter value */ +void fmc_wscnt_set(uint8_t wscnt); +/* fmc wait state enable */ +void fmc_wait_state_enable(void); +/* fmc wait state disable */ +void fmc_wait_state_disable(void); +/* FMC erase page */ +fmc_state_enum fmc_page_erase(uint32_t page_address); +/* FMC erase whole chip */ +fmc_state_enum fmc_mass_erase(void); +/* FMC program a word at the corresponding address */ +fmc_state_enum fmc_word_program(uint32_t address, uint32_t data); +/* FMC program a half word at the corresponding address */ +fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data); +/* FMC program a word at the corresponding address without erasing */ +fmc_state_enum fmc_word_reprogram(uint32_t address, uint32_t data); + +/* FMC option bytes programming functions */ +/* unlock the option byte operation */ +void ob_unlock(void); +/* lock the option byte operation */ +void ob_lock(void); +/* reload the option byte and generate a system reset */ +void ob_reset(void); +/* erase option byte */ +fmc_state_enum ob_erase(void); +/* enable option byte write protection (OB_WP) */ +fmc_state_enum ob_write_protection_enable(uint16_t ob_wp); +/* configure read out protect */ +fmc_state_enum ob_security_protection_config(uint8_t ob_spc); +/* write the FMC option byte user */ +fmc_state_enum ob_user_write(uint8_t ob_user); +/* write the FMC option byte data */ +fmc_state_enum ob_data_program(uint32_t address, uint8_t data); +/* get the FMC option byte OB_USER */ +uint8_t ob_user_get(void); +/* get the FMC option byte OB_DATA */ +uint16_t ob_data_get(void); +/* get the FMC option byte write protection */ +uint16_t ob_write_protection_get(void); +/* get the value of FMC option byte security protection level (PLEVEL) in FMC_OBSTAT register */ +uint32_t ob_obstat_plevel_get(void); + +/* FMC interrupts and flags management functions */ +/* enable FMC interrupt */ +void fmc_interrupt_enable(uint32_t interrupt); +/* disable FMC interrupt */ +void fmc_interrupt_disable(uint32_t interrupt); +/* get flag set or reset */ +FlagStatus fmc_flag_get(uint32_t flag); +/* clear the FMC pending flag */ +void fmc_flag_clear(uint32_t flag); +/* get interrupt flag set or reset */ +FlagStatus fmc_interrupt_flag_get(uint32_t flag); +/* clear the FMC interrupt pending flag */ +void fmc_interrupt_flag_clear(uint32_t flag); +/* return the FMC state */ +fmc_state_enum fmc_state_get(void); +/* check FMC ready or not */ +fmc_state_enum fmc_ready_wait(uint32_t timeout); +/* get current option byte value */ +void ob_parm_get(ob_parm_struct *ob_parm); +/* modify the target option byte depending on the original value */ +void ob_value_modify(uint32_t address, uint16_t value,ob_parm_struct *ob_parm); + +#endif /* GD32F3X0_FMC_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_fwdgt.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_fwdgt.h new file mode 100644 index 0000000000..8b2d9db64f --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_fwdgt.h @@ -0,0 +1,124 @@ +/*! + \file gd32f3x0_fwdgt.h + \brief definitions for the FWDGT + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + +#ifndef GD32F3X0_FWDGT_H +#define GD32F3X0_FWDGT_H + +#include "gd32f3x0.h" + +/* FWDGT definitions */ +#define FWDGT FWDGT_BASE + +/* registers definitions */ +#define FWDGT_CTL REG32(FWDGT + 0x00000000U) /*!< FWDGT control register */ +#define FWDGT_PSC REG32(FWDGT + 0x00000004U) /*!< FWDGT prescaler register */ +#define FWDGT_RLD REG32(FWDGT + 0x00000008U) /*!< FWDGT reload register */ +#define FWDGT_STAT REG32(FWDGT + 0x0000000CU) /*!< FWDGT status register */ +#define FWDGT_WND REG32(FWDGT + 0x00000010U) /*!< FWDGT window register */ + +/* bits definitions */ +/* FWDGT_CTL */ +#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */ + +/* FWDGT_PSC */ +#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */ + +/* FWDGT_RLD */ +#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */ + +/* FWDGT_STAT */ +#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */ +#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */ +#define FWDGT_STAT_WUD BIT(2) /*!< FWDGT counter window value update */ + +/* FWDGT_WND */ +#define FWDGT_WND_WND BITS(0,11) /*!< FWDGT counter window value */ + +/* constants definitions */ +/* FWDGT_CTL register value */ +#define CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0U)) /*!< write value to FWDGT_CTL_CMD bit field */ + +/* FWDGT_PSC register value */ +#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0U)) +#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */ +#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */ +#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */ +#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */ +#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */ +#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */ +#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */ + +/* FWDGT_RLD register value */ +#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0U)) /*!< write value to FWDGT_RLD_RLD bit field */ + +/* FWDGT_WND register value */ +#define WND_WND(regval) (BITS(0,11) & ((uint32_t)(regval) << 0U)) /*!< write value to FWDGT_WND_WND bit field */ + +/* control value */ +#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U) /*!< FWDGT_CTL bits write access enable value */ +#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U) /*!< FWDGT_CTL bits write access disable value */ +#define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */ +#define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */ + +/* FWDGT timeout value */ +#define FWDGT_WND_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_WND register write operation state flag timeout */ +#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */ +#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */ + +/* FWDGT flag definitions */ +#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< a write operation to FWDGT_PSC register is on going */ +#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< a write operation to FWDGT_RLD register is on going */ +#define FWDGT_FLAG_WUD FWDGT_STAT_WUD /*!< a write operation to FWDGT_WND register is on going */ + +/* function declarations */ +/* enable write access to FWDGT_PSC and FWDGT_RLD */ +void fwdgt_write_enable(void); +/* disable write access to FWDGT_PSC,FWDGT_RLD and FWDGT_WND */ +void fwdgt_write_disable(void); +/* start the free watchdog timer counter */ +void fwdgt_enable(void); + +/* configure the free watchdog timer counter window value */ +ErrStatus fwdgt_window_value_config(uint16_t window_value); +/* reload the counter of FWDGT */ +void fwdgt_counter_reload(void); +/* configure counter reload value, and prescaler divider value */ +ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div); + +/* get flag state of FWDGT */ +FlagStatus fwdgt_flag_get(uint16_t flag); + +#endif /* GD32F3X0_FWDGT_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_gpio.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_gpio.h new file mode 100644 index 0000000000..045accbd02 --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_gpio.h @@ -0,0 +1,408 @@ +/*! + \file gd32f3x0_gpio.h + \brief definitions for the GPIO + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F3X0_GPIO_H +#define GD32F3X0_GPIO_H + +#include "gd32f3x0.h" + +/* GPIOx(x=A,B,C,D,F) definitions */ +#define GPIOA (GPIO_BASE + 0x00000000U) +#define GPIOB (GPIO_BASE + 0x00000400U) +#define GPIOC (GPIO_BASE + 0x00000800U) +#define GPIOD (GPIO_BASE + 0x00000C00U) +#define GPIOF (GPIO_BASE + 0x00001400U) + +/* registers definitions */ +#define GPIO_CTL(gpiox) REG32((gpiox) + 0x00000000U) /*!< GPIO port control register */ +#define GPIO_OMODE(gpiox) REG32((gpiox) + 0x00000004U) /*!< GPIO port output mode register */ +#define GPIO_OSPD0(gpiox) REG32((gpiox) + 0x00000008U) /*!< GPIO port output speed register 0 */ +#define GPIO_PUD(gpiox) REG32((gpiox) + 0x0000000CU) /*!< GPIO port pull-up/pull-down register */ +#define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x00000010U) /*!< GPIO port input status register */ +#define GPIO_OCTL(gpiox) REG32((gpiox) + 0x00000014U) /*!< GPIO port output control register */ +#define GPIO_BOP(gpiox) REG32((gpiox) + 0x00000018U) /*!< GPIO port bit operation register */ +#define GPIO_LOCK(gpiox) REG32((gpiox) + 0x0000001CU) /*!< GPIO port configuration lock register */ +#define GPIO_AFSEL0(gpiox) REG32((gpiox) + 0x00000020U) /*!< GPIO alternate function selected register 0 */ +#define GPIO_AFSEL1(gpiox) REG32((gpiox) + 0x00000024U) /*!< GPIO alternate function selected register 1 */ +#define GPIO_BC(gpiox) REG32((gpiox) + 0x00000028U) /*!< GPIO bit clear register */ +#define GPIO_TG(gpiox) REG32((gpiox) + 0x0000002CU) /*!< GPIO port bit toggle register */ +#define GPIO_OSPD1(gpiox) REG32((gpiox) + 0x0000003CU) /*!< GPIO port output speed register 1 */ + +/* bits definitions */ +/* GPIO_CTL */ +#define GPIO_CTL_CTL0 BITS(0,1) /*!< pin 0 configuration bits */ +#define GPIO_CTL_CTL1 BITS(2,3) /*!< pin 1 configuration bits */ +#define GPIO_CTL_CTL2 BITS(4,5) /*!< pin 2 configuration bits */ +#define GPIO_CTL_CTL3 BITS(6,7) /*!< pin 3 configuration bits */ +#define GPIO_CTL_CTL4 BITS(8,9) /*!< pin 4 configuration bits */ +#define GPIO_CTL_CTL5 BITS(10,11) /*!< pin 5 configuration bits */ +#define GPIO_CTL_CTL6 BITS(12,13) /*!< pin 6 configuration bits */ +#define GPIO_CTL_CTL7 BITS(14,15) /*!< pin 7 configuration bits */ +#define GPIO_CTL_CTL8 BITS(16,17) /*!< pin 8 configuration bits */ +#define GPIO_CTL_CTL9 BITS(18,19) /*!< pin 9 configuration bits */ +#define GPIO_CTL_CTL10 BITS(20,21) /*!< pin 10 configuration bits */ +#define GPIO_CTL_CTL11 BITS(22,23) /*!< pin 11 configuration bits */ +#define GPIO_CTL_CTL12 BITS(24,25) /*!< pin 12 configuration bits */ +#define GPIO_CTL_CTL13 BITS(26,27) /*!< pin 13 configuration bits */ +#define GPIO_CTL_CTL14 BITS(28,29) /*!< pin 14 configuration bits */ +#define GPIO_CTL_CTL15 BITS(30,31) /*!< pin 15 configuration bits */ + +/* GPIO_OMODE */ +#define GPIO_OMODE_OM0 BIT(0) /*!< pin 0 output mode bit */ +#define GPIO_OMODE_OM1 BIT(1) /*!< pin 1 output mode bit */ +#define GPIO_OMODE_OM2 BIT(2) /*!< pin 2 output mode bit */ +#define GPIO_OMODE_OM3 BIT(3) /*!< pin 3 output mode bit */ +#define GPIO_OMODE_OM4 BIT(4) /*!< pin 4 output mode bit */ +#define GPIO_OMODE_OM5 BIT(5) /*!< pin 5 output mode bit */ +#define GPIO_OMODE_OM6 BIT(6) /*!< pin 6 output mode bit */ +#define GPIO_OMODE_OM7 BIT(7) /*!< pin 7 output mode bit */ +#define GPIO_OMODE_OM8 BIT(8) /*!< pin 8 output mode bit */ +#define GPIO_OMODE_OM9 BIT(9) /*!< pin 9 output mode bit */ +#define GPIO_OMODE_OM10 BIT(10) /*!< pin 10 output mode bit */ +#define GPIO_OMODE_OM11 BIT(11) /*!< pin 11 output mode bit */ +#define GPIO_OMODE_OM12 BIT(12) /*!< pin 12 output mode bit */ +#define GPIO_OMODE_OM13 BIT(13) /*!< pin 13 output mode bit */ +#define GPIO_OMODE_OM14 BIT(14) /*!< pin 14 output mode bit */ +#define GPIO_OMODE_OM15 BIT(15) /*!< pin 15 output mode bit */ + +/* GPIO_OSPD0 */ +#define GPIO_OSPD0_OSPD0 BITS(0,1) /*!< pin 0 output max speed bits */ +#define GPIO_OSPD0_OSPD1 BITS(2,3) /*!< pin 1 output max speed bits */ +#define GPIO_OSPD0_OSPD2 BITS(4,5) /*!< pin 2 output max speed bits */ +#define GPIO_OSPD0_OSPD3 BITS(6,7) /*!< pin 3 output max speed bits */ +#define GPIO_OSPD0_OSPD4 BITS(8,9) /*!< pin 4 output max speed bits */ +#define GPIO_OSPD0_OSPD5 BITS(10,11) /*!< pin 5 output max speed bits */ +#define GPIO_OSPD0_OSPD6 BITS(12,13) /*!< pin 6 output max speed bits */ +#define GPIO_OSPD0_OSPD7 BITS(14,15) /*!< pin 7 output max speed bits */ +#define GPIO_OSPD0_OSPD8 BITS(16,17) /*!< pin 8 output max speed bits */ +#define GPIO_OSPD0_OSPD9 BITS(18,19) /*!< pin 9 output max speed bits */ +#define GPIO_OSPD0_OSPD10 BITS(20,21) /*!< pin 10 output max speed bits */ +#define GPIO_OSPD0_OSPD11 BITS(22,23) /*!< pin 11 output max speed bits */ +#define GPIO_OSPD0_OSPD12 BITS(24,25) /*!< pin 12 output max speed bits */ +#define GPIO_OSPD0_OSPD13 BITS(26,27) /*!< pin 13 output max speed bits */ +#define GPIO_OSPD0_OSPD14 BITS(28,29) /*!< pin 14 output max speed bits */ +#define GPIO_OSPD0_OSPD15 BITS(30,31) /*!< pin 15 output max speed bits */ + +/* GPIO_PUD */ +#define GPIO_PUD_PUD0 BITS(0,1) /*!< pin 0 pull-up or pull-down bits */ +#define GPIO_PUD_PUD1 BITS(2,3) /*!< pin 1 pull-up or pull-down bits */ +#define GPIO_PUD_PUD2 BITS(4,5) /*!< pin 2 pull-up or pull-down bits */ +#define GPIO_PUD_PUD3 BITS(6,7) /*!< pin 3 pull-up or pull-down bits */ +#define GPIO_PUD_PUD4 BITS(8,9) /*!< pin 4 pull-up or pull-down bits */ +#define GPIO_PUD_PUD5 BITS(10,11) /*!< pin 5 pull-up or pull-down bits */ +#define GPIO_PUD_PUD6 BITS(12,13) /*!< pin 6 pull-up or pull-down bits */ +#define GPIO_PUD_PUD7 BITS(14,15) /*!< pin 7 pull-up or pull-down bits */ +#define GPIO_PUD_PUD8 BITS(16,17) /*!< pin 8 pull-up or pull-down bits */ +#define GPIO_PUD_PUD9 BITS(18,19) /*!< pin 9 pull-up or pull-down bits */ +#define GPIO_PUD_PUD10 BITS(20,21) /*!< pin 10 pull-up or pull-down bits */ +#define GPIO_PUD_PUD11 BITS(22,23) /*!< pin 11 pull-up or pull-down bits */ +#define GPIO_PUD_PUD12 BITS(24,25) /*!< pin 12 pull-up or pull-down bits */ +#define GPIO_PUD_PUD13 BITS(26,27) /*!< pin 13 pull-up or pull-down bits */ +#define GPIO_PUD_PUD14 BITS(28,29) /*!< pin 14 pull-up or pull-down bits */ +#define GPIO_PUD_PUD15 BITS(30,31) /*!< pin 15 pull-up or pull-down bits */ + +/* GPIO_ISTAT */ +#define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */ +#define GPIO_ISTAT_ISTAT1 BIT(1) /*!< pin 1 input status */ +#define GPIO_ISTAT_ISTAT2 BIT(2) /*!< pin 2 input status */ +#define GPIO_ISTAT_ISTAT3 BIT(3) /*!< pin 3 input status */ +#define GPIO_ISTAT_ISTAT4 BIT(4) /*!< pin 4 input status */ +#define GPIO_ISTAT_ISTAT5 BIT(5) /*!< pin 5 input status */ +#define GPIO_ISTAT_ISTAT6 BIT(6) /*!< pin 6 input status */ +#define GPIO_ISTAT_ISTAT7 BIT(7) /*!< pin 7 input status */ +#define GPIO_ISTAT_ISTAT8 BIT(8) /*!< pin 8 input status */ +#define GPIO_ISTAT_ISTAT9 BIT(9) /*!< pin 9 input status */ +#define GPIO_ISTAT_ISTAT10 BIT(10) /*!< pin 10 input status */ +#define GPIO_ISTAT_ISTAT11 BIT(11) /*!< pin 11 input status */ +#define GPIO_ISTAT_ISTAT12 BIT(12) /*!< pin 12 input status */ +#define GPIO_ISTAT_ISTAT13 BIT(13) /*!< pin 13 input status */ +#define GPIO_ISTAT_ISTAT14 BIT(14) /*!< pin 14 input status */ +#define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */ + +/* GPIO_OCTL */ +#define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output bit */ +#define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output bit */ +#define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output bit */ +#define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output bit */ +#define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output bit */ +#define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output bit */ +#define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output bit */ +#define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output bit */ +#define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output bit */ +#define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output bit */ +#define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output bit */ +#define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output bit */ +#define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output bit */ +#define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output bit */ +#define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output bit */ +#define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output bit */ + +/* GPIO_BOP */ +#define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */ +#define GPIO_BOP_BOP1 BIT(1) /*!< pin 1 set bit */ +#define GPIO_BOP_BOP2 BIT(2) /*!< pin 2 set bit */ +#define GPIO_BOP_BOP3 BIT(3) /*!< pin 3 set bit */ +#define GPIO_BOP_BOP4 BIT(4) /*!< pin 4 set bit */ +#define GPIO_BOP_BOP5 BIT(5) /*!< pin 5 set bit */ +#define GPIO_BOP_BOP6 BIT(6) /*!< pin 6 set bit */ +#define GPIO_BOP_BOP7 BIT(7) /*!< pin 7 set bit */ +#define GPIO_BOP_BOP8 BIT(8) /*!< pin 8 set bit */ +#define GPIO_BOP_BOP9 BIT(9) /*!< pin 9 set bit */ +#define GPIO_BOP_BOP10 BIT(10) /*!< pin 10 set bit */ +#define GPIO_BOP_BOP11 BIT(11) /*!< pin 11 set bit */ +#define GPIO_BOP_BOP12 BIT(12) /*!< pin 12 set bit */ +#define GPIO_BOP_BOP13 BIT(13) /*!< pin 13 set bit */ +#define GPIO_BOP_BOP14 BIT(14) /*!< pin 14 set bit */ +#define GPIO_BOP_BOP15 BIT(15) /*!< pin 15 set bit */ +#define GPIO_BOP_CR0 BIT(16) /*!< pin 0 clear bit */ +#define GPIO_BOP_CR1 BIT(17) /*!< pin 1 clear bit */ +#define GPIO_BOP_CR2 BIT(18) /*!< pin 2 clear bit */ +#define GPIO_BOP_CR3 BIT(19) /*!< pin 3 clear bit */ +#define GPIO_BOP_CR4 BIT(20) /*!< pin 4 clear bit */ +#define GPIO_BOP_CR5 BIT(21) /*!< pin 5 clear bit */ +#define GPIO_BOP_CR6 BIT(22) /*!< pin 6 clear bit */ +#define GPIO_BOP_CR7 BIT(23) /*!< pin 7 clear bit */ +#define GPIO_BOP_CR8 BIT(24) /*!< pin 8 clear bit */ +#define GPIO_BOP_CR9 BIT(25) /*!< pin 9 clear bit */ +#define GPIO_BOP_CR10 BIT(26) /*!< pin 10 clear bit */ +#define GPIO_BOP_CR11 BIT(27) /*!< pin 11 clear bit */ +#define GPIO_BOP_CR12 BIT(28) /*!< pin 12 clear bit */ +#define GPIO_BOP_CR13 BIT(29) /*!< pin 13 clear bit */ +#define GPIO_BOP_CR14 BIT(30) /*!< pin 14 clear bit */ +#define GPIO_BOP_CR15 BIT(31) /*!< pin 15 clear bit */ + +/* GPIO_LOCK */ +#define GPIO_LOCK_LK0 BIT(0) /*!< pin 0 lock bit */ +#define GPIO_LOCK_LK1 BIT(1) /*!< pin 1 lock bit */ +#define GPIO_LOCK_LK2 BIT(2) /*!< pin 2 lock bit */ +#define GPIO_LOCK_LK3 BIT(3) /*!< pin 3 lock bit */ +#define GPIO_LOCK_LK4 BIT(4) /*!< pin 4 lock bit */ +#define GPIO_LOCK_LK5 BIT(5) /*!< pin 5 lock bit */ +#define GPIO_LOCK_LK6 BIT(6) /*!< pin 6 lock bit */ +#define GPIO_LOCK_LK7 BIT(7) /*!< pin 7 lock bit */ +#define GPIO_LOCK_LK8 BIT(8) /*!< pin 8 lock bit */ +#define GPIO_LOCK_LK9 BIT(9) /*!< pin 9 lock bit */ +#define GPIO_LOCK_LK10 BIT(10) /*!< pin 10 lock bit */ +#define GPIO_LOCK_LK11 BIT(11) /*!< pin 11 lock bit */ +#define GPIO_LOCK_LK12 BIT(12) /*!< pin 12 lock bit */ +#define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */ +#define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */ +#define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */ +#define GPIO_LOCK_LKK BIT(16) /*!< pin sequence lock key */ + +/* GPIO_AFSEL0 */ +#define GPIO_AFSEL0_SEL0 BITS(0,3) /*!< pin 0 alternate function selected */ +#define GPIO_AFSEL0_SEL1 BITS(4,7) /*!< pin 1 alternate function selected */ +#define GPIO_AFSEL0_SEL2 BITS(8,11) /*!< pin 2 alternate function selected */ +#define GPIO_AFSEL0_SEL3 BITS(12,15) /*!< pin 3 alternate function selected */ +#define GPIO_AFSEL0_SEL4 BITS(16,19) /*!< pin 4 alternate function selected */ +#define GPIO_AFSEL0_SEL5 BITS(20,23) /*!< pin 5 alternate function selected */ +#define GPIO_AFSEL0_SEL6 BITS(24,27) /*!< pin 6 alternate function selected */ +#define GPIO_AFSEL0_SEL7 BITS(28,31) /*!< pin 7 alternate function selected */ + +/* GPIO_AFSEL1 */ +#define GPIO_AFSEL1_SEL8 BITS(0,3) /*!< pin 8 alternate function selected */ +#define GPIO_AFSEL1_SEL9 BITS(4,7) /*!< pin 9 alternate function selected */ +#define GPIO_AFSEL1_SEL10 BITS(8,11) /*!< pin 10 alternate function selected */ +#define GPIO_AFSEL1_SEL11 BITS(12,15) /*!< pin 11 alternate function selected */ +#define GPIO_AFSEL1_SEL12 BITS(16,19) /*!< pin 12 alternate function selected */ +#define GPIO_AFSEL1_SEL13 BITS(20,23) /*!< pin 13 alternate function selected */ +#define GPIO_AFSEL1_SEL14 BITS(24,27) /*!< pin 14 alternate function selected */ +#define GPIO_AFSEL1_SEL15 BITS(28,31) /*!< pin 15 alternate function selected */ + +/* GPIO_BC */ +#define GPIO_BC_CR0 BIT(0) /*!< pin 0 clear bit */ +#define GPIO_BC_CR1 BIT(1) /*!< pin 1 clear bit */ +#define GPIO_BC_CR2 BIT(2) /*!< pin 2 clear bit */ +#define GPIO_BC_CR3 BIT(3) /*!< pin 3 clear bit */ +#define GPIO_BC_CR4 BIT(4) /*!< pin 4 clear bit */ +#define GPIO_BC_CR5 BIT(5) /*!< pin 5 clear bit */ +#define GPIO_BC_CR6 BIT(6) /*!< pin 6 clear bit */ +#define GPIO_BC_CR7 BIT(7) /*!< pin 7 clear bit */ +#define GPIO_BC_CR8 BIT(8) /*!< pin 8 clear bit */ +#define GPIO_BC_CR9 BIT(9) /*!< pin 9 clear bit */ +#define GPIO_BC_CR10 BIT(10) /*!< pin 10 clear bit */ +#define GPIO_BC_CR11 BIT(11) /*!< pin 11 clear bit */ +#define GPIO_BC_CR12 BIT(12) /*!< pin 12 clear bit */ +#define GPIO_BC_CR13 BIT(13) /*!< pin 13 clear bit */ +#define GPIO_BC_CR14 BIT(14) /*!< pin 14 clear bit */ +#define GPIO_BC_CR15 BIT(15) /*!< pin 15 clear bit */ + +/* GPIO_TG */ +#define GPIO_TG_TG0 BIT(0) /*!< pin 0 toggle bit */ +#define GPIO_TG_TG1 BIT(1) /*!< pin 1 toggle bit */ +#define GPIO_TG_TG2 BIT(2) /*!< pin 2 toggle bit */ +#define GPIO_TG_TG3 BIT(3) /*!< pin 3 toggle bit */ +#define GPIO_TG_TG4 BIT(4) /*!< pin 4 toggle bit */ +#define GPIO_TG_TG5 BIT(5) /*!< pin 5 toggle bit */ +#define GPIO_TG_TG6 BIT(6) /*!< pin 6 toggle bit */ +#define GPIO_TG_TG7 BIT(7) /*!< pin 7 toggle bit */ +#define GPIO_TG_TG8 BIT(8) /*!< pin 8 toggle bit */ +#define GPIO_TG_TG9 BIT(9) /*!< pin 9 toggle bit */ +#define GPIO_TG_TG10 BIT(10) /*!< pin 10 toggle bit */ +#define GPIO_TG_TG11 BIT(11) /*!< pin 11 toggle bit */ +#define GPIO_TG_TG12 BIT(12) /*!< pin 12 toggle bit */ +#define GPIO_TG_TG13 BIT(13) /*!< pin 13 toggle bit */ +#define GPIO_TG_TG14 BIT(14) /*!< pin 14 toggle bit */ +#define GPIO_TG_TG15 BIT(15) /*!< pin 15 toggle bit */ + +/* GPIO_OSPD1 */ +#define GPIO_OSPD1_SPD0 BIT(0) /*!< set pin 0 very high output speed when OSPD0 is "11" */ +#define GPIO_OSPD1_SPD1 BIT(1) /*!< set pin 1 very high output speed when OSPD1 is "11" */ +#define GPIO_OSPD1_SPD2 BIT(2) /*!< set pin 2 very high output speed when OSPD2 is "11" */ +#define GPIO_OSPD1_SPD3 BIT(3) /*!< set pin 3 very high output speed when OSPD3 is "11" */ +#define GPIO_OSPD1_SPD4 BIT(4) /*!< set pin 4 very high output speed when OSPD4 is "11" */ +#define GPIO_OSPD1_SPD5 BIT(5) /*!< set pin 5 very high output speed when OSPD5 is "11" */ +#define GPIO_OSPD1_SPD6 BIT(6) /*!< set pin 6 very high output speed when OSPD6 is "11" */ +#define GPIO_OSPD1_SPD7 BIT(7) /*!< set pin 7 very high output speed when OSPD7 is "11" */ +#define GPIO_OSPD1_SPD8 BIT(8) /*!< set pin 8 very high output speed when OSPD8 is "11" */ +#define GPIO_OSPD1_SPD9 BIT(9) /*!< set pin 9 very high output speed when OSPD9 is "11" */ +#define GPIO_OSPD1_SPD10 BIT(10) /*!< set pin 10 very high output speed when OSPD10 is "11" */ +#define GPIO_OSPD1_SPD11 BIT(11) /*!< set pin 11 very high output speed when OSPD11 is "11" */ +#define GPIO_OSPD1_SPD12 BIT(12) /*!< set pin 12 very high output speed when OSPD12 is "11" */ +#define GPIO_OSPD1_SPD13 BIT(13) /*!< set pin 13 very high output speed when OSPD13 is "11" */ +#define GPIO_OSPD1_SPD14 BIT(14) /*!< set pin 14 very high output speed when OSPD14 is "11" */ +#define GPIO_OSPD1_SPD15 BIT(15) /*!< set pin 15 very high output speed when OSPD15 is "11" */ + +/* constants definitions */ +typedef FlagStatus bit_status; + +/* output mode definitions */ +#define CTL_CLTR(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define GPIO_MODE_INPUT CTL_CLTR(0) /*!< input mode */ +#define GPIO_MODE_OUTPUT CTL_CLTR(1) /*!< output mode */ +#define GPIO_MODE_AF CTL_CLTR(2) /*!< alternate function mode */ +#define GPIO_MODE_ANALOG CTL_CLTR(3) /*!< analog mode */ + +/* pull-up/pull-down definitions */ +#define PUD_PUPD(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define GPIO_PUPD_NONE PUD_PUPD(0) /*!< floating mode, no pull-up and pull-down resistors */ +#define GPIO_PUPD_PULLUP PUD_PUPD(1) /*!< with pull-up resistor */ +#define GPIO_PUPD_PULLDOWN PUD_PUPD(2) /*!< with pull-down resistor */ + +/* GPIO pin definitions */ +#define GPIO_PIN_0 BIT(0) /*!< GPIO pin 0 */ +#define GPIO_PIN_1 BIT(1) /*!< GPIO pin 1 */ +#define GPIO_PIN_2 BIT(2) /*!< GPIO pin 2 */ +#define GPIO_PIN_3 BIT(3) /*!< GPIO pin 3 */ +#define GPIO_PIN_4 BIT(4) /*!< GPIO pin 4 */ +#define GPIO_PIN_5 BIT(5) /*!< GPIO pin 5 */ +#define GPIO_PIN_6 BIT(6) /*!< GPIO pin 6 */ +#define GPIO_PIN_7 BIT(7) /*!< GPIO pin 7 */ +#define GPIO_PIN_8 BIT(8) /*!< GPIO pin 8 */ +#define GPIO_PIN_9 BIT(9) /*!< GPIO pin 9 */ +#define GPIO_PIN_10 BIT(10) /*!< GPIO pin 10 */ +#define GPIO_PIN_11 BIT(11) /*!< GPIO pin 11 */ +#define GPIO_PIN_12 BIT(12) /*!< GPIO pin 12 */ +#define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */ +#define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */ +#define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */ +#define GPIO_PIN_ALL BITS(0,15) /*!< GPIO pin all */ + +/* GPIO mode configuration values */ +#define GPIO_MODE_SET(n, mode) ((uint32_t)((uint32_t)(mode) << (2U * (n)))) +#define GPIO_MODE_MASK(n) ((uint32_t)((uint32_t)0x00000003U << (2U * (n)))) + +/* GPIO pull-up/pull-down values */ +#define GPIO_PUPD_SET(n, pupd) ((uint32_t)((uint32_t)(pupd) << (2U * (n)))) +#define GPIO_PUPD_MASK(n) ((uint32_t)((uint32_t)0x00000003U << (2U * (n)))) + +/* GPIO output speed values */ +#define GPIO_OSPEED_SET(n, speed) ((uint32_t)((uint32_t)(speed) << (2U * (n)))) +#define GPIO_OSPEED_MASK(n) ((uint32_t)((uint32_t)0x00000003U << (2U * (n)))) + +/* GPIO output type */ +#define GPIO_OTYPE_PP ((uint8_t)(0x00U)) /*!< push pull mode */ +#define GPIO_OTYPE_OD ((uint8_t)(0x01U)) /*!< open drain mode */ + +/* GPIO output max speed value */ +#define OSPD_OSPD0(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define GPIO_OSPEED_2MHZ OSPD_OSPD0(0) /*!< output max speed 2MHz */ +#define GPIO_OSPEED_10MHZ OSPD_OSPD0(1) /*!< output max speed 10MHz */ +#define GPIO_OSPEED_50MHZ OSPD_OSPD0(3) /*!< output max speed 50MHz */ +#define GPIO_OSPEED_MAX ((uint32_t)0x0000FFFFU) /*!< GPIO very high output speed, max speed more than 50MHz */ + +/* GPIO alternate function values */ +#define GPIO_AFR_SET(n, af) ((uint32_t)((uint32_t)(af) << (4U * (n)))) +#define GPIO_AFR_MASK(n) ((uint32_t)((uint32_t)0x0000000FU << (4U * (n)))) + +/* GPIO alternate function */ +#define AF(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) +#define GPIO_AF_0 AF(0) /*!< alternate function 0 selected */ +#define GPIO_AF_1 AF(1) /*!< alternate function 1 selected */ +#define GPIO_AF_2 AF(2) /*!< alternate function 2 selected */ +#define GPIO_AF_3 AF(3) /*!< alternate function 3 selected */ +#define GPIO_AF_4 AF(4) /*!< alternate function 4 selected (port A,B only) */ +#define GPIO_AF_5 AF(5) /*!< alternate function 5 selected (port A,B only) */ +#define GPIO_AF_6 AF(6) /*!< alternate function 6 selected (port A,B only) */ +#define GPIO_AF_7 AF(7) /*!< alternate function 7 selected (port A,B only) */ + +/* function declarations */ +/* reset GPIO port */ +void gpio_deinit(uint32_t gpio_periph); +/* set GPIO mode */ +void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, uint32_t pin); +/* set GPIO output type and speed */ +void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin); + +/* set GPIO pin bit */ +void gpio_bit_set(uint32_t gpio_periph, uint32_t pin); +/* reset GPIO pin bit */ +void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin); +/* write data to the specified GPIO pin */ +void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value); +/* write data to the specified GPIO port */ +void gpio_port_write(uint32_t gpio_periph, uint16_t data); + +/* get GPIO pin input status */ +FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin); +/* get GPIO port input status */ +uint16_t gpio_input_port_get(uint32_t gpio_periph); +/* get GPIO pin output status */ +FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin); +/* get GPIO port output status */ +uint16_t gpio_output_port_get(uint32_t gpio_periph); + +/* set GPIO alternate function */ +void gpio_af_set(uint32_t gpio_periph,uint32_t alt_func_num, uint32_t pin); +/* lock GPIO pin bit */ +void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin); + +/* toggle GPIO pin status */ +void gpio_bit_toggle(uint32_t gpio_periph, uint32_t pin); +/* toggle GPIO port status */ +void gpio_port_toggle(uint32_t gpio_periph); + +#endif /* GD32F3X0_GPIO_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_i2c.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_i2c.h new file mode 100644 index 0000000000..d37cc1cf38 --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_i2c.h @@ -0,0 +1,347 @@ +/*! + \file gd32f3x0_i2c.h + \brief definitions for the I2C + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + +#ifndef GD32F3X0_I2C_H +#define GD32F3X0_I2C_H + +#include "gd32f3x0.h" + +/* I2Cx(x=0,1) definitions */ +#define I2C0 I2C_BASE /*!< I2C0 base address */ +#define I2C1 (I2C_BASE+0x00000400U) /*!< I2C1 base address */ + +/* registers definitions */ +#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00000000U) /*!< I2C control register 0 */ +#define I2C_CTL1(i2cx) REG32((i2cx) + 0x00000004U) /*!< I2C control register 1 */ +#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x00000008U) /*!< I2C slave address register 0*/ +#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0000000CU) /*!< I2C slave address register */ +#define I2C_DATA(i2cx) REG32((i2cx) + 0x00000010U) /*!< I2C transfer buffer register */ +#define I2C_STAT0(i2cx) REG32((i2cx) + 0x00000014U) /*!< I2C transfer status register 0 */ +#define I2C_STAT1(i2cx) REG32((i2cx) + 0x00000018U) /*!< I2C transfer status register */ +#define I2C_CKCFG(i2cx) REG32((i2cx) + 0x0000001CU) /*!< I2C clock configure register */ +#define I2C_RT(i2cx) REG32((i2cx) + 0x00000020U) /*!< I2C rise time register */ +#define I2C_FMPCFG(i2cx) REG32((i2cx) + 0x00000090U) /*!< I2C fast-mode-plus configure register */ + +/* bits definitions */ +/* I2Cx_CTL0 */ +#define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */ +#define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */ +#define I2C_CTL0_SMBSEL BIT(3) /*!< SMBus type */ +#define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */ +#define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */ +#define I2C_CTL0_GCEN BIT(6) /*!< general call enable */ +#define I2C_CTL0_SS BIT(7) /*!< clock stretching disable (slave mode) */ +#define I2C_CTL0_START BIT(8) /*!< start generation */ +#define I2C_CTL0_STOP BIT(9) /*!< stop generation */ +#define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */ +#define I2C_CTL0_POAP BIT(11) /*!< acknowledge/PEC position (for data reception) */ +#define I2C_CTL0_PECTRANS BIT(12) /*!< packet error checking */ +#define I2C_CTL0_SALT BIT(13) /*!< SMBus alert */ +#define I2C_CTL0_SRESET BIT(15) /*!< software reset */ + +/* I2Cx_CTL1 */ +#define I2C_CTL1_I2CCLK BITS(0,6) /*!< I2CCLK[6:0] bits (peripheral clock frequency) */ +#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt inable */ +#define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */ +#define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */ +#define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */ +#define I2C_CTL1_DMALST BIT(12) /*!< DMA last transfer */ + +/* I2Cx_SADDR0 */ +#define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */ +#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ +#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */ +#define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */ + +/* I2Cx_SADDR1 */ +#define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */ +#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */ + +/* I2Cx_DATA */ +#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */ + +/* I2Cx_STAT0 */ +#define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */ +#define I2C_STAT0_ADDSEND BIT(1) /*!< address sent (master mode)/matched (slave mode) */ +#define I2C_STAT0_BTC BIT(2) /*!< byte transfer finished */ +#define I2C_STAT0_ADD10SEND BIT(3) /*!< 10-bit header sent (master mode) */ +#define I2C_STAT0_STPDET BIT(4) /*!< stop detection (slave mode) */ +#define I2C_STAT0_RBNE BIT(6) /*!< data register not empty (receivers) */ +#define I2C_STAT0_TBE BIT(7) /*!< data register empty (transmitters) */ +#define I2C_STAT0_BERR BIT(8) /*!< bus error */ +#define I2C_STAT0_LOSTARB BIT(9) /*!< arbitration lost (master mode) */ +#define I2C_STAT0_AERR BIT(10) /*!< acknowledge failure */ +#define I2C_STAT0_OUERR BIT(11) /*!< overrun/underrun */ +#define I2C_STAT0_PECERR BIT(12) /*!< PEC error in reception */ +#define I2C_STAT0_SMBTO BIT(14) /*!< timeout signal in SMBus mode */ +#define I2C_STAT0_SMBALT BIT(15) /*!< SMBus alert status */ + +/* I2Cx_STAT1 */ +#define I2C_STAT1_MASTER BIT(0) /*!< master/slave */ +#define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */ +#define I2C_STAT1_TR BIT(2) /*!< transmitter/receiver */ +#define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */ +#define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */ +#define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */ +#define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */ +#define I2C_STAT1_PECV BITS(8,15) /*!< packet error checking value */ + +/* I2Cx_CKCFG */ +#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode or fast mode plus(master mode) */ +#define I2C_CKCFG_DTCY BIT(14) /*!< duty cycle of fast mode or fast mode plus */ +#define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */ + +/* I2Cx_RT */ +#define I2C_RT_RISETIME BITS(0,6) /*!< maximum rise time in fast/standard mode or fast mode plus(master mode) */ + +/* I2Cx_FMPCFG */ +#define I2C_FMPCFG_FMPEN BIT(0) /*!< fast mode plus enable bit */ + +/* constants definitions */ +/* define the I2C bit position and its register index offset */ +#define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6))) +#define I2C_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU) +#define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ + | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) +#define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22))) +#define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16) + +/* register offset */ +#define I2C_CTL1_REG_OFFSET (0x00000004U) /*!< CTL1 register offset */ +#define I2C_STAT0_REG_OFFSET (0x00000014U) /*!< STAT0 register offset */ +#define I2C_STAT1_REG_OFFSET (0x00000018U) /*!< STAT1 register offset */ +/* I2C flags */ +typedef enum +{ + /* flags in STAT0 register */ + I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */ + I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */ + I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ + I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */ + I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */ + I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not empty during receiving */ + I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */ + I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */ + I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */ + I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */ + I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */ + I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */ + I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */ + I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */ + /* flags in STAT1 register */ + I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */ + I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */ + I2C_FLAG_TR = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */ + I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */ + I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */ + I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */ + I2C_FLAG_DUMOD = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U) /*!< dual flag in slave mode indicating which address is matched in dual-address mode */ +}i2c_flag_enum; + +/* I2C interrupt flags */ +typedef enum +{ + /* interrupt flags in CTL1 register */ + I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode interrupt flag */ + I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode interrupt flag */ + I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ + I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */ + I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */ + I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not empty during receiving interrupt flag */ + I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */ + I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */ + I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode interrupt flag */ + I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error interrupt flag */ + I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode interrupt flag */ + I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data interrupt flag */ + I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode interrupt flag */ + I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus Alert status interrupt flag */ +}i2c_interrupt_flag_enum; + +/* I2C interrupt enable or disable */ +typedef enum +{ + /* interrupt in CTL1 register */ + I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt enable */ + I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt enable */ + I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt enable */ +}i2c_interrupt_enum; + +/* SMBus/I2C mode switch and SMBus type selection */ +#define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */ +#define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */ + +/* SMBus/I2C mode switch and SMBus type selection */ +#define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */ +#define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */ + +/* I2C transfer direction */ +#define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */ +#define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */ + +/* whether or not to send an ACK */ +#define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */ +#define I2C_ACK_ENABLE ((uint32_t)0x00000001U) /*!< ACK will be sent */ + +/* I2C POAP position*/ +#define I2C_ACKPOS_NEXT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK for the next byte */ +#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000001U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */ + +/* whether or not to stretch SCL low */ +#define I2C_SCLSTRETCH_DISABLE I2C_CTL0_SS /*!< SCL stretching is enabled */ +#define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U) /*!< SCL stretching is disabled */ + +/* whether or not to response to a general call */ +#define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */ +#define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */ + +/* software reset I2C */ +#define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */ +#define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */ + +/* I2C DMA mode configure */ +/* DMA mode switch */ +#define I2C_DMA_ON I2C_CTL1_DMAON /*!< DMA mode enabled */ +#define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< DMA mode disabled */ + +/* flag indicating DMA last transfer */ +#define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */ +#define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */ + +/* I2C PEC configure */ +/* PEC enable */ +#define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */ +#define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */ + +/* PEC transfer */ +#define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC */ +#define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */ + +/* I2C SMBus configure */ +/* issue or not alert through SMBA pin */ +#define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */ +#define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */ + +/* ARP protocol in SMBus switch */ +#define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< ARP enable */ +#define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< ARP disable */ + +/* fast mode plus enable */ +#define I2C_FAST_MODE_PLUS_ENABLE I2C_FMPCFG_FMPEN /*!< fast mode plus enable */ +#define I2C_FAST_MODE_PLUS_DISABLE ((uint32_t)0x00000000U) /*!< fast mode plus disable */ + +/* transmit I2C data */ +#define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) + +/* receive I2C data */ +#define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7) + +/* I2C duty cycle in fast mode or fast mode plus */ +#define I2C_DTCY_2 ((uint32_t)0x00000000U) /*!< in I2C fast mode or fast mode plus Tlow/Thigh = 2 */ +#define I2C_DTCY_16_9 I2C_CKCFG_DTCY /*!< in I2C fast mode or fast mode plus Tlow/Thigh = 16/9 */ + +/* address mode for the I2C slave */ +#define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address:7 bits */ +#define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address:10 bits */ + +/* function declarations */ +/* reset I2C */ +void i2c_deinit(uint32_t i2c_periph); +/* configure I2C clock */ +void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc); +/* configure I2C address */ +void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr); +/* SMBus type selection */ +void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type); +/* whether or not to send an ACK */ +void i2c_ack_config(uint32_t i2c_periph, uint32_t ack); +/* configure I2C position of ACK and PEC when receiving */ +void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos); +/* master sends slave address */ +void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection); +/* enable dual-address mode */ +void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr); +/* disable dual-address mode */ +void i2c_dualaddr_disable(uint32_t i2c_periph); +/* enable I2C */ +void i2c_enable(uint32_t i2c_periph); +/* disable I2C */ +void i2c_disable(uint32_t i2c_periph); + +/* generate a START condition on I2C bus */ +void i2c_start_on_bus(uint32_t i2c_periph); +/* generate a STOP condition on I2C bus */ +void i2c_stop_on_bus(uint32_t i2c_periph); +/* I2C transmit data function */ +void i2c_data_transmit(uint32_t i2c_periph, uint8_t data); +/* I2C receive data function */ +uint8_t i2c_data_receive(uint32_t i2c_periph); +/* enable I2C DMA mode */ +void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate); +/* configure whether next DMA EOT is DMA last transfer or not */ +void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast); +/* whether to stretch SCL low when data is not ready in slave mode */ +void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara); +/* whether or not to response to a general call */ +void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara); +/* software reset I2C */ +void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset); + +/* whether to enable I2C PEC calculation or not */ +void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate); +/* I2C whether to transfer PEC value */ +void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara); +/* packet error checking value */ +uint8_t i2c_pec_value_get(uint32_t i2c_periph); +/* I2C issue alert through SMBA pin */ +void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara); +/* whether ARP is enabled under SMBus */ +void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate); + +/* check I2C flag is set or not */ +FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag); +/* clear I2C flag */ +void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag); +/* enable I2C interrupt */ +void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); +/* disable I2C interrupt */ +void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); +/* check I2C interrupt flag */ +FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); +/* clear I2C interrupt flag */ +void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); +#endif /* GD32F3X0_I2C_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_misc.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_misc.h new file mode 100644 index 0000000000..08586feda5 --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_misc.h @@ -0,0 +1,92 @@ +/*! + \file gd32f3x0_misc.h + \brief definitions for the MISC + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F3X0_MISC_H +#define GD32F3X0_MISC_H + +#include "gd32f3x0.h" + +/* constants definitions */ +/* set the RAM and FLASH base address */ +#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< RAM base address */ +#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< Flash base address */ + +/* set the NVIC vector table offset mask */ +#define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80) /*!< NVIC vector table offset mask */ + +/* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */ +#define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) /*!< NVIC VECTKEY mask */ + +/* priority group - define the pre-emption priority and the subpriority */ +#define NVIC_PRIGROUP_PRE0_SUB4 ((uint32_t)0x00000700) /*!< 0 bits for pre-emption priority 4 bits for subpriority */ +#define NVIC_PRIGROUP_PRE1_SUB3 ((uint32_t)0x00000600) /*!< 1 bits for pre-emption priority 3 bits for subpriority */ +#define NVIC_PRIGROUP_PRE2_SUB2 ((uint32_t)0x00000500) /*!< 2 bits for pre-emption priority 2 bits for subpriority */ +#define NVIC_PRIGROUP_PRE3_SUB1 ((uint32_t)0x00000400) /*!< 3 bits for pre-emption priority 1 bits for subpriority */ +#define NVIC_PRIGROUP_PRE4_SUB0 ((uint32_t)0x00000300) /*!< 4 bits for pre-emption priority 0 bits for subpriority */ + +/* choose the method to enter or exit the lowpower mode */ +#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< choose the the system whether enter low power mode by exiting from ISR */ +#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */ +#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< choose the interrupt source that can wake up the lowpower mode */ + +#define SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT /*!< low power mode by exiting from ISR */ +#define SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP /*!< DEEPSLEEP mode or SLEEP mode */ +#define SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND /*!< wakeup by all interrupt */ + +/* choose the systick clock source */ +#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */ +#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */ + +/* function declarations */ +/* set the priority group */ +void nvic_priority_group_set(uint32_t nvic_prigroup); + +/* enable NVIC request */ +void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority); +/* disable NVIC request */ +void nvic_irq_disable(uint8_t nvic_irq); + +/* set the NVIC vector table base address */ +void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset); + +/* set the state of the low power mode */ +void system_lowpower_set(uint8_t lowpower_mode); +/* reset the state of the low power mode */ +void system_lowpower_reset(uint8_t lowpower_mode); + +/* set the systick clock source */ +void systick_clksource_set(uint32_t systick_clksource); + +#endif /* GD32F3X0_MISC_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_pmu.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_pmu.h new file mode 100644 index 0000000000..230180bf9c --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_pmu.h @@ -0,0 +1,197 @@ +/*! + \file gd32f3x0_pmu.h + \brief definitions for the PMU + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F3X0_PMU_H +#define GD32F3X0_PMU_H + +#include "gd32f3x0.h" + +/* PMU definitions */ +#define PMU PMU_BASE /*!< PMU base address */ + +/* registers definitions */ +#define PMU_CTL REG32(PMU + 0x00000000U) /*!< PMU control register */ +#define PMU_CS REG32(PMU + 0x00000004U) /*!< PMU control and status register */ + +/* bits definitions */ +/* PMU_CTL */ +#define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */ +#define PMU_CTL_STBMOD BIT(1) /*!< standby mode */ +#define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */ +#define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */ +#define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */ +#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */ +#define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */ +#define PMU_CTL_LDLP BIT(10) /*!< low-driver mode when use low power LDO */ +#define PMU_CTL_LDNP BIT(11) /*!< low-driver mode when use normal power LDO */ +#define PMU_CTL_LDOVS BITS(14,15) /*!< LDO output voltage select */ +#define PMU_CTL_HDEN BIT(16) /*!< high-driver mode enable */ +#define PMU_CTL_HDS BIT(17) /*!< high-driver mode switch */ +#define PMU_CTL_LDEN BITS(18,19) /*!< low-driver mode enable in deep-sleep mode */ + +/* PMU_CS */ +#define PMU_CS_WUF BIT(0) /*!< wakeup flag */ +#define PMU_CS_STBF BIT(1) /*!< standby flag */ +#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */ +#define PMU_CS_WUPEN0 BIT(8) /*!< wakeup pin enable */ +#define PMU_CS_WUPEN1 BIT(9) /*!< wakeup pin enable */ +#define PMU_CS_WUPEN4 BIT(12) /*!< wakeup pin enable */ +#define PMU_CS_WUPEN5 BIT(13) /*!< wakeup pin enable */ +#define PMU_CS_WUPEN6 BIT(14) /*!< wakeup pin enable */ +#define PMU_CS_LDOVSRF BIT(15) /*!< LDO voltage select ready flag */ +#define PMU_CS_HDRF BIT(16) /*!< high-driver ready flag */ +#define PMU_CS_HDSRF BIT(17) /*!< high-driver switch ready flag */ +#define PMU_CS_LDRF BITS(18,19) /*!< low-driver mode ready flag */ + +/* constants definitions */ +/* PMU low voltage detector threshold definitions */ +#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5)) +#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.1V */ +#define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */ +#define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */ +#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.6V */ +#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.7V */ +#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.9V */ +#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 3.0V */ +#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 3.1V */ + +/* PMU LDO output voltage select definitions */ +#define CTL_LDOVS(regval) (BITS(14,15)&((uint32_t)(regval)<<14)) +#define PMU_LDOVS_LOW CTL_LDOVS(1) /*!< LDO output voltage low mode */ +#define PMU_LDOVS_MID CTL_LDOVS(2) /*!< LDO output voltage mid mode */ +#define PMU_LDOVS_HIGH CTL_LDOVS(3) /*!< LDO output voltage high mode */ + +/* PMU low-driver mode enable in deep-sleep mode */ +#define CTL_LDEN(regval) (BITS(18,19)&((uint32_t)(regval)<<18)) +#define PMU_LOWDRIVER_DISABLE CTL_LDEN(0) /*!< low-driver mode disable in deep-sleep mode */ +#define PMU_LOWDRIVER_ENABLE CTL_LDEN(3) /*!< low-driver mode enable in deep-sleep mode */ + +/* PMU high-driver mode switch */ +#define PMU_HIGHDR_SWITCH_NONE ((uint32_t)0x00000000U) /*!< no high-driver mode switch */ +#define PMU_HIGHDR_SWITCH_EN PMU_CTL_HDS /*!< high-driver mode switch */ + +/* PMU low-driver mode when use normal power LDO */ +#define PMU_NORMALDR_NORMALPWR ((uint32_t)0x00000000U) /*!< normal-driver when use normal power LDO */ +#define PMU_LOWDR_NORMALPWR PMU_CTL_LDNP /*!< low-driver mode enabled when LDEN is 11 and use normal power LDO */ + +/* PMU low-driver mode when use low power LDO */ +#define PMU_NORMALDR_LOWPWR ((uint32_t)0x00000000U) /*!< normal-driver when use low power LDO */ +#define PMU_LOWDR_LOWPWR PMU_CTL_LDLP /*!< low-driver mode enabled when LDEN is 11 and use low power LDO */ + +/* PMU ldo definitions */ +#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO operates normally when PMU enter deepsleep mode */ +#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */ + +/* PMU low power mode ready flag definitions */ +#define CS_LDRF(regval) (BITS(18,19)&((uint32_t)(regval)<<18)) +#define PMU_LDRF_NORMAL CS_LDRF(0) /*!< normal-driver in deep-sleep mode */ +#define PMU_LDRF_LOWDRIVER CS_LDRF(3) /*!< low-driver mode in deep-sleep mode */ + +/* PMU flag definitions */ +#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */ +#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */ +#define PMU_FLAG_LVD PMU_CS_LVDF /*!< LVD flag status */ +#define PMU_FLAG_LDOVSR PMU_CS_LDOVSRF /*!< LDO voltage select ready flag */ +#define PMU_FLAG_HDR PMU_CS_HDRF /*!< high-driver ready flag */ +#define PMU_FLAG_HDSR PMU_CS_HDSRF /*!< high-driver switch ready flag */ +#define PMU_FLAG_LDR PMU_CS_LDRF /*!< low-driver mode ready flag */ + +/* PMU WKUP pin definitions */ +#define PMU_WAKEUP_PIN0 PMU_CS_WUPEN0 /*!< WKUP Pin 0 (PA0) enable */ +#define PMU_WAKEUP_PIN1 PMU_CS_WUPEN1 /*!< WKUP Pin 1 (PC13) enable */ +#define PMU_WAKEUP_PIN4 PMU_CS_WUPEN4 /*!< WKUP Pin 4 (PC5) enable */ +#define PMU_WAKEUP_PIN5 PMU_CS_WUPEN5 /*!< WKUP Pin 5 (PB5) enable */ +#define PMU_WAKEUP_PIN6 PMU_CS_WUPEN6 /*!< WKUP Pin 6 (PB15) enable */ + +/* PMU flag reset definitions */ +#define PMU_FLAG_RESET_WAKEUP PMU_CTL_WURST /*!< wakeup flag reset */ +#define PMU_FLAG_RESET_STANDBY PMU_CTL_STBRST /*!< standby flag reset */ + +/* PMU command constants definitions */ +#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */ +#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */ + +/* function declarations */ +/* function configuration */ +/* reset PMU registers */ +void pmu_deinit(void); +/* select low voltage detector threshold */ +void pmu_lvd_select(uint32_t lvdt_n); +/* select LDO output voltage */ +void pmu_ldo_output_select(uint32_t ldo_output); +/* disable PMU lvd */ +void pmu_lvd_disable(void); + +/* functions of low-driver mode and high-driver mode in deep-sleep mode */ +/* enable low-driver mode in deep-sleep mode */ +void pmu_lowdriver_mode_enable(void); +/* disable low-driver mode in deep-sleep mode */ +void pmu_lowdriver_mode_disable(void); +/* enable high-driver mode */ +void pmu_highdriver_mode_enable(void); +/* disable high-driver mode */ +void pmu_highdriver_mode_disable(void); +/* switch high-driver mode */ +void pmu_highdriver_switch_select(uint32_t highdr_switch); +/* in deep-sleep mode, low-driver mode when use low power LDO */ +void pmu_lowpower_driver_config(uint32_t mode); +/* in deep-sleep mode, low-driver mode when use normal power LDO */ +void pmu_normalpower_driver_config(uint32_t mode); + +/* set PMU mode */ +/* PMU work in sleep mode */ +void pmu_to_sleepmode(uint8_t sleepmodecmd); +/* PMU work in deepsleep mode */ +void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd); +/* PMU work in standby mode */ +void pmu_to_standbymode(uint8_t standbymodecmd); +/* enable PMU wakeup pin */ +void pmu_wakeup_pin_enable(uint32_t wakeup_pin); +/* disable PMU wakeup pin */ +void pmu_wakeup_pin_disable(uint32_t wakeup_pin); + +/* backup related functions */ +/* enable backup domain write */ +void pmu_backup_write_enable(void); +/* disable backup domain write */ +void pmu_backup_write_disable(void); + +/* flag functions */ +/* clear flag bit */ +void pmu_flag_clear(uint32_t flag_clear); +/* get flag state */ +FlagStatus pmu_flag_get(uint32_t flag); + +#endif /* GD32F3X0_PMU_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_rcu.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_rcu.h new file mode 100644 index 0000000000..b870b69db1 --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_rcu.h @@ -0,0 +1,797 @@ +/*! + \file gd32f3x0_rcu.h + \brief definitions for the RCU + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F3X0_RCU_H +#define GD32F3X0_RCU_H + +#include "gd32f3x0.h" + +/* RCU definitions */ +#define RCU RCU_BASE + +/* registers definitions */ +#define RCU_CTL0 REG32(RCU + 0x00000000U) /*!< control register 0 */ +#define RCU_CFG0 REG32(RCU + 0x00000004U) /*!< configuration register 0 */ +#define RCU_INT REG32(RCU + 0x00000008U) /*!< interrupt register */ +#define RCU_APB2RST REG32(RCU + 0x0000000CU) /*!< APB2 reset register */ +#define RCU_APB1RST REG32(RCU + 0x00000010U) /*!< APB1 reset register */ +#define RCU_AHBEN REG32(RCU + 0x00000014U) /*!< AHB enable register */ +#define RCU_APB2EN REG32(RCU + 0x00000018U) /*!< APB2 enable register */ +#define RCU_APB1EN REG32(RCU + 0x0000001CU) /*!< APB1 enable register */ +#define RCU_BDCTL REG32(RCU + 0x00000020U) /*!< backup domain control register */ +#define RCU_RSTSCK REG32(RCU + 0x00000024U) /*!< reset source /clock register */ +#define RCU_AHBRST REG32(RCU + 0x00000028U) /*!< AHB reset register */ +#define RCU_CFG1 REG32(RCU + 0x0000002CU) /*!< configuration register 1 */ +#define RCU_CFG2 REG32(RCU + 0x00000030U) /*!< configuration register 2 */ +#define RCU_CTL1 REG32(RCU + 0x00000034U) /*!< control register 1 */ +#define RCU_ADDCTL REG32(RCU + 0x000000C0U) /*!< additional clock control register */ +#define RCU_ADDINT REG32(RCU + 0x000000CCU) /*!< additional clock interrupt register */ +#define RCU_ADDAPB1EN REG32(RCU + 0x000000F8U) /*!< APB1 additional enable register */ +#define RCU_ADDAPB1RST REG32(RCU + 0x000000FCU) /*!< APB1 additional reset register */ +#define RCU_VKEY REG32(RCU + 0x00000100U) /*!< voltage key register */ +#define RCU_DSV REG32(RCU + 0x00000134U) /*!< deep-sleep mode voltage register */ + +/* bits definitions */ +/* RCU_CTL0 */ +#define RCU_CTL0_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */ +#define RCU_CTL0_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ +#define RCU_CTL0_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ +#define RCU_CTL0_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ +#define RCU_CTL0_HXTALEN BIT(16) /*!< external high speed oscillator enable */ +#define RCU_CTL0_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ +#define RCU_CTL0_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ +#define RCU_CTL0_CKMEN BIT(19) /*!< HXTAL clock monitor enable */ +#define RCU_CTL0_PLLEN BIT(24) /*!< PLL enable */ +#define RCU_CTL0_PLLSTB BIT(25) /*!< PLL clock stabilization flag */ + +/* RCU_CFG0 */ +#define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ +#define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ +#define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ +#define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */ +#define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */ +#define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC clock prescaler selection */ +#define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */ +#define RCU_CFG0_PLLPREDV BIT(17) /*!< divider for PLL source clock selection */ +#define RCU_CFG0_PLLMF (BIT(27) | BITS(18,21)) /*!< PLL multiply factor */ +#define RCU_CFG0_USBFSPSC BITS(22,23) /*!< USBFS clock prescaler selection */ +#define RCU_CFG0_CKOUTSEL BITS(24,26) /*!< CK_OUT clock source selection */ +#define RCU_CFG0_PLLMF4 BIT(27) /*!< bit 4 of PLLMF */ +#define RCU_CFG0_CKOUTDIV BITS(28,30) /*!< CK_OUT divider which the CK_OUT frequency can be reduced */ +#define RCU_CFG0_PLLDV BIT(31) /*!< CK_PLL divide by 1 or 2 */ + +/* RCU_INT */ +#define RCU_INT_IRC40KSTBIF BIT(0) /*!< IRC40K stabilization interrupt flag */ +#define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */ +#define RCU_INT_IRC8MSTBIF BIT(2) /*!< IRC8M stabilization interrupt flag */ +#define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */ +#define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */ +#define RCU_INT_IRC28MSTBIF BIT(5) /*!< IRC28M stabilization interrupt flag */ +#define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */ +#define RCU_INT_IRC40KSTBIE BIT(8) /*!< IRC40K stabilization interrupt enable */ +#define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */ +#define RCU_INT_IRC8MSTBIE BIT(10) /*!< IRC8M stabilization interrupt enable */ +#define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */ +#define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */ +#define RCU_INT_IRC28MSTBIE BIT(13) /*!< IRC28M stabilization interrupt enable */ +#define RCU_INT_IRC40KSTBIC BIT(16) /*!< IRC40K stabilization interrupt clear */ +#define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL stabilization interrupt clear */ +#define RCU_INT_IRC8MSTBIC BIT(18) /*!< IRC8M stabilization interrupt clear */ +#define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL stabilization interrupt clear */ +#define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization interrupt clear */ +#define RCU_INT_IRC28MSTBIC BIT(21) /*!< IRC28M stabilization interrupt clear */ +#define RCU_INT_CKMIC BIT(23) /*!< HXTAL clock stuck interrupt clear */ + +/* RCU_APB2RST */ +#define RCU_APB2RST_CFGRST BIT(0) /*!< system configuration reset */ +#define RCU_APB2RST_ADCRST BIT(9) /*!< ADC reset */ +#define RCU_APB2RST_TIMER0RST BIT(11) /*!< TIMER0 reset */ +#define RCU_APB2RST_SPI0RST BIT(12) /*!< SPI0 reset */ +#define RCU_APB2RST_USART0RST BIT(14) /*!< USART0 reset */ +#define RCU_APB2RST_TIMER14RST BIT(16) /*!< TIMER14 reset */ +#define RCU_APB2RST_TIMER15RST BIT(17) /*!< TIMER15 reset */ +#define RCU_APB2RST_TIMER16RST BIT(18) /*!< TIMER16 reset */ + +/* RCU_APB1RST */ +#define RCU_APB1RST_TIMER1RST BIT(0) /*!< TIMER1 timer reset */ +#define RCU_APB1RST_TIMER2RST BIT(1) /*!< TIMER2 timer reset */ +#define RCU_APB1RST_TIMER5RST BIT(4) /*!< TIMER5 timer reset */ +#define RCU_APB1RST_TIMER13RST BIT(8) /*!< TIMER13 timer reset */ +#define RCU_APB1RST_WWDGTRST BIT(11) /*!< window watchdog timer reset */ +#define RCU_APB1RST_SPI1RST BIT(14) /*!< SPI1 reset */ +#define RCU_APB1RST_USART1RST BIT(17) /*!< USART1 reset */ +#define RCU_APB1RST_I2C0RST BIT(21) /*!< I2C0 reset */ +#define RCU_APB1RST_I2C1RST BIT(22) /*!< I2C1 reset */ +#define RCU_APB1RST_PMURST BIT(28) /*!< power control reset */ +#define RCU_APB1RST_DACRST BIT(29) /*!< DAC reset */ +#define RCU_APB1RST_CECRST BIT(30) /*!< HDMI CEC reset */ + +/* RCU_AHBEN */ +#define RCU_AHBEN_DMAEN BIT(0) /*!< DMA clock enable */ +#define RCU_AHBEN_SRAMSPEN BIT(2) /*!< SRAM interface clock enable */ +#define RCU_AHBEN_FMCSPEN BIT(4) /*!< FMC clock enable */ +#define RCU_AHBEN_CRCEN BIT(6) /*!< CRC clock enable */ +#define RCU_AHBEN_USBFS BIT(12) /*!< USBFS clock enable */ +#define RCU_AHBEN_PAEN BIT(17) /*!< GPIO port A clock enable */ +#define RCU_AHBEN_PBEN BIT(18) /*!< GPIO port B clock enable */ +#define RCU_AHBEN_PCEN BIT(19) /*!< GPIO port C clock enable */ +#define RCU_AHBEN_PDEN BIT(20) /*!< GPIO port D clock enable */ +#define RCU_AHBEN_PFEN BIT(22) /*!< GPIO port F clock enable */ +#define RCU_AHBEN_TSIEN BIT(24) /*!< TSI clock enable */ + +/* RCU_APB2EN */ +#define RCU_APB2EN_CFGCMPEN BIT(0) /*!< system configuration and comparator clock enable */ +#define RCU_APB2EN_ADCEN BIT(9) /*!< ADC interface clock enable */ +#define RCU_APB2EN_TIMER0EN BIT(11) /*!< TIMER0 timer clock enable */ +#define RCU_APB2EN_SPI0EN BIT(12) /*!< SPI0 clock enable */ +#define RCU_APB2EN_USART0EN BIT(14) /*!< USART0 clock enable */ +#define RCU_APB2EN_TIMER14EN BIT(16) /*!< TIMER14 timer clock enable */ +#define RCU_APB2EN_TIMER15EN BIT(17) /*!< TIMER15 timer clock enable */ +#define RCU_APB2EN_TIMER16EN BIT(18) /*!< TIMER16 timer clock enable */ + +/* RCU_APB1EN */ +#define RCU_APB1EN_TIMER1EN BIT(0) /*!< TIMER1 timer clock enable */ +#define RCU_APB1EN_TIMER2EN BIT(1) /*!< TIMER2 timer clock enable */ +#define RCU_APB1EN_TIMER5EN BIT(4) /*!< TIMER5 timer clock enable */ +#define RCU_APB1EN_TIMER13EN BIT(8) /*!< TIMER13 timer clock enable */ +#define RCU_APB1EN_WWDGTEN BIT(11) /*!< window watchdog timer clock enable */ +#define RCU_APB1EN_SPI1EN BIT(14) /*!< SPI1 clock enable */ +#define RCU_APB1EN_USART1EN BIT(17) /*!< USART1 clock enable */ +#define RCU_APB1EN_I2C0EN BIT(21) /*!< I2C0 clock enable */ +#define RCU_APB1EN_I2C1EN BIT(22) /*!< I2C1 clock enable */ +#define RCU_APB1EN_PMUEN BIT(28) /*!< power interface clock enable */ +#define RCU_APB1EN_DACEN BIT(29) /*!< DAC interface clock enable */ +#define RCU_APB1EN_CECEN BIT(30) /*!< HDMI CEC interface clock enable */ + +/* RCU_BDCTL */ +#define RCU_BDCTL_LXTALEN BIT(0) /*!< LXTAL enable */ +#define RCU_BDCTL_LXTALSTB BIT(1) /*!< external low-speed oscillator stabilization */ +#define RCU_BDCTL_LXTALBPS BIT(2) /*!< LXTAL bypass mode enable */ +#define RCU_BDCTL_LXTALDRI BITS(3,4) /*!< LXTAL drive capability */ +#define RCU_BDCTL_RTCSRC BITS(8,9) /*!< RTC clock entry selection */ +#define RCU_BDCTL_RTCEN BIT(15) /*!< RTC clock enable */ +#define RCU_BDCTL_BKPRST BIT(16) /*!< backup domain reset */ + +/* RCU_RSTSCK */ +#define RCU_RSTSCK_IRC40KEN BIT(0) /*!< IRC40K enable */ +#define RCU_RSTSCK_IRC40KSTB BIT(1) /*!< IRC40K stabilization */ +#define RCU_RSTSCK_V12RSTF BIT(23) /*!< V12 domain power reset flag */ +#define RCU_RSTSCK_RSTFC BIT(24) /*!< reset flag clear */ +#define RCU_RSTSCK_OBLRSTF BIT(25) /*!< option byte loader reset flag */ +#define RCU_RSTSCK_EPRSTF BIT(26) /*!< external pin reset flag */ +#define RCU_RSTSCK_PORRSTF BIT(27) /*!< power reset flag */ +#define RCU_RSTSCK_SWRSTF BIT(28) /*!< software reset flag */ +#define RCU_RSTSCK_FWDGTRSTF BIT(29) /*!< free watchdog timer reset flag */ +#define RCU_RSTSCK_WWDGTRSTF BIT(30) /*!< window watchdog timer reset flag */ +#define RCU_RSTSCK_LPRSTF BIT(31) /*!< low-power reset flag */ + +/* RCU_AHBRST */ +#define RCU_AHBRST_USBFSRST BIT(12) /*!< USBFS reset */ +#define RCU_AHBRST_PARST BIT(17) /*!< GPIO port A reset */ +#define RCU_AHBRST_PBRST BIT(18) /*!< GPIO port B reset */ +#define RCU_AHBRST_PCRST BIT(19) /*!< GPIO port C reset */ +#define RCU_AHBRST_PDRST BIT(20) /*!< GPIO port D reset */ +#define RCU_AHBRST_PFRST BIT(22) /*!< GPIO port F reset */ +#define RCU_AHBRST_TSIRST BIT(24) /*!< TSI unit reset */ + +/* RCU_CFG1 */ +#define RCU_CFG1_PREDV BITS(0,3) /*!< CK_HXTAL divider previous PLL */ +#define RCU_CFG1_PLLPRESEL BIT(30) /*!< PLL clock source preselection */ +#define RCU_CFG1_PLLMF5 BIT(31) /*!< bit 5 of PLLMF */ + +/* RCU_CFG2 */ +#define RCU_CFG2_USART0SEL BITS(0,1) /*!< CK_USART0 clock source selection */ +#define RCU_CFG2_CECSEL BIT(6) /*!< CK_CEC clock source selection */ +#define RCU_CFG2_ADCSEL BIT(8) /*!< CK_ADC clock source selection */ +#define RCU_CFG2_IRC28MDIV BIT(16) /*!< CK_IRC28M divider 2 or not */ +#define RCU_CFG2_USBFSPSC2 BIT(30) /*!< bit 2 of USBFSPSC */ +#define RCU_CFG2_ADCPSC2 BIT(31) /*!< bit 2 of ADCPSC */ + +/* RCU_CTL1 */ +#define RCU_CTL1_IRC28MEN BIT(0) /*!< IRC28M internal 28M RC oscillator enable */ +#define RCU_CTL1_IRC28MSTB BIT(1) /*!< IRC28M internal 28M RC oscillator stabilization flag */ +#define RCU_CTL1_IRC28MADJ BITS(3,7) /*!< internal 28M RC oscillator clock trim adjust value */ +#define RCU_CTL1_IRC28MCALIB BITS(8,15) /*!< internal 28M RC oscillator calibration value register */ + +/* RCU_ADDCTL */ +#define RCU_ADDCTL_CK48MSEL BIT(0) /*!< 48M clock selection */ +#define RCU_ADDCTL_IRC48MEN BIT(16) /*!< IRC48M internal 48M RC oscillator enable */ +#define RCU_ADDCTL_IRC48MSTB BIT(17) /*!< internal 48M RC oscillator stabilization flag */ +#define RCU_ADDCTL_IRC48MCALIB BITS(24,31) /*!< internal 48M RC oscillator calibration value register */ + +/* RCU_ADDINT */ +#define RCU_ADDINT_IRC48MSTBIF BIT(6) /*!< IRC48M stabilization interrupt flag */ +#define RCU_ADDINT_IRC48MSTBIE BIT(14) /*!< IRC48M stabilization interrupt enable */ +#define RCU_ADDINT_IRC48MSTBIC BIT(22) /*!< IRC48M stabilization interrupt clear */ + +/* RCU_ADDAPB1EN */ +#define RCU_ADDAPB1EN_CTCEN BIT(27) /*!< CTC unit clock enable */ + +/* RCU_ADDAPB1RST */ +#define RCU_ADDAPB1RST_CTCRST BIT(27) /*!< CTC unit reset */ + +/* RCU_VKEY */ +#define RCU_VKEY_KEY BITS(0,31) /*!< key of RCU_DSV register */ + +/* RCU_DSV */ +#define RCU_DSV_DSLPVS BITS(0,1) /*!< deep-sleep mode voltage select */ + +/* constants definitions */ +/* define the peripheral clock enable bit position and its register index offset */ +#define RCU_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx)<<6) | (uint32_t)(bitpos)) +#define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph)>>6))) +#define RCU_BIT_POS(val) ((uint32_t)(val) & (uint32_t)0x0000001FU) +/* define the voltage key unlock value */ +#define RCU_VKEY_UNLOCK ((uint32_t)0x1A2B3C4DU) + +/* register index */ +typedef enum +{ + /* peripherals enable */ + IDX_AHBEN = ((uint32_t)0x00000014U), + IDX_APB2EN = ((uint32_t)0x00000018U), + IDX_APB1EN = ((uint32_t)0x0000001CU), + IDX_ADDAPB1EN = ((uint32_t)0x000000F8U), + /* peripherals reset */ + IDX_AHBRST = ((uint32_t)0x00000028U), + IDX_APB2RST = ((uint32_t)0x0000000CU), + IDX_APB1RST = ((uint32_t)0x00000010U), + IDX_ADDAPB1RST = ((uint32_t)0x000000FCU), + /* clock stabilization */ + IDX_CTL0 = ((uint32_t)0x00000000U), + IDX_BDCTL = ((uint32_t)0x00000020U), + IDX_CTL1 = ((uint32_t)0x00000034U), + IDX_ADDCTL = ((uint32_t)0x000000C0U), + /* peripheral reset */ + IDX_RSTSCK = ((uint32_t)0x00000024U), + /* clock stabilization and stuck interrupt */ + IDX_INT = ((uint32_t)0x00000008U), + IDX_ADDINT = ((uint32_t)0x000000CCU), + /* configuration register */ + IDX_CFG0 = ((uint32_t)0x00000004U), + IDX_CFG2 = ((uint32_t)0x00000030U) +}reg_idx; + +/* peripheral clock enable */ +typedef enum +{ + /* AHB peripherals */ + RCU_DMA = RCU_REGIDX_BIT(IDX_AHBEN, 0U), /*!< DMA clock */ + RCU_CRC = RCU_REGIDX_BIT(IDX_AHBEN, 6U), /*!< CRC clock */ + RCU_GPIOA = RCU_REGIDX_BIT(IDX_AHBEN, 17U), /*!< GPIOA clock */ + RCU_GPIOB = RCU_REGIDX_BIT(IDX_AHBEN, 18U), /*!< GPIOB clock */ + RCU_GPIOC = RCU_REGIDX_BIT(IDX_AHBEN, 19U), /*!< GPIOC clock */ + RCU_GPIOD = RCU_REGIDX_BIT(IDX_AHBEN, 20U), /*!< GPIOD clock */ + RCU_GPIOF = RCU_REGIDX_BIT(IDX_AHBEN, 22U), /*!< GPIOF clock */ + RCU_TSI = RCU_REGIDX_BIT(IDX_AHBEN, 24U), /*!< TSI clock */ + + /* APB2 peripherals */ + RCU_CFGCMP = RCU_REGIDX_BIT(IDX_APB2EN, 0U), /*!< CFGCMP clock */ + RCU_ADC = RCU_REGIDX_BIT(IDX_APB2EN, 9U), /*!< ADC clock */ + RCU_TIMER0 = RCU_REGIDX_BIT(IDX_APB2EN, 11U), /*!< TIMER0 clock */ + RCU_SPI0 = RCU_REGIDX_BIT(IDX_APB2EN, 12U), /*!< SPI0 clock */ + RCU_USART0 = RCU_REGIDX_BIT(IDX_APB2EN, 14U), /*!< USART0 clock */ + RCU_TIMER14 = RCU_REGIDX_BIT(IDX_APB2EN, 16U), /*!< TIMER14 clock */ + RCU_TIMER15 = RCU_REGIDX_BIT(IDX_APB2EN, 17U), /*!< TIMER15 clock */ + RCU_TIMER16 = RCU_REGIDX_BIT(IDX_APB2EN, 18U), /*!< TIMER16 clock */ + + /* APB1 peripherals */ + RCU_TIMER1 = RCU_REGIDX_BIT(IDX_APB1EN, 0U), /*!< TIMER1 clock */ + RCU_TIMER2 = RCU_REGIDX_BIT(IDX_APB1EN, 1U), /*!< TIMER2 clock */ + RCU_TIMER13 = RCU_REGIDX_BIT(IDX_APB1EN, 8U), /*!< TIMER13 clock */ + RCU_WWDGT = RCU_REGIDX_BIT(IDX_APB1EN, 11U), /*!< WWDGT clock */ + RCU_SPI1 = RCU_REGIDX_BIT(IDX_APB1EN, 14U), /*!< SPI1 clock */ + RCU_USART1 = RCU_REGIDX_BIT(IDX_APB1EN, 17U), /*!< USART1 clock */ + RCU_I2C0 = RCU_REGIDX_BIT(IDX_APB1EN, 21U), /*!< I2C0 clock */ + RCU_I2C1 = RCU_REGIDX_BIT(IDX_APB1EN, 22U), /*!< I2C1 clock */ + RCU_PMU = RCU_REGIDX_BIT(IDX_APB1EN, 28U), /*!< PMU clock */ +#if defined(GD32F350) + RCU_DAC = RCU_REGIDX_BIT(IDX_APB1EN, 29U), /*!< DAC clock */ + RCU_CEC = RCU_REGIDX_BIT(IDX_APB1EN, 30U), /*!< CEC clock */ + RCU_TIMER5 = RCU_REGIDX_BIT(IDX_APB1EN, 4U), /*!< TIMER5 clock */ + RCU_USBFS = RCU_REGIDX_BIT(IDX_AHBEN, 12U), /*!< USBFS clock */ +#endif /* GD32F350 */ + RCU_RTC = RCU_REGIDX_BIT(IDX_BDCTL, 15U), /*!< RTC clock */ + + /* RCU_ADDAPB1EN */ + RCU_CTC = RCU_REGIDX_BIT(IDX_ADDAPB1EN, 27U) /*!< CTC clock */ +}rcu_periph_enum; + +/* peripheral clock enable when sleep mode*/ +typedef enum +{ + /* AHB peripherals */ + RCU_SRAM_SLP = RCU_REGIDX_BIT(IDX_AHBEN, 2U), /*!< SRAM clock */ + RCU_FMC_SLP = RCU_REGIDX_BIT(IDX_AHBEN, 4U), /*!< FMC clock */ +}rcu_periph_sleep_enum; + +/* peripherals reset */ +typedef enum +{ + /* AHB peripherals reset */ + RCU_GPIOARST = RCU_REGIDX_BIT(IDX_AHBRST, 17U), /*!< GPIOA reset */ + RCU_GPIOBRST = RCU_REGIDX_BIT(IDX_AHBRST, 18U), /*!< GPIOB reset */ + RCU_GPIOCRST = RCU_REGIDX_BIT(IDX_AHBRST, 19U), /*!< GPIOC reset */ + RCU_GPIODRST = RCU_REGIDX_BIT(IDX_AHBRST, 20U), /*!< GPIOD reset */ + RCU_GPIOFRST = RCU_REGIDX_BIT(IDX_AHBRST, 22U), /*!< GPIOF reset */ + RCU_TSIRST = RCU_REGIDX_BIT(IDX_AHBRST, 24U), /*!< TSI reset */ + + /* APB2 peripherals reset */ + RCU_CFGCMPRST = RCU_REGIDX_BIT(IDX_APB2RST, 0U), /*!< CFGCMP reset */ + RCU_ADCRST = RCU_REGIDX_BIT(IDX_APB2RST, 9U), /*!< ADC reset */ + RCU_TIMER0RST = RCU_REGIDX_BIT(IDX_APB2RST, 11U), /*!< TIMER0 reset */ + RCU_SPI0RST = RCU_REGIDX_BIT(IDX_APB2RST, 12U), /*!< SPI0 reset */ + RCU_USART0RST = RCU_REGIDX_BIT(IDX_APB2RST, 14U), /*!< USART0 reset */ + RCU_TIMER14RST = RCU_REGIDX_BIT(IDX_APB2RST, 16U), /*!< TIMER14 reset */ + RCU_TIMER15RST = RCU_REGIDX_BIT(IDX_APB2RST, 17U), /*!< TIMER15 reset */ + RCU_TIMER16RST = RCU_REGIDX_BIT(IDX_APB2RST, 18U), /*!< TIMER16 reset */ + + /* APB1 peripherals reset */ + RCU_TIMER1RST = RCU_REGIDX_BIT(IDX_APB1RST, 0U), /*!< TIMER1 reset */ + RCU_TIMER2RST = RCU_REGIDX_BIT(IDX_APB1RST, 1U), /*!< TIMER2 reset */ + RCU_TIMER13RST = RCU_REGIDX_BIT(IDX_APB1RST, 8U), /*!< TIMER13 reset */ + RCU_WWDGTRST = RCU_REGIDX_BIT(IDX_APB1RST, 11U), /*!< WWDGT reset */ + RCU_SPI1RST = RCU_REGIDX_BIT(IDX_APB1RST, 14U), /*!< SPI1 reset */ + RCU_USART1RST = RCU_REGIDX_BIT(IDX_APB1RST, 17U), /*!< USART1 reset */ + RCU_I2C0RST = RCU_REGIDX_BIT(IDX_APB1RST, 21U), /*!< I2C0 reset */ + RCU_I2C1RST = RCU_REGIDX_BIT(IDX_APB1RST, 22U), /*!< I2C1 reset */ + RCU_PMURST = RCU_REGIDX_BIT(IDX_APB1RST, 28U), /*!< PMU reset */ +#if defined(GD32F350) + RCU_DACRST = RCU_REGIDX_BIT(IDX_APB1RST, 29U), /*!< DAC reset */ + RCU_CECRST = RCU_REGIDX_BIT(IDX_APB1RST, 30U), /*!< CEC reset */ + RCU_TIMER5RST = RCU_REGIDX_BIT(IDX_APB1RST, 4U), /*!< TIMER5 reset */ + RCU_USBFSRST = RCU_REGIDX_BIT(IDX_AHBRST, 12U), /*!< USBFS reset */ +#endif /* GD32F350 */ + /* RCU_ADDAPB1RST */ + RCU_CTCRST = RCU_REGIDX_BIT(IDX_ADDAPB1RST, 27U), /*!< CTC reset */ +}rcu_periph_reset_enum; + +/* clock stabilization and peripheral reset flags */ +typedef enum +{ + RCU_FLAG_IRC40KSTB = RCU_REGIDX_BIT(IDX_RSTSCK, 1U), /*!< IRC40K stabilization flags */ + RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(IDX_BDCTL, 1U), /*!< LXTAL stabilization flags */ + RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(IDX_CTL0, 1U), /*!< IRC8M stabilization flags */ + RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(IDX_CTL0, 17U), /*!< HXTAL stabilization flags */ + RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(IDX_CTL0, 25U), /*!< PLL stabilization flags */ + RCU_FLAG_IRC28MSTB = RCU_REGIDX_BIT(IDX_CTL1, 1U), /*!< IRC28M stabilization flags */ + RCU_FLAG_IRC48MSTB = RCU_REGIDX_BIT(IDX_ADDCTL, 17U), /*!< IRC48M stabilization flags */ + + RCU_FLAG_V12RST = RCU_REGIDX_BIT(IDX_RSTSCK, 23U), /*!< V12 reset flags */ + RCU_FLAG_OBLRST = RCU_REGIDX_BIT(IDX_RSTSCK, 25U), /*!< OBL reset flags */ + RCU_FLAG_EPRST = RCU_REGIDX_BIT(IDX_RSTSCK, 26U), /*!< EPR reset flags */ + RCU_FLAG_PORRST = RCU_REGIDX_BIT(IDX_RSTSCK, 27U), /*!< power reset flags */ + RCU_FLAG_SWRST = RCU_REGIDX_BIT(IDX_RSTSCK, 28U), /*!< SW reset flags */ + RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(IDX_RSTSCK, 29U), /*!< FWDGT reset flags */ + RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(IDX_RSTSCK, 30U), /*!< WWDGT reset flags */ + RCU_FLAG_LPRST = RCU_REGIDX_BIT(IDX_RSTSCK, 31U) /*!< LP reset flags */ +}rcu_flag_enum; + +/* clock stabilization and ckm interrupt flags */ +typedef enum +{ + RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(IDX_INT, 0U), /*!< IRC40K stabilization interrupt flag */ + RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(IDX_INT, 1U), /*!< LXTAL stabilization interrupt flag */ + RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(IDX_INT, 2U), /*!< IRC8M stabilization interrupt flag */ + RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(IDX_INT, 3U), /*!< HXTAL stabilization interrupt flag */ + RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(IDX_INT, 4U), /*!< PLL stabilization interrupt flag */ + RCU_INT_FLAG_IRC28MSTB = RCU_REGIDX_BIT(IDX_INT, 5U), /*!< IRC28M stabilization interrupt flag */ + RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(IDX_INT, 7U), /*!< CKM interrupt flag */ + RCU_INT_FLAG_IRC48MSTB = RCU_REGIDX_BIT(IDX_ADDCTL, 6U) /*!< IRC48M stabilization interrupt flag */ +}rcu_int_flag_enum; + +/* clock stabilization and stuck interrupt flags clear */ +typedef enum +{ + RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 16U), /*!< IRC40K stabilization interrupt flags clear */ + RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 17U), /*!< LXTAL stabilization interrupt flags clear */ + RCU_INT_FLAG_IRC8MSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 18U), /*!< IRC8M stabilization interrupt flags clear */ + RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 19U), /*!< HXTAL stabilization interrupt flags clear */ + RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 20U), /*!< PLL stabilization interrupt flags clear */ + RCU_INT_FLAG_IRC28MSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 21U), /*!< IRC28M stabilization interrupt flags clear */ + RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(IDX_INT, 23U), /*!< CKM interrupt flags clear */ + RCU_INT_FLAG_IRC48MSTB_CLR = RCU_REGIDX_BIT(IDX_ADDCTL, 22U) /*!< IRC48M stabilization interrupt flag clear */ +}rcu_int_flag_clear_enum; + +/* clock stabilization interrupt enable or disable */ +typedef enum +{ + RCU_INT_IRC40KSTB = RCU_REGIDX_BIT(IDX_INT, 8U), /*!< IRC40K stabilization interrupt */ + RCU_INT_LXTALSTB = RCU_REGIDX_BIT(IDX_INT, 9U), /*!< LXTAL stabilization interrupt */ + RCU_INT_IRC8MSTB = RCU_REGIDX_BIT(IDX_INT, 10U), /*!< IRC8M stabilization interrupt */ + RCU_INT_HXTALSTB = RCU_REGIDX_BIT(IDX_INT, 11U), /*!< HXTAL stabilization interrupt */ + RCU_INT_PLLSTB = RCU_REGIDX_BIT(IDX_INT, 12U), /*!< PLL stabilization interrupt */ + RCU_INT_IRC28MSTB = RCU_REGIDX_BIT(IDX_INT, 13U), /*!< IRC28M stabilization interrupt */ + RCU_INT_IRC48MSTB = RCU_REGIDX_BIT(IDX_ADDINT, 14U) /*!< IRC48M stabilization interrupt */ +}rcu_int_enum; + +/* ADC clock source */ +typedef enum +{ + RCU_ADCCK_IRC28M_DIV2 = 0U, /*!< ADC clock source select IRC28M/2 */ + RCU_ADCCK_IRC28M, /*!< ADC clock source select IRC28M */ + RCU_ADCCK_APB2_DIV2, /*!< ADC clock source select APB2/2 */ + RCU_ADCCK_AHB_DIV3, /*!< ADC clock source select AHB/3 */ + RCU_ADCCK_APB2_DIV4, /*!< ADC clock source select APB2/4 */ + RCU_ADCCK_AHB_DIV5, /*!< ADC clock source select AHB/5 */ + RCU_ADCCK_APB2_DIV6, /*!< ADC clock source select APB2/6 */ + RCU_ADCCK_AHB_DIV7, /*!< ADC clock source select AHB/7 */ + RCU_ADCCK_APB2_DIV8, /*!< ADC clock source select APB2/8 */ + RCU_ADCCK_AHB_DIV9 /*!< ADC clock source select AHB/9 */ +}rcu_adc_clock_enum; + +/* oscillator types */ +typedef enum +{ + RCU_HXTAL = RCU_REGIDX_BIT(IDX_CTL0, 16U), /*!< HXTAL */ + RCU_LXTAL = RCU_REGIDX_BIT(IDX_BDCTL, 0U), /*!< LXTAL */ + RCU_IRC8M = RCU_REGIDX_BIT(IDX_CTL0, 0U), /*!< IRC8M */ + RCU_IRC28M = RCU_REGIDX_BIT(IDX_CTL1, 0U), /*!< IRC28M */ + RCU_IRC48M = RCU_REGIDX_BIT(IDX_ADDCTL, 16U), /*!< IRC48M */ + RCU_IRC40K = RCU_REGIDX_BIT(IDX_RSTSCK, 0U), /*!< IRC40K */ + RCU_PLL_CK = RCU_REGIDX_BIT(IDX_CTL0, 24U) /*!< PLL */ +}rcu_osci_type_enum; + +/* rcu clock frequency */ +typedef enum +{ + CK_SYS = 0U, /*!< system clock */ + CK_AHB, /*!< AHB clock */ + CK_APB1, /*!< APB1 clock */ + CK_APB2, /*!< APB2 clock */ + CK_ADC, /*!< ADC clock */ + CK_CEC, /*!< CEC clock */ + CK_USART /*!< USART clock */ +}rcu_clock_freq_enum; + +/* system clock source select */ +#define CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define RCU_CKSYSSRC_IRC8M CFG0_SCS(0) /*!< system clock source select IRC8M */ +#define RCU_CKSYSSRC_HXTAL CFG0_SCS(1) /*!< system clock source select HXTAL */ +#define RCU_CKSYSSRC_PLL CFG0_SCS(2) /*!< system clock source select PLL */ + +/* system clock source select status */ +#define CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) +#define RCU_SCSS_IRC8M CFG0_SCSS(0) /*!< system clock source select IRC8M */ +#define RCU_SCSS_HXTAL CFG0_SCSS(1) /*!< system clock source select HXTAL */ +#define RCU_SCSS_PLL CFG0_SCSS(2) /*!< system clock source select PLL */ + +/* AHB prescaler selection */ +#define CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) +#define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0) /*!< AHB prescaler select CK_SYS */ +#define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8) /*!< AHB prescaler select CK_SYS/2 */ +#define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9) /*!< AHB prescaler select CK_SYS/4 */ +#define RCU_AHB_CKSYS_DIV8 CFG0_AHBPSC(10) /*!< AHB prescaler select CK_SYS/8 */ +#define RCU_AHB_CKSYS_DIV16 CFG0_AHBPSC(11) /*!< AHB prescaler select CK_SYS/16 */ +#define RCU_AHB_CKSYS_DIV64 CFG0_AHBPSC(12) /*!< AHB prescaler select CK_SYS/64 */ +#define RCU_AHB_CKSYS_DIV128 CFG0_AHBPSC(13) /*!< AHB prescaler select CK_SYS/128 */ +#define RCU_AHB_CKSYS_DIV256 CFG0_AHBPSC(14) /*!< AHB prescaler select CK_SYS/256 */ +#define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15) /*!< AHB prescaler select CK_SYS/512 */ + +/* APB1 prescaler selection */ +#define CFG0_APB1PSC(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) +#define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0) /*!< APB1 prescaler select CK_AHB */ +#define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4) /*!< APB1 prescaler select CK_AHB/2 */ +#define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5) /*!< APB1 prescaler select CK_AHB/4 */ +#define RCU_APB1_CKAHB_DIV8 CFG0_APB1PSC(6) /*!< APB1 prescaler select CK_AHB/8 */ +#define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7) /*!< APB1 prescaler select CK_AHB/16 */ + +/* APB2 prescaler selection */ +#define CFG0_APB2PSC(regval) (BITS(11,13) & ((uint32_t)(regval) << 11)) +#define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0) /*!< APB2 prescaler select CK_AHB */ +#define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4) /*!< APB2 prescaler select CK_AHB/2 */ +#define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5) /*!< APB2 prescaler select CK_AHB/4 */ +#define RCU_APB2_CKAHB_DIV8 CFG0_APB2PSC(6) /*!< APB2 prescaler select CK_AHB/8 */ +#define RCU_APB2_CKAHB_DIV16 CFG0_APB2PSC(7) /*!< APB2 prescaler select CK_AHB/16 */ + +/* ADC clock prescaler selection */ +#define CFG0_ADCPSC(regval) (BITS(14,15) & ((uint32_t)(regval) << 14)) +#define RCU_ADC_CKAPB2_DIV2 CFG0_ADCPSC(0) /*!< ADC clock prescaler select CK_APB2/2 */ +#define RCU_ADC_CKAPB2_DIV4 CFG0_ADCPSC(1) /*!< ADC clock prescaler select CK_APB2/4 */ +#define RCU_ADC_CKAPB2_DIV6 CFG0_ADCPSC(2) /*!< ADC clock prescaler select CK_APB2/6 */ +#define RCU_ADC_CKAPB2_DIV8 CFG0_ADCPSC(3) /*!< ADC clock prescaler select CK_APB2/8 */ + +/* PLL clock source selection */ +#define RCU_PLLSRC_IRC8M_DIV2 ((uint32_t)0x00000000U) /*!< PLL clock source select IRC8M/2 */ +#define RCU_PLLSRC_HXTAL_IRC48M RCU_CFG0_PLLSEL /*!< PLL clock source select HXTAL or IRC48M*/ + +/* PLL clock source preselection */ +#define RCU_PLLPRESEL_HXTAL ((uint32_t)0x00000000U) /*!< PLL clock source preselection HXTAL */ +#define RCU_PLLPRESEL_IRC48M RCU_CFG1_PLLPRESEL /*!< PLL clock source preselection IRC48M */ + +/* HXTAL or IRC48M divider for PLL source clock selection */ +#define RCU_PLLPREDV ((uint32_t)0x00000000U) /*!< HXTAL or IRC48M clock selected */ +#define RCU_PLLPREDV_DIV2 RCU_CFG0_PLLPREDV /*!< (HXTAL or IRC48M) /2 clock selected */ + +/* PLL multiply factor */ +#define CFG0_PLLMF(regval) (BITS(18,21) & ((uint32_t)(regval) << 18)) +#define RCU_PLL_MUL2 CFG0_PLLMF(0) /*!< PLL source clock multiply by 2 */ +#define RCU_PLL_MUL3 CFG0_PLLMF(1) /*!< PLL source clock multiply by 3 */ +#define RCU_PLL_MUL4 CFG0_PLLMF(2) /*!< PLL source clock multiply by 4 */ +#define RCU_PLL_MUL5 CFG0_PLLMF(3) /*!< PLL source clock multiply by 5 */ +#define RCU_PLL_MUL6 CFG0_PLLMF(4) /*!< PLL source clock multiply by 6 */ +#define RCU_PLL_MUL7 CFG0_PLLMF(5) /*!< PLL source clock multiply by 7 */ +#define RCU_PLL_MUL8 CFG0_PLLMF(6) /*!< PLL source clock multiply by 8 */ +#define RCU_PLL_MUL9 CFG0_PLLMF(7) /*!< PLL source clock multiply by 9 */ +#define RCU_PLL_MUL10 CFG0_PLLMF(8) /*!< PLL source clock multiply by 10 */ +#define RCU_PLL_MUL11 CFG0_PLLMF(9) /*!< PLL source clock multiply by 11 */ +#define RCU_PLL_MUL12 CFG0_PLLMF(10) /*!< PLL source clock multiply by 12 */ +#define RCU_PLL_MUL13 CFG0_PLLMF(11) /*!< PLL source clock multiply by 13 */ +#define RCU_PLL_MUL14 CFG0_PLLMF(12) /*!< PLL source clock multiply by 14 */ +#define RCU_PLL_MUL15 CFG0_PLLMF(13) /*!< PLL source clock multiply by 15 */ +#define RCU_PLL_MUL16 CFG0_PLLMF(14) /*!< PLL source clock multiply by 16 */ +#define RCU_PLL_MUL17 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(0)) /*!< PLL source clock multiply by 17 */ +#define RCU_PLL_MUL18 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(1)) /*!< PLL source clock multiply by 18 */ +#define RCU_PLL_MUL19 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(2)) /*!< PLL source clock multiply by 19 */ +#define RCU_PLL_MUL20 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(3)) /*!< PLL source clock multiply by 20 */ +#define RCU_PLL_MUL21 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(4)) /*!< PLL source clock multiply by 21 */ +#define RCU_PLL_MUL22 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(5)) /*!< PLL source clock multiply by 22 */ +#define RCU_PLL_MUL23 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(6)) /*!< PLL source clock multiply by 23 */ +#define RCU_PLL_MUL24 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(7)) /*!< PLL source clock multiply by 24 */ +#define RCU_PLL_MUL25 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(8)) /*!< PLL source clock multiply by 25 */ +#define RCU_PLL_MUL26 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(9)) /*!< PLL source clock multiply by 26 */ +#define RCU_PLL_MUL27 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(10)) /*!< PLL source clock multiply by 27 */ +#define RCU_PLL_MUL28 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(11)) /*!< PLL source clock multiply by 28 */ +#define RCU_PLL_MUL29 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(12)) /*!< PLL source clock multiply by 29 */ +#define RCU_PLL_MUL30 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(13)) /*!< PLL source clock multiply by 30 */ +#define RCU_PLL_MUL31 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(14)) /*!< PLL source clock multiply by 31 */ +#define RCU_PLL_MUL32 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(15)) /*!< PLL source clock multiply by 32 */ +#define RCU_PLL_MUL33 (CFG0_PLLMF(0) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 33 */ +#define RCU_PLL_MUL34 (CFG0_PLLMF(1) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 34 */ +#define RCU_PLL_MUL35 (CFG0_PLLMF(2) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 35 */ +#define RCU_PLL_MUL36 (CFG0_PLLMF(3) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 36 */ +#define RCU_PLL_MUL37 (CFG0_PLLMF(4) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 37 */ +#define RCU_PLL_MUL38 (CFG0_PLLMF(5) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 38 */ +#define RCU_PLL_MUL39 (CFG0_PLLMF(6) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 39 */ +#define RCU_PLL_MUL40 (CFG0_PLLMF(7) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 40 */ +#define RCU_PLL_MUL41 (CFG0_PLLMF(8) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 41 */ +#define RCU_PLL_MUL42 (CFG0_PLLMF(9) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 42 */ +#define RCU_PLL_MUL43 (CFG0_PLLMF(10) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 43 */ +#define RCU_PLL_MUL44 (CFG0_PLLMF(11) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 44 */ +#define RCU_PLL_MUL45 (CFG0_PLLMF(12) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 45 */ +#define RCU_PLL_MUL46 (CFG0_PLLMF(13) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 46 */ +#define RCU_PLL_MUL47 (CFG0_PLLMF(14) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 47 */ +#define RCU_PLL_MUL48 (CFG0_PLLMF(15) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 48 */ +#define RCU_PLL_MUL49 (RCU_CFG0_PLLMF4 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 49 */ +#define RCU_PLL_MUL50 (RCU_PLL_MUL18 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 50 */ +#define RCU_PLL_MUL51 (RCU_PLL_MUL19 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 51 */ +#define RCU_PLL_MUL52 (RCU_PLL_MUL20 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 52 */ +#define RCU_PLL_MUL53 (RCU_PLL_MUL21 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 53 */ +#define RCU_PLL_MUL54 (RCU_PLL_MUL22 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 54 */ +#define RCU_PLL_MUL55 (RCU_PLL_MUL23 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 55 */ +#define RCU_PLL_MUL56 (RCU_PLL_MUL24 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 56 */ +#define RCU_PLL_MUL57 (RCU_PLL_MUL25 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 57 */ +#define RCU_PLL_MUL58 (RCU_PLL_MUL26 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 58 */ +#define RCU_PLL_MUL59 (RCU_PLL_MUL27 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 59 */ +#define RCU_PLL_MUL60 (RCU_PLL_MUL28 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 60 */ +#define RCU_PLL_MUL61 (RCU_PLL_MUL29 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 61 */ +#define RCU_PLL_MUL62 (RCU_PLL_MUL30 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 62 */ +#define RCU_PLL_MUL63 (RCU_PLL_MUL31 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 63 */ +#define RCU_PLL_MUL64 (RCU_PLL_MUL32 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 64 */ + +/* USBFS clock prescaler selection */ +#define CFG0_USBFSPSC(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) +#define RCU_USBFS_CKPLL_DIV1_5 CFG0_USBFSPSC(0) /*!< USBFS clock prescaler select CK_PLL/1.5 */ +#define RCU_USBFS_CKPLL_DIV1 CFG0_USBFSPSC(1) /*!< USBFS clock prescaler select CK_PLL */ +#define RCU_USBFS_CKPLL_DIV2_5 CFG0_USBFSPSC(2) /*!< USBFS clock prescaler select CK_PLL/2.5 */ +#define RCU_USBFS_CKPLL_DIV2 CFG0_USBFSPSC(3) /*!< USBFS clock prescaler select CK_PLL/2 */ +#define RCU_USBFS_CKPLL_DIV3 RCU_CFG2_USBFSPSC2 /*!< USBFS clock prescaler select CK_PLL/3 */ +#define RCU_USBFS_CKPLL_DIV3_5 (CFG0_USBFSPSC(1)|RCU_CFG2_USBFSPSC2) /*!< USBFS clock prescaler select CK_PLL/3.5 */ + +/* CK_OUT clock source selection */ +#define CFG0_CKOUTSEL(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) +#define RCU_CKOUTSRC_NONE CFG0_CKOUTSEL(0) /*!< no clock selected */ +#define RCU_CKOUTSRC_IRC28M CFG0_CKOUTSEL(1) /*!< CK_OUT clock source select IRC28M */ +#define RCU_CKOUTSRC_IRC40K CFG0_CKOUTSEL(2) /*!< CK_OUT clock source select IRC40K */ +#define RCU_CKOUTSRC_LXTAL CFG0_CKOUTSEL(3) /*!< CK_OUT clock source select LXTAL */ +#define RCU_CKOUTSRC_CKSYS CFG0_CKOUTSEL(4) /*!< CK_OUT clock source select CKSYS */ +#define RCU_CKOUTSRC_IRC8M CFG0_CKOUTSEL(5) /*!< CK_OUT clock source select IRC8M */ +#define RCU_CKOUTSRC_HXTAL CFG0_CKOUTSEL(6) /*!< CK_OUT clock source select HXTAL */ +#define RCU_CKOUTSRC_CKPLL_DIV1 (RCU_CFG0_PLLDV | CFG0_CKOUTSEL(7)) /*!< CK_OUT clock source select CK_PLL */ +#define RCU_CKOUTSRC_CKPLL_DIV2 CFG0_CKOUTSEL(7) /*!< CK_OUT clock source select CK_PLL/2 */ + +/* CK_OUT divider */ +#define CFG0_CKOUTDIV(regval) (BITS(28,30) & ((uint32_t)(regval) << 28)) +#define RCU_CKOUT_DIV1 CFG0_CKOUTDIV(0) /*!< CK_OUT is divided by 1 */ +#define RCU_CKOUT_DIV2 CFG0_CKOUTDIV(1) /*!< CK_OUT is divided by 2 */ +#define RCU_CKOUT_DIV4 CFG0_CKOUTDIV(2) /*!< CK_OUT is divided by 4 */ +#define RCU_CKOUT_DIV8 CFG0_CKOUTDIV(3) /*!< CK_OUT is divided by 8 */ +#define RCU_CKOUT_DIV16 CFG0_CKOUTDIV(4) /*!< CK_OUT is divided by 16 */ +#define RCU_CKOUT_DIV32 CFG0_CKOUTDIV(5) /*!< CK_OUT is divided by 32 */ +#define RCU_CKOUT_DIV64 CFG0_CKOUTDIV(6) /*!< CK_OUT is divided by 64 */ +#define RCU_CKOUT_DIV128 CFG0_CKOUTDIV(7) /*!< CK_OUT is divided by 128 */ + +/* CK_PLL divide by 1 or 2 for CK_OUT */ +#define RCU_PLLDV_CKPLL_DIV2 ((uint32_t)0x00000000U) /*!< CK_PLL divide by 2 for CK_OUT */ +#define RCU_PLLDV_CKPLL RCU_CFG0_PLLDV /*!< CK_PLL divide by 1 for CK_OUT */ + +/* LXTAL drive capability */ +#define BDCTL_LXTALDRI(regval) (BITS(3,4) & ((uint32_t)(regval) << 3)) +#define RCU_LXTAL_LOWDRI BDCTL_LXTALDRI(0) /*!< lower driving capability */ +#define RCU_LXTAL_MED_LOWDRI BDCTL_LXTALDRI(1) /*!< medium low driving capability */ +#define RCU_LXTAL_MED_HIGHDRI BDCTL_LXTALDRI(2) /*!< medium high driving capability */ +#define RCU_LXTAL_HIGHDRI BDCTL_LXTALDRI(3) /*!< higher driving capability */ + +/* RTC clock entry selection */ +#define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) +#define RCU_RTCSRC_NONE BDCTL_RTCSRC(0) /*!< no clock selected */ +#define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1) /*!< LXTAL selected as RTC source clock */ +#define RCU_RTCSRC_IRC40K BDCTL_RTCSRC(2) /*!< IRC40K selected as RTC source clock */ +#define RCU_RTCSRC_HXTAL_DIV32 BDCTL_RTCSRC(3) /*!< HXTAL/32 selected as RTC source clock */ + +/* CK_HXTAL divider previous PLL */ +#define CFG1_PREDV(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) +#define RCU_PLL_PREDV1 CFG1_PREDV(0) /*!< PLL not divided */ +#define RCU_PLL_PREDV2 CFG1_PREDV(1) /*!< PLL divided by 2 */ +#define RCU_PLL_PREDV3 CFG1_PREDV(2) /*!< PLL divided by 3 */ +#define RCU_PLL_PREDV4 CFG1_PREDV(3) /*!< PLL divided by 4 */ +#define RCU_PLL_PREDV5 CFG1_PREDV(4) /*!< PLL divided by 5 */ +#define RCU_PLL_PREDV6 CFG1_PREDV(5) /*!< PLL divided by 6 */ +#define RCU_PLL_PREDV7 CFG1_PREDV(6) /*!< PLL divided by 7 */ +#define RCU_PLL_PREDV8 CFG1_PREDV(7) /*!< PLL divided by 8 */ +#define RCU_PLL_PREDV9 CFG1_PREDV(8) /*!< PLL divided by 9 */ +#define RCU_PLL_PREDV10 CFG1_PREDV(9) /*!< PLL divided by 10 */ +#define RCU_PLL_PREDV11 CFG1_PREDV(10) /*!< PLL divided by 11 */ +#define RCU_PLL_PREDV12 CFG1_PREDV(11) /*!< PLL divided by 12 */ +#define RCU_PLL_PREDV13 CFG1_PREDV(12) /*!< PLL divided by 13 */ +#define RCU_PLL_PREDV14 CFG1_PREDV(13) /*!< PLL divided by 14 */ +#define RCU_PLL_PREDV15 CFG1_PREDV(14) /*!< PLL divided by 15 */ +#define RCU_PLL_PREDV16 CFG1_PREDV(15) /*!< PLL divided by 16 */ + +/* USART0 clock source selection */ +#define CFG2_USART0SEL(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define RCU_USART0SRC_CKAPB2 CFG2_USART0SEL(0) /*!< CK_USART0 select CK_APB2 */ +#define RCU_USART0SRC_CKSYS CFG2_USART0SEL(1) /*!< CK_USART0 select CK_SYS */ +#define RCU_USART0SRC_LXTAL CFG2_USART0SEL(2) /*!< CK_USART0 select LXTAL */ +#define RCU_USART0SRC_IRC8M CFG2_USART0SEL(3) /*!< CK_USART0 select IRC8M */ + +/* CEC clock source selection */ +#define RCU_CECSRC_IRC8M_DIV244 ((uint32_t)0x00000000U) /*!< CK_CEC clock source select IRC8M/244 */ +#define RCU_CECSRC_LXTAL RCU_CFG2_CECSEL /*!< CK_CEC clock source select LXTAL */ + +/* ADC clock source selection */ +#define RCU_ADCSRC_IRC28M ((uint32_t)0x00000000U) /*!< ADC clock source select */ +#define RCU_ADCSRC_AHB_APB2DIV RCU_CFG2_ADCSEL /*!< ADC clock source select */ + +/* IRC28M clock divider for ADC */ +#define RCU_ADC_IRC28M_DIV2 ((uint32_t)0x00000000U) /*!< IRC28M/2 select to ADC clock */ +#define RCU_ADC_IRC28M_DIV1 RCU_CFG2_IRC28MDIV /*!< IRC28M select to ADC clock */ + +/* CK48M clock source selection */ +#define RCU_CK48MSRC_PLL48M ((uint32_t)0x00000000U) /*!< CK48M source clock select PLL48M */ +#define RCU_CK48MSRC_IRC48M RCU_ADDCTL_CK48MSEL /*!< CK48M source clock select IRC48M */ + +/* Deep-sleep mode voltage */ +#define DSV_DSLPVS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(0) /*!< core voltage is 1.0V in deep-sleep mode */ +#define RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(1) /*!< core voltage is 0.9V in deep-sleep mode */ +#define RCU_DEEPSLEEP_V_0_8 DSV_DSLPVS(2) /*!< core voltage is 0.8V in deep-sleep mode */ +#define RCU_DEEPSLEEP_V_0_7 DSV_DSLPVS(3) /*!< core voltage is 0.7V in deep-sleep mode */ + +/* function declarations */ +/* deinitialize the RCU */ +void rcu_deinit(void); +/* enable the peripherals clock */ +void rcu_periph_clock_enable(rcu_periph_enum periph); +/* disable the peripherals clock */ +void rcu_periph_clock_disable(rcu_periph_enum periph); +/* enable the peripherals clock when sleep mode */ +void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph); +/* disable the peripherals clock when sleep mode */ +void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph); +/* reset the peripherals */ +void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset); +/* disable reset the peripheral */ +void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset); +/* reset the BKP */ +void rcu_bkp_reset_enable(void); +/* disable the BKP reset */ +void rcu_bkp_reset_disable(void); + +/* configure the system clock source */ +void rcu_system_clock_source_config(uint32_t ck_sys); +/* get the system clock source */ +uint32_t rcu_system_clock_source_get(void); +/* configure the AHB prescaler selection */ +void rcu_ahb_clock_config(uint32_t ck_ahb); +/* configure the APB1 prescaler selection */ +void rcu_apb1_clock_config(uint32_t ck_apb1); +/* configure the APB2 prescaler selection */ +void rcu_apb2_clock_config(uint32_t ck_apb2); +/* configure the ADC clock source and prescaler selection */ +void rcu_adc_clock_config(rcu_adc_clock_enum ck_adc); +/* configure the USBFS prescaler selection */ +void rcu_usbfs_clock_config(uint32_t ck_usbfs); +/* configure the CK_OUT clock source and divider */ +void rcu_ckout_config(uint32_t ckout_src, uint32_t ckout_div); + +/* configure the PLL clock source preselection */ +void rcu_pll_preselection_config(uint32_t pll_presel); +/* configure the PLL clock source selection and PLL multiply factor */ +void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul); +/* configure the USART clock source selection */ +void rcu_usart_clock_config(uint32_t ck_usart); +/* configure the CEC clock source selection */ +void rcu_cec_clock_config(uint32_t ck_cec); +/* configure the RTC clock source selection */ +void rcu_rtc_clock_config(uint32_t rtc_clock_source); +/* configure the CK48M clock selection */ +void rcu_ck48m_clock_config(uint32_t ck48m_clock_source); +/* configure the HXTAL divider used as input of PLL */ +void rcu_hxtal_prediv_config(uint32_t hxtal_prediv); +/* configure the LXTAL drive capability */ +void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap); + +/* get the clock stabilization and periphral reset flags */ +FlagStatus rcu_flag_get(rcu_flag_enum flag); +/* clear the reset flag */ +void rcu_all_reset_flag_clear(void); +/* get the clock stabilization interrupt and ckm flags */ +FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag); +/* clear the interrupt flags */ +void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear); +/* enable the stabilization interrupt */ +void rcu_interrupt_enable(rcu_int_enum stab_int); +/* disable the stabilization interrupt */ +void rcu_interrupt_disable(rcu_int_enum stab_int); + +/* wait until oscillator stabilization flags is SET */ +ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci); +/* turn on the oscillator */ +void rcu_osci_on(rcu_osci_type_enum osci); +/* turn off the oscillator */ +void rcu_osci_off(rcu_osci_type_enum osci); +/* enable the oscillator bypass mode */ +void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci); +/* disable the oscillator bypass mode */ +void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci); +/* enable the HXTAL clock monitor */ +void rcu_hxtal_clock_monitor_enable(void); +/* disable the HXTAL clock monitor */ +void rcu_hxtal_clock_monitor_disable(void); + +/* set the IRC8M adjust value */ +void rcu_irc8m_adjust_value_set(uint8_t irc8m_adjval); +/* set the IRC28M adjust value */ +void rcu_irc28m_adjust_value_set(uint8_t irc28m_adjval); +/* unlock the voltage key */ +void rcu_voltage_key_unlock(void); +/* set the deep sleep mode voltage */ +void rcu_deepsleep_voltage_set(uint32_t dsvol); + +/* get the system clock, bus and peripheral clock frequency */ +uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock); + +#endif /* GD32F3X0_RCU_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_rtc.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_rtc.h new file mode 100644 index 0000000000..767d90992d --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_rtc.h @@ -0,0 +1,560 @@ +/*! + \file gd32f3x0_rtc.h + \brief definitions for the RTC + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F3X0_RTC_H +#define GD32F3X0_RTC_H + +#include "gd32f3x0.h" + +/* RTC definitions */ +#define RTC RTC_BASE + +/* registers definitions */ +#define RTC_TIME REG32(RTC + 0x00000000U) /*!< RTC time of day register */ +#define RTC_DATE REG32(RTC + 0x00000004U) /*!< RTC date register */ +#define RTC_CTL REG32(RTC + 0x00000008U) /*!< RTC control register */ +#define RTC_STAT REG32(RTC + 0x0000000CU) /*!< RTC status register */ +#define RTC_PSC REG32(RTC + 0x00000010U) /*!< RTC time prescaler register */ +#define RTC_ALRM0TD REG32(RTC + 0x0000001CU) /*!< RTC alarm 0 time and date register */ +#define RTC_WPK REG32(RTC + 0x00000024U) /*!< RTC write protection key register */ +#define RTC_SS REG32(RTC + 0x00000028U) /*!< RTC sub second register */ +#define RTC_SHIFTCTL REG32(RTC + 0x0000002CU) /*!< RTC shift function control register */ +#define RTC_TTS REG32(RTC + 0x00000030U) /*!< RTC time of timestamp register */ +#define RTC_DTS REG32(RTC + 0x00000034U) /*!< RTC date of timestamp register */ +#define RTC_SSTS REG32(RTC + 0x00000038U) /*!< RTC sub second of timestamp register */ +#define RTC_HRFC REG32(RTC + 0x0000003CU) /*!< RTC high resolution frequency compensation registor */ +#define RTC_TAMP REG32(RTC + 0x00000040U) /*!< RTC tamper register */ +#define RTC_ALRM0SS REG32(RTC + 0x00000044U) /*!< RTC alarm 0 sub second register */ +#define RTC_BKP0 REG32(RTC + 0x00000050U) /*!< RTC backup 0 register */ +#define RTC_BKP1 REG32(RTC + 0x00000054U) /*!< RTC backup 1 register */ +#define RTC_BKP2 REG32(RTC + 0x00000058U) /*!< RTC backup 2 register */ +#define RTC_BKP3 REG32(RTC + 0x0000005CU) /*!< RTC backup 3 register */ +#define RTC_BKP4 REG32(RTC + 0x00000060U) /*!< RTC backup 4 register */ + +/* bits definitions */ +/* RTC_TIME */ +#define RTC_TIME_SCU BITS(0,3) /*!< second units in BCD code */ +#define RTC_TIME_SCT BITS(4,6) /*!< second tens in BCD code */ +#define RTC_TIME_MNU BITS(8,11) /*!< minute units in BCD code */ +#define RTC_TIME_MNT BITS(12,14) /*!< minute tens in BCD code */ +#define RTC_TIME_HRU BITS(16,19) /*!< hour units in BCD code */ +#define RTC_TIME_HRT BITS(20,21) /*!< hour tens in BCD code */ +#define RTC_TIME_PM BIT(22) /*!< AM/PM notation */ + +/* RTC_DATE */ +#define RTC_DATE_DAYU BITS(0,3) /*!< date units in BCD code */ +#define RTC_DATE_DAYT BITS(4,5) /*!< date tens in BCD code */ +#define RTC_DATE_MONU BITS(8,11) /*!< month units in BCD code */ +#define RTC_DATE_MONT BIT(12) /*!< month tens in BCD code */ +#define RTC_DATE_DOW BITS(13,15) /*!< day of week units */ +#define RTC_DATE_YRU BITS(16,19) /*!< year units in BCD code */ +#define RTC_DATE_YRT BITS(20,23) /*!< year tens in BCD code */ + +/* RTC_CTL */ +#define RTC_CTL_TSEG BIT(3) /*!< valid event edge of time-stamp */ +#define RTC_CTL_REFEN BIT(4) /*!< reference clock detection function enable */ +#define RTC_CTL_BPSHAD BIT(5) /*!< shadow registers bypass control */ +#define RTC_CTL_CS BIT(6) /*!< display format of clock system */ +#define RTC_CTL_ALRM0EN BIT(8) /*!< alarm function enable */ +#define RTC_CTL_TSEN BIT(11) /*!< time-stamp function enable */ +#define RTC_CTL_ALRM0IE BIT(12) /*!< RTC alarm interrupt enable */ +#define RTC_CTL_TSIE BIT(15) /*!< time-stamp interrupt enable */ +#define RTC_CTL_A1H BIT(16) /*!< add 1 hour(summer time change) */ +#define RTC_CTL_S1H BIT(17) /*!< subtract 1 hour(winter time change) */ +#define RTC_CTL_DSM BIT(18) /*!< daylight saving mark */ +#define RTC_CTL_COS BIT(19) /*!< calibration output selection */ +#define RTC_CTL_OPOL BIT(20) /*!< output polarity */ +#define RTC_CTL_OS BITS(21,22) /*!< output selection */ +#define RTC_CTL_COEN BIT(23) /*!< calibration output enable */ + +/* RTC_STAT */ +#define RTC_STAT_ALRM0WF BIT(0) /*!< alarm configuration can be write flag */ +#define RTC_STAT_SOPF BIT(3) /*!< shift function operation pending flag */ +#define RTC_STAT_YCM BIT(4) /*!< year configuration mark status flag */ +#define RTC_STAT_RSYNF BIT(5) /*!< register synchronization flag */ +#define RTC_STAT_INITF BIT(6) /*!< initialization state flag */ +#define RTC_STAT_INITM BIT(7) /*!< enter initialization mode */ +#define RTC_STAT_ALRM0F BIT(8) /*!< alarm occurs flag */ +#define RTC_STAT_TSF BIT(11) /*!< time-stamp flag */ +#define RTC_STAT_TSOVRF BIT(12) /*!< time-stamp overflow flag */ +#define RTC_STAT_TP0F BIT(13) /*!< RTC tamp 0 detected flag */ +#define RTC_STAT_TP1F BIT(14) /*!< RTC tamp 1 detected flag */ +#define RTC_STAT_SCPF BIT(16) /*!< recalibration pending flag */ + +/* RTC_PSC */ +#define RTC_PSC_FACTOR_S BITS(0,14) /*!< synchronous prescaler factor */ +#define RTC_PSC_FACTOR_A BITS(16,22) /*!< asynchronous prescaler factor */ + +/* RTC_ALRM0TD */ +#define RTC_ALRM0TD_SCU BITS(0,3) /*!< second units in BCD code */ +#define RTC_ALRM0TD_SCT BITS(4,6) /*!< second tens in BCD code */ +#define RTC_ALRM0TD_MSKS BIT(7) /*!< alarm second mask bit */ +#define RTC_ALRM0TD_MNU BITS(8,11) /*!< minutes units in BCD code */ +#define RTC_ALRM0TD_MNT BITS(12,14) /*!< minutes tens in BCD code */ +#define RTC_ALRM0TD_MSKM BIT(15) /*!< alarm minutes mask bit */ +#define RTC_ALRM0TD_HRU BITS(16,19) /*!< hour units in BCD code */ +#define RTC_ALRM0TD_HRT BITS(20,21) /*!< hour units in BCD code */ +#define RTC_ALRM0TD_PM BIT(22) /*!< AM/PM flag */ +#define RTC_ALRM0TD_MSKH BIT(23) /*!< alarm hour mask bit */ +#define RTC_ALRM0TD_DAYU BITS(24,27) /*!< date units or week day in BCD code */ +#define RTC_ALRM0TD_DAYT BITS(28,29) /*!< date tens in BCD code */ +#define RTC_ALRM0TD_DOWS BIT(30) /*!< day of week selection */ +#define RTC_ALRM0TD_MSKD BIT(31) /*!< alarm date mask bit */ + +/* RTC_WPK */ +#define RTC_WPK_WPK BITS(0,7) /*!< key for write protection */ + +/* RTC_SS */ +#define RTC_SS_SSC BITS(0,15) /*!< sub second value */ + +/* RTC_SHIFTCTL */ +#define RTC_SHIFTCTL_SFS BITS(0,14) /*!< subtract a fraction of a second */ +#define RTC_SHIFTCTL_A1S BIT(31) /*!< one second add */ + +/* RTC_TTS */ +#define RTC_TTS_SCU BITS(0,3) /*!< second units in BCD code */ +#define RTC_TTS_SCT BITS(4,6) /*!< second units in BCD code */ +#define RTC_TTS_MNU BITS(8,11) /*!< minute units in BCD code */ +#define RTC_TTS_MNT BITS(12,14) /*!< minute tens in BCD code */ +#define RTC_TTS_HRU BITS(16,19) /*!< hour units in BCD code */ +#define RTC_TTS_HRT BITS(20,21) /*!< hour tens in BCD code */ +#define RTC_TTS_PM BIT(22) /*!< AM/PM notation */ + +/* RTC_DTS */ +#define RTC_DTS_DAYU BITS(0,3) /*!< date units in BCD code */ +#define RTC_DTS_DAYT BITS(4,5) /*!< date tens in BCD code */ +#define RTC_DTS_MONU BITS(8,11) /*!< month units in BCD code */ +#define RTC_DTS_MONT BIT(12) /*!< month tens in BCD code */ +#define RTC_DTS_DOW BITS(13,15) /*!< day of week units */ + +/* RTC_SSTS */ +#define RTC_SSTS_SSC BITS(0,15) /*!< timestamp sub second units */ + +/* RTC_HRFC */ +#define RTC_HRFC_CMSK BITS(0,8) /*!< calibration mask number */ +#define RTC_HRFC_CWND16 BIT(13) /*!< calibration window select 16 seconds */ +#define RTC_HRFC_CWND8 BIT(14) /*!< calibration window select 16 seconds */ +#define RTC_HRFC_FREQI BIT(15) /*!< increase RTC frequency by 488.5ppm */ + +/* RTC_TAMP */ +#define RTC_TAMP_TP0EN BIT(0) /*!< tamper 0 detection enable */ +#define RTC_TAMP_TP0EG BIT(1) /*!< tamper 0 event trigger edge for RTC tamp 0 input */ +#define RTC_TAMP_TPIE BIT(2) /*!< tamper detection interrupt enable */ +#define RTC_TAMP_TP1EN BIT(3) /*!< tamper 1 detection enable */ +#define RTC_TAMP_TP1EG BIT(4) /*!< tamper 1 event trigger edge for RTC tamp 1 input */ +#define RTC_TAMP_TPTS BIT(7) /*!< make tamper function used for timestamp function */ +#define RTC_TAMP_FREQ BITS(8,10) /*!< sample frequency of tamper event detection */ +#define RTC_TAMP_FLT BITS(11,12) /*!< RTC tamp x filter count setting */ +#define RTC_TAMP_PRCH BITS(13,14) /*!< precharge duration time of RTC tamp x */ +#define RTC_TAMP_DISPU BIT(15) /*!< RTC tamp x pull up disable bit */ +#define RTC_TAMP_PC13VAL BIT(18) /*!< alarm output type control/PC13 output value */ +#define RTC_TAMP_PC13MDE BIT(19) /*!< PC13 mode */ +#define RTC_TAMP_PC14VAL BIT(20) /*!< PC14 output value */ +#define RTC_TAMP_PC14MDE BIT(21) /*!< PC14 mode */ +#define RTC_TAMP_PC15VAL BIT(22) /*!< PC15 output value */ +#define RTC_TAMP_PC15MDE BIT(23) /*!< PC15 mode */ + +/* RTC_ALRM0SS */ +#define RTC_ALRM0SS_SSC BITS(0,14) /*!< alarm sub second value */ +#define RTC_ALRM0SS_MASKSSC BITS(24,27) /*!< mask control bit of SS */ + +/* RTC_BKP0 */ +#define RTC_BKP0_DATA BITS(0,31) /*!< backup domain registers */ + +/* RTC_BKP1 */ +#define RTC_BKP1_DATA BITS(0,31) /*!< backup domain registers */ + +/* RTC_BKP2 */ +#define RTC_BKP2_DATA BITS(0,31) /*!< backup domain registers */ + +/* RTC_BKP3 */ +#define RTC_BKP3_DATA BITS(0,31) /*!< backup domain registers */ + +/* RTC_BKP4 */ +#define RTC_BKP4_DATA BITS(0,31) /*!< backup domain registers */ + +/* constants definitions */ +/* structure for initialization of the RTC */ +typedef struct +{ + uint8_t rtc_year; /*!< RTC year value: 0x0 - 0x99(BCD format) */ + uint8_t rtc_month; /*!< RTC month value */ + uint8_t rtc_date; /*!< RTC date value: 0x1 - 0x31(BCD format) */ + uint8_t rtc_day_of_week; /*!< RTC weekday value */ + uint8_t rtc_hour; /*!< RTC hour value */ + uint8_t rtc_minute; /*!< RTC minute value: 0x0 - 0x59(BCD format) */ + uint8_t rtc_second; /*!< RTC second value: 0x0 - 0x59(BCD format) */ + uint16_t rtc_factor_asyn; /*!< RTC asynchronous prescaler value: 0x0 - 0x7F */ + uint16_t rtc_factor_syn; /*!< RTC synchronous prescaler value: 0x0 - 0x7FFF */ + uint32_t rtc_am_pm; /*!< RTC AM/PM value */ + uint32_t rtc_display_format; /*!< RTC time notation */ +}rtc_parameter_struct; + +/* structure for RTC alarm configuration */ +typedef struct +{ + uint32_t rtc_alarm_mask; /*!< RTC alarm mask */ + uint32_t rtc_weekday_or_date; /*!< specify RTC alarm is on date or weekday */ + uint8_t rtc_alarm_day; /*!< RTC alarm date or weekday value*/ + uint8_t rtc_alarm_hour; /*!< RTC alarm hour value */ + uint8_t rtc_alarm_minute; /*!< RTC alarm minute value: 0x0 - 0x59(BCD format) */ + uint8_t rtc_alarm_second; /*!< RTC alarm second value: 0x0 - 0x59(BCD format) */ + uint32_t rtc_am_pm; /*!< RTC alarm AM/PM value */ +}rtc_alarm_struct; + +/* structure for RTC time-stamp configuration */ +typedef struct +{ + uint8_t rtc_timestamp_month; /*!< RTC time-stamp month value */ + uint8_t rtc_timestamp_date; /*!< RTC time-stamp date value: 0x1 - 0x31(BCD format) */ + uint8_t rtc_timestamp_day; /*!< RTC time-stamp weekday value */ + uint8_t rtc_timestamp_hour; /*!< RTC time-stamp hour value */ + uint8_t rtc_timestamp_minute; /*!< RTC time-stamp minute value: 0x0 - 0x59(BCD format) */ + uint8_t rtc_timestamp_second; /*!< RTC time-stamp second value: 0x0 - 0x59(BCD format) */ + uint32_t rtc_am_pm; /*!< RTC time-stamp AM/PM value */ +}rtc_timestamp_struct; + +/* structure for RTC tamper configuration */ +typedef struct +{ + uint32_t rtc_tamper_source; /*!< RTC tamper source */ + uint32_t rtc_tamper_trigger; /*!< RTC tamper trigger */ + uint32_t rtc_tamper_filter; /*!< RTC tamper consecutive samples needed during a voltage level detection */ + uint32_t rtc_tamper_sample_frequency; /*!< RTC tamper sampling frequency during a voltage level detection */ + ControlStatus rtc_tamper_precharge_enable; /*!< RTC tamper precharge feature during a voltage level detection */ + uint32_t rtc_tamper_precharge_time; /*!< RTC tamper precharge duration if precharge feature is enabled */ + ControlStatus rtc_tamper_with_timestamp; /*!< RTC tamper time-stamp feature */ +}rtc_tamper_struct; + +/* time register value */ +#define TIME_SC(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_TIME_SC bit field */ +#define GET_TIME_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_TIME_SC bit field */ + +#define TIME_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_TIME_MN bit field */ +#define GET_TIME_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_TIME_MN bit field */ + +#define TIME_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_TIME_HR bit field */ +#define GET_TIME_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_TIME_HR bit field */ + +#define RTC_AM ((uint32_t)0x00000000U) /*!< AM format */ +#define RTC_PM RTC_TIME_PM /*!< PM format */ + +/* date register value */ +#define DATE_DAY(regval) (BITS(0,5) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_DATE_DAY bit field */ +#define GET_DATE_DAY(regval) GET_BITS((regval),0,5) /*!< get value of RTC_DATE_DAY bit field */ + +#define DATE_MON(regval) (BITS(8,12) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_DATE_MON bit field */ +#define GET_DATE_MON(regval) GET_BITS((regval),8,12) /*!< get value of RTC_DATE_MON bit field */ +#define RTC_JAN ((uint8_t)0x01U) /*!< Janurary */ +#define RTC_FEB ((uint8_t)0x02U) /*!< February */ +#define RTC_MAR ((uint8_t)0x03U) /*!< March */ +#define RTC_APR ((uint8_t)0x04U) /*!< April */ +#define RTC_MAY ((uint8_t)0x05U) /*!< May */ +#define RTC_JUN ((uint8_t)0x06U) /*!< June */ +#define RTC_JUL ((uint8_t)0x07U) /*!< July */ +#define RTC_AUG ((uint8_t)0x08U) /*!< August */ +#define RTC_SEP ((uint8_t)0x09U) /*!< September */ +#define RTC_OCT ((uint8_t)0x10U) /*!< October */ +#define RTC_NOV ((uint8_t)0x11U) /*!< November */ +#define RTC_DEC ((uint8_t)0x12U) /*!< December */ + +#define DATE_DOW(regval) (BITS(13,15) & ((uint32_t)(regval) << 13U)) /*!< write value to RTC_DATE_DOW bit field */ +#define GET_DATE_DOW(regval) GET_BITS((regval),13,15) /*!< get value of RTC_DATE_DOW bit field */ +#define RTC_MONDAY ((uint8_t)0x01U) /*!< Monday */ +#define RTC_TUESDAY ((uint8_t)0x02U) /*!< Tuesday */ +#define RTC_WEDSDAY ((uint8_t)0x03U) /*!< Wednesday */ +#define RTC_THURSDAY ((uint8_t)0x04U) /*!< Thursday */ +#define RTC_FRIDAY ((uint8_t)0x05U) /*!< Friday */ +#define RTC_SATURDAY ((uint8_t)0x06U) /*!< Saturday */ +#define RTC_SUNDAY ((uint8_t)0x07U) /*!< Sunday */ + +#define DATE_YR(regval) (BITS(16,23) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_DATE_YR bit field */ +#define GET_DATE_YR(regval) GET_BITS((regval),16,23) /*!< get value of RTC_DATE_YR bit field */ + +/* ctl register value */ +#define CTL_OS(regval) (BITS(21,22) & ((uint32_t)(regval) << 21U)) /*!< write value to RTC_CTL_OS bit field */ +#define RTC_OS_DISABLE CTL_OS(0) /*!< disable output RTC_ALARM */ +#define RTC_OS_ENABLE CTL_OS(1) /*!< enable alarm flag output */ + +#define RTC_CALIBRATION_512HZ RTC_CTL_COEN /*!< calibration output of 512Hz is enable */ +#define RTC_CALIBRATION_1HZ RTC_CTL_COEN | RTC_CTL_COS /*!< calibration output of 1Hz is enable */ +#define RTC_ALARM_HIGH RTC_CTL_OS_ENABLE /*!< enable alarm flag output with high level */ +#define RTC_ALARM_LOW RTC_CTL_OS_ENABLE | RTC_CTL_OPOL /*!< enable alarm flag output with low level*/ + +#define RTC_24HOUR ((uint32_t)0x00000000U) /*!< 24-hour format */ +#define RTC_12HOUR RTC_CTL_CS /*!< 12-hour format */ + +#define RTC_TIMESTAMP_RISING_EDGE ((uint32_t)0x00000000U) /*!< rising edge is valid event edge for time-stamp event */ +#define RTC_TIMESTAMP_FALLING_EDGE RTC_CTL_TSEG /*!< falling edge is valid event edge for time-stamp event */ + +/* psc register value */ +#define PSC_FACTOR_S(regval) (BITS(0,14) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_PSC_FACTOR_S bit field */ +#define GET_PSC_FACTOR_S(regval) GET_BITS((regval),0,14) /*!< get value of RTC_PSC_FACTOR_S bit field */ + +#define PSC_FACTOR_A(regval) (BITS(16,22) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_PSC_FACTOR_A bit field */ +#define GET_PSC_FACTOR_A(regval) GET_BITS((regval),16,22) /*!< get value of RTC_PSC_FACTOR_A bit field */ + +/* alrm0td register value */ +#define ALRM0TD_SC(regval) (BITS(0,6) & ((uint32_t)(regval)<< 0U)) /*!< write value to RTC_ALRM0TD_SC bit field */ +#define GET_ALRM0TD_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_ALRM0TD_SC bit field */ + +#define ALRM0TD_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_ALRM0TD_MN bit field */ +#define GET_ALRM0TD_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_ALRM0TD_MN bit field */ + +#define ALRM0TD_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_ALRM0TD_HR bit field */ +#define GET_ALRM0TD_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_ALRM0TD_HR bit field */ + +#define ALRM0TD_DAY(regval) (BITS(24,29) & ((uint32_t)(regval) << 24U)) /*!< write value to RTC_ALRM0TD_DAY bit field */ +#define GET_ALRM0TD_DAY(regval) GET_BITS((regval),24,29) /*!< get value of RTC_ALRM0TD_DAY bit field */ + +#define RTC_ALARM_NONE_MASK ((uint32_t)0x00000000U) /*!< alarm none mask */ +#define RTC_ALARM_DATE_MASK RTC_ALRM0TD_MSKD /*!< alarm date mask */ +#define RTC_ALARM_HOUR_MASK RTC_ALRM0TD_MSKH /*!< alarm hour mask */ +#define RTC_ALARM_MINUTE_MASK RTC_ALRM0TD_MSKM /*!< alarm minute mask */ +#define RTC_ALARM_SECOND_MASK RTC_ALRM0TD_MSKS /*!< alarm second mask */ +#define RTC_ALARM_ALL_MASK (RTC_ALRM0TD_MSKD|RTC_ALRM0TD_MSKH|RTC_ALRM0TD_MSKM|RTC_ALRM0TD_MSKS) /*!< alarm all mask */ + +#define RTC_ALARM_DATE_SELECTED ((uint32_t)0x00000000U) /*!< alarm date format selected */ +#define RTC_ALARM_WEEKDAY_SELECTED RTC_ALRM0TD_DOWS /*!< alarm weekday format selected */ + +/* wpk register value */ +#define WPK_WPK(regval) (BITS(0,7) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_WPK_WPK bit field */ + +/* ss register value */ +#define SS_SSC(regval) (BITS(0,15) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_SS_SSC bit field */ + +/* shiftctl register value */ +#define SHIFTCTL_SFS(regval) (BITS(0,14) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_SHIFTCTL_SFS bit field */ + +#define RTC_SHIFT_ADD1S_RESET ((uint32_t)0x00000000U) /*!< not add 1 second */ +#define RTC_SHIFT_ADD1S_SET RTC_SHIFTCTL_A1S /*!< add one second to the clock */ + +/* tts register value */ +#define TTS_SC(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_TTS_SC bit field */ +#define GET_TTS_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_TTS_SC bit field */ + +#define TTS_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_TTS_MN bit field */ +#define GET_TTS_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_TTS_MN bit field */ + +#define TTS_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_TTS_HR bit field */ +#define GET_TTS_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_TTS_HR bit field */ + +/* dts register value */ +#define DTS_DAY(regval) (BITS(0,5) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_DTS_DAY bit field */ +#define GET_DTS_DAY(regval) GET_BITS((regval),0,5) /*!< get value of RTC_DTS_DAY bit field */ + +#define DTS_MON(regval) (BITS(8,12) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_DTS_MON bit field */ +#define GET_DTS_MON(regval) GET_BITS((regval),8,12) /*!< get value of RTC_DTS_MON bit field */ + +#define DTS_DOW(regval) (BITS(13,15) & ((uint32_t)(regval) << 13U)) /*!< write value to RTC_DTS_DOW bit field */ +#define GET_DTS_DOW(regval) GET_BITS((regval),13,15) /*!< get value of RTC_DTS_DOW bit field */ + +/* ssts register value */ +#define SSTS_SSC(regval) (BITS(0,15) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_SSTS_SSC bit field */ + +/* hrfc register value */ +#define HRFC_CMSK(regval) (BITS(0,8) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_HRFC_CMSK bit field */ + +#define RTC_CALIBRATION_WINDOW_32S ((uint32_t)0x00000000U) /*!< 2exp20 RTCCLK cycles, 32s if RTCCLK = 32768 Hz */ +#define RTC_CALIBRATION_WINDOW_16S RTC_HRFC_CWND16 /*!< 2exp19 RTCCLK cycles, 16s if RTCCLK = 32768 Hz */ +#define RTC_CALIBRATION_WINDOW_8S RTC_HRFC_CWND8 /*!< 2exp18 RTCCLK cycles, 8s if RTCCLK = 32768 Hz */ + +#define RTC_CALIBRATION_PLUS_SET RTC_HRFC_FREQI /*!< increase RTC frequency by 488.5ppm */ +#define RTC_CALIBRATION_PLUS_RESET ((uint32_t)0x00000000U) /*!< no effect */ + +/* tamp register value */ +#define TAMP_FREQ(regval) (BITS(8,10) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_TAMP_FREQ bit field */ +#define RTC_FREQ_DIV32768 TAMP_FREQ(0) /*!< sample once every 32768 RTCCLK(1Hz if RTCCLK=32.768KHz) */ +#define RTC_FREQ_DIV16384 TAMP_FREQ(1) /*!< sample once every 16384 RTCCLK(2Hz if RTCCLK=32.768KHz) */ +#define RTC_FREQ_DIV8192 TAMP_FREQ(2) /*!< sample once every 8192 RTCCLK(4Hz if RTCCLK=32.768KHz) */ +#define RTC_FREQ_DIV4096 TAMP_FREQ(3) /*!< sample once every 4096 RTCCLK(8Hz if RTCCLK=32.768KHz) */ +#define RTC_FREQ_DIV2048 TAMP_FREQ(4) /*!< sample once every 2048 RTCCLK(16Hz if RTCCLK=32.768KHz) */ +#define RTC_FREQ_DIV1024 TAMP_FREQ(5) /*!< sample once every 1024 RTCCLK(32Hz if RTCCLK=32.768KHz) */ +#define RTC_FREQ_DIV512 TAMP_FREQ(6) /*!< sample once every 512 RTCCLK(64Hz if RTCCLK=32.768KHz) */ +#define RTC_FREQ_DIV256 TAMP_FREQ(7) /*!< sample once every 256 RTCCLK(128Hz if RTCCLK=32.768KHz) */ + +#define TAMP_FLT(regval) (BITS(11,12) & ((uint32_t)(regval) << 11U)) /*!< write value to RTC_TAMP_FLT bit field */ +#define RTC_FLT_EDGE TAMP_FLT(0) /*!< detecting tamper event using edge mode. precharge duration is disabled automatically */ +#define RTC_FLT_2S TAMP_FLT(1) /*!< detecting tamper event using level mode.2 consecutive valid level samples will make a effective tamper event */ +#define RTC_FLT_4S TAMP_FLT(2) /*!< detecting tamper event using level mode.4 consecutive valid level samples will make an effective tamper event */ +#define RTC_FLT_8S TAMP_FLT(3) /*!< detecting tamper event using level mode.8 consecutive valid level samples will make a effective tamper event */ + +#define TAMP_PRCH(regval) (BITS(13,14) & ((uint32_t)(regval) << 13U)) /*!< write value to RTC_TAMP_PRCH bit field */ +#define RTC_PRCH_1C TAMP_PRCH(0) /*!< 1 RTC clock prechagre time before each sampling */ +#define RTC_PRCH_2C TAMP_PRCH(1) /*!< 2 RTC clock prechagre time before each sampling */ +#define RTC_PRCH_4C TAMP_PRCH(2) /*!< 4 RTC clock prechagre time before each sampling */ +#define RTC_PRCH_8C TAMP_PRCH(3) /*!< 8 RTC clock prechagre time before each sampling */ + +#define RTC_TAMPER0 RTC_TAMP_TP0EN /*!< tamper 0 detection enable */ +#define RTC_TAMPER1 RTC_TAMP_TP1EN /*!< tamper 1 detection enable */ + +#define RTC_TAMPER_TRIGGER_EDGE_RISING ((uint32_t)0x00000000U) /*!< tamper detection is in rising edge mode */ +#define RTC_TAMPER_TRIGGER_EDGE_FALLING RTC_TAMP_TP0EG /*!< tamper detection is in falling edge mode */ +#define RTC_TAMPER_TRIGGER_LEVEL_LOW ((uint32_t)0x00000000U) /*!< tamper detection is in low level mode */ +#define RTC_TAMPER_TRIGGER_LEVEL_HIGH RTC_TAMP_TP0EG /*!< tamper detection is in high level mode */ + +#define RTC_TAMPER_TRIGGER_POS ((uint32_t)0x00000001U) /* shift position of trigger relative to source */ + +#define RTC_ALARM_OUTPUT_OD ((uint32_t)0x00000000U) /*!< RTC alarm output open-drain mode */ +#define RTC_ALARM_OUTPUT_PP RTC_TAMP_PC13VAL /*!< RTC alarm output push-pull mode */ + +/* alrm0ss register value */ +#define ALRM0SS_SSC(regval) (BITS(0,14) & ((uint32_t)(regval)<< 0U)) /*!< write value to RTC_ALRM0SS_SSC bit field */ + +#define ALRM0SS_MASKSSC(regval) (BITS(24,27) & ((uint32_t)(regval) << 24U)) /*!< write value to RTC_ALRM0SS_MASKSSC bit field */ +#define RTC_MASKSSC_0_14 ALRM0SS_MASKSSC(0) /*!< mask alarm subsecond configuration */ +#define RTC_MASKSSC_1_14 ALRM0SS_MASKSSC(1) /*!< mask RTC_ALRM0SS_SSC[14:1], and RTC_ALRM0SS_SSC[0] is to be compared */ +#define RTC_MASKSSC_2_14 ALRM0SS_MASKSSC(2) /*!< mask RTC_ALRM0SS_SSC[14:2], and RTC_ALRM0SS_SSC[1:0] is to be compared */ +#define RTC_MASKSSC_3_14 ALRM0SS_MASKSSC(3) /*!< mask RTC_ALRM0SS_SSC[14:3], and RTC_ALRM0SS_SSC[2:0] is to be compared */ +#define RTC_MASKSSC_4_14 ALRM0SS_MASKSSC(4) /*!< mask RTC_ALRM0SS_SSC[14:4], and RTC_ALRM0SS_SSC[3:0] is to be compared */ +#define RTC_MASKSSC_5_14 ALRM0SS_MASKSSC(5) /*!< mask RTC_ALRM0SS_SSC[14:5], and RTC_ALRM0SS_SSC[4:0] is to be compared */ +#define RTC_MASKSSC_6_14 ALRM0SS_MASKSSC(6) /*!< mask RTC_ALRM0SS_SSC[14:6], and RTC_ALRM0SS_SSC[5:0] is to be compared */ +#define RTC_MASKSSC_7_14 ALRM0SS_MASKSSC(7) /*!< mask RTC_ALRM0SS_SSC[14:7], and RTC_ALRM0SS_SSC[6:0] is to be compared */ +#define RTC_MASKSSC_8_14 ALRM0SS_MASKSSC(8) /*!< mask RTC_ALRM0SS_SSC[14:8], and RTC_ALRM0SS_SSC[7:0] is to be compared */ +#define RTC_MASKSSC_9_14 ALRM0SS_MASKSSC(9) /*!< mask RTC_ALRM0SS_SSC[14:9], and RTC_ALRM0SS_SSC[8:0] is to be compared */ +#define RTC_MASKSSC_10_14 ALRM0SS_MASKSSC(10) /*!< mask RTC_ALRM0SS_SSC[14:10], and RTC_ALRM0SS_SSC[9:0] is to be compared */ +#define RTC_MASKSSC_11_14 ALRM0SS_MASKSSC(11) /*!< mask RTC_ALRM0SS_SSC[14:11], and RTC_ALRM0SS_SSC[10:0] is to be compared */ +#define RTC_MASKSSC_12_14 ALRM0SS_MASKSSC(12) /*!< mask RTC_ALRM0SS_SSC[14:12], and RTC_ALRM0SS_SSC[11:0] is to be compared */ +#define RTC_MASKSSC_13_14 ALRM0SS_MASKSSC(13) /*!< mask RTC_ALRM0SS_SSC[14:13], and RTC_ALRM0SS_SSC[12:0] is to be compared */ +#define RTC_MASKSSC_14 ALRM0SS_MASKSSC(14) /*!< mask RTC_ALRM0SS_SSC[14], and RTC_ALRM0SS_SSC[13:0] is to be compared */ +#define RTC_MASKSSC_NONE ALRM0SS_MASKSSC(15) /*!< mask none, and RTC_ALRM0SS_SSC[14:0] is to be compared */ + +/* RTC interrupt source */ +#define RTC_INT_TIMESTAMP RTC_CTL_TSIE /*!< time-stamp interrupt enable */ +#define RTC_INT_ALARM RTC_CTL_ALRM0IE /*!< RTC alarm interrupt enable */ +#define RTC_INT_TAMP RTC_TAMP_TPIE /*!< tamper detection interrupt enable */ + +/* write protect key */ +#define RTC_UNLOCK_KEY1 ((uint8_t)0xCAU) /*!< RTC unlock key1 */ +#define RTC_UNLOCK_KEY2 ((uint8_t)0x53U) /*!< RTC unlock key2 */ +#define RTC_LOCK_KEY ((uint8_t)0xFFU) /*!< RTC lock key */ + +/* registers reset value */ +#define RTC_REGISTER_RESET ((uint32_t)0x00000000U) /*!< RTC common register reset value */ +#define RTC_DATE_RESET ((uint32_t)0x00002101U) /*!< RTC_DATE register reset value */ +#define RTC_STAT_RESET ((uint32_t)0x00000007U) /*!< RTC_STAT register reset value */ +#define RTC_PSC_RESET ((uint32_t)0x007F00FFU) /*!< RTC_PSC register reset value */ + +/* RTC timeout value */ +#define RTC_INITM_TIMEOUT ((uint32_t)0x00004000U) /*!< initialization state flag timeout */ +#define RTC_RSYNF_TIMEOUT ((uint32_t)0x00008000U) /*!< register synchronization flag timeout */ +#define RTC_HRFC_TIMEOUT ((uint32_t)0x00001000U) /*!< recalibration pending flag timeout */ +#define RTC_SHIFTCTL_TIMEOUT ((uint32_t)0x00001000U) /*!< shift function operation pending flag timeout */ +#define RTC_ALRM0WF_TIMEOUT ((uint32_t)0x00008000U) /*!< alarm configuration can be write flag timeout */ + +/* RTC flag */ +#define RTC_FLAG_RECALIBRATION RTC_STAT_SCPF /*!< recalibration pending flag */ +#define RTC_FLAG_TAMP1 RTC_STAT_TP1F /*!< tamper 1 event flag */ +#define RTC_FLAG_TAMP0 RTC_STAT_TP0F /*!< tamper 0 event flag */ +#define RTC_FLAG_TIMESTAMP_OVERFLOW RTC_STAT_TSOVRF /*!< time-stamp overflow event flag */ +#define RTC_FLAG_TIMESTAMP RTC_STAT_TSF /*!< time-stamp event flag */ +#define RTC_FLAG_ALARM0 RTC_STAT_ALRM0F /*!< alarm event flag */ +#define RTC_FLAG_INIT RTC_STAT_INITF /*!< init mode event flag */ +#define RTC_FLAG_RSYN RTC_STAT_RSYNF /*!< registers synchronized flag */ +#define RTC_FLAG_YCM RTC_STAT_YCM /*!< year parameter configured event flag */ +#define RTC_FLAG_SHIFT RTC_STAT_SOPF /*!< shift operation pending flag */ +#define RTC_FLAG_ALARM0_WRITTEN RTC_STAT_ALRM0WF /*!< alarm written available flag */ + +/* function declarations */ +/* reset most of the RTC registers */ +ErrStatus rtc_deinit(void); +/* initialize RTC registers */ +ErrStatus rtc_init(rtc_parameter_struct* rtc_initpara_struct); +/* enter RTC init mode */ +ErrStatus rtc_init_mode_enter(void); +/* exit RTC init mode */ +void rtc_init_mode_exit(void); +/* wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow registers are updated */ +ErrStatus rtc_register_sync_wait(void); + +/* get current time and date */ +void rtc_current_time_get(rtc_parameter_struct* rtc_initpara_struct); +/* get current subsecond value */ +uint32_t rtc_subsecond_get(void); + +/* configure RTC alarm */ +void rtc_alarm_config(rtc_alarm_struct* rtc_alarm_time); +/* configure subsecond of RTC alarm */ +void rtc_alarm_subsecond_config(uint32_t mask_subsecond, uint32_t subsecond); +/* get RTC alarm */ +void rtc_alarm_get(rtc_alarm_struct* rtc_alarm_time); +/* get RTC alarm subsecond */ +uint32_t rtc_alarm_subsecond_get(void); +/* enable RTC alarm */ +void rtc_alarm_enable(void); +/* disable RTC alarm */ +ErrStatus rtc_alarm_disable(void); + +/* enable RTC time-stamp */ +void rtc_timestamp_enable(uint32_t edge); +/* disable RTC time-stamp */ +void rtc_timestamp_disable(void); +/* get RTC timestamp time and date */ +void rtc_timestamp_get(rtc_timestamp_struct* rtc_timestamp); +/* get RTC time-stamp subsecond */ +uint32_t rtc_timestamp_subsecond_get(void); + +/* enable RTC tamper */ +void rtc_tamper_enable(rtc_tamper_struct* rtc_tamper); +/* disable RTC tamper */ +void rtc_tamper_disable(uint32_t source); + +/* enable specified RTC interrupt */ +void rtc_interrupt_enable(uint32_t interrupt); +/* disble specified RTC interrupt */ +void rtc_interrupt_disable(uint32_t interrupt); +/* check specified flag */ +FlagStatus rtc_flag_get(uint32_t flag); +/* clear specified flag */ +void rtc_flag_clear(uint32_t flag); + +/* configure RTC alternate output source */ +void rtc_alter_output_config(uint32_t source, uint32_t mode); +/* configure RTC calibration register */ +ErrStatus rtc_calibration_config(uint32_t window, uint32_t plus, uint32_t minus); +/* ajust the daylight saving time by adding or substracting one hour from the current time */ +void rtc_hour_adjust(uint32_t operation); +/* ajust RTC second or subsecond value of current time */ +ErrStatus rtc_second_adjust(uint32_t add, uint32_t minus); +/* enable RTC bypass shadow registers function */ +void rtc_bypass_shadow_enable(void); +/* disable RTC bypass shadow registers function */ +void rtc_bypass_shadow_disable(void); +/* enable RTC reference clock detection function */ +ErrStatus rtc_refclock_detection_enable(void); +/* disable RTC reference clock detection function */ +ErrStatus rtc_refclock_detection_disable(void); + +#endif /* GD32F3X0_RTC_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_spi.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_spi.h new file mode 100644 index 0000000000..c24aad66a4 --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_spi.h @@ -0,0 +1,368 @@ +/*! + \file gd32f3x0_spi.h + \brief definitions for the SPI + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F3X0_SPI_H +#define GD32F3X0_SPI_H + +#include "gd32f3x0.h" + +/* SPIx(x=0,1) definitions */ +#define SPI0 (SPI_BASE + 0x0000F800U) +#define SPI1 SPI_BASE + +/* SPI registers definitions */ +#define SPI_CTL0(spix) REG32((spix) + 0x00000000U) /*!< SPI control register 0 */ +#define SPI_CTL1(spix) REG32((spix) + 0x00000004U) /*!< SPI control register 1*/ +#define SPI_STAT(spix) REG32((spix) + 0x00000008U) /*!< SPI status register */ +#define SPI_DATA(spix) REG32((spix) + 0x0000000CU) /*!< SPI data register */ +#define SPI_CRCPOLY(spix) REG32((spix) + 0x00000010U) /*!< SPI CRC polynomial register */ +#define SPI_RCRC(spix) REG32((spix) + 0x00000014U) /*!< SPI receive CRC register */ +#define SPI_TCRC(spix) REG32((spix) + 0x00000018U) /*!< SPI transmit CRC register */ +#define SPI_I2SCTL(spix) REG32((spix) + 0x0000001CU) /*!< SPI I2S control register */ +#define SPI_I2SPSC(spix) REG32((spix) + 0x00000020U) /*!< SPI I2S clock prescaler register */ +#define SPI_QCTL(spix) REG32((spix) + 0x00000080U) /*!< SPI quad mode control register(only SPI1) */ + +/* bits definitions */ +/* SPI_CTL0 */ +#define SPI_CTL0_CKPH BIT(0) /*!< clock phase selection*/ +#define SPI_CTL0_CKPL BIT(1) /*!< clock polarity selection */ +#define SPI_CTL0_MSTMOD BIT(2) /*!< master mode enable */ +#define SPI_CTL0_PSC BITS(3,5) /*!< master clock prescaler selection */ +#define SPI_CTL0_SPIEN BIT(6) /*!< SPI enable*/ +#define SPI_CTL0_LF BIT(7) /*!< LSB first mode */ +#define SPI_CTL0_SWNSS BIT(8) /*!< NSS pin selection in NSS software mode */ +#define SPI_CTL0_SWNSSEN BIT(9) /*!< NSS software mode selection */ +#define SPI_CTL0_RO BIT(10) /*!< receive only */ +#define SPI_CTL0_FF16 BIT(11) /*!< data frame size */ +#define SPI_CTL0_CRCNT BIT(12) /*!< CRC next transfer */ +#define SPI_CTL0_CRCEN BIT(13) /*!< CRC calculation enable */ +#define SPI_CTL0_BDOEN BIT(14) /*!< bidirectional transmit output enable*/ +#define SPI_CTL0_BDEN BIT(15) /*!< bidirectional enable */ + +/* SPI_CTL1 */ +#define SPI_CTL1_DMAREN BIT(0) /*!< receive buffer dma enable */ +#define SPI_CTL1_DMATEN BIT(1) /*!< transmit buffer dma enable */ +#define SPI_CTL1_NSSDRV BIT(2) /*!< drive NSS output */ +#define SPI_CTL1_NSSP BIT(3) /*!< SPI NSS pulse mode enable */ +#define SPI_CTL1_TMOD BIT(4) /*!< SPI TI mode enable */ +#define SPI_CTL1_ERRIE BIT(5) /*!< errors interrupt enable */ +#define SPI_CTL1_RBNEIE BIT(6) /*!< receive buffer not empty interrupt enable */ +#define SPI_CTL1_TBEIE BIT(7) /*!< transmit buffer empty interrupt enable */ + +/* SPI_STAT */ +#define SPI_STAT_RBNE BIT(0) /*!< receive buffer not empty */ +#define SPI_STAT_TBE BIT(1) /*!< transmit buffer empty */ +#define SPI_STAT_I2SCH BIT(2) /*!< I2S channel side */ +#define SPI_STAT_TXURERR BIT(3) /*!< I2S transmission underrun error bit */ +#define SPI_STAT_CRCERR BIT(4) /*!< SPI CRC error bit */ +#define SPI_STAT_CONFERR BIT(5) /*!< SPI configuration error bit */ +#define SPI_STAT_RXORERR BIT(6) /*!< SPI reception overrun error bit */ +#define SPI_STAT_TRANS BIT(7) /*!< transmitting on-going bit */ +#define SPI_STAT_FERR BIT(8) /*!< format error bit */ + +/* SPI_DATA */ +#define SPI_DATA_DATA BITS(0,15) /*!< data transfer register */ + +/* SPI_CRCPOLY */ +#define SPI_CRCPOLY_CRCPOLY BITS(0,15) /*!< CRC polynomial value */ + +/* SPI_RCRC */ +#define SPI_RCRC_RCRC BITS(0,15) /*!< RX CRC value */ + +/* SPI_TCRC */ +#define SPI_TCRC_TCRC BITS(0,15) /*!< TX CRC value */ + +/* SPI_I2SCTL */ +#define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */ +#define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */ +#define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */ +#define SPI_I2SCTL_I2SSTD BITS(4,5) /*!< I2S standard selection */ +#define SPI_I2SCTL_PCMSMOD BIT(7) /*!< PCM frame synchronization mode */ +#define SPI_I2SCTL_I2SOPMOD BITS(8,9) /*!< I2S operation mode */ +#define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */ +#define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */ + +/* SPI_I2SPSC */ +#define SPI_I2SPSC_DIV BITS(0,7) /*!< dividing factor for the prescaler */ +#define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */ +#define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */ + +/* SPI_QCTL(only for SPI1) */ +#define SPI_QCTL_QMOD BIT(0) /*!< quad-SPI mode enable */ +#define SPI_QCTL_QRD BIT(1) /*!< quad-SPI mode read select */ +#define SPI_QCTL_IO23_DRV BIT(2) /*!< drive SPI_IO2 and SPI_IO3 enable */ + +/* constants definitions */ +/* SPI and I2S parameter struct definitions */ +typedef struct +{ + uint32_t device_mode; /*!< SPI master or slave */ + uint32_t trans_mode; /*!< SPI transtype */ + uint32_t frame_size; /*!< SPI frame size */ + uint32_t nss; /*!< SPI NSS control by handware or software */ + uint32_t endian; /*!< SPI big endian or little endian */ + uint32_t clock_polarity_phase; /*!< SPI clock phase and polarity */ + uint32_t prescale; /*!< SPI prescale factor */ +}spi_parameter_struct; + +/* SPI mode definitions */ +#define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master */ +#define SPI_SLAVE ((uint32_t)0x00000000U) /*!< SPI as slave */ + +/* SPI bidirectional transfer direction */ +#define SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN /*!< SPI work in transmit-only mode */ +#define SPI_BIDIRECTIONAL_RECEIVE (~SPI_CTL0_BDOEN) /*!< SPI work in receive-only mode */ + +/* SPI transmit type */ +#define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U) /*!< SPI receive and send data at fullduplex communication */ +#define SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO /*!< SPI only receive data */ +#define SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN /*!< bidirectional receive data */ +#define SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN) /*!< bidirectional transmit data*/ + +/* SPI frame size */ +#define SPI_FRAMESIZE_16BIT SPI_CTL0_FF16 /*!< SPI frame size is 16 bits */ +#define SPI_FRAMESIZE_8BIT ((uint32_t)0x00000000U) /*!< SPI frame size is 8 bits */ + +/* SPI NSS control mode */ +#define SPI_NSS_SOFT SPI_CTL0_SWNSSEN /*!< SPI NSS control by sofrware */ +#define SPI_NSS_HARD ((uint32_t)0x00000000U) /*!< SPI NSS control by hardware */ + +/* SPI transmit way */ +#define SPI_ENDIAN_MSB ((uint32_t)0x00000000U) /*!< SPI transmit way is big endian: transmit MSB first */ +#define SPI_ENDIAN_LSB SPI_CTL0_LF /*!< SPI transmit way is little endian: transmit LSB first */ + +/* SPI clock phase and polarity */ +#define SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U) /*!< SPI clock polarity is low level and phase is first edge */ +#define SPI_CK_PL_HIGH_PH_1EDGE SPI_CTL0_CKPL /*!< SPI clock polarity is high level and phase is first edge */ +#define SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH /*!< SPI clock polarity is low level and phase is second edge */ +#define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL | SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */ + +/* SPI clock prescale factor */ +#define CTL0_PSC(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) +#define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescale factor is 2 */ +#define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescale factor is 4 */ +#define SPI_PSC_8 CTL0_PSC(2) /*!< SPI clock prescale factor is 8 */ +#define SPI_PSC_16 CTL0_PSC(3) /*!< SPI clock prescale factor is 16 */ +#define SPI_PSC_32 CTL0_PSC(4) /*!< SPI clock prescale factor is 32 */ +#define SPI_PSC_64 CTL0_PSC(5) /*!< SPI clock prescale factor is 64 */ +#define SPI_PSC_128 CTL0_PSC(6) /*!< SPI clock prescale factor is 128 */ +#define SPI_PSC_256 CTL0_PSC(7) /*!< SPI clock prescale factor is 256 */ + +#ifdef GD32F350 +/* I2S audio sample rate */ +#define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U) /*!< I2S audio sample rate is 8KHz */ +#define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U) /*!< I2S audio sample rate is 11KHz */ +#define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U) /*!< I2S audio sample rate is 16KHz */ +#define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U) /*!< I2S audio sample rate is 22KHz */ +#define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U) /*!< I2S audio sample rate is 32KHz */ +#define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U) /*!< I2S audio sample rate is 44KHz */ +#define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U) /*!< I2S audio sample rate is 48KHz */ +#define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U) /*!< I2S audio sample rate is 96KHz */ +#define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */ + +/* I2S frame format */ +#define I2SCTL_DTLEN(regval) (BITS(1,2) & ((uint32_t)(regval) << 1)) +#define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */ +#define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */ +#define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */ +#define I2S_FRAMEFORMAT_DT32B_CH32B (I2SCTL_DTLEN(2) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 32 bit and channel length is 32 bit */ + +/* I2S master clock output */ +#define I2S_MCKOUT_DISABLE ((uint32_t)0x00000000U) /*!< I2S master clock output disable */ +#define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN /*!< I2S master clock output enable */ + +/* I2S operation mode */ +#define I2SCTL_I2SOPMOD(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) +#define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */ +#define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */ +#define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */ +#define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */ + +/* I2S standard */ +#define I2SCTL_I2SSTD(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) +#define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0) /*!< I2S phillips standard */ +#define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */ +#define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */ +#define I2S_STD_PCMSHORT I2SCTL_I2SSTD(3) /*!< I2S PCM short standard */ +#define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */ + +/* I2S clock polarity */ +#define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */ +#define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */ +#endif /* GD32F350 */ + +/* SPI DMA constants definitions */ +#define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */ +#define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */ + +/* SPI CRC constants definitions */ +#define SPI_CRC_TX ((uint8_t)0x00U) /*!< SPI transmit CRC value */ +#define SPI_CRC_RX ((uint8_t)0x01U) /*!< SPI receive CRC value */ + +/* SPI/I2S interrupt enable/disable constants definitions */ +#define SPI_I2S_INT_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt */ +#define SPI_I2S_INT_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt */ +#define SPI_I2S_INT_ERR ((uint8_t)0x02U) /*!< error interrupt */ + +/* SPI/I2S interrupt flag constants definitions */ +#define SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt flag */ +#define SPI_I2S_INT_FLAG_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt flag */ +#define SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x02U) /*!< overrun interrupt flag */ +#define SPI_INT_FLAG_CONFERR ((uint8_t)0x03U) /*!< config error interrupt flag */ +#define SPI_INT_FLAG_CRCERR ((uint8_t)0x04U) /*!< CRC error interrupt flag */ +#define I2S_INT_FLAG_TXURERR ((uint8_t)0x05U) /*!< underrun error interrupt flag */ +#define SPI_I2S_INT_FLAG_FERR ((uint8_t)0x06U) /*!< format error interrupt flag */ + +/* SPI flag definitions */ +#define SPI_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ +#define SPI_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ +#define SPI_FLAG_CRCERR SPI_STAT_CRCERR /*!< CRC error flag */ +#define SPI_FLAG_CONFERR SPI_STAT_CONFERR /*!< mode config error flag */ +#define SPI_FLAG_RXORERR SPI_STAT_RXORERR /*!< receive overrun error flag */ +#define SPI_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ +#define SPI_FLAG_FERR SPI_STAT_FERR /*!< format error interrupt flag */ + +#ifdef GD32F350 +/* I2S flag definitions */ +#define I2S_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ +#define I2S_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ +#define I2S_FLAG_CH SPI_STAT_I2SCH /*!< channel side flag */ +#define I2S_FLAG_TXURERR SPI_STAT_TXURERR /*!< underrun error flag */ +#define I2S_FLAG_RXORERR SPI_STAT_RXORERR /*!< overrun error flag */ +#define I2S_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ +#define I2S_FLAG_FERR SPI_STAT_FERR /*!< format error interrupt flag */ +#endif /* GD32F350 */ + +/* function declarations */ +/* SPI/I2S deinitialization and initialization functions */ +/* reset SPI and I2S */ +void spi_i2s_deinit(uint32_t spi_periph); +/* initialize the parameters of SPI struct with the default values */ +void spi_struct_para_init(spi_parameter_struct* spi_struct); +/* initialize SPI parameter */ +void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct); +/* enable SPI */ +void spi_enable(uint32_t spi_periph); +/* disable SPI */ +void spi_disable(uint32_t spi_periph); + +#ifdef GD32F350 +/* initialize I2S parameter */ +void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl); +/* configure I2S prescaler */ +void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout); +/* enable I2S */ +void i2s_enable(uint32_t spi_periph); +/* disable I2S */ +void i2s_disable(uint32_t spi_periph); +#endif /* GD32F350 */ + +/* NSS functions */ +/* enable SPI NSS output */ +void spi_nss_output_enable(uint32_t spi_periph); +/* disable SPI NSS output */ +void spi_nss_output_disable(uint32_t spi_periph); +/* SPI NSS pin high level in software mode */ +void spi_nss_internal_high(uint32_t spi_periph); +/* SPI NSS pin low level in software mode */ +void spi_nss_internal_low(uint32_t spi_periph); + +/* enable SPI DMA */ +void spi_dma_enable(uint32_t spi_periph, uint8_t dma); +/* disable SPI DMA */ +void spi_dma_disable(uint32_t spi_periph, uint8_t dma); + +/* configure SPI/I2S data frame format */ +void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format); +/* SPI transmit data */ +void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data); +/* SPI receive data */ +uint16_t spi_i2s_data_receive(uint32_t spi_periph); +/* configure SPI bidirectional transfer direction */ +void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction); + +/* SPI CRC functions */ +/* set SPI CRC polynomial */ +void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly); +/* get SPI CRC polynomial */ +uint16_t spi_crc_polynomial_get(uint32_t spi_periph); +/* turn on SPI CRC function */ +void spi_crc_on(uint32_t spi_periph); +/* turn off SPI CRC function */ +void spi_crc_off(uint32_t spi_periph); +/* SPI next data is CRC value */ +void spi_crc_next(uint32_t spi_periph); +/* get SPI CRC send value or receive value */ +uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc); + +/* SPI TI mode functions */ +/* enable SPI TI mode */ +void spi_ti_mode_enable(uint32_t spi_periph); +/* disable SPI TI mode */ +void spi_ti_mode_disable(uint32_t spi_periph); + +/* SPI NSS pulse mode functions */ +/* enable SPI NSS pulse mode */ +void spi_nssp_mode_enable(uint32_t spi_periph); +/* disable SPI NSS pulse mode */ +void spi_nssp_mode_disable(uint32_t spi_periph); + +/* quad wire SPI functions */ +/* enable quad wire SPI */ +void qspi_enable(uint32_t spi_periph); +/* disable quad wire SPI */ +void qspi_disable(uint32_t spi_periph); +/* enable quad wire SPI write */ +void qspi_write_enable(uint32_t spi_periph); +/* enable quad wire SPI read */ +void qspi_read_enable(uint32_t spi_periph); +/* enable quad wire SPI_IO2 and SPI_IO3 pin output */ +void qspi_io23_output_enable(uint32_t spi_periph); +/* disable quad wire SPI_IO2 and SPI_IO3 pin output */ +void qspi_io23_output_disable(uint32_t spi_periph); + +/* flag and interrupt functions */ +/* enable SPI and I2S interrupt */ +void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt); +/* disable SPI and I2S interrupt */ +void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt); +/* get SPI and I2S interrupt status */ +FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt); +/* get SPI and I2S flag status */ +FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag); +/* clear SPI CRC error flag status */ +void spi_crc_error_clear(uint32_t spi_periph); + +#endif /* GD32F3X0_SPI_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_syscfg.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_syscfg.h new file mode 100644 index 0000000000..861d0bec8c --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_syscfg.h @@ -0,0 +1,190 @@ +/*! + \file gd32f3x0_syscfg.h + \brief definitions for the SYSCFG + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F3X0_SYSCFG_H +#define GD32F3X0_SYSCFG_H + +#include "gd32f3x0.h" + +/* SYSCFG definitions */ +#define SYSCFG SYSCFG_BASE + +/* registers definitions */ +#define SYSCFG_CFG0 REG32(SYSCFG + 0x00000000U) /*!< system configuration register 0 */ +#define SYSCFG_EXTISS0 REG32(SYSCFG + 0x00000008U) /*!< EXTI sources selection register 0 */ +#define SYSCFG_EXTISS1 REG32(SYSCFG + 0x0000000CU) /*!< EXTI sources selection register 1 */ +#define SYSCFG_EXTISS2 REG32(SYSCFG + 0x00000010U) /*!< EXTI sources selection register 2 */ +#define SYSCFG_EXTISS3 REG32(SYSCFG + 0x00000014U) /*!< EXTI sources selection register 3 */ +#define SYSCFG_CFG2 REG32(SYSCFG + 0x00000018U) /*!< system configuration register 2 */ +#define SYSCFG_CPSCTL REG32(SYSCFG + 0x00000020U) /*!< system I/O compensation control register */ + +/* SYSCFG_CFG0 bits definitions */ +#define SYSCFG_CFG0_BOOT_MODE BITS(0,1) /*!< SYSCFG memory remap config */ +#define SYSCFG_CFG0_ADC_DMA_RMP BIT(8) /*!< ADC DMA remap config */ +#define SYSCFG_CFG0_USART0_TX_DMA_RMP BIT(9) /*!< USART0 Tx DMA remap config */ +#define SYSCFG_CFG0_USART0_RX_DMA_RMP BIT(10) /*!< USART0 Rx DMA remap config */ +#define SYSCFG_CFG0_TIMER15_DMA_RMP BIT(11) /*!< TIMER 15 DMA remap config */ +#define SYSCFG_CFG0_TIMER16_DMA_RMP BIT(12) /*!< TIMER 16 DMA remap config */ +#define SYSCFG_CFG0_PB9_HCCE BIT(19) /*!< PB9 pin high current capability enable */ + +/* SYSCFG_EXTISS0 bits definitions */ +#define SYSCFG_EXTISS0_EXTI0_SS BITS(0,3) /*!< EXTI 0 configuration */ +#define SYSCFG_EXTISS0_EXTI1_SS BITS(4,7) /*!< EXTI 1 configuration */ +#define SYSCFG_EXTISS0_EXTI2_SS BITS(8,11) /*!< EXTI 2 configuration */ +#define SYSCFG_EXTISS0_EXTI3_SS BITS(12,15) /*!< EXTI 3 configuration */ + +/* SYSCFG_EXTISS1 bits definitions */ +#define SYSCFG_EXTISS1_EXTI4_SS BITS(0,3) /*!< EXTI 4 configuration */ +#define SYSCFG_EXTISS1_EXTI5_SS BITS(4,7) /*!< EXTI 5 configuration */ +#define SYSCFG_EXTISS1_EXTI6_SS BITS(8,11) /*!< EXTI 6 configuration */ +#define SYSCFG_EXTISS1_EXTI7_SS BITS(12,15) /*!< EXTI 7 configuration */ + +/* SYSCFG_EXTISS2 bits definitions */ +#define SYSCFG_EXTISS2_EXTI8_SS BITS(0,3) /*!< EXTI 8 configuration */ +#define SYSCFG_EXTISS2_EXTI9_SS BITS(4,7) /*!< EXTI 9 configuration */ +#define SYSCFG_EXTISS2_EXTI10_SS BITS(8,11) /*!< EXTI 10 configuration */ +#define SYSCFG_EXTISS2_EXTI11_SS BITS(12,15) /*!< EXTI 11 configuration */ + +/* SYSCFG_EXTISS3 bits definitions */ +#define SYSCFG_EXTISS3_EXTI12_SS BITS(0,3) /*!< EXTI 12 configuration */ +#define SYSCFG_EXTISS3_EXTI13_SS BITS(4,7) /*!< EXTI 13 configuration */ +#define SYSCFG_EXTISS3_EXTI14_SS BITS(8,11) /*!< EXTI 14 configuration */ +#define SYSCFG_EXTISS3_EXTI15_SS BITS(12,15) /*!< EXTI 15 configuration */ + +/* SYSCFG_CFG2 bits definitions */ +#define SYSCFG_CFG2_LOCKUP_LOCK BIT(0) /*!< enable and lock the LOCKUP (Hardfault) output of Cortex-M4 with break input of TIMER0/14/15/16 */ +#define SYSCFG_CFG2_SRAM_PARITY_ERROR_LOCK BIT(1) /*!< enable and lock the SRAM_PARITY error signal with break input of TIMER0/14/15/16 */ +#define SYSCFG_CFG2_LVD_LOCK BIT(2) /*!< enable and lock the LVD connection with TIMER0 break input and also the LVD_EN and LVDSEL[2:0] bits of the power control interface */ +#define SYSCFG_CFG2_SRAM_PCEF BIT(8) /*!< SRAM parity check error flag */ + +/* SYSCFG_CPSCTL bits definitions */ +#define SYSCFG_CPSCTL_CPS_EN BIT(0) /*!< I/O compensation cell enable */ +#define SYSCFG_CPSCTL_CPS_RDY BIT(8) /*!< I/O compensation cell is ready or not */ + +/* constants definitions */ +/* DMA remap definitions */ +#define SYSCFG_DMA_REMAP_ADC SYSCFG_CFG0_ADC_DMA_RMP /*!< ADC DMA remap */ +#define SYSCFG_DMA_REMAP_USART0TX SYSCFG_CFG0_USART0_TX_DMA_RMP /*!< USART0_TX DMA remap */ +#define SYSCFG_DMA_REMAP_USART0RX SYSCFG_CFG0_USART0_RX_DMA_RMP /*!< USART0_RX DMA remap */ +#define SYSCFG_DMA_REMAP_TIMER15 SYSCFG_CFG0_TIMER15_DMA_RMP /*!< TIMER15 DMA remap */ +#define SYSCFG_DMA_REMAP_TIMER16 SYSCFG_CFG0_TIMER16_DMA_RMP /*!< TIMER16 DMA remap */ + +/* high current definitions */ +#define SYSCFG_HIGH_CURRENT_ENABLE SYSCFG_CFG0_PB9_HCCE /*!< high current enable */ +#define SYSCFG_HIGH_CURRENT_DISABLE (~SYSCFG_CFG0_PB9_HCCE) /*!< high current disable */ + +/* EXTI source select definition */ +#define EXTISS0 ((uint8_t)0x00U) /*!< EXTI source select register 0 */ +#define EXTISS1 ((uint8_t)0x01U) /*!< EXTI source select register 1 */ +#define EXTISS2 ((uint8_t)0x02U) /*!< EXTI source select register 2 */ +#define EXTISS3 ((uint8_t)0x03U) /*!< EXTI source select register 3 */ + +/* EXTI source select mask bits definition */ +#define EXTI_SS_MASK BITS(0,3) /*!< EXTI source select mask */ + +/* EXTI source select jumping step definition */ +#define EXTI_SS_JSTEP ((uint8_t)0x04U) /*!< EXTI source select jumping step */ + +/* EXTI source select moving step definition */ +#define EXTI_SS_MSTEP(pin) (EXTI_SS_JSTEP * ((pin) % EXTI_SS_JSTEP)) /*!< EXTI source select moving step */ + +/* EXTI source port definitions */ +#define EXTI_SOURCE_GPIOA ((uint8_t)0x00U) /*!< EXTI GPIOA configuration */ +#define EXTI_SOURCE_GPIOB ((uint8_t)0x01U) /*!< EXTI GPIOB configuration */ +#define EXTI_SOURCE_GPIOC ((uint8_t)0x02U) /*!< EXTI GPIOC configuration */ +#define EXTI_SOURCE_GPIOD ((uint8_t)0x03U) /*!< EXTI GPIOD configuration */ +#define EXTI_SOURCE_GPIOF ((uint8_t)0x05U) /*!< EXTI GPIOF configuration */ + +/* EXTI source pin definitions */ +#define EXTI_SOURCE_PIN0 ((uint8_t)0x00U) /*!< EXTI GPIO pin0 configuration */ +#define EXTI_SOURCE_PIN1 ((uint8_t)0x01U) /*!< EXTI GPIO pin1 configuration */ +#define EXTI_SOURCE_PIN2 ((uint8_t)0x02U) /*!< EXTI GPIO pin2 configuration */ +#define EXTI_SOURCE_PIN3 ((uint8_t)0x03U) /*!< EXTI GPIO pin3 configuration */ +#define EXTI_SOURCE_PIN4 ((uint8_t)0x04U) /*!< EXTI GPIO pin4 configuration */ +#define EXTI_SOURCE_PIN5 ((uint8_t)0x05U) /*!< EXTI GPIO pin5 configuration */ +#define EXTI_SOURCE_PIN6 ((uint8_t)0x06U) /*!< EXTI GPIO pin6 configuration */ +#define EXTI_SOURCE_PIN7 ((uint8_t)0x07U) /*!< EXTI GPIO pin7 configuration */ +#define EXTI_SOURCE_PIN8 ((uint8_t)0x08U) /*!< EXTI GPIO pin8 configuration */ +#define EXTI_SOURCE_PIN9 ((uint8_t)0x09U) /*!< EXTI GPIO pin9 configuration */ +#define EXTI_SOURCE_PIN10 ((uint8_t)0x0AU) /*!< EXTI GPIO pin10 configuration */ +#define EXTI_SOURCE_PIN11 ((uint8_t)0x0BU) /*!< EXTI GPIO pin11 configuration */ +#define EXTI_SOURCE_PIN12 ((uint8_t)0x0CU) /*!< EXTI GPIO pin12 configuration */ +#define EXTI_SOURCE_PIN13 ((uint8_t)0x0DU) /*!< EXTI GPIO pin13 configuration */ +#define EXTI_SOURCE_PIN14 ((uint8_t)0x0EU) /*!< EXTI GPIO pin14 configuration */ +#define EXTI_SOURCE_PIN15 ((uint8_t)0x0FU) /*!< EXTI GPIO pin15 configuration */ + +/* lock definitions */ +#define SYSCFG_LOCK_LOCKUP SYSCFG_CFG2_LOCKUP_LOCK /*!< LOCKUP output lock */ +#define SYSCFG_LOCK_SRAM_PARITY_ERROR SYSCFG_CFG2_SRAM_PARITY_ERROR_LOCK /*!< SRAM parity error lock */ +#define SYSCFG_LOCK_LVD SYSCFG_CFG2_LVD_LOCK /*!< LVD lock */ + +/* SRAM parity check error flag definitions */ +#define SYSCFG_SRAM_PCEF SYSCFG_CFG2_SRAM_PCEF /*!< SRAM parity check error flag */ + +/* I/O compensation cell enable/disable */ +#define SYSCFG_COMPENSATION(regval) (BIT(0) & ((uint32_t)(regval) << 0)) +#define SYSCFG_COMPENSATION_DISABLE SYSCFG_COMPENSATION(0) /*!< I/O compensation cell is power-down */ +#define SYSCFG_COMPENSATION_ENABLE SYSCFG_COMPENSATION(1) /*!< I/O compensation cell is enabled */ + +/* function declarations */ +/* deinit syscfg module */ +void syscfg_deinit(void); + +/* enable the DMA channels remapping */ +void syscfg_dma_remap_enable(uint32_t syscfg_dma_remap); +/* disable the DMA channels remapping */ +void syscfg_dma_remap_disable(uint32_t syscfg_dma_remap); + +/* enable PB9 high current capability */ +void syscfg_high_current_enable(void); +/* disable PB9 high current capability */ +void syscfg_high_current_disable(void); + +/* configure the GPIO pin as EXTI Line */ +void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin); +/* connect TIMER0/14/15/16 break input to the selected parameter */ +void syscfg_lock_config(uint32_t syscfg_lock); + +/* check if the specified flag in SYSCFG_CFG2 is set or not */ +FlagStatus syscfg_flag_get(uint32_t syscfg_flag); +/* clear the flag in SYSCFG_CFG2 by writing 1 */ +void syscfg_flag_clear(uint32_t syscfg_flag); + +/* configure the I/O compensation cell */ +void syscfg_compensation_config(uint32_t syscfg_compensation); +/* check if the I/O compensation cell ready flag is set or not */ +FlagStatus syscfg_cps_rdy_flag_get(void); + +#endif /* GD32F3X0_SYSCFG_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_timer.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_timer.h new file mode 100644 index 0000000000..b9e3cb9ed6 --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_timer.h @@ -0,0 +1,768 @@ +/*! + \file gd32f3x0_timer.h + \brief definitions for the TIMER + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F3X0_TIMER_H +#define GD32F3X0_TIMER_H + +#include "gd32f3x0.h" + +/* TIMERx(x=0,1,2,5,13..16) definitions */ +#define TIMER0 (TIMER_BASE + 0x00012C00U) +#define TIMER1 (TIMER_BASE + 0x00000000U) +#define TIMER2 (TIMER_BASE + 0x00000400U) +#ifdef GD32F350 +#define TIMER5 (TIMER_BASE + 0x00001000U) +#endif +#define TIMER13 (TIMER_BASE + 0x00002000U) +#define TIMER14 (TIMER_BASE + 0x00014000U) +#define TIMER15 (TIMER_BASE + 0x00014400U) +#define TIMER16 (TIMER_BASE + 0x00014800U) + +/* registers definitions */ +#define TIMER_CTL0(timerx) REG32((timerx) + 0x00000000U) /*!< TIMER control register 0 */ +#define TIMER_CTL1(timerx) REG32((timerx) + 0x00000004U) /*!< TIMER control register 1 */ +#define TIMER_SMCFG(timerx) REG32((timerx) + 0x00000008U) /*!< TIMER slave mode configuration register */ +#define TIMER_DMAINTEN(timerx) REG32((timerx) + 0x0000000CU) /*!< TIMER DMA and interrupt enable register */ +#define TIMER_INTF(timerx) REG32((timerx) + 0x00000010U) /*!< TIMER interrupt flag register */ +#define TIMER_SWEVG(timerx) REG32((timerx) + 0x00000014U) /*!< TIMER software event generation register */ +#define TIMER_CHCTL0(timerx) REG32((timerx) + 0x00000018U) /*!< TIMER channel control register 0 */ +#define TIMER_CHCTL1(timerx) REG32((timerx) + 0x0000001CU) /*!< TIMER channel control register 1 */ +#define TIMER_CHCTL2(timerx) REG32((timerx) + 0x00000020U) /*!< TIMER channel control register 2 */ +#define TIMER_CNT(timerx) REG32((timerx) + 0x00000024U) /*!< TIMER counter register */ +#define TIMER_PSC(timerx) REG32((timerx) + 0x00000028U) /*!< TIMER prescaler register */ +#define TIMER_CAR(timerx) REG32((timerx) + 0x0000002CU) /*!< TIMER counter auto reload register */ +#define TIMER_CREP(timerx) REG32((timerx) + 0x00000030U) /*!< TIMER counter repetition register */ +#define TIMER_CH0CV(timerx) REG32((timerx) + 0x00000034U) /*!< TIMER channel 0 capture/compare value register */ +#define TIMER_CH1CV(timerx) REG32((timerx) + 0x00000038U) /*!< TIMER channel 1 capture/compare value register */ +#define TIMER_CH2CV(timerx) REG32((timerx) + 0x0000003CU) /*!< TIMER channel 2 capture/compare value register */ +#define TIMER_CH3CV(timerx) REG32((timerx) + 0x00000040U) /*!< TIMER channel 3 capture/compare value register */ +#define TIMER_CCHP(timerx) REG32((timerx) + 0x00000044U) /*!< TIMER complementary channel protection register */ +#define TIMER_DMACFG(timerx) REG32((timerx) + 0x00000048U) /*!< TIMER DMA configuration register */ +#define TIMER_DMATB(timerx) REG32((timerx) + 0x0000004CU) /*!< TIMER DMA transfer buffer register */ +#define TIMER_IRMP(timerx) REG32((timerx) + 0x00000050U) /*!< TIMER channel input remap register */ +#define TIMER_CFG(timerx) REG32((timerx) + 0x000000FCU) /*!< TIMER configuration register */ + +/* bits definitions */ +/* TIMER_CTL0 */ +#define TIMER_CTL0_CEN BIT(0) /*!< TIMER counter enable */ +#define TIMER_CTL0_UPDIS BIT(1) /*!< update disable */ +#define TIMER_CTL0_UPS BIT(2) /*!< update source */ +#define TIMER_CTL0_SPM BIT(3) /*!< single pulse mode */ +#define TIMER_CTL0_DIR BIT(4) /*!< timer counter direction */ +#define TIMER_CTL0_CAM BITS(5,6) /*!< center-aligned mode selection */ +#define TIMER_CTL0_ARSE BIT(7) /*!< auto-reload shadow enable */ +#define TIMER_CTL0_CKDIV BITS(8,9) /*!< clock division */ + +/* TIMER_CTL1 */ +#define TIMER_CTL1_CCSE BIT(0) /*!< commutation control shadow enable */ +#define TIMER_CTL1_CCUC BIT(2) /*!< commutation control shadow register update control */ +#define TIMER_CTL1_DMAS BIT(3) /*!< DMA request source selection */ +#define TIMER_CTL1_MMC BITS(4,6) /*!< master mode control */ +#define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection(hall mode selection) */ +#define TIMER_CTL1_ISO0 BIT(8) /*!< idle state of channel 0 output */ +#define TIMER_CTL1_ISO0N BIT(9) /*!< idle state of channel 0 complementary output */ +#define TIMER_CTL1_ISO1 BIT(10) /*!< idle state of channel 1 output */ +#define TIMER_CTL1_ISO1N BIT(11) /*!< idle state of channel 1 complementary output */ +#define TIMER_CTL1_ISO2 BIT(12) /*!< idle state of channel 2 output */ +#define TIMER_CTL1_ISO2N BIT(13) /*!< idle state of channel 2 complementary output */ +#define TIMER_CTL1_ISO3 BIT(14) /*!< idle state of channel 3 output */ + +/* TIMER_SMCFG */ +#define TIMER_SMCFG_SMC BITS(0,2) /*!< slave mode control */ +#define TIMER_SMCFG_OCRC BIT(3) /*!< OCPRE clear source selection */ +#define TIMER_SMCFG_TRGS BITS(4,6) /*!< trigger selection */ +#define TIMER_SMCFG_MSM BIT(7) /*!< master-slave mode */ +#define TIMER_SMCFG_ETFC BITS(8,11) /*!< external trigger filter control */ +#define TIMER_SMCFG_ETPSC BITS(12,13) /*!< external trigger prescaler */ +#define TIMER_SMCFG_SMC1 BIT(14) /*!< part of SMC for enable external clock mode 1 */ +#define TIMER_SMCFG_ETP BIT(15) /*!< external trigger polarity */ + +/* TIMER_DMAINTEN */ +#define TIMER_DMAINTEN_UPIE BIT(0) /*!< update interrupt enable */ +#define TIMER_DMAINTEN_CH0IE BIT(1) /*!< channel 0 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CH1IE BIT(2) /*!< channel 1 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CH2IE BIT(3) /*!< channel 2 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CH3IE BIT(4) /*!< channel 3 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CMTIE BIT(5) /*!< commutation interrupt request enable */ +#define TIMER_DMAINTEN_TRGIE BIT(6) /*!< trigger interrupt enable */ +#define TIMER_DMAINTEN_BRKIE BIT(7) /*!< break interrupt enable */ +#define TIMER_DMAINTEN_UPDEN BIT(8) /*!< update DMA request enable */ +#define TIMER_DMAINTEN_CH0DEN BIT(9) /*!< channel 0 DMA request enable */ +#define TIMER_DMAINTEN_CH1DEN BIT(10) /*!< channel 1 DMA request enable */ +#define TIMER_DMAINTEN_CH2DEN BIT(11) /*!< channel 2 DMA request enable */ +#define TIMER_DMAINTEN_CH3DEN BIT(12) /*!< channel 3 DMA request enable */ +#define TIMER_DMAINTEN_CMTDEN BIT(13) /*!< commutation DMA request enable */ +#define TIMER_DMAINTEN_TRGDEN BIT(14) /*!< trigger DMA request enable */ + +/* TIMER_INTF */ +#define TIMER_INTF_UPIF BIT(0) /*!< update interrupt flag */ +#define TIMER_INTF_CH0IF BIT(1) /*!< channel 0 capture/compare interrupt flag */ +#define TIMER_INTF_CH1IF BIT(2) /*!< channel 1 capture/compare interrupt flag */ +#define TIMER_INTF_CH2IF BIT(3) /*!< channel 2 capture/compare interrupt flag */ +#define TIMER_INTF_CH3IF BIT(4) /*!< channel 3 capture/compare interrupt flag */ +#define TIMER_INTF_CMTIF BIT(5) /*!< channel commutation interrupt flag */ +#define TIMER_INTF_TRGIF BIT(6) /*!< trigger interrupt flag */ +#define TIMER_INTF_BRKIF BIT(7) /*!< break interrupt flag */ +#define TIMER_INTF_CH0OF BIT(9) /*!< channel 0 overcapture flag */ +#define TIMER_INTF_CH1OF BIT(10) /*!< channel 1 overcapture flag */ +#define TIMER_INTF_CH2OF BIT(11) /*!< channel 2 overcapture flag */ +#define TIMER_INTF_CH3OF BIT(12) /*!< channel 3 overcapture flag */ + +/* TIMER_SWEVG */ +#define TIMER_SWEVG_UPG BIT(0) /*!< update event generate */ +#define TIMER_SWEVG_CH0G BIT(1) /*!< channel 0 capture or compare event generation */ +#define TIMER_SWEVG_CH1G BIT(2) /*!< channel 1 capture or compare event generation */ +#define TIMER_SWEVG_CH2G BIT(3) /*!< channel 2 capture or compare event generation */ +#define TIMER_SWEVG_CH3G BIT(4) /*!< channel 3 capture or compare event generation */ +#define TIMER_SWEVG_CMTG BIT(5) /*!< channel commutation event generation */ +#define TIMER_SWEVG_TRGG BIT(6) /*!< trigger event generation */ +#define TIMER_SWEVG_BRKG BIT(7) /*!< break event generation */ + +/* TIMER_CHCTL0 */ +/* output compare mode */ +#define TIMER_CHCTL0_CH0MS BITS(0,1) /*!< channel 0 mode selection */ +#define TIMER_CHCTL0_CH0COMFEN BIT(2) /*!< channel 0 output compare fast enable */ +#define TIMER_CHCTL0_CH0COMSEN BIT(3) /*!< channel 0 output compare shadow enable */ +#define TIMER_CHCTL0_CH0COMCTL BITS(4,6) /*!< channel 0 output compare mode */ +#define TIMER_CHCTL0_CH0COMCEN BIT(7) /*!< channel 0 output compare clear enable */ +#define TIMER_CHCTL0_CH1MS BITS(8,9) /*!< channel 1 mode selection */ +#define TIMER_CHCTL0_CH1COMFEN BIT(10) /*!< channel 1 output compare fast enable */ +#define TIMER_CHCTL0_CH1COMSEN BIT(11) /*!< channel 1 output compare shadow enable */ +#define TIMER_CHCTL0_CH1COMCTL BITS(12,14) /*!< channel 1 output compare mode */ +#define TIMER_CHCTL0_CH1COMCEN BIT(15) /*!< channel 1 output compare clear enable */ +/* input capture mode */ +#define TIMER_CHCTL0_CH0CAPPSC BITS(2,3) /*!< channel 0 input capture prescaler */ +#define TIMER_CHCTL0_CH0CAPFLT BITS(4,7) /*!< channel 0 input capture filter control */ +#define TIMER_CHCTL0_CH1CAPPSC BITS(10,11) /*!< channel 1 input capture prescaler */ +#define TIMER_CHCTL0_CH1CAPFLT BITS(12,15) /*!< channel 1 input capture filter control */ + +/* TIMER_CHCTL1 */ +/* output compare mode */ +#define TIMER_CHCTL1_CH2MS BITS(0,1) /*!< channel 2 mode selection */ +#define TIMER_CHCTL1_CH2COMFEN BIT(2) /*!< channel 2 output compare fast enable */ +#define TIMER_CHCTL1_CH2COMSEN BIT(3) /*!< channel 2 output compare shadow enable */ +#define TIMER_CHCTL1_CH2COMCTL BITS(4,6) /*!< channel 2 output compare mode */ +#define TIMER_CHCTL1_CH2COMCEN BIT(7) /*!< channel 2 output compare clear enable */ +#define TIMER_CHCTL1_CH3MS BITS(8,9) /*!< channel 3 mode selection */ +#define TIMER_CHCTL1_CH3COMFEN BIT(10) /*!< channel 3 output compare fast enable */ +#define TIMER_CHCTL1_CH3COMSEN BIT(11) /*!< channel 3 output compare shadow enable */ +#define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 output compare mode */ +#define TIMER_CHCTL1_CH3COMCEN BIT(15) /*!< channel 3 output compare clear enable */ +/* input capture mode */ +#define TIMER_CHCTL1_CH2CAPPSC BITS(2,3) /*!< channel 2 input capture prescaler */ +#define TIMER_CHCTL1_CH2CAPFLT BITS(4,7) /*!< channel 2 input capture filter control */ +#define TIMER_CHCTL1_CH3CAPPSC BITS(10,11) /*!< channel 3 input capture prescaler */ +#define TIMER_CHCTL1_CH3CAPFLT BITS(12,15) /*!< channel 3 input capture filter control */ + +/* TIMER_CHCTL2 */ +#define TIMER_CHCTL2_CH0EN BIT(0) /*!< channel 0 capture/compare function enable */ +#define TIMER_CHCTL2_CH0P BIT(1) /*!< channel 0 capture/compare function polarity */ +#define TIMER_CHCTL2_CH0NEN BIT(2) /*!< channel 0 complementary output enable */ +#define TIMER_CHCTL2_CH0NP BIT(3) /*!< channel 0 complementary output polarity */ +#define TIMER_CHCTL2_CH1EN BIT(4) /*!< channel 1 capture/compare function enable */ +#define TIMER_CHCTL2_CH1P BIT(5) /*!< channel 1 capture/compare function polarity */ +#define TIMER_CHCTL2_CH1NEN BIT(6) /*!< channel 1 complementary output enable */ +#define TIMER_CHCTL2_CH1NP BIT(7) /*!< channel 1 complementary output polarity */ +#define TIMER_CHCTL2_CH2EN BIT(8) /*!< channel 2 capture/compare function enable */ +#define TIMER_CHCTL2_CH2P BIT(9) /*!< channel 2 capture/compare function polarity */ +#define TIMER_CHCTL2_CH2NEN BIT(10) /*!< channel 2 complementary output enable */ +#define TIMER_CHCTL2_CH2NP BIT(11) /*!< channel 2 complementary output polarity */ +#define TIMER_CHCTL2_CH3EN BIT(12) /*!< channel 3 capture/compare function enable */ +#define TIMER_CHCTL2_CH3P BIT(13) /*!< channel 3 capture/compare function polarity */ +#define TIMER_CHCTL2_CH3NP BIT(15) /*!< channel 3 complementary output polarity */ + +/* TIMER_CNT */ +#define TIMER_CNT_CNT16 BITS(0,15) /*!< 16 bit timer counter */ +#define TIMER_CNT_CNT32 BITS(0,31) /*!< 32 bit(TIMER1) timer counter */ + +/* TIMER_PSC */ +#define TIMER_PSC_PSC BITS(0,15) /*!< prescaler value of the counter clock */ + +/* TIMER_CAR */ +#define TIMER_CAR_CARL16 BITS(0,15) /*!< 16 bit counter auto reload value */ +#define TIMER_CAR_CARL32 BITS(0,31) /*!< 32 bit(TIMER1) counter auto reload value */ + +/* TIMER_CREP */ +#define TIMER_CREP_CREP BITS(0,7) /*!< counter repetition value */ + +/* TIMER_CH0CV */ +#define TIMER_CH0CV_CH0VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 0 */ +#define TIMER_CH0CV_CH0VAL32 BITS(0,31) /*!< 32 bit(TIMER1) capture/compare value of channel 0 */ + +/* TIMER_CH1CV */ +#define TIMER_CH1CV_CH1VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 1 */ +#define TIMER_CH1CV_CH1VAL32 BITS(0,31) /*!< 32 bit(TIMER1) capture/compare value of channel 1 */ + +/* TIMER_CH2CV */ +#define TIMER_CH2CV_CH2VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 2 */ +#define TIMER_CH2CV_CH2VAL32 BITS(0,31) /*!< 32 bit(TIMER1) capture/compare value of channel 2 */ + +/* TIMER_CH3CV */ +#define TIMER_CH3CV_CH3VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 3 */ +#define TIMER_CH3CV_CH3VAL32 BITS(0,31) /*!< 32 bit(TIMER1) capture/compare value of channel 3 */ + +/* TIMER_CCHP */ +#define TIMER_CCHP_DTCFG BITS(0,7) /*!< dead time configure */ +#define TIMER_CCHP_PROT BITS(8,9) /*!< complementary register protect control */ +#define TIMER_CCHP_IOS BIT(10) /*!< idle mode off-state configure */ +#define TIMER_CCHP_ROS BIT(11) /*!< run mode off-state configure */ +#define TIMER_CCHP_BRKEN BIT(12) /*!< break enable */ +#define TIMER_CCHP_BRKP BIT(13) /*!< break polarity */ +#define TIMER_CCHP_OAEN BIT(14) /*!< output automatic enable */ +#define TIMER_CCHP_POEN BIT(15) /*!< primary output enable */ + +/* TIMER_DMACFG */ +#define TIMER_DMACFG_DMATA BITS(0,4) /*!< DMA transfer access start address */ +#define TIMER_DMACFG_DMATC BITS(8,12) /*!< DMA transfer count */ + +/* TIMER_DMATB */ +#define TIMER_DMATB_DMATB BITS(0,15) /*!< DMA transfer buffer address */ + +/* TIMER_IRMP */ +#define TIMER13_IRMP_CI0_RMP BITS(0,1) /*!< TIMER13 channel 0 input remap */ + +/* TIMER_CFG */ +#define TIMER_CFG_OUTSEL BIT(0) /*!< the output value selection */ +#define TIMER_CFG_CHVSEL BIT(1) /*!< write CHxVAL register selection */ + +/* constants definitions */ +/* TIMER init parameter struct definitions*/ +typedef struct +{ + uint16_t prescaler; /*!< prescaler value */ + uint16_t alignedmode; /*!< aligned mode */ + uint16_t counterdirection; /*!< counter direction */ + uint16_t clockdivision; /*!< clock division value */ + uint32_t period; /*!< period value */ + uint8_t repetitioncounter; /*!< the counter repetition value */ +}timer_parameter_struct; + +/* break parameter struct definitions*/ +typedef struct +{ + uint32_t runoffstate; /*!< run mode off-state */ + uint32_t ideloffstate; /*!< idle mode off-state */ + uint16_t deadtime; /*!< dead time */ + uint16_t breakpolarity; /*!< break polarity */ + uint32_t outputautostate; /*!< output automatic enable */ + uint32_t protectmode; /*!< complementary register protect control */ + uint32_t breakstate; /*!< break enable */ +}timer_break_parameter_struct; + +/* channel output parameter struct definitions */ +typedef struct +{ + uint32_t outputstate; /*!< channel output state */ + uint16_t outputnstate; /*!< channel complementary output state */ + uint16_t ocpolarity; /*!< channel output polarity */ + uint16_t ocnpolarity; /*!< channel complementary output polarity */ + uint16_t ocidlestate; /*!< idle state of channel output */ + uint16_t ocnidlestate; /*!< idle state of channel complementary output */ +}timer_oc_parameter_struct; + +/* channel input parameter struct definitions */ +typedef struct +{ + uint16_t icpolarity; /*!< channel input polarity */ + uint16_t icselection; /*!< channel input mode selection */ + uint16_t icprescaler; /*!< channel input capture prescaler */ + uint16_t icfilter; /*!< channel input capture filter control */ +}timer_ic_parameter_struct; + +/* TIMER interrupt enable or disable */ +#define TIMER_INT_UP TIMER_DMAINTEN_UPIE /*!< update interrupt */ +#define TIMER_INT_CH0 TIMER_DMAINTEN_CH0IE /*!< channel 0 interrupt */ +#define TIMER_INT_CH1 TIMER_DMAINTEN_CH1IE /*!< channel 1 interrupt */ +#define TIMER_INT_CH2 TIMER_DMAINTEN_CH2IE /*!< channel 2 interrupt */ +#define TIMER_INT_CH3 TIMER_DMAINTEN_CH3IE /*!< channel 3 interrupt */ +#define TIMER_INT_CMT TIMER_DMAINTEN_CMTIE /*!< channel commutation interrupt flag */ +#define TIMER_INT_TRG TIMER_DMAINTEN_TRGIE /*!< trigger interrupt */ +#define TIMER_INT_BRK TIMER_DMAINTEN_BRKIE /*!< break interrupt */ + +/* TIMER flag */ +#define TIMER_FLAG_UP TIMER_INTF_UPIF /*!< update flag */ +#define TIMER_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 flag */ +#define TIMER_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 flag */ +#define TIMER_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 flag */ +#define TIMER_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 flag */ +#define TIMER_FLAG_CMT TIMER_INTF_CMTIF /*!< channel commutation flag */ +#define TIMER_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger flag */ +#define TIMER_FLAG_BRK TIMER_INTF_BRKIF /*!< break flag */ +#define TIMER_FLAG_CH0O TIMER_INTF_CH0OF /*!< channel 0 overcapture flag */ +#define TIMER_FLAG_CH1O TIMER_INTF_CH1OF /*!< channel 1 overcapture flag */ +#define TIMER_FLAG_CH2O TIMER_INTF_CH2OF /*!< channel 2 overcapture flag */ +#define TIMER_FLAG_CH3O TIMER_INTF_CH3OF /*!< channel 3 overcapture flag */ + +/* TIMER interrupt flag */ +#define TIMER_INT_FLAG_UP TIMER_INTF_UPIF /*!< update interrupt flag */ +#define TIMER_INT_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 interrupt flag */ +#define TIMER_INT_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 interrupt flag */ +#define TIMER_INT_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 interrupt flag */ +#define TIMER_INT_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 interrupt flag */ +#define TIMER_INT_FLAG_CMT TIMER_INTF_CMTIF /*!< channel commutation interrupt flag */ +#define TIMER_INT_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger interrupt flag */ +#define TIMER_INT_FLAG_BRK TIMER_INTF_BRKIF + +/* TIMER DMA source enable */ +#define TIMER_DMA_UPD ((uint16_t)TIMER_DMAINTEN_UPDEN) /*!< update DMA enable */ +#define TIMER_DMA_CH0D ((uint16_t)TIMER_DMAINTEN_CH0DEN) /*!< channel 0 DMA enable */ +#define TIMER_DMA_CH1D ((uint16_t)TIMER_DMAINTEN_CH1DEN) /*!< channel 1 DMA enable */ +#define TIMER_DMA_CH2D ((uint16_t)TIMER_DMAINTEN_CH2DEN) /*!< channel 2 DMA enable */ +#define TIMER_DMA_CH3D ((uint16_t)TIMER_DMAINTEN_CH3DEN) /*!< channel 3 DMA enable */ +#define TIMER_DMA_CMTD ((uint16_t)TIMER_DMAINTEN_CMTDEN) /*!< commutation DMA request enable */ +#define TIMER_DMA_TRGD ((uint16_t)TIMER_DMAINTEN_TRGDEN) /*!< trigger DMA enable */ + +/* channel DMA request source selection */ +#define TIMER_DMAREQUEST_UPDATEEVENT ((uint8_t)0x00U) /*!< DMA request of channel y is sent when update event occurs */ +#define TIMER_DMAREQUEST_CHANNELEVENT ((uint8_t)0x01U) /*!< DMA request of channel y is sent when channel y event occurs */ + +/* DMA access base address */ +#define DMACFG_DMATA(regval) (BITS(0, 4) & ((uint32_t)(regval) << 0U)) +#define TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0) /*!< DMA transfer address is TIMER_CTL0 */ +#define TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1) /*!< DMA transfer address is TIMER_CTL1 */ +#define TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2) /*!< DMA transfer address is TIMER_SMCFG */ +#define TIMER_DMACFG_DMATA_DMAINTEN DMACFG_DMATA(3) /*!< DMA transfer address is TIMER_DMAINTEN */ +#define TIMER_DMACFG_DMATA_INTF DMACFG_DMATA(4) /*!< DMA transfer address is TIMER_INTF */ +#define TIMER_DMACFG_DMATA_SWEVG DMACFG_DMATA(5) /*!< DMA transfer address is TIMER_SWEVG */ +#define TIMER_DMACFG_DMATA_CHCTL0 DMACFG_DMATA(6) /*!< DMA transfer address is TIMER_CHCTL0 */ +#define TIMER_DMACFG_DMATA_CHCTL1 DMACFG_DMATA(7) /*!< DMA transfer address is TIMER_CHCTL1 */ +#define TIMER_DMACFG_DMATA_CHCTL2 DMACFG_DMATA(8) /*!< DMA transfer address is TIMER_CHCTL2 */ +#define TIMER_DMACFG_DMATA_CNT DMACFG_DMATA(9) /*!< DMA transfer address is TIMER_CNT */ +#define TIMER_DMACFG_DMATA_PSC DMACFG_DMATA(10) /*!< DMA transfer address is TIMER_PSC */ +#define TIMER_DMACFG_DMATA_CAR DMACFG_DMATA(11) /*!< DMA transfer address is TIMER_CAR */ +#define TIMER_DMACFG_DMATA_CREP DMACFG_DMATA(12) /*!< DMA transfer address is TIMER_CREP */ +#define TIMER_DMACFG_DMATA_CH0CV DMACFG_DMATA(13) /*!< DMA transfer address is TIMER_CH0CV */ +#define TIMER_DMACFG_DMATA_CH1CV DMACFG_DMATA(14) /*!< DMA transfer address is TIMER_CH1CV */ +#define TIMER_DMACFG_DMATA_CH2CV DMACFG_DMATA(15) /*!< DMA transfer address is TIMER_CH2CV */ +#define TIMER_DMACFG_DMATA_CH3CV DMACFG_DMATA(16) /*!< DMA transfer address is TIMER_CH3CV */ +#define TIMER_DMACFG_DMATA_CCHP DMACFG_DMATA(17) /*!< DMA transfer address is TIMER_CCHP */ +#define TIMER_DMACFG_DMATA_DMACFG DMACFG_DMATA(18) /*!< DMA transfer address is TIMER_DMACFG */ +#define TIMER_DMACFG_DMATA_DMATB DMACFG_DMATA(19) /*!< DMA transfer address is TIMER_DMATB */ + +/* DMA access burst length */ +#define DMACFG_DMATC(regval) (BITS(8, 12) & ((uint32_t)(regval) << 8U)) +#define TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0) /*!< DMA transfer 1 time */ +#define TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1) /*!< DMA transfer 2 times */ +#define TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2) /*!< DMA transfer 3 times */ +#define TIMER_DMACFG_DMATC_4TRANSFER DMACFG_DMATC(3) /*!< DMA transfer 4 times */ +#define TIMER_DMACFG_DMATC_5TRANSFER DMACFG_DMATC(4) /*!< DMA transfer 5 times */ +#define TIMER_DMACFG_DMATC_6TRANSFER DMACFG_DMATC(5) /*!< DMA transfer 6 times */ +#define TIMER_DMACFG_DMATC_7TRANSFER DMACFG_DMATC(6) /*!< DMA transfer 7 times */ +#define TIMER_DMACFG_DMATC_8TRANSFER DMACFG_DMATC(7) /*!< DMA transfer 8 times */ +#define TIMER_DMACFG_DMATC_9TRANSFER DMACFG_DMATC(8) /*!< DMA transfer 9 times */ +#define TIMER_DMACFG_DMATC_10TRANSFER DMACFG_DMATC(9) /*!< DMA transfer 10 times */ +#define TIMER_DMACFG_DMATC_11TRANSFER DMACFG_DMATC(10) /*!< DMA transfer 11 times */ +#define TIMER_DMACFG_DMATC_12TRANSFER DMACFG_DMATC(11) /*!< DMA transfer 12 times */ +#define TIMER_DMACFG_DMATC_13TRANSFER DMACFG_DMATC(12) /*!< DMA transfer 13 times */ +#define TIMER_DMACFG_DMATC_14TRANSFER DMACFG_DMATC(13) /*!< DMA transfer 14 times */ +#define TIMER_DMACFG_DMATC_15TRANSFER DMACFG_DMATC(14) /*!< DMA transfer 15 times */ +#define TIMER_DMACFG_DMATC_16TRANSFER DMACFG_DMATC(15) /*!< DMA transfer 16 times */ +#define TIMER_DMACFG_DMATC_17TRANSFER DMACFG_DMATC(16) /*!< DMA transfer 17 times */ +#define TIMER_DMACFG_DMATC_18TRANSFER DMACFG_DMATC(17) /*!< DMA transfer 18 times */ + +/* TIMER software event generation source */ +#define TIMER_EVENT_SRC_UPG ((uint16_t)0x0001U) /*!< update event generation */ +#define TIMER_EVENT_SRC_CH0G ((uint16_t)0x0002U) /*!< channel 0 capture or compare event generation */ +#define TIMER_EVENT_SRC_CH1G ((uint16_t)0x0004U) /*!< channel 1 capture or compare event generation */ +#define TIMER_EVENT_SRC_CH2G ((uint16_t)0x0008U) /*!< channel 2 capture or compare event generation */ +#define TIMER_EVENT_SRC_CH3G ((uint16_t)0x0010U) /*!< channel 3 capture or compare event generation */ +#define TIMER_EVENT_SRC_CMTG ((uint16_t)0x0020U) /*!< channel commutation event generation */ +#define TIMER_EVENT_SRC_TRGG ((uint16_t)0x0040U) /*!< trigger event generation */ +#define TIMER_EVENT_SRC_BRKG ((uint16_t)0x0080U) /*!< break event generation */ + +/* center-aligned mode selection */ +#define CTL0_CAM(regval) ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U))) +#define TIMER_COUNTER_EDGE CTL0_CAM(0) /*!< edge-aligned mode */ +#define TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1) /*!< center-aligned and counting down assert mode */ +#define TIMER_COUNTER_CENTER_UP CTL0_CAM(2) /*!< center-aligned and counting up assert mode */ +#define TIMER_COUNTER_CENTER_BOTH CTL0_CAM(3) /*!< center-aligned and counting up/down assert mode */ + +/* TIMER prescaler reload mode */ +#define TIMER_PSC_RELOAD_NOW ((uint8_t)0x00U) /*!< the prescaler is loaded right now */ +#define TIMER_PSC_RELOAD_UPDATE ((uint8_t)0x01U) /*!< the prescaler is loaded at the next update event */ + +/* count direction */ +#define TIMER_COUNTER_UP ((uint16_t)0x0000U) /*!< counter up direction */ +#define TIMER_COUNTER_DOWN ((uint16_t)0x0010U) /*!< counter down direction */ + +/* specify division ratio between TIMER clock and dead-time and sampling clock */ +#define CTL0_CKDIV(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) +#define TIMER_CKDIV_DIV1 CTL0_CKDIV(0) /*!< clock division value is 1, fDTS=fTIMER_CK */ +#define TIMER_CKDIV_DIV2 CTL0_CKDIV(1) /*!< clock division value is 2, fDTS= fTIMER_CK/2 */ +#define TIMER_CKDIV_DIV4 CTL0_CKDIV(2) /*!< clock division value is 4, fDTS= fTIMER_CK/4 */ + +/* single pulse mode */ +#define TIMER_SP_MODE_SINGLE ((uint8_t)0x00U) /*!< single pulse mode */ +#define TIMER_SP_MODE_REPETITIVE ((uint8_t)0x01U) /*!< repetitive pulse mode */ + +/* update source */ +#define TIMER_UPDATE_SRC_REGULAR ((uint8_t)0x00U) /*!< update generate only by counter overflow/underflow */ +#define TIMER_UPDATE_SRC_GLOBAL ((uint8_t)0x01U) /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */ + +/* run mode off-state configure */ +#define TIMER_ROS_STATE_ENABLE ((uint32_t)0x00000800U) /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ +#define TIMER_ROS_STATE_DISABLE ((uint32_t)0x00000000U) /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are disabled */ + +/* idle mode off-state configure */ +#define TIMER_IOS_STATE_ENABLE ((uint16_t)0x0400U) /*!< when POEN bit is reset, he channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ +#define TIMER_IOS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is reset, the channel output signals (CHx_O/CHx_ON) are disabled */ + +/* break input polarity */ +#define TIMER_BREAK_POLARITY_LOW ((uint16_t)0x0000U) /*!< break input polarity is low */ +#define TIMER_BREAK_POLARITY_HIGH ((uint16_t)0x2000U) /*!< break input polarity is high */ + +/* output automatic enable */ +#define TIMER_OUTAUTO_ENABLE ((uint16_t)0x4000U) /*!< output automatic enable */ +#define TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000U) /*!< output automatic disable */ + +/* complementary register protect control */ +#define CCHP_PROT(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) +#define TIMER_CCHP_PROT_OFF CCHP_PROT(0) /*!< protect disable */ +#define TIMER_CCHP_PROT_0 CCHP_PROT(1) /*!< PROT mode 0 */ +#define TIMER_CCHP_PROT_1 CCHP_PROT(2) /*!< PROT mode 1 */ +#define TIMER_CCHP_PROT_2 CCHP_PROT(3) /*!< PROT mode 2 */ + +/* break input enable */ +#define TIMER_BREAK_ENABLE ((uint16_t)0x1000U) /*!< break input enable */ +#define TIMER_BREAK_DISABLE ((uint16_t)0x0000U) /*!< break input disable */ + +/* TIMER channel n(n=0,1,2,3) */ +#define TIMER_CH_0 ((uint16_t)0x0000U) /*!< TIMER channel 0(TIMERx(x=0..2,13..16)) */ +#define TIMER_CH_1 ((uint16_t)0x0001U) /*!< TIMER channel 1(TIMERx(x=0..2,14)) */ +#define TIMER_CH_2 ((uint16_t)0x0002U) /*!< TIMER channel 2(TIMERx(x=0..2)) */ +#define TIMER_CH_3 ((uint16_t)0x0003U) /*!< TIMER channel 3(TIMERx(x=0..2)) */ + +/* channel enable state*/ +#define TIMER_CCX_ENABLE ((uint32_t)0x00000001U) /*!< channel enable */ +#define TIMER_CCX_DISABLE ((uint32_t)0x00000000U) /*!< channel disable */ + +/* channel complementary output enable state*/ +#define TIMER_CCXN_ENABLE ((uint16_t)0x0004U) /*!< channel complementary enable */ +#define TIMER_CCXN_DISABLE ((uint16_t)0x0000U) /*!< channel complementary disable */ + +/* channel output polarity */ +#define TIMER_OC_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel output polarity is high */ +#define TIMER_OC_POLARITY_LOW ((uint16_t)0x0002U) /*!< channel output polarity is low */ + +/* channel complementary output polarity */ +#define TIMER_OCN_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel complementary output polarity is high */ +#define TIMER_OCN_POLARITY_LOW ((uint16_t)0x0008U) /*!< channel complementary output polarity is low */ + +/* idle state of channel output */ +#define TIMER_OC_IDLE_STATE_HIGH ((uint16_t)0x0100) /*!< idle state of channel output is high */ +#define TIMER_OC_IDLE_STATE_LOW ((uint16_t)0x0000) /*!< idle state of channel output is low */ + +/* idle state of channel complementary output */ +#define TIMER_OCN_IDLE_STATE_HIGH ((uint16_t)0x0200U) /*!< idle state of channel complementary output is high */ +#define TIMER_OCN_IDLE_STATE_LOW ((uint16_t)0x0000U) /*!< idle state of channel complementary output is low */ + +/* channel output compare mode */ +#define TIMER_OC_MODE_TIMING ((uint16_t)0x0000U) /*!< timing mode */ +#define TIMER_OC_MODE_ACTIVE ((uint16_t)0x0010U) /*!< active mode */ +#define TIMER_OC_MODE_INACTIVE ((uint16_t)0x0020U) /*!< inactive mode */ +#define TIMER_OC_MODE_TOGGLE ((uint16_t)0x0030U) /*!< toggle mode */ +#define TIMER_OC_MODE_LOW ((uint16_t)0x0040U) /*!< force low mode */ +#define TIMER_OC_MODE_HIGH ((uint16_t)0x0050U) /*!< force high mode */ +#define TIMER_OC_MODE_PWM0 ((uint16_t)0x0060U) /*!< PWM0 mode */ +#define TIMER_OC_MODE_PWM1 ((uint16_t)0x0070U) /*!< PWM1 mode*/ + +/* channel output compare shadow enable */ +#define TIMER_OC_SHADOW_ENABLE ((uint16_t)0x0008U) /*!< channel output shadow state enable */ +#define TIMER_OC_SHADOW_DISABLE ((uint16_t)0x0000U) /*!< channel output shadow state disable */ + +/* channel output compare fast enable */ +#define TIMER_OC_FAST_ENABLE ((uint16_t)0x0004) /*!< channel output fast function enable */ +#define TIMER_OC_FAST_DISABLE ((uint16_t)0x0000) /*!< channel output fast function disable */ + +/* channel output compare clear enable */ +#define TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080U) /*!< channel output clear function enable */ +#define TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000U) /*!< channel output clear function disable */ + +/* channel control shadow register update control */ +#define TIMER_UPDATECTL_CCU ((uint8_t)0x00U) /*!< the shadow registers update by when CMTG bit is set */ +#define TIMER_UPDATECTL_CCUTRI ((uint8_t)0x01U) /*!< the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs */ + +/* channel input capture polarity */ +#define TIMER_IC_POLARITY_RISING ((uint16_t)0x0000U) /*!< input capture rising edge */ +#define TIMER_IC_POLARITY_FALLING ((uint16_t)0x0002U) /*!< input capture falling edge */ +#define TIMER_IC_POLARITY_BOTH_EDGE ((uint16_t)0x000AU) /*!< input capture both edge */ + +/* timer input capture selection */ +#define TIMER_IC_SELECTION_DIRECTTI ((uint16_t)0x0001U) /*!< channel y is configured as input and icy is mapped on CIy */ +#define TIMER_IC_SELECTION_INDIRECTTI ((uint16_t)0x0002U) /*!< channel y is configured as input and icy is mapped on opposite input */ +#define TIMER_IC_SELECTION_ITS ((uint16_t)0x0003U) /*!< channel y is configured as input and icy is mapped on ITS */ + +/* channel input capture prescaler */ +#define TIMER_IC_PSC_DIV1 ((uint16_t)0x0000U) /*!< no prescaler */ +#define TIMER_IC_PSC_DIV2 ((uint16_t)0x0004U) /*!< divided by 2 */ +#define TIMER_IC_PSC_DIV4 ((uint16_t)0x0008U) /*!< divided by 4*/ +#define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU) /*!< divided by 8 */ + +/* trigger selection */ +#define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) +#define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */ +#define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */ +#define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */ +#define TIMER_SMCFG_TRGSEL_ITI3 SMCFG_TRGSEL(3) /*!< internal trigger 3 */ +#define TIMER_SMCFG_TRGSEL_CI0F_ED SMCFG_TRGSEL(4) /*!< TI0 Edge Detector */ +#define TIMER_SMCFG_TRGSEL_CI0FE0 SMCFG_TRGSEL(5) /*!< filtered TIMER input 0 */ +#define TIMER_SMCFG_TRGSEL_CI1FE1 SMCFG_TRGSEL(6) /*!< filtered TIMER input 1 */ +#define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7) /*!< external trigger */ + +/* master mode control */ +#define CTL1_MMC(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) +#define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0) /*!< the UPG bit as trigger output */ +#define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1) /*!< the counter enable signal TIMER_CTL0_CEN as trigger output */ +#define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2) /*!< update event as trigger output */ +#define TIMER_TRI_OUT_SRC_CH0 CTL1_MMC(3) /*!< a capture or a compare match occurred in channal0 as trigger output TRGO */ +#define TIMER_TRI_OUT_SRC_O0CPRE CTL1_MMC(4) /*!< O0CPRE as trigger output */ +#define TIMER_TRI_OUT_SRC_O1CPRE CTL1_MMC(5) /*!< O1CPRE as trigger output */ +#define TIMER_TRI_OUT_SRC_O2CPRE CTL1_MMC(6) /*!< O2CPRE as trigger output */ +#define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7) /*!< O3CPRE as trigger output */ + +/* slave mode control */ +#define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U)) +#define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */ +#define TIMER_ENCODER_MODE0 SMCFG_SMC(1) /*!< encoder mode 0 */ +#define TIMER_ENCODER_MODE1 SMCFG_SMC(2) /*!< encoder mode 1 */ +#define TIMER_ENCODER_MODE2 SMCFG_SMC(3) /*!< encoder mode 2 */ +#define TIMER_SLAVE_MODE_RESTART SMCFG_SMC(4) /*!< restart mode */ +#define TIMER_SLAVE_MODE_PAUSE SMCFG_SMC(5) /*!< pause mode */ +#define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6) /*!< event mode */ +#define TIMER_SLAVE_MODE_EXTERNAL0 SMCFG_SMC(7) /*!< external clock mode 0 */ + +/* OCPRE clear source selection */ +#define TIMER_OCPRE_CLEAR_SOURCE_CLR ((uint8_t)0x00U) /*!< OCPRE_CLR_INT is connected to the OCPRE_CLR input */ +#define TIMER_OCPRE_CLEAR_SOURCE_ETIF ((uint8_t)0x01U) /*!< OCPRE_CLR_INT is connected to ETIF */ + +/* master slave mode selection */ +#define TIMER_MASTER_SLAVE_MODE_ENABLE ((uint8_t)0x00U) /*!< master slave mode enable */ +#define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint8_t)0x01U) /*!< master slave mode disable */ + +/* external trigger prescaler */ +#define SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U)) +#define TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0) /*!< no divided */ +#define TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1) /*!< divided by 2 */ +#define TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2) /*!< divided by 4 */ +#define TIMER_EXT_TRI_PSC_DIV8 SMCFG_ETPSC(3) /*!< divided by 8 */ + +/* external trigger polarity */ +#define TIMER_ETP_FALLING TIMER_SMCFG_ETP /*!< active low or falling edge active */ +#define TIMER_ETP_RISING ((uint32_t)0x00000000U) /*!< active high or rising edge active */ + +/* channel 0 trigger input selection */ +#define TIMER_HALLINTERFACE_ENABLE ((uint8_t)0x00U) /*!< TIMER hall sensor mode enable */ +#define TIMER_HALLINTERFACE_DISABLE ((uint8_t)0x01U) /*!< TIMER hall sensor mode disable */ + +/* timerx(x=0,1,2,13,14,15,16) write CHxVAL register selection */ +#define TIMER_CHVSEL_ENABLE ((uint16_t)0x0002U) /*!< write CHxVAL register selection enable */ +#define TIMER_CHVSEL_DISABLE ((uint16_t)0x0000U) /*!< write CHxVAL register selection disable */ + +/* the output value selection */ +#define TIMER_OUTSEL_DISABLE ((uint16_t)0x0000U) /*!< output value selection disable */ +#define TIMER_OUTSEL_ENABLE ((uint16_t)0x0001U) /*!< output value selection enable */ + +/* timer13 channel 0 input remap */ +#define TIMER13_IRMP(regval) (BITS(0, 1) & ((uint32_t)(regval) << 0U)) +#define TIMER13_CI0_RMP_GPIO TIMER13_IRMP(0) /*!< timer13 channel 0 input is connected to GPIO(TIMER13_CH0) */ +#define TIMER13_CI0_RMP_RTCCLK TIMER13_IRMP(1) /*!< timer13 channel 0 input is connected to the RTCCLK */ +#define TIMER13_CI0_RMP_HXTAL_DIV32 TIMER13_IRMP(2) /*!< timer13 channel 0 input is connected to HXTAL/32 clock */ +#define TIMER13_CI0_RMP_CKOUTSEL TIMER13_IRMP(3) /*!< timer13 channel 0 input is connected to CKOUTSEL */ + +/* function declarations */ +/* TIMER timebase*/ +/* deinit a TIMER */ +void timer_deinit(uint32_t timer_periph); +/* initialize TIMER init parameter struct */ +void timer_struct_para_init(timer_parameter_struct* initpara); +/* initialize TIMER counter */ +void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara); +/* enable a TIMER */ +void timer_enable(uint32_t timer_periph); +/* disable a TIMER */ +void timer_disable(uint32_t timer_periph); +/* enable the auto reload shadow function */ +void timer_auto_reload_shadow_enable(uint32_t timer_periph); +/* disable the auto reload shadow function */ +void timer_auto_reload_shadow_disable(uint32_t timer_periph); +/* enable the update event */ +void timer_update_event_enable(uint32_t timer_periph); +/* disable the update event */ +void timer_update_event_disable(uint32_t timer_periph); +/* set TIMER counter alignment mode */ +void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned); +/* set TIMER counter up direction */ +void timer_counter_up_direction(uint32_t timer_periph); +/* set TIMER counter down direction */ +void timer_counter_down_direction(uint32_t timer_periph); +/* configure TIMER prescaler */ +void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload); +/* configure TIMER repetition register value */ +void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition); +/* configure TIMER autoreload register value */ +void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload); +/* configure TIMER counter register value */ +void timer_counter_value_config(uint32_t timer_periph , uint32_t counter); +/* read TIMER counter value */ +uint32_t timer_counter_read(uint32_t timer_periph); +/* read TIMER prescaler value */ +uint16_t timer_prescaler_read(uint32_t timer_periph); +/* configure TIMER single pulse mode */ +void timer_single_pulse_mode_config(uint32_t timer_periph, uint8_t spmode); +/* configure TIMER update source */ +void timer_update_source_config(uint32_t timer_periph, uint8_t update); +/* OCPRE clear source selection */ +void timer_ocpre_clear_source_config(uint32_t timer_periph, uint8_t ocpreclear); + +/* TIMER interrupt and flag*/ +/* enable the TIMER interrupt */ +void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt); +/* disable the TIMER interrupt */ +void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt); +/* get TIMER interrupt flag */ +FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt); +/* clear TIMER interrupt flag */ +void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt); +/* get TIMER flags */ +FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag); +/* clear TIMER flags */ +void timer_flag_clear(uint32_t timer_periph, uint32_t flag); + +/* TIMER DMA and event*/ +/* enable the TIMER DMA */ +void timer_dma_enable(uint32_t timer_periph, uint16_t dma); +/* disable the TIMER DMA */ +void timer_dma_disable(uint32_t timer_periph, uint16_t dma); +/* channel DMA request source selection */ +void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request); +/* configure the TIMER DMA transfer */ +void timer_dma_transfer_config(uint32_t timer_periph,uint32_t dma_baseaddr, uint32_t dma_lenth); +/* software generate events */ +void timer_event_software_generate(uint32_t timer_periph, uint16_t event); + +/* TIMER channel complementary protection */ +/* initialize TIMER break parameter struct */ +void timer_break_struct_para_init(timer_break_parameter_struct* breakpara); +/* configure TIMER break function */ +void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara); +/* enable TIMER break function */ +void timer_break_enable(uint32_t timer_periph); +/* disable TIMER break function */ +void timer_break_disable(uint32_t timer_periph); +/* enable TIMER output automatic function */ +void timer_automatic_output_enable(uint32_t timer_periph); +/* disable TIMER output automatic function */ +void timer_automatic_output_disable(uint32_t timer_periph); +/* enable or disable TIMER primary output function */ +void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue); +/* enable or disable channel capture/compare control shadow register */ +void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue); +/* configure TIMER channel control shadow register update control */ +void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl); + +/* TIMER channel output */ +/* initialize TIMER channel output parameter struct */ +void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara); +/* configure TIMER channel output function */ +void timer_channel_output_config(uint32_t timer_periph,uint16_t channel, timer_oc_parameter_struct* ocpara); +/* configure TIMER channel output compare mode */ +void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel,uint16_t ocmode); +/* configure TIMER channel output pulse value */ +void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse); +/* configure TIMER channel output shadow function */ +void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow); +/* configure TIMER channel output fast function */ +void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast); +/* configure TIMER channel output clear function */ +void timer_channel_output_clear_config(uint32_t timer_periph,uint16_t channel,uint16_t occlear); +/* configure TIMER channel output polarity */ +void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity); +/* configure TIMER channel complementary output polarity */ +void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity); +/* configure TIMER channel enable state */ +void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state); +/* configure TIMER channel complementary output enable state */ +void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate); + +/* TIMER channel input */ +/* initialize TIMER channel input parameter struct */ +void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara); +/* configure TIMER input capture parameter */ +void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara); +/* configure TIMER channel input capture prescaler value */ +void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler); +/* read TIMER channel capture compare register value */ +uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel); +/* configure TIMER input pwm capture function */ +void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm); +/* configure TIMER hall sensor mode */ +void timer_hall_mode_config(uint32_t timer_periph, uint8_t hallmode); + +/* TIMER master and slave */ +/* select TIMER input trigger source */ +void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger); +/* select TIMER master mode output trigger source */ +void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger); +/* select TIMER slave mode */ +void timer_slave_mode_select(uint32_t timer_periph,uint32_t slavemode); +/* configure TIMER master slave mode */ +void timer_master_slave_mode_config(uint32_t timer_periph, uint8_t masterslave); +/* configure TIMER external trigger input */ +void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); +/* configure TIMER quadrature decoder mode */ +void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity); +/* configure TIMER internal clock mode */ +void timer_internal_clock_config(uint32_t timer_periph); +/* configure TIMER the internal trigger as external clock input */ +void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger); +/* configure TIMER the external trigger as external clock input */ +void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity,uint32_t extfilter); +/* configure TIMER the external clock mode 0 */ +void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); +/* configure TIMER the external clock mode 1 */ +void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); +/* disable TIMER the external clock mode 1 */ +void timer_external_clock_mode1_disable(uint32_t timer_periph); +/* configure TIMER channel remap function */ +void timer_channel_remap_config(uint32_t timer_periph,uint32_t remap); + +/* TIMER configure */ +/* configure TIMER write CHxVAL register selection */ +void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel); +/* configure TIMER output value selection */ +void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel); + +#endif /* GD32F3X0_TIMER_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_tsi.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_tsi.h new file mode 100644 index 0000000000..ec03a4bc8a --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_tsi.h @@ -0,0 +1,396 @@ +/*! + \file gd32f3x0_tsi.h + \brief definitions for the TSI + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F3X0_TSI_H +#define GD32F3X0_TSI_H + +#include "gd32f3x0.h" + +/* TSI definitions */ +#define TSI TSI_BASE /*!< TSI base address */ + +/* registers definitions */ +#define TSI_CTL0 REG32(TSI + 0x00000000U)/*!< TSI control register0 */ +#define TSI_INTEN REG32(TSI + 0x00000004U)/*!< TSI interrupt enable register */ +#define TSI_INTC REG32(TSI + 0x00000008U)/*!< TSI interrupt flag clear register */ +#define TSI_INTF REG32(TSI + 0x0000000CU)/*!< TSI interrupt flag register */ +#define TSI_PHM REG32(TSI + 0x00000010U)/*!< TSI pin hysteresis mode register */ +#define TSI_ASW REG32(TSI + 0x00000018U)/*!< TSI analog switch register */ +#define TSI_SAMPCFG REG32(TSI + 0x00000020U)/*!< TSI sample configuration register */ +#define TSI_CHCFG REG32(TSI + 0x00000028U)/*!< TSI channel configuration register */ +#define TSI_GCTL REG32(TSI + 0x00000030U)/*!< TSI group control register */ +#define TSI_G0CYCN REG32(TSI + 0x00000034U)/*!< TSI group 0 cycle number register */ +#define TSI_G1CYCN REG32(TSI + 0x00000038U)/*!< TSI group 1 cycle number register */ +#define TSI_G2CYCN REG32(TSI + 0x0000003CU)/*!< TSI group 2 cycle number register */ +#define TSI_G3CYCN REG32(TSI + 0x00000040U)/*!< TSI group 3 cycle number register */ +#define TSI_G4CYCN REG32(TSI + 0x00000044U)/*!< TSI group 4 cycle number register */ +#define TSI_G5CYCN REG32(TSI + 0x00000048U)/*!< TSI group 5 cycle number register */ +#define TSI_CTL1 REG32(TSI + 0x00000300U)/*!< TSI control registers1 */ + +/* bits definitions */ +/* TSI_CTL0 */ +#define TSI_CTL0_TSIEN BIT(0) /*!< TSI enable */ +#define TSI_CTL0_TSIS BIT(1) /*!< TSI start */ +#define TSI_CTL0_TRGMOD BIT(2) /*!< trigger mode selection */ +#define TSI_CTL0_EGSEL BIT(3) /*!< edge selection */ +#define TSI_CTL0_PINMOD BIT(4) /*!< pin mode */ +#define TSI_CTL0_MCN BITS(5,7) /*!< max cycle number of a sequence */ +#define TSI_CTL0_CTCDIV BITS(12,14) /*!< CTCLK clock division factor */ +#define TSI_CTL0_ECDIV BIT(15) /*!< ECCLK clock division factor */ +#define TSI_CTL0_ECEN BIT(16) /*!< extend charge state enable */ +#define TSI_CTL0_ECDT BITS(17,23) /*!< extend charge State maximum duration time */ +#define TSI_CTL0_CTDT BITS(24,27) /*!< charge transfer state duration time */ +#define TSI_CTL0_CDT BITS(28,31) /*!< charge state duration time */ + +/* TSI_INTEN */ +#define TSI_INTEN_CTCFIE BIT(0) /*!< charge transfer complete flag interrupt enable */ +#define TSI_INTEN_MNERRIE BIT(1) /*!< max cycle number error interrupt enable */ + +/* TSI_INTC */ +#define TSI_INTC_CCTCF BIT(0) /*!< clear charge transfer complete flag */ +#define TSI_INTC_CMNERR BIT(1) /*!< clear max cycle number error */ + +/* TSI_INTF */ +#define TSI_INTF_CTCF BIT(0) /*!< charge transfer complete flag */ +#define TSI_INTF_MNERR BIT(1) /*!< max cycle number error */ + +/* TSI_PHM */ +#define TSI_PHM_G0P0 BIT(0) /*!< pin G0P0 Schmitt trigger hysteresis state */ +#define TSI_PHM_G0P1 BIT(1) /*!< pin G0P1 Schmitt trigger hysteresis state */ +#define TSI_PHM_G0P2 BIT(2) /*!< pin G0P2 Schmitt trigger hysteresis state */ +#define TSI_PHM_G0P3 BIT(3) /*!< pin G0P3 Schmitt trigger hysteresis state */ +#define TSI_PHM_G1P0 BIT(4) /*!< pin G1P0 Schmitt trigger hysteresis state */ +#define TSI_PHM_G1P1 BIT(5) /*!< pin G1P1 Schmitt trigger hysteresis state */ +#define TSI_PHM_G1P2 BIT(6) /*!< pin G1P2 Schmitt trigger hysteresis state */ +#define TSI_PHM_G1P3 BIT(7) /*!< pin G1P3 Schmitt trigger hysteresis state */ +#define TSI_PHM_G2P0 BIT(8) /*!< pin G2P0 Schmitt trigger hysteresis state */ +#define TSI_PHM_G2P1 BIT(9) /*!< pin G2P1 Schmitt trigger hysteresis state */ +#define TSI_PHM_G2P2 BIT(10) /*!< pin G2P2 Schmitt trigger hysteresis state */ +#define TSI_PHM_G2P3 BIT(11) /*!< pin G2P3 Schmitt trigger hysteresis state */ +#define TSI_PHM_G3P0 BIT(12) /*!< pin G3P0 Schmitt trigger hysteresis state */ +#define TSI_PHM_G3P1 BIT(13) /*!< pin G3P1 Schmitt trigger hysteresis state */ +#define TSI_PHM_G3P2 BIT(14) /*!< pin G3P2 Schmitt trigger hysteresis state */ +#define TSI_PHM_G3P3 BIT(15) /*!< pin G3P3 Schmitt trigger hysteresis state */ +#define TSI_PHM_G4P0 BIT(16) /*!< pin G4P0 Schmitt trigger hysteresis state */ +#define TSI_PHM_G4P1 BIT(17) /*!< pin G4P1 Schmitt trigger hysteresis state */ +#define TSI_PHM_G4P2 BIT(18) /*!< pin G4P2 Schmitt trigger hysteresis state */ +#define TSI_PHM_G4P3 BIT(19) /*!< pin G4P3 Schmitt trigger hysteresis state */ +#define TSI_PHM_G5P0 BIT(20) /*!< pin G5P0 Schmitt trigger hysteresis state */ +#define TSI_PHM_G5P1 BIT(21) /*!< pin G5P1 Schmitt trigger hysteresis state */ +#define TSI_PHM_G5P2 BIT(22) /*!< pin G5P2 Schmitt trigger hysteresis state */ +#define TSI_PHM_G5P3 BIT(23) /*!< pin G5P3 Schmitt trigger hysteresis state */ + +/* TSI_ASW */ +#define TSI_ASW_G0P0 BIT(0) /*!< pin G0P0 analog switch state */ +#define TSI_ASW_G0P1 BIT(1) /*!< pin G0P1 analog switch state */ +#define TSI_ASW_G0P2 BIT(2) /*!< pin G0P2 analog switch state */ +#define TSI_ASW_G0P3 BIT(3) /*!< pin G0P3 analog switch state */ +#define TSI_ASW_G1P0 BIT(4) /*!< pin G1P0 analog switch state */ +#define TSI_ASW_G1P1 BIT(5) /*!< pin G1P1 analog switch state */ +#define TSI_ASW_G1P2 BIT(6) /*!< pin G1P2 analog switch state */ +#define TSI_ASW_G1P3 BIT(7) /*!< pin G1P3 analog switch state */ +#define TSI_ASW_G2P0 BIT(8) /*!< pin G2P0 analog switch state */ +#define TSI_ASW_G2P1 BIT(9) /*!< pin G2P1 analog switch state */ +#define TSI_ASW_G2P2 BIT(10) /*!< pin G2P2 analog switch state */ +#define TSI_ASW_G2P3 BIT(11) /*!< pin G2P3 analog switch state */ +#define TSI_ASW_G3P0 BIT(12) /*!< pin G3P0 analog switch state */ +#define TSI_ASW_G3P1 BIT(13) /*!< pin G3P1 analog switch state */ +#define TSI_ASW_G3P2 BIT(14) /*!< pin G3P2 analog switch state */ +#define TSI_ASW_G3P3 BIT(15) /*!< pin G3P3 analog switch state */ +#define TSI_ASW_G4P0 BIT(16) /*!< pin G4P0 analog switch state */ +#define TSI_ASW_G4P1 BIT(17) /*!< pin G4P1 analog switch state */ +#define TSI_ASW_G4P2 BIT(18) /*!< pin G4P2 analog switch state */ +#define TSI_ASW_G4P3 BIT(19) /*!< pin G4P3 analog switch state */ +#define TSI_ASW_G5P0 BIT(20) /*!< pin G5P0 analog switch state */ +#define TSI_ASW_G5P1 BIT(21) /*!< pin G5P1 analog switch state */ +#define TSI_ASW_G5P2 BIT(22) /*!< pin G5P2 analog switch state */ +#define TSI_ASW_G5P3 BIT(23) /*!< pin G5P3 analog switch state */ + +/* TSI_SAMPCFG */ +#define TSI_SAMPCFG_G0P0 BIT(0) /*!< pin G0P0 sample pin mode */ +#define TSI_SAMPCFG_G0P1 BIT(1) /*!< pin G0P1 sample pin mode */ +#define TSI_SAMPCFG_G0P2 BIT(2) /*!< pin G0P2 sample pin mode */ +#define TSI_SAMPCFG_G0P3 BIT(3) /*!< pin G0P3 sample pin mode */ +#define TSI_SAMPCFG_G1P0 BIT(4) /*!< pin G1P0 sample pin mode */ +#define TSI_SAMPCFG_G1P1 BIT(5) /*!< pin G1P1 sample pin mode */ +#define TSI_SAMPCFG_G1P2 BIT(6) /*!< pin G1P2 sample pin mode */ +#define TSI_SAMPCFG_G1P3 BIT(7) /*!< pin G1P3 sample pin mode */ +#define TSI_SAMPCFG_G2P0 BIT(8) /*!< pin G2P0 sample pin mode */ +#define TSI_SAMPCFG_G2P1 BIT(9) /*!< pin G2P1 sample pin mode */ +#define TSI_SAMPCFG_G2P2 BIT(10) /*!< pin G2P2 sample pin mode */ +#define TSI_SAMPCFG_G2P3 BIT(11) /*!< pin G2P3 sample pin mode */ +#define TSI_SAMPCFG_G3P0 BIT(12) /*!< pin G3P0 sample pin mode */ +#define TSI_SAMPCFG_G3P1 BIT(13) /*!< pin G3P1 sample pin mode */ +#define TSI_SAMPCFG_G3P2 BIT(14) /*!< pin G3P2 sample pin mode */ +#define TSI_SAMPCFG_G3P3 BIT(15) /*!< pin G3P3 sample pin mode */ +#define TSI_SAMPCFG_G4P0 BIT(16) /*!< pin G4P0 sample pin mode */ +#define TSI_SAMPCFG_G4P1 BIT(17) /*!< pin G4P1 sample pin mode */ +#define TSI_SAMPCFG_G4P2 BIT(18) /*!< pin G4P2 sample pin mode */ +#define TSI_SAMPCFG_G4P3 BIT(19) /*!< pin G4P3 sample pin mode */ +#define TSI_SAMPCFG_G5P0 BIT(20) /*!< pin G5P0 sample pin mode */ +#define TSI_SAMPCFG_G5P1 BIT(21) /*!< pin G5P1 sample pin mode */ +#define TSI_SAMPCFG_G5P2 BIT(22) /*!< pin G5P2 sample pin mode */ +#define TSI_SAMPCFG_G5P3 BIT(23) /*!< pin G5P3 sample pin mode */ + +/* TSI_CHCFG */ +#define TSI_CHCFG_G0P0 BIT(0) /*!< pin G0P0 channel pin mode */ +#define TSI_CHCFG_G0P1 BIT(1) /*!< pin G0P1 channel pin mode */ +#define TSI_CHCFG_G0P2 BIT(2) /*!< pin G0P2 channel pin mode */ +#define TSI_CHCFG_G0P3 BIT(3) /*!< pin G0P3 channel pin mode */ +#define TSI_CHCFG_G1P0 BIT(4) /*!< pin G1P0 channel pin mode */ +#define TSI_CHCFG_G1P1 BIT(5) /*!< pin G1P1 channel pin mode */ +#define TSI_CHCFG_G1P2 BIT(6) /*!< pin G1P2 channel pin mode */ +#define TSI_CHCFG_G1P3 BIT(7) /*!< pin G1P3 channel pin mode */ +#define TSI_CHCFG_G2P0 BIT(8) /*!< pin G2P0 channel pin mode */ +#define TSI_CHCFG_G2P1 BIT(9) /*!< pin G2P1 channel pin mode */ +#define TSI_CHCFG_G2P2 BIT(10) /*!< pin G2P2 channel pin mode */ +#define TSI_CHCFG_G2P3 BIT(11) /*!< pin G2P3 channel pin mode */ +#define TSI_CHCFG_G3P0 BIT(12) /*!< pin G3P0 channel pin mode */ +#define TSI_CHCFG_G3P1 BIT(13) /*!< pin G3P1 channel pin mode */ +#define TSI_CHCFG_G3P2 BIT(14) /*!< pin G3P2 channel pin mode */ +#define TSI_CHCFG_G3P3 BIT(15) /*!< pin G3P3 channel pin mode */ +#define TSI_CHCFG_G4P0 BIT(16) /*!< pin G4P0 channel pin mode */ +#define TSI_CHCFG_G4P1 BIT(17) /*!< pin G4P1 channel pin mode */ +#define TSI_CHCFG_G4P2 BIT(18) /*!< pin G4P2 channel pin mode */ +#define TSI_CHCFG_G4P3 BIT(19) /*!< pin G4P3 channel pin mode */ +#define TSI_CHCFG_G5P0 BIT(20) /*!< pin G5P0 channel pin mode */ +#define TSI_CHCFG_G5P1 BIT(21) /*!< pin G5P1 channel pin mode */ +#define TSI_CHCFG_G5P2 BIT(22) /*!< pin G5P2 channel pin mode */ +#define TSI_CHCFG_G5P3 BIT(23) /*!< pin G5P3 channel pin mode */ + +/* TSI_GCTL */ +#define TSI_GCTL_GE0 BIT(0) /*!< group0 enable */ +#define TSI_GCTL_GE1 BIT(1) /*!< group1 enable */ +#define TSI_GCTL_GE2 BIT(2) /*!< group2 enable */ +#define TSI_GCTL_GE3 BIT(3) /*!< group3 enable */ +#define TSI_GCTL_GE4 BIT(4) /*!< group4 enable */ +#define TSI_GCTL_GE5 BIT(5) /*!< group5 enable */ +#define TSI_GCTL_GC0 BIT(16) /*!< group0 complete */ +#define TSI_GCTL_GC1 BIT(17) /*!< group1 complete */ +#define TSI_GCTL_GC2 BIT(18) /*!< group2 complete */ +#define TSI_GCTL_GC3 BIT(19) /*!< group3 complete */ +#define TSI_GCTL_GC4 BIT(20) /*!< group4 complete */ +#define TSI_GCTL_GC5 BIT(21) /*!< group5 complete */ + +/* TSI_CTL1 */ +#define TSI_CTL1_CTCDIV BIT(24) /*!< CTCLK clock division factor */ +#define TSI_CTL1_ECDIV BITS(28,29) /*!< ECCLK clock division factor */ + +/* constants definitions */ +/* TSI interrupt enable bit */ +#define TSI_INT_CCTCF TSI_INTEN_CTCFIE /*!< charge transfer complete flag interrupt enable */ +#define TSI_INT_MNERR TSI_INTEN_MNERRIE /*!< max cycle number error interrupt enable */ + +/* I2C interrupt flags */ +#define TSI_INT_FLAG_CTCF TSI_INTF_CTCF /*!< charge transfer complete flag */ +#define TSI_INT_FLAG_MNERR TSI_INTF_MNERR /*!< max cycle number error */ + +/* I2C interrupt clear flags */ +#define TSI_INT_FLAG_CTCF_CLR TSI_INTC_CCTCF /*!< clear charge transfer complete flag */ +#define TSI_INT_FLAG_MNERR_CLR TSI_INTC_CMNERR /*!< clear max cycle number error */ + +/* I2C flags */ +#define TSI_FLAG_CTCF TSI_INTF_CTCF /*!< charge transfer complete flag */ +#define TSI_FLAG_MNERR TSI_INTF_MNERR /*!< max cycle number error */ + +/* I2C clear flags */ +#define TSI_FLAG_CTCF_CLR TSI_INTC_CCTCF /*!< clear charge transfer complete flag */ +#define TSI_FLAG_MNERR_CLR TSI_INTC_CMNERR /*!< clear max cycle number error */ + +/* CTCLK clock division factor */ +#define TSI_CTCDIV_DIV1 ((uint32_t)0x00000000U) /*!< fCTCLK = fHCLK */ +#define TSI_CTCDIV_DIV2 ((uint32_t)0x00000001U) /*!< fCTCLK = fHCLK/2 */ +#define TSI_CTCDIV_DIV4 ((uint32_t)0x00000002U) /*!< fCTCLK = fHCLK/4 */ +#define TSI_CTCDIV_DIV8 ((uint32_t)0x00000003U) /*!< fCTCLK = fHCLK/8 */ +#define TSI_CTCDIV_DIV16 ((uint32_t)0x00000004U) /*!< fCTCLK = fHCLK/16 */ +#define TSI_CTCDIV_DIV32 ((uint32_t)0x00000005U) /*!< fCTCLK = fHCLK/32 */ +#define TSI_CTCDIV_DIV64 ((uint32_t)0x00000006U) /*!< fCTCLK = fHCLK/64 */ +#define TSI_CTCDIV_DIV128 ((uint32_t)0x00000007U) /*!< fCTCLK = fHCLK/128 */ +#define TSI_CTCDIV_DIV256 ((uint32_t)0x00000008U) /*!< fCTCLK = fHCLK/256 */ +#define TSI_CTCDIV_DIV512 ((uint32_t)0x00000009U) /*!< fCTCLK = fHCLK/512 */ +#define TSI_CTCDIV_DIV1024 ((uint32_t)0x0000000AU) /*!< fCTCLK = fHCLK/1024 */ +#define TSI_CTCDIV_DIV2048 ((uint32_t)0x0000000BU) /*!< fCTCLK = fHCLK/2048 */ +#define TSI_CTCDIV_DIV4096 ((uint32_t)0x0000000CU) /*!< fCTCLK = fHCLK/4096 */ +#define TSI_CTCDIV_DIV8192 ((uint32_t)0x0000000DU) /*!< fCTCLK = fHCLK/8192 */ +#define TSI_CTCDIV_DIV16384 ((uint32_t)0x0000000EU) /*!< fCTCLK = fHCLK/16384 */ +#define TSI_CTCDIV_DIV32768 ((uint32_t)0x0000000FU) /*!< fCTCLK = fHCLK/32768 */ + +/* charge transfer state duration Time */ +#define CTL_CTDT(regval) (BITS(24,27) & ((uint32_t)(regval) << 24U)) +#define TSI_TRANSFER_1CTCLK CTL_CTDT(0) /*!< the duration time of transfer state is 1 CTCLK */ +#define TSI_TRANSFER_2CTCLK CTL_CTDT(1) /*!< the duration time of transfer state is 2 CTCLK */ +#define TSI_TRANSFER_3CTCLK CTL_CTDT(2) /*!< the duration time of transfer state is 3 CTCLK */ +#define TSI_TRANSFER_4CTCLK CTL_CTDT(3) /*!< the duration time of transfer state is 4 CTCLK */ +#define TSI_TRANSFER_5CTCLK CTL_CTDT(4) /*!< the duration time of transfer state is 5 CTCLK */ +#define TSI_TRANSFER_6CTCLK CTL_CTDT(5) /*!< the duration time of transfer state is 6 CTCLK */ +#define TSI_TRANSFER_7CTCLK CTL_CTDT(6) /*!< the duration time of transfer state is 7 CTCLK */ +#define TSI_TRANSFER_8CTCLK CTL_CTDT(7) /*!< the duration time of transfer state is 8 CTCLK */ +#define TSI_TRANSFER_9CTCLK CTL_CTDT(8) /*!< the duration time of transfer state is 9 CTCLK */ +#define TSI_TRANSFER_10CTCLK CTL_CTDT(9) /*!< the duration time of transfer state is 10 CTCLK */ +#define TSI_TRANSFER_11CTCLK CTL_CTDT(10) /*!< the duration time of transfer state is 11 CTCLK */ +#define TSI_TRANSFER_12CTCLK CTL_CTDT(11) /*!< the duration time of transfer state is 12 CTCLK */ +#define TSI_TRANSFER_13CTCLK CTL_CTDT(12) /*!< the duration time of transfer state is 13 CTCLK */ +#define TSI_TRANSFER_14CTCLK CTL_CTDT(13) /*!< the duration time of transfer state is 14 CTCLK */ +#define TSI_TRANSFER_15CTCLK CTL_CTDT(14) /*!< the duration time of transfer state is 15 CTCLK */ +#define TSI_TRANSFER_16CTCLK CTL_CTDT(15) /*!< the duration time of transfer state is 16 CTCLK */ + +/* charge state duration time */ +#define CTL_CDT(regval) (BITS(28,31) & ((uint32_t)(regval) << 28U)) +#define TSI_CHARGE_1CTCLK CTL_CDT(0) /*!< the duration time of charge state is 1 CTCLK */ +#define TSI_CHARGE_2CTCLK CTL_CDT(1) /*!< the duration time of charge state is 2 CTCLK */ +#define TSI_CHARGE_3CTCLK CTL_CDT(2) /*!< the duration time of charge state is 3 CTCLK */ +#define TSI_CHARGE_4CTCLK CTL_CDT(3) /*!< the duration time of charge state is 4 CTCLK */ +#define TSI_CHARGE_5CTCLK CTL_CDT(4) /*!< the duration time of charge state is 5 CTCLK */ +#define TSI_CHARGE_6CTCLK CTL_CDT(5) /*!< the duration time of charge state is 6 CTCLK */ +#define TSI_CHARGE_7CTCLK CTL_CDT(6) /*!< the duration time of charge state is 7 CTCLK */ +#define TSI_CHARGE_8CTCLK CTL_CDT(7) /*!< the duration time of charge state is 8 CTCLK */ +#define TSI_CHARGE_9CTCLK CTL_CDT(8) /*!< the duration time of charge state is 9 CTCLK */ +#define TSI_CHARGE_10CTCLK CTL_CDT(9) /*!< the duration time of charge state is 10 CTCLK */ +#define TSI_CHARGE_11CTCLK CTL_CDT(10) /*!< the duration time of charge state is 11 CTCLK */ +#define TSI_CHARGE_12CTCLK CTL_CDT(11) /*!< the duration time of charge state is 12 CTCLK */ +#define TSI_CHARGE_13CTCLK CTL_CDT(12) /*!< the duration time of charge state is 13 CTCLK */ +#define TSI_CHARGE_14CTCLK CTL_CDT(13) /*!< the duration time of charge state is 14 CTCLK */ +#define TSI_CHARGE_15CTCLK CTL_CDT(14) /*!< the duration time of charge state is 15 CTCLK */ +#define TSI_CHARGE_16CTCLK CTL_CDT(15) /*!< the duration time of charge state is 16 CTCLK */ + +/* max cycle number of a sequence */ +#define CTL_MCN(regval) (BITS(5,7) & ((uint32_t)(regval) << 5U)) +#define TSI_MAXNUM255 CTL_MCN(0) /*!< the max cycle number of a sequence is 255 */ +#define TSI_MAXNUM511 CTL_MCN(1) /*!< the max cycle number of a sequence is 511 */ +#define TSI_MAXNUM1023 CTL_MCN(2) /*!< the max cycle number of a sequence is 1023 */ +#define TSI_MAXNUM2047 CTL_MCN(3) /*!< the max cycle number of a sequence is 2047 */ +#define TSI_MAXNUM4095 CTL_MCN(4) /*!< the max cycle number of a sequence is 4095 */ +#define TSI_MAXNUM8191 CTL_MCN(5) /*!< the max cycle number of a sequence is 8191 */ +#define TSI_MAXNUM16383 CTL_MCN(6) /*!< the max cycle number of a sequence is 16383 */ + +/* ECCLK clock division factor */ +#define TSI_EXTEND_DIV1 ((uint32_t)0x00000000U) /*!< fECCLK = fHCLK */ +#define TSI_EXTEND_DIV2 ((uint32_t)0x00000001U) /*!< fECCLK = fHCLK/2 */ +#define TSI_EXTEND_DIV3 ((uint32_t)0x00000002U) /*!< fECCLK = fHCLK/3 */ +#define TSI_EXTEND_DIV4 ((uint32_t)0x00000003U) /*!< fECCLK = fHCLK/4 */ +#define TSI_EXTEND_DIV5 ((uint32_t)0x00000004U) /*!< fECCLK = fHCLK/5 */ +#define TSI_EXTEND_DIV6 ((uint32_t)0x00000005U) /*!< fECCLK = fHCLK/6 */ +#define TSI_EXTEND_DIV7 ((uint32_t)0x00000006U) /*!< fECCLK = fHCLK/7 */ +#define TSI_EXTEND_DIV8 ((uint32_t)0x00000007U) /*!< fECCLK = fHCLK/8 */ + +/* extend charge state maximum duration time */ +#define TSI_EXTENDMAX(regval) (BITS(17,23) & ((uint32_t)(regval) << 17U)) /* value range 1..128,extend charge state maximum duration time */ + +/* hardware trigger mode */ +#define TSI_FALLING_TRIGGER 0x00U /*!< falling edge trigger TSI charge transfer sequence */ +#define TSI_RISING_TRIGGER 0x01U /*!< rising edge trigger TSI charge transfer sequence */ + +/* pin mode */ +#define TSI_OUTPUT_LOW 0x00U /*!< TSI pin will output low when IDLE */ +#define TSI_INPUT_FLOATING 0x01U /*!< TSI pin will keep input_floating when IDLE */ + +/* function declarations */ +/* reset TSI peripheral */ +void tsi_deinit(void); +/* initialize TSI plus prescaler,charge plus,transfer plus,max cycle number */ +void tsi_init(uint32_t prescaler,uint32_t charge_duration,uint32_t transfer_duration,uint32_t max_number); +/* enable TSI module */ +void tsi_enable(void); +/* disable TSI module */ +void tsi_disable(void); +/* enable sample pin */ +void tsi_sample_pin_enable(uint32_t sample); +/* disable sample pin */ +void tsi_sample_pin_disable(uint32_t sample); +/* enable channel pin */ +void tsi_channel_pin_enable(uint32_t channel); +/* disable channel pin */ +void tsi_channel_pin_disable(uint32_t channel); + +/* configure TSI triggering by software */ +void tsi_sofeware_mode_config(void); +/* start a charge-transfer sequence when TSI is in software trigger mode */ +void tsi_software_start(void); +/* stop a charge-transfer sequence when TSI is in software trigger mode */ +void tsi_software_stop(void); +/* configure TSI triggering by hardware */ +void tsi_hardware_mode_config(uint8_t trigger_edge); +/* configure TSI pin mode when charge-transfer sequence is IDLE */ +void tsi_pin_mode_config(uint8_t pin_mode); +/* configure extend charge state */ +void tsi_extend_charge_config(ControlStatus extend,uint8_t prescaler,uint32_t max_duration); + +/* configure charge plus and transfer plus */ +void tsi_plus_config(uint32_t prescaler,uint32_t charge_duration,uint32_t transfer_duration); +/* configure the max cycle number of a charge-transfer sequence */ +void tsi_max_number_config(uint32_t max_number); +/* switch on hysteresis pin */ +void tsi_hysteresis_on(uint32_t group_pin); +/* switch off hysteresis pin */ +void tsi_hysteresis_off(uint32_t group_pin); +/* switch on analog pin */ +void tsi_analog_on(uint32_t group_pin); +/* switch off analog pin */ +void tsi_analog_off(uint32_t group_pin); + +/* enable TSI interrupt */ +void tsi_interrupt_enable(uint32_t source); +/* disable TSI interrupt */ +void tsi_interrupt_disable(uint32_t source); +/* clear interrupt flag */ +void tsi_interrupt_flag_clear(uint32_t flag); +/* get TSI interrupt flag */ +FlagStatus tsi_interrupt_flag_get(uint32_t flag); + +/* clear flag */ +void tsi_flag_clear(uint32_t flag); +/* get flag */ +FlagStatus tsi_flag_get(uint32_t flag); + +/* enbale group */ +void tsi_group_enable(uint32_t group); +/* disbale group */ +void tsi_group_disable(uint32_t group); +/* get group complete status */ +FlagStatus tsi_group_status_get(uint32_t group); +/* get the cycle number for group0 as soon as a charge-transfer sequence completes */ +uint16_t tsi_group0_cycle_get(void); +/* get the cycle number for group1 as soon as a charge-transfer sequence completes */ +uint16_t tsi_group1_cycle_get(void); +/* get the cycle number for group2 as soon as a charge-transfer sequence completes */ +uint16_t tsi_group2_cycle_get(void); +/* get the cycle number for group3 as soon as a charge-transfer sequence completes */ +uint16_t tsi_group3_cycle_get(void); +/* get the cycle number for group4 as soon as a charge-transfer sequence completes */ +uint16_t tsi_group4_cycle_get(void); +/* get the cycle number for group5 as soon as a charge-transfer sequence completes */ +uint16_t tsi_group5_cycle_get(void); + +#endif /* GD32F3X0_TSI_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_usart.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_usart.h new file mode 100644 index 0000000000..fb06b818de --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_usart.h @@ -0,0 +1,595 @@ +/*! + \file gd32f3x0_usart.h + \brief definitions for the USART + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F3X0_USART_H +#define GD32F3X0_USART_H + +#include "gd32f3x0.h" + +/* USARTx(x=0,1) definitions */ +#define USART0 (USART_BASE + 0x0000F400U) +#define USART1 USART_BASE + +/* registers definitions */ +#define USART_CTL0(usartx) REG32((usartx) + 0x00000000U) /*!< USART control register 0 */ +#define USART_CTL1(usartx) REG32((usartx) + 0x00000004U) /*!< USART control register 1 */ +#define USART_CTL2(usartx) REG32((usartx) + 0x00000008U) /*!< USART control register 2 */ +#define USART_BAUD(usartx) REG32((usartx) + 0x0000000CU) /*!< USART baud rate register */ +#define USART_GP(usartx) REG32((usartx) + 0x00000010U) /*!< USART guard time and prescaler register */ +#define USART_RT(usartx) REG32((usartx) + 0x00000014U) /*!< USART receiver timeout register */ +#define USART_CMD(usartx) REG32((usartx) + 0x00000018U) /*!< USART command register */ +#define USART_STAT(usartx) REG32((usartx) + 0x0000001CU) /*!< USART status register */ +#define USART_INTC(usartx) REG32((usartx) + 0x00000020U) /*!< USART status clear register */ +#define USART_RDATA(usartx) REG32((usartx) + 0x00000024U) /*!< USART receive data register */ +#define USART_TDATA(usartx) REG32((usartx) + 0x00000028U) /*!< USART transmit data register */ +#define USART_RFCS(usartx) REG32((usartx) + 0x000000D0U) /*!< USART receive FIFO control and status register */ + +/* bits definitions */ +/* USARTx_CTL0 */ +#define USART_CTL0_UEN BIT(0) /*!< USART enable */ +#define USART_CTL0_UESM BIT(1) /*!< USART enable in deep-sleep mode */ +#define USART_CTL0_REN BIT(2) /*!< receiver enable */ +#define USART_CTL0_TEN BIT(3) /*!< transmitter enable */ +#define USART_CTL0_IDLEIE BIT(4) /*!< idle line detected interrupt enable */ +#define USART_CTL0_RBNEIE BIT(5) /*!< read data buffer not empty interrupt and overrun error interrupt enable */ +#define USART_CTL0_TCIE BIT(6) /*!< transmission complete interrupt enable */ +#define USART_CTL0_TBEIE BIT(7) /*!< transmitter register empty interrupt enable */ +#define USART_CTL0_PERRIE BIT(8) /*!< parity error interrupt enable */ +#define USART_CTL0_PM BIT(9) /*!< parity mode */ +#define USART_CTL0_PCEN BIT(10) /*!< parity control enable */ +#define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */ +#define USART_CTL0_WL BIT(12) /*!< word length */ +#define USART_CTL0_MEN BIT(13) /*!< mute mode enable */ +#define USART_CTL0_AMIE BIT(14) /*!< address match interrupt enable */ +#define USART_CTL0_OVSMOD BIT(15) /*!< oversample mode */ +#define USART_CTL0_DED BITS(16,20) /*!< driver enable deassertion time */ +#define USART_CTL0_DEA BITS(21,25) /*!< driver enable assertion time */ +#define USART_CTL0_RTIE BIT(26) /*!< receiver timeout interrupt enable */ +#define USART_CTL0_EBIE BIT(27) /*!< end of block interrupt enable */ + +/* USARTx_CTL1 */ +#define USART_CTL1_ADDM BIT(4) /*!< address detection mode */ +#define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */ +#define USART_CTL1_LBDIE BIT(6) /*!< LIN break detection interrupt enable */ +#define USART_CTL1_CLEN BIT(8) /*!< last bit clock pulse */ +#define USART_CTL1_CPH BIT(9) /*!< clock phase */ +#define USART_CTL1_CPL BIT(10) /*!< clock polarity */ +#define USART_CTL1_CKEN BIT(11) /*!< ck pin enable */ +#define USART_CTL1_STB BITS(12,13) /*!< stop bits length */ +#define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */ +#define USART_CTL1_STRP BIT(15) /*!< swap TX/RX pins */ +#define USART_CTL1_RINV BIT(16) /*!< RX pin level inversion */ +#define USART_CTL1_TINV BIT(17) /*!< TX pin level inversion */ +#define USART_CTL1_DINV BIT(18) /*!< data bit level inversion */ +#define USART_CTL1_MSBF BIT(19) /*!< most significant bit first */ +#define USART_CTL1_ABDEN BIT(20) /*!< auto baud rate enable */ +#define USART_CTL1_ABDM BITS(21,22) /*!< auto baud rate mode */ +#define USART_CTL1_RTEN BIT(23) /*!< receiver timeout enable */ +#define USART_CTL1_ADDR BITS(24,31) /*!< address of the USART terminal */ + +/* USARTx_CTL2 */ +#define USART_CTL2_ERRIE BIT(0) /*!< error interrupt enable in multibuffer communication */ +#define USART_CTL2_IREN BIT(1) /*!< IrDA mode enable */ +#define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */ +#define USART_CTL2_HDEN BIT(3) /*!< half-duplex enable */ +#define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */ +#define USART_CTL2_SCEN BIT(5) /*!< smartcard mode enable */ +#define USART_CTL2_DENR BIT(6) /*!< DMA enable for reception */ +#define USART_CTL2_DENT BIT(7) /*!< DMA enable for transmission */ +#define USART_CTL2_RTSEN BIT(8) /*!< RTS enable */ +#define USART_CTL2_CTSEN BIT(9) /*!< CTS enable */ +#define USART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */ +#define USART_CTL2_OSB BIT(11) /*!< one sample bit mode */ +#define USART_CTL2_OVRD BIT(12) /*!< overrun disable */ +#define USART_CTL2_DDRE BIT(13) /*!< disable DMA on reception error */ +#define USART_CTL2_DEM BIT(14) /*!< driver enable mode */ +#define USART_CTL2_DEP BIT(15) /*!< driver enable polarity mode */ +#define USART_CTL2_SCRTNUM BITS(17,19) /*!< smartcard auto-retry number */ +#define USART_CTL2_WUM BITS(20,21) /*!< wakeup mode from deep-sleep mode */ +#define USART_CTL2_WUIE BIT(22) /*!< wakeup from deep-sleep mode interrupt enable */ + +/* USARTx_BAUD */ +#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction of baud-rate divider */ +#define USART_BAUD_INTDIV BITS(4,15) /*!< integer of baud-rate divider */ + +/* USARTx_GP */ +#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ +#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ + +/* USARTx_RT */ +#define USART_RT_RT BITS(0,23) /*!< receiver timeout threshold */ +#define USART_RT_BL BITS(24,31) /*!< block length */ + +/* USARTx_CMD */ +#define USART_CMD_ABDCMD BIT(0) /*!< auto baudrate detection command */ +#define USART_CMD_SBKCMD BIT(1) /*!< send break command */ +#define USART_CMD_MMCMD BIT(2) /*!< mute mode command */ +#define USART_CMD_RXFCMD BIT(3) /*!< receive data flush command */ +#define USART_CMD_TXFCMD BIT(4) /*!< transmit data flush request */ + +/* USARTx_STAT */ +#define USART_STAT_PERR BIT(0) /*!< parity error flag */ +#define USART_STAT_FERR BIT(1) /*!< frame error flag */ +#define USART_STAT_NERR BIT(2) /*!< noise error flag */ +#define USART_STAT_ORERR BIT(3) /*!< overrun error */ +#define USART_STAT_IDLEF BIT(4) /*!< idle line detected flag */ +#define USART_STAT_RBNE BIT(5) /*!< read data buffer not empty */ +#define USART_STAT_TC BIT(6) /*!< transmission completed */ +#define USART_STAT_TBE BIT(7) /*!< transmit data register empty */ +#define USART_STAT_LBDF BIT(8) /*!< LIN break detected flag */ +#define USART_STAT_CTSF BIT(9) /*!< CTS change flag */ +#define USART_STAT_CTS BIT(10) /*!< CTS level */ +#define USART_STAT_RTF BIT(11) /*!< receiver timeout flag */ +#define USART_STAT_EBF BIT(12) /*!< end of block flag */ +#define USART_STAT_ABDE BIT(14) /*!< auto baudrate detection error */ +#define USART_STAT_ABDF BIT(15) /*!< auto baudrate detection flag */ +#define USART_STAT_BSY BIT(16) /*!< busy flag */ +#define USART_STAT_AMF BIT(17) /*!< address match flag */ +#define USART_STAT_SBF BIT(18) /*!< send break flag */ +#define USART_STAT_RWU BIT(19) /*!< receiver wakeup from mute mode */ +#define USART_STAT_WUF BIT(20) /*!< wakeup from deep-sleep mode flag */ +#define USART_STAT_TEA BIT(21) /*!< transmit enable acknowledge flag */ +#define USART_STAT_REA BIT(22) /*!< receive enable acknowledge flag */ + +/* USARTx_INTC */ +#define USART_INTC_PEC BIT(0) /*!< parity error clear */ +#define USART_INTC_FEC BIT(1) /*!< frame error flag clear */ +#define USART_INTC_NEC BIT(2) /*!< noise detected clear */ +#define USART_INTC_OREC BIT(3) /*!< overrun error clear */ +#define USART_INTC_IDLEC BIT(4) /*!< idle line detected clear */ +#define USART_INTC_TCC BIT(6) /*!< transmission complete clear */ +#define USART_INTC_LBDC BIT(8) /*!< LIN break detected clear */ +#define USART_INTC_CTSC BIT(9) /*!< CTS change clear */ +#define USART_INTC_RTC BIT(11) /*!< receiver timeout clear */ +#define USART_INTC_EBC BIT(12) /*!< end of timeout clear */ +#define USART_INTC_AMC BIT(17) /*!< address match clear */ +#define USART_INTC_WUC BIT(20) /*!< wakeup from deep-sleep mode clear */ + +/* USARTx_RDATA */ +#define USART_RDATA_RDATA BITS(0,8) /*!< receive data value */ + +/* USARTx_TDATA */ +#define USART_TDATA_TDATA BITS(0,8) /*!< transmit data value */ + +/* USARTx_RFCS */ +#define USART_RFCS_ELNACK BIT(0) /*!< early NACK */ +#define USART_RFCS_RFEN BIT(8) /*!< receive FIFO enable */ +#define USART_RFCS_RFFIE BIT(9) /*!< receive FIFO full interrupt enable */ +#define USART_RFCS_RFE BIT(10) /*!< receive FIFO empty flag */ +#define USART_RFCS_RFF BIT(11) /*!< receive FIFO full flag */ +#define USART_RFCS_RFCNT BITS(12,14) /*!< receive FIFO counter number */ +#define USART_RFCS_RFFINT BIT(15) /*!< receive FIFO full interrupt flag */ + +/* constants definitions */ + +/* define the USART bit position and its register index offset */ +#define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6))) +#define USART_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU) +#define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ + | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) +#define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22))) +#define USART_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16) + +/* register offset */ +#define USART_CTL0_REG_OFFSET (0x00000000U) /*!< CTL0 register offset */ +#define USART_CTL1_REG_OFFSET (0x00000004U) /*!< CTL1 register offset */ +#define USART_CTL2_REG_OFFSET (0x00000008U) /*!< CTL2 register offset */ +#define USART_STAT_REG_OFFSET (0x0000001CU) /*!< STAT register offset */ +#define USART_RFCS_REG_OFFSET (0x000000D0U) /*!< RFCS register offset */ + +/* USART flags */ +typedef enum{ + /* flags in STAT register */ + USART_FLAG_REA = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 22U), /*!< receive enable acknowledge flag */ + USART_FLAG_TEA = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 21U), /*!< transmit enable acknowledge flag */ + USART_FLAG_WU = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 20U), /*!< wakeup from deep-sleep mode flag */ + USART_FLAG_RWU = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 19U), /*!< receiver wakeup from mute mode */ + USART_FLAG_SB = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 18U), /*!< send break flag */ + USART_FLAG_AM = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 17U), /*!< ADDR match flag */ + USART_FLAG_BSY = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 16U), /*!< busy flag */ + USART_FLAG_ABD = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 15U), /*!< auto baudrate detection flag */ + USART_FLAG_ABDE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 14U), /*!< auto baudrate detection error */ + USART_FLAG_EB = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 12U), /*!< end of block flag */ + USART_FLAG_RT = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 11U), /*!< receiver timeout flag */ + USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 10U), /*!< CTS level */ + USART_FLAG_CTSF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 9U), /*!< CTS change flag */ + USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected flag */ + USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 7U), /*!< transmit data buffer empty */ + USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 6U), /*!< transmission complete */ + USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty */ + USART_FLAG_IDLE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 4U), /*!< IDLE line detected flag */ + USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 3U), /*!< overrun error */ + USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 2U), /*!< noise error flag */ + USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 1U), /*!< frame error flag */ + USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 0U), /*!< parity error flag */ + /* flags in RFCS register */ + USART_FLAG_RFF = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 11U), /*!< receive FIFO full flag */ + USART_FLAG_RFE = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 10U), /*!< receive FIFO empty flag */ +}usart_flag_enum; + +/* USART interrupt flags */ +typedef enum +{ + /* interrupt flags in CTL0 register */ + USART_INT_FLAG_EB = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 27U, USART_STAT_REG_OFFSET, 12U), /*!< end of block interrupt flag */ + USART_INT_FLAG_RT = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 26U, USART_STAT_REG_OFFSET, 11U), /*!< receiver timeout interrupt flag */ + USART_INT_FLAG_AM = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 14U, USART_STAT_REG_OFFSET, 17U), /*!< address match interrupt flag */ + USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT_REG_OFFSET, 0U), /*!< parity error interrupt flag */ + USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt flag */ + USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 6U), /*!< transmission complete interrupt flag */ + USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt flag */ + USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 3U), /*!< overrun error interrupt flag */ + USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT_REG_OFFSET, 4U), /*!< IDLE line detected interrupt flag */ + /* interrupt flags in CTL1 register */ + USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected interrupt flag */ + /* interrupt flags in CTL2 register */ + USART_INT_FLAG_WU = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 22U, USART_STAT_REG_OFFSET, 20U), /*!< wakeup from deep-sleep mode interrupt flag */ + USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT_REG_OFFSET, 9U), /*!< CTS interrupt flag */ + USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 2U), /*!< noise error interrupt flag */ + USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 3U), /*!< overrun error interrupt flag */ + USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 1U), /*!< frame error interrupt flag */ + /* interrupt flags in RFCS register */ + USART_INT_FLAG_RFFINT = USART_REGIDX_BIT2(USART_RFCS_REG_OFFSET, 9U, USART_RFCS_REG_OFFSET, 15U), /*!< receive FIFO full interrupt flag */ +}usart_interrupt_flag_enum; + +/* USART interrupt enable or disable */ +typedef enum +{ + /* interrupt in CTL0 register */ + USART_INT_EB = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 27U), /*!< end of block interrupt */ + USART_INT_RT = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 26U), /*!< receiver timeout interrupt */ + USART_INT_AM = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 14U), /*!< address match interrupt */ + USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */ + USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */ + USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */ + USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */ + USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */ + /* interrupt in CTL1 register */ + USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */ + /* interrupt in CTL2 register */ + USART_INT_WU = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 22U), /*!< wakeup from deep-sleep mode interrupt */ + USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */ + USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U), /*!< error interrupt */ + /* interrupt in RFCS register */ + USART_INT_RFF = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 9U), /*!< receive FIFO full interrupt */ +}usart_interrupt_enum; + +/* USART invert configure */ +typedef enum { + /* data bit level inversion */ + USART_DINV_ENABLE, /*!< data bit level inversion */ + USART_DINV_DISABLE, /*!< data bit level not inversion */ + /* TX pin level inversion */ + USART_TXPIN_ENABLE, /*!< TX pin level inversion */ + USART_TXPIN_DISABLE, /*!< TX pin level not inversion */ + /* RX pin level inversion */ + USART_RXPIN_ENABLE, /*!< RX pin level inversion */ + USART_RXPIN_DISABLE, /*!< RX pin level not inversion */ + /* swap TX/RX pins */ + USART_SWAP_ENABLE, /*!< swap TX/RX pins */ + USART_SWAP_DISABLE, /*!< not swap TX/RX pins */ +}usart_invert_enum; + +/* USART receiver configure */ +#define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2)) +#define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */ +#define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */ + +/* USART transmitter configure */ +#define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3)) +#define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */ +#define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */ + +/* USART parity bits definitions */ +#define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9)) +#define USART_PM_NONE CTL0_PM(0) /*!< no parity */ +#define USART_PM_EVEN CTL0_PM(2) /*!< even parity */ +#define USART_PM_ODD CTL0_PM(3) /*!< odd parity */ + +/* USART wakeup method in mute mode */ +#define CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11)) +#define USART_WM_IDLE CTL0_WM(0) /*!< idle line */ +#define USART_WM_ADDR CTL0_WM(1) /*!< address match */ + +/* USART word length definitions */ +#define CTL0_WL(regval) (BIT(12) & ((uint32_t)(regval) << 12)) +#define USART_WL_8BIT CTL0_WL(0) /*!< 8 bits */ +#define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */ + +/* USART oversample mode */ +#define CTL0_OVSMOD(regval) (BIT(15) & ((uint32_t)(regval) << 15)) +#define USART_OVSMOD_8 CTL0_OVSMOD(1) /*!< oversampling by 8 */ +#define USART_OVSMOD_16 CTL0_OVSMOD(0) /*!< oversampling by 16 */ + +/* USART address detection mode */ +#define CTL1_ADDM(regval) (BIT(4) & ((uint32_t)(regval) << 4)) +#define USART_ADDM_4BIT CTL1_ADDM(0) /*!< 4-bit address detection */ +#define USART_ADDM_FULLBIT CTL1_ADDM(1) /*!< full-bit address detection */ + +/* USART LIN break frame length */ +#define CTL1_LBLEN(regval) (BIT(5) & ((uint32_t)(regval) << 5)) +#define USART_LBLEN_10B CTL1_LBLEN(0) /*!< 10 bits break detection */ +#define USART_LBLEN_11B CTL1_LBLEN(1) /*!< 11 bits break detection */ + +/* USART last bit clock pulse */ +#define CTL1_CLEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) +#define USART_CLEN_NONE CTL1_CLEN(0) /*!< clock pulse of the last data bit (MSB) is not output to the CK pin */ +#define USART_CLEN_EN CTL1_CLEN(1) /*!< clock pulse of the last data bit (MSB) is output to the CK pin */ + +/* USART clock phase */ +#define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9)) +#define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition is the first data capture edge */ +#define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition is the first data capture edge */ + +/* USART clock polarity */ +#define CTL1_CPL(regval) (BIT(10) & ((uint32_t)(regval) << 10)) +#define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */ +#define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */ + +/* USART stop bits definitions */ +#define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) +#define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */ +#define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */ +#define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */ +#define USART_STB_1_5BIT CTL1_STB(3) /*!< 1.5 bits */ + +/* USART data is transmitted/received with the LSB/MSB first */ +#define CTL1_MSBF(regval) (BIT(19) & ((uint32_t)(regval) << 19)) +#define USART_MSBF_LSB CTL1_MSBF(0) /*!< LSB first */ +#define USART_MSBF_MSB CTL1_MSBF(1) /*!< MSB first */ + +/* USART auto baud rate detection mode bits definitions */ +#define CTL1_ABDM(regval) (BITS(21,22) & ((uint32_t)(regval) << 21)) +#define USART_ABDM_FTOR CTL1_ABDM(0) /*!< falling edge to rising edge measurement */ +#define USART_ABDM_FTOF CTL1_ABDM(1) /*!< falling edge to falling edge measurement */ + +/* USART IrDA low-power enable */ +#define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2)) +#define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */ +#define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */ + +/* DMA enable for reception */ +#define CTL2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6)) +#define USART_DENR_ENABLE CTL2_DENR(1) /*!< enable for reception */ +#define USART_DENR_DISABLE CTL2_DENR(0) /*!< disable for reception */ + +/* DMA enable for transmission */ +#define CTL2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7)) +#define USART_DENT_ENABLE CTL2_DENT(1) /*!< enable for transmission */ +#define USART_DENT_DISABLE CTL2_DENT(0) /*!< disable for transmission */ + +/* USART RTS hardware flow control configure */ +#define CTL2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) +#define USART_RTS_ENABLE CTL2_RTSEN(1) /*!< RTS hardware flow control enabled */ +#define USART_RTS_DISABLE CTL2_RTSEN(0) /*!< RTS hardware flow control disabled */ + +/* USART CTS hardware flow control configure */ +#define CTL2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9)) +#define USART_CTS_ENABLE CTL2_CTSEN(1) /*!< CTS hardware flow control enabled */ +#define USART_CTS_DISABLE CTL2_CTSEN(0) /*!< CTS hardware flow control disabled */ + +/* USART one sample bit method configure */ +#define CTL2_OSB(regval) (BIT(11) & ((uint32_t)(regval) << 11)) +#define USART_OSB_1BIT CTL2_OSB(1) /*!< 1 sample bit */ +#define USART_OSB_3BIT CTL2_OSB(0) /*!< 3 sample bits */ + +/* USART driver enable polarity mode */ +#define CTL2_DEP(regval) (BIT(15) & ((uint32_t)(regval) << 15)) +#define USART_DEP_HIGH CTL2_DEP(0) /*!< DE signal is active high */ +#define USART_DEP_LOW CTL2_DEP(1) /*!< DE signal is active low */ + +/* USART wakeup mode from deep-sleep mode */ +#define CTL2_WUM(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) +#define USART_WUM_ADDR CTL2_WUM(0) /*!< WUF active on address match */ +#define USART_WUM_STARTB CTL2_WUM(2) /*!< WUF active on start bit */ +#define USART_WUM_RBNE CTL2_WUM(3) /*!< WUF active on RBNE */ + +/* function declarations */ +/* initialization functions */ +/* reset USART */ +void usart_deinit(uint32_t usart_periph); +/* configure USART baud rate value */ +void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval); +/* configure USART parity function */ +void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg); +/* configure USART word length */ +void usart_word_length_set(uint32_t usart_periph, uint32_t wlen); +/* configure USART stop bit length */ +void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen); +/* enable USART */ +void usart_enable(uint32_t usart_periph); +/* disable USART */ +void usart_disable(uint32_t usart_periph); +/* configure USART transmitter */ +void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig); +/* configure USART receiver */ +void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig); + +/* USART normal mode communication */ +/* data is transmitted/received with the LSB/MSB first */ +void usart_data_first_config(uint32_t usart_periph, uint32_t msbf); +/* configure USART inverted */ +void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara); +/* enable the USART overrun function */ +void usart_overrun_enable(uint32_t usart_periph); +/* disable the USART overrun function */ +void usart_overrun_disable(uint32_t usart_periph); +/* configure the USART oversample mode */ +void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp); +/* configure sample bit method */ +void usart_sample_bit_config(uint32_t usart_periph, uint32_t osb); +/* enable receiver timeout */ +void usart_receiver_timeout_enable(uint32_t usart_periph); +/* disable receiver timeout */ +void usart_receiver_timeout_disable(uint32_t usart_periph); +/* configure receiver timeout threshold */ +void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout); +/* USART transmit data function */ +void usart_data_transmit(uint32_t usart_periph, uint32_t data); +/* USART receive data function */ +uint16_t usart_data_receive(uint32_t usart_periph); + +/* auto baud rate detection */ +/* enable auto baud rate detection */ +void usart_autobaud_detection_enable(uint32_t usart_periph); +/* disable auto baud rate detection */ +void usart_autobaud_detection_disable(uint32_t usart_periph); +/* configure auto baud rate detection mode */ +void usart_autobaud_detection_mode_config(uint32_t usart_periph, uint32_t abdmod); + +/* multi-processor communication */ +/* configure the address of the USART in wake up by address match mode */ +void usart_address_config(uint32_t usart_periph, uint8_t addr); +/* configure address detection mode */ +void usart_address_detection_mode_config(uint32_t usart_periph, uint32_t addmod); +/* enable mute mode */ +void usart_mute_mode_enable(uint32_t usart_periph); +/* disable mute mode */ +void usart_mute_mode_disable(uint32_t usart_periph); +/* configure wakeup method in mute mode */ +void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod); + +/* LIN mode communication */ +/* enable LIN mode */ +void usart_lin_mode_enable(uint32_t usart_periph); +/* disable LIN mode */ +void usart_lin_mode_disable(uint32_t usart_periph); +/* configure LIN break frame length */ +void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen); + +/* half-duplex communication */ +/* enable half-duplex mode */ +void usart_halfduplex_enable(uint32_t usart_periph); +/* disable half-duplex mode */ +void usart_halfduplex_disable(uint32_t usart_periph); + +/* synchronous communication */ +/* enable USART clock */ +void usart_clock_enable(uint32_t usart_periph); +/* disable USART clock */ +void usart_clock_disable(uint32_t usart_periph); +/* configure USART synchronous mode parameters */ +void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl); + +/* smartcard communication */ +/* configure guard time value in smartcard mode */ +void usart_guard_time_config(uint32_t usart_periph, uint32_t guat); +/* enable smartcard mode */ +void usart_smartcard_mode_enable(uint32_t usart_periph); +/* disable smartcard mode */ +void usart_smartcard_mode_disable(uint32_t usart_periph); +/* enable NACK in smartcard mode */ +void usart_smartcard_mode_nack_enable(uint32_t usart_periph); +/* disable NACK in smartcard mode */ +void usart_smartcard_mode_nack_disable(uint32_t usart_periph); +/* enable early NACK in smartcard mode */ +void usart_smartcard_mode_early_nack_enable(uint32_t usart_periph); +/* disable early NACK in smartcard mode */ +void usart_smartcard_mode_early_nack_disable(uint32_t usart_periph); +/* configure smartcard auto-retry number */ +void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum); +/* configure block length */ +void usart_block_length_config(uint32_t usart_periph, uint32_t bl); + +/* IrDA communication */ +/* enable IrDA mode */ +void usart_irda_mode_enable(uint32_t usart_periph); +/* disable IrDA mode */ +void usart_irda_mode_disable(uint32_t usart_periph); +/* configure the peripheral clock prescaler in USART IrDA low-power mode or SmartCard mode */ +void usart_prescaler_config(uint32_t usart_periph, uint32_t psc); +/* configure IrDA low-power */ +void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp); + +/* hardware flow communication */ +/* configure hardware flow control RTS */ +void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig); +/* configure hardware flow control CTS */ +void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig); + +/* enable RS485 driver */ +void usart_rs485_driver_enable(uint32_t usart_periph); +/* disable RS485 driver */ +void usart_rs485_driver_disable(uint32_t usart_periph); +/* configure driver enable assertion time */ +void usart_driver_assertime_config(uint32_t usart_periph, uint32_t deatime); +/* configure driver enable de-assertion time */ +void usart_driver_deassertime_config(uint32_t usart_periph, uint32_t dedtime); +/* configure driver enable polarity mode */ +void usart_depolarity_config(uint32_t usart_periph, uint32_t dep); + +/* USART DMA */ +/* configure USART DMA for reception */ +void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd); +/* configure USART DMA for transmission */ +void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd); +/* disable DMA on reception error */ +void usart_reception_error_dma_disable(uint32_t usart_periph); +/* enable DMA on reception error */ +void usart_reception_error_dma_enable(uint32_t usart_periph); + +/* enable USART to wakeup the mcu from deep-sleep mode */ +void usart_wakeup_enable(uint32_t usart_periph); +/* disable USART to wakeup the mcu from deep-sleep mode */ +void usart_wakeup_disable(uint32_t usart_periph); +/* configure the USART wakeup mode from deep-sleep mode */ +void usart_wakeup_mode_config(uint32_t usart_periph, uint32_t wum); +/* enable USART command */ +void usart_command_enable(uint32_t usart_periph, uint32_t cmdtype); + +/* USART receive FIFO */ +/* enable receive FIFO */ +void usart_receive_fifo_enable(uint32_t usart_periph); +/* disable receive FIFO */ +void usart_receive_fifo_disable(uint32_t usart_periph); +/* read receive FIFO counter number */ +uint8_t usart_receive_fifo_counter_number(uint32_t usart_periph); + +/* flag & interrupt functions */ +/* get flag in STAT/RFCS register */ +FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag); +/* clear flag in STAT register */ +void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag); +/* enable USART interrupt */ +void usart_interrupt_enable(uint32_t usart_periph, usart_interrupt_enum interrupt); +/* disable USART interrupt */ +void usart_interrupt_disable(uint32_t usart_periph, usart_interrupt_enum interrupt); +/* get USART interrupt and flag status */ +FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_enum int_flag); +/* clear USART interrupt flag */ +void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum int_flag); + +#endif /* GD32F3X0_USART_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_wwdgt.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_wwdgt.h new file mode 100644 index 0000000000..9905fa75c1 --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_wwdgt.h @@ -0,0 +1,93 @@ +/*! + \file gd32f3x0_wwdgt.h + \brief definitions for the WWDGT + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F3X0_WWDGT_H +#define GD32F3X0_WWDGT_H + +#include "gd32f3x0.h" + +/* WWDGT definitions */ +#define WWDGT WWDGT_BASE + +/* registers definitions */ +#define WWDGT_CTL REG32(WWDGT + 0x00000000U) /*!< WWDGT control register */ +#define WWDGT_CFG REG32(WWDGT + 0x00000004U) /*!< WWDGT configuration register */ +#define WWDGT_STAT REG32(WWDGT + 0x00000008U) /*!< WWDGT status register */ + +/* bits definitions */ +/* WWDGT_CTL */ +#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */ +#define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */ + +/* WWDGT_CFG */ +#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */ +#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */ +#define WWDGT_CFG_EWIE BIT(9) /*!< WWDGT early wakeup interrupt enable */ + +/* WWDGT_STAT */ +#define WWDGT_STAT_EWIF BIT(0) /*!< WWDGT early wakeup interrupt flag */ + +/* constants definitions */ +/* WWDGT_CTL register value */ +#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U)) /*!< write value to WWDGT_CTL_CNT bit field */ + +/* WWDGT_CFG register value */ +#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U)) /*!< write value to WWDGT_CFG_WIN bit field */ + +#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7U)) /*!< write value to WWDGT_CFG_PSC bit field */ +#define WWDGT_CFG_PSC_DIV1 ((uint32_t)CFG_PSC(0)) /*!< the time base of WWDGT = (PCLK1/4096)/1 */ +#define WWDGT_CFG_PSC_DIV2 ((uint32_t)CFG_PSC(1)) /*!< the time base of WWDGT = (PCLK1/4096)/2 */ +#define WWDGT_CFG_PSC_DIV4 ((uint32_t)CFG_PSC(2)) /*!< the time base of WWDGT = (PCLK1/4096)/4 */ +#define WWDGT_CFG_PSC_DIV8 ((uint32_t)CFG_PSC(3)) /*!< the time base of WWDGT = (PCLK1/4096)/8 */ + +/* function declarations */ +/* reset the window watchdog timer configuration */ +void wwdgt_deinit(void); +/* start the window watchdog timer counter */ +void wwdgt_enable(void); + +/* configure the window watchdog timer counter value */ +void wwdgt_counter_update(uint16_t counter_value); +/* configure counter value, window value, and prescaler divider value */ +void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler); + +/* enable early wakeup interrupt of WWDGT */ +void wwdgt_interrupt_enable(void); +/* check early wakeup interrupt state of WWDGT */ +FlagStatus wwdgt_flag_get(void); +/* clear early wakeup interrupt state of WWDGT */ +void wwdgt_flag_clear(void); + +#endif /* GD32F3X0_WWDGT_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_adc.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_adc.c new file mode 100644 index 0000000000..490f3f9663 --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_adc.c @@ -0,0 +1,869 @@ +/*! + \file gd32f3x0_adc.c + \brief ADC driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f3x0_adc.h" + +/*! + \brief reset ADC + \param[in] none + \param[out] none + \retval none +*/ +void adc_deinit(void) +{ + rcu_periph_reset_enable(RCU_ADCRST); + rcu_periph_reset_disable(RCU_ADCRST); +} + +/*! + \brief enable ADC interface + \param[in] none + \param[out] none + \retval none +*/ +void adc_enable(void) +{ + if(RESET == (ADC_CTL1 & ADC_CTL1_ADCON)){ + ADC_CTL1 |= (uint32_t)ADC_CTL1_ADCON; + } +} + +/*! + \brief disable ADC interface + \param[in] none + \param[out] none + \retval none +*/ +void adc_disable(void) +{ + ADC_CTL1 &= ~((uint32_t)ADC_CTL1_ADCON); +} + +/*! + \brief ADC calibration and reset calibration + \param[in] none + \param[out] none + \retval none +*/ +void adc_calibration_enable(void) +{ + /* reset the selected ADC calibration register */ + ADC_CTL1 |= (uint32_t) ADC_CTL1_RSTCLB; + /* check the RSTCLB bit state */ + while((ADC_CTL1 & ADC_CTL1_RSTCLB)){ + } + + /* enable ADC calibration process */ + ADC_CTL1 |= ADC_CTL1_CLB; + /* check the CLB bit state */ + while((ADC_CTL1 & ADC_CTL1_CLB)){ + } +} + +/*! + \brief enable DMA request + \param[in] none + \param[out] none + \retval none +*/ +void adc_dma_mode_enable(void) +{ + ADC_CTL1 |= (uint32_t)(ADC_CTL1_DMA); +} + +/*! + \brief disable DMA request + \param[in] none + \param[out] none + \retval none +*/ +void adc_dma_mode_disable(void) +{ + ADC_CTL1 &= ~((uint32_t)ADC_CTL1_DMA); +} + +/*! + \brief enable the temperature sensor and Vrefint channel + \param[in] none + \param[out] none + \retval none +*/ +void adc_tempsensor_vrefint_enable(void) +{ + /* enable the temperature sensor and Vrefint channel */ + ADC_CTL1 |= ADC_CTL1_TSVREN; +} + +/*! + \brief disable the temperature sensor and Vrefint channel + \param[in] none + \param[out] none + \retval none +*/ +void adc_tempsensor_vrefint_disable(void) +{ + /* disable the temperature sensor and Vrefint channel */ + ADC_CTL1 &= ~ADC_CTL1_TSVREN; +} + +/*! + \brief enable the vbat channel + \param[in] none + \param[out] none + \retval none +*/ +void adc_vbat_enable(void) +{ + /* enable the vbat channel */ + ADC_CTL1 |= ADC_CTL1_VBETEN; +} + +/*! + \brief disable the vbat channel + \param[in] none + \param[out] none + \retval none +*/ +void adc_vbat_disable(void) +{ + /* disable the vbat channel */ + ADC_CTL1 &= ~ADC_CTL1_VBETEN; +} + +/*! + \brief configure ADC discontinuous mode + \param[in] channel_group: select the channel group + only one parameter can be selected which is shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \arg ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of regular and inserted channel + \param[in] length: number of conversions in discontinuous mode,the number can be 1..8 + for regular channel, the number has no effect for inserted channel + \param[out] none + \retval none +*/ +void adc_discontinuous_mode_config(uint8_t channel_group, uint8_t length) +{ + ADC_CTL0 &= ~((uint32_t)(ADC_CTL0_DISRC | ADC_CTL0_DISIC)); + + switch(channel_group){ + case ADC_REGULAR_CHANNEL: + /* configure the number of conversions in discontinuous mode */ + ADC_CTL0 &= ~((uint32_t)ADC_CTL0_DISNUM); + ADC_CTL0 |= CTL0_DISNUM(((uint32_t)length - 1U)); + ADC_CTL0 |= (uint32_t)ADC_CTL0_DISRC; + break; + case ADC_INSERTED_CHANNEL: + ADC_CTL0 |= (uint32_t)ADC_CTL0_DISIC; + break; + case ADC_CHANNEL_DISCON_DISABLE: + default: + break; + } +} + +/*! + \brief configure ADC special function + \param[in] function: the function to configure + one or more parameters can be selected which is shown as below: + \arg ADC_SCAN_MODE: scan mode select + \arg ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically + \arg ADC_CONTINUOUS_MODE: continuous mode select + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void adc_special_function_config(uint32_t function, ControlStatus newvalue) +{ + if(newvalue){ + /* enable ADC scan mode */ + if(RESET != (function & ADC_SCAN_MODE)){ + ADC_CTL0 |= ADC_SCAN_MODE; + } + /* enable ADC inserted channel group convert automatically */ + if(RESET != (function & ADC_INSERTED_CHANNEL_AUTO)){ + ADC_CTL0 |= ADC_INSERTED_CHANNEL_AUTO; + } + /* enable ADC continuous mode */ + if(RESET != (function & ADC_CONTINUOUS_MODE)){ + ADC_CTL1 |= ADC_CONTINUOUS_MODE; + } + }else{ + /* disable ADC scan mode */ + if(RESET != (function & ADC_SCAN_MODE)){ + ADC_CTL0 &= ~ADC_SCAN_MODE; + } + /* disable ADC inserted channel group convert automatically */ + if(RESET != (function & ADC_INSERTED_CHANNEL_AUTO)){ + ADC_CTL0 &= ~ADC_INSERTED_CHANNEL_AUTO; + } + /* disable ADC continuous mode */ + if(RESET != (function & ADC_CONTINUOUS_MODE)){ + ADC_CTL1 &= ~ADC_CONTINUOUS_MODE; + } + } +} + +/*! + \brief configure ADC data alignment + \param[in] data_alignment: data alignment select + only one parameter can be selected which is shown as below: + \arg ADC_DATAALIGN_RIGHT: right alignment + \arg ADC_DATAALIGN_LEFT: left alignment + \param[out] none + \retval none +*/ +void adc_data_alignment_config(uint32_t data_alignment) +{ + if(ADC_DATAALIGN_RIGHT != data_alignment){ + ADC_CTL1 |= ADC_CTL1_DAL; + }else{ + ADC_CTL1 &= ~((uint32_t)ADC_CTL1_DAL); + } +} + +/*! + \brief configure the length of regular channel group or inserted channel group + \param[in] channel_group: select the channel group + only one parameter can be selected which is shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \param[in] length: the length of the channel + regular channel 1-16 + inserted channel 1-4 + \param[out] none + \retval none +*/ +void adc_channel_length_config(uint8_t channel_group, uint32_t length) +{ + switch(channel_group){ + case ADC_REGULAR_CHANNEL: + /* configure the length of regular channel group */ + ADC_RSQ0 &= ~((uint32_t)ADC_RSQ0_RL); + ADC_RSQ0 |= RSQ0_RL((uint32_t)(length-1U)); + break; + case ADC_INSERTED_CHANNEL: + /* configure the length of inserted channel group */ + ADC_ISQ &= ~((uint32_t)ADC_ISQ_IL); + ADC_ISQ |= ISQ_IL((uint32_t)(length-1U)); + break; + default: + break; + } +} + +/*! + \brief configure ADC regular channel + \param[in] rank: the regular group sequence rank, this parameter must be between 0 to 15 + \param[in] channel: the selected ADC channel + only one parameter can be selected which is shown as below: + \arg ADC_CHANNEL_x(x=0..18): ADC Channelx + \param[in] sample_time: the sample time value + only one parameter can be selected which is shown as below: + \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles + \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles + \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles + \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles + \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles + \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles + \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles + \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles + \param[out] none + \retval none +*/ +void adc_regular_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time) +{ + uint32_t rsq,sampt; + + /* configure ADC regular sequence */ + if(rank < 6U){ + rsq = ADC_RSQ2; + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*rank))); + rsq |= ((uint32_t)channel << (5U*rank)); + ADC_RSQ2 = rsq; + }else if(rank < 12U){ + rsq = ADC_RSQ1; + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*(rank-6U)))); + rsq |= ((uint32_t)channel << (5U*(rank-6U))); + ADC_RSQ1 = rsq; + }else if(rank < 16U){ + rsq = ADC_RSQ0; + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*(rank-12U)))); + rsq |= ((uint32_t)channel << (5U*(rank-12U))); + ADC_RSQ0 = rsq; + }else{ + } + + /* configure ADC sampling time */ + if(channel < 10U){ + sampt = ADC_SAMPT1; + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*channel))); + sampt |= (uint32_t)(sample_time << (3U*channel)); + ADC_SAMPT1 = sampt; + }else if(channel < 19U){ + sampt = ADC_SAMPT0; + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*(channel-10U)))); + sampt |= (uint32_t)(sample_time << (3U*(channel-10U))); + ADC_SAMPT0 = sampt; + }else{ + /* illegal parameters */ + } +} + +/*! + \brief configure ADC inserted channel + \param[in] rank: the inserted group sequencer rank,this parameter must be between 0 to 3 + \param[in] channel: the selected ADC channel + only one parameter can be selected which is shown as below: + \arg ADC_CHANNEL_x(x=0..18): ADC Channelx + \param[in] sample_time: The sample time value + only one parameter can be selected which is shown as below: + \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles + \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles + \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles + \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles + \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles + \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles + \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles + \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles + \param[out] none + \retval none +*/ +void adc_inserted_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time) +{ + uint8_t inserted_length; + uint32_t isq,sampt; + + inserted_length = (uint8_t)GET_BITS(ADC_ISQ , 20U , 21U); + + isq = ADC_ISQ; + isq &= ~((uint32_t)(ADC_ISQ_ISQN << (15U - (inserted_length - rank)*5U))); + isq |= ((uint32_t)channel << (15U - (inserted_length - rank)*5U)); + ADC_ISQ = isq; + + /* configure ADC sampling time */ + if(channel < 10U){ + sampt = ADC_SAMPT1; + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*channel))); + sampt |= (uint32_t) sample_time << (3U*channel); + ADC_SAMPT1 = sampt; + }else if(channel < 19U){ + sampt = ADC_SAMPT0; + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*(channel - 10U)))); + sampt |= ((uint32_t)sample_time << (3U*(channel - 10U))); + ADC_SAMPT0 = sampt; + }else{ + /* illegal parameters */ + } +} + +/*! + \brief configure ADC inserted channel offset + \param[in] inserted_channel: insert channel select + only one parameter can be selected which is shown as below: + \arg ADC_INSERTED_CHANNEL_0: ADC inserted channel 0 + \arg ADC_INSERTED_CHANNEL_1: ADC inserted channel 1 + \arg ADC_INSERTED_CHANNEL_2: ADC inserted channel 2 + \arg ADC_INSERTED_CHANNEL_3: ADC inserted channel 3 + \param[in] offset: the offset data + \param[out] none + \retval none +*/ +void adc_inserted_channel_offset_config(uint8_t inserted_channel, uint16_t offset) +{ + uint8_t inserted_length; + uint32_t num = 0U; + + inserted_length = (uint8_t)GET_BITS(ADC_ISQ, 20U, 21U); + num = 3U - (inserted_length - inserted_channel); + + if(num <= 3U){ + /* calculate the offset of the register */ + num = num * 4U; + /* configure the offset of the selected channels */ + REG32((ADC) + 0x14U + num) = IOFFX_IOFF((uint32_t)offset); + } +} + +/*! + \brief enable or disable ADC external trigger + \param[in] channel_group: select the channel group + one or more parameters can be selected which is shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void adc_external_trigger_config(uint8_t channel_group, ControlStatus newvalue) +{ + if(newvalue){ + /* external trigger enable for regular channel */ + if(RESET != (channel_group & ADC_REGULAR_CHANNEL)){ + ADC_CTL1 |= ADC_CTL1_ETERC; + } + /* external trigger enable for inserted channel */ + if(RESET != (channel_group & ADC_INSERTED_CHANNEL)){ + ADC_CTL1 |= ADC_CTL1_ETEIC; + } + }else{ + /* external trigger disable for regular channel */ + if(RESET != (channel_group & ADC_REGULAR_CHANNEL)){ + ADC_CTL1 &= ~ADC_CTL1_ETERC; + } + /* external trigger disable for inserted channel */ + if(RESET != (channel_group & ADC_INSERTED_CHANNEL)){ + ADC_CTL1 &= ~ADC_CTL1_ETEIC; + } + } +} + +/*! + \brief configure ADC external trigger source + \param[in] channel_group: select the channel group + only one parameter can be selected which is shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \param[in] external_trigger_source: regular or inserted group trigger source + only one parameter can be selected which is shown as below: + for regular channel: + \arg ADC_EXTTRIG_REGULAR_T0_CH0: TIMER0 CH0 event select + \arg ADC_EXTTRIG_REGULAR_T0_CH1: TIMER0 CH1 event select + \arg ADC_EXTTRIG_REGULAR_T0_CH2: TIMER0 CH2 event select + \arg ADC_EXTTRIG_REGULAR_T1_CH1: TIMER1 CH1 event select + \arg ADC_EXTTRIG_REGULAR_T2_TRGO: TIMER2 TRGO event select + \arg ADC_EXTTRIG_REGULAR_T14_CH0: TIMER14 CH0 event select + \arg ADC_EXTTRIG_REGULAR_EXTI_11: external interrupt line 11 + \arg ADC_EXTTRIG_REGULAR_NONE: software trigger + for inserted channel: + \arg ADC_EXTTRIG_INSERTED_T0_TRGO: TIMER0 TRGO event select + \arg ADC_EXTTRIG_INSERTED_T0_CH3: TIMER0 CH3 event select + \arg ADC_EXTTRIG_INSERTED_T1_TRGO: TIMER1 TRGO event select + \arg ADC_EXTTRIG_INSERTED_T1_CH0: TIMER1 CH0 event select + \arg ADC_EXTTRIG_INSERTED_T2_CH3: TIMER2 CH3 event select + \arg ADC_EXTTRIG_INSERTED_T14_TRGO: TIMER14 TRGO event select + \arg ADC_EXTTRIG_INSERTED_EXTI_15: external interrupt line 15 + \arg ADC_EXTTRIG_INSERTED_NONE: software trigger + \param[out] none + \retval none +*/ +void adc_external_trigger_source_config(uint8_t channel_group, uint32_t external_trigger_source) +{ + switch(channel_group){ + case ADC_REGULAR_CHANNEL: + /* external trigger select for regular channel */ + ADC_CTL1 &= ~((uint32_t)ADC_CTL1_ETSRC); + ADC_CTL1 |= (uint32_t)external_trigger_source; + break; + case ADC_INSERTED_CHANNEL: + /* external trigger select for inserted channel */ + ADC_CTL1 &= ~((uint32_t)ADC_CTL1_ETSIC); + ADC_CTL1 |= (uint32_t)external_trigger_source; + break; + default: + break; + } +} + +/*! + \brief enable ADC software trigger + \param[in] channel_group: select the channel group + one or more parameters can be selected which is shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \param[out] none + \retval none +*/ +void adc_software_trigger_enable(uint8_t channel_group) +{ + /* enable regular group channel software trigger */ + if(RESET != (channel_group & ADC_REGULAR_CHANNEL)){ + ADC_CTL1 |= ADC_CTL1_SWRCST; + } + /* enable inserted channel group software trigger */ + if(RESET != (channel_group & ADC_INSERTED_CHANNEL)){ + ADC_CTL1 |= ADC_CTL1_SWICST; + } +} + +/*! + \brief read ADC regular group data register + \param[in] none + \param[out] none + \retval the conversion value +*/ +uint16_t adc_regular_data_read(void) +{ + return ((uint16_t)ADC_RDATA); +} + +/*! + \brief read ADC inserted group data register + \param[in] inserted_channel: inserted channel select + only one parameter can be selected which is shown as below: + \arg ADC_INSERTED_CHANNEL_0: ADC inserted channel 0 + \arg ADC_INSERTED_CHANNEL_1: ADC inserted channel 1 + \arg ADC_INSERTED_CHANNEL_2: ADC inserted channel 2 + \arg ADC_INSERTED_CHANNEL_3: ADC inserted channel 3 + \param[out] none + \retval the conversion value +*/ +uint16_t adc_inserted_data_read(uint8_t inserted_channel) +{ + uint32_t idata; + /* read the data of the selected channel */ + switch(inserted_channel){ + case ADC_INSERTED_CHANNEL_0: + idata = ADC_IDATA0; + break; + case ADC_INSERTED_CHANNEL_1: + idata = ADC_IDATA1; + break; + case ADC_INSERTED_CHANNEL_2: + idata = ADC_IDATA2; + break; + case ADC_INSERTED_CHANNEL_3: + idata = ADC_IDATA3; + break; + default: + idata = 0U; + break; + } + return (uint16_t)idata; +} + +/*! + \brief get the ADC flag bits + \param[in] flag: the adc flag bits + only one parameter can be selected which is shown as below: + \arg ADC_FLAG_WDE: analog watchdog event flag + \arg ADC_FLAG_EOC: end of group conversion flag + \arg ADC_FLAG_EOIC: end of inserted group conversion flag + \arg ADC_FLAG_STIC: start flag of inserted channel group + \arg ADC_FLAG_STRC: start flag of regular channel group + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus adc_flag_get(uint32_t flag) +{ + FlagStatus reval = RESET; + + if(ADC_STAT & flag){ + reval = SET; + } + return reval; +} + +/*! + \brief clear the ADC flag + \param[in] flag: the adc flag + one or more parameters can be selected which is shown as below: + \arg ADC_FLAG_WDE: analog watchdog event flag + \arg ADC_FLAG_EOC: end of group conversion flag + \arg ADC_FLAG_EOIC: end of inserted group conversion flag + \arg ADC_FLAG_STIC: start flag of inserted channel group + \arg ADC_FLAG_STRC: start flag of regular channel group + \param[out] none + \retval none +*/ +void adc_flag_clear(uint32_t flag) +{ + ADC_STAT &= ~((uint32_t)flag); +} + +/*! + \brief get the ADC interrupt flag + \param[in] flag: the adc interrupt flag + only one parameter can be selected which is shown as below: + \arg ADC_INT_FLAG_WDE: analog watchdog interrupt flag + \arg ADC_INT_FLAG_EOC: end of group conversion interrupt flag + \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus adc_interrupt_flag_get(uint32_t flag) +{ + FlagStatus interrupt_flag = RESET; + uint32_t state; + + /* check the interrupt bits */ + switch(flag){ + case ADC_INT_FLAG_WDE: + state = ADC_STAT & ADC_STAT_WDE; + if((ADC_CTL0 & ADC_CTL0_WDEIE) && state){ + interrupt_flag = SET; + } + break; + case ADC_INT_FLAG_EOC: + state = ADC_STAT & ADC_STAT_EOC; + if((ADC_CTL0 & ADC_CTL0_EOCIE) && state){ + interrupt_flag = SET; + } + break; + case ADC_INT_FLAG_EOIC: + state = ADC_STAT & ADC_STAT_EOIC; + if((ADC_CTL0 & ADC_CTL0_EOICIE) && state){ + interrupt_flag = SET; + } + break; + default: + break; + } + return interrupt_flag; +} + +/*! + \brief clear ADC interrupt flag + \param[in] flag: the adc interrupt flag + only one parameter can be selected which is shown as below: + \arg ADC_INT_FLAG_WDE: analog watchdog interrupt flag + \arg ADC_INT_FLAG_EOC: end of group conversion interrupt flag + \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt flag + \param[out] none + \retval none +*/ +void adc_interrupt_flag_clear(uint32_t flag) +{ + ADC_STAT &= ~((uint32_t)flag); +} + +/*! + \brief enable ADC interrupt + \param[in] interrupt: the adc interrupt + one or more parameters can be selected which is shown as below: + \arg ADC_INT_WDE: analog watchdog interrupt + \arg ADC_INT_EOC: end of group conversion interrupt + \arg ADC_INT_EOIC: end of inserted group conversion interrupt + \param[out] none + \retval none +*/ +void adc_interrupt_enable(uint32_t interrupt) +{ + /* enable analog watchdog interrupt */ + if(RESET != (interrupt & ADC_INT_WDE)){ + ADC_CTL0 |= (uint32_t)ADC_CTL0_WDEIE; + } + + /* enable end of group conversion interrupt */ + if(RESET != (interrupt & ADC_INT_EOC)){ + ADC_CTL0 |= (uint32_t)ADC_CTL0_EOCIE; + } + + /* enable end of inserted group conversion interrupt */ + if(RESET != (interrupt & ADC_INT_EOIC)){ + ADC_CTL0 |= (uint32_t)ADC_CTL0_EOICIE; + } +} + +/*! + \brief disable ADC interrupt + \param[in] interrupt: the adc interrupt flag + one or more parameters can be selected which is shown as below: + \arg ADC_INT_WDE: analog watchdog interrupt + \arg ADC_INT_EOC: end of group conversion interrupt + \arg ADC_INT_EOIC: end of inserted group conversion interrupt + \param[out] none + \retval none +*/ +void adc_interrupt_disable(uint32_t interrupt) +{ + /* disable analog watchdog interrupt */ + if(RESET != (interrupt & ADC_INT_WDE)){ + ADC_CTL0 &= ~(uint32_t)ADC_CTL0_WDEIE; + } + + /* disable end of group conversion interrupt */ + if(RESET != (interrupt & ADC_INT_EOC)){ + ADC_CTL0 &= ~(uint32_t)ADC_CTL0_EOCIE; + } + + /* disable end of inserted group conversion interrupt */ + if(RESET != (interrupt & ADC_INT_EOIC)){ + ADC_CTL0 &= ~(uint32_t)ADC_CTL0_EOICIE; + } +} + +/*! + \brief configure ADC analog watchdog single channel + \param[in] channel: the selected ADC channel + only one parameter can be selected which is shown as below: + \arg ADC_CHANNEL_x(x=0..18): ADC Channelx + \param[out] none + \retval none +*/ +void adc_watchdog_single_channel_enable(uint8_t channel) +{ + ADC_CTL0 &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL); + + ADC_CTL0 |= (uint32_t)channel; + ADC_CTL0 |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC); +} + +/*! + \brief configure ADC analog watchdog group channel + \param[in] channel_group: the channel group use analog watchdog + only one parameter can be selected which is shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group + \param[out] none + \retval none +*/ +void adc_watchdog_group_channel_enable(uint8_t channel_group) +{ + ADC_CTL0 &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC); + + /* select the group */ + switch(channel_group){ + case ADC_REGULAR_CHANNEL: + ADC_CTL0 |= (uint32_t)ADC_CTL0_RWDEN; + break; + case ADC_INSERTED_CHANNEL: + ADC_CTL0 |= (uint32_t)ADC_CTL0_IWDEN; + break; + case ADC_REGULAR_INSERTED_CHANNEL: + ADC_CTL0 |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN); + break; + default: + break; + } +} + +/*! + \brief disable ADC analog watchdog + \param[in] none + \param[out] none + \retval none +*/ +void adc_watchdog_disable(void) +{ + ADC_CTL0 &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL); +} + +/*! + \brief configure ADC analog watchdog threshold + \param[in] low_threshold: analog watchdog low threshold,0..4095 + \param[in] high_threshold: analog watchdog high threshold,0..4095 + \param[out] none + \retval none +*/ +void adc_watchdog_threshold_config(uint16_t low_threshold, uint16_t high_threshold) +{ + ADC_WDLT = (uint32_t)WDLT_WDLT(low_threshold); + ADC_WDHT = (uint32_t)WDHT_WDHT(high_threshold); +} + +/*! + \brief configure ADC resolution + \param[in] resolution: ADC resolution + only one parameter can be selected which is shown as below: + \arg ADC_RESOLUTION_12B: 12-bit ADC resolution + \arg ADC_RESOLUTION_10B: 10-bit ADC resolution + \arg ADC_RESOLUTION_8B: 8-bit ADC resolution + \arg ADC_RESOLUTION_6B: 6-bit ADC resolution + \param[out] none + \retval none +*/ +void adc_resolution_config(uint32_t resolution) +{ + ADC_CTL0 &= ~((uint32_t)ADC_CTL0_DRES); + ADC_CTL0 |= (uint32_t)resolution; +} + +/*! + \brief configure ADC oversample mode + \param[in] mode: ADC oversampling mode + only one parameter can be selected which is shown as below: + \arg ADC_OVERSAMPLING_ALL_CONVERT: all oversampled conversions for a channel are done consecutively after a trigger + \arg ADC_OVERSAMPLING_ONE_CONVERT: each oversampled conversion for a channel needs a trigger + \param[in] shift: ADC oversampling shift + only one parameter can be selected which is shown as below: + \arg ADC_OVERSAMPLING_SHIFT_NONE: no oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_1B: 1-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_2B: 2-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_3B: 3-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_4B: 3-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_5B: 5-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_6B: 6-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_7B: 7-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_8B: 8-bit oversampling shift + \param[in] ratio: ADC oversampling ratio + only one parameter can be selected which is shown as below: + \arg ADC_OVERSAMPLING_RATIO_MUL2: oversampling ratio multiple 2 + \arg ADC_OVERSAMPLING_RATIO_MUL4: oversampling ratio multiple 4 + \arg ADC_OVERSAMPLING_RATIO_MUL8: oversampling ratio multiple 8 + \arg ADC_OVERSAMPLING_RATIO_MUL16: oversampling ratio multiple 16 + \arg ADC_OVERSAMPLING_RATIO_MUL32: oversampling ratio multiple 32 + \arg ADC_OVERSAMPLING_RATIO_MUL64: oversampling ratio multiple 64 + \arg ADC_OVERSAMPLING_RATIO_MUL128: oversampling ratio multiple 128 + \arg ADC_OVERSAMPLING_RATIO_MUL256: oversampling ratio multiple 256 + \param[out] none + \retval none +*/ +void adc_oversample_mode_config(uint8_t mode, uint16_t shift, uint8_t ratio) +{ + /* configure ADC oversampling mode */ + if(ADC_OVERSAMPLING_ONE_CONVERT == mode){ + ADC_OVSAMPCTL |= (uint32_t)ADC_OVSAMPCTL_TOVS; + }else{ + ADC_OVSAMPCTL &= ~((uint32_t)ADC_OVSAMPCTL_TOVS); + } + + /* configure the shift and ratio */ + ADC_OVSAMPCTL &= ~((uint32_t)(ADC_OVSAMPCTL_OVSR | ADC_OVSAMPCTL_OVSS)); + ADC_OVSAMPCTL |= ((uint32_t)shift | (uint32_t)ratio); +} + +/*! + \brief enable ADC oversample mode + \param[in] none + \param[out] none + \retval none +*/ +void adc_oversample_mode_enable(void) +{ + ADC_OVSAMPCTL |= ADC_OVSAMPCTL_OVSEN; +} + +/*! + \brief disable ADC oversample mode + \param[in] none + \param[out] none + \retval none +*/ +void adc_oversample_mode_disable(void) +{ + ADC_OVSAMPCTL &= ~((uint32_t)ADC_OVSAMPCTL_OVSEN); +} diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_cec.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_cec.c new file mode 100644 index 0000000000..42b0d50253 --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_cec.c @@ -0,0 +1,499 @@ +/*! + \file gd32f3x0_cec.c + \brief CEC driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifdef GD32F350 + +#include "gd32f3x0_cec.h" + +/*! + \brief reset HDMI-CEC controller + \param[in] none + \param[out] none + \retval none +*/ +void cec_deinit(void) +{ + rcu_periph_reset_enable(RCU_CECRST); + rcu_periph_reset_disable(RCU_CECRST); +} + +/*! + \brief configure signal free time,the signal free time counter start option,own address + \param[in] sftmopt: signal free time counter start option + only one parameter can be selected which is shown as below: + \arg CEC_SFT_START_STAOM: signal free time counter starts counting when STAOM is asserted + \arg CEC_SFT_START_LAST: signal free time counter starts automatically after transmission/reception end + \param[in] sft: signal free time + only one parameter can be selected which is shown as below: + \arg CEC_SFT_PROTOCOL_PERIOD: the signal free time will perform as HDMI-CEC protocol description + \arg CEC_SFT_1POINT5_PERIOD: 1.5 nominal data bit periods + \arg CEC_SFT_2POINT5_PERIOD: 2.5 nominal data bit periods + \arg CEC_SFT_3POINT5_PERIOD: 3.5 nominal data bit periods + \arg CEC_SFT_4POINT5_PERIOD: 4.5 nominal data bit periods + \arg CEC_SFT_5POINT5_PERIOD: 5.5 nominal data bit periods + \arg CEC_SFT_6POINT5_PERIOD: 6.5 nominal data bit periods + \arg CEC_SFT_7POINT5_PERIOD: 7.5 nominal data bit periods + \param[in] address: own address + only one parameter can be selected which is shown as below: + \arg CEC_OWN_ADDRESS_CLEAR: own address is cleared + \arg CEC_OWN_ADDRESSx(x=0..14): own address is x + \param[out] none + \retval none +*/ +void cec_init(uint32_t sftmopt, uint32_t sft, uint32_t address) +{ + uint32_t cfg; + cfg = CEC_CFG; + /* clear SFTMOPT bit,SFT[2:0] */ + cfg &= ~(CEC_CFG_SFTOPT | CEC_CFG_SFT); + /* assign SFTMOPT bit,SFT[2:0] */ + cfg |= (sftmopt | sft); + CEC_CFG = cfg; + if(CEC_OWN_ADDRESS_CLEAR == address){ + CEC_CFG &= ~CEC_CFG_OWN_ADDRESS; + }else{ + CEC_CFG |= address; + } +} + +/*! + \brief configure generate Error-bit when detected some abnormal situation or not, + whether stop receive message when detected bit rising error + \param[in] broadcast: + only one parameter can be selected which is shown as below: + \arg CEC_BROADCAST_ERROR_BIT_ON:generate Error-bit in broadcast + \arg CEC_BROADCAST_ERROR_BIT_OFF:do not generate Error-bit in broadcast + \param[in] singlecast_lbpe: + only one parameter can be selected which is shown as below: + \arg CEC_LONG_PERIOD_ERROR_BIT_ON:generate Error-bit on long bit period error + \arg CEC_LONG_PERIOD_ERROR_BIT_OFF:do not generate Error-bit on long bit period error + \param[in] singlecast_bre: + only one parameter can be selected which is shown as below: + \arg CEC_RISING_PERIOD_ERROR_BIT_ON:generate Error-bit on bit rising error + \arg CEC_RISING_PERIOD_ERROR_BIT_OFF:do not generate Error-bit on bit rising error + \param[in] rxbrestp: + only one parameter can be selected which is shown as below: + \arg CEC_STOP_RISING_ERROR_BIT_ON: stop reception when detected bit rising error + \arg CEC_STOP_RISING_ERROR_BIT_OFF: do not stop reception when detected bit rising error + \param[out] none + \retval none +*/ +void cec_error_config(uint32_t broadcast, uint32_t singlecast_lbpe, uint32_t singlecast_bre, uint32_t rxbrestp) +{ + uint32_t cfg; + cfg = CEC_CFG; + /* clear BCNG bit, BPLEG bit, BREG bit */ + cfg &= ~(CEC_CFG_BCNG | CEC_CFG_BPLEG | CEC_CFG_BREG); + /* assign BCNG bit, BPLEG bit, BREG bit */ + cfg |= (broadcast | singlecast_lbpe | singlecast_bre); + CEC_CFG = cfg; + if(CEC_STOP_RISING_ERROR_BIT_ON == rxbrestp){ + CEC_CFG |= CEC_CFG_BRES; + }else{ + CEC_CFG &= ~CEC_CFG_BRES; + } +} + +/*! + \brief enable HDMI-CEC controller + \param[in] none + \param[out] none + \retval none +*/ +void cec_enable(void) +{ + CEC_CTL |= CEC_CTL_CECEN; +} + +/*! + \brief disable HDMI-CEC controller + \param[in] none + \param[out] none + \retval none +*/ +void cec_disable(void) +{ + CEC_CTL &= ~CEC_CTL_CECEN; +} + +/*! + \brief start CEC message transmission + \param[in] none + \param[out] none + \retval none +*/ +void cec_transmission_start(void) +{ + CEC_CTL |= CEC_CTL_STAOM; +} + +/*! + \brief end CEC message transmission + \param[in] none + \param[out] none + \retval none +*/ +void cec_transmission_end(void) +{ + CEC_CTL |= CEC_CTL_ENDOM; +} + +/*! + \brief enable CEC listen mode. + \param[in] none + \param[out] none + \retval none +*/ +void cec_listen_mode_enable(void) +{ + CEC_CFG |= CEC_CFG_LMEN; +} + +/*! + \brief disable CEC listen mode. + \param[in] none + \param[out] none + \retval none +*/ +void cec_listen_mode_disable(void) +{ + CEC_CFG &= ~CEC_CFG_LMEN; +} + +/*! + \brief configure and clear own address.the controller can be configured to multiple own address + \param[in] address: own address + one or more parameters can be selected which are shown as below: + \arg CEC_OWN_ADDRESS_CLEAR: own address is cleared + \arg CEC_OWN_ADDRESSx(x=0..14): own address is x + \param[out] none + \retval none +*/ +void cec_own_address_config(uint32_t address) +{ + if(CEC_OWN_ADDRESS_CLEAR == address){ + CEC_CFG &= ~CEC_CFG_OWN_ADDRESS; + } else { + CEC_CFG |= address; + } +} + +/*! + \brief configure signal free time and the signal free time counter start option + \param[in] sftmopt: signal free time counter start option + only one parameter can be selected which is shown as below: + \arg CEC_SFT_START_STAOM: signal free time counter starts counting when STAOM is asserted + \arg CEC_SFT_START_LAST: signal free time counter starts automatically after transmission/reception end + \param[in] sft: signal free time + only one parameter can be selected which is shown as below: + \arg CEC_SFT_PROTOCOL_PERIOD: the signal free time will perform as HDMI-CEC protocol description + \arg CEC_SFT_1POINT5_PERIOD: 1.5 nominal data bit periods + \arg CEC_SFT_2POINT5_PERIOD: 2.5 nominal data bit periods + \arg CEC_SFT_3POINT5_PERIOD: 3.5 nominal data bit periods + \arg CEC_SFT_4POINT5_PERIOD: 4.5 nominal data bit periods + \arg CEC_SFT_5POINT5_PERIOD: 5.5 nominal data bit periods + \arg CEC_SFT_6POINT5_PERIOD: 6.5 nominal data bit periods + \arg CEC_SFT_7POINT5_PERIOD: 7.5 nominal data bit periods + \param[out] none + \retval none +*/ +void cec_sft_config(uint32_t sftmopt, uint32_t sft) +{ + uint32_t cfg; + cfg = CEC_CFG; + /* clear SFTMOPT bit,SFT[2:0] */ + cfg &= ~(CEC_CFG_SFTOPT | CEC_CFG_SFT); + /* assign SFTMOPT bit,SFT[2:0] */ + cfg |= (sftmopt | sft); + CEC_CFG = cfg; +} + +/*! + \brief configure generate Error-bit when detected some abnormal situation or not + \param[in] broadcast: + only one parameter can be selected which is shown as below: + \arg CEC_BROADCAST_ERROR_BIT_ON:generate Error-bit in broadcast + \arg CEC_BROADCAST_ERROR_BIT_OFF:do not generate Error-bit in broadcast + \param[in] singlecast_lbpe: + only one parameter can be selected which is shown as below: + \arg CEC_LONG_PERIOD_ERROR_BIT_ON:generate Error-bit on long bit period error + \arg CEC_LONG_PERIOD_ERROR_BIT_OFF:do not generate Error-bit on long bit period error + \param[in] singlecast_bre: + only one parameter can be selected which is shown as below: + \arg CEC_RISING_PERIOD_ERROR_BIT_ON:generate Error-bit on bit rising error + \arg CEC_RISING_PERIOD_ERROR_BIT_OFF:do not generate Error-bit on bit rising error + \param[out] none + \retval none +*/ +void cec_generate_errorbit_config(uint32_t broadcast, uint32_t singlecast_lbpe, uint32_t singlecast_bre) +{ + uint32_t cfg; + cfg = CEC_CFG; + /* clear BCNG bit, RLBPEGEN bit, RBREGEN bit */ + cfg &= ~(CEC_CFG_BCNG | CEC_CFG_BPLEG | CEC_CFG_BREG); + /* assign BCNG bit, RLBPEGEN bit, RBREGEN bit */ + cfg |= (broadcast | singlecast_lbpe | singlecast_bre); + CEC_CFG = cfg; +} + +/*! + \brief whether stop receive message when detected bit rising error + \param[in] rxbrestp: + only one parameter can be selected which is shown as below: + \arg CEC_STOP_RISING_ERROR_BIT_ON: stop reception when detected bit rising error + \arg CEC_STOP_RISING_ERROR_BIT_OFF: do not stop reception when detected bit rising error + \param[out] none + \retval none +*/ +void cec_stop_receive_bre_config(uint32_t rxbrestp) +{ + if(CEC_STOP_RISING_ERROR_BIT_ON == rxbrestp){ + CEC_CFG |= CEC_CFG_BRES; + } else { + CEC_CFG &= ~CEC_CFG_BRES; + } +} + +/*! + \brief enable reception bit timing tolerance + \param[in] none + \param[out] none + \retval none +*/ +void cec_reception_tolerance_enable(void) +{ + CEC_CFG |= CEC_CFG_RTOL; +} + +/*! + \brief disable reception bit timing tolerance + \param[in] none + \param[out] none + \retval none +*/ +void cec_reception_tolerance_disable(void) +{ + CEC_CFG &= ~CEC_CFG_RTOL; +} + +/*! + \brief send a data by the CEC peripheral + \param[in] data: the data to transmit + \param[out] none + \retval none +*/ +void cec_data_send(uint8_t data) +{ + CEC_TDATA = (uint32_t)data; +} + +/*! + \brief receive a data by the CEC peripheral + \param[in] data: the data to receive + \param[out] none + \retval none +*/ +uint8_t cec_data_receive(void) +{ + return (uint8_t)CEC_RDATA; +} + + +/*! + \brief enable interrupt + \param[in] flag: specify which flag + one or more parameters can be selected which are shown as below: + \arg CEC_INT_BR: enable Rx-byte data received interrupt + \arg CEC_INT_REND: enable end of reception interrupt + \arg CEC_INT_RO: enable RX overrun interrupt + \arg CEC_INT_BRE: enable bit rising error interrupt + \arg CEC_INT_BPSE: enable short bit period error interrupt + \arg CEC_INT_BPLE: enable long bit period error interrupt + \arg CEC_INT_RAE: enable Rx ACK error interrupt + \arg CEC_INT_ARBF: enable arbitration lost interrupt + \arg CEC_INT_TBR: enable Tx-byte data request interrupt + \arg CEC_INT_TEND: enable transmission successfully end interrupt + \arg CEC_INT_TU: enable Tx data buffer underrun interrupt + \arg CEC_INT_TERR: enable Tx-error interrupt + \arg CEC_INT_TAERR: enable Tx ACK error interrupt + \param[out] none + \retval none +*/ +void cec_interrupt_enable(uint32_t flag) +{ + CEC_INTEN |= flag; +} + +/*! + \brief disable interrupt + \param[in] flag: specify which flag + one or more parameters can be selected which are shown as below: + \arg CEC_INT_BR: disable Rx-byte data received interrupt + \arg CEC_INT_REND: disable end of reception interrupt + \arg CEC_INT_RO: disable RX overrun interrupt + \arg CEC_INT_BRE: disable bit rising error interrupt + \arg CEC_INT_BPSE: disable short bit period error interrupt + \arg CEC_INT_BPLE: disable long bit period error interrupt + \arg CEC_INT_RAE: disable Rx ACK error interrupt + \arg CEC_INT_ARBF: disable arbitration lost interrupt + \arg CEC_INT_TBR: disable Tx-byte data request interrupt + \arg CEC_INT_TEND: disable transmission successfully end interrupt + \arg CEC_INT_TU: disable Tx data buffer underrun interrupt + \arg CEC_INT_TERR: disable Tx-error interrupt + \arg CEC_INT_TAERR: disable Tx ACK error interrupt + + \param[out] none + \retval none +*/ +void cec_interrupt_disable(uint32_t flag) +{ + CEC_INTEN &= ~flag; +} + + +/*! + \brief get CEC status + \param[in] flag: specify which flag + one or more parameters can be selected which are shown as below: + \arg CEC_FLAG_BR: Rx-byte data received + \arg CEC_FLAG_REND: end of reception + \arg CEC_FLAG_RO: RX overrun + \arg CEC_FLAG_BRE: bit rising error + \arg CEC_FLAG_BPSE: short bit period error + \arg CEC_FLAG_BPLE: long bit period error + \arg CEC_FLAG_RAE: Rx ACK error + \arg CEC_FLAG_ARBF: arbitration lost + \arg CEC_FLAG_TBR: Tx-byte data request + \arg CEC_FLAG_TEND: transmission successfully end + \arg CEC_FLAG_TU: Tx data buffer underrun + \arg CEC_FLAG_TERR: Tx-error + \arg CEC_FLAG_TAERR Tx ACK error flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus cec_flag_get(uint32_t flag) +{ + if(CEC_INTF & flag){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear CEC status + \param[in] flag: specify which flag + one or more parameters can be selected which are shown as below: + \arg CEC_FLAG_BR: Rx-byte data received + \arg CEC_FLAG_REND: end of reception + \arg CEC_FLAG_RO: RX overrun + \arg CEC_FLAG_BRE: bit rising error + \arg CEC_FLAG_BPSE: short bit period error + \arg CEC_FLAG_BPLE: long bit period error + \arg CEC_FLAG_RAE: Rx ACK error + \arg CEC_FLAG_ARBF: arbitration lost + \arg CEC_FLAG_TBR: Tx-byte data request + \arg CEC_FLAG_TEND: transmission successfully end + \arg CEC_FLAG_TU: Tx data buffer underrun + \arg CEC_FLAG_TERR: Tx-error + \arg CEC_FLAG_TAERR: Tx ACK error flag + + \param[out] none + \retval FlagStatus: SET or RESET +*/ +void cec_flag_clear(uint32_t flag) +{ + CEC_INTF |= flag; +} + +/*! + \brief get CEC int flag and status + \param[in] flag: specify which flag + one or more parameters can be selected which are shown as below: + \arg CEC_INT_FLAG_BR: Rx-byte data received + \arg CEC_INT_FLAG_REND: end of reception + \arg CEC_INT_FLAG_RO: RX overrun + \arg CEC_INT_FLAG_BRE: bit rising error + \arg CEC_INT_FLAG_BPSE: short bit period error + \arg CEC_INT_FLAG_BPLE: long bit period error + \arg CEC_INT_FLAG_RAE: Rx ACK error + \arg CEC_INT_FLAG_ARBF: arbitration lost + \arg CEC_INT_FLAG_TBR: Tx-byte data request + \arg CEC_INT_FLAG_TEND: transmission successfully end + \arg CEC_INT_FLAG_TU: Tx data buffer underrun + \arg CEC_INT_FLAG_TERR: Tx-error + \arg CEC_INT_FLAG_TAERR: Tx ACK error flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus cec_interrupt_flag_get(uint32_t flag) +{ + uint32_t interrupt_enable = 0U,interrupt_flag = 0U; + interrupt_flag = (CEC_INTF & flag); + interrupt_enable = (CEC_INTEN & flag); + if(interrupt_flag && interrupt_enable){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear CEC int flag and status + \param[in] flag: specify which flag + one or more parameters can be selected which are shown as below: + \arg CEC_INT_FLAG_BR: Rx-byte data received + \arg CEC_INT_FLAG_REND: end of reception + \arg CEC_INT_FLAG_RO: RX overrun + \arg CEC_INT_FLAG_BRE: bit rising error + \arg CEC_INT_FLAG_BPSE: short bit period error + \arg CEC_INT_FLAG_BPLE: long bit period error + \arg CEC_INT_FLAG_RAE: Rx ACK error + \arg CEC_INT_FLAG_ARBF: arbitration lost + \arg CEC_INT_FLAG_TBR: Tx-byte data request + \arg CEC_INT_FLAG_TEND: transmission successfully end + \arg CEC_INT_FLAG_TU: Tx data buffer underrun + \arg CEC_INT_FLAG_TERR: Tx-error + \arg CEC_INT_FLAG_TAERR: Tx ACK error flag + \param[out] none + \retval none +*/ +void cec_interrupt_flag_clear(uint32_t flag) +{ + CEC_INTF = flag; +} + + +#endif diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_cmp.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_cmp.c new file mode 100644 index 0000000000..2a5d6c7922 --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_cmp.c @@ -0,0 +1,255 @@ +/*! + \file gd32f3x0_cmp.c + \brief CMP driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f3x0_cmp.h" + +/*! + \brief deinitialize comparator + \param[in] none + \param[out] none + \retval none +*/ +void cmp_deinit(void) +{ + CMP_CS = ((uint32_t)0x00000000U); +} + +/*! + \brief initialize comparator mode + \param[in] cmp_periph + \arg CMP0: comparator 0 + \arg CMP1: comparator 1 + \param[in] operating_mode + \arg CMP_HIGHSPEED: high speed mode + \arg CMP_MIDDLESPEED: medium speed mode + \arg CMP_LOWSPEED: low speed mode + \arg CMP_VERYLOWSPEED: very-low speed mode + \param[in] inverting_input + \arg CMP_1_4VREFINT: VREFINT *1/4 input + \arg CMP_1_2VREFINT: VREFINT *1/2 input + \arg CMP_3_4VREFINT: VREFINT *3/4 input + \arg CMP_VREFINT: VREFINT input + \arg CMP_DAC: PA4 (DAC) input + \arg CMP_PA5: PA5 input + \arg CMP_PA_0_2: PA0 or PA2 input + \param[in] hysteresis + \arg CMP_HYSTERESIS_NO: output no hysteresis + \arg CMP_HYSTERESIS_LOW: output low hysteresis + \arg CMP_HYSTERESIS_MIDDLE: output middle hysteresis + \arg CMP_HYSTERESIS_HIGH: output high hysteresis + \param[out] none + \retval none +*/ +void cmp_mode_init(uint32_t cmp_periph, operating_mode_enum operating_mode, inverting_input_enum inverting_input, cmp_hysteresis_enum output_hysteresis) +{ + if(CMP0 == cmp_periph){ + /* initialize comparator 0 mode */ + CMP_CS &= ~(uint32_t)(CMP_CS_CMP0M | CMP_CS_CMP0MSEL | CMP_CS_CMP0HST ); + CMP_CS |= CS_CMP0M(operating_mode) | CS_CMP0MSEL(inverting_input) | CS_CMP0HST(output_hysteresis); + }else{ + /* initialize comparator 1 mode */ + CMP_CS &= ~(uint32_t)(CMP_CS_CMP1M | CMP_CS_CMP1MSEL | CMP_CS_CMP1HST ); + CMP_CS |= CS_CMP1M(operating_mode) | CS_CMP1MSEL(inverting_input) | CS_CMP1HST(output_hysteresis); + } +} + +/*! + \brief initialize comparator output + \param[in] cmp_periph + \arg CMP0: comparator 0 + \arg CMP1: comparator 1 + \param[in] output_slection + \arg CMP_OUTPUT_NONE: output no selection + \arg CMP_OUTPUT_TIMER0BKIN: TIMER 0 break input + \arg CMP_OUTPUT_TIMER0IC0: TIMER 0 channel0 input capture + \arg CMP_OUTPUT_TIMER0OCPRECLR: TIMER 0 OCPRE_CLR input + \arg CMP_OUTPUT_TIMER1IC3: TIMER 1 channel3 input capture + \arg CMP_OUTPUT_TIMER1OCPRECLR: TIMER 1 OCPRE_CLR input + \arg CMP_OUTPUT_TIMER2IC0: TIMER 2 channel0 input capture + \arg CMP_OUTPUT_TIMER2OCPRECLR: TIMER 2 OCPRE_CLR input + \param[in] output_polarity + \arg CMP_OUTPUT_POLARITY_INVERTED: output is inverted + \arg CMP_OUTPUT_POLARITY_NOINVERTED: output is not inverted + \param[out] none + \retval none +*/ +void cmp_output_init(uint32_t cmp_periph, cmp_output_enum output_slection, uint32_t output_polarity) +{ + /* initialize comparator 0 output */ + if(CMP0 == cmp_periph){ + CMP_CS &= ~(uint32_t)CMP_CS_CMP0OSEL; + CMP_CS |= CS_CMP0OSEL(output_slection); + /* output polarity */ + if(CMP_OUTPUT_POLARITY_INVERTED == output_polarity){ + CMP_CS |= CMP_CS_CMP0PL; + }else{ + CMP_CS &= ~CMP_CS_CMP0PL; + } + }else{ + /* initialize comparator 1 output */ + CMP_CS &= ~(uint32_t)CMP_CS_CMP1OSEL; + CMP_CS |= CS_CMP1OSEL(output_slection); + /* output polarity */ + if(CMP_OUTPUT_POLARITY_INVERTED == output_polarity){ + CMP_CS |= CMP_CS_CMP1PL; + }else{ + CMP_CS &= ~CMP_CS_CMP1PL; + } + } +} + +/*! + \brief enable comparator + \param[in] cmp_periph + \arg CMP0: comparator 0 + \arg CMP1: comparator 1 + \param[out] none + \retval none +*/ +void cmp_enable(uint32_t cmp_periph) +{ + if(CMP0 == cmp_periph){ + CMP_CS |= CMP_CS_CMP0EN; + }else{ + CMP_CS |= CMP_CS_CMP1EN; + } +} + +/*! + \brief disable comparator + \param[in] cmp_periph + \arg CMP0: comparator 0 + \arg CMP1: comparator 1 + \param[out] none + \retval none +*/ +void cmp_disable(uint32_t cmp_periph) +{ + if(CMP0 == cmp_periph){ + CMP_CS &= ~CMP_CS_CMP0EN; + }else{ + CMP_CS &= ~CMP_CS_CMP1EN; + } +} + +/*! + \brief enable comparator switch + \param[in] none + \param[out] none + \retval none +*/ +void cmp_switch_enable(void) +{ + CMP_CS |= CMP_CS_CMP0SW; +} + +/*! + \brief disable comparator switch + \param[in] none + \param[out] none + \retval none +*/ +void cmp_switch_disable(void) +{ + CMP_CS &= ~CMP_CS_CMP0SW; +} + +/*! + \brief enable the window mode + \param[in] none + \param[out] none + \retval none +*/ +void cmp_window_enable(void) +{ + CMP_CS |= CMP_CS_WNDEN; +} + +/*! + \brief disable the window mode + \param[in] none + \param[out] none + \retval none +*/ +void cmp_window_disable(void) +{ + CMP_CS &= ~CMP_CS_WNDEN; +} + +/*! + \brief lock the comparator + \param[in] cmp_periph + \arg CMP0: comparator 0 + \arg CMP1: comparator 1 + \param[out] none + \retval none +*/ +void cmp_lock_enable(uint32_t cmp_periph) +{ + if(CMP0 == cmp_periph){ + /* lock CMP0 */ + CMP_CS |= CMP_CS_CMP0LK; + }else{ + /* lock CMP1 */ + CMP_CS |= CMP_CS_CMP1LK; + } +} + +/*! + \brief get output level + \param[in] cmp_periph + \arg CMP0: comparator 0 + \arg CMP1: comparator 1 + \param[out] none + \retval the output level +*/ +uint32_t cmp_output_level_get(uint32_t cmp_periph) +{ + if(CMP0 == cmp_periph){ + /* get output level of CMP0 */ + if(CMP_CS & CMP_CS_CMP0O){ + return CMP_OUTPUTLEVEL_HIGH; + }else{ + return CMP_OUTPUTLEVEL_LOW; + } + }else{ + /* get output level of CMP1 */ + if(CMP_CS & CMP_CS_CMP1O){ + return CMP_OUTPUTLEVEL_HIGH; + }else{ + return CMP_OUTPUTLEVEL_LOW; + } + } +} diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_crc.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_crc.c new file mode 100644 index 0000000000..4166723b28 --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_crc.c @@ -0,0 +1,207 @@ +/*! + \file gd32f3x0_crc.c + \brief CRC driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f3x0_crc.h" + +/*! + \brief deinit CRC calculation unit + \param[in] none + \param[out] none + \retval none +*/ +void crc_deinit(void) +{ + CRC_IDATA = (uint32_t)0xFFFFFFFFU; + CRC_DATA = (uint32_t)0xFFFFFFFFU; + CRC_FDATA = (uint32_t)0x00000000U; + CRC_POLY = (uint32_t)0x04C11DB7U; + CRC_CTL = CRC_CTL_RST; +} + +/*! + \brief enable the reverse operation of output data + \param[in] none + \param[out] none + \retval none +*/ +void crc_reverse_output_data_enable(void) +{ + CRC_CTL &= (uint32_t)(~ CRC_CTL_REV_O); + CRC_CTL |= (uint32_t)CRC_CTL_REV_O; +} + +/*! + \brief disable the reverse operation of output data + \param[in] none + \param[out] none + \retval none +*/ +void crc_reverse_output_data_disable(void) +{ + CRC_CTL &= (uint32_t)(~ CRC_CTL_REV_O); +} + +/*! + \brief reset data register to the value of initializaiton data register + \param[in] none + \param[out] none + \retval none +*/ +void crc_data_register_reset(void) +{ + CRC_CTL |= (uint32_t)CRC_CTL_RST; +} + +/*! + \brief read the data register + \param[in] none + \param[out] none + \retval 32-bit value of the data register +*/ +uint32_t crc_data_register_read(void) +{ + uint32_t data; + data = CRC_DATA; + return (data); +} + +/*! + \brief read the free data register + \param[in] none + \param[out] none + \retval 8-bit value of the free data register +*/ +uint8_t crc_free_data_register_read(void) +{ + uint8_t fdata; + fdata = (uint8_t)CRC_FDATA; + return (fdata); +} + +/*! + \brief write the free data register + \param[in] free_data: specify 8-bit data + \param[out] none + \retval none +*/ +void crc_free_data_register_write(uint8_t free_data) +{ + CRC_FDATA = (uint32_t)free_data; +} + +/*! + \brief write the initializaiton data register + \param[in] init_data:specify 32-bit data + \param[out] none + \retval none +*/ +void crc_init_data_register_write(uint32_t init_data) +{ + CRC_IDATA = (uint32_t)init_data; +} + +/*! + \brief configure the CRC input data function + \param[in] data_reverse: specify input data reverse function + only one parameter can be selected which is shown as below: + \arg CRC_INPUT_DATA_NOT: input data is not reversed + \arg CRC_INPUT_DATA_BYTE: input data is reversed on 8 bits + \arg CRC_INPUT_DATA_HALFWORD: input data is reversed on 16 bits + \arg CRC_INPUT_DATA_WORD: input data is reversed on 32 bits + \param[out] none + \retval none +*/ +void crc_input_data_reverse_config(uint32_t data_reverse) +{ + CRC_CTL &= (uint32_t)(~CRC_CTL_REV_I); + CRC_CTL |= (uint32_t)data_reverse; +} + +/*! + \brief configure the CRC size of polynomial function + \param[in] poly_size: size of polynomial + only one parameter can be selected which is shown as below: + \arg CRC_CTL_PS_32: 32-bit polynomial for CRC calculation + \arg CRC_CTL_PS_16: 16-bit polynomial for CRC calculation + \arg CRC_CTL_PS_8: 8-bit polynomial for CRC calculation + \arg CRC_CTL_PS_7: 7-bit polynomial for CRC calculation + \param[out] none + \retval none +*/ +void crc_polynomial_size_set(uint32_t poly_size) +{ + CRC_CTL &= (uint32_t)(~(CRC_CTL_PS)); + CRC_CTL |= (uint32_t)poly_size; +} + +/*! + \brief configure the CRC polynomial value function + \param[in] poly: configurable polynomial value + \param[out] none + \retval none +*/ +void crc_polynomial_set(uint32_t poly) +{ + CRC_POLY &= (uint32_t)(~CRC_POLY_POLY); + CRC_POLY = poly; +} + +/*! + \brief CRC calculate a 32-bit data + \param[in] sdata: specify 32-bit data + \param[out] none + \retval 32-bit CRC calculate value +*/ +uint32_t crc_single_data_calculate(uint32_t sdata) +{ + CRC_DATA = sdata; + return(CRC_DATA); +} + +/*! + \brief CRC calculate a 32-bit data array + \param[in] array: pointer to an array of 32 bit data words + \param[in] size: size of the array + \param[out] none + \retval 32-bit CRC calculate value +*/ +uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size) +{ + uint32_t index; + for(index = 0U; index < size; index++){ + CRC_DATA = array[index]; + } + return (CRC_DATA); +} diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_ctc.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_ctc.c new file mode 100644 index 0000000000..c065ddb7e5 --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_ctc.c @@ -0,0 +1,382 @@ +/*! + \file gd32f3x0_ctc.c + \brief CTC driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f3x0_ctc.h" + +#define CTC_FLAG_MASK ((uint32_t)0x00000700U) + +/*! + \brief reset CTC clock trim controller + \param[in] none + \param[out] none + \retval none +*/ +void ctc_deinit(void) +{ + /* reset CTC */ + rcu_periph_reset_enable(RCU_CTCRST); + rcu_periph_reset_disable(RCU_CTCRST); +} + +/*! + \brief configure reference signal source polarity + \param[in] polarity: + only one parameter can be selected which is shown as below: + \arg CTC_REFSOURCE_POLARITY_FALLING: reference signal source polarity is falling edge + \arg CTC_REFSOURCE_POLARITY_RISING: reference signal source polarity is rising edge + \param[out] none + \retval none +*/ +void ctc_refsource_polarity_config(uint32_t polarity) +{ + CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPOL); + CTC_CTL1 |= (uint32_t)polarity; +} + +/*! + \brief select reference signal source + \param[in] refs: + only one parameter can be selected which is shown as below: + \arg CTC_REFSOURCE_GPIO: GPIO is selected + \arg CTC_REFSOURCE_LXTAL: LXTAL is clock selected + \arg CTC_REFSOURCE_USBSOF: USBSOF is selected + \param[out] none + \retval none +*/ +void ctc_refsource_signal_select(uint32_t refs) +{ + CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFSEL); + CTC_CTL1 |= (uint32_t)refs; +} + +/*! + \brief configure reference signal source prescaler + \param[in] prescaler: + only one parameter can be selected which is shown as below: + \arg CTC_REFSOURCE_PSC_OFF: reference signal not divided + \arg CTC_REFSOURCE_PSC_DIV2: reference signal divided by 2 + \arg CTC_REFSOURCE_PSC_DIV4: reference signal divided by 4 + \arg CTC_REFSOURCE_PSC_DIV8: reference signal divided by 8 + \arg CTC_REFSOURCE_PSC_DIV16: reference signal divided by 16 + \arg CTC_REFSOURCE_PSC_DIV32: reference signal divided by 32 + \arg CTC_REFSOURCE_PSC_DIV64: reference signal divided by 64 + \arg CTC_REFSOURCE_PSC_DIV128: reference signal divided by 128 + \param[out] none + \retval none +*/ +void ctc_refsource_prescaler_config(uint32_t prescaler) +{ + CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPSC); + CTC_CTL1 |= (uint32_t)prescaler; +} + +/*! + \brief configure clock trim base limit value + \param[in] limit_value: 8-bit clock trim base limit value + \arg 0x00-0xFF + \param[out] none + \retval none +*/ +void ctc_clock_limit_value_config(uint8_t limit_value) +{ + CTC_CTL1 &= (uint32_t)(~CTC_CTL1_CKLIM); + CTC_CTL1 |= CTL1_CKLIM(limit_value); +} + +/*! + \brief configure CTC counter reload value + \param[in] reload_value: 16-bit CTC counter reload value + \arg 0x0000-0xFFFF + \param[out] none + \retval none +*/ +void ctc_counter_reload_value_config(uint16_t reload_value) +{ + CTC_CTL1 &= (uint32_t)(~CTC_CTL1_RLVALUE); + CTC_CTL1 |= (uint32_t)reload_value; +} + +/*! + \brief enable CTC trim counter + \param[in] none + \param[out] none + \retval none +*/ +void ctc_counter_enable(void) +{ + CTC_CTL0 |= (uint32_t)CTC_CTL0_CNTEN; +} + +/*! + \brief disable CTC trim counter + \param[in] none + \param[out] none + \retval none +*/ +void ctc_counter_disable(void) +{ + CTC_CTL0 &= (uint32_t)(~CTC_CTL0_CNTEN); +} + +/*! + \brief configure the IRC48M trim value + \param[in] trim_value: 8-bit IRC48M trim value + \arg 0x00-0x3F + \param[out] none + \retval none +*/ +void ctc_irc48m_trim_value_config(uint8_t trim_value) +{ + /* clear TRIMVALUE bits */ + CTC_CTL0 &= (~(uint32_t)CTC_CTL0_TRIMVALUE); + /* set TRIMVALUE bits */ + CTC_CTL0 |= CTL0_TRIMVALUE(trim_value); +} + +/*! + \brief generate software reference source sync pulse + \param[in] none + \param[out] none + \retval none +*/ +void ctc_software_refsource_pulse_generate(void) +{ + CTC_CTL0 |= (uint32_t)CTC_CTL0_SWREFPUL; +} + +/*! + \brief configure hardware automatically trim mode + \param[in] hardmode: + only one parameter can be selected which is shown as below: + \arg CTC_HARDWARE_TRIM_MODE_ENABLE: hardware automatically trim mode enable + \arg CTC_HARDWARE_TRIM_MODE_DISABLE: hardware automatically trim mode disable + \param[out] none + \retval none +*/ +void ctc_hardware_trim_mode_config(uint32_t hardmode) +{ + CTC_CTL0 &= (uint32_t)(~CTC_CTL0_AUTOTRIM); + CTC_CTL0 |= (uint32_t)hardmode; +} + +/*! + \brief read CTC counter capture value when reference sync pulse occurred + \param[in] none + \param[out] none + \retval the 16-bit CTC counter capture value +*/ +uint16_t ctc_counter_capture_value_read(void) +{ + uint16_t capture_value = 0U; + capture_value = (uint16_t)GET_STAT_REFCAP(CTC_STAT); + return (capture_value); +} + +/*! + \brief read CTC trim counter direction when reference sync pulse occurred + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET + \arg SET: CTC trim counter direction is down-counting + \arg RESET: CTC trim counter direction is up-counting +*/ +FlagStatus ctc_counter_direction_read(void) +{ + FlagStatus ret_status = RESET; + if(RESET != (CTC_STAT & CTC_STAT_REFDIR)){ + ret_status = SET; + } + return ret_status; +} + +/*! + \brief read CTC counter reload value + \param[in] none + \param[out] none + \retval the 16-bit CTC counter reload value +*/ +uint16_t ctc_counter_reload_value_read(void) +{ + uint16_t reload_value = 0U; + reload_value = (uint16_t)(CTC_CTL1 & CTC_CTL1_RLVALUE); + return (reload_value); +} + +/*! + \brief read the IRC48M trim value + \param[in] none + \param[out] none + \retval the 8-bit IRC48M trim value +*/ +uint8_t ctc_irc48m_trim_value_read(void) +{ + uint8_t trim_value = 0U; + trim_value = (uint8_t)GET_CTL0_TRIMVALUE(CTC_CTL0); + return (trim_value); +} + +/*! + \brief enable the CTC interrupt + \param[in] interrupt: CTC interrupt enable + one or more parameters can be selected which are shown as below: + \arg CTC_INT_CKOK: clock trim OK interrupt enable + \arg CTC_INT_CKWARN: clock trim warning interrupt enable + \arg CTC_INT_ERR: error interrupt enable + \arg CTC_INT_EREF: expect reference interrupt enable + \param[out] none + \retval none +*/ +void ctc_interrupt_enable(uint32_t interrupt) +{ + CTC_CTL0 |= (uint32_t)interrupt; +} + +/*! + \brief disable the CTC interrupt + \param[in] interrupt: CTC interrupt enable source + one or more parameters can be selected which are shown as below: + \arg CTC_INT_CKOK: clock trim OK interrupt enable + \arg CTC_INT_CKWARN: clock trim warning interrupt enable + \arg CTC_INT_ERR: error interrupt enable + \arg CTC_INT_EREF: expect reference interrupt enable + \param[out] none + \retval none +*/ +void ctc_interrupt_disable(uint32_t interrupt) +{ + CTC_CTL0 &= (uint32_t)(~(interrupt)); +} + +/*! + \brief get CTC flag + \param[in] flag: the CTC flag + only one parameter can be selected which is shown as below: + \arg CTC_FLAG_CKOK: clock trim OK flag + \arg CTC_FLAG_CKWARN: clock trim warning flag + \arg CTC_FLAG_ERR: error flag + \arg CTC_FLAG_EREF: expect reference flag + \arg CTC_FLAG_CKERR: clock trim error bit + \arg CTC_FLAG_REFMISS: reference sync pulse miss + \arg CTC_FLAG_TRIMERR: trim value error bit + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus ctc_flag_get(uint32_t flag) +{ + FlagStatus ret_status = RESET; + + if(RESET != (CTC_STAT & flag)){ + ret_status = SET; + } + return ret_status; +} + +/*! + \brief clear CTC flag + \param[in] flag: the CTC flag + only one parameter can be selected which is shown as below: + \arg CTC_FLAG_CKOK: clock trim OK flag + \arg CTC_FLAG_CKWARN: clock trim warning flag + \arg CTC_FLAG_ERR: error flag + \arg CTC_FLAG_EREF: expect reference flag + \arg CTC_FLAG_CKERR: clock trim error bit + \arg CTC_FLAG_REFMISS: reference sync pulse miss + \arg CTC_FLAG_TRIMERR: trim value error bit + \param[out] none + \retval none +*/ +void ctc_flag_clear(uint32_t flag) +{ + if(flag & CTC_FLAG_MASK){ + CTC_INTC |= CTC_INTC_ERRIC; + }else{ + CTC_INTC |= flag; + } +} + +/*! + \brief get CTC interrupt flag + \param[in] interrupt: the CTC interrupt flag + only one parameter can be selected which is shown as below: + \arg CTC_INT_FLAG_CKOK: clock trim OK interrupt + \arg CTC_INT_FLAG_CKWARN: clock trim warning interrupt + \arg CTC_INT_FLAG_ERR: error interrupt + \arg CTC_INT_FLAG_EREF: expect reference interrupt + \arg CTC_INT_FLAG_CKERR: clock trim error bit interrupt + \arg CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt + \arg CTC_INT_FLAG_TRIMERR: trim value error interrupt + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus ctc_interrupt_flag_get(uint32_t interrupt) +{ + uint32_t ctc_int = 0U, intenable = 0U; + FlagStatus ret_status = RESET; + + if(interrupt & CTC_FLAG_MASK){ + intenable = CTC_CTL0 & CTC_INT_ERR; + }else{ + intenable = CTC_CTL0 & interrupt; + } + ctc_int = CTC_STAT & interrupt; + + if(ctc_int && intenable){ + ret_status = SET; + } + return ret_status; +} + +/*! + \brief clear CTC interrupt flag + \param[in] interrupt: the CTC interrupt flag + only one parameter can be selected which is shown as below: + \arg CTC_INT_FLAG_CKOK: clock trim OK interrupt + \arg CTC_INT_FLAG_CKWARN: clock trim warning interrupt + \arg CTC_INT_FLAG_ERR: error interrupt + \arg CTC_INT_FLAG_EREF: expect reference interrupt + \arg CTC_INT_FLAG_CKERR: clock trim error bit interrupt + \arg CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt + \arg CTC_INT_FLAG_TRIMERR: trim value error interrupt + \param[out] none + \retval none +*/ +void ctc_interrupt_flag_clear(uint32_t interrupt) +{ + if(interrupt & CTC_FLAG_MASK){ + CTC_INTC |= CTC_INTC_ERRIC; + }else{ + CTC_INTC |= interrupt; + } +} diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_dac.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_dac.c new file mode 100644 index 0000000000..689118c41e --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_dac.c @@ -0,0 +1,387 @@ +/*! + \file gd32f3x0_dac.c + \brief DAC driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifdef GD32F350 +#include "gd32f3x0_dac.h" + +/*! + \brief deinitialize DAC + \param[in] none + \param[out] none + \retval none +*/ +void dac_deinit(void) +{ + rcu_periph_reset_enable(RCU_DACRST); + rcu_periph_reset_disable(RCU_DACRST); +} + +/*! + \brief enable DAC + \param[in] none + \param[out] none + \retval none +*/ +void dac_enable(void) +{ + DAC_CTL |= DAC_CTL_DEN; +} + +/*! + \brief disable DAC + \param[in] none + \param[out] none + \retval none +*/ +void dac_disable(void) +{ + DAC_CTL &= ~DAC_CTL_DEN; +} + +/*! + \brief enable DAC DMA + \param[in] none + \param[out] none + \retval none +*/ +void dac_dma_enable(void) +{ + DAC_CTL |= DAC_CTL_DDMAEN; +} + +/*! + \brief disable DAC DMA + \param[in] none + \param[out] none + \retval none +*/ +void dac_dma_disable(void) +{ + DAC_CTL &= ~DAC_CTL_DDMAEN; +} + +/*! + \brief enable DAC output buffer + \param[in] none + \param[out] none + \retval none +*/ +void dac_output_buffer_enable(void) +{ + DAC_CTL &= ~DAC_CTL_DBOFF; +} + +/*! + \brief disable DAC output buffer + \param[in] none + \param[out] none + \retval none +*/ +void dac_output_buffer_disable(void) +{ + DAC_CTL |= DAC_CTL_DBOFF; +} + +/*! + \brief enable DAC trigger + \param[in] none + \param[out] none + \retval none +*/ +void dac_trigger_enable(void) +{ + DAC_CTL |= DAC_CTL_DTEN; +} + +/*! + \brief disable DAC trigger + \param[in] none + \param[out] none + \retval none +*/ +void dac_trigger_disable(void) +{ + DAC_CTL &= ~DAC_CTL_DTEN; +} + +/*! + \brief enable DAC software trigger + \param[in] none + \param[out] none + \retval none +*/ +void dac_software_trigger_enable(void) +{ + DAC_SWT |= DAC_SWT_SWTR; +} + +/*! + \brief disable DAC software trigger + \param[in] none + \param[out] none + \retval none +*/ +void dac_software_trigger_disable(void) +{ + DAC_SWT &= ~DAC_SWT_SWTR; +} + +/*! + \brief enable DAC interrupt(DAC DMA underrun interrupt) + \param[in] none + \param[out] none + \retval none +*/ +void dac_interrupt_enable(void) +{ + DAC_CTL |= DAC_CTL_DDUDRIE; +} + +/*! + \brief disable DAC interrupt(DAC DMA underrun interrupt) + \param[in] none + \param[out] none + \retval none +*/ +void dac_interrupt_disable(void) +{ + DAC_CTL &= ~DAC_CTL_DDUDRIE; +} + +/*! + \brief set DAC tgigger source + \param[in] triggersource: external triggers of DAC + \arg DAC_TRIGGER_T1_TRGO: trigger source is TIMER1 TRGO + \arg DAC_TRIGGER_T2_TRGO: trigger source is TIMER2 TRGO + \arg DAC_TRIGGER_T5_TRGO: trigger source is TIMER5 TRGO + \arg DAC_TRIGGER_T14_TRGO: trigger source is TIMER14 TRGO + \arg DAC_TRIGGER_EXTI_9: trigger source is EXTI interrupt line9 event + \arg DAC_TRIGGER_SOFTWARE: software trigger + \param[out] none + \retval none +*/ +void dac_trigger_source_config(uint32_t triggersource) +{ + DAC_CTL &= ~DAC_CTL_DTSEL; + DAC_CTL |= triggersource; +} + +/*! + \brief configure DAC wave mode + \param[in] wave_mode + \arg DAC_WAVE_DISABLE: wave disable + \arg DAC_WAVE_MODE_LFSR: LFSR noise mode + \arg DAC_WAVE_MODE_TRIANGLE: triangle noise mode + \param[out] none + \retval none +*/ +void dac_wave_mode_config(uint32_t wave_mode) +{ + DAC_CTL &= ~DAC_CTL_DWM; + DAC_CTL |= wave_mode; +} + +/*! + \brief configure DAC wave bit width + \param[in] bit_width + \arg DAC_WAVE_BIT_WIDTH_1: bit width of the wave signal is 1 + \arg DAC_WAVE_BIT_WIDTH_2: bit width of the wave signal is 2 + \arg DAC_WAVE_BIT_WIDTH_3: bit width of the wave signal is 3 + \arg DAC_WAVE_BIT_WIDTH_4: bit width of the wave signal is 4 + \arg DAC_WAVE_BIT_WIDTH_5: bit width of the wave signal is 5 + \arg DAC_WAVE_BIT_WIDTH_6: bit width of the wave signal is 6 + \arg DAC_WAVE_BIT_WIDTH_7: bit width of the wave signal is 7 + \arg DAC_WAVE_BIT_WIDTH_8: bit width of the wave signal is 8 + \arg DAC_WAVE_BIT_WIDTH_9: bit width of the wave signal is 9 + \arg DAC_WAVE_BIT_WIDTH_10: bit width of the wave signal is 10 + \arg DAC_WAVE_BIT_WIDTH_11: bit width of the wave signal is 11 + \arg DAC_WAVE_BIT_WIDTH_12: bit width of the wave signal is 12 + \param[out] none + \retval none +*/ +void dac_wave_bit_width_config(uint32_t bit_width) +{ + DAC_CTL &= ~DAC_CTL_DWBW; + DAC_CTL |= bit_width; +} + +/*! + \brief configure DAC LFSR noise mode + \param[in] unmask_bits + \arg DAC_LFSR_BIT0: unmask the LFSR bit0 + \arg DAC_LFSR_BITS1_0: unmask the LFSR bits[1:0] + \arg DAC_LFSR_BITS2_0: unmask the LFSR bits[2:0] + \arg DAC_LFSR_BITS3_0: unmask the LFSR bits[3:0] + \arg DAC_LFSR_BITS4_0: unmask the LFSR bits[4:0] + \arg DAC_LFSR_BITS5_0: unmask the LFSR bits[5:0] + \arg DAC_LFSR_BITS6_0: unmask the LFSR bits[6:0] + \arg DAC_LFSR_BITS7_0: unmask the LFSR bits[7:0] + \arg DAC_LFSR_BITS8_0: unmask the LFSR bits[8:0] + \arg DAC_LFSR_BITS9_0: unmask the LFSR bits[9:0] + \arg DAC_LFSR_BITS10_0: unmask the LFSR bits[10:0] + \arg DAC_LFSR_BITS11_0: unmask the LFSR bits[11:0] + \param[out] none + \retval none +*/ +void dac_lfsr_noise_config(uint32_t unmask_bits) +{ + DAC_CTL &= ~DAC_CTL_DWBW; + DAC_CTL |= unmask_bits; +} + +/*! + \brief configure DAC triangle noise mode + \param[in] amplitude + \arg DAC_TRIANGLE_AMPLITUDE_1: triangle amplitude is 1 + \arg DAC_TRIANGLE_AMPLITUDE_3: triangle amplitude is 3 + \arg DAC_TRIANGLE_AMPLITUDE_7: triangle amplitude is 7 + \arg DAC_TRIANGLE_AMPLITUDE_15: triangle amplitude is 15 + \arg DAC_TRIANGLE_AMPLITUDE_31: triangle amplitude is 31 + \arg DAC_TRIANGLE_AMPLITUDE_63: triangle amplitude is 63 + \arg DAC_TRIANGLE_AMPLITUDE_127: triangle amplitude is 127 + \arg DAC_TRIANGLE_AMPLITUDE_255: triangle amplitude is 255 + \arg DAC_TRIANGLE_AMPLITUDE_511: triangle amplitude is 511 + \arg DAC_TRIANGLE_AMPLITUDE_1023: triangle amplitude is 1023 + \arg DAC_TRIANGLE_AMPLITUDE_2047: triangle amplitude is 2047 + \arg DAC_TRIANGLE_AMPLITUDE_4095: triangle amplitude is 4095 + \param[out] none + \retval none +*/ +void dac_triangle_noise_config(uint32_t amplitude) +{ + DAC_CTL &= ~DAC_CTL_DWBW; + DAC_CTL |= amplitude; +} + +/*! + \brief get DAC output value + \param[in] none + \param[out] none + \retval DAC output data +*/ +uint16_t dac_output_value_get(void) +{ + uint16_t data = 0U; + data = (uint16_t)DAC_DO; + return data; +} + +/*! + \brief get the specified DAC flag(DAC DMA underrun flag) + \param[in] none + \param[out] none + \retval the state of dac bit(SET or RESET) +*/ +FlagStatus dac_flag_get(void) +{ + /* check the DMA underrun flag */ + if((uint8_t)RESET != (DAC_STAT & DAC_STAT_DDUDR)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear the specified DAC flag(DAC DMA underrun flag) + \param[in] none + \param[out] none + \retval none +*/ +void dac_flag_clear(void) +{ + DAC_STAT |= DAC_STAT_DDUDR; +} + +/*! + \brief get the specified DAC interrupt flag(DAC DMA underrun interrupt flag) + \param[in] none + \param[out] none + \retval the state of DAC interrupt flag(SET or RESET) +*/ +FlagStatus dac_interrupt_flag_get(void) +{ + FlagStatus temp_flag = RESET; + uint32_t ddudr_flag = 0U, ddudrie_flag = 0U; + /* check the DMA underrun flag and DAC DMA underrun interrupt enable flag */ + ddudr_flag = DAC_STAT & DAC_STAT_DDUDR; + ddudrie_flag = DAC_CTL & DAC_CTL_DDUDRIE; + if((RESET != ddudr_flag) && (RESET != ddudrie_flag)){ + temp_flag = SET; + } + return temp_flag; +} + +/*! + \brief clear the specified DAC interrupt flag(DAC DMA underrun interrupt flag) + \param[in] none + \param[out] none + \retval none +*/ +void dac_interrupt_flag_clear(void) +{ + DAC_STAT |= DAC_STAT_DDUDR; +} + +/*! + \brief set DAC data holding register value + \param[in] dac_align + \arg DAC_ALIGN_8B_R: data right 8b alignment + \arg DAC_ALIGN_12B_R: data right 12b alignment + \arg DAC_ALIGN_12B_L: data left 12b alignment + \param[in] data: data to be loaded + \param[out] none + \retval none +*/ +void dac_data_set(uint32_t dac_align, uint16_t data) +{ + switch(dac_align){ + /* data right 12b alignment */ + case DAC_ALIGN_12B_R: + DAC_R12DH = data; + break; + /* data left 12b alignment */ + case DAC_ALIGN_12B_L: + DAC_L12DH = data; + break; + /* data right 8b alignment */ + case DAC_ALIGN_8B_R: + DAC_R8DH = data; + break; + default: + break; + } +} +#endif /* GD32F350 */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_dbg.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_dbg.c new file mode 100644 index 0000000000..1ff7928c80 --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_dbg.c @@ -0,0 +1,131 @@ +/*! + \file gd32f3x0_dbg.c + \brief DBG driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f3x0_dbg.h" + +#define DBG_RESET_VAL ((uint32_t)0x00000000U) /*!< DBG reset value */ + +/*! + \brief deinitialize the DBG + \param[in] none + \param[out] none + \retval none +*/ +void dbg_deinit(void) +{ + DBG_CTL0 = DBG_RESET_VAL; + DBG_CTL1 = DBG_RESET_VAL; +} + +/*! + \brief read DBG_ID code register + \param[in] none + \param[out] none + \retval DBG_ID code +*/ +uint32_t dbg_id_get(void) +{ + return DBG_ID; +} + +/*! + \brief enable low power behavior when the mcu is in debug mode + \param[in] dbg_low_power: + one or more parameters can be selected which are shown as below: + \arg DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode + \arg DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode + \arg DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode + \param[out] none + \retval none +*/ +void dbg_low_power_enable(uint32_t dbg_low_power) +{ + DBG_CTL0 |= dbg_low_power; +} + +/*! + \brief disable low power behavior when the mcu is in debug mode + \param[in] dbg_low_power: + one or more parameters can be selected which are shown as below: + \arg DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode + \arg DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode + \arg DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode + \param[out] none + \retval none +*/ +void dbg_low_power_disable(uint32_t dbg_low_power) +{ + DBG_CTL0 &= ~dbg_low_power; +} + +/*! + \brief enable peripheral behavior when the mcu is in debug mode + \param[in] dbg_periph: refer to dbg_periph_enum + one or more parameters can be selected which are shown as below: + \arg DBG_SLEEP_HOLD: keep debugger connection during sleep mode + \arg DBG_DEEPSLEEP_HOLD: keep debugger connection during deepsleep mode + \arg DBG_STANDBY_HOLD: keep debugger connection during standby mode + \arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted + \arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted + \arg DBG_TIMERx_HOLD (x=0,1,2,5,13,14,15,16,TIMER5 is only available in GD32F350): hold TIMERx counter when core is halted + \arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted + \arg DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted + \param[out] none + \retval none +*/ +void dbg_periph_enable(dbg_periph_enum dbg_periph) +{ + DBG_REG_VAL(dbg_periph) |= BIT(DBG_BIT_POS(dbg_periph)); +} + +/*! + \brief disable peripheral behavior when the mcu is in debug mode + \param[in] dbg_periph: refer to dbg_periph_enum + one or more parameters can be selected which are shown as below: + \arg DBG_SLEEP_HOLD: keep debugger connection during sleep mode + \arg DBG_DEEPSLEEP_HOLD: keep debugger connection during deepsleep mode + \arg DBG_STANDBY_HOLD: keep debugger connection during standby mode + \arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted + \arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted + \arg DBG_TIMERx_HOLD (x=0,1,2,5,13,14,15,16,TIMER5 is only available in GD32F350): hold TIMERx counter when core is halted + \arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted + \arg DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted + \param[out] none + \retval none +*/ +void dbg_periph_disable(dbg_periph_enum dbg_periph) +{ + DBG_REG_VAL(dbg_periph) &= ~BIT(DBG_BIT_POS(dbg_periph)); +} diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_dma.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_dma.c new file mode 100644 index 0000000000..971a0b72b6 --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_dma.c @@ -0,0 +1,561 @@ +/*! + \file gd32f3x0_dma.c + \brief DMA driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f3x0_dma.h" + +/*! + \brief deinitialize DMA a channel registers + \param[in] channelx: specify which DMA channel is deinitialized + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[out] none + \retval none +*/ +void dma_deinit(dma_channel_enum channelx) +{ + /* disable DMA a channel */ + DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CHEN; + /* reset DMA channel registers */ + DMA_CHCTL(channelx) = DMA_CHCTL_RESET_VALUE; + DMA_CHCNT(channelx) = DMA_CHCNT_RESET_VALUE; + DMA_CHPADDR(channelx) = DMA_CHPADDR_RESET_VALUE; + DMA_CHMADDR(channelx) = DMA_CHMADDR_RESET_VALUE; + DMA_INTC |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx); +} + +/*! + \brief initialize the parameters of DMA struct with the default values + \param[in] init_struct: the initialization data needed to initialize DMA channel + \param[out] none + \retval none +*/ +void dma_struct_para_init(dma_parameter_struct* init_struct) +{ + /* set the DMA struct with the default values */ + init_struct->periph_addr = 0U; + init_struct->periph_width = 0U; + init_struct->periph_inc = (uint8_t)DMA_PERIPH_INCREASE_DISABLE; + init_struct->memory_addr = 0U; + init_struct->memory_width = 0U; + init_struct->memory_inc = (uint8_t)DMA_MEMORY_INCREASE_DISABLE; + init_struct->number = 0U; + init_struct->direction = (uint8_t)DMA_PERIPHERAL_TO_MEMORY; + init_struct->priority = (uint32_t)DMA_PRIORITY_LOW; +} + +/*! + \brief initialize DMA channel + \param[in] channelx: specify which DMA channel is initialized + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[in] init_struct: the data needed to initialize DMA channel + periph_addr: peripheral base address + periph_width: DMA_PERIPHERAL_WIDTH_8BIT,DMA_PERIPHERAL_WIDTH_16BIT,DMA_PERIPHERAL_WIDTH_32BIT + periph_inc: DMA_PERIPH_INCREASE_ENABLE,DMA_PERIPH_INCREASE_DISABLE + memory_addr: memory base address + memory_width: DMA_MEMORY_WIDTH_8BIT,DMA_MEMORY_WIDTH_16BIT,DMA_MEMORY_WIDTH_32BIT + memory_inc: DMA_MEMORY_INCREASE_ENABLE,DMA_MEMORY_INCREASE_DISABLE + direction: DMA_PERIPHERAL_TO_MEMORY,DMA_MEMORY_TO_PERIPHERAL + number: the number of remaining data to be transferred by the DMA + priority: DMA_PRIORITY_LOW,DMA_PRIORITY_MEDIUM,DMA_PRIORITY_HIGH,DMA_PRIORITY_ULTRA_HIGH + \param[out] none + \retval none +*/ +void dma_init(dma_channel_enum channelx, dma_parameter_struct* init_struct) +{ + uint32_t ctl; + + dma_channel_disable(channelx); + + /* configure peripheral base address */ + DMA_CHPADDR(channelx) = init_struct->periph_addr; + + /* configure memory base address */ + DMA_CHMADDR(channelx) = init_struct->memory_addr; + + /* configure the number of remaining data to be transferred */ + DMA_CHCNT(channelx) = (init_struct->number & DMA_CHANNEL_CNT_MASK); + + /* configure peripheral transfer width,memory transfer width,channel priotity */ + ctl = DMA_CHCTL(channelx); + ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO); + ctl |= (init_struct->periph_width | init_struct->memory_width | init_struct->priority); + DMA_CHCTL(channelx) = ctl; + + /* configure peripheral increasing mode */ + if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc){ + DMA_CHCTL(channelx) |= DMA_CHXCTL_PNAGA; + }else{ + DMA_CHCTL(channelx) &= ~DMA_CHXCTL_PNAGA; + } + + /* configure memory increasing mode */ + if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc){ + DMA_CHCTL(channelx) |= DMA_CHXCTL_MNAGA; + }else{ + DMA_CHCTL(channelx) &= ~DMA_CHXCTL_MNAGA; + } + + /* configure the direction of data transfer */ + if(DMA_PERIPHERAL_TO_MEMORY == init_struct->direction){ + DMA_CHCTL(channelx) &= ~DMA_CHXCTL_DIR; + }else{ + DMA_CHCTL(channelx) |= DMA_CHXCTL_DIR; + } +} + +/*! + \brief enable DMA circulation mode + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[out] none + \retval none +*/ +void dma_circulation_enable(dma_channel_enum channelx) +{ + DMA_CHCTL(channelx) |= DMA_CHXCTL_CMEN; +} + +/*! + \brief disable DMA circulation mode + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[out] none + \retval none +*/ +void dma_circulation_disable(dma_channel_enum channelx) +{ + DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CMEN; +} + +/*! + \brief enable memory to memory mode + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[out] none + \retval none +*/ +void dma_memory_to_memory_enable(dma_channel_enum channelx) +{ + DMA_CHCTL(channelx) |= DMA_CHXCTL_M2M; +} + +/*! + \brief disable memory to memory mode + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[out] none + \retval none +*/ +void dma_memory_to_memory_disable(dma_channel_enum channelx) +{ + DMA_CHCTL(channelx) &= ~DMA_CHXCTL_M2M; +} + +/*! + \brief enable DMA channel + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[out] none + \retval none +*/ +void dma_channel_enable(dma_channel_enum channelx) +{ + DMA_CHCTL(channelx) |= DMA_CHXCTL_CHEN; +} + +/*! + \brief disable DMA channel + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[out] none + \retval none +*/ +void dma_channel_disable(dma_channel_enum channelx) +{ + DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CHEN; +} + +/*! + \brief set DMA peripheral base address + \param[in] channelx: specify which DMA channel to set peripheral base address + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[in] address: peripheral base address + \param[out] none + \retval none +*/ +void dma_periph_address_config(dma_channel_enum channelx, uint32_t address) +{ + DMA_CHPADDR(channelx) = address; +} + +/*! + \brief set DMA memory base address + \param[in] channelx: specify which DMA channel to set memory base address + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[in] address: memory base address + \param[out] none + \retval none +*/ +void dma_memory_address_config(dma_channel_enum channelx, uint32_t address) +{ + DMA_CHMADDR(channelx) = address; +} + +/*! + \brief set the number of remaining data to be transferred by the DMA + \param[in] channelx: specify which DMA channel to set number + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[in] number: the number of remaining data to be transferred by the DMA + \param[out] none + \retval none +*/ +void dma_transfer_number_config(dma_channel_enum channelx, uint32_t number) +{ + DMA_CHCNT(channelx) = (number & DMA_CHANNEL_CNT_MASK); +} + +/*! + \brief get the number of remaining data to be transferred by the DMA + \param[in] channelx: specify which DMA channel to set number + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[out] none + \retval the number of remaining data to be transferred by the DMA +*/ +uint32_t dma_transfer_number_get(dma_channel_enum channelx) +{ + return (uint32_t)DMA_CHCNT(channelx); +} + +/*! + \brief configure priority level of DMA channel + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[in] priority: priority level of this channel + only one parameter can be selected which is shown as below: + \arg DMA_PRIORITY_LOW: low priority + \arg DMA_PRIORITY_MEDIUM: medium priority + \arg DMA_PRIORITY_HIGH: high priority + \arg DMA_PRIORITY_ULTRA_HIGH: ultra high priority + \param[out] none + \retval none +*/ +void dma_priority_config(dma_channel_enum channelx, uint32_t priority) +{ + uint32_t ctl; + + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_PRIO; + ctl |= priority; + DMA_CHCTL(channelx) = ctl; +} + +/*! + \brief configure transfer data width of memory + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[in] mwidth: transfer data width of memory + only one parameter can be selected which is shown as below: + \arg DMA_MEMORY_WIDTH_8BIT: transfer data width of memory is 8-bit + \arg DMA_MEMORY_WIDTH_16BIT: transfer data width of memory is 16-bit + \arg DMA_MEMORY_WIDTH_32BIT: transfer data width of memory is 32-bit + \param[out] none + \retval none +*/ +void dma_memory_width_config(dma_channel_enum channelx, uint32_t mwidth) +{ + uint32_t ctl; + + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_MWIDTH; + ctl |= mwidth; + DMA_CHCTL(channelx) = ctl; +} + +/*! + \brief configure transfer data width of peripheral + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[in] pwidth: transfer data width of peripheral + only one parameter can be selected which is shown as below: + \arg DMA_PERIPHERAL_WIDTH_8BIT: transfer data width of peripheral is 8-bit + \arg DMA_PERIPHERAL_WIDTH_16BIT: transfer data width of peripheral is 16-bit + \arg DMA_PERIPHERAL_WIDTH_32BIT: transfer data width of peripheral is 32-bit + \param[out] none + \retval none +*/ +void dma_periph_width_config(dma_channel_enum channelx, uint32_t pwidth) +{ + uint32_t ctl; + + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_PWIDTH; + ctl |= pwidth; + DMA_CHCTL(channelx) = ctl; +} + +/*! + \brief enable next address increasement algorithm of memory + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[out] none + \retval none +*/ +void dma_memory_increase_enable(dma_channel_enum channelx) +{ + DMA_CHCTL(channelx) |= DMA_CHXCTL_MNAGA; +} + +/*! + \brief disable next address increasement algorithm of memory + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[out] none + \retval none +*/ +void dma_memory_increase_disable(dma_channel_enum channelx) +{ + DMA_CHCTL(channelx) &= ~DMA_CHXCTL_MNAGA; +} + +/*! + \brief enable next address increasement algorithm of peripheral + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[out] none + \retval none +*/ +void dma_periph_increase_enable(dma_channel_enum channelx) +{ + DMA_CHCTL(channelx) |= DMA_CHXCTL_PNAGA; +} + +/*! + \brief disable next address increasement algorithm of peripheral + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[out] none + \retval none +*/ +void dma_periph_increase_disable(dma_channel_enum channelx) +{ + DMA_CHCTL(channelx) &= ~DMA_CHXCTL_PNAGA; +} + +/*! + \brief configure the direction of data transfer on the channel + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[in] direction: specify the direction of data transfer + only one parameter can be selected which is shown as below: + \arg DMA_PERIPHERAL_TO_MEMORY: read from peripheral and write to memory + \arg DMA_MEMORY_TO_PERIPHERAL: read from memory and write to peripheral + \param[out] none + \retval none +*/ +void dma_transfer_direction_config(dma_channel_enum channelx, uint32_t direction) +{ + if(DMA_PERIPHERAL_TO_MEMORY == direction){ + DMA_CHCTL(channelx) &= ~DMA_CHXCTL_DIR; + } else { + DMA_CHCTL(channelx) |= DMA_CHXCTL_DIR; + } +} + +/*! + \brief check DMA flag is set or not + \param[in] channelx: specify which DMA channel to get flag + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_FLAG_G: global interrupt flag of channel + \arg DMA_FLAG_FTF: full transfer finish flag of channel + \arg DMA_FLAG_HTF: half transfer finish flag of channel + \arg DMA_FLAG_ERR: error flag of channel + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus dma_flag_get(dma_channel_enum channelx, uint32_t flag) +{ + FlagStatus reval; + + if(RESET != (DMA_INTF & DMA_FLAG_ADD(flag, channelx))){ + reval = SET; + }else{ + reval = RESET; + } + + return reval; +} + +/*! + \brief clear DMA a channel flag + \param[in] channelx: specify which DMA channel to clear flag + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_FLAG_G: global interrupt flag of channel + \arg DMA_FLAG_FTF: full transfer finish flag of channel + \arg DMA_FLAG_HTF: half transfer finish flag of channel + \arg DMA_FLAG_ERR: error flag of channel + \param[out] none + \retval none +*/ +void dma_flag_clear(dma_channel_enum channelx, uint32_t flag) +{ + DMA_INTC |= DMA_FLAG_ADD(flag, channelx); +} + +/*! + \brief check DMA flag and interrupt enable bit is set or not + \param[in] channelx: specify which DMA channel to get flag + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_INT_FLAG_FTF: transfer finish flag of channel + \arg DMA_INT_FLAG_HTF: half transfer finish flag of channel + \arg DMA_INT_FLAG_ERR: error flag of channel + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus dma_interrupt_flag_get(dma_channel_enum channelx, uint32_t flag) +{ + uint32_t interrupt_enable = 0U, interrupt_flag = 0U; + + switch(flag){ + case DMA_INT_FLAG_FTF: + interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx); + interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_FTFIE; + break; + case DMA_INT_FLAG_HTF: + interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx); + interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_HTFIE; + break; + case DMA_INT_FLAG_ERR: + interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx); + interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_ERRIE; + break; + default: + break; + } + + if(interrupt_flag && interrupt_enable){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear DMA a channel interrupt flag + \param[in] channelx: specify which DMA channel to clear flag + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_INT_FLAG_G: global interrupt flag of channel + \arg DMA_INT_FLAG_FTF: transfer finish flag of channel + \arg DMA_INT_FLAG_HTF: half transfer finish flag of channel + \arg DMA_INT_FLAG_ERR: error flag of channel + \param[out] none + \retval none +*/ +void dma_interrupt_flag_clear(dma_channel_enum channelx, uint32_t flag) +{ + DMA_INTC |= DMA_FLAG_ADD(flag,channelx); +} + +/*! + \brief enable DMA interrupt + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[in] source: specify which interrupt to enable + only one parameter can be selected which is shown as below: + \arg DMA_INT_ERR: channel error interrupt + \arg DMA_INT_HTF: channel half transfer finish interrupt + \arg DMA_INT_FTF: channel full transfer finish interrupt + \param[out] none + \retval none +*/ +void dma_interrupt_enable(dma_channel_enum channelx, uint32_t source) +{ + DMA_CHCTL(channelx) |= source; +} + +/*! + \brief disable DMA interrupt + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[in] source: specify which interrupt to disable + only one parameter can be selected which is shown as below: + \arg DMA_INT_ERR: channel error interrupt + \arg DMA_INT_HTF: channel half transfer finish interrupt + \arg DMA_INT_FTF: channel full transfer finish interrupt + \param[out] none + \retval none +*/ +void dma_interrupt_disable(dma_channel_enum channelx, uint32_t source) +{ + DMA_CHCTL(channelx) &= ~source; +} diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_exti.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_exti.c new file mode 100644 index 0000000000..e14ed36472 --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_exti.c @@ -0,0 +1,253 @@ +/*! + \file gd32f3x0_exti.c + \brief EXTI driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f3x0_exti.h" + +/*! + \brief deinitialize the EXTI + \param[in] none + \param[out] none + \retval none +*/ +void exti_deinit(void) +{ + /* reset the value of all the EXTI registers */ + EXTI_INTEN = (uint32_t)0x0F940000U; + EXTI_EVEN = (uint32_t)0x00000000U; + EXTI_RTEN = (uint32_t)0x00000000U; + EXTI_FTEN = (uint32_t)0x00000000U; + EXTI_SWIEV = (uint32_t)0x00000000U; +} + +/*! + \brief initialize the EXTI, enable the configuration of EXTI initialize + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19,21,22): EXTI line x + \param[in] mode: interrupt or event mode, refer to exti_mode_enum + only one parameter can be selected which is shown as below: + \arg EXTI_INTERRUPT: interrupt mode + \arg EXTI_EVENT: event mode + \param[in] trig_type: interrupt trigger type, refer to exti_trig_type_enum + only one parameter can be selected which is shown as below: + \arg EXTI_TRIG_RISING: rising edge trigger + \arg EXTI_TRIG_FALLING: falling trigger + \arg EXTI_TRIG_BOTH: rising and falling trigger + \param[out] none + \retval none +*/ +void exti_init(exti_line_enum linex, \ + exti_mode_enum mode, \ + exti_trig_type_enum trig_type) +{ + /* reset the EXTI line x */ + EXTI_INTEN &= ~(uint32_t)linex; + EXTI_EVEN &= ~(uint32_t)linex; + EXTI_RTEN &= ~(uint32_t)linex; + EXTI_FTEN &= ~(uint32_t)linex; + + /* set the EXTI mode and enable the interrupts or events from EXTI line x */ + switch(mode){ + case EXTI_INTERRUPT: + EXTI_INTEN |= (uint32_t)linex; + break; + case EXTI_EVENT: + EXTI_EVEN |= (uint32_t)linex; + break; + default: + break; + } + + /* set the EXTI trigger type */ + switch(trig_type){ + case EXTI_TRIG_RISING: + EXTI_RTEN |= (uint32_t)linex; + EXTI_FTEN &= ~(uint32_t)linex; + break; + case EXTI_TRIG_FALLING: + EXTI_RTEN &= ~(uint32_t)linex; + EXTI_FTEN |= (uint32_t)linex; + break; + case EXTI_TRIG_BOTH: + EXTI_RTEN |= (uint32_t)linex; + EXTI_FTEN |= (uint32_t)linex; + break; + default: + break; + } +} + +/*! + \brief enable the interrupts from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..27): EXTI line x + \param[out] none + \retval none +*/ +void exti_interrupt_enable(exti_line_enum linex) +{ + EXTI_INTEN |= (uint32_t)linex; +} + +/*! + \brief disable the interrupt from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..27): EXTI line x + \param[out] none + \retval none +*/ +void exti_interrupt_disable(exti_line_enum linex) +{ + EXTI_INTEN &= ~(uint32_t)linex; +} + +/*! + \brief enable the events from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..27): EXTI line x + \param[out] none + \retval none +*/ +void exti_event_enable(exti_line_enum linex) +{ + EXTI_EVEN |= (uint32_t)linex; +} + +/*! + \brief disable the events from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..27): EXTI line x + \param[out] none + \retval none +*/ +void exti_event_disable(exti_line_enum linex) +{ + EXTI_EVEN &= ~(uint32_t)linex; +} + +/*! + \brief enable EXTI software interrupt event + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19,21,22): EXTI line x + \param[out] none + \retval none +*/ +void exti_software_interrupt_enable(exti_line_enum linex) +{ + EXTI_SWIEV |= (uint32_t)linex; +} + +/*! + \brief disable EXTI software interrupt event + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19,21,22): EXTI line x + \param[out] none + \retval none +*/ +void exti_software_interrupt_disable(exti_line_enum linex) +{ + EXTI_SWIEV &= ~(uint32_t)linex; +} + +/*! + \brief get EXTI line x pending flag + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19,21,22): EXTI line x + \param[out] none + \retval FlagStatus: status of flag (RESET or SET) +*/ +FlagStatus exti_flag_get(exti_line_enum linex) +{ + if(RESET != (EXTI_PD & (uint32_t)linex)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear EXTI line x pending flag + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19,21,22): EXTI line x + \param[out] none + \retval none +*/ +void exti_flag_clear(exti_line_enum linex) +{ + EXTI_PD = (uint32_t)linex; +} + +/*! + \brief get EXTI line x flag when the interrupt flag is set + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19,21,22): EXTI line x + \param[out] none + \retval FlagStatus: status of flag (RESET or SET) +*/ +FlagStatus exti_interrupt_flag_get(exti_line_enum linex) +{ + uint32_t flag_left, flag_right; + + flag_left = EXTI_PD & (uint32_t)linex; + flag_right = EXTI_INTEN & (uint32_t)linex; + + if((RESET != flag_left) && (RESET != flag_right)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear EXTI line x pending flag + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19,21,22): EXTI line x + \param[out] none + \retval none +*/ +void exti_interrupt_flag_clear(exti_line_enum linex) +{ + EXTI_PD = (uint32_t)linex; +} diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_fmc.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_fmc.c new file mode 100644 index 0000000000..e1341fa363 --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_fmc.c @@ -0,0 +1,888 @@ +/*! + \file gd32f3x0_fmc.c + \brief FMC driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f3x0_fmc.h" + +/* FMC main memory programming functions */ + +/*! + \brief unlock the main FMC operation + it is better to used in pairs with fmc_lock + \param[in] none + \param[out] none + \retval none +*/ +void fmc_unlock(void) +{ + if((RESET != (FMC_CTL & FMC_CTL_LK))){ + /* write the FMC key */ + FMC_KEY = UNLOCK_KEY0; + FMC_KEY = UNLOCK_KEY1; + } +} + +/*! + \brief lock the main FMC operation + it is better to used in pairs with fmc_unlock after an operation + \param[in] none + \param[out] none + \retval none +*/ +void fmc_lock(void) +{ + /* set the LK bit*/ + FMC_CTL |= FMC_CTL_LK; +} + +/*! + \brief set the wait state counter value + \param[in] wscnt: wait state counter value + only one parameter can be selected which is shown as below: + \arg WS_WSCNT_0: 0 wait state added + \arg WS_WSCNT_1: 1 wait state added + \arg WS_WSCNT_2: 2 wait state added + \param[out] none + \retval none +*/ +void fmc_wscnt_set(uint8_t wscnt) +{ + uint32_t reg; + + reg = FMC_WS; + /* set the wait state counter value */ + reg &= ~FMC_WS_WSCNT; + FMC_WS = (reg | wscnt); +} + +/*! + \brief fmc wait state enable + \param[in] none + \param[out] none + \retval none +*/ +void fmc_wait_state_enable(void) +{ + /* unlock the main flash */ + fmc_unlock(); + + /* set the WSEN bit in register FMC_WSEN */ + FMC_WSEN |= FMC_WSEN_WSEN; + + /* lock the main flash after operation */ + fmc_lock(); +} + +/*! + \brief fmc wait state disable + \param[in] none + \param[out] none + \retval none +*/ +void fmc_wait_state_disable(void) +{ + /* unlock the main flash */ + fmc_unlock(); + + /* reset the WSEN bit in register FMC_WSEN */ + FMC_WSEN &= ~FMC_WSEN_WSEN; + + /* lock the main flash after operation */ + fmc_lock(); +} + +/*! + \brief erase page + \param[in] page_address: target page start address + \param[out] none + \retval fmc_state +*/ +fmc_state_enum fmc_page_erase(uint32_t page_address) +{ + fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* start page erase */ + FMC_CTL |= FMC_CTL_PER; + FMC_ADDR = page_address; + FMC_CTL |= FMC_CTL_START; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the PER bit */ + FMC_CTL &= ~FMC_CTL_PER; + } + + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief erase whole chip + \param[in] none + \param[out] none + \retval fmc_state +*/ +fmc_state_enum fmc_mass_erase(void) +{ + fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* start chip erase */ + FMC_CTL |= FMC_CTL_MER; + FMC_CTL |= FMC_CTL_START; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the MER bit */ + FMC_CTL &= ~FMC_CTL_MER; + } + + /* return the fmc state */ + return fmc_state; +} + +/*! + \brief program a word at the corresponding address + \param[in] address: address to program + \param[in] data: word to program + \param[out] none + \retval fmc_state +*/ +fmc_state_enum fmc_word_program(uint32_t address, uint32_t data) +{ + fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* set the PG bit to start program */ + FMC_CTL |= FMC_CTL_PG; + + REG32(address) = data; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the PG bit */ + FMC_CTL &= ~FMC_CTL_PG; + } + + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief program a half word at the corresponding address + \param[in] address: address to program + \param[in] data: word to program + \param[out] none + \retval fmc_state +*/ +fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data) +{ + fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* set the PG bit to start program */ + FMC_CTL |= FMC_CTL_PG; + + REG16(address) = data; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the PG bit */ + FMC_CTL &= ~FMC_CTL_PG; + } + + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief program a word at the corresponding address without erasing + \param[in] address: address to program + \param[in] data: word to program + \param[out] none + \retval fmc_state +*/ +fmc_state_enum fmc_word_reprogram(uint32_t address, uint32_t data) +{ + fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + FMC_WSEN |= FMC_WSEN_BPEN; + + if(FMC_READY == fmc_state){ + /* set the PG bit to start program */ + FMC_CTL |= FMC_CTL_PG; + + REG32(address) = data; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the PG bit */ + FMC_CTL &= ~FMC_CTL_PG; + } + + /* return the FMC state */ + return fmc_state; +} + +/* FMC option bytes programming functions */ + +/*! + \brief unlock the option byte operation + it is better to used in pairs with ob_lock + \param[in] none + \param[out] none + \retval none +*/ +void ob_unlock(void) +{ + if(RESET == (FMC_CTL & FMC_CTL_OBWEN)){ + /* write the FMC key */ + FMC_OBKEY = UNLOCK_KEY0; + FMC_OBKEY = UNLOCK_KEY1; + } +} + +/*! + \brief lock the option byte operation + it is better to used in pairs with ob_unlock after an operation + \param[in] none + \param[out] none + \retval none +*/ +void ob_lock(void) +{ + /* reset the OBWE bit */ + FMC_CTL &= ~FMC_CTL_OBWEN; +} + +/*! + \brief reload the option byte and generate a system reset + \param[in] none + \param[out] none + \retval none +*/ +void ob_reset(void) +{ + /* set the OBRLD bit */ + FMC_CTL |= FMC_CTL_OBRLD; +} + +/*! + \brief erase the option byte + programmer must ensure FMC & option byte are both unlocked before calling this function + \param[in] none + \param[out] none + \retval fmc_state +*/ +fmc_state_enum ob_erase(void) +{ + uint16_t fmc_spc; + + uint32_t fmc_plevel = ob_obstat_plevel_get(); + fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + /* get the original option byte security protection code */ + if(OB_OBSTAT_PLEVEL_NO == fmc_plevel){ + fmc_spc = FMC_NSPC; + }else if(OB_OBSTAT_PLEVEL_LOW == fmc_plevel){ + fmc_spc = FMC_LSPC; + }else{ + fmc_spc = FMC_HSPC; + fmc_state = FMC_OB_HSPC; + } + + if(FMC_READY == fmc_state){ + /* start erase the option byte */ + FMC_CTL |= FMC_CTL_OBER; + FMC_CTL |= FMC_CTL_START; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* reset the OBER bit */ + FMC_CTL &= ~FMC_CTL_OBER; + + /* set the OBPG bit */ + FMC_CTL |= FMC_CTL_OBPG; + + /* restore the last get option byte security protection code */ + OB_SPC = fmc_spc; + OB_USER = OB_USER_DEFAULT; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_TOERR != fmc_state){ + /* reset the OBPG bit */ + FMC_CTL &= ~FMC_CTL_OBPG; + } + }else{ + if(FMC_TOERR != fmc_state){ + /* reset the OBPG bit */ + FMC_CTL &= ~FMC_CTL_OBPG; + } + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief enable option byte write protection(OB_WP) depending on current option byte + \param[in] ob_wp: write protection configuration data + setting the bit of ob_wp means enabling the corresponding sector write protection + \param[out] none + \retval fmc_state +*/ +fmc_state_enum ob_write_protection_enable(uint16_t ob_wp) +{ + uint8_t ob_wrp0, ob_wrp1; + ob_parm_struct ob_parm; + fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + ob_parm_get(&ob_parm); + ob_wp = (uint16_t)(~ob_wp); + ob_wrp0 = (uint8_t)(ob_wp & OB_LWP); + ob_wrp1 = (uint8_t)((ob_wp & OB_HWP) >> 8U); + + if(0xFFU == (uint8_t)OB_WP0){ + if (0xFFU == (uint8_t)OB_WP1){ + if(FMC_READY == fmc_state){ + /* set the OBPG bit*/ + FMC_CTL |= FMC_CTL_OBPG; + + if(0xFFU != ob_wrp0){ + OB_WP0 = ob_wrp0 ; + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + } + + if((FMC_READY == fmc_state) && (0xFFU != ob_wrp1)){ + OB_WP1 = ob_wrp1 ; + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + } + + if(FMC_TOERR != fmc_state){ + /* reset the OBPG bit */ + FMC_CTL &= ~FMC_CTL_OBPG; + } + } + } + }else{ + if(FMC_READY == fmc_state){ + /* start erase the option byte */ + FMC_CTL |= FMC_CTL_OBER; + FMC_CTL |= FMC_CTL_START; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + + /* reset the OBER bit */ + FMC_CTL &= ~FMC_CTL_OBER; + + /* enable the option bytes programming */ + FMC_CTL |= FMC_CTL_OBPG; + + ob_value_modify(OB_WP_ADDR0, ob_wp ,&ob_parm); + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_TOERR != fmc_state){ + /* reset the OBPG bit */ + FMC_CTL &= ~FMC_CTL_OBPG; + } + }else{ + if(FMC_TOERR != fmc_state){ + /* reset the OBER bit */ + FMC_CTL &= ~FMC_CTL_OBER; + } + } + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief configure security protection + \param[in] ob_spc: specify security protection code + only one parameter can be selected which is shown as below: + \arg FMC_NSPC: no security protection + \arg FMC_LSPC: low security protection + \arg FMC_HSPC: high security protection + \param[out] none + \retval fmc_state +*/ +fmc_state_enum ob_security_protection_config(uint8_t ob_spc) +{ + fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + ob_parm_struct ob_parm; + ob_parm_get(&ob_parm); + + /* the OB_SPC byte cannot be reprogrammed if protection level is high */ + if(OB_OBSTAT_PLEVEL_HIGH == ob_obstat_plevel_get()){ + fmc_state = FMC_OB_HSPC; + } + + if(FMC_READY == fmc_state){ + /* start erase the option byte */ + FMC_CTL |= FMC_CTL_OBER; + FMC_CTL |= FMC_CTL_START; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + + /* reset the OBER bit */ + FMC_CTL &= ~FMC_CTL_OBER; + + /* enable the option bytes programming */ + FMC_CTL |= FMC_CTL_OBPG; + + ob_value_modify(OB_SPC_ADDR, (uint16_t)ob_spc ,&ob_parm); + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_TOERR != fmc_state){ + /* reset the OBPG bit */ + FMC_CTL &= ~FMC_CTL_OBPG; + } + }else{ + if(FMC_TOERR != fmc_state){ + /* reset the OBER bit */ + FMC_CTL &= ~FMC_CTL_OBER; + } + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief program the FMC user option byte depending on current option byte + \param[in] ob_user: user option byte + one or more parameters (bitwise AND) can be selected which are shown as below: + \arg OB_FWDGT_HW: hardware free watchdog timer + \arg OB_DEEPSLEEP_RST: generate a reset instead of entering deepsleep mode + \arg OB_STDBY_RST: generate a reset instead of entering standby mode + \arg OB_BOOT1_SET_1: BOOT1 bit is 1 + \arg OB_VDDA_DISABLE: disable VDDA monitor + \arg OB_SRAM_PARITY_ENABLE: enable sram parity check + \param[out] none + \retval fmc_state +*/ +fmc_state_enum ob_user_write(uint8_t ob_user) +{ + /* check whether FMC is ready or not */ + fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + ob_parm_struct ob_parm; + ob_parm_get(&ob_parm); + + if(FMC_READY == fmc_state){ + /* start erase the option byte */ + FMC_CTL |= FMC_CTL_OBER; + FMC_CTL |= FMC_CTL_START; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* reset the OBER bit */ + FMC_CTL &= ~FMC_CTL_OBER; + + /* set the OBPG bit */ + FMC_CTL |= FMC_CTL_OBPG; + + /* restore the last get option byte security protection code */ + ob_value_modify(OB_USER_ADDR, (uint16_t)ob_user, &ob_parm); + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_TOERR != fmc_state){ + /* reset the OBPG bit */ + FMC_CTL &= ~FMC_CTL_OBPG; + } + }else{ + if(FMC_TOERR != fmc_state){ + /* reset the OBPG bit */ + FMC_CTL &= ~FMC_CTL_OBPG; + } + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief program the FMC data option byte + \param[in] address: OB_DATA_ADDR0 or OB_DATA_ADDR1 + only one parameter can be selected which is shown as below: + \arg OB_DATA_ADDR0: option byte data address 0 + \arg OB_DATA_ADDR1: option byte data address 1 + \param[in] data: the byte to be programmed + \param[out] none + \retval fmc_state +*/ +fmc_state_enum ob_data_program(uint32_t address, uint8_t data) +{ + fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + ob_parm_struct ob_parm; + ob_parm_get(&ob_parm); + if(0xFFU == REG8(address)) + { + if(FMC_READY == fmc_state){ + /* set the OBPG bit */ + FMC_CTL |= FMC_CTL_OBPG; + + REG16(address) = data ; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_TOERR != fmc_state){ + /* reset the OBPG bit */ + FMC_CTL &= ~FMC_CTL_OBPG; + } + } + }else{ + if(FMC_READY == fmc_state){ + /* start erase the option byte */ + FMC_CTL |= FMC_CTL_OBER; + FMC_CTL |= FMC_CTL_START; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + + /* reset the OBER bit */ + FMC_CTL &= ~FMC_CTL_OBER; + + /* enable the option bytes programming */ + FMC_CTL |= FMC_CTL_OBPG; + + ob_value_modify(address, (uint16_t)data ,&ob_parm); + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_TOERR != fmc_state){ + /* reset the OBPG bit */ + FMC_CTL &= ~FMC_CTL_OBPG; + } + }else{ + if(FMC_TOERR != fmc_state){ + /* reset the OBER bit */ + FMC_CTL &= ~FMC_CTL_OBER; + } + } + } + } + + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief get OB_USER in register FMC_OBSTAT + \param[in] none + \param[out] none + \retval ob_user +*/ +uint8_t ob_user_get(void) +{ + return (uint8_t)(FMC_OBSTAT >> 8U); +} + +/*! + \brief get OB_DATA in register FMC_OBSTAT + \param[in] none + \param[out] none + \retval ob_data +*/ +uint16_t ob_data_get(void) +{ + return (uint16_t)(FMC_OBSTAT >> 16U); +} + +/*! + \brief get the FMC option byte write protection (OB_WP) in register FMC_WP + \param[in] none + \param[out] none + \retval OB_WP +*/ +uint16_t ob_write_protection_get(void) +{ + return (uint16_t)(FMC_WP); +} + +/*! + \brief get the value of FMC option byte security protection level (PLEVEL) in FMC_OBSTAT register + \param[in] none + \param[out] none + \retval the value of PLEVEL +*/ +uint32_t ob_obstat_plevel_get(void) +{ + return (FMC_OBSTAT & (FMC_OBSTAT_PLEVEL_BIT0 | FMC_OBSTAT_PLEVEL_BIT1)); +} + +/* FMC interrupts and flags management functions */ +/*! + \brief enable FMC interrupt + \param[in] interrupt: the FMC interrupt source + one or more parameters can be selected which are shown as below: + \arg FMC_INTEN_END: FMC end of operation interrupt + \arg FMC_INTEN_ERR: FMC error interrupt + \param[out] none + \retval none +*/ +void fmc_interrupt_enable(uint32_t interrupt) +{ + FMC_CTL |= interrupt; +} + +/*! + \brief disable FMC interrupt + \param[in] interrupt: the FMC interrupt source + one or more parameters can be selected which are shown as below: + \arg FMC_INTEN_END: FMC end of operation interrupt + \arg FMC_INTEN_ERR: FMC error interrupt + \param[out] none + \retval none +*/ +void fmc_interrupt_disable(uint32_t interrupt) +{ + FMC_CTL &= ~(uint32_t)interrupt; +} + +/*! + \brief get flag set or reset + \param[in] flag: check FMC flag + only one parameter can be selected which is shown as below: + \arg FMC_FLAG_BUSY: FMC busy flag + \arg FMC_FLAG_PGERR: FMC programming error flag + \arg FMC_FLAG_WPERR: FMC write protection error flag + \arg FMC_FLAG_END: FMC end of programming flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus fmc_flag_get(uint32_t flag) +{ + FlagStatus status = RESET; + + if(FMC_STAT & flag){ + status = SET; + } + /* return the state of corresponding FMC flag */ + return status; +} + +/*! + \brief clear the FMC pending flag by writing 1 + \param[in] flag: clear FMC flag + only one parameter can be selected which is shown as below: + \arg FMC_FLAG_PGERR: FMC programming error flag + \arg FMC_FLAG_WPERR: FMC write protection error flag + \arg FMC_FLAG_END: fmc end of programming flag + \param[out] none + \retval none +*/ +void fmc_flag_clear(uint32_t flag) +{ + /* clear the flags */ + FMC_STAT = flag; +} + +/*! + \brief get flag set or reset + \param[in] flag: check FMC flag + only one parameter can be selected which is shown as below: + \arg FMC_FLAG_PGERR: FMC programming error flag + \arg FMC_FLAG_WPERR: FMC write protection error flag + \arg FMC_FLAG_END: FMC end of programming flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus fmc_interrupt_flag_get(uint32_t flag) +{ + FlagStatus status = RESET; + + if(FMC_STAT & flag){ + status = SET; + } + /* return the state of corresponding FMC flag */ + return status; +} + +/*! + \brief clear the FMC pending flag by writing 1 + \param[in] flag: clear FMC flag + only one parameter can be selected which is shown as below: + \arg FMC_FLAG_PGERR: FMC programming error flag + \arg FMC_FLAG_WPERR: FMC write protection error flag + \arg FMC_FLAG_END: fmc end of programming flag + \param[out] none + \retval none +*/ +void fmc_interrupt_flag_clear(uint32_t flag) +{ + /* clear the flags */ + FMC_STAT = flag; +} + +/*! + \brief get the FMC state + \param[in] none + \param[out] none + \retval fmc_state +*/ +fmc_state_enum fmc_state_get(void) +{ + fmc_state_enum fmc_state = FMC_READY; + + if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_BUSY)){ + fmc_state = FMC_BUSY; + }else{ + if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_WPERR)){ + fmc_state = FMC_WPERR; + }else{ + if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_PGERR)){ + fmc_state = FMC_PGERR; + } + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief check whether FMC is ready or not + \param[in] timeout: timeout count + \param[out] none + \retval fmc_state +*/ +fmc_state_enum fmc_ready_wait(uint32_t timeout) +{ + fmc_state_enum fmc_state = FMC_BUSY; + + /* wait for FMC ready */ + do{ + /* get FMC state */ + fmc_state = fmc_state_get(); + timeout--; + }while((FMC_BUSY == fmc_state) && (0U != timeout)); + + if(FMC_BUSY == fmc_state){ + fmc_state = FMC_TOERR; + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief get current option byte value + \param[in] ob_parm: pointer to option byte parameter struct + \param[out] ob_parm: pointer to option byte parameter struct + \retval none +*/ +void ob_parm_get(ob_parm_struct *ob_parm) +{ + /* get current option byte value */ + ob_parm->spc = (uint8_t)OB_SPC; + ob_parm->user = (uint8_t)OB_USER; + ob_parm->data0 = (uint8_t)OB_DATA0; + ob_parm->data1 = (uint8_t)OB_DATA1; + ob_parm->wp0 = (uint8_t)OB_WP0; + ob_parm->wp1 = (uint8_t)OB_WP1; +} + +/*! + \brief modify the target option byte depending on the original value + \param[in] address: target option byte address + \param[in] value: target option byte value + \param[in] ob_parm: pointer to option byte parameter struct + \param[out] none + \retval none +*/ +void ob_value_modify(uint32_t address, uint16_t value,ob_parm_struct *ob_parm) +{ + uint8_t spc, user, data0, data1, wp0, wp1; + /* store the original option bytes */ + spc = ob_parm->spc; + user = ob_parm->user; + data0 = ob_parm->data0; + data1 = ob_parm->data1; + wp0 = ob_parm->wp0; + wp1 = ob_parm->wp1; + + /* bring in the target option byte */ + if(OB_SPC_ADDR == address){ + spc = (uint8_t)value; + }else if(OB_DATA_ADDR0 == address){ + data0 = (uint8_t)value; + }else if(OB_DATA_ADDR1 == address){ + data1 = (uint8_t)value; + }else if(OB_USER_ADDR == address){ + user = user & (uint8_t)value; + }else{ + wp0 = wp0 & ((uint8_t) (value)); + wp1 = wp1 & ((uint8_t) (value >> 8U)); + } + /* basing on original value, modify the target option byte */ + OB_SPC = spc; + OB_USER = user; + if(0xFFU != data0){ + OB_DATA0 = data0; + } + if(0xFFU != data1){ + OB_DATA1 = data1; + } + if(0xFFU != wp0){ + OB_WP0 = wp0; + } + if(0xFFU != wp1){ + OB_WP1 = wp1; + } +} diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_fwdgt.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_fwdgt.c new file mode 100644 index 0000000000..a3fcc3c564 --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_fwdgt.c @@ -0,0 +1,180 @@ +/*! + \file gd32f3x0_fwdgt.c + \brief FWDGT driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f3x0_fwdgt.h" + +/*! + \brief enable write access to FWDGT_PSC and FWDGT_RLD + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_write_enable(void) +{ + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; +} + +/*! + \brief disable write access to FWDGT_PSC,FWDGT_RLD and FWDGT_WND + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_write_disable(void) +{ + FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE; +} + +/*! + \brief start the free watchdog timer counter + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_enable(void) +{ + FWDGT_CTL = FWDGT_KEY_ENABLE; +} + +/*! + \brief configure the free watchdog timer counter window value + \param[in] window_value: specify window value(0x0000 - 0x0FFF) + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus fwdgt_window_value_config(uint16_t window_value) +{ + uint32_t time_index = FWDGT_WND_TIMEOUT; + uint32_t flag_status = RESET; + + /* enable write access to FWDGT_WND */ + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; + + /* wait until the WUD flag to be reset */ + do{ + flag_status = FWDGT_STAT & FWDGT_STAT_WUD; + }while((--time_index > 0U) && (RESET != flag_status)); + + if (RESET != flag_status){ + return ERROR; + } + + FWDGT_WND = WND_WND(window_value); + + return SUCCESS; +} + +/*! + \brief reload the counter of FWDGT + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_counter_reload(void) +{ + FWDGT_CTL = FWDGT_KEY_RELOAD; +} + + +/*! + \brief configure counter reload value, and prescaler divider value + \param[in] reload_value: specify reload value(0x0000 - 0x0FFF) + \param[in] prescaler_div: FWDGT prescaler value + only one parameter can be selected which is shown as below: + \arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4 + \arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8 + \arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16 + \arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32 + \arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64 + \arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128 + \arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256 + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div) +{ + uint32_t timeout = FWDGT_PSC_TIMEOUT; + uint32_t flag_status = RESET; + + /* enable write access to FWDGT_PSC,and FWDGT_RLD */ + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; + + /* wait until the PUD flag to be reset */ + do{ + flag_status = FWDGT_STAT & FWDGT_STAT_PUD; + }while((--timeout > 0U) && (RESET != flag_status)); + + if (RESET != flag_status){ + return ERROR; + } + + /* configure FWDGT */ + FWDGT_PSC = (uint32_t)prescaler_div; + + timeout = FWDGT_RLD_TIMEOUT; + /* wait until the RUD flag to be reset */ + do{ + flag_status = FWDGT_STAT & FWDGT_STAT_RUD; + }while((--timeout > 0U) && (RESET != flag_status)); + + if (RESET != flag_status){ + return ERROR; + } + + FWDGT_RLD = RLD_RLD(reload_value); + + /* reload the counter */ + FWDGT_CTL = FWDGT_KEY_RELOAD; + + return SUCCESS; +} + +/*! + \brief get flag state of FWDGT + \param[in] flag: flag to get + only one parameter can be selected which is shown as below: + \arg FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going + \arg FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going + \arg FWDGT_FLAG_WUD: a write operation to FWDGT_WND register is on going + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus fwdgt_flag_get(uint16_t flag) +{ + if(FWDGT_STAT & flag){ + return SET; + } + return RESET; +} diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_gpio.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_gpio.c new file mode 100644 index 0000000000..6af393fe13 --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_gpio.c @@ -0,0 +1,424 @@ +/*! + \file gd32f3x0_gpio.c + \brief GPIO driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f3x0_gpio.h" + +/*! + \brief reset GPIO port + \param[in] gpio_periph: GPIOx(x = A,B,C,D,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,F) + \param[out] none + \retval none +*/ +void gpio_deinit(uint32_t gpio_periph) +{ + switch(gpio_periph){ + case GPIOA: + /* reset GPIOA */ + rcu_periph_reset_enable(RCU_GPIOARST); + rcu_periph_reset_disable(RCU_GPIOARST); + break; + case GPIOB: + /* reset GPIOB */ + rcu_periph_reset_enable(RCU_GPIOBRST); + rcu_periph_reset_disable(RCU_GPIOBRST); + break; + case GPIOC: + /* reset GPIOC */ + rcu_periph_reset_enable(RCU_GPIOCRST); + rcu_periph_reset_disable(RCU_GPIOCRST); + break; + case GPIOD: + /* reset GPIOD */ + rcu_periph_reset_enable(RCU_GPIODRST); + rcu_periph_reset_disable(RCU_GPIODRST); + break; + case GPIOF: + /* reset GPIOF */ + rcu_periph_reset_enable(RCU_GPIOFRST); + rcu_periph_reset_disable(RCU_GPIOFRST); + break; + default: + break; + } +} + +/*! + \brief set GPIO mode + \param[in] gpio_periph: GPIOx(x = A,B,C,D,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,F) + \param[in] mode: gpio pin mode + only one parameter can be selected which is shown as below: + \arg GPIO_MODE_INPUT: input mode + \arg GPIO_MODE_OUTPUT: output mode + \arg GPIO_MODE_AF: alternate function mode + \arg GPIO_MODE_ANALOG: analog mode + \param[in] pull_up_down: gpio pin with pull-up or pull-down resistor + only one parameter can be selected which is shown as below: + \arg GPIO_PUPD_NONE: floating mode, no pull-up and pull-down resistors + \arg GPIO_PUPD_PULLUP: with pull-up resistor + \arg GPIO_PUPD_PULLDOWN:with pull-down resistor + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, uint32_t pin) +{ + uint16_t i; + uint32_t ctl, pupd; + + ctl = GPIO_CTL(gpio_periph); + pupd = GPIO_PUD(gpio_periph); + + for(i = 0U;i < 16U;i++){ + if((1U << i) & pin){ + /* clear the specified pin mode bits */ + ctl &= ~GPIO_MODE_MASK(i); + /* set the specified pin mode bits */ + ctl |= GPIO_MODE_SET(i, mode); + + /* clear the specified pin pupd bits */ + pupd &= ~GPIO_PUPD_MASK(i); + /* set the specified pin pupd bits */ + pupd |= GPIO_PUPD_SET(i, pull_up_down); + } + } + + GPIO_CTL(gpio_periph) = ctl; + GPIO_PUD(gpio_periph) = pupd; +} + +/*! + \brief set GPIO output type and speed + \param[in] gpio_periph: GPIOx(x = A,B,C,D,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,F) + \param[in] otype: gpio pin output mode + only one parameter can be selected which is shown as below: + \arg GPIO_OTYPE_PP: push pull mode + \arg GPIO_OTYPE_OD: open drain mode + \param[in] speed: gpio pin output max speed + only one parameter can be selected which is shown as below: + \arg GPIO_OSPEED_2MHZ: output max speed 2MHz + \arg GPIO_OSPEED_10MHZ: output max speed 10MHz + \arg GPIO_OSPEED_50MHZ: output max speed 50MHz + \arg GPIO_OSPEED_MAX: GPIO very high output speed, max speed more than 50MHz + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin) +{ + uint16_t i; + uint32_t ospeed0,ospeed1; + + if(GPIO_OTYPE_OD == otype){ + GPIO_OMODE(gpio_periph) |= (uint32_t)pin; + }else{ + GPIO_OMODE(gpio_periph) &= (uint32_t)(~pin); + } + + /* get the specified pin output speed bits value */ + ospeed0 = GPIO_OSPD0(gpio_periph); + + if(GPIO_OSPEED_MAX == speed){ + ospeed1 = GPIO_OSPD1(gpio_periph); + + for(i = 0U;i < 16U;i++){ + if((1U << i) & pin){ + /* enable very high output speed function of the pin when the corresponding OSPDy(y=0..15) + is "11" (output max speed 50MHz) */ + ospeed0 |= GPIO_OSPEED_SET(i,0x03); + ospeed1 |= (1U << i); + } + } + GPIO_OSPD0(gpio_periph) = ospeed0; + GPIO_OSPD1(gpio_periph) = ospeed1; + }else{ + for(i = 0U;i < 16U;i++){ + if((1U << i) & pin){ + /* clear the specified pin output speed bits */ + ospeed0 &= ~GPIO_OSPEED_MASK(i); + /* set the specified pin output speed bits */ + ospeed0 |= GPIO_OSPEED_SET(i,speed); + } + } + GPIO_OSPD0(gpio_periph) = ospeed0; + } +} + +/*! + \brief set GPIO pin bit + \param[in] gpio_periph: GPIOx(x = A,B,C,D,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,F) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_bit_set(uint32_t gpio_periph, uint32_t pin) +{ + GPIO_BOP(gpio_periph) = (uint32_t)pin; +} + +/*! + \brief reset GPIO pin bit + \param[in] gpio_periph: GPIOx(x = A,B,C,D,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,F) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin) +{ + GPIO_BC(gpio_periph) = (uint32_t)pin; +} + +/*! + \brief write data to the specified GPIO pin + \param[in] gpio_periph: GPIOx(x = A,B,C,D,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,F) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[in] bit_value: SET or RESET + only one parameter can be selected which is shown as below: + \arg RESET: clear the port pin + \arg SET: set the port pin + \param[out] none + \retval none +*/ +void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value) +{ + if(RESET != bit_value){ + GPIO_BOP(gpio_periph) = (uint32_t)pin; + }else{ + GPIO_BC(gpio_periph) = (uint32_t)pin; + } +} + +/*! + \brief write data to the specified GPIO port + \param[in] gpio_periph: GPIOx(x = A,B,C,D,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,F) + \param[in] data: specify the value to be written to the port output control register + \param[out] none + \retval none +*/ +void gpio_port_write(uint32_t gpio_periph, uint16_t data) +{ + GPIO_OCTL(gpio_periph) = (uint32_t)data; +} + +/*! + \brief get GPIO pin input status + \param[in] gpio_periph: GPIOx(x = A,B,C,D,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,F) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval SET or RESET +*/ +FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin) +{ + if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph)&(pin))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief get GPIO all pins input status + \param[in] gpio_periph: GPIOx(x = A,B,C,D,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,F) + \param[out] none + \retval state of GPIO all pins +*/ +uint16_t gpio_input_port_get(uint32_t gpio_periph) +{ + return (uint16_t)GPIO_ISTAT(gpio_periph); +} + +/*! + \brief get GPIO pin output status + \param[in] gpio_periph: GPIOx(x = A,B,C,D,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,F) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval SET or RESET +*/ +FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin) +{ + if((uint32_t)RESET != (GPIO_OCTL(gpio_periph)&(pin))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief get GPIO all pins output status + \param[in] gpio_periph: GPIOx(x = A,B,C,D,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,F) + \param[out] none + \retval state of GPIO all pins +*/ +uint16_t gpio_output_port_get(uint32_t gpio_periph) +{ + return (uint16_t)GPIO_OCTL(gpio_periph); +} + +/*! + \brief set GPIO alternate function + \param[in] gpio_periph: GPIOx(x = A,B,C) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C) + \param[in] alt_func_num: GPIO pin af function, please refer to specific device datasheet + only one parameter can be selected which is shown as below: + \arg GPIO_AF_0: TIMER2, TIMER13, TIMER14, TIMER16, SPI0, SPI1, I2S0, CK_OUT, USART0, CEC, + IFRP, TSI, CTC, I2C0, I2C1, SWDIO, SWCLK + \arg GPIO_AF_1: USART0, USART1, TIMER2, TIMER14, I2C0, I2C1, IFRP, CEC + \arg GPIO_AF_2: TIMER0, TIMER1, TIMER15, TIMER16, I2S0 + \arg GPIO_AF_3: TSI, I2C0, TIMER14 + \arg GPIO_AF_4(port A,B only): USART1, I2C0, I2C1, TIMER13 + \arg GPIO_AF_5(port A,B only): TIMER15, TIMER16, USBFS, I2S0 + \arg GPIO_AF_6(port A,B only): CTC, SPI1 + \arg GPIO_AF_7(port A,B only): CMP0, CMP1 + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_af_set(uint32_t gpio_periph, uint32_t alt_func_num, uint32_t pin) +{ + uint16_t i; + uint32_t afrl, afrh; + + afrl = GPIO_AFSEL0(gpio_periph); + afrh = GPIO_AFSEL1(gpio_periph); + + for(i = 0U;i < 8U;i++){ + if((1U << i) & pin){ + /* clear the specified pin alternate function bits */ + afrl &= ~GPIO_AFR_MASK(i); + afrl |= GPIO_AFR_SET(i,alt_func_num); + } + } + + for(i = 8U;i < 16U;i++){ + if((1U << i) & pin){ + /* clear the specified pin alternate function bits */ + afrh &= ~GPIO_AFR_MASK(i - 8U); + afrh |= GPIO_AFR_SET(i - 8U,alt_func_num); + } + } + + GPIO_AFSEL0(gpio_periph) = afrl; + GPIO_AFSEL1(gpio_periph) = afrh; +} + +/*! + \brief lock GPIO pin bit + \param[in] gpio_periph: GPIOx(x = A,B) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin) +{ + uint32_t lock = 0x00010000U; + lock |= pin; + + /* lock key writing sequence: write 1->write 0->write 1->read 0->read 1 */ + GPIO_LOCK(gpio_periph) = (uint32_t)lock; + GPIO_LOCK(gpio_periph) = (uint32_t)pin; + GPIO_LOCK(gpio_periph) = (uint32_t)lock; + lock = GPIO_LOCK(gpio_periph); + lock = GPIO_LOCK(gpio_periph); +} + +/*! + \brief toggle GPIO pin status + \param[in] gpio_periph: GPIOx(x = A,B,C,D,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,F) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_bit_toggle(uint32_t gpio_periph, uint32_t pin) +{ + GPIO_TG(gpio_periph) = (uint32_t)pin; +} + +/*! + \brief toggle GPIO port status + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,F) + \param[out] none + \retval none +*/ +void gpio_port_toggle(uint32_t gpio_periph) +{ + GPIO_TG(gpio_periph) = 0x0000FFFFU; +} diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_i2c.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_i2c.c new file mode 100644 index 0000000000..2f428b1881 --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_i2c.c @@ -0,0 +1,729 @@ +/*! + \file gd32f3x0_i2c.c + \brief I2C driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f3x0_i2c.h" + +/* I2C register bit mask */ +#define I2CCLK_MAX ((uint32_t)0x0000003FU) /*!< i2cclk maximum value */ +#define I2CCLK_MIN ((uint32_t)0x00000002U) /*!< i2cclk minimum value */ +#define I2C_FLAG_MASK ((uint32_t)0x0000FFFFU) /*!< i2c flag mask */ +#define I2C_ADDRESS_MASK ((uint32_t)0x000003FFU) /*!< i2c address mask */ +#define I2C_ADDRESS2_MASK ((uint32_t)0x000000FEU) /*!< the second i2c address mask */ + +/* I2C register bit offset */ +#define STAT1_PECV_OFFSET ((uint32_t)8U) /* bit offset of PECV in I2C_STAT1 */ + +/*! + \brief reset I2C + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_deinit(uint32_t i2c_periph) +{ + switch(i2c_periph){ + case I2C0: + /* reset I2C0 */ + rcu_periph_reset_enable(RCU_I2C0RST); + rcu_periph_reset_disable(RCU_I2C0RST); + break; + case I2C1: + /* reset I2C1 */ + rcu_periph_reset_enable(RCU_I2C1RST); + rcu_periph_reset_disable(RCU_I2C1RST); + break; + default: + break; + } +} + +/*! + \brief configure I2C clock + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] clkspeed: I2C clock speed, supports standard mode (up to 100 kHz), fast mode (up to 400 kHz) + and fast mode plus (up to 1MHz) + \param[in] dutycyc: duty cycle in fast mode or fast mode plus + only one parameter can be selected which is shown as below: + \arg I2C_DTCY_2: T_low/T_high=2 + \arg I2C_DTCY_16_9: T_low/T_high=16/9 + \param[out] none + \retval none +*/ +void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc) +{ + uint32_t pclk1, clkc, freq, risetime; + uint32_t temp; + + pclk1 = rcu_clock_freq_get(CK_APB1); + /* I2C peripheral clock frequency */ + freq = (uint32_t)(pclk1/1000000U); + if(freq >= I2CCLK_MAX){ + freq = I2CCLK_MAX; + } + temp = I2C_CTL1(i2c_periph); + temp &= ~I2C_CTL1_I2CCLK; + temp |= freq; + + I2C_CTL1(i2c_periph) = temp; + + if(100000U >= clkspeed){ + /* the maximum SCL rise time is 1000ns in standard mode */ + risetime = (uint32_t)((pclk1/1000000U)+1U); + if(risetime >= I2CCLK_MAX){ + I2C_RT(i2c_periph) = I2CCLK_MAX; + }else if(risetime <= I2CCLK_MIN){ + I2C_RT(i2c_periph) = I2CCLK_MIN; + }else{ + I2C_RT(i2c_periph) = risetime; + } + clkc = (uint32_t)(pclk1/(clkspeed*2U)); + if(clkc < 0x04U){ + /* the CLKC in standard mode minmum value is 4 */ + clkc = 0x04U; + } + I2C_CKCFG(i2c_periph) |= (I2C_CKCFG_CLKC & clkc); + + }else if(400000U >= clkspeed){ + /* the maximum SCL rise time is 300ns in fast mode */ + I2C_RT(i2c_periph) = (uint32_t)(((freq*(uint32_t)300U)/(uint32_t)1000U)+(uint32_t)1U); + if(I2C_DTCY_2 == dutycyc){ + /* I2C duty cycle is 2 */ + clkc = (uint32_t)(pclk1/(clkspeed*3U)); + I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY; + }else{ + /* I2C duty cycle is 16/9 */ + clkc = (uint32_t)(pclk1/(clkspeed*25U)); + I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY; + } + if(0U == (clkc & I2C_CKCFG_CLKC)){ + /* the CLKC in fast mode minmum value is 1 */ + clkc |= 0x0001U; + } + I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST; + I2C_CKCFG(i2c_periph) |= clkc; + }else{ + /* fast mode plus, the maximum SCL rise time is 120ns */ + I2C_RT(i2c_periph) = (uint32_t)(((freq*(uint32_t)120U)/(uint32_t)1000U)+(uint32_t)1U); + if(I2C_DTCY_2 == dutycyc){ + /* I2C duty cycle is 2 */ + clkc = (uint32_t)(pclk1/(clkspeed*3U)); + I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY; + }else{ + /* I2C duty cycle is 16/9 */ + clkc = (uint32_t)(pclk1/(clkspeed*25U)); + I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY; + } + /* enable fast mode */ + I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST; + I2C_CKCFG(i2c_periph) |= clkc; + /* enable I2C fast mode plus */ + I2C_FMPCFG(i2c_periph) = I2C_FMPCFG_FMPEN; + } +} + +/*! + \brief configure I2C address + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] mode: + only one parameter can be selected which is shown as below: + \arg I2C_I2CMODE_ENABLE: I2C mode + \arg I2C_SMBUSMODE_ENABLE: SMBus mode + \param[in] addformat: 7bits or 10bits + only one parameter can be selected which is shown as below: + \arg I2C_ADDFORMAT_7BITS: 7bits + \arg I2C_ADDFORMAT_10BITS: 10bits + \param[in] addr: I2C address + \param[out] none + \retval none +*/ +void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr) +{ + /* SMBus/I2C mode selected */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_SMBEN); + ctl |= mode; + I2C_CTL0(i2c_periph) = ctl; + /* configure address */ + addr = addr & I2C_ADDRESS_MASK; + I2C_SADDR0(i2c_periph) = (addformat | addr); +} + +/*! + \brief SMBus type selection + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] type: + only one parameter can be selected which is shown as below: + \arg I2C_SMBUS_DEVICE: device + \arg I2C_SMBUS_HOST: host + \param[out] none + \retval none +*/ +void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type) +{ + if(I2C_SMBUS_HOST == type){ + I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBSEL; + }else{ + I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_SMBSEL); + } +} + +/*! + \brief whether or not to send an ACK + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] ack: + only one parameter can be selected which is shown as below: + \arg I2C_ACK_ENABLE: ACK will be sent + \arg I2C_ACK_DISABLE: ACK will not be sent + \param[out] none + \retval none +*/ +void i2c_ack_config(uint32_t i2c_periph, uint32_t ack) +{ + if(I2C_ACK_ENABLE == ack){ + I2C_CTL0(i2c_periph) |= I2C_CTL0_ACKEN; + }else{ + I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_ACKEN); + } +} + +/*! + \brief configure I2C position of ACK and PEC when receiving + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] pos: + only one parameter can be selected which is shown as below: + \arg I2C_ACKPOS_CURRENT: whether to send ACK or not for the current + \arg I2C_ACKPOS_NEXT: whether to send ACK or not for the next byte + \param[out] none + \retval none +*/ +void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos) +{ + /* configure I2C POAP position */ + if(I2C_ACKPOS_NEXT == pos){ + I2C_CTL0(i2c_periph) |= I2C_CTL0_POAP; + }else{ + I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_POAP); + } +} + +/*! + \brief master sends slave address + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] addr: slave address + \param[in] trandirection: transmitter or receiver + only one parameter can be selected which is shown as below: + \arg I2C_TRANSMITTER: transmitter + \arg I2C_RECEIVER: receiver + \param[out] none + \retval none +*/ +void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection) +{ + /* master is a transmitter or a receiver */ + if(I2C_TRANSMITTER == trandirection){ + addr = addr & I2C_TRANSMITTER; + }else{ + addr = addr | I2C_RECEIVER; + } + /* send slave address */ + I2C_DATA(i2c_periph) = addr; +} + +/*! + \brief enable dual-address mode + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] addr: the second address in dual-address mode + \param[out] none + \retval none +*/ +void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr) +{ + /* configure address */ + addr = addr & I2C_ADDRESS2_MASK; + I2C_SADDR1(i2c_periph) = (I2C_SADDR1_DUADEN | addr); +} + +/*! + \brief disable dual-address mode + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_dualaddr_disable(uint32_t i2c_periph) +{ + I2C_SADDR1(i2c_periph) &= ~(I2C_SADDR1_DUADEN); +} + +/*! + \brief enable I2C + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_enable(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) |= I2C_CTL0_I2CEN; +} + +/*! + \brief disable I2C + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_disable(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_I2CEN); +} + +/*! + \brief generate a START condition on I2C bus + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_start_on_bus(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) |= I2C_CTL0_START; +} + +/*! + \brief generate a STOP condition on I2C bus + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_stop_on_bus(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) |= I2C_CTL0_STOP; +} + +/*! + \brief I2C transmit data function + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] data: data of transmission + \param[out] none + \retval none +*/ +void i2c_data_transmit(uint32_t i2c_periph, uint8_t data) +{ + I2C_DATA(i2c_periph) = DATA_TRANS(data); +} + +/*! + \brief I2C receive data function + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval data of received +*/ +uint8_t i2c_data_receive(uint32_t i2c_periph) +{ + return (uint8_t)DATA_RECV(I2C_DATA(i2c_periph)); +} + +/*! + \brief enable I2C DMA mode + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] dmastate: + only one parameter can be selected which is shown as below: + \arg I2C_DMA_ON: DMA mode enable + \arg I2C_DMA_OFF: DMA mode disable + \param[out] none + \retval none +*/ +void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate) +{ + /* configure I2C DMA function */ + uint32_t ctl = 0U; + + ctl = I2C_CTL1(i2c_periph); + ctl &= ~(I2C_CTL1_DMAON); + ctl |= dmastate; + I2C_CTL1(i2c_periph) = ctl; +} + +/*! + \brief configure whether next DMA EOT is DMA last transfer or not + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] dmalast: + only one parameter can be selected which is shown as below: + \arg I2C_DMALST_ON: next DMA EOT is the last transfer + \arg I2C_DMALST_OFF: next DMA EOT is not the last transfer + \param[out] none + \retval none +*/ +void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast) +{ + /* configure DMA last transfer */ + uint32_t ctl = 0U; + + ctl = I2C_CTL1(i2c_periph); + ctl &= ~(I2C_CTL1_DMALST); + ctl |= dmalast; + I2C_CTL1(i2c_periph) = ctl; +} + +/*! + \brief whether to stretch SCL low when data is not ready in slave mode + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] stretchpara: + only one parameter can be selected which is shown as below: + \arg I2C_SCLSTRETCH_ENABLE: SCL stretching is enabled + \arg I2C_SCLSTRETCH_DISABLE: SCL stretching is disabled + \param[out] none + \retval none +*/ +void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara) +{ + /* configure I2C SCL strerching enable or disable */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_SS); + ctl |= stretchpara; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief whether or not to response to a general call + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] gcallpara: + only one parameter can be selected which is shown as below: + \arg I2C_GCEN_ENABLE: slave will response to a general call + \arg I2C_GCEN_DISABLE: slave will not response to a general call + \param[out] none + \retval none +*/ +void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara) +{ + /* configure slave response to a general call enable or disable */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_GCEN); + ctl |= gcallpara; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief software reset I2C + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] sreset: + only one parameter can be selected which is shown as below: + \arg I2C_SRESET_SET: I2C is under reset + \arg I2C_SRESET_RESET: I2C is not under reset + \param[out] none + \retval none +*/ +void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset) +{ + /* modify CTL0 and configure software reset I2C state */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_SRESET); + ctl |= sreset; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief whether to enable I2C PEC calculation or not + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] pecpara: + only one parameter can be selected which is shown as below: + \arg I2C_PEC_ENABLE: PEC calculation on + \arg I2C_PEC_DISABLE: PEC calculation off + \param[out] none + \retval none +*/ +void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate) +{ + /* on/off PEC calculation */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_PECEN); + ctl |= pecstate; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief I2C whether to transfer PEC value + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] pecpara: + only one parameter can be selected which is shown as below: + \arg I2C_PECTRANS_ENABLE: transfer PEC + \arg I2C_PECTRANS_DISABLE: not transfer PEC + \param[out] none + \retval none +*/ +void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara) +{ + /* whether to transfer PEC */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_PECTRANS); + ctl |= pecpara; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief get packet error checking value + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval PEC value +*/ +uint8_t i2c_pec_value_get(uint32_t i2c_periph) +{ + return (uint8_t)((I2C_STAT1(i2c_periph) & I2C_STAT1_PECV)>>STAT1_PECV_OFFSET); +} + +/*! + \brief I2C issue alert through SMBA pin + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] smbuspara: + only one parameter can be selected which is shown as below: + \arg I2C_SALTSEND_ENABLE: issue alert through SMBA pin + \arg I2C_SALTSEND_DISABLE: not issue alert through SMBA pin + \param[out] none + \retval none +*/ +void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara) +{ + /* issue alert through SMBA pin configure*/ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_SALT); + ctl |= smbuspara; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief whether ARP is enabled under SMBus + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] arpstate: + only one parameter can be selected which is shown as below: + \arg I2C_ARP_ENABLE: enable ARP + \arg I2C_ARP_DISABLE: disable ARP + \param[out] none + \retval none +*/ +void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate) +{ + /* enable or disable I2C ARP protocol */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_ARPEN); + ctl |= arpstate; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief check I2C flag is set or not + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] flag: I2C flags, refer to i2c_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_FLAG_SBSEND: start condition send out + \arg I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode + \arg I2C_FLAG_BTC: byte transmission finishes + \arg I2C_FLAG_ADD10SEND: header of 10-bit address is sent in master mode + \arg I2C_FLAG_STPDET: stop condition detected in slave mode + \arg I2C_FLAG_RBNE: I2C_DATA is not empty during receiving + \arg I2C_FLAG_TBE: I2C_DATA is empty during transmitting + \arg I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus + \arg I2C_FLAG_LOSTARB: arbitration lost in master mode + \arg I2C_FLAG_AERR: acknowledge error + \arg I2C_FLAG_OUERR: overrun or underrun situation occurs in slave mode + \arg I2C_FLAG_PECERR: PEC error when receiving data + \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode + \arg I2C_FLAG_SMBALT: SMBus alert status + \arg I2C_FLAG_MASTER: a flag indicating whether I2C block is in master or slave mode + \arg I2C_FLAG_I2CBSY: busy flag + \arg I2C_FLAG_TR: whether the I2C is a transmitter or a receiver + \arg I2C_FLAG_RXGC: general call address (00h) received + \arg I2C_FLAG_DEFSMB: default address of SMBus device + \arg I2C_FLAG_HSTSMB: SMBus host header detected in slave mode + \arg I2C_FLAG_DUMOD: dual flag in slave mode indicating which address is matched in dual-address mode + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag) +{ + if(RESET != (I2C_REG_VAL(i2c_periph, flag) & BIT(I2C_BIT_POS(flag)))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear I2C flag + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] flag: I2C flags, refer to i2c_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_FLAG_SMBALT: SMBus Alert status + \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode + \arg I2C_FLAG_PECERR: PEC error when receiving data + \arg I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode + \arg I2C_FLAG_AERR: acknowledge error + \arg I2C_FLAG_LOSTARB: arbitration lost in master mode + \arg I2C_FLAG_BERR: a bus error + \arg I2C_FLAG_ADDSEND: cleared by reading I2C_STAT0 and reading I2C_STAT1 + \param[out] none + \retval none +*/ +void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag) +{ + if(I2C_FLAG_ADDSEND == flag){ + /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ + I2C_STAT0(i2c_periph); + I2C_STAT1(i2c_periph); + }else{ + I2C_REG_VAL(i2c_periph, flag) &= ~BIT(I2C_BIT_POS(flag)); + } +} + +/*! + \brief enable I2C interrupt + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] interrupt: I2C interrupts, refer to i2c_interrupt_enum + only one parameter can be selected which is shown as below: + \arg I2C_INT_ERR: error interrupt enable + \arg I2C_INT_EV: event interrupt enable + \arg I2C_INT_BUF: buffer interrupt enable + \param[out] none + \retval none +*/ +void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) +{ + I2C_REG_VAL(i2c_periph, interrupt) |= BIT(I2C_BIT_POS(interrupt)); +} + +/*! + \brief disable I2C interrupt + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] interrupt: interrupt type + only one parameter can be selected which is shown as below: + \arg I2C_INT_ERR: error interrupt enable + \arg I2C_INT_EV: event interrupt enable + \arg I2C_INT_BUF: buffer interrupt enable + \param[out] none + \retval none +*/ +void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) +{ + I2C_REG_VAL(i2c_periph, interrupt) &= ~BIT(I2C_BIT_POS(interrupt)); +} + +/*! + \brief check I2C interrupt flag + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_INT_FLAG_SBSEND: start condition sent out in master mode interrupt flag + \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag + \arg I2C_INT_FLAG_BTC: byte transmission finishes + \arg I2C_INT_FLAG_ADD10SEND: header of 10-bit address is sent in master mode interrupt flag + \arg I2C_INT_FLAG_STPDET: etop condition detected in slave mode interrupt flag + \arg I2C_INT_FLAG_RBNE: I2C_DATA is not Empty during receiving interrupt flag + \arg I2C_INT_FLAG_TBE: I2C_DATA is empty during transmitting interrupt flag + \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag + \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag + \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag + \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag + \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag + \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag + \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) +{ + uint32_t intenable = 0U, flagstatus = 0U, bufie; + + /* check BUFIE */ + bufie = I2C_CTL1(i2c_periph)&I2C_CTL1_BUFIE; + + /* get the interrupt enable bit status */ + intenable = (I2C_REG_VAL(i2c_periph, int_flag) & BIT(I2C_BIT_POS(int_flag))); + /* get the corresponding flag bit status */ + flagstatus = (I2C_REG_VAL2(i2c_periph, int_flag) & BIT(I2C_BIT_POS2(int_flag))); + + if((I2C_INT_FLAG_RBNE == int_flag) || (I2C_INT_FLAG_TBE == int_flag)){ + if(intenable && bufie){ + intenable = 1U; + }else{ + intenable = 0U; + } + } + if((0U != flagstatus) && (0U != intenable)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear I2C interrupt flag + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] intflag: I2C interrupt flags, refer to i2c_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag + \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag + \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag + \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag + \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag + \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag + \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag + \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag + \param[out] none + \retval none +*/ +void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) +{ + if(I2C_INT_FLAG_ADDSEND == int_flag){ + /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ + I2C_STAT0(i2c_periph); + I2C_STAT1(i2c_periph); + }else{ + I2C_REG_VAL2(i2c_periph, int_flag) &= ~BIT(I2C_BIT_POS2(int_flag)); + } +} + diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_misc.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_misc.c new file mode 100644 index 0000000000..d467c32b82 --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_misc.c @@ -0,0 +1,189 @@ +/*! + \file gd32f3x0_misc.c + \brief MISC driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f3x0_misc.h" + +/*! + \brief set the priority group + \param[in] nvic_prigroup: the NVIC priority group + only one parameter can be selected which is shown as below: + \arg NVIC_PRIGROUP_PRE0_SUB4:0 bits for pre-emption priority 4 bits for subpriority + \arg NVIC_PRIGROUP_PRE1_SUB3:1 bits for pre-emption priority 3 bits for subpriority + \arg NVIC_PRIGROUP_PRE2_SUB2:2 bits for pre-emption priority 2 bits for subpriority + \arg NVIC_PRIGROUP_PRE3_SUB1:3 bits for pre-emption priority 1 bits for subpriority + \arg NVIC_PRIGROUP_PRE4_SUB0:4 bits for pre-emption priority 0 bits for subpriority + \param[out] none + \retval none +*/ +void nvic_priority_group_set(uint32_t nvic_prigroup) +{ + /* set the priority group value */ + SCB->AIRCR = NVIC_AIRCR_VECTKEY_MASK | nvic_prigroup; +} + +/*! + \brief enable NVIC request + \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type + \param[in] nvic_irq_pre_priority: the pre-emption priority needed to set + \param[in] nvic_irq_sub_priority: the subpriority needed to set + \param[out] none + \retval none +*/ +void nvic_irq_enable(uint8_t nvic_irq, + uint8_t nvic_irq_pre_priority, + uint8_t nvic_irq_sub_priority) +{ + uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U; + + /* use the priority group value to get the temp_pre and the temp_sub */ + switch ((SCB->AIRCR) & (uint32_t)0x700U) { + case NVIC_PRIGROUP_PRE0_SUB4: + temp_pre = 0U; + temp_sub = 0x4U; + break; + case NVIC_PRIGROUP_PRE1_SUB3: + temp_pre = 1U; + temp_sub = 0x3U; + break; + case NVIC_PRIGROUP_PRE2_SUB2: + temp_pre = 2U; + temp_sub = 0x2U; + break; + case NVIC_PRIGROUP_PRE3_SUB1: + temp_pre = 3U; + temp_sub = 0x1U; + break; + case NVIC_PRIGROUP_PRE4_SUB0: + temp_pre = 4U; + temp_sub = 0x0U; + break; + default: + nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2); + temp_pre = 2U; + temp_sub = 0x2U; + break; + } + + /* get the temp_priority to fill the NVIC->IP register */ + temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre); + temp_priority |= nvic_irq_sub_priority &(0x0FU >> (0x4U - temp_sub)); + temp_priority = temp_priority << 0x04U; + NVIC->IP[nvic_irq] = (uint8_t)temp_priority; + + /* enable the selected IRQ */ + NVIC->ISER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU); +} + +/*! + \brief disable NVIC request + \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type + \param[out] none + \retval none +*/ +void nvic_irq_disable(uint8_t nvic_irq) +{ + /* disable the selected IRQ.*/ + NVIC->ICER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU); +} + +/*! + \brief set the NVIC vector table base address + \param[in] nvic_vict_tab: the RAM or FLASH base address + only one parameter can be selected which is shown as below: + \arg NVIC_VECTTAB_RAM: RAM base address + \are NVIC_VECTTAB_FLASH: Flash base address + \param[in] offset: Vector Table offset + \param[out] none + \retval none +*/ +void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset) +{ + SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK); +} + +/*! + \brief set the state of the low power mode + \param[in] lowpower_mode: the low power mode state + only one parameter can be selected which is shown as below: + \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power + mode by exiting from ISR + \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode + \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up + by all the enable and disable interrupts + \param[out] none + \retval none +*/ +void system_lowpower_set(uint8_t lowpower_mode) +{ + SCB->SCR |= (uint32_t)lowpower_mode; +} + +/*! + \brief reset the state of the low power mode + \param[in] lowpower_mode: the low power mode state + only one parameter can be selected which is shown as below: + \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power + mode by exiting from ISR + \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode + \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be + woke up by the enable interrupts + \param[out] none + \retval none +*/ +void system_lowpower_reset(uint8_t lowpower_mode) +{ + SCB->SCR &= (~(uint32_t)lowpower_mode); +} + +/*! + \brief set the systick clock source + \param[in] systick_clksource: the systick clock source needed to choose + only one parameter can be selected which is shown as below: + \arg SYSTICK_CLKSOURCE_HCLK: systick clock source is from HCLK + \arg SYSTICK_CLKSOURCE_HCLK_DIV8: systick clock source is from HCLK/8 + \param[out] none + \retval none +*/ + +void systick_clksource_set(uint32_t systick_clksource) +{ + if(SYSTICK_CLKSOURCE_HCLK == systick_clksource ){ + /* set the systick clock source from HCLK */ + SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + }else{ + /* set the systick clock source from HCLK/8 */ + SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8; + } +} diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_pmu.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_pmu.c new file mode 100644 index 0000000000..c537c600da --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_pmu.c @@ -0,0 +1,407 @@ +/*! + \file gd32f3x0_pmu.c + \brief PMU driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f3x0_pmu.h" + + +/*! + \brief reset PMU register + \param[in] none + \param[out] none + \retval none +*/ +void pmu_deinit(void) +{ + /* reset PMU */ + rcu_periph_reset_enable(RCU_PMURST); + rcu_periph_reset_disable(RCU_PMURST); +} + +/*! + \brief select low voltage detector threshold + \param[in] lvdt_n: + only one parameter can be selected which is shown as below: + \arg PMU_LVDT_0: voltage threshold is 2.1V + \arg PMU_LVDT_1: voltage threshold is 2.3V + \arg PMU_LVDT_2: voltage threshold is 2.4V + \arg PMU_LVDT_3: voltage threshold is 2.6V + \arg PMU_LVDT_4: voltage threshold is 2.7V + \arg PMU_LVDT_5: voltage threshold is 2.9V + \arg PMU_LVDT_6: voltage threshold is 3.0V + \arg PMU_LVDT_7: voltage threshold is 3.1V + \param[out] none + \retval none +*/ +void pmu_lvd_select(uint32_t lvdt_n) +{ + /* disable LVD */ + PMU_CTL &= ~PMU_CTL_LVDEN; + /* clear LVDT bits */ + PMU_CTL &= ~PMU_CTL_LVDT; + /* set LVDT bits according to lvdt_n */ + PMU_CTL |= lvdt_n; + /* enable LVD */ + PMU_CTL |= PMU_CTL_LVDEN; +} + +/*! + \brief select LDO output voltage + these bits set by software when the main PLL closed + \param[in] ldo_output: + only one parameter can be selected which is shown as below: + \arg PMU_LDOVS_LOW: LDO output voltage low mode + \arg PMU_LDOVS_MID: LDO output voltage mid mode + \arg PMU_LDOVS_HIGH: LDO output voltage high mode + \param[out] none + \retval none +*/ +void pmu_ldo_output_select(uint32_t ldo_output) +{ + PMU_CTL &= ~PMU_CTL_LDOVS; + PMU_CTL |= ldo_output; +} + +/*! + \brief disable PMU lvd + \param[in] none + \param[out] none + \retval none +*/ +void pmu_lvd_disable(void) +{ + /* disable LVD */ + PMU_CTL &= ~PMU_CTL_LVDEN; +} + +/*! + \brief enable low-driver mode in deep-sleep mode + \param[in] none + \param[out] none + \retval none +*/ +void pmu_lowdriver_mode_enable(void) +{ + PMU_CTL &= ~PMU_CTL_LDEN; + PMU_CTL |= PMU_LOWDRIVER_ENABLE; +} + +/*! + \brief disable low-driver mode in deep-sleep mode + \param[in] none + \param[out] none + \retval none +*/ +void pmu_lowdriver_mode_disable(void) +{ + PMU_CTL &= ~PMU_CTL_LDEN; + PMU_CTL |= PMU_LOWDRIVER_DISABLE; +} + +/*! + \brief enable high-driver mode + this bit set by software only when IRC8M or HXTAL used as system clock + \param[in] none + \param[out] none + \retval none +*/ +void pmu_highdriver_mode_enable(void) +{ + PMU_CTL |= PMU_CTL_HDEN; +} + +/*! + \brief disable high-driver mode + \param[in] none + \param[out] none + \retval none +*/ +void pmu_highdriver_mode_disable(void) +{ + PMU_CTL &= ~PMU_CTL_HDEN; +} + +/*! + \brief switch high-driver mode + this bit set by software only when IRC8M or HXTAL used as system clock + \param[in] highdr_switch: + only one parameter can be selected which is shown as below: + \arg PMU_HIGHDR_SWITCH_NONE: disable high-driver mode switch + \arg PMU_HIGHDR_SWITCH_EN: enable high-driver mode switch + \param[out] none + \retval none +*/ +void pmu_highdriver_switch_select(uint32_t highdr_switch) +{ + /* wait for HDRF flag to be set */ + while(SET != pmu_flag_get(PMU_FLAG_HDR)){ + } + PMU_CTL &= ~PMU_CTL_HDS; + PMU_CTL |= highdr_switch; +} + +/*! + \brief low-driver mode when use low power LDO + \param[in] mode: + only one parameter can be selected which is shown as below: + \arg PMU_NORMALDR_LOWPWR: normal-driver when use low power LDO + \arg PMU_LOWDR_LOWPWR: low-driver mode enabled when LDEN is 11 and use low power LDO + \param[out] none + \retval none +*/ +void pmu_lowpower_driver_config(uint32_t mode) +{ + PMU_CTL &= ~PMU_CTL_LDLP; + PMU_CTL |= mode; +} + +/*! + \brief low-driver mode when use normal power LDO + \param[in] mode: + only one parameter can be selected which is shown as below: + \arg PMU_NORMALDR_NORMALPWR: normal-driver when use low power LDO + \arg PMU_LOWDR_NORMALPWR: low-driver mode enabled when LDEN is 11 and use low power LDO + \param[out] none + \retval none +*/ +void pmu_normalpower_driver_config(uint32_t mode) +{ + PMU_CTL &= ~PMU_CTL_LDNP; + PMU_CTL |= mode; +} + +/*! + \brief PMU work at sleep mode + \param[in] sleepmodecmd: + only one parameter can be selected which is shown as below: + \arg WFI_CMD: use WFI command + \arg WFE_CMD: use WFE command + \param[out] none + \retval none +*/ +void pmu_to_sleepmode(uint8_t sleepmodecmd) +{ + /* clear sleepdeep bit of Cortex-M4 system control register */ + SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + + /* select WFI or WFE command to enter sleep mode */ + if(WFI_CMD == sleepmodecmd){ + __WFI(); + }else{ + __WFE(); + } +} + +/*! + \brief PMU work at deepsleep mode + \param[in] ldo: + only one parameter can be selected which is shown as below: + \arg PMU_LDO_NORMAL: LDO operates normally when pmu enter deepsleep mode + \arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode + \param[in] deepsleepmodecmd: + only one parameter can be selected which is shown as below: + \arg WFI_CMD: use WFI command + \arg WFE_CMD: use WFE command + \param[out] none + \retval none +*/ +void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd) +{ + static uint32_t reg_snap[ 4 ]; + /* clear stbmod and ldolp bits */ + PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP)); + + /* set ldolp bit according to pmu_ldo */ + PMU_CTL |= ldo; + + /* set sleepdeep bit of Cortex-M4 system control register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + reg_snap[ 0 ] = REG32( 0xE000E010U ); + reg_snap[ 1 ] = REG32( 0xE000E100U ); + reg_snap[ 2 ] = REG32( 0xE000E104U ); + reg_snap[ 3 ] = REG32( 0xE000E108U ); + + REG32( 0xE000E010U ) &= 0x00010004U; + REG32( 0xE000E180U ) = 0XB7FFEF19U; + REG32( 0xE000E184U ) = 0XFFFFFBFFU; + REG32( 0xE000E188U ) = 0xFFFFFFFFU; + + /* select WFI or WFE command to enter deepsleep mode */ + if(WFI_CMD == deepsleepmodecmd){ + __WFI(); + }else{ + __SEV(); + __WFE(); + __WFE(); + } + + REG32( 0xE000E010U ) = reg_snap[ 0 ] ; + REG32( 0xE000E100U ) = reg_snap[ 1 ] ; + REG32( 0xE000E104U ) = reg_snap[ 2 ] ; + REG32( 0xE000E108U ) = reg_snap[ 3 ] ; + + /* reset sleepdeep bit of Cortex-M4 system control register */ + SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); +} + +/*! + \brief pmu work at standby mode + \param[in] standbymodecmd: + only one parameter can be selected which is shown as below: + \arg WFI_CMD: use WFI command + \arg WFE_CMD: use WFE command + \param[out] none + \retval none +*/ +void pmu_to_standbymode(uint8_t standbymodecmd) +{ + /* set sleepdeep bit of Cortex-M4 system control register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* set stbmod bit */ + PMU_CTL |= PMU_CTL_STBMOD; + + /* reset wakeup flag */ + PMU_CTL |= PMU_CTL_WURST; + + /* select WFI or WFE command to enter standby mode */ + if(WFI_CMD == standbymodecmd){ + __WFI(); + }else{ + __WFE(); + } +} + +/*! + \brief enable wakeup pin + \param[in] wakeup_pin: + one or more parameters can be selected which are shown as below: + \arg PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0) + \arg PMU_WAKEUP_PIN1: WKUP Pin 1 (PC13) + \arg PMU_WAKEUP_PIN4: WKUP Pin 4 (PC5) + \arg PMU_WAKEUP_PIN5: WKUP Pin 5 (PB5) + \arg PMU_WAKEUP_PIN6: WKUP Pin 6 (PB15) + \param[out] none + \retval none +*/ +void pmu_wakeup_pin_enable(uint32_t wakeup_pin) +{ + PMU_CS |= wakeup_pin; +} + +/*! + \brief disable wakeup pin + \param[in] wakeup_pin: + one or more parameters can be selected which are shown as below: + \arg PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0) + \arg PMU_WAKEUP_PIN1: WKUP Pin 1 (PC13) + \arg PMU_WAKEUP_PIN4: WKUP Pin 4 (PC5) + \arg PMU_WAKEUP_PIN5: WKUP Pin 5 (PB5) + \arg PMU_WAKEUP_PIN6: WKUP Pin 6 (PB15) + \param[out] none + \retval none +*/ +void pmu_wakeup_pin_disable(uint32_t wakeup_pin) +{ + PMU_CS &= ~(wakeup_pin); +} + +/*! + \brief enable backup domain write + \param[in] none + \param[out] none + \retval none +*/ +void pmu_backup_write_enable(void) +{ + PMU_CTL |= PMU_CTL_BKPWEN; +} + +/*! + \brief disable backup domain write + \param[in] none + \param[out] none + \retval none +*/ +void pmu_backup_write_disable(void) +{ + PMU_CTL &= ~PMU_CTL_BKPWEN; +} + +/*! + \brief clear flag bit + \param[in] flag_clear: + one or more parameters can be selected which are shown as below: + \arg PMU_FLAG_RESET_WAKEUP: reset wakeup flag + \arg PMU_FLAG_RESET_STANDBY: reset standby flag + \param[out] none + \retval none +*/ +void pmu_flag_clear(uint32_t flag_clear) +{ + if(RESET != (flag_clear & PMU_FLAG_RESET_WAKEUP)){ + /* reset wakeup flag */ + PMU_CTL |= PMU_CTL_WURST; + } + if(RESET != (flag_clear & PMU_FLAG_RESET_STANDBY)){ + /* reset standby flag */ + PMU_CTL |= PMU_CTL_STBRST; + } +} + +/*! + \brief get flag state + \param[in] flag: + only one parameter can be selected which is shown as below: + \arg PMU_FLAG_WAKEUP: wakeup flag + \arg PMU_FLAG_STANDBY: standby flag + \arg PMU_FLAG_LVD: lvd flag + \arg PMU_FLAG_LDOVSR: LDO voltage select ready flag + \arg PMU_FLAG_HDR: high-driver ready flag + \arg PMU_FLAG_HDSR: high-driver switch ready flag + \arg PMU_FLAG_LDR: low-driver mode ready flag + \param[out] none + \retval FlagStatus SET or RESET +*/ +FlagStatus pmu_flag_get(uint32_t flag) +{ + FlagStatus ret_status = RESET; + + if(PMU_CS & flag){ + ret_status = SET; + } + + return ret_status; +} diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_rcu.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_rcu.c new file mode 100644 index 0000000000..980092bd5f --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_rcu.c @@ -0,0 +1,1204 @@ +/*! + \file gd32f3x0_rcu.c + \brief RCU driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f3x0_rcu.h" + +/* define clock source */ +#define SEL_IRC8M ((uint32_t)0x00000000U) +#define SEL_HXTAL ((uint32_t)0x00000001U) +#define SEL_PLL ((uint32_t)0x00000002U) + +/* define startup timeout count */ +#define OSC_STARTUP_TIMEOUT ((uint32_t)0x000FFFFFU) +#define LXTAL_STARTUP_TIMEOUT ((uint32_t)0x03FFFFFFU) + +/*! + \brief deinitialize the RCU + \param[in] none + \param[out] none + \retval none +*/ +void rcu_deinit(void) +{ + /* enable IRC8M */ + RCU_CTL0 |= RCU_CTL0_IRC8MEN; + while(0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)){ + } + /* reset RCU */ + RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |\ + RCU_CFG0_ADCPSC | RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV); + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV); +#if (defined(GD32F350)) + RCU_CFG0 &= ~(RCU_CFG0_USBFSPSC); + RCU_CFG2 &= ~(RCU_CFG2_CECSEL | RCU_CFG2_USBFSPSC2); +#endif /* GD32F350 */ + RCU_CTL0 &= ~(RCU_CTL0_HXTALEN | RCU_CTL0_CKMEN | RCU_CTL0_PLLEN | RCU_CTL0_HXTALBPS); + RCU_CFG1 &= ~(RCU_CFG1_PREDV | RCU_CFG1_PLLMF5 | RCU_CFG1_PLLPRESEL); + RCU_CFG2 &= ~(RCU_CFG2_USART0SEL | RCU_CFG2_ADCSEL); + RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV; + RCU_CFG2 &= ~RCU_CFG2_ADCPSC2; + RCU_CTL1 &= ~RCU_CTL1_IRC28MEN; + RCU_ADDCTL &= ~RCU_ADDCTL_IRC48MEN; + RCU_INT = 0x00000000U; + RCU_ADDINT = 0x00000000U; +} + +/*! + \brief enable the peripherals clock + \param[in] periph: RCU peripherals, refer to rcu_periph_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOx (x=A,B,C,D,F): GPIO ports clock + \arg RCU_DMA: DMA clock + \arg RCU_CRC: CRC clock + \arg RCU_TSI: TSI clock + \arg RCU_CFGCMP: CFGCMP clock + \arg RCU_ADC: ADC clock + \arg RCU_TIMERx (x=0,1,2,5,13,14,15,16): TIMER clock (RCU_TIMER5 only for GD32F350) + \arg RCU_SPIx (x=0,1): SPI clock + \arg RCU_USARTx (x=0,1): USART clock + \arg RCU_WWDGT: WWDGT clock + \arg RCU_I2Cx (x=0,1): I2C clock + \arg RCU_USBFS: USBFS clock (only for GD32F350) + \arg RCU_PMU: PMU clock + \arg RCU_DAC: DAC clock (only for GD32F350) + \arg RCU_CEC: CEC clock (only for GD32F350) + \arg RCU_CTC: CTC clock + \arg RCU_RTC: RTC clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_enable(rcu_periph_enum periph) +{ + RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); +} + +/*! + \brief disable the peripherals clock + \param[in] periph: RCU peripherals, refer to rcu_periph_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOx (x=A,B,C,D,F): GPIO ports clock + \arg RCU_DMA: DMA clock + \arg RCU_CRC: CRC clock + \arg RCU_TSI: TSI clock + \arg RCU_CFGCMP: CFGCMP clock + \arg RCU_ADC: ADC clock + \arg RCU_TIMERx (x=0,1,2,5,13,14,15,16): TIMER clock (RCU_TIMER5 only for GD32F350) + \arg RCU_SPIx (x=0,1): SPI clock + \arg RCU_USARTx (x=0,1): USART clock + \arg RCU_WWDGT: WWDGT clock + \arg RCU_I2Cx (x=0,1): I2C clock + \arg RCU_USBFS: USBFS clock (only for GD32F350) + \arg RCU_PMU: PMU clock + \arg RCU_DAC: DAC clock (only for GD32F350) + \arg RCU_CEC: CEC clock (only for GD32F350) + \arg RCU_CTC: CTC clock + \arg RCU_RTC: RTC clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_disable(rcu_periph_enum periph) +{ + RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); +} + +/*! + \brief enable the peripherals clock when sleep mode + \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum + only one parameter can be selected which is shown as below: + \arg RCU_FMC_SLP: FMC clock + \arg RCU_SRAM_SLP: SRAM clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph) +{ + RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); +} + +/*! + \brief disable the peripherals clock when sleep mode + \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum + only one parameter can be selected which is shown as below: + \arg RCU_FMC_SLP: FMC clock + \arg RCU_SRAM_SLP: SRAM clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph) +{ + RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); +} +/*! + \brief reset the peripherals + \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOxRST (x=A,B,C,D,F): reset GPIO ports + \arg RCU_TSIRST: reset TSI + \arg RCU_CFGCMPRST: reset CFGCMP + \arg RCU_ADCRST: reset ADC + \arg RCU_TIMERxRST (x=0,1,2,5,13,14,15,16): reset TIMER (RCU_TIMER5 only for GD32F350) + \arg RCU_SPIxRST (x=0,1): reset SPI + \arg RCU_USARTxRST (x=0,1): reset USART + \arg RCU_WWDGTRST: reset WWDGT + \arg RCU_I2CxRST (x=0,1): reset I2C + \arg RCU_USBFSRST: reset USBFS (only for GD32F350) + \arg RCU_PMURST: reset PMU + \arg RCU_DACRST: reset DAC (only for GD32F350) + \arg RCU_CECRST: reset CEC (only for GD32F350) + \arg RCU_CTCRST: reset CTC + \param[out] none + \retval none +*/ +void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset) +{ + RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset)); +} + +/*! + \brief disable reset the peripheral + \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOxRST (x=A,B,C,D,F): reset GPIO ports + \arg RCU_TSIRST: reset TSI + \arg RCU_CFGCMPRST: reset CFGCMP + \arg RCU_ADCRST: reset ADC + \arg RCU_TIMERxRST (x=0,1,2,5,13,14,15,16): reset TIMER (RCU_TIMER5 only for GD32F350) + \arg RCU_SPIxRST (x=0,1,2): reset SPI + \arg RCU_USARTxRST (x=0,1): reset USART + \arg RCU_WWDGTRST: reset WWDGT + \arg RCU_I2CxRST (x=0,1,2): reset I2C + \arg RCU_USBFSRST: reset USBFS (only for GD32F350) + \arg RCU_PMURST: reset PMU + \arg RCU_DACRST: reset DAC (only for GD32F350) + \arg RCU_CECRST: reset CEC (only for GD32F350) + \arg RCU_CTCRST: reset CTC + \param[out] none + \retval none +*/ +void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset) +{ + RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset)); +} + +/*! + \brief reset the BKP + \param[in] none + \param[out] none + \retval none +*/ +void rcu_bkp_reset_enable(void) +{ + RCU_BDCTL |= RCU_BDCTL_BKPRST; +} + +/*! + \brief disable the BKP reset + \param[in] none + \param[out] none + \retval none +*/ +void rcu_bkp_reset_disable(void) +{ + RCU_BDCTL &= ~RCU_BDCTL_BKPRST; +} + +/*! + \brief configure the system clock source + \param[in] ck_sys: system clock source select + only one parameter can be selected which is shown as below: + \arg RCU_CKSYSSRC_IRC8M: select CK_IRC8M as the CK_SYS source + \arg RCU_CKSYSSRC_HXTAL: select CK_HXTAL as the CK_SYS source + \arg RCU_CKSYSSRC_PLL: select CK_PLL as the CK_SYS source + \param[out] none + \retval none +*/ +void rcu_system_clock_source_config(uint32_t ck_sys) +{ + uint32_t cksys_source = 0U; + cksys_source = RCU_CFG0; + /* reset the SCS bits and set according to ck_sys */ + cksys_source &= ~RCU_CFG0_SCS; + RCU_CFG0 = (ck_sys | cksys_source); +} + +/*! + \brief get the system clock source + \param[in] none + \param[out] none + \retval which clock is selected as CK_SYS source + only one parameter can be selected which is shown as below: + \arg RCU_SCSS_IRC8M: select CK_IRC8M as the CK_SYS source + \arg RCU_SCSS_HXTAL: select CK_HXTAL as the CK_SYS source + \arg RCU_SCSS_PLL: select CK_PLL as the CK_SYS source +*/ +uint32_t rcu_system_clock_source_get(void) +{ + return (RCU_CFG0 & RCU_CFG0_SCSS); +} + +/*! + \brief configure the AHB clock prescaler selection + \param[in] ck_ahb: AHB clock prescaler selection + only one parameter can be selected which is shown as below: + \arg RCU_AHB_CKSYS_DIVx, x=1, 2, 4, 8, 16, 64, 128, 256, 512 + \param[out] none + \retval none +*/ +void rcu_ahb_clock_config(uint32_t ck_ahb) +{ + uint32_t ahbpsc = 0U; + ahbpsc = RCU_CFG0; + /* reset the AHBPSC bits and set according to ck_ahb */ + ahbpsc &= ~RCU_CFG0_AHBPSC; + RCU_CFG0 = (ck_ahb | ahbpsc); +} + +/*! + \brief configure the APB1 clock prescaler selection + \param[in] ck_apb1: APB1 clock prescaler selection + only one parameter can be selected which is shown as below: + \arg RCU_APB1_CKAHB_DIV1: select CK_AHB as CK_APB1 + \arg RCU_APB1_CKAHB_DIV2: select CK_AHB/2 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV4: select CK_AHB/4 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV8: select CK_AHB/8 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV16: select CK_AHB/16 as CK_APB1 + \param[out] none + \retval none +*/ +void rcu_apb1_clock_config(uint32_t ck_apb1) +{ + uint32_t apb1psc = 0U; + apb1psc = RCU_CFG0; + /* reset the APB1PSC and set according to ck_apb1 */ + apb1psc &= ~RCU_CFG0_APB1PSC; + RCU_CFG0 = (ck_apb1 | apb1psc); +} + +/*! + \brief configure the APB2 clock prescaler selection + \param[in] ck_apb2: APB2 clock prescaler selection + only one parameter can be selected which is shown as below: + \arg RCU_APB2_CKAHB_DIV1: select CK_AHB as CK_APB2 + \arg RCU_APB2_CKAHB_DIV2: select CK_AHB/2 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV4: select CK_AHB/4 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV8: select CK_AHB/8 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV16: select CK_AHB/16 as CK_APB2 + \param[out] none + \retval none +*/ +void rcu_apb2_clock_config(uint32_t ck_apb2) +{ + uint32_t apb2psc = 0U; + apb2psc = RCU_CFG0; + /* reset the APB2PSC and set according to ck_apb2 */ + apb2psc &= ~RCU_CFG0_APB2PSC; + RCU_CFG0 = (ck_apb2 | apb2psc); +} + +/*! + \brief configure the ADC clock prescaler selection + \param[in] ck_adc: ADC clock prescaler selection, refer to rcu_adc_clock_enum + only one parameter can be selected which is shown as below: + \arg RCU_ADCCK_IRC28M_DIV2: select CK_IRC28M/2 as CK_ADC + \arg RCU_ADCCK_IRC28M: select CK_IRC28M as CK_ADC + \arg RCU_ADCCK_APB2_DIV2: select CK_APB2/2 as CK_ADC + \arg RCU_ADCCK_AHB_DIV3: select CK_AHB/3 as CK_ADC + \arg RCU_ADCCK_APB2_DIV4: select CK_APB2/4 as CK_ADC + \arg RCU_ADCCK_AHB_DIV5: select CK_AHB/5 as CK_ADC + \arg RCU_ADCCK_APB2_DIV6: select CK_APB2/6 as CK_ADC + \arg RCU_ADCCK_AHB_DIV7: select CK_AHB/7 as CK_ADC + \arg RCU_ADCCK_APB2_DIV8: select CK_APB2/8 as CK_ADC + \arg RCU_ADCCK_AHB_DIV9: select CK_AHB/9 as CK_ADC + \param[out] none + \retval none +*/ +void rcu_adc_clock_config(rcu_adc_clock_enum ck_adc) +{ + /* reset the ADCPSC, ADCSEL, IRC28MDIV bits */ + RCU_CFG0 &= ~RCU_CFG0_ADCPSC; + RCU_CFG2 &= ~(RCU_CFG2_ADCSEL | RCU_CFG2_IRC28MDIV | RCU_CFG2_ADCPSC2); + + /* set the ADC clock according to ck_adc */ + switch(ck_adc){ + case RCU_ADCCK_IRC28M_DIV2: + RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV; + RCU_CFG2 &= ~RCU_CFG2_ADCSEL; + break; + case RCU_ADCCK_IRC28M: + RCU_CFG2 |= RCU_CFG2_IRC28MDIV; + RCU_CFG2 &= ~RCU_CFG2_ADCSEL; + break; + case RCU_ADCCK_APB2_DIV2: + RCU_CFG0 |= RCU_ADC_CKAPB2_DIV2; + RCU_CFG2 |= RCU_CFG2_ADCSEL; + break; + case RCU_ADCCK_AHB_DIV3: + RCU_CFG0 |= RCU_ADC_CKAPB2_DIV2; + RCU_CFG2 |= RCU_CFG2_ADCPSC2; + RCU_CFG2 |= RCU_CFG2_ADCSEL; + break; + case RCU_ADCCK_APB2_DIV4: + RCU_CFG0 |= RCU_ADC_CKAPB2_DIV4; + RCU_CFG2 |= RCU_CFG2_ADCSEL; + break; + case RCU_ADCCK_AHB_DIV5: + RCU_CFG0 |= RCU_ADC_CKAPB2_DIV4; + RCU_CFG2 |= RCU_CFG2_ADCPSC2; + RCU_CFG2 |= RCU_CFG2_ADCSEL; + break; + case RCU_ADCCK_APB2_DIV6: + RCU_CFG0 |= RCU_ADC_CKAPB2_DIV6; + RCU_CFG2 |= RCU_CFG2_ADCSEL; + break; + case RCU_ADCCK_AHB_DIV7: + RCU_CFG0 |= RCU_ADC_CKAPB2_DIV6; + RCU_CFG2 |= RCU_CFG2_ADCPSC2; + RCU_CFG2 |= RCU_CFG2_ADCSEL; + break; + case RCU_ADCCK_APB2_DIV8: + RCU_CFG0 |= RCU_ADC_CKAPB2_DIV8; + RCU_CFG2 |= RCU_CFG2_ADCSEL; + break; + case RCU_ADCCK_AHB_DIV9: + RCU_CFG0 |= RCU_ADC_CKAPB2_DIV8; + RCU_CFG2 |= RCU_CFG2_ADCPSC2; + RCU_CFG2 |= RCU_CFG2_ADCSEL; + break; + default: + break; + } +} + +/*! + \brief configure the USBFS clock prescaler selection + \param[in] ck_usbfs: USBFS clock prescaler selection + only one parameter can be selected which is shown as below: + \arg RCU_USBFS_CKPLL_DIV1_5: select CK_PLL/1.5 as CK_USBFS + \arg RCU_USBFS_CKPLL_DIV1: select CK_PLL as CK_USBFS + \arg RCU_USBFS_CKPLL_DIV2_5: select CK_PLL/2.5 as CK_USBFS + \arg RCU_USBFS_CKPLL_DIV2: select CK_PLL/2 as CK_USBFS + \arg RCU_USBFS_CKPLL_DIV3: select CK_PLL/3 as CK_USBFS + \arg RCU_USBFS_CKPLL_DIV3_5: select CK_PLL/3.5 as CK_USBFS + \param[out] none + \retval none +*/ +void rcu_usbfs_clock_config(uint32_t ck_usbfs) +{ + /* reset the USBFSPSC bits and set according to ck_usbfs */ + RCU_CFG0 &= ~RCU_CFG0_USBFSPSC; + RCU_CFG2 &= ~RCU_CFG2_USBFSPSC2; + + RCU_CFG0 |= (ck_usbfs & (~RCU_CFG2_USBFSPSC2)); + RCU_CFG2 |= (ck_usbfs & RCU_CFG2_USBFSPSC2); +} + +/*! + \brief configure the CK_OUT clock source and divider + \param[in] ckout_src: CK_OUT clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_CKOUTSRC_NONE: no clock selected + \arg RCU_CKOUTSRC_IRC28M: IRC28M selected + \arg RCU_CKOUTSRC_IRC40K: IRC40K selected + \arg RCU_CKOUTSRC_LXTAL: LXTAL selected + \arg RCU_CKOUTSRC_CKSYS: CKSYS selected + \arg RCU_CKOUTSRC_IRC8M: IRC8M selected + \arg RCU_CKOUTSRC_HXTAL: HXTAL selected + \arg RCU_CKOUTSRC_CKPLL_DIV1: CK_PLL selected + \arg RCU_CKOUTSRC_CKPLL_DIV2: CK_PLL/2 selected + \param[in] ckout_div: CK_OUT divider + \arg RCU_CKOUT_DIVx(x=1,2,4,8,16,32,64,128): CK_OUT is divided by x + \param[out] none + \retval none +*/ +void rcu_ckout_config(uint32_t ckout_src, uint32_t ckout_div) +{ + uint32_t ckout = 0U; + ckout = RCU_CFG0; + /* reset the CKOUTSEL, CKOUTDIV and PLLDV bits and set according to ckout_src and ckout_div */ + ckout &= ~(RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV); + RCU_CFG0 = (ckout | ckout_src | ckout_div); +} + +/*! + \brief configure the PLL clock source preselection + \param[in] pll_presel: PLL clock source preselection + only one parameter can be selected which is shown as below: + \arg RCU_PLLPRESEL_IRC48M: select IRC48M as PLL preselection clock + \arg RCU_PLLPRESEL_HXTAL: select HXTAL as PLL preselection clock + \param[out] none + \retval none +*/ +void rcu_pll_preselection_config(uint32_t pll_presel) +{ + RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL); + RCU_CFG1 |= pll_presel; +} + +/*! + \brief configure the PLL clock source selection and PLL multiply factor + \param[in] pll_src: PLL clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_PLLSRC_IRC8M_DIV2: select CK_IRC8M/2 as PLL source clock + \arg RCU_PLLSRC_HXTAL_IRC48M: select HXTAL or IRC48M as PLL source clock + \param[in] pll_mul: PLL multiply factor + only one parameter can be selected which is shown as below: + \arg RCU_PLL_MULx(x=2..64): PLL source clock * x + \param[out] none + \retval none +*/ +void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul) +{ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF); + RCU_CFG1 &= ~(RCU_CFG1_PLLMF5); + RCU_CFG0 |= (pll_src | (pll_mul & (~RCU_CFG1_PLLMF5))); + RCU_CFG1 |= (pll_mul & RCU_CFG1_PLLMF5); +} + +/*! + \brief configure the USART clock source selection + \param[in] ck_usart: USART clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_USART0SRC_CKAPB2: CK_USART0 select CK_APB2 + \arg RCU_USART0SRC_CKSYS: CK_USART0 select CK_SYS + \arg RCU_USART0SRC_LXTAL: CK_USART0 select CK_LXTAL + \arg RCU_USART0SRC_IRC8M: CK_USART0 select CK_IRC8M + \param[out] none + \retval none +*/ +void rcu_usart_clock_config(uint32_t ck_usart) +{ + /* reset the USART0SEL bits and set according to ck_usart */ + RCU_CFG2 &= ~RCU_CFG2_USART0SEL; + RCU_CFG2 |= ck_usart; +} + +/*! + \brief configure the CEC clock source selection + \param[in] ck_cec: CEC clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_CECSRC_IRC8M_DIV244: CK_CEC select CK_IRC8M/244 + \arg RCU_CECSRC_LXTAL: CK_CEC select CK_LXTAL + \param[out] none + \retval none +*/ +void rcu_cec_clock_config(uint32_t ck_cec) +{ + /* reset the CECSEL bit and set according to ck_cec */ + RCU_CFG2 &= ~RCU_CFG2_CECSEL; + RCU_CFG2 |= ck_cec; +} + +/*! + \brief configure the RTC clock source selection + \param[in] rtc_clock_source: RTC clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_RTCSRC_NONE: no clock selected + \arg RCU_RTCSRC_LXTAL: CK_LXTAL selected as RTC source clock + \arg RCU_RTCSRC_IRC40K: CK_IRC40K selected as RTC source clock + \arg RCU_RTCSRC_HXTAL_DIV32: CK_HXTAL/32 selected as RTC source clock + \param[out] none + \retval none +*/ +void rcu_rtc_clock_config(uint32_t rtc_clock_source) +{ + /* reset the RTCSRC bits and set according to rtc_clock_source */ + RCU_BDCTL &= ~RCU_BDCTL_RTCSRC; + RCU_BDCTL |= rtc_clock_source; +} + +/*! + \brief configure the CK48M clock source selection + \param[in] ck48m_clock_source: CK48M clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_CK48MSRC_PLL48M: CK_PLL48M selected as CK48M source clock + \arg RCU_CK48MSRC_IRC48M: CK_IRC48M selected as CK48M source clock + \param[out] none + \retval none +*/ +void rcu_ck48m_clock_config(uint32_t ck48m_clock_source) +{ + uint32_t reg; + + reg = RCU_ADDCTL; + /* reset the CK48MSEL bit and set according to ck48m_clock_source */ + reg &= ~RCU_ADDCTL_CK48MSEL; + RCU_ADDCTL = (reg | ck48m_clock_source); +} + +/*! + \brief configure the HXTAL divider used as input of PLL + \param[in] hxtal_prediv: HXTAL divider used as input of PLL + only one parameter can be selected which is shown as below: + \arg RCU_PLL_PREDVx(x=1..16): HXTAL or IRC48M divided x used as input of PLL + \param[out] none + \retval none +*/ +void rcu_hxtal_prediv_config(uint32_t hxtal_prediv) +{ + uint32_t prediv = 0U; + prediv = RCU_CFG1; + /* reset the HXTALPREDV bits and set according to hxtal_prediv */ + prediv &= ~RCU_CFG1_PREDV; + RCU_CFG1 = (prediv | hxtal_prediv); +} + +/*! + \brief configure the LXTAL drive capability + \param[in] lxtal_dricap: drive capability of LXTAL + only one parameter can be selected which is shown as below: + \arg RCU_LXTAL_LOWDRI: lower driving capability + \arg RCU_LXTAL_MED_LOWDRI: medium low driving capability + \arg RCU_LXTAL_MED_HIGHDRI: medium high driving capability + \arg RCU_LXTAL_HIGHDRI: higher driving capability + \param[out] none + \retval none +*/ +void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap) +{ + /* reset the LXTALDRI bits and set according to lxtal_dricap */ + RCU_BDCTL &= ~RCU_BDCTL_LXTALDRI; + RCU_BDCTL |= lxtal_dricap; +} + +/*! + \brief get the clock stabilization and periphral reset flags + \param[in] flag: the clock stabilization and periphral reset flags, refer to rcu_flag_enum + only one parameter can be selected which is shown as below: + \arg RCU_FLAG_IRC40KSTB: IRC40K stabilization flag + \arg RCU_FLAG_LXTALSTB: LXTAL stabilization flag + \arg RCU_FLAG_IRC8MSTB: IRC8M stabilization flag + \arg RCU_FLAG_HXTALSTB: HXTAL stabilization flag + \arg RCU_FLAG_PLLSTB: PLL stabilization flag + \arg RCU_FLAG_IRC28MSTB: IRC28M stabilization flag + \arg RCU_FLAG_IRC48MSTB: IRC48M stabilization flag + \arg RCU_FLAG_V12RST: V12 domain power reset flag + \arg RCU_FLAG_OBLRST: option byte loader reset flag + \arg RCU_FLAG_EPRST: external pin reset flag + \arg RCU_FLAG_PORRST: power reset flag + \arg RCU_FLAG_SWRST: software reset flag + \arg RCU_FLAG_FWDGTRST: free watchdog timer reset flag + \arg RCU_FLAG_WWDGTRST: window watchdog timer reset flag + \arg RCU_FLAG_LPRST: low-power reset flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus rcu_flag_get(rcu_flag_enum flag) +{ + if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear the reset flag + \param[in] none + \param[out] none + \retval none +*/ +void rcu_all_reset_flag_clear(void) +{ + RCU_RSTSCK |= RCU_RSTSCK_RSTFC; +} + +/*! + \brief get the clock stabilization interrupt and ckm flags + \param[in] int_flag: interrupt and ckm flags, refer to rcu_int_flag_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_FLAG_IRC40KSTB: IRC40K stabilization interrupt flag + \arg RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag + \arg RCU_INT_FLAG_IRC8MSTB: IRC8M stabilization interrupt flag + \arg RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag + \arg RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag + \arg RCU_INT_FLAG_IRC28MSTB: IRC28M stabilization interrupt flag + \arg RCU_INT_FLAG_IRC48MSTB: IRC48M stabilization interrupt flag + \arg RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag) +{ + if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear the interrupt flags + \param[in] int_flag_clear: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_FLAG_IRC40KSTB_CLR: IRC40K stabilization interrupt flag clear + \arg RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear + \arg RCU_INT_FLAG_IRC8MSTB_CLR: IRC8M stabilization interrupt flag clear + \arg RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear + \arg RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear + \arg RCU_INT_FLAG_IRC28MSTB_CLR: IRC28M stabilization interrupt flag clear + \arg RCU_INT_FLAG_IRC48MSTB_CLR: IRC48M stabilization interrupt flag clear + \arg RCU_INT_FLAG_CKM_CLR: clock stuck interrupt flag clear + \param[out] none + \retval none +*/ +void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear) +{ + RCU_REG_VAL(int_flag_clear) |= BIT(RCU_BIT_POS(int_flag_clear)); +} + +/*! + \brief enable the stabilization interrupt + \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable + \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable + \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable + \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable + \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable + \arg RCU_INT_IRC28MSTB: IRC28M stabilization interrupt enable + \arg RCU_INT_IRC48MSTB: IRC48M stabilization interrupt enable + \param[out] none + \retval none +*/ +void rcu_interrupt_enable(rcu_int_enum stab_int) +{ + RCU_REG_VAL(stab_int) |= BIT(RCU_BIT_POS(stab_int)); +} + + +/*! + \brief disable the stabilization interrupt + \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt disable + \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt disable + \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt disable + \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt disable + \arg RCU_INT_PLLSTB: PLL stabilization interrupt disable + \arg RCU_INT_IRC28MSTB: IRC28M stabilization interrupt disable + \arg RCU_INT_IRC48MSTB: IRC48M stabilization interrupt disable + \param[out] none + \retval none +*/ +void rcu_interrupt_disable(rcu_int_enum stab_int) +{ + RCU_REG_VAL(stab_int) &= ~BIT(RCU_BIT_POS(stab_int)); +} + +/*! + \brief wait until oscillator stabilization flags is SET + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: HXTAL + \arg RCU_LXTAL: LXTAL + \arg RCU_IRC8M: IRC8M + \arg RCU_IRC28M: IRC28M + \arg RCU_IRC48M: IRC48M + \arg RCU_IRC40K: IRC40K + \arg RCU_PLL_CK: PLL + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci) +{ + uint32_t stb_cnt = 0U; + ErrStatus reval = ERROR; + FlagStatus osci_stat = RESET; + switch(osci){ + case RCU_HXTAL: + /* wait until HXTAL is stabilization and osci_stat is not more than timeout */ + while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)){ + osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB); + stb_cnt++; + } + if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)){ + reval = SUCCESS; + } + break; + /* wait LXTAL stable */ + case RCU_LXTAL: + while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)){ + osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)){ + reval = SUCCESS; + } + break; + + /* wait IRC8M stable */ + case RCU_IRC8M: + while((RESET == osci_stat) && (IRC8M_STARTUP_TIMEOUT != stb_cnt)){ + osci_stat = rcu_flag_get(RCU_FLAG_IRC8MSTB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_IRC8MSTB)){ + reval = SUCCESS; + } + break; + + /* wait IRC28M stable */ + case RCU_IRC28M: + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ + osci_stat = rcu_flag_get(RCU_FLAG_IRC28MSTB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_IRC28MSTB)){ + reval = SUCCESS; + } + break; + /* wait IRC48M stable */ + case RCU_IRC48M: + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ + osci_stat = rcu_flag_get(RCU_FLAG_IRC48MSTB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if (RESET != rcu_flag_get(RCU_FLAG_IRC48MSTB)){ + reval = SUCCESS; + } + break; + + /* wait IRC40K stable */ + case RCU_IRC40K: + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ + osci_stat = rcu_flag_get(RCU_FLAG_IRC40KSTB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_IRC40KSTB)){ + reval = SUCCESS; + } + break; + + /* wait PLL stable */ + case RCU_PLL_CK: + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ + osci_stat = rcu_flag_get(RCU_FLAG_PLLSTB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_PLLSTB)){ + reval = SUCCESS; + } + break; + + default: + break; + } + /* return value */ + return reval; +} + +/*! + \brief turn on the oscillator + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: HXTAL + \arg RCU_LXTAL: LXTAL + \arg RCU_IRC8M: IRC8M + \arg RCU_IRC28M: IRC28M + \arg RCU_IRC48M: IRC48M + \arg RCU_IRC40K: IRC40K + \arg RCU_PLL_CK: PLL + \param[out] none + \retval none +*/ +void rcu_osci_on(rcu_osci_type_enum osci) +{ + RCU_REG_VAL(osci) |= BIT(RCU_BIT_POS(osci)); +} + +/*! + \brief turn off the oscillator + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: HXTAL + \arg RCU_LXTAL: LXTAL + \arg RCU_IRC8M: IRC8M + \arg RCU_IRC28M: IRC28M + \arg RCU_IRC48M: IRC48M + \arg RCU_IRC40K: IRC40K + \arg RCU_PLL_CK: PLL + \param[out] none + \retval none +*/ +void rcu_osci_off(rcu_osci_type_enum osci) +{ + RCU_REG_VAL(osci) &= ~BIT(RCU_BIT_POS(osci)); +} + +/*! + \brief enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: HXTAL + \arg RCU_LXTAL: LXTAL + \param[out] none + \retval none +*/ +void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci) +{ + uint32_t reg; + switch(osci){ + case RCU_HXTAL: + /* HXTALEN must be reset before enable the oscillator bypass mode */ + reg = RCU_CTL0; + RCU_CTL0 &= ~RCU_CTL0_HXTALEN; + RCU_CTL0 = (reg | RCU_CTL0_HXTALBPS); + break; + case RCU_LXTAL: + /* LXTALEN must be reset before enable the oscillator bypass mode */ + reg = RCU_BDCTL; + RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; + RCU_BDCTL = (reg | RCU_BDCTL_LXTALBPS); + break; + case RCU_IRC8M: + case RCU_IRC28M: + case RCU_IRC48M: + case RCU_IRC40K: + case RCU_PLL_CK: + break; + default: + break; + } +} + +/*! + \brief disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: HXTAL + \arg RCU_LXTAL: LXTAL + \param[out] none + \retval none +*/ +void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci) +{ + uint32_t reg; + switch(osci){ + case RCU_HXTAL: + /* HXTALEN must be reset before disable the oscillator bypass mode */ + reg = RCU_CTL0; + RCU_CTL0 &= ~RCU_CTL0_HXTALEN; + RCU_CTL0 = (reg & (~RCU_CTL0_HXTALBPS)); + break; + case RCU_LXTAL: + /* LXTALEN must be reset before disable the oscillator bypass mode */ + reg = RCU_BDCTL; + RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; + RCU_BDCTL = (reg & (~RCU_BDCTL_LXTALBPS)); + break; + case RCU_IRC8M: + case RCU_IRC28M: + case RCU_IRC48M: + case RCU_IRC40K: + case RCU_PLL_CK: + break; + default: + break; + } +} + +/*! + \brief enable the HXTAL clock monitor + \param[in] none + \param[out] none + \retval none +*/ +void rcu_hxtal_clock_monitor_enable(void) +{ + RCU_CTL0 |= RCU_CTL0_CKMEN; +} + +/*! + \brief disable the HXTAL clock monitor + \param[in] none + \param[out] none + \retval none +*/ +void rcu_hxtal_clock_monitor_disable(void) +{ + RCU_CTL0 &= ~RCU_CTL0_CKMEN; +} + +/*! + \brief set the IRC8M adjust value + \param[in] irc8m_adjval: IRC8M adjust value, must be between 0 and 0x1F + \param[out] none + \retval none +*/ +void rcu_irc8m_adjust_value_set(uint8_t irc8m_adjval) +{ + uint32_t adjust = 0U; + adjust = RCU_CTL0; + /* reset the IRC8MADJ bits and set according to irc8m_adjval */ + adjust &= ~RCU_CTL0_IRC8MADJ; + RCU_CTL0 = (adjust | (((uint32_t)irc8m_adjval)<<3)); +} + +/*! + \brief set the IRC28M adjust value + \param[in] irc28m_adjval: IRC28M adjust value, must be between 0 and 0x1F + \param[out] none + \retval none +*/ +void rcu_irc28m_adjust_value_set(uint8_t irc28m_adjval) +{ + uint32_t adjust = 0U; + adjust = RCU_CTL1; + /* reset the IRC28MADJ bits and set according to irc28m_adjval */ + adjust &= ~RCU_CTL1_IRC28MADJ; + RCU_CTL1 = (adjust | (((uint32_t)irc28m_adjval)<<3)); +} + +/*! + \brief unlock the voltage key + \param[in] none + \param[out] none + \retval none +*/ +void rcu_voltage_key_unlock(void) +{ + /* reset the KEY bits and set 0x1A2B3C4D */ + RCU_VKEY &= ~RCU_VKEY_KEY; + RCU_VKEY |= RCU_VKEY_UNLOCK; +} + +/*! + \brief set voltage in deep sleep mode + \param[in] dsvol: deep sleep mode voltage + only one parameter can be selected which is shown as below: + \arg RCU_DEEPSLEEP_V_1_0: the core voltage is 1.0V + \arg RCU_DEEPSLEEP_V_0_9: the core voltage is 0.9V + \arg RCU_DEEPSLEEP_V_0_8: the core voltage is 0.8V + \arg RCU_DEEPSLEEP_V_0_7: the core voltage is 0.7V + \param[out] none + \retval none +*/ +void rcu_deepsleep_voltage_set(uint32_t dsvol) +{ + /* reset the DSLPVS bits and set according to dsvol */ + RCU_DSV &= ~RCU_DSV_DSLPVS; + RCU_DSV |= dsvol; +} + +/*! + \brief get the system clock, bus and peripheral clock frequency + \param[in] clock: the clock frequency which to get + only one parameter can be selected which is shown as below: + \arg CK_SYS: system clock frequency + \arg CK_AHB: AHB clock frequency + \arg CK_APB1: APB1 clock frequency + \arg CK_APB2: APB2 clock frequency + \arg CK_ADC: ADC clock frequency + \arg CK_CEC: CEC clock frequency + \arg CK_USART: USART clock frequency + \param[out] none + \retval clock frequency of system, AHB, APB1, APB2, ADC, CEC or USRAT +*/ +uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) +{ + uint32_t sws = 0U, adcps = 0U, adcps2 = 0U, ck_freq = 0U; + uint32_t cksys_freq = 0U, ahb_freq = 0U, apb1_freq = 0U, apb2_freq = 0U; + uint32_t adc_freq = 0U, cec_freq = 0U, usart_freq = 0U; + uint32_t pllmf = 0U, pllmf4 = 0U, pllmf5 = 0U, pllsel = 0U, pllpresel = 0U, prediv = 0U, idx = 0U, clk_exp = 0U; + /* exponent of AHB, APB1 and APB2 clock divider */ + const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + const uint8_t apb1_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + const uint8_t apb2_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + + sws = GET_BITS(RCU_CFG0, 2, 3); + switch(sws){ + /* IRC8M is selected as CK_SYS */ + case SEL_IRC8M: + cksys_freq = IRC8M_VALUE; + break; + /* HXTAL is selected as CK_SYS */ + case SEL_HXTAL: + cksys_freq = HXTAL_VALUE; + break; + /* PLL is selected as CK_SYS */ + case SEL_PLL: + /* get the value of PLLMF[3:0] */ + pllmf = GET_BITS(RCU_CFG0, 18, 21); + pllmf4 = GET_BITS(RCU_CFG0, 27, 27); + pllmf5 = GET_BITS(RCU_CFG1, 31, 31); + /* high 16 bits */ + if(1U == pllmf4){ + pllmf += 17U; + }else{ + if(pllmf == 15U){ + pllmf += 1U; + }else{ + pllmf += 2U; + } + } + if(1U == pllmf5){ + pllmf += 31U; + } + + /* PLL clock source selection, HXTAL or IRC48M or IRC8M/2 */ + pllsel = GET_BITS(RCU_CFG0, 16, 16); + pllpresel = GET_BITS(RCU_CFG1, 30, 30); + if(0U != pllsel){ + prediv = (GET_BITS(RCU_CFG1,0, 3) + 1U); + if(0U == pllpresel){ + cksys_freq = (HXTAL_VALUE / prediv) * pllmf; + }else{ + cksys_freq = (IRC48M_VALUE / prediv) * pllmf; + } + }else{ + cksys_freq = (IRC8M_VALUE >> 1) * pllmf; + } + break; + /* IRC8M is selected as CK_SYS */ + default: + cksys_freq = IRC8M_VALUE; + break; + } + /* calculate AHB clock frequency */ + idx = GET_BITS(RCU_CFG0, 4, 7); + clk_exp = ahb_exp[idx]; + ahb_freq = cksys_freq >> clk_exp; + + /* calculate APB1 clock frequency */ + idx = GET_BITS(RCU_CFG0, 8, 10); + clk_exp = apb1_exp[idx]; + apb1_freq = ahb_freq >> clk_exp; + + /* calculate APB2 clock frequency */ + idx = GET_BITS(RCU_CFG0, 11, 13); + clk_exp = apb2_exp[idx]; + apb2_freq = ahb_freq >> clk_exp; + + /* return the clocks frequency */ + switch(clock){ + case CK_SYS: + ck_freq = cksys_freq; + break; + case CK_AHB: + ck_freq = ahb_freq; + break; + case CK_APB1: + ck_freq = apb1_freq; + break; + case CK_APB2: + ck_freq = apb2_freq; + break; + case CK_ADC: + /* calculate ADC clock frequency */ + if(RCU_ADCSRC_AHB_APB2DIV != (RCU_CFG2 & RCU_CFG2_ADCSEL)){ + if(RCU_ADC_IRC28M_DIV1 != (RCU_CFG2 & RCU_CFG2_IRC28MDIV)){ + adc_freq = IRC28M_VALUE >> 1; + }else{ + adc_freq = IRC28M_VALUE; + } + }else{ + /* ADC clock select CK_APB2 divided by 2/4/6/8 or CK_AHB divided by 3/5/7/9 */ + adcps = GET_BITS(RCU_CFG0, 14, 15); + adcps2 = GET_BITS(RCU_CFG2, 31, 31); + switch(adcps){ + case 0: + if(0U == adcps2){ + adc_freq = apb2_freq / 2U; + }else{ + adc_freq = ahb_freq / 3U; + } + break; + case 1: + if(0U == adcps2){ + adc_freq = apb2_freq / 4U; + }else{ + adc_freq = ahb_freq / 5U; + } + break; + case 2: + if(0U == adcps2){ + adc_freq = apb2_freq / 6U; + }else{ + adc_freq = ahb_freq / 7U; + } + break; + case 3: + if(0U == adcps2){ + adc_freq = apb2_freq / 8U; + }else{ + adc_freq = ahb_freq / 9U; + } + break; + default: + break; + } + } + ck_freq = adc_freq; + break; + case CK_CEC: + /* calculate CEC clock frequency */ + if(RCU_CECSRC_LXTAL != (RCU_CFG2 & RCU_CFG2_CECSEL)){ + cec_freq = IRC8M_VALUE / 244U; + }else{ + cec_freq = LXTAL_VALUE; + } + ck_freq = cec_freq; + break; + case CK_USART: + /* calculate USART clock frequency */ + if(RCU_USART0SRC_CKAPB2 == (RCU_CFG2 & RCU_CFG2_USART0SEL)){ + usart_freq = apb2_freq; + }else if(RCU_USART0SRC_CKSYS == (RCU_CFG2 & RCU_CFG2_USART0SEL)){ + usart_freq = cksys_freq; + }else if(RCU_USART0SRC_LXTAL == (RCU_CFG2 & RCU_CFG2_USART0SEL)){ + usart_freq = LXTAL_VALUE; + }else if(RCU_USART0SRC_IRC8M == (RCU_CFG2 & RCU_CFG2_USART0SEL)){ + usart_freq = IRC8M_VALUE; + }else{ + } + ck_freq = usart_freq; + break; + default: + break; + } + return ck_freq; +} diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_rtc.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_rtc.c new file mode 100644 index 0000000000..5b7a3f59e1 --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_rtc.c @@ -0,0 +1,966 @@ +/*! + \file gd32f3x0_rtc.c + \brief RTC driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f3x0_rtc.h" + +/*! + \brief reset most of the RTC registers + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_deinit(void) +{ + ErrStatus error_status = ERROR; + + /* RTC_TAMP register is not under write protection */ + RTC_TAMP = RTC_REGISTER_RESET; + + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* reset RTC_CTL register, this can be done without the init mode */ + RTC_CTL &= RTC_REGISTER_RESET; + + /* enter init mode */ + error_status = rtc_init_mode_enter(); + + if(ERROR != error_status){ + /* before reset RTC_TIME and RTC_DATE, BPSHAD bit in RTC_CTL should be reset as the condition. + in order to read calendar from shadow register, not the real registers being reset */ + RTC_TIME = RTC_REGISTER_RESET; + RTC_DATE = RTC_DATE_RESET; + + RTC_PSC = RTC_PSC_RESET; + + /* reset RTC_STAT register, also exit init mode. + at the same time, RTC_STAT_SOPF bit is reset, as the condition to reset RTC_SHIFTCTL register later */ + RTC_STAT = RTC_STAT_RESET; + + /* to write RTC_ALRM0SS register, ALRM0EN bit in RTC_CTL register should be reset as the condition */ + RTC_ALRM0TD = RTC_REGISTER_RESET; + RTC_ALRM0SS = RTC_REGISTER_RESET; + + /* reset RTC_SHIFTCTL and RTC_HRFC register, this can be done without the init mode */ + RTC_SHIFTCTL = RTC_REGISTER_RESET; + RTC_HRFC = RTC_REGISTER_RESET; + + error_status = rtc_register_sync_wait(); + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + + return error_status; +} + +/*! + \brief initialize RTC registers + \param[in] rtc_initpara_struct: pointer to a rtc_parameter_struct structure which contains + parameters for initialization of the rtc peripheral + members of the structure and the member values are shown as below: + rtc_year: 0x0 - 0x99(BCD format) + rtc_month: RTC_JAN, RTC_FEB, RTC_MAR, RTC_APR, RTC_MAY, RTC_JUN, + RTC_JUL, RTC_AUG, RTC_SEP, RTC_OCT, RTC_NOV, RTC_DEC + rtc_date: 0x1 - 0x31(BCD format) + rtc_day_of_week: RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY + RTC_FRIDAY, RTC_SATURDAY, RTC_SUNDAY + rtc_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format chose + rtc_minute: 0x0 - 0x59(BCD format) + rtc_second: 0x0 - 0x59(BCD format) + rtc_factor_asyn: 0x0 - 0x7F + rtc_factor_syn: 0x0 - 0x7FFF + rtc_am_pm: RTC_AM, RTC_PM + rtc_display_format: RTC_24HOUR, RTC_12HOUR + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_init(rtc_parameter_struct* rtc_initpara_struct) +{ + ErrStatus error_status = ERROR; + uint32_t reg_time = 0x00U, reg_date = 0x00U; + + reg_date = (DATE_YR(rtc_initpara_struct->rtc_year) | \ + DATE_DOW(rtc_initpara_struct->rtc_day_of_week) | \ + DATE_MON(rtc_initpara_struct->rtc_month) | \ + DATE_DAY(rtc_initpara_struct->rtc_date)); + + reg_time = (rtc_initpara_struct->rtc_am_pm| \ + TIME_HR(rtc_initpara_struct->rtc_hour) | \ + TIME_MN(rtc_initpara_struct->rtc_minute) | \ + TIME_SC(rtc_initpara_struct->rtc_second)); + + /* 1st: disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* 2nd: enter init mode */ + error_status = rtc_init_mode_enter(); + + if(ERROR != error_status){ + RTC_PSC = (uint32_t)(PSC_FACTOR_A(rtc_initpara_struct->rtc_factor_asyn)| \ + PSC_FACTOR_S(rtc_initpara_struct->rtc_factor_syn)); + + RTC_TIME = (uint32_t)reg_time; + RTC_DATE = (uint32_t)reg_date; + + RTC_CTL &= (uint32_t)(~RTC_CTL_CS); + RTC_CTL |= rtc_initpara_struct->rtc_display_format; + + /* 3rd: exit init mode */ + rtc_init_mode_exit(); + + /* 4th: wait the RSYNF flag to set */ + error_status = rtc_register_sync_wait(); + } + + /* 5th: enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + + return error_status; +} + +/*! + \brief enter RTC init mode + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_init_mode_enter(void) +{ + uint32_t time_index = RTC_INITM_TIMEOUT; + uint32_t flag_status = RESET; + ErrStatus error_status = ERROR; + + /* check whether it has been in init mode */ + if(RESET == (RTC_STAT & RTC_STAT_INITF)){ + RTC_STAT |= RTC_STAT_INITM; + + /* wait until the INITF flag to be set */ + do{ + flag_status = RTC_STAT & RTC_STAT_INITF; + }while((--time_index > 0x00U) && (RESET == flag_status)); + + if(RESET != flag_status){ + error_status = SUCCESS; + } + }else{ + error_status = SUCCESS; + } + return error_status; +} + +/*! + \brief exit RTC init mode + \param[in] none + \param[out] none + \retval none +*/ +void rtc_init_mode_exit(void) +{ + RTC_STAT &= (uint32_t)(~RTC_STAT_INITM); +} + +/*! + \brief wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow + registers are updated + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_register_sync_wait(void) +{ + volatile uint32_t time_index = RTC_RSYNF_TIMEOUT; + uint32_t flag_status = RESET; + ErrStatus error_status = ERROR; + + if(RESET == (RTC_CTL & RTC_CTL_BPSHAD)){ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* firstly clear RSYNF flag */ + RTC_STAT &= (uint32_t)(~RTC_STAT_RSYNF); + + /* wait until RSYNF flag to be set */ + do{ + flag_status = RTC_STAT & RTC_STAT_RSYNF; + }while((--time_index > 0x00U) && (RESET == flag_status)); + + if(RESET != flag_status){ + error_status = SUCCESS; + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + }else{ + error_status = SUCCESS; + } + + return error_status; +} + +/*! + \brief get current time and date + \param[in] none + \param[out] rtc_initpara_struct: pointer to a rtc_parameter_struct structure which contains + parameters for initialization of the rtc peripheral + members of the structure and the member values are shown as below: + rtc_year: 0x0 - 0x99(BCD format) + rtc_month: RTC_JAN, RTC_FEB, RTC_MAR, RTC_APR, RTC_MAY, RTC_JUN, + RTC_JUL, RTC_AUG, RTC_SEP, RTC_OCT, RTC_NOV, RTC_DEC + rtc_date: 0x1 - 0x31(BCD format) + rtc_day_of_week: RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY + RTC_FRIDAY, RTC_SATURDAY, RTC_SUNDAY + rtc_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format chose + rtc_minute: 0x0 - 0x59(BCD format) + rtc_second: 0x0 - 0x59(BCD format) + rtc_factor_asyn: 0x0 - 0x7F + rtc_factor_syn: 0x0 - 0x7FFF + rtc_am_pm: RTC_AM, RTC_PM + rtc_display_format: RTC_24HOUR, RTC_12HOUR + \retval none +*/ +void rtc_current_time_get(rtc_parameter_struct* rtc_initpara_struct) +{ + uint32_t temp_tr = 0x00U, temp_dr = 0x00U, temp_pscr = 0x00U, temp_ctlr = 0x00U; + + temp_tr = (uint32_t)RTC_TIME; + temp_dr = (uint32_t)RTC_DATE; + temp_pscr = (uint32_t)RTC_PSC; + temp_ctlr = (uint32_t)RTC_CTL; + + /* get current time and construct rtc_parameter_struct structure */ + rtc_initpara_struct->rtc_year = (uint8_t)GET_DATE_YR(temp_dr); + rtc_initpara_struct->rtc_month = (uint8_t)GET_DATE_MON(temp_dr); + rtc_initpara_struct->rtc_date = (uint8_t)GET_DATE_DAY(temp_dr); + rtc_initpara_struct->rtc_day_of_week = (uint8_t)GET_DATE_DOW(temp_dr); + rtc_initpara_struct->rtc_hour = (uint8_t)GET_TIME_HR(temp_tr); + rtc_initpara_struct->rtc_minute = (uint8_t)GET_TIME_MN(temp_tr); + rtc_initpara_struct->rtc_second = (uint8_t)GET_TIME_SC(temp_tr); + rtc_initpara_struct->rtc_factor_asyn = (uint16_t)GET_PSC_FACTOR_A(temp_pscr); + rtc_initpara_struct->rtc_factor_syn = (uint16_t)GET_PSC_FACTOR_S(temp_pscr); + rtc_initpara_struct->rtc_am_pm = (uint32_t)(temp_pscr & RTC_TIME_PM); + rtc_initpara_struct->rtc_display_format = (uint32_t)(temp_ctlr & RTC_CTL_CS); +} + +/*! + \brief get current subsecond value + \param[in] none + \param[out] none + \retval current subsecond value +*/ +uint32_t rtc_subsecond_get(void) +{ + uint32_t reg = 0x00U; + /* if BPSHAD bit is reset, reading RTC_SS will lock RTC_TIME and RTC_DATE automatically */ + reg = (uint32_t)RTC_SS; + /* read RTC_DATE to unlock the 3 shadow registers */ + (void) (RTC_DATE); + + return reg; +} + +/*! + \brief configure RTC alarm + \param[in] rtc_alarm_time: pointer to a rtc_alarm_struct structure which contains + parameters for RTC alarm configuration + members of the structure and the member values are shown as below: + rtc_alarm_mask: RTC_ALARM_NONE_MASK, RTC_ALARM_DATE_MASK, RTC_ALARM_HOUR_MASK + RTC_ALARM_MINUTE_MASK, RTC_ALARM_SECOND_MASK, RTC_ALARM_ALL_MASK + rtc_weekday_or_date: RTC_ALARM_DATE_SELECTED, RTC_ALARM_WEEKDAY_SELECTED + rtc_alarm_day: 1) 0x1 - 0x31(BCD format) if RTC_ALARM_DATE_SELECTED is set + 2) RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY, RTC_FRIDAY, + RTC_SATURDAY, RTC_SUNDAY if RTC_ALARM_WEEKDAY_SELECTED is set + rtc_alarm_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format + rtc_alarm_minute: 0x0 - 0x59(BCD format) + rtc_alarm_second: 0x0 - 0x59(BCD format) + rtc_am_pm: RTC_AM, RTC_PM + \param[out] none + \retval none +*/ +void rtc_alarm_config(rtc_alarm_struct* rtc_alarm_time) +{ + uint32_t reg_alrm0td = 0x00U; + + reg_alrm0td = (rtc_alarm_time->rtc_alarm_mask | \ + rtc_alarm_time->rtc_weekday_or_date | \ + rtc_alarm_time->rtc_am_pm | \ + ALRM0TD_DAY(rtc_alarm_time->rtc_alarm_day) | \ + ALRM0TD_HR(rtc_alarm_time->rtc_alarm_hour) | \ + ALRM0TD_MN(rtc_alarm_time->rtc_alarm_minute) | \ + ALRM0TD_SC(rtc_alarm_time->rtc_alarm_second)); + + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + RTC_ALRM0TD = (uint32_t)reg_alrm0td; + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief configure subsecond of RTC alarm + \param[in] mask_subsecond: alarm subsecond mask + only one parameter can be selected which is shown as below: + \arg RTC_MASKSSC_0_14: mask alarm subsecond configuration + \arg RTC_MASKSSC_1_14: mask RTC_ALRM0SS_SSC[14:1], and RTC_ALRM0SS_SSC[0] is to be compared + \arg RTC_MASKSSC_2_14: mask RTC_ALRM0SS_SSC[14:2], and RTC_ALRM0SS_SSC[1:0] is to be compared + \arg RTC_MASKSSC_3_14: mask RTC_ALRM0SS_SSC[14:3], and RTC_ALRM0SS_SSC[2:0] is to be compared + \arg RTC_MASKSSC_4_14: mask RTC_ALRM0SS_SSC[14:4], and RTC_ALRM0SS_SSC[3:0] is to be compared + \arg RTC_MASKSSC_5_14: mask RTC_ALRM0SS_SSC[14:5], and RTC_ALRM0SS_SSC[4:0] is to be compared + \arg RTC_MASKSSC_6_14: mask RTC_ALRM0SS_SSC[14:6], and RTC_ALRM0SS_SSC[5:0] is to be compared + \arg RTC_MASKSSC_7_14: mask RTC_ALRM0SS_SSC[14:7], and RTC_ALRM0SS_SSC[6:0] is to be compared + \arg RTC_MASKSSC_8_14: mask RTC_ALRM0SS_SSC[14:8], and RTC_ALRM0SS_SSC[7:0] is to be compared + \arg RTC_MASKSSC_9_14: mask RTC_ALRM0SS_SSC[14:9], and RTC_ALRM0SS_SSC[8:0] is to be compared + \arg RTC_MASKSSC_10_14: mask RTC_ALRM0SS_SSC[14:10], and RTC_ALRM0SS_SSC[9:0] is to be compared + \arg RTC_MASKSSC_11_14: mask RTC_ALRM0SS_SSC[14:11], and RTC_ALRM0SS_SSC[10:0] is to be compared + \arg RTC_MASKSSC_12_14: mask RTC_ALRM0SS_SSC[14:12], and RTC_ALRM0SS_SSC[11:0] is to be compared + \arg RTC_MASKSSC_13_14: mask RTC_ALRM0SS_SSC[14:13], and RTC_ALRM0SS_SSC[12:0] is to be compared + \arg RTC_MASKSSC_14: mask RTC_ALRM0SS_SSC[14], and RTC_ALRM0SS_SSC[13:0] is to be compared + \arg RTC_MASKSSC_NONE: mask none, and RTC_ALRM0SS_SSC[14:0] is to be compared + \param[in] subsecond: alarm subsecond value(0x000 - 0x7FFF) + \param[out] none + \retval none +*/ +void rtc_alarm_subsecond_config(uint32_t mask_subsecond, uint32_t subsecond) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + RTC_ALRM0SS = mask_subsecond | subsecond; + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief get RTC alarm + \param[in] none + \param[out] rtc_alarm_time: pointer to a rtc_alarm_struct structure which contains + parameters for RTC alarm configuration + members of the structure and the member values are shown as below: + rtc_alarm_mask: RTC_ALARM_NONE_MASK, RTC_ALARM_DATE_MASK, RTC_ALARM_HOUR_MASK + RTC_ALARM_MINUTE_MASK, RTC_ALARM_SECOND_MASK, RTC_ALARM_ALL_MASK + rtc_weekday_or_date: RTC_ALARM_DATE_SELECTED, RTC_ALARM_WEEKDAY_SELECTED + rtc_alarm_day: 1) 0x1 - 0x31(BCD format) if RTC_ALARM_DATE_SELECTED is set + 2) RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY, RTC_FRIDAY, + RTC_SATURDAY, RTC_SUNDAY if RTC_ALARM_WEEKDAY_SELECTED is set + rtc_alarm_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format + rtc_alarm_minute: 0x0 - 0x59(BCD format) + rtc_alarm_second: 0x0 - 0x59(BCD format) + rtc_am_pm: RTC_AM, RTC_PM + \retval none +*/ +void rtc_alarm_get(rtc_alarm_struct* rtc_alarm_time) +{ + uint32_t reg_alrm0td = 0x00U; + + /* get the value of RTC_ALRM0TD register */ + reg_alrm0td = RTC_ALRM0TD; + + /* get alarm parameters and construct the rtc_alarm_struct structure */ + rtc_alarm_time->rtc_alarm_mask = reg_alrm0td & RTC_ALARM_ALL_MASK; + rtc_alarm_time->rtc_am_pm = (uint32_t)(reg_alrm0td & RTC_ALRM0TD_PM); + rtc_alarm_time->rtc_weekday_or_date = (uint32_t)(reg_alrm0td & RTC_ALRM0TD_DOWS); + rtc_alarm_time->rtc_alarm_day = (uint8_t)GET_ALRM0TD_DAY(reg_alrm0td); + rtc_alarm_time->rtc_alarm_hour = (uint8_t)GET_ALRM0TD_HR(reg_alrm0td); + rtc_alarm_time->rtc_alarm_minute = (uint8_t)GET_ALRM0TD_MN(reg_alrm0td); + rtc_alarm_time->rtc_alarm_second = (uint8_t)GET_ALRM0TD_SC(reg_alrm0td); +} + +/*! + \brief get RTC alarm subsecond + \param[in] none + \param[out] none + \retval RTC alarm subsecond value +*/ +uint32_t rtc_alarm_subsecond_get(void) +{ + return ((uint32_t)(RTC_ALRM0SS & RTC_ALRM0SS_SSC)); +} + +/*! + \brief enable RTC alarm + \param[in] none + \param[out] none + \retval none +*/ +void rtc_alarm_enable(void) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + RTC_CTL |= RTC_CTL_ALRM0EN; + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief disable RTC alarm + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_alarm_disable(void) +{ + volatile uint32_t time_index = RTC_ALRM0WF_TIMEOUT; + ErrStatus error_status = ERROR; + uint32_t flag_status = RESET; + + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* clear the state of alarm */ + RTC_CTL &= (uint32_t)(~RTC_CTL_ALRM0EN); + + /* wait until ALRM0WF flag to be set after the alarm is disabled */ + do{ + flag_status = RTC_STAT & RTC_STAT_ALRM0WF; + }while((--time_index > 0x00U) && (RESET == flag_status)); + + if(RESET != flag_status){ + error_status = SUCCESS; + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + + return error_status; +} + +/*! + \brief enable RTC time-stamp + \param[in] edge: specify which edge to detect of time-stamp + only one parameter can be selected which is shown as below: + \arg RTC_TIMESTAMP_RISING_EDGE: rising edge is valid event edge for timestamp event + \arg RTC_TIMESTAMP_FALLING_EDGE: falling edge is valid event edge for timestamp event + \param[out] none + \retval none +*/ +void rtc_timestamp_enable(uint32_t edge) +{ + uint32_t reg_ctl = 0x00U; + + /* clear the bits to be configured in RTC_CTL */ + reg_ctl = (uint32_t)(RTC_CTL & (uint32_t)(~(RTC_CTL_TSEG | RTC_CTL_TSEN))); + + /* new configuration */ + reg_ctl |= (uint32_t)(edge | RTC_CTL_TSEN); + + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + RTC_CTL = (uint32_t)reg_ctl; + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief disable RTC time-stamp + \param[in] none + \param[out] none + \retval none +*/ +void rtc_timestamp_disable(void) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* clear the TSEN bit */ + RTC_CTL &= (uint32_t)(~ RTC_CTL_TSEN); + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief get RTC timestamp time and date + \param[in] none + \param[out] rtc_timestamp: pointer to a rtc_timestamp_struct structure which contains + parameters for RTC time-stamp configuration + members of the structure and the member values are shown as below: + rtc_timestamp_month: RTC_JAN, RTC_FEB, RTC_MAR, RTC_APR, RTC_MAY, RTC_JUN, + RTC_JUL, RTC_AUG, RTC_SEP, RTC_OCT, RTC_NOV, RTC_DEC + rtc_timestamp_date: 0x1 - 0x31(BCD format) + rtc_timestamp_day: RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY, RTC_FRIDAY, + RTC_SATURDAY, RTC_SUNDAY if RTC_ALARM_WEEKDAY_SELECTED is set + rtc_timestamp_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format + rtc_timestamp_minute: 0x0 - 0x59(BCD format) + rtc_timestamp_second: 0x0 - 0x59(BCD format) + rtc_am_pm: RTC_AM, RTC_PM + \retval none +*/ +void rtc_timestamp_get(rtc_timestamp_struct* rtc_timestamp) +{ + uint32_t temp_tts = 0x00U, temp_dts = 0x00U; + + /* get the value of time_stamp registers */ + temp_tts = (uint32_t)RTC_TTS; + temp_dts = (uint32_t)RTC_DTS; + + /* get timestamp time and construct the rtc_timestamp_struct structure */ + rtc_timestamp->rtc_am_pm = (uint32_t)(temp_tts & RTC_TTS_PM); + rtc_timestamp->rtc_timestamp_month = (uint8_t)GET_DTS_MON(temp_dts); + rtc_timestamp->rtc_timestamp_date = (uint8_t)GET_DTS_DAY(temp_dts); + rtc_timestamp->rtc_timestamp_day = (uint8_t)GET_DTS_DOW(temp_dts); + rtc_timestamp->rtc_timestamp_hour = (uint8_t)GET_TTS_HR(temp_tts); + rtc_timestamp->rtc_timestamp_minute = (uint8_t)GET_TTS_MN(temp_tts); + rtc_timestamp->rtc_timestamp_second = (uint8_t)GET_TTS_SC(temp_tts); +} + +/*! + \brief get RTC time-stamp subsecond + \param[in] none + \param[out] none + \retval RTC time-stamp subsecond value +*/ +uint32_t rtc_timestamp_subsecond_get(void) +{ + return ((uint32_t)RTC_SSTS); +} + +/*! + \brief enable RTC tamper + \param[in] rtc_tamper: pointer to a rtc_tamper_struct structure which contains + parameters for RTC tamper configuration + members of the structure and the member values are shown as below: + rtc_tamper_source: RTC_TAMPER0, RTC_TAMPER1 + rtc_tamper_trigger: RTC_TAMPER_TRIGGER_EDGE_RISING, RTC_TAMPER_TRIGGER_EDGE_FALLING + RTC_TAMPER_TRIGGER_LEVEL_LOW, RTC_TAMPER_TRIGGER_LEVEL_HIGH + rtc_tamper_filter: RTC_FLT_EDGE, RTC_FLT_2S, RTC_FLT_4S, RTC_FLT_8S + rtc_tamper_sample_frequency: RTC_FREQ_DIV32768, RTC_FREQ_DIV16384, RTC_FREQ_DIV8192, + RTC_FREQ_DIV4096, RTC_FREQ_DIV2048, RTC_FREQ_DIV1024, + RTC_FREQ_DIV512, RTC_FREQ_DIV256 + rtc_tamper_precharge_enable: DISABLE, ENABLE + rtc_tamper_precharge_time: RTC_PRCH_1C, RTC_PRCH_2C, RTC_PRCH_4C, RTC_PRCH_8C + rtc_tamper_with_timestamp: DISABLE, ENABLE + \param[out] none + \retval none +*/ +void rtc_tamper_enable(rtc_tamper_struct* rtc_tamper) +{ + /* disable tamper */ + RTC_TAMP &= (uint32_t)~(rtc_tamper->rtc_tamper_source); + + /* tamper filter must be used when the tamper source is voltage level detection */ + RTC_TAMP &= (uint32_t)~RTC_TAMP_FLT; + + /* the tamper source is voltage level detection */ + if(rtc_tamper->rtc_tamper_filter != RTC_FLT_EDGE ){ + RTC_TAMP &= (uint32_t)~(RTC_TAMP_DISPU | RTC_TAMP_PRCH | RTC_TAMP_FREQ | RTC_TAMP_FLT); + + /* check if the tamper pin need precharge, if need, then configure the precharge time */ + if(DISABLE == rtc_tamper->rtc_tamper_precharge_enable){ + RTC_TAMP |= (uint32_t)RTC_TAMP_DISPU; + }else{ + RTC_TAMP |= (uint32_t)(rtc_tamper->rtc_tamper_precharge_time); + } + + RTC_TAMP |= (uint32_t)(rtc_tamper->rtc_tamper_sample_frequency); + RTC_TAMP |= (uint32_t)(rtc_tamper->rtc_tamper_filter); + } + + RTC_TAMP &= (uint32_t)~RTC_TAMP_TPTS; + + if(DISABLE != rtc_tamper->rtc_tamper_with_timestamp){ + /* the tamper event also cause a time-stamp event */ + RTC_TAMP |= (uint32_t)RTC_TAMP_TPTS; + } + + /* configure the tamper trigger */ + RTC_TAMP &= ((uint32_t)~((rtc_tamper->rtc_tamper_source) << RTC_TAMPER_TRIGGER_POS)); + if(RTC_TAMPER_TRIGGER_EDGE_RISING != rtc_tamper->rtc_tamper_trigger){ + RTC_TAMP |= (uint32_t)((rtc_tamper->rtc_tamper_source)<< RTC_TAMPER_TRIGGER_POS); + } + /* enable tamper */ + RTC_TAMP |= (uint32_t)(rtc_tamper->rtc_tamper_source); +} + +/*! + \brief disable RTC tamper + \param[in] source: specify which tamper source to be disabled + only one parameter can be selected which is shown as below: + \arg RTC_TAMPER0 + \arg RTC_TAMPER1 + \param[out] none + \retval none +*/ +void rtc_tamper_disable(uint32_t source) +{ + /* disable tamper */ + RTC_TAMP &= (uint32_t)~source; + +} + +/*! + \brief enable specified RTC interrupt + \param[in] interrupt: specify which interrupt source to be enabled + only one parameter can be selected which is shown as below: + \arg RTC_INT_TIMESTAMP: timestamp interrupt + \arg RTC_INT_ALARM: alarm interrupt + \arg RTC_INT_TAMP: tamp interrupt + \param[out] none + \retval none +*/ +void rtc_interrupt_enable(uint32_t interrupt) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* enable the interrupts in RTC_CTL register */ + RTC_CTL |= (uint32_t)(interrupt & (uint32_t)~RTC_TAMP_TPIE); + /* enable the interrupts in RTC_TAMP register */ + RTC_TAMP |= (uint32_t)(interrupt & RTC_TAMP_TPIE); + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief disble specified RTC interrupt + \param[in] interrupt: specify which interrupt source to be disabled + only one parameter can be selected which is shown as below: + \arg RTC_INT_TIMESTAMP: timestamp interrupt + \arg RTC_INT_ALARM: alarm interrupt + \arg RTC_INT_TAMP: tamp interrupt + \param[out] none + \retval none +*/ +void rtc_interrupt_disable(uint32_t interrupt) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* disable the interrupts in RTC_CTL register */ + RTC_CTL &= (uint32_t)~(interrupt & (uint32_t)~RTC_TAMP_TPIE); + /* disable the interrupts in RTC_TAMP register */ + RTC_TAMP &= (uint32_t)~(interrupt & RTC_TAMP_TPIE); + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief check specified flag + \param[in] flag: specify which flag to check + only one parameter can be selected which is shown as below: + \arg RTC_FLAG_RECALIBRATION: recalibration pending flag + \arg RTC_FLAG_TAMP1: tamper 1 event flag + \arg RTC_FLAG_TAMP0: tamper 0 event flag + \arg RTC_FLAG_TIMESTAMP_OVERFLOW: time-stamp overflow event flag + \arg RTC_FLAG_TIMESTAMP: time-stamp event flag + \arg RTC_FLAG_ALARM0: alarm event flag + \arg RTC_FLAG_INIT: init mode event flag + \arg RTC_FLAG_RSYN: time and date registers synchronized event flag + \arg RTC_FLAG_YCM: year parameter configured event flag + \arg RTC_FLAG_SHIFT: shift operation pending flag + \arg RTC_FLAG_ALARM0_WRITTEN: alarm writen available flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus rtc_flag_get(uint32_t flag) +{ + FlagStatus flag_state = RESET; + + if(RESET != (RTC_STAT & flag)){ + flag_state = SET; + } + return flag_state; +} + +/*! + \brief clear specified flag + \param[in] flag: specify which flag to clear + \arg RTC_FLAG_TAMP1: tamper 1 event flag + \arg RTC_FLAG_TAMP0: tamper 0 event flag + \arg RTC_FLAG_TIMESTAMP_OVERFLOW: time-stamp overflow event flag + \arg RTC_FLAG_TIMESTAMP: time-stamp event flag + \arg RTC_FLAG_ALARM0: alarm event flag + \arg RTC_FLAG_RSYN: time and date registers synchronized event flag + \param[out] none + \retval none +*/ +void rtc_flag_clear(uint32_t flag) +{ + RTC_STAT &= (uint32_t)(~flag); +} + +/*! + \brief configure rtc alternate output source + \param[in] source: specify signal to output + only one parameter can be selected which is shown as below: + \arg RTC_CALIBRATION_512HZ: when the LSE freqency is 32768Hz and the RTC_PSC + is the default value, output 512Hz signal + \arg RTC_CALIBRATION_1HZ: when the LSE freqency is 32768Hz and the RTC_PSC + is the default value, output 1Hz signal + \arg RTC_ALARM_HIGH: when the alarm flag is set, the output pin is high + \arg RTC_ALARM_LOW: when the Alarm flag is set, the output pin is low + \param[in] mode: specify the output pin (PC13) mode when output alarm signal + only one parameter can be selected which is shown as below: + \arg RTC_ALARM_OUTPUT_OD: open drain mode + \arg RTC_ALARM_OUTPUT_PP: push pull mode + \param[out] none + \retval none +*/ +void rtc_alter_output_config(uint32_t source, uint32_t mode) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + RTC_CTL &= (uint32_t)~(RTC_CTL_COEN | RTC_CTL_OS | RTC_CTL_OPOL | RTC_CTL_COS); + + RTC_CTL |= (uint32_t)(source); + + /* alarm output */ + if(RESET != (source & RTC_OS_ENABLE)){ + RTC_TAMP &= (uint32_t)~(RTC_TAMP_PC13VAL); + RTC_TAMP |= (uint32_t)(mode); + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + + +/*! + \brief configure RTC calibration register + \param[in] window: select calibration window + only one parameter can be selected which is shown as below: + \arg RTC_CALIBRATION_WINDOW_32S: 2exp20 RTCCLK cycles, 32s if RTCCLK = 32768 Hz + \arg RTC_CALIBRATION_WINDOW_16S: 2exp19 RTCCLK cycles, 16s if RTCCLK = 32768 Hz + \arg RTC_CALIBRATION_WINDOW_8S: 2exp18 RTCCLK cycles, 8s if RTCCLK = 32768 Hz + \param[in] plus: add RTC clock or not + only one parameter can be selected which is shown as below: + \arg RTC_CALIBRATION_PLUS_SET: add one RTC clock every 2048 rtc clock + \arg RTC_CALIBRATION_PLUS_RESET: no effect + \param[in] minus: the RTC clock to minus during the calibration window(0x0 - 0x1FF) + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_calibration_config(uint32_t window, uint32_t plus, uint32_t minus) +{ + uint32_t time_index = RTC_HRFC_TIMEOUT; + ErrStatus error_status = ERROR; + uint32_t flag_status = RESET; + + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* check if a calibration operation is ongoing */ + do{ + flag_status = RTC_STAT & RTC_STAT_SCPF; + }while((--time_index > 0x00U) && (RESET != flag_status)); + + if(RESET == flag_status){ + RTC_HRFC = (uint32_t)(window | plus | HRFC_CMSK(minus)); + error_status = SUCCESS; + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + + return error_status; +} + +/*! + \brief ajust the daylight saving time by adding or substracting one hour from the current time + \param[in] operation: hour ajustment operation + only one parameter can be selected which is shown as below: + \arg RTC_CTL_A1H: add one hour + \arg RTC_CTL_S1H: substract one hour + \param[out] none + \retval none +*/ +void rtc_hour_adjust(uint32_t operation) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + RTC_CTL |= (uint32_t)(operation); + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief ajust RTC second or subsecond value of current time + \param[in] add: add 1s to current time or not + only one parameter can be selected which is shown as below: + \arg RTC_SHIFT_ADD1S_RESET: no effect + \arg RTC_SHIFT_ADD1S_SET: add 1s to current time + \param[in] minus: number of subsecond to minus from current time(0x0 - 0x7FFF) + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_second_adjust(uint32_t add, uint32_t minus) +{ + uint32_t time_index = RTC_SHIFTCTL_TIMEOUT; + ErrStatus error_status = ERROR; + uint32_t flag_status = RESET; + uint32_t temp=0U; + + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* check if a shift operation is ongoing */ + do{ + flag_status = RTC_STAT & RTC_STAT_SOPF; + }while((--time_index > 0x00U) && (RESET != flag_status)); + + temp = RTC_CTL & RTC_CTL_REFEN; + /* check if the function of reference clock detection is disabled */ + if((RESET == flag_status) && (RESET == temp)){ + RTC_SHIFTCTL = (uint32_t)(add | SHIFTCTL_SFS(minus)); + error_status = rtc_register_sync_wait(); + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + + return error_status; +} + +/*! + \brief enable RTC bypass shadow registers function + \param[in] none + \param[out] none + \retval none +*/ +void rtc_bypass_shadow_enable(void) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + RTC_CTL |= (uint8_t)RTC_CTL_BPSHAD; + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief disable RTC bypass shadow registers function + \param[in] none + \param[out] none + \retval none +*/ +void rtc_bypass_shadow_disable(void) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + RTC_CTL &= (uint8_t)~RTC_CTL_BPSHAD; + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief enable RTC reference clock detection function + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_refclock_detection_enable(void) +{ + ErrStatus error_status = ERROR; + + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* enter init mode */ + error_status = rtc_init_mode_enter(); + + if(ERROR != error_status){ + RTC_CTL |= (uint32_t)RTC_CTL_REFEN; + /* exit init mode */ + rtc_init_mode_exit(); + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + + return error_status; +} + +/*! + \brief disable RTC reference clock detection function + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_refclock_detection_disable(void) +{ + ErrStatus error_status = ERROR; + + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* enter init mode */ + error_status = rtc_init_mode_enter(); + + if(ERROR != error_status){ + RTC_CTL &= (uint32_t)~RTC_CTL_REFEN; + /* exit init mode */ + rtc_init_mode_exit(); + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + + return error_status; +} + + diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_spi.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_spi.c new file mode 100644 index 0000000000..3aa2f3deb3 --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_spi.c @@ -0,0 +1,792 @@ +/*! + \file gd32f3x0_spi.c + \brief SPI driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f3x0_spi.h" + +#define SPI_INIT_MASK ((uint32_t)0x00003040U) /*!< SPI parameter initialization mask */ +#define I2S_INIT_MASK ((uint32_t)0x0000F047U) /*!< I2S parameter initialization mask */ + +#define SPI_I2SPSC_DEFAULT_VALUE ((uint32_t)0x00000002U) /*!< default value of SPI_I2SPSC register */ + +/*! + \brief reset SPI and I2S + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_i2s_deinit(uint32_t spi_periph) +{ + switch(spi_periph){ + case SPI0: + /* reset SPI0 and I2S0 */ + rcu_periph_reset_enable(RCU_SPI0RST); + rcu_periph_reset_disable(RCU_SPI0RST); + break; + case SPI1: + /* reset SPI1 */ + rcu_periph_reset_enable(RCU_SPI1RST); + rcu_periph_reset_disable(RCU_SPI1RST); + break; + default : + break; + } +} + +/*! + \brief initialize the parameters of SPI struct with the default values + \param[in] spi_struct: SPI parameter stuct + \param[out] none + \retval none +*/ +void spi_struct_para_init(spi_parameter_struct* spi_struct) +{ + /* set the SPI struct with the default values */ + spi_struct->device_mode = SPI_SLAVE; + spi_struct->trans_mode = SPI_TRANSMODE_FULLDUPLEX; + spi_struct->frame_size = SPI_FRAMESIZE_8BIT; + spi_struct->nss = SPI_NSS_HARD; + spi_struct->clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; + spi_struct->prescale = SPI_PSC_2; +} + +/*! + \brief initialize SPI parameter + \param[in] spi_periph: SPIx(x=0,1) + \param[in] spi_struct: SPI parameter initialization stuct members of the structure + and the member values are shown as below: + device_mode: SPI_MASTER, SPI_SLAVE + trans_mode: SPI_TRANSMODE_FULLDUPLEX, SPI_TRANSMODE_RECEIVEONLY, + SPI_TRANSMODE_BDRECEIVE, SPI_TRANSMODE_BDTRANSMIT + frame_size: SPI_FRAMESIZE_16BIT, SPI_FRAMESIZE_8BIT + nss: SPI_NSS_SOFT, SPI_NSS_HARD + endian: SPI_ENDIAN_MSB, SPI_ENDIAN_LSB + clock_polarity_phase: SPI_CK_PL_LOW_PH_1EDGE, SPI_CK_PL_HIGH_PH_1EDGE + SPI_CK_PL_LOW_PH_2EDGE, SPI_CK_PL_HIGH_PH_2EDGE + prescale: SPI_PSC_n (n=2,4,8,16,32,64,128,256) + \param[out] none + \retval none +*/ +void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct) +{ + uint32_t reg = 0U; + reg = SPI_CTL0(spi_periph); + reg &= SPI_INIT_MASK; + + /* select SPI as master or slave */ + reg |= spi_struct->device_mode; + /* select SPI transfer mode */ + reg |= spi_struct->trans_mode; + /* select SPI frame size */ + reg |= spi_struct->frame_size; + /* select SPI NSS use hardware or software */ + reg |= spi_struct->nss; + /* select SPI LSB or MSB */ + reg |= spi_struct->endian; + /* select SPI polarity and phase */ + reg |= spi_struct->clock_polarity_phase; + /* select SPI prescale to adjust transmit speed */ + reg |= spi_struct->prescale; + + /* write to SPI_CTL0 register */ + SPI_CTL0(spi_periph) = (uint32_t)reg; + + /* select SPI mode */ + SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SSEL); +} + +/*! + \brief enable SPI + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_enable(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN; +} + +/*! + \brief disable SPI + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_disable(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN); +} + + +#ifdef GD32F350 +/*! + \brief initialize I2S parameter + \param[in] spi_periph: SPI0 + \param[in] mode: I2S operation mode + only one parameter can be selected which is shown as below: + \arg I2S_MODE_SLAVETX: I2S slave transmit mode + \arg I2S_MODE_SLAVERX: I2S slave receive mode + \arg I2S_MODE_MASTERTX: I2S master transmit mode + \arg I2S_MODE_MASTERRX: I2S master receive mode + \param[in] standard: I2S standard + only one parameter can be selected which is shown as below: + \arg I2S_STD_PHILLIPS: I2S phillips standard + \arg I2S_STD_MSB: I2S MSB standard + \arg I2S_STD_LSB: I2S LSB standard + \arg I2S_STD_PCMSHORT: I2S PCM short standard + \arg I2S_STD_PCMLONG: I2S PCM long standard + \param[in] ckpl: I2S idle state clock polarity + only one parameter can be selected which is shown as below: + \arg I2S_CKPL_LOW: I2S clock polarity low level + \arg I2S_CKPL_HIGH: I2S clock polarity high level + \param[out] none + \retval none +*/ +void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl) +{ + uint32_t reg = 0U; + reg = SPI_I2SCTL(spi_periph); + reg &= I2S_INIT_MASK; + + /* enable I2S mode */ + reg |= (uint32_t)SPI_I2SCTL_I2SSEL; + /* select I2S mode */ + reg |= (uint32_t)mode; + /* select I2S standard */ + reg |= (uint32_t)standard; + /* select I2S polarity */ + reg |= (uint32_t)ckpl; + + /* write to SPI_I2SCTL register */ + SPI_I2SCTL(spi_periph) = (uint32_t)reg; +} + +/*! + \brief configure I2S prescaler + \param[in] spi_periph: SPI0 + \param[in] audiosample: I2S audio sample rate + only one parameter can be selected which is shown as below: + \arg I2S_AUDIOSAMPLE_8K: audio sample rate is 8KHz + \arg I2S_AUDIOSAMPLE_11K: audio sample rate is 11KHz + \arg I2S_AUDIOSAMPLE_16K: audio sample rate is 16KHz + \arg I2S_AUDIOSAMPLE_22K: audio sample rate is 22KHz + \arg I2S_AUDIOSAMPLE_32K: audio sample rate is 32KHz + \arg I2S_AUDIOSAMPLE_44K: audio sample rate is 44KHz + \arg I2S_AUDIOSAMPLE_48K: audio sample rate is 48KHz + \arg I2S_AUDIOSAMPLE_96K: audio sample rate is 96KHz + \arg I2S_AUDIOSAMPLE_192K: audio sample rate is 192KHz + \param[in] frameformat: I2S data length and channel length + only one parameter can be selected which is shown as below: + \arg I2S_FRAMEFORMAT_DT16B_CH16B: I2S data length is 16 bit and channel length is 16 bit + \arg I2S_FRAMEFORMAT_DT16B_CH32B: I2S data length is 16 bit and channel length is 32 bit + \arg I2S_FRAMEFORMAT_DT24B_CH32B: I2S data length is 24 bit and channel length is 32 bit + \arg I2S_FRAMEFORMAT_DT32B_CH32B: I2S data length is 32 bit and channel length is 32 bit + \param[in] mckout: I2S master clock output + only one parameter can be selected which is shown as below: + \arg I2S_MCKOUT_ENABLE: I2S master clock output enable + \arg I2S_MCKOUT_DISABLE: I2S master clock output disable + \param[out] none + \retval none +*/ +void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout) +{ + uint32_t i2sdiv = 2U, i2sof = 0U; + uint32_t clks = 0U; + uint32_t i2sclock = 0U; + + /* deinit SPI_I2SPSC register */ + SPI_I2SPSC(spi_periph) = SPI_I2SPSC_DEFAULT_VALUE; + + /* get system clock */ + i2sclock = rcu_clock_freq_get(CK_SYS); + + /* config the prescaler depending on the mclk output state, the frame format and audio sample rate */ + if(I2S_MCKOUT_ENABLE == mckout){ + clks = (uint32_t)(((i2sclock / 256U) * 10U) / audiosample); + }else{ + if(I2S_FRAMEFORMAT_DT16B_CH16B == frameformat){ + clks = (uint32_t)(((i2sclock / 32U) *10U ) / audiosample); + }else{ + clks = (uint32_t)(((i2sclock / 64U) *10U ) / audiosample); + } + } + + /* remove the floating point */ + clks = (clks + 5U) / 10U; + i2sof = (clks & 0x00000001U); + i2sdiv = ((clks - i2sof) / 2U); + i2sof = (i2sof << 8U); + + /* set the default values */ + if((i2sdiv < 2U) || (i2sdiv > 255U)){ + i2sdiv = 2U; + i2sof = 0U; + } + + /* configure SPI_I2SPSC */ + SPI_I2SPSC(spi_periph) = (uint32_t)(i2sdiv | i2sof | mckout); + + /* clear SPI_I2SCTL_DTLEN and SPI_I2SCTL_CHLEN bits */ + SPI_I2SCTL(spi_periph) &= (uint32_t)(~(SPI_I2SCTL_DTLEN | SPI_I2SCTL_CHLEN)); + /* configure data frame format */ + SPI_I2SCTL(spi_periph) |= (uint32_t)frameformat; +} + +/*! + \brief enable I2S + \param[in] spi_periph: SPI0 + \param[out] none + \retval none +*/ +void i2s_enable(uint32_t spi_periph) +{ + SPI_I2SCTL(spi_periph) |= (uint32_t)SPI_I2SCTL_I2SEN; +} + +/*! + \brief disable I2S + \param[in] spi_periph: SPI0 + \param[out] none + \retval none +*/ +void i2s_disable(uint32_t spi_periph) +{ + SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SEN); +} + +#endif /* GD32F350 */ + +/*! + \brief enable SPI NSS output + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_nss_output_enable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV; +} + +/*! + \brief disable SPI NSS output + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_nss_output_disable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV); +} + +/*! + \brief SPI NSS pin high level in software mode + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_nss_internal_high(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS; +} + +/*! + \brief SPI NSS pin low level in software mode + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_nss_internal_low(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS); +} + +/*! + \brief enable SPI DMA send or receive + \param[in] spi_periph: SPIx(x=0,1) + \param[in] dma: SPI DMA mode + only one parameter can be selected which is shown as below: + \arg SPI_DMA_TRANSMIT: SPI transmit data using DMA + \arg SPI_DMA_RECEIVE: SPI receive data using DMA + \param[out] none + \retval none +*/ +void spi_dma_enable(uint32_t spi_periph, uint8_t dma) +{ + if(SPI_DMA_TRANSMIT == dma){ + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN; + }else{ + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN; + } +} + +/*! + \brief disable SPI DMA send or receive + \param[in] spi_periph: SPIx(x=0,1) + \param[in] dma: SPI DMA mode + only one parameter can be selected which is shown as below: + \arg SPI_DMA_TRANSMIT: SPI transmit data using DMA + \arg SPI_DMA_RECEIVE: SPI receive data using DMA + \param[out] none + \retval none +*/ +void spi_dma_disable(uint32_t spi_periph, uint8_t dma) +{ + if(SPI_DMA_TRANSMIT == dma){ + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN); + }else{ + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN); + } +} + +/*! + \brief configure SPI/I2S data frame format + \param[in] spi_periph: SPIx(x=0,1) + \param[in] frame_format: SPI frame size + only one parameter can be selected which is shown as below: + \arg SPI_FRAMESIZE_16BIT: SPI frame size is 16 bits + \arg SPI_FRAMESIZE_8BIT: SPI frame size is 8 bits + \param[out] none + \retval none +*/ +void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format) +{ + /* clear SPI_CTL0_FF16 bit */ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16); + /* confige SPI_CTL0_FF16 bit */ + SPI_CTL0(spi_periph) |= (uint32_t)frame_format; +} + +/*! + \brief SPI transmit data + \param[in] spi_periph: SPIx(x=0,1) + \param[in] data: 16-bit data + \param[out] none + \retval none +*/ +void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data) +{ + SPI_DATA(spi_periph) = (uint32_t)data; +} + +/*! + \brief SPI receive data + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval 16-bit data +*/ +uint16_t spi_i2s_data_receive(uint32_t spi_periph) +{ + return ((uint16_t)SPI_DATA(spi_periph)); +} + +/*! + \brief configure SPI bidirectional transfer direction + \param[in] spi_periph: SPIx(x=0,1) + \param[in] transfer_direction: SPI transfer direction + only one parameter can be selected which is shown as below: + \arg SPI_BIDIRECTIONAL_TRANSMIT: SPI work in transmit-only mode + \arg SPI_BIDIRECTIONAL_RECEIVE: SPI work in receive-only mode + \param[out] none + \retval none +*/ +void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction) +{ + if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction){ + /* set the transmit only mode */ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT; + }else{ + /* set the receive only mode */ + SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE; + } +} + +/*! + \brief set CRC polynomial + \param[in] spi_periph: SPIx(x=0,1) + \param[in] crc_poly: CRC polynomial value + \param[out] none + \retval none +*/ +void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly) +{ + /* enable SPI CRC */ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; + /* set SPI CRC polynomial */ + SPI_CRCPOLY(spi_periph) = (uint32_t)crc_poly; +} + +/*! + \brief get SPI CRC polynomial + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval 16-bit CRC polynomial +*/ +uint16_t spi_crc_polynomial_get(uint32_t spi_periph) +{ + return ((uint16_t)SPI_CRCPOLY(spi_periph)); +} + +/*! + \brief turn on CRC function + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_crc_on(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; +} + +/*! + \brief turn off CRC function + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_crc_off(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCEN); +} + +/*! + \brief SPI next data is CRC value + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_crc_next(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCNT; +} + +/*! + \brief get SPI CRC send value or receive value + \param[in] spi_periph: SPIx(x=0,1) + \param[in] crc: SPI crc value + \arg SPI_CRC_TX: get transmit crc value + \arg SPI_CRC_RX: get receive crc value + \param[out] none + \retval 16-bit CRC value +*/ +uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc) +{ + if(SPI_CRC_TX == crc){ + return ((uint16_t)(SPI_TCRC(spi_periph))); + }else{ + return ((uint16_t)(SPI_RCRC(spi_periph))); + } +} + +/*! + \brief enable SPI TI mode + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_ti_mode_enable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD; +} + +/*! + \brief disable SPI TI mode + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_ti_mode_disable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD); +} + +/*! + \brief enable SPI NSS pulse mode + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_nssp_mode_enable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSP; +} + +/*! + \brief disable SPI NSS pulse mode + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_nssp_mode_disable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSP); +} + +/*! + \brief enable quad wire SPI + \param[in] spi_periph: SPI1 + \param[out] none + \retval none +*/ +void qspi_enable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QMOD; +} + +/*! + \brief disable quad wire SPI + \param[in] spi_periph: SPI1 + \param[out] none + \retval none +*/ +void qspi_disable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QMOD); +} + +/*! + \brief enable quad wire SPI write + \param[in] spi_periph: SPI1 + \param[out] none + \retval none +*/ +void qspi_write_enable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QRD); +} + +/*! + \brief enable quad wire SPI read + \param[in] spi_periph: SPI1 + \param[out] none + \retval none +*/ +void qspi_read_enable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QRD; +} + +/*! + \brief enable SPI_IO2 and SPI_IO3 pin output + \param[in] spi_periph: SPI1 + \param[out] none + \retval none +*/ +void qspi_io23_output_enable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_IO23_DRV; +} + + /*! + \brief disable SPI_IO2 and SPI_IO3 pin output + \param[in] spi_periph: SPI1 + \param[out] none + \retval none +*/ + void qspi_io23_output_disable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_IO23_DRV); +} + +/*! + \brief enable SPI and I2S interrupt + \param[in] spi_periph: SPIx(x=0,1) + \param[in] interrupt: SPI/I2S interrupt + only one parameter can be selected which is shown as below: + \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt + \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt + \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, + transmission underrun error and format error interrupt + \param[out] none + \retval none +*/ +void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt) +{ + switch(interrupt){ + /* SPI/I2S transmit buffer empty interrupt */ + case SPI_I2S_INT_TBE: + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE; + break; + /* SPI/I2S receive buffer not empty interrupt */ + case SPI_I2S_INT_RBNE: + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_RBNEIE; + break; + /* SPI/I2S error */ + case SPI_I2S_INT_ERR: + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE; + break; + default: + break; + } +} + +/*! + \brief disable SPI and I2S interrupt + \param[in] spi_periph: SPIx(x=0,1) + \param[in] interrupt: SPI/I2S interrupt + only one parameter can be selected which is shown as below: + \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt + \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt + \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, + transmission underrun error and format error interrupt + \param[out] none + \retval none +*/ +void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt) +{ + switch(interrupt){ + /* SPI/I2S transmit buffer empty interrupt */ + case SPI_I2S_INT_TBE: + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE); + break; + /* SPI/I2S receive buffer not empty interrupt */ + case SPI_I2S_INT_RBNE: + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RBNEIE); + break; + /* SPI/I2S error */ + case SPI_I2S_INT_ERR: + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE); + break; + default : + break; + } +} + +/*! + \brief get SPI and I2S interrupt flag status + \param[in] spi_periph: SPIx(x=0,1) + \param[in] interrupt: SPI/I2S interrupt flag status + only one parameter can be selected which is shown as below: + \arg SPI_I2S_INT_FLAG_TBE: transmit buffer empty interrupt flag + \arg SPI_I2S_INT_FLAG_RBNE: receive buffer not empty interrupt flag + \arg SPI_I2S_INT_FLAG_RXORERR: overrun interrupt flag + \arg SPI_INT_FLAG_CONFERR: config error interrupt flag + \arg SPI_INT_FLAG_CRCERR: CRC error interrupt flag + \arg I2S_INT_FLAG_TXURERR: underrun error interrupt flag + \arg SPI_I2S_INT_FLAG_FERR: format error interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt) +{ + uint32_t reg1 = SPI_STAT(spi_periph); + uint32_t reg2 = SPI_CTL1(spi_periph); + + switch(interrupt){ + /* SPI/I2S transmit buffer empty interrupt */ + case SPI_I2S_INT_FLAG_TBE: + reg1 = reg1 & SPI_STAT_TBE; + reg2 = reg2 & SPI_CTL1_TBEIE; + break; + /* SPI/I2S receive buffer not empty interrupt */ + case SPI_I2S_INT_FLAG_RBNE: + reg1 = reg1 & SPI_STAT_RBNE; + reg2 = reg2 & SPI_CTL1_RBNEIE; + break; + /* SPI/I2S overrun interrupt */ + case SPI_I2S_INT_FLAG_RXORERR: + reg1 = reg1 & SPI_STAT_RXORERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* SPI config error interrupt */ + case SPI_INT_FLAG_CONFERR: + reg1 = reg1 & SPI_STAT_CONFERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* SPI CRC error interrupt */ + case SPI_INT_FLAG_CRCERR: + reg1 = reg1 & SPI_STAT_CRCERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* I2S underrun error interrupt */ + case I2S_INT_FLAG_TXURERR: + reg1 = reg1 & SPI_STAT_TXURERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* SPI/I2S format error interrupt */ + case SPI_I2S_INT_FLAG_FERR: + reg1 = reg1 & SPI_STAT_FERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + default : + break; + } + /*get SPI/I2S interrupt flag status */ + if((0U != reg1) && (0U != reg2)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief get SPI and I2S flag status + \param[in] spi_periph: SPIx(x=0,1) + \param[in] flag: SPI/I2S flag status + one or more parameters can be selected which are shown as below: + \arg SPI_FLAG_TBE: transmit buffer empty flag + \arg SPI_FLAG_RBNE: receive buffer not empty flag + \arg SPI_FLAG_TRANS: transmit on-going flag + \arg SPI_FLAG_RXORERR: receive overrun error flag + \arg SPI_FLAG_CONFERR: mode config error flag + \arg SPI_FLAG_CRCERR: CRC error flag + \arg SPI_FLAG_FERR: format error interrupt flag + \arg I2S_FLAG_TBE: transmit buffer empty flag + \arg I2S_FLAG_RBNE: receive buffer not empty flag + \arg I2S_FLAG_TRANS: transmit on-going flag + \arg I2S_FLAG_RXORERR: overrun error flag + \arg I2S_FLAG_TXURERR: underrun error flag + \arg I2S_FLAG_CH: channel side flag + \arg I2S_FLAG_FERR: format error interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag) +{ + if(RESET != (SPI_STAT(spi_periph) & flag)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear SPI CRC error flag status + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_crc_error_clear(uint32_t spi_periph) +{ + SPI_STAT(spi_periph) &= (uint32_t)(~SPI_FLAG_CRCERR); +} diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_syscfg.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_syscfg.c new file mode 100644 index 0000000000..7a4aef5fc6 --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_syscfg.c @@ -0,0 +1,227 @@ +/*! + \file gd32f3x0_syscfg.c + \brief SYSCFG driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f3x0_syscfg.h" + +/*! + \brief reset the SYSCFG registers + \param[in] none + \param[out] none + \retval none +*/ +void syscfg_deinit(void) +{ + rcu_periph_reset_enable(RCU_CFGCMPRST); + rcu_periph_reset_disable(RCU_CFGCMPRST); +} + +/*! + \brief enable the DMA channels remapping + \param[in] syscfg_dma_remap: specify the DMA channels to remap + one or more parameters can be selected which is shown as below: + \arg SYSCFG_DMA_REMAP_TIMER16: remap TIMER16 channel0 and UP DMA requests to channel1(defaut channel0) + \arg SYSCFG_DMA_REMAP_TIMER15: remap TIMER15 channel2 and UP DMA requests to channel3(defaut channel2) + \arg SYSCFG_DMA_REMAP_USART0RX: remap USART0 Rx DMA request to channel4(default channel2) + \arg SYSCFG_DMA_REMAP_USART0TX: remap USART0 Tx DMA request to channel3(default channel1) + \arg SYSCFG_DMA_REMAP_ADC: remap ADC DMA requests from channel0 to channel1 + \param[out] none + \retval none +*/ +void syscfg_dma_remap_enable(uint32_t syscfg_dma_remap) +{ + SYSCFG_CFG0 |= syscfg_dma_remap; +} + +/*! + \brief disable the DMA channels remapping + \param[in] syscfg_dma_remap: specify the DMA channels to remap + one or more parameters can be selected which is shown as below: + \arg SYSCFG_DMA_REMAP_TIMER16: remap TIMER16 channel0 and UP DMA requests to channel1(defaut channel0) + \arg SYSCFG_DMA_REMAP_TIMER15: remap TIMER15 channel2 and UP DMA requests to channel3(defaut channel2) + \arg SYSCFG_DMA_REMAP_USART0RX: remap USART0 Rx DMA request to channel4(default channel2) + \arg SYSCFG_DMA_REMAP_USART0TX: remap USART0 Tx DMA request to channel3(default channel1) + \arg SYSCFG_DMA_REMAP_ADC: remap ADC DMA requests from channel0 to channel1 + \param[out] none + \retval none +*/ +void syscfg_dma_remap_disable(uint32_t syscfg_dma_remap) +{ + SYSCFG_CFG0 &= ~syscfg_dma_remap; +} + +/*! + \brief enable PB9 high current capability + \param[in] none + \param[out] none + \retval none +*/ +void syscfg_high_current_enable(void) +{ + SYSCFG_CFG0 |= SYSCFG_HIGH_CURRENT_ENABLE; +} + +/*! + \brief disable PB9 high current capability + \param[in] none + \param[out] none + \retval none +*/ +void syscfg_high_current_disable(void) +{ + SYSCFG_CFG0 &= SYSCFG_HIGH_CURRENT_DISABLE; +} + +/*! + \brief configure the GPIO pin as EXTI Line + \param[in] exti_port: specify the GPIO port used in EXTI + only one parameter can be selected which is shown as below: + \arg EXTI_SOURCE_GPIOx(x = A,B,C,D,F): EXTI GPIO port + \param[in] exti_pin: specify the EXTI line + only one parameter can be selected which is shown as below: + \arg EXTI_SOURCE_PINx(x = 0..15): EXTI GPIO pin + \param[out] none + \retval none +*/ +void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin) +{ + uint32_t clear_exti_mask = ~((uint32_t)EXTI_SS_MASK << (EXTI_SS_MSTEP(exti_pin))); + uint32_t config_exti_mask = ((uint32_t)exti_port) << (EXTI_SS_MSTEP(exti_pin)); + + switch(exti_pin / EXTI_SS_JSTEP){ + case EXTISS0: + /* clear EXTI source line(0..3) */ + SYSCFG_EXTISS0 &= clear_exti_mask; + /* configure EXTI soure line(0..3) */ + SYSCFG_EXTISS0 |= config_exti_mask; + break; + case EXTISS1: + /* clear EXTI soure line(4..7) */ + SYSCFG_EXTISS1 &= clear_exti_mask; + /* configure EXTI soure line(4..7) */ + SYSCFG_EXTISS1 |= config_exti_mask; + break; + case EXTISS2: + /* clear EXTI soure line(8..11) */ + SYSCFG_EXTISS2 &= clear_exti_mask; + /* configure EXTI soure line(8..11) */ + SYSCFG_EXTISS2 |= config_exti_mask; + break; + case EXTISS3: + /* clear EXTI soure line(12..15) */ + SYSCFG_EXTISS3 &= clear_exti_mask; + /* configure EXTI soure line(12..15) */ + SYSCFG_EXTISS3 |= config_exti_mask; + break; + default: + break; + } +} + +/*! + \brief connect TIMER0/14/15/16 break input to the selected parameter + \param[in] syscfg_lock: Specify the parameter to be connected + one or more parameters can be selected which is shown as below: + \arg SYSCFG_LOCK_LOCKUP: Cortex-M4 lockup output connected to the break input + \arg SYSCFG_LOCK_SRAM_PARITY_ERROR: SRAM_PARITY check error connected to the break input + \arg SYSCFG_LOCK_LVD: LVD interrupt connected to the break input + \param[out] none + \retval none +*/ +void syscfg_lock_config(uint32_t syscfg_lock) +{ + SYSCFG_CFG2 |= syscfg_lock; +} + +/*! + \brief check if the specified flag in SYSCFG_CFG2 is set or not. + \param[in] syscfg_flag: specify the flag in SYSCFG_CFG2 to check. + \arg SYSCFG_SRAM_PCEF: SRAM parity check error flag. + \param[out] none + \retval the syscfg_flag state returned (SET or RESET). + */ +FlagStatus syscfg_flag_get(uint32_t syscfg_flag) +{ + if((SYSCFG_CFG2 & syscfg_flag) != (uint32_t)RESET){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear the flag in SYSCFG_CFG2 by writing 1. + \param[in] syscfg_flag: Specify the flag in SYSCFG_CFG2 to clear. + \arg SYSCFG_SRAM_PCEF: SRAM parity check error flag. + \param[out] none + \retval none +*/ +void syscfg_flag_clear(uint32_t syscfg_flag) +{ + SYSCFG_CFG2 |= (uint32_t) syscfg_flag; +} + +/*! + \brief configure the I/O compensation cell + \param[in] syscfg_compensation: specifies the I/O compensation cell mode + only one parameter can be selected which is shown as below: + \arg SYSCFG_COMPENSATION_ENABLE: I/O compensation cell is enabled + \arg SYSCFG_COMPENSATION_DISABLE: I/O compensation cell is disabled + \param[out] none + \retval none +*/ +void syscfg_compensation_config(uint32_t syscfg_compensation) +{ + uint32_t reg; + + reg = SYSCFG_CPSCTL; + /* reset the SYSCFG_CPSCTL_CPS_EN bit and set according to syscfg_compensation */ + reg &= ~SYSCFG_CPSCTL_CPS_EN; + SYSCFG_CPSCTL = (reg | syscfg_compensation); +} + +/*! + \brief check if the I/O compensation cell ready flag is set or not + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET + */ +FlagStatus syscfg_cps_rdy_flag_get(void) +{ + if(((uint32_t)RESET) != (SYSCFG_CPSCTL & SYSCFG_CPSCTL_CPS_RDY)){ + return SET; + }else{ + return RESET; + } +} diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_timer.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_timer.c new file mode 100644 index 0000000000..0e34c59618 --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_timer.c @@ -0,0 +1,2063 @@ +/*! + \file gd32f3x0_timer.c + \brief TIMER driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + +#include "gd32f3x0_timer.h" + +/*! + \brief deinit a TIMER + \param[in] timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 + \param[out] none + \retval none +*/ +void timer_deinit(uint32_t timer_periph) +{ + switch(timer_periph){ + case TIMER0: + /* reset TIMER0 */ + rcu_periph_reset_enable(RCU_TIMER0RST); + rcu_periph_reset_disable(RCU_TIMER0RST); + break; + case TIMER1: + /* reset TIMER1 */ + rcu_periph_reset_enable(RCU_TIMER1RST); + rcu_periph_reset_disable(RCU_TIMER1RST); + break; + case TIMER2: + /* reset TIMER2 */ + rcu_periph_reset_enable(RCU_TIMER2RST); + rcu_periph_reset_disable(RCU_TIMER2RST); + break; +#ifdef GD32F350 + case TIMER5: + /* reset TIMER5 */ + rcu_periph_reset_enable(RCU_TIMER5RST); + rcu_periph_reset_disable(RCU_TIMER5RST); + break; +#endif + case TIMER13: + /* reset TIMER13 */ + rcu_periph_reset_enable(RCU_TIMER13RST); + rcu_periph_reset_disable(RCU_TIMER13RST); + break; + case TIMER14: + /* reset TIMER14 */ + rcu_periph_reset_enable(RCU_TIMER14RST); + rcu_periph_reset_disable(RCU_TIMER14RST); + break; + case TIMER15: + /* reset TIMER15 */ + rcu_periph_reset_enable(RCU_TIMER15RST); + rcu_periph_reset_disable(RCU_TIMER15RST); + break; + case TIMER16: + /* reset TIMER16 */ + rcu_periph_reset_enable(RCU_TIMER16RST); + rcu_periph_reset_disable(RCU_TIMER16RST); + break; + default: + break; + } +} + +/*! + \brief initialize TIMER init parameter struct with a default value + \param[in] initpara: init parameter struct + \param[out] none + \retval none +*/ +void timer_struct_para_init(timer_parameter_struct* initpara) +{ + /* initialize the init parameter struct member with the default value */ + initpara->prescaler = 0U; + initpara->alignedmode = TIMER_COUNTER_EDGE; + initpara->counterdirection = TIMER_COUNTER_UP; + initpara->period = 65535U; + initpara->clockdivision = TIMER_CKDIV_DIV1; + initpara->repetitioncounter = 0U; +} + +/*! + \brief initialize TIMER counter + \param[in] timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 + \param[in] timer_initpara: init parameter struct + prescaler: prescaler value of the counter clock,0~65535 + alignedmode: TIMER_COUNTER_EDGE,TIMER_COUNTER_CENTER_DOWN,TIMER_COUNTER_CENTER_UP,TIMER_COUNTER_CENTER_BOTH + counterdirection: TIMER_COUNTER_UP,TIMER_COUNTER_DOWN + period: counter auto reload value,(TIMER1 32 bit) + clockdivision: TIMER_CKDIV_DIV1,TIMER_CKDIV_DIV2,TIMER_CKDIV_DIV4 + repetitioncounter: counter repetition value,0~255 + \param[out] none + \retval none +*/ +void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara) +{ + /* configure the counter prescaler value */ + TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler; + + /* configure the counter direction and aligned mode */ + if((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph)){ + TIMER_CTL0(timer_periph) &= ~(uint32_t)(TIMER_CTL0_DIR|TIMER_CTL0_CAM); + TIMER_CTL0(timer_periph) |= (uint32_t)initpara->alignedmode; + TIMER_CTL0(timer_periph) |= (uint32_t)initpara->counterdirection; + } + + /* configure the autoreload value */ + TIMER_CAR(timer_periph) = (uint32_t)initpara->period; + + if((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph) || (TIMER13 == timer_periph) + || (TIMER14 == timer_periph) || (TIMER15 == timer_periph) || (TIMER16 == timer_periph)){ + /* reset the CKDIV bit */ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CKDIV; + TIMER_CTL0(timer_periph) |= (uint32_t)initpara->clockdivision; + } + + if((TIMER0 == timer_periph) || (TIMER14 == timer_periph) || (TIMER15 == timer_periph) || (TIMER16 == timer_periph)){ + /* configure the repetition counter value */ + TIMER_CREP(timer_periph) = (uint32_t)initpara->repetitioncounter; + } + + /* generate an update event */ + TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; +} + +/*! + \brief enable a TIMER + \param[in] timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 + \param[out] none + \retval none +*/ +void timer_enable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_CEN; +} + +/*! + \brief disable a TIMER + \param[in] timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 + \param[out] none + \retval none +*/ +void timer_disable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CEN; +} + +/*! + \brief enable the auto reload shadow function + \param[in] timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 + \param[out] none + \retval none +*/ +void timer_auto_reload_shadow_enable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_ARSE; +} + +/*! + \brief disable the auto reload shadow function + \param[in] timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 + \param[out] none + \retval none +*/ +void timer_auto_reload_shadow_disable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_ARSE; +} + +/*! + \brief enable the update event + \param[in] timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 + \param[out] none + \retval none +*/ +void timer_update_event_enable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPDIS; +} + +/*! + \brief disable the update event + \param[in] timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 + \param[out] none + \retval none +*/ +void timer_update_event_disable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t) TIMER_CTL0_UPDIS; +} + +/*! + \brief set TIMER counter alignment mode + \param[in] timer_periph: TIMERx(x=0..2) + \param[in] aligned: + only one parameter can be selected which is shown as below: + \arg TIMER_COUNTER_EDGE: edge-aligned mode + \arg TIMER_COUNTER_CENTER_DOWN: center-aligned and counting down assert mode + \arg TIMER_COUNTER_CENTER_UP: center-aligned and counting up assert mode + \arg TIMER_COUNTER_CENTER_BOTH: center-aligned and counting up/down assert mode + \param[out] none + \retval none +*/ +void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CAM; + TIMER_CTL0(timer_periph) |= (uint32_t)aligned; +} + +/*! + \brief set TIMER counter up direction + \param[in] timer_periph: TIMERx(x=0..2) + \param[out] none + \retval none +*/ +void timer_counter_up_direction(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_DIR; +} + +/*! + \brief set TIMER counter down direction + \param[in] timer_periph: TIMERx(x=0..2) + \param[out] none + \retval none +*/ +void timer_counter_down_direction(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_DIR; +} + +/*! + \brief configure TIMER prescaler + \param[in] timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 + \param[in] prescaler: prescaler value + \param[in] pscreload: prescaler reload mode + only one parameter can be selected which is shown as below: + \arg TIMER_PSC_RELOAD_NOW: the prescaler is loaded right now + \arg TIMER_PSC_RELOAD_UPDATE: the prescaler is loaded at the next update event + \param[out] none + \retval none +*/ +void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload) +{ + TIMER_PSC(timer_periph) = (uint32_t)prescaler; + + if(TIMER_PSC_RELOAD_NOW == pscreload){ + TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; + } +} + +/*! + \brief configure TIMER repetition register value + \param[in] timer_periph: TIMERx(x=0,15,16) + \param[in] repetition: the counter repetition value,0~255 + \param[out] none + \retval none +*/ +void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition) +{ + TIMER_CREP(timer_periph) = (uint32_t)repetition; +} + +/*! + \brief configure TIMER autoreload register value + \param[in] timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 + \param[in] autoreload: the counter auto-reload value + \param[out] none + \retval none +*/ +void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload) +{ + TIMER_CAR(timer_periph) = (uint32_t)autoreload; +} + +/*! + \brief configure TIMER counter register value + \param[in] timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 + \param[in] counter: the counter value + \param[out] none + \retval none +*/ +void timer_counter_value_config(uint32_t timer_periph, uint32_t counter) +{ + TIMER_CNT(timer_periph) = (uint32_t)counter; +} + +/*! + \brief read TIMER counter value + \param[in] timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 + \param[out] none + \retval counter value +*/ +uint32_t timer_counter_read(uint32_t timer_periph) +{ + uint32_t count_value = 0U; + count_value = TIMER_CNT(timer_periph); + return (count_value); +} + +/*! + \brief read TIMER prescaler value + \param[in] timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 + \param[out] none + \retval prescaler register value +*/ +uint16_t timer_prescaler_read(uint32_t timer_periph) +{ + uint16_t prescaler_value = 0U; + prescaler_value = (uint16_t)(TIMER_PSC(timer_periph)); + return (prescaler_value); +} + +/*! + \brief configure TIMER single pulse mode + \param[in] timer_periph: TIMERx(x=0..2,14..16),TIMER5 just for GD32F350 + \param[in] spmode: + only one parameter can be selected which is shown as below: + \arg TIMER_SP_MODE_SINGLE: single pulse mode + \arg TIMER_SP_MODE_REPETITIVE: repetitive pulse mode + \param[out] none + \retval none +*/ +void timer_single_pulse_mode_config(uint32_t timer_periph, uint8_t spmode) +{ + if(TIMER_SP_MODE_SINGLE == spmode){ + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM; + }else if(TIMER_SP_MODE_REPETITIVE == spmode){ + TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM); + }else{ + /* illegal parameters */ + } +} + +/*! + \brief configure TIMER update source + \param[in] timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 + \param[in] update: + only one parameter can be selected which is shown as below: + \arg TIMER_UPDATE_SRC_GLOBAL: update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger + \arg TIMER_UPDATE_SRC_REGULAR: update generate only by counter overflow/underflow + \param[out] none + \retval none +*/ +void timer_update_source_config(uint32_t timer_periph, uint8_t update) +{ + if(TIMER_UPDATE_SRC_REGULAR == update){ + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS; + }else if(TIMER_UPDATE_SRC_GLOBAL == update){ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS; + }else{ + /* illegal parameters */ + } +} + +/*! + \brief configure TIMER OCPRE clear source selection + \param[in] timer_periph: TIMERx(x=0..2) + \param[in] ocpreclear: + only one parameter can be selected which is shown as below: + \arg TIMER_OCPRE_CLEAR_SOURCE_CLR: OCPRE_CLR_INT is connected to the OCPRE_CLR input + \arg TIMER_OCPRE_CLEAR_SOURCE_ETIF: OCPRE_CLR_INT is connected to ETIF + \param[out] none + \retval none +*/ +void timer_ocpre_clear_source_config(uint32_t timer_periph, uint8_t ocpreclear) +{ + if(TIMER_OCPRE_CLEAR_SOURCE_ETIF == ocpreclear){ + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_OCRC; + }else if(TIMER_OCPRE_CLEAR_SOURCE_CLR == ocpreclear){ + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_OCRC; + }else{ + /* illegal parameters */ + } +} + +/*! + \brief enable the TIMER interrupt + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: timer interrupt enable source + only one parameter can be selected which is shown as below: + \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 + \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..2,13..16) + \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..2,14) + \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..2) + \arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..2) + \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,14..16) + \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..2,14) + \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,14..16) + \param[out] none + \retval none +*/ +void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt) +{ + TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt; +} + +/*! + \brief disable the TIMER interrupt + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: timer interrupt source disable + only one parameter can be selected which is shown as below: + \arg TIMER_INT_UP: update interrupt disable, TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 + \arg TIMER_INT_CH0: channel 0 interrupt disable, TIMERx(x=0..2,13..16) + \arg TIMER_INT_CH1: channel 1 interrupt disable, TIMERx(x=0..2,14) + \arg TIMER_INT_CH2: channel 2 interrupt disable, TIMERx(x=0..2) + \arg TIMER_INT_CH3: channel 3 interrupt disable , TIMERx(x=0..2) + \arg TIMER_INT_CMT: commutation interrupt disable, TIMERx(x=0,14..16) + \arg TIMER_INT_TRG: trigger interrupt disable, TIMERx(x=0..2,14) + \arg TIMER_INT_BRK: break interrupt disable, TIMERx(x=0,14..16) + \param[out] none + \retval none +*/ +void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt) +{ + TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt); +} + +/*! + \brief get timer interrupt flag + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: the timer interrupt bits + only one parameter can be selected which is shown as below: + \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 + \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..2,13..16) + \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..2,14) + \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..2) + \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..2) + \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,14..16) + \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0..2,14) + \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,14..16) + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt) +{ + uint32_t val; + val = (TIMER_DMAINTEN(timer_periph) & interrupt); + if((RESET != (TIMER_INTF(timer_periph) & interrupt) ) && (RESET != val)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear TIMER interrupt flag + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: the timer interrupt bits + only one parameter can be selected which is shown as below: + \arg TIMER_INT_FLAG_UP: update interrupt flag, TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 + \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag, TIMERx(x=0..2,13..16) + \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag, TIMERx(x=0..2,14) + \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag, TIMERx(x=0..2) + \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag, TIMERx(x=0..2) + \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag, TIMERx(x=0,14..16) + \arg TIMER_INT_FLAG_TRG: trigger interrupt flag, TIMERx(x=0..2,14) + \arg TIMER_INT_FLAG_BRK: break interrupt flag, TIMERx(x=0,14..16) + \param[out] none + \retval none +*/ +void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt) +{ + TIMER_INTF(timer_periph) = (~(uint32_t)interrupt); +} + +/*! + \brief get TIMER flags + \param[in] timer_periph: please refer to the following parameters + \param[in] flag: the timer interrupt flags + only one parameter can be selected which is shown as below: + \arg TIMER_FLAG_UP: update flag, TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 + \arg TIMER_FLAG_CH0: channel 0 flag, TIMERx(x=0..2,13..16) + \arg TIMER_FLAG_CH1: channel 1 flag, TIMERx(x=0..2,14) + \arg TIMER_FLAG_CH2: channel 2 flag, TIMERx(x=0..2) + \arg TIMER_FLAG_CH3: channel 3 flag, TIMERx(x=0..2) + \arg TIMER_FLAG_CMT: channel control update flag, TIMERx(x=0,14..16) + \arg TIMER_FLAG_TRG: trigger flag, TIMERx(x=0..2,14) + \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,14..16) + \arg TIMER_FLAG_CH0O: channel 0 overcapture flag, TIMERx(x=0..2,13..16) + \arg TIMER_FLAG_CH1O: channel 1 overcapture flag, TIMERx(x=0..2,14) + \arg TIMER_FLAG_CH2O: channel 2 overcapture flag, TIMERx(x=0..2) + \arg TIMER_FLAG_CH3O: channel 3 overcapture flag, TIMERx(x=0..2) + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag) +{ + if(RESET != (TIMER_INTF(timer_periph) & flag)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear TIMER flags + \param[in] timer_periph: please refer to the following parameters + \param[in] flag: the timer interrupt flags + only one parameter can be selected which is shown as below: + \arg TIMER_FLAG_UP: update flag, TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 + \arg TIMER_FLAG_CH0: channel 0 flag, TIMERx(x=0..2,13..16) + \arg TIMER_FLAG_CH1: channel 1 flag, TIMERx(x=0..2,14) + \arg TIMER_FLAG_CH2: channel 2 flag, TIMERx(x=0..2) + \arg TIMER_FLAG_CH3: channel 3 flag, TIMERx(x=0..2) + \arg TIMER_FLAG_CMT: channel control update flag, TIMERx(x=0,14..16) + \arg TIMER_FLAG_TRG: trigger flag, TIMERx(x=0..2,14) + \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,14..16) + \arg TIMER_FLAG_CH0O: channel 0 overcapture flag, TIMERx(x=0..2,13..16) + \arg TIMER_FLAG_CH1O: channel 1 overcapture flag, TIMERx(x=0..2,14) + \arg TIMER_FLAG_CH2O: channel 2 overcapture flag, TIMERx(x=0..2) + \arg TIMER_FLAG_CH3O: channel 3 overcapture flag, TIMERx(x=0..2) + \param[out] none + \retval none +*/ +void timer_flag_clear(uint32_t timer_periph, uint32_t flag) +{ + TIMER_INTF(timer_periph) = (~(uint32_t)flag); +} + +/*! + \brief enable the TIMER DMA + \param[in] timer_periph: please refer to the following parameters + \param[in] dma: specify which DMA to enable + one or more parameters can be selected which is shown as below: + \arg TIMER_DMA_UPD: update DMA, TIMERx(x=0..2,14..16),TIMER5 just for GD32F350 + \arg TIMER_DMA_CH0D: channel 0 DMA request, TIMERx(x=0..2,14..16) + \arg TIMER_DMA_CH1D: channel 1 DMA request, TIMERx(x=0..2,14) + \arg TIMER_DMA_CH2D: channel 2 DMA request, TIMERx(x=0..2) + \arg TIMER_DMA_CH3D: channel 3 DMA request, TIMERx(x=0..2) + \arg TIMER_DMA_CMTD: commutation DMA request, TIMERx(x=0,14) + \arg TIMER_DMA_TRGD: trigger DMA request, TIMERx(x=0..2,14) + \param[out] none + \retval none +*/ +void timer_dma_enable(uint32_t timer_periph, uint16_t dma) +{ + TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma; +} + +/*! + \brief disable the TIMER DMA + \param[in] timer_periph: please refer to the following parameters + \param[in] dma: specify which DMA to disable + one or more parameters can be selected which are shown as below: + \arg TIMER_DMA_UPD: update DMA, TIMERx(x=0..2,14..16),TIMER5 just for GD32F350 + \arg TIMER_DMA_CH0D: channel 0 DMA request, TIMERx(x=0..2,14..16) + \arg TIMER_DMA_CH1D: channel 1 DMA request, TIMERx(x=0..2,14) + \arg TIMER_DMA_CH2D: channel 2 DMA request, TIMERx(x=0..2) + \arg TIMER_DMA_CH3D: channel 3 DMA request, TIMERx(x=0..2) + \arg TIMER_DMA_CMTD: commutation DMA request , TIMERx(x=0,14) + \arg TIMER_DMA_TRGD: trigger DMA request, TIMERx(x=0..2,14) + \param[out] none + \retval none +*/ +void timer_dma_disable(uint32_t timer_periph, uint16_t dma) +{ + TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma)); +} + +/*! + \brief channel DMA request source selection + \param[in] timer_periph: TIMERx(x=0..2,14..16) + \param[in] dma_request: channel DMA request source selection + only one parameter can be selected which is shown as below: + \arg TIMER_DMAREQUEST_CHANNELEVENT: DMA request of channel y is sent when channel y event occurs + \arg TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel y is sent when update event occurs + \param[out] none + \retval none +*/ +void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request) +{ + if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request){ + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS; + }else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request){ + TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS; + }else{ + /* illegal parameters */ + } +} + +/*! + \brief configure the TIMER DMA transfer + \param[in] timer_periph: TIMERx(x=0..2,14..16) + \param[in] dma_baseaddr: + only one parameter can be selected which is shown as below: + \arg TIMER_DMACFG_DMATA_CTL0: DMA transfer address is TIMER_CTL0, TIMERx(x=0..2,14..16) + \arg TIMER_DMACFG_DMATA_CTL1: DMA transfer address is TIMER_CTL1, TIMERx(x=0..2,14..16) + \arg TIMER_DMACFG_DMATA_SMCFG: DMA transfer address is TIMER_SMCFG, TIMERx(x=0..2,14) + \arg TIMER_DMACFG_DMATA_DMAINTEN: DMA transfer address is TIMER_DMAINTEN, TIMERx(x=0..2,14..16) + \arg TIMER_DMACFG_DMATA_INTF: DMA transfer address is TIMER_INTF, TIMERx(x=0..2,14..16) + \arg TIMER_DMACFG_DMATA_SWEVG: DMA transfer address is TIMER_SWEVG, TIMERx(x=0..2,14..16) + \arg TIMER_DMACFG_DMATA_CHCTL0: DMA transfer address is TIMER_CHCTL0, TIMERx(x=0..2,14..16) + \arg TIMER_DMACFG_DMATA_CHCTL1: DMA transfer address is TIMER_CHCTL1, TIMERx(x=0..2) + \arg TIMER_DMACFG_DMATA_CHCTL2: DMA transfer address is TIMER_CHCTL2, TIMERx(x=0..2,14..16) + \arg TIMER_DMACFG_DMATA_CNT: DMA transfer address is TIMER_CNT, TIMERx(x=0..2,14..16) + \arg TIMER_DMACFG_DMATA_PSC: DMA transfer address is TIMER_PSC, TIMERx(x=0..2,14..16) + \arg TIMER_DMACFG_DMATA_CAR: DMA transfer address is TIMER_CAR, TIMERx(x=0..2,14..16) + \arg TIMER_DMACFG_DMATA_CREP: DMA transfer address is TIMER_CREP, TIMERx(x=0,14..16) + \arg TIMER_DMACFG_DMATA_CH0CV: DMA transfer address is TIMER_CH0CV, TIMERx(x=0..2,14..16) + \arg TIMER_DMACFG_DMATA_CH1CV: DMA transfer address is TIMER_CH1CV, TIMERx(x=0..2,14) + \arg TIMER_DMACFG_DMATA_CH2CV: DMA transfer address is TIMER_CH2CV, TIMERx(x=0..2) + \arg TIMER_DMACFG_DMATA_CH3CV: DMA transfer address is TIMER_CH3CV, TIMERx(x=0..2) + \arg TIMER_DMACFG_DMATA_CCHP: DMA transfer address is TIMER_CCHP, TIMERx(x=0,14..16) + \arg TIMER_DMACFG_DMATA_DMACFG: DMA transfer address is TIMER_DMACFG, TIMERx(x=0..2,14..16) + \arg TIMER_DMACFG_DMATA_DMATB: DMA transfer address is TIMER_DMATB, TIMERx(x=0..2,14..16) + \param[in] dma_lenth: + only one parameter can be selected which is shown as below: + \arg TIMER_DMACFG_DMATC_xTRANSFER(x=1..18): DMA transfer x time + \param[out] none + \retval none +*/ +void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth) +{ + TIMER_DMACFG(timer_periph) &= (~(uint32_t)(TIMER_DMACFG_DMATA | TIMER_DMACFG_DMATC)); + TIMER_DMACFG(timer_periph) |= (uint32_t)(dma_baseaddr | dma_lenth); +} + +/*! + \brief software generate events + \param[in] timer_periph: please refer to the following parameters + \param[in] event: the timer software event generation sources + one or more parameters can be selected which are shown as below: + \arg TIMER_EVENT_SRC_UPG: update event,TIMERx(x=0..2,13..16), TIMER5 just for GD32F350 + \arg TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation, TIMERx(x=0..2,13..16) + \arg TIMER_EVENT_SRC_CH1G: channel 1 capture or compare event generation, TIMERx(x=0..2,14) + \arg TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation, TIMERx(x=0..2) + \arg TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation, TIMERx(x=0..2) + \arg TIMER_EVENT_SRC_CMTG: channel commutation event generation, TIMERx(x=0,14..16) + \arg TIMER_EVENT_SRC_TRGG: trigger event generation, TIMERx(x=0..2,14) + \arg TIMER_EVENT_SRC_BRKG: break event generation, TIMERx(x=0,14..16) + \param[out] none + \retval none +*/ +void timer_event_software_generate(uint32_t timer_periph, uint16_t event) +{ + TIMER_SWEVG(timer_periph) |= (uint32_t)event; +} + +/*! + \brief initialize TIMER break parameter struct with a default value + \param[in] breakpara: TIMER break parameter struct + \param[out] none + \retval none +*/ +void timer_break_struct_para_init(timer_break_parameter_struct* breakpara) +{ + /* initialize the break parameter struct member with the default value */ + breakpara->runoffstate = TIMER_ROS_STATE_DISABLE; + breakpara->ideloffstate = TIMER_IOS_STATE_DISABLE; + breakpara->deadtime = 0U; + breakpara->breakpolarity = TIMER_BREAK_POLARITY_LOW; + breakpara->outputautostate = TIMER_OUTAUTO_DISABLE; + breakpara->protectmode = TIMER_CCHP_PROT_OFF; + breakpara->breakstate = TIMER_BREAK_DISABLE; +} + +/*! + \brief configure TIMER break function + \param[in] timer_periph: TIMERx(x=0,14..16) + \param[in] breakpara: TIMER break parameter struct + runoffstate: TIMER_ROS_STATE_ENABLE,TIMER_ROS_STATE_DISABLE + ideloffstate: TIMER_IOS_STATE_ENABLE,TIMER_IOS_STATE_DISABLE + deadtime: 0~255 + breakpolarity: TIMER_BREAK_POLARITY_LOW,TIMER_BREAK_POLARITY_HIGH + outputautostate: TIMER_OUTAUTO_ENABLE,TIMER_OUTAUTO_DISABLE + protectmode: TIMER_CCHP_PROT_OFF,TIMER_CCHP_PROT_0,TIMER_CCHP_PROT_1,TIMER_CCHP_PROT_2 + breakstate: TIMER_BREAK_ENABLE,TIMER_BREAK_DISABLE + \param[out] none + \retval none +*/ +void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara) +{ + TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate))| + ((uint32_t)(breakpara->ideloffstate))| + ((uint32_t)(breakpara->deadtime))| + ((uint32_t)(breakpara->breakpolarity))| + ((uint32_t)(breakpara->outputautostate)) | + ((uint32_t)(breakpara->protectmode))| + ((uint32_t)(breakpara->breakstate))) ; +} + +/*! + \brief enable TIMER break function + \param[in] timer_periph: TIMERx(x=0,14..16) + \param[out] none + \retval none +*/ +void timer_break_enable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_BRKEN; +} + +/*! + \brief disable TIMER break function + \param[in] timer_periph: TIMERx(x=0,14..16) + \param[out] none + \retval none +*/ +void timer_break_disable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_BRKEN; +} + +/*! + \brief enable TIMER output automatic function + \param[in] timer_periph: TIMERx(x=0,14..16) + \param[out] none + \retval none +*/ +void timer_automatic_output_enable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_OAEN; +} + +/*! + \brief disable TIMER output automatic function + \param[in] timer_periph: TIMERx(x=0,14..16) + \param[out] none + \retval none +*/ +void timer_automatic_output_disable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_OAEN; +} + +/*! + \brief configure TIMER primary output function + \param[in] timer_periph: TIMERx(x=0,14..16) + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue) +{ + if(ENABLE == newvalue){ + TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN; + }else{ + TIMER_CCHP(timer_periph) &= (~(uint32_t)TIMER_CCHP_POEN); + } +} + +/*! + \brief enable or disable channel capture/compare control shadow register + \param[in] timer_periph: TIMERx(x=0,14..16) + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue) +{ + if(ENABLE == newvalue){ + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE; + }else{ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE); + } +} + +/*! + \brief configure TIMER channel control shadow register update control + \param[in] timer_periph: TIMERx(x=0,14..16) + \param[in] ccuctl: channel control shadow register update control + only one parameter can be selected which is shown as below: + \arg TIMER_UPDATECTL_CCU: the shadow registers update by when CMTG bit is set + \arg TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs + \param[out] none + \retval none +*/ +void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl) +{ + if(TIMER_UPDATECTL_CCU == ccuctl){ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC); + }else if(TIMER_UPDATECTL_CCUTRI == ccuctl){ + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC; + }else{ + /* illegal parameters */ + } +} + +/*! + \brief initialize TIMER channel output parameter struct with a default value + \param[in] ocpara: TIMER channel n output parameter struct + \param[out] none + \retval none +*/ +void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara) +{ + /* initialize the channel output parameter struct member with the default value */ + ocpara->outputstate = (uint16_t)TIMER_CCX_DISABLE; + ocpara->outputnstate = TIMER_CCXN_DISABLE; + ocpara->ocpolarity = TIMER_OC_POLARITY_HIGH; + ocpara->ocnpolarity = TIMER_OCN_POLARITY_HIGH; + ocpara->ocidlestate = TIMER_OC_IDLE_STATE_LOW; + ocpara->ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; +} + +/*! + \brief configure TIMER channel output function + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..2,13..16)) + \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..2,14)) + \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..2)) + \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..2)) + \param[in] ocpara: TIMER channeln output parameter struct + outputstate: TIMER_CCX_ENABLE,TIMER_CCX_DISABLE + outputnstate: TIMER_CCXN_ENABLE,TIMER_CCXN_DISABLE + ocpolarity: TIMER_OC_POLARITY_HIGH,TIMER_OC_POLARITY_LOW + ocnpolarity: TIMER_OCN_POLARITY_HIGH,TIMER_OCN_POLARITY_LOW + ocidlestate: TIMER_OC_IDLE_STATE_LOW,TIMER_OC_IDLE_STATE_HIGH + ocnidlestate: TIMER_OCN_IDLE_STATE_LOW,TIMER_OCN_IDLE_STATE_HIGH + \param[out] none + \retval none +*/ +void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH0MS; + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputstate; + /* reset the CH0P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); + /* set the CH0P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocpolarity; + + if((TIMER0 == timer_periph) || (TIMER14 == timer_periph) || (TIMER15 == timer_periph) || (TIMER16 == timer_periph)){ + /* reset the CH0NEN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); + /* set the CH0NEN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputnstate; + /* reset the CH0NP bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); + /* set the CH0NP bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocnpolarity; + /* reset the ISO0 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0); + /* set the ISO0 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate; + /* reset the ISO0N bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N); + /* set the ISO0N bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate; + } + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH1MS; + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)(ocpara->outputstate << 4U); + /* reset the CH1P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); + /* set the CH1P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 4U); + + if(TIMER0 == timer_periph){ + /* reset the CH1NEN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); + /* set the CH1NEN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 4U); + /* reset the CH1NP bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); + /* set the CH1NP bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 4U); + /* reset the ISO1 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1); + /* set the ISO1 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 2U); + /* reset the ISO1N bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1N); + /* set the ISO1N bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 2U); + } + + if(TIMER14 == timer_periph){ + /* reset the ISO1 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1); + /* set the ISO1 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 2U); + } + + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + /* reset the CH2EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); + TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH2MS; + /* set the CH2EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)(ocpara->outputstate << 8U); + /* reset the CH2P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); + /* set the CH2P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 8U); + + if(TIMER0 == timer_periph){ + /* reset the CH2NEN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); + /* set the CH2NEN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 8U); + /* reset the CH2NP bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); + /* set the CH2NP bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 8U); + /* reset the ISO2 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2); + /* set the ISO2 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 4U); + /* reset the ISO2N bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2N); + /* set the ISO2N bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 4U); + } + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + /* reset the CH3EN bit */ + TIMER_CHCTL2(timer_periph) &=(~(uint32_t)TIMER_CHCTL2_CH3EN); + TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH3MS; + /* set the CH3EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)(ocpara->outputstate << 12U); + /* reset the CH3P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); + /* set the CH3P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 12U); + + if(TIMER0 == timer_periph){ + /* reset the ISO3 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO3); + /* set the ISO3 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 6U); + } + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output compare mode + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..2)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..2)) + \param[in] ocmode: channel output compare mode + only one parameter can be selected which is shown as below: + \arg TIMER_OC_MODE_TIMING: timing mode + \arg TIMER_OC_MODE_ACTIVE: active mode + \arg TIMER_OC_MODE_INACTIVE: inactive mode + \arg TIMER_OC_MODE_TOGGLE: toggle mode + \arg TIMER_OC_MODE_LOW: force low mode + \arg TIMER_OC_MODE_HIGH: force high mode + \arg TIMER_OC_MODE_PWM0: PWM0 mode + \arg TIMER_OC_MODE_PWM1: PWM1 mode + \param[out] none + \retval none +*/ +void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCTL); + TIMER_CHCTL0(timer_periph) |= (uint32_t)ocmode; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCTL); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCTL); + TIMER_CHCTL1(timer_periph) |= (uint32_t)ocmode; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output pulse value + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..2)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..2)) + \param[in] pulse: channel output pulse value,0~65535 + \param[out] none + \retval none +*/ +void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CH0CV(timer_periph) = (uint32_t)pulse; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CH1CV(timer_periph) = (uint32_t)pulse; + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CH2CV(timer_periph) = (uint32_t)pulse; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CH3CV(timer_periph) = (uint32_t)pulse; + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output shadow function + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..2)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..2)) + \param[in] ocshadow: channel output shadow state + only one parameter can be selected which is shown as below: + \arg TIMER_OC_SHADOW_ENABLE: channel output shadow state enable + \arg TIMER_OC_SHADOW_DISABLE: channel output shadow state disable + \param[out] none + \retval none +*/ +void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMSEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)ocshadow; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMSEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMSEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)ocshadow; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMSEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output fast function + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..2)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..2)) + \param[in] ocfast: channel output fast function + only one parameter can be selected which is shown as below: + \arg TIMER_OC_FAST_ENABLE: channel output fast function enable + \arg TIMER_OC_FAST_DISABLE: channel output fast function disable + \param[out] none + \retval none +*/ +void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMFEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)ocfast; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMFEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMFEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)ocfast; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMFEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output clear function + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..2)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..2)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..2)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..2)) + \param[in] occlear: channel output clear function + only one parameter can be selected which is shown as below: + \arg TIMER_OC_CLEAR_ENABLE: channel output clear function enable + \arg TIMER_OC_CLEAR_DISABLE: channel output clear function disable + \param[out] none + \retval none +*/ +void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)occlear; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)occlear; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output polarity + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..2)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..2)) + \param[in] ocpolarity: channel output polarity + only one parameter can be selected which is shown as below: + \arg TIMER_OC_POLARITY_HIGH: channel output polarity is high + \arg TIMER_OC_POLARITY_LOW: channel output polarity is low + \param[out] none + \retval none +*/ +void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpolarity; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 8U); + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 12U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel complementary output polarity + \param[in] timer_periph: TIMERx(x=0..2,14) + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..2)) + \arg TIMER_CH_3: TIMER channel2(TIMERx(x=1,2)) + \param[in] ocnpolarity: channel complementary output polarity + only one parameter can be selected which is shown as below: + \arg TIMER_OCN_POLARITY_HIGH: channel complementary output polarity is high + \arg TIMER_OCN_POLARITY_LOW: channel complementary output polarity is low + \param[out] none + \retval none +*/ +void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnpolarity; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 8U); + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3NP); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 12U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel enable state + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..2)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..2)) + \param[in] state: TIMER channel enable state + only one parameter can be selected which is shown as below: + \arg TIMER_CCX_ENABLE: channel enable + \arg TIMER_CCX_DISABLE: channel disable + \param[out] none + \retval none +*/ +void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)state; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 8U); + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 12U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel complementary output enable state + \param[in] timer_periph: TIMERx(x=0,14..16) + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,14..16)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0)) + \param[in] ocnstate: TIMER channel complementary output enable state + only one parameter can be selected which is shown as below: + \arg TIMER_CCXN_ENABLE: channel complementary enable + \arg TIMER_CCXN_DISABLE: channel complementary disable + \param[out] none + \retval none +*/ +void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnstate; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 8U); + break; + default: + break; + } +} + +/*! + \brief initialize TIMER channel input parameter struct with a default value + \param[in] icpara: TIMER channel intput parameter struct + \param[out] none + \retval none +*/ +void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara) +{ + /* initialize the channel input parameter struct member with the default value */ + icpara->icpolarity = TIMER_IC_POLARITY_RISING; + icpara->icselection = TIMER_IC_SELECTION_DIRECTTI; + icpara->icprescaler = TIMER_IC_PSC_DIV1; + icpara->icfilter = 0U; +} + +/*! + \brief configure TIMER input capture parameter + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..2)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..2)) + \param[in] icpara: TIMER channel intput parameter struct + icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING,TIMER_IC_POLARITY_BOTH_EDGE + icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI,TIMER_IC_SELECTION_ITS + icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8 + icfilter: 0~15 + \param[out] none + \retval none +*/ +void timer_input_capture_config(uint32_t timer_periph,uint16_t channel, timer_ic_parameter_struct* icpara) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + + /* reset the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpara->icpolarity); + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpara->icselection); + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); + + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + break; + + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + + /* reset the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 4U); + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U); + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); + + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + /* reset the CH2EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); + + /* reset the CH2P and CH2NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH2P|TIMER_CHCTL2_CH2NP)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 8U); + + /* reset the CH2MS bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2MS); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection)); + + /* reset the CH2CAPFLT bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPFLT); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); + + /* set the CH2EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH2EN; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + /* reset the CH3EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); + + /* reset the CH3P and CH3NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH3P|TIMER_CHCTL2_CH3NP)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 12U); + + /* reset the CH3MS bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3MS); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U); + + /* reset the CH3CAPFLT bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPFLT); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); + + /* set the CH3EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH3EN; + break; + default: + break; + } + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph, channel, (uint16_t)(icpara->icprescaler)); +} + +/*! + \brief configure TIMER channel input capture prescaler value + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..2)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..2)) + \param[in] prescaler: channel input capture prescaler value + only one parameter can be selected which is shown as below: + \arg TIMER_IC_PSC_DIV1: no prescaler + \arg TIMER_IC_PSC_DIV2: divided by 2 + \arg TIMER_IC_PSC_DIV4: divided by 4 + \arg TIMER_IC_PSC_DIV8: divided by 8 + \param[out] none + \retval none +*/ +void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPPSC); + TIMER_CHCTL0(timer_periph) |= (uint32_t)prescaler; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPPSC); + TIMER_CHCTL0(timer_periph) |= ((uint32_t)prescaler << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPPSC); + TIMER_CHCTL1(timer_periph) |= (uint32_t)prescaler; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPPSC); + TIMER_CHCTL1(timer_periph) |= ((uint32_t)prescaler << 8U); + break; + default: + break; + } +} + +/*! + \brief read TIMER channel capture compare register value + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..2)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..2)) + \param[out] none + \retval channel capture compare register value +*/ +uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel) +{ + uint32_t count_value = 0U; + + switch(channel){ + /* read TIMER channel 0 capture compare register value */ + case TIMER_CH_0: + count_value = TIMER_CH0CV(timer_periph); + break; + /* read TIMER channel 1 capture compare register value */ + case TIMER_CH_1: + count_value = TIMER_CH1CV(timer_periph); + break; + /* read TIMER channel 2 capture compare register value */ + case TIMER_CH_2: + count_value = TIMER_CH2CV(timer_periph); + break; + /* read TIMER channel 3 capture compare register value */ + case TIMER_CH_3: + count_value = TIMER_CH3CV(timer_periph); + break; + default: + break; + } + return (count_value); +} + +/*! + \brief configure TIMER input pwm capture function + \param[in] timer_periph: TIMERx(x=0..2,14) + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0 + \arg TIMER_CH_1: TIMER channel1 + \param[in] icpwm:TIMER channel intput pwm parameter struct + icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING + icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI + icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8 + icfilter: 0~15 + \param[out] none + \retval none +*/ +void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm) +{ + uint16_t icpolarity = 0x0U; + uint16_t icselection = 0x0U; + + /* Set channel input polarity */ + if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity){ + icpolarity = TIMER_IC_POLARITY_FALLING; + }else{ + icpolarity = TIMER_IC_POLARITY_RISING; + } + + /* Set channel input mode selection */ + if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection){ + icselection = TIMER_IC_SELECTION_INDIRECTTI; + }else{ + icselection = TIMER_IC_SELECTION_DIRECTTI; + } + + if(TIMER_CH_0 == channel){ + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + /* reset the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); + /* set the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpwm->icpolarity); + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + /* set the CH0MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpwm->icselection); + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + /* set the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_0,(uint16_t)(icpwm->icprescaler)); + + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + /* reset the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); + /* set the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity << 4U); + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + /* set the CH1MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection << 8U); + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + /* set the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U); + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_1,(uint16_t)(icpwm->icprescaler)); + }else{ + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + /* reset the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); + /* set the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icpolarity) << 4U); + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + /* set the CH1MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icselection) << 8U); + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + /* set the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U); + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler)); + + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + /* reset the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); + /* set the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)icpolarity; + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + /* set the CH0MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)icselection; + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + /* set the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler)); + } +} + +/*! + \brief configure TIMER hall sensor mode + \param[in] timer_periph: TIMERx(x=0..2) + \param[in] hallmode: + only one parameter can be selected which is shown as below: + \arg TIMER_HALLINTERFACE_ENABLE: TIMER hall sensor mode enable + \arg TIMER_HALLINTERFACE_DISABLE: TIMER hall sensor mode disable + \param[out] none + \retval none +*/ +void timer_hall_mode_config(uint32_t timer_periph, uint8_t hallmode) +{ + if(TIMER_HALLINTERFACE_ENABLE == hallmode){ + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S; + }else if(TIMER_HALLINTERFACE_DISABLE == hallmode){ + TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S; + }else{ + /* illegal parameters */ + } +} + +/*! + \brief select TIMER input trigger source + \param[in] timer_periph: TIMERx(x=0..2,14) + \param[in] intrigger: + only one parameter can be selected which is shown as below: + \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0(TIMERx(x=0..2,14)) + \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1(TIMERx(x=0..2,14)) + \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2(TIMERx(x=0..2)) + \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector(TIMERx(x=0..2,14)) + \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0(TIMERx(x=0..2,14)) + \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1(TIMERx(x=0..2,14)) + \arg TIMER_SMCFG_TRGSEL_ETIFP: external trigger(TIMERx(x=0..2)) + \param[out] none + \retval none +*/ +void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger) +{ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_TRGS); + TIMER_SMCFG(timer_periph) |= (uint32_t)intrigger; +} + +/*! + \brief select TIMER master mode output trigger source + \param[in] timer_periph: TIMERx(x=0..2,14),TIMER5 just for GD32F350 + \param[in] outrigger: + only one parameter can be selected which is shown as below: + \arg TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output(TIMERx(x=0..2,14),TIMER5 just for GD32F350) + \arg TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal TIMER_CTL0_CEN as trigger output(TIMERx(x=0..2,14),TIMER5 just for GD32F350) + \arg TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output(TIMERx(x=0..2,14),TIMER5 just for GD32F350) + \arg TIMER_TRI_OUT_SRC_CH0: a capture or a compare match occurred in channal0 as trigger output TRGO + \arg TIMER_TRI_OUT_SRC_O0CPRE: O0CPRE as trigger output(TIMERx(x=0..2,14)) + \arg TIMER_TRI_OUT_SRC_O1CPRE: O1CPRE as trigger output(TIMERx(x=0..2,14)) + \arg TIMER_TRI_OUT_SRC_O2CPRE: O2CPRE as trigger output(TIMERx(x=0..2,14)) + \arg TIMER_TRI_OUT_SRC_O3CPRE: O3CPRE as trigger output(TIMERx(x=0..2,14)) + \param[out] none + \retval none +*/ +void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger) +{ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_MMC); + TIMER_CTL1(timer_periph) |= (uint32_t)outrigger; +} + +/*! + \brief select TIMER slave mode + \param[in] timer_periph: TIMERx(x=0..2,14) + \param[in] slavemode: + only one parameter can be selected which is shown as below: + \arg TIMER_SLAVE_MODE_DISABLE: slave mode disable(TIMERx(x=0..2,14)) + \arg TIMER_ENCODER_MODE0: encoder mode 0(TIMERx(x=0..2)) + \arg TIMER_ENCODER_MODE1: encoder mode 1(TIMERx(x=0..2)) + \arg TIMER_ENCODER_MODE2: encoder mode 2(TIMERx(x=0..2)) + \arg TIMER_SLAVE_MODE_RESTART: restart mode(TIMERx(x=0..2,14)) + \arg TIMER_SLAVE_MODE_PAUSE: pause mode(TIMERx(x=0..2,14)) + \arg TIMER_SLAVE_MODE_EVENT: event mode(TIMERx(x=0..2,14)) + \arg TIMER_SLAVE_MODE_EXTERNAL0: external clock mode 0(TIMERx(x=0..2,14)) + \param[out] none + \retval none +*/ + +void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode) +{ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); + + TIMER_SMCFG(timer_periph) |= (uint32_t)slavemode; +} + +/*! + \brief configure TIMER master slave mode + \param[in] timer_periph: TIMERx(x=0..2,14) + \param[in] masterslave: + only one parameter can be selected which is shown as below: + \arg TIMER_MASTER_SLAVE_MODE_ENABLE: master slave mode enable + \arg TIMER_MASTER_SLAVE_MODE_DISABLE: master slave mode disable + \param[out] none + \retval none +*/ +void timer_master_slave_mode_config(uint32_t timer_periph, uint8_t masterslave) +{ + if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave){ + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM; + }else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave){ + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM; + }else{ + /* illegal parameters */ + } +} + +/*! + \brief configure TIMER external trigger input + \param[in] timer_periph: TIMERx(x=0..2) + \param[in] extprescaler: + only one parameter can be selected which is shown as below: + \arg TIMER_EXT_TRI_PSC_OFF: no divided + \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 + \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 + \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 + \param[in] extpolarity: + only one parameter can be selected which is shown as below: + \arg TIMER_ETP_FALLING: active low or falling edge active + \arg TIMER_ETP_RISING: active high or rising edge active + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, + uint32_t extpolarity, uint32_t extfilter) +{ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_ETP | TIMER_SMCFG_ETPSC | TIMER_SMCFG_ETFC)); + TIMER_SMCFG(timer_periph) |= (uint32_t)(extprescaler | extpolarity); + TIMER_SMCFG(timer_periph) |= (uint32_t)(extfilter << 8U); +} + +/*! + \brief configure TIMER quadrature decoder mode + \param[in] timer_periph: TIMERx(x=0..2) + \param[in] decomode: + only one parameter can be selected which is shown as below: + \arg TIMER_ENCODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level + \arg TIMER_ENCODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level + \arg TIMER_ENCODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input + \param[in] ic0polarity: + only one parameter can be selected which is shown as below: + \arg TIMER_IC_POLARITY_RISING: capture rising edge + \arg TIMER_IC_POLARITY_FALLING: capture falling edge + \param[in] ic1polarity: + only one parameter can be selected which is shown as below: + \arg TIMER_IC_POLARITY_RISING: capture rising edge + \arg TIMER_IC_POLARITY_FALLING: capture falling edge + \param[out] none + \retval none +*/ +void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, + uint16_t ic0polarity, uint16_t ic1polarity) +{ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); + TIMER_SMCFG(timer_periph) |= (uint32_t)decomode; + + TIMER_CHCTL0(timer_periph) &= (uint32_t)(((~(uint32_t)TIMER_CHCTL0_CH0MS))&((~(uint32_t)TIMER_CHCTL0_CH1MS))); + TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI|((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U)); + + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); + TIMER_CHCTL2(timer_periph) |= ((uint32_t)ic0polarity|((uint32_t)ic1polarity << 4U)); +} + +/*! + \brief configure TIMER internal clock mode + \param[in] timer_periph: TIMERx(x=0..2,14) + \param[out] none + \retval none +*/ +void timer_internal_clock_config(uint32_t timer_periph) +{ + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; +} + +/*! + \brief configure TIMER the internal trigger as external clock input + \param[in] timer_periph: TIMERx(x=0..2,14) + \param[in] intrigger: + only one parameter can be selected which is shown as below: + \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0(TIMERx(x=0..2,14)) + \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1(TIMERx(x=0..2,14)) + \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2(TIMERx(x=0..2)) + \param[out] none + \retval none +*/ +void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger) +{ + timer_input_trigger_source_select(timer_periph, intrigger); + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; +} + +/*! + \brief configure TIMER the external trigger as external clock input + \param[in] timer_periph: TIMERx(x=0..2,14) + \param[in] extrigger: + only one parameter can be selected which is shown as below: + \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector + \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0 + \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1 + \param[in] extpolarity: + only one parameter can be selected which is shown as below: + \arg TIMER_IC_POLARITY_RISING: active high or rising edge active + \arg TIMER_IC_POLARITY_FALLING: active low or falling edge active + \arg TIMER_IC_POLARITY_BOTH_EDGE: active both edge + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, + uint16_t extpolarity, uint32_t extfilter) +{ + if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger){ + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + /* reset the CH1NP bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); + /* set the CH1NP bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)extpolarity << 4U); + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + /* set the CH1MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U); + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + /* set the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 8U); + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + }else{ + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + /* reset the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); + /* set the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)extpolarity; + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + /* set the CH0MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)TIMER_IC_SELECTION_DIRECTTI; + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)extfilter; + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + } + /* select TIMER input trigger source */ + timer_input_trigger_source_select(timer_periph,extrigger); + /* reset the SMC bit */ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); + /* set the SMC bit */ + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; +} + +/*! + \brief configure TIMER the external clock mode0 + \param[in] timer_periph: TIMERx(x=0..2) + \param[in] extprescaler: + only one parameter can be selected which is shown as below: + \arg TIMER_EXT_TRI_PSC_OFF: no divided + \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 + \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 + \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 + \param[in] extpolarity: + only one parameter can be selected which is shown as below: + \arg TIMER_ETP_FALLING: active low or falling edge active + \arg TIMER_ETP_RISING: active high or rising edge active + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, + uint32_t extpolarity, uint32_t extfilter) +{ + /* configure TIMER external trigger input */ + timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter); + + /* reset the SMC bit,TRGS bit */ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_SMC | TIMER_SMCFG_TRGS)); + /* set the SMC bit,TRGS bit */ + TIMER_SMCFG(timer_periph) |= (uint32_t)(TIMER_SLAVE_MODE_EXTERNAL0 | TIMER_SMCFG_TRGSEL_ETIFP); +} + +/*! + \brief configure TIMER the external clock mode1 + \param[in] timer_periph: TIMERx(x=0..2) + \param[in] extprescaler: + only one parameter can be selected which is shown as below: + \arg TIMER_EXT_TRI_PSC_OFF: no divided + \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 + \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 + \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 + \param[in] extpolarity: + only one parameter can be selected which is shown as below: + \arg TIMER_ETP_FALLING: active low or falling edge active + \arg TIMER_ETP_RISING: active high or rising edge active + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, + uint32_t extpolarity, uint32_t extfilter) +{ + /* configure TIMER external trigger input */ + timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter); + + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_SMC1; +} + +/*! + \brief disable TIMER the external clock mode1 + \param[in] timer_periph: TIMERx(x=0..2) + \param[out] none + \retval none +*/ +void timer_external_clock_mode1_disable(uint32_t timer_periph) +{ + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC1; +} + +/*! + \brief configure TIMER channel remap function + \param[in] timer_periph: TIMERx(x=13) + \param[in] remap: + only one parameter can be selected which is shown as below: + \arg TIMER13_CI0_RMP_GPIO: timer13 channel 0 input is connected to GPIO(TIMER13_CH0) + \arg TIMER13_CI0_RMP_RTCCLK: timer13 channel 0 input is connected to the RTCCLK + \arg TIMER13_CI0_RMP_HXTAL_DIV32: timer13 channel 0 input is connected to HXTAL/32 clock + \arg TIMER13_CI0_RMP_CKOUTSEL: timer13 channel 0 input is connected to CKOUTSEL + \param[out] none + \retval none +*/ +void timer_channel_remap_config(uint32_t timer_periph, uint32_t remap) +{ + TIMER_IRMP(timer_periph) = (uint32_t)remap; +} + +/*! + \brief configure TIMER write CHxVAL register selection + \param[in] timer_periph: TIMERx(x=0..2,13..16) + \param[in] ccsel: + only one parameter can be selected which is shown as below: + \arg TIMER_CHVSEL_DISABLE: no effect + \arg TIMER_CHVSEL_ENABLE: when write the CHxVAL register, if the write value is same as the CHxVAL value, the write access is ignored + \param[out] none + \retval none +*/ +void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel) +{ + if(TIMER_CHVSEL_ENABLE == ccsel){ + TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_CHVSEL; + }else if(TIMER_CHVSEL_DISABLE == ccsel){ + TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_CHVSEL; + }else{ + /* illegal parameters */ + } +} + +/*! + \brief configure TIMER output value selection + \param[in] timer_periph: TIMERx(x=0,14..16) + \param[in] outsel: + only one parameter can be selected which is shown as below: + \arg TIMER_OUTSEL_DISABLE: no effect + \arg TIMER_OUTSEL_ENABLE: if POEN and IOS is 0, the output disabled + \param[out] none + \retval none +*/ +void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel) +{ + if(TIMER_OUTSEL_ENABLE == outsel){ + TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_OUTSEL; + }else if(TIMER_OUTSEL_DISABLE == outsel){ + TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_OUTSEL; + }else{ + /* illegal parameters */ + } +} diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_tsi.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_tsi.c new file mode 100644 index 0000000000..5a0bf95fec --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_tsi.c @@ -0,0 +1,686 @@ +/*! + \file gd32f3x0_tsi.c + \brief TSI driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f3x0_tsi.h" + +/*! + \brief reset TSI peripheral + \param[in] none + \param[out] none + \retval none +*/ +void tsi_deinit(void) +{ + rcu_periph_reset_enable(RCU_TSIRST); + rcu_periph_reset_disable(RCU_TSIRST); +} + +/*! + \brief initialize TSI plus prescaler,charge plus,transfer plus,max cycle number + \param[in] prescaler: CTCLK clock division factor + only one parameter can be selected which is shown as below: + \arg TSI_CTCDIV_DIV1: fCTCLK = fHCLK + \arg TSI_CTCDIV_DIV2: fCTCLK = fHCLK/2 + \arg TSI_CTCDIV_DIV4: fCTCLK = fHCLK/4 + \arg TSI_CTCDIV_DIV8: fCTCLK = fHCLK/8 + \arg TSI_CTCDIV_DIV16: fCTCLK = fHCLK/16 + \arg TSI_CTCDIV_DIV32: fCTCLK = fHCLK/32 + \arg TSI_CTCDIV_DIV64: fCTCLK = fHCLK/64 + \arg TSI_CTCDIV_DIV128: fCTCLK = fHCLK/128 + \arg TSI_CTCDIV_DIV256: fCTCLK = fHCLK/256 + \arg TSI_CTCDIV_DIV512: fCTCLK = fHCLK/512 + \arg TSI_CTCDIV_DIV1024: fCTCLK = fHCLK/1024 + \arg TSI_CTCDIV_DIV2048: fCTCLK = fHCLK/2048 + \arg TSI_CTCDIV_DIV4096: fCTCLK = fHCLK/4096 + \arg TSI_CTCDIV_DIV8192: fCTCLK = fHCLK/8192 + \arg TSI_CTCDIV_DIV16384: fCTCLK = fHCLK/16384 + \arg TSI_CTCDIV_DIV32768: fCTCLK = fHCLK/32768 + \param[in] charge_duration: charge state duration time + only one parameter can be selected which is shown as below: + \arg TSI_CHARGE_1CTCLK(x=1..16): the duration time of charge state is x CTCLK + \param[in] transfer_duration: charge transfer state duration time + only one parameter can be selected which is shown as below: + \arg TSI_TRANSFER_xCTCLK(x=1..16): the duration time of transfer state is x CTCLK + \param[in] max_number: max cycle number + only one parameter can be selected which is shown as below: + \arg TSI_MAXNUM255: the max cycle number of a sequence is 255 + \arg TSI_MAXNUM511: the max cycle number of a sequence is 511 + \arg TSI_MAXNUM1023: the max cycle number of a sequence is 1023 + \arg TSI_MAXNUM2047: the max cycle number of a sequence is 2047 + \arg TSI_MAXNUM4095: the max cycle number of a sequence is 4095 + \arg TSI_MAXNUM8191: the max cycle number of a sequence is 8191 + \arg TSI_MAXNUM16383: the max cycle number of a sequence is 16383 + \param[out] none + \retval none +*/ +void tsi_init(uint32_t prescaler,uint32_t charge_duration,uint32_t transfer_duration,uint32_t max_number) +{ + uint32_t ctl0,ctl1; + if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){ + if(TSI_CTCDIV_DIV256 > prescaler){ + /* config TSI_CTL0 */ + ctl0 = TSI_CTL0; + /*configure TSI clock division factor,charge state duration time,charge transfer state duration time */ + ctl0 &= ~(TSI_CTL0_CTCDIV|TSI_CTL0_CTDT|TSI_CTL0_CDT|TSI_CTL0_MCN); + ctl0 |= ((prescaler<<12U)|charge_duration|transfer_duration|max_number); + TSI_CTL0 = ctl0; + + /* config TSI_CTL1 */ + ctl1 = TSI_CTL1; + ctl1 &= ~TSI_CTL1_CTCDIV; + TSI_CTL1 = ctl1; + }else{ + /* config TSI_CTL0 */ + ctl0 = TSI_CTL0; + prescaler &= ~0x08U; + /*configure TSI clock division factor,charge state duration time,charge transfer state duration time */ + ctl0 &= ~(TSI_CTL0_CTCDIV|TSI_CTL0_CTDT|TSI_CTL0_CDT|TSI_CTL0_MCN); + ctl0 |= ((prescaler<<12U)|charge_duration|transfer_duration|max_number); + TSI_CTL0 = ctl0; + + /* config TSI_CTL1 */ + ctl1 = TSI_CTL1; + ctl1 |= TSI_CTL1_CTCDIV; + TSI_CTL1 = ctl1; + } + } +} + +/*! + \brief enable TSI module + \param[in] none + \param[out] none + \retval none +*/ +void tsi_enable(void) +{ + TSI_CTL0 |= TSI_CTL0_TSIEN; +} + +/*! + \brief disable TSI module + \param[in] none + \param[out] none + \retval none +*/ +void tsi_disable(void) +{ + TSI_CTL0 &= ~TSI_CTL0_TSIEN; +} + +/*! + \brief enable sample pin + \param[in] sample: sample pin + one or more parameters can be selected which are shown as below: + \arg TSI_SAMPCFG_GxPy( x=0..5,y=0..3):pin y of group x is sample pin + \param[out] none + \retval none +*/ +void tsi_sample_pin_enable(uint32_t sample) +{ + if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){ + TSI_SAMPCFG |= sample; + } +} + +/*! + \brief disable sample pin + \param[in] sample: sample pin + one or more parameters can be selected which are shown as below: + \arg TSI_SAMPCFG_GxPy( x=0..5,y=0..3): pin y of group x is sample pin + \param[out] none + \retval none +*/ +void tsi_sample_pin_disable(uint32_t sample) +{ + if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){ + TSI_SAMPCFG &= ~sample; + } +} + +/*! + \brief enable channel pin + \param[in] channel: channel pin + one or more parameters can be selected which are shown as below: + \arg TSI_CHCFG_GxPy( x=0..5,y=0..3): pin y of group x + \param[out] none + \retval none +*/ +void tsi_channel_pin_enable(uint32_t channel) +{ + TSI_CHCFG |= channel; +} + +/*! + \brief disable channel pin + \param[in] channel: channel pin + one or more parameters can be selected which are shown as below: + \arg TSI_CHCFG_GxPy( x=0..5,y=0..3): pin y of group x + \param[out] none + \retval none +*/ +void tsi_channel_pin_disable(uint32_t channel) +{ + TSI_CHCFG &= ~channel; +} + +/*! + \brief configure TSI triggering by software + \param[in] none + \param[out] none + \retval none +*/ +void tsi_sofeware_mode_config(void) +{ + if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){ + TSI_CTL0 &= ~TSI_CTL0_TRGMOD; + } +} + +/*! + \brief start a charge-transfer sequence when TSI is in software trigger mode + \param[in] none + \param[out] none + \retval none +*/ +void tsi_software_start(void) +{ + TSI_CTL0 |= TSI_CTL0_TSIS; +} + +/*! + \brief stop a charge-transfer sequence when TSI is in software trigger mode + \param[in] none + \param[out] none + \retval none +*/ +void tsi_software_stop(void) +{ + TSI_CTL0 &= ~TSI_CTL0_TSIS; +} + +/*! + \brief configure TSI triggering by hardware + \param[in] trigger_edge: the edge type in hardware trigger mode + only one parameter can be selected which is shown as below: + \arg TSI_FALLING_TRIGGER: falling edge trigger TSI charge transfer sequence + \arg TSI_RISING_TRIGGER: rising edge trigger TSI charge transfer sequence + \param[out] none + \retval none +*/ +void tsi_hardware_mode_config(uint8_t trigger_edge) +{ + if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){ + /*enable hardware mode*/ + TSI_CTL0 |= TSI_CTL0_TRGMOD; + /*configure the edge type in hardware trigger mode*/ + if(TSI_FALLING_TRIGGER == trigger_edge){ + TSI_CTL0 &= ~TSI_CTL0_EGSEL; + }else{ + TSI_CTL0 |= TSI_CTL0_EGSEL; + } + } +} + +/*! + \brief configure TSI pin mode when charge-transfer sequence is IDLE + \param[in] pin_mode: pin mode when charge-transfer sequence is IDLE + only one parameter can be selected which is shown as below: + \arg TSI_OUTPUT_LOW: TSI pin will output low when IDLE + \arg TSI_INPUT_FLOATING: TSI pin will keep input_floating when IDLE + \param[out] none + \retval none +*/ +void tsi_pin_mode_config(uint8_t pin_mode) +{ + if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){ + if(TSI_OUTPUT_LOW == pin_mode){ + TSI_CTL0 &= ~TSI_CTL0_PINMOD; + }else{ + TSI_CTL0 |= TSI_CTL0_PINMOD; + } + } +} + +/*! + \brief configure extend charge state + \param[in] extend: enable or disable extend charge state + only one parameter can be selected which is shown as below: + \arg ENABLE: enable extend charge state + \arg DISABLE: disable extend charge state + \param[in] prescaler: ECCLK clock division factor + only one parameter can be selected which is shown as below: + \arg TSI_EXTEND_DIV1: fECCLK = fHCLK + \arg TSI_EXTEND_DIV2: fECCLK = fHCLK/2 + \arg TSI_EXTEND_DIV3: fECCLK = fHCLK/3 + \arg TSI_EXTEND_DIV4: fECCLK = fHCLK/4 + \arg TSI_EXTEND_DIV5: fECCLK = fHCLK/5 + \arg TSI_EXTEND_DIV6: fECCLK = fHCLK/6 + \arg TSI_EXTEND_DIV7: fECCLK = fHCLK/7 + \arg TSI_EXTEND_DIV8: fECCLK = fHCLK/8 + \param[in] max_duration: value range 1...128,extend charge state maximum duration time is 1*tECCLK~128*tECCLK + \param[out] none + \retval none +*/ +void tsi_extend_charge_config(ControlStatus extend,uint8_t prescaler,uint32_t max_duration) +{ + uint32_t ctl0,ctl1; + if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){ + if(DISABLE == extend){ + /*disable extend charge state*/ + TSI_CTL0 &= ~TSI_CTL0_ECEN; + }else{ + if(TSI_EXTEND_DIV3 > prescaler){ + /*configure extend charge state maximum duration time*/ + ctl0 = TSI_CTL0; + ctl0 &= ~TSI_CTL0_ECDT; + ctl0 |= TSI_EXTENDMAX((max_duration-1U)); + TSI_CTL0 = ctl0; + /*configure ECCLK clock division factor*/ + ctl0 = TSI_CTL0; + ctl0 &= ~TSI_CTL0_ECDIV; + ctl0 |= (uint32_t)prescaler<<15U; + TSI_CTL0 = ctl0; + /*enable extend charge state*/ + TSI_CTL0 |= TSI_CTL0_ECEN; + }else{ + /*configure extend charge state maximum duration time*/ + ctl0 = TSI_CTL0; + ctl0 &= ~TSI_CTL0_ECDT; + ctl0 |= TSI_EXTENDMAX((max_duration-1U)); + TSI_CTL0 = ctl0; + /*configure ECCLK clock division factor*/ + ctl0 = TSI_CTL0; + ctl0 &= ~TSI_CTL0_ECDIV; + ctl0 |= (prescaler & 0x01U)<<15U; + TSI_CTL0 = ctl0; + ctl1 = TSI_CTL1; + ctl1 &= ~TSI_CTL1_ECDIV; + ctl1 |= (prescaler & 0x06U)<<28U; + TSI_CTL1 = ctl1; + /*enable extend charge state*/ + TSI_CTL0 |= TSI_CTL0_ECEN; + } + } + } +} + +/*! + \brief configure charge plus and transfer plus + \param[in] prescaler: CTCLK clock division factor + only one parameter can be selected which is shown as below: + \arg TSI_CTCDIV_DIV1: fCTCLK = fHCLK + \arg TSI_CTCDIV_DIV2: fCTCLK = fHCLK/2 + \arg TSI_CTCDIV_DIV4: fCTCLK = fHCLK/4 + \arg TSI_CTCDIV_DIV8: fCTCLK = fHCLK/8 + \arg TSI_CTCDIV_DIV16: fCTCLK = fHCLK/16 + \arg TSI_CTCDIV_DIV32: fCTCLK = fHCLK/32 + \arg TSI_CTCDIV_DIV64: fCTCLK = fHCLK/64 + \arg TSI_CTCDIV_DIV128: fCTCLK = fHCLK/128 + \arg TSI_CTCDIV_DIV256: fCTCLK = fHCLK/256 + \arg TSI_CTCDIV_DIV512: fCTCLK = fHCLK/512 + \arg TSI_CTCDIV_DIV1024: fCTCLK = fHCLK/1024 + \arg TSI_CTCDIV_DIV2048: fCTCLK = fHCLK/2048 + \arg TSI_CTCDIV_DIV4096: fCTCLK = fHCLK/4096 + \arg TSI_CTCDIV_DIV8192: fCTCLK = fHCLK/8192 + \arg TSI_CTCDIV_DIV16384: fCTCLK = fHCLK/16384 + \arg TSI_CTCDIV_DIV32768: fCTCLK = fHCLK/32768 + \param[in] charge_duration: charge state duration time + only one parameter can be selected which is shown as below: + \arg TSI_CHARGE_xCTCLK(x=1..16): the duration time of charge state is x CTCLK + \param[in] transfer_duration: charge transfer state duration time + only one parameter can be selected which is shown as below: + \arg TSI_TRANSFER_xCTCLK(x=1..16): the duration time of transfer state is x CTCLK + \param[out] none + \retval none +*/ +void tsi_plus_config(uint32_t prescaler,uint32_t charge_duration,uint32_t transfer_duration) +{ + uint32_t ctl0,ctl1; + if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){ + if(TSI_CTCDIV_DIV256 > prescaler){ + /* config TSI_CTL0 */ + ctl0 = TSI_CTL0; + /*configure TSI clock division factor,charge state duration time,charge transfer state duration time */ + ctl0 &= ~(TSI_CTL0_CTCDIV|TSI_CTL0_CTDT|TSI_CTL0_CDT); + ctl0 |= ((prescaler<<12U)|charge_duration|transfer_duration); + TSI_CTL0 = ctl0; + + /* config TSI_CTL1 */ + ctl1 = TSI_CTL1; + ctl1 &= ~TSI_CTL1_CTCDIV; + TSI_CTL1 = ctl1; + }else{ + /* config TSI_CTL */ + ctl0 = TSI_CTL0; + prescaler &= ~0x08U; + /*configure TSI clock division factor,charge state duration time,charge transfer state duration time */ + ctl0 &= ~(TSI_CTL0_CTCDIV|TSI_CTL0_CTDT|TSI_CTL0_CDT); + ctl0 |= ((prescaler<<12U)|charge_duration|transfer_duration); + TSI_CTL0 = ctl0; + + /* config TSI_CTL2 */ + ctl1 = TSI_CTL1; + ctl1 |= TSI_CTL1_CTCDIV; + TSI_CTL1 = ctl1; + } + } +} + +/*! + \brief configure the max cycle number of a charge-transfer sequence + \param[in] max_number: max cycle number + only one parameter can be selected which is shown as below: + \arg TSI_MAXNUM255: the max cycle number of a sequence is 255 + \arg TSI_MAXNUM511: the max cycle number of a sequence is 511 + \arg TSI_MAXNUM1023: the max cycle number of a sequence is 1023 + \arg TSI_MAXNUM2047: the max cycle number of a sequence is 2047 + \arg TSI_MAXNUM4095: the max cycle number of a sequence is 4095 + \arg TSI_MAXNUM8191: the max cycle number of a sequence is 8191 + \arg TSI_MAXNUM16383: the max cycle number of a sequence is 16383 + \param[out] none + \retval none +*/ +void tsi_max_number_config(uint32_t max_number) +{ + if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){ + uint32_t maxnum; + maxnum = TSI_CTL0; + /*configure the max cycle number of a charge-transfer sequence*/ + maxnum &= ~TSI_CTL0_MCN; + maxnum |= max_number; + TSI_CTL0 = maxnum; + } +} + +/*! + \brief switch on hysteresis pin + \param[in] group_pin: select pin which will be switched on hysteresis + one or more parameters can be selected which are shown as below: + \arg TSI_PHM_GxPy(x=0..5,y=0..3): pin y of group x switch on hysteresis + \param[out] none + \retval none +*/ +void tsi_hysteresis_on(uint32_t group_pin) +{ + TSI_PHM |= group_pin; +} + +/*! + \brief switch off hysteresis pin + \param[in] group_pin: select pin which will be switched off hysteresis + one or more parameters can be selected which are shown as below: + \arg TSI_PHM_GxPy(x=0..5,y=0..3): pin y of group x switch off hysteresis + \param[out] none + \retval none +*/ +void tsi_hysteresis_off(uint32_t group_pin) +{ + TSI_PHM &= ~group_pin; +} + +/*! + \brief switch on analog pin + \param[in] group_pin: select pin which will be switched on analog + one or more parameters can be selected which are shown as below: + \arg TSI_ASW_GxPy(x=0..5,y=0..3):pin y of group x switch on analog + \param[out] none + \retval none +*/ +void tsi_analog_on(uint32_t group_pin) +{ + TSI_ASW |= group_pin; +} + +/*! + \brief switch off analog pin + \param[in] group_pin: select pin which will be switched off analog + one or more parameters can be selected which are shown as below: + \arg TSI_ASW_GxPy(x=0..5,y=0..3):pin y of group x switch off analog + \param[out] none + \retval none +*/ +void tsi_analog_off(uint32_t group_pin) +{ + TSI_ASW &= ~group_pin; +} + +/*! + \brief enable TSI interrupt + \param[in] source: select interrupt which will be enabled + only one parameter can be selected which is shown as below: + \arg TSI_INT_CCTCF: charge-transfer complete flag interrupt enable + \arg TSI_INT_MNERR: max cycle number error interrupt enable + \param[out] none + \retval none +*/ +void tsi_interrupt_enable(uint32_t source) +{ + TSI_INTEN |= source; +} + +/*! + \brief disable TSI interrupt + \param[in] source: select interrupt which will be disabled + only one parameter can be selected which is shown as below: + \arg TSI_INT_CCTCF: charge-transfer complete flag interrupt disable + \arg TSI_INT_MNERR: max cycle number error interrupt disable + \param[out] none + \retval none +*/ +void tsi_interrupt_disable(uint32_t source) +{ + TSI_INTEN &= ~source; +} + +/*! + \brief clear TSI interrupt flag + \param[in] flag: select flag which will be cleared + only one parameter can be selected which is shown as below: + \arg TSI_INT_FLAG_CTCF_CLR: clear charge-transfer complete flag + \arg TSI_INT_FLAG_MNERR_CLR: clear max cycle number error + \param[out] none + \retval none +*/ +void tsi_interrupt_flag_clear(uint32_t flag) +{ + TSI_INTC |= flag; +} + +/*! + \brief get TSI interrupt flag + \param[in] flag: + only one parameter can be selected which is shown as below: + \arg TSI_INT_FLAG_CTCF: charge-transfer complete flag + \arg TSI_INT_FLAG_MNERR: max Cycle Number Error + \param[out] none + \retval FlagStatus:SET or RESET +*/ +FlagStatus tsi_interrupt_flag_get(uint32_t flag) +{ + uint32_t interrupt_enable = 0U,interrupt_flag = 0U; + interrupt_flag = (TSI_INTF & flag); + interrupt_enable = (TSI_INTEN & flag); + if(interrupt_flag && interrupt_enable){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear flag + \param[in] flag: select flag which will be cleared + only one parameter can be selected which is shown as below: + \arg TSI_FLAG_CTCF_CLR: clear charge-transfer complete flag + \arg TSI_FLAG_MNERR_CLR: clear max cycle number error + \param[out] none + \retval none +*/ +void tsi_flag_clear(uint32_t flag) +{ + TSI_INTC |= flag; +} + +/*! + \brief get flag + \param[in] flag: + only one parameter can be selected which is shown as below: + \arg TSI_FLAG_CTCF: charge-transfer complete flag + \arg TSI_FLAG_MNERR: max Cycle Number Error + \param[out] none + \retval FlagStatus:SET or RESET +*/ +FlagStatus tsi_flag_get(uint32_t flag) +{ + FlagStatus flag_status; + if(TSI_INTF & flag){ + flag_status = SET; + }else{ + flag_status = RESET; + } + return flag_status; +} + +/*! + \brief enbale group + \param[in] group: select group to be enabled + one or more parameters can be selected which are shown as below: + \arg TSI_GCTL_GEx(x=0..5): the x group will be enabled + \param[out] none + \retval none +*/ +void tsi_group_enable(uint32_t group) +{ + TSI_GCTL |= group; +} + +/*! + \brief disbale group + \param[in] group: select group to be disabled + one or more parameters can be selected which are shown as below: + \arg TSI_GCTL_GEx(x=0..5):the x group will be disabled + \param[out] none + \retval none +*/ +void tsi_group_disable(uint32_t group) +{ + TSI_GCTL &= ~group; +} + +/*! + \brief get group complete status + \param[in] group: select group + one or more parameters can be selected which are shown as below: + \arg TSI_GCTL_GCx(x=0..5): get the complete status of group x + \param[out] none + \retval FlagStatus: group complete status,SET or RESET +*/ +FlagStatus tsi_group_status_get(uint32_t group) +{ + FlagStatus flag_status; + if(TSI_GCTL & group){ + flag_status = SET; + }else{ + flag_status = RESET; + } + return flag_status; +} + +/*! + \brief get the cycle number for group0 as soon as a charge-transfer sequence completes + \param[in] none + \param[out] none + \retval group0 cycle number +*/ +uint16_t tsi_group0_cycle_get(void) +{ + return (uint16_t)TSI_G0CYCN; +} + +/*! + \brief get the cycle number for group1 as soon as a charge-transfer sequence completes + \param[in] none + \param[out] none + \retval group1 cycle number +*/ +uint16_t tsi_group1_cycle_get(void) +{ + return (uint16_t)TSI_G1CYCN; +} + +/*! + \brief get the cycle number for group2 as soon as a charge-transfer sequence completes + \param[in] none + \param[out] none + \retval group2 cycle number +*/ +uint16_t tsi_group2_cycle_get(void) +{ + return (uint16_t)TSI_G2CYCN; +} + +/*! + \brief get the cycle number for group3 as soon as a charge-transfer sequence completes + \param[in] none + \param[out] none + \retval group3 cycle number +*/ +uint16_t tsi_group3_cycle_get(void) +{ + return (uint16_t)TSI_G3CYCN; +} + +/*! + \brief get the cycle number for group4 as soon as a charge-transfer sequence completes + \param[in] none + \param[out] none + \retval group4 cycle number +*/ +uint16_t tsi_group4_cycle_get(void) +{ + return (uint16_t)TSI_G4CYCN; +} + +/*! + \brief get the cycle number for group5 as soon as a charge-transfer sequence completes + \param[in] none + \param[out] none + \retval group5 cycle number +*/ +uint16_t tsi_group5_cycle_get(void) +{ + return (uint16_t)TSI_G5CYCN; +} diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_usart.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_usart.c new file mode 100644 index 0000000000..f4dd5a4ca3 --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_usart.c @@ -0,0 +1,1308 @@ +/*! + \file gd32f3x0_usart.c + \brief USART driver + + \version 2017-06-06 V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f3x0_usart.h" + +/* USART register bit offset */ +#define CTL1_ADDR_OFFSET ((uint32_t)24U) /* bit offset of ADDR in USART_CTL1 */ +#define GP_GUAT_OFFSET ((uint32_t)8U) /* bit offset of GUAT in USART_GP */ +#define CTL2_SCRTNUM_OFFSET ((uint32_t)17U) /* bit offset of SCRTNUM in USART_CTL2 */ +#define RT_BL_OFFSET ((uint32_t)24U) /* bit offset of BL in USART_RT */ +#define CTL0_DEA_OFFSET ((uint32_t)21U) /* bit offset of DEA in USART_CTL0 */ +#define CTL0_DED_OFFSET ((uint32_t)16U) /* bit offset of DED in USART_CTL0 */ + +/*! + \brief reset USART + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_deinit(uint32_t usart_periph) +{ + switch(usart_periph){ + case USART0: + /* reset USART0 */ + rcu_periph_reset_enable(RCU_USART0RST); + rcu_periph_reset_disable(RCU_USART0RST); + break; + case USART1: + /* reset USART1 */ + rcu_periph_reset_enable(RCU_USART1RST); + rcu_periph_reset_disable(RCU_USART1RST); + break; + default: + break; + } +} + +/*! + \brief configure USART baud rate value + \param[in] usart_periph: USARTx(x=0,1) + \param[in] baudval: baud rate value + \param[out] none + \retval none +*/ +void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval) +{ + uint32_t uclk = 0U, intdiv = 0U, fradiv = 0U, udiv = 0U; + switch(usart_periph){ + /* get clock frequency */ + case USART0: + /* get USART0 clock */ + uclk = rcu_clock_freq_get(CK_USART); + break; + case USART1: + /* get USART1 clock */ + uclk = rcu_clock_freq_get(CK_APB1); + break; + default: + break; + } + if(USART_CTL0(usart_periph) & USART_CTL0_OVSMOD){ + /* oversampling by 8, configure the value of USART_BAUD */ + udiv = ((2U*uclk)+baudval/2U)/baudval; + intdiv = udiv & 0x0000fff0U; + fradiv = (udiv>>1U) & 0x00000007U; + USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); + }else{ + /* oversampling by 16, configure the value of USART_BAUD */ + udiv = (uclk+baudval/2U)/baudval; + intdiv = udiv & 0x0000fff0U; + fradiv = udiv & 0x0000000fU; + USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); + } +} + +/*! + \brief configure USART parity + \param[in] usart_periph: USARTx(x=0,1) + \param[in] paritycfg: USART parity configure + only one parameter can be selected which is shown as below: + \arg USART_PM_NONE: no parity + \arg USART_PM_ODD: odd parity + \arg USART_PM_EVEN: even parity + \param[out] none + \retval none +*/ +void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* clear USART_CTL0 PM,PCEN bits */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_PM | USART_CTL0_PCEN); + /* configure USART parity mode */ + USART_CTL0(usart_periph) |= paritycfg; +} + +/*! + \brief configure USART word length + \param[in] usart_periph: USARTx(x=0,1) + \param[in] wlen: USART word length configure + only one parameter can be selected which is shown as below: + \arg USART_WL_8BIT: 8 bits + \arg USART_WL_9BIT: 9 bits + \param[out] none + \retval none +*/ +void usart_word_length_set(uint32_t usart_periph, uint32_t wlen) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* clear USART_CTL0 WL bit */ + USART_CTL0(usart_periph) &= ~USART_CTL0_WL; + /* configure USART word length */ + USART_CTL0(usart_periph) |= wlen; +} + +/*! + \brief configure USART stop bit length + \param[in] usart_periph: USARTx(x=0,1) + \param[in] stblen: USART stop bit configure + only one parameter can be selected which is shown as below: + \arg USART_STB_1BIT: 1 bit + \arg USART_STB_0_5BIT: 0.5bit + \arg USART_STB_2BIT: 2 bits + \arg USART_STB_1_5BIT: 1.5bit + \param[out] none + \retval none +*/ +void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* clear USART_CTL1 STB bits */ + USART_CTL1(usart_periph) &= ~USART_CTL1_STB; + USART_CTL1(usart_periph) |= stblen; +} + +/*! + \brief enable USART + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_enable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) |= USART_CTL0_UEN; +} + +/*! + \brief disable USART + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_disable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); +} + +/*! + \brief configure USART transmitter + \param[in] usart_periph: USARTx(x=0,1) + \param[in] txconfig: enable or disable USART transmitter + only one parameter can be selected which is shown as below: + \arg USART_TRANSMIT_ENABLE: enable USART transmission + \arg USART_TRANSMIT_DISABLE: enable USART transmission + \param[out] none + \retval none +*/ +void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig) +{ + USART_CTL0(usart_periph) &= ~USART_CTL0_TEN; + /* configure transfer mode */ + USART_CTL0(usart_periph) |= txconfig; +} + +/*! + \brief configure USART receiver + \param[in] usart_periph: USARTx(x=0,1) + \param[in] rxconfig: enable or disable USART receiver + only one parameter can be selected which is shown as below: + \arg USART_RECEIVE_ENABLE: enable USART reception + \arg USART_RECEIVE_DISABLE: disable USART reception + \param[out] none + \retval none +*/ +void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig) +{ + USART_CTL0(usart_periph) &= ~USART_CTL0_REN; + /* configure receiver mode */ + USART_CTL0(usart_periph) |= rxconfig; +} + +/*! + \brief data is transmitted/received with the LSB/MSB first + \param[in] usart_periph: USARTx(x=0,1) + \param[in] msbf: LSB/MSB + only one parameter can be selected which is shown as below: + \arg USART_MSBF_LSB: LSB first + \arg USART_MSBF_MSB: MSB first + \param[out] none + \retval none +*/ +void usart_data_first_config(uint32_t usart_periph, uint32_t msbf) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* configure LSB or MSB first */ + USART_CTL1(usart_periph) &= ~(USART_CTL1_MSBF); + USART_CTL1(usart_periph) |= (USART_CTL1_MSBF & msbf); +} + +/*! + \brief USART inverted configure + \param[in] usart_periph: USARTx(x=0,1) + \param[in] invertpara: refer to usart_invert_enum + only one parameter can be selected which is shown as below: + \arg USART_DINV_ENABLE: data bit level inversion + \arg USART_DINV_DISABLE: data bit level not inversion + \arg USART_TXPIN_ENABLE: TX pin level inversion + \arg USART_TXPIN_DISABLE: TX pin level not inversion + \arg USART_RXPIN_ENABLE: RX pin level inversion + \arg USART_RXPIN_DISABLE: RX pin level not inversion + \arg USART_SWAP_ENABLE: swap TX/RX pins + \arg USART_SWAP_DISABLE: not swap TX/RX pins + \param[out] none + \retval none +*/ +void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* inverted or not the specified signal */ + switch(invertpara){ + case USART_DINV_ENABLE: + USART_CTL1(usart_periph) |= USART_CTL1_DINV; + break; + case USART_DINV_DISABLE: + USART_CTL1(usart_periph) &= ~(USART_CTL1_DINV); + break; + case USART_TXPIN_ENABLE: + USART_CTL1(usart_periph) |= USART_CTL1_TINV; + break; + case USART_TXPIN_DISABLE: + USART_CTL1(usart_periph) &= ~(USART_CTL1_TINV); + break; + case USART_RXPIN_ENABLE: + USART_CTL1(usart_periph) |= USART_CTL1_RINV; + break; + case USART_RXPIN_DISABLE: + USART_CTL1(usart_periph) &= ~(USART_CTL1_RINV); + break; + case USART_SWAP_ENABLE: + USART_CTL1(usart_periph) |= USART_CTL1_STRP; + break; + case USART_SWAP_DISABLE: + USART_CTL1(usart_periph) &= ~(USART_CTL1_STRP); + break; + default: + break; + } +} + +/*! + \brief enable the USART overrun function + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_overrun_enable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* enable overrun function */ + USART_CTL2(usart_periph) &= ~(USART_CTL2_OVRD); +} + +/*! + \brief disable the USART overrun function + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_overrun_disable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* disable overrun function */ + USART_CTL2(usart_periph) |= USART_CTL2_OVRD; +} + +/*! + \brief configure the USART oversample mode + \param[in] usart_periph: USARTx(x=0,1) + \param[in] oversamp: oversample value + only one parameter can be selected which is shown as below: + \arg USART_OVSMOD_8: oversampling by 8 + \arg USART_OVSMOD_16: oversampling by 16 + \param[out] none + \retval none +*/ +void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* clear OVSMOD bit */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_OVSMOD); + USART_CTL0(usart_periph) |= oversamp; +} + +/*! + \brief configure the sample bit method + \param[in] usart_periph: USARTx(x=0,1) + \param[in] osb: sample bit + only one parameter can be selected which is shown as below: + \arg USART_OSB_1BIT: 1 bit + \arg USART_OSB_3BIT: 3 bits + \param[out] none + \retval none +*/ +void usart_sample_bit_config(uint32_t usart_periph, uint32_t osb) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) &= ~(USART_CTL2_OSB); + USART_CTL2(usart_periph) |= osb; +} + +/*! + \brief enable receiver timeout + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_receiver_timeout_enable(uint32_t usart_periph) +{ + USART_CTL1(usart_periph) |= USART_CTL1_RTEN; +} + +/*! + \brief disable receiver timeout + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_receiver_timeout_disable(uint32_t usart_periph) +{ + USART_CTL1(usart_periph) &= ~(USART_CTL1_RTEN); +} + +/*! + \brief configure receiver timeout threshold + \param[in] usart_periph: USARTx(x=0) + \param[in] rtimeout: 0x00000000-0x00FFFFFF, receiver timeout value in terms of number of baud clocks + \param[out] none + \retval none +*/ +void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout) +{ + USART_RT(usart_periph) &= ~(USART_RT_RT); + USART_RT(usart_periph) |= rtimeout; +} + +/*! + \brief USART transmit data function + \param[in] usart_periph: USARTx(x=0,1) + \param[in] data: data of transmission + \param[out] none + \retval none +*/ +void usart_data_transmit(uint32_t usart_periph, uint32_t data) +{ + USART_TDATA(usart_periph) = (USART_TDATA_TDATA & data); +} + +/*! + \brief USART receive data function + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval data of received +*/ +uint16_t usart_data_receive(uint32_t usart_periph) +{ + return (uint16_t)(GET_BITS(USART_RDATA(usart_periph), 0U, 8U)); +} + +/*! + \brief enable auto baud rate detection + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_autobaud_detection_enable(uint32_t usart_periph) +{ + USART_CTL1(usart_periph) |= USART_CTL1_ABDEN; +} + +/*! + \brief disable auto baud rate detection + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_autobaud_detection_disable(uint32_t usart_periph) +{ + USART_CTL1(usart_periph) &= ~(USART_CTL1_ABDEN); +} + +/*! + \brief configure auto baud rate detection mode + \param[in] usart_periph: USARTx(x=0) + \param[in] abdmod: auto baud rate detection mode + only one parameter can be selected which is shown as below: + \arg USART_ABDM_FTOR: falling edge to rising edge measurement + \arg USART_ABDM_FTOF: falling edge to falling edge measurement + \param[out] none + \retval none +*/ +void usart_autobaud_detection_mode_config(uint32_t usart_periph, uint32_t abdmod) +{ + /* reset ABDM bits */ + USART_CTL1(usart_periph) &= ~(USART_CTL1_ABDM); + USART_CTL1(usart_periph) |= abdmod; +} + +/*! + \brief address of the USART terminal + \param[in] usart_periph: USARTx(x=0,1) + \param[in] addr: 0x00-0xFF, address of USART terminal + \param[out] none + \retval none +*/ +void usart_address_config(uint32_t usart_periph, uint8_t addr) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDR); + USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & (((uint32_t)addr) << CTL1_ADDR_OFFSET)); +} + +/*! + \brief configure the address of the USART in wake up by address match mode + \param[in] usart_periph: USARTx(x=0,1) + \param[in] addmod: address detection mode + only one parameter can be selected which is shown as below: + \arg USART_ADDM_4BIT: 4 bits + \arg USART_ADDM_FULLBIT: full bits + \param[out] none + \retval none +*/ +void usart_address_detection_mode_config(uint32_t usart_periph, uint32_t addmod) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDM); + USART_CTL1(usart_periph) |= USART_CTL1_ADDM & (addmod); +} + +/*! + \brief enable mute mode + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_mute_mode_enable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) |= USART_CTL0_MEN; +} + +/*! + \brief disable mute mode + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_mute_mode_disable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_MEN); +} + +/*! + \brief configure wakeup method in mute mode + \param[in] usart_periph: USARTx(x=0,1) + \param[in] wmethod: two methods be used to enter or exit the mute mode + only one parameter can be selected which is shown as below: + \arg USART_WM_IDLE: idle line + \arg USART_WM_ADDR: address mark + \param[out] none + \retval none +*/ +void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL0(usart_periph) &= ~(USART_CTL0_WM); + USART_CTL0(usart_periph) |= wmethod; +} + +/*! + \brief enable LIN mode + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_lin_mode_enable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL1(usart_periph) |= USART_CTL1_LMEN; +} + +/*! + \brief disable LIN mode + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_lin_mode_disable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN); +} + +/*! + \brief configure LIN break frame length + \param[in] usart_periph: USARTx(x=0) + \param[in] lblen: LIN break detection length + only one parameter can be selected which is shown as below: + \arg USART_LBLEN_10B: 10 bits break detection + \arg USART_LBLEN_11B: 11 bits break detection + \param[out] none + \retval none +*/ +void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + USART_CTL1(usart_periph) &= ~(USART_CTL1_LBLEN); + USART_CTL1(usart_periph) |= USART_CTL1_LBLEN & (lblen); +} + +/*! + \brief enable half-duplex mode + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_halfduplex_enable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) |= USART_CTL2_HDEN; +} + +/*! + \brief disable half-duplex mode + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_halfduplex_disable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) &= ~(USART_CTL2_HDEN); +} + +/*! + \brief enable USART clock + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_clock_enable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL1(usart_periph) |= USART_CTL1_CKEN; +} + +/*! + \brief disable USART clock + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_clock_disable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL1(usart_periph) &= ~(USART_CTL1_CKEN); +} + +/*! + \brief configure USART synchronous mode parameters + \param[in] usart_periph: USARTx(x=0,1) + \param[in] clen: last bit clock pulse + only one parameter can be selected which is shown as below: + \arg USART_CLEN_NONE: clock pulse of the last data bit (MSB) is not output to the CK pin + \arg USART_CLEN_EN: clock pulse of the last data bit (MSB) is output to the CK pin + \param[in] cph: clock phase + only one parameter can be selected which is shown as below: + \arg USART_CPH_1CK: first clock transition is the first data capture edge + \arg USART_CPH_2CK: second clock transition is the first data capture edge + \param[in] cpl: clock polarity + only one parameter can be selected which is shown as below: + \arg USART_CPL_LOW: steady low value on CK pin + \arg USART_CPL_HIGH: steady high value on CK pin + \param[out] none + \retval none +*/ +void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* reset USART_CTL1 CLEN,CPH,CPL bits */ + USART_CTL1(usart_periph) &= ~(USART_CTL1_CLEN | USART_CTL1_CPH | USART_CTL1_CPL); + + USART_CTL1(usart_periph) |= (USART_CTL1_CLEN & clen); + USART_CTL1(usart_periph) |= (USART_CTL1_CPH & cph); + USART_CTL1(usart_periph) |= (USART_CTL1_CPL & cpl); +} + +/*! + \brief configure guard time value in smartcard mode + \param[in] usart_periph: USARTx(x=0) + \param[in] guat: 0x00-0xFF + \param[out] none + \retval none +*/ +void usart_guard_time_config(uint32_t usart_periph, uint32_t guat) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_GP(usart_periph) &= ~(USART_GP_GUAT); + USART_GP(usart_periph) |= (USART_GP_GUAT & ((guat) << GP_GUAT_OFFSET)); +} + +/*! + \brief enable smartcard mode + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_enable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) |= USART_CTL2_SCEN; +} + +/*! + \brief disable smartcard mode + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_disable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) &= ~(USART_CTL2_SCEN); +} + +/*! + \brief enable NACK in smartcard mode + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_nack_enable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) |= USART_CTL2_NKEN; +} + +/*! + \brief disable NACK in smartcard mode + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_nack_disable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) &= ~(USART_CTL2_NKEN); +} + +/*! + \brief enable early NACK in smartcard mode + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_early_nack_enable(uint32_t usart_periph) +{ + USART_RFCS(usart_periph) |= USART_RFCS_ELNACK; +} + +/*! + \brief disable early NACK in smartcard mode + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_early_nack_disable(uint32_t usart_periph) +{ + USART_RFCS(usart_periph) &= ~USART_RFCS_ELNACK; +} + +/*! + \brief configure smartcard auto-retry number + \param[in] usart_periph: USARTx(x=0) + \param[in] scrtnum: 0x00000000-0x00000007, smartcard auto-retry number + \param[out] none + \retval none +*/ +void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + USART_CTL2(usart_periph) &= ~(USART_CTL2_SCRTNUM); + USART_CTL2(usart_periph) |= (USART_CTL2_SCRTNUM & (scrtnum << CTL2_SCRTNUM_OFFSET)); +} + +/*! + \brief configure block length + \param[in] usart_periph: USARTx(x=0) + \param[in] bl: 0x00000000-0x000000FF + \param[out] none + \retval none +*/ +void usart_block_length_config(uint32_t usart_periph, uint32_t bl) +{ + USART_RT(usart_periph) &= ~(USART_RT_BL); + USART_RT(usart_periph) |= (USART_RT_BL & ((bl) << RT_BL_OFFSET)); +} + +/*! + \brief enable IrDA mode + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_irda_mode_enable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) |= USART_CTL2_IREN; +} + +/*! + \brief disable IrDA mode + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_irda_mode_disable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) &= ~(USART_CTL2_IREN); +} + +/*! + \brief configure the peripheral clock prescaler in USART IrDA low-power or SmartCard mode + \param[in] usart_periph: USARTx(x=0) + \param[in] psc: 0x00000000-0x000000FF + \param[out] none + \retval none +*/ +void usart_prescaler_config(uint32_t usart_periph, uint32_t psc) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + USART_GP(usart_periph) &= ~(USART_GP_PSC); + USART_GP(usart_periph) |= psc; +} + +/*! + \brief configure IrDA low-power + \param[in] usart_periph: USARTx(x=0) + \param[in] irlp: IrDA low-power or normal + only one parameter can be selected which is shown as below: + \arg USART_IRLP_LOW: low-power + \arg USART_IRLP_NORMAL: normal + \param[out] none + \retval none +*/ +void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + USART_CTL2(usart_periph) &= ~(USART_CTL2_IRLP); + USART_CTL2(usart_periph) |= (USART_CTL2_IRLP & irlp); +} + +/*! + \brief configure hardware flow control RTS + \param[in] usart_periph: USARTx(x=0,1) + \param[in] rtsconfig: enable or disable RTS + only one parameter can be selected which is shown as below: + \arg USART_RTS_ENABLE: enable RTS + \arg USART_RTS_DISABLE: disable RTS + \param[out] none + \retval none +*/ +void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) &= ~(USART_CTL2_RTSEN); + USART_CTL2(usart_periph) |= rtsconfig; +} + +/*! + \brief configure hardware flow control CTS + \param[in] usart_periph: USARTx(x=0,1) + \param[in] ctsconfig: enable or disable CTS + only one parameter can be selected which is shown as below: + \arg USART_CTS_ENABLE: enable CTS + \arg USART_CTS_DISABLE: disable CTS + \param[out] none + \retval none +*/ +void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) &= ~USART_CTL2_CTSEN; + USART_CTL2(usart_periph) |= ctsconfig; +} + +/*! + \brief enable RS485 driver + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_rs485_driver_enable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) |= USART_CTL2_DEM; +} + +/*! + \brief disable RS485 driver + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_rs485_driver_disable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) &= ~(USART_CTL2_DEM); +} + +/*! + \brief configure driver enable assertion time + \param[in] usart_periph: USARTx(x=0,1) + \param[in] deatime: 0x00000000-0x0000001F + \param[out] none + \retval none +*/ +void usart_driver_assertime_config(uint32_t usart_periph, uint32_t deatime) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL0(usart_periph) &= ~(USART_CTL0_DEA); + USART_CTL0(usart_periph) |= (USART_CTL0_DEA & ((deatime) << CTL0_DEA_OFFSET)); +} + +/*! + \brief configure driver enable de-assertion time + \param[in] usart_periph: USARTx(x=0,1) + \param[in] dedtime: 0x00000000-0x0000001F + \param[out] none + \retval none +*/ +void usart_driver_deassertime_config(uint32_t usart_periph, uint32_t dedtime) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL0(usart_periph) &= ~(USART_CTL0_DED); + USART_CTL0(usart_periph) |= (USART_CTL0_DED & ((dedtime) << CTL0_DED_OFFSET)); +} + +/*! + \brief configure driver enable polarity mode + \param[in] usart_periph: USARTx(x=0,1) + \param[in] dep: DE signal + only one parameter can be selected which is shown as below: + \arg USART_DEP_HIGH: DE signal is active high + \arg USART_DEP_LOW: DE signal is active low + \param[out] none + \retval none +*/ +void usart_depolarity_config(uint32_t usart_periph, uint32_t dep) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* reset DEP bit */ + USART_CTL2(usart_periph) &= ~(USART_CTL2_DEP); + USART_CTL2(usart_periph) |= (USART_CTL2_DEP & dep); +} + +/*! + \brief configure USART DMA reception + \param[in] usart_periph: USARTx(x=0,1) + \param[in] dmacmd: enable or disable DMA for reception + only one parameter can be selected which is shown as below: + \arg USART_DENR_ENABLE: DMA enable for reception + \arg USART_DENR_DISABLE: DMA disable for reception + \param[out] none + \retval none +*/ +void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd) +{ + USART_CTL2(usart_periph) &= ~USART_CTL2_DENR; + /* configure DMA reception */ + USART_CTL2(usart_periph) |= dmacmd; +} + +/*! + \brief configure USART DMA transmission + \param[in] usart_periph: USARTx(x=0,1) + \param[in] dmacmd: enable or disable DMA for transmission + only one parameter can be selected which is shown as below: + \arg USART_DENT_ENABLE: DMA enable for transmission + \arg USART_DENT_DISABLE: DMA disable for transmission + \param[out] none + \retval none +*/ +void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd) +{ + USART_CTL2(usart_periph) &= ~USART_CTL2_DENT; + /* configure DMA transmission */ + USART_CTL2(usart_periph) |= dmacmd; +} + +/*! + \brief disable DMA on reception error + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_reception_error_dma_disable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) |= USART_CTL2_DDRE; +} + +/*! + \brief enable DMA on reception error + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_reception_error_dma_enable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) &= ~(USART_CTL2_DDRE); +} + +/*! + \brief enable USART to wakeup the mcu from deep-sleep mode + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_wakeup_enable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) |= USART_CTL0_UESM; +} + +/*! + \brief disable USART to wakeup the mcu from deep-sleep mode + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_wakeup_disable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UESM); +} + +/*! + \brief configure the USART wakeup mode from deep-sleep mode + \param[in] usart_periph: USARTx(x=0) + \param[in] wum: wakeup mode + only one parameter can be selected which is shown as below: + \arg USART_WUM_ADDR: WUF active on address match + \arg USART_WUM_STARTB: WUF active on start bit + \arg USART_WUM_RBNE: WUF active on RBNE + \param[out] none + \retval none +*/ +void usart_wakeup_mode_config(uint32_t usart_periph, uint32_t wum) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* reset WUM bit */ + USART_CTL2(usart_periph) &= ~(USART_CTL2_WUM); + USART_CTL2(usart_periph) |= USART_CTL2_WUM & (wum); +} + +/*! + \brief enable USART command + \param[in] usart_periph: USARTx(x=0,1) + \param[in] cmdtype: command type + only one parameter can be selected which is shown as below: + \arg USART_CMD_ABDCMD: auto baudrate detection command + \arg USART_CMD_SBKCMD: send break command + \arg USART_CMD_MMCMD: mute mode command + \arg USART_CMD_RXFCMD: receive data flush command + \arg USART_CMD_TXFCMD: transmit data flush request + \param[out] none + \retval none +*/ +void usart_command_enable(uint32_t usart_periph, uint32_t cmdtype) +{ + USART_CMD(usart_periph) |= (cmdtype); +} + +/*! + \brief enable receive FIFO + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_receive_fifo_enable(uint32_t usart_periph) +{ + USART_RFCS(usart_periph) |= USART_RFCS_RFEN; +} + +/*! + \brief disable receive FIFO + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_receive_fifo_disable(uint32_t usart_periph) +{ + USART_RFCS(usart_periph) &= ~(USART_RFCS_RFEN); +} + +/*! + \brief read receive FIFO counter number + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval receive FIFO counter number +*/ +uint8_t usart_receive_fifo_counter_number(uint32_t usart_periph) +{ + return (uint8_t)(GET_BITS(USART_RFCS(usart_periph), 12U, 14U)); +} + +/*! + \brief get flag in STAT/CHC/RFCS register + \param[in] usart_periph: USARTx(x=0,1) + \param[in] flag: flag type + only one parameter can be selected which is shown as below: + \arg USART_FLAG_PERR: parity error flag + \arg USART_FLAG_FERR: frame error flag + \arg USART_FLAG_NERR: noise error flag + \arg USART_FLAG_ORERR: overrun error + \arg USART_FLAG_IDLE: idle line detected flag + \arg USART_FLAG_RBNE: read data buffer not empty + \arg USART_FLAG_TC: transmission completed + \arg USART_FLAG_TBE: transmit data register empty + \arg USART_FLAG_LBD: LIN break detected flag + \arg USART_FLAG_CTSF: CTS change flag + \arg USART_FLAG_CTS: CTS level + \arg USART_FLAG_RT: receiver timeout flag + \arg USART_FLAG_EB: end of block flag + \arg USART_FLAG_ABDE: auto baudrate detection error + \arg USART_FLAG_ABD: auto baudrate detection flag + \arg USART_FLAG_BSY: busy flag + \arg USART_FLAG_AM: address match flag + \arg USART_FLAG_SB: send break flag + \arg USART_FLAG_RWU: receiver wakeup from mute mode. + \arg USART_FLAG_WU: wakeup from deep-sleep mode flag + \arg USART_FLAG_TEA: transmit enable acknowledge flag + \arg USART_FLAG_REA: receive enable acknowledge flag + \arg USART_FLAG_EPERR: early parity error flag + \arg USART_FLAG_RFE: receive FIFO empty flag + \arg USART_FLAG_RFF: receive FIFO full flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag) +{ + if(RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag)))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear USART status + \param[in] usart_periph: USARTx(x=0,1) + \param[in] flag: flag type + only one parameter can be selected which is shown as below: + \arg USART_FLAG_PERR: parity error flag + \arg USART_FLAG_FERR: frame error flag + \arg USART_FLAG_NERR: noise detected flag + \arg USART_FLAG_ORERR: overrun error flag + \arg USART_FLAG_IDLE: idle line detected flag + \arg USART_FLAG_TC: transmission complete flag + \arg USART_FLAG_LBD: LIN break detected flag + \arg USART_FLAG_CTSF: CTS change flag + \arg USART_FLAG_RT: receiver timeout flag + \arg USART_FLAG_EB: end of block flag + \arg USART_FLAG_AM: address match flag + \arg USART_FLAG_WU: wakeup from deep-sleep mode flag + \arg USART_FLAG_EPERR: early parity error flag + \param[out] none + \retval none +*/ +void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag) +{ + USART_INTC(usart_periph) |= BIT(USART_BIT_POS(flag)); +} + +/*! + \brief enable USART interrupt + \param[in] usart_periph: USARTx(x=0,1) + \param[in] interrupt: interrupt + only one parameter can be selected which is shown as below: + \arg USART_INT_IDLE: idle interrupt + \arg USART_INT_RBNE: read data buffer not empty interrupt and + overrun error interrupt enable interrupt + \arg USART_INT_TC: transmission complete interrupt + \arg USART_INT_TBE: transmit data register empty interrupt + \arg USART_INT_PERR: parity error interrupt + \arg USART_INT_AM: address match interrupt + \arg USART_INT_RT: receiver timeout interrupt + \arg USART_INT_EB: end of block interrupt + \arg USART_INT_LBD: LIN break detection interrupt + \arg USART_INT_ERR: error interrupt enable in multibuffer communication + \arg USART_INT_CTS: CTS interrupt + \arg USART_INT_WU: wakeup from deep-sleep mode interrupt + \arg USART_INT_RFF: receive FIFO full interrupt enable + \param[out] none + \retval none +*/ +void usart_interrupt_enable(uint32_t usart_periph, usart_interrupt_enum interrupt) +{ + USART_REG_VAL(usart_periph, interrupt) |= BIT(USART_BIT_POS(interrupt)); +} + +/*! + \brief disable USART interrupt + \param[in] usart_periph: USARTx(x=0,1) + \param[in] interrupt: interrupt + only one parameter can be selected which is shown as below: + \arg USART_INT_IDLE: idle interrupt + \arg USART_INT_RBNE: read data buffer not empty interrupt and + overrun error interrupt + \arg USART_INT_TC: transmission complete interrupt + \arg USART_INT_TBE: transmit data register empty interrupt + \arg USART_INT_PERR: parity error interrupt + \arg USART_INT_AM: address match interrupt + \arg USART_INT_RT: receiver timeout interrupt + \arg USART_INT_EB: end of block interrupt + \arg USART_INT_LBD: LIN break detection interrupt + \arg USART_INT_ERR: error interrupt enable in multibuffer communication + \arg USART_INT_CTS: CTS interrupt + \arg USART_INT_WU: wakeup from deep-sleep mode interrupt + \arg USART_INT_RFF: receive FIFO full interrupt enable + \param[out] none + \retval none +*/ +void usart_interrupt_disable(uint32_t usart_periph, usart_interrupt_enum interrupt) +{ + USART_REG_VAL(usart_periph, interrupt) &= ~BIT(USART_BIT_POS(interrupt)); +} + +/*! + \brief get USART interrupt and flag status + \param[in] usart_periph: USARTx(x=0,1) + \param[in] int_flag: interrupt and flag type, refer to usart_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg USART_INT_FLAG_EB: end of block interrupt and interrupt flag + \arg USART_INT_FLAG_RT: receiver timeout interrupt flag + \arg USART_INT_FLAG_AM: address match interrupt flag + \arg USART_INT_FLAG_PERR: parity error interrupt flag + \arg USART_INT_FLAG_TBE: transmitter buffer empty interrupt flag + \arg USART_INT_FLAG_TC: transmission complete interrupt flag + \arg USART_INT_FLAG_RBNE: read data buffer not empty interrupt flag + \arg USART_INT_FLAG_RBNE_ORERR: overrun error interrupt flag + \arg USART_INT_FLAG_IDLE: IDLE line detected interrupt flag + \arg USART_INT_FLAG_LBD: LIN break detected interrupt flag + \arg USART_INT_FLAG_WU: wakeup from deep-sleep mode interrupt flag + \arg USART_INT_FLAG_CTS: CTS interrupt flag + \arg USART_INT_FLAG_ERR_NERR: noise error interrupt flag + \arg USART_INT_FLAG_ERR_ORERR: overrun error interrupt flag + \arg USART_INT_FLAG_ERR_FERR: frame error interrupt flag + \arg USART_INT_FLAG_RFFINT: receive FIFO full interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_enum int_flag) +{ + uint32_t intenable = 0U, flagstatus = 0U; + /* get the interrupt enable bit status */ + intenable = (USART_REG_VAL(usart_periph, int_flag) & BIT(USART_BIT_POS(int_flag))); + /* get the corresponding flag bit status */ + flagstatus = (USART_REG_VAL2(usart_periph, int_flag) & BIT(USART_BIT_POS2(int_flag))); + + if(flagstatus && intenable){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear USART interrupt flag + \param[in] usart_periph: USARTx(x=0,1) + \param[in] flag: USART interrupt flag + only one parameter can be selected which is shown as below: + \arg USART_INT_FLAG_PERR: parity error interrupt flag + \arg USART_INT_FLAG_ERR_FERR: frame error interrupt flag + \arg USART_INT_FLAG_ERR_NERR: noise detected interrupt flag + \arg USART_INT_FLAG_RBNE_ORERR: overrun error interrupt flag + \arg USART_INT_FLAG_ERR_ORERR: overrun error interrupt flag + \arg USART_INT_FLAG_IDLE: idle line detected interrupt flag + \arg USART_INT_FLAG_TC: transmission complete interrupt flag + \arg USART_INT_FLAG_LBD: LIN break detected interrupt flag + \arg USART_INT_FLAG_CTS: CTS change interrupt flag + \arg USART_INT_FLAG_RT: receiver timeout interrupt flag + \arg USART_INT_FLAG_EB: end of block interrupt flag + \arg USART_INT_FLAG_AM: address match interrupt flag + \arg USART_INT_FLAG_WU: wakeup from deep-sleep mode interrupt flag + \arg USART_INT_FLAG_RFFINT: receive FIFO full interrupt flag + \param[out] none + \retval none +*/ +void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum int_flag) +{ + if(USART_INT_FLAG_RFFINT == int_flag){ + USART_RFCS(usart_periph) &= (uint32_t)(~USART_RFCS_RFFINT); + }else{ + USART_INTC(usart_periph) |= BIT(USART_BIT_POS2(int_flag)); + } +} diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_wwdgt.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_wwdgt.c new file mode 100644 index 0000000000..10af2b5fb8 --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_wwdgt.c @@ -0,0 +1,142 @@ +/*! + \file gd32f3x0_wwdgt.c + \brief WWDGT driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f3x0_wwdgt.h" +#include "gd32f3x0_rcu.h" + +/*! + \brief reset the window watchdog timer configuration + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_deinit(void) +{ + rcu_periph_reset_enable(RCU_WWDGTRST); + rcu_periph_reset_disable(RCU_WWDGTRST); +} + +/*! + \brief start the window watchdog timer counter + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_enable(void) +{ + WWDGT_CTL |= WWDGT_CTL_WDGTEN; +} + +/*! + \brief configure the window watchdog timer counter value + \param[in] counter_value: 0x00 - 0x7F + \param[out] none + \retval none +*/ +void wwdgt_counter_update(uint16_t counter_value) +{ + uint32_t reg = 0x0U; + + reg = WWDGT_CTL &(~(uint32_t)WWDGT_CTL_CNT); + reg |= (uint32_t)(CTL_CNT(counter_value)); + + WWDGT_CTL = (uint32_t)reg; +} + +/*! + \brief configure counter value, window value, and prescaler divider value + \param[in] counter: 0x00 - 0x7F + \param[in] window: 0x00 - 0x7F + \param[in] prescaler: wwdgt prescaler value + only one parameter can be selected which is shown as below: + \arg WWDGT_CFG_PSC_DIV1: the time base of window watchdog counter = (PCLK1/4096)/1 + \arg WWDGT_CFG_PSC_DIV2: the time base of window watchdog counter = (PCLK1/4096)/2 + \arg WWDGT_CFG_PSC_DIV4: the time base of window watchdog counter = (PCLK1/4096)/4 + \arg WWDGT_CFG_PSC_DIV8: the time base of window watchdog counter = (PCLK1/4096)/8 + \param[out] none + \retval none +*/ +void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler) +{ + uint32_t reg_cfg = 0x0U, reg_ctl = 0x0U; + + /* clear WIN and PSC bits, clear CNT bit */ + reg_cfg = WWDGT_CFG &(~((uint32_t)WWDGT_CFG_WIN|(uint32_t)WWDGT_CFG_PSC)); + reg_ctl = WWDGT_CTL &(~(uint32_t)WWDGT_CTL_CNT); + + /* configure WIN and PSC bits, configure CNT bit */ + reg_cfg |= (uint32_t)(CFG_WIN(window)); + reg_cfg |= (uint32_t)(prescaler); + reg_ctl |= (uint32_t)(CTL_CNT(counter)); + + WWDGT_CFG = (uint32_t)reg_cfg; + WWDGT_CTL = (uint32_t)reg_ctl; +} + +/*! + \brief enable early wakeup interrupt of WWDGT + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_interrupt_enable(void) +{ + WWDGT_CFG |= WWDGT_CFG_EWIE; +} + +/*! + \brief check early wakeup interrupt state of WWDGT + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus wwdgt_flag_get(void) +{ + if(WWDGT_STAT & WWDGT_STAT_EWIF){ + return SET; + } + return RESET; +} + +/*! + \brief clear early wakeup interrupt state of WWDGT + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_flag_clear(void) +{ + WWDGT_STAT &= (uint32_t)(~(uint32_t)WWDGT_STAT_EWIF); +} diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usb_core.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usb_core.h similarity index 81% rename from bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usb_core.h rename to bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usb_core.h index 2891e0219c..a3f6b5a005 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usb_core.h +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usb_core.h @@ -1,12 +1,36 @@ /*! \file usb_core.h \brief USB core driver header file + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2019, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef USB_CORE_H @@ -20,13 +44,8 @@ #define RX_MAX_DATA_LENGTH 512U /* host rx buffer max data length */ #define HC_MAX_PACKET_COUNT 140U /* host channel max packet count */ -#ifdef USE_USBFS - #define USB_MAX_DEV_EPCOUNT USBFS_MAX_DEV_EPCOUNT - #define USB_MAX_FIFOS (USBFS_MAX_HOST_CHANNELCOUNT * 2U - 1U) -#elif defined(USE_USBHS) - #define USB_MAX_DEV_EPCOUNT USBHS_MAX_DEV_EPCOUNT - #define USB_MAX_FIFOS (USBHS_MAX_HOST_CHANNELCOUNT * 2U - 1U) -#endif /* USE_USBFS */ +#define USB_MAX_DEV_EPCOUNT USBFS_MAX_DEV_EPCOUNT +#define USB_MAX_FIFOS (USBFS_MAX_HOST_CHANNELCOUNT * 2U - 1U) /* USB core status */ typedef enum @@ -68,7 +87,6 @@ typedef struct uint8_t phy_interface; /* USB PHY interface */ uint8_t host_channel_num; /* USB host channel number */ uint8_t dev_endp_num; /* USB device endpoint number */ - uint8_t dma_enable; /* USBHS can use DMA */ uint8_t sof_output; /* USB SOF output */ uint8_t low_power; /* USB low power */ uint16_t max_packet_size; /* USB max packet size */ @@ -97,9 +115,9 @@ typedef enum /* USB transfer direction */ typedef enum { - USBD_RX = 0, /* receive direction type value */ - USBD_TX /* transmit direction type value */ -}usbd_dir_enum; + USB_RX = 0, /* receive direction type value */ + USB_TX /* transmit direction type value */ +}usb_dir_enum; /* USB endpoint in device mode */ typedef struct @@ -130,7 +148,7 @@ typedef struct typedef struct { uint8_t config_num; /* USB configuration number */ - uint8_t status; /* USB status */ + __IO uint8_t status; /* USB status */ uint8_t ctl_status; /* USB control status */ uint8_t prev_status; /* USB previous status */ uint8_t connection_status; /* USB connection status */ @@ -153,7 +171,7 @@ typedef struct uint8_t (*class_init) (void *pudev, uint8_t config_index); /* device class initialize */ uint8_t (*class_deinit) (void *pudev, uint8_t config_index); /* device class deinitialize */ uint8_t (*class_req_handler) (void *pudev, usb_device_req_struct *req); /* device request handler */ - uint8_t (*class_data_handler) (void *pudev, usbd_dir_enum rx_tx, uint8_t ep_id); /* device data handler */ + uint8_t (*class_data_handler) (void *pudev, usb_dir_enum rx_tx, uint8_t ep_num); /* device data handler */ }dcd_dev_struct; /* USB core host mode channel */ @@ -162,20 +180,17 @@ typedef struct uint8_t dev_addr; /* device address */ uint8_t dev_speed; /* device speed */ uint8_t DPID; /* endpoint transfer data pid */ - uint8_t endp_id; /* endpoint id */ + uint8_t endp_id; /* endpoint number */ uint8_t endp_in; /* endpoint in */ uint8_t endp_type; /* endpoint type */ uint16_t endp_mps; /* endpoint max pactet size */ uint16_t info; /* channel information */ - uint8_t do_ping; /* USBHS ping */ - uint8_t *xfer_buff; /* transfer buffer */ uint32_t xfer_len; /* transfer length */ uint32_t xfer_count; /* trasnfer count */ uint32_t err_count; /* USB transfer error count */ - uint32_t dma_addr; /* USBHS can use DMA */ hc_status_enum status; /* channel status */ urb_state_enum urb_state; /* URB state */ @@ -236,7 +251,7 @@ usb_status_enum usb_core_select (usb_core_handle_struct *pudev, usb_core_id_enum /* read a packet from the Rx FIFO associated with the endpoint */ void* usb_fifo_read (uint8_t *dest, uint16_t len); /* write a packet into the Tx FIFO associated with the endpoint */ -usb_status_enum usb_fifo_write (uint8_t *src, uint8_t ep_id, uint16_t len); +usb_status_enum usb_fifo_write (uint8_t *src, uint8_t chep_num, uint16_t len); /* flush a Tx FIFO or all Tx FIFOs */ usb_status_enum usb_txfifo_flush (usb_core_handle_struct *pudev, uint8_t fifo_num); /* flush the entire Rx FIFO */ @@ -257,8 +272,6 @@ usb_status_enum usb_hostchannel_init (usb_core_handle_struct *pudev, uint8_t hc_ usb_status_enum usb_hostchannel_halt (usb_core_handle_struct *pudev, uint8_t hc_num); /* prepare host channel for transferring packets */ usb_status_enum usb_hostchannel_startxfer (usb_core_handle_struct *pudev, uint8_t hc_num); -/* issue a ping token */ -usb_status_enum usb_hostchannel_ping (usb_core_handle_struct *pudev, uint8_t hc_num); /* reset host port */ uint32_t usb_port_reset (usb_core_handle_struct *pudev); /* control the VBUS to power */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usb_defines.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usb_defines.h similarity index 74% rename from bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usb_defines.h rename to bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usb_defines.h index 309e23f32f..19b419bd19 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usb_defines.h +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usb_defines.h @@ -1,12 +1,36 @@ /*! \file usb_defines.h \brief USB core defines + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2019, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef USB_DEFINES_H @@ -41,8 +65,8 @@ #define GRSTATR_RPCKST_IN 2U /* IN data packet received */ #define GRSTATR_RPCKST_IN_XFER_COMP 3U /* IN transfer completed (generates an interrupt if poped) */ -#define GRSTATR_RPCKST_DATA_TOGGLE_ERR 5U /* Data toggle error (generates an interrupt if poped) */ -#define GRSTATR_RPCKST_CH_HALTED 7U /* Channel halted (generates an interrupt if poped) */ +#define GRSTATR_RPCKST_DATA_TOGGLE_ERR 5U /* data toggle error (generates an interrupt if poped) */ +#define GRSTATR_RPCKST_CH_HALTED 7U /* channel halted (generates an interrupt if poped) */ #define DEVICE_MODE 0U /* USB core in device mode */ #define HOST_MODE 1U /* USB core in host mode */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usb_regs.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usb_regs.h similarity index 65% rename from bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usb_regs.h rename to bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usb_regs.h index db05aa25ff..2d414a58e2 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usb_regs.h +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usb_regs.h @@ -1,12 +1,36 @@ /*! \file usb_regs.h - \brief USB FS&HS cell registers definition and handle macros + \brief USB FS cell registers definition and handle macros + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2019, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef USB_REGS_H @@ -15,105 +39,88 @@ #include "usb_conf.h" #define USBFS USBFS_BASE /*!< base address of USBFS registers */ -#define USBHS USBHS_BASE /*!< base address of USBHS registers */ - -#ifdef USE_USBFS - #define USBX USBFS /*!< USB full speed mode */ -#endif /* USE_USBFS */ - -#ifdef USE_USBHS - #define USBX USBHS /*!< USB high speed mode */ -#endif /* USE_USBHS */ /* registers location definitions */ -#define LOCATE_DIEPTFLEN(x) (0x104U + 4U * ((x) - 1U)) /*!< locate device IN endpoint-x transfer length registers */ +#define LOCATE_DIEPTFLEN(x) (0x104U + 4U * ((x) - 1U)) /*!< locate device IN endpoint-x (x = 1..3) transfer length registers */ #define LOCATE_HCHCTL(x) (0x500U + 0x20U * (x)) /*!< locate host channel-x control registers */ -#define LOCATE_HCHSTCTL(x) (0x504U + 0x20U * (x)) /*!< locate host channel-x split transaction control registers */ #define LOCATE_HCHINTF(x) (0x508U + 0x20U * (x)) /*!< locate host channel-x interrupt flag registers */ #define LOCATE_HCHINTEN(x) (0x50CU + 0x20U * (x)) /*!< locate host channel-x interrupt enable registers */ #define LOCATE_HCHLEN(x) (0x510U + 0x20U * (x)) /*!< locate host channel-x transfer length registers */ -#define LOCATE_HCHDMAADDR(x) (0x514U + 0x20U * (x)) /*!< locate host channel-x DMA address registers */ #define LOCATE_DIEPCTL(x) (0x900U + 0x20U * (x)) /*!< locate device IN endpoint-x control registers */ #define LOCATE_DOEPCTL(x) (0xB00U + 0x20U * (x)) /*!< locate device OUT endpoint-x control registers */ #define LOCATE_DIEPINTF(x) (0x908U + 0x20U * (x)) /*!< locate device IN endpoint-x interrupt flag registers */ #define LOCATE_DOEPINTF(x) (0xB08U + 0x20U * (x)) /*!< locate device OUT endpoint-x interrupt flag registers */ #define LOCATE_DIEPLEN(x) (0x910U + 0x20U * (x)) /*!< locate device IN endpoint-x transfer length registers */ #define LOCATE_DOEPLEN(x) (0xB10U + 0x20U * (x)) /*!< locate device OUT endpoint-x transfer length registers */ -#define LOCATE_DIEPxDMAADDR(x) (0x914U + 0x20U * (x)) /*!< locate device IN endpoint-x DMA address registers */ -#define LOCATE_DOEPxDMAADDR(x) (0xB14U + 0x20U * (x)) /*!< locate device OUT endpoint-x DMA address registers */ #define LOCATE_DIEPxTFSTAT(x) (0x918U + 0x20U * (x)) /*!< locate Device IN endpoint-x transmit FIFO status register */ #define LOCATE_FIFO(x) (((x) + 1U) << 12U) /*!< locate FIFO-x memory */ /* registers definitions */ -#define USB_GOTGCS REG32(((USBX) + 0x0000U)) /*!< global OTG control and status register */ -#define USB_GOTGINTF REG32(((USBX) + 0x0004U)) /*!< global OTG interrupt flag register */ -#define USB_GAHBCS REG32(((USBX) + 0x0008U)) /*!< global AHB control and status register */ -#define USB_GUSBCS REG32(((USBX) + 0x000CU)) /*!< global USB control and status register */ -#define USB_GRSTCTL REG32(((USBX) + 0x0010U)) /*!< global reset control register */ -#define USB_GINTF REG32(((USBX) + 0x0014U)) /*!< global interrupt flag register */ -#define USB_GINTEN REG32(((USBX) + 0x0018U)) /*!< global interrupt enable register */ -#define USB_GRSTATR REG32(((USBX) + 0x001CU)) /*!< global receive status read register */ -#define USB_GRSTATP REG32(((USBX) + 0x0020U)) /*!< global receive status read and pop register */ -#define USB_GRFLEN REG32(((USBX) + 0x0024U)) /*!< global receive FIFO length register */ -#define USB_HNPTFLEN REG32(((USBX) + 0x0028U)) /*!< host non-periodic transmit FIFO length register */ -#define USB_DIEP0TFLEN REG32(((USBX) + 0x0028U)) /*!< device IN endpoint 0 transmit FIFO length register */ -#define USB_HNPTFQSTAT REG32(((USBX) + 0x002CU)) /*!< host non-periodic transmint FIFO/queue status register */ -#define USB_GCCFG REG32(((USBX) + 0x0038U)) /*!< global core configuration register */ -#define USB_CID REG32(((USBX) + 0x003CU)) /*!< core id register */ -#define USB_HPTFLEN REG32(((USBX) + 0x0100U)) /*!< host periodic transmit FIFO length register */ -#define USB_DIEPxTFLEN(x) REG32(((USBX) + LOCATE_DIEPTFLEN(x))) /*!< device IN endpoint transmit FIFO length register */ +#define USB_GOTGCS REG32(((USBFS) + 0x00000000U)) /*!< global OTG control and status register */ +#define USB_GOTGINTF REG32(((USBFS) + 0x00000004U)) /*!< global OTG interrupt flag register */ +#define USB_GAHBCS REG32(((USBFS) + 0x00000008U)) /*!< global AHB control and status register */ +#define USB_GUSBCS REG32(((USBFS) + 0x0000000CU)) /*!< global USB control and status register */ +#define USB_GRSTCTL REG32(((USBFS) + 0x00000010U)) /*!< global reset control register */ +#define USB_GINTF REG32(((USBFS) + 0x00000014U)) /*!< global interrupt flag register */ +#define USB_GINTEN REG32(((USBFS) + 0x00000018U)) /*!< global interrupt enable register */ +#define USB_GRSTATR REG32(((USBFS) + 0x0000001CU)) /*!< global receive status read register */ +#define USB_GRSTATP REG32(((USBFS) + 0x00000020U)) /*!< global receive status read and pop register */ +#define USB_GRFLEN REG32(((USBFS) + 0x00000024U)) /*!< global receive FIFO length register */ +#define USB_HNPTFLEN REG32(((USBFS) + 0x00000028U)) /*!< host non-periodic transmit FIFO length register */ +#define USB_DIEP0TFLEN REG32(((USBFS) + 0x00000028U)) /*!< device IN endpoint 0 transmit FIFO length register */ +#define USB_HNPTFQSTAT REG32(((USBFS) + 0x0000002CU)) /*!< host non-periodic transmint FIFO/queue status register */ +#define USB_GCCFG REG32(((USBFS) + 0x00000038U)) /*!< global core configuration register */ +#define USB_CID REG32(((USBFS) + 0x0000003CU)) /*!< core id register */ +#define USB_HPTFLEN REG32(((USBFS) + 0x00000100U)) /*!< host periodic transmit FIFO length register */ +#define USB_DIEPxTFLEN(x) REG32(((USBFS) + LOCATE_DIEPTFLEN(x))) /*!< device IN endpoint transmit FIFO length register */ -#define USB_HCTL REG32(((USBX) + 0x0400U)) /*!< host control register */ -#define USB_HFT REG32(((USBX) + 0x0404U)) /*!< host frame interval register */ -#define USB_HFINFR REG32(((USBX) + 0x0408U)) /*!< host frame information remaining register */ -#define USB_HPTFQSTAT REG32(((USBX) + 0x0410U)) /*!< host periodic transmit FIFO/queue status register */ -#define USB_HACHINT REG32(((USBX) + 0x0414U)) /*!< host all channels interrupt register */ -#define USB_HACHINTEN REG32(((USBX) + 0x0418U)) /*!< host all channels interrupt enable register */ -#define USB_HPCS REG32(((USBX) + 0x0440U)) /*!< host port control and status register */ -#define USB_HCHxCTL(x) REG32(((USBX) + LOCATE_HCHCTL(x))) /*!< host channel-x control register */ -#define USB_HCHxSTCTL(x) REG32(((USBX) + LOCATE_HCHSTCTL(x))) /*!< host channel-x split transaction control register */ -#define USB_HCHxINTF(x) REG32(((USBX) + LOCATE_HCHINTF(x))) /*!< host channel-x interrupt flag register */ -#define USB_HCHxINTEN(x) REG32(((USBX) + LOCATE_HCHINTEN(x))) /*!< host channel-x interrupt enable register */ -#define USB_HCHxLEN(x) REG32(((USBX) + LOCATE_HCHLEN(x))) /*!< host channel-x tranfer length register */ -#define USB_HCHxDMAADDR(x) REG32(((USBX) + LOCATE_HCHDMAADDR(x))) /*!< host channel-x DMA address register */ +#define USB_HCTL REG32(((USBFS) + 0x00000400U)) /*!< host control register */ +#define USB_HFT REG32(((USBFS) + 0x00000404U)) /*!< host frame interval register */ +#define USB_HFINFR REG32(((USBFS) + 0x00000408U)) /*!< host frame information remaining register */ +#define USB_HPTFQSTAT REG32(((USBFS) + 0x00000410U)) /*!< host periodic transmit FIFO/queue status register */ +#define USB_HACHINT REG32(((USBFS) + 0x00000414U)) /*!< host all channels interrupt register */ +#define USB_HACHINTEN REG32(((USBFS) + 0x00000418U)) /*!< host all channels interrupt enable register */ +#define USB_HPCS REG32(((USBFS) + 0x00000440U)) /*!< host port control and status register */ +#define USB_HCHxCTL(x) REG32(((USBFS) + LOCATE_HCHCTL(x))) /*!< host channel-x control register */ +#define USB_HCHxINTF(x) REG32(((USBFS) + LOCATE_HCHINTF(x))) /*!< host channel-x interrupt flag register */ +#define USB_HCHxINTEN(x) REG32(((USBFS) + LOCATE_HCHINTEN(x))) /*!< host channel-x interrupt enable register */ +#define USB_HCHxLEN(x) REG32(((USBFS) + LOCATE_HCHLEN(x))) /*!< host channel-x tranfer length register */ -#define USB_DCFG REG32(((USBX) + 0x0800U)) /*!< device configuration register */ -#define USB_DCTL REG32(((USBX) + 0x0804U)) /*!< device control register */ -#define USB_DSTAT REG32(((USBX) + 0x0808U)) /*!< device status register */ -#define USB_DIEPINTEN REG32(((USBX) + 0x0810U)) /*!< device IN endpoint common interrupt enable register */ -#define USB_DOEPINTEN REG32(((USBX) + 0x0814U)) /*!< device OUT endpoint common interrupt enable register */ -#define USB_DAEPINT REG32(((USBX) + 0x0818U)) /*!< device all endpoints interrupt register */ -#define USB_DAEPINTEN REG32(((USBX) + 0x081CU)) /*!< device all endpoints interrupt enable register */ -#define USB_DVBUSDT REG32(((USBX) + 0x0828U)) /*!< device vbus discharge time register */ -#define USB_DVBUSPT REG32(((USBX) + 0x082CU)) /*!< device vbus pulsing time register */ -#define USB_DIEPFEINTEN REG32(((USBX) + 0x0834U)) /*!< device IN endpoint FIFO empty interrupt enable register */ -#define USB_DEP1INT REG32(((USBX) + 0x0838U)) /*!< device endpoint 1 interrupt register */ -#define USB_DEP1INTEN REG32(((USBX) + 0x083CU)) /*!< device endpoint 1 interrupt enable register */ -#define USB_DIEP1INTEN REG32(((USBX) + 0x0844U)) /*!< device IN endpoint 1 interrupt enable register */ -#define USB_DOEP1INTEN REG32(((USBX) + 0x0884U)) /*!< device OUT endpoint 1 interrupt enable register */ -#define USB_DIEP0CTL REG32(((USBX) + 0x0900U)) /*!< device IN endpoint 0 control register */ -#define USB_DIEP0LEN REG32(((USBX) + 0x0910U)) /*!< device IN endpoint 0 transfer length register */ -#define USB_DOEP0CTL REG32(((USBX) + 0x0B00U)) /*!< device OUT endpoint 0 control register */ -#define USB_DOEP0LEN REG32(((USBX) + 0x0B10U)) /*!< device OUT endpoint 0 transfer length register */ -#define USB_DIEPxCTL(x) REG32(((USBX) + LOCATE_DIEPCTL(x))) /*!< device IN endpoint-x control register */ -#define USB_DOEPxCTL(x) REG32(((USBX) + LOCATE_DOEPCTL(x))) /*!< device OUT endpoint-x control register */ -#define USB_DIEPxINTF(x) REG32(((USBX) + LOCATE_DIEPINTF(x))) /*!< device IN endpoint-x interrupt flag register */ -#define USB_DOEPxINTF(x) REG32(((USBX) + LOCATE_DOEPINTF(x))) /*!< device OUT endpoint-x interrupt flag register */ -#define USB_DIEPxLEN(x) REG32(((USBX) + LOCATE_DIEPLEN(x))) /*!< device IN endpoint-x transfer length register */ -#define USB_DOEPxLEN(x) REG32(((USBX) + LOCATE_DOEPLEN(x))) /*!< device OUT endpoint-x transfer length register */ -#define USB_DIEPxDMAADDR(x) REG32(((USBX) + LOCATE_DIEPxDMAADDR(x)))/*!< device IN endpoint-x DMA address register */ -#define USB_DOEPxDMAADDR(x) REG32(((USBX) + LOCATE_DOEPxDMAADDR(x)))/*!< device OUT endpoint-x DMA address register */ -#define USB_DIEPxTFSTAT(x) REG32(((USBX) + LOCATE_DIEPxTFSTAT(x))) /*!< device IN endpoint-x transmit FIFO status register */ +#define USB_DCFG REG32(((USBFS) + 0x00000800U)) /*!< device configuration register */ +#define USB_DCTL REG32(((USBFS) + 0x00000804U)) /*!< device control register */ +#define USB_DSTAT REG32(((USBFS) + 0x00000808U)) /*!< device status register */ +#define USB_DIEPINTEN REG32(((USBFS) + 0x00000810U)) /*!< device IN endpoint common interrupt enable register */ +#define USB_DOEPINTEN REG32(((USBFS) + 0x00000814U)) /*!< device OUT endpoint common interrupt enable register */ +#define USB_DAEPINT REG32(((USBFS) + 0x00000818U)) /*!< device all endpoints interrupt register */ +#define USB_DAEPINTEN REG32(((USBFS) + 0x0000081CU)) /*!< device all endpoints interrupt enable register */ +#define USB_DVBUSDT REG32(((USBFS) + 0x00000828U)) /*!< device vbus discharge time register */ +#define USB_DVBUSPT REG32(((USBFS) + 0x0000082CU)) /*!< device vbus pulsing time register */ +#define USB_DIEPFEINTEN REG32(((USBFS) + 0x00000834U)) /*!< device IN endpoint FIFO empty interrupt enable register */ +#define USB_DEP1INT REG32(((USBFS) + 0x00000838U)) /*!< device endpoint 1 interrupt register */ +#define USB_DEP1INTEN REG32(((USBFS) + 0x0000083CU)) /*!< device endpoint 1 interrupt enable register */ +#define USB_DIEP1INTEN REG32(((USBFS) + 0x00000844U)) /*!< device IN endpoint 1 interrupt enable register */ +#define USB_DOEP1INTEN REG32(((USBFS) + 0x00000884U)) /*!< device OUT endpoint 1 interrupt enable register */ +#define USB_DIEP0CTL REG32(((USBFS) + 0x00000900U)) /*!< device IN endpoint 0 control register */ +#define USB_DIEP0LEN REG32(((USBFS) + 0x00000910U)) /*!< device IN endpoint 0 transfer length register */ +#define USB_DOEP0CTL REG32(((USBFS) + 0x00000B00U)) /*!< device OUT endpoint 0 control register */ +#define USB_DOEP0LEN REG32(((USBFS) + 0x00000B10U)) /*!< device OUT endpoint 0 transfer length register */ +#define USB_DIEPxCTL(x) REG32(((USBFS) + LOCATE_DIEPCTL(x))) /*!< device IN endpoint-x control register */ +#define USB_DOEPxCTL(x) REG32(((USBFS) + LOCATE_DOEPCTL(x))) /*!< device OUT endpoint-x control register */ +#define USB_DIEPxINTF(x) REG32(((USBFS) + LOCATE_DIEPINTF(x))) /*!< device IN endpoint-x interrupt flag register */ +#define USB_DOEPxINTF(x) REG32(((USBFS) + LOCATE_DOEPINTF(x))) /*!< device OUT endpoint-x interrupt flag register */ +#define USB_DIEPxLEN(x) REG32(((USBFS) + LOCATE_DIEPLEN(x))) /*!< device IN endpoint-x transfer length register */ +#define USB_DOEPxLEN(x) REG32(((USBFS) + LOCATE_DOEPLEN(x))) /*!< device OUT endpoint-x transfer length register */ +#define USB_DIEPxTFSTAT(x) REG32(((USBFS) + LOCATE_DIEPxTFSTAT(x)))/*!< device IN endpoint-x transmit FIFO status register */ -#define USB_PWRCLKCTL REG32(((USBX) + 0x0E00U)) /*!< power and clock register */ +#define USB_PWRCLKCTL REG32(((USBFS) + 0x0E00U)) /*!< power and clock register */ -#define USB_FIFO(x) (®32(((USBX) + LOCATE_FIFO(x)))) /*!< FIFO memory */ +#define USB_FIFO(x) (®32(((USBFS) + LOCATE_FIFO(x)))) /*!< FIFO memory */ /* global OTG control and status register bits definitions */ #define GOTGCS_BSV BIT(19) /*!< B-Session Valid */ #define GOTGCS_ASV BIT(18) /*!< A-session valid */ #define GOTGCS_DI BIT(17) /*!< debounce interval */ -#define GOTGCS_CIDPS BIT(16) /*!< id pin status */ +#define GOTGCS_IDPS BIT(16) /*!< id pin status */ #define GOTGCS_DHNPEN BIT(11) /*!< device HNP enable */ #define GOTGCS_HHNPEN BIT(10) /*!< host HNP enable */ #define GOTGCS_HNPREQ BIT(9) /*!< HNP request */ @@ -132,24 +139,17 @@ /* global AHB control and status register bits definitions */ #define GAHBCS_PTXFTH BIT(8) /*!< periodic Tx FIFO threshold */ #define GAHBCS_TXFTH BIT(7) /*!< tx FIFO threshold */ -#define GAHBCS_DMAEN BIT(5) /*!< DMA function Enable */ -#define GAHBCS_BURST BITS(1, 4) /*!< the AHB burst type used by DMA */ #define GAHBCS_GINTEN BIT(0) /*!< global interrupt enable */ /* global USB control and status register bits definitions */ #define GUSBCS_FDM BIT(30) /*!< force device mode */ #define GUSBCS_FHM BIT(29) /*!< force host mode */ -#define GUSBCS_ULPIEOI BIT(21) /*!< ULPI external over-current indicator */ -#define GUSBCS_ULPIEVD BIT(20) /*!< ULPI external VBUS driver */ #define GUSBCS_UTT BITS(10, 13) /*!< USB turnaround time */ #define GUSBCS_HNPCEN BIT(9) /*!< HNP capability enable */ #define GUSBCS_SRPCEN BIT(8) /*!< SRP capability enable */ -#define GUSBCS_EMBPHY BIT(6) /*!< embedded PHY selected */ #define GUSBCS_TOC BITS(0, 2) /*!< timeout calibration */ /* global reset control register bits definitions */ -#define GRSTCTL_DMAIDL BIT(31) /*!< DMA idle state */ -#define GRSTCTL_DMABSY BIT(30) /*!< DMA busy */ #define GRSTCTL_TXFNUM BITS(6, 10) /*!< tx FIFO number */ #define GRSTCTL_TXFF BIT(5) /*!< tx FIFO flush */ #define GRSTCTL_RXFF BIT(4) /*!< rx FIFO flush */ @@ -172,7 +172,7 @@ #define GINTF_IEPIF BIT(18) /*!< IN endpoint interrupt flag */ #define GINTF_EOPFIF BIT(15) /*!< end of periodic frame interrupt flag */ #define GINTF_ISOOPDIF BIT(14) /*!< isochronous OUT packet dropped interrupt flag */ -#define GINTF_ENUMFIF BIT(13) /*!< enumeration finished */ +#define GINTF_ENUMF BIT(13) /*!< enumeration finished */ #define GINTF_RST BIT(12) /*!< USB reset */ #define GINTF_SP BIT(11) /*!< USB suspend */ #define GINTF_ESP BIT(10) /*!< early suspend */ @@ -193,7 +193,7 @@ #define GINTEN_PTXFEIE BIT(26) /*!< periodic tx FIFO empty interrupt enable */ #define GINTEN_HCIE BIT(25) /*!< host channels interrupt enable */ #define GINTEN_HPIE BIT(24) /*!< host port interrupt enable */ -#define GINTEN_IPXIE BIT(21) /*!< periodic transfer not complete interrupt enable */ +#define GINTEN_PXNCIE BIT(21) /*!< periodic transfer not complete interrupt enable */ #define GINTEN_ISOONCIE BIT(21) /*!< isochronous OUT transfer not complete interrupt enable */ #define GINTEN_ISOINCIE BIT(20) /*!< isochronous IN transfer not complete interrupt enable */ #define GINTEN_OEPIE BIT(19) /*!< OUT endpoints interrupt enable */ @@ -212,17 +212,12 @@ #define GINTEN_OTGIE BIT(2) /*!< OTG interrupt enable */ #define GINTEN_MFIE BIT(1) /*!< mode fault interrupt enable */ -/* global receive status debug read register bits definitions */ -#define GRSTATR_RPCKST BITS(17, 20) /*!< received packet status */ -#define GRSTATR_DPID BITS(15, 16) /*!< data PID */ -#define GRSTATR_BCOUNT BITS(4, 14) /*!< byte count */ -#define GRSTATR_CNUM BITS(0, 3) /*!< channel number */ - -/* global status read and pop register bits definitions */ -#define GRSTATP_RPCKST BITS(17, 20) /*!< received packet status */ -#define GRSTATP_DPID BITS(15, 16) /*!< data PID */ -#define GRSTATP_BCOUNT BITS(4, 14) /*!< byte count */ -#define GRSTATP_EPNUM BITS(0, 3) /*!< endpoint number */ +/* global receive status read and pop register bits definitions */ +#define GRSTATRP_RPCKST BITS(17, 20) /*!< received packet status */ +#define GRSTATRP_DPID BITS(15, 16) /*!< data PID */ +#define GRSTATRP_BCOUNT BITS(4, 14) /*!< byte count */ +#define GRSTATRP_CNUM BITS(0, 3) /*!< channel number */ +#define GRSTATRP_EPNUM BITS(0, 3) /*!< endpoint number */ /* global receive FIFO length register bits definitions */ #define GRFLEN_RXFD BITS(0, 15) /*!< rx FIFO depth */ @@ -263,7 +258,6 @@ #define DIEPTFLEN_IEPTXRSAR BITS(0, 15) /*!< IN endpoint FIFOx Tx x RAM start address */ /* host control register bits definitions */ -#define HCTL_SPDFSLS BIT(2) /*!< speed limited to FS and LS */ #define HCTL_CLKSEL BITS(0, 1) /*!< clock select for USB clock */ /* host frame interval register bits definitions */ @@ -284,10 +278,10 @@ #define HPTFQSTAT_TMF BIT(24) /*!< terminate flag */ /* host all channels interrupt register bits definitions */ -#define HACHINT_HACHINT BITS(0, 11) /*!< host all channel interrupts */ +#define HACHINT_HACHINT BITS(0, 7) /*!< host all channel interrupts */ /* host all channels interrupt enable register bits definitions */ -#define HACHINTEN_CINTEN BITS(0, 11) /*!< channel interrupt enable */ +#define HACHINTEN_CINTEN BITS(0, 7) /*!< channel interrupt enable */ /* host port control and status register bits definitions */ #define HPCS_PS BITS(17, 18) /*!< port speed */ @@ -313,13 +307,6 @@ #define HCHCTL_EPNUM BITS(11, 14) /*!< endpoint number */ #define HCHCTL_MPL BITS(0, 10) /*!< maximum packet length */ -/* host channel-x split transaction register bits definitions */ -#define HCHSTCTL_SPLEN BIT(31) /*!< enable high-speed split transaction */ -#define HCHSTCTL_CSPLT BIT(16) /*!< complete-split enable */ -#define HCHSTCTL_ISOPCE BITS(14, 15) /*!< isochronous OUT payload continuation encoding */ -#define HCHSTCTL_HADDR BITS(7, 13) /*!< HUB address */ -#define HCHSTCTL_PADDR BITS(0, 6) /*!< port address */ - /* host channel-x interrupt flag register bits definitions */ #define HCHINTF_DTER BIT(10) /*!< data toggle error */ #define HCHINTF_REQOVR BIT(9) /*!< request queue overrun */ @@ -329,7 +316,6 @@ #define HCHINTF_ACK BIT(5) /*!< ACK */ #define HCHINTF_NAK BIT(4) /*!< NAK */ #define HCHINTF_STALL BIT(3) /*!< STALL */ -#define HCHINTF_DMAER BIT(2) /*!< DMA error */ #define HCHINTF_CH BIT(1) /*!< channel halted */ #define HCHINTF_TF BIT(0) /*!< transfer finished */ @@ -342,19 +328,14 @@ #define HCHINTEN_ACKIE BIT(5) /*!< ACK interrupt enable */ #define HCHINTEN_NAKIE BIT(4) /*!< NAK interrupt enable */ #define HCHINTEN_STALLIE BIT(3) /*!< STALL interrupt enable */ -#define HCHINTEN_DMAERIE BIT(2) /*!< DMA error interrupt enable */ #define HCHINTEN_CHIE BIT(1) /*!< channel halted interrupt enable */ #define HCHINTEN_TFIE BIT(0) /*!< transfer finished interrupt enable */ /* host channel-x transfer length register bits definitions */ -#define HCHLEN_PING BIT(31) /*!< PING token request */ #define HCHLEN_DPID BITS(29, 30) /*!< data PID */ #define HCHLEN_PCNT BITS(19, 28) /*!< packet count */ #define HCHLEN_TLEN BITS(0, 18) /*!< transfer length */ -/* host channel-x DMA address register bits definitions */ -#define HCHDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */ - /* device control and status registers */ /* device configuration registers bits definitions */ #define DCFG_EOPFT BITS(11, 12) /*!< end of periodic frame time */ @@ -379,7 +360,6 @@ #define DSTAT_SPST BIT(0) /*!< suspend status */ /* device IN endpoint common interrupt enable registers bits definitions */ -#define DIEPINTEN_NAKEN BIT(13) /*!< NAK handshake sent by USBHS interrupt enable bit */ #define DIEPINTEN_TXFEEN BIT(7) /*!< transmit FIFO empty interrupt enable bit */ #define DIEPINTEN_IEPNEEN BIT(6) /*!< IN endpoint NAK effective interrupt enable bit */ #define DIEPINTEN_EPTXFUDEN BIT(4) /*!< endpoint Tx FIFO underrun interrupt enable bit */ @@ -388,7 +368,6 @@ #define DIEPINTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */ /* device OUT endpoint common interrupt enable registers bits definitions */ -#define DOEPINTEN_NYETEN BIT(14) /*!< NYET handshake is sent interrupt enable bit */ #define DOEPINTEN_BTBSTPEN BIT(6) /*!< back-to-back SETUP packets interrupt enable bit */ #define DOEPINTEN_EPRXFOVREN BIT(4) /*!< endpoint Rx FIFO overrun interrupt enable bit */ #define DOEPINTEN_STPFEN BIT(3) /*!< SETUP phase finished interrupt enable bit */ @@ -410,94 +389,39 @@ #define DVBUSPT_DVBUSPT BITS(0, 11) /*!< device VBUS pulsing time */ /* device IN endpoint FIFO empty interrupt enable register bits definitions */ -#define DIEPFEINTEN_IEPTXFEIE BITS(0, 5) /*!< IN endpoint Tx FIFO empty interrupt enable bits */ +#define DIEPFEINTEN_IEPTXFEIE BITS(0, 3) /*!< IN endpoint Tx FIFO empty interrupt enable bits */ -/* device endpoint 1 interrupt register bits definitions */ -#define DEP1INT_OEP1INT BIT(17) /*!< OUT Endpoint 1 interrupt */ -#define DEP1INT_IEP1INT BIT(1) /*!< IN Endpoint 1 interrupt */ - -/* device endpoint 1 interrupt register enable bits definitions */ -#define DEP1INTEN_OEP1INTEN BIT(17) /*!< OUT Endpoint 1 interrupt enable */ -#define DEP1INTEN_IEP1INTEN BIT(1) /*!< IN Endpoint 1 interrupt enable */ - -/* device IN endpoint 1 interrupt enable register bits definitions */ -#define DIEP1INTEN_NAKEN BIT(13) /*!< NAK handshake sent by USBHS interrupt enable bit */ -#define DIEP1INTEN_IEPNEEN BIT(6) /*!< IN endpoint NAK effective interrupt enable bit */ -#define DIEP1INTEN_EPTXFUDEN BIT(4) /*!< endpoint Tx FIFO underrun interrupt enable bit */ -#define DIEP1INTEN_CITOEN BIT(3) /*!< control In Timeout interrupt enable bit */ -#define DIEP1INTEN_EPDISEN BIT(1) /*!< endpoint disabled interrupt enable bit */ -#define DIEP1INTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */ - -/* device OUT endpoint 1 interrupt enable register bits definitions */ -#define DOEP1INTEN_NYETEN BIT(14) /*!< NYET handshake is sent interrupt enable bit */ -#define DOEP1INTEN_BTBSTPEN BIT(6) /*!< back-to-back SETUP packets interrupt enable bit */ -#define DOEP1INTEN_EPRXOVREN BIT(4) /*!< endpoint Rx FIFO over run interrupt enable bit */ -#define DOEP1INTEN_STPFEN BIT(3) /*!< SETUP phase finished interrupt enable bit */ -#define DOEP1INTEN_EPDISEN BIT(1) /*!< endpoint disabled interrupt enable bit */ -#define DOEP1INTEN_TFEN BIT(0) /*!< back-to-back SETUP packets interrupt enable bit */ - -/* device IN endpoint 0 control register bits definitions */ -#define DIEP0CTL_EPEN BIT(31) /*!< endpoint enable */ -#define DIEP0CTL_EPD BIT(30) /*!< endpoint disable */ -#define DIEP0CTL_SNAK BIT(27) /*!< set NAK */ -#define DIEP0CTL_CNAK BIT(26) /*!< clear NAK */ +/* device endpoint 0 control register bits definitions */ +#define DEP0CTL_EPEN BIT(31) /*!< endpoint enable */ +#define DEP0CTL_EPD BIT(30) /*!< endpoint disable */ +#define DEP0CTL_SNAK BIT(27) /*!< set NAK */ +#define DEP0CTL_CNAK BIT(26) /*!< clear NAK */ #define DIEP0CTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */ -#define DIEP0CTL_STALL BIT(21) /*!< STALL handshake */ -#define DIEP0CTL_EPTYPE BITS(18, 19) /*!< endpoint type */ -#define DIEP0CTL_NAKS BIT(17) /*!< NAK status */ -#define DIEP0CTL_EPACT BIT(15) /*!< endpoint active */ -#define DIEP0CTL_MPL BITS(0, 1) /*!< maximum packet length */ +#define DEP0CTL_STALL BIT(21) /*!< STALL handshake */ +#define DEP0CTL_EPTYPE BITS(18, 19) /*!< endpoint type */ +#define DEP0CTL_NAKS BIT(17) /*!< NAK status */ +#define DEP0CTL_EPACT BIT(15) /*!< endpoint active */ +#define DEP0CTL_MPL BITS(0, 1) /*!< maximum packet length */ -/* device IN endpoint x control register bits definitions */ -#define DIEPCTL_EPEN BIT(31) /*!< endpoint enable */ -#define DIEPCTL_EPD BIT(30) /*!< endpoint disable */ -#define DIEPCTL_SODDFRM BIT(29) /*!< set odd frame */ -#define DIEPCTL_SD1PID BIT(29) /*!< set DATA1 PID */ -#define DIEPCTL_SEVNFRM BIT(28) /*!< set even frame */ -#define DIEPCTL_SD0PID BIT(28) /*!< set DATA0 PID */ -#define DIEPCTL_SNAK BIT(27) /*!< set NAK */ -#define DIEPCTL_CNAK BIT(26) /*!< clear NAK */ +/* device endpoint x control register bits definitions */ +#define DEPCTL_EPEN BIT(31) /*!< endpoint enable */ +#define DEPCTL_EPD BIT(30) /*!< endpoint disable */ +#define DEPCTL_SODDFRM BIT(29) /*!< set odd frame */ +#define DEPCTL_SD1PID BIT(29) /*!< set DATA1 PID */ +#define DEPCTL_SEVNFRM BIT(28) /*!< set even frame */ +#define DEPCTL_SD0PID BIT(28) /*!< set DATA0 PID */ +#define DEPCTL_SNAK BIT(27) /*!< set NAK */ +#define DEPCTL_CNAK BIT(26) /*!< clear NAK */ #define DIEPCTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */ -#define DIEPCTL_STALL BIT(21) /*!< STALL handshake */ -#define DIEPCTL_EPTYPE BITS(18, 19) /*!< endpoint type */ -#define DIEPCTL_NAKS BIT(17) /*!< NAK status */ -#define DIEPCTL_EOFRM BIT(16) /*!< even/odd frame */ -#define DIEPCTL_DPID BIT(16) /*!< endpoint data PID */ -#define DIEPCTL_EPACT BIT(15) /*!< endpoint active */ -#define DIEPCTL_MPL BITS(0, 10) /*!< maximum packet length */ - -/* device OUT endpoint 0 control register bits definitions */ -#define DOEP0CTL_EPEN BIT(31) /*!< endpoint enable */ -#define DOEP0CTL_EPD BIT(30) /*!< endpoint disable */ -#define DOEP0CTL_SNAK BIT(27) /*!< set NAK */ -#define DOEP0CTL_CNAK BIT(26) /*!< clear NAK */ -#define DOEP0CTL_STALL BIT(21) /*!< STALL handshake */ -#define DOEP0CTL_SNOOP BIT(20) /*!< snoop mode */ -#define DOEP0CTL_EPTYPE BITS(18, 19) /*!< endpoint type */ -#define DOEP0CTL_NAKS BIT(17) /*!< NAK status */ -#define DOEP0CTL_EPACT BIT(15) /*!< endpoint active */ -#define DOEP0CTL_MPL BITS(0, 1) /*!< maximum packet length */ - -/* device OUT endpoint-x control register bits definitions */ -#define DOEPCTL_EPEN BIT(31) /*!< endpoint enable */ -#define DOEPCTL_EPD BIT(30) /*!< endpoint disable */ -#define DOEPCTL_SODDFRM BIT(29) /*!< set odd frame */ -#define DOEPCTL_SD1PID BIT(29) /*!< set DATA1 PID */ -#define DOEPCTL_SEVNFRM BIT(28) /*!< set even frame */ -#define DOEPCTL_SD0PID BIT(28) /*!< set DATA0 PID */ -#define DOEPCTL_SNAK BIT(27) /*!< set NAK */ -#define DOEPCTL_CNAK BIT(26) /*!< clear NAK */ -#define DOEPCTL_STALL BIT(21) /*!< STALL handshake */ -#define DOEPCTL_SNOOP BIT(20) /*!< snoop mode */ -#define DOEPCTL_EPTYPE BITS(18, 19) /*!< endpoint type */ -#define DOEPCTL_NAKS BIT(17) /*!< NAK status */ -#define DOEPCTL_EOFRM BIT(16) /*!< even/odd frame */ -#define DOEPCTL_DPID BIT(16) /*!< endpoint data PID */ -#define DOEPCTL_EPACT BIT(15) /*!< endpoint active */ -#define DOEPCTL_MPL BITS(0, 10) /*!< maximum packet length */ +#define DEPCTL_STALL BIT(21) /*!< STALL handshake */ +#define DEPCTL_EPTYPE BITS(18, 19) /*!< endpoint type */ +#define DEPCTL_NAKS BIT(17) /*!< NAK status */ +#define DEPCTL_EOFRM BIT(16) /*!< even/odd frame */ +#define DEPCTL_DPID BIT(16) /*!< endpoint data PID */ +#define DEPCTL_EPACT BIT(15) /*!< endpoint active */ +#define DEPCTL_MPL BITS(0, 10) /*!< maximum packet length */ /* device IN endpoint-x interrupt flag register bits definitions */ -#define DIEPINTF_NAK BIT(13) /*!< NAK handshake sent by USBHS */ #define DIEPINTF_TXFE BIT(7) /*!< transmit FIFO empty */ #define DIEPINTF_IEPNE BIT(6) /*!< IN endpoint NAK effective */ #define DIEPINTF_EPTXFUD BIT(4) /*!< endpoint Tx FIFO underrun */ @@ -506,7 +430,6 @@ #define DIEPINTF_TF BIT(0) /*!< transfer finished */ /* device OUT endpoint-x interrupt flag register bits definitions */ -#define DOEPINTF_NYET BIT(14) /*!< NYET handshake is sent */ #define DOEPINTF_BTBSTP BIT(6) /*!< back-to-back SETUP packets */ #define DOEPINTF_EPRXFOVR BIT(4) /*!< endpoint Rx FIFO overrun */ #define DOEPINTF_STPF BIT(3) /*!< SETUP phase finished */ @@ -522,22 +445,12 @@ #define DOEP0LEN_PCNT BIT(19) /*!< packet count */ #define DOEP0LEN_TLEN BITS(0, 6) /*!< transfer length */ -/* device IN endpoint-x transfer length register bits definitions */ -#define DIEPLEN_MCNT BITS(29, 30) /*!< multi count */ -#define DIEPLEN_PCNT BITS(19, 28) /*!< packet count */ -#define DIEPLEN_TLEN BITS(0, 18) /*!< transfer length */ - /* device OUT endpoint-x transfer length register bits definitions */ #define DOEPLEN_RXDPID BITS(29, 30) /*!< received data PID */ #define DOEPLEN_STPCNT BITS(29, 30) /*!< SETUP packet count */ -#define DOEPLEN_PCNT BITS(19, 28) /*!< packet count */ -#define DOEPLEN_TLEN BITS(0, 18) /*!< transfer length */ - -/* device IN endpoint-x DMA address register bits definitions */ -#define DIEPDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */ - -/* device OUT endpoint-x DMA address register bits definitions */ -#define DOEPDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */ +#define DIEPLEN_MCNT BITS(29, 30) /*!< multi count */ +#define DEPLEN_PCNT BITS(19, 28) /*!< packet count */ +#define DEPLEN_TLEN BITS(0, 18) /*!< transfer length */ /* device IN endpoint-x transmit FIFO status register bits definitions */ #define DIEPTFSTAT_IEPTFS BITS(0, 15) /*!< IN endpoints Tx FIFO space remaining */ @@ -573,12 +486,12 @@ #define FRAME_INTERVAL_90 DCFG_PFRI(2U) /*!< 90% of the frame time */ #define FRAME_INTERVAL_95 DCFG_PFRI(3U) /*!< 95% of the frame time */ -#define DEP0CTL_MPL(regval) (DOEP0CTL_MPL & ((regval) << 0U)) /*!< maximum packet length configuration */ +#define DEP0_MPL(regval) (DEP0CTL_MPL & ((regval) << 0U)) /*!< maximum packet length configuration */ -#define EP0MPL_64 DEP0CTL_MPL(0U) /*!< maximum packet length 64 bytes */ -#define EP0MPL_32 DEP0CTL_MPL(1U) /*!< maximum packet length 32 bytes */ -#define EP0MPL_16 DEP0CTL_MPL(2U) /*!< maximum packet length 16 bytes */ -#define EP0MPL_8 DEP0CTL_MPL(3U) /*!< maximum packet length 8 bytes */ +#define EP0MPL_64 DEP0_MPL(0U) /*!< maximum packet length 64 bytes */ +#define EP0MPL_32 DEP0_MPL(1U) /*!< maximum packet length 32 bytes */ +#define EP0MPL_16 DEP0_MPL(2U) /*!< maximum packet length 16 bytes */ +#define EP0MPL_8 DEP0_MPL(3U) /*!< maximum packet length 8 bytes */ /* endpoints address */ @@ -604,17 +517,17 @@ /* read global interrupt flag */ #define USB_CORE_INTR_READ(x) \ do { \ - uint32_t global_intf = USB_GINTF; \ - (x) = global_intf & USB_GINTEN; \ + uint32_t global_intf = USB_GINTF; \ + (x) = global_intf & USB_GINTEN; \ } while(0) /* read global interrupt flag */ #define USB_DAOEP_INTR_READ(x) \ do { \ - uint32_t dev_all_ep_inten = USB_DAEPINTEN; \ - uint32_t dev_all_ep_int = USB_DAEPINT; \ - uint32_t out_ep_intb = DAEPINT_OEPITB; \ - (x) = (dev_all_ep_inten & dev_all_ep_int & out_ep_intb) >> 16; \ + uint32_t dev_all_ep_inten = USB_DAEPINTEN; \ + uint32_t dev_all_ep_int = USB_DAEPINT; \ + uint32_t out_ep_intb = DAEPINT_OEPITB; \ + (x) = (dev_all_ep_inten & dev_all_ep_int & out_ep_intb) >> 16; \ } while(0) /* read out endpoint-x interrupt flag */ @@ -627,10 +540,10 @@ do { \ /* read all in endpoint interrupt flag */ #define USB_DAIEP_INTR_READ(x) \ do { \ - uint32_t dev_all_ep_inten = USB_DAEPINTEN; \ - uint32_t dev_all_ep_int = USB_DAEPINT; \ - uint32_t in_ep_intb = DAEPINT_IEPITB; \ - (x) = dev_all_ep_inten & dev_all_ep_int & in_ep_intb; \ + uint32_t dev_all_ep_inten = USB_DAEPINTEN; \ + uint32_t dev_all_ep_int = USB_DAEPINT; \ + uint32_t in_ep_intb = DAEPINT_IEPITB; \ + (x) = dev_all_ep_inten & dev_all_ep_int & in_ep_intb; \ } while(0) diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usb_std.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usb_std.h similarity index 87% rename from bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usb_std.h rename to bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usb_std.h index b7fa5d8e9a..5871882ed3 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usb_std.h +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usb_std.h @@ -1,12 +1,36 @@ /*! \file usb_std.h \brief USB 2.0 standard defines + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2019, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef USB_STD_H diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbd_core.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbd_core.h similarity index 53% rename from bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbd_core.h rename to bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbd_core.h index 8b79c2ed5a..91e69eb724 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbd_core.h +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbd_core.h @@ -1,15 +1,38 @@ /*! \file usbd_core.h - \brief USB device-mode core driver header file + \brief USB device mode core driver header file + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2019, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ - #ifndef USBD_CORE_H #define USBD_CORE_H @@ -27,7 +50,7 @@ /* initailizes the USB device-mode handler stack */ void usbd_init (usb_core_handle_struct *pudev, usb_core_id_enum core_id); /* endpoint initialization */ -void usbd_ep_init (usb_core_handle_struct *pudev, const usb_descriptor_endpoint_struct *pep_desc); +void usbd_ep_init (usb_core_handle_struct *pudev, const usb_descriptor_endpoint_struct *ep_desc); /* endpoint deinitialize */ void usbd_ep_deinit (usb_core_handle_struct *pudev, uint8_t ep_addr); /* endpoint prepare to receive data */ @@ -49,6 +72,6 @@ void usbd_ep_clear_stall (usb_core_handle_struct *pudev, uint8_t ep_addr); /* flushes the FIFOs */ void usbd_ep_fifo_flush (usb_core_handle_struct *pudev, uint8_t ep_addr); /* get the received data length */ -uint16_t usbd_rxcount_get (usb_core_handle_struct *pudev, uint8_t ep_id); +uint16_t usbd_rxcount_get (usb_core_handle_struct *pudev, uint8_t ep_num); #endif /* USBD_CORE_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbd_int.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbd_int.h new file mode 100644 index 0000000000..b2b8d99e88 --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbd_int.h @@ -0,0 +1,53 @@ +/*! + \file usbd_int.h + \brief USB device mode interrupt handler header file + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USBD_INT_H +#define USBD_INT_H + +#include "usbd_core.h" + +typedef struct +{ + uint8_t (*SOF) (usb_core_handle_struct *pudev); +}usbd_int_cb_struct; + +extern usbd_int_cb_struct *usbd_int_fops; + +/* function declarations */ +/* USB device-mode interrupts global service routine handler */ +uint32_t usbd_isr (usb_core_handle_struct *pudev); + +#endif /* USBD_INT_H */ + diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbd_std.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbd_std.h similarity index 62% rename from bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbd_std.h rename to bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbd_std.h index 494f0ec3aa..d968082a1a 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbd_std.h +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbd_std.h @@ -1,12 +1,36 @@ /*! \file usbd_std.h - \brief USB 2.0 standard driver + \brief USB 2.0 standard defines + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2019, GigaDevice Semiconductor Inc. - 2016-06-30, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef USBD_STD_H diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbh_core.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbh_core.h similarity index 90% rename from bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbh_core.h rename to bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbh_core.h index f4e8739687..f2b16fc179 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbh_core.h +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbh_core.h @@ -1,12 +1,36 @@ /*! \file usbh_core.h \brief header file for usbh_core.c + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2019, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.1, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef USBH_CORE_H diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbh_ctrl.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbh_ctrl.h new file mode 100644 index 0000000000..19534dc518 --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbh_ctrl.h @@ -0,0 +1,69 @@ +/*! + \file usbh_ctrl.h + \brief header file for usbh_ctrl.c + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USBH_CTRL_H +#define USBH_CTRL_H + +#include "usbh_core.h" +#include "usbh_usr.h" + +#define CTRL_HANDLE_TABLE_SIZE 13U /*!< the ctrl handle table size define */ + +extern state_table_struct ctrl_handle_table[CTRL_HANDLE_TABLE_SIZE]; +extern uint8_t ctrl_polling_handle_flag; + +/* the enum of CTRL event */ +typedef enum +{ + CTRL_EVENT_IDLE = 0, /* the ctrl idle event */ + CTRL_EVENT_SETUP, /* the ctrl setup event */ + CTRL_EVENT_DATA, /* the ctrl data event */ + CTRL_EVENT_STATUS, /* the ctrl status event */ + CTRL_EVENT_COMPLETE, /* the ctrl complete event */ + CTRL_EVENT_ERROR, /* the ctrl error event */ + CTRL_EVENT_STALLED, /* the ctrl stalled event */ +}ctrl_event_enum; + +/* function declarations */ +/* the polling function of control transfer state handle */ +usbh_status_enum ctrl_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); +/* send datas from the host channel */ +usbh_status_enum usbh_xfer (usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num, uint16_t len); +/* send the setup packet to the device */ +usbh_status_enum usbh_ctltx_setup (usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num); +/* this function prepare a hc and start a transfer */ +uint32_t hcd_submit_request (usb_core_handle_struct *pudev, uint8_t channel_num); + +#endif /* USBH_CTRL_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbh_hcs.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbh_hcs.h new file mode 100644 index 0000000000..6e566e6ff7 --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbh_hcs.h @@ -0,0 +1,70 @@ +/*! + \file usbh_hcs.h + \brief header file for usbh_hcs.c + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USBH_HCS_H +#define USBH_HCS_H + +#include "usbh_core.h" + +#define HC_MAX 8U + +#define HC_OK 0x0000U +#define HC_USED 0x8000U +#define HC_ERROR 0xFFFFU +#define HC_USED_MASK 0x7FFFU + +/* function declarations */ +/* allocate a new channel for the pipe */ +uint8_t usbh_channel_alloc (usb_core_handle_struct *pudev, uint8_t ep_addr); +/* free all usb host channel */ +uint8_t usbh_allchannel_dealloc (usb_core_handle_struct *pudev); +/* free the usb host channel */ +uint8_t usbh_channel_free (usb_core_handle_struct *pudev, uint8_t index); +/* open a channel */ +uint8_t usbh_channel_open (usb_core_handle_struct *pudev, + uint8_t channel_num, + uint8_t dev_addr, + uint8_t dev_speed, + uint8_t ep_type, + uint16_t ep_mps); +/* modify a channel */ +uint8_t usbh_channel_modify (usb_core_handle_struct *pudev, + uint8_t channel_num, + uint8_t dev_addr, + uint8_t dev_speed, + uint8_t ep_type, + uint16_t ep_mps); + +#endif /* USBH_HCS_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbh_int.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbh_int.h new file mode 100644 index 0000000000..b5fe3bb951 --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbh_int.h @@ -0,0 +1,54 @@ +/*! + \file usbh_int.h + \brief USB host mode interrupt handler header file + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USBH_INT_H +#define USBH_INT_H + +#include "usb_core.h" + +typedef struct +{ + uint8_t (*sof) (usb_core_handle_struct *pudev); + uint8_t (*device_connected) (usb_core_handle_struct *pudev); + uint8_t (*device_disconnected) (usb_core_handle_struct *pudev); +}usbh_hcd_int_cb_struct; + +extern usbh_hcd_int_cb_struct *usbh_hcd_int_fops; + +/* function declarations */ +/* handle global host interrupt */ +uint32_t usbh_isr (usb_core_handle_struct *pudev); + +#endif /* USBH_INT_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbh_std.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbh_std.h similarity index 66% rename from bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbh_std.h rename to bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbh_std.h index 2dbc45ee30..48bc65c785 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbh_std.h +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbh_std.h @@ -1,12 +1,36 @@ /*! \file usbh_std.h \brief header file for usbh_std.c + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2019, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef USBH_STD_H diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/system_gd32f3x0.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/system_gd32f3x0.c new file mode 100644 index 0000000000..0ebd5ddea2 --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/system_gd32f3x0.c @@ -0,0 +1,665 @@ +/*! + \file system_gd32f3x0.c + \brief CMSIS Cortex-M4 Device Peripheral Access Layer Source File for + GD32F3x0 Device Series +*/ + +/* Copyright (c) 2012 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ + +#include "gd32f3x0.h" + +/* system frequency define */ +#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */ +#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */ +#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */ + +/* select a system clock by uncommenting the following line */ +#if defined (GD32F330) +//#define __SYSTEM_CLOCK_8M_HXTAL (__HXTAL) +//#define __SYSTEM_CLOCK_8M_IRC8M (__IRC8M) +//#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000) +//#define __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2 (uint32_t)(72000000) +#define __SYSTEM_CLOCK_84M_PLL_HXTAL (uint32_t)(84000000) +//#define __SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2 (uint32_t)(84000000) +#endif /* GD32F330 */ + +#if defined (GD32F350) +//#define __SYSTEM_CLOCK_8M_HXTAL (__HXTAL) +//#define __SYSTEM_CLOCK_8M_IRC8M (__IRC8M) +//#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000) +//#define __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2 (uint32_t)(72000000) +//#define __SYSTEM_CLOCK_84M_PLL_HXTAL (uint32_t)(84000000) +//#define __SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2 (uint32_t)(84000000) +//#define __SYSTEM_CLOCK_96M_PLL_HXTAL (uint32_t)(96000000) +#define __SYSTEM_CLOCK_96M_PLL_IRC8M_DIV2 (uint32_t)(96000000) +//#define __SYSTEM_CLOCK_108M_PLL_HXTAL (uint32_t)(108000000) +//#define __SYSTEM_CLOCK_108M_PLL_IRC8M_DIV2 (uint32_t)(108000000) +#endif /* GD32F350 */ + +#define SEL_IRC8M 0x00 +#define SEL_HXTAL 0x01 +#define SEL_PLL 0x02 + +/* set the system clock frequency and declare the system clock configuration function */ +#ifdef __SYSTEM_CLOCK_8M_HXTAL +uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_HXTAL; +static void system_clock_8m_hxtal(void); + +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL; +static void system_clock_72m_hxtal(void); + +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2; +static void system_clock_72m_irc8m(void); + +#elif defined (__SYSTEM_CLOCK_84M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_84M_PLL_HXTAL; +static void system_clock_84m_hxtal(void); + +#elif defined (__SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2; +static void system_clock_84m_irc8m(void); + +#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_96M_PLL_HXTAL; +static void system_clock_96m_hxtal(void); + +#elif defined (__SYSTEM_CLOCK_96M_PLL_IRC8M_DIV2) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_96M_PLL_IRC8M_DIV2; +static void system_clock_96m_irc8m(void); + +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_HXTAL; +static void system_clock_108m_hxtal(void); + +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M_DIV2) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_IRC8M_DIV2; +static void system_clock_108m_irc8m(void); + +#else +uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_IRC8M; +static void system_clock_8m_irc8m(void); +#endif /* __SYSTEM_CLOCK_8M_HXTAL */ + +/* configure the system clock */ +static void system_clock_config(void); + +/*! + \brief setup the microcontroller system, initialize the system + \param[in] none + \param[out] none + \retval none +*/ +void SystemInit (void) +{ + /* enable IRC8M */ + RCU_CTL0 |= RCU_CTL0_IRC8MEN; + while(0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)){ + } + /* reset RCU */ + RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |\ + RCU_CFG0_ADCPSC | RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV); + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV); +#if (defined(GD32F350)) + RCU_CFG0 &= ~(RCU_CFG0_USBFSPSC); + RCU_CFG2 &= ~(RCU_CFG2_CECSEL | RCU_CFG2_USBFSPSC2); +#endif /* GD32F350 */ + RCU_CTL0 &= ~(RCU_CTL0_HXTALEN | RCU_CTL0_CKMEN | RCU_CTL0_PLLEN | RCU_CTL0_HXTALBPS); + RCU_CFG1 &= ~(RCU_CFG1_PREDV | RCU_CFG1_PLLMF5 | RCU_CFG1_PLLPRESEL); + RCU_CFG2 &= ~(RCU_CFG2_USART0SEL | RCU_CFG2_ADCSEL); + RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV; + RCU_CFG2 &= ~RCU_CFG2_ADCPSC2; + RCU_CTL1 &= ~RCU_CTL1_IRC28MEN; + RCU_ADDCTL &= ~RCU_ADDCTL_IRC48MEN; + RCU_INT = 0x00000000U; + RCU_ADDINT = 0x00000000U; + /* configure system clock */ + system_clock_config(); +} + +/*! + \brief configure the system clock + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_config(void) +{ +#ifdef __SYSTEM_CLOCK_8M_HXTAL + system_clock_8m_hxtal(); +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) + system_clock_72m_hxtal(); +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2) + system_clock_72m_irc8m(); +#elif defined (__SYSTEM_CLOCK_84M_PLL_HXTAL) + system_clock_84m_hxtal(); +#elif defined (__SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2) + system_clock_84m_irc8m(); +#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) + system_clock_96m_hxtal(); +#elif defined (__SYSTEM_CLOCK_96M_PLL_IRC8M_DIV2) + system_clock_96m_irc8m(); +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) + system_clock_108m_hxtal(); +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M_DIV2) + system_clock_108m_irc8m(); +#else + system_clock_8m_irc8m(); +#endif /* __SYSTEM_CLOCK_8M_HXTAL */ +} + +#ifdef __SYSTEM_CLOCK_8M_HXTAL +/*! + \brief configure the system clock to 8M by HXTAL + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_8m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL0 |= RCU_CTL0_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB); + } + while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + /* if fail */ + if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){ + return; + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV1; + + /* select HXTAL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_HXTAL; + + /* wait until HXTAL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_HXTAL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) +/*! + \brief configure the system clock to 72M by PLL which selects HXTAL as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_72m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL0 |= RCU_CTL0_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB); + } + while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + /* if fail */ + if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){ + return; + } + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* PLL = HXTAL * 9 = 72 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLDV); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL9); + + /* enable PLL */ + RCU_CTL0 |= RCU_CTL0_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + + +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2) +/*! + \brief configure the system clock to 72M by PLL which selects IRC8M/2 as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_72m_irc8m(void) +{ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + /* PLL = (IRC8M/2) * 18 = 72 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF); + RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL18); + + /* enable PLL */ + RCU_CTL0 |= RCU_CTL0_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_84M_PLL_HXTAL) +/*! + \brief configure the system clock to 84M by PLL which selects HXTAL as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_84m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + /* enable HXTAL */ + RCU_CTL0 |= RCU_CTL0_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB); + } + while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + /* if fail */ + if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){ + return; + } + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* PLL = HXTAL /2 * 21 = 84 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV); + RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PLLMF5); + RCU_CFG1 |= RCU_PLL_PREDV2; + RCU_CFG0 |= (RCU_CFG0_PLLSEL | RCU_PLL_MUL21); + + /* enable PLL */ + RCU_CTL0 |= RCU_CTL0_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2) +/*! + \brief configure the system clock to 84M by PLL which selects IRC8M/2 as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_84m_irc8m(void) +{ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + /* PLL = (IRC8M/2) * 21 = 84 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF); + RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL21); + + /* enable PLL */ + RCU_CTL0 |= RCU_CTL0_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) +/*! + \brief configure the system clock to 96M by PLL which selects HXTAL as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_96m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + /* enable HXTAL */ + RCU_CTL0 |= RCU_CTL0_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB); + } + while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + /* if fail */ + if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){ + return; + } + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* PLL = HXTAL /2 * 24 = 96 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV); + RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PLLMF5); + RCU_CFG1 |= RCU_PLL_PREDV2; + RCU_CFG0 |= (RCU_CFG0_PLLSEL | RCU_PLL_MUL24); + + /* enable PLL */ + RCU_CTL0 |= RCU_CTL0_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_96M_PLL_IRC8M_DIV2) +/*! + \brief configure the system clock to 96M by PLL which selects IRC8M/2 as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_96m_irc8m(void) +{ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + /* PLL = (IRC8M/2) * 24 = 96 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF); + RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL24); + + /* enable PLL */ + RCU_CTL0 |= RCU_CTL0_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) +/*! + \brief configure the system clock to 84M by PLL which selects HXTAL as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_108m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL0 |= RCU_CTL0_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB); + } + while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + /* if fail */ + if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){ + return; + } + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* PLL = HXTAL /2 * 27 = 108 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV); + RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PLLMF5); + RCU_CFG1 |= RCU_PLL_PREDV2; + RCU_CFG0 |= (RCU_CFG0_PLLSEL | RCU_PLL_MUL27); + + /* enable PLL */ + RCU_CTL0 |= RCU_CTL0_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M_DIV2) +/*! + \brief configure the system clock to 108M by PLL which selects IRC8M/2 as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_108m_irc8m(void) +{ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + /* PLL = (IRC8M/2) * 27 = 108 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF); + RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL27); + + /* enable PLL */ + RCU_CTL0 |= RCU_CTL0_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#else +/*! + \brief configure the system clock to 8M by IRC8M + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_8m_irc8m(void) +{ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV1; + + /* select IRC8M as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_IRC8M; + + /* wait until IRC8M is selected as system clock */ + while(0U != (RCU_CFG0 & RCU_SCSS_IRC8M)){ + } +} +#endif /* __SYSTEM_CLOCK_8M_HXTAL */ + +/*! + \brief update the SystemCoreClock with current core clock retrieved from cpu registers + \param[in] none + \param[out] none + \retval none +*/ +void SystemCoreClockUpdate (void) +{ + uint32_t sws = 0U; + uint32_t pllmf = 0U, pllmf4 = 0U, pllmf5 = 0U, pllsel = 0U, pllpresel = 0U, prediv = 0U, idx = 0U, clk_exp = 0U; + /* exponent of AHB clock divider */ + const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + + sws = GET_BITS(RCU_CFG0, 2, 3); + switch(sws){ + /* IRC8M is selected as CK_SYS */ + case SEL_IRC8M: + SystemCoreClock = IRC8M_VALUE; + break; + /* HXTAL is selected as CK_SYS */ + case SEL_HXTAL: + SystemCoreClock = HXTAL_VALUE; + break; + /* PLL is selected as CK_SYS */ + case SEL_PLL: + /* get the value of PLLMF[3:0] */ + pllmf = GET_BITS(RCU_CFG0, 18, 21); + pllmf4 = GET_BITS(RCU_CFG0, 27, 27); + pllmf5 = GET_BITS(RCU_CFG1, 31, 31); + /* high 16 bits */ + if(1U == pllmf4){ + pllmf += 17U; + }else{ + pllmf += 2U; + } + if(1U == pllmf5){ + pllmf += 31U; + } + /* PLL clock source selection, HXTAL or IRC8M/2 */ + pllsel = GET_BITS(RCU_CFG0, 16, 16); + if(0U != pllsel){ + prediv = (GET_BITS(RCU_CFG1, 0, 3) + 1U); + if(0U == pllpresel){ + SystemCoreClock = (HXTAL_VALUE / prediv) * pllmf; + }else{ + SystemCoreClock = (IRC48M_VALUE / prediv) * pllmf; + } + }else{ + SystemCoreClock = (IRC8M_VALUE >> 1) * pllmf; + } + break; + /* IRC8M is selected as CK_SYS */ + default: + SystemCoreClock = IRC8M_VALUE; + break; + } + /* calculate AHB clock frequency */ + idx = GET_BITS(RCU_CFG0, 4, 7); + clk_exp = ahb_exp[idx]; + SystemCoreClock >>= clk_exp; +} diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usb_core.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usb_core.c similarity index 60% rename from bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usb_core.c rename to bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usb_core.c index 18834acd9e..336645e746 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usb_core.c +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usb_core.c @@ -1,12 +1,36 @@ /*! \file usb_core.c \brief USB core driver which can operate in host-mode and device-mode + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2019, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "usb_core.h" @@ -71,15 +95,15 @@ static usb_status_enum usb_core_reset (usb_core_handle_struct *pudev) /*! \brief write a packet into the Tx FIFO associated with the endpoint \param[in] src: pointer to source buffer - \param[in] ep_id: endpoint identifier which is in (0..3) + \param[in] chep_num: channel or endpoint identifier which is in (0..3) \param[in] len: packet length \param[out] none \retval operation status */ -usb_status_enum usb_fifo_write (uint8_t *src, uint8_t ep_id, uint16_t len) +usb_status_enum usb_fifo_write (uint8_t *src, uint8_t chep_num, uint16_t len) { uint32_t count32b = 0U, i = 0U; - __IO uint32_t *fifo = USB_FIFO(ep_id); + __IO uint32_t *fifo = USB_FIFO(chep_num); count32b = (len + 3U) / 4U; @@ -128,10 +152,9 @@ usb_status_enum usb_core_select (usb_core_handle_struct *pudev, usb_core_id_enum pudev->cfg.core_speed = USB_CORE_SPEED_FULL; pudev->cfg.max_packet_size = USBFS_MAX_PACKET_SIZE; - pudev->cfg.dma_enable = 0U; - /* initialize the core parameters */ if (USB_FS_CORE_ID == core_id) { + pudev->cfg.core_id = USB_FS_CORE_ID; /* set the host channel numbers */ @@ -146,45 +169,13 @@ usb_status_enum usb_core_select (usb_core_handle_struct *pudev, usb_core_id_enum /* OTG_FS core use embedded physical layer */ pudev->cfg.phy_interface = USB_CORE_EMBEDDED_PHY; -#ifdef USBFS_SOF_OUTPUT_ENABLED - pudev->cfg.sof_output = 1U; -#endif /* USBFS_SOF_OUTPUT_ENABLED */ - -#ifdef USBFS_LOW_PWR_MGMT_SUPPORT - pudev->cfg.low_power = 1U; -#endif /* USBFS_LOW_PWR_MGMT_SUPPORT */ - - } else if (USB_HS_CORE_ID == core_id) { - pudev->cfg.core_id = USB_HS_CORE_ID; - - /* set the host channel numbers */ - pudev->cfg.host_channel_num = USBHS_MAX_HOST_CHANNELCOUNT; - - /* set the device endpoint numbers */ - pudev->cfg.dev_endp_num = USBHS_MAX_DEV_EPCOUNT; - - /* fifo size is in terms of DWORD */ - pudev->cfg.max_fifo_size = USBHS_MAX_FIFO_WORDLEN; - -#ifdef USB_ULPI_PHY_ENABLED - pudev->cfg.phy_interface = USB_CORE_ULPI_PHY; -#elif defined(USB_EMBEDDED_PHY_ENABLED) - pudev->cfg.phy_interface = USB_CORE_EMBEDDED_PHY; -#endif /* USB_ULPI_PHY_ENABLED */ - -#ifdef USBHS_INTERNAL_DMA_ENABLED - pudev->cfg.dma_enable = 1U; -#endif /* USBHS_INTERNAL_DMA_ENABLED */ - -#ifdef USBHS_SOF_OUTPUT_ENABLED + #ifdef USBFS_SOF_OUTPUT_ENABLED pudev->cfg.sof_output = 1U; -#endif /* USBHS_SOF_OUTPUT_ENABLED */ + #endif /* USBFS_SOF_OUTPUT_ENABLED */ -#ifdef USBHS_LOW_PWR_MGMT_SUPPORT + #ifdef USBFS_LOW_PWR_MGMT_SUPPORT pudev->cfg.low_power = 1U; -#endif /* USBHS_LOW_PWR_MGMT_SUPPORT */ - } else { - /* no operation */ + #endif /* USBFS_LOW_PWR_MGMT_SUPPORT */ } return USB_OK; @@ -199,62 +190,28 @@ usb_status_enum usb_core_select (usb_core_handle_struct *pudev, usb_core_id_enum */ usb_status_enum usb_core_init (usb_core_handle_struct *pudev) { - if (USB_CORE_ULPI_PHY == pudev->cfg.phy_interface) { - USB_GCCFG &= ~GCCFG_PWRON; + /* soft reset the core */ + usb_core_reset(pudev); - if (pudev->cfg.sof_output) { - USB_GCCFG |= GCCFG_SOFOEN; - } + /* active the transceiver and enable vbus sensing */ + USB_GCCFG |= GCCFG_PWRON | GCCFG_VBUSACEN | GCCFG_VBUSBCEN; - /* use high-speed interface */ - USB_GUSBCS &= ~GUSBCS_EMBPHY; - - /* use internal over-current indicator */ - USB_GUSBCS &= ~GUSBCS_ULPIEOI; - -#ifdef USBHS_EXTERNAL_VBUS_ENABLED - /* use external VBUS driver */ - USB_GUSBCS |= GUSBCS_ULPIEVD; -#else - /* use internal VBUS driver */ - USB_GUSBCS &= ~GUSBCS_ULPIEVD; -#endif - - /* soft reset the core */ - usb_core_reset(pudev); - } else if (USB_CORE_EMBEDDED_PHY == pudev->cfg.phy_interface) { - if (USB_HS_CORE_ID == pudev->cfg.core_id) { - USB_GUSBCS |= GUSBCS_EMBPHY; - } - - /* soft reset the core */ - usb_core_reset(pudev); - - /* active the transceiver and enable vbus sensing */ - USB_GCCFG |= GCCFG_PWRON | GCCFG_VBUSACEN | GCCFG_VBUSBCEN; - - /* set Tx FIFO empty level to half empty mode */ - USB_GAHBCS &= ~GAHBCS_TXFTH | TXFIFO_EMPTY_HALF; + /* set Tx FIFO empty level to half empty mode */ + USB_GAHBCS &= ~GAHBCS_TXFTH | TXFIFO_EMPTY_HALF; #ifndef VBUS_SENSING_ENABLED - USB_GCCFG |= GCCFG_VBUSIG; + USB_GCCFG |= GCCFG_VBUSIG; #endif /* VBUS_SENSING_ENABLED */ - if(pudev->cfg.sof_output){ - USB_GCCFG |= GCCFG_SOFOEN; - } - - if (NULL != pudev->mdelay) { - pudev->mdelay(20U); - } - } else { - /* no operation */ + if(pudev->cfg.sof_output){ + USB_GCCFG |= GCCFG_SOFOEN; } - if (1U == pudev->cfg.dma_enable) { - USB_GAHBCS = DMA_INCR8 | GAHBCS_DMAEN; + if (NULL != pudev->mdelay) { + pudev->mdelay(20U); } + #ifdef USE_OTG_MODE /* enable OTG features */ USB_GUSBCS |= GUSBCS_HNPCAP | GUSBCS_SRPCAP; @@ -276,6 +233,7 @@ usb_status_enum usb_txfifo_flush (usb_core_handle_struct *pudev, uint8_t fifo_nu { uint32_t count = 0U; + USB_GRSTCTL &= ~GRSTCTL_TXFNUM; USB_GRSTCTL = ((uint32_t)fifo_num << 6U) | GRSTCTL_TXFF; /* wait for Tx FIFO flush bit is set */ @@ -359,11 +317,11 @@ usb_status_enum usb_mode_set (usb_core_handle_struct *pudev, uint8_t mode) usb_status_enum usb_hostcore_init (usb_core_handle_struct *pudev) { uint32_t i = 0U; - __IO uint32_t host_nptxfifo_size = 0U; - __IO uint32_t host_ptxfifo_size = 0U; + __IO uint32_t nptxfifolen = 0U; + __IO uint32_t ptxfifolen = 0U; #ifdef USE_OTG_MODE - __IO uint32_t OtgCtrl = 0; + __IO uint32_t otgctl = 0; #endif /* USE_OTG_MODE */ /* restart the PHY clock */ @@ -377,53 +335,30 @@ usb_status_enum usb_hostcore_init (usb_core_handle_struct *pudev) } /* configure data FIFO sizes */ -#ifdef USBFS_CORE if (USB_FS_CORE_ID == pudev->cfg.core_id) { /* set Rx FIFO size */ USB_GRFLEN = USBFS_RX_FIFO_SIZE; /* set non-periodic Tx FIFO size and address */ - host_nptxfifo_size &= ~HNPTFLEN_HNPTXRSAR; - host_nptxfifo_size |= USBFS_RX_FIFO_SIZE; - host_nptxfifo_size &= ~HNPTFLEN_HNPTXFD; - host_nptxfifo_size |= USBFS_HTX_NPFIFO_SIZE << 16; - USB_HNPTFLEN = host_nptxfifo_size; + nptxfifolen &= ~HNPTFLEN_HNPTXRSAR; + nptxfifolen |= USBFS_RX_FIFO_SIZE; + nptxfifolen &= ~HNPTFLEN_HNPTXFD; + nptxfifolen |= USBFS_HTX_NPFIFO_SIZE << 16; + USB_HNPTFLEN = nptxfifolen; /* set periodic Tx FIFO size and address */ - host_ptxfifo_size &= ~HPTFLEN_HPTXFSAR; - host_ptxfifo_size |= USBFS_RX_FIFO_SIZE + USBFS_HTX_PFIFO_SIZE; - host_ptxfifo_size &= ~HPTFLEN_HPTXFD; - host_ptxfifo_size |= USBFS_HTX_PFIFO_SIZE << 16; - USB_HPTFLEN = host_ptxfifo_size; + ptxfifolen &= ~HPTFLEN_HPTXFSAR; + ptxfifolen |= USBFS_RX_FIFO_SIZE + USBFS_HTX_PFIFO_SIZE; + ptxfifolen &= ~HPTFLEN_HPTXFD; + ptxfifolen |= USBFS_HTX_PFIFO_SIZE << 16; + USB_HPTFLEN = ptxfifolen; } -#endif /* USBFS_CORE */ - -#ifdef USBHS_CORE - if (USB_HS_CORE_ID == pudev->cfg.core_id) { - /* set Rx FIFO size */ - USB_GRFLEN = USBHS_RX_FIFO_SIZE; - - /* set non-periodic Tx FIFO size and address */ - host_nptxfifo_size &= ~HNPTFLEN_HNPTXRSAR; - host_nptxfifo_size |= USBHS_RX_FIFO_SIZE; - host_nptxfifo_size &= ~HNPTFLEN_HNPTXFD; - host_nptxfifo_size |= USBHS_HTX_NPFIFO_SIZE << 16; - USB_HNPTFLEN = host_nptxfifo_size; - - /* set periodic Tx FIFO size and address */ - host_ptxfifo_size &= ~HPTFLEN_HPTXFSAR; - host_ptxfifo_size |= USBHS_RX_FIFO_SIZE + USBHS_HTX_PFIFO_SIZE; - host_ptxfifo_size &= ~HPTFLEN_HPTXFD; - host_ptxfifo_size |= USBHS_HTX_PFIFO_SIZE << 16; - USB_HPTFLEN = host_ptxfifo_size; - } -#endif /* USBHS_CORE */ #ifdef USE_OTG_MODE /* clear Host Set HNP Enable bit in the USB OTG Control Register */ - OtgCtrl |= GOTGCS_HHNPEN; - USB_GOTGCS &= ~OtgCtrl; + otgctl |= GOTGCS_HHNPEN; + USB_GOTGCS &= ~otgctl; USB_GOTGCS |= 0; #endif /* USE_OTG_MODE */ @@ -495,7 +430,7 @@ void usb_vbus_drive (usb_core_handle_struct *pudev, uint8_t state) */ usb_status_enum usb_hostint_enable (usb_core_handle_struct *pudev) { - uint32_t global_int_flag = 0U; + uint32_t gintf = 0U; /* disable all interrupts */ USB_GINTEN = 0U; @@ -506,16 +441,13 @@ usb_status_enum usb_hostint_enable (usb_core_handle_struct *pudev) /* enable the common interrupts */ usb_commonint_enable(pudev); - if (0U == pudev->cfg.dma_enable) { - global_int_flag |= GINTF_RXFNEIF; - } + gintf |= GINTF_RXFNEIF; /* enable host_mode-related interrupts */ - global_int_flag |= GINTF_HPIF | GINTF_HCIF | GINTF_DISCIF \ - | GINTF_SOF | GINTF_ISOONCIF; + gintf |= GINTF_HPIF | GINTF_HCIF | GINTF_DISCIF | GINTF_SOF | GINTF_ISOONCIF; - USB_GINTEN &= ~global_int_flag; - USB_GINTEN |= global_int_flag; + USB_GINTEN &= ~gintf; + USB_GINTEN |= gintf; return USB_OK; } @@ -531,7 +463,7 @@ uint32_t usb_port_reset (usb_core_handle_struct *pudev) USB_HPCS = USB_PORT_READ() | HPCS_PRST; if (NULL != pudev->mdelay) { - pudev->mdelay(10U); + pudev->mdelay(100U); } USB_HPCS &= ~HPCS_PRST; @@ -552,52 +484,43 @@ uint32_t usb_port_reset (usb_core_handle_struct *pudev) */ usb_status_enum usb_hostchannel_init(usb_core_handle_struct *pudev, uint8_t hc_num) { - usb_status_enum status = USB_OK; uint8_t is_low_speed = 0U; - __IO uint32_t host_channel_inten = 0U; - __IO uint32_t host_channel_ctlr = 0U; + __IO uint32_t chinten = 0U; + __IO uint32_t chctl = 0U; usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num]; /* clear old interrupt conditions for this host channel */ USB_HCHxINTF((uint16_t)hc_num) = 0xFFFFFFFFU; - if (1U == pudev->cfg.dma_enable) { - host_channel_inten |= HCHINTEN_DMAERIE; - } - /* enable channel interrupts required for this transfer */ switch (puhc->endp_type) { case USB_EPTYPE_CTRL: case USB_EPTYPE_BULK: - host_channel_inten |= HCHINTEN_TFIE | HCHINTEN_STALLIE | HCHINTEN_USBERIE \ + chinten |= HCHINTEN_TFIE | HCHINTEN_STALLIE | HCHINTEN_USBERIE \ | HCHINTEN_DTERIE | HCHINTEN_NAKIE; if (puhc->endp_in) { - host_channel_inten |= HCHINTEN_BBERIE; + chinten |= HCHINTEN_BBERIE; } else { - host_channel_inten |= HCHINTEN_NYETIE; - - if (puhc->do_ping) { - host_channel_inten |= HCHINTEN_ACKIE; - } + chinten |= HCHINTEN_NYETIE; } break; case USB_EPTYPE_INTR: - host_channel_inten |= HCHINTEN_TFIE | HCHINTEN_STALLIE | HCHINTEN_USBERIE | HCHINTEN_DTERIE \ + chinten |= HCHINTEN_TFIE | HCHINTEN_STALLIE | HCHINTEN_USBERIE | HCHINTEN_DTERIE \ | HCHINTEN_NAKIE | HCHINTEN_REQOVRIE; if (puhc->endp_in) { - host_channel_inten |= HCHINTEN_BBERIE; + chinten |= HCHINTEN_BBERIE; } break; case USB_EPTYPE_ISOC: - host_channel_inten |= HCHINTEN_TFIE | HCHINTEN_REQOVRIE | HCHINTEN_ACKIE; + chinten |= HCHINTEN_TFIE | HCHINTEN_REQOVRIE | HCHINTEN_ACKIE; if (puhc->endp_in) { - host_channel_inten |= HCHINTEN_USBERIE | HCHINTEN_BBERIE; + chinten |= HCHINTEN_USBERIE | HCHINTEN_BBERIE; } break; @@ -605,7 +528,7 @@ usb_status_enum usb_hostchannel_init(usb_core_handle_struct *pudev, uint8_t hc_n break; } - USB_HCHxINTEN((uint16_t)hc_num) = host_channel_inten; + USB_HCHxINTEN((uint16_t)hc_num) = chinten; /* enable the top level host channel interrupt */ USB_HACHINTEN |= 1U << hc_num; @@ -614,26 +537,26 @@ usb_status_enum usb_hostchannel_init(usb_core_handle_struct *pudev, uint8_t hc_n USB_GINTEN |= GINTEN_HCIE; /* program the hcctlr register */ - host_channel_ctlr = 0U; + chctl = 0U; if (HPRT_PRTSPD_LOW_SPEED == puhc->dev_speed) { is_low_speed = 1U; } - host_channel_ctlr |= (uint32_t)puhc->dev_addr << 22U; - host_channel_ctlr |= (uint32_t)puhc->endp_type << 18U; - host_channel_ctlr |= (uint32_t)puhc->endp_id << 11U; - host_channel_ctlr |= (uint32_t)puhc->endp_in << 15U; - host_channel_ctlr |= (uint32_t)is_low_speed << 17U; - host_channel_ctlr |= puhc->endp_mps; + chctl |= (uint32_t)puhc->dev_addr << 22U; + chctl |= (uint32_t)puhc->endp_type << 18U; + chctl |= (uint32_t)puhc->endp_id << 11U; + chctl |= (uint32_t)puhc->endp_in << 15U; + chctl |= (uint32_t)is_low_speed << 17U; + chctl |= puhc->endp_mps; if (HCCHAR_INTR == puhc->endp_type) { - host_channel_ctlr |= HCHCTL_ODDFRM; + chctl |= HCHCTL_ODDFRM; } - USB_HCHxCTL((uint16_t)hc_num) = host_channel_ctlr; + USB_HCHxCTL((uint16_t)hc_num) = chctl; - return status; + return USB_OK; } /*! @@ -645,13 +568,11 @@ usb_status_enum usb_hostchannel_init(usb_core_handle_struct *pudev, uint8_t hc_n */ usb_status_enum usb_hostchannel_startxfer(usb_core_handle_struct *pudev, uint8_t hc_num) { - usb_status_enum status = USB_OK; - uint16_t dword_len = 0U; uint16_t packet_num = 0U; - __IO uint32_t host_channel_xlen = 0U; - __IO uint32_t host_channel_ctlr = 0U; + __IO uint32_t chxlen = 0U; + __IO uint32_t chctl = 0U; usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num]; @@ -672,66 +593,60 @@ usb_status_enum usb_hostchannel_startxfer(usb_core_handle_struct *pudev, uint8_t } /* initialize the host channel length register */ - host_channel_xlen &= ~HCHLEN_TLEN; - host_channel_xlen |= puhc->xfer_len; - host_channel_xlen &= ~HCHLEN_PCNT; - host_channel_xlen |= (uint32_t)packet_num << 19U; - host_channel_xlen &= ~HCHLEN_DPID; - host_channel_xlen |= (uint32_t)(puhc->DPID) << 29U; - USB_HCHxLEN((uint16_t)hc_num) = (uint32_t)host_channel_xlen; - - if (1U == pudev->cfg.dma_enable) { - USB_HCHxDMAADDR((uint16_t)hc_num) = (uint32_t)puhc->xfer_buff; - } + chxlen &= ~HCHLEN_TLEN; + chxlen |= puhc->xfer_len; + chxlen &= ~HCHLEN_PCNT; + chxlen |= (uint32_t)packet_num << 19; + chxlen &= ~HCHLEN_DPID; + chxlen |= (uint32_t)(puhc->DPID) << 29; + USB_HCHxLEN((uint16_t)hc_num) = (uint32_t)chxlen; /* set host channel enable */ - host_channel_ctlr = USB_HCHxCTL((uint16_t)hc_num); + chctl = USB_HCHxCTL((uint16_t)hc_num); - if (1U == USB_EVEN_FRAME()) { - host_channel_ctlr |= HCHCTL_ODDFRM; + if (1 == USB_EVEN_FRAME()) { + chctl |= HCHCTL_ODDFRM; } else { - host_channel_ctlr &= ~HCHCTL_ODDFRM; + chctl &= ~HCHCTL_ODDFRM; } - host_channel_ctlr |= HCHCTL_CEN; - host_channel_ctlr &= ~HCHCTL_CDIS; - USB_HCHxCTL((uint16_t)hc_num) = host_channel_ctlr; + chctl |= HCHCTL_CEN; + chctl &= ~HCHCTL_CDIS; + USB_HCHxCTL((uint16_t)hc_num) = chctl; - if (0U == pudev->cfg.dma_enable) { - if ((0U == puhc->endp_in) && (puhc->xfer_len > 0U)) { - dword_len = (uint16_t)(puhc->xfer_len + 3U) / 4U; + if ((0U == puhc->endp_in) && (puhc->xfer_len > 0U)) { + dword_len = (uint16_t)(puhc->xfer_len + 3U) / 4U; - switch (puhc->endp_type) { - /* non-periodic transfer */ - case USB_EPTYPE_CTRL: - case USB_EPTYPE_BULK: - /* check if there is enough space in fifo space */ - if (dword_len > (USB_HNPTFQSTAT & HNPTFQSTAT_NPTXFS)) { - /* need to process data in non-periodic transfer fifo empty interrupt */ - USB_GINTEN |= GINTEN_NPTXFEIE; - } - break; + switch (puhc->endp_type) { + /* non-periodic transfer */ + case USB_EPTYPE_CTRL: + case USB_EPTYPE_BULK: + /* check if there is enough space in fifo space */ + if (dword_len > (USB_HNPTFQSTAT & HNPTFQSTAT_NPTXFS)) { + /* need to process data in non-periodic transfer fifo empty interrupt */ + USB_GINTEN |= GINTEN_NPTXFEIE; + } + break; - /* periodic transfer */ - case USB_EPTYPE_INTR: - case USB_EPTYPE_ISOC: - /* check if there is enough space in FIFO space */ - if (dword_len > (USB_HPTFQSTAT & HPTFQSTAT_PTXFS)) { - /* need to process data in periodic transfer fifo empty interrupt */ - USB_GINTEN |= GINTEN_PTXFEIE; - } - break; + /* periodic transfer */ + case USB_EPTYPE_INTR: + case USB_EPTYPE_ISOC: + /* check if there is enough space in FIFO space */ + if (dword_len > (USB_HPTFQSTAT & HPTFQSTAT_PTXFS)) { + /* need to process data in periodic transfer fifo empty interrupt */ + USB_GINTEN |= GINTEN_PTXFEIE; + } + break; - default: - break; - } - - /* write packet into the Tx FIFO. */ - usb_fifo_write(puhc->xfer_buff, hc_num, (uint16_t)puhc->xfer_len); + default: + break; } + + /* write packet into the Tx FIFO. */ + usb_fifo_write(puhc->xfer_buff, hc_num, (uint16_t)puhc->xfer_len); } - return status; + return USB_OK; } /*! @@ -744,46 +659,24 @@ usb_status_enum usb_hostchannel_startxfer(usb_core_handle_struct *pudev, uint8_t usb_status_enum usb_hostchannel_halt(usb_core_handle_struct *pudev, uint8_t hc_num) { uint8_t endp_type = 0U; - __IO uint32_t host_channel_ctrl = USB_HCHxCTL((uint16_t)hc_num); + __IO uint32_t chctl = USB_HCHxCTL((uint16_t)hc_num); - host_channel_ctrl |= HCHCTL_CEN | HCHCTL_CDIS; + chctl |= HCHCTL_CEN | HCHCTL_CDIS; - endp_type = (uint8_t)((host_channel_ctrl & HCHCTL_EPTYPE) >> 18U); + endp_type = (uint8_t)((chctl & HCHCTL_EPTYPE) >> 18U); /* check for space in the request queue to issue the halt. */ if ((HCCHAR_CTRL == endp_type) || (HCCHAR_BULK == endp_type)) { if (0U == (USB_HNPTFQSTAT & HNPTFQSTAT_NPTXFS)) { - host_channel_ctrl |= HCHCTL_CDIS; + chctl &= ~HCHCTL_CEN; } } else { if (0U == (USB_HPTFQSTAT & HPTFQSTAT_PTXFS)) { - host_channel_ctrl |= HCHCTL_CEN; + chctl &= ~HCHCTL_CEN; } } - USB_HCHxCTL((uint16_t)hc_num) = host_channel_ctrl; - - return USB_OK; -} - -/*! - \brief issue a ping token - \param[in] pudev: pointer to usb device - \param[in] hc_num: host channel number which is in (0..7) - \param[out] none - \retval operation status -*/ -usb_status_enum usb_hostchannel_ping(usb_core_handle_struct *pudev, uint8_t hc_num) -{ - uint32_t host_channel_ctrl = 0U; - - USB_HCHxLEN((uint16_t)hc_num) = HCHLEN_PING | (HCHLEN_PCNT & (1U << 19U)); - - host_channel_ctrl = USB_HCHxCTL((uint16_t)hc_num); - host_channel_ctrl |= HCHCTL_CEN; - host_channel_ctrl &= ~HCHCTL_CDIS; - - USB_HCHxCTL((uint16_t)hc_num) = host_channel_ctrl; + USB_HCHxCTL((uint16_t)hc_num) = chctl; return USB_OK; } @@ -817,8 +710,6 @@ void usb_host_stop(usb_core_handle_struct *pudev) #ifdef USE_DEVICE_MODE -#ifdef USBFS_CORE - /* USB endpoint Tx FIFO size */ static uint16_t USBFS_TX_FIFO_SIZE[USBFS_MAX_DEV_EPCOUNT] = { @@ -828,20 +719,6 @@ static uint16_t USBFS_TX_FIFO_SIZE[USBFS_MAX_DEV_EPCOUNT] = (uint16_t)TX3_FIFO_FS_SIZE }; -#elif defined(USBHS_CORE) - -uint16_t USBHS_TX_FIFO_SIZE[USBHS_MAX_DEV_EPCOUNT] = -{ - (uint16_t)TX0_FIFO_HS_SIZE, - (uint16_t)TX1_FIFO_HS_SIZE, - (uint16_t)TX2_FIFO_HS_SIZE, - (uint16_t)TX3_FIFO_HS_SIZE, - (uint16_t)TX4_FIFO_HS_SIZE, - (uint16_t)TX5_FIFO_HS_SIZE -}; - -#endif /* USBFS_CORE */ - static usb_status_enum usb_devint_enable(usb_core_handle_struct *pudev); /*! @@ -853,8 +730,8 @@ static usb_status_enum usb_devint_enable(usb_core_handle_struct *pudev); usb_status_enum usb_devcore_init (usb_core_handle_struct *pudev) { uint32_t i, ram_address = 0U; - __IO uint32_t dev_in_ep0_inf = USB_DIEP0TFLEN; - __IO uint32_t dev_in_ep_inf = 0U; + __IO uint32_t devinep0intf = USB_DIEP0TFLEN; + __IO uint32_t devinepintf = 0U; /* restart the Phy Clock (Maybe don't need to...) */ USB_PWRCLKCTL = 0U; @@ -863,7 +740,6 @@ usb_status_enum usb_devcore_init (usb_core_handle_struct *pudev) USB_DCFG &= ~DCFG_EOPFT; USB_DCFG |= FRAME_INTERVAL_80; -#ifdef USBFS_CORE if (USB_FS_CORE_ID == pudev->cfg.core_id) { /* set full speed PHY */ USB_DCFG &= ~DCFG_DS; @@ -871,70 +747,30 @@ usb_status_enum usb_devcore_init (usb_core_handle_struct *pudev) /* set Rx FIFO size */ USB_GRFLEN &= ~GRFLEN_RXFD; - USB_GRFLEN |= RX_FIFO_FS_SIZE; + USB_GRFLEN |= (uint32_t)RX_FIFO_FS_SIZE; /* set endpoint 0 Tx FIFO length and RAM address */ - dev_in_ep0_inf &= ~DIEP0TFLEN_IEP0TXFD; - dev_in_ep0_inf |= TX0_FIFO_FS_SIZE << 16; - dev_in_ep0_inf &= ~DIEP0TFLEN_IEP0TXRSAR; - dev_in_ep0_inf |= RX_FIFO_FS_SIZE; + devinep0intf &= ~DIEP0TFLEN_IEP0TXFD; + devinep0intf |= (uint32_t)TX0_FIFO_FS_SIZE << 16; + devinep0intf &= ~DIEP0TFLEN_IEP0TXRSAR; + devinep0intf |= (uint32_t)RX_FIFO_FS_SIZE; - USB_DIEP0TFLEN = dev_in_ep0_inf; + USB_DIEP0TFLEN = devinep0intf; - ram_address = RX_FIFO_FS_SIZE; + ram_address = (uint32_t)RX_FIFO_FS_SIZE; /* set endpoint 1 to 3's Tx FIFO length and RAM address */ for (i = 1U; i < USBFS_MAX_DEV_EPCOUNT; i++) { ram_address += USBFS_TX_FIFO_SIZE[i - 1U]; - dev_in_ep_inf &= ~DIEPTFLEN_IEPTXFD; - dev_in_ep_inf |= (uint32_t)USBFS_TX_FIFO_SIZE[i] << 16U; - dev_in_ep_inf &= ~DIEPTFLEN_IEPTXRSAR; - dev_in_ep_inf |= ram_address; + devinepintf &= ~DIEPTFLEN_IEPTXFD; + devinepintf |= (uint32_t)USBFS_TX_FIFO_SIZE[i] << 16U; + devinepintf &= ~DIEPTFLEN_IEPTXRSAR; + devinepintf |= ram_address; - USB_DIEPxTFLEN(i) = dev_in_ep_inf; + USB_DIEPxTFLEN(i) = devinepintf; } } -#endif /* USBFS_CORE */ - -#ifdef USBHS_CORE - if (USB_HS_CORE_ID == pudev->cfg.core_id) { - USB_DCFG &= ~DCFG_DS; - - if (USB_CORE_EMBEDDED_PHY == pudev->cfg.phy_interface) { - /* set full speed PHY in USB high speed core */ - USB_DCFG |= USB_SPEED_INP_FULL; - } else if (USB_CORE_ULPI_PHY == pudev->cfg.phy_interface) { - USB_DCFG |= USB_SPEED_EXP_HIGH; - } - - /* set Rx FIFO size */ - USB_GRFLEN &= ~GRFLEN_RXFD; - USB_GRFLEN |= RX_FIFO_HS_SIZE; - - /* set endpoint 0 Tx FIFO length and RAM address */ - dev_in_ep0_inf &= ~DIEP0TFLEN_IEP0TXFD; - dev_in_ep0_inf |= TX0_FIFO_HS_SIZE << 16; - dev_in_ep0_inf &= ~DIEP0TFLEN_IEP0TXRSAR; - dev_in_ep0_inf |= RX_FIFO_HS_SIZE; - - USB_DIEP0TFLEN = dev_in_ep0_inf; - - ram_address = RX_FIFO_HS_SIZE; - - /* set endpoint 1 to 3's Tx FIFO length and RAM address */ - for (i = 1; i < USBHS_MAX_DEV_EPCOUNT; i++) { - ram_address += USBHS_TX_FIFO_SIZE[i - 1]; - - dev_in_ep_inf &= ~DIEPTFLEN_IEPTXFD; - dev_in_ep_inf |= USBHS_TX_FIFO_SIZE[i] << 16; - dev_in_ep_inf &= ~DIEPTFLEN_IEPTXRSAR; - dev_in_ep_inf |= ram_address; - - USB_DIEPxTFLEN(i) = dev_in_ep_inf; - } - } -#endif /* USBHS_CORE */ /* make sure all FIFOs are flushed */ @@ -947,19 +783,19 @@ usb_status_enum usb_devcore_init (usb_core_handle_struct *pudev) /* clear all pending device interrupts */ USB_DIEPINTEN = 0U; USB_DOEPINTEN = 0U; - USB_DAEPINT = 0xFFFFFFFF; + USB_DAEPINT = 0xFFFFFFFFU; USB_DAEPINTEN = 0U; /* configure all IN/OUT endpoints */ for (i = 0U; i < pudev->cfg.dev_endp_num; i++) { - if (USB_DIEPxCTL(i) & DIEPCTL_EPEN) { - USB_DIEPxCTL(i) |= DIEPCTL_EPD | DIEPCTL_SNAK; + if (USB_DIEPxCTL(i) & DEPCTL_EPEN) { + USB_DIEPxCTL(i) |= DEPCTL_EPD | DEPCTL_SNAK; } else { USB_DIEPxCTL(i) = 0U; } - if (USB_DOEPxCTL(i) & DOEPCTL_EPEN) { - USB_DOEPxCTL(i) |= DOEPCTL_EPD | DOEPCTL_SNAK; + if (USB_DOEPxCTL(i) & DEPCTL_EPEN) { + USB_DOEPxCTL(i) |= DEPCTL_EPD | DEPCTL_SNAK; } else { USB_DOEPxCTL(i) = 0U; } @@ -973,7 +809,6 @@ usb_status_enum usb_devcore_init (usb_core_handle_struct *pudev) USB_DOEPxINTF(i) = 0xFFU; } - USB_DIEPINTEN |= DIEPINTEN_EPTXFUDEN; usb_devint_enable(pudev); return USB_OK; @@ -998,9 +833,7 @@ static usb_status_enum usb_devint_enable(usb_core_handle_struct *pudev) /* enable the common interrupts */ usb_commonint_enable(pudev); - if (0U == pudev->cfg.dma_enable) { - int_mask = GINTEN_RXFNEIE; - } + int_mask = GINTEN_RXFNEIE; /* enable device_mode-related interrupts */ int_mask |= GINTEN_SPIE | GINTEN_RSTIE | GINTEN_ENUMFIE \ @@ -1025,27 +858,21 @@ static usb_status_enum usb_devint_enable(usb_core_handle_struct *pudev) */ void usb_ep0_startout(usb_core_handle_struct *pudev) { - __IO uint32_t ep0_xlen = 0U; + __IO uint32_t ep0len = 0U; /* set OUT endpoint 0 receive length to 24 bytes */ - ep0_xlen &= ~DOEP0LEN_TLEN; - ep0_xlen |= 8U * 3U; + ep0len &= ~DOEP0LEN_TLEN; + ep0len |= 8U * 3U; /* set OUT endpoint 0 receive length to 1 packet */ - ep0_xlen &= ~DOEP0LEN_PCNT; - ep0_xlen |= 1U << 19; + ep0len &= ~DOEP0LEN_PCNT; + ep0len |= 1U << 19; /* set SETUP packet count to 3 */ - ep0_xlen &= ~DOEP0LEN_STPCNT; - ep0_xlen |= 3U << 29; + ep0len &= ~DOEP0LEN_STPCNT; + ep0len |= 3U << 29; - USB_DOEPxLEN(0U) = ep0_xlen; - - if (1U == pudev->cfg.dma_enable) { - USB_DOEPxDMAADDR(0U) = (uint32_t)&pudev->dev.setup_packet; - - USB_DOEPxCTL(0U) = DOEPCTL_EPEN | DOEPCTL_EPACT; - } + USB_DOEPxLEN(0U) = ep0len; } /*! @@ -1129,4 +956,4 @@ void usb_device_stop (usb_core_handle_struct *pudev) usb_rxfifo_flush(pudev); usb_txfifo_flush(pudev, 0x10U); } -#endif /* USE_DEVICE_MODE */ +#endif /* USE_DEVICE_MODE */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbd_core.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbd_core.c similarity index 55% rename from bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbd_core.c rename to bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbd_core.c index 0d15a7950f..0bf5841e15 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbd_core.c +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbd_core.c @@ -1,12 +1,36 @@ /*! \file usbd_core.c - \brief USB device-mode core driver + \brief USB device mode core driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2019, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "usbd_core.h" @@ -59,88 +83,68 @@ void usbd_init (usb_core_handle_struct *pudev, usb_core_id_enum core_id) /*! \brief endpoint initialization \param[in] pudev: pointer to usb device instance - \param[in] pep_desc: pointer to usb endpoint descriptor + \param[in] ep_desc: pointer to usb endpoint descriptor \param[out] none \retval none */ -void usbd_ep_init (usb_core_handle_struct *pudev, const usb_descriptor_endpoint_struct *pep_desc) +void usbd_ep_init (usb_core_handle_struct *pudev, const usb_descriptor_endpoint_struct *ep_desc) { usb_ep_struct *ep; + usb_dir_enum ep_dir; - uint32_t dev_all_ep_int_en = 0U; - uint32_t dev_ep_ctlr = 0U; + uint32_t devepinten = 0U; + uint32_t devepctl = 0U; - uint8_t ep_id = pep_desc->bEndpointAddress & 0x7FU; - uint8_t ep_type = pep_desc->bmAttributes & USB_EPTYPE_MASK; - uint16_t ep_mps = pep_desc->wMaxPacketSize; + uint8_t ep_num = ep_desc->bEndpointAddress & 0x7FU; + uint8_t ep_type = ep_desc->bmAttributes & USB_EPTYPE_MASK; + uint16_t ep_mps = ep_desc->wMaxPacketSize; - if (pep_desc->bEndpointAddress >> 7) { - ep = &pudev->dev.in_ep[ep_id]; + if (ep_desc->bEndpointAddress >> 7) { + ep = &pudev->dev.in_ep[ep_num]; - dev_all_ep_int_en |= 1U << ep_id; - dev_ep_ctlr = USB_DIEPxCTL((uint16_t)ep_id); + devepinten |= 1U << ep_num; + devepctl = USB_DIEPxCTL((uint16_t)ep_num); - /* if the endpoint is not active, need change the endpoint control register */ - if (!(dev_ep_ctlr & DIEPCTL_EPACT)) { - if (0U == ep_id) { - dev_ep_ctlr &= ~DIEP0CTL_MPL; - } else { - dev_ep_ctlr &= ~DIEPCTL_MPL; - } - dev_ep_ctlr |= ep_mps; - - dev_ep_ctlr &= ~DIEPCTL_EPTYPE; - dev_ep_ctlr |= (uint32_t)ep_type << 18; - - dev_ep_ctlr &= ~DIEPCTL_TXFNUM; - dev_ep_ctlr |= (uint32_t)ep_id << 22; - - if (0U != ep_id) { - dev_ep_ctlr |= DIEPCTL_SD0PID; - dev_ep_ctlr |= DIEPCTL_EPACT; - } - - USB_DIEPxCTL((uint16_t)ep_id) = dev_ep_ctlr; - } + ep_dir = USB_TX; } else { - ep = &pudev->dev.out_ep[ep_id]; + ep = &pudev->dev.out_ep[ep_num]; - dev_all_ep_int_en |= (1U << ep_id) << 16; - dev_ep_ctlr = USB_DOEPxCTL((uint16_t)ep_id); + devepinten |= (1U << ep_num) << 16; + devepctl = USB_DOEPxCTL((uint16_t)ep_num); - /* if the endpoint is not active, need change the endpoint control register */ - if (!(dev_ep_ctlr & DOEPCTL_EPACT)) { - if (0U == ep_id) { - dev_ep_ctlr &= ~DOEP0CTL_MPL; - } else { - dev_ep_ctlr &= ~DOEPCTL_MPL; - } - dev_ep_ctlr |= ep_mps; + ep_dir = USB_RX; + } - dev_ep_ctlr &= ~DOEPCTL_EPTYPE; - dev_ep_ctlr |= (uint32_t)ep_type << 18; + /* if the endpoint is not active, need change the endpoint control register */ + if (!(devepctl & DEPCTL_EPACT)) { + devepctl &= ~DEPCTL_MPL; + devepctl |= ep_mps; - if (0U != ep_id) { - dev_ep_ctlr |= DOEPCTL_SD0PID; - dev_ep_ctlr |= DOEPCTL_EPACT; - } + devepctl &= ~DEPCTL_EPTYPE; + devepctl |= (uint32_t)ep_type << 18; - USB_DOEPxCTL((uint16_t)ep_id) = dev_ep_ctlr; + if (USB_TX == ep_dir) { + devepctl &= ~DIEPCTL_TXFNUM; + devepctl |= (uint32_t)ep_num << 22; } + + devepctl |= DEPCTL_SD0PID; + devepctl |= DEPCTL_EPACT; + } + + if (USB_TX == ep_dir) { + USB_DIEPxCTL((uint16_t)ep_num) = devepctl; + } else if (USB_RX == ep_dir) { + USB_DOEPxCTL((uint16_t)ep_num) = devepctl; + } else { + /* no operation */ } ep->endp_mps = ep_mps; ep->endp_type = ep_type; /* enable the interrupts for this endpoint */ -#ifdef USBHS_DEDICATED_EP1_ENABLED - if ((1 == ep_id) && (USB_HS_CORE_ID == pudev->cfg.core_id)) { - USB_DEP1INTEN |= dev_all_ep_int_en; - } else -#endif /* USBHS_DEDICATED_EP1_ENABLED */ - { - USB_DAEPINTEN |= dev_all_ep_int_en; - } + USB_DAEPINTEN |= devepinten; } /*! @@ -152,28 +156,21 @@ void usbd_ep_init (usb_core_handle_struct *pudev, const usb_descriptor_endpoint_ */ void usbd_ep_deinit (usb_core_handle_struct *pudev, uint8_t ep_addr) { - uint32_t dev_all_ep_int_en = 0U; - uint8_t ep_id = ep_addr & 0x7FU; + uint32_t devepinten = 0U; + uint8_t ep_num = ep_addr & 0x7FU; if (ep_addr >> 7) { - dev_all_ep_int_en |= 1U << ep_id; + devepinten |= 1U << ep_num; - USB_DIEPxCTL((uint16_t)ep_id) &= ~DIEPCTL_EPACT; + USB_DIEPxCTL((uint16_t)ep_num) &= ~DEPCTL_EPACT; } else { - dev_all_ep_int_en |= (1U << ep_id) << 16U; + devepinten |= (1U << ep_num) << 16U; - USB_DOEPxCTL((uint16_t)ep_id) &= ~DOEPCTL_EPACT; + USB_DOEPxCTL((uint16_t)ep_num) &= ~DEPCTL_EPACT; } /* disable the interrupts for this endpoint */ -#ifdef USBHS_DEDICATED_EP1_ENABLED - if ((1U == ep_id) && (USB_HS_CORE_ID == pudev->cfg.core_id)) { - USB_DEP1INTEN &= ~dev_all_ep_int_en; - } else -#endif /* USBHS_DEDICATED_EP1_ENABLED */ - { - USB_DAEPINTEN &= ~dev_all_ep_int_en; - } + USB_DAEPINTEN &= ~devepinten; } /*! @@ -188,68 +185,61 @@ void usbd_ep_deinit (usb_core_handle_struct *pudev, uint8_t ep_addr) void usbd_ep_rx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len) { usb_ep_struct *ep; - uint8_t ep_id = ep_addr & 0x7FU; - uint32_t dev_ep_ctlr = 0U, dev_ep_xlen = 0U; + uint8_t ep_num = ep_addr & 0x7FU; + uint32_t devepctl = 0U, devepxlen = 0U; - ep = &pudev->dev.out_ep[ep_id]; + ep = &pudev->dev.out_ep[ep_num]; /* setup and start the Xfer */ ep->xfer_buff = pbuf; ep->xfer_len = buf_len; ep->xfer_count = 0U; - if (1U == pudev->cfg.dma_enable) { - ep->dma_addr = (uint32_t)pbuf; - } + devepctl = USB_DOEPxCTL((uint16_t)ep_num); + devepxlen = USB_DOEPxLEN((uint16_t)ep_num); - dev_ep_ctlr = USB_DOEPxCTL((uint16_t)ep_id); - dev_ep_xlen = USB_DOEPxLEN((uint16_t)ep_id); - - dev_ep_xlen &= ~DOEPLEN_TLEN; - dev_ep_xlen &= ~DOEPLEN_PCNT; + devepxlen &= ~DEPLEN_TLEN; + devepxlen &= ~DEPLEN_PCNT; /* zero length packet */ if (0U == ep->xfer_len) { /* set the transfer length to max packet size */ - dev_ep_xlen |= ep->endp_mps; + devepxlen |= ep->endp_mps; /* set the transfer packet count to 1 */ - dev_ep_xlen |= 1U << 19U; + devepxlen |= 1U << 19U; } else { - if (0U == ep_id) { + + if (0U == ep_num) { /* set the transfer length to max packet size */ - dev_ep_xlen |= ep->endp_mps; + devepxlen |= ep->endp_mps; /* set the transfer packet count to 1 */ - dev_ep_xlen |= 1U << 19U; + devepxlen |= 1U << 19U; } else { /* configure the transfer size and packet count as follows: * pktcnt = N * xfersize = N * maxpacket */ - dev_ep_xlen |= ((ep->xfer_len + ep->endp_mps - 1U) / ep->endp_mps) << 19U; - dev_ep_xlen |= ((dev_ep_xlen & DOEPLEN_PCNT) >> 19U) * ep->endp_mps; + devepxlen |= ((ep->xfer_len + ep->endp_mps - 1U) / ep->endp_mps) << 19U; + devepxlen |= ((devepxlen & DEPLEN_PCNT) >> 19U) * ep->endp_mps; } } - USB_DOEPxLEN((uint16_t)ep_id) = dev_ep_xlen; - - if (1U == pudev->cfg.dma_enable) { - USB_DOEPxDMAADDR((uint16_t)ep_id) = ep->dma_addr; - } + USB_DOEPxLEN((uint16_t)ep_num) = devepxlen; if (USB_EPTYPE_ISOC == ep->endp_type) { if (ep->endp_frame) { - dev_ep_ctlr |= DOEPCTL_SODDFRM; + devepctl |= DEPCTL_SODDFRM; } else { - dev_ep_ctlr |= DOEPCTL_SEVNFRM; + devepctl |= DEPCTL_SEVNFRM; } } /* enable the endpoint and clear the NAK */ - dev_ep_ctlr |= DOEPCTL_EPEN | DOEPCTL_CNAK; + devepctl |= DEPCTL_EPEN | DEPCTL_CNAK; - USB_DOEPxCTL((uint16_t)ep_id) = dev_ep_ctlr; + USB_DOEPxCTL((uint16_t)ep_num) = devepctl; } /*! @@ -264,84 +254,74 @@ void usbd_ep_rx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, void usbd_ep_tx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len) { usb_ep_struct *ep; - uint8_t ep_id = ep_addr & 0x7FU; - __IO uint32_t dev_ep_ctlr = 0U; - __IO uint32_t dev_ep_xlen = 0U; + uint8_t ep_num = ep_addr & 0x7FU; + __IO uint32_t devepctl = 0U; + __IO uint32_t deveplen = 0U; - ep = &pudev->dev.in_ep[ep_id]; + ep = &pudev->dev.in_ep[ep_num]; /* setup and start the transfer */ ep->xfer_buff = pbuf; ep->xfer_len = buf_len; ep->xfer_count = 0U; - if (1U == pudev->cfg.dma_enable) { - ep->dma_addr = (uint32_t)pbuf; - } - - dev_ep_ctlr = USB_DIEPxCTL((uint16_t)ep_id); - dev_ep_xlen = USB_DIEPxLEN((uint16_t)ep_id); + devepctl = USB_DIEPxCTL((uint16_t)ep_num); + deveplen = USB_DIEPxLEN((uint16_t)ep_num); /* clear transfer length to 0 */ - dev_ep_xlen &= ~DIEPLEN_TLEN; + deveplen &= ~DEPLEN_TLEN; /* clear transfer packet to 0 */ - dev_ep_xlen &= ~DIEPLEN_PCNT; + deveplen &= ~DEPLEN_PCNT; /* zero length packet */ if (0U == ep->xfer_len) { /* set transfer packet count to 1 */ - dev_ep_xlen |= 1U << 19U; + deveplen |= 1U << 19U; } else { - if (0U == ep_id) { + if (0U == ep_num) { if (ep->xfer_len > ep->endp_mps) { ep->xfer_len = ep->endp_mps; } - dev_ep_xlen |= 1U << 19U; + deveplen |= 1U << 19U; } else { - dev_ep_xlen |= ((ep->xfer_len - 1U + ep->endp_mps) / ep->endp_mps) << 19U; + deveplen |= ((ep->xfer_len - 1U + ep->endp_mps) / ep->endp_mps) << 19U; } /* configure the transfer size and packet count as follows: * xfersize = N * maxpacket + short_packet * pktcnt = N + (short_packet exist ? 1 : 0) */ - dev_ep_xlen |= ep->xfer_len; + deveplen |= ep->xfer_len; if (USB_EPTYPE_ISOC == ep->endp_type) { - dev_ep_xlen |= DIEPLEN_MCNT & (1U << 29U); + deveplen |= DIEPLEN_MCNT & (1U << 29U); } } - USB_DIEPxLEN((uint16_t)ep_id) = dev_ep_xlen; + USB_DIEPxLEN((uint16_t)ep_num) = deveplen; if (USB_EPTYPE_ISOC == ep->endp_type) { if (0U == (((USB_DSTAT & DSTAT_FNRSOF) >> 8U) & 0x1U)) { - dev_ep_ctlr |= DIEPCTL_SODDFRM; + devepctl |= DEPCTL_SODDFRM; } else { - dev_ep_ctlr |= DIEPCTL_SEVNFRM; + devepctl |= DEPCTL_SEVNFRM; } } - if (1U == pudev->cfg.dma_enable) { - USB_DIEPxDMAADDR((uint16_t)ep_id) = ep->dma_addr; - } - /* enable the endpoint and clear the NAK */ - dev_ep_ctlr |= DIEPCTL_EPEN | DIEPCTL_CNAK; + devepctl |= DEPCTL_EPEN | DEPCTL_CNAK; - USB_DIEPxCTL((uint16_t)ep_id) = dev_ep_ctlr; + USB_DIEPxCTL((uint16_t)ep_num) = devepctl; - if (0U == pudev->cfg.dma_enable) { - if (USB_EPTYPE_ISOC != ep->endp_type) { - /* enable the Tx FIFO empty interrupt for this endpoint */ - if (ep->xfer_len > 0U) { - USB_DIEPFEINTEN |= 1U << ep_id; - } - } else { - usb_fifo_write(ep->xfer_buff, ep_id, (uint16_t)ep->xfer_len); + if (USB_EPTYPE_ISOC != ep->endp_type) { + /* enable the Tx FIFO empty interrupt for this endpoint */ + if (ep->xfer_len > 0U) { + USB_DIEPFEINTEN |= 1U << ep_num; } + } else { + usb_fifo_write(ep->xfer_buff, ep_num, (uint16_t)ep->xfer_len); } } @@ -428,24 +408,24 @@ usbd_status_enum usbd_ctlstatus_rx (usb_core_handle_struct *pudev) */ void usbd_ep_stall (usb_core_handle_struct *pudev, uint8_t ep_addr) { - uint8_t ep_id = ep_addr & 0x7FU; - __IO uint32_t dev_ep_ctlr = 0U; + uint8_t ep_num = ep_addr & 0x7FU; + __IO uint32_t devepctl = 0U; if (ep_addr >> 7U) { - dev_ep_ctlr = USB_DIEPxCTL((uint16_t)ep_id); + devepctl = USB_DIEPxCTL((uint16_t)ep_num); /* set the endpoint disable bit */ - if (dev_ep_ctlr & DIEPCTL_EPEN) { - dev_ep_ctlr |= DIEPCTL_EPD; + if (devepctl & DEPCTL_EPEN) { + devepctl |= DEPCTL_EPD; } /* set the endpoint stall bit */ - dev_ep_ctlr |= DIEPCTL_STALL; + devepctl |= DEPCTL_STALL; - USB_DIEPxCTL((uint16_t)ep_id) = dev_ep_ctlr; + USB_DIEPxCTL((uint16_t)ep_num) = devepctl; } else { /* set the endpoint stall bit */ - USB_DOEPxCTL((uint16_t)ep_id) |= DOEPCTL_STALL; + USB_DOEPxCTL((uint16_t)ep_num) |= DEPCTL_STALL; } } @@ -459,35 +439,35 @@ void usbd_ep_stall (usb_core_handle_struct *pudev, uint8_t ep_addr) void usbd_ep_clear_stall (usb_core_handle_struct *pudev, uint8_t ep_addr) { usb_ep_struct *ep; - uint8_t ep_id = ep_addr & 0x7FU; - __IO uint32_t dev_ep_ctlr = 0U; + uint8_t ep_num = ep_addr & 0x7FU; + __IO uint32_t devepctl = 0U; if(ep_addr >> 7){ - ep = &pudev->dev.in_ep[ep_id]; + ep = &pudev->dev.in_ep[ep_num]; - dev_ep_ctlr = USB_DIEPxCTL((uint16_t)ep_id); + devepctl = USB_DIEPxCTL((uint16_t)ep_num); /* clear the IN endpoint stall bits */ - dev_ep_ctlr &= ~DIEPCTL_STALL; + devepctl &= ~DEPCTL_STALL; if ((USB_EPTYPE_INTR == ep->endp_type) || (USB_EPTYPE_BULK == ep->endp_type)) { - dev_ep_ctlr |= DIEPCTL_SEVNFRM; + devepctl |= DEPCTL_SEVNFRM; } - USB_DIEPxCTL((uint16_t)ep_id) = dev_ep_ctlr; + USB_DIEPxCTL((uint16_t)ep_num) = devepctl; } else { - ep = &pudev->dev.out_ep[ep_id]; + ep = &pudev->dev.out_ep[ep_num]; - dev_ep_ctlr = USB_DOEPxCTL((uint16_t)ep_id); + devepctl = USB_DOEPxCTL((uint16_t)ep_num); /* clear the OUT endpoint stall bits */ - dev_ep_ctlr &= ~DOEPCTL_STALL; + devepctl &= ~DEPCTL_STALL; if ((USB_EPTYPE_INTR == ep->endp_type) || (USB_EPTYPE_BULK == ep->endp_type)) { - dev_ep_ctlr |= DOEPCTL_SEVNFRM; + devepctl |= DEPCTL_SEVNFRM; } - USB_DOEPxCTL((uint16_t)ep_id) = dev_ep_ctlr; + USB_DOEPxCTL((uint16_t)ep_num) = devepctl; } } @@ -510,11 +490,11 @@ void usbd_ep_fifo_flush (usb_core_handle_struct *pudev, uint8_t ep_addr) /*! \brief get the received data length \param[in] pudev: pointer to usb device instance - \param[in] ep_id: endpoint identifier which is in (0..3) + \param[in] ep_num: endpoint identifier which is in (0..3) \param[out] none \retval received data length */ -uint16_t usbd_rxcount_get (usb_core_handle_struct *pudev, uint8_t ep_id) +uint16_t usbd_rxcount_get (usb_core_handle_struct *pudev, uint8_t ep_num) { - return (uint16_t)pudev->dev.out_ep[ep_id].xfer_count; + return (uint16_t)pudev->dev.out_ep[ep_num].xfer_count; } diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbd_int.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbd_int.c similarity index 77% rename from bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbd_int.c rename to bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbd_int.c index 01338e2e9b..970cf812ad 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbd_int.c +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbd_int.c @@ -1,12 +1,36 @@ /*! - \file usbd_int.c + \file usbd_int.c \brief USB device mode interrupt routines + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2019, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "usbd_int.h" @@ -32,7 +56,7 @@ static uint32_t usbd_emptytxfifo_write (usb_core_handle_struct *pudev, ui static uint32_t usbd_intf_otg (usb_core_handle_struct *pudev); static uint32_t usbd_intf_sessionrequest (usb_core_handle_struct *pudev); -#endif +#endif /* VBUS_SENSING_ENABLED */ static usb_speed_enum USB_SPEED[4] = { [DSTAT_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ] = USB_SPEED_HIGH, @@ -48,103 +72,6 @@ static const uint8_t EP0_MAXLEN[4] = { [DSTAT_ENUMSPD_LS_PHY_6MHZ] = EP0MPL_8 }; -#ifdef USBHS_DEDICATED_EP1_ENABLED - -/*! - \brief USB dedicated OUT endpoint 1 interrupt service routine handler - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -uint32_t USBD_EP1OUT_ISR_Handler (usb_core_handle_struct *pudev) -{ - uint32_t out_endp_int = 0; - uint32_t out_endp_size = 0; - - out_endp_int = USB_DOEPxINTF(1); - out_endp_int &= USB_DOEP1INTEN; - - /* transfer complete */ - if (out_endp_int & DOEPINTF_TF) { - /* clear the interrupt bit */ - USB_DOEPxINTF(1) = DOEPINTF_TF; - - if (1U == pudev->cfg.dma_enable) { - out_endp_size = USB_DOEPxLEN(1); - - /* handle more than one single MPS size packet */ - pudev->dev.out_ep[1].xfer_count = pudev->dev.out_ep[1].endp_mps - \ - (out_endp_size & DOEPLEN_TLEN); - } - - /* inform upper layer: data ready */ - - /* receive complete */ - usbd_out_transaction(pudev, 1); - } - - /* endpoint disable interrupt */ - if (out_endp_int & DOEPINTF_EPDIS) { - /* clear the interrupt bit */ - USB_DOEPxINTF(1) = DOEPINTF_EPDIS; - } - - return 1; -} - -/*! - \brief USB dedicated IN endpoint 1 interrupt service routine handler - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -uint32_t USBD_EP1IN_ISR_Handler (usb_core_handle_struct *pudev) -{ - uint32_t fifoemptymask = 0, mask = 0; - uint32_t in_endp_int = 0; - - mask = USB_DIEP1INTEN; - mask |= ((USB_DIEPFEINTEN >> 1) & 0x01) << 7; - in_endp_int = USB_DIEPxINTF(1) & mask; - - if (in_endp_int & DIEPINTF_TF) { - fifoemptymask = 0x01 << 1; - USB_DIEPFEINTEN &= ~fifoemptymask; - - USB_DIEPxINTF(1) = DIEPINTF_TF; - - /* transmit complete */ - usbd_in_transaction(pudev , 1); - } - - if (in_endp_int & DIEPINTF_EPDIS) { - USB_DIEPxINTF(1) = DIEPINTF_EPDIS; - } - - if (in_endp_int & DIEPINTF_CITO) { - USB_DIEPxINTF(1) = DIEPINTF_CITO; - } - - if (in_endp_int & DIEPINTF_EPTXFUD) { - USB_DIEPxINTF(1) = DIEPINTF_EPTXFUD; - } - - if (in_endp_int & DIEPINTF_IEPNE) { - USB_DIEPxINTF(1) = DIEPINTF_IEPNE; - } - - if (in_endp_int & DIEPINTF_TXFE) { - usbd_emptytxfifo_write(pudev, 1); - - USB_DIEPxINTF(1) = DIEPINTF_IEPNE; - } - - return 1; -} - -#endif - - /*! \brief USB device-mode interrupts global service routine handler \param[in] pudev: pointer to usb device instance @@ -212,7 +139,7 @@ uint32_t usbd_isr (usb_core_handle_struct *pudev) } /* enumeration has been finished interrupt */ - if (int_status & GINTF_ENUMFIF) { + if (int_status & GINTF_ENUMF) { retval |= usbd_intf_enumfinish(pudev); } @@ -267,22 +194,8 @@ static uint32_t usbd_intf_outep (usb_core_handle_struct *pudev) if (out_endp_intr & DOEPINTF_TF) { USB_DOEPxINTF((uint16_t)endp_num) = DOEPINTF_TF; - if (1U == pudev->cfg.dma_enable) { - uint32_t xfer_size = USB_DOEPxLEN((uint16_t)endp_num) & DOEPLEN_TLEN; - - pudev->dev.out_ep[endp_num].xfer_count = pudev->dev.out_ep[endp_num].endp_mps - \ - xfer_size; - } - /* data receive is completed */ usbd_out_transaction(pudev, endp_num); - - if (1U == pudev->cfg.dma_enable) { - if ((0U == endp_num) && (USB_CTRL_STATUS_OUT == pudev->dev.ctl_status)) { - /* prepare to receive more setup packets */ - usb_ep0_startout(pudev); - } - } } /* endpoint disable interrupt */ @@ -339,13 +252,6 @@ static uint32_t usbd_intf_inep(usb_core_handle_struct *pudev) /* data transmittion is completed */ usbd_in_transaction(pudev, endp_num); - - if (1U == pudev->cfg.dma_enable) { - if ((0U == endp_num) && (USB_CTRL_STATUS_IN == pudev->dev.ctl_status)) { - /* prepare to receive more setup packets */ - usb_ep0_startout(pudev); - } - } } if (in_endp_intr & DIEPINTF_CITO) { @@ -441,7 +347,9 @@ static uint32_t usbd_intf_resume (usb_core_handle_struct *pudev) */ static uint32_t usbd_intf_sof(usb_core_handle_struct *pudev) { -// USBD_DCD_INT_fops->SOF(pudev); + if (NULL != usbd_int_fops) { + usbd_int_fops->SOF(pudev); + } USB_GINTF = GINTF_SOF; @@ -458,7 +366,7 @@ static uint32_t usbd_intf_rxfifo (usb_core_handle_struct *pudev) { usb_ep_struct *ep; uint8_t data_pid = 0U, endp_num = 0U; - uint32_t bcount = 0U; + uint32_t bcount = 0U, packet_num = 0U; /* get the status from the top of the fifo (must be read to a variable) */ __IO uint32_t rx_status = USB_GRSTATP; @@ -466,21 +374,26 @@ static uint32_t usbd_intf_rxfifo (usb_core_handle_struct *pudev) /* disable the rx fifo non-empty interrupt */ USB_GINTEN &= ~GINTEN_RXFNEIE; - endp_num = (uint8_t)(rx_status & GRSTATP_EPNUM); - bcount = (rx_status & GRSTATP_BCOUNT) >> 4U; - data_pid = (uint8_t)((rx_status & GRSTATP_DPID) >> 15U); + endp_num = (uint8_t)(rx_status & GRSTATRP_EPNUM); + bcount = (rx_status & GRSTATRP_BCOUNT) >> 4U; + data_pid = (uint8_t)((rx_status & GRSTATRP_DPID) >> 15U); - if ((endp_num == 1) && ((*(uint32_t *)0x40040B30 & 0x1FF80000) == 0)) { - *(uint32_t *)0x40040B20 = ((*(uint32_t *)0x40040B20 | 0x08000000) & 0x3FFFFFFF); + /* ensure no-DMA mode can work */ + packet_num = USB_DOEPxLEN((uint16_t)endp_num) & DEPLEN_PCNT; + if ((1U == endp_num) && (0U == packet_num)) { + uint32_t devepctl = USB_DOEPxCTL((uint16_t)endp_num); + + devepctl |= DEPCTL_SNAK; + devepctl &= ~DEPCTL_EPEN; + devepctl &= ~DEPCTL_EPD; + + USB_DOEPxCTL((uint16_t)endp_num) = devepctl; } ep = &pudev->dev.out_ep[endp_num]; - switch ((rx_status & GRSTATP_RPCKST) >> 17U) { + switch ((rx_status & GRSTATRP_RPCKST) >> 17U) { case RXSTAT_GOUT_NAK: - if(0U != bcount) { - return 0U; - } break; case RXSTAT_DATA_UPDT: if (bcount > 0U) { @@ -490,14 +403,8 @@ static uint32_t usbd_intf_rxfifo (usb_core_handle_struct *pudev) } break; case RXSTAT_XFER_COMP: - if (0U != bcount) { - return 0U; - } break; case RXSTAT_SETUP_COMP: - if(0U != bcount) { - return 0U; - } break; case RXSTAT_SETUP_UPDT: if ((0U == endp_num) && (8U == bcount) && (DPID_DATA0 == data_pid)) { @@ -540,7 +447,7 @@ static uint32_t usbd_intf_reset(usb_core_handle_struct *pudev) } /* clear all pending device endpoint interrupts */ - USB_DAEPINT = 0xFFFFFFFF; + USB_DAEPINT = 0xFFFFFFFFU; /* enable endpoint 0 interrupts */ USB_DAEPINTEN &= ~DAEPINTEN_OEPIE; @@ -550,17 +457,9 @@ static uint32_t usbd_intf_reset(usb_core_handle_struct *pudev) /* enable out endpoint interrupts */ USB_DOEPINTEN = DOEPINTEN_STPFEN | DOEPINTEN_TFEN | DOEPINTEN_EPDISEN; -#ifdef USBHS_DEDICATED_EP1_ENABLED - USB_DOEP1INTEN = DOEPINTEN_STPFEN | DOEPINTEN_TFEN | DOEPINTEN_EPDISEN; -#endif - /* enable in endpoint interrupts */ USB_DIEPINTEN = DIEPINTEN_TFEN | DIEPINTEN_CITOEN | DIEPINTEN_EPDISEN; -#ifdef USBHS_DEDICATED_EP1_ENABLED - USB_DIEP1INTEN = DIEPINTEN_TFEN | DIEPINTEN_CITOEN | DIEPINTEN_EPDISEN; -#endif - /* reset device address */ USB_DCFG &= ~DCFG_DAR; USB_DCFG |= 0U << 4U; @@ -574,14 +473,14 @@ static uint32_t usbd_intf_reset(usb_core_handle_struct *pudev) /* open EP0 IN */ ep = &pudev->dev.in_ep[0]; - USB_DIEPxCTL(0U) &= ~DIEP0CTL_MPL; - USB_DIEPxCTL(0U) &= ~DIEPCTL_EPTYPE; + USB_DIEPxCTL(0U) &= ~DEP0CTL_MPL; + USB_DIEPxCTL(0U) &= ~DEPCTL_EPTYPE; USB_DIEPxCTL(0U) &= ~DIEPCTL_TXFNUM; - if (!(USB_DIEPxCTL(0U) & DIEPCTL_EPACT)) { + if (!(USB_DIEPxCTL(0U) & DEP0CTL_EPACT)) { USB_DIEPxCTL(0U) |= USB_MAX_EP0_SIZE; USB_DIEPxCTL(0U) |= (USB_EPTYPE_CTRL << 18U); - USB_DIEPxCTL(0U) |= DIEP0CTL_EPACT; + USB_DIEPxCTL(0U) |= DEP0CTL_EPACT; } ep->endp_mps = USB_MAX_EP0_SIZE; @@ -590,13 +489,13 @@ static uint32_t usbd_intf_reset(usb_core_handle_struct *pudev) /* open EP0 OUT */ ep = &pudev->dev.out_ep[0]; - USB_DOEPxCTL(0U) &= ~DOEP0CTL_MPL; - USB_DOEPxCTL(0U) &= ~DOEPCTL_EPTYPE; + USB_DOEPxCTL(0U) &= ~DEP0CTL_MPL; + USB_DOEPxCTL(0U) &= ~DEPCTL_EPTYPE; - if (!(USB_DOEPxCTL(0U) & DOEPCTL_EPACT)) { + if (!(USB_DOEPxCTL(0U) & DEP0CTL_EPACT)) { USB_DOEPxCTL(0U) |= USB_MAX_EP0_SIZE; USB_DOEPxCTL(0U) |= (USB_EPTYPE_CTRL << 18U); - USB_DOEPxCTL(0U) |= DOEP0CTL_EPACT; + USB_DOEPxCTL(0U) |= DEP0CTL_EPACT; } ep->endp_mps = USB_MAX_EP0_SIZE; @@ -640,7 +539,7 @@ static uint32_t usbd_intf_enumfinish(usb_core_handle_struct *pudev) } /* clear interrupt */ - USB_GINTF = GINTF_ENUMFIF; + USB_GINTF = GINTF_ENUMF; return 1U; } @@ -686,7 +585,7 @@ static uint32_t usbd_intf_isooutincomplete(usb_core_handle_struct *pudev) */ static uint32_t usbd_emptytxfifo_write(usb_core_handle_struct *pudev, uint8_t ep_num) { - uint32_t len = 0U, word_len = 0U; + uint32_t len = 0U, word_len = 0U, fifo_empty_mask = 0U; usb_ep_struct *ep; ep = &pudev->dev.in_ep[ep_num]; @@ -713,6 +612,11 @@ static uint32_t usbd_emptytxfifo_write(usb_core_handle_struct *pudev, uint8_t ep ep->xfer_buff += len; ep->xfer_count += len; + + if(ep->xfer_len == ep->xfer_count) { + fifo_empty_mask = 0x1U << ep_num; + USB_DIEPFEINTEN &= ~fifo_empty_mask; + } } return 1U; diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbd_std.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbd_std.c similarity index 89% rename from bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbd_std.c rename to bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbd_std.c index 0ae93e4472..9bdba6a2c0 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbd_std.c +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbd_std.c @@ -1,12 +1,36 @@ /*! - \file usbd_std.c + \file usbd_std.c \brief USB 2.0 standard handler driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2019, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "usbd_std.h" @@ -111,25 +135,20 @@ usbd_status_enum usbd_out_transaction (usb_core_handle_struct *pudev, uint8_t en if (pudev->dev.remain_len > ep->endp_mps) { pudev->dev.remain_len -= ep->endp_mps; - if (1U == pudev->cfg.dma_enable) { - /* update buffer location */ - ep->xfer_buff += ep->endp_mps; - } - usbd_ep_rx (pudev, 0U, ep->xfer_buff, (uint16_t)USB_MIN(pudev->dev.remain_len, ep->endp_mps)); } else { if (USB_STATUS_CONFIGURED == pudev->dev.status) { - pudev->dev.class_data_handler(pudev, USBD_RX, 0U); + pudev->dev.class_data_handler(pudev, USB_RX, 0U); } usbd_ctlstatus_tx(pudev); } } } else if (USB_STATUS_CONFIGURED == pudev->dev.status) { - pudev->dev.class_data_handler(pudev, USBD_RX, endp_num); + pudev->dev.class_data_handler(pudev, USB_RX, endp_num); } else { /* no operation */ } @@ -155,12 +174,9 @@ usbd_status_enum usbd_in_transaction (usb_core_handle_struct *pudev, uint8_t end if (pudev->dev.remain_len > ep->endp_mps) { pudev->dev.remain_len -= ep->endp_mps; - if (1U == pudev->cfg.dma_enable) { - /* update buffer location */ - ep->xfer_buff += ep->endp_mps; - } - usbd_ep_tx (pudev, 0U, ep->xfer_buff, pudev->dev.remain_len); + + usbd_ep_rx (pudev, 0U, NULL, 0U); } else { /* last packet is MPS multiple, so send ZLP packet */ if ((pudev->dev.sum_len % ep->endp_mps == 0U) && @@ -168,9 +184,11 @@ usbd_status_enum usbd_in_transaction (usb_core_handle_struct *pudev, uint8_t end (pudev->dev.sum_len < pudev->dev.ctl_len)) { usbd_ep_tx (pudev, 0U, NULL, 0U); pudev->dev.ctl_len = 0U; + + usbd_ep_rx (pudev, 0U, NULL, 0U); } else { if (USB_STATUS_CONFIGURED == pudev->dev.status) { - pudev->dev.class_data_handler(pudev, USBD_TX, 0U); + pudev->dev.class_data_handler(pudev, USB_TX, 0U); } usbd_ctlstatus_rx(pudev); @@ -178,7 +196,7 @@ usbd_status_enum usbd_in_transaction (usb_core_handle_struct *pudev, uint8_t end } } } else if (USB_STATUS_CONFIGURED == pudev->dev.status) { - pudev->dev.class_data_handler(pudev, USBD_TX, endp_num); + pudev->dev.class_data_handler(pudev, USB_TX, endp_num); } else { /* no operation */ } @@ -509,19 +527,20 @@ static void usbd_setaddress (usb_core_handle_struct *pudev, usb_device_req_stru static void usbd_getdescriptor (usb_core_handle_struct *pudev, usb_device_req_struct *req) { if (USB_REQTYPE_DEVICE == (req->bmRequestType & USB_REQTYPE_MASK)) { - uint8_t desc_index = (uint8_t)(req->wValue >> 8U); + uint8_t desc_type = (uint8_t)(req->wValue >> 8); + uint8_t desc_index = (uint8_t)(req->wValue) & 0xFFU; - if (desc_index <= 0x03U) { + if ((desc_type <= 0x03U) && (desc_index <= 0x05U)) { uint16_t len; uint8_t *pbuf; /* call corresponding descriptor get function */ - pbuf = standard_descriptor_get[desc_index - 1U](pudev, (uint8_t)(req->wValue) & 0xFFU, &len); + pbuf = standard_descriptor_get[desc_type - 1U](pudev, desc_index, &len); if ((0U != len) && (0U != req->wLength)) { len = USB_MIN(len, req->wLength); - if ((1U == desc_index) && (64U == req->wLength)) { + if ((1U == desc_type) && (64U == req->wLength)) { len = 8U; } diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbh_core.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbh_core.c similarity index 92% rename from bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbh_core.c rename to bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbh_core.c index 1c90b55187..d717e87b21 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbh_core.c +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbh_core.c @@ -1,12 +1,36 @@ /*! \file usbh_core.c \brief this file implements the functions for the core state machine process + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2019, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "usbh_hcs.h" @@ -537,10 +561,10 @@ void scd_table_regist (usbh_state_handle_struct* pustate, */ void scd_begin(usbh_state_handle_struct* pustate, uint8_t table_id) { - uint8_t i = 0, table_num = pustate->usbh_regist_state_table_num; + uint8_t i = 0U, table_num = pustate->usbh_regist_state_table_num; usbh_state_regist_table_struct *cur_state_reg_table; - for (i = 0; i < table_num; i++) { + for (i = 0U; i < table_num; i++) { cur_state_reg_table = &pustate->usbh_regist_state_table[i]; if (table_id == cur_state_reg_table->id) { @@ -579,13 +603,13 @@ usbh_status_enum scd_event_handle (usb_core_handle_struct *pudev, uint8_t event, uint8_t state) { - uint8_t i = 0; + uint8_t i = 0U; ACT_FUN event_act_fun = NULL; state_table_struct *backup_state_t = pustate->usbh_current_state_table; state_table_struct *executive_state_table = pustate->usbh_current_state_table; /* look up the table to find the action function */ - for (i = 0; i < pustate->usbh_current_state_table_size; i++) { + for (i = 0U; i < pustate->usbh_current_state_table_size; i++) { if (state == executive_state_table->cur_state) { if (event == executive_state_table->cur_event) { state = executive_state_table->next_state; diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbh_ctrl.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbh_ctrl.c similarity index 92% rename from bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbh_ctrl.c rename to bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbh_ctrl.c index b61484053e..c40df945f3 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbh_ctrl.c +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbh_ctrl.c @@ -1,13 +1,38 @@ /*! \file usbh_ctrl.c \brief this file implements the functions for the control transmit process + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2019, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ + #include "usbh_core.h" #include "usbh_std.h" #include "usbh_ctrl.h" @@ -69,8 +94,8 @@ state_table_struct ctrl_handle_table[CTRL_HANDLE_TABLE_SIZE] = \retval none */ usbh_status_enum ctrl_state_polling_fun (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - void *pustate) + usbh_host_struct *puhost, + void *pustate) { usbh_status_enum exe_state = USBH_BUSY; usbh_state_handle_struct *p_state; @@ -391,15 +416,6 @@ static void ctrl_status_handle (usb_core_handle_struct *pudev, ctrl_status_wait_flag = 1U; pudev->host.host_channel[puhost->control.hc_out_num].data_tg_out ^= 1U; usbh_xfer (pudev, 0U, puhost->control.hc_out_num, 0U); - - { - uint32_t host_ctlr = 0; - - host_ctlr = USB_HCHxLEN(puhost->control.hc_out_num); - USB_HCHxLEN(puhost->control.hc_out_num) = host_ctlr | 1; - host_ctlr = USB_HCHxCTL(puhost->control.hc_out_num); - USB_HCHxCTL(puhost->control.hc_out_num) = (host_ctlr & 0x3FFFFFFF) | 0x80000000; - } } else { urb_status = hcd_urb_state_get(pudev, puhost->control.hc_out_num); diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbh_hcs.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbh_hcs.c similarity index 72% rename from bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbh_hcs.c rename to bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbh_hcs.c index 035459d195..801cb5069e 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbh_hcs.c +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbh_hcs.c @@ -1,12 +1,36 @@ /*! \file usbh_hcs.c \brief this file implements functions for opening and closing host channels + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2019, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "usbh_hcs.h" @@ -44,10 +68,6 @@ uint8_t usbh_channel_open (usb_core_handle_struct *pudev, puhc->data_tg_in = 0U; puhc->data_tg_out = 0U; - if (HPRT_PRTSPD_HIGH_SPEED == dev_speed) { - puhc->do_ping = 1U; - } - usb_hostchannel_init(pudev, channel_num); return (uint8_t)HC_OK; diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbh_int.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbh_int.c similarity index 89% rename from bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbh_int.c rename to bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbh_int.c index a386d185ed..0d7c8c043a 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbh_int.c +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbh_int.c @@ -1,12 +1,36 @@ /*! \file usbh_int.c \brief USB host mode interrupt handler file + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2019, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.1, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "usb_core.h" @@ -272,8 +296,6 @@ static uint32_t usbh_intf_port (usb_core_handle_struct *pudev) /* for high speed device and others */ port_reset = 1U; } - - } } @@ -360,17 +382,9 @@ static uint32_t usbh_intf_hc_out (usb_core_handle_struct *pudev, uint8_t channel } break; case HC_NAK: - if (URB_PING == puhc->urb_state) { - usb_hostchannel_ping(pudev, channel_num); - } else { - puhc->urb_state = URB_NOTREADY; - } + puhc->urb_state = URB_NOTREADY; break; case HC_NYET: - if (1U == puhc->do_ping) { - usb_hostchannel_ping(pudev, channel_num); - puhc->urb_state = URB_PING; - } break; case HC_STALL: puhc->urb_state = URB_STALL; @@ -441,11 +455,6 @@ static uint32_t usbh_intf_hc_in (usb_core_handle_struct *pudev, uint8_t channel_ usb_hostchannel_halt(pudev, channel_num); USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_REQOVR; } else if (channle_intf & HCHINTF_TF) { - if (pudev->cfg.dma_enable == 1U) { - uint32_t xfer_size = USB_HCHxLEN((uint16_t)channel_num) & HCHLEN_TLEN; - puhc->xfer_count = puhc->xfer_len - xfer_size; - } - puhc->status = HC_XF; puhc->err_count = 0U; USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_TF; @@ -531,12 +540,12 @@ static uint32_t usbh_intf_rxfifo_noempty (usb_core_handle_struct *pudev) USB_GINTEN &= ~GINTF_RXFNEIF; rx_status = USB_GRSTATP; - channel_num = (uint8_t)(rx_status & GRSTATR_CNUM); + channel_num = (uint8_t)(rx_status & GRSTATRP_CNUM); puhc = &pudev->host.host_channel[channel_num]; - switch ((rx_status & GRSTATR_RPCKST) >> 17) { + switch ((rx_status & GRSTATRP_RPCKST) >> 17) { case GRSTATR_RPCKST_IN: - count = (rx_status & GRSTATR_BCOUNT) >> 4; + count = (rx_status & GRSTATRP_BCOUNT) >> 4; /* read the data into the host buffer. */ if ((count > 0U) && (puhc->xfer_buff != (void *)0)) { @@ -556,8 +565,17 @@ static uint32_t usbh_intf_rxfifo_noempty (usb_core_handle_struct *pudev) } break; case GRSTATR_RPCKST_IN_XFER_COMP: + break; case GRSTATR_RPCKST_DATA_TOGGLE_ERR: + count = (rx_status & GRSTATRP_BCOUNT) >> 4; + + while (count > 0) { + rx_status = USB_GRSTATP; + count--; + } + break; case GRSTATR_RPCKST_CH_HALTED: + break; default: break; } diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbh_std.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbh_std.c similarity index 94% rename from bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbh_std.c rename to bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbh_std.c index 57f9e996a4..04adcfabc6 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbh_std.c +++ b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbh_std.c @@ -1,12 +1,36 @@ /*! \file usbh_std.c \brief USB 2.0 standard function definition + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2019, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.1, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "usbh_core.h" @@ -83,7 +107,7 @@ usbh_status_enum enum_state_polling_fun (usb_core_handle_struct *pudev, usbh_hos /* start the enumeration state handle */ scd_begin(p_state,ENUM_FSM_ID); - if (0U == p_state->usbh_current_state_stack_top) { + if (0 == p_state->usbh_current_state_stack_top) { enum_state_handle[p_state->usbh_current_state](pudev, puhost, p_state); } else { enum_state_handle[p_state->stack[1].state](pudev, puhost, p_state); @@ -404,7 +428,7 @@ static void enum_get_product_string_desc_handle (usb_core_handle_struct *pudev, if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { usbh_string_desc_parse(pudev->host.rx_buffer, local_buffer, 0xffU); - /* User callback for Product string */ + /* user callback for product string */ puhost->usr_cb->product_string(local_buffer); scd_event_handle(pudev, @@ -413,7 +437,6 @@ static void enum_get_product_string_desc_handle (usb_core_handle_struct *pudev, ENUN_EVENT_GET_SERIALNUM_STRING_DESC, pustate->usbh_current_state); } - } else { puhost->usr_cb->product_string("N/A"); scd_event_handle(pudev, diff --git a/bsp/gd32350r-eval/Libraries/SConscript b/bsp/gd32350r-eval/Libraries/SConscript new file mode 100644 index 0000000000..dad0c6c89e --- /dev/null +++ b/bsp/gd32350r-eval/Libraries/SConscript @@ -0,0 +1,33 @@ +import rtconfig +from building import * + +# get current directory +cwd = GetCurrentDir() + +# The set of source files associated with this SConscript file. + +src = Glob('GD32F3x0_standard_peripheral/Source/*.c') +src += [cwd + '/CMSIS/GD/GD32F3x0/Source/system_gd32f3x0.c'] + +#add for startup script +if rtconfig.CROSS_TOOL == 'gcc': + src += [cwd + '/CMSIS/GD/GD32F3x0/Source/GCC/startup_gd32f3x0.S'] +elif rtconfig.CROSS_TOOL == 'keil': + src += [cwd + '/CMSIS/GD/GD32F3x0/Source/ARM/startup_gd32f3x0.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src += [cwd + '/CMSIS/GD/GD32F3x0/Source/IAR/startup_gd32f3x0.s'] + +path = [ + cwd + '/CMSIS/GD/GD32F3x0/Include', + cwd + '/CMSIS', + cwd + '/GD32F3x0_standard_peripheral/Include',] + +if GetDepend(['RT_USING_BSP_USB']): + path += [cwd + '/GD32F4xx_usb_driver/Include'] + src += [cwd + '/GD32F4xx_usb_driver/Source'] + +CPPDEFINES = ['USE_STDPERIPH_DRIVER', 'GD32F350'] + +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/gd32350r-eval/README.md b/bsp/gd32350r-eval/README.md new file mode 100644 index 0000000000..8f2a434511 --- /dev/null +++ b/bsp/gd32350r-eval/README.md @@ -0,0 +1,55 @@ +# GD32350R-EVAL + +## 简介 + +GD32350R-EVAL是-兆易创新推出的一款GD32F350系列的评估板，板载资源主要如下： + +| 硬件 | 描述 | +| --------- | ------------- | +| 芯片型号 | GD32F350R8T6 | +| CPU | ARM Cortex M4 | +| 主频 | 108M | +| 片内SRAM | 16K | +| 片内FLASH | 64K | + +## 编译说明 + +GD32450Z-EVAL板级包支持MDK5开发环境以下是具体版本信息： + +| IDE/编译器 | 已测试版本 | +| ---------- | ---------- | +| MDK5 | MDK524a | + +## 烧写及执行 + +供电方式：开发板使用 Mini USB 接口或者 DC-005 连接器提供 5V 电源。 + +下载程序：下载程序到开发板需要一套 JLink 或者使用 GD-Link 工具。 + +串口连接：使用串口线连接到COM1(UART0)，或者使用USB转TTL模块连接PA9(MCU TX)和PA10(MCU RX)。 + +### 运行结果 + +如果编译 & 烧写无误，当复位设备后，会在串口上看到RT-Thread的启动logo信息： + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.4 build Jun 21 2021 + 2006 - 2021 Copyright by rt-thread team + + + +msh > +``` +## 驱动支持情况及计划 + +| 驱动 | 支持情况 | 备注 | +| --------- | -------- | :------------------------: | +| UART | 支持 | UART0~1 | +| GPIO | 支持 | ALL | + +## 联系人信息 + +维护人：[RiceChen](https://gitee.com/RiceChen0) +邮箱：980307037@qq.com diff --git a/bsp/gd32350r-eval/SConscript b/bsp/gd32350r-eval/SConscript new file mode 100644 index 0000000000..fe0ae941ae --- /dev/null +++ b/bsp/gd32350r-eval/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +Import('RTT_ROOT') + +cwd = str(Dir('#')) +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/gd32350r-eval/SConstruct b/bsp/gd32350r-eval/SConstruct new file mode 100644 index 0000000000..63793d5195 --- /dev/null +++ b/bsp/gd32350r-eval/SConstruct @@ -0,0 +1,40 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread-gd32f3x0.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/gd32350r-eval/applications/SConscript b/bsp/gd32350r-eval/applications/SConscript new file mode 100644 index 0000000000..01eb940dfb --- /dev/null +++ b/bsp/gd32350r-eval/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = os.path.join(str(Dir('#')), 'applications') +src = Glob('*.c') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/gd32350r-eval/applications/main.c b/bsp/gd32350r-eval/applications/main.c new file mode 100644 index 0000000000..3aa60cf2b2 --- /dev/null +++ b/bsp/gd32350r-eval/applications/main.c @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-06-21 RiceChen the first version + */ + +#include +#include +#include "rtdevice.h" + +int main(void) +{ + rt_kprintf("\n\n\n"); + + return 0; +} diff --git a/bsp/gd32350r-eval/drivers/SConscript b/bsp/gd32350r-eval/drivers/SConscript new file mode 100644 index 0000000000..f40845bdf7 --- /dev/null +++ b/bsp/gd32350r-eval/drivers/SConscript @@ -0,0 +1,24 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = os.path.join(str(Dir('#')), 'drivers') + +# add the general drivers. +src = Split(""" +board.c +""") + +CPPPATH = [cwd] + +# add pin drivers. +if GetDepend('RT_USING_PIN'): + src += ['drv_gpio.c'] + +# add uart drivers. +if GetDepend('RT_USING_SERIAL'): + src += ['drv_usart.c'] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/gd32350r-eval/drivers/board.c b/bsp/gd32350r-eval/drivers/board.c new file mode 100644 index 0000000000..93d3f93bd5 --- /dev/null +++ b/bsp/gd32350r-eval/drivers/board.c @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-01-05 Bernard first implementation + */ +#include +#include +#include + +#include +#include +#include + +/** + * @brief This function is executed in case of error occurrence. + * @param None + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler */ + /* User can add his own implementation to report the HAL error return state */ + while (1) + { + } + /* USER CODE END Error_Handler */ +} + +/** System Clock Configuration +*/ +void SystemClock_Config(void) +{ + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + NVIC_SetPriority(SysTick_IRQn, 0); +} + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +char heap[1024 *16]; +/** + * This function will initial GD32 board. + */ +void rt_hw_board_init() +{ + /* NVIC Configuration */ +#define NVIC_VTOR_MASK 0x3FFFFF80 +#ifdef VECT_TAB_RAM + /* Set the Vector Table base location at 0x10000000 */ + SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK); +#else /* VECT_TAB_FLASH */ + /* Set the Vector Table base location at 0x08000000 */ + SCB->VTOR = (0x08000000 & NVIC_VTOR_MASK); +#endif + + SystemClock_Config(); + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +#ifdef BSP_USING_SDRAM + rt_system_heap_init((void *)EXT_SDRAM_BEGIN, (void *)EXT_SDRAM_END); +#else + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif +} + +/*@}*/ diff --git a/bsp/gd32350r-eval/drivers/board.h b/bsp/gd32350r-eval/drivers/board.h new file mode 100644 index 0000000000..05d3c7e972 --- /dev/null +++ b/bsp/gd32350r-eval/drivers/board.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-09-22 Bernard add board.h to this bsp + */ + +// <<< Use Configuration Wizard in Context Menu >>> +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include + +#define EXT_SDRAM_BEGIN (0xC0000000U) /* the begining address of external SDRAM */ +#define EXT_SDRAM_END (EXT_SDRAM_BEGIN + (32U * 1024 * 1024)) /* the end address of external SDRAM */ + +// Internal SRAM memory size[Kbytes] <8-64> +// Default: 64 +#ifdef __ICCARM__ +// Use *.icf ram symbal, to avoid hardcode. +extern char __ICFEDIT_region_RAM_end__; +#define GD32_SRAM_END &__ICFEDIT_region_RAM_end__ +#else +#define GD32_SRAM_SIZE 16 +#define GD32_SRAM_END (0x20000000 + GD32_SRAM_SIZE * 1024) +#endif + +#ifdef __CC_ARM +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) +#else +extern int __bss_end; +#define HEAP_BEGIN (&__bss_end) +#endif + +#define HEAP_END GD32_SRAM_END + +#endif + +//*** <<< end of configuration section >>> *** diff --git a/bsp/gd32350r-eval/drivers/drv_gpio.c b/bsp/gd32350r-eval/drivers/drv_gpio.c new file mode 100644 index 0000000000..7d15638d5f --- /dev/null +++ b/bsp/gd32350r-eval/drivers/drv_gpio.c @@ -0,0 +1,490 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-06-20 RiceChen the first version + */ + +#include +#include + +#ifdef RT_USING_PIN + +#include "drv_gpio.h" + +static const struct pin_index pins[] = +{ + GD32_PIN(1, A, 0), + GD32_PIN(2, A, 1), + GD32_PIN(3, A, 2), + GD32_PIN(4, A, 3), + GD32_PIN(5, A, 4), + GD32_PIN(6, A, 5), + GD32_PIN(7, A, 6), + GD32_PIN(8, A, 7), + GD32_PIN(9, A, 8), + GD32_PIN(10, A, 9), + GD32_PIN(11, A, 10), + GD32_PIN(12, A, 11), + GD32_PIN(13, A, 12), + GD32_PIN(14, A, 13), + GD32_PIN(15, A, 14), + GD32_PIN(16, A, 15), + GD32_PIN(17, B, 0), + GD32_PIN(18, B, 1), + GD32_PIN(19, B, 2), + GD32_PIN(20, B, 3), + GD32_PIN(21, B, 4), + GD32_PIN(22, B, 5), + GD32_PIN(23, B, 6), + GD32_PIN(24, B, 7), + GD32_PIN(25, B, 8), + GD32_PIN(26, B, 9), + GD32_PIN(27, B, 10), + GD32_PIN(28, B, 11), + GD32_PIN(29, B, 12), + GD32_PIN(30, B, 13), + GD32_PIN(31, B, 14), + GD32_PIN(32, B, 15), + GD32_PIN(33, C, 0), + GD32_PIN(34, C, 1), + GD32_PIN(35, C, 2), + GD32_PIN(36, C, 3), + GD32_PIN(37, C, 4), + GD32_PIN(38, C, 5), + GD32_PIN(39, C, 6), + GD32_PIN(40, C, 7), + GD32_PIN(41, C, 8), + GD32_PIN(42, C, 9), + GD32_PIN(43, C, 10), + GD32_PIN(44, C, 11), + GD32_PIN(45, C, 12), + GD32_PIN(46, C, 13), + GD32_PIN(47, C, 14), + GD32_PIN(48, C, 15), + GD32_PIN(51, D, 2), + GD32_PIN_DEFAULT, + GD32_PIN_DEFAULT, + GD32_PIN_DEFAULT, + GD32_PIN_DEFAULT, + GD32_PIN_DEFAULT, + GD32_PIN_DEFAULT, + GD32_PIN_DEFAULT, + GD32_PIN_DEFAULT, + GD32_PIN_DEFAULT, + GD32_PIN_DEFAULT, + GD32_PIN_DEFAULT, + GD32_PIN_DEFAULT, + GD32_PIN_DEFAULT, + GD32_PIN(65, F, 0), + GD32_PIN(66, F, 1), + GD32_PIN_DEFAULT, + GD32_PIN_DEFAULT, + GD32_PIN(69, F, 4), + GD32_PIN(70, F, 5), + GD32_PIN(71, F, 6), + GD32_PIN(72, F, 7), + GD32_PIN_DEFAULT, + GD32_PIN_DEFAULT, + GD32_PIN_DEFAULT, + GD32_PIN_DEFAULT, + GD32_PIN_DEFAULT, + GD32_PIN_DEFAULT, + GD32_PIN_DEFAULT, + GD32_PIN_DEFAULT, +}; + +static const struct pin_irq_map pin_irq_map[] = +{ + {GPIO_PIN_0, EXTI0_1_IRQn}, + {GPIO_PIN_1, EXTI0_1_IRQn}, + {GPIO_PIN_2, EXTI2_3_IRQn}, + {GPIO_PIN_3, EXTI2_3_IRQn}, + {GPIO_PIN_4, EXTI4_15_IRQn}, + {GPIO_PIN_5, EXTI4_15_IRQn}, + {GPIO_PIN_6, EXTI4_15_IRQn}, + {GPIO_PIN_7, EXTI4_15_IRQn}, + {GPIO_PIN_8, EXTI4_15_IRQn}, + {GPIO_PIN_9, EXTI4_15_IRQn}, + {GPIO_PIN_10, EXTI4_15_IRQn}, + {GPIO_PIN_11, EXTI4_15_IRQn}, + {GPIO_PIN_12, EXTI4_15_IRQn}, + {GPIO_PIN_13, EXTI4_15_IRQn}, + {GPIO_PIN_14, EXTI4_15_IRQn}, + {GPIO_PIN_15, EXTI4_15_IRQn}, +}; + +struct rt_pin_irq_hdr pin_irq_hdr_tab[] = +{ + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, +}; + +#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) +const struct pin_index *get_pin(rt_uint8_t pin) +{ + const struct pin_index *index; + + if (pin < ITEM_NUM(pins)) + { + index = &pins[pin]; + if (index->index == -1) + index = RT_NULL; + } + else + { + index = RT_NULL; + } + + return index; +}; + +void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +{ + const struct pin_index *index = RT_NULL; + rt_uint32_t pin_mode = 0, pin_pupd = 0, pin_odpp = 0; + + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + + /* GPIO Periph clock enable */ + rcu_periph_clock_enable(index->clk); + pin_mode = GPIO_MODE_OUTPUT; + + switch(mode) + { + case PIN_MODE_OUTPUT: + /* output setting */ + pin_mode = GPIO_MODE_OUTPUT; + pin_pupd = GPIO_PUPD_NONE; + pin_odpp = GPIO_OTYPE_PP; + break; + case PIN_MODE_OUTPUT_OD: + /* output setting: od. */ + pin_mode = GPIO_MODE_OUTPUT; + pin_pupd = GPIO_PUPD_NONE; + pin_odpp = GPIO_OTYPE_OD; + break; + case PIN_MODE_INPUT: + /* input setting: not pull. */ + pin_mode = GPIO_MODE_INPUT; + pin_pupd = GPIO_PUPD_PULLUP | GPIO_PUPD_PULLDOWN; + break; + case PIN_MODE_INPUT_PULLUP: + /* input setting: pull up. */ + pin_mode = GPIO_MODE_INPUT; + pin_pupd = GPIO_PUPD_PULLUP; + break; + case PIN_MODE_INPUT_PULLDOWN: + /* input setting: pull down. */ + pin_mode = GPIO_MODE_INPUT; + pin_pupd = GPIO_PUPD_PULLDOWN; + break; + default: + break; + } + + gpio_mode_set(index->gpio_periph, pin_mode, pin_pupd, index->pin); + if(pin_mode == GPIO_MODE_OUTPUT) + { + gpio_output_options_set(index->gpio_periph, pin_odpp, GPIO_OSPEED_50MHZ, index->pin); + } +} + +void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +{ + const struct pin_index *index = RT_NULL; + + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + + gpio_bit_write(index->gpio_periph, index->pin, (bit_status)value); +} + +int gd32_pin_read(rt_device_t dev, rt_base_t pin) +{ + int value = PIN_LOW; + const struct pin_index *index = RT_NULL; + + index = get_pin(pin); + if (index == RT_NULL) + { + return value; + } + + value = gpio_input_bit_get(index->gpio_periph, index->pin); + return value; +} + +rt_inline rt_int32_t bit2bitno(rt_uint32_t bit) +{ + rt_uint8_t i; + for (i = 0; i < 32; i++) + { + if ((0x01 << i) == bit) + { + return i; + } + } + return -1; +} + +rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint32_t pinbit) +{ + rt_int32_t map_index = bit2bitno(pinbit); + if (map_index < 0 || map_index >= ITEM_NUM(pin_irq_map)) + { + return RT_NULL; + } + return &pin_irq_map[map_index]; +}; + +rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_int32_t pin, + rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + const struct pin_index *index = RT_NULL; + rt_base_t level; + rt_int32_t hdr_index = -1; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_EINVAL; + } + + hdr_index = bit2bitno(index->pin); + if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map)) + { + return RT_EINVAL; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[hdr_index].pin == pin && + pin_irq_hdr_tab[hdr_index].hdr == hdr && + pin_irq_hdr_tab[hdr_index].mode == mode && + pin_irq_hdr_tab[hdr_index].args == args) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + if (pin_irq_hdr_tab[hdr_index].pin != -1) + { + rt_hw_interrupt_enable(level); + return RT_EFULL; + } + pin_irq_hdr_tab[hdr_index].pin = pin; + pin_irq_hdr_tab[hdr_index].hdr = hdr; + pin_irq_hdr_tab[hdr_index].mode = mode; + pin_irq_hdr_tab[hdr_index].args = args; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +rt_err_t gd32_pin_detach_irq(struct rt_device *device, rt_int32_t pin) +{ + const struct pin_index *index = RT_NULL; + rt_base_t level; + rt_int32_t hdr_index = -1; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_EINVAL; + } + + hdr_index = bit2bitno(index->pin); + if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map)) + { + return RT_EINVAL; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[hdr_index].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + pin_irq_hdr_tab[hdr_index].pin = -1; + pin_irq_hdr_tab[hdr_index].hdr = RT_NULL; + pin_irq_hdr_tab[hdr_index].mode = 0; + pin_irq_hdr_tab[hdr_index].args = RT_NULL; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled) +{ + const struct pin_index *index; + const struct pin_irq_map *irqmap; + rt_base_t level; + rt_int32_t hdr_index = -1; + exti_trig_type_enum trigger_mode; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_EINVAL; + } + + if (enabled == PIN_IRQ_ENABLE) + { + hdr_index = bit2bitno(index->pin); + if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map)) + { + return RT_EINVAL; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[hdr_index].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EINVAL; + } + + irqmap = &pin_irq_map[hdr_index]; + + switch (pin_irq_hdr_tab[hdr_index].mode) + { + case PIN_IRQ_MODE_RISING: + trigger_mode = EXTI_TRIG_RISING; + break; + case PIN_IRQ_MODE_FALLING: + trigger_mode = EXTI_TRIG_FALLING; + break; + case PIN_IRQ_MODE_RISING_FALLING: + trigger_mode = EXTI_TRIG_BOTH; + break; + default: + rt_hw_interrupt_enable(level); + return RT_EINVAL; + } + + rcu_periph_clock_enable(RCU_CFGCMP); + + /* enable and set interrupt priority */ + nvic_irq_enable(irqmap->irqno, 5U, 0U); + + /* connect EXTI line to GPIO pin */ + syscfg_exti_line_config(index->port_src, index->pin_src); + + /* configure EXTI line */ + exti_init((exti_line_enum)(index->pin), EXTI_INTERRUPT, trigger_mode); + exti_interrupt_flag_clear((exti_line_enum)(index->pin)); + + rt_hw_interrupt_enable(level); + } + else if (enabled == PIN_IRQ_DISABLE) + { + irqmap = get_pin_irq_map(index->pin); + if (irqmap == RT_NULL) + { + return RT_EINVAL; + } + nvic_irq_disable(irqmap->irqno); + } + else + { + return RT_EINVAL; + } + + return RT_EOK; +} + +const static struct rt_pin_ops gd32_pin_ops = +{ + gd32_pin_mode, + gd32_pin_write, + gd32_pin_read, + gd32_pin_attach_irq, + gd32_pin_detach_irq, + gd32_pin_irq_enable, + RT_NULL, +}; + +rt_inline void pin_irq_hdr(int irqno) +{ + if (pin_irq_hdr_tab[irqno].hdr) + { + pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); + } +} + +void GD32_GPIO_EXTI_IRQHandler(rt_int8_t exti_line) +{ + if(RESET != exti_interrupt_flag_get((exti_line_enum)(1 << exti_line))) + { + pin_irq_hdr(exti_line); + exti_interrupt_flag_clear((exti_line_enum)(1 << exti_line)); + } +} + +void EXTI0_1_IRQHandler(void) +{ + rt_interrupt_enter(); + GD32_GPIO_EXTI_IRQHandler(0); + GD32_GPIO_EXTI_IRQHandler(1); + rt_interrupt_leave(); +} + +void EXTI2_3_IRQHandler(void) +{ + rt_interrupt_enter(); + GD32_GPIO_EXTI_IRQHandler(2); + GD32_GPIO_EXTI_IRQHandler(3); + rt_interrupt_leave(); +} + +void EXTI4_15_IRQHandler(void) +{ + rt_interrupt_enter(); + GD32_GPIO_EXTI_IRQHandler(4); + GD32_GPIO_EXTI_IRQHandler(5); + GD32_GPIO_EXTI_IRQHandler(6); + GD32_GPIO_EXTI_IRQHandler(7); + GD32_GPIO_EXTI_IRQHandler(8); + GD32_GPIO_EXTI_IRQHandler(9); + GD32_GPIO_EXTI_IRQHandler(10); + GD32_GPIO_EXTI_IRQHandler(11); + GD32_GPIO_EXTI_IRQHandler(12); + GD32_GPIO_EXTI_IRQHandler(13); + GD32_GPIO_EXTI_IRQHandler(14); + GD32_GPIO_EXTI_IRQHandler(15); + rt_interrupt_leave(); +} + +int rt_hw_pin_init(void) +{ + int result; + + result = rt_device_pin_register("pin", &gd32_pin_ops, RT_NULL); + + return result; +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + +#endif diff --git a/bsp/gd32350r-eval/drivers/drv_gpio.h b/bsp/gd32350r-eval/drivers/drv_gpio.h new file mode 100644 index 0000000000..f3e750970d --- /dev/null +++ b/bsp/gd32350r-eval/drivers/drv_gpio.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-06-20 RiceChen the first version + */ + +#ifndef __DRV_GPIO_H__ +#define __DRV_GPIO_H__ + +#include "gd32f3x0.h" +#include "gd32f3x0_exti.h" + +#define GD32_PIN(index, port, pin) {index, RCU_GPIO##port, \ + GPIO##port, GPIO_PIN_##pin, \ + EXTI_SOURCE_GPIO##port, \ + EXTI_SOURCE_PIN##pin} +#define GD32_PIN_DEFAULT {-1, (rcu_periph_enum)0, 0, 0, 0, 0} + +struct pin_index +{ + rt_int16_t index; + rcu_periph_enum clk; + rt_uint32_t gpio_periph; + rt_uint32_t pin; + rt_uint8_t port_src; + rt_uint8_t pin_src; +}; + +struct pin_irq_map +{ + rt_uint16_t pinbit; + IRQn_Type irqno; +}; + +#endif diff --git a/bsp/gd32350r-eval/drivers/drv_usart.c b/bsp/gd32350r-eval/drivers/drv_usart.c new file mode 100644 index 0000000000..254b24a093 --- /dev/null +++ b/bsp/gd32350r-eval/drivers/drv_usart.c @@ -0,0 +1,248 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-06-21 RiceChen the first version + */ + + +#include + +#ifdef RT_USING_SERIAL + +#if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) +#error "Please define at least one UARTx" +#endif + +#include "drv_usart.h" + +static struct gd32_usart_config usart_config[] = +{ +#ifdef BSP_USING_UART0 + UART0_BUS_CONFIG, +#endif +#ifdef BSP_USING_UART1 + UART1_BUS_CONFIG, +#endif +}; + +static struct gd32_usart_bus usart_obj[sizeof(usart_config) / sizeof(usart_config[0])]; + +void gd32_usart_gpio_init(struct gd32_usart_bus *bus) +{ + rcu_periph_clock_enable(bus->config->per_clk); + rcu_periph_clock_enable(bus->config->tx_gpio_clk); + rcu_periph_clock_enable(bus->config->rx_gpio_clk); + + gpio_af_set(bus->config->tx_port, GPIO_AF_1, bus->config->tx_pin); + gpio_af_set(bus->config->rx_port, GPIO_AF_1, bus->config->rx_pin); + + gpio_mode_set(bus->config->tx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, bus->config->tx_pin); + gpio_output_options_set(bus->config->tx_port, GPIO_OTYPE_PP, GPIO_OSPEED_10MHZ, bus->config->tx_pin); + + gpio_mode_set(bus->config->rx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, bus->config->rx_pin); + gpio_output_options_set(bus->config->rx_port, GPIO_OTYPE_PP, GPIO_OSPEED_10MHZ, bus->config->rx_pin); + + NVIC_SetPriority(bus->config->irqn, 0); + NVIC_EnableIRQ(bus->config->irqn); + usart_deinit(bus->config->periph); +} + +rt_err_t gd32_usart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct gd32_usart_bus *bus = RT_NULL; + + bus = (struct gd32_usart_bus *)serial->parent.user_data; + + gd32_usart_gpio_init(bus); + + usart_baudrate_set(bus->config->periph, cfg->baud_rate); + + switch (cfg->data_bits) + { + case DATA_BITS_9: + usart_word_length_set(bus->config->periph, USART_WL_9BIT); + break; + + default: + usart_word_length_set(bus->config->periph, USART_WL_8BIT); + break; + } + + switch (cfg->stop_bits) + { + case STOP_BITS_2: + usart_stop_bit_set(bus->config->periph, USART_STB_2BIT); + break; + default: + usart_stop_bit_set(bus->config->periph, USART_STB_1BIT); + break; + } + + switch (cfg->parity) + { + case PARITY_ODD: + usart_parity_config(bus->config->periph, USART_PM_ODD); + break; + case PARITY_EVEN: + usart_parity_config(bus->config->periph, USART_PM_EVEN); + break; + default: + usart_parity_config(bus->config->periph, USART_PM_NONE); + break; + } + + usart_receive_config(bus->config->periph, USART_RECEIVE_ENABLE); + usart_transmit_config(bus->config->periph, USART_TRANSMIT_ENABLE); + usart_enable(bus->config->periph); + + return RT_EOK; +} + +rt_err_t gd32_usart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct gd32_usart_bus *bus = RT_NULL; + + bus = (struct gd32_usart_bus *)serial->parent.user_data; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + NVIC_DisableIRQ(bus->config->irqn); + /* disable interrupt */ + usart_interrupt_disable(bus->config->periph, USART_INT_RBNE); + + break; + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + NVIC_EnableIRQ(bus->config->irqn); + /* enable interrupt */ + usart_interrupt_enable(bus->config->periph, USART_INT_RBNE); + break; + } + + return RT_EOK; +} + +int gd32_usart_putc(struct rt_serial_device *serial, char c) +{ + struct gd32_usart_bus *bus = RT_NULL; + + bus = (struct gd32_usart_bus *)serial->parent.user_data; + + usart_data_transmit(bus->config->periph, c); + while((usart_flag_get(bus->config->periph, USART_FLAG_TC) == RESET)); + + return 1; +} + +int gd32_usart_getc(struct rt_serial_device *serial) +{ + int ch; + struct gd32_usart_bus *bus = RT_NULL; + + bus = (struct gd32_usart_bus *)serial->parent.user_data; + + ch = -1; + if (usart_flag_get(bus->config->periph, USART_FLAG_RBNE) != RESET) + ch = usart_data_receive(bus->config->periph); + return ch; +} + +rt_size_t gd32_usart_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction) +{ + return RT_EOK; +} + +static struct rt_uart_ops usart_ops = +{ + gd32_usart_configure, + gd32_usart_control, + gd32_usart_putc, + gd32_usart_getc, + gd32_usart_dma_transmit, +}; + +static void uart_isr(rt_uint32_t periph) +{ + int obj_num = 0; + struct gd32_usart_bus *bus = RT_NULL; + + obj_num = sizeof(usart_config) / sizeof(usart_config[0]); + + for(int i = 0; i < obj_num; i++) + { + if(usart_obj[i].config->periph == periph) + { + bus = &usart_obj[i]; + break; + } + } + + if(bus != RT_NULL) + { + if ((usart_interrupt_flag_get(bus->config->periph, USART_INT_FLAG_RBNE) != RESET) && + (usart_flag_get(bus->config->periph, USART_FLAG_RBNE) != RESET)) + { + rt_hw_serial_isr(&bus->serial, RT_SERIAL_EVENT_RX_IND); + /* Clear RXNE interrupt flag */ + usart_flag_clear(bus->config->periph, USART_FLAG_RBNE); + } + } +} + +#ifdef BSP_USING_UART0 +void USART0_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(USART0); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_UART1 +void USART1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(USART1); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +int rt_hw_usart_init(void) +{ + int obj_num = 0; + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + + obj_num = sizeof(usart_config) / sizeof(usart_config[0]); + + for(int i = 0; i < obj_num; i++) + { + usart_obj[i].serial.ops = &usart_ops; + usart_obj[i].serial.config = config; + usart_obj[i].config = &usart_config[i]; + + /* register UART device */ + rt_hw_serial_register(&usart_obj[i].serial, + usart_obj[i].config->dev_name, + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + (void *)&usart_obj[i]); + } + + return RT_EOK; +} +INIT_BOARD_EXPORT(rt_hw_usart_init); + +#endif diff --git a/bsp/gd32350r-eval/drivers/drv_usart.h b/bsp/gd32350r-eval/drivers/drv_usart.h new file mode 100644 index 0000000000..10561646a7 --- /dev/null +++ b/bsp/gd32350r-eval/drivers/drv_usart.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-06-20 RiceChen the first version + */ + +#ifndef __DRV_USART_H__ +#define __DRV_USART_H__ + +#include +#include +#include "gd32f3x0.h" +#include "gd32f3x0_usart.h" +#include "gd32f3x0_exti.h" + +struct gd32_usart_config +{ + char *dev_name; + rt_uint32_t periph; + IRQn_Type irqn; + rcu_periph_enum per_clk; + rcu_periph_enum tx_gpio_clk; + rcu_periph_enum rx_gpio_clk; + rt_uint32_t tx_port; + rt_uint32_t tx_pin; + rt_uint32_t rx_port; + rt_uint32_t rx_pin; +}; + +struct gd32_usart_bus +{ + struct rt_serial_device serial; + struct gd32_usart_config *config; +}; + +#ifdef BSP_USING_UART0 +#define UART0_BUS_CONFIG \ + { \ + .dev_name = "uart0", \ + .periph = USART0, \ + .irqn = USART0_IRQn, \ + .per_clk = RCU_USART0, \ + .tx_gpio_clk = RCU_GPIOA, \ + .rx_gpio_clk = RCU_GPIOA, \ + .tx_port = GPIOA, \ + .tx_pin = GPIO_PIN_9, \ + .rx_port = GPIOA, \ + .rx_pin = GPIO_PIN_10, \ + } +#endif /* BSP_USING_UART0 */ + +#ifdef BSP_USING_UART1 +#define UART1_BUS_CONFIG \ + { \ + .dev_name = "uart1", \ + .periph = USART1, \ + .irqn = USART1_IRQn, \ + .per_clk = RCU_USART1, \ + .tx_gpio_clk = RCU_GPIOA, \ + .rx_gpio_clk = RCU_GPIOA, \ + .tx_port = GPIOA, \ + .tx_pin = GPIO_PIN_2, \ + .rx_port = GPIOA, \ + .rx_pin = GPIO_PIN_3, \ + } +#endif /* BSP_USING_UART1 */ + +#endif diff --git a/bsp/gd32350r-eval/drivers/gd32f3x0_libopt.h b/bsp/gd32350r-eval/drivers/gd32f3x0_libopt.h new file mode 100644 index 0000000000..7192e4fb12 --- /dev/null +++ b/bsp/gd32350r-eval/drivers/gd32f3x0_libopt.h @@ -0,0 +1,66 @@ +/*! + \file gd32f3x0_libopt.h + \brief library optional for gd32f3x0 + + \version 2017-06-28, V1.0.0, demo for GD32F3x0 + \version 2019-06-01, V2.0.0, demo for GD32F3x0 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F3X0_LIBOPT_H +#define GD32F3X0_LIBOPT_H + +#include "gd32f3x0_adc.h" +#include "gd32f3x0_crc.h" +#include "gd32f3x0_ctc.h" +#include "gd32f3x0_dbg.h" +#include "gd32f3x0_dma.h" +#include "gd32f3x0_exti.h" +#include "gd32f3x0_fmc.h" +#include "gd32f3x0_gpio.h" +#include "gd32f3x0_syscfg.h" +#include "gd32f3x0_i2c.h" +#include "gd32f3x0_fwdgt.h" +#include "gd32f3x0_pmu.h" +#include "gd32f3x0_rcu.h" +#include "gd32f3x0_rtc.h" +#include "gd32f3x0_spi.h" +#include "gd32f3x0_timer.h" +#include "gd32f3x0_usart.h" +#include "gd32f3x0_wwdgt.h" +#include "gd32f3x0_misc.h" +#include "gd32f3x0_tsi.h" + +#ifdef GD32F350 +#include "gd32f3x0_cec.h" +#include "gd32f3x0_cmp.h" +#include "gd32f3x0_dac.h" +#endif /* GD32F350 */ + +#endif /* GD32F3X0_LIBOPT_H */ diff --git a/bsp/gd32350r-eval/gd32_rom.icf b/bsp/gd32350r-eval/gd32_rom.icf new file mode 100644 index 0000000000..1741be6a71 --- /dev/null +++ b/bsp/gd32350r-eval/gd32_rom.icf @@ -0,0 +1,40 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x082FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x2000; +define symbol __ICFEDIT_size_heap__ = 0x2000; +/**** End of ICF editor section. ###ICF###*/ + +export symbol __ICFEDIT_region_RAM_end__; + +define symbol __region_RAM1_start__ = 0x10000000; +define symbol __region_RAM1_end__ = 0x1000FFFF; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region RAM1_region = mem:[from __region_RAM1_start__ to __region_RAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +keep { section FSymTab }; +keep { section VSymTab }; +keep { section .rti_fn* }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; +place in RAM1_region { section .sram }; \ No newline at end of file diff --git a/bsp/gd32350r-eval/gd32_rom.ld b/bsp/gd32350r-eval/gd32_rom.ld new file mode 100644 index 0000000000..ec1c65c34e --- /dev/null +++ b/bsp/gd32350r-eval/gd32_rom.ld @@ -0,0 +1,142 @@ +/* + * linker script for GD32F4xx with GNU ld + * bernard.xiong 2009-10-14 + */ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + CODE (rx) : ORIGIN = 0x08000000, LENGTH = 3072k /* 3072KB flash */ + DATA (rw) : ORIGIN = 0x20000000, LENGTH = 192k /* 192KB sram */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x200; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + . = ALIGN(4); + _etext = .; + } > CODE = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > CODE + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >DATA + + .stack : + { + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >DATA + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > DATA + __bss_end = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/gd32350r-eval/gd32_rom.sct b/bsp/gd32350r-eval/gd32_rom.sct new file mode 100644 index 0000000000..a4fc4f2765 --- /dev/null +++ b/bsp/gd32350r-eval/gd32_rom.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x00200000 { ; load region size_region + ER_IROM1 0x08000000 0x00200000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00004000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/gd32350r-eval/project.uvoptx b/bsp/gd32350r-eval/project.uvoptx new file mode 100644 index 0000000000..45a8b35cef --- /dev/null +++ b/bsp/gd32350r-eval/project.uvoptx @@ -0,0 +1,1094 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
+ + + + rt-thread_gd32f30x + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + GD32F350R8 + GigaDevice + GigaDevice.GD32F3x0_DFP.2.0.0 + http://gd32mcu.21ic.com/data/documents/yingyongruanjian/ + IRAM(0x20000000,0x04000) IROM(0x08000000,0x10000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F3x0 -FS08000000 -FL010000 -FP0($$Device:GD32F350R8$Flash\GD32F3x0.FLM)) + 0 + $$Device:GD32F350R8$Device\Include\gd32f3x0.h + + + + + + + + + + $$Device:GD32F350R8$SVD\GD32F3x0.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rtthread-gd32f3x0 + 1 + 0 + 1 + 1 + 0 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 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applications;.;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m4;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;drivers;..\..\components\finsh;.;..\..\include;..\..\components\libc\compilers\common;..\..\components\libc\compilers\common\none-gcc;Libraries\CMSIS\GD\GD32F3x0\Include;Libraries\CMSIS;Libraries\GD32F3x0_standard_peripheral\Include;..\..\examples\utest\testcases\kernel + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\gd32_rom.ld + + + + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + CPU + + + showmem.c + 1 + ..\..\libcpu\arm\common\showmem.c + + + div0.c + 1 + ..\..\libcpu\arm\common\div0.c + + + backtrace.c + 1 + ..\..\libcpu\arm\common\backtrace.c + + + context_rvds.S + 2 + ..\..\libcpu\arm\cortex-m4\context_rvds.S + + + cpuport.c + 1 + ..\..\libcpu\arm\cortex-m4\cpuport.c + + + + + DeviceDrivers + + + pin.c + 1 + ..\..\components\drivers\misc\pin.c + + + serial.c + 1 + ..\..\components\drivers\serial\serial.c + + + completion.c + 1 + ..\..\components\drivers\src\completion.c + + + workqueue.c + 1 + ..\..\components\drivers\src\workqueue.c + + + ringblk_buf.c + 1 + ..\..\components\drivers\src\ringblk_buf.c + + + waitqueue.c + 1 + ..\..\components\drivers\src\waitqueue.c + + + ringbuffer.c + 1 + ..\..\components\drivers\src\ringbuffer.c + + + dataqueue.c + 1 + ..\..\components\drivers\src\dataqueue.c + + + pipe.c + 1 + ..\..\components\drivers\src\pipe.c + + + + + Drivers + + + drv_gpio.c + 1 + drivers\drv_gpio.c + + + drv_usart.c + 1 + drivers\drv_usart.c + + + board.c + 1 + drivers\board.c + + + + + finsh + + + finsh_node.c + 1 + ..\..\components\finsh\finsh_node.c + + + finsh_parser.c + 1 + ..\..\components\finsh\finsh_parser.c + + + cmd.c + 1 + ..\..\components\finsh\cmd.c + + + finsh_vm.c + 1 + ..\..\components\finsh\finsh_vm.c + + + shell.c + 1 + ..\..\components\finsh\shell.c + + + finsh_var.c + 1 + ..\..\components\finsh\finsh_var.c + + + finsh_compiler.c + 1 + ..\..\components\finsh\finsh_compiler.c + + + finsh_heap.c + 1 + ..\..\components\finsh\finsh_heap.c + + + finsh_ops.c + 1 + ..\..\components\finsh\finsh_ops.c + + + msh.c + 1 + ..\..\components\finsh\msh.c + + + finsh_error.c + 1 + ..\..\components\finsh\finsh_error.c + + + finsh_token.c + 1 + ..\..\components\finsh\finsh_token.c + + + finsh_init.c + 1 + ..\..\components\finsh\finsh_init.c + + + + + Kernel + + + components.c + 1 + ..\..\src\components.c + + + mem.c + 1 + ..\..\src\mem.c + + + object.c + 1 + ..\..\src\object.c + + + device.c + 1 + ..\..\src\device.c + + + thread.c + 1 + ..\..\src\thread.c + + + irq.c + 1 + ..\..\src\irq.c + + + clock.c + 1 + ..\..\src\clock.c + + + idle.c + 1 + ..\..\src\idle.c + + + timer.c + 1 + ..\..\src\timer.c + + + kservice.c + 1 + ..\..\src\kservice.c + + + scheduler.c + 1 + ..\..\src\scheduler.c + + + ipc.c + 1 + ..\..\src\ipc.c + + + mempool.c + 1 + ..\..\src\mempool.c + + + + + Libraries + + + gd32f3x0_dbg.c + 1 + Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_dbg.c + + + gd32f3x0_dac.c + 1 + Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_dac.c + + + gd32f3x0_timer.c + 1 + Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_timer.c + + + gd32f3x0_rtc.c + 1 + Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_rtc.c + + + gd32f3x0_exti.c + 1 + Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_exti.c + + + gd32f3x0_i2c.c + 1 + Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_i2c.c + + + gd32f3x0_gpio.c + 1 + Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_gpio.c + + + gd32f3x0_fwdgt.c + 1 + Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_fwdgt.c + + + system_gd32f3x0.c + 1 + Libraries\CMSIS\GD\GD32F3x0\Source\system_gd32f3x0.c + + + gd32f3x0_cec.c + 1 + Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_cec.c + + + gd32f3x0_wwdgt.c + 1 + Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_wwdgt.c + + + gd32f3x0_ctc.c + 1 + Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_ctc.c + + + gd32f3x0_rcu.c + 1 + Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_rcu.c + + + gd32f3x0_dma.c + 1 + Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_dma.c + + + gd32f3x0_spi.c + 1 + Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_spi.c + + + gd32f3x0_syscfg.c + 1 + Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_syscfg.c + + + startup_gd32f3x0.s + 2 + Libraries\CMSIS\GD\GD32F3x0\Source\ARM\startup_gd32f3x0.s + + + gd32f3x0_misc.c + 1 + Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_misc.c + + + gd32f3x0_fmc.c + 1 + Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_fmc.c + + + gd32f3x0_usart.c + 1 + Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_usart.c + + + gd32f3x0_adc.c + 1 + Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_adc.c + + + gd32f3x0_crc.c + 1 + Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_crc.c + + + gd32f3x0_tsi.c + 1 + Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_tsi.c + + + gd32f3x0_pmu.c + 1 + Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_pmu.c + + + gd32f3x0_cmp.c + 1 + Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_cmp.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/bsp/gd32350r-eval/rtconfig.h b/bsp/gd32350r-eval/rtconfig.h new file mode 100644 index 0000000000..add7a07ad6 --- /dev/null +++ b/bsp/gd32350r-eval/rtconfig.h @@ -0,0 +1,169 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 + +/* kservice optimization */ + +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x40004 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using USB */ + + +/* POSIX layer and C standard library */ + + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + + +/* AI packages */ + + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + +#define SOC_GD32350R +#define BSP_USING_UART0 + +#endif diff --git a/bsp/gd32350r-eval/rtconfig.py b/bsp/gd32350r-eval/rtconfig.py new file mode 100644 index 0000000000..1db5d5c2ba --- /dev/null +++ b/bsp/gd32350r-eval/rtconfig.py @@ -0,0 +1,126 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='keil' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'D:/toolchain/gnu_tools_arm_embedded/5.4_2016q3/bin' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'D:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # tool-chains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' # -D' + PART_TYPE + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-gd32.map,-cref,-u,Reset_Handler -T gd32_rom.ld' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu=cortex-m4.fp' + CFLAGS = DEVICE + ' --apcs=interwork --cpu Cortex-M4.fp' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-gd32.map --scatter gd32_rom.sct' + + CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' + + EXEC_PATH += '/arm/bin40/' + + CFLAGS += ' --c99' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = ' -D USE_STDPERIPH_DRIVER' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --debug' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' -Ol' + CFLAGS += ' --use_c++_inline' + + AFLAGS = '' + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu None' + + LFLAGS = ' --config gd32_rom.icf' + LFLAGS += ' --redirect _Printf=_PrintfTiny' + LFLAGS += ' --redirect _Scanf=_ScanfSmall' + LFLAGS += ' --entry __iar_program_start' + + EXEC_PATH += '/arm/bin/' + POST_ACTION = '' diff --git a/bsp/gd32350r-eval/template.uvoptx b/bsp/gd32350r-eval/template.uvoptx new file mode 100644 index 0000000000..96b3c092db --- /dev/null +++ b/bsp/gd32350r-eval/template.uvoptx @@ -0,0 +1,190 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread_gd32f30x + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0GD32F3x0.FLM -FS08000000 -FL020000 -FP0($$Device:GD32F350R8$Flash\GD32F3x0.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0GD32F3x0 -FL010000 -FS08000000 -FP0($$Device:GD32F350R8$Flash\GD32F3x0.FLM) + + + 0 + JL2CM3 + -U59401765 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0GD32F4xx_3MB.FLM -FS08000000 -FL0300000 -FP0($$Device:GD32F450ZK$Flash\GD32F4xx_3MB.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/gd32350r-eval/template.uvprojx b/bsp/gd32350r-eval/template.uvprojx new file mode 100644 index 0000000000..101d86a955 --- /dev/null +++ b/bsp/gd32350r-eval/template.uvprojx @@ -0,0 +1,401 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread_gd32f30x + 0x4 + ARM-ADS + 0 + + + GD32F350R8 + GigaDevice + GigaDevice.GD32F3x0_DFP.2.0.0 + http://gd32mcu.21ic.com/data/documents/yingyongruanjian/ + IRAM(0x20000000,0x04000) IROM(0x08000000,0x10000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F3x0 -FS08000000 -FL010000 -FP0($$Device:GD32F350R8$Flash\GD32F3x0.FLM)) + 0 + $$Device:GD32F350R8$Device\Include\gd32f3x0.h + + + + + + + + + + $$Device:GD32F350R8$SVD\GD32F3x0.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rtthread-gd32f3x0 + 1 + 0 + 1 + 1 + 0 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x4000 + + + 1 + 0x8000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x4000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\gd32_rom.ld + + + + + + + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Include/gd32f4xx.h b/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Include/gd32f4xx.h index 722e943b88..a901975bbd 100644 --- a/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Include/gd32f4xx.h +++ b/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Include/gd32f4xx.h @@ -1,27 +1,55 @@ /*! - \file gd32f4xx.h - \brief general definitions for GD32F4xx + \file gd32f4xx.h + \brief general definitions for GD32F4xx + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware update for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_H #define GD32F4XX_H -#ifdef cplusplus +#ifdef __cplusplus extern "C" { -#endif +#endif /* define GD32F4xx */ -#if !defined (GD32F4xx) - #define GD32F4xx +#if !defined (GD32F450) && !defined (GD32F405) && !defined (GD32F407) + /* #define GD32F450 */ + /* #define GD32F405 */ + /* #define GD32F407 */ #endif /* define GD32F4xx */ -#if !defined (GD32F4xx) - #error "Please select the target GD32F4xx device used in your application (in gd32f4xx.h file)" + +#if !defined (GD32F450) && !defined (GD32F405) && !defined (GD32F407) + #error "Please select the target GD32F4xx device in gd32f4xx.h file" #endif /* undefine GD32F4xx tip */ /* define value of high speed crystal oscillator (HXTAL) in Hz */ @@ -31,11 +59,11 @@ /* define startup timeout value of high speed crystal oscillator (HXTAL) */ #if !defined (HXTAL_STARTUP_TIMEOUT) -#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0x0800) +#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0xFFFF) #endif /* high speed crystal oscillator startup timeout */ /* define value of internal 16MHz RC oscillator (IRC16M) in Hz */ -#if !defined (IRC16M_VALUE) +#if !defined (IRC16M_VALUE) #define IRC16M_VALUE ((uint32_t)16000000) #endif /* internal 16MHz RC oscillator value */ @@ -45,12 +73,12 @@ #endif /* internal 16MHz RC oscillator startup timeout */ /* define value of internal 32KHz RC oscillator(IRC32K) in Hz */ -#if !defined (IRC32K_VALUE) +#if !defined (IRC32K_VALUE) #define IRC32K_VALUE ((uint32_t)32000) #endif /* internal 32KHz RC oscillator value */ /* define value of low speed crystal oscillator (LXTAL)in Hz */ -#if !defined (LXTAL_VALUE) +#if !defined (LXTAL_VALUE) #define LXTAL_VALUE ((uint32_t)32768) #endif /* low speed crystal oscillator value */ @@ -61,35 +89,35 @@ #define __GD32F4xx_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:24] main version */ #define __GD32F4xx_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ #define __GD32F4xx_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __GD32F4xx_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __GD32F4xx_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __GD32F4xx_STDPERIPH_VERSION ((__GD32F4xx_STDPERIPH_VERSION_MAIN << 24)\ |(__GD32F4xx_STDPERIPH_VERSION_SUB1 << 16)\ |(__GD32F4xx_STDPERIPH_VERSION_SUB2 << 8)\ |(__GD32F4xx_STDPERIPH_VERSION_RC)) -/* configuration of the Cortex-M4 processor and core peripherals */ -#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 1 /*!< GD32F4xx do not provide MPU */ +/* configuration of the cortex-M4 processor and core peripherals */ +#define __CM4_REV 0x0001 /*!< core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< GD32F4xx provide MPU */ #define __NVIC_PRIO_BITS 4 /*!< GD32F4xx uses 4 bits for the priority levels */ -#define __VENDOR_SYSTICKCONFIG 0 /*!< set to 1 if different sysTick config is used */ +#define __Vendor_SysTickConfig 0 /*!< set to 1 if different sysTick config is used */ #define __FPU_PRESENT 1 /*!< FPU present */ /* define interrupt number */ typedef enum IRQn { - /* Cortex-M4 processor exceptions numbers */ + /* cortex-M4 processor exceptions numbers */ NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 memory management interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M4 bus fault interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M4 usage fault interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV call interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 debug monitor interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M4 pend SV interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M4 system tick interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 cortex-M4 memory management interrupt */ + BusFault_IRQn = -11, /*!< 5 cortex-M4 bus fault interrupt */ + UsageFault_IRQn = -10, /*!< 6 cortex-M4 usage fault interrupt */ + SVCall_IRQn = -5, /*!< 11 cortex-M4 SV call interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 cortex-M4 debug monitor interrupt */ + PendSV_IRQn = -2, /*!< 14 cortex-M4 pend SV interrupt */ + SysTick_IRQn = -1, /*!< 15 cortex-M4 system tick interrupt */ /* interruput numbers */ - WWDGT_IRQn = 0, /*!< window watchDog timer interrupt */ + WWDGT_IRQn = 0, /*!< window watchdog timer interrupt */ LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */ - TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp through EXTI Line detect */ - RTC_WKUP_IRQn = 3, /*!< RTC Wakeup through EXTI line interrupt */ + TAMPER_STAMP_IRQn = 2, /*!< tamper and timestamp through EXTI line detect */ + RTC_WKUP_IRQn = 3, /*!< RTC wakeup through EXTI line interrupt */ FMC_IRQn = 4, /*!< FMC interrupt */ RCU_CTC_IRQn = 5, /*!< RCU and CTC interrupt */ EXTI0_IRQn = 6, /*!< EXTI line 0 interrupts */ @@ -97,23 +125,23 @@ typedef enum IRQn EXTI2_IRQn = 8, /*!< EXTI line 2 interrupts */ EXTI3_IRQn = 9, /*!< EXTI line 3 interrupts */ EXTI4_IRQn = 10, /*!< EXTI line 4 interrupts */ - DMA0_Channel0_IRQn = 11, /*!< DMA0 Channel0 Interrupt */ - DMA0_Channel1_IRQn = 12, /*!< DMA0 Channel1 Interrupt */ - DMA0_Channel2_IRQn = 13, /*!< DMA0 Channel2 Interrupt */ - DMA0_Channel3_IRQn = 14, /*!< DMA0 Channel3 Interrupt */ - DMA0_Channel4_IRQn = 15, /*!< DMA0 Channel4 Interrupt */ - DMA0_Channel5_IRQn = 16, /*!< DMA0 Channel5 Interrupt */ - DMA0_Channel6_IRQn = 17, /*!< DMA0 Channel6 Interrupt */ + DMA0_Channel0_IRQn = 11, /*!< DMA0 channel0 Interrupt */ + DMA0_Channel1_IRQn = 12, /*!< DMA0 channel1 Interrupt */ + DMA0_Channel2_IRQn = 13, /*!< DMA0 channel2 interrupt */ + DMA0_Channel3_IRQn = 14, /*!< DMA0 channel3 interrupt */ + DMA0_Channel4_IRQn = 15, /*!< DMA0 channel4 interrupt */ + DMA0_Channel5_IRQn = 16, /*!< DMA0 channel5 interrupt */ + DMA0_Channel6_IRQn = 17, /*!< DMA0 channel6 interrupt */ ADC_IRQn = 18, /*!< ADC interrupt */ - CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */ - CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */ - CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */ - CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */ + CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupt */ + CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupt */ + CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupt */ + CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupt */ EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */ - TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 Break and TIMER8 interrupts */ - TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 Update and TIMER9 interrupts */ - TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 Trigger and Commutation and TIMER10 interrupts */ - TIMER0_CC_IRQn = 27, /*!< TIMER0 Capture Compare interrupts */ + TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupts */ + TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupts */ + TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupts */ + TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupt */ TIMER1_IRQn = 28, /*!< TIMER1 interrupt */ TIMER2_IRQn = 29, /*!< TIMER2 interrupt */ TIMER3_IRQn = 30, /*!< TIMER3 interrupts */ @@ -127,54 +155,127 @@ typedef enum IRQn USART1_IRQn = 38, /*!< USART1 interrupt */ USART2_IRQn = 39, /*!< USART2 interrupt */ EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm interrupt */ - USBFS_WKUP_IRQn = 42, /*!< USBFS Wakeup interrupt */ - TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 Break and TIMER11 interrupts */ - TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 Update and TIMER12 interrupts */ - TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 Trigger and Commutation and TIMER13 interrupts */ - TIMER7_CC_IRQn = 46, /*!< TIMER7 Capture Compare interrupts */ - DMA0_Channel7_IRQn = 47, /*!< DMA0 Channel7 Interrupt */ - EXMC_IRQn = 48, /*!< EXMC Interrupt */ - SDIO_IRQn = 49, /*!< SDIO Interrupt */ - TIMER4_IRQn = 50, /*!< TIMER4 Interrupt */ - SPI2_IRQn = 51, /*!< SPI2 Interrupt */ - UART3_IRQn = 52, /*!< UART3 Interrupt */ - UART4_IRQn = 53, /*!< UART4 Interrupt */ - TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC0 DAC1 Underrun error Interrupt */ - TIMER6_IRQn = 55, /*!< TIMER6 Interrupt */ - DMA1_Channel0_IRQn = 56, /*!< DMA1 Channel0 Interrupt */ - DMA1_Channel1_IRQn = 57, /*!< DMA1 Channel1 Interrupt */ - DMA1_Channel2_IRQn = 58, /*!< DMA1 Channel2 Interrupt */ - DMA1_Channel3_IRQn = 59, /*!< DMA1 Channel3 Interrupt */ - DMA1_Channel4_IRQn = 60, /*!< DMA1 Channel4 Interrupt */ - ENET_IRQn = 61, /*!< Ethernet Interrupt */ - ENET_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI Line Interrupt */ - CAN1_TX_IRQn = 63, /*!< CAN1 TX Interrupt */ - CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 Interrupt */ - CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 Interrupt */ - CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC Interrupt */ - USBFS_IRQn = 67, /*!< USBFS Interrupt */ - DMA1_Channel5_IRQn = 68, /*!< DMA1 Channel5 Interrupt */ - DMA1_Channel6_IRQn = 69, /*!< DMA1 Channel6 Interrupt */ - DMA1_Channel7_IRQn = 70, /*!< DMA1 Channel7 Interrupt */ - USART5_IRQn = 71, /*!< USART5 Interrupt */ - I2C2_EV_IRQn = 72, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 73, /*!< I2C2 Error Interrupt */ - USBHS_EP1_Out_IRQn = 74, /*!< USBHS Endpoint 1 Out Interrupt */ - USBHS_EP1_In_IRQn = 75, /*!< USBHS Endpoint 1 in Interrupt */ - USBHS_WKUP_IRQn = 76, /*!< USBHS Wakeup through EXTI Line Interrupt */ - USBHS_IRQn = 77, /*!< USBHS Interrupt */ - DCI_IRQn = 78, /*!< DCI Interrupt */ - TRNG_IRQn = 80, /*!< TRNG Interrupt */ - FPU_IRQn = 81, /*!< FPU Interrupt */ - UART6_IRQn = 82, /*!< UART6 Interrupt */ - UART7_IRQn = 83, /*!< UART7 Interrupt */ - SPI3_IRQn = 84, /*!< SPI3 Interrupt */ - SPI4_IRQn = 85, /*!< SPI4 Interrupt */ - SPI5_IRQn = 86, /*!< SPI5 Interrupt */ - TLI_IRQn = 88, /*!< TLI Interrupt */ - TLI_ER_IRQn = 89, /*!< TLI Error Interrupt */ - IPA_IRQn = 90, /*!< IPA Interrupt */ + RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */ + USBFS_WKUP_IRQn = 42, /*!< USBFS wakeup interrupt */ + TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupts */ + TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupts */ + TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupts */ + TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupt */ + DMA0_Channel7_IRQn = 47, /*!< DMA0 channel7 interrupt */ + +#if defined (GD32F450) + EXMC_IRQn = 48, /*!< EXMC interrupt */ + SDIO_IRQn = 49, /*!< SDIO interrupt */ + TIMER4_IRQn = 50, /*!< TIMER4 interrupt */ + SPI2_IRQn = 51, /*!< SPI2 interrupt */ + UART3_IRQn = 52, /*!< UART3 interrupt */ + UART4_IRQn = 53, /*!< UART4 interrupt */ + TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC0 DAC1 underrun error interrupts */ + TIMER6_IRQn = 55, /*!< TIMER6 interrupt */ + DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 interrupt */ + DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 interrupt */ + DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 interrupt */ + DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 interrupt */ + DMA1_Channel4_IRQn = 60, /*!< DMA1 channel4 interrupt */ + ENET_IRQn = 61, /*!< ENET interrupt */ + ENET_WKUP_IRQn = 62, /*!< ENET wakeup through EXTI line interrupt */ + CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */ + CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */ + CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */ + CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */ + USBFS_IRQn = 67, /*!< USBFS interrupt */ + DMA1_Channel5_IRQn = 68, /*!< DMA1 channel5 interrupt */ + DMA1_Channel6_IRQn = 69, /*!< DMA1 channel6 interrupt */ + DMA1_Channel7_IRQn = 70, /*!< DMA1 channel7 interrupt */ + USART5_IRQn = 71, /*!< USART5 interrupt */ + I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */ + I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */ + USBHS_EP1_Out_IRQn = 74, /*!< USBHS endpoint 1 out interrupt */ + USBHS_EP1_In_IRQn = 75, /*!< USBHS endpoint 1 in interrupt */ + USBHS_WKUP_IRQn = 76, /*!< USBHS wakeup through EXTI line interrupt */ + USBHS_IRQn = 77, /*!< USBHS interrupt */ + DCI_IRQn = 78, /*!< DCI interrupt */ + TRNG_IRQn = 80, /*!< TRNG interrupt */ + FPU_IRQn = 81, /*!< FPU interrupt */ + UART6_IRQn = 82, /*!< UART6 interrupt */ + UART7_IRQn = 83, /*!< UART7 interrupt */ + SPI3_IRQn = 84, /*!< SPI3 interrupt */ + SPI4_IRQn = 85, /*!< SPI4 interrupt */ + SPI5_IRQn = 86, /*!< SPI5 interrupt */ + TLI_IRQn = 88, /*!< TLI interrupt */ + TLI_ER_IRQn = 89, /*!< TLI error interrupt */ + IPA_IRQn = 90, /*!< IPA interrupt */ +#endif /* GD32F450 */ + +#if defined (GD32F405) + SDIO_IRQn = 49, /*!< SDIO interrupt */ + TIMER4_IRQn = 50, /*!< TIMER4 interrupt */ + SPI2_IRQn = 51, /*!< SPI2 interrupt */ + UART3_IRQn = 52, /*!< UART3 interrupt */ + UART4_IRQn = 53, /*!< UART4 interrupt */ + TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC0 DAC1 underrun error interrupts */ + TIMER6_IRQn = 55, /*!< TIMER6 interrupt */ + DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 interrupt */ + DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 interrupt */ + DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 interrupt */ + DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 interrupt */ + DMA1_Channel4_IRQn = 60, /*!< DMA1 channel4 interrupt */ + CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */ + CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */ + CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */ + CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */ + USBFS_IRQn = 67, /*!< USBFS interrupt */ + DMA1_Channel5_IRQn = 68, /*!< DMA1 channel5 interrupt */ + DMA1_Channel6_IRQn = 69, /*!< DMA1 channel6 interrupt */ + DMA1_Channel7_IRQn = 70, /*!< DMA1 channel7 interrupt */ + USART5_IRQn = 71, /*!< USART5 interrupt */ + I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */ + I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */ + USBHS_EP1_Out_IRQn = 74, /*!< USBHS endpoint 1 Out interrupt */ + USBHS_EP1_In_IRQn = 75, /*!< USBHS endpoint 1 in interrupt */ + USBHS_WKUP_IRQn = 76, /*!< USBHS wakeup through EXTI line interrupt */ + USBHS_IRQn = 77, /*!< USBHS interrupt */ + DCI_IRQn = 78, /*!< DCI interrupt */ + TRNG_IRQn = 80, /*!< TRNG interrupt */ + FPU_IRQn = 81, /*!< FPU interrupt */ +#endif /* GD32F405 */ + +#if defined (GD32F407) + EXMC_IRQn = 48, /*!< EXMC interrupt */ + SDIO_IRQn = 49, /*!< SDIO interrupt */ + TIMER4_IRQn = 50, /*!< TIMER4 interrupt */ + SPI2_IRQn = 51, /*!< SPI2 interrupt */ + UART3_IRQn = 52, /*!< UART3 interrupt */ + UART4_IRQn = 53, /*!< UART4 interrupt */ + TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC0 DAC1 underrun error interrupts */ + TIMER6_IRQn = 55, /*!< TIMER6 interrupt */ + DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 interrupt */ + DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 interrupt */ + DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 interrupt */ + DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 interrupt */ + DMA1_Channel4_IRQn = 60, /*!< DMA1 channel4 interrupt */ + ENET_IRQn = 61, /*!< ENET interrupt */ + ENET_WKUP_IRQn = 62, /*!< ENET wakeup through EXTI line interrupt */ + CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */ + CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */ + CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */ + CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */ + USBFS_IRQn = 67, /*!< USBFS interrupt */ + DMA1_Channel5_IRQn = 68, /*!< DMA1 channel5 interrupt */ + DMA1_Channel6_IRQn = 69, /*!< DMA1 channel6 interrupt */ + DMA1_Channel7_IRQn = 70, /*!< DMA1 channel7 interrupt */ + USART5_IRQn = 71, /*!< USART5 interrupt */ + I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */ + I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */ + USBHS_EP1_Out_IRQn = 74, /*!< USBHS endpoint 1 out interrupt */ + USBHS_EP1_In_IRQn = 75, /*!< USBHS endpoint 1 in interrupt */ + USBHS_WKUP_IRQn = 76, /*!< USBHS wakeup through EXTI line interrupt */ + USBHS_IRQn = 77, /*!< USBHS interrupt */ + DCI_IRQn = 78, /*!< DCI interrupt */ + TRNG_IRQn = 80, /*!< TRNG interrupt */ + FPU_IRQn = 81, /*!< FPU interrupt */ +#endif /* GD32F407 */ + } IRQn_Type; /* includes */ @@ -193,7 +294,7 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; #define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) #define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) #define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) -#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) +#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) #define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) /* main flash and SRAM memory map */ @@ -254,7 +355,7 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; /* define marco USE_STDPERIPH_DRIVER */ #if !defined USE_STDPERIPH_DRIVER #define USE_STDPERIPH_DRIVER -#endif +#endif #ifdef USE_STDPERIPH_DRIVER #include "gd32f4xx_libopt.h" #endif /* USE_STDPERIPH_DRIVER */ @@ -262,4 +363,4 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; #ifdef cplusplus } #endif -#endif +#endif diff --git a/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Source/system_gd32f4xx.c b/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Source/system_gd32f4xx.c index 6da45fa40e..2ea97ae3f8 100644 --- a/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Source/system_gd32f4xx.c +++ b/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Source/system_gd32f4xx.c @@ -56,6 +56,9 @@ #define SEL_IRC16M 0x00U #define SEL_HXTAL 0x01U #define SEL_PLLP 0x02U +#define RCU_MODIFY {volatile uint32_t i; \ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV2; \ + for(i=0;i<50000;i++);} /* set the system clock frequency and declare the system clock configuration function */ #ifdef __SYSTEM_CLOCK_IRC16M @@ -109,10 +112,12 @@ void SystemInit (void) #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ #endif - /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Reset the RCU clock configuration to the default reset state ------------*/ /* Set IRC16MEN bit */ RCU_CTL |= RCU_CTL_IRC16MEN; + RCU_MODIFY + /* Reset CFG0 register */ RCU_CFG0 = 0x00000000U; @@ -127,12 +132,10 @@ void SystemInit (void) /* Disable all interrupts */ RCU_INT = 0x00000000U; - - /* Configure the System clock source, PLL Multiplier and Divider factors, + + /* Configure the System clock source, PLL Multiplier and Divider factors, AHB/APBx prescalers and Flash settings ----------------------------------*/ system_clock_config(); - - } /*! \brief configure the system clock @@ -164,7 +167,7 @@ static void system_clock_config(void) system_clock_200m_8m_hxtal(); #elif defined (__SYSTEM_CLOCK_200M_PLL_25M_HXTAL) system_clock_200m_25m_hxtal(); -#endif /* __SYSTEM_CLOCK_IRC16M */ +#endif /* __SYSTEM_CLOCK_IRC16M */ } #ifdef __SYSTEM_CLOCK_IRC16M @@ -178,34 +181,33 @@ static void system_clock_16m_irc16m(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable IRC16M */ RCU_CTL |= RCU_CTL_IRC16MEN; - + /* wait until IRC16M is stable or the startup time is longer than IRC16M_STARTUP_TIMEOUT */ do{ timeout++; stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB); - } - while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout)); - + }while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout)); + /* if fail */ if(0U == (RCU_CTL & RCU_CTL_IRC16MSTB)){ - while(1){ - } + while(1){ + } } - + /* AHB = SYSCLK */ RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; /* APB2 = AHB */ RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; /* APB1 = AHB */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV1; - + /* select IRC16M as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_IRC16M; - + /* wait until IRC16M is selected as system clock */ while(0 != (RCU_CFG0 & RCU_SCSS_IRC16M)){ } @@ -222,34 +224,33 @@ static void system_clock_hxtal(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable HXTAL */ RCU_CTL |= RCU_CTL_HXTALEN; - + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ do{ timeout++; stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - } - while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + /* if fail */ if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } + while(1){ + } } - + /* AHB = SYSCLK */ RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; /* APB2 = AHB */ RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; /* APB1 = AHB */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV1; - + /* select HXTAL as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_HXTAL; - + /* wait until HXTAL is selected as system clock */ while(0 == (RCU_CFG0 & RCU_SCSS_HXTAL)){ } @@ -266,7 +267,7 @@ static void system_clock_120m_irc16m(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable IRC16M */ RCU_CTL |= RCU_CTL_IRC16MEN; @@ -274,15 +275,14 @@ static void system_clock_120m_irc16m(void) do{ timeout++; stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB); - } - while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout)); + }while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout)); /* if fail */ if(0U == (RCU_CTL & RCU_CTL_IRC16MSTB)){ - while(1){ - } + while(1){ + } } - + RCU_APB1EN |= RCU_APB1EN_PMUEN; PMU_CTL |= PMU_CTL_LDOVS; @@ -294,7 +294,7 @@ static void system_clock_120m_irc16m(void) /* APB1 = AHB/4 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - /* Configure the main PLL, PLL_M = 16, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */ + /* Configure the main PLL, PSC = 16, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */ RCU_PLL = (16U | (240U << 6U) | (((2U >> 1U) - 1U) << 16U) | (RCU_PLLSRC_IRC16M) | (5U << 24U)); @@ -304,19 +304,17 @@ static void system_clock_120m_irc16m(void) /* wait until PLL is stable */ while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ } - + /* Enable the high-drive to extend the clock frequency to 120 Mhz */ PMU_CTL |= PMU_CTL_HDEN; - while(0U == (PMU_CS & PMU_CS_HDRF)) - { + while(0U == (PMU_CS & PMU_CS_HDRF)){ } - + /* select the high-drive mode */ PMU_CTL |= PMU_CTL_HDS; - while(0U == (PMU_CS & PMU_CS_HDSRF)) - { - } - + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + /* select PLL as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_PLLP; @@ -337,7 +335,7 @@ static void system_clock_120m_8m_hxtal(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable HXTAL */ RCU_CTL |= RCU_CTL_HXTALEN; @@ -345,15 +343,14 @@ static void system_clock_120m_8m_hxtal(void) do{ timeout++; stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - } - while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); /* if fail */ if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } + while(1){ + } } - + RCU_APB1EN |= RCU_APB1EN_PMUEN; PMU_CTL |= PMU_CTL_LDOVS; @@ -365,7 +362,7 @@ static void system_clock_120m_8m_hxtal(void) /* APB1 = AHB/4 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - /* Configure the main PLL, PLL_M = 8, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */ + /* Configure the main PLL, PSC = 8, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */ RCU_PLL = (8U | (240U << 6U) | (((2U >> 1U) - 1U) << 16U) | (RCU_PLLSRC_HXTAL) | (5U << 24U)); @@ -375,19 +372,17 @@ static void system_clock_120m_8m_hxtal(void) /* wait until PLL is stable */ while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ } - + /* Enable the high-drive to extend the clock frequency to 120 Mhz */ PMU_CTL |= PMU_CTL_HDEN; - while(0U == (PMU_CS & PMU_CS_HDRF)) - { + while(0U == (PMU_CS & PMU_CS_HDRF)){ } - + /* select the high-drive mode */ PMU_CTL |= PMU_CTL_HDS; - while(0U == (PMU_CS & PMU_CS_HDSRF)) - { - } - + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + /* select PLL as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_PLLP; @@ -408,7 +403,7 @@ static void system_clock_120m_25m_hxtal(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable HXTAL */ RCU_CTL |= RCU_CTL_HXTALEN; @@ -416,15 +411,14 @@ static void system_clock_120m_25m_hxtal(void) do{ timeout++; stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - } - while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); /* if fail */ if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } + while(1){ + } } - + RCU_APB1EN |= RCU_APB1EN_PMUEN; PMU_CTL |= PMU_CTL_LDOVS; @@ -436,7 +430,7 @@ static void system_clock_120m_25m_hxtal(void) /* APB1 = AHB/4 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - /* Configure the main PLL, PLL_M = 25, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */ + /* Configure the main PLL, PSC = 25, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */ RCU_PLL = (25U | (240U << 6U) | (((2U >> 1U) - 1U) << 16U) | (RCU_PLLSRC_HXTAL) | (5U << 24U)); @@ -446,19 +440,17 @@ static void system_clock_120m_25m_hxtal(void) /* wait until PLL is stable */ while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ } - + /* Enable the high-drive to extend the clock frequency to 120 Mhz */ PMU_CTL |= PMU_CTL_HDEN; - while(0U == (PMU_CS & PMU_CS_HDRF)) - { + while(0U == (PMU_CS & PMU_CS_HDRF)){ } - + /* select the high-drive mode */ PMU_CTL |= PMU_CTL_HDS; - while(0U == (PMU_CS & PMU_CS_HDSRF)) - { - } - + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + /* select PLL as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_PLLP; @@ -479,7 +471,7 @@ static void system_clock_168m_irc16m(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable IRC16M */ RCU_CTL |= RCU_CTL_IRC16MEN; @@ -487,15 +479,14 @@ static void system_clock_168m_irc16m(void) do{ timeout++; stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB); - } - while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout)); + }while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout)); /* if fail */ if(0U == (RCU_CTL & RCU_CTL_IRC16MSTB)){ - while(1){ - } + while(1){ + } } - + RCU_APB1EN |= RCU_APB1EN_PMUEN; PMU_CTL |= PMU_CTL_LDOVS; @@ -507,7 +498,7 @@ static void system_clock_168m_irc16m(void) /* APB1 = AHB/4 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - /* Configure the main PLL, PLL_M = 16, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */ + /* Configure the main PLL, PSC = 16, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */ RCU_PLL = (16U | (336U << 6U) | (((2U >> 1U) - 1U) << 16U) | (RCU_PLLSRC_IRC16M) | (7U << 24U)); @@ -517,19 +508,17 @@ static void system_clock_168m_irc16m(void) /* wait until PLL is stable */ while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ } - + /* Enable the high-drive to extend the clock frequency to 168 Mhz */ PMU_CTL |= PMU_CTL_HDEN; - while(0U == (PMU_CS & PMU_CS_HDRF)) - { + while(0U == (PMU_CS & PMU_CS_HDRF)){ } - + /* select the high-drive mode */ PMU_CTL |= PMU_CTL_HDS; - while(0U == (PMU_CS & PMU_CS_HDSRF)) - { - } - + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + /* select PLL as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_PLLP; @@ -549,7 +538,7 @@ static void system_clock_168m_irc16m(void) static void system_clock_168m_8m_hxtal(void) { uint32_t timeout = 0U; - + /* enable HXTAL */ RCU_CTL |= RCU_CTL_HXTALEN; @@ -559,8 +548,8 @@ static void system_clock_168m_8m_hxtal(void) /* if fail */ if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } + while(1){ + } } RCU_APB1EN |= RCU_APB1EN_PMUEN; @@ -573,7 +562,7 @@ static void system_clock_168m_8m_hxtal(void) /* APB1 = AHB/4 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - /* Configure the main PLL, PLL_M = 8, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */ + /* Configure the main PLL, PSC = 8, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */ RCU_PLL = (8U | (336 << 6U) | (((2 >> 1U) -1U) << 16U) | (RCU_PLLSRC_HXTAL) | (7 << 24U)); @@ -583,17 +572,15 @@ static void system_clock_168m_8m_hxtal(void) /* wait until PLL is stable */ while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ } - + /* Enable the high-drive to extend the clock frequency to 168 Mhz */ PMU_CTL |= PMU_CTL_HDEN; - while(0U == (PMU_CS & PMU_CS_HDRF)) - { + while(0U == (PMU_CS & PMU_CS_HDRF)){ } - + /* select the high-drive mode */ PMU_CTL |= PMU_CTL_HDS; - while(0U == (PMU_CS & PMU_CS_HDSRF)) - { + while(0U == (PMU_CS & PMU_CS_HDSRF)){ } /* select PLL as system clock */ @@ -616,7 +603,7 @@ static void system_clock_168m_25m_hxtal(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable HXTAL */ RCU_CTL |= RCU_CTL_HXTALEN; @@ -624,15 +611,14 @@ static void system_clock_168m_25m_hxtal(void) do{ timeout++; stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - } - while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); /* if fail */ if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } + while(1){ + } } - + RCU_APB1EN |= RCU_APB1EN_PMUEN; PMU_CTL |= PMU_CTL_LDOVS; @@ -644,7 +630,7 @@ static void system_clock_168m_25m_hxtal(void) /* APB1 = AHB */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - /* Configure the main PLL, PLL_M = 25, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */ + /* Configure the main PLL, PSC = 25, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */ RCU_PLL = (25U | (336U << 6U) | (((2U >> 1U) - 1U) << 16U) | (RCU_PLLSRC_HXTAL) | (7U << 24U)); @@ -654,19 +640,17 @@ static void system_clock_168m_25m_hxtal(void) /* wait until PLL is stable */ while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ } - + /* Enable the high-drive to extend the clock frequency to 168 Mhz */ PMU_CTL |= PMU_CTL_HDEN; - while(0U == (PMU_CS & PMU_CS_HDRF)) - { + while(0U == (PMU_CS & PMU_CS_HDRF)){ } - + /* select the high-drive mode */ PMU_CTL |= PMU_CTL_HDS; - while(0U == (PMU_CS & PMU_CS_HDSRF)) - { - } - + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + /* select PLL as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_PLLP; @@ -687,7 +671,7 @@ static void system_clock_200m_irc16m(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable IRC16M */ RCU_CTL |= RCU_CTL_IRC16MEN; @@ -695,15 +679,14 @@ static void system_clock_200m_irc16m(void) do{ timeout++; stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB); - } - while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout)); + }while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout)); /* if fail */ if(0U == (RCU_CTL & RCU_CTL_IRC16MSTB)){ - while(1){ - } + while(1){ + } } - + RCU_APB1EN |= RCU_APB1EN_PMUEN; PMU_CTL |= PMU_CTL_LDOVS; @@ -715,7 +698,7 @@ static void system_clock_200m_irc16m(void) /* APB1 = AHB/4 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - /* Configure the main PLL, PLL_M = 16, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */ + /* Configure the main PLL, PSC = 16, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */ RCU_PLL = (16U | (400U << 6U) | (((2U >> 1U) - 1U) << 16U) | (RCU_PLLSRC_IRC16M) | (9U << 24U)); @@ -725,19 +708,17 @@ static void system_clock_200m_irc16m(void) /* wait until PLL is stable */ while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ } - + /* Enable the high-drive to extend the clock frequency to 200 Mhz */ PMU_CTL |= PMU_CTL_HDEN; - while(0U == (PMU_CS & PMU_CS_HDRF)) - { + while(0U == (PMU_CS & PMU_CS_HDRF)){ } - + /* select the high-drive mode */ PMU_CTL |= PMU_CTL_HDS; - while(0U == (PMU_CS & PMU_CS_HDSRF)) - { - } - + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + /* select PLL as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_PLLP; @@ -758,7 +739,7 @@ static void system_clock_200m_8m_hxtal(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable HXTAL */ RCU_CTL |= RCU_CTL_HXTALEN; @@ -766,15 +747,14 @@ static void system_clock_200m_8m_hxtal(void) do{ timeout++; stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - } - while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); /* if fail */ if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } + while(1){ + } } - + RCU_APB1EN |= RCU_APB1EN_PMUEN; PMU_CTL |= PMU_CTL_LDOVS; @@ -786,7 +766,7 @@ static void system_clock_200m_8m_hxtal(void) /* APB1 = AHB/4 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - /* Configure the main PLL, PLL_M = 8, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */ + /* Configure the main PLL, PSC = 8, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */ RCU_PLL = (8U | (400U << 6U) | (((2U >> 1U) - 1U) << 16U) | (RCU_PLLSRC_HXTAL) | (9U << 24U)); @@ -796,19 +776,17 @@ static void system_clock_200m_8m_hxtal(void) /* wait until PLL is stable */ while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ } - + /* Enable the high-drive to extend the clock frequency to 200 Mhz */ PMU_CTL |= PMU_CTL_HDEN; - while(0U == (PMU_CS & PMU_CS_HDRF)) - { + while(0U == (PMU_CS & PMU_CS_HDRF)){ } - + /* select the high-drive mode */ PMU_CTL |= PMU_CTL_HDS; - while(0U == (PMU_CS & PMU_CS_HDSRF)) - { - } - + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + /* select PLL as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_PLLP; @@ -829,7 +807,7 @@ static void system_clock_200m_25m_hxtal(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable HXTAL */ RCU_CTL |= RCU_CTL_HXTALEN; @@ -837,15 +815,14 @@ static void system_clock_200m_25m_hxtal(void) do{ timeout++; stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - } - while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); /* if fail */ if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } + while(1){ + } } - + RCU_APB1EN |= RCU_APB1EN_PMUEN; PMU_CTL |= PMU_CTL_LDOVS; @@ -857,7 +834,7 @@ static void system_clock_200m_25m_hxtal(void) /* APB1 = AHB/4 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - /* Configure the main PLL, PLL_M = 25, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */ + /* Configure the main PLL, PSC = 25, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */ RCU_PLL = (25U | (400U << 6U) | (((2U >> 1U) - 1U) << 16U) | (RCU_PLLSRC_HXTAL) | (9U << 24U)); @@ -867,19 +844,17 @@ static void system_clock_200m_25m_hxtal(void) /* wait until PLL is stable */ while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ } - + /* Enable the high-drive to extend the clock frequency to 200 Mhz */ PMU_CTL |= PMU_CTL_HDEN; - while(0U == (PMU_CS & PMU_CS_HDRF)) - { + while(0U == (PMU_CS & PMU_CS_HDRF)){ } - + /* select the high-drive mode */ PMU_CTL |= PMU_CTL_HDS; - while(0U == (PMU_CS & PMU_CS_HDSRF)) - { - } - + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + /* select PLL as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_PLLP; @@ -900,7 +875,7 @@ void SystemCoreClockUpdate (void) { uint32_t sws; uint32_t pllpsc, plln, pllsel, pllp, ck_src, idx, clk_exp; - + /* exponent of AHB, APB1 and APB2 clock divider */ const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; diff --git a/bsp/gd32450z-eval/Libraries/CMSIS/core_cm4.h b/bsp/gd32450z-eval/Libraries/CMSIS/core_cm4.h index d82841442c..e3cd89f728 100644 --- a/bsp/gd32450z-eval/Libraries/CMSIS/core_cm4.h +++ b/bsp/gd32450z-eval/Libraries/CMSIS/core_cm4.h @@ -100,7 +100,7 @@ #define __INLINE inline /*!< inline keyword for TASKING Compiler */ #define __STATIC_INLINE static inline -#elif defined ( __CSMC__ ) /* Cosmic */ +#elif defined ( __CSMC__ ) /* Cosmic */ #define __packed #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ @@ -170,8 +170,8 @@ #define __FPU_USED 0 #endif -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser #if (__FPU_PRESENT == 1) #define __FPU_USED 1 #else diff --git a/bsp/gd32450z-eval/Libraries/CMSIS/core_cmFunc.h b/bsp/gd32450z-eval/Libraries/CMSIS/core_cmFunc.h index b6ad0a4c5f..834bd17645 100644 --- a/bsp/gd32450z-eval/Libraries/CMSIS/core_cmFunc.h +++ b/bsp/gd32450z-eval/Libraries/CMSIS/core_cmFunc.h @@ -552,7 +552,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t v /** \brief Set Base Priority with condition This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. + or the new value increases the BASEPRI priority level. \param [in] basePri Base Priority value to set */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_adc.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_adc.h index 694428f07c..4f6020a50a 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_adc.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_adc.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_adc.h - \brief definitions for the ADC + \file gd32f4xx_adc.h + \brief definitions for the ADC + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_ADC_H @@ -68,7 +93,7 @@ #define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */ #define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */ #define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */ -#define ADC_CTL0_ROVFIE BIT(26) /*!< interrupt enable for ROVF */ +#define ADC_CTL0_ROVFIE BIT(26) /*!< interrupt enable for ROVF */ /* ADC_CTL1 */ #define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */ @@ -152,65 +177,6 @@ #define ADC_SYNCDATA_SYNCDATA1 BITS(16,31) /*!< regular data2 in ADC synchronization mode */ /* constants definitions */ -/* ADC channel group definitions */ -#define ADC_REGULAR_CHANNEL ((uint8_t)0x00U) /*!< adc regular channel group */ -#define ADC_INSERTED_CHANNEL ((uint8_t)0x01U) /*!< adc inserted channel group */ -#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< both regular and inserted channel group */ - -/* external trigger mode for regular and inserted channel */ -#define EXTERNAL_TRIGGER_DISABLE ((uint32_t)0x00000000U) /*!< external trigger disable */ -#define EXTERNAL_TRIGGER_RISING ((uint32_t)0x00000001U) /*!< rising edge of external trigger */ -#define EXTERNAL_TRIGGER_FALLING ((uint32_t)0x00000002U) /*!< falling edge of external trigger */ -#define EXTERNAL_TRIGGER_RISING_FALLING ((uint32_t)0x00000003U) /*!< rising and falling edge of external trigger */ - -/* ADC inserted channel definitions */ -#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< adc inserted channel 0 */ -#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< adc inserted channel 1 */ -#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< adc inserted channel 2 */ -#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< adc inserted channel 3 */ - -/* ADC special function definitions */ -#define ADC_SCAN_MODE ((uint8_t)0x00U) /*!< scan mode */ -#define ADC_INSERTED_CHANNEL_AUTO ((uint8_t)0x01U) /*!< inserted channel group convert automatically */ -#define ADC_VBAT_CHANNEL_SWITCH ((uint8_t)0x02U) /*!< VBAT channel */ -#define ADC_TEMP_VREF_CHANNEL_SWITCH ((uint8_t)0x03U) /*!< Vref and Vtemp channel */ -#define ADC_CONTINUOUS_MODE ((uint8_t)0x04U) /*!< continuous mode */ - -/* ADC channel definitions */ -#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */ -#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */ -#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */ -#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */ -#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */ -#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */ -#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */ -#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */ -#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */ -#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */ -#define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */ -#define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */ -#define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */ -#define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */ -#define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */ -#define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */ -#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */ -#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */ -#define ADC_CHANNEL_18 ((uint8_t)0x12U) /*!< ADC channel 18 */ - -/* ADC channel sample time */ -#define ADC_SAMPLETIME_3 ((uint8_t)0x00U) /*!< 3 sampling cycles */ -#define ADC_SAMPLETIME_15 ((uint8_t)0x01U) /*!< 15 sampling cycles */ -#define ADC_SAMPLETIME_28 ((uint8_t)0x02U) /*!< 28 sampling cycles */ -#define ADC_SAMPLETIME_56 ((uint8_t)0x03U) /*!< 56 sampling cycles */ -#define ADC_SAMPLETIME_84 ((uint8_t)0x04U) /*!< 84 sampling cycles */ -#define ADC_SAMPLETIME_112 ((uint8_t)0x05U) /*!< 112 sampling cycles */ -#define ADC_SAMPLETIME_144 ((uint8_t)0x06U) /*!< 144 sampling cycles */ -#define ADC_SAMPLETIME_480 ((uint8_t)0x07U) /*!< 480 sampling cycles */ - -/* ADC data alignment */ -#define ADC_DATAALIGN_RIGHT ((uint8_t)0x00U) /*!< LSB alignment */ -#define ADC_DATAALIGN_LEFT ((uint8_t)0x01U) /*!< MSB alignment */ - /* ADC status flag */ #define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */ #define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */ @@ -219,18 +185,43 @@ #define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */ #define ADC_FLAG_ROVF ADC_STAT_ROVF /*!< regular data register overflow */ -/* ADC interrupt flag */ -#define ADC_INT_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */ -#define ADC_INT_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */ -#define ADC_INT_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */ -#define ADC_INT_ROVF ADC_STAT_ROVF /*!< regular data register overflow */ +/* adc_ctl0 register value */ +#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */ -/* ADC resolution definitions */ -#define CTL0_DRES(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) -#define ADC_RESOLUTION_12B CTL0_DRES(0) /*!< 12-bit ADC resolution */ -#define ADC_RESOLUTION_10B CTL0_DRES(1) /*!< 10-bit ADC resolution */ -#define ADC_RESOLUTION_8B CTL0_DRES(2) /*!< 8-bit ADC resolution */ -#define ADC_RESOLUTION_6B CTL0_DRES(3) /*!< 6-bit ADC resolution */ +/* ADC special function definitions */ +#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */ +#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */ +#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */ + +/* temperature sensor channel, internal reference voltage channel, VBAT channel */ +#define ADC_VBAT_CHANNEL_SWITCH ADC_SYNCCTL_VBATEN /*!< VBAT channel */ +#define ADC_TEMP_VREF_CHANNEL_SWITCH ADC_SYNCCTL_TSVREN /*!< Vref and Vtemp channel */ + +/* ADC synchronization mode */ +#define SYNCCTL_SYNCM(regval) (BITS(0,4) & ((uint32_t)(regval))) /*!< write value to ADC_CTL0_SYNCM bit field */ +#define ADC_SYNC_MODE_INDEPENDENT SYNCCTL_SYNCM(0) /*!< ADC synchronization mode disabled.All the ADCs work independently */ +#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL SYNCCTL_SYNCM(1) /*!< ADC0 and ADC1 work in combined regular parallel & inserted parallel mode. ADC2 works independently */ +#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION SYNCCTL_SYNCM(2) /*!< ADC0 and ADC1 work in combined regular parallel & trigger rotation mode. ADC2 works independently */ +#define ADC_DAUL_INSERTED_PARALLEL SYNCCTL_SYNCM(5) /*!< ADC0 and ADC1 work in inserted parallel mode. ADC2 works independently */ +#define ADC_DAUL_REGULAL_PARALLEL SYNCCTL_SYNCM(6) /*!< ADC0 and ADC1 work in regular parallel mode. ADC2 works independently */ +#define ADC_DAUL_REGULAL_FOLLOW_UP SYNCCTL_SYNCM(7) /*!< ADC0 and ADC1 work in follow-up mode. ADC2 works independently */ +#define ADC_DAUL_INSERTED_TRRIGGER_ROTATION SYNCCTL_SYNCM(9) /*!< ADC0 and ADC1 work in trigger rotation mode. ADC2 works independently */ +#define ADC_ALL_REGULAL_PARALLEL_INSERTED_PARALLEL SYNCCTL_SYNCM(17) /*!< all ADCs work in combined regular parallel & inserted parallel mode */ +#define ADC_ALL_REGULAL_PARALLEL_INSERTED_ROTATION SYNCCTL_SYNCM(18) /*!< all ADCs work in combined regular parallel & trigger rotation mode */ +#define ADC_ALL_INSERTED_PARALLEL SYNCCTL_SYNCM(21) /*!< all ADCs work in inserted parallel mode */ +#define ADC_ALL_REGULAL_PARALLEL SYNCCTL_SYNCM(22) /*!< all ADCs work in regular parallel mode */ +#define ADC_ALL_REGULAL_FOLLOW_UP SYNCCTL_SYNCM(23) /*!< all ADCs work in follow-up mode */ +#define ADC_ALL_INSERTED_TRRIGGER_ROTATION SYNCCTL_SYNCM(25) /*!< all ADCs work in trigger rotation mode */ + +/* ADC data alignment */ +#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< LSB alignment */ +#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */ + +/* external trigger mode for regular and inserted channel */ +#define EXTERNAL_TRIGGER_DISABLE ((uint32_t)0x00000000U) /*!< external trigger disable */ +#define EXTERNAL_TRIGGER_RISING ((uint32_t)0x00000001U) /*!< rising edge of external trigger */ +#define EXTERNAL_TRIGGER_FALLING ((uint32_t)0x00000002U) /*!< falling edge of external trigger */ +#define EXTERNAL_TRIGGER_RISING_FALLING ((uint32_t)0x00000003U) /*!< rising and falling edge of external trigger */ /* ADC external trigger select for regular channel */ #define CTL1_ETSRC(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) @@ -270,32 +261,111 @@ #define ADC_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(14) /*!< timer7 capture compare 3 */ #define ADC_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(15) /*!< external interrupt line 15 */ -/* ADC oversampling mode */ -#define ADC_OVERSAMPLING_ALL_CONVERT 0U /*!< all oversampled conversions for a channel are done consecutively after a trigger */ -#define ADC_OVERSAMPLING_ONE_CONVERT 1U /*!< each oversampled conversion for a channel needs a trigger */ +/* ADC channel sample time */ +#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */ +#define ADC_SAMPLETIME_3 SAMPTX_SPT(0) /*!< 3 sampling cycles */ +#define ADC_SAMPLETIME_15 SAMPTX_SPT(1) /*!< 15 sampling cycles */ +#define ADC_SAMPLETIME_28 SAMPTX_SPT(2) /*!< 28 sampling cycles */ +#define ADC_SAMPLETIME_56 SAMPTX_SPT(3) /*!< 56 sampling cycles */ +#define ADC_SAMPLETIME_84 SAMPTX_SPT(4) /*!< 84 sampling cycles */ +#define ADC_SAMPLETIME_112 SAMPTX_SPT(5) /*!< 112 sampling cycles */ +#define ADC_SAMPLETIME_144 SAMPTX_SPT(6) /*!< 144 sampling cycles */ +#define ADC_SAMPLETIME_480 SAMPTX_SPT(7) /*!< 480 sampling cycles */ -/* ADC oversampling shift */ -#define OVCTL_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) -#define ADC_OVERSAMPLING_SHIFT_NONE OVCTL_OVSS(0) /*!< no oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_1B OVCTL_OVSS(1) /*!< 1-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_2B OVCTL_OVSS(2) /*!< 2-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_3B OVCTL_OVSS(3) /*!< 3-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_4B OVCTL_OVSS(4) /*!< 4-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_5B OVCTL_OVSS(5) /*!< 5-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_6B OVCTL_OVSS(6) /*!< 6-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_7B OVCTL_OVSS(7) /*!< 7-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_8B OVCTL_OVSS(8) /*!< 8-bit oversampling shift */ +/* adc_ioffx register value */ +#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */ -/* ADC oversampling ratio */ -#define OVCTL_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) -#define ADC_OVERSAMPLING_RATIO_MUL2 OVCTL_OVSR(0) /*!< oversampling ratio multiple 2 */ -#define ADC_OVERSAMPLING_RATIO_MUL4 OVCTL_OVSR(1) /*!< oversampling ratio multiple 4 */ -#define ADC_OVERSAMPLING_RATIO_MUL8 OVCTL_OVSR(2) /*!< oversampling ratio multiple 8 */ -#define ADC_OVERSAMPLING_RATIO_MUL16 OVCTL_OVSR(3) /*!< oversampling ratio multiple 16 */ -#define ADC_OVERSAMPLING_RATIO_MUL32 OVCTL_OVSR(4) /*!< oversampling ratio multiple 32 */ -#define ADC_OVERSAMPLING_RATIO_MUL64 OVCTL_OVSR(5) /*!< oversampling ratio multiple 64 */ -#define ADC_OVERSAMPLING_RATIO_MUL128 OVCTL_OVSR(6) /*!< oversampling ratio multiple 128 */ -#define ADC_OVERSAMPLING_RATIO_MUL256 OVCTL_OVSR(7) /*!< oversampling ratio multiple 256 */ +/* adc_wdht register value */ +#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */ + +/* adc_wdlt register value */ +#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */ + +/* adc_rsqx register value */ +#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */ + +/* adc_isq register value */ +#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */ + +/* adc_ovsampctl register value */ +/* ADC resolution */ +#define CTL0_DRES(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) /*!< write value to ADC_CTL0_DRES bit field */ +#define ADC_RESOLUTION_12B CTL0_DRES(0) /*!< 12-bit ADC resolution */ +#define ADC_RESOLUTION_10B CTL0_DRES(1) /*!< 10-bit ADC resolution */ +#define ADC_RESOLUTION_8B CTL0_DRES(2) /*!< 8-bit ADC resolution */ +#define ADC_RESOLUTION_6B CTL0_DRES(3) /*!< 6-bit ADC resolution */ + +/* oversampling shift */ +#define OVSAMPCTL_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) /*!< write value to ADC_OVSAMPCTL_OVSS bit field */ +#define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0) /*!< no oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1) /*!< 1-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2) /*!< 2-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_3B OVSAMPCTL_OVSS(3) /*!< 3-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_4B OVSAMPCTL_OVSS(4) /*!< 4-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_5B OVSAMPCTL_OVSS(5) /*!< 5-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_6B OVSAMPCTL_OVSS(6) /*!< 6-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_7B OVSAMPCTL_OVSS(7) /*!< 7-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8) /*!< 8-bit oversampling shift */ + +/* oversampling ratio */ +#define OVSAMPCTL_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ADC_OVSAMPCTL_OVSR bit field */ +#define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0) /*!< oversampling ratio multiple 2 */ +#define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1) /*!< oversampling ratio multiple 4 */ +#define ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2) /*!< oversampling ratio multiple 8 */ +#define ADC_OVERSAMPLING_RATIO_MUL16 OVSAMPCTL_OVSR(3) /*!< oversampling ratio multiple 16 */ +#define ADC_OVERSAMPLING_RATIO_MUL32 OVSAMPCTL_OVSR(4) /*!< oversampling ratio multiple 32 */ +#define ADC_OVERSAMPLING_RATIO_MUL64 OVSAMPCTL_OVSR(5) /*!< oversampling ratio multiple 64 */ +#define ADC_OVERSAMPLING_RATIO_MUL128 OVSAMPCTL_OVSR(6) /*!< oversampling ratio multiple 128 */ +#define ADC_OVERSAMPLING_RATIO_MUL256 OVSAMPCTL_OVSR(7) /*!< oversampling ratio multiple 256 */ + +/* triggered Oversampling */ +#define ADC_OVERSAMPLING_ALL_CONVERT ((uint32_t)0x00000000U) /*!< all oversampled conversions for a channel are done consecutively after a trigger */ +#define ADC_OVERSAMPLING_ONE_CONVERT ADC_OVSAMPCTL_TOVS /*!< each oversampled conversion for a channel needs a trigger */ + +/* ADC channel group definitions */ +#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< adc regular channel group */ +#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< adc inserted channel group */ +#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */ +#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */ + +/* ADC inserted channel definitions */ +#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< adc inserted channel 0 */ +#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< adc inserted channel 1 */ +#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< adc inserted channel 2 */ +#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< adc inserted channel 3 */ + +/* ADC channel definitions */ +#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */ +#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */ +#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */ +#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */ +#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */ +#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */ +#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */ +#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */ +#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */ +#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */ +#define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */ +#define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */ +#define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */ +#define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */ +#define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */ +#define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */ +#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */ +#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */ +#define ADC_CHANNEL_18 ((uint8_t)0x12U) /*!< ADC channel 18 */ + +/* ADC interrupt flag */ +#define ADC_INT_WDE ADC_CTL0_WDEIE /*!< analog watchdog event interrupt */ +#define ADC_INT_EOC ADC_CTL0_EOCIE /*!< end of group conversion interrupt */ +#define ADC_INT_EOIC ADC_CTL0_EOICIE /*!< end of inserted group conversion interrupt */ +#define ADC_INT_ROVF ADC_CTL0_ROVFIE /*!< regular data register overflow */ + +/* ADC interrupt flag */ +#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */ +#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */ +#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */ +#define ADC_INT_FLAG_ROVF ADC_STAT_ROVF /*!< regular data register overflow */ /* configure the ADC clock for all the ADCs */ #define SYNCCTL_ADCCK(regval) (BITS(16,18) & ((uint32_t)(regval) << 16)) @@ -308,21 +378,6 @@ #define ADC_ADCCK_HCLK_DIV10 SYNCCTL_ADCCK(6) /*!< HCLK div10 */ #define ADC_ADCCK_HCLK_DIV20 SYNCCTL_ADCCK(7) /*!< HCLK div20 */ -/* ADC synchronization mode */ -#define ADC_SYNC_MODE_INDEPENDENT ((uint32_t)0x00000000U) /*!< ADC synchronization mode disabled.All the ADCs work independently */ -#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL ((uint32_t)0x00000001U) /*!< ADC0 and ADC1 work in combined regular parallel & inserted parallel mode. ADC2 works independently */ -#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION ((uint32_t)0x00000002U) /*!< ADC0 and ADC1 work in combined regular parallel & trigger rotation mode. ADC2 works independently */ -#define ADC_DAUL_INSERTED_PARALLEL ((uint32_t)0x00000005U) /*!< ADC0 and ADC1 work in inserted parallel mode. ADC2 works independently */ -#define ADC_DAUL_REGULAL_PARALLEL ((uint32_t)0x00000006U) /*!< ADC0 and ADC1 work in regular parallel mode. ADC2 works independently */ -#define ADC_DAUL_REGULAL_FOLLOW_UP ((uint32_t)0x00000007U) /*!< ADC0 and ADC1 work in follow-up mode. ADC2 works independently */ -#define ADC_DAUL_INSERTED_TRRIGGER_ROTATION ((uint32_t)0x00000009U) /*!< ADC0 and ADC1 work in trigger rotation mode. ADC2 works independently */ -#define ADC_ALL_REGULAL_PARALLEL_INSERTED_PARALLEL ((uint32_t)0x00000011U) /*!< all ADCs work in combined regular parallel & inserted parallel mode */ -#define ADC_ALL_REGULAL_PARALLEL_INSERTED_ROTATION ((uint32_t)0x00000012U) /*!< all ADCs work in combined regular parallel & trigger rotation mode */ -#define ADC_ALL_INSERTED_PARALLEL ((uint32_t)0x00000015U) /*!< all ADCs work in inserted parallel mode */ -#define ADC_ALL_REGULAL_PARALLEL ((uint32_t)0x00000016U) /*!< all ADCs work in regular parallel mode */ -#define ADC_ALL_REGULAL_FOLLOW_UP ((uint32_t)0x00000017U) /*!< all ADCs work in follow-up mode */ -#define ADC_ALL_INSERTED_TRRIGGER_ROTATION ((uint32_t)0x00000019U) /*!< all ADCs work in trigger rotation mode */ - /* ADC synchronization delay */ #define ADC_SYNC_DELAY_5CYCLE ((uint32_t)0x00000000U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 5 ADC clock cycles. */ #define ADC_SYNC_DELAY_6CYCLE ((uint32_t)0x00000100U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 6 ADC clock cycles. */ @@ -351,98 +406,97 @@ #define ADC_EOC_SET_CONVERSION ((uint8_t)0x01U) /*!< at the end of each regular conversion, the EOC bit is set */ /* function declarations */ -/* ADC reset */ +/* initialization config */ +/* reset ADC */ void adc_deinit(void); +/* configure the ADC clock for all the ADCs */ +void adc_clock_config(uint32_t prescaler); +/* enable or disable ADC special function */ +void adc_special_function_config(uint32_t adc_periph , uint32_t function , ControlStatus newvalue); +/* configure ADC data alignment */ +void adc_data_alignment_config(uint32_t adc_periph , uint32_t data_alignment); /* enable ADC interface */ void adc_enable(uint32_t adc_periph); /* disable ADC interface */ void adc_disable(uint32_t adc_periph); -/* ADC data alignment config */ -void adc_data_alignment_config(uint32_t adc_periph , uint8_t data_alignment); -/* ADC resolution config */ -void adc_resolution_config(uint32_t adc_periph , uint32_t resolution); /* ADC calibration and reset calibration */ void adc_calibration_enable(uint32_t adc_periph); -/* ADC discontinuous mode config */ -void adc_discontinuous_mode_config(uint32_t adc_periph , uint8_t adc_channel_group , uint8_t length); -/* config end of conversion mode */ -void adc_end_of_conversion_config(uint32_t adc_periph , uint8_t end_selection); -/* ADC special function enable or disable */ -void adc_special_function_config(uint32_t adc_periph , uint8_t function , ControlStatus newvalue); -/* configure the ADC clock for all the ADCs */ -void adc_clock_config(uint32_t prescaler); +/* configure temperature sensor and internal reference voltage channel or VBAT channel function */ +void adc_channel_16_to_18(uint32_t function, ControlStatus newvalue); +/* configure ADC resolution */ +void adc_resolution_config(uint32_t adc_periph, uint32_t resolution); +/* configure ADC oversample mode */ +void adc_oversample_mode_config(uint32_t adc_periph, uint32_t mode, uint16_t shift, uint8_t ratio); +/* enable ADC oversample mode */ +void adc_oversample_mode_enable(uint32_t adc_periph); +/* disable ADC oversample mode */ +void adc_oversample_mode_disable(uint32_t adc_periph); -/* ADC channel */ -/* configure the ADC clock for all the ADCs */ -void adc_channel_16_to_18(uint8_t function,ControlStatus newvalue); -/* config the length of regular channel group or inserted channel group */ -void adc_channel_length_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t length); - -/* ADC trigger */ -/* ADC external trigger enable */ -void adc_external_trigger_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t trigger_mode); -/* ADC external trigger source config */ -void adc_external_trigger_source_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t external_trigger_source); -/* ADC software trigger enable */ -void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_channel_group); - -/* ADC flag and interrupt */ -/* get the ADC flag bits */ -FlagStatus adc_flag_get(uint32_t adc_periph , uint32_t adc_flag); -/* clear the ADC flag bits */ -void adc_flag_clear(uint32_t adc_periph , uint32_t adc_flag); -/* get the ADC interrupt bits */ -FlagStatus adc_interrupt_flag_get(uint32_t adc_periph , uint32_t adc_interrupt); -/* clear the ADC flag */ -void adc_interrupt_flag_clear(uint32_t adc_periph , uint32_t adc_interrupt); -/* ADC interrupt enable */ -void adc_interrupt_enable(uint32_t adc_periph , uint32_t adc_interrupt); -/* ADC interrupt disable */ -void adc_interrupt_disable(uint32_t adc_periph , uint32_t adc_interrupt); - -/* ADC analog watchdog */ -/* ADC analog watchdog single channel disable */ -void adc_watchdog_single_channel_disable(uint32_t adc_periph ); -/* ADC analog watchdog single channel enable */ -void adc_watchdog_single_channel_enable(uint32_t adc_periph , uint8_t adc_channel); -/* adc analog watchdog group channel config */ -void adc_watchdog_enable(uint32_t adc_periph , uint8_t adc_channel_group); -/* ADC analog watchdog disable */ -void adc_watchdog_disable(uint32_t adc_periph , uint8_t adc_channel_group); -/* ADC analog watchdog threshold config */ -void adc_watchdog_threshold_config(uint32_t adc_periph , uint16_t low_threshold , uint16_t high_threshold); - -/* regular channel */ -/* ADC regular channel config */ -void adc_regular_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time); -/* ADC regular group data register read */ -uint16_t adc_regular_data_read(uint32_t adc_periph); - -/* inserted channel */ -/* ADC inserted channel config */ -void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint8_t sample_time); -/* ADC inserted channel offset config */ -void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_channel , uint16_t offset); -/* ADC inserted group data register read */ -uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel); - -/* ADC DMA */ -/* DMA request enable */ +/* DMA config */ +/* enable DMA request */ void adc_dma_mode_enable(uint32_t adc_periph); -/* DMA request disable */ +/* disable DMA request */ void adc_dma_mode_disable(uint32_t adc_periph); /* when DMA=1, the DMA engine issues a request at end of each regular conversion */ void adc_dma_request_after_last_enable(uint32_t adc_periph); /* the DMA engine is disabled after the end of transfer signal from DMA controller is detected */ void adc_dma_request_after_last_disable(uint32_t adc_periph); -/* ADC oversample */ -/* ADC oversample mode config */ -void adc_oversample_mode_config(uint32_t adc_periph , uint8_t mode , uint16_t shift , uint8_t ratio); -/* ADC oversample mode enable */ -void adc_oversample_mode_enable(uint32_t adc_periph ); -/* ADC oversample mode disable */ -void adc_oversample_mode_disable(uint32_t adc_periph ); +/* regular group and inserted group config */ +/* configure ADC discontinuous mode */ +void adc_discontinuous_mode_config(uint32_t adc_periph , uint8_t adc_channel_group , uint8_t length); +/* configure the length of regular channel group or inserted channel group */ +void adc_channel_length_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t length); +/* configure ADC regular channel */ +void adc_regular_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time); +/* configure ADC inserted channel */ +void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time); +/* configure ADC inserted channel offset */ +void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_channel , uint16_t offset); +/* configure ADC external trigger source */ +void adc_external_trigger_source_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t external_trigger_source); +/* enable ADC external trigger */ +void adc_external_trigger_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t trigger_mode); +/* enable ADC software trigger */ +void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_channel_group); +/* configure end of conversion mode */ +void adc_end_of_conversion_config(uint32_t adc_periph , uint8_t end_selection); + +/* get channel data */ +/* read ADC regular group data register */ +uint16_t adc_regular_data_read(uint32_t adc_periph); +/* read ADC inserted group data register */ +uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel); + +/* watchdog config */ +/* disable ADC analog watchdog single channel */ +void adc_watchdog_single_channel_disable(uint32_t adc_periph ); +/* enable ADC analog watchdog single channel */ +void adc_watchdog_single_channel_enable(uint32_t adc_periph , uint8_t adc_channel); +/* configure ADC analog watchdog group channel */ +void adc_watchdog_group_channel_enable(uint32_t adc_periph , uint8_t adc_channel_group); +/* disable ADC analog watchdog */ +void adc_watchdog_disable(uint32_t adc_periph , uint8_t adc_channel_group); +/* configure ADC analog watchdog threshold */ +void adc_watchdog_threshold_config(uint32_t adc_periph , uint16_t low_threshold , uint16_t high_threshold); + +/* interrupt & flag functions */ +/* get the ADC flag bits */ +FlagStatus adc_flag_get(uint32_t adc_periph , uint32_t adc_flag); +/* clear the ADC flag bits */ +void adc_flag_clear(uint32_t adc_periph , uint32_t adc_flag); +/* get the bit state of ADCx software start conversion */ +FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph); +/* get the bit state of ADCx software inserted channel start conversion */ +FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph); +/* get the ADC interrupt bits */ +FlagStatus adc_interrupt_flag_get(uint32_t adc_periph , uint32_t adc_interrupt); +/* clear the ADC flag */ +void adc_interrupt_flag_clear(uint32_t adc_periph , uint32_t adc_interrupt); +/* enable ADC interrupt */ +void adc_interrupt_enable(uint32_t adc_periph , uint32_t adc_interrupt); +/* disable ADC interrupt */ +void adc_interrupt_disable(uint32_t adc_periph , uint32_t adc_interrupt); /* ADC synchronization */ /* configure the ADC sync mode */ @@ -455,7 +509,7 @@ void adc_sync_dma_config(uint32_t dma_mode ); void adc_sync_dma_request_after_last_enable(void); /* configure ADC sync DMA engine issues requests according to the SYNCDMA bits */ void adc_sync_dma_request_after_last_disable(void); -/* ADC sync regular data register read */ +/* read ADC sync regular data register */ uint32_t adc_sync_regular_data_read(void); #endif /* GD32F4XX_ADC_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_can.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_can.h index 2be5832462..7310f63a75 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_can.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_can.h @@ -1,12 +1,38 @@ /*! - \file gd32f4xx_can.h - \brief definitions for the CAN + \file gd32f4xx_can.h + \brief definitions for the CAN + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2019-11-27, V2.0.1, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_CAN_H @@ -42,7 +68,7 @@ #define CAN_RFIFOMI0(canx) REG32((canx) + 0x1B0U) /*!< CAN receive FIFO0 mailbox identifier register */ #define CAN_RFIFOMP0(canx) REG32((canx) + 0x1B4U) /*!< CAN receive FIFO0 mailbox property register */ #define CAN_RFIFOMDATA00(canx) REG32((canx) + 0x1B8U) /*!< CAN receive FIFO0 mailbox data0 register */ -#define CAN_RFIFOMDATA10(canx) REG32((canx) + 0x1CCU) /*!< CAN receive FIFO0 mailbox data1 register */ +#define CAN_RFIFOMDATA10(canx) REG32((canx) + 0x1BCU) /*!< CAN receive FIFO0 mailbox data1 register */ #define CAN_RFIFOMI1(canx) REG32((canx) + 0x1C0U) /*!< CAN receive FIFO1 mailbox identifier register */ #define CAN_RFIFOMP1(canx) REG32((canx) + 0x1C4U) /*!< CAN receive FIFO1 mailbox property register */ #define CAN_RFIFOMDATA01(canx) REG32((canx) + 0x1C8U) /*!< CAN receive FIFO1 mailbox data0 register */ @@ -110,20 +136,20 @@ #define CAN_F27DATA1(canx) REG32((canx) + 0x31CU) /*!< CAN filter 27 data 1 register */ /* CAN transmit mailbox bank */ -#define CAN_TMI(canx, bank) REG32((canx) + 0x180U + ((bank) * 0x10U)) /*!< CAN transmit mailbox identifier register */ -#define CAN_TMP(canx, bank) REG32((canx) + 0x184U + ((bank) * 0x10U)) /*!< CAN transmit mailbox property register */ -#define CAN_TMDATA0(canx, bank) REG32((canx) + 0x188U + ((bank) * 0x10U)) /*!< CAN transmit mailbox data0 register */ -#define CAN_TMDATA1(canx, bank) REG32((canx) + 0x18CU + ((bank) * 0x10U)) /*!< CAN transmit mailbox data1 register */ +#define CAN_TMI(canx, bank) REG32((canx) + 0x180U + ((bank) * 0x10U)) /*!< CAN transmit mailbox identifier register */ +#define CAN_TMP(canx, bank) REG32((canx) + 0x184U + ((bank) * 0x10U)) /*!< CAN transmit mailbox property register */ +#define CAN_TMDATA0(canx, bank) REG32((canx) + 0x188U + ((bank) * 0x10U)) /*!< CAN transmit mailbox data0 register */ +#define CAN_TMDATA1(canx, bank) REG32((canx) + 0x18CU + ((bank) * 0x10U)) /*!< CAN transmit mailbox data1 register */ /* CAN filter bank */ -#define CAN_FDATA0(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x0U) /*!< CAN filter data 0 register */ -#define CAN_FDATA1(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x4U) /*!< CAN filter data 1 register */ +#define CAN_FDATA0(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x0U) /*!< CAN filter data 0 register */ +#define CAN_FDATA1(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x4U) /*!< CAN filter data 1 register */ /* CAN receive fifo mailbox bank */ -#define CAN_RFIFOMI(canx, bank) REG32((canx) + 0x1B0U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox identifier register */ -#define CAN_RFIFOMP(canx, bank) REG32((canx) + 0x1B4U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox property register */ -#define CAN_RFIFOMDATA0(canx, bank) REG32((canx) + 0x1B8U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data0 register */ -#define CAN_RFIFOMDATA1(canx, bank) REG32((canx) + 0x1BCU + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data1 register */ +#define CAN_RFIFOMI(canx, bank) REG32((canx) + 0x1B0U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox identifier register */ +#define CAN_RFIFOMP(canx, bank) REG32((canx) + 0x1B4U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox property register */ +#define CAN_RFIFOMDATA0(canx, bank) REG32((canx) + 0x1B8U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data0 register */ +#define CAN_RFIFOMDATA1(canx, bank) REG32((canx) + 0x1BCU + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data1 register */ /* bits definitions */ /* CAN_CTL */ @@ -198,7 +224,7 @@ #define CAN_INTEN_BOIE BIT(10) /*!< bus-off interrupt enable */ #define CAN_INTEN_ERRNIE BIT(11) /*!< error number interrupt enable */ #define CAN_INTEN_ERRIE BIT(15) /*!< error interrupt enable */ -#define CAN_INTEN_WUIE BIT(16) /*!< wakeup interrupt enable */ +#define CAN_INTEN_WIE BIT(16) /*!< wakeup interrupt enable */ #define CAN_INTEN_SLPWIE BIT(17) /*!< sleep working interrupt enable */ /* CAN_ERR */ @@ -280,11 +306,19 @@ /* CAN_FW */ #define CAN_FW_FW(regval) BIT(regval) /*!< filter working */ +/* CAN_FxDATAy */ +#define CAN_FDATA_FD(regval) BIT(regval) /*!< filter data */ + /* consts definitions */ /* define the CAN bit position and its register index offset */ -#define CAN_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define CAN_REG_VAL(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 6))) -#define CAN_BIT_POS(val) ((uint32_t)(val) & 0x1FU) +#define CAN_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define CAN_REG_VAL(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 6))) +#define CAN_BIT_POS(val) ((uint32_t)(val) & 0x1FU) + +#define CAN_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1)) +#define CAN_REG_VALS(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 12))) +#define CAN_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU) +#define CAN_BIT_POS1(val) ((uint32_t)(val) & 0x1FU) /* register offset */ #define STAT_REG_OFFSET ((uint8_t)0x04U) /*!< STAT register offset */ @@ -296,45 +330,84 @@ /* CAN flags */ typedef enum { + /* flags in STAT register */ + CAN_FLAG_RXL = CAN_REGIDX_BIT(STAT_REG_OFFSET, 11U), /*!< RX level */ + CAN_FLAG_LASTRX = CAN_REGIDX_BIT(STAT_REG_OFFSET, 10U), /*!< last sample value of RX pin */ + CAN_FLAG_RS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 9U), /*!< receiving state */ + CAN_FLAG_TS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 8U), /*!< transmitting state */ + CAN_FLAG_SLPIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 4U), /*!< status change flag of entering sleep working mode */ + CAN_FLAG_WUIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 3U), /*!< status change flag of wakeup from sleep working mode */ + CAN_FLAG_ERRIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 2U), /*!< error flag */ + CAN_FLAG_SLPWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 1U), /*!< sleep working state */ + CAN_FLAG_IWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 0U), /*!< initial working state */ /* flags in TSTAT register */ - CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U), /*!< mailbox 2 transmit error */ - CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U), /*!< mailbox 1 transmit error */ - CAN_FLAG_MTE0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 3U), /*!< mailbox 0 transmit error */ - CAN_FLAG_MTF2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 16U), /*!< mailbox 2 transmit finished */ - CAN_FLAG_MTF1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 8U), /*!< mailbox 1 transmit finished */ - CAN_FLAG_MTF0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 0U), /*!< mailbox 0 transmit finished */ + CAN_FLAG_TMLS2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 31U), /*!< transmit mailbox 2 last sending in Tx FIFO */ + CAN_FLAG_TMLS1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 30U), /*!< transmit mailbox 1 last sending in Tx FIFO */ + CAN_FLAG_TMLS0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 29U), /*!< transmit mailbox 0 last sending in Tx FIFO */ + CAN_FLAG_TME2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 28U), /*!< transmit mailbox 2 empty */ + CAN_FLAG_TME1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 27U), /*!< transmit mailbox 1 empty */ + CAN_FLAG_TME0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 26U), /*!< transmit mailbox 0 empty */ + CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U), /*!< mailbox 2 transmit error */ + CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U), /*!< mailbox 1 transmit error */ + CAN_FLAG_MTE0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 3U), /*!< mailbox 0 transmit error */ + CAN_FLAG_MAL2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 18U), /*!< mailbox 2 arbitration lost */ + CAN_FLAG_MAL1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 10U), /*!< mailbox 1 arbitration lost */ + CAN_FLAG_MAL0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 2U), /*!< mailbox 0 arbitration lost */ + CAN_FLAG_MTFNERR2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 17U), /*!< mailbox 2 transmit finished with no error */ + CAN_FLAG_MTFNERR1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 9U), /*!< mailbox 1 transmit finished with no error */ + CAN_FLAG_MTFNERR0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 1U), /*!< mailbox 0 transmit finished with no error */ + CAN_FLAG_MTF2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 16U), /*!< mailbox 2 transmit finished */ + CAN_FLAG_MTF1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 8U), /*!< mailbox 1 transmit finished */ + CAN_FLAG_MTF0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 0U), /*!< mailbox 0 transmit finished */ /* flags in RFIFO0 register */ - CAN_FLAG_RFO0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 4U), /*!< receive FIFO0 overfull */ - CAN_FLAG_RFF0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 3U), /*!< receive FIFO0 full */ + CAN_FLAG_RFO0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 4U), /*!< receive FIFO0 overfull */ + CAN_FLAG_RFF0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 3U), /*!< receive FIFO0 full */ /* flags in RFIFO1 register */ - CAN_FLAG_RFO1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 4U), /*!< receive FIFO1 overfull */ - CAN_FLAG_RFF1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 3U), /*!< receive FIFO1 full */ + CAN_FLAG_RFO1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 4U), /*!< receive FIFO1 overfull */ + CAN_FLAG_RFF1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 3U), /*!< receive FIFO1 full */ /* flags in ERR register */ - CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U), /*!< bus-off error */ - CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U), /*!< passive error */ - CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U), /*!< warning error */ + CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U), /*!< bus-off error */ + CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U), /*!< passive error */ + CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U), /*!< warning error */ }can_flag_enum; /* CAN interrupt flags */ typedef enum { /* interrupt flags in STAT register */ - CAN_INT_SLPIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 4U), /*!< status change interrupt flag of sleep working mode entering */ - CAN_INT_WUIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 3U), /*!< status change interrupt flag of wakeup from sleep working mode */ - CAN_INT_ERRIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 2U), /*!< error interrupt flag */ + CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U), /*!< status change interrupt flag of sleep working mode entering */ + CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16), /*!< status change interrupt flag of wakeup from sleep working mode */ + CAN_INT_FLAG_ERRIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 2U, 15), /*!< error interrupt flag */ + /* interrupt flags in TSTAT register */ + CAN_INT_FLAG_MTF2 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 16U, 0U), /*!< mailbox 2 transmit finished interrupt flag */ + CAN_INT_FLAG_MTF1 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 8U, 0U), /*!< mailbox 1 transmit finished interrupt flag */ + CAN_INT_FLAG_MTF0 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 0U, 0U), /*!< mailbox 0 transmit finished interrupt flag */ + /* interrupt flags in RFIFO0 register */ + CAN_INT_FLAG_RFO0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 4U, 3U), /*!< receive FIFO0 overfull interrupt flag */ + CAN_INT_FLAG_RFF0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 3U, 2U), /*!< receive FIFO0 full interrupt flag */ + CAN_INT_FLAG_RFL0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 2U, 1U), /*!< receive FIFO0 not empty interrupt flag */ + /* interrupt flags in RFIFO0 register */ + CAN_INT_FLAG_RFO1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 4U, 6U), /*!< receive FIFO1 overfull interrupt flag */ + CAN_INT_FLAG_RFF1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 3U, 5U), /*!< receive FIFO1 full interrupt flag */ + CAN_INT_FLAG_RFL1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 2U, 4U), /*!< receive FIFO0 not empty interrupt flag */ + /* interrupt flags in ERR register */ + CAN_INT_FLAG_ERRN = CAN_REGIDX_BITS(ERR_REG_OFFSET, 3U, 11U), /*!< error number interrupt flag */ + CAN_INT_FLAG_BOERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 2U, 10U), /*!< bus-off error interrupt flag */ + CAN_INT_FLAG_PERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 1U, 9U), /*!< passive error interrupt flag */ + CAN_INT_FLAG_WERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 0U, 8U), /*!< warning error interrupt flag */ }can_interrupt_flag_enum; /* CAN initiliaze parameters struct */ typedef struct { - uint8_t working_mode; /*!< CAN working mode */ + uint8_t working_mode; /*!< CAN working mode */ uint8_t resync_jump_width; /*!< CAN resynchronization jump width */ uint8_t time_segment_1; /*!< time segment 1 */ uint8_t time_segment_2; /*!< time segment 2 */ ControlStatus time_triggered; /*!< time triggered communication mode */ ControlStatus auto_bus_off_recovery; /*!< automatic bus-off recovery */ ControlStatus auto_wake_up; /*!< automatic wake-up mode */ - ControlStatus auto_retrans; /*!< automatic retransmission mode */ + ControlStatus no_auto_retrans; /*!< automatic retransmission mode disable */ ControlStatus rec_fifo_overwrite; /*!< receive FIFO overwrite mode */ ControlStatus trans_fifo_order; /*!< transmit FIFO order */ uint16_t prescaler; /*!< baudrate prescaler */ @@ -387,18 +460,26 @@ typedef enum CAN_ERROR_BITRECESSIVE, /*!< bit recessive error */ CAN_ERROR_BITDOMINANTER, /*!< bit dominant error */ CAN_ERROR_CRC, /*!< CRC error */ - CAN_ERROR_SOFTWARECFG /*!< software configure */ + CAN_ERROR_SOFTWARECFG, /*!< software configure */ }can_error_enum; /* transmit states */ typedef enum { - CAN_TRANSMIT_FAILED = 0, /*!< CAN transmitted failure */ - CAN_TRANSMIT_OK = 1, /*!< CAN transmitted success */ - CAN_TRANSMIT_PENDING = 2, /*!< CAN transmitted pending */ - CAN_TRANSMIT_NOMAILBOX = 4, /*!< no empty mailbox to be used for CAN */ + CAN_TRANSMIT_FAILED = 0U, /*!< CAN transmitted failure */ + CAN_TRANSMIT_OK = 1U, /*!< CAN transmitted success */ + CAN_TRANSMIT_PENDING = 2U, /*!< CAN transmitted pending */ + CAN_TRANSMIT_NOMAILBOX = 4U, /*!< no empty mailbox to be used for CAN */ }can_transmit_state_enum; +typedef enum +{ + CAN_INIT_STRUCT = 0, /* CAN initiliaze parameters struct */ + CAN_FILTER_STRUCT, /* CAN filter parameters struct */ + CAN_TX_MESSAGE_STRUCT, /* CAN transmit message struct */ + CAN_RX_MESSAGE_STRUCT, /* CAN receive message struct */ +}can_struct_type_enum; + /* CAN baudrate prescaler*/ #define BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0)) @@ -438,66 +519,76 @@ typedef enum /* transmit data byte 2 */ #define TMDATA0_DB2(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) -/* transmit data byte 3 */ +/* transmit data byte 3 */ #define TMDATA0_DB3(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) -/* transmit data byte 4 */ +/* transmit data byte 4 */ #define TMDATA1_DB4(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) -/* transmit data byte 5 */ +/* transmit data byte 5 */ #define TMDATA1_DB5(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) -/* transmit data byte 6 */ +/* transmit data byte 6 */ #define TMDATA1_DB6(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) -/* transmit data byte 7 */ +/* transmit data byte 7 */ #define TMDATA1_DB7(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) /* receive mailbox extended identifier*/ -#define RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3, 31) +#define GET_RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3U, 31U) /* receive mailbox standrad identifier*/ -#define RFIFOMI_SFID(regval) GET_BITS((uint32_t)(regval), 21, 31) +#define GET_RFIFOMI_SFID(regval) GET_BITS((uint32_t)(regval), 21U, 31U) /* receive data length */ -#define RFIFOMP_DLENC(regval) GET_BITS((uint32_t)(regval), 0, 3) +#define GET_RFIFOMP_DLENC(regval) GET_BITS((uint32_t)(regval), 0U, 3U) -#define RFIFOMP_FI(regval) GET_BITS((uint32_t)(regval), 8, 15) +/* the index of the filter by which the frame is passed */ +#define GET_RFIFOMP_FI(regval) GET_BITS((uint32_t)(regval), 8U, 15U) /* receive data byte 0 */ -#define RFIFOMDATA0_DB0(regval) GET_BITS((uint32_t)(regval), 0, 7) +#define GET_RFIFOMDATA0_DB0(regval) GET_BITS((uint32_t)(regval), 0U, 7U) /* receive data byte 1 */ -#define RFIFOMDATA0_DB1(regval) GET_BITS((uint32_t)(regval), 8, 15) +#define GET_RFIFOMDATA0_DB1(regval) GET_BITS((uint32_t)(regval), 8U, 15U) /* receive data byte 2 */ -#define RFIFOMDATA0_DB2(regval) GET_BITS((uint32_t)(regval), 16, 23) +#define GET_RFIFOMDATA0_DB2(regval) GET_BITS((uint32_t)(regval), 16U, 23U) /* receive data byte 3 */ -#define RFIFOMDATA0_DB3(regval) GET_BITS((uint32_t)(regval), 24, 31) +#define GET_RFIFOMDATA0_DB3(regval) GET_BITS((uint32_t)(regval), 24U, 31U) /* receive data byte 4 */ -#define RFIFOMDATA1_DB4(regval) GET_BITS((uint32_t)(regval), 0, 7) +#define GET_RFIFOMDATA1_DB4(regval) GET_BITS((uint32_t)(regval), 0U, 7U) /* receive data byte 5 */ -#define RFIFOMDATA1_DB5(regval) GET_BITS((uint32_t)(regval), 8, 15) +#define GET_RFIFOMDATA1_DB5(regval) GET_BITS((uint32_t)(regval), 8U, 15U) /* receive data byte 6 */ -#define RFIFOMDATA1_DB6(regval) GET_BITS((uint32_t)(regval), 16, 23) +#define GET_RFIFOMDATA1_DB6(regval) GET_BITS((uint32_t)(regval), 16U, 23U) /* receive data byte 7 */ -#define RFIFOMDATA1_DB7(regval) GET_BITS((uint32_t)(regval), 24, 31) +#define GET_RFIFOMDATA1_DB7(regval) GET_BITS((uint32_t)(regval), 24U, 31U) + +/* error number */ +#define GET_ERR_ERRN(regval) GET_BITS((uint32_t)(regval), 4U, 6U) + +/* transmit error count */ +#define GET_ERR_TECNT(regval) GET_BITS((uint32_t)(regval), 16U, 23U) + +/* receive error count */ +#define GET_ERR_RECNT(regval) GET_BITS((uint32_t)(regval), 24U, 31U) /* CAN errors */ #define ERR_ERRN(regval) (BITS(4,6) & ((uint32_t)(regval) << 4)) -#define CAN_ERRN_0 ERR_ERRN(0) /* no error */ -#define CAN_ERRN_1 ERR_ERRN(1) /*!< fill error */ -#define CAN_ERRN_2 ERR_ERRN(2) /*!< format error */ -#define CAN_ERRN_3 ERR_ERRN(3) /*!< ACK error */ -#define CAN_ERRN_4 ERR_ERRN(4) /*!< bit recessive error */ -#define CAN_ERRN_5 ERR_ERRN(5) /*!< bit dominant error */ -#define CAN_ERRN_6 ERR_ERRN(6) /*!< CRC error */ -#define CAN_ERRN_7 ERR_ERRN(7) /*!< software error */ +#define CAN_ERRN_0 ERR_ERRN(0U) /* no error */ +#define CAN_ERRN_1 ERR_ERRN(1U) /*!< fill error */ +#define CAN_ERRN_2 ERR_ERRN(2U) /*!< format error */ +#define CAN_ERRN_3 ERR_ERRN(3U) /*!< ACK error */ +#define CAN_ERRN_4 ERR_ERRN(4U) /*!< bit recessive error */ +#define CAN_ERRN_5 ERR_ERRN(5U) /*!< bit dominant error */ +#define CAN_ERRN_6 ERR_ERRN(6U) /*!< CRC error */ +#define CAN_ERRN_7 ERR_ERRN(7U) /*!< software error */ #define CAN_STATE_PENDING ((uint32_t)0x00000000U) /*!< CAN pending */ @@ -556,7 +647,7 @@ typedef enum #define CAN_FIFO1 ((uint8_t)0x01U) /*!< receive FIFO1 */ /* frame number of receive fifo */ -#define CAN_RFIFO_RFL0_MASK ((uint32_t)0x00000003U) /*!< mask for frame number in receive FIFO0 */ +#define CAN_RFIF_RFL_MASK ((uint32_t)0x00000003U) /*!< mask for frame number in receive FIFOx */ #define CAN_SFID_MASK ((uint32_t)0x000007FFU) /*!< mask of standard identifier */ #define CAN_EFID_MASK ((uint32_t)0x1FFFFFFFU) /*!< mask of extended identifier */ @@ -575,7 +666,7 @@ typedef enum #define CAN_FILTERMODE_LIST ((uint8_t)0x01U) /*!< list mode */ /* filter 16 bits mask */ -#define CAN_FILTER_MASK_16BITS ((uint32_t)0x0000FFFFU) +#define CAN_FILTER_MASK_16BITS ((uint32_t)0x0000FFFFU) /*!< can filter 16 bits mask */ /* frame type */ #define CAN_FT_DATA ((uint32_t)0x00000000U) /*!< data frame */ @@ -584,62 +675,72 @@ typedef enum /* CAN timeout */ #define CAN_TIMEOUT ((uint32_t)0x0000FFFFU) /*!< timeout value */ +/* interrupt enable bits */ +#define CAN_INT_TME CAN_INTEN_TMEIE /*!< transmit mailbox empty interrupt enable */ +#define CAN_INT_RFNE0 CAN_INTEN_RFNEIE0 /*!< receive FIFO0 not empty interrupt enable */ +#define CAN_INT_RFF0 CAN_INTEN_RFFIE0 /*!< receive FIFO0 full interrupt enable */ +#define CAN_INT_RFO0 CAN_INTEN_RFOIE0 /*!< receive FIFO0 overfull interrupt enable */ +#define CAN_INT_RFNE1 CAN_INTEN_RFNEIE1 /*!< receive FIFO1 not empty interrupt enable */ +#define CAN_INT_RFF1 CAN_INTEN_RFFIE1 /*!< receive FIFO1 full interrupt enable */ +#define CAN_INT_RFO1 CAN_INTEN_RFOIE1 /*!< receive FIFO1 overfull interrupt enable */ +#define CAN_INT_WERR CAN_INTEN_WERRIE /*!< warning error interrupt enable */ +#define CAN_INT_PERR CAN_INTEN_PERRIE /*!< passive error interrupt enable */ +#define CAN_INT_BO CAN_INTEN_BOIE /*!< bus-off interrupt enable */ +#define CAN_INT_ERRN CAN_INTEN_ERRNIE /*!< error number interrupt enable */ +#define CAN_INT_ERR CAN_INTEN_ERRIE /*!< error interrupt enable */ +#define CAN_INT_WAKEUP CAN_INTEN_WIE /*!< wakeup interrupt enable */ +#define CAN_INT_SLPW CAN_INTEN_SLPWIE /*!< sleep working interrupt enable */ + /* function declarations */ -/* initialization functions */ -/* CAN deinit */ +/* deinitialize CAN */ void can_deinit(uint32_t can_periph); -/* CAN init */ +/* initialize CAN struct */ +void can_struct_para_init(can_struct_type_enum type, void* p_struct); +/* initialize CAN */ ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init); - -/* transmit functions */ -/* CAN transmit message */ -uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message); -/* CAN transmit state */ -can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number); -/* CAN stop transmission */ -void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number); -/* CAN transmit error number */ -uint8_t can_transmit_error_number(uint32_t can_periph); - -/* filter functions */ /* CAN filter init */ void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init); /* set can1 fliter start bank number */ void can1_filter_start_bank(uint8_t start_bank); - /* enable functions */ /* CAN debug freeze enable */ void can_debug_freeze_enable(uint32_t can_periph); /* CAN debug freeze disable */ void can_debug_freeze_disable(uint32_t can_periph); -/* CAN time triggle mode enable */ +/* CAN time trigger mode enable */ void can_time_trigger_mode_enable(uint32_t can_periph); -/* CAN time triggle mode disable */ +/* CAN time trigger mode disable */ void can_time_trigger_mode_disable(uint32_t can_periph); -/* CAN interrupt enable */ -void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt); -/* CAN interrupt disable */ -void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt); -/* receive functions */ +/* transmit functions */ +/* transmit CAN message */ +uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message); +/* get CAN transmit state */ +can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number); +/* stop CAN transmission */ +void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number); /* CAN receive message */ void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message); /* CAN release fifo */ void can_fifo_release(uint32_t can_periph, uint8_t fifo_number); /* CAN receive message length */ -uint8_t can_receive_message_length(uint32_t can_periph, uint8_t fifo_number); -/* CAN receive error number */ -uint8_t can_receive_error_number(uint32_t can_periph); - -/* mode functions */ +uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number); /* CAN working mode */ ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode); /* CAN wakeup from sleep mode */ ErrStatus can_wakeup(uint32_t can_periph); -/* flag functions */ /* CAN get error */ can_error_enum can_error_get(uint32_t can_periph); +/* get CAN receive error number */ +uint8_t can_receive_error_number_get(uint32_t can_periph); +/* get CAN transmit error number */ +uint8_t can_transmit_error_number_get(uint32_t can_periph); + +/* CAN interrupt enable */ +void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt); +/* CAN interrupt disable */ +void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt); /* CAN get flag state */ FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag); /* CAN clear flag state */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_crc.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_crc.h index 983dd944a5..01f2c6bc3f 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_crc.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_crc.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_crc.h - \brief definitions for the CRC + \file gd32f4xx_crc.h + \brief definitions for the CRC + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_CRC_H @@ -37,19 +62,19 @@ /* deinit CRC calculation unit */ void crc_deinit(void); -/* reset data register to the value of initializaiton data register */ +/* reset data register(CRC_DATA) to the value of 0xFFFFFFFF */ void crc_data_register_reset(void); -/* read the data register */ +/* read the value of the data register */ uint32_t crc_data_register_read(void); -/* read the free data register */ +/* read the value of the free data register */ uint8_t crc_free_data_register_read(void); -/* write the free data register */ +/* write data to the free data register */ void crc_free_data_register_write(uint8_t free_data); -/* CRC calculate a 32-bit data */ +/* calculate the CRC value of a 32-bit data */ uint32_t crc_single_data_calculate(uint32_t sdata); -/* CRC calculate a 32-bit data array */ +/* calculate the CRC value of an array of 32-bit values */ uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size); #endif /* GD32F4XX_CRC_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_ctc.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_ctc.h index 605d5530d5..00e4e7f298 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_ctc.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_ctc.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_ctc.h - \brief definitions for the CTC + \file gd32f4xx_ctc.h + \brief definitions for the CTC + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_CTC_H @@ -25,7 +50,7 @@ /* bits definitions */ /* CTC_CTL0 */ -#define CTC_CTL0_CKOKIE BIT(0) /*!< clock trim OK(CKOKIF) interrupt enable */ +#define CTC_CTL0_CKOKIE BIT(0) /*!< clock trim OK(CKOKIF) interrupt enable */ #define CTC_CTL0_CKWARNIE BIT(1) /*!< clock trim warning(CKWARNIF) interrupt enable */ #define CTC_CTL0_ERRIE BIT(2) /*!< error(ERRIF) interrupt enable */ #define CTC_CTL0_EREFIE BIT(3) /*!< EREFIF interrupt enable */ @@ -90,19 +115,19 @@ #define CTC_REFSOURCE_PSC_DIV128 CTL1_REFPSC(7) /*!< reference signal divided by 128 */ /* CTC interrupt enable definitions */ -#define CTC_INT_CKOKIE CTC_CTL0_CKOKIE /*!< clock trim OK interrupt enable */ -#define CTC_INT_CKWARNIE CTC_CTL0_CKWARNIE /*!< clock trim warning interrupt enable */ -#define CTC_INT_ERRIE CTC_CTL0_ERRIE /*!< error interrupt enable */ -#define CTC_INT_EREFIE CTC_CTL0_EREFIE /*!< expect reference interrupt enable */ +#define CTC_INT_CKOK CTC_CTL0_CKOKIE /*!< clock trim OK interrupt enable */ +#define CTC_INT_CKWARN CTC_CTL0_CKWARNIE /*!< clock trim warning interrupt enable */ +#define CTC_INT_ERR CTC_CTL0_ERRIE /*!< error interrupt enable */ +#define CTC_INT_EREF CTC_CTL0_EREFIE /*!< expect reference interrupt enable */ /* CTC interrupt source definitions */ -#define CTC_INT_CKOK CTC_STAT_CKOKIF /*!< clock trim OK interrupt flag */ -#define CTC_INT_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning interrupt flag */ -#define CTC_INT_ERR CTC_STAT_ERRIF /*!< error interrupt flag */ -#define CTC_INT_EREF CTC_STAT_EREFIF /*!< expect reference interrupt flag */ -#define CTC_INT_CKERR CTC_STAT_CKERR /*!< clock trim error bit */ -#define CTC_INT_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */ -#define CTC_INT_TRIMERR CTC_STAT_TRIMERR /*!< trim value error */ +#define CTC_INT_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK interrupt flag */ +#define CTC_INT_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning interrupt flag */ +#define CTC_INT_FLAG_ERR CTC_STAT_ERRIF /*!< error interrupt flag */ +#define CTC_INT_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference interrupt flag */ +#define CTC_INT_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */ +#define CTC_INT_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */ +#define CTC_INT_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error */ /* CTC flag definitions */ #define CTC_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK flag */ @@ -116,45 +141,30 @@ /* function declarations */ /* reset ctc clock trim controller */ void ctc_deinit(void); - -/* enable the CTC interrupt */ -void ctc_interrupt_enable(uint32_t ctc_interrupt); -/* disable the CTC interrupt */ -void ctc_interrupt_disable(uint32_t ctc_interrupt); -/* get CTC interrupt flag */ -FlagStatus ctc_interrupt_flag_get(uint32_t ctc_interrupt); -/* clear CTC interrupt flag */ -void ctc_interrupt_flag_clear(uint32_t ctc_interrupt); - -/* get CTC flag */ -FlagStatus ctc_flag_get(uint32_t ctc_flag); -/* clear CTC flag */ -void ctc_flag_clear(uint32_t ctc_flag); +/* enable CTC trim counter */ +void ctc_counter_enable(void); +/* disable CTC trim counter */ +void ctc_counter_disable(void); /* configure the IRC48M trim value */ -void ctc_irc48m_trim_value_config(uint8_t ctc_trim_value); +void ctc_irc48m_trim_value_config(uint8_t trim_value); /* generate software reference source sync pulse */ void ctc_software_refsource_pulse_generate(void); /* configure hardware automatically trim mode */ -void ctc_hardware_trim_mode_config(uint32_t ctc_hardmode); - -/* enable CTC counter */ -void ctc_counter_enable(void); -/* disable CTC counter */ -void ctc_counter_disable(void); +void ctc_hardware_trim_mode_config(uint32_t hardmode); /* configure reference signal source polarity */ -void ctc_refsource_polarity_config(uint32_t ctc_polarity); +void ctc_refsource_polarity_config(uint32_t polarity); /* select USBFS or USBHS SOF signal */ -void ctc_usbsof_signal_select(uint32_t ctc_usbsof); +void ctc_usbsof_signal_select(uint32_t usbsof); /* select reference signal source */ -void ctc_refsource_signal_select(uint32_t ctc_refs); +void ctc_refsource_signal_select(uint32_t refs); /* configure reference signal source prescaler */ -void ctc_refsource_prescaler_config(uint32_t ctc_prescaler); +void ctc_refsource_prescaler_config(uint32_t prescaler); /* configure clock trim base limit value */ -void ctc_clock_limit_value_config(uint8_t ctc_limit_value); +void ctc_clock_limit_value_config(uint8_t limit_value); /* configure CTC counter reload value */ -void ctc_counter_reload_value_config(uint16_t ctc_reload_value); +void ctc_counter_reload_value_config(uint16_t reload_value); /* read CTC counter capture value when reference sync pulse occurred */ uint16_t ctc_counter_capture_value_read(void); @@ -165,4 +175,18 @@ uint16_t ctc_counter_reload_value_read(void); /* read the IRC48M trim value */ uint8_t ctc_irc48m_trim_value_read(void); +/* interrupt & flag functions */ +/* enable the CTC interrupt */ +void ctc_interrupt_enable(uint32_t interrupt); +/* disable the CTC interrupt */ +void ctc_interrupt_disable(uint32_t interrupt); +/* get CTC interrupt flag */ +FlagStatus ctc_interrupt_flag_get(uint32_t int_flag); +/* clear CTC interrupt flag */ +void ctc_interrupt_flag_clear(uint32_t int_flag); +/* get CTC flag */ +FlagStatus ctc_flag_get(uint32_t flag); +/* clear CTC flag */ +void ctc_flag_clear(uint32_t flag); + #endif /* GD32F4XX_CTC_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dac.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dac.h index 8a668fcc0c..573fb31336 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dac.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dac.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_dac.h - \brief definitions for the DAC + \file gd32f4xx_dac.h + \brief definitions for the DAC + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_DAC_H @@ -20,152 +45,153 @@ #define DAC1 1U /* registers definitions */ -#define DAC_CTL REG32(DAC + 0x00U) /*!< DAC control register */ -#define DAC_SWT REG32(DAC + 0x04U) /*!< DAC software trigger register */ -#define DAC0_R12DH REG32(DAC + 0x08U) /*!< DAC0 12-bit right-aligned data holding register */ -#define DAC0_L12DH REG32(DAC + 0x0CU) /*!< DAC0 12-bit left-aligned data holding register */ -#define DAC0_R8DH REG32(DAC + 0x10U) /*!< DAC0 8-bit right-aligned data holding register */ -#define DAC1_R12DH REG32(DAC + 0x14U) /*!< DAC1 12-bit right-aligned data holding register */ -#define DAC1_L12DH REG32(DAC + 0x18U) /*!< DAC1 12-bit left-aligned data holding register */ -#define DAC1_R8DH REG32(DAC + 0x1CU) /*!< DAC1 8-bit right-aligned data holding register */ -#define DACC_R12DH REG32(DAC + 0x20U) /*!< DAC concurrent mode 12-bit right-aligned data holding register */ -#define DACC_L12DH REG32(DAC + 0x24U) /*!< DAC concurrent mode 12-bit left-aligned data holding register */ -#define DACC_R8DH REG32(DAC + 0x28U) /*!< DAC concurrent mode 8-bit right-aligned data holding register */ -#define DAC0_DO REG32(DAC + 0x2CU) /*!< DAC0 data output register */ -#define DAC1_DO REG32(DAC + 0x30U) /*!< DAC1 data output register */ -#define DAC_STAT REG32(DAC + 0x34U) /*!< DAC status register */ +#define DAC_CTL REG32(DAC + 0x00U) /*!< DAC control register */ +#define DAC_SWT REG32(DAC + 0x04U) /*!< DAC software trigger register */ +#define DAC0_R12DH REG32(DAC + 0x08U) /*!< DAC0 12-bit right-aligned data holding register */ +#define DAC0_L12DH REG32(DAC + 0x0CU) /*!< DAC0 12-bit left-aligned data holding register */ +#define DAC0_R8DH REG32(DAC + 0x10U) /*!< DAC0 8-bit right-aligned data holding register */ +#define DAC1_R12DH REG32(DAC + 0x14U) /*!< DAC1 12-bit right-aligned data holding register */ +#define DAC1_L12DH REG32(DAC + 0x18U) /*!< DAC1 12-bit left-aligned data holding register */ +#define DAC1_R8DH REG32(DAC + 0x1CU) /*!< DAC1 8-bit right-aligned data holding register */ +#define DACC_R12DH REG32(DAC + 0x20U) /*!< DAC concurrent mode 12-bit right-aligned data holding register */ +#define DACC_L12DH REG32(DAC + 0x24U) /*!< DAC concurrent mode 12-bit left-aligned data holding register */ +#define DACC_R8DH REG32(DAC + 0x28U) /*!< DAC concurrent mode 8-bit right-aligned data holding register */ +#define DAC0_DO REG32(DAC + 0x2CU) /*!< DAC0 data output register */ +#define DAC1_DO REG32(DAC + 0x30U) /*!< DAC1 data output register */ +#define DAC_STAT REG32(DAC + 0x34U) /*!< DAC status register */ /* bits definitions */ -/* DAC_CLT */ -#define DAC_CTL_DEN0 BIT(0) /*!< DAC0 enable/disable bit */ -#define DAC_CTL_DBOFF0 BIT(1) /*!< DAC0 output buffer turn on/turn off bit */ -#define DAC_CTL_DTEN0 BIT(2) /*!< DAC0 trigger enable/disable bit */ -#define DAC_CTL_DTSEL0 BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */ -#define DAC_CTL_DWM0 BITS(6,7) /*!< DAC0 noise wave mode */ -#define DAC_CTL_DWBW0 BITS(8,11) /*!< DAC0 noise wave bit width */ -#define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disanle bit */ -#define DAC_CTL_DDUDRIE0 BIT(13) /*!< DAC0 DMA underrun interrupt enable/disable bit */ -#define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */ -#define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */ -#define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */ -#define DAC_CTL_DTSEL1 BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */ -#define DAC_CTL_DWM1 BITS(22,23) /*!< DAC1 noise wave mode */ -#define DAC_CTL_DWBW1 BITS(24,27) /*!< DAC1 noise wave bit width */ -#define DAC_CTL_DDMAEN1 BIT(28) /*!< DAC1 DMA enable/disanle bit */ -#define DAC_CTL_DDUDRIE1 BIT(29) /*!< DAC1 DMA underrun interrupt enable/disable bit */ +/* DAC_CTL */ +#define DAC_CTL_DEN0 BIT(0) /*!< DAC0 enable/disable bit */ +#define DAC_CTL_DBOFF0 BIT(1) /*!< DAC0 output buffer turn on/turn off bit */ +#define DAC_CTL_DTEN0 BIT(2) /*!< DAC0 trigger enable/disable bit */ +#define DAC_CTL_DTSEL0 BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */ +#define DAC_CTL_DWM0 BITS(6,7) /*!< DAC0 noise wave mode */ +#define DAC_CTL_DWBW0 BITS(8,11) /*!< DAC0 noise wave bit width */ +#define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disable bit */ +#define DAC_CTL_DDUDRIE0 BIT(13) /*!< DAC0 DMA underrun interrupt enable/disable bit */ +#define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */ +#define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */ +#define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */ +#define DAC_CTL_DTSEL1 BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */ +#define DAC_CTL_DWM1 BITS(22,23) /*!< DAC1 noise wave mode */ +#define DAC_CTL_DWBW1 BITS(24,27) /*!< DAC1 noise wave bit width */ +#define DAC_CTL_DDMAEN1 BIT(28) /*!< DAC1 DMA enable/disable bit */ +#define DAC_CTL_DDUDRIE1 BIT(29) /*!< DAC1 DMA underrun interrupt enable/disable bit */ /* DAC_SWT */ -#define DAC_SWT_SWTR0 BIT(0) /*!< DAC0 software trigger bit, cleared by hardware */ -#define DAC_SWT_SWTR1 BIT(1) /*!< DAC1 software trigger bit, cleared by hardware */ +#define DAC_SWT_SWTR0 BIT(0) /*!< DAC0 software trigger bit, cleared by hardware */ +#define DAC_SWT_SWTR1 BIT(1) /*!< DAC1 software trigger bit, cleared by hardware */ /* DAC0_R12DH */ -#define DAC0_R12DH_DAC0_DH BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */ +#define DAC0_R12DH_DAC0_DH BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */ /* DAC0_L12DH */ -#define DAC0_L12DH_DAC0_DH BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */ +#define DAC0_L12DH_DAC0_DH BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */ /* DAC0_R8DH */ -#define DAC0_R8DH_DAC0_DH BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */ +#define DAC0_R8DH_DAC0_DH BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */ /* DAC1_R12DH */ -#define DAC1_R12DH_DAC1_DH BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */ +#define DAC1_R12DH_DAC1_DH BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */ /* DAC1_L12DH */ -#define DAC1_L12DH_DAC1_DH BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */ +#define DAC1_L12DH_DAC1_DH BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */ /* DAC1_R8DH */ -#define DAC1_R8DH_DAC1_DH BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */ +#define DAC1_R8DH_DAC1_DH BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */ /* DACC_R12DH */ -#define DACC_R12DH_DAC0_DH BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */ -#define DACC_R12DH_DAC1_DH BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */ +#define DACC_R12DH_DAC0_DH BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */ +#define DACC_R12DH_DAC1_DH BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */ /* DACC_L12DH */ -#define DACC_L12DH_DAC0_DH BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */ -#define DACC_L12DH_DAC1_DH BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */ +#define DACC_L12DH_DAC0_DH BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */ +#define DACC_L12DH_DAC1_DH BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */ /* DACC_R8DH */ -#define DACC_R8DH_DAC0_DH BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */ -#define DACC_R8DH_DAC1_DH BITS(16,23) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */ +#define DACC_R8DH_DAC0_DH BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */ +#define DACC_R8DH_DAC1_DH BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */ /* DAC0_DO */ -#define DAC0_DO_DAC0_DO BITS(0,11) /*!< DAC0 12-bit output data bits */ +#define DAC0_DO_DAC0_DO BITS(0,11) /*!< DAC0 12-bit output data bits */ /* DAC1_DO */ -#define DAC1_DO_DAC1_DO BITS(0,11) /*!< DAC1 12-bit output data bits */ +#define DAC1_DO_DAC1_DO BITS(0,11) /*!< DAC1 12-bit output data bits */ /* DAC_STAT */ -#define DAC_STAT_DDUDR0 BIT(13) /*!< DAC0 DMA underrun flag */ -#define DAC_STAT_DDUDR1 BIT(29) /*!< DAC1 DMA underrun flag */ +#define DAC_STAT_DDUDR0 BIT(13) /*!< DAC0 DMA underrun flag */ +#define DAC_STAT_DDUDR1 BIT(29) /*!< DAC1 DMA underrun flag */ /* constants definitions */ /* DAC trigger source */ #define CTL_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) -#define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */ -#define DAC_TRIGGER_T7_TRGO CTL_DTSEL(1) /*!< TIMER7 TRGO */ -#define DAC_TRIGGER_T6_TRGO CTL_DTSEL(2) /*!< TIMER6 TRGO */ -#define DAC_TRIGGER_T4_TRGO CTL_DTSEL(3) /*!< TIMER4 TRGO */ -#define DAC_TRIGGER_T1_TRGO CTL_DTSEL(4) /*!< TIMER1 TRGO */ -#define DAC_TRIGGER_T3_TRGO CTL_DTSEL(5) /*!< TIMER3 TRGO */ -#define DAC_TRIGGER_EXTI_9 CTL_DTSEL(6) /*!< EXTI interrupt line9 event */ -#define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7) /*!< software trigger */ +#define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */ +#define DAC_TRIGGER_T7_TRGO CTL_DTSEL(1) /*!< TIMER7 TRGO */ +#define DAC_TRIGGER_T6_TRGO CTL_DTSEL(2) /*!< TIMER6 TRGO */ +#define DAC_TRIGGER_T4_TRGO CTL_DTSEL(3) /*!< TIMER4 TRGO */ +#define DAC_TRIGGER_T1_TRGO CTL_DTSEL(4) /*!< TIMER1 TRGO */ +#define DAC_TRIGGER_T3_TRGO CTL_DTSEL(5) /*!< TIMER3 TRGO */ +#define DAC_TRIGGER_EXTI_9 CTL_DTSEL(6) /*!< EXTI interrupt line9 event */ +#define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7) /*!< software trigger */ /* DAC noise wave mode */ #define CTL_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) -#define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disable */ -#define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */ -#define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */ +#define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disable */ +#define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */ +#define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */ /* DAC noise wave bit width */ #define DWBW(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) -#define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */ -#define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */ -#define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */ -#define DAC_WAVE_BIT_WIDTH_4 DWBW(3) /*!< bit width of the wave signal is 4 */ -#define DAC_WAVE_BIT_WIDTH_5 DWBW(4) /*!< bit width of the wave signal is 5 */ -#define DAC_WAVE_BIT_WIDTH_6 DWBW(5) /*!< bit width of the wave signal is 6 */ -#define DAC_WAVE_BIT_WIDTH_7 DWBW(6) /*!< bit width of the wave signal is 7 */ -#define DAC_WAVE_BIT_WIDTH_8 DWBW(7) /*!< bit width of the wave signal is 8 */ -#define DAC_WAVE_BIT_WIDTH_9 DWBW(8) /*!< bit width of the wave signal is 9 */ -#define DAC_WAVE_BIT_WIDTH_10 DWBW(9) /*!< bit width of the wave signal is 10 */ -#define DAC_WAVE_BIT_WIDTH_11 DWBW(10) /*!< bit width of the wave signal is 11 */ -#define DAC_WAVE_BIT_WIDTH_12 DWBW(11) /*!< bit width of the wave signal is 12 */ +#define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */ +#define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */ +#define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */ +#define DAC_WAVE_BIT_WIDTH_4 DWBW(3) /*!< bit width of the wave signal is 4 */ +#define DAC_WAVE_BIT_WIDTH_5 DWBW(4) /*!< bit width of the wave signal is 5 */ +#define DAC_WAVE_BIT_WIDTH_6 DWBW(5) /*!< bit width of the wave signal is 6 */ +#define DAC_WAVE_BIT_WIDTH_7 DWBW(6) /*!< bit width of the wave signal is 7 */ +#define DAC_WAVE_BIT_WIDTH_8 DWBW(7) /*!< bit width of the wave signal is 8 */ +#define DAC_WAVE_BIT_WIDTH_9 DWBW(8) /*!< bit width of the wave signal is 9 */ +#define DAC_WAVE_BIT_WIDTH_10 DWBW(9) /*!< bit width of the wave signal is 10 */ +#define DAC_WAVE_BIT_WIDTH_11 DWBW(10) /*!< bit width of the wave signal is 11 */ +#define DAC_WAVE_BIT_WIDTH_12 DWBW(11) /*!< bit width of the wave signal is 12 */ /* unmask LFSR bits in DAC LFSR noise mode */ -#define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1 /*!< unmask the LFSR bit0 */ -#define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2 /*!< unmask the LFSR bits[1:0] */ -#define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3 /*!< unmask the LFSR bits[2:0] */ -#define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4 /*!< unmask the LFSR bits[3:0] */ -#define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5 /*!< unmask the LFSR bits[4:0] */ -#define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6 /*!< unmask the LFSR bits[5:0] */ -#define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7 /*!< unmask the LFSR bits[6:0] */ -#define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8 /*!< unmask the LFSR bits[7:0] */ -#define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9 /*!< unmask the LFSR bits[8:0] */ -#define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */ -#define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */ -#define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */ - -/* triangle amplitude in DAC triangle noise mode */ -#define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1 /*!< triangle amplitude is 1 */ -#define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2 /*!< triangle amplitude is 3 */ -#define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3 /*!< triangle amplitude is 7 */ -#define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4 /*!< triangle amplitude is 15 */ -#define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5 /*!< triangle amplitude is 31 */ -#define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6 /*!< triangle amplitude is 63 */ -#define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7 /*!< triangle amplitude is 127 */ -#define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8 /*!< triangle amplitude is 255 */ -#define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9 /*!< triangle amplitude is 511 */ -#define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */ -#define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */ -#define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */ +#define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1 /*!< unmask the LFSR bit0 */ +#define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2 /*!< unmask the LFSR bits[1:0] */ +#define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3 /*!< unmask the LFSR bits[2:0] */ +#define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4 /*!< unmask the LFSR bits[3:0] */ +#define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5 /*!< unmask the LFSR bits[4:0] */ +#define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6 /*!< unmask the LFSR bits[5:0] */ +#define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7 /*!< unmask the LFSR bits[6:0] */ +#define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8 /*!< unmask the LFSR bits[7:0] */ +#define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9 /*!< unmask the LFSR bits[8:0] */ +#define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */ +#define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */ +#define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */ /* DAC data alignment */ #define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< data right 12b alignment */ -#define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< data left 12b alignment */ -#define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< data right 8b alignment */ +#define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< data right 12 bit alignment */ +#define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< data left 12 bit alignment */ +#define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< data right 8 bit alignment */ + +/* triangle amplitude in DAC triangle noise mode */ +#define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1 /*!< triangle amplitude is 1 */ +#define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2 /*!< triangle amplitude is 3 */ +#define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3 /*!< triangle amplitude is 7 */ +#define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4 /*!< triangle amplitude is 15 */ +#define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5 /*!< triangle amplitude is 31 */ +#define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6 /*!< triangle amplitude is 63 */ +#define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7 /*!< triangle amplitude is 127 */ +#define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8 /*!< triangle amplitude is 255 */ +#define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9 /*!< triangle amplitude is 511 */ +#define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */ +#define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */ +#define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */ /* function declarations */ +/* initialization functions */ /* deinitialize DAC */ void dac_deinit(void); /* enable DAC */ @@ -175,26 +201,29 @@ void dac_disable(uint32_t dac_periph); /* enable DAC DMA */ void dac_dma_enable(uint32_t dac_periph); /* disable DAC DMA */ -void dac_dma_disable(uint32_t dac_periph); +void dac_dma_disable(uint32_t dac_periph); /* enable DAC output buffer */ void dac_output_buffer_enable(uint32_t dac_periph); /* disable DAC output buffer */ void dac_output_buffer_disable(uint32_t dac_periph); +/* get the last data output value */ +uint16_t dac_output_value_get(uint32_t dac_periph); +/* set DAC data holding register value */ +void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data); + +/* DAC trigger configuration */ /* enable DAC trigger */ void dac_trigger_enable(uint32_t dac_periph); /* disable DAC trigger */ void dac_trigger_disable(uint32_t dac_periph); +/* configure DAC trigger source */ +void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource); /* enable DAC software trigger */ void dac_software_trigger_enable(uint32_t dac_periph); /* disable DAC software trigger */ void dac_software_trigger_disable(uint32_t dac_periph); -/* enable DAC interrupt(DAC0 DMA underrun interrupt) */ -void dac_interrupt_enable(uint32_t dac_periph); -/* disable DAC interrupt(DAC0 DMA underrun interrupt) */ -void dac_interrupt_disable(uint32_t dac_periph); -/* configure DAC trigger source */ -void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource); +/* DAC wave mode configuration */ /* configure DAC wave mode */ void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode); /* configure DAC wave bit width */ @@ -203,14 +232,8 @@ void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width); void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits); /* configure DAC triangle noise mode */ void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude); -/* get the last data output value */ -uint16_t dac_output_value_get(uint32_t dac_periph); - -/* set DAC data holding register value */ -void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data); -/* set DAC concurrent mode data holding register value */ -void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1); +/* DAC concurrent mode configuration */ /* enable DAC concurrent mode */ void dac_concurrent_enable(void); /* disable DAC concurrent mode */ @@ -223,11 +246,18 @@ void dac_concurrent_software_trigger_disable(void); void dac_concurrent_output_buffer_enable(void); /* disable DAC concurrent buffer function */ void dac_concurrent_output_buffer_disable(void); +/* set DAC concurrent mode data holding register value */ +void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1); /* enable DAC concurrent interrupt */ void dac_concurrent_interrupt_enable(void); /* disable DAC concurrent interrupt */ void dac_concurrent_interrupt_disable(void); +/* DAC interrupt configuration */ +/* enable DAC interrupt(DAC DMA underrun interrupt) */ +void dac_interrupt_enable(uint32_t dac_periph); +/* disable DAC interrupt(DAC DMA underrun interrupt) */ +void dac_interrupt_disable(uint32_t dac_periph); /* get the specified DAC flag(DAC DMA underrun flag) */ FlagStatus dac_flag_get(uint32_t dac_periph); /* clear the specified DAC flag(DAC DMA underrun flag) */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dbg.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dbg.h index 273b13e7fb..fde91597f7 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dbg.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dbg.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_dbg.h - \brief definitions for the DBG + \file gd32f4xx_dbg.h + \brief definitions for the DBG + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_DBG_H @@ -65,30 +90,43 @@ #define DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */ #define DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD /*!< keep debugger connection during standby mode */ +/* define the peripheral debug hold bit position and its register index offset */ +#define DBG_REGIDX_BIT(regidx, bitpos) (((regidx) << 6) | (bitpos)) +#define DBG_REG_VAL(periph) (REG32(DBG + ((uint32_t)(periph) >> 6))) +#define DBG_BIT_POS(val) ((uint32_t)(val) & 0x1FU) + +/* register index */ +enum dbg_reg_idx +{ + DBG_IDX_CTL0 = 0x04U, + DBG_IDX_CTL1 = 0x08U, + DBG_IDX_CTL2 = 0x0CU +}; + typedef enum { - DBG_TIMER1_HOLD = BIT(0), /*!< hold TIMER1 counter when core is halted */ - DBG_TIMER2_HOLD = BIT(1), /*!< hold TIMER2 counter when core is halted */ - DBG_TIMER3_HOLD = BIT(2), /*!< hold TIMER3 counter when core is halted */ - DBG_TIMER4_HOLD = BIT(3), /*!< hold TIMER4 counter when core is halted */ - DBG_TIMER5_HOLD = BIT(4), /*!< hold TIMER5 counter when core is halted */ - DBG_TIMER6_HOLD = BIT(5), /*!< hold TIMER6 counter when core is halted */ - DBG_TIMER11_HOLD = BIT(6), /*!< hold TIMER11 counter when core is halted */ - DBG_TIMER12_HOLD = BIT(7), /*!< hold TIMER12 counter when core is halted */ - DBG_TIMER13_HOLD = BIT(8), /*!< hold TIMER13 counter when core is halted */ - DBG_RTC_HOLD = BIT(10), /*!< hold RTC calendar and wakeup counter when core is halted */ - DBG_WWDGT_HOLD = BIT(11), /*!< debug WWDGT kept when core is halted */ - DBG_FWDGT_HOLD = BIT(12), /*!< debug FWDGT kept when core is halted */ - DBG_I2C0_HOLD = BIT(21), /*!< hold I2C0 smbus when core is halted */ - DBG_I2C1_HOLD = BIT(22), /*!< hold I2C1 smbus when core is halted */ - DBG_I2C2_HOLD = BIT(23), /*!< hold I2C2 smbus when core is halted */ - DBG_CAN0_HOLD = BIT(25), /*!< debug CAN0 kept when core is halted */ - DBG_CAN1_HOLD = BIT(26), /*!< debug CAN1 kept when core is halted */ - DBG_TIMER0_HOLD = (BIT(0) | BIT(30)), /*!< hold TIMER0 counter when core is halted */ - DBG_TIMER7_HOLD = (BIT(1) | BIT(30)), /*!< hold TIMER7 counter when core is halted */ - DBG_TIMER8_HOLD = (BIT(16) | BIT(30)), /*!< hold TIMER8 counter when core is halted */ - DBG_TIMER9_HOLD = (BIT(17) | BIT(30)), /*!< hold TIMER9 counter when core is halted */ - DBG_TIMER10_HOLD = (BIT(18) | BIT(30)), /*!< hold TIMER10 counter when core is halted */ + DBG_TIMER1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 0U), /*!< hold TIMER1 counter when core is halted */ + DBG_TIMER2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 1U), /*!< hold TIMER2 counter when core is halted */ + DBG_TIMER3_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 2U), /*!< hold TIMER3 counter when core is halted */ + DBG_TIMER4_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 3U), /*!< hold TIMER4 counter when core is halted */ + DBG_TIMER5_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 4U), /*!< hold TIMER5 counter when core is halted */ + DBG_TIMER6_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 5U), /*!< hold TIMER6 counter when core is halted */ + DBG_TIMER11_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 6U), /*!< hold TIMER11 counter when core is halted */ + DBG_TIMER12_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 7U), /*!< hold TIMER12 counter when core is halted */ + DBG_TIMER13_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 8U), /*!< hold TIMER13 counter when core is halted */ + DBG_RTC_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 10U), /*!< hold RTC calendar and wakeup counter when core is halted */ + DBG_WWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 11U), /*!< debug WWDGT kept when core is halted */ + DBG_FWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 12U), /*!< debug FWDGT kept when core is halted */ + DBG_I2C0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 21U), /*!< hold I2C0 smbus when core is halted */ + DBG_I2C1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 22U), /*!< hold I2C1 smbus when core is halted */ + DBG_I2C2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 23U), /*!< hold I2C2 smbus when core is halted */ + DBG_CAN0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 25U), /*!< debug CAN0 kept when core is halted */ + DBG_CAN1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 26U), /*!< debug CAN1 kept when core is halted */ + DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 0U), /*!< hold TIMER0 counter when core is halted */ + DBG_TIMER7_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 1U), /*!< hold TIMER7 counter when core is halted */ + DBG_TIMER8_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 16U), /*!< hold TIMER8 counter when core is halted */ + DBG_TIMER9_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 17U), /*!< hold TIMER9 counter when core is halted */ + DBG_TIMER10_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 18U) /*!< hold TIMER10 counter when core is halted */ }dbg_periph_enum; #define CTL0_TRACE_MODE(regval) (BITS(6,7)&((uint32_t)(regval)<<6)) @@ -98,6 +136,8 @@ typedef enum #define TRACE_MODE_SYNC_DATASIZE_4 CTL0_TRACE_MODE(3) /*!< trace pin used for sync mode and data size is 4 */ /* function declarations */ +/* deinitialize the DBG */ +void dbg_deinit(void); /* read DBG_ID code register */ uint32_t dbg_id_get(void); diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dci.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dci.h index 7c9b445138..4986d5afd4 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dci.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dci.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_dci.h - \brief definitions for the DCI + \file gd32f4xx_dci.h + \brief definitions for the DCI + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_DCI_H @@ -32,17 +57,17 @@ /* bits definitions */ /* DCI_CTL */ -#define DCI_CTL_CAP BIT(0) /*!< capture enable */ -#define DCI_CTL_SNAP BIT(1) /*!< snapshot mode */ -#define DCI_CTL_WDEN BIT(2) /*!< window enable */ -#define DCI_CTL_JM BIT(3) /*!< jpeg mode */ -#define DCI_CTL_ESM BIT(4) /*!< embedded synchronous mode */ -#define DCI_CTL_CKS BIT(5) /*!< clock polarity selection */ -#define DCI_CTL_HPS BIT(6) /*!< horizontal polarity selection */ -#define DCI_CTL_VPS BIT(7) /*!< vertical polarity selection */ -#define DCI_CTL_FR BITS(8,9) /*!< frame rate */ -#define DCI_CTL_DCIF BITS(10,11) /*!< digital camera interface format */ -#define DCI_CTL_DCIEN BIT(14) /*!< dci enable */ +#define DCI_CTL_CAP BIT(0) /*!< capture enable */ +#define DCI_CTL_SNAP BIT(1) /*!< snapshot mode */ +#define DCI_CTL_WDEN BIT(2) /*!< window enable */ +#define DCI_CTL_JM BIT(3) /*!< JPEG mode */ +#define DCI_CTL_ESM BIT(4) /*!< embedded synchronous mode */ +#define DCI_CTL_CKS BIT(5) /*!< clock polarity selection */ +#define DCI_CTL_HPS BIT(6) /*!< horizontal polarity selection */ +#define DCI_CTL_VPS BIT(7) /*!< vertical polarity selection */ +#define DCI_CTL_FR BITS(8,9) /*!< frame rate */ +#define DCI_CTL_DCIF BITS(10,11) /*!< digital camera interface format */ +#define DCI_CTL_DCIEN BIT(14) /*!< DCI enable */ /* DCI_STAT0 */ #define DCI_STAT0_HS BIT(0) /*!< HS line status */ @@ -98,16 +123,16 @@ #define DCI_CWSZ_WVSZ BITS(16,29) /*!< window vertical size */ /* constants definitions */ -/* DCI parameter struct definitions */ +/* DCI parameter structure definitions */ typedef struct -{ +{ uint32_t capture_mode; /*!< DCI capture mode: continuous or snapshot */ uint32_t clock_polarity; /*!< clock polarity selection */ uint32_t hsync_polarity; /*!< horizontal polarity selection */ uint32_t vsync_polarity; /*!< vertical polarity selection */ uint32_t frame_rate; /*!< frame capture rate */ uint32_t interface_format; /*!< digital camera interface format */ -}dci_parameter_struct; +}dci_parameter_struct; #define DCI_CAPTURE_MODE_CONTINUOUS ((uint32_t)0x00000000U) /*!< continuous capture mode */ #define DCI_CAPTURE_MODE_SNAPSHOT DCI_CTL_SNAP /*!< snapshot capture mode */ @@ -120,36 +145,44 @@ typedef struct #define DCI_VSYNC_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level during blanking period */ #define DCI_VSYNC_POLARITY_HIGH DCI_CTL_VPS /*!< high level during blanking period*/ - -#define CTL_FR(regval) (BITS(8,9)&((uint32_t)(regval) << 8U)) + +#define CTL_FR(regval) (BITS(8,9)&((uint32_t)(regval) << 8U)) #define DCI_FRAME_RATE_ALL CTL_FR(0) /*!< capture all frames */ #define DCI_FRAME_RATE_1_2 CTL_FR(1) /*!< capture one in 2 frames */ #define DCI_FRAME_RATE_1_4 CTL_FR(2) /*!< capture one in 4 frames */ -#define CTL_DCIF(regval) (BITS(10,11)&((uint32_t)(regval) << 10U)) +#define CTL_DCIF(regval) (BITS(10,11)&((uint32_t)(regval) << 10U)) #define DCI_INTERFACE_FORMAT_8BITS CTL_DCIF(0) /*!< 8-bit data on every pixel clock */ #define DCI_INTERFACE_FORMAT_10BITS CTL_DCIF(1) /*!< 10-bit data on every pixel clock */ #define DCI_INTERFACE_FORMAT_12BITS CTL_DCIF(2) /*!< 12-bit data on every pixel clock */ #define DCI_INTERFACE_FORMAT_14BITS CTL_DCIF(3) /*!< 14-bit data on every pixel clock */ /* DCI interrupt constants definitions */ -#define DCI_INT_EF ((uint32_t)0x00000001U) /*!< end of frame interrupt */ -#define DCI_INT_OVR ((uint32_t)0x00000002U) /*!< FIFO overrun interrupt */ -#define DCI_INT_ESE ((uint32_t)0x00000004U) /*!< embedded synchronous error interrupt */ -#define DCI_INT_VS ((uint32_t)0x00000008U) /*!< vsync interrupt */ -#define DCI_INT_EL ((uint32_t)0x00000010U) /*!< end of line interrupt */ +#define DCI_INT_EF BIT(0) /*!< end of frame interrupt */ +#define DCI_INT_OVR BIT(1) /*!< FIFO overrun interrupt */ +#define DCI_INT_ESE BIT(2) /*!< embedded synchronous error interrupt */ +#define DCI_INT_VSYNC BIT(3) /*!< vsync interrupt */ +#define DCI_INT_EL BIT(4) /*!< end of line interrupt */ -/* DCI flag definitions */ -#define DCI_FLAG_HS ((uint8_t)0x01U) /*!< HS line status */ -#define DCI_FLAG_VS ((uint8_t)0x02U) /*!< VS line status */ -#define DCI_FLAG_FV ((uint8_t)0x03U) /*!< FIFO valid */ -#define DCI_FLAG_EFF ((uint8_t)0x04U) /*!< end of frame flag */ -#define DCI_FLAG_OVRF ((uint8_t)0x05U) /*!< FIFO overrun flag */ -#define DCI_FLAG_ESEF ((uint8_t)0x06U) /*!< embedded synchronous error flag */ -#define DCI_FLAG_VSF ((uint8_t)0x07U) /*!< vsync flag */ -#define DCI_FLAG_ELF ((uint8_t)0x08U) /*!< end of line flag */ +/* DCI interrupt flag definitions */ +#define DCI_INT_FLAG_EF BIT(0) /*!< end of frame interrupt flag */ +#define DCI_INT_FLAG_OVR BIT(1) /*!< FIFO overrun interrupt flag */ +#define DCI_INT_FLAG_ESE BIT(2) /*!< embedded synchronous error interrupt flag */ +#define DCI_INT_FLAG_VSYNC BIT(3) /*!< vsync interrupt flag */ +#define DCI_INT_FLAG_EL BIT(4) /*!< end of line interrupt flag */ + +/* DCI flag definitions */ +#define DCI_FLAG_HS DCI_STAT0_HS /*!< HS line status */ +#define DCI_FLAG_VS DCI_STAT0_VS /*!< VS line status */ +#define DCI_FLAG_FV DCI_STAT0_FV /*!< FIFO valid */ +#define DCI_FLAG_EF (DCI_STAT1_EFF | BIT(31)) /*!< end of frame flag */ +#define DCI_FLAG_OVR (DCI_STAT1_OVRF | BIT(31)) /*!< FIFO overrun flag */ +#define DCI_FLAG_ESE (DCI_STAT1_ESEF | BIT(31)) /*!< embedded synchronous error flag */ +#define DCI_FLAG_VSYNC (DCI_STAT1_VSF | BIT(31)) /*!< vsync flag */ +#define DCI_FLAG_EL (DCI_STAT1_ELF | BIT(31)) /*!< end of line flag */ /* function declarations */ +/* initialization functions */ /* DCI deinit */ void dci_deinit(void); /* initialize DCI registers */ @@ -157,44 +190,49 @@ void dci_init(dci_parameter_struct* dci_struct); /* enable DCI function */ void dci_enable(void); -/* disble DCI function */ +/* disable DCI function */ void dci_disable(void); /* enable DCI capture */ void dci_capture_enable(void); -/* disble DCI capture */ +/* disable DCI capture */ void dci_capture_disable(void); /* enable DCI jpeg mode */ void dci_jpeg_enable(void); -/* disble DCI jpeg mode */ +/* disable DCI jpeg mode */ void dci_jpeg_disable(void); +/* function configuration */ /* enable cropping window function */ void dci_crop_window_enable(void); -/* disble cropping window function */ +/* disable cropping window function */ void dci_crop_window_disable(void); -/* config DCI cropping window */ +/* configure DCI cropping window */ void dci_crop_window_config(uint16_t start_x, uint16_t start_y, uint16_t size_width, uint16_t size_height); -/* enable sync codes function */ -void dci_sync_codes_enable(void); -/* disble sync codes function */ -void dci_sync_codes_disable(void); -/* config sync codes */ +/* enable embedded synchronous mode */ +void dci_embedded_sync_enable(void); +/* disable embedded synchronous mode */ +void dci_embedded_sync_disable(void); +/* configure synchronous codes in embedded synchronous mode */ void dci_sync_codes_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end); -/* config sync codes unmask */ +/* configure synchronous codes unmask in embedded synchronous mode */ void dci_sync_codes_unmask_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end); /* read DCI data register */ uint32_t dci_data_read(void); -/* enable specified DCI interrupt */ -void dci_interrupt_enable(uint32_t interrupt); -/* disble specified DCI interrupt */ -void dci_interrupt_disable(uint32_t interrupt); -/* clear specified interrupt */ -void dci_interrupt_clear(uint32_t interrupt); +/* interrupt & flag functions */ /* get specified flag */ FlagStatus dci_flag_get(uint32_t flag); +/* enable specified DCI interrupt */ +void dci_interrupt_enable(uint32_t interrupt); +/* disable specified DCI interrupt */ +void dci_interrupt_disable(uint32_t interrupt); + + /* get specified interrupt flag */ -FlagStatus dci_interrupt_flag_get(uint32_t interrupt); +FlagStatus dci_interrupt_flag_get(uint32_t int_flag); +/* clear specified interrupt flag */ +void dci_interrupt_flag_clear(uint32_t int_flag); + #endif /* GD32F4XX_DCI_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dma.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dma.h index be59a229f6..cac70b85eb 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dma.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dma.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_dma.h - \brief definitions for the DMA + \file gd32f4xx_dma.c + \brief definitions for the DMA + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_DMA_H @@ -123,10 +148,10 @@ #define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */ /* DMA_CHxM0ADDR,x=0..7 */ -#define DMA_CHXM0ADDR_PADDR BITS(0,31) /*!< memory 0 base address */ +#define DMA_CHXM0ADDR_M0ADDR BITS(0,31) /*!< memory 0 base address */ /* DMA_CHxM1ADDR,x=0..7 */ -#define DMA_CHXM1ADDR_PADDR BITS(0,31) /*!< memory 1 base address */ +#define DMA_CHXM1ADDR_M0ADDR BITS(0,31) /*!< memory 1 base address */ /* DMA_CHxFCTL,x=0..7 */ #define DMA_CHXFCTL_FCCV BITS(0,1) /*!< FIFO counter critical value */ @@ -136,7 +161,7 @@ /* constants definitions */ /* DMA channel select */ -typedef enum +typedef enum { DMA_CH0 = 0, /*!< DMA Channel 0 */ DMA_CH1, /*!< DMA Channel 1 */ @@ -149,7 +174,7 @@ typedef enum } dma_channel_enum; /* DMA peripheral select */ -typedef enum +typedef enum { DMA_SUBPERI0 = 0, /*!< DMA Peripheral 0 */ DMA_SUBPERI1, /*!< DMA Peripheral 1 */ @@ -166,7 +191,7 @@ typedef struct { uint32_t periph_addr; /*!< peripheral base address */ uint32_t periph_width; /*!< transfer data size of peripheral */ - uint32_t periph_inc; /*!< peripheral increasing mode */ + uint32_t periph_inc; /*!< peripheral increasing mode */ uint32_t memory0_addr; /*!< memory 0 base address */ uint32_t memory_width; /*!< transfer data size of memory */ @@ -176,7 +201,7 @@ typedef struct uint32_t periph_burst_width; /*!< multi data mode enable */ uint32_t critical_value; /*!< FIFO critical */ - uint32_t circular_mode; + uint32_t circular_mode; /*!< DMA circular mode */ uint32_t direction; /*!< channel data transfer direction */ uint32_t number; /*!< channel transfer number */ uint32_t priority; /*!< channel priority level */ @@ -186,7 +211,7 @@ typedef struct typedef struct { uint32_t periph_addr; /*!< peripheral base address */ - uint32_t periph_inc; /*!< peripheral increasing mode */ + uint32_t periph_inc; /*!< peripheral increasing mode */ uint32_t memory0_addr; /*!< memory 0 base address */ uint32_t memory_inc; /*!< memory increasing mode */ @@ -296,85 +321,108 @@ typedef struct #define DMA_FIFO_STATUS_FULL ((uint32_t)0x00000005U) /*!< the data in the FIFO is full */ /* DMA reset value */ -#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */ -#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */ -#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */ -#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */ -#define DMA_CHINTF_RESET_VALUE ((uint32_t)0x0000003DU) /*!< clear DMA channel CHXINTFS register */ -#define DMA_CHFCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXFCTL register */ +#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */ +#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */ +#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */ +#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */ +#define DMA_CHINTF_RESET_VALUE ((uint32_t)0x0000003DU) /*!< clear DMA channel CHXINTFS register */ +#define DMA_CHFCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXFCTL register */ + +/* DMA_INTF register */ +/* interrupt flag bits */ +#define DMA_INT_FLAG_FEE DMA_INTF_FEEIF /*!< FIFO error and exception flag */ +#define DMA_INT_FLAG_SDE DMA_INTF_SDEIF /*!< single data mode exception flag */ +#define DMA_INT_FLAG_TAE DMA_INTF_TAEIF /*!< transfer access error flag */ +#define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag */ +#define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag */ + +/* flag bits */ +#define DMA_FLAG_FEE DMA_INTF_FEEIF /*!< FIFO error and exception flag */ +#define DMA_FLAG_SDE DMA_INTF_SDEIF /*!< single data mode exception flag */ +#define DMA_FLAG_TAE DMA_INTF_TAEIF /*!< transfer access error flag */ +#define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag */ +#define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag */ + /* function declarations */ +/* DMA deinitialization and initialization functions */ /* deinitialize DMA a channel registers */ -void dma_deinit(uint32_t dma_periph,dma_channel_enum channelx); +void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx); +/* initialize the DMA single data mode parameters struct with the default values */ +void dma_single_data_para_struct_init(dma_single_data_parameter_struct* init_struct); +/* initialize the DMA multi data mode parameters struct with the default values */ +void dma_multi_data_para_struct_init(dma_multi_data_parameter_struct* init_struct); /* DMA single data mode initialize */ -void dma_single_data_mode_init(uint32_t dma_periph,dma_channel_enum channelx,dma_single_data_parameter_struct init_struct); +void dma_single_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dma_single_data_parameter_struct* init_struct); /* DMA multi data mode initialize */ -void dma_multi_data_mode_init(uint32_t dma_periph,dma_channel_enum channelx,dma_multi_data_parameter_struct init_struct); +void dma_multi_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dma_multi_data_parameter_struct* init_struct); +/* DMA configuration functions */ /* set DMA peripheral base address */ -void dma_periph_address_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t address); +void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address); /* set DMA Memory base address */ -void dma_memory_address_config(uint32_t dma_periph,dma_channel_enum channelx,uint8_t memory_flag,uint32_t address); +void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t memory_flag, uint32_t address); /* set the number of remaining data to be transferred by the DMA */ -void dma_transfer_number_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t number); +void dma_transfer_number_config(uint32_t dma_periph,dma_channel_enum channelx, uint32_t number); /* get the number of remaining data to be transferred by the DMA */ -uint32_t dma_transfer_number_get(uint32_t dma_periph,dma_channel_enum channelx); +uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx); /* configure priority level of DMA channel */ -void dma_priority_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t priority); +void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority); /* configure transfer burst beats of memory */ -void dma_memory_burst_beats_config (uint32_t dma_periph,dma_channel_enum channelx,uint32_t mbeat); +void dma_memory_burst_beats_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t mbeat); /* configure transfer burst beats of peripheral */ -void dma_periph_burst_beats_config (uint32_t dma_periph,dma_channel_enum channelx,uint32_t pbeat); +void dma_periph_burst_beats_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t pbeat); /* configure transfer data size of memory */ -void dma_memory_width_config (uint32_t dma_periph,dma_channel_enum channelx,uint32_t msize); +void dma_memory_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t msize); /* configure transfer data size of peripheral */ -void dma_periph_width_config (uint32_t dma_periph,dma_channel_enum channelx,uint32_t psize); +void dma_periph_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t psize); /* configure next address increasement algorithm of memory */ -void dma_memory_address_generation_config(uint32_t dma_periph,dma_channel_enum channelx,uint8_t generation_algorithm); +void dma_memory_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm); /* configure next address increasement algorithm of peripheral */ -void dma_peripheral_address_generation_config(uint32_t dma_periph,dma_channel_enum channelx,uint8_t generation_algorithm); +void dma_peripheral_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm); /* enable DMA circulation mode */ -void dma_circulation_enable(uint32_t dma_periph,dma_channel_enum channelx); +void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx); /* disable DMA circulation mode */ -void dma_circulation_disable(uint32_t dma_periph,dma_channel_enum channelx); +void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx); /* enable DMA channel */ -void dma_channel_enable(uint32_t dma_periph,dma_channel_enum channelx); +void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx); /* disable DMA channel */ -void dma_channel_disable(uint32_t dma_periph,dma_channel_enum channelx); +void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx); /* configure the direction of data transfer on the channel */ -void dma_transfer_direction_config(uint32_t dma_periph,dma_channel_enum channelx,uint8_t direction); +void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t direction); /* DMA switch buffer mode config */ -void dma_switch_buffer_mode_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t memory1_addr,uint32_t memory_select); +void dma_switch_buffer_mode_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t memory1_addr, uint32_t memory_select); /* DMA using memory get */ -uint32_t dma_using_memory_get(uint32_t dma_periph,dma_channel_enum channelx); +uint32_t dma_using_memory_get(uint32_t dma_periph, dma_channel_enum channelx); /* DMA channel peripheral select */ -void dma_channel_subperipheral_select(uint32_t dma_periph,dma_channel_enum channelx,dma_subperipheral_enum sub_periph); +void dma_channel_subperipheral_select(uint32_t dma_periph, dma_channel_enum channelx, dma_subperipheral_enum sub_periph); /* DMA flow controller configure */ -void dma_flow_controller_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t controller); +void dma_flow_controller_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t controller); /* DMA flow controller enable */ -void dma_switch_buffer_mode_enable(uint32_t dma_periph,dma_channel_enum channelx,ControlStatus newvalue); +void dma_switch_buffer_mode_enable(uint32_t dma_periph, dma_channel_enum channelx, ControlStatus newvalue); /* DMA FIFO status get */ -uint32_t dma_fifo_status_get(uint32_t dma_periph,dma_channel_enum channelx); +uint32_t dma_fifo_status_get(uint32_t dma_periph, dma_channel_enum channelx); +/* flag and interrupt functions */ /* check DMA flag is set or not */ -FlagStatus dma_flag_get(uint32_t dma_periph,dma_channel_enum channelx,uint32_t flag); +FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); /* clear DMA a channel flag */ -void dma_flag_clear(uint32_t dma_periph,dma_channel_enum channelx,uint32_t flag); +void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); /* check DMA flag is set or not */ -FlagStatus dma_interrupt_flag_get(uint32_t dma_periph,dma_channel_enum channelx,uint32_t interrupt); +FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt); /* clear DMA a channel flag */ -void dma_interrupt_flag_clear(uint32_t dma_periph,dma_channel_enum channelx,uint32_t interrupt); +void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt); /* enable DMA interrupt */ -void dma_interrupt_enable(uint32_t dma_periph,dma_channel_enum channelx,uint32_t source); +void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); /* disable DMA interrupt */ -void dma_interrupt_disable(uint32_t dma_periph,dma_channel_enum channelx,uint32_t source); +void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); #endif /* GD32F4XX_DMA_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_enet.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_enet.h index 7a0de03860..1dfc880d37 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_enet.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_enet.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_enet.h - \brief definitions for the ENET + \file gd32f4xx_enet.h + \brief definitions for the ENET + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.1, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_ENET_H @@ -36,7 +61,7 @@ #define ENET_TXBUF_SIZE ENET_MAX_FRAME_SIZE /*!< ethernet transmit buffer size */ #endif -//#define SELECT_DESCRIPTORS_ENHANCED_MODE +//#define SELECT_DESCRIPTORS_ENHANCED_MODE //#define USE_DELAY @@ -47,7 +72,7 @@ #define PHY_ADDRESS ((uint16_t)1U) /*!< phy address determined by the hardware */ -/* PHY read write timeouts */ +/* PHY read write timeouts */ #define PHY_READ_TO ((uint32_t)0x0004FFFFU) /*!< PHY read timeout */ #define PHY_WRITE_TO ((uint32_t)0x0004FFFFU) /*!< PHY write timeout */ @@ -55,7 +80,7 @@ #define PHY_RESETDELAY ((uint32_t)0x008FFFFFU) /*!< PHY reset delay */ #define PHY_CONFIGDELAY ((uint32_t)0x00FFFFFFU) /*!< PHY configure delay */ -/* PHY register address */ +/* PHY register address */ #define PHY_REG_BCR 0U /*!< tranceiver basic control register */ #define PHY_REG_BSR 1U /*!< tranceiver basic status register */ @@ -76,7 +101,7 @@ #define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< valid link established */ #define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< jabber condition detected */ -#if(PHY_TYPE == LAN8700) +#if(PHY_TYPE == LAN8700) #define PHY_SR 31U /*!< tranceiver status register */ #define PHY_SPEED_STATUS ((uint16_t)0x0004) /*!< configured information of speed: 10Mbit/s */ #define PHY_DUPLEX_STATUS ((uint16_t)0x0010) /*!< configured information of duplex: full-duplex */ @@ -93,55 +118,55 @@ #define ENET ENET_BASE /* registers definitions */ -#define ENET_MAC_CFG REG32((ENET) + 0x00U) /*!< ethernet MAC configuration register */ -#define ENET_MAC_FRMF REG32((ENET) + 0x04U) /*!< ethernet MAC frame filter register */ -#define ENET_MAC_HLH REG32((ENET) + 0x08U) /*!< ethernet MAC hash list high register */ -#define ENET_MAC_HLL REG32((ENET) + 0x0CU) /*!< ethernet MAC hash list low register */ -#define ENET_MAC_PHY_CTL REG32((ENET) + 0x10U) /*!< ethernet MAC PHY control register */ -#define ENET_MAC_PHY_DATA REG32((ENET) + 0x14U) /*!< ethernet MAC MII data register */ -#define ENET_MAC_FCTL REG32((ENET) + 0x18U) /*!< ethernet MAC flow control register */ -#define ENET_MAC_VLT REG32((ENET) + 0x1CU) /*!< ethernet MAC VLAN tag register */ -#define ENET_MAC_RWFF REG32((ENET) + 0x28U) /*!< ethernet MAC remote wakeup frame filter register */ -#define ENET_MAC_WUM REG32((ENET) + 0x2CU) /*!< ethernet MAC wakeup management register */ -#define ENET_MAC_DBG REG32((ENET) + 0x34U) /*!< ethernet MAC debug register */ -#define ENET_MAC_INTF REG32((ENET) + 0x38U) /*!< ethernet MAC interrupt flag register */ -#define ENET_MAC_INTMSK REG32((ENET) + 0x3CU) /*!< ethernet MAC interrupt mask register */ -#define ENET_MAC_ADDR0H REG32((ENET) + 0x40U) /*!< ethernet MAC address 0 high register */ -#define ENET_MAC_ADDR0L REG32((ENET) + 0x44U) /*!< ethernet MAC address 0 low register */ -#define ENET_MAC_ADDR1H REG32((ENET) + 0x48U) /*!< ethernet MAC address 1 high register */ -#define ENET_MAC_ADDR1L REG32((ENET) + 0x4CU) /*!< ethernet MAC address 1 low register */ -#define ENET_MAC_ADDT2H REG32((ENET) + 0x50U) /*!< ethernet MAC address 2 high register */ -#define ENET_MAC_ADDR2L REG32((ENET) + 0x54U) /*!< ethernet MAC address 2 low register */ -#define ENET_MAC_ADDR3H REG32((ENET) + 0x58U) /*!< ethernet MAC address 3 high register */ -#define ENET_MAC_ADDR3L REG32((ENET) + 0x5CU) /*!< ethernet MAC address 3 low register */ +#define ENET_MAC_CFG REG32((ENET) + 0x0000U) /*!< ethernet MAC configuration register */ +#define ENET_MAC_FRMF REG32((ENET) + 0x0004U) /*!< ethernet MAC frame filter register */ +#define ENET_MAC_HLH REG32((ENET) + 0x0008U) /*!< ethernet MAC hash list high register */ +#define ENET_MAC_HLL REG32((ENET) + 0x000CU) /*!< ethernet MAC hash list low register */ +#define ENET_MAC_PHY_CTL REG32((ENET) + 0x0010U) /*!< ethernet MAC PHY control register */ +#define ENET_MAC_PHY_DATA REG32((ENET) + 0x0014U) /*!< ethernet MAC MII data register */ +#define ENET_MAC_FCTL REG32((ENET) + 0x0018U) /*!< ethernet MAC flow control register */ +#define ENET_MAC_VLT REG32((ENET) + 0x001CU) /*!< ethernet MAC VLAN tag register */ +#define ENET_MAC_RWFF REG32((ENET) + 0x0028U) /*!< ethernet MAC remote wakeup frame filter register */ +#define ENET_MAC_WUM REG32((ENET) + 0x002CU) /*!< ethernet MAC wakeup management register */ +#define ENET_MAC_DBG REG32((ENET) + 0x0034U) /*!< ethernet MAC debug register */ +#define ENET_MAC_INTF REG32((ENET) + 0x0038U) /*!< ethernet MAC interrupt flag register */ +#define ENET_MAC_INTMSK REG32((ENET) + 0x003CU) /*!< ethernet MAC interrupt mask register */ +#define ENET_MAC_ADDR0H REG32((ENET) + 0x0040U) /*!< ethernet MAC address 0 high register */ +#define ENET_MAC_ADDR0L REG32((ENET) + 0x0044U) /*!< ethernet MAC address 0 low register */ +#define ENET_MAC_ADDR1H REG32((ENET) + 0x0048U) /*!< ethernet MAC address 1 high register */ +#define ENET_MAC_ADDR1L REG32((ENET) + 0x004CU) /*!< ethernet MAC address 1 low register */ +#define ENET_MAC_ADDT2H REG32((ENET) + 0x0050U) /*!< ethernet MAC address 2 high register */ +#define ENET_MAC_ADDR2L REG32((ENET) + 0x0054U) /*!< ethernet MAC address 2 low register */ +#define ENET_MAC_ADDR3H REG32((ENET) + 0x0058U) /*!< ethernet MAC address 3 high register */ +#define ENET_MAC_ADDR3L REG32((ENET) + 0x005CU) /*!< ethernet MAC address 3 low register */ #define ENET_MAC_FCTH REG32((ENET) + 0x1080U) /*!< ethernet MAC flow control threshold register */ -#define ENET_MSC_CTL REG32((ENET) + 0x100U) /*!< ethernet MSC control register */ -#define ENET_MSC_RINTF REG32((ENET) + 0x104U) /*!< ethernet MSC receive interrupt flag register */ -#define ENET_MSC_TINTF REG32((ENET) + 0x108U) /*!< ethernet MSC transmit interrupt flag register */ -#define ENET_MSC_RINTMSK REG32((ENET) + 0x10CU) /*!< ethernet MSC receive interrupt mask register */ -#define ENET_MSC_TINTMSK REG32((ENET) + 0x110U) /*!< ethernet MSC transmit interrupt mask register */ -#define ENET_MSC_SCCNT REG32((ENET) + 0x14CU) /*!< ethernet MSC transmitted good frames after a single collision counter register */ -#define ENET_MSC_MSCCNT REG32((ENET) + 0x150U) /*!< ethernet MSC transmitted good frames after more than a single collision counter register */ -#define ENET_MSC_TGFCNT REG32((ENET) + 0x168U) /*!< ethernet MSC transmitted good frames counter register */ -#define ENET_MSC_RFCECNT REG32((ENET) + 0x194U) /*!< ethernet MSC received frames with CRC error counter register */ -#define ENET_MSC_RFAECNT REG32((ENET) + 0x198U) /*!< ethernet MSC received frames with alignment error counter register */ -#define ENET_MSC_RGUFCNT REG32((ENET) + 0x1C4U) /*!< ethernet MSC received good unicast frames counter register */ +#define ENET_MSC_CTL REG32((ENET) + 0x0100U) /*!< ethernet MSC control register */ +#define ENET_MSC_RINTF REG32((ENET) + 0x0104U) /*!< ethernet MSC receive interrupt flag register */ +#define ENET_MSC_TINTF REG32((ENET) + 0x0108U) /*!< ethernet MSC transmit interrupt flag register */ +#define ENET_MSC_RINTMSK REG32((ENET) + 0x010CU) /*!< ethernet MSC receive interrupt mask register */ +#define ENET_MSC_TINTMSK REG32((ENET) + 0x0110U) /*!< ethernet MSC transmit interrupt mask register */ +#define ENET_MSC_SCCNT REG32((ENET) + 0x014CU) /*!< ethernet MSC transmitted good frames after a single collision counter register */ +#define ENET_MSC_MSCCNT REG32((ENET) + 0x0150U) /*!< ethernet MSC transmitted good frames after more than a single collision counter register */ +#define ENET_MSC_TGFCNT REG32((ENET) + 0x0168U) /*!< ethernet MSC transmitted good frames counter register */ +#define ENET_MSC_RFCECNT REG32((ENET) + 0x0194U) /*!< ethernet MSC received frames with CRC error counter register */ +#define ENET_MSC_RFAECNT REG32((ENET) + 0x0198U) /*!< ethernet MSC received frames with alignment error counter register */ +#define ENET_MSC_RGUFCNT REG32((ENET) + 0x01C4U) /*!< ethernet MSC received good unicast frames counter register */ -#define ENET_PTP_TSCTL REG32((ENET) + 0x700U) /*!< ethernet PTP time stamp control register */ -#define ENET_PTP_SSINC REG32((ENET) + 0x704U) /*!< ethernet PTP subsecond increment register */ -#define ENET_PTP_TSH REG32((ENET) + 0x708U) /*!< ethernet PTP time stamp high register */ -#define ENET_PTP_TSL REG32((ENET) + 0x70CU) /*!< ethernet PTP time stamp low register */ -#define ENET_PTP_TSUH REG32((ENET) + 0x710U) /*!< ethernet PTP time stamp update high register */ -#define ENET_PTP_TSUL REG32((ENET) + 0x714U) /*!< ethernet PTP time stamp update low register */ -#define ENET_PTP_TSADDEND REG32((ENET) + 0x718U) /*!< ethernet PTP time stamp addend register */ -#define ENET_PTP_ETH REG32((ENET) + 0x71CU) /*!< ethernet PTP expected time high register */ -#define ENET_PTP_ETL REG32((ENET) + 0x720U) /*!< ethernet PTP expected time low register */ -#define ENET_PTP_TSF REG32((ENET) + 0x728U) /*!< ethernet PTP time stamp flag register */ -#define ENET_PTP_PPSCTL REG32((ENET) + 0x72CU) /*!< ethernet PTP PPS control register */ +#define ENET_PTP_TSCTL REG32((ENET) + 0x0700U) /*!< ethernet PTP time stamp control register */ +#define ENET_PTP_SSINC REG32((ENET) + 0x0704U) /*!< ethernet PTP subsecond increment register */ +#define ENET_PTP_TSH REG32((ENET) + 0x0708U) /*!< ethernet PTP time stamp high register */ +#define ENET_PTP_TSL REG32((ENET) + 0x070CU) /*!< ethernet PTP time stamp low register */ +#define ENET_PTP_TSUH REG32((ENET) + 0x0710U) /*!< ethernet PTP time stamp update high register */ +#define ENET_PTP_TSUL REG32((ENET) + 0x0714U) /*!< ethernet PTP time stamp update low register */ +#define ENET_PTP_TSADDEND REG32((ENET) + 0x0718U) /*!< ethernet PTP time stamp addend register */ +#define ENET_PTP_ETH REG32((ENET) + 0x071CU) /*!< ethernet PTP expected time high register */ +#define ENET_PTP_ETL REG32((ENET) + 0x0720U) /*!< ethernet PTP expected time low register */ +#define ENET_PTP_TSF REG32((ENET) + 0x0728U) /*!< ethernet PTP time stamp flag register */ +#define ENET_PTP_PPSCTL REG32((ENET) + 0x072CU) /*!< ethernet PTP PPS control register */ #define ENET_DMA_BCTL REG32((ENET) + 0x1000U) /*!< ethernet DMA bus control register */ -#define ENET_DMA_TPEN REG32((ENET) + 0x1004U) /*!< ethernet DMA transmit poll enable register */ +#define ENET_DMA_TPEN REG32((ENET) + 0x1004U) /*!< ethernet DMA transmit poll enable register */ #define ENET_DMA_RPEN REG32((ENET) + 0x1008U) /*!< ethernet DMA receive poll enable register */ #define ENET_DMA_RDTADDR REG32((ENET) + 0x100CU) /*!< ethernet DMA receive descriptor table address register */ #define ENET_DMA_TDTADDR REG32((ENET) + 0x1010U) /*!< ethernet DMA transmit descriptor table address register */ @@ -150,7 +175,7 @@ #define ENET_DMA_INTEN REG32((ENET) + 0x101CU) /*!< ethernet DMA interrupt enable register */ #define ENET_DMA_MFBOCNT REG32((ENET) + 0x1020U) /*!< ethernet DMA missed frame and buffer overflow counter register */ #define ENET_DMA_RSWDC REG32((ENET) + 0x1024U) /*!< ethernet DMA receive state watchdog counter register */ -#define ENET_DMA_CTDADDR REG32((ENET) + 0x1048U) /*!< ethernet DMA current transmit descriptor address register */ +#define ENET_DMA_CTDADDR REG32((ENET) + 0x1048U) /*!< ethernet DMA current transmit descriptor address register */ #define ENET_DMA_CRDADDR REG32((ENET) + 0x104CU) /*!< ethernet DMA current receive descriptor address register */ #define ENET_DMA_CTBADDR REG32((ENET) + 0x1050U) /*!< ethernet DMA current transmit buffer address register */ #define ENET_DMA_CRBADDR REG32((ENET) + 0x1054U) /*!< ethernet DMA current receive buffer address register */ @@ -169,7 +194,7 @@ #define ENET_MAC_CFG_ROD BIT(13) /*!< receive own disable */ #define ENET_MAC_CFG_SPD BIT(14) /*!< fast eneternet speed */ #define ENET_MAC_CFG_CSD BIT(16) /*!< carrier sense disable */ -#define ENET_MAC_CFG_IGBS BITS(17,19) /*!< inter-frame gap bit selection */ +#define ENET_MAC_CFG_IGBS BITS(17,19) /*!< inter-frame gap bit selection */ #define ENET_MAC_CFG_JBD BIT(22) /*!< jabber disable */ #define ENET_MAC_CFG_WDD BIT(23) /*!< watchdog disable */ #define ENET_MAC_CFG_TFCD BIT(25) /*!< type frame CRC dropping */ @@ -177,49 +202,49 @@ /* ENET_MAC_FRMF */ #define ENET_MAC_FRMF_PM BIT(0) /*!< promiscuous mode */ #define ENET_MAC_FRMF_HUF BIT(1) /*!< hash unicast filter */ -#define ENET_MAC_FRMF_HMF BIT(2) /*!< hash multicast filter */ -#define ENET_MAC_FRMF_DAIFLT BIT(3) /*!< destination address inverse filtering enable */ -#define ENET_MAC_FRMF_MFD BIT(4) /*!< multicast filter disable */ -#define ENET_MAC_FRMF_BFRMD BIT(5) /*!< broadcast frame disable */ -#define ENET_MAC_FRMF_PCFRM BITS(6,7) /*!< pass control frames */ -#define ENET_MAC_FRMF_SAIFLT BIT(8) /*!< source address inverse filtering */ -#define ENET_MAC_FRMF_SAFLT BIT(9) /*!< source address filter */ -#define ENET_MAC_FRMF_HPFLT BIT(10) /*!< hash or perfect filter */ -#define ENET_MAC_FRMF_FAR BIT(31) /*!< frames all receive */ - +#define ENET_MAC_FRMF_HMF BIT(2) /*!< hash multicast filter */ +#define ENET_MAC_FRMF_DAIFLT BIT(3) /*!< destination address inverse filtering enable */ +#define ENET_MAC_FRMF_MFD BIT(4) /*!< multicast filter disable */ +#define ENET_MAC_FRMF_BFRMD BIT(5) /*!< broadcast frame disable */ +#define ENET_MAC_FRMF_PCFRM BITS(6,7) /*!< pass control frames */ +#define ENET_MAC_FRMF_SAIFLT BIT(8) /*!< source address inverse filtering */ +#define ENET_MAC_FRMF_SAFLT BIT(9) /*!< source address filter */ +#define ENET_MAC_FRMF_HPFLT BIT(10) /*!< hash or perfect filter */ +#define ENET_MAC_FRMF_FAR BIT(31) /*!< frames all receive */ + /* ENET_MAC_HLH */ #define ENET_MAC_HLH_HLH BITS(0,31) /*!< hash list high */ - + /* ENET_MAC_HLL */ #define ENET_MAC_HLL_HLL BITS(0,31) /*!< hash list low */ - + /* ENET_MAC_PHY_CTL */ -#define ENET_MAC_PHY_CTL_PB BIT(0) /*!< PHY busy */ -#define ENET_MAC_PHY_CTL_PW BIT(1) /*!< PHY write */ -#define ENET_MAC_PHY_CTL_CLR BITS(2,4) /*!< clock range */ -#define ENET_MAC_PHY_CTL_PR BITS(6,10) /*!< PHY register */ -#define ENET_MAC_PHY_CTL_PA BITS(11,15) /*!< PHY address */ - +#define ENET_MAC_PHY_CTL_PB BIT(0) /*!< PHY busy */ +#define ENET_MAC_PHY_CTL_PW BIT(1) /*!< PHY write */ +#define ENET_MAC_PHY_CTL_CLR BITS(2,4) /*!< clock range */ +#define ENET_MAC_PHY_CTL_PR BITS(6,10) /*!< PHY register */ +#define ENET_MAC_PHY_CTL_PA BITS(11,15) /*!< PHY address */ + /* ENET_MAC_PHY_DATA */ #define ENET_MAC_PHY_DATA_PD BITS(0,15) /*!< PHY data */ - + /* ENET_MAC_FCTL */ #define ENET_MAC_FCTL_FLCBBKPA BIT(0) /*!< flow control busy(in full duplex mode)/backpressure activate(in half duplex mode) */ #define ENET_MAC_FCTL_TFCEN BIT(1) /*!< transmit flow control enable */ #define ENET_MAC_FCTL_RFCEN BIT(2) /*!< receive flow control enable */ #define ENET_MAC_FCTL_UPFDT BIT(3) /*!< unicast pause frame detect */ -#define ENET_MAC_FCTL_PLTS BITS(4,5) /*!< pause low threshold */ +#define ENET_MAC_FCTL_PLTS BITS(4,5) /*!< pause low threshold */ #define ENET_MAC_FCTL_DZQP BIT(7) /*!< disable zero-quanta pause */ #define ENET_MAC_FCTL_PTM BITS(16,31) /*!< pause time */ - + /* ENET_MAC_VLT */ #define ENET_MAC_VLT_VLTI BITS(0,15) /*!< VLAN tag identifier(for receive frames) */ #define ENET_MAC_VLT_VLTC BIT(16) /*!< 12-bit VLAN tag comparison */ - + /* ENET_MAC_RWFF */ #define ENET_MAC_RWFF_DATA BITS(0,31) /*!< wakeup frame filter register data */ - -/* ENET_MAC_WUM */ + +/* ENET_MAC_WUM */ #define ENET_MAC_WUM_PWD BIT(0) /*!< power down */ #define ENET_MAC_WUM_MPEN BIT(1) /*!< magic packet enable */ #define ENET_MAC_WUM_WFEN BIT(2) /*!< wakeup frame enable */ @@ -228,7 +253,7 @@ #define ENET_MAC_WUM_GU BIT(9) /*!< global unicast */ #define ENET_MAC_WUM_WUFFRPR BIT(31) /*!< wakeup frame filter register pointer reset */ -/* ENET_MAC_DBG */ +/* ENET_MAC_DBG */ #define ENET_MAC_DBG_MRNI BIT(0) /*!< MAC receive state not idle */ #define ENET_MAC_DBG_RXAFS BITS(1,2) /*!< Rx asynchronous FIFO status */ #define ENET_MAC_DBG_RXFW BIT(4) /*!< RxFIFO is writing */ @@ -242,7 +267,7 @@ #define ENET_MAC_DBG_TXFNE BIT(24) /*!< TxFIFO not empty flag */ #define ENET_MAC_DBG_TXFF BIT(25) /*!< TxFIFO full flag */ -/* ENET_MAC_INTF */ +/* ENET_MAC_INTF */ #define ENET_MAC_INTF_WUM BIT(3) /*!< WUM status */ #define ENET_MAC_INTF_MSC BIT(4) /*!< MSC status */ #define ENET_MAC_INTF_MSCR BIT(5) /*!< MSC receive status */ @@ -256,28 +281,28 @@ /* ENET_MAC_ADDR0H */ #define ENET_MAC_ADDR0H_ADDR0H BITS(0,15) /*!< MAC address0 high */ #define ENET_MAC_ADDR0H_MO BIT(31) /*!< always read 1 and must be kept */ - + /* ENET_MAC_ADDR0L */ #define ENET_MAC_ADDR0L_ADDR0L BITS(0,31) /*!< MAC address0 low */ - + /* ENET_MAC_ADDR1H */ #define ENET_MAC_ADDR1H_ADDR1H BITS(0,15) /*!< MAC address1 high */ -#define ENET_MAC_ADDR1H_MB BITS(24,29) /*!< mask byte */ +#define ENET_MAC_ADDR1H_MB BITS(24,29) /*!< mask byte */ #define ENET_MAC_ADDR1H_SAF BIT(30) /*!< source address filter */ #define ENET_MAC_ADDR1H_AFE BIT(31) /*!< address filter enable */ - + /* ENET_MAC_ADDR1L */ #define ENET_MAC_ADDR1L_ADDR1L BITS(0,31) /*!< MAC address1 low */ - + /* ENET_MAC_ADDR2H */ #define ENET_MAC_ADDR2H_ADDR2H BITS(0,15) /*!< MAC address2 high */ #define ENET_MAC_ADDR2H_MB BITS(24,29) /*!< mask byte */ #define ENET_MAC_ADDR2H_SAF BIT(30) /*!< source address filter */ #define ENET_MAC_ADDR2H_AFE BIT(31) /*!< address filter enable */ - + /* ENET_MAC_ADDR2L */ #define ENET_MAC_ADDR2L_ADDR2L BITS(0,31) /*!< MAC address2 low */ - + /* ENET_MAC_ADDR3H */ #define ENET_MAC_ADDR3H_ADDR3H BITS(0,15) /*!< MAC address3 high */ #define ENET_MAC_ADDR3H_MB BITS(24,29) /*!< mask byte */ @@ -286,11 +311,11 @@ /* ENET_MAC_ADDR3L */ #define ENET_MAC_ADDR3L_ADDR3L BITS(0,31) /*!< MAC address3 low */ - + /* ENET_MAC_FCTH */ #define ENET_MAC_FCTH_RFA BITS(0,2) /*!< threshold of active flow control */ #define ENET_MAC_FCTH_RFD BITS(4,6) /*!< threshold of deactive flow control */ - + /* ENET_MSC_CTL */ #define ENET_MSC_CTL_CTR BIT(0) /*!< counter reset */ #define ENET_MSC_CTL_CTSR BIT(1) /*!< counter stop rollover */ @@ -303,7 +328,7 @@ #define ENET_MSC_RINTF_RFCE BIT(5) /*!< received frames CRC error */ #define ENET_MSC_RINTF_RFAE BIT(6) /*!< received frames alignment error */ #define ENET_MSC_RINTF_RGUF BIT(17) /*!< receive good unicast frames */ - + /* ENET_MSC_TINTF */ #define ENET_MSC_TINTF_TGFSC BIT(14) /*!< transmitted good frames single collision */ #define ENET_MSC_TINTF_TGFMSC BIT(15) /*!< transmitted good frames more single collision */ @@ -313,30 +338,30 @@ #define ENET_MSC_RINTMSK_RFCEIM BIT(5) /*!< received frame CRC error interrupt mask */ #define ENET_MSC_RINTMSK_RFAEIM BIT(6) /*!< received frames alignment error interrupt mask */ #define ENET_MSC_RINTMSK_RGUFIM BIT(17) /*!< received good unicast frames interrupt mask */ - + /* ENET_MSC_TINTMSK */ #define ENET_MSC_TINTMSK_TGFSCIM BIT(14) /*!< transmitted good frames single collision interrupt mask */ #define ENET_MSC_TINTMSK_TGFMSCIM BIT(15) /*!< transmitted good frames more single collision interrupt mask */ #define ENET_MSC_TINTMSK_TGFIM BIT(21) /*!< transmitted good frames interrupt mask */ - + /* ENET_MSC_SCCNT */ #define ENET_MSC_SCCNT_SCC BITS(0,31) /*!< transmitted good frames single collision counter */ - + /* ENET_MSC_MSCCNT */ #define ENET_MSC_MSCCNT_MSCC BITS(0,31) /*!< transmitted good frames more one single collision counter */ - + /* ENET_MSC_TGFCNT */ #define ENET_MSC_TGFCNT_TGF BITS(0,31) /*!< transmitted good frames counter */ - + /* ENET_MSC_RFCECNT */ #define ENET_MSC_RFCECNT_RFCER BITS(0,31) /*!< received frames with CRC error counter */ - + /* ENET_MSC_RFAECNT */ #define ENET_MSC_RFAECNT_RFAER BITS(0,31) /*!< received frames alignment error counter */ - + /* ENET_MSC_RGUFCNT */ #define ENET_MSC_RGUFCNT_RGUF BITS(0,31) /*!< received good unicast frames counter */ - + /* ENET_PTP_TSCTL */ #define PTP_TSCTL_CKNT(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) /*!< write value to ENET_PTP_TSCTL_CKNT bit field */ @@ -356,37 +381,37 @@ #define ENET_PTP_TSCTL_MNMSEN BIT(15) /*!< received master node message snapshot enable */ #define ENET_PTP_TSCTL_CKNT BITS(16,17) /*!< clock node type for time stamp */ #define ENET_PTP_TSCTL_MAFEN BIT(18) /*!< MAC address filter enable for PTP frame */ - + /* ENET_PTP_SSINC */ #define ENET_PTP_SSINC_STMSSI BITS(0,7) /*!< system time subsecond increment */ - + /* ENET_PTP_TSH */ #define ENET_PTP_TSH_STMS BITS(0,31) /*!< system time second */ - + /* ENET_PTP_TSL */ #define ENET_PTP_TSL_STMSS BITS(0,30) /*!< system time subseconds */ #define ENET_PTP_TSL_STS BIT(31) /*!< system time sign */ - + /* ENET_PTP_TSUH */ #define ENET_PTP_TSUH_TMSUS BITS(0,31) /*!< timestamp update seconds */ - + /* ENET_PTP_TSUL */ #define ENET_PTP_TSUL_TMSUSS BITS(0,30) /*!< timestamp update subseconds */ #define ENET_PTP_TSUL_TMSUPNS BIT(31) /*!< timestamp update positive or negative sign */ /* ENET_PTP_TSADDAND */ #define ENET_PTP_TSADDAND_TMSA BITS(0,31) /*!< timestamp addend */ - + /* ENET_PTP_ETH */ #define ENET_PTP_ETH_ETSH BITS(0,31) /*!< expected time high */ - + /* ENET_PTP_ETL */ #define ENET_PTP_ETL_ETSL BITS(0,31) /*!< expected time low */ - + /* ENET_PTP_TSF */ #define ENET_PTP_TSF_TSSCO BIT(0) /*!< timestamp second counter overflow */ #define ENET_PTP_TSF_TTM BIT(1) /*!< target time match */ - + /* ENET_PTP_PPSCTL */ #define ENET_PTP_PPSCTL_PPSOFC BITS(0,3) /*!< PPS output frequency configure */ @@ -403,19 +428,19 @@ #define ENET_DMA_BCTL_FPBL BIT(24) /*!< four times PGBL mode */ #define ENET_DMA_BCTL_AA BIT(25) /*!< address-aligned */ #define ENET_DMA_BCTL_MB BIT(26) /*!< mixed burst */ - + /* ENET_DMA_TPEN */ #define ENET_DMA_TPEN_TPE BITS(0,31) /*!< transmit poll enable */ - + /* ENET_DMA_RPEN */ #define ENET_DMA_RPEN_RPE BITS(0,31) /*!< receive poll enable */ /* ENET_DMA_RDTADDR */ #define ENET_DMA_RDTADDR_SRT BITS(0,31) /*!< start address of receive table */ - + /* ENET_DMA_TDTADDR */ #define ENET_DMA_TDTADDR_STT BITS(0,31) /*!< start address of transmit table */ - + /* ENET_DMA_STAT */ #define ENET_DMA_STAT_TS BIT(0) /*!< transmit status */ #define ENET_DMA_STAT_TPS BIT(1) /*!< transmit process stopped status */ @@ -438,7 +463,7 @@ #define ENET_DMA_STAT_MSC BIT(27) /*!< MSC status */ #define ENET_DMA_STAT_WUM BIT(28) /*!< WUM status */ #define ENET_DMA_STAT_TST BIT(29) /*!< timestamp trigger status */ - + /* ENET_DMA_CTL */ #define ENET_DMA_CTL_SRE BIT(1) /*!< start/stop receive enable */ #define ENET_DMA_CTL_OSF BIT(2) /*!< operate on second frame */ @@ -452,7 +477,7 @@ #define ENET_DMA_CTL_DAFRF BIT(24) /*!< disable flushing of received frames */ #define ENET_DMA_CTL_RSFD BIT(25) /*!< receive store-and-forward */ #define ENET_DMA_CTL_DTCERFD BIT(26) /*!< dropping of TCP/IP checksum error frames disable */ - + /* ENET_DMA_INTEN */ #define ENET_DMA_INTEN_TIE BIT(0) /*!< transmit interrupt enable */ #define ENET_DMA_INTEN_TPSIE BIT(1) /*!< transmit process stopped interrupt enable */ @@ -469,7 +494,7 @@ #define ENET_DMA_INTEN_ERIE BIT(14) /*!< early receive interrupt enable */ #define ENET_DMA_INTEN_AIE BIT(15) /*!< abnormal interrupt summary enable */ #define ENET_DMA_INTEN_NIE BIT(16) /*!< normal interrupt summary enable */ - + /* ENET_DMA_MFBOCNT */ #define ENET_DMA_MFBOCNT_MSFC BITS(0,15) /*!< missed frames by the controller */ #define ENET_DMA_MFBOCNT_MSFA BITS(17,27) /*!< missed frames by the application */ @@ -482,10 +507,10 @@ /* ENET_DMA_CRDADDR */ #define ENET_DMA_CRDADDR_RDAP BITS(0,31) /*!< receive descriptor address pointer */ - + /* ENET_DMA_CTBADDR */ #define ENET_DMA_CTBADDR_TBAP BITS(0,31) /*!< transmit buffer address pointer */ - + /* ENET_DMA_CRBADDR */ #define ENET_DMA_CRBADDR_RBAP BITS(0,31) /*!< receive buffer address pointer */ @@ -545,7 +570,7 @@ #define ENET_RDES0_LCO BIT(6) /*!< late collision */ #define ENET_RDES0_IPHERR BIT(7) /*!< IP frame header error */ #define ENET_RDES0_TSV BIT(7) /*!< timestamp valid */ -#define ENET_RDES0_LDES BIT(8) /*!< last descriptor */ +#define ENET_RDES0_LDES BIT(8) /*!< last descriptor */ #define ENET_RDES0_FDES BIT(9) /*!< first descriptor */ #define ENET_RDES0_VTAG BIT(10) /*!< VLAN tag */ #define ENET_RDES0_OERR BIT(11) /*!< overflow Error */ @@ -557,7 +582,7 @@ #define ENET_RDES0_DAFF BIT(30) /*!< destination address filter fail */ #define ENET_RDES0_DAV BIT(31) /*!< descriptor available */ -/* ENET DMA Rx descriptor RDES1 */ +/* ENET DMA Rx descriptor RDES1 */ #define ENET_RDES1_RB1S BITS(0,12) /*!< receive buffer 1 size */ #define ENET_RDES1_RCHM BIT(14) /*!< receive chained mode for second address */ #define ENET_RDES1_RERM BIT(15) /*!< receive end of ring mode*/ @@ -592,53 +617,53 @@ /* constants definitions */ /* define bit position and its register index offset */ #define ENET_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define ENET_REG_VAL(periph) (REG32(ENET + ((uint32_t)(periph)>>6))) +#define ENET_REG_VAL(periph) (REG32(ENET + ((uint32_t)(periph) >> 6))) #define ENET_BIT_POS(val) ((uint32_t)(val) & 0x1FU) /* ENET clock range judgement */ #define ENET_RANGE(hclk, n, m) (((hclk) >= (n))&&((hclk) < (m))) /* define MAC address configuration and reference address */ -#define ENET_SET_MACADDRH(p) (((uint32_t)(p)[5] << 8) | (uint32_t)(p)[4]) +#define ENET_SET_MACADDRH(p) (((uint32_t)(p)[5] << 8) | (uint32_t)(p)[4]) #define ENET_SET_MACADDRL(p) (((uint32_t)(p)[3] << 24) | ((uint32_t)(p)[2] << 16) | ((uint32_t)(p)[1] << 8) | (uint32_t)(p)[0]) #define ENET_ADDRH_BASE ((ENET) + 0x40U) #define ENET_ADDRL_BASE ((ENET) + 0x44U) #define ENET_GET_MACADDR(offset, n) ((uint8_t)((REG32((ENET_ADDRL_BASE + (offset)) - (((n) / 4U) * 4U)) >> (8U * ((n) % 4U))) & 0xFFU)) /* register offset */ -#define MAC_FCTL_REG_OFFSET 0x0018U /*!< MAC flow control register offset */ -#define MAC_WUM_REG_OFFSET 0x002CU /*!< MAC wakeup management register offset */ -#define MAC_INTF_REG_OFFSET 0x0038U /*!< MAC interrupt flag register offset */ -#define MAC_INTMSK_REG_OFFSET 0x003CU /*!< MAC interrupt mask register offset */ +#define MAC_FCTL_REG_OFFSET ((uint16_t)0x0018U) /*!< MAC flow control register offset */ +#define MAC_WUM_REG_OFFSET ((uint16_t)0x002CU) /*!< MAC wakeup management register offset */ +#define MAC_INTF_REG_OFFSET ((uint16_t)0x0038U) /*!< MAC interrupt flag register offset */ +#define MAC_INTMSK_REG_OFFSET ((uint16_t)0x003CU) /*!< MAC interrupt mask register offset */ -#define MSC_RINTF_REG_OFFSET 0x0104U /*!< MSC receive interrupt flag register offset */ -#define MSC_TINTF_REG_OFFSET 0x0108U /*!< MSC transmit interrupt flag register offset */ -#define MSC_RINTMSK_REG_OFFSET 0x010CU /*!< MSC receive interrupt mask register offset */ -#define MSC_TINTMSK_REG_OFFSET 0x0110U /*!< MSC transmit interrupt mask register offset */ -#define MSC_SCCNT_REG_OFFSET 0x014CU /*!< MSC transmitted good frames after a single collision counter register offset */ -#define MSC_MSCCNT_REG_OFFSET 0x0150U /*!< MSC transmitted good frames after more than a single collision counter register offset */ -#define MSC_TGFCNT_REG_OFFSET 0x0168U /*!< MSC transmitted good frames counter register offset */ -#define MSC_RFCECNT_REG_OFFSET 0x0194U /*!< MSC received frames with CRC error counter register offset */ -#define MSC_RFAECNT_REG_OFFSET 0x0198U /*!< MSC received frames with alignment error counter register offset */ -#define MSC_RGUFCNT_REG_OFFSET 0x01C4U /*!< MSC received good unicast frames counter register offset */ - -#define PTP_TSF_REG_OFFSET 0x0728U /*!< PTP time stamp flag register offset */ +#define MSC_RINTF_REG_OFFSET ((uint16_t)0x0104U) /*!< MSC receive interrupt flag register offset */ +#define MSC_TINTF_REG_OFFSET ((uint16_t)0x0108U) /*!< MSC transmit interrupt flag register offset */ +#define MSC_RINTMSK_REG_OFFSET ((uint16_t)0x010CU) /*!< MSC receive interrupt mask register offset */ +#define MSC_TINTMSK_REG_OFFSET ((uint16_t)0x0110U) /*!< MSC transmit interrupt mask register offset */ +#define MSC_SCCNT_REG_OFFSET ((uint16_t)0x014CU) /*!< MSC transmitted good frames after a single collision counter register offset */ +#define MSC_MSCCNT_REG_OFFSET ((uint16_t)0x0150U) /*!< MSC transmitted good frames after more than a single collision counter register offset */ +#define MSC_TGFCNT_REG_OFFSET ((uint16_t)0x0168U) /*!< MSC transmitted good frames counter register offset */ +#define MSC_RFCECNT_REG_OFFSET ((uint16_t)0x0194U) /*!< MSC received frames with CRC error counter register offset */ +#define MSC_RFAECNT_REG_OFFSET ((uint16_t)0x0198U) /*!< MSC received frames with alignment error counter register offset */ +#define MSC_RGUFCNT_REG_OFFSET ((uint16_t)0x01C4U) /*!< MSC received good unicast frames counter register offset */ -#define DMA_STAT_REG_OFFSET 0x1014U /*!< DMA status register offset */ -#define DMA_INTEN_REG_OFFSET 0x101CU /*!< DMA interrupt enable register offset */ -#define DMA_TDTADDR_REG_OFFSET 0x1010U /*!< DMA transmit descriptor table address register offset */ -#define DMA_CTDADDR_REG_OFFSET 0x1048U /*!< DMA current transmit descriptor address register */ -#define DMA_CTBADDR_REG_OFFSET 0x1050U /*!< DMA current transmit buffer address register */ -#define DMA_RDTADDR_REG_OFFSET 0x100CU /*!< DMA receive descriptor table address register */ -#define DMA_CRDADDR_REG_OFFSET 0x104CU /*!< DMA current receive descriptor address register */ -#define DMA_CRBADDR_REG_OFFSET 0x1054U /*!< DMA current receive buffer address register */ +#define PTP_TSF_REG_OFFSET ((uint16_t)0x0728U) /*!< PTP time stamp flag register offset */ + +#define DMA_STAT_REG_OFFSET ((uint16_t)0x1014U) /*!< DMA status register offset */ +#define DMA_INTEN_REG_OFFSET ((uint16_t)0x101CU) /*!< DMA interrupt enable register offset */ +#define DMA_TDTADDR_REG_OFFSET ((uint16_t)0x1010U) /*!< DMA transmit descriptor table address register offset */ +#define DMA_CTDADDR_REG_OFFSET ((uint16_t)0x1048U) /*!< DMA current transmit descriptor address register */ +#define DMA_CTBADDR_REG_OFFSET ((uint16_t)0x1050U) /*!< DMA current transmit buffer address register */ +#define DMA_RDTADDR_REG_OFFSET ((uint16_t)0x100CU) /*!< DMA receive descriptor table address register */ +#define DMA_CRDADDR_REG_OFFSET ((uint16_t)0x104CU) /*!< DMA current receive descriptor address register */ +#define DMA_CRBADDR_REG_OFFSET ((uint16_t)0x1054U) /*!< DMA current receive buffer address register */ /* ENET status flag get */ typedef enum { /* ENET_MAC_WUM register */ ENET_MAC_FLAG_MPKR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 5U), /*!< magic packet received flag */ - ENET_MAC_FLAG_WUFR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 6U), /*!< wakeup frame received flag */ + ENET_MAC_FLAG_WUFR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 6U), /*!< wakeup frame received flag */ /* ENET_MAC_FCTL register */ ENET_MAC_FLAG_FLOWCONTROL = ENET_REGIDX_BIT(MAC_FCTL_REG_OFFSET, 0U), /*!< flow control status flag */ /* ENET_MAC_INTF register */ @@ -648,13 +673,13 @@ typedef enum ENET_MAC_FLAG_MSCT = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 6U), /*!< MSC transmit status flag */ ENET_MAC_FLAG_TMST = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 9U), /*!< timestamp trigger status flag */ /* ENET_PTP_TSF register */ - ENET_PTP_FLAG_TSSCO = ENET_REGIDX_BIT(PTP_TSF_REG_OFFSET, 0U), /*!< timestamp second counter overflow flag */ + ENET_PTP_FLAG_TSSCO = ENET_REGIDX_BIT(PTP_TSF_REG_OFFSET, 0U), /*!< timestamp second counter overflow flag */ ENET_PTP_FLAG_TTM = ENET_REGIDX_BIT(PTP_TSF_REG_OFFSET, 1U), /*!< target time match flag */ /* ENET_MSC_RINTF register */ ENET_MSC_FLAG_RFCE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 5U), /*!< received frames CRC error flag */ ENET_MSC_FLAG_RFAE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 6U), /*!< received frames alignment error flag */ ENET_MSC_FLAG_RGUF = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 17U), /*!< received good unicast frames flag */ - /* ENET_MSC_TINTF register */ + /* ENET_MSC_TINTF register */ ENET_MSC_FLAG_TGFSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 14U), /*!< transmitted good frames single collision flag */ ENET_MSC_FLAG_TGFMSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 15U), /*!< transmitted good frames more single collision flag */ ENET_MSC_FLAG_TGF = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 21U), /*!< transmitted good frames flag */ @@ -679,7 +704,7 @@ typedef enum ENET_DMA_FLAG_EB_ACCESS_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 25U), /*!< error during data buffer/descriptor access flag */ ENET_DMA_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U), /*!< MSC status flag */ ENET_DMA_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U), /*!< WUM status flag */ - ENET_DMA_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */ + ENET_DMA_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */ }enet_flag_enum; /* ENET stutus flag clear */ @@ -700,7 +725,7 @@ typedef enum ENET_DMA_FLAG_FBE_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ ENET_DMA_FLAG_ER_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ ENET_DMA_FLAG_AI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ - ENET_DMA_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ + ENET_DMA_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ }enet_flag_clear_enum; /* ENET interrupt enable/disable */ @@ -709,15 +734,15 @@ typedef enum /* ENET_MAC_INTMSK register */ ENET_MAC_INT_WUMIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 3U), /*!< WUM interrupt mask */ ENET_MAC_INT_TMSTIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 9U), /*!< timestamp trigger interrupt mask */ - /* ENET_MSC_RINTMSK register */ + /* ENET_MSC_RINTMSK register */ ENET_MSC_INT_RFCEIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 5U), /*!< received frame CRC error interrupt mask */ ENET_MSC_INT_RFAEIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 6U), /*!< received frames alignment error interrupt mask */ ENET_MSC_INT_RGUFIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 17U), /*!< received good unicast frames interrupt mask */ - /* ENET_MSC_TINTMSK register */ + /* ENET_MSC_TINTMSK register */ ENET_MSC_INT_TGFSCIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 14U), /*!< transmitted good frames single collision interrupt mask */ ENET_MSC_INT_TGFMSCIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 15U), /*!< transmitted good frames more single collision interrupt mask */ ENET_MSC_INT_TGFIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 21U), /*!< transmitted good frames interrupt mask */ - /* ENET_DMA_INTEN register */ + /* ENET_DMA_INTEN register */ ENET_DMA_INT_TIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 0U), /*!< transmit interrupt enable */ ENET_DMA_INT_TPSIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 1U), /*!< transmit process stopped interrupt enable */ ENET_DMA_INT_TBUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 2U), /*!< transmit buffer unavailable interrupt enable */ @@ -734,7 +759,7 @@ typedef enum ENET_DMA_INT_AIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 15U), /*!< abnormal interrupt summary enable */ ENET_DMA_INT_NIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 16U), /*!< normal interrupt summary enable */ }enet_int_enum; - + /* ENET interrupt flag get */ typedef enum { @@ -770,7 +795,7 @@ typedef enum ENET_DMA_INT_FLAG_NI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ ENET_DMA_INT_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U), /*!< MSC status flag */ ENET_DMA_INT_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U), /*!< WUM status flag */ - ENET_DMA_INT_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */ + ENET_DMA_INT_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */ }enet_int_flag_enum; /* ENET interrupt flag clear */ @@ -814,7 +839,7 @@ typedef enum ENET_MSC_RX_RFCECNT = MSC_RFCECNT_REG_OFFSET, /*!< MSC received frames with CRC error counter */ ENET_MSC_RX_RFAECNT = MSC_RFAECNT_REG_OFFSET, /*!< MSC received frames with alignment error counter */ ENET_MSC_RX_RGUFCNT = MSC_RGUFCNT_REG_OFFSET /*!< MSC received good unicast frames counter */ -}enet_msc_counter_enum; +}enet_msc_counter_enum; /* function option, used for ENET initialization */ typedef enum @@ -838,7 +863,7 @@ typedef enum /* phy mode and mac loopback configurations */ typedef enum { - ENET_AUTO_NEGOTIATION = 0x01u, /*!< PHY auto negotiation */ + ENET_AUTO_NEGOTIATION = 0x01U, /*!< PHY auto negotiation */ ENET_100M_FULLDUPLEX = (ENET_MAC_CFG_SPD | ENET_MAC_CFG_DPM), /*!< 100Mbit/s, full-duplex */ ENET_100M_HALFDUPLEX = ENET_MAC_CFG_SPD , /*!< 100Mbit/s, half-duplex */ ENET_10M_FULLDUPLEX = ENET_MAC_CFG_DPM, /*!< 10Mbit/s, full-duplex */ @@ -867,10 +892,10 @@ typedef enum /* register group value get */ typedef enum { - ALL_MAC_REG = 0, /*!< MAC register group */ - ALL_MSC_REG = 22, /*!< MSC register group */ - ALL_PTP_REG = 33, /*!< PTP register group */ - ALL_DMA_REG = 44, /*!< DMA register group */ + ALL_MAC_REG = 0U, /*!< MAC register group */ + ALL_MSC_REG = 22U, /*!< MSC register group */ + ALL_PTP_REG = 33U, /*!< PTP register group */ + ALL_DMA_REG = 44U, /*!< DMA register group */ }enet_registers_type_enum; /* dma direction select */ @@ -894,7 +919,7 @@ typedef enum ENET_REG_WRITE /*!< write register */ }enet_regdirection_enum; -/* ENET MAC addresses */ +/* ENET MAC addresses */ typedef enum { ENET_MAC_ADDRESS0 = ((uint32_t)0x00000000), /*!< MAC address0 */ @@ -928,7 +953,7 @@ typedef enum{ ENET_CKNT_END_TO_END = PTP_TSCTL_CKNT(2), /*!< type of end-to-end transparent clock node type for timestamp */ ENET_CKNT_PEER_TO_PEER = PTP_TSCTL_CKNT(3), /*!< type of peer-to-peer transparent clock node type for timestamp */ ENET_PTP_SYSTIME_INIT = ENET_PTP_TSCTL_TMSSTI, /*!< timestamp initialize */ - ENET_PTP_SYSTIME_UPDATE = ENET_PTP_TSCTL_TMSSTU, /*!< timestamp update */ + ENET_PTP_SYSTIME_UPDATE = ENET_PTP_TSCTL_TMSSTU, /*!< timestamp update */ ENET_PTP_ADDEND_UPDATE = ENET_PTP_TSCTL_TMSARU, /*!< addend register update */ ENET_PTP_FINEMODE = (int32_t)(ENET_PTP_TSCTL_TMSFCU| BIT(31)), /*!< the system timestamp uses the fine method for updating */ ENET_PTP_COARSEMODE = ENET_PTP_TSCTL_TMSFCU, /*!< the system timestamp uses the coarse method for updating */ @@ -946,24 +971,24 @@ typedef enum{ typedef struct { uint32_t option_enable; /*!< select which function to configure */ - uint32_t forward_frame; /*!< frame forward related parameters */ + uint32_t forward_frame; /*!< frame forward related parameters */ uint32_t dmabus_mode; /*!< DMA bus mode related parameters */ uint32_t dma_maxburst; /*!< DMA max burst related parameters */ uint32_t dma_arbitration; /*!< DMA Tx and Rx arbitration related parameters */ uint32_t store_forward_mode; /*!< store forward mode related parameters */ uint32_t dma_function; /*!< DMA control related parameters */ - uint32_t vlan_config; /*!< VLAN tag related parameters */ + uint32_t vlan_config; /*!< VLAN tag related parameters */ uint32_t flow_control; /*!< flow control related parameters */ uint32_t hashtable_high; /*!< hash list high 32-bit related parameters */ uint32_t hashtable_low; /*!< hash list low 32-bit related parameters */ uint32_t framesfilter_mode; /*!< frame filter control related parameters */ - uint32_t halfduplex_param; /*!< halfduplex related parameters */ + uint32_t halfduplex_param; /*!< halfduplex related parameters */ uint32_t timer_config; /*!< frame timer related parameters */ uint32_t interframegap; /*!< inter frame gap related parameters */ }enet_initpara_struct; -/* structure for ENET DMA desciptors */ -typedef struct +/* structure for ENET DMA desciptors */ +typedef struct { uint32_t status; /*!< status */ uint32_t control_buffer_size; /*!< control and buffer1, buffer2 lengths */ @@ -974,12 +999,12 @@ typedef struct uint32_t extended_status; /*!< extended status */ uint32_t reserved; /*!< reserved */ uint32_t timestamp_low; /*!< timestamp low */ - uint32_t timestamp_high; /*!< timestamp high */ -#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ - + uint32_t timestamp_high; /*!< timestamp high */ +#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ + } enet_descriptors_struct; -/* structure of PTP system time */ +/* structure of PTP system time */ typedef struct { uint32_t second; /*!< second of system time */ @@ -992,17 +1017,17 @@ typedef struct #define ENET_BACKOFFLIMIT_10 MAC_CFG_BOL(0) /*!< min (n, 10) */ #define ENET_BACKOFFLIMIT_8 MAC_CFG_BOL(1) /*!< min (n, 8) */ #define ENET_BACKOFFLIMIT_4 MAC_CFG_BOL(2) /*!< min (n, 4) */ -#define ENET_BACKOFFLIMIT_1 MAC_CFG_BOL(3) /*!< min (n, 1) */ +#define ENET_BACKOFFLIMIT_1 MAC_CFG_BOL(3) /*!< min (n, 1) */ #define MAC_CFG_IGBS(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ENET_MAC_CFG_IGBS bit field */ -#define ENET_INTERFRAMEGAP_96BIT MAC_CFG_IGBS(0) /*!< minimum 96 bit times */ +#define ENET_INTERFRAMEGAP_96BIT MAC_CFG_IGBS(0) /*!< minimum 96 bit times */ #define ENET_INTERFRAMEGAP_88BIT MAC_CFG_IGBS(1) /*!< minimum 88 bit times */ #define ENET_INTERFRAMEGAP_80BIT MAC_CFG_IGBS(2) /*!< minimum 80 bit times */ #define ENET_INTERFRAMEGAP_72BIT MAC_CFG_IGBS(3) /*!< minimum 72 bit times */ -#define ENET_INTERFRAMEGAP_64BIT MAC_CFG_IGBS(4) /*!< minimum 64 bit times */ +#define ENET_INTERFRAMEGAP_64BIT MAC_CFG_IGBS(4) /*!< minimum 64 bit times */ #define ENET_INTERFRAMEGAP_56BIT MAC_CFG_IGBS(5) /*!< minimum 56 bit times */ #define ENET_INTERFRAMEGAP_48BIT MAC_CFG_IGBS(6) /*!< minimum 48 bit times */ -#define ENET_INTERFRAMEGAP_40BIT MAC_CFG_IGBS(7) /*!< minimum 40 bit times */ +#define ENET_INTERFRAMEGAP_40BIT MAC_CFG_IGBS(7) /*!< minimum 40 bit times */ #define ENET_TYPEFRAME_CRC_DROP_ENABLE ENET_MAC_CFG_TFCD /*!< FCS field(last 4 bytes) of frame will be dropped before forwarding */ #define ENET_TYPEFRAME_CRC_DROP_DISABLE ((uint32_t)0x00000000U) /*!< FCS field(last 4 bytes) of frame will not be dropped before forwarding */ @@ -1010,13 +1035,13 @@ typedef struct #define ENET_WATCHDOG_ENABLE ((uint32_t)0x00000000U) /*!< the MAC allows no more than 2048 bytes of the frame being received */ #define ENET_WATCHDOG_DISABLE ENET_MAC_CFG_WDD /*!< the MAC disables the watchdog timer on the receiver, and can receive frames of up to 16384 bytes */ - + #define ENET_JABBER_ENABLE ((uint32_t)0x00000000U) /*!< the maximum transmission byte is 2048 */ #define ENET_JABBER_DISABLE ENET_MAC_CFG_JBD /*!< the maximum transmission byte can be 16384 */ #define ENET_CARRIERSENSE_ENABLE ((uint32_t)0x00000000U) /*!< the MAC transmitter generates carrier sense error and aborts the transmission */ #define ENET_CARRIERSENSE_DISABLE ENET_MAC_CFG_CSD /*!< the MAC transmitter ignores the MII CRS signal during frame transmission in half-duplex mode */ - + #define ENET_SPEEDMODE_10M ((uint32_t)0x00000000U) /*!< 10 Mbit/s */ #define ENET_SPEEDMODE_100M ENET_MAC_CFG_SPD /*!< 100 Mbit/s */ @@ -1048,10 +1073,10 @@ typedef struct #define ENET_PCFRM_PREVENT_PAUSEFRAME MAC_FRMF_PCFRM(1) /*!< MAC only forwards all other control frames except pause control frame */ #define ENET_PCFRM_FORWARD_ALL MAC_FRMF_PCFRM(2) /*!< MAC forwards all control frames to application even if they fail the address filter */ #define ENET_PCFRM_FORWARD_FILTERED MAC_FRMF_PCFRM(3) /*!< MAC forwards control frames that only pass the address filter */ - + #define ENET_RX_FILTER_DISABLE ENET_MAC_FRMF_FAR /*!< all received frame are forwarded to application */ #define ENET_RX_FILTER_ENABLE ((uint32_t)0x00000000U) /*!< only the frame passed the filter can be forwarded to application */ - + #define ENET_SRC_FILTER_NORMAL_ENABLE ENET_MAC_FRMF_SAFLT /*!< filter source address */ #define ENET_SRC_FILTER_INVERSE_ENABLE (ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT) /*!< inverse source address filtering result */ #define ENET_SRC_FILTER_DISABLE ((uint32_t)0x00000000U) /*!< source address function in filter disable */ @@ -1060,14 +1085,14 @@ typedef struct #define ENET_BROADCASTFRAMES_ENABLE ((uint32_t)0x00000000U) /*!< the address filters pass all received broadcast frames */ #define ENET_BROADCASTFRAMES_DISABLE ENET_MAC_FRMF_BFRMD /*!< the address filters filter all incoming broadcast frames */ - + #define ENET_DEST_FILTER_INVERSE_ENABLE ENET_MAC_FRMF_DAIFLT /*!< inverse DA filtering result */ #define ENET_DEST_FILTER_INVERSE_DISABLE ((uint32_t)0x00000000U) /*!< not inverse DA filtering result */ #define ENET_DEST_FILTER_INVERSE ENET_MAC_FRMF_DAIFLT /*!< inverse DA filtering result function */ #define ENET_PROMISCUOUS_ENABLE ENET_MAC_FRMF_PM /*!< promiscuous mode enabled */ #define ENET_PROMISCUOUS_DISABLE ((uint32_t)0x00000000U) /*!< promiscuous mode disabled */ - + #define ENET_MULTICAST_FILTER_HASH_OR_PERFECT (ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT) /*!< pass multicast frames that match either the perfect or the hash filtering */ #define ENET_MULTICAST_FILTER_HASH ENET_MAC_FRMF_HMF /*!< pass multicast frames that match the hash filtering */ #define ENET_MULTICAST_FILTER_PERFECT ((uint32_t)0x00000000U) /*!< pass multicast frames that match the perfect filtering */ @@ -1101,7 +1126,7 @@ typedef struct #define ENET_PAUSETIME_MINUS4 MAC_FCTL_PLTS(0) /*!< pause time minus 4 slot times */ #define ENET_PAUSETIME_MINUS28 MAC_FCTL_PLTS(1) /*!< pause time minus 28 slot times */ #define ENET_PAUSETIME_MINUS144 MAC_FCTL_PLTS(2) /*!< pause time minus 144 slot times */ -#define ENET_PAUSETIME_MINUS256 MAC_FCTL_PLTS(3) /*!< pause time minus 256 slot times */ +#define ENET_PAUSETIME_MINUS256 MAC_FCTL_PLTS(3) /*!< pause time minus 256 slot times */ #define ENET_ZERO_QUANTA_PAUSE_ENABLE ((uint32_t)0x00000000U) /*!< enable the automatic zero-quanta generation function */ #define ENET_ZERO_QUANTA_PAUSE_DISABLE ENET_MAC_FCTL_DZQP /*!< disable the automatic zero-quanta generation function */ @@ -1109,7 +1134,7 @@ typedef struct #define ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT ENET_MAC_FCTL_UPFDT /*!< besides the unique multicast address, MAC also use the MAC0 address to detect pause frame */ #define ENET_UNIQUE_PAUSEDETECT ((uint32_t)0x00000000U) /*!< only the unique multicast address for pause frame which is specified in IEEE802.3 can be detected */ - + #define ENET_RX_FLOWCONTROL_ENABLE ENET_MAC_FCTL_RFCEN /*!< enable decoding function for the received pause frame and process it */ #define ENET_RX_FLOWCONTROL_DISABLE ((uint32_t)0x00000000U) /*!< decode function for pause frame is disabled */ #define ENET_RX_FLOWCONTROL ENET_MAC_FCTL_RFCEN /*!< decoding function for the received pause frame and process it */ @@ -1121,33 +1146,34 @@ typedef struct #define ENET_BACK_PRESSURE_ENABLE ENET_MAC_FCTL_FLCBBKPA /*!< enable the back pressure operation in the MAC */ #define ENET_BACK_PRESSURE_DISABLE ((uint32_t)0x00000000U) /*!< disable the back pressure operation in the MAC */ #define ENET_BACK_PRESSURE ENET_MAC_FCTL_FLCBBKPA /*!< the back pressure operation in the MAC */ - + #define MAC_FCTL_PTM(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) /*!< write value to ENET_MAC_FCTL_PTM bit field */ /* mac_vlt register value */ #define MAC_VLT_VLTI(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_VLT_VLTI bit field */ - + #define ENET_VLANTAGCOMPARISON_12BIT ENET_MAC_VLT_VLTC /*!< only low 12 bits of the VLAN tag are used for comparison */ #define ENET_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U) /*!< all 16 bits of the VLAN tag are used for comparison */ -/* mac_wum register value */ +/* mac_wum register value */ #define ENET_WUM_FLAG_WUFFRPR ENET_MAC_WUM_WUFFRPR /*!< wakeup frame filter register poniter reset */ #define ENET_WUM_FLAG_WUFR ENET_MAC_WUM_WUFR /*!< wakeup frame received */ #define ENET_WUM_FLAG_MPKR ENET_MAC_WUM_MPKR /*!< magic packet received */ -#define ENET_WUM_POWER_DOWN ENET_MAC_WUM_PWD /*!< power down mode */ -#define ENET_WUM_MAGIC_PACKET_FRAME ENET_MAC_WUM_MPEN /*!< enable a wakeup event due to magic packet reception */ -#define ENET_WUM_WAKE_UP_FRAME ENET_MAC_WUM_WFEN /*!< enable a wakeup event due to wakeup frame reception */ +#define ENET_WUM_POWER_DOWN ENET_MAC_WUM_PWD /*!< power down mode */ +#define ENET_WUM_MAGIC_PACKET_FRAME ENET_MAC_WUM_MPEN /*!< enable a wakeup event due to magic packet reception */ +#define ENET_WUM_WAKE_UP_FRAME ENET_MAC_WUM_WFEN /*!< enable a wakeup event due to wakeup frame reception */ #define ENET_WUM_GLOBAL_UNICAST ENET_MAC_WUM_GU /*!< any received unicast frame passed filter is considered to be a wakeup frame */ + /* mac_dbg register value */ #define ENET_MAC_RECEIVER_NOT_IDLE ENET_MAC_DBG_MRNI /*!< MAC receiver is not in idle state */ #define ENET_RX_ASYNCHRONOUS_FIFO_STATE ENET_MAC_DBG_RXAFS /*!< Rx asynchronous FIFO status */ -#define ENET_RXFIFO_NOT_WRITING ENET_MAC_DBG_RXFW /*!< RxFIFO is not doing write operation */ +#define ENET_RXFIFO_WRITING ENET_MAC_DBG_RXFW /*!< RxFIFO is doing write operation */ #define ENET_RXFIFO_READ_STATUS ENET_MAC_DBG_RXFRS /*!< RxFIFO read operation status */ #define ENET_RXFIFO_STATE ENET_MAC_DBG_RXFS /*!< RxFIFO state */ #define ENET_MAC_TRANSMITTER_NOT_IDLE ENET_MAC_DBG_MTNI /*!< MAC transmitter is not in idle state */ #define ENET_MAC_TRANSMITTER_STATUS ENET_MAC_DBG_SOMT /*!< status of MAC transmitter */ #define ENET_PAUSE_CONDITION_STATUS ENET_MAC_DBG_PCS /*!< pause condition status */ #define ENET_TXFIFO_READ_STATUS ENET_MAC_DBG_TXFRS /*!< TxFIFO read operation status */ -#define ENET_TXFIFO_NOT_WRITING ENET_MAC_DBG_TXFW /*!< TxFIFO is not doing write operation */ +#define ENET_TXFIFO_WRITING ENET_MAC_DBG_TXFW /*!< TxFIFO is doing write operation */ #define ENET_TXFIFO_NOT_EMPTY ENET_MAC_DBG_TXFNE /*!< TxFIFO is not empty */ #define ENET_TXFIFO_FULL ENET_MAC_DBG_TXFF /*!< TxFIFO is full */ @@ -1176,7 +1202,7 @@ typedef struct #define ENET_ADDRESS_FILTER_SA BIT(30) /*!< use MAC address[47:0] is to compare with the SA fields of the received frame */ #define ENET_ADDRESS_FILTER_DA ((uint32_t)0x00000000) /*!< use MAC address[47:0] is to compare with the DA fields of the received frame */ - + /* mac_fcth register value */ #define MAC_FCTH_RFA(regval) ((BITS(0,2) & ((uint32_t)(regval) << 0))<<8) /*!< write value to ENET_MAC_FCTH_RFA bit field */ #define ENET_ACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFA(0) /*!< threshold level is 256 bytes */ @@ -1215,7 +1241,7 @@ typedef struct /* ptp_tsl register value */ #define GET_PTP_TSL_STMSS(regval) GET_BITS((uint32_t)(regval),0,30) /*!< get value of ENET_PTP_TSL_STMSS bit field */ - + #define ENET_PTP_TIME_POSITIVE ((uint32_t)0x00000000) /*!< time value is positive */ #define ENET_PTP_TIME_NEGATIVE ENET_PTP_TSL_STS /*!< time value is negative */ @@ -1259,7 +1285,7 @@ typedef struct #define ENET_PGBL_4BEAT DMA_BCTL_PGBL(4) /*!< maximum number of beats is 4 */ #define ENET_PGBL_8BEAT DMA_BCTL_PGBL(8) /*!< maximum number of beats is 8 */ #define ENET_PGBL_16BEAT DMA_BCTL_PGBL(16) /*!< maximum number of beats is 16 */ -#define ENET_PGBL_32BEAT DMA_BCTL_PGBL(32) /*!< maximum number of beats is 32 */ +#define ENET_PGBL_32BEAT DMA_BCTL_PGBL(32) /*!< maximum number of beats is 32 */ #define ENET_PGBL_4xPGBL_4BEAT (DMA_BCTL_PGBL(1)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 4 */ #define ENET_PGBL_4xPGBL_8BEAT (DMA_BCTL_PGBL(2)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 8 */ #define ENET_PGBL_4xPGBL_16BEAT (DMA_BCTL_PGBL(4)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 16 */ @@ -1271,7 +1297,7 @@ typedef struct #define ENET_ARBITRATION_RXTX_1_1 DMA_BCTL_RTPR(0) /*!< receive and transmit priority ratio is 1:1*/ #define ENET_ARBITRATION_RXTX_2_1 DMA_BCTL_RTPR(1) /*!< receive and transmit priority ratio is 2:1*/ #define ENET_ARBITRATION_RXTX_3_1 DMA_BCTL_RTPR(2) /*!< receive and transmit priority ratio is 3:1 */ -#define ENET_ARBITRATION_RXTX_4_1 DMA_BCTL_RTPR(3) /*!< receive and transmit priority ratio is 4:1 */ +#define ENET_ARBITRATION_RXTX_4_1 DMA_BCTL_RTPR(3) /*!< receive and transmit priority ratio is 4:1 */ #define ENET_ARBITRATION_RXPRIORTX ENET_DMA_BCTL_DAB /*!< RxDMA has higher priority than TxDMA */ #define ENET_FIXED_BURST_ENABLE ENET_DMA_BCTL_FB /*!< AHB can only use SINGLE/INCR4/INCR8/INCR16 during start of normal burst transfers */ @@ -1283,13 +1309,13 @@ typedef struct #define ENET_RXDP_4BEAT DMA_BCTL_RXDP(4) /*!< maximum number of beats 4 */ #define ENET_RXDP_8BEAT DMA_BCTL_RXDP(8) /*!< maximum number of beats 8 */ #define ENET_RXDP_16BEAT DMA_BCTL_RXDP(16) /*!< maximum number of beats 16 */ -#define ENET_RXDP_32BEAT DMA_BCTL_RXDP(32) /*!< maximum number of beats 32 */ +#define ENET_RXDP_32BEAT DMA_BCTL_RXDP(32) /*!< maximum number of beats 32 */ #define ENET_RXDP_4xPGBL_4BEAT (DMA_BCTL_RXDP(1)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 4 */ #define ENET_RXDP_4xPGBL_8BEAT (DMA_BCTL_RXDP(2)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 8 */ #define ENET_RXDP_4xPGBL_16BEAT (DMA_BCTL_RXDP(4)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 16 */ #define ENET_RXDP_4xPGBL_32BEAT (DMA_BCTL_RXDP(8)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 32 */ #define ENET_RXDP_4xPGBL_64BEAT (DMA_BCTL_RXDP(16)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 64 */ -#define ENET_RXDP_4xPGBL_128BEAT (DMA_BCTL_RXDP(32)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 128 */ +#define ENET_RXDP_4xPGBL_128BEAT (DMA_BCTL_RXDP(32)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 128 */ #define ENET_RXTX_DIFFERENT_PGBL ENET_DMA_BCTL_UIP /*!< RxDMA uses the RXDP[5:0], while TxDMA uses the PGBL[5:0] */ #define ENET_RXTX_SAME_PGBL ((uint32_t)0x00000000) /*!< RxDMA/TxDMA uses PGBL[5:0] */ @@ -1347,7 +1373,7 @@ typedef struct #define ENET_FLUSH_RXFRAME_ENABLE ((uint32_t)0x00000000) /*!< RxDMA flushes all frames */ #define ENET_FLUSH_RXFRAME_DISABLE ENET_DMA_CTL_DAFRF /*!< RxDMA does not flush any frames */ -#define ENET_FLUSH_RXFRAME ENET_DMA_CTL_DAFRF /*!< RxDMA flushes frames function */ +#define ENET_NO_FLUSH_RXFRAME ENET_DMA_CTL_DAFRF /*!< RxDMA flushes frames function */ #define ENET_TX_MODE_STOREFORWARD ENET_DMA_CTL_TSFD /*!< TxFIFO operates in store-and-forward mode */ #define ENET_TX_MODE_CUTTHROUGH ((uint32_t)0x00000000) /*!< TxFIFO operates in cut-through mode */ @@ -1357,7 +1383,7 @@ typedef struct #define ENET_FORWARD_ERRFRAMES (ENET_DMA_CTL_FERF<<2) /*!< the function that all frame received with error except runt error are forwarded to memory */ #define ENET_FORWARD_UNDERSZ_GOODFRAMES_ENABLE (ENET_DMA_CTL_FUF<<2) /*!< forward undersized good frames */ -#define ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE ((uint32_t)0x00000000) /*!< RxFIFO drops all frames whose length is less than 64 bytes */ +#define ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE ((uint32_t)0x00000000) /*!< RxFIFO drops all frames whose length is less than 64 bytes */ #define ENET_FORWARD_UNDERSZ_GOODFRAMES (ENET_DMA_CTL_FUF<<2) /*!< the function that forwarding undersized good frames */ #define ENET_SECONDFRAME_OPT_ENABLE ENET_DMA_CTL_OSF /*!< TxDMA controller operate on second frame mode enable*/ @@ -1376,10 +1402,10 @@ typedef struct #define GET_TDES0_COCNT(regval) GET_BITS((regval),3,6) /*!< get value of ENET DMA TDES0 CONT bit field */ #define TDES0_CM(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) /*!< write value to ENET DMA TDES0 CM bit field */ -#define ENET_CHECKSUM_DISABLE TDES0_CM(0) /*!< checksum insertion disabled */ -#define ENET_CHECKSUM_IPV4HEADER TDES0_CM(1) /*!< only IP header checksum calculation and insertion are enabled */ -#define ENET_CHECKSUM_TCPUDPICMP_SEGMENT TDES0_CM(2) /*!< TCP/UDP/ICMP checksum insertion calculated but pseudo-header */ -#define ENET_CHECKSUM_TCPUDPICMP_FULL TDES0_CM(3) /*!< TCP/UDP/ICMP checksum insertion fully calculated */ +#define ENET_CHECKSUM_DISABLE TDES0_CM(0) /*!< checksum insertion disabled */ +#define ENET_CHECKSUM_IPV4HEADER TDES0_CM(1) /*!< only IP header checksum calculation and insertion are enabled */ +#define ENET_CHECKSUM_TCPUDPICMP_SEGMENT TDES0_CM(2) /*!< TCP/UDP/ICMP checksum insertion calculated but pseudo-header */ +#define ENET_CHECKSUM_TCPUDPICMP_FULL TDES0_CM(3) /*!< TCP/UDP/ICMP checksum insertion fully calculated */ /* dma tx descriptor tdes1 register value */ #define TDES1_TB1S(regval) (BITS(0,12) & ((uint32_t)(regval) << 0)) /*!< write value to ENET DMA TDES1 TB1S bit field */ @@ -1413,18 +1439,18 @@ typedef struct #define ENET_MSC_PRESET_MASK (~(ENET_MSC_CTL_PMC | ENET_MSC_CTL_AFHPM)) /*!< ENET_MSC_CTL preset mask */ #ifdef SELECT_DESCRIPTORS_ENHANCED_MODE -#define ETH_DMATXDESC_SIZE 0x20U /*!< TxDMA enhanced descriptor size */ -#define ETH_DMARXDESC_SIZE 0x20U /*!< RxDMA enhanced descriptor size */ +#define ETH_DMATXDESC_SIZE ((uint32_t)0x00000020U) /*!< TxDMA enhanced descriptor size */ +#define ETH_DMARXDESC_SIZE ((uint32_t)0x00000020U) /*!< RxDMA enhanced descriptor size */ #else -#define ETH_DMATXDESC_SIZE 0x10U /*!< TxDMA descriptor size */ -#define ETH_DMARXDESC_SIZE 0x10U /*!< RxDMA descriptor size */ -#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ +#define ETH_DMATXDESC_SIZE ((uint32_t)0x00000010U) /*!< TxDMA descriptor size */ +#define ETH_DMARXDESC_SIZE ((uint32_t)0x00000010U) /*!< RxDMA descriptor size */ +#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ /* ENET remote wake-up frame register length */ #define ETH_WAKEUP_REGISTER_LENGTH 8U /*!< remote wake-up frame register length */ -/* ENET frame size */ -#define ENET_MAX_FRAME_SIZE 1524U /*!< header + frame_extra + payload + CRC */ +/* ENET frame size */ +#define ENET_MAX_FRAME_SIZE 1524U /*!< header + frame_extra + payload + CRC */ /* ENET delay timeout */ #define ENET_DELAY_TO ((uint32_t)0x0004FFFFU) /*!< ENET delay timeout */ @@ -1459,12 +1485,12 @@ ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length); /* configure the transmit IP frame checksum offload calculation and insertion */ void enet_transmit_checksum_config(enet_descriptors_struct *desc, uint32_t checksum); /* ENET Tx and Rx function enable (include MAC and DMA module) */ -void enet_enable(void); +void enet_enable(void); /* ENET Tx and Rx function disable (include MAC and DMA module) */ void enet_disable(void); /* configure MAC address */ void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[]); -/* get MAC address */ +/* get MAC address */ void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[]); /* get the ENET MAC/MSC/PTP/DMA status flag */ @@ -1532,7 +1558,7 @@ void enet_flowcontrol_feature_disable(uint32_t feature); /* DMA function */ /* get the dma transmit/receive process state */ -uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction); +uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction); /* poll the dma transmission/reception enable */ void enet_dmaprocess_resume(enet_dmadirection_enum direction); /* check and recover the Rx process */ @@ -1552,7 +1578,7 @@ FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag) /* set the bit flag of ENET dma tx descriptor */ void enet_desc_flag_set(enet_descriptors_struct *desc, uint32_t desc_flag); /* clear the bit flag of ENET dma tx descriptor */ -void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag); +void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag); /* when receiving the completed, set RS bit in ENET_DMA_STAT register will immediately set */ void enet_rx_desc_immediate_receive_complete_interrupt(enet_descriptors_struct *desc); /* when receiving the completed, set RS bit in ENET_DMA_STAT register will is set after a configurable delay time */ @@ -1616,13 +1642,13 @@ void enet_wum_feature_disable(uint32_t feature); /* MSC function */ /* reset the MAC statistics counters */ void enet_msc_counters_reset(void); -/* enable the MAC statistics counter features */ +/* enable the MAC statistics counter features */ void enet_msc_feature_enable(uint32_t feature); -/* disable the MAC statistics counter features */ +/* disable the MAC statistics counter features */ void enet_msc_feature_disable(uint32_t feature); /* configure MAC statistics counters preset mode */ void enet_msc_counters_preset_config(enet_msc_preset_enum mode); -/* get MAC statistics counter */ +/* get MAC statistics counter */ uint32_t enet_msc_counters_get(enet_msc_counter_enum counter); /* PTP function */ @@ -1649,16 +1675,6 @@ void enet_ptp_pps_output_frequency_config(uint32_t freq); /* internal function */ /* reset the ENET initpara struct, call it before using enet_initpara_config() */ void enet_initpara_reset(void); -/* initialize ENET peripheral with generally concerned parameters, call it by enet_init() */ -static void enet_default_init(void); -#ifdef USE_DELAY -/* user can provide more timing precise _ENET_DELAY_ function */ -#define _ENET_DELAY_ delay_ms -#else -/* insert a delay time */ -static void enet_delay(uint32_t ncount); -/* default _ENET_DELAY_ function with less precise timing */ -#define _ENET_DELAY_ enet_delay -#endif + #endif /* GD32F4XX_ENET_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_exmc.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_exmc.h index 3844c699d2..94baf2f6f3 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_exmc.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_exmc.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_exmc.h - \brief definitions for the EXMC + \file gd32f4xx_exmc.h + \brief definitions for the EXMC + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_EXMC_H @@ -15,224 +40,224 @@ #include "gd32f4xx.h" /* EXMC definitions */ -#define EXMC (EXMC_BASE) /*!< EXMC register base address */ -#define EXMC_NOR_PSRAM (EXMC_BASE - 0x40000000) /*!< EXMC NOR/PSRAM base address */ -#define EXMC_NAND (EXMC_BASE - 0x30000000) /*!< EXMC NAND base address */ -#define EXMC_PCCARD (EXMC_BASE - 0x10000000) /*!< EXMC PC card base address */ -#define EXMC_SDRAM (EXMC_BASE + 0x20000000) /*!< EXMC SDRAM base address */ +#define EXMC (EXMC_BASE) /*!< EXMC register base address */ +#define EXMC_NOR_PSRAM (EXMC_BASE - 0x40000000) /*!< EXMC NOR/PSRAM base address */ +#define EXMC_NAND (EXMC_BASE - 0x30000000) /*!< EXMC NAND base address */ +#define EXMC_PCCARD (EXMC_BASE - 0x10000000) /*!< EXMC PC card base address */ +#define EXMC_SDRAM (EXMC_BASE + 0x20000000) /*!< EXMC SDRAM base address */ /* registers definitions */ /* NOR/PSRAM */ -#define EXMC_SNCTL0 REG32(EXMC + 0x00U) /*!< EXMC SRAM/NOR flash control register */ -#define EXMC_SNTCFG0 REG32(EXMC + 0x04U) /*!< EXMC SRAM/NOR flash timing configuration register */ -#define EXMC_SNWTCFG0 REG32(EXMC + 0x104U) /*!< EXMC SRAM/NOR flash write timing configuration register */ +#define EXMC_SNCTL0 REG32(EXMC + 0x00U) /*!< EXMC SRAM/NOR flash control register for region0 */ +#define EXMC_SNTCFG0 REG32(EXMC + 0x04U) /*!< EXMC SRAM/NOR flash timing configuration register for region0 */ +#define EXMC_SNWTCFG0 REG32(EXMC + 0x104U) /*!< EXMC SRAM/NOR flash write timing configuration register for region0 */ -#define EXMC_SNCTL1 REG32(EXMC + 0x08U) /*!< EXMC SRAM/NOR flash control register */ -#define EXMC_SNTCFG1 REG32(EXMC + 0x0CU) /*!< EXMC SRAM/NOR flash timing configuration register */ -#define EXMC_SNWTCFG1 REG32(EXMC + 0x10CU) /*!< EXMC SRAM/NOR flash write timing configuration register */ +#define EXMC_SNCTL1 REG32(EXMC + 0x08U) /*!< EXMC SRAM/NOR flash control register for region1 */ +#define EXMC_SNTCFG1 REG32(EXMC + 0x0CU) /*!< EXMC SRAM/NOR flash timing configuration register for region1 */ +#define EXMC_SNWTCFG1 REG32(EXMC + 0x10CU) /*!< EXMC SRAM/NOR flash write timing configuration register for region1 */ -#define EXMC_SNCTL2 REG32(EXMC + 0x10U) /*!< EXMC SRAM/NOR flash control register */ -#define EXMC_SNTCFG2 REG32(EXMC + 0x14U) /*!< EXMC SRAM/NOR flash timing configuration register */ -#define EXMC_SNWTCFG2 REG32(EXMC + 0x114U) /*!< EXMC SRAM/NOR flash write timing configuration register */ +#define EXMC_SNCTL2 REG32(EXMC + 0x10U) /*!< EXMC SRAM/NOR flash control register for region2 */ +#define EXMC_SNTCFG2 REG32(EXMC + 0x14U) /*!< EXMC SRAM/NOR flash timing configuration register for region2 */ +#define EXMC_SNWTCFG2 REG32(EXMC + 0x114U) /*!< EXMC SRAM/NOR flash write timing configuration register for region2 */ -#define EXMC_SNCTL3 REG32(EXMC + 0x18U) /*!< EXMC SRAM/NOR flash control register */ -#define EXMC_SNTCFG3 REG32(EXMC + 0x1CU) /*!< EXMC SRAM/NOR flash timing configuration register */ -#define EXMC_SNWTCFG3 REG32(EXMC + 0x11CU) /*!< EXMC SRAM/NOR flash write timing configuration register */ +#define EXMC_SNCTL3 REG32(EXMC + 0x18U) /*!< EXMC SRAM/NOR flash control register for region3 */ +#define EXMC_SNTCFG3 REG32(EXMC + 0x1CU) /*!< EXMC SRAM/NOR flash timing configuration register for region3 */ +#define EXMC_SNWTCFG3 REG32(EXMC + 0x11CU) /*!< EXMC SRAM/NOR flash write timing configuration register for region3 */ /* NAND/PC card */ -#define EXMC_NPCTL1 REG32(EXMC + 0x40U) /*!< EXMC NAND/PC card control register */ -#define EXMC_NPINTEN1 REG32(EXMC + 0x44U) /*!< EXMC NAND/PC card interrupt enable register */ -#define EXMC_NPCTCFG1 REG32(EXMC + 0x48U) /*!< EXMC NAND/PC card common space timing configuration register */ -#define EXMC_NPATCFG1 REG32(EXMC + 0x4CU) /*!< EXMC NAND/PC card attribute space timing configuration register */ -#define EXMC_NECC1 REG32(EXMC + 0x54U) /*!< EXMC NAND ECC register */ +#define EXMC_NPCTL1 REG32(EXMC + 0x60U) /*!< EXMC NAND/PC card control register for bank1 */ +#define EXMC_NPINTEN1 REG32(EXMC + 0x64U) /*!< EXMC NAND/PC card interrupt enable register for bank1 */ +#define EXMC_NPCTCFG1 REG32(EXMC + 0x68U) /*!< EXMC NAND/PC card common space timing configuration register for bank1 */ +#define EXMC_NPATCFG1 REG32(EXMC + 0x6CU) /*!< EXMC NAND/PC card attribute space timing configuration register for bank1 */ +#define EXMC_NECC1 REG32(EXMC + 0x74U) /*!< EXMC NAND ECC register */ -#define EXMC_NPCTL2 REG32(EXMC + 0x60U) /*!< EXMC NAND/PC card control register */ -#define EXMC_NPINTEN2 REG32(EXMC + 0x64U) /*!< EXMC NAND/PC card interrupt enable register */ -#define EXMC_NPCTCFG2 REG32(EXMC + 0x68U) /*!< EXMC NAND/PC card common space timing configuration register */ -#define EXMC_NPATCFG2 REG32(EXMC + 0x6CU) /*!< EXMC NAND/PC card attribute space timing configuration register */ -#define EXMC_NECC2 REG32(EXMC + 0x74U) /*!< EXMC NAND ECC register */ +#define EXMC_NPCTL2 REG32(EXMC + 0x80U) /*!< EXMC NAND/PC card control register for bank2 */ +#define EXMC_NPINTEN2 REG32(EXMC + 0x84U) /*!< EXMC NAND/PC card interrupt enable register for bank2 */ +#define EXMC_NPCTCFG2 REG32(EXMC + 0x88U) /*!< EXMC NAND/PC card common space timing configuration register for bank2 */ +#define EXMC_NPATCFG2 REG32(EXMC + 0x8CU) /*!< EXMC NAND/PC card attribute space timing configuration register for bank2 */ +#define EXMC_NECC2 REG32(EXMC + 0x94U) /*!< EXMC NAND ECC register */ -#define EXMC_NPCTL3 REG32(EXMC + 0x80U) /*!< EXMC NAND/PC card control register */ -#define EXMC_NPINTEN3 REG32(EXMC + 0x84U) /*!< EXMC NAND/PC card interrupt enable register */ -#define EXMC_NPCTCFG3 REG32(EXMC + 0x88U) /*!< EXMC NAND/PC card common space timing configuration register */ -#define EXMC_NPATCFG3 REG32(EXMC + 0x8CU) /*!< EXMC NAND/PC card attribute space timing configuration register */ -#define EXMC_PIOTCFG3 REG32(EXMC + 0xB0U) /*!< EXMC PC card I/O space timing configuration register */ +#define EXMC_NPCTL3 REG32(EXMC + 0xA0U) /*!< EXMC NAND/PC card control register for bank3 */ +#define EXMC_NPINTEN3 REG32(EXMC + 0xA4U) /*!< EXMC NAND/PC card interrupt enable register for bank3 */ +#define EXMC_NPCTCFG3 REG32(EXMC + 0xA8U) /*!< EXMC NAND/PC card common space timing configuration register for bank3 */ +#define EXMC_NPATCFG3 REG32(EXMC + 0xACU) /*!< EXMC NAND/PC card attribute space timing configuration register for bank3 */ +#define EXMC_PIOTCFG3 REG32(EXMC + 0xB0U) /*!< EXMC PC card I/O space timing configuration register for bank3 */ /* SDRAM */ -#define EXMC_SDCTL0 REG32(EXMC + 0x140U) /*!< EXMC SDRAM control register */ -#define EXMC_SDTCFG0 REG32(EXMC + 0x148U) /*!< EXMC SDRAM timing configuration register register */ +#define EXMC_SDCTL0 REG32(EXMC + 0x140U) /*!< EXMC SDRAM control register for device0 */ +#define EXMC_SDTCFG0 REG32(EXMC + 0x148U) /*!< EXMC SDRAM timing configuration register register for device0 */ -#define EXMC_SDCTL1 REG32(EXMC + 0x144U) /*!< EXMC SDRAM control register */ -#define EXMC_SDTCFG1 REG32(EXMC + 0x14CU) /*!< EXMC SDRAM timing configuration register register */ +#define EXMC_SDCTL1 REG32(EXMC + 0x144U) /*!< EXMC SDRAM control register for device1 */ +#define EXMC_SDTCFG1 REG32(EXMC + 0x14CU) /*!< EXMC SDRAM timing configuration register register for device1 */ -#define EXMC_SDCMD REG32(EXMC + 0x150U) /*!< EXMC SDRAM command register */ -#define EXMC_SDARI REG32(EXMC + 0x154U) /*!< EXMC SDRAM auto-refresh interval register */ -#define EXMC_SDSTAT REG32(EXMC + 0x158U) /*!< EXMC SDRAM status register */ -#define EXMC_SDRSCTL REG32(EXMC + 0x180U) /*!< EXMC SDRAM read sample control register */ +#define EXMC_SDCMD REG32(EXMC + 0x150U) /*!< EXMC SDRAM command register */ +#define EXMC_SDARI REG32(EXMC + 0x154U) /*!< EXMC SDRAM auto-refresh interval register */ +#define EXMC_SDSTAT REG32(EXMC + 0x158U) /*!< EXMC SDRAM status register */ +#define EXMC_SDRSCTL REG32(EXMC + 0x180U) /*!< EXMC SDRAM read sample control register */ /* SQPI PSRAM */ -#define EXMC_SINIT REG32(EXMC + 0x310U) /*!< EXMC SPI initialization register */ -#define EXMC_SRCMD REG32(EXMC + 0x320U) /*!< EXMC SPI read command register */ -#define EXMC_SWCMD REG32(EXMC + 0x330U) /*!< EXMC SPI write command register */ -#define EXMC_SIDL REG32(EXMC + 0x340U) /*!< EXMC SPI ID low register */ -#define EXMC_SIDH REG32(EXMC + 0x350U) /*!< EXMC SPI ID high register */ +#define EXMC_SINIT REG32(EXMC + 0x310U) /*!< EXMC SPI initialization register */ +#define EXMC_SRCMD REG32(EXMC + 0x320U) /*!< EXMC SPI read command register */ +#define EXMC_SWCMD REG32(EXMC + 0x330U) /*!< EXMC SPI write command register */ +#define EXMC_SIDL REG32(EXMC + 0x340U) /*!< EXMC SPI ID low register */ +#define EXMC_SIDH REG32(EXMC + 0x350U) /*!< EXMC SPI ID high register */ /* bits definitions */ /* EXMC_SNCTLx,x=0..3 */ -#define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR bank enable */ -#define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR bank memory address/data multiplexing */ -#define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR bank memory type */ -#define EXMC_SNCTL_NRW BITS(4,5) /*!< NOR bank memory data bus width */ -#define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */ -#define EXMC_SNCTL_SBRSTEN BIT(8) /*!< synchronous burst enable */ -#define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */ -#define EXMC_SNCTL_WRAPEN BIT(10) /*!< wrapped burst mode enable */ -#define EXMC_SNCTL_NRWTCFG BIT(11) /*!< NWAIT signal configuration, only work in synchronous mode */ -#define EXMC_SNCTL_WREN BIT(12) /*!< write enable */ -#define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */ -#define EXMC_SNCTL_EXMODEN BIT(14) /*!< extended mode enable */ -#define EXMC_SNCTL_ASYNCWAIT BIT(15) /*!< asynchronous wait */ -#define EXMC_SNCTL_CPS BITS(16,18) /*!< CRAM page size */ -#define EXMC_SNCTL_SYNCWR BIT(19) /*!< synchronous write */ -#define EXMC_SNCTL_CCK BIT(20) /*!< consecutive clock */ +#define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR bank enable */ +#define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR bank memory address/data multiplexing enable */ +#define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR bank memory type */ +#define EXMC_SNCTL_NRW BITS(4,5) /*!< NOR bank memory data bus width */ +#define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */ +#define EXMC_SNCTL_SBRSTEN BIT(8) /*!< synchronous burst enable */ +#define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */ +#define EXMC_SNCTL_WRAPEN BIT(10) /*!< wrapped burst mode enable */ +#define EXMC_SNCTL_NRWTCFG BIT(11) /*!< NWAIT signal configuration, only work in synchronous mode */ +#define EXMC_SNCTL_WREN BIT(12) /*!< write enable */ +#define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */ +#define EXMC_SNCTL_EXMODEN BIT(14) /*!< extended mode enable */ +#define EXMC_SNCTL_ASYNCWAIT BIT(15) /*!< asynchronous wait enable */ +#define EXMC_SNCTL_CPS BITS(16,18) /*!< CRAM page size */ +#define EXMC_SNCTL_SYNCWR BIT(19) /*!< synchronous write config */ +#define EXMC_SNCTL_CCK BIT(20) /*!< consecutive clock config */ /* EXMC_SNTCFGx,x=0..3 */ -#define EXMC_SNTCFG_ASET BITS(0,3) /*!< address setup time */ -#define EXMC_SNTCFG_AHLD BITS(4,7) /*!< address hold time */ -#define EXMC_SNTCFG_DSET BITS(8,15) /*!< data setup time */ -#define EXMC_SNTCFG_BUSLAT BITS(16,19) /*!< bus latency */ -#define EXMC_SNTCFG_CKDIV BITS(20,23) /*!< synchronous clock divide ratio */ -#define EXMC_SNTCFG_DLAT BITS(24,27) /*!< data latency for NOR flash */ -#define EXMC_SNTCFG_ASYNCMOD BITS(28,29) /*!< asynchronous access mode */ +#define EXMC_SNTCFG_ASET BITS(0,3) /*!< asynchronous address setup time */ +#define EXMC_SNTCFG_AHLD BITS(4,7) /*!< asynchronous address hold time */ +#define EXMC_SNTCFG_DSET BITS(8,15) /*!< asynchronous data setup time */ +#define EXMC_SNTCFG_BUSLAT BITS(16,19) /*!< bus latency */ +#define EXMC_SNTCFG_CKDIV BITS(20,23) /*!< synchronous clock divide ratio */ +#define EXMC_SNTCFG_DLAT BITS(24,27) /*!< synchronous data latency for NOR flash */ +#define EXMC_SNTCFG_ASYNCMOD BITS(28,29) /*!< asynchronous access mode */ /* EXMC_SNWTCFGx,x=0..3 */ -#define EXMC_SNWTCFG_WASET BITS(0,3) /*!< address setup time */ -#define EXMC_SNWTCFG_WAHLD BITS(4,7) /*!< address hold time */ -#define EXMC_SNWTCFG_WDSET BITS(8,15) /*!< data setup time */ -#define EXMC_SNWTCFG_WBUSLAT BITS(16,19) /*!< bus latency */ -#define EXMC_SNWTCFG_WASYNCMOD BITS(28,29) /*!< asynchronous access mode */ +#define EXMC_SNWTCFG_WASET BITS(0,3) /*!< asynchronous address setup time */ +#define EXMC_SNWTCFG_WAHLD BITS(4,7) /*!< asynchronous address hold time */ +#define EXMC_SNWTCFG_WDSET BITS(8,15) /*!< asynchronous data setup time */ +#define EXMC_SNWTCFG_WBUSLAT BITS(16,19) /*!< bus latency */ +#define EXMC_SNWTCFG_WASYNCMOD BITS(28,29) /*!< asynchronous access mode */ /* EXMC_NPCTLx,x=1..3 */ -#define EXMC_NPCTL_NDWTEN BIT(1) /*!< wait feature enable */ -#define EXMC_NPCTL_NDBKEN BIT(2) /*!< NAND bank enable */ -#define EXMC_NPCTL_NDTP BIT(3) /*!< NAND bank memory type */ -#define EXMC_NPCTL_NDW BITS(4,5) /*!< NAND bank memory data bus width */ -#define EXMC_NPCTL_ECCEN BIT(6) /*!< ECC enable */ -#define EXMC_NPCTL_CTR BITS(9,12) /*!< CLE to RE delay */ -#define EXMC_NPCTL_ATR BITS(13,16) /*!< ALE to RE delay */ -#define EXMC_NPCTL_ECCSZ BITS(17,19) /*!< ECC size */ +#define EXMC_NPCTL_NDWTEN BIT(1) /*!< wait feature enable */ +#define EXMC_NPCTL_NDBKEN BIT(2) /*!< NAND bank enable */ +#define EXMC_NPCTL_NDTP BIT(3) /*!< NAND bank memory type */ +#define EXMC_NPCTL_NDW BITS(4,5) /*!< NAND bank memory data bus width */ +#define EXMC_NPCTL_ECCEN BIT(6) /*!< ECC enable */ +#define EXMC_NPCTL_CTR BITS(9,12) /*!< CLE to RE delay */ +#define EXMC_NPCTL_ATR BITS(13,16) /*!< ALE to RE delay */ +#define EXMC_NPCTL_ECCSZ BITS(17,19) /*!< ECC size */ /* EXMC_NPINTENx,x=1..3 */ -#define EXMC_NPINTEN_INTRS BIT(0) /*!< interrupt rising edge status */ -#define EXMC_NPINTEN_INTHS BIT(1) /*!< interrupt high-level status */ -#define EXMC_NPINTEN_INTFS BIT(2) /*!< interrupt falling edge status */ -#define EXMC_NPINTEN_INTREN BIT(3) /*!< interrupt rising edge detection enable */ -#define EXMC_NPINTEN_INTHEN BIT(4) /*!< interrupt high-level detection enable */ -#define EXMC_NPINTEN_INTFEN BIT(5) /*!< interrupt falling edge detection enable */ -#define EXMC_NPINTEN_INTEPT BIT(6) /*!< FIFO empty flag */ +#define EXMC_NPINTEN_INTRS BIT(0) /*!< interrupt rising edge status */ +#define EXMC_NPINTEN_INTHS BIT(1) /*!< interrupt high-level status */ +#define EXMC_NPINTEN_INTFS BIT(2) /*!< interrupt falling edge status */ +#define EXMC_NPINTEN_INTREN BIT(3) /*!< interrupt rising edge detection enable */ +#define EXMC_NPINTEN_INTHEN BIT(4) /*!< interrupt high-level detection enable */ +#define EXMC_NPINTEN_INTFEN BIT(5) /*!< interrupt falling edge detection enable */ +#define EXMC_NPINTEN_FFEPT BIT(6) /*!< FIFO empty flag */ /* EXMC_NPCTCFGx,x=1..3 */ -#define EXMC_NPCTCFG_COMSET BITS(0,7) /*!< common memory data bus HiZ time */ -#define EXMC_NPCTCFG_COMWAIT BITS(8,15) /*!< common memory hold time */ -#define EXMC_NPCTCFG_COMHLD BITS(16,23) /*!< common memory wait time */ -#define EXMC_NPCTCFG_COMHIZ BITS(24,31) /*!< common memory setup time */ +#define EXMC_NPCTCFG_COMSET BITS(0,7) /*!< common memory setup time */ +#define EXMC_NPCTCFG_COMWAIT BITS(8,15) /*!< common memory wait time */ +#define EXMC_NPCTCFG_COMHLD BITS(16,23) /*!< common memory hold time */ +#define EXMC_NPCTCFG_COMHIZ BITS(24,31) /*!< common memory data bus HiZ time */ /* EXMC_NPATCFGx,x=1..3 */ -#define EXMC_NPATCFG_ATTSET BITS(0,7) /*!< attribute memory data bus HiZ time */ -#define EXMC_NPATCFG_ATTWAIT BITS(8,15) /*!< attribute memory hold time */ -#define EXMC_NPATCFG_ATTHLD BITS(16,23) /*!< attribute memory wait time */ -#define EXMC_NPATCFG_ATTHIZ BITS(24,31) /*!< attribute memory setup time */ +#define EXMC_NPATCFG_ATTSET BITS(0,7) /*!< attribute memory setup time */ +#define EXMC_NPATCFG_ATTWAIT BITS(8,15) /*!< attribute memory wait time */ +#define EXMC_NPATCFG_ATTHLD BITS(16,23) /*!< attribute memory hold time */ +#define EXMC_NPATCFG_ATTHIZ BITS(24,31) /*!< attribute memory data bus HiZ time */ /* EXMC_PIOTCFG3 */ -#define EXMC_PIOTCFG3_IOSET BITS(0,7) /*!< IO space data bus HiZ time */ -#define EXMC_PIOTCFG3_IOWAIT BITS(8,15) /*!< IO space hold time */ -#define EXMC_PIOTCFG3_IOHLD BITS(16,23) /*!< IO space wait time */ -#define EXMC_PIOTCFG3_IOHIZ BITS(24,31) /*!< IO space setup time */ +#define EXMC_PIOTCFG3_IOSET BITS(0,7) /*!< IO space setup time */ +#define EXMC_PIOTCFG3_IOWAIT BITS(8,15) /*!< IO space wait time */ +#define EXMC_PIOTCFG3_IOHLD BITS(16,23) /*!< IO space hold time */ +#define EXMC_PIOTCFG3_IOHIZ BITS(24,31) /*!< IO space data bus HiZ time */ /* EXMC_NECCx,x=1..2 */ -#define EXMC_NECC_ECC BITS(0,31) /*!< ECC result */ +#define EXMC_NECC_ECC BITS(0,31) /*!< ECC result */ /* EXMC_SDCTLx,x=0..1 */ -#define EXMC_SDCTL_CAW BITS(0,1) /*!< column address bit width */ -#define EXMC_SDCTL_RAW BITS(2,3) /*!< row address bit width */ -#define EXMC_SDCTL_SDW BITS(4,5) /*!< SDRAM data bus width */ -#define EXMC_SDCTL_NBK BIT(6) /*!< number of banks */ -#define EXMC_SDCTL_CL BIT(7,8) /*!< CAS Latency */ -#define EXMC_SDCTL_WPEN BIT(9) /*!< write protection enable */ -#define EXMC_SDCTL_SDCLK BITS(10,11) /*!< SDRAM clock configuration */ -#define EXMC_SDCTL_BRSTRD BIT(12) /*!< burst read */ -#define EXMC_SDCTL_PIPED BITS(13,14) /*!< pipeline delay */ +#define EXMC_SDCTL_CAW BITS(0,1) /*!< column address bit width */ +#define EXMC_SDCTL_RAW BITS(2,3) /*!< row address bit width */ +#define EXMC_SDCTL_SDW BITS(4,5) /*!< SDRAM data bus width */ +#define EXMC_SDCTL_NBK BIT(6) /*!< number of banks */ +#define EXMC_SDCTL_CL BIT(7,8) /*!< CAS Latency */ +#define EXMC_SDCTL_WPEN BIT(9) /*!< write protection enable */ +#define EXMC_SDCTL_SDCLK BITS(10,11) /*!< SDRAM clock configuration */ +#define EXMC_SDCTL_BRSTRD BIT(12) /*!< burst read enable */ +#define EXMC_SDCTL_PIPED BITS(13,14) /*!< pipeline delay */ /* EXMC_SDTCFGx,x=0..1 */ -#define EXMC_SDTCFG_LMRD BITS(0,3) /*!< load mode register delay */ -#define EXMC_SDTCFG_XSRD BITS(4,7) /*!< exit self-refresh delay */ -#define EXMC_SDTCFG_RASD BITS(8,11) /*!< row address select delay */ -#define EXMC_SDTCFG_ARFD BITS(12,15) /*!< auto refresh delay */ -#define EXMC_SDTCFG_WRD BITS(16,19) /*!< write recovery delay */ -#define EXMC_SDTCFG_RPD BITS(20,23) /*!< row precharge delay */ -#define EXMC_SDTCFG_RCD BITS(24,27) /*!< row to column delay */ +#define EXMC_SDTCFG_LMRD BITS(0,3) /*!< load mode register delay */ +#define EXMC_SDTCFG_XSRD BITS(4,7) /*!< exit self-refresh delay */ +#define EXMC_SDTCFG_RASD BITS(8,11) /*!< row address select delay */ +#define EXMC_SDTCFG_ARFD BITS(12,15) /*!< auto refresh delay */ +#define EXMC_SDTCFG_WRD BITS(16,19) /*!< write recovery delay */ +#define EXMC_SDTCFG_RPD BITS(20,23) /*!< row precharge delay */ +#define EXMC_SDTCFG_RCD BITS(24,27) /*!< row to column delay */ /* EXMC_SDCMD */ -#define EXMC_SDCMD_CMD BITS(0,2) /*!< command */ -#define EXMC_SDCMD_DS1 BIT(3) /*!< device select 1 */ -#define EXMC_SDCMD_DS0 BIT(4) /*!< device select 0 */ -#define EXMC_SDCMD_NARF BITS(5,8) /*!< number of successive auto-refresh */ -#define EXMC_SDCMD_MRC BITS(9,21) /*!< mode register content */ +#define EXMC_SDCMD_CMD BITS(0,2) /*!< command */ +#define EXMC_SDCMD_DS1 BIT(3) /*!< select device1 */ +#define EXMC_SDCMD_DS0 BIT(4) /*!< select device0 */ +#define EXMC_SDCMD_NARF BITS(5,8) /*!< number of successive auto-refresh */ +#define EXMC_SDCMD_MRC BITS(9,21) /*!< mode register content */ /* EXMC_SDARI */ -#define EXMC_SDARI_REC BIT(0) /*!< refresh error flag clear */ -#define EXMC_SDARI_ARINTV BITS(1,13) /*!< auto-refresh interval */ -#define EXMC_SDARI_REIE BIT(14) /*!< interrupt refresh error enable */ +#define EXMC_SDARI_REC BIT(0) /*!< refresh error flag clear */ +#define EXMC_SDARI_ARINTV BITS(1,13) /*!< auto-refresh interval */ +#define EXMC_SDARI_REIE BIT(14) /*!< interrupt refresh error enable */ /* EXMC_SDSTAT */ -#define EXMC_SDSDAT_REIF BIT(0) /*!< refresh error interrupt flag */ -#define EXMC_SDSDAT_STA0 BITS(1,2) /*!< device 0 status */ -#define EXMC_SDSDAT_STA1 BITS(3,4) /*!< device 1 status */ -#define EXMC_SDSDAT_NRDY BIT(5) /*!< not ready status */ +#define EXMC_SDSDAT_REIF BIT(0) /*!< refresh error interrupt flag */ +#define EXMC_SDSDAT_STA0 BITS(1,2) /*!< device0 status */ +#define EXMC_SDSDAT_STA1 BITS(3,4) /*!< device1 status */ +#define EXMC_SDSDAT_NRDY BIT(5) /*!< not ready status */ /* EXMC_SDRSCTL */ -#define EXMC_SDRSCTL_RSEN BIT(0) /*!< read sample enable */ -#define EXMC_SDRSCTL_SSCR BIT(1) /*!< select sample cycle of read data */ -#define EXMC_SDRSCTL_SDSC BITS(4,7) /*!< select the delayed sample clock of read data */ +#define EXMC_SDRSCTL_RSEN BIT(0) /*!< read sample enable */ +#define EXMC_SDRSCTL_SSCR BIT(1) /*!< select sample cycle of read data */ +#define EXMC_SDRSCTL_SDSC BITS(4,7) /*!< select the delayed sample clock of read data */ /* EXMC_SINIT */ -#define EXMC_SINIT_CMDBIT BITS(16,17) /*!< bit number of SPI PSRAM command phase */ -#define EXMC_SINIT_ARDBIT BITS(24,28) /*!< bit number of SPI PSRAM address phase */ -#define EXMC_SINIT_IDL BITS(29,30) /*!< SPI PSRAM ID length */ -#define EXMC_SINIT_POL BIT(31) /*!< read data sample polarity */ +#define EXMC_SINIT_CMDBIT BITS(16,17) /*!< bit number of SPI PSRAM command phase */ +#define EXMC_SINIT_ARDBIT BITS(24,28) /*!< bit number of SPI PSRAM address phase */ +#define EXMC_SINIT_IDL BITS(29,30) /*!< SPI PSRAM ID length */ +#define EXMC_SINIT_POL BIT(31) /*!< read data sample polarity */ /* EXMC_SRCMD */ -#define EXMC_SRCMD_RCMD BITS(0,15) /*!< SPI read command for AHB read transfer */ -#define EXMC_SRCMD_RWAITCYCLE BITS(16,19) /*!< SPI read wait cycle number after address phase */ -#define EXMC_SRCMD_RMODE BITS(20,21) /*!< SPI PSRAM read command mode */ -#define EXMC_SRCMD_RDID BIT(31) /*!< send SPI read ID command */ +#define EXMC_SRCMD_RCMD BITS(0,15) /*!< SPI read command for AHB read transfer */ +#define EXMC_SRCMD_RWAITCYCLE BITS(16,19) /*!< SPI read wait cycle number after address phase */ +#define EXMC_SRCMD_RMODE BITS(20,21) /*!< SPI PSRAM read command mode */ +#define EXMC_SRCMD_RDID BIT(31) /*!< send SPI read ID command */ /* EXMC_SWCMD */ -#define EXMC_SWCMD_WCMD BITS(0,15) /*!< send SPI special command */ -#define EXMC_SWCMD_WWAITCYCLE BITS(16,19) /*!< SPI PSRAM write command mode */ -#define EXMC_SWCMD_WMODE BITS(20,21) /*!< SPI write wait cycle number after address phase */ -#define EXMC_SWCMD_SC BIT(31) /*!< SPI write command for AHB write transfer */ +#define EXMC_SWCMD_WCMD BITS(0,15) /*!< SPI write command for AHB write transfer */ +#define EXMC_SWCMD_WWAITCYCLE BITS(16,19) /*!< SPI write wait cycle number after address phase */ +#define EXMC_SWCMD_WMODE BITS(20,21) /*!< SPI PSRAM write command mode */ +#define EXMC_SWCMD_SC BIT(31) /*!< send SPI special command */ /* EXMC_SIDL */ -#define EXMC_SIDL_SIDL BITS(0,31) /*!< ID low data saved for SPI read ID command */ +#define EXMC_SIDL_SIDL BITS(0,31) /*!< ID low data saved for SPI read ID command */ /* EXMC_SIDH */ -#define EXMC_SIDL_SIDH BITS(0,31) /*!< ID high Data saved for SPI read ID command */ +#define EXMC_SIDL_SIDH BITS(0,31) /*!< ID high Data saved for SPI read ID command */ /* constants definitions */ -/* EXMC NOR/SRAM timing initialize struct */ +/* EXMC NOR/SRAM timing initialize structure */ typedef struct { uint32_t asyn_access_mode; /*!< asynchronous access mode */ uint32_t syn_data_latency; /*!< configure the data latency */ uint32_t syn_clk_division; /*!< configure the clock divide ratio */ uint32_t bus_latency; /*!< configure the bus latency */ - uint32_t asyn_data_setuptime; /*!< configure the data setup time,asynchronous access mode valid */ - uint32_t asyn_address_holdtime; /*!< configure the address hold time,asynchronous access mode valid */ - uint32_t asyn_address_setuptime; /*!< configure the data setup time,asynchronous access mode valid */ + uint32_t asyn_data_setuptime; /*!< configure the data setup time, asynchronous access mode valid */ + uint32_t asyn_address_holdtime; /*!< configure the address hold time, asynchronous access mode valid */ + uint32_t asyn_address_setuptime; /*!< configure the address setup time, asynchronous access mode valid */ }exmc_norsram_timing_parameter_struct; -/* EXMC NOR/SRAM initialize struct */ +/* EXMC NOR/SRAM initialize structure */ typedef struct { uint32_t norsram_region; /*!< select the region of EXMC NOR/SRAM bank */ @@ -248,7 +273,7 @@ typedef struct uint32_t databus_width; /*!< specifies the databus width of external memory */ uint32_t memory_type; /*!< specifies the type of external memory */ uint32_t address_data_mux; /*!< specifies whether the data bus and address bus are multiplexed */ - exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for read and write if the extendedmode is not used or the timing + exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for read and write if the extendedmode is not used or the timing parameters for read if the extendedmode is used. */ exmc_norsram_timing_parameter_struct* write_timing; /*!< timing parameters for write when the extendedmode is used. */ }exmc_norsram_parameter_struct; @@ -265,15 +290,15 @@ typedef struct /* EXMC NAND initialize struct */ typedef struct { - uint32_t nand_bank; /*!< select the bank of NAND */ + uint32_t nand_bank; /*!< select the bank of NAND */ uint32_t ecc_size; /*!< the page size for the ECC calculation */ uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */ uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */ uint32_t ecc_logic; /*!< enable or disable the ECC calculation logic */ uint32_t databus_width; /*!< the NAND flash databus width */ - uint32_t wait_feature; /*!< enables or disables the wait feature */ - exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for NAND flash Common Space */ - exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash Attribute Space */ + uint32_t wait_feature; /*!< enable or disable the wait feature */ + exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for NAND flash common space */ + exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */ }exmc_nand_parameter_struct; /* EXMC PC card initialize struct */ @@ -281,11 +306,11 @@ typedef struct { uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */ uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */ - uint32_t wait_feature; /*!< enables or disables the Wait feature */ - exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for NAND flash Common Space */ - exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash Attribute Space */ - exmc_nand_pccard_timing_parameter_struct* io_space_timing; /*!< the timing parameters for NAND flash IO Space */ -}exmc_pccard_parameter_struct;; + uint32_t wait_feature; /*!< enable or disable the wait feature */ + exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for PC card common space */ + exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for PC card attribute space */ + exmc_nand_pccard_timing_parameter_struct* io_space_timing; /*!< the timing parameters for PC card IO space */ +}exmc_pccard_parameter_struct; /* EXMC SDRAM timing initialize struct */ typedef struct @@ -293,7 +318,7 @@ typedef struct uint32_t row_to_column_delay; /*!< configure the row to column delay */ uint32_t row_precharge_delay; /*!< configure the row precharge delay */ uint32_t write_recovery_delay; /*!< configure the write recovery delay */ - uint32_t auto_refresh_delay; /*!< configure the auto refresh delay */ + uint32_t auto_refresh_delay; /*!< configure the auto refresh delay */ uint32_t row_address_select_delay; /*!< configure the row address select delay */ uint32_t exit_selfrefresh_delay; /*!< configure the exit self-refresh delay */ uint32_t load_mode_register_delay; /*!< configure the load mode register delay */ @@ -308,7 +333,7 @@ typedef struct uint32_t sdclock_config; /*!< the SDCLK memory clock for both SDRAM banks */ uint32_t write_protection; /*!< enable or disable SDRAM bank write protection function */ uint32_t cas_latency; /*!< configure the SDRAM CAS latency */ - uint32_t internal_bank_number; /*!< the number internal banks */ + uint32_t internal_bank_number; /*!< the number of internal bank */ uint32_t data_width; /*!< the databus width of SDRAM memory */ uint32_t row_address_width; /*!< the bit width of a row address */ uint32_t column_address_width; /*!< the bit width of a column address */ @@ -333,400 +358,414 @@ typedef struct{ }exmc_sqpipsram_parameter_struct; /* EXMC_register address */ -#define EXMC_SNCTL(bank) REG32(EXMC + 0x08U*((uint32_t)(bank))) /*!< EXMC SRAM/NOR flash control register */ -#define EXMC_SNTCFG(bank) REG32(EXMC + 0x04U + 0x08U*(bank)) /*!< EXMC SRAM/NOR flash timing configuration register */ -#define EXMC_SNWTCFG(bank) REG32(EXMC + 0x104U + 0x08U*(bank)) /*!< EXMC SRAM/NOR flash write timing configuration register */ +#define EXMC_SNCTL(region) REG32(EXMC + 0x08U*((uint32_t)(region))) /*!< EXMC SRAM/NOR flash control registers, region = 0,1,2,3 */ +#define EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U*((uint32_t)(region))) /*!< EXMC SRAM/NOR flash timing configuration registers, region = 0,1,2,3 */ +#define EXMC_SNWTCFG(region) REG32(EXMC + 0x104U + 0x08U*((uint32_t)(region))) /*!< EXMC SRAM/NOR flash write timing configuration registers, region = 0,1,2,3 */ -#define EXMC_NPCTL(bank) REG32(EXMC + 0x40U + 0x20U*(bank)) /*!< EXMC NAND/PC card control register */ -#define EXMC_NPINTEN(bank) REG32(EXMC + 0x44U + 0x20U*(bank)) /*!< EXMC NAND/PC card interrupt enable register */ -#define EXMC_NPCTCFG(bank) REG32(EXMC + 0x48U + 0x20U*(bank)) /*!< EXMC NAND/PC card common space timing configuration register */ -#define EXMC_NPATCFG(bank) REG32(EXMC + 0x4CU + 0x20U*(bank)) /*!< EXMC NAND/PC card attribute space timing configuration register */ -#define EXMC_NECC(bank) REG32(EXMC + 0x54U + 0x20U*(bank)) /*!< EXMC NAND ECC register */ +#define EXMC_NPCTL(bank) REG32(EXMC + 0x40U + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND/PC card control registers, bank = 1,2,3 */ +#define EXMC_NPINTEN(bank) REG32(EXMC + 0x44U + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND/PC card interrupt enable registers, bank = 1,2,3 */ +#define EXMC_NPCTCFG(bank) REG32(EXMC + 0x48U + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND/PC card common space timing configuration registers, bank = 1,2,3 */ +#define EXMC_NPATCFG(bank) REG32(EXMC + 0x4CU + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND/PC card attribute space timing configuration registers, bank = 1,2,3 */ +#define EXMC_NECC(bank) REG32(EXMC + 0x54U + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND ECC registers, bank = 1,2 */ -#define EXMC_SDCTL(bank) REG32(EXMC + 0x140U + 0x4U*((bank) - 0x4U)) /*!< EXMC SDRAM control register */ -#define EXMC_SDTCFG(bank) REG32(EXMC + 0x148U + 0x4U*((bank) - 0x4U)) /*!< EXMC SDRAM timing configuration register */ +#define EXMC_SDCTL(device) REG32(EXMC + 0x140U + 0x4U*(((uint32_t)(device)) - 0x4U)) /*!< EXMC SDRAM control registers,device = 0,1 */ +#define EXMC_SDTCFG(device) REG32(EXMC + 0x148U + 0x4U*(((uint32_t)(device)) - 0x4U)) /*!< EXMC SDRAM timing configuration registers,device = 0,1 */ /* CRAM page size */ -#define SNCTL_CPS(regval) (BITS(16,18) & ((uint32_t)(regval) << 16)) -#define EXMC_CRAM_AUTO_SPLIT SNCTL_CPS(0) /*!< automatic burst split on page boundary crossing */ -#define EXMC_CRAM_PAGE_SIZE_128_BYTES SNCTL_CPS(1) /*!< page size is 128 bytes */ -#define EXMC_CRAM_PAGE_SIZE_256_BYTES SNCTL_CPS(2) /*!< page size is 256 bytes */ -#define EXMC_CRAM_PAGE_SIZE_512_BYTES SNCTL_CPS(3) /*!< page size is 512 bytes */ -#define EXMC_CRAM_PAGE_SIZE_1024_BYTES SNCTL_CPS(4) /*!< page size is 1024 bytes */ +#define SNCTL_CPS(regval) (BITS(16,18) & ((uint32_t)(regval) << 16)) +#define EXMC_CRAM_AUTO_SPLIT SNCTL_CPS(0) /*!< automatic burst split on page boundary crossing */ +#define EXMC_CRAM_PAGE_SIZE_128_BYTES SNCTL_CPS(1) /*!< page size is 128 bytes */ +#define EXMC_CRAM_PAGE_SIZE_256_BYTES SNCTL_CPS(2) /*!< page size is 256 bytes */ +#define EXMC_CRAM_PAGE_SIZE_512_BYTES SNCTL_CPS(3) /*!< page size is 512 bytes */ +#define EXMC_CRAM_PAGE_SIZE_1024_BYTES SNCTL_CPS(4) /*!< page size is 1024 bytes */ /* NOR bank memory data bus width */ -#define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) -#define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width 8 bits */ -#define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width 16 bits */ +#define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) +#define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width is 8 bits */ +#define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width is 16 bits */ /* NOR bank memory type */ -#define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) -#define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */ -#define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */ -#define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */ +#define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) +#define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */ +#define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */ +#define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */ /* asynchronous access mode */ -#define SNTCFG_ASYNCMOD(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) -#define EXMC_ACCESS_MODE_A SNTCFG_ASYNCMOD(0) /*!< mode A access */ -#define EXMC_ACCESS_MODE_B SNTCFG_ASYNCMOD(1) /*!< mode B access */ -#define EXMC_ACCESS_MODE_C SNTCFG_ASYNCMOD(2) /*!< mode C access */ -#define EXMC_ACCESS_MODE_D SNTCFG_ASYNCMOD(3) /*!< mode D access */ +#define SNTCFG_ASYNCMOD(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) +#define EXMC_ACCESS_MODE_A SNTCFG_ASYNCMOD(0) /*!< mode A access */ +#define EXMC_ACCESS_MODE_B SNTCFG_ASYNCMOD(1) /*!< mode B access */ +#define EXMC_ACCESS_MODE_C SNTCFG_ASYNCMOD(2) /*!< mode C access */ +#define EXMC_ACCESS_MODE_D SNTCFG_ASYNCMOD(3) /*!< mode D access */ /* data latency for NOR flash */ -#define SNTCFG_DLAT(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) -#define EXMC_DATALAT_2_CLK SNTCFG_DLAT(0) /*!< data latency 2 EXMC_CLK */ -#define EXMC_DATALAT_3_CLK SNTCFG_DLAT(1) /*!< data latency 3 EXMC_CLK */ -#define EXMC_DATALAT_4_CLK SNTCFG_DLAT(2) /*!< data latency 4 EXMC_CLK */ -#define EXMC_DATALAT_5_CLK SNTCFG_DLAT(3) /*!< data latency 5 EXMC_CLK */ -#define EXMC_DATALAT_6_CLK SNTCFG_DLAT(4) /*!< data latency 6 EXMC_CLK */ -#define EXMC_DATALAT_7_CLK SNTCFG_DLAT(5) /*!< data latency 7 EXMC_CLK */ -#define EXMC_DATALAT_8_CLK SNTCFG_DLAT(6) /*!< data latency 8 EXMC_CLK */ -#define EXMC_DATALAT_9_CLK SNTCFG_DLAT(7) /*!< data latency 9 EXMC_CLK */ -#define EXMC_DATALAT_10_CLK SNTCFG_DLAT(8) /*!< data latency 10 EXMC_CLK */ -#define EXMC_DATALAT_11_CLK SNTCFG_DLAT(9) /*!< data latency 11 EXMC_CLK */ -#define EXMC_DATALAT_12_CLK SNTCFG_DLAT(10) /*!< data latency 12 EXMC_CLK */ -#define EXMC_DATALAT_13_CLK SNTCFG_DLAT(11) /*!< data latency 13 EXMC_CLK */ -#define EXMC_DATALAT_14_CLK SNTCFG_DLAT(12) /*!< data latency 14 EXMC_CLK */ -#define EXMC_DATALAT_15_CLK SNTCFG_DLAT(13) /*!< data latency 15 EXMC_CLK */ -#define EXMC_DATALAT_16_CLK SNTCFG_DLAT(14) /*!< data latency 16 EXMC_CLK */ -#define EXMC_DATALAT_17_CLK SNTCFG_DLAT(15) /*!< data latency 17 EXMC_CLK */ +#define SNTCFG_DLAT(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) +#define EXMC_DATALAT_2_CLK SNTCFG_DLAT(0) /*!< data latency of first burst access is 2 EXMC_CLK */ +#define EXMC_DATALAT_3_CLK SNTCFG_DLAT(1) /*!< data latency of first burst access is 3 EXMC_CLK */ +#define EXMC_DATALAT_4_CLK SNTCFG_DLAT(2) /*!< data latency of first burst access is 4 EXMC_CLK */ +#define EXMC_DATALAT_5_CLK SNTCFG_DLAT(3) /*!< data latency of first burst access is 5 EXMC_CLK */ +#define EXMC_DATALAT_6_CLK SNTCFG_DLAT(4) /*!< data latency of first burst access is 6 EXMC_CLK */ +#define EXMC_DATALAT_7_CLK SNTCFG_DLAT(5) /*!< data latency of first burst access is 7 EXMC_CLK */ +#define EXMC_DATALAT_8_CLK SNTCFG_DLAT(6) /*!< data latency of first burst access is 8 EXMC_CLK */ +#define EXMC_DATALAT_9_CLK SNTCFG_DLAT(7) /*!< data latency of first burst access is 9 EXMC_CLK */ +#define EXMC_DATALAT_10_CLK SNTCFG_DLAT(8) /*!< data latency of first burst access is 10 EXMC_CLK */ +#define EXMC_DATALAT_11_CLK SNTCFG_DLAT(9) /*!< data latency of first burst access is 11 EXMC_CLK */ +#define EXMC_DATALAT_12_CLK SNTCFG_DLAT(10) /*!< data latency of first burst access is 12 EXMC_CLK */ +#define EXMC_DATALAT_13_CLK SNTCFG_DLAT(11) /*!< data latency of first burst access is 13 EXMC_CLK */ +#define EXMC_DATALAT_14_CLK SNTCFG_DLAT(12) /*!< data latency of first burst access is 14 EXMC_CLK */ +#define EXMC_DATALAT_15_CLK SNTCFG_DLAT(13) /*!< data latency of first burst access is 15 EXMC_CLK */ +#define EXMC_DATALAT_16_CLK SNTCFG_DLAT(14) /*!< data latency of first burst access is 16 EXMC_CLK */ +#define EXMC_DATALAT_17_CLK SNTCFG_DLAT(15) /*!< data latency of first burst access is 17 EXMC_CLK */ /* synchronous clock divide ratio */ -#define SNTCFG_CKDIV(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) -#define EXMC_SYN_CLOCK_RATIO_DISABLE SNTCFG_CKDIV(0) /*!< EXMC_CLK disable */ -#define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1) /*!< EXMC_CLK = 2*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2) /*!< EXMC_CLK = 3*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_4_CLK SNTCFG_CKDIV(3) /*!< EXMC_CLK = 4*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_5_CLK SNTCFG_CKDIV(4) /*!< EXMC_CLK = 5*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_6_CLK SNTCFG_CKDIV(5) /*!< EXMC_CLK = 6*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_7_CLK SNTCFG_CKDIV(6) /*!< EXMC_CLK = 7*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_8_CLK SNTCFG_CKDIV(7) /*!< EXMC_CLK = 8*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_9_CLK SNTCFG_CKDIV(8) /*!< EXMC_CLK = 9*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_10_CLK SNTCFG_CKDIV(9) /*!< EXMC_CLK = 10*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_11_CLK SNTCFG_CKDIV(10) /*!< EXMC_CLK = 11*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_12_CLK SNTCFG_CKDIV(11) /*!< EXMC_CLK = 12*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_13_CLK SNTCFG_CKDIV(12) /*!< EXMC_CLK = 13*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_14_CLK SNTCFG_CKDIV(13) /*!< EXMC_CLK = 14*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_15_CLK SNTCFG_CKDIV(14) /*!< EXMC_CLK = 15*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_16_CLK SNTCFG_CKDIV(15) /*!< EXMC_CLK = 16*HCLK */ +#define SNTCFG_CKDIV(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) +#define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1) /*!< EXMC_CLK = 2*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2) /*!< EXMC_CLK = 3*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_4_CLK SNTCFG_CKDIV(3) /*!< EXMC_CLK = 4*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_5_CLK SNTCFG_CKDIV(4) /*!< EXMC_CLK = 5*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_6_CLK SNTCFG_CKDIV(5) /*!< EXMC_CLK = 6*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_7_CLK SNTCFG_CKDIV(6) /*!< EXMC_CLK = 7*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_8_CLK SNTCFG_CKDIV(7) /*!< EXMC_CLK = 8*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_9_CLK SNTCFG_CKDIV(8) /*!< EXMC_CLK = 9*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_10_CLK SNTCFG_CKDIV(9) /*!< EXMC_CLK = 10*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_11_CLK SNTCFG_CKDIV(10) /*!< EXMC_CLK = 11*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_12_CLK SNTCFG_CKDIV(11) /*!< EXMC_CLK = 12*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_13_CLK SNTCFG_CKDIV(12) /*!< EXMC_CLK = 13*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_14_CLK SNTCFG_CKDIV(13) /*!< EXMC_CLK = 14*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_15_CLK SNTCFG_CKDIV(14) /*!< EXMC_CLK = 15*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_16_CLK SNTCFG_CKDIV(15) /*!< EXMC_CLK = 16*HCLK */ /* ECC size */ -#define NPCTL_ECCSZ(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) -#define EXMC_ECC_SIZE_256BYTES NPCTL_ECCSZ(0) /* 256 bytes */ -#define EXMC_ECC_SIZE_512BYTES NPCTL_ECCSZ(1) /* 512 bytes */ -#define EXMC_ECC_SIZE_1024BYTES NPCTL_ECCSZ(2) /* 1024 bytes */ -#define EXMC_ECC_SIZE_2048BYTES NPCTL_ECCSZ(3) /* 2048 bytes */ -#define EXMC_ECC_SIZE_4096BYTES NPCTL_ECCSZ(4) /* 4096 bytes */ -#define EXMC_ECC_SIZE_8192BYTES NPCTL_ECCSZ(5) /* 8192 bytes */ +#define NPCTL_ECCSZ(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) +#define EXMC_ECC_SIZE_256BYTES NPCTL_ECCSZ(0) /* ECC size is 256 bytes */ +#define EXMC_ECC_SIZE_512BYTES NPCTL_ECCSZ(1) /* ECC size is 512 bytes */ +#define EXMC_ECC_SIZE_1024BYTES NPCTL_ECCSZ(2) /* ECC size is 1024 bytes */ +#define EXMC_ECC_SIZE_2048BYTES NPCTL_ECCSZ(3) /* ECC size is 2048 bytes */ +#define EXMC_ECC_SIZE_4096BYTES NPCTL_ECCSZ(4) /* ECC size is 4096 bytes */ +#define EXMC_ECC_SIZE_8192BYTES NPCTL_ECCSZ(5) /* ECC size is 8192 bytes */ /* ALE to RE delay */ -#define NPCTL_ATR(regval) (BITS(13,16) & ((uint32_t)(regval) << 13)) -#define EXMC_ALE_RE_DELAY_1_HCLK NPCTL_ATR(0) /* ALE to RE delay = 1*HCLK */ -#define EXMC_ALE_RE_DELAY_2_HCLK NPCTL_ATR(1) /* ALE to RE delay = 2*HCLK */ -#define EXMC_ALE_RE_DELAY_3_HCLK NPCTL_ATR(2) /* ALE to RE delay = 3*HCLK */ -#define EXMC_ALE_RE_DELAY_4_HCLK NPCTL_ATR(3) /* ALE to RE delay = 4*HCLK */ -#define EXMC_ALE_RE_DELAY_5_HCLK NPCTL_ATR(4) /* ALE to RE delay = 5*HCLK */ -#define EXMC_ALE_RE_DELAY_6_HCLK NPCTL_ATR(5) /* ALE to RE delay = 6*HCLK */ -#define EXMC_ALE_RE_DELAY_7_HCLK NPCTL_ATR(6) /* ALE to RE delay = 7*HCLK */ -#define EXMC_ALE_RE_DELAY_8_HCLK NPCTL_ATR(7) /* ALE to RE delay = 8*HCLK */ -#define EXMC_ALE_RE_DELAY_9_HCLK NPCTL_ATR(8) /* ALE to RE delay = 9*HCLK */ -#define EXMC_ALE_RE_DELAY_10_HCLK NPCTL_ATR(9) /* ALE to RE delay = 10*HCLK */ -#define EXMC_ALE_RE_DELAY_11_HCLK NPCTL_ATR(10) /* ALE to RE delay = 11*HCLK */ -#define EXMC_ALE_RE_DELAY_12_HCLK NPCTL_ATR(11) /* ALE to RE delay = 12*HCLK */ -#define EXMC_ALE_RE_DELAY_13_HCLK NPCTL_ATR(12) /* ALE to RE delay = 13*HCLK */ -#define EXMC_ALE_RE_DELAY_14_HCLK NPCTL_ATR(13) /* ALE to RE delay = 14*HCLK */ -#define EXMC_ALE_RE_DELAY_15_HCLK NPCTL_ATR(14) /* ALE to RE delay = 15*HCLK */ -#define EXMC_ALE_RE_DELAY_16_HCLK NPCTL_ATR(15) /* ALE to RE delay = 16*HCLK */ +#define NPCTL_ATR(regval) (BITS(13,16) & ((uint32_t)(regval) << 13)) +#define EXMC_ALE_RE_DELAY_1_HCLK NPCTL_ATR(0) /* ALE to RE delay = 1*HCLK */ +#define EXMC_ALE_RE_DELAY_2_HCLK NPCTL_ATR(1) /* ALE to RE delay = 2*HCLK */ +#define EXMC_ALE_RE_DELAY_3_HCLK NPCTL_ATR(2) /* ALE to RE delay = 3*HCLK */ +#define EXMC_ALE_RE_DELAY_4_HCLK NPCTL_ATR(3) /* ALE to RE delay = 4*HCLK */ +#define EXMC_ALE_RE_DELAY_5_HCLK NPCTL_ATR(4) /* ALE to RE delay = 5*HCLK */ +#define EXMC_ALE_RE_DELAY_6_HCLK NPCTL_ATR(5) /* ALE to RE delay = 6*HCLK */ +#define EXMC_ALE_RE_DELAY_7_HCLK NPCTL_ATR(6) /* ALE to RE delay = 7*HCLK */ +#define EXMC_ALE_RE_DELAY_8_HCLK NPCTL_ATR(7) /* ALE to RE delay = 8*HCLK */ +#define EXMC_ALE_RE_DELAY_9_HCLK NPCTL_ATR(8) /* ALE to RE delay = 9*HCLK */ +#define EXMC_ALE_RE_DELAY_10_HCLK NPCTL_ATR(9) /* ALE to RE delay = 10*HCLK */ +#define EXMC_ALE_RE_DELAY_11_HCLK NPCTL_ATR(10) /* ALE to RE delay = 11*HCLK */ +#define EXMC_ALE_RE_DELAY_12_HCLK NPCTL_ATR(11) /* ALE to RE delay = 12*HCLK */ +#define EXMC_ALE_RE_DELAY_13_HCLK NPCTL_ATR(12) /* ALE to RE delay = 13*HCLK */ +#define EXMC_ALE_RE_DELAY_14_HCLK NPCTL_ATR(13) /* ALE to RE delay = 14*HCLK */ +#define EXMC_ALE_RE_DELAY_15_HCLK NPCTL_ATR(14) /* ALE to RE delay = 15*HCLK */ +#define EXMC_ALE_RE_DELAY_16_HCLK NPCTL_ATR(15) /* ALE to RE delay = 16*HCLK */ /* CLE to RE delay */ -#define NPCTL_CTR(regval) (BITS(9,12) & ((uint32_t)(regval) << 9)) -#define EXMC_CLE_RE_DELAY_1_HCLK NPCTL_CTR(0) /* CLE to RE delay = 1*HCLK */ -#define EXMC_CLE_RE_DELAY_2_HCLK NPCTL_CTR(1) /* CLE to RE delay = 2*HCLK */ -#define EXMC_CLE_RE_DELAY_3_HCLK NPCTL_CTR(2) /* CLE to RE delay = 3*HCLK */ -#define EXMC_CLE_RE_DELAY_4_HCLK NPCTL_CTR(3) /* CLE to RE delay = 4*HCLK */ -#define EXMC_CLE_RE_DELAY_5_HCLK NPCTL_CTR(4) /* CLE to RE delay = 5*HCLK */ -#define EXMC_CLE_RE_DELAY_6_HCLK NPCTL_CTR(5) /* CLE to RE delay = 6*HCLK */ -#define EXMC_CLE_RE_DELAY_7_HCLK NPCTL_CTR(6) /* CLE to RE delay = 7*HCLK */ -#define EXMC_CLE_RE_DELAY_8_HCLK NPCTL_CTR(7) /* CLE to RE delay = 8*HCLK */ -#define EXMC_CLE_RE_DELAY_9_HCLK NPCTL_CTR(8) /* CLE to RE delay = 9*HCLK */ -#define EXMC_CLE_RE_DELAY_10_HCLK NPCTL_CTR(9) /* CLE to RE delay = 10*HCLK */ -#define EXMC_CLE_RE_DELAY_11_HCLK NPCTL_CTR(10) /* CLE to RE delay = 11*HCLK */ -#define EXMC_CLE_RE_DELAY_12_HCLK NPCTL_CTR(11) /* CLE to RE delay = 12*HCLK */ -#define EXMC_CLE_RE_DELAY_13_HCLK NPCTL_CTR(12) /* CLE to RE delay = 13*HCLK */ -#define EXMC_CLE_RE_DELAY_14_HCLK NPCTL_CTR(13) /* CLE to RE delay = 14*HCLK */ -#define EXMC_CLE_RE_DELAY_15_HCLK NPCTL_CTR(14) /* CLE to RE delay = 15*HCLK */ -#define EXMC_CLE_RE_DELAY_16_HCLK NPCTL_CTR(15) /* CLE to RE delay = 16*HCLK */ +#define NPCTL_CTR(regval) (BITS(9,12) & ((uint32_t)(regval) << 9)) +#define EXMC_CLE_RE_DELAY_1_HCLK NPCTL_CTR(0) /* CLE to RE delay = 1*HCLK */ +#define EXMC_CLE_RE_DELAY_2_HCLK NPCTL_CTR(1) /* CLE to RE delay = 2*HCLK */ +#define EXMC_CLE_RE_DELAY_3_HCLK NPCTL_CTR(2) /* CLE to RE delay = 3*HCLK */ +#define EXMC_CLE_RE_DELAY_4_HCLK NPCTL_CTR(3) /* CLE to RE delay = 4*HCLK */ +#define EXMC_CLE_RE_DELAY_5_HCLK NPCTL_CTR(4) /* CLE to RE delay = 5*HCLK */ +#define EXMC_CLE_RE_DELAY_6_HCLK NPCTL_CTR(5) /* CLE to RE delay = 6*HCLK */ +#define EXMC_CLE_RE_DELAY_7_HCLK NPCTL_CTR(6) /* CLE to RE delay = 7*HCLK */ +#define EXMC_CLE_RE_DELAY_8_HCLK NPCTL_CTR(7) /* CLE to RE delay = 8*HCLK */ +#define EXMC_CLE_RE_DELAY_9_HCLK NPCTL_CTR(8) /* CLE to RE delay = 9*HCLK */ +#define EXMC_CLE_RE_DELAY_10_HCLK NPCTL_CTR(9) /* CLE to RE delay = 10*HCLK */ +#define EXMC_CLE_RE_DELAY_11_HCLK NPCTL_CTR(10) /* CLE to RE delay = 11*HCLK */ +#define EXMC_CLE_RE_DELAY_12_HCLK NPCTL_CTR(11) /* CLE to RE delay = 12*HCLK */ +#define EXMC_CLE_RE_DELAY_13_HCLK NPCTL_CTR(12) /* CLE to RE delay = 13*HCLK */ +#define EXMC_CLE_RE_DELAY_14_HCLK NPCTL_CTR(13) /* CLE to RE delay = 14*HCLK */ +#define EXMC_CLE_RE_DELAY_15_HCLK NPCTL_CTR(14) /* CLE to RE delay = 15*HCLK */ +#define EXMC_CLE_RE_DELAY_16_HCLK NPCTL_CTR(15) /* CLE to RE delay = 16*HCLK */ /* NAND bank memory data bus width */ -#define NPCTL_NDW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) -#define EXMC_NAND_DATABUS_WIDTH_8B NPCTL_NDW(0) /*!< NAND data width 8 bits */ -#define EXMC_NAND_DATABUS_WIDTH_16B NPCTL_NDW(1) /*!< NAND data width 16 bits */ +#define NPCTL_NDW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) +#define EXMC_NAND_DATABUS_WIDTH_8B NPCTL_NDW(0) /*!< NAND data width is 8 bits */ +#define EXMC_NAND_DATABUS_WIDTH_16B NPCTL_NDW(1) /*!< NAND data width is 16 bits */ /* SDRAM pipeline delay */ -#define SDCTL_PIPED(regval) (BITS(13,14) & ((uint32_t)(regval) << 13)) -#define EXMC_PIPELINE_DELAY_0_HCLK SDCTL_PIPED(0) /*!< 0 HCLK clock cycle delay */ -#define EXMC_PIPELINE_DELAY_1_HCLK SDCTL_PIPED(1) /*!< 1 HCLK clock cycle delay */ -#define EXMC_PIPELINE_DELAY_2_HCLK SDCTL_PIPED(2) /*!< 2 HCLK clock cycle delay */ +#define SDCTL_PIPED(regval) (BITS(13,14) & ((uint32_t)(regval) << 13)) +#define EXMC_PIPELINE_DELAY_0_HCLK SDCTL_PIPED(0) /*!< 0 HCLK clock cycle delay */ +#define EXMC_PIPELINE_DELAY_1_HCLK SDCTL_PIPED(1) /*!< 1 HCLK clock cycle delay */ +#define EXMC_PIPELINE_DELAY_2_HCLK SDCTL_PIPED(2) /*!< 2 HCLK clock cycle delay */ /* SDRAM clock configuration */ -#define SDCTL_SDCLK(regval) (BITS(10,11) & ((uint32_t)(regval) << 10)) -#define EXMC_SDCLK_DISABLE SDCTL_SDCLK(0) /*!< SDCLK memory clock disabled */ -#define EXMC_SDCLK_PERIODS_2_HCLK SDCTL_SDCLK(2) /*!< SDCLK memory period = 2*HCLK */ -#define EXMC_SDCLK_PERIODS_3_HCLK SDCTL_SDCLK(3) /*!< SDCLK memory period = 3*HCLK */ +#define SDCTL_SDCLK(regval) (BITS(10,11) & ((uint32_t)(regval) << 10)) +#define EXMC_SDCLK_DISABLE SDCTL_SDCLK(0) /*!< SDCLK memory clock disabled */ +#define EXMC_SDCLK_PERIODS_2_HCLK SDCTL_SDCLK(2) /*!< SDCLK memory period = 2*HCLK */ +#define EXMC_SDCLK_PERIODS_3_HCLK SDCTL_SDCLK(3) /*!< SDCLK memory period = 3*HCLK */ /* CAS latency */ -#define SDCTL_CL(regval) (BITS(7,8) & ((uint32_t)(regval) << 7)) -#define EXMC_CAS_LATENCY_1_SDCLK SDCTL_CL(1) /*!< CAS latency is 1 memory clock cycle */ -#define EXMC_CAS_LATENCY_2_SDCLK SDCTL_CL(2) /*!< CAS latency is 2 memory clock cycle */ -#define EXMC_CAS_LATENCY_3_SDCLK SDCTL_CL(3) /*!< CAS latency is 3 memory clock cycle */ +#define SDCTL_CL(regval) (BITS(7,8) & ((uint32_t)(regval) << 7)) +#define EXMC_CAS_LATENCY_1_SDCLK SDCTL_CL(1) /*!< CAS latency is 1 memory clock cycle */ +#define EXMC_CAS_LATENCY_2_SDCLK SDCTL_CL(2) /*!< CAS latency is 2 memory clock cycle */ +#define EXMC_CAS_LATENCY_3_SDCLK SDCTL_CL(3) /*!< CAS latency is 3 memory clock cycle */ /* SDRAM data bus width */ -#define SDCTL_SDW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) -#define EXMC_SDRAM_DATABUS_WIDTH_8B SDCTL_SDW(0) /*!< SDRAM data width 8 bits */ -#define EXMC_SDRAM_DATABUS_WIDTH_16B SDCTL_SDW(1) /*!< SDRAM data width 16 bits */ -#define EXMC_SDRAM_DATABUS_WIDTH_32B SDCTL_SDW(2) /*!< SDRAM data width 32 bits */ +#define SDCTL_SDW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) +#define EXMC_SDRAM_DATABUS_WIDTH_8B SDCTL_SDW(0) /*!< SDRAM data width 8 bits */ +#define EXMC_SDRAM_DATABUS_WIDTH_16B SDCTL_SDW(1) /*!< SDRAM data width 16 bits */ +#define EXMC_SDRAM_DATABUS_WIDTH_32B SDCTL_SDW(2) /*!< SDRAM data width 32 bits */ /* SDRAM row address bit width */ -#define SDCTL_RAW(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) -#define EXMC_SDRAM_ROW_ADDRESS_11 SDCTL_RAW(0) /*!< row address bit width is 11 bits */ -#define EXMC_SDRAM_ROW_ADDRESS_12 SDCTL_RAW(1) /*!< row address bit width is 12 bits */ -#define EXMC_SDRAM_ROW_ADDRESS_13 SDCTL_RAW(2) /*!< row address bit width is 13 bits */ +#define SDCTL_RAW(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) +#define EXMC_SDRAM_ROW_ADDRESS_11 SDCTL_RAW(0) /*!< row address bit width is 11 bits */ +#define EXMC_SDRAM_ROW_ADDRESS_12 SDCTL_RAW(1) /*!< row address bit width is 12 bits */ +#define EXMC_SDRAM_ROW_ADDRESS_13 SDCTL_RAW(2) /*!< row address bit width is 13 bits */ /* SDRAM column address bit width */ -#define SDCTL_CAW(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define EXMC_SDRAM_COW_ADDRESS_8 SDCTL_CAW(0) /*!< column address bit width is 8 bits */ -#define EXMC_SDRAM_COW_ADDRESS_9 SDCTL_CAW(1) /*!< column address bit width is 9 bits */ -#define EXMC_SDRAM_COW_ADDRESS_10 SDCTL_CAW(2) /*!< column address bit width is 10 bits */ -#define EXMC_SDRAM_COW_ADDRESS_11 SDCTL_CAW(3) /*!< column address bit width is 11 bits */ +#define SDCTL_CAW(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define EXMC_SDRAM_COW_ADDRESS_8 SDCTL_CAW(0) /*!< column address bit width is 8 bits */ +#define EXMC_SDRAM_COW_ADDRESS_9 SDCTL_CAW(1) /*!< column address bit width is 9 bits */ +#define EXMC_SDRAM_COW_ADDRESS_10 SDCTL_CAW(2) /*!< column address bit width is 10 bits */ +#define EXMC_SDRAM_COW_ADDRESS_11 SDCTL_CAW(3) /*!< column address bit width is 11 bits */ /* SDRAM number of successive auto-refresh */ -#define SDCMD_NARF(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) -#define EXMC_SDRAM_AUTO_REFLESH_1_SDCLK SDCMD_NARF(0) /*!< 1 auto-refresh cycle */ -#define EXMC_SDRAM_AUTO_REFLESH_2_SDCLK SDCMD_NARF(1) /*!< 2 auto-refresh cycles */ -#define EXMC_SDRAM_AUTO_REFLESH_3_SDCLK SDCMD_NARF(2) /*!< 3 auto-refresh cycles */ -#define EXMC_SDRAM_AUTO_REFLESH_4_SDCLK SDCMD_NARF(3) /*!< 4 auto-refresh cycles */ -#define EXMC_SDRAM_AUTO_REFLESH_5_SDCLK SDCMD_NARF(4) /*!< 5 auto-refresh cycles */ -#define EXMC_SDRAM_AUTO_REFLESH_6_SDCLK SDCMD_NARF(5) /*!< 6 auto-refresh cycles */ -#define EXMC_SDRAM_AUTO_REFLESH_7_SDCLK SDCMD_NARF(6) /*!< 7 auto-refresh cycles */ -#define EXMC_SDRAM_AUTO_REFLESH_8_SDCLK SDCMD_NARF(7) /*!< 8 auto-refresh cycles */ -#define EXMC_SDRAM_AUTO_REFLESH_9_SDCLK SDCMD_NARF(8) /*!< 9 auto-refresh cycles */ -#define EXMC_SDRAM_AUTO_REFLESH_10_SDCLK SDCMD_NARF(9) /*!< 10 auto-refresh cycles */ -#define EXMC_SDRAM_AUTO_REFLESH_11_SDCLK SDCMD_NARF(10) /*!< 11 auto-refresh cycles */ -#define EXMC_SDRAM_AUTO_REFLESH_12_SDCLK SDCMD_NARF(11) /*!< 12 auto-refresh cycles */ -#define EXMC_SDRAM_AUTO_REFLESH_13_SDCLK SDCMD_NARF(12) /*!< 13 auto-refresh cycles */ -#define EXMC_SDRAM_AUTO_REFLESH_14_SDCLK SDCMD_NARF(13) /*!< 14 auto-refresh cycles */ -#define EXMC_SDRAM_AUTO_REFLESH_15_SDCLK SDCMD_NARF(14) /*!< 15 auto-refresh cycles */ +#define SDCMD_NARF(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) +#define EXMC_SDRAM_AUTO_REFLESH_1_SDCLK SDCMD_NARF(0) /*!< 1 auto-refresh cycle */ +#define EXMC_SDRAM_AUTO_REFLESH_2_SDCLK SDCMD_NARF(1) /*!< 2 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_3_SDCLK SDCMD_NARF(2) /*!< 3 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_4_SDCLK SDCMD_NARF(3) /*!< 4 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_5_SDCLK SDCMD_NARF(4) /*!< 5 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_6_SDCLK SDCMD_NARF(5) /*!< 6 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_7_SDCLK SDCMD_NARF(6) /*!< 7 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_8_SDCLK SDCMD_NARF(7) /*!< 8 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_9_SDCLK SDCMD_NARF(8) /*!< 9 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_10_SDCLK SDCMD_NARF(9) /*!< 10 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_11_SDCLK SDCMD_NARF(10) /*!< 11 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_12_SDCLK SDCMD_NARF(11) /*!< 12 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_13_SDCLK SDCMD_NARF(12) /*!< 13 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_14_SDCLK SDCMD_NARF(13) /*!< 14 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_15_SDCLK SDCMD_NARF(14) /*!< 15 auto-refresh cycles */ /* SDRAM command select */ -#define SDCMD_CMD(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) -#define EXMC_SDRAM_NORMAL_OPERATION SDCMD_CMD(0) /*!< normal operation command */ -#define EXMC_SDRAM_CLOCK_ENABLE SDCMD_CMD(1) /*!< clock enable command */ -#define EXMC_SDRAM_PRECHARGE_ALL SDCMD_CMD(2) /*!< precharge all command */ -#define EXMC_SDRAM_AUTO_REFRESH SDCMD_CMD(3) /*!< auto-refresh command */ -#define EXMC_SDRAM_LOAD_MODE_REGISTER SDCMD_CMD(4) /*!< load mode register command */ -#define EXMC_SDRAM_SELF_REFRESH SDCMD_CMD(5) /*!< self-refresh command */ -#define EXMC_SDRAM_POWERDOWN_ENTRY SDCMD_CMD(6) /*!< power-down entry command */ +#define SDCMD_CMD(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) +#define EXMC_SDRAM_NORMAL_OPERATION SDCMD_CMD(0) /*!< normal operation command */ +#define EXMC_SDRAM_CLOCK_ENABLE SDCMD_CMD(1) /*!< clock enable command */ +#define EXMC_SDRAM_PRECHARGE_ALL SDCMD_CMD(2) /*!< precharge all command */ +#define EXMC_SDRAM_AUTO_REFRESH SDCMD_CMD(3) /*!< auto-refresh command */ +#define EXMC_SDRAM_LOAD_MODE_REGISTER SDCMD_CMD(4) /*!< load mode register command */ +#define EXMC_SDRAM_SELF_REFRESH SDCMD_CMD(5) /*!< self-refresh command */ +#define EXMC_SDRAM_POWERDOWN_ENTRY SDCMD_CMD(6) /*!< power-down entry command */ /* SDRAM the delayed sample clock of read data */ -#define SDRSCTL_SDSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) -#define EXMC_SDRAM_0_DELAY_CELL SDRSCTL_SDSC(0) /*!< select the clock after 0 delay cell */ -#define EXMC_SDRAM_1_DELAY_CELL SDRSCTL_SDSC(1) /*!< select the clock after 1 delay cell */ -#define EXMC_SDRAM_2_DELAY_CELL SDRSCTL_SDSC(2) /*!< select the clock after 2 delay cell */ -#define EXMC_SDRAM_3_DELAY_CELL SDRSCTL_SDSC(3) /*!< select the clock after 3 delay cell */ -#define EXMC_SDRAM_4_DELAY_CELL SDRSCTL_SDSC(4) /*!< select the clock after 4 delay cell */ -#define EXMC_SDRAM_5_DELAY_CELL SDRSCTL_SDSC(5) /*!< select the clock after 5 delay cell */ -#define EXMC_SDRAM_6_DELAY_CELL SDRSCTL_SDSC(6) /*!< select the clock after 6 delay cell */ -#define EXMC_SDRAM_7_DELAY_CELL SDRSCTL_SDSC(7) /*!< select the clock after 7 delay cell */ -#define EXMC_SDRAM_8_DELAY_CELL SDRSCTL_SDSC(8) /*!< select the clock after 8 delay cell */ -#define EXMC_SDRAM_9_DELAY_CELL SDRSCTL_SDSC(9) /*!< select the clock after 9 delay cell */ -#define EXMC_SDRAM_10_DELAY_CELL SDRSCTL_SDSC(10) /*!< select the clock after 10 delay cell */ -#define EXMC_SDRAM_11_DELAY_CELL SDRSCTL_SDSC(11) /*!< select the clock after 11 delay cell */ -#define EXMC_SDRAM_12_DELAY_CELL SDRSCTL_SDSC(12) /*!< select the clock after 12 delay cell */ -#define EXMC_SDRAM_13_DELAY_CELL SDRSCTL_SDSC(13) /*!< select the clock after 13 delay cell */ -#define EXMC_SDRAM_14_DELAY_CELL SDRSCTL_SDSC(14) /*!< select the clock after 14 delay cell */ -#define EXMC_SDRAM_15_DELAY_CELL SDRSCTL_SDSC(15) /*!< select the clock after 15 delay cell */ +#define SDRSCTL_SDSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) +#define EXMC_SDRAM_0_DELAY_CELL SDRSCTL_SDSC(0) /*!< select the clock after 0 delay cell */ +#define EXMC_SDRAM_1_DELAY_CELL SDRSCTL_SDSC(1) /*!< select the clock after 1 delay cell */ +#define EXMC_SDRAM_2_DELAY_CELL SDRSCTL_SDSC(2) /*!< select the clock after 2 delay cell */ +#define EXMC_SDRAM_3_DELAY_CELL SDRSCTL_SDSC(3) /*!< select the clock after 3 delay cell */ +#define EXMC_SDRAM_4_DELAY_CELL SDRSCTL_SDSC(4) /*!< select the clock after 4 delay cell */ +#define EXMC_SDRAM_5_DELAY_CELL SDRSCTL_SDSC(5) /*!< select the clock after 5 delay cell */ +#define EXMC_SDRAM_6_DELAY_CELL SDRSCTL_SDSC(6) /*!< select the clock after 6 delay cell */ +#define EXMC_SDRAM_7_DELAY_CELL SDRSCTL_SDSC(7) /*!< select the clock after 7 delay cell */ +#define EXMC_SDRAM_8_DELAY_CELL SDRSCTL_SDSC(8) /*!< select the clock after 8 delay cell */ +#define EXMC_SDRAM_9_DELAY_CELL SDRSCTL_SDSC(9) /*!< select the clock after 9 delay cell */ +#define EXMC_SDRAM_10_DELAY_CELL SDRSCTL_SDSC(10) /*!< select the clock after 10 delay cell */ +#define EXMC_SDRAM_11_DELAY_CELL SDRSCTL_SDSC(11) /*!< select the clock after 11 delay cell */ +#define EXMC_SDRAM_12_DELAY_CELL SDRSCTL_SDSC(12) /*!< select the clock after 12 delay cell */ +#define EXMC_SDRAM_13_DELAY_CELL SDRSCTL_SDSC(13) /*!< select the clock after 13 delay cell */ +#define EXMC_SDRAM_14_DELAY_CELL SDRSCTL_SDSC(14) /*!< select the clock after 14 delay cell */ +#define EXMC_SDRAM_15_DELAY_CELL SDRSCTL_SDSC(15) /*!< select the clock after 15 delay cell */ /* SPI PSRAM ID length */ -#define SINIT_IDL(regval) (BITS(29,30) & ((uint32_t)(regval) << 29)) -#define EXMC_SQPIPSRAM_ID_LENGTH_64B SINIT_IDL(0) /*!< SPI PSRAM ID length is 64 bits */ -#define EXMC_SQPIPSRAM_ID_LENGTH_32B SINIT_IDL(1) /*!< SPI PSRAM ID length is 32 bits */ -#define EXMC_SQPIPSRAM_ID_LENGTH_16B SINIT_IDL(2) /*!< SPI PSRAM ID length is 16 bits */ -#define EXMC_SQPIPSRAM_ID_LENGTH_8B SINIT_IDL(3) /*!< SPI PSRAM ID length is 8 bits */ +#define SINIT_IDL(regval) (BITS(29,30) & ((uint32_t)(regval) << 29)) +#define EXMC_SQPIPSRAM_ID_LENGTH_64B SINIT_IDL(0) /*!< SPI PSRAM ID length is 64 bits */ +#define EXMC_SQPIPSRAM_ID_LENGTH_32B SINIT_IDL(1) /*!< SPI PSRAM ID length is 32 bits */ +#define EXMC_SQPIPSRAM_ID_LENGTH_16B SINIT_IDL(2) /*!< SPI PSRAM ID length is 16 bits */ +#define EXMC_SQPIPSRAM_ID_LENGTH_8B SINIT_IDL(3) /*!< SPI PSRAM ID length is 8 bits */ /* SPI PSRAM bit number of address phase */ -#define SINIT_ADRBIT(regval) (BITS(24,28) & ((uint32_t)(regval) << 24)) -#define EXMC_SQPIPSRAM_ADDR_LENGTH_1B SINIT_ADRBIT(1) /*!< SPI PSRAM address is 1 bit */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_2B SINIT_ADRBIT(2) /*!< SPI PSRAM address is 2 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_3B SINIT_ADRBIT(3) /*!< SPI PSRAM address is 3 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_4B SINIT_ADRBIT(4) /*!< SPI PSRAM address is 4 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_5B SINIT_ADRBIT(5) /*!< SPI PSRAM address is 5 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_6B SINIT_ADRBIT(6) /*!< SPI PSRAM address is 6 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_7B SINIT_ADRBIT(7) /*!< SPI PSRAM address is 7 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_8B SINIT_ADRBIT(8) /*!< SPI PSRAM address is 8 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_9B SINIT_ADRBIT(9) /*!< SPI PSRAM address is 9 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_10B SINIT_ADRBIT(10) /*!< SPI PSRAM address is 10 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_11B SINIT_ADRBIT(11) /*!< SPI PSRAM address is 11 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_12B SINIT_ADRBIT(12) /*!< SPI PSRAM address is 12 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_13B SINIT_ADRBIT(13) /*!< SPI PSRAM address is 13 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_14B SINIT_ADRBIT(14) /*!< SPI PSRAM address is 14 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_15B SINIT_ADRBIT(15) /*!< SPI PSRAM address is 15 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_16B SINIT_ADRBIT(16) /*!< SPI PSRAM address is 16 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_17B SINIT_ADRBIT(17) /*!< SPI PSRAM address is 17 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_18B SINIT_ADRBIT(18) /*!< SPI PSRAM address is 18 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_19B SINIT_ADRBIT(19) /*!< SPI PSRAM address is 19 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_20B SINIT_ADRBIT(20) /*!< SPI PSRAM address is 20 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_21B SINIT_ADRBIT(21) /*!< SPI PSRAM address is 21 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_22B SINIT_ADRBIT(22) /*!< SPI PSRAM address is 22 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_23B SINIT_ADRBIT(23) /*!< SPI PSRAM address is 23 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_24B SINIT_ADRBIT(24) /*!< SPI PSRAM address is 24 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_25B SINIT_ADRBIT(25) /*!< SPI PSRAM address is 25 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_26B SINIT_ADRBIT(26) /*!< SPI PSRAM address is 26 bits */ +#define SINIT_ADRBIT(regval) (BITS(24,28) & ((uint32_t)(regval) << 24)) +#define EXMC_SQPIPSRAM_ADDR_LENGTH_1B SINIT_ADRBIT(1) /*!< SPI PSRAM address is 1 bit */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_2B SINIT_ADRBIT(2) /*!< SPI PSRAM address is 2 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_3B SINIT_ADRBIT(3) /*!< SPI PSRAM address is 3 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_4B SINIT_ADRBIT(4) /*!< SPI PSRAM address is 4 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_5B SINIT_ADRBIT(5) /*!< SPI PSRAM address is 5 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_6B SINIT_ADRBIT(6) /*!< SPI PSRAM address is 6 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_7B SINIT_ADRBIT(7) /*!< SPI PSRAM address is 7 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_8B SINIT_ADRBIT(8) /*!< SPI PSRAM address is 8 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_9B SINIT_ADRBIT(9) /*!< SPI PSRAM address is 9 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_10B SINIT_ADRBIT(10) /*!< SPI PSRAM address is 10 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_11B SINIT_ADRBIT(11) /*!< SPI PSRAM address is 11 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_12B SINIT_ADRBIT(12) /*!< SPI PSRAM address is 12 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_13B SINIT_ADRBIT(13) /*!< SPI PSRAM address is 13 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_14B SINIT_ADRBIT(14) /*!< SPI PSRAM address is 14 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_15B SINIT_ADRBIT(15) /*!< SPI PSRAM address is 15 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_16B SINIT_ADRBIT(16) /*!< SPI PSRAM address is 16 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_17B SINIT_ADRBIT(17) /*!< SPI PSRAM address is 17 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_18B SINIT_ADRBIT(18) /*!< SPI PSRAM address is 18 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_19B SINIT_ADRBIT(19) /*!< SPI PSRAM address is 19 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_20B SINIT_ADRBIT(20) /*!< SPI PSRAM address is 20 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_21B SINIT_ADRBIT(21) /*!< SPI PSRAM address is 21 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_22B SINIT_ADRBIT(22) /*!< SPI PSRAM address is 22 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_23B SINIT_ADRBIT(23) /*!< SPI PSRAM address is 23 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_24B SINIT_ADRBIT(24) /*!< SPI PSRAM address is 24 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_25B SINIT_ADRBIT(25) /*!< SPI PSRAM address is 25 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_26B SINIT_ADRBIT(26) /*!< SPI PSRAM address is 26 bits */ /* SPI PSRAM bit number of command phase */ -#define SINIT_CMDBIT(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) -#define EXMC_SQPIPSRAM_COMMAND_LENGTH_4B SINIT_CMDBIT(0) /*!< SPI PSRAM command is 4 bits */ -#define EXMC_SQPIPSRAM_COMMAND_LENGTH_8B SINIT_CMDBIT(1) /*!< SPI PSRAM command is 8 bits */ -#define EXMC_SQPIPSRAM_COMMAND_LENGTH_16B SINIT_CMDBIT(2) /*!< SPI PSRAM command is 16 bits */ +#define SINIT_CMDBIT(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) +#define EXMC_SQPIPSRAM_COMMAND_LENGTH_4B SINIT_CMDBIT(0) /*!< SPI PSRAM command is 4 bits */ +#define EXMC_SQPIPSRAM_COMMAND_LENGTH_8B SINIT_CMDBIT(1) /*!< SPI PSRAM command is 8 bits */ +#define EXMC_SQPIPSRAM_COMMAND_LENGTH_16B SINIT_CMDBIT(2) /*!< SPI PSRAM command is 16 bits */ /* SPI PSRAM read command mode */ -#define SRCMD_RMODE(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) -#define EXMC_SQPIPSRAM_READ_MODE_DISABLE SRCMD_RMODE(0) /*!< not SPI mode */ -#define EXMC_SQPIPSRAM_READ_MODE_SPI SRCMD_RMODE(1) /*!< SPI mode */ -#define EXMC_SQPIPSRAM_READ_MODE_SQPI SRCMD_RMODE(2) /*!< SQPI mode */ -#define EXMC_SQPIPSRAM_READ_MODE_QPI SRCMD_RMODE(3) /*!< QPI mode */ +#define SRCMD_RMODE(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) +#define EXMC_SQPIPSRAM_READ_MODE_DISABLE SRCMD_RMODE(0) /*!< not SPI mode */ +#define EXMC_SQPIPSRAM_READ_MODE_SPI SRCMD_RMODE(1) /*!< SPI mode */ +#define EXMC_SQPIPSRAM_READ_MODE_SQPI SRCMD_RMODE(2) /*!< SQPI mode */ +#define EXMC_SQPIPSRAM_READ_MODE_QPI SRCMD_RMODE(3) /*!< QPI mode */ /* SPI PSRAM write command mode */ -#define SRCMD_WMODE(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) -#define EXMC_SQPIPSRAM_WRITE_MODE_DISABLE SRCMD_WMODE(0) /*!< not SPI mode */ -#define EXMC_SQPIPSRAM_WRITE_MODE_SPI SRCMD_WMODE(1) /*!< SPI mode */ -#define EXMC_SQPIPSRAM_WRITE_MODE_SQPI SRCMD_WMODE(2) /*!< SQPI mode */ -#define EXMC_SQPIPSRAM_WRITE_MODE_QPI SRCMD_WMODE(3) /*!< QPI mode */ +#define SRCMD_WMODE(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) +#define EXMC_SQPIPSRAM_WRITE_MODE_DISABLE SRCMD_WMODE(0) /*!< not SPI mode */ +#define EXMC_SQPIPSRAM_WRITE_MODE_SPI SRCMD_WMODE(1) /*!< SPI mode */ +#define EXMC_SQPIPSRAM_WRITE_MODE_SQPI SRCMD_WMODE(2) /*!< SQPI mode */ +#define EXMC_SQPIPSRAM_WRITE_MODE_QPI SRCMD_WMODE(3) /*!< QPI mode */ /* EXMC NOR/SRAM bank region definition */ -#define EXMC_BANK0_NORSRAM_REGION0 ((uint32_t)0x00000000U) /*!< bank0 NOR/SRAM region0 */ -#define EXMC_BANK0_NORSRAM_REGION1 ((uint32_t)0x00000001U) /*!< bank0 NOR/SRAM region1 */ -#define EXMC_BANK0_NORSRAM_REGION2 ((uint32_t)0x00000002U) /*!< bank0 NOR/SRAM region2 */ -#define EXMC_BANK0_NORSRAM_REGION3 ((uint32_t)0x00000003U) /*!< bank0 NOR/SRAM region3 */ +#define EXMC_BANK0_NORSRAM_REGION0 ((uint32_t)0x00000000U) /*!< bank0 NOR/SRAM region0 */ +#define EXMC_BANK0_NORSRAM_REGION1 ((uint32_t)0x00000001U) /*!< bank0 NOR/SRAM region1 */ +#define EXMC_BANK0_NORSRAM_REGION2 ((uint32_t)0x00000002U) /*!< bank0 NOR/SRAM region2 */ +#define EXMC_BANK0_NORSRAM_REGION3 ((uint32_t)0x00000003U) /*!< bank0 NOR/SRAM region3 */ /* EXMC consecutive clock */ -#define EXMC_CLOCK_SYN_MODE ((uint32_t)0x00000000U) /*!< EXMC_CLK is generated only during synchronous access */ -#define EXMC_CLOCK_UNCONDITIONALLY ((uint32_t)0x00010000U) /*!< EXMC_CLK is generated unconditionally */ +#define EXMC_CLOCK_SYN_MODE ((uint32_t)0x00000000U) /*!< EXMC_CLK is generated only during synchronous access */ +#define EXMC_CLOCK_UNCONDITIONALLY EXMC_SNCTL_CCK /*!< EXMC_CLK is generated unconditionally */ /* EXMC NOR/SRAM write mode */ -#define EXMC_ASYN_WRITE ((uint32_t)0x00000000U) /*!< asynchronous write mode */ -#define EXMC_SYN_WRITE ((uint32_t)0x00008000U) /*!< synchronous write mode */ +#define EXMC_ASYN_WRITE ((uint32_t)0x00000000U) /*!< asynchronous write mode */ +#define EXMC_SYN_WRITE EXMC_SNCTL_SYNCWR /*!< synchronous write mode */ /* EXMC NWAIT signal configuration */ -#define EXMC_NWAIT_CONFIG_BEFORE ((uint32_t)0x00000000U) /*!< NWAIT signal is active one data cycle before wait state */ -#define EXMC_NWAIT_CONFIG_DURING ((uint32_t)0x00000800U) /*!< NWAIT signal is active during wait state */ +#define EXMC_NWAIT_CONFIG_BEFORE ((uint32_t)0x00000000U) /*!< NWAIT signal is active one data cycle before wait state */ +#define EXMC_NWAIT_CONFIG_DURING EXMC_SNCTL_NRWTCFG /*!< NWAIT signal is active during wait state */ /* EXMC NWAIT signal polarity configuration */ -#define EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level is active of NWAIT */ -#define EXMC_NWAIT_POLARITY_HIGH ((uint32_t)0x00000200U) /*!< high level is active of NWAIT */ +#define EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level is active of NWAIT */ +#define EXMC_NWAIT_POLARITY_HIGH EXMC_SNCTL_NRWTPOL /*!< high level is active of NWAIT */ /* EXMC NAND/PC card bank definition */ -#define EXMC_BANK1_NAND ((uint32_t)0x00000001U) /*!< bank1 NAND flash */ -#define EXMC_BANK2_NAND ((uint32_t)0x00000002U) /*!< bank2 NAND flash */ -#define EXMC_BANK3_PCCARD ((uint32_t)0x00000003U) /*!< bank3 PC card */ +#define EXMC_BANK1_NAND ((uint32_t)0x00000001U) /*!< NAND flash bank1 */ +#define EXMC_BANK2_NAND ((uint32_t)0x00000002U) /*!< NAND flash bank2 */ +#define EXMC_BANK3_PCCARD ((uint32_t)0x00000003U) /*!< PC card bank3 */ /* EXMC SDRAM bank definition */ -#define EXMC_SDRAM_DEVICE0 ((uint32_t)0x00000004U) /*!< SDRAM device0 */ -#define EXMC_SDRAM_DEVICE1 ((uint32_t)0x00000005U) /*!< SDRAM device1 */ +#define EXMC_SDRAM_DEVICE0 ((uint32_t)0x00000004U) /*!< SDRAM device0 */ +#define EXMC_SDRAM_DEVICE1 ((uint32_t)0x00000005U) /*!< SDRAM device1 */ /* EXMC SDRAM internal banks */ -#define EXMC_SDRAM_2_INTER_BANK ((uint32_t)0x00000000U) /*!< 2 internal banks */ -#define EXMC_SDRAM_4_INTER_BANK ((uint32_t)0x00000040U) /*!< 4 internal banks */ +#define EXMC_SDRAM_2_INTER_BANK ((uint32_t)0x00000000U) /*!< 2 internal banks */ +#define EXMC_SDRAM_4_INTER_BANK EXMC_SDCTL_NBK /*!< 4 internal banks */ /* SDRAM device0 select */ -#define EXMC_SDRAM_DEVICE0_UNSELECT ((uint32_t)0x00000000U) /*!< NAND data width 8 bits */ -#define EXMC_SDRAM_DEVICE0_SELECT ((uint32_t)0x00000010U) /*!< NAND data width 16 bits */ +#define EXMC_SDRAM_DEVICE0_UNSELECT ((uint32_t)0x00000000U) /*!< SDRAM device0 unselect */ +#define EXMC_SDRAM_DEVICE0_SELECT EXMC_SDCMD_DS0 /*!< SDRAM device0 select */ /* SDRAM device1 select */ -#define EXMC_SDRAM_DEVICE1_UNSELECT ((uint32_t)0x00000000U) /*!< NAND data width 8 bits */ -#define EXMC_SDRAM_DEVICE1_SELECT ((uint32_t)0x00000008U) /*!< NAND data width 16 bits */ +#define EXMC_SDRAM_DEVICE1_UNSELECT ((uint32_t)0x00000000U) /*!< SDRAM device1 unselect */ +#define EXMC_SDRAM_DEVICE1_SELECT EXMC_SDCMD_DS1 /*!< SDRAM device1 select */ /* SDRAM device status */ -#define EXMC_SDRAM_DEVICE_NORMAL ((uint32_t)0x00000000U) /*!< normal status */ -#define EXMC_SDRAM_DEVICE_SELF_REFRESH ((uint32_t)0x00000001U) /*!< self refresh status */ -#define EXMC_SDRAM_DEVICE_POWER_DOWN ((uint32_t)0x00000002U) /*!< power down status */ +#define EXMC_SDRAM_DEVICE_NORMAL ((uint32_t)0x00000000U) /*!< normal status */ +#define EXMC_SDRAM_DEVICE_SELF_REFRESH ((uint32_t)0x00000001U) /*!< self refresh status */ +#define EXMC_SDRAM_DEVICE_POWER_DOWN ((uint32_t)0x00000002U) /*!< power down status */ /* sample cycle of read data */ -#define EXMC_SDRAM_READSAMPLE_0_EXTRAHCLK ((uint32_t)0x00000000U) /*!< add 0 extra HCLK cycle to the read data sample clock besides the delay chain */ -#define EXMC_SDRAM_READSAMPLE_1_EXTRAHCLK ((uint32_t)0x00000002U) /*!< add 1 extra HCLK cycle to the read data sample clock besides the delay chain */ +#define EXMC_SDRAM_READSAMPLE_0_EXTRAHCLK ((uint32_t)0x00000000U) /*!< add 0 extra HCLK cycle to the read data sample clock besides the delay chain */ +#define EXMC_SDRAM_READSAMPLE_1_EXTRAHCLK EXMC_SDRSCTL_SSCR /*!< add 1 extra HCLK cycle to the read data sample clock besides the delay chain */ /* read data sample polarity */ -#define EXMC_SDRAM_SAMPLE_RISING_EDGE ((uint32_t)0x00000000U) /*!< sample data at rising edge */ -#define EXMC_SDRAM_SAMPLE_FALLING_EDGE ((uint32_t)0x80000000U) /*!< sample data at falling edge */ +#define EXMC_SQPIPSRAM_SAMPLE_RISING_EDGE ((uint32_t)0x00000000U) /*!< sample data at rising edge */ +#define EXMC_SQPIPSRAM_SAMPLE_FALLING_EDGE EXMC_SINIT_POL /*!< sample data at falling edge */ /* SQPI SRAM command flag */ -#define EXMC_SEND_COMMAND_FLAG_RDID EXMC_SRCMD_RDID /*!< EXMC_SRCMD_RDID flag bit */ -#define EXMC_SEND_COMMAND_FLAG_SC EXMC_SWCMD_SC /*!< EXMC_SWCMD_SC flag bit */ +#define EXMC_SEND_COMMAND_FLAG_RDID EXMC_SRCMD_RDID /*!< EXMC_SRCMD_RDID flag bit */ +#define EXMC_SEND_COMMAND_FLAG_SC EXMC_SWCMD_SC /*!< EXMC_SWCMD_SC flag bit */ /* EXMC flag bits */ -#define EXMC_NAND_PCCARD_FLAG_RISE EXMC_NPINTENx_INTRS /*!< interrupt rising edge status */ -#define EXMC_NAND_PCCARD_FLAG_LEVEL EXMC_NPINTENx_INTHS /*!< interrupt high-level status */ -#define EXMC_NAND_PCCARD_FLAG_FALL EXMC_NPINTENx_INTFS /*!< interrupt falling edge status */ -#define EXMC_NAND_PCCARD_FLAG_FIFOE EXMC_NPINTENx_INTEPT /*!< FIFO empty flag */ -#define EXMC_SDRAM_FLAG_REFRESH EXMC_SDSDAT_REIF /*!< refresh error interrupt flag */ -#define EXMC_SDRAM_FLAG_NREADY EXMC_SDSDAT_NRDY /*!< not ready status */ +#define EXMC_NAND_PCCARD_FLAG_RISE EXMC_NPINTEN_INTRS /*!< interrupt rising edge status */ +#define EXMC_NAND_PCCARD_FLAG_LEVEL EXMC_NPINTEN_INTHS /*!< interrupt high-level status */ +#define EXMC_NAND_PCCARD_FLAG_FALL EXMC_NPINTEN_INTFS /*!< interrupt falling edge status */ +#define EXMC_NAND_PCCARD_FLAG_FIFOE EXMC_NPINTEN_FFEPT /*!< FIFO empty flag */ +#define EXMC_SDRAM_FLAG_REFRESH EXMC_SDSDAT_REIF /*!< refresh error interrupt flag */ +#define EXMC_SDRAM_FLAG_NREADY EXMC_SDSDAT_NRDY /*!< not ready status */ /* EXMC interrupt flag bits */ -#define EXMC_NAND_PCCARD_INT_RISE EXMC_NPINTENx_INTREN /*!< interrupt rising edge detection enable */ -#define EXMC_NAND_PCCARD_INT_LEVEL EXMC_NPINTENx_INTHEN /*!< interrupt high-level detection enable */ -#define EXMC_NAND_PCCARD_INT_FALL EXMC_NPINTENx_INTFEN /*!< interrupt falling edge detection enable */ -#define EXMC_SDRAM_INT_REFRESH EXMC_SDARI_REIE /*!< interrupt refresh error enable */ +#define EXMC_NAND_PCCARD_INT_FLAG_RISE EXMC_NPINTEN_INTREN /*!< rising edge interrupt and flag */ +#define EXMC_NAND_PCCARD_INT_FLAG_LEVEL EXMC_NPINTEN_INTHEN /*!< high-level interrupt and flag */ +#define EXMC_NAND_PCCARD_INT_FLAG_FALL EXMC_NPINTEN_INTFEN /*!< falling edge interrupt and flag */ +#define EXMC_SDRAM_INT_FLAG_REFRESH EXMC_SDARI_REIE /*!< refresh error interrupt and flag */ /* function declarations */ +/* initialization functions */ +/* NOR/SRAM */ /* deinitialize EXMC NOR/SRAM region */ void exmc_norsram_deinit(uint32_t exmc_norsram_region); +/* initialize exmc_norsram_parameter_struct with the default values */ +void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); /* initialize EXMC NOR/SRAM region */ void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); -/* exmc_norsram_parameter_struct parameter initialize */ -void exmc_norsram_parameter_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); -/* consecutive clock configure */ -void exmc_norsram_consecutive_clock_config(uint32_t clock_mode); -/* CRAM page size configure */ -void exmc_norsram_page_size_config(uint32_t page_size); -/* EXMC NOR/SRAM bank enable */ +/* enable EXMC NOR/SRAM region */ void exmc_norsram_enable(uint32_t exmc_norsram_region); -/* EXMC NOR/SRAM bank disable */ +/* disable EXMC NOR/SRAM region */ void exmc_norsram_disable(uint32_t exmc_norsram_region); - - +/* NAND */ /* deinitialize EXMC NAND bank */ void exmc_nand_deinit(uint32_t exmc_nand_bank); +/* initialize exmc_norsram_parameter_struct with the default values */ +void exmc_nand_struct_para_init(exmc_nand_parameter_struct* exmc_nand_init_struct); /* initialize EXMC NAND bank */ void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct); -/* exmc_norsram_parameter_struct parameter initialize */ -void exmc_nand_parameter_init(exmc_nand_parameter_struct* exmc_nand_init_struct); -/* EXMC NAND bank enable */ +/* enable EXMC NAND bank */ void exmc_nand_enable(uint32_t exmc_nand_bank); -/* EXMC NAND bank disable */ +/* disable EXMC NAND bank */ void exmc_nand_disable(uint32_t exmc_nand_bank); +/* PC card */ +/* deinitialize EXMC PC card bank */ +void exmc_pccard_deinit(void); +/* initialize exmc_pccard_parameter_struct with the default values */ +void exmc_pccard_struct_para_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct); +/* initialize EXMC PC card bank */ +void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct); +/* enable EXMC PC card bank */ +void exmc_pccard_enable(void); +/* disable EXMC PC card bank */ +void exmc_pccard_disable(void); +/* SDRAM */ +/* deinitialize EXMC SDRAM device */ +void exmc_sdram_deinit(uint32_t exmc_sdram_device); +/* initialize exmc_sdram_parameter_struct with the default values */ +void exmc_sdram_struct_para_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct); +/* initialize EXMC SDRAM device */ +void exmc_sdram_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct); +/* SQPIPSRAM */ +/* deinitialize EXMC SQPIPSRAM */ +void exmc_sqpipsram_deinit(void); +/* initialize exmc_sqpipsram_parameter_struct with the default values */ +void exmc_sqpipsram_struct_para_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_struct); +/* initialize EXMC SQPIPSRAM */ +void exmc_sqpipsram_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_struct); + +/* function configuration */ +/* NOR/SRAM */ +/* configure consecutive clock */ +void exmc_norsram_consecutive_clock_config(uint32_t clock_mode); +/* configure CRAM page size */ +void exmc_norsram_page_size_config(uint32_t exmc_norsram_region, uint32_t page_size); +/* NAND */ /* enable or disable the EXMC NAND ECC function */ void exmc_nand_ecc_config(uint32_t exmc_nand_bank, ControlStatus newvalue); /* get the EXMC ECC value */ uint32_t exmc_ecc_get(uint32_t exmc_nand_bank); - - -/* deinitialize EXMC PC card bank */ -void exmc_pccard_deinit(void); -/* initialize EXMC PC card bank */ -void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct); -/* exmc_pccard_parameter_struct parameter initialize */ -void exmc_pccard_parameter_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct); -/* EXMC PC card bank enable */ -void exmc_pccard_enable(void); -/* EXMC PC card bank disable */ -void exmc_pccard_disable(void); - - -/* deinitialize EXMC SDRAM device */ -void exmc_sdram_deinit(uint32_t exmc_sdram_device); -/* initialize EXMC SDRAM device */ -void exmc_sdram_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct); -/* exmc_sdram_parameter_struct parameter initialize */ -void exmc_sdram_parameter_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct); +/* SDRAM */ +/* enable or disable read sample */ +void exmc_sdram_readsample_enable(ControlStatus newvalue); +/* configure the delayed sample clock of read data */ +void exmc_sdram_readsample_config(uint32_t delay_cell, uint32_t extra_hclk); /* configure the SDRAM memory command */ void exmc_sdram_command_config(exmc_sdram_command_parameter_struct* exmc_sdram_command_init_struct); /* set auto-refresh interval */ @@ -737,18 +776,7 @@ void exmc_sdram_autorefresh_number_set(uint32_t exmc_number); void exmc_sdram_write_protection_config(uint32_t exmc_sdram_device, ControlStatus newvalue); /* get the status of SDRAM device0 or device1 */ uint32_t exmc_sdram_bankstatus_get(uint32_t exmc_sdram_device); -/* configure the delayed sample clock of read data */ -void exmc_sdram_readsample_config(uint32_t delay_cell, uint32_t extra_hclk); -/* enable or disable read sample */ -void exmc_sdram_readsample_enable(ControlStatus newvalue); - - -/* deinitialize EXMC SQPIPSRAM */ -void exmc_sqpipsram_deinit(void); -/* initialize EXMC SQPIPSRAM */ -void exmc_sqpipsram_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_struct); -/* exmc_sqpipsram_parameter_struct parameter initialize */ -void exmc_sqpipsram_parameter_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_struct); +/* SQPIPSRAM */ /* set the read command */ void exmc_sqpipsram_read_command_set(uint32_t read_command_mode,uint32_t read_wait_cycle,uint32_t read_command_code); /* set the write command */ @@ -764,18 +792,18 @@ uint32_t exmc_sqpipsram_high_id_get(void); /* get the bit value of EXMC send write command bit or read ID command */ FlagStatus exmc_sqpipsram_send_command_state_get(uint32_t send_command_flag); - -/* check EXMC flag is set or not */ -FlagStatus exmc_flag_get(uint32_t exmc_bank,uint32_t flag); -/* clear EXMC flag */ -void exmc_flag_clear(uint32_t exmc_bank,uint32_t flag); -/* check EXMC flag is set or not */ -FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank,uint32_t interrupt_source); -/* clear EXMC one channel flag */ -void exmc_interrupt_flag_clear(uint32_t exmc_bank,uint32_t interrupt_source); +/* interrupt & flag functions */ /* enable EXMC interrupt */ -void exmc_interrupt_enable(uint32_t exmc_bank,uint32_t interrupt_source); +void exmc_interrupt_enable(uint32_t exmc_bank,uint32_t interrupt); /* disable EXMC interrupt */ -void exmc_interrupt_disable(uint32_t exmc_bank,uint32_t interrupt_source); +void exmc_interrupt_disable(uint32_t exmc_bank,uint32_t interrupt); +/* get EXMC flag status */ +FlagStatus exmc_flag_get(uint32_t exmc_bank,uint32_t flag); +/* clear EXMC flag status */ +void exmc_flag_clear(uint32_t exmc_bank,uint32_t flag); +/* get EXMC interrupt flag */ +FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank,uint32_t interrupt); +/* clear EXMC interrupt flag */ +void exmc_interrupt_flag_clear(uint32_t exmc_bank,uint32_t interrupt); #endif /* GD32F4XX_EXMC_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_exti.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_exti.h index a0ad59400a..3c2a27149d 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_exti.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_exti.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_exti.h - \brief definitions for the EXTI + \file gd32f4xx_exti.h + \brief definitions for the EXTI + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.1, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_EXTI_H @@ -97,6 +122,7 @@ #define EXTI_RTEN_RTEN17 BIT(17) /*!< rising edge from line 17 */ #define EXTI_RTEN_RTEN18 BIT(18) /*!< rising edge from line 18 */ #define EXTI_RTEN_RTEN19 BIT(19) /*!< rising edge from line 19 */ +#define EXTI_RTEN_RTEN20 BIT(20) /*!< rising edge from line 20 */ #define EXTI_RTEN_RTEN21 BIT(21) /*!< rising edge from line 21 */ #define EXTI_RTEN_RTEN22 BIT(22) /*!< rising edge from line 22 */ @@ -121,6 +147,7 @@ #define EXTI_FTEN_FTEN17 BIT(17) /*!< falling edge from line 17 */ #define EXTI_FTEN_FTEN18 BIT(18) /*!< falling edge from line 18 */ #define EXTI_FTEN_FTEN19 BIT(19) /*!< falling edge from line 19 */ +#define EXTI_FTEN_FTEN20 BIT(20) /*!< falling edge from line 20 */ #define EXTI_FTEN_FTEN21 BIT(21) /*!< falling edge from line 21 */ #define EXTI_FTEN_FTEN22 BIT(22) /*!< falling edge from line 22 */ @@ -145,6 +172,7 @@ #define EXTI_SWIEV_SWIEV17 BIT(17) /*!< software interrupt/event request from line 17 */ #define EXTI_SWIEV_SWIEV18 BIT(18) /*!< software interrupt/event request from line 18 */ #define EXTI_SWIEV_SWIEV19 BIT(19) /*!< software interrupt/event request from line 19 */ +#define EXTI_SWIEV_SWIEV20 BIT(20) /*!< software interrupt/event request from line 20 */ #define EXTI_SWIEV_SWIEV21 BIT(21) /*!< software interrupt/event request from line 21 */ #define EXTI_SWIEV_SWIEV22 BIT(22) /*!< software interrupt/event request from line 22 */ @@ -169,13 +197,14 @@ #define EXTI_PD_PD17 BIT(17) /*!< interrupt/event pending status from line 17 */ #define EXTI_PD_PD18 BIT(18) /*!< interrupt/event pending status from line 18 */ #define EXTI_PD_PD19 BIT(19) /*!< interrupt/event pending status from line 19 */ +#define EXTI_PD_PD20 BIT(20) /*!< interrupt/event pending status from line 20 */ #define EXTI_PD_PD21 BIT(21) /*!< interrupt/event pending status from line 21 */ #define EXTI_PD_PD22 BIT(22) /*!< interrupt/event pending status from line 22 */ /* constants definitions */ /* EXTI line number */ typedef enum -{ +{ EXTI_0 = BIT(0), /*!< EXTI line 0 */ EXTI_1 = BIT(1), /*!< EXTI line 1 */ EXTI_2 = BIT(2), /*!< EXTI line 2 */ @@ -196,7 +225,7 @@ typedef enum EXTI_17 = BIT(17), /*!< EXTI line 17 */ EXTI_18 = BIT(18), /*!< EXTI line 18 */ EXTI_19 = BIT(19), /*!< EXTI line 19 */ - EXTI_20 = BIT(20), /*!< EXTI line 20 */ + EXTI_20 = BIT(20), /*!< EXTI line 20 */ EXTI_21 = BIT(21), /*!< EXTI line 21 */ EXTI_22 = BIT(22), /*!< EXTI line 22 */ }exti_line_enum; @@ -210,10 +239,11 @@ typedef enum /* interrupt trigger mode */ typedef enum -{ +{ EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */ EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */ - EXTI_TRIG_BOTH /*!< EXTI rising and falling edge trigger */ + EXTI_TRIG_BOTH, /*!< EXTI rising and falling edge trigger */ + EXTI_TRIG_NONE /*!< none EXTI edge trigger */ }exti_trig_type_enum; /* function declarations */ @@ -223,13 +253,18 @@ void exti_deinit(void); void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type); /* enable the interrupts from EXTI line x */ void exti_interrupt_enable(exti_line_enum linex); -/* enable the events from EXTI line x */ -void exti_event_enable(exti_line_enum linex); /* disable the interrupts from EXTI line x */ void exti_interrupt_disable(exti_line_enum linex); +/* enable the events from EXTI line x */ +void exti_event_enable(exti_line_enum linex); /* disable the events from EXTI line x */ void exti_event_disable(exti_line_enum linex); +/* EXTI software interrupt event enable */ +void exti_software_interrupt_enable(exti_line_enum linex); +/* EXTI software interrupt event disable */ +void exti_software_interrupt_disable(exti_line_enum linex); +/* interrupt & flag functions */ /* get EXTI lines pending flag */ FlagStatus exti_flag_get(exti_line_enum linex); /* clear EXTI lines pending flag */ @@ -238,9 +273,5 @@ void exti_flag_clear(exti_line_enum linex); FlagStatus exti_interrupt_flag_get(exti_line_enum linex); /* clear EXTI lines pending flag */ void exti_interrupt_flag_clear(exti_line_enum linex); -/* EXTI software interrupt event enable */ -void exti_software_interrupt_enable(exti_line_enum linex); -/* EXTI software interrupt event disable */ -void exti_software_interrupt_disable(exti_line_enum linex); #endif /* GD32F4XX_EXTI_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_fmc.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_fmc.h index c3b360ab02..9b1b82c083 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_fmc.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_fmc.h @@ -1,13 +1,40 @@ /*! - \file gd32f4xx_fmc.h - \brief definitions for the FMC + \file gd32f4xx_fmc.h + \brief definitions for the FMC + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ + + #ifndef GD32F4XX_FMC_H #define GD32F4XX_FMC_H @@ -18,15 +45,15 @@ #define OB OB_BASE /*!< option byte base address */ /* registers definitions */ -#define FMC_WS REG32((FMC) + 0x00U) /*!< FMC wait state register */ -#define FMC_KEY REG32((FMC) + 0x04U) /*!< FMC unlock key register */ -#define FMC_OBKEY REG32((FMC) + 0x08U) /*!< FMC option byte unlock key register */ -#define FMC_STAT REG32((FMC) + 0x0CU) /*!< FMC status register */ -#define FMC_CTL REG32((FMC) + 0x10U) /*!< FMC control register */ -#define FMC_OBCTL0 REG32((FMC) + 0x14U) /*!< FMC option byte control register 0 */ -#define FMC_OBCTL1 REG32((FMC) + 0x18U) /*!< FMC option byte control register 1 */ -#define FMC_WSEN REG32((FMC) + 0xFCU) /*!< FMC wait state enable register */ -#define FMC_PID REG32((FMC) + 0x100U) /*!< FMC product ID register */ +#define FMC_WS REG32((FMC) + 0x0000U) /*!< FMC wait state register */ +#define FMC_KEY REG32((FMC) + 0x0004U) /*!< FMC unlock key register */ +#define FMC_OBKEY REG32((FMC) + 0x0008U) /*!< FMC option byte unlock key register */ +#define FMC_STAT REG32((FMC) + 0x000CU) /*!< FMC status register */ +#define FMC_CTL REG32((FMC) + 0x0010U) /*!< FMC control register */ +#define FMC_OBCTL0 REG32((FMC) + 0x0014U) /*!< FMC option byte control register 0 */ +#define FMC_OBCTL1 REG32((FMC) + 0x0018U) /*!< FMC option byte control register 1 */ +#define FMC_WSEN REG32((FMC) + 0x00FCU) /*!< FMC wait state enable register */ +#define FMC_PID REG32((FMC) + 0x0100U) /*!< FMC product ID register */ #define OB_WP1 REG32((OB) + 0x00000008U) /*!< option byte write protection 1 */ #define OB_USER REG32((OB) + 0x00010000U) /*!< option byte user value*/ @@ -98,7 +125,6 @@ typedef enum FMC_WPERR, /*!< erase/program protection error */ FMC_OPERR, /*!< operation error */ FMC_PGERR, /*!< program error */ - FMC_TOERR /*!< timeout error */ }fmc_state_enum; /* unlock key */ @@ -108,9 +134,6 @@ typedef enum #define OB_UNLOCK_KEY0 ((uint32_t)0x08192A3BU) /*!< ob unlock key 0 */ #define OB_UNLOCK_KEY1 ((uint32_t)0x4C5D6E7FU) /*!< ob unlock key 1 */ -/* FMC time out */ -#define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000) /*!< enable FMC error timeout */ - /* option byte write protection */ #define OB_LWP ((uint32_t)0x000000FFU) /*!< write protection low bits */ #define OB_HWP ((uint32_t)0x0000FF00U) /*!< write protection high bits */ @@ -146,7 +169,7 @@ typedef enum #define OB_BB_DISABLE OBCTL0_BB(0) /*!< boot from bank0 */ #define OB_BB_ENABLE OBCTL0_BB(1) /*!< boot from bank1 or bank0 if bank1 is void */ -/* option byte software/hardware free watch dog timer */ +/* option byte software/hardware free watch dog timer */ #define OBCTL0_NWDG_HW(regval) (BIT(5) & ((uint32_t)(regval))<< 5) #define OB_FWDGT_SW OBCTL0_NWDG_HW(1) /*!< software free watchdog */ #define OB_FWDGT_HW OBCTL0_NWDG_HW(0) /*!< hardware free watchdog */ @@ -179,19 +202,19 @@ typedef enum #define OB_WP_9 ((uint32_t)0x00000200U) /*!< erase/program protection of sector 9 */ #define OB_WP_10 ((uint32_t)0x00000400U) /*!< erase/program protection of sector 10 */ #define OB_WP_11 ((uint32_t)0x00000800U) /*!< erase/program protection of sector 11 */ -#define OB_WP_12 ((uint32_t)0x00000001U) /*!< erase/program protection of sector 12 */ -#define OB_WP_13 ((uint32_t)0x00000002U) /*!< erase/program protection of sector 13 */ -#define OB_WP_14 ((uint32_t)0x00000004U) /*!< erase/program protection of sector 14 */ -#define OB_WP_15 ((uint32_t)0x00000008U) /*!< erase/program protection of sector 15 */ -#define OB_WP_16 ((uint32_t)0x00000010U) /*!< erase/program protection of sector 16 */ -#define OB_WP_17 ((uint32_t)0x00000020U) /*!< erase/program protection of sector 17 */ -#define OB_WP_18 ((uint32_t)0x00000040U) /*!< erase/program protection of sector 18 */ -#define OB_WP_19 ((uint32_t)0x00000080U) /*!< erase/program protection of sector 19 */ -#define OB_WP_20 ((uint32_t)0x00000100U) /*!< erase/program protection of sector 20 */ -#define OB_WP_21 ((uint32_t)0x00000200U) /*!< erase/program protection of sector 21 */ -#define OB_WP_22 ((uint32_t)0x00000400U) /*!< erase/program protection of sector 22 */ -#define OB_WP_23_30 ((uint32_t)0x00000800U) /*!< erase/program protection of sector 23~30 */ -#define OB_WP_ALL ((uint32_t)0x00000FFFU) /*!< erase/program protection of all sectors */ +#define OB_WP_12 ((uint32_t)0x00010000U) /*!< erase/program protection of sector 12 */ +#define OB_WP_13 ((uint32_t)0x00020000U) /*!< erase/program protection of sector 13 */ +#define OB_WP_14 ((uint32_t)0x00040000U) /*!< erase/program protection of sector 14 */ +#define OB_WP_15 ((uint32_t)0x00080000U) /*!< erase/program protection of sector 15 */ +#define OB_WP_16 ((uint32_t)0x00100000U) /*!< erase/program protection of sector 16 */ +#define OB_WP_17 ((uint32_t)0x00200000U) /*!< erase/program protection of sector 17 */ +#define OB_WP_18 ((uint32_t)0x00400000U) /*!< erase/program protection of sector 18 */ +#define OB_WP_19 ((uint32_t)0x00800000U) /*!< erase/program protection of sector 19 */ +#define OB_WP_20 ((uint32_t)0x01000000U) /*!< erase/program protection of sector 20 */ +#define OB_WP_21 ((uint32_t)0x02000000U) /*!< erase/program protection of sector 21 */ +#define OB_WP_22 ((uint32_t)0x04000000U) /*!< erase/program protection of sector 22 */ +#define OB_WP_23_27 ((uint32_t)0x08000000U) /*!< erase/program protection of sector 23~27 */ +#define OB_WP_ALL ((uint32_t)0x0FFF0FFFU) /*!< erase/program protection of all sectors */ /* option bytes D-bus read protection */ #define OB_DRP_0 ((uint32_t)0x00000001U) /*!< D-bus read protection protection of sector 0 */ @@ -206,26 +229,25 @@ typedef enum #define OB_DRP_9 ((uint32_t)0x00000200U) /*!< D-bus read protection protection of sector 9 */ #define OB_DRP_10 ((uint32_t)0x00000400U) /*!< D-bus read protection protection of sector 10 */ #define OB_DRP_11 ((uint32_t)0x00000800U) /*!< D-bus read protection protection of sector 11 */ -#define OB_DRP_12 ((uint32_t)0x00000001U) /*!< D-bus read protection protection of sector 12 */ -#define OB_DRP_13 ((uint32_t)0x00000002U) /*!< D-bus read protection protection of sector 13 */ -#define OB_DRP_14 ((uint32_t)0x00000004U) /*!< D-bus read protection protection of sector 14 */ -#define OB_DRP_15 ((uint32_t)0x00000008U) /*!< D-bus read protection protection of sector 15 */ -#define OB_DRP_16 ((uint32_t)0x00000010U) /*!< D-bus read protection protection of sector 16 */ -#define OB_DRP_17 ((uint32_t)0x00000020U) /*!< D-bus read protection protection of sector 17 */ -#define OB_DRP_18 ((uint32_t)0x00000040U) /*!< D-bus read protection protection of sector 18 */ -#define OB_DRP_19 ((uint32_t)0x00000080U) /*!< D-bus read protection protection of sector 19 */ -#define OB_DRP_20 ((uint32_t)0x00000100U) /*!< D-bus read protection protection of sector 20 */ -#define OB_DRP_21 ((uint32_t)0x00000200U) /*!< D-bus read protection protection of sector 21 */ -#define OB_DRP_22 ((uint32_t)0x00000400U) /*!< D-bus read protection protection of sector 22 */ -#define OB_DRP_23_30 ((uint32_t)0x00000800U) /*!< D-bus read protection protection of sector 23~30 */ -#define OB_DRP_ALL ((uint32_t)0x00000FFFU) /*!< D-bus read protection protection of all sectors */ +#define OB_DRP_12 ((uint32_t)0x00010000U) /*!< D-bus read protection protection of sector 12 */ +#define OB_DRP_13 ((uint32_t)0x00020000U) /*!< D-bus read protection protection of sector 13 */ +#define OB_DRP_14 ((uint32_t)0x00040000U) /*!< D-bus read protection protection of sector 14 */ +#define OB_DRP_15 ((uint32_t)0x00080000U) /*!< D-bus read protection protection of sector 15 */ +#define OB_DRP_16 ((uint32_t)0x00100000U) /*!< D-bus read protection protection of sector 16 */ +#define OB_DRP_17 ((uint32_t)0x00200000U) /*!< D-bus read protection protection of sector 17 */ +#define OB_DRP_18 ((uint32_t)0x00400000U) /*!< D-bus read protection protection of sector 18 */ +#define OB_DRP_19 ((uint32_t)0x00800000U) /*!< D-bus read protection protection of sector 19 */ +#define OB_DRP_20 ((uint32_t)0x01000000U) /*!< D-bus read protection protection of sector 20 */ +#define OB_DRP_21 ((uint32_t)0x02000000U) /*!< D-bus read protection protection of sector 21 */ +#define OB_DRP_22 ((uint32_t)0x04000000U) /*!< D-bus read protection protection of sector 22 */ +#define OB_DRP_23_27 ((uint32_t)0x08000000U) /*!< D-bus read protection protection of sector 23~27 */ -/* double banks or single bank selection when flash size is 1M bytes */ +/* double banks or single bank selection when flash size is 1M bytes */ #define OBCTL0_DBS(regval) (BIT(30) & ((uint32_t)(regval)<<30)) #define OB_DBS_DISABLE OBCTL0_DBS(0) /*!< single bank when flash size is 1M bytes */ #define OB_DBS_ENABLE OBCTL0_DBS(1) /*!< double bank when flash size is 1M bytes */ -/* option bytes D-bus read protection mode */ +/* option bytes D-bus read protection mode */ #define OBCTL0_DRP(regval) (BIT(31) & ((uint32_t)(regval)<<31)) #define OB_DRP_DISABLE OBCTL0_DRP(0) /*!< the WPx bits used as erase/program protection of each sector */ #define OB_DRP_ENABLE OBCTL0_DRP(1) /*!< the WPx bits used as erase/program protection and D-bus read protection of each sector */ @@ -260,19 +282,17 @@ typedef enum #define CTL_SECTOR_NUMBER_21 CTL_SN(25) /*!< sector 21 */ #define CTL_SECTOR_NUMBER_22 CTL_SN(26) /*!< sector 22 */ #define CTL_SECTOR_NUMBER_23 CTL_SN(27) /*!< sector 23 */ -#define CTL_SECTOR_NUMBER_28 CTL_SN(28) /*!< sector 28 */ -#define CTL_SECTOR_NUMBER_29 CTL_SN(29) /*!< sector 29 */ -#define CTL_SECTOR_NUMBER_30 CTL_SN(30) /*!< sector 30 */ -/* FMC program size */ + +/* FMC program size */ #define CTL_PSZ(regval) (BITS(8,9) & ((uint32_t)(regval))<< 8) #define CTL_PSZ_BYTE CTL_PSZ(0) /*!< FMC program by byte access */ #define CTL_PSZ_HALF_WORD CTL_PSZ(1) /*!< FMC program by half-word access */ #define CTL_PSZ_WORD CTL_PSZ(2) /*!< FMC program by word access */ /* FMC interrupt enable */ -#define FMC_INTEN_END ((uint32_t)0x01000000U) /*!< enable FMC end of program interrupt */ -#define FMC_INTEN_ERR ((uint32_t)0x02000000U) /*!< enable FMC error interrupt */ +#define FMC_INT_END ((uint32_t)0x01000000U) /*!< enable FMC end of program interrupt */ +#define FMC_INT_ERR ((uint32_t)0x02000000U) /*!< enable FMC error interrupt */ /* FMC flags */ #define FMC_FLAG_END ((uint32_t)0x00000001U) /*!< FMC end of operation flag bit */ @@ -281,7 +301,7 @@ typedef enum #define FMC_FLAG_PGMERR ((uint32_t)0x00000040U) /*!< FMC program size not match error flag bit */ #define FMC_FLAG_PGSERR ((uint32_t)0x00000080U) /*!< FMC program sequence error flag bit */ #define FMC_FLAG_RDDERR ((uint32_t)0x00000100U) /*!< FMC read D-bus protection error flag bit */ -#define FMC_FLAG_BUSY ((uint32_t)0x00010000U) /*!< FMC busy flag */ +#define FMC_FLAG_BUSY ((uint32_t)0x00010000U) /*!< FMC busy flag */ /* function declarations */ /* FMC main memory programming functions */ @@ -313,25 +333,17 @@ void ob_unlock(void); void ob_lock(void); /* send option byte change command */ void ob_start(void); +/* erase option byte */ +void ob_erase(void); /* enable write protect */ -void ob_write_protection0_enable(uint32_t ob_wp); +void ob_write_protection_enable(uint32_t ob_wp); /* disable write protect */ -void ob_write_protection0_disable(uint32_t ob_wp); -/* enable write protect */ -void ob_write_protection1_enable(uint32_t ob_wp); -/* disable write protect */ -void ob_write_protection1_disable(uint32_t ob_wp); -/* configure the erase/program protection mode */ -void ob_drp_config(uint32_t ob_drp); -/* enable the erase/program protection mode */ -void ob_drp0_enable(uint32_t ob_drp); -/* disable the erase/program protection mode */ -void ob_drp0_disable(uint32_t ob_drp); -/* enable the erase/program protection mode */ -void ob_drp1_enable(uint32_t ob_drp); -/* disable the erase/program protection mode */ -void ob_drp1_disable(uint32_t ob_drp); -/* set the option byte security protection level */ +void ob_write_protection_disable(uint32_t ob_wp); +/* enable erase/program protection and D-bus read protection */ +void ob_drp_enable(uint32_t ob_drp); +/* disable erase/program protection and D-bus read protection */ +void ob_drp_disable(uint32_t ob_drp); +/* set the option byte security protection level */ void ob_security_protection_config(uint8_t ob_spc); /* write the FMC option byte user */ void ob_user_write(uint32_t ob_fwdgt, uint32_t ob_deepsleep, uint32_t ob_stdby); @@ -366,6 +378,6 @@ void fmc_flag_clear(uint32_t fmc_flag); /* return the FMC state */ fmc_state_enum fmc_state_get(void); /* check FMC ready or not */ -fmc_state_enum fmc_ready_wait(uint32_t count); +fmc_state_enum fmc_ready_wait(void); #endif /* GD32F4XX_FMC_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_fwdgt.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_fwdgt.h index b63efc9293..ebee04b637 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_fwdgt.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_fwdgt.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_fwdgt.h - \brief definitions for the FWDGT + \file gd32f4xx_fwdgt.h + \brief definitions for the FWDGT + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_FWDGT_H @@ -58,7 +83,13 @@ #define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */ #define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */ +/* FWDGT flag definitions */ +#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< FWDGT prescaler divider value update flag */ +#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< FWDGT counter reload value update flag */ + /* function declarations */ +/* enable write access to FWDGT_PSC and FWDGT_RLD */ +void fwdgt_write_enable(void); /* disable write access to FWDGT_PSC and FWDGT_RLD */ void fwdgt_write_disable(void); /* start the free watchdog timer counter */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_gpio.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_gpio.h index 257962d6de..81da899427 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_gpio.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_gpio.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_gpio.h - \brief definitions for the GPIO + \file gd32f4xx_gpio.h + \brief definitions for the GPIO + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_GPIO_H @@ -41,343 +66,343 @@ /* bits definitions */ /* GPIO_CTL */ -#define GPIO_CTL_CTL0 BITS(0,1) /*!< pin 0 configuration bits */ -#define GPIO_CTL_CTL1 BITS(2,3) /*!< pin 1 configuration bits */ -#define GPIO_CTL_CTL2 BITS(4,5) /*!< pin 2 configuration bits */ -#define GPIO_CTL_CTL3 BITS(6,7) /*!< pin 3 configuration bits */ -#define GPIO_CTL_CTL4 BITS(8,9) /*!< pin 4 configuration bits */ -#define GPIO_CTL_CTL5 BITS(10,11) /*!< pin 5 configuration bits */ -#define GPIO_CTL_CTL6 BITS(12,13) /*!< pin 6 configuration bits */ -#define GPIO_CTL_CTL7 BITS(14,15) /*!< pin 7 configuration bits */ -#define GPIO_CTL_CTL8 BITS(16,17) /*!< pin 8 configuration bits */ -#define GPIO_CTL_CTL9 BITS(18,19) /*!< pin 9 configuration bits */ -#define GPIO_CTL_CTL10 BITS(20,21) /*!< pin 10 configuration bits */ -#define GPIO_CTL_CTL11 BITS(22,23) /*!< pin 11 configuration bits */ -#define GPIO_CTL_CTL12 BITS(24,25) /*!< pin 12 configuration bits */ -#define GPIO_CTL_CTL13 BITS(26,27) /*!< pin 13 configuration bits */ -#define GPIO_CTL_CTL14 BITS(28,29) /*!< pin 14 configuration bits */ -#define GPIO_CTL_CTL15 BITS(30,31) /*!< pin 15 configuration bits */ +#define GPIO_CTL_CTL0 BITS(0,1) /*!< pin 0 configuration bits */ +#define GPIO_CTL_CTL1 BITS(2,3) /*!< pin 1 configuration bits */ +#define GPIO_CTL_CTL2 BITS(4,5) /*!< pin 2 configuration bits */ +#define GPIO_CTL_CTL3 BITS(6,7) /*!< pin 3 configuration bits */ +#define GPIO_CTL_CTL4 BITS(8,9) /*!< pin 4 configuration bits */ +#define GPIO_CTL_CTL5 BITS(10,11) /*!< pin 5 configuration bits */ +#define GPIO_CTL_CTL6 BITS(12,13) /*!< pin 6 configuration bits */ +#define GPIO_CTL_CTL7 BITS(14,15) /*!< pin 7 configuration bits */ +#define GPIO_CTL_CTL8 BITS(16,17) /*!< pin 8 configuration bits */ +#define GPIO_CTL_CTL9 BITS(18,19) /*!< pin 9 configuration bits */ +#define GPIO_CTL_CTL10 BITS(20,21) /*!< pin 10 configuration bits */ +#define GPIO_CTL_CTL11 BITS(22,23) /*!< pin 11 configuration bits */ +#define GPIO_CTL_CTL12 BITS(24,25) /*!< pin 12 configuration bits */ +#define GPIO_CTL_CTL13 BITS(26,27) /*!< pin 13 configuration bits */ +#define GPIO_CTL_CTL14 BITS(28,29) /*!< pin 14 configuration bits */ +#define GPIO_CTL_CTL15 BITS(30,31) /*!< pin 15 configuration bits */ /* GPIO_OMODE */ -#define GPIO_OMODE_OM0 BIT(0) /*!< pin 0 output mode bit */ -#define GPIO_OMODE_OM1 BIT(1) /*!< pin 1 output mode bit */ -#define GPIO_OMODE_OM2 BIT(2) /*!< pin 2 output mode bit */ -#define GPIO_OMODE_OM3 BIT(3) /*!< pin 3 output mode bit */ -#define GPIO_OMODE_OM4 BIT(4) /*!< pin 4 output mode bit */ -#define GPIO_OMODE_OM5 BIT(5) /*!< pin 5 output mode bit */ -#define GPIO_OMODE_OM6 BIT(6) /*!< pin 6 output mode bit */ -#define GPIO_OMODE_OM7 BIT(7) /*!< pin 7 output mode bit */ -#define GPIO_OMODE_OM8 BIT(8) /*!< pin 8 output mode bit */ -#define GPIO_OMODE_OM9 BIT(9) /*!< pin 9 output mode bit */ -#define GPIO_OMODE_OM10 BIT(10) /*!< pin 10 output mode bit */ -#define GPIO_OMODE_OM11 BIT(11) /*!< pin 11 output mode bit */ -#define GPIO_OMODE_OM12 BIT(12) /*!< pin 12 output mode bit */ -#define GPIO_OMODE_OM13 BIT(13) /*!< pin 13 output mode bit */ -#define GPIO_OMODE_OM14 BIT(14) /*!< pin 14 output mode bit */ -#define GPIO_OMODE_OM15 BIT(15) /*!< pin 15 output mode bit */ +#define GPIO_OMODE_OM0 BIT(0) /*!< pin 0 output mode bit */ +#define GPIO_OMODE_OM1 BIT(1) /*!< pin 1 output mode bit */ +#define GPIO_OMODE_OM2 BIT(2) /*!< pin 2 output mode bit */ +#define GPIO_OMODE_OM3 BIT(3) /*!< pin 3 output mode bit */ +#define GPIO_OMODE_OM4 BIT(4) /*!< pin 4 output mode bit */ +#define GPIO_OMODE_OM5 BIT(5) /*!< pin 5 output mode bit */ +#define GPIO_OMODE_OM6 BIT(6) /*!< pin 6 output mode bit */ +#define GPIO_OMODE_OM7 BIT(7) /*!< pin 7 output mode bit */ +#define GPIO_OMODE_OM8 BIT(8) /*!< pin 8 output mode bit */ +#define GPIO_OMODE_OM9 BIT(9) /*!< pin 9 output mode bit */ +#define GPIO_OMODE_OM10 BIT(10) /*!< pin 10 output mode bit */ +#define GPIO_OMODE_OM11 BIT(11) /*!< pin 11 output mode bit */ +#define GPIO_OMODE_OM12 BIT(12) /*!< pin 12 output mode bit */ +#define GPIO_OMODE_OM13 BIT(13) /*!< pin 13 output mode bit */ +#define GPIO_OMODE_OM14 BIT(14) /*!< pin 14 output mode bit */ +#define GPIO_OMODE_OM15 BIT(15) /*!< pin 15 output mode bit */ /* GPIO_OSPD */ -#define GPIO_OSPD_OSPD0 BITS(0,1) /*!< pin 0 output max speed bits */ -#define GPIO_OSPD_OSPD1 BITS(2,3) /*!< pin 1 output max speed bits */ -#define GPIO_OSPD_OSPD2 BITS(4,5) /*!< pin 2 output max speed bits */ -#define GPIO_OSPD_OSPD3 BITS(6,7) /*!< pin 3 output max speed bits */ -#define GPIO_OSPD_OSPD4 BITS(8,9) /*!< pin 4 output max speed bits */ -#define GPIO_OSPD_OSPD5 BITS(10,11) /*!< pin 5 output max speed bits */ -#define GPIO_OSPD_OSPD6 BITS(12,13) /*!< pin 6 output max speed bits */ -#define GPIO_OSPD_OSPD7 BITS(14,15) /*!< pin 7 output max speed bits */ -#define GPIO_OSPD_OSPD8 BITS(16,17) /*!< pin 8 output max speed bits */ -#define GPIO_OSPD_OSPD9 BITS(18,19) /*!< pin 9 output max speed bits */ -#define GPIO_OSPD_OSPD10 BITS(20,21) /*!< pin 10 output max speed bits */ -#define GPIO_OSPD_OSPD11 BITS(22,23) /*!< pin 11 output max speed bits */ -#define GPIO_OSPD_OSPD12 BITS(24,25) /*!< pin 12 output max speed bits */ -#define GPIO_OSPD_OSPD13 BITS(26,27) /*!< pin 13 output max speed bits */ -#define GPIO_OSPD_OSPD14 BITS(28,29) /*!< pin 14 output max speed bits */ -#define GPIO_OSPD_OSPD15 BITS(30,31) /*!< pin 15 output max speed bits */ +#define GPIO_OSPD_OSPD0 BITS(0,1) /*!< pin 0 output max speed bits */ +#define GPIO_OSPD_OSPD1 BITS(2,3) /*!< pin 1 output max speed bits */ +#define GPIO_OSPD_OSPD2 BITS(4,5) /*!< pin 2 output max speed bits */ +#define GPIO_OSPD_OSPD3 BITS(6,7) /*!< pin 3 output max speed bits */ +#define GPIO_OSPD_OSPD4 BITS(8,9) /*!< pin 4 output max speed bits */ +#define GPIO_OSPD_OSPD5 BITS(10,11) /*!< pin 5 output max speed bits */ +#define GPIO_OSPD_OSPD6 BITS(12,13) /*!< pin 6 output max speed bits */ +#define GPIO_OSPD_OSPD7 BITS(14,15) /*!< pin 7 output max speed bits */ +#define GPIO_OSPD_OSPD8 BITS(16,17) /*!< pin 8 output max speed bits */ +#define GPIO_OSPD_OSPD9 BITS(18,19) /*!< pin 9 output max speed bits */ +#define GPIO_OSPD_OSPD10 BITS(20,21) /*!< pin 10 output max speed bits */ +#define GPIO_OSPD_OSPD11 BITS(22,23) /*!< pin 11 output max speed bits */ +#define GPIO_OSPD_OSPD12 BITS(24,25) /*!< pin 12 output max speed bits */ +#define GPIO_OSPD_OSPD13 BITS(26,27) /*!< pin 13 output max speed bits */ +#define GPIO_OSPD_OSPD14 BITS(28,29) /*!< pin 14 output max speed bits */ +#define GPIO_OSPD_OSPD15 BITS(30,31) /*!< pin 15 output max speed bits */ /* GPIO_PUD */ -#define GPIO_PUD_PUD0 BITS(0,1) /*!< pin 0 pull-up or pull-down bits */ -#define GPIO_PUD_PUD1 BITS(2,3) /*!< pin 1 pull-up or pull-down bits */ -#define GPIO_PUD_PUD2 BITS(4,5) /*!< pin 2 pull-up or pull-down bits */ -#define GPIO_PUD_PUD3 BITS(6,7) /*!< pin 3 pull-up or pull-down bits */ -#define GPIO_PUD_PUD4 BITS(8,9) /*!< pin 4 pull-up or pull-down bits */ -#define GPIO_PUD_PUD5 BITS(10,11) /*!< pin 5 pull-up or pull-down bits */ -#define GPIO_PUD_PUD6 BITS(12,13) /*!< pin 6 pull-up or pull-down bits */ -#define GPIO_PUD_PUD7 BITS(14,15) /*!< pin 7 pull-up or pull-down bits */ -#define GPIO_PUD_PUD8 BITS(16,17) /*!< pin 8 pull-up or pull-down bits */ -#define GPIO_PUD_PUD9 BITS(18,19) /*!< pin 9 pull-up or pull-down bits */ -#define GPIO_PUD_PUD10 BITS(20,21) /*!< pin 10 pull-up or pull-down bits */ -#define GPIO_PUD_PUD11 BITS(22,23) /*!< pin 11 pull-up or pull-down bits */ -#define GPIO_PUD_PUD12 BITS(24,25) /*!< pin 12 pull-up or pull-down bits */ -#define GPIO_PUD_PUD13 BITS(26,27) /*!< pin 13 pull-up or pull-down bits */ -#define GPIO_PUD_PUD14 BITS(28,29) /*!< pin 14 pull-up or pull-down bits */ -#define GPIO_PUD_PUD15 BITS(30,31) /*!< pin 15 pull-up or pull-down bits */ +#define GPIO_PUD_PUD0 BITS(0,1) /*!< pin 0 pull-up or pull-down bits */ +#define GPIO_PUD_PUD1 BITS(2,3) /*!< pin 1 pull-up or pull-down bits */ +#define GPIO_PUD_PUD2 BITS(4,5) /*!< pin 2 pull-up or pull-down bits */ +#define GPIO_PUD_PUD3 BITS(6,7) /*!< pin 3 pull-up or pull-down bits */ +#define GPIO_PUD_PUD4 BITS(8,9) /*!< pin 4 pull-up or pull-down bits */ +#define GPIO_PUD_PUD5 BITS(10,11) /*!< pin 5 pull-up or pull-down bits */ +#define GPIO_PUD_PUD6 BITS(12,13) /*!< pin 6 pull-up or pull-down bits */ +#define GPIO_PUD_PUD7 BITS(14,15) /*!< pin 7 pull-up or pull-down bits */ +#define GPIO_PUD_PUD8 BITS(16,17) /*!< pin 8 pull-up or pull-down bits */ +#define GPIO_PUD_PUD9 BITS(18,19) /*!< pin 9 pull-up or pull-down bits */ +#define GPIO_PUD_PUD10 BITS(20,21) /*!< pin 10 pull-up or pull-down bits */ +#define GPIO_PUD_PUD11 BITS(22,23) /*!< pin 11 pull-up or pull-down bits */ +#define GPIO_PUD_PUD12 BITS(24,25) /*!< pin 12 pull-up or pull-down bits */ +#define GPIO_PUD_PUD13 BITS(26,27) /*!< pin 13 pull-up or pull-down bits */ +#define GPIO_PUD_PUD14 BITS(28,29) /*!< pin 14 pull-up or pull-down bits */ +#define GPIO_PUD_PUD15 BITS(30,31) /*!< pin 15 pull-up or pull-down bits */ /* GPIO_ISTAT */ -#define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */ -#define GPIO_ISTAT_ISTAT1 BIT(1) /*!< pin 1 input status */ -#define GPIO_ISTAT_ISTAT2 BIT(2) /*!< pin 2 input status */ -#define GPIO_ISTAT_ISTAT3 BIT(3) /*!< pin 3 input status */ -#define GPIO_ISTAT_ISTAT4 BIT(4) /*!< pin 4 input status */ -#define GPIO_ISTAT_ISTAT5 BIT(5) /*!< pin 5 input status */ -#define GPIO_ISTAT_ISTAT6 BIT(6) /*!< pin 6 input status */ -#define GPIO_ISTAT_ISTAT7 BIT(7) /*!< pin 7 input status */ -#define GPIO_ISTAT_ISTAT8 BIT(8) /*!< pin 8 input status */ -#define GPIO_ISTAT_ISTAT9 BIT(9) /*!< pin 9 input status */ -#define GPIO_ISTAT_ISTAT10 BIT(10) /*!< pin 10 input status */ -#define GPIO_ISTAT_ISTAT11 BIT(11) /*!< pin 11 input status */ -#define GPIO_ISTAT_ISTAT12 BIT(12) /*!< pin 12 input status */ -#define GPIO_ISTAT_ISTAT13 BIT(13) /*!< pin 13 input status */ -#define GPIO_ISTAT_ISTAT14 BIT(14) /*!< pin 14 input status */ -#define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */ +#define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */ +#define GPIO_ISTAT_ISTAT1 BIT(1) /*!< pin 1 input status */ +#define GPIO_ISTAT_ISTAT2 BIT(2) /*!< pin 2 input status */ +#define GPIO_ISTAT_ISTAT3 BIT(3) /*!< pin 3 input status */ +#define GPIO_ISTAT_ISTAT4 BIT(4) /*!< pin 4 input status */ +#define GPIO_ISTAT_ISTAT5 BIT(5) /*!< pin 5 input status */ +#define GPIO_ISTAT_ISTAT6 BIT(6) /*!< pin 6 input status */ +#define GPIO_ISTAT_ISTAT7 BIT(7) /*!< pin 7 input status */ +#define GPIO_ISTAT_ISTAT8 BIT(8) /*!< pin 8 input status */ +#define GPIO_ISTAT_ISTAT9 BIT(9) /*!< pin 9 input status */ +#define GPIO_ISTAT_ISTAT10 BIT(10) /*!< pin 10 input status */ +#define GPIO_ISTAT_ISTAT11 BIT(11) /*!< pin 11 input status */ +#define GPIO_ISTAT_ISTAT12 BIT(12) /*!< pin 12 input status */ +#define GPIO_ISTAT_ISTAT13 BIT(13) /*!< pin 13 input status */ +#define GPIO_ISTAT_ISTAT14 BIT(14) /*!< pin 14 input status */ +#define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */ /* GPIO_OCTL */ -#define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output bit */ -#define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output bit */ -#define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output bit */ -#define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output bit */ -#define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output bit */ -#define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output bit */ -#define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output bit */ -#define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output bit */ -#define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output bit */ -#define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output bit */ -#define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output bit */ -#define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output bit */ -#define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output bit */ -#define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output bit */ -#define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output bit */ -#define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output bit */ +#define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output bit */ +#define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output bit */ +#define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output bit */ +#define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output bit */ +#define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output bit */ +#define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output bit */ +#define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output bit */ +#define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output bit */ +#define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output bit */ +#define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output bit */ +#define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output bit */ +#define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output bit */ +#define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output bit */ +#define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output bit */ +#define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output bit */ +#define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output bit */ /* GPIO_BOP */ -#define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */ -#define GPIO_BOP_BOP1 BIT(1) /*!< pin 1 set bit */ -#define GPIO_BOP_BOP2 BIT(2) /*!< pin 2 set bit */ -#define GPIO_BOP_BOP3 BIT(3) /*!< pin 3 set bit */ -#define GPIO_BOP_BOP4 BIT(4) /*!< pin 4 set bit */ -#define GPIO_BOP_BOP5 BIT(5) /*!< pin 5 set bit */ -#define GPIO_BOP_BOP6 BIT(6) /*!< pin 6 set bit */ -#define GPIO_BOP_BOP7 BIT(7) /*!< pin 7 set bit */ -#define GPIO_BOP_BOP8 BIT(8) /*!< pin 8 set bit */ -#define GPIO_BOP_BOP9 BIT(9) /*!< pin 9 set bit */ -#define GPIO_BOP_BOP10 BIT(10) /*!< pin 10 set bit */ -#define GPIO_BOP_BOP11 BIT(11) /*!< pin 11 set bit */ -#define GPIO_BOP_BOP12 BIT(12) /*!< pin 12 set bit */ -#define GPIO_BOP_BOP13 BIT(13) /*!< pin 13 set bit */ -#define GPIO_BOP_BOP14 BIT(14) /*!< pin 14 set bit */ -#define GPIO_BOP_BOP15 BIT(15) /*!< pin 15 set bit */ -#define GPIO_BOP_CR0 BIT(16) /*!< pin 0 clear bit */ -#define GPIO_BOP_CR1 BIT(17) /*!< pin 1 clear bit */ -#define GPIO_BOP_CR2 BIT(18) /*!< pin 2 clear bit */ -#define GPIO_BOP_CR3 BIT(19) /*!< pin 3 clear bit */ -#define GPIO_BOP_CR4 BIT(20) /*!< pin 4 clear bit */ -#define GPIO_BOP_CR5 BIT(21) /*!< pin 5 clear bit */ -#define GPIO_BOP_CR6 BIT(22) /*!< pin 6 clear bit */ -#define GPIO_BOP_CR7 BIT(23) /*!< pin 7 clear bit */ -#define GPIO_BOP_CR8 BIT(24) /*!< pin 8 clear bit */ -#define GPIO_BOP_CR9 BIT(25) /*!< pin 9 clear bit */ -#define GPIO_BOP_CR10 BIT(26) /*!< pin 10 clear bit */ -#define GPIO_BOP_CR11 BIT(27) /*!< pin 11 clear bit */ -#define GPIO_BOP_CR12 BIT(28) /*!< pin 12 clear bit */ -#define GPIO_BOP_CR13 BIT(29) /*!< pin 13 clear bit */ -#define GPIO_BOP_CR14 BIT(30) /*!< pin 14 clear bit */ -#define GPIO_BOP_CR15 BIT(31) /*!< pin 15 clear bit */ +#define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */ +#define GPIO_BOP_BOP1 BIT(1) /*!< pin 1 set bit */ +#define GPIO_BOP_BOP2 BIT(2) /*!< pin 2 set bit */ +#define GPIO_BOP_BOP3 BIT(3) /*!< pin 3 set bit */ +#define GPIO_BOP_BOP4 BIT(4) /*!< pin 4 set bit */ +#define GPIO_BOP_BOP5 BIT(5) /*!< pin 5 set bit */ +#define GPIO_BOP_BOP6 BIT(6) /*!< pin 6 set bit */ +#define GPIO_BOP_BOP7 BIT(7) /*!< pin 7 set bit */ +#define GPIO_BOP_BOP8 BIT(8) /*!< pin 8 set bit */ +#define GPIO_BOP_BOP9 BIT(9) /*!< pin 9 set bit */ +#define GPIO_BOP_BOP10 BIT(10) /*!< pin 10 set bit */ +#define GPIO_BOP_BOP11 BIT(11) /*!< pin 11 set bit */ +#define GPIO_BOP_BOP12 BIT(12) /*!< pin 12 set bit */ +#define GPIO_BOP_BOP13 BIT(13) /*!< pin 13 set bit */ +#define GPIO_BOP_BOP14 BIT(14) /*!< pin 14 set bit */ +#define GPIO_BOP_BOP15 BIT(15) /*!< pin 15 set bit */ +#define GPIO_BOP_CR0 BIT(16) /*!< pin 0 clear bit */ +#define GPIO_BOP_CR1 BIT(17) /*!< pin 1 clear bit */ +#define GPIO_BOP_CR2 BIT(18) /*!< pin 2 clear bit */ +#define GPIO_BOP_CR3 BIT(19) /*!< pin 3 clear bit */ +#define GPIO_BOP_CR4 BIT(20) /*!< pin 4 clear bit */ +#define GPIO_BOP_CR5 BIT(21) /*!< pin 5 clear bit */ +#define GPIO_BOP_CR6 BIT(22) /*!< pin 6 clear bit */ +#define GPIO_BOP_CR7 BIT(23) /*!< pin 7 clear bit */ +#define GPIO_BOP_CR8 BIT(24) /*!< pin 8 clear bit */ +#define GPIO_BOP_CR9 BIT(25) /*!< pin 9 clear bit */ +#define GPIO_BOP_CR10 BIT(26) /*!< pin 10 clear bit */ +#define GPIO_BOP_CR11 BIT(27) /*!< pin 11 clear bit */ +#define GPIO_BOP_CR12 BIT(28) /*!< pin 12 clear bit */ +#define GPIO_BOP_CR13 BIT(29) /*!< pin 13 clear bit */ +#define GPIO_BOP_CR14 BIT(30) /*!< pin 14 clear bit */ +#define GPIO_BOP_CR15 BIT(31) /*!< pin 15 clear bit */ /* GPIO_LOCK */ -#define GPIO_LOCK_LK0 BIT(0) /*!< pin 0 lock bit */ -#define GPIO_LOCK_LK1 BIT(1) /*!< pin 1 lock bit */ -#define GPIO_LOCK_LK2 BIT(2) /*!< pin 2 lock bit */ -#define GPIO_LOCK_LK3 BIT(3) /*!< pin 3 lock bit */ -#define GPIO_LOCK_LK4 BIT(4) /*!< pin 4 lock bit */ -#define GPIO_LOCK_LK5 BIT(5) /*!< pin 5 lock bit */ -#define GPIO_LOCK_LK6 BIT(6) /*!< pin 6 lock bit */ -#define GPIO_LOCK_LK7 BIT(7) /*!< pin 7 lock bit */ -#define GPIO_LOCK_LK8 BIT(8) /*!< pin 8 lock bit */ -#define GPIO_LOCK_LK9 BIT(9) /*!< pin 9 lock bit */ -#define GPIO_LOCK_LK10 BIT(10) /*!< pin 10 lock bit */ -#define GPIO_LOCK_LK11 BIT(11) /*!< pin 11 lock bit */ -#define GPIO_LOCK_LK12 BIT(12) /*!< pin 12 lock bit */ -#define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */ -#define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */ -#define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */ -#define GPIO_LOCK_LKK BIT(16) /*!< pin sequence lock key */ +#define GPIO_LOCK_LK0 BIT(0) /*!< pin 0 lock bit */ +#define GPIO_LOCK_LK1 BIT(1) /*!< pin 1 lock bit */ +#define GPIO_LOCK_LK2 BIT(2) /*!< pin 2 lock bit */ +#define GPIO_LOCK_LK3 BIT(3) /*!< pin 3 lock bit */ +#define GPIO_LOCK_LK4 BIT(4) /*!< pin 4 lock bit */ +#define GPIO_LOCK_LK5 BIT(5) /*!< pin 5 lock bit */ +#define GPIO_LOCK_LK6 BIT(6) /*!< pin 6 lock bit */ +#define GPIO_LOCK_LK7 BIT(7) /*!< pin 7 lock bit */ +#define GPIO_LOCK_LK8 BIT(8) /*!< pin 8 lock bit */ +#define GPIO_LOCK_LK9 BIT(9) /*!< pin 9 lock bit */ +#define GPIO_LOCK_LK10 BIT(10) /*!< pin 10 lock bit */ +#define GPIO_LOCK_LK11 BIT(11) /*!< pin 11 lock bit */ +#define GPIO_LOCK_LK12 BIT(12) /*!< pin 12 lock bit */ +#define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */ +#define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */ +#define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */ +#define GPIO_LOCK_LKK BIT(16) /*!< pin sequence lock key */ /* GPIO_AFSEL0 */ -#define GPIO_AFSEL0_SEL0 BITS(0,3) /*!< pin 0 alternate function selected */ -#define GPIO_AFSEL0_SEL1 BITS(4,7) /*!< pin 1 alternate function selected */ -#define GPIO_AFSEL0_SEL2 BITS(8,11) /*!< pin 2 alternate function selected */ -#define GPIO_AFSEL0_SEL3 BITS(12,15) /*!< pin 3 alternate function selected */ -#define GPIO_AFSEL0_SEL4 BITS(16,19) /*!< pin 4 alternate function selected */ -#define GPIO_AFSEL0_SEL5 BITS(20,23) /*!< pin 5 alternate function selected */ -#define GPIO_AFSEL0_SEL6 BITS(24,27) /*!< pin 6 alternate function selected */ -#define GPIO_AFSEL0_SEL7 BITS(28,31) /*!< pin 7 alternate function selected */ +#define GPIO_AFSEL0_SEL0 BITS(0,3) /*!< pin 0 alternate function selected */ +#define GPIO_AFSEL0_SEL1 BITS(4,7) /*!< pin 1 alternate function selected */ +#define GPIO_AFSEL0_SEL2 BITS(8,11) /*!< pin 2 alternate function selected */ +#define GPIO_AFSEL0_SEL3 BITS(12,15) /*!< pin 3 alternate function selected */ +#define GPIO_AFSEL0_SEL4 BITS(16,19) /*!< pin 4 alternate function selected */ +#define GPIO_AFSEL0_SEL5 BITS(20,23) /*!< pin 5 alternate function selected */ +#define GPIO_AFSEL0_SEL6 BITS(24,27) /*!< pin 6 alternate function selected */ +#define GPIO_AFSEL0_SEL7 BITS(28,31) /*!< pin 7 alternate function selected */ /* GPIO_AFSEL1 */ -#define GPIO_AFSEL1_SEL8 BITS(0,3) /*!< pin 8 alternate function selected */ -#define GPIO_AFSEL1_SEL9 BITS(4,7) /*!< pin 9 alternate function selected */ -#define GPIO_AFSEL1_SEL10 BITS(8,11) /*!< pin 10 alternate function selected */ -#define GPIO_AFSEL1_SEL11 BITS(12,15) /*!< pin 11 alternate function selected */ -#define GPIO_AFSEL1_SEL12 BITS(16,19) /*!< pin 12 alternate function selected */ -#define GPIO_AFSEL1_SEL13 BITS(20,23) /*!< pin 13 alternate function selected */ -#define GPIO_AFSEL1_SEL14 BITS(24,27) /*!< pin 14 alternate function selected */ -#define GPIO_AFSEL1_SEL15 BITS(28,31) /*!< pin 15 alternate function selected */ +#define GPIO_AFSEL1_SEL8 BITS(0,3) /*!< pin 8 alternate function selected */ +#define GPIO_AFSEL1_SEL9 BITS(4,7) /*!< pin 9 alternate function selected */ +#define GPIO_AFSEL1_SEL10 BITS(8,11) /*!< pin 10 alternate function selected */ +#define GPIO_AFSEL1_SEL11 BITS(12,15) /*!< pin 11 alternate function selected */ +#define GPIO_AFSEL1_SEL12 BITS(16,19) /*!< pin 12 alternate function selected */ +#define GPIO_AFSEL1_SEL13 BITS(20,23) /*!< pin 13 alternate function selected */ +#define GPIO_AFSEL1_SEL14 BITS(24,27) /*!< pin 14 alternate function selected */ +#define GPIO_AFSEL1_SEL15 BITS(28,31) /*!< pin 15 alternate function selected */ /* GPIO_BC */ -#define GPIO_BC_CR0 BIT(0) /*!< pin 0 clear bit */ -#define GPIO_BC_CR1 BIT(1) /*!< pin 1 clear bit */ -#define GPIO_BC_CR2 BIT(2) /*!< pin 2 clear bit */ -#define GPIO_BC_CR3 BIT(3) /*!< pin 3 clear bit */ -#define GPIO_BC_CR4 BIT(4) /*!< pin 4 clear bit */ -#define GPIO_BC_CR5 BIT(5) /*!< pin 5 clear bit */ -#define GPIO_BC_CR6 BIT(6) /*!< pin 6 clear bit */ -#define GPIO_BC_CR7 BIT(7) /*!< pin 7 clear bit */ -#define GPIO_BC_CR8 BIT(8) /*!< pin 8 clear bit */ -#define GPIO_BC_CR9 BIT(9) /*!< pin 9 clear bit */ -#define GPIO_BC_CR10 BIT(10) /*!< pin 10 clear bit */ -#define GPIO_BC_CR11 BIT(11) /*!< pin 11 clear bit */ -#define GPIO_BC_CR12 BIT(12) /*!< pin 12 clear bit */ -#define GPIO_BC_CR13 BIT(13) /*!< pin 13 clear bit */ -#define GPIO_BC_CR14 BIT(14) /*!< pin 14 clear bit */ -#define GPIO_BC_CR15 BIT(15) /*!< pin 15 clear bit */ +#define GPIO_BC_CR0 BIT(0) /*!< pin 0 clear bit */ +#define GPIO_BC_CR1 BIT(1) /*!< pin 1 clear bit */ +#define GPIO_BC_CR2 BIT(2) /*!< pin 2 clear bit */ +#define GPIO_BC_CR3 BIT(3) /*!< pin 3 clear bit */ +#define GPIO_BC_CR4 BIT(4) /*!< pin 4 clear bit */ +#define GPIO_BC_CR5 BIT(5) /*!< pin 5 clear bit */ +#define GPIO_BC_CR6 BIT(6) /*!< pin 6 clear bit */ +#define GPIO_BC_CR7 BIT(7) /*!< pin 7 clear bit */ +#define GPIO_BC_CR8 BIT(8) /*!< pin 8 clear bit */ +#define GPIO_BC_CR9 BIT(9) /*!< pin 9 clear bit */ +#define GPIO_BC_CR10 BIT(10) /*!< pin 10 clear bit */ +#define GPIO_BC_CR11 BIT(11) /*!< pin 11 clear bit */ +#define GPIO_BC_CR12 BIT(12) /*!< pin 12 clear bit */ +#define GPIO_BC_CR13 BIT(13) /*!< pin 13 clear bit */ +#define GPIO_BC_CR14 BIT(14) /*!< pin 14 clear bit */ +#define GPIO_BC_CR15 BIT(15) /*!< pin 15 clear bit */ /* GPIO_TG */ -#define GPIO_TG_TG0 BIT(0) /*!< pin 0 toggle bit */ -#define GPIO_TG_TG1 BIT(1) /*!< pin 1 toggle bit */ -#define GPIO_TG_TG2 BIT(2) /*!< pin 2 toggle bit */ -#define GPIO_TG_TG3 BIT(3) /*!< pin 3 toggle bit */ -#define GPIO_TG_TG4 BIT(4) /*!< pin 4 toggle bit */ -#define GPIO_TG_TG5 BIT(5) /*!< pin 5 toggle bit */ -#define GPIO_TG_TG6 BIT(6) /*!< pin 6 toggle bit */ -#define GPIO_TG_TG7 BIT(7) /*!< pin 7 toggle bit */ -#define GPIO_TG_TG8 BIT(8) /*!< pin 8 toggle bit */ -#define GPIO_TG_TG9 BIT(9) /*!< pin 9 toggle bit */ -#define GPIO_TG_TG10 BIT(10) /*!< pin 10 toggle bit */ -#define GPIO_TG_TG11 BIT(11) /*!< pin 11 toggle bit */ -#define GPIO_TG_TG12 BIT(12) /*!< pin 12 toggle bit */ -#define GPIO_TG_TG13 BIT(13) /*!< pin 13 toggle bit */ -#define GPIO_TG_TG14 BIT(14) /*!< pin 14 toggle bit */ -#define GPIO_TG_TG15 BIT(15) /*!< pin 15 toggle bit */ +#define GPIO_TG_TG0 BIT(0) /*!< pin 0 toggle bit */ +#define GPIO_TG_TG1 BIT(1) /*!< pin 1 toggle bit */ +#define GPIO_TG_TG2 BIT(2) /*!< pin 2 toggle bit */ +#define GPIO_TG_TG3 BIT(3) /*!< pin 3 toggle bit */ +#define GPIO_TG_TG4 BIT(4) /*!< pin 4 toggle bit */ +#define GPIO_TG_TG5 BIT(5) /*!< pin 5 toggle bit */ +#define GPIO_TG_TG6 BIT(6) /*!< pin 6 toggle bit */ +#define GPIO_TG_TG7 BIT(7) /*!< pin 7 toggle bit */ +#define GPIO_TG_TG8 BIT(8) /*!< pin 8 toggle bit */ +#define GPIO_TG_TG9 BIT(9) /*!< pin 9 toggle bit */ +#define GPIO_TG_TG10 BIT(10) /*!< pin 10 toggle bit */ +#define GPIO_TG_TG11 BIT(11) /*!< pin 11 toggle bit */ +#define GPIO_TG_TG12 BIT(12) /*!< pin 12 toggle bit */ +#define GPIO_TG_TG13 BIT(13) /*!< pin 13 toggle bit */ +#define GPIO_TG_TG14 BIT(14) /*!< pin 14 toggle bit */ +#define GPIO_TG_TG15 BIT(15) /*!< pin 15 toggle bit */ /* constants definitions */ typedef FlagStatus bit_status; /* output mode definitions */ #define CTL_CLTR(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define GPIO_MODE_INPUT CTL_CLTR(0) /*!< input mode */ -#define GPIO_MODE_OUTPUT CTL_CLTR(1) /*!< output mode */ -#define GPIO_MODE_AF CTL_CLTR(2) /*!< alternate function mode */ -#define GPIO_MODE_ANALOG CTL_CLTR(3) /*!< analog mode */ +#define GPIO_MODE_INPUT CTL_CLTR(0) /*!< input mode */ +#define GPIO_MODE_OUTPUT CTL_CLTR(1) /*!< output mode */ +#define GPIO_MODE_AF CTL_CLTR(2) /*!< alternate function mode */ +#define GPIO_MODE_ANALOG CTL_CLTR(3) /*!< analog mode */ -/* pull up pull down definitions */ +/* pull-up/ pull-down definitions */ #define PUD_PUPD(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define GPIO_PUPD_NONE PUD_PUPD(0) /*!< without weak pull-up and pull-down resistors */ -#define GPIO_PUPD_PULLUP PUD_PUPD(1) /*!< with weak pull-up resistor */ -#define GPIO_PUPD_PULLDOWN PUD_PUPD(2) /*!< with weak pull-down resistor */ +#define GPIO_PUPD_NONE PUD_PUPD(0) /*!< floating mode, no pull-up and pull-down resistors */ +#define GPIO_PUPD_PULLUP PUD_PUPD(1) /*!< with pull-up resistor */ +#define GPIO_PUPD_PULLDOWN PUD_PUPD(2) /*!< with pull-down resistor */ -/* gpio pin definitions */ -#define GPIO_PIN_0 BIT(0) /*!< GPIO pin 0 */ -#define GPIO_PIN_1 BIT(1) /*!< GPIO pin 1 */ -#define GPIO_PIN_2 BIT(2) /*!< GPIO pin 2 */ -#define GPIO_PIN_3 BIT(3) /*!< GPIO pin 3 */ -#define GPIO_PIN_4 BIT(4) /*!< GPIO pin 4 */ -#define GPIO_PIN_5 BIT(5) /*!< GPIO pin 5 */ -#define GPIO_PIN_6 BIT(6) /*!< GPIO pin 6 */ -#define GPIO_PIN_7 BIT(7) /*!< GPIO pin 7 */ -#define GPIO_PIN_8 BIT(8) /*!< GPIO pin 8 */ -#define GPIO_PIN_9 BIT(9) /*!< GPIO pin 9 */ -#define GPIO_PIN_10 BIT(10) /*!< GPIO pin 10 */ -#define GPIO_PIN_11 BIT(11) /*!< GPIO pin 11 */ -#define GPIO_PIN_12 BIT(12) /*!< GPIO pin 12 */ -#define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */ -#define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */ -#define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */ -#define GPIO_PIN_ALL ((uint32_t)(0xFFFF)) /*!< GPIO pin all */ +/* GPIO pin definitions */ +#define GPIO_PIN_0 BIT(0) /*!< GPIO pin 0 */ +#define GPIO_PIN_1 BIT(1) /*!< GPIO pin 1 */ +#define GPIO_PIN_2 BIT(2) /*!< GPIO pin 2 */ +#define GPIO_PIN_3 BIT(3) /*!< GPIO pin 3 */ +#define GPIO_PIN_4 BIT(4) /*!< GPIO pin 4 */ +#define GPIO_PIN_5 BIT(5) /*!< GPIO pin 5 */ +#define GPIO_PIN_6 BIT(6) /*!< GPIO pin 6 */ +#define GPIO_PIN_7 BIT(7) /*!< GPIO pin 7 */ +#define GPIO_PIN_8 BIT(8) /*!< GPIO pin 8 */ +#define GPIO_PIN_9 BIT(9) /*!< GPIO pin 9 */ +#define GPIO_PIN_10 BIT(10) /*!< GPIO pin 10 */ +#define GPIO_PIN_11 BIT(11) /*!< GPIO pin 11 */ +#define GPIO_PIN_12 BIT(12) /*!< GPIO pin 12 */ +#define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */ +#define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */ +#define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */ +#define GPIO_PIN_ALL BITS(0,15) /*!< GPIO pin all */ -/* gpio ctlr values */ +/* GPIO mode configuration values */ #define GPIO_MODE_SET(n, mode) ((uint32_t)((uint32_t)(mode) << (2U * (n)))) #define GPIO_MODE_MASK(n) (0x3U << (2U * (n))) -/* gpio pull up pull down values */ +/* GPIO pull-up/ pull-down values */ #define GPIO_PUPD_SET(n, pupd) ((uint32_t)((uint32_t)(pupd) << (2U * (n)))) #define GPIO_PUPD_MASK(n) (0x3U << (2U * (n))) -/* gpio output speed values */ +/* GPIO output speed values */ #define GPIO_OSPEED_SET(n, speed) ((uint32_t)((uint32_t)(speed) << (2U * (n)))) #define GPIO_OSPEED_MASK(n) (0x3U << (2U * (n))) -/* gpio output type */ -#define GPIO_OTYPE_PP ((uint8_t)(0x00)) /*!< push pull mode */ -#define GPIO_OTYPE_OD ((uint8_t)(0x01)) /*!< open drain mode */ +/* GPIO output type */ +#define GPIO_OTYPE_PP ((uint8_t)(0x00U)) /*!< push pull mode */ +#define GPIO_OTYPE_OD ((uint8_t)(0x01U)) /*!< open drain mode */ -/* gpio output max speed level */ +/* GPIO output max speed level */ #define OSPD_OSPD(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define GPIO_OSPEED_LEVEL0 OSPD_OSPD(0) /*!< output max speed level 0 */ -#define GPIO_OSPEED_LEVEL1 OSPD_OSPD(1) /*!< output max speed level 1 */ -#define GPIO_OSPEED_LEVEL2 OSPD_OSPD(2) /*!< output max speed level 2 */ -#define GPIO_OSPEED_LEVEL3 OSPD_OSPD(3) /*!< output max speed level 3 */ +#define GPIO_OSPEED_LEVEL0 OSPD_OSPD(0) /*!< output max speed level 0 */ +#define GPIO_OSPEED_LEVEL1 OSPD_OSPD(1) /*!< output max speed level 1 */ +#define GPIO_OSPEED_LEVEL2 OSPD_OSPD(2) /*!< output max speed level 2 */ +#define GPIO_OSPEED_LEVEL3 OSPD_OSPD(3) /*!< output max speed level 3 */ -/* gpio output max speed value */ -#define GPIO_OSPEED_2MHZ GPIO_OSPEED_LEVEL0 /*!< output max speed 2M */ -#define GPIO_OSPEED_25MHZ GPIO_OSPEED_LEVEL1 /*!< output max speed 25M */ -#define GPIO_OSPEED_50MHZ GPIO_OSPEED_LEVEL2 /*!< output max speed 50M */ -#define GPIO_OSPEED_200MHZ GPIO_OSPEED_LEVEL3 /*!< output max speed 200M */ +/* GPIO output max speed value */ +#define GPIO_OSPEED_2MHZ GPIO_OSPEED_LEVEL0 /*!< output max speed 2MHz */ +#define GPIO_OSPEED_25MHZ GPIO_OSPEED_LEVEL1 /*!< output max speed 25MHz */ +#define GPIO_OSPEED_50MHZ GPIO_OSPEED_LEVEL2 /*!< output max speed 50MHz */ +#define GPIO_OSPEED_200MHZ GPIO_OSPEED_LEVEL3 /*!< output max speed 200MHz */ -/* gpio alternate function values */ +/* GPIO alternate function values */ #define GPIO_AFR_SET(n, af) ((uint32_t)((uint32_t)(af) << (4U * (n)))) #define GPIO_AFR_MASK(n) (0xFU << (4U * (n))) - -/* gpio alternate function */ -#define AF(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) -#define GPIO_AF_0 AF(0) /*!< alternate function selected 0 */ -#define GPIO_AF_1 AF(1) /*!< alternate function selected 1 */ -#define GPIO_AF_2 AF(2) /*!< alternate function selected 2 */ -#define GPIO_AF_3 AF(3) /*!< alternate function selected 3 */ -#define GPIO_AF_4 AF(4) /*!< alternate function selected 4 */ -#define GPIO_AF_5 AF(5) /*!< alternate function selected 5 */ -#define GPIO_AF_6 AF(6) /*!< alternate function selected 6 */ -#define GPIO_AF_7 AF(7) /*!< alternate function selected 7 */ -#define GPIO_AF_8 AF(8) /*!< alternate function selected 8 */ -#define GPIO_AF_9 AF(9) /*!< alternate function selected 9 */ -#define GPIO_AF_10 AF(10) /*!< alternate function selected 10 */ -#define GPIO_AF_11 AF(11) /*!< alternate function selected 11 */ -#define GPIO_AF_12 AF(12) /*!< alternate function selected 12 */ -#define GPIO_AF_13 AF(13) /*!< alternate function selected 13 */ -#define GPIO_AF_14 AF(14) /*!< alternate function selected 14 */ -#define GPIO_AF_15 AF(15) /*!< alternate function selected 15 */ + +/* GPIO alternate function */ +#define AF(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) +#define GPIO_AF_0 AF(0) /*!< alternate function 0 selected */ +#define GPIO_AF_1 AF(1) /*!< alternate function 1 selected */ +#define GPIO_AF_2 AF(2) /*!< alternate function 2 selected */ +#define GPIO_AF_3 AF(3) /*!< alternate function 3 selected */ +#define GPIO_AF_4 AF(4) /*!< alternate function 4 selected */ +#define GPIO_AF_5 AF(5) /*!< alternate function 5 selected */ +#define GPIO_AF_6 AF(6) /*!< alternate function 6 selected */ +#define GPIO_AF_7 AF(7) /*!< alternate function 7 selected */ +#define GPIO_AF_8 AF(8) /*!< alternate function 8 selected */ +#define GPIO_AF_9 AF(9) /*!< alternate function 9 selected */ +#define GPIO_AF_10 AF(10) /*!< alternate function 10 selected */ +#define GPIO_AF_11 AF(11) /*!< alternate function 11 selected */ +#define GPIO_AF_12 AF(12) /*!< alternate function 12 selected */ +#define GPIO_AF_13 AF(13) /*!< alternate function 13 selected */ +#define GPIO_AF_14 AF(14) /*!< alternate function 14 selected */ +#define GPIO_AF_15 AF(15) /*!< alternate function 15 selected */ /* function declarations */ -/* reset gpio port */ +/* reset GPIO port */ void gpio_deinit(uint32_t gpio_periph); -/* set gpio mode */ -void gpio_mode_set(uint32_t gpio_periph,uint32_t mode,uint32_t pull_up_down,uint32_t pin); -/* set gpio output type and speed */ -void gpio_output_options_set(uint32_t gpio_periph,uint8_t otype,uint32_t speed,uint32_t pin); +/* set GPIO mode */ +void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, uint32_t pin); +/* set GPIO output type and speed */ +void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin); -/* set gpio pin bit */ -void gpio_bit_set(uint32_t gpio_periph,uint32_t pin); -/* reset gpio pin bit */ -void gpio_bit_reset(uint32_t gpio_periph,uint32_t pin); -/* write data to the specified gpio pin */ -void gpio_bit_write(uint32_t gpio_periph,uint32_t pin,bit_status bit_value); -/* write data to the specified gpio port */ -void gpio_port_write(uint32_t gpio_periph,uint16_t data); +/* set GPIO pin bit */ +void gpio_bit_set(uint32_t gpio_periph, uint32_t pin); +/* reset GPIO pin bit */ +void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin); +/* write data to the specified GPIO pin */ +void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value); +/* write data to the specified GPIO port */ +void gpio_port_write(uint32_t gpio_periph, uint16_t data); -/* get gpio pin input status */ -FlagStatus gpio_input_bit_get(uint32_t gpio_periph,uint32_t pin); -/* get gpio port input status */ +/* get GPIO pin input status */ +FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin); +/* get GPIO port input status */ uint16_t gpio_input_port_get(uint32_t gpio_periph); -/* get gpio pin output status */ -FlagStatus gpio_output_bit_get(uint32_t gpio_periph,uint32_t pin); -/* get gpio port output status */ +/* get GPIO pin output status */ +FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin); +/* get GPIO port output status */ uint16_t gpio_output_port_get(uint32_t gpio_periph); -/* set gpio alternate function */ -void gpio_af_set(uint32_t gpio_periph,uint32_t alt_func_num,uint32_t pin); -/* lock gpio pin bit */ -void gpio_pin_lock(uint32_t gpio_periph,uint32_t pin); +/* set GPIO alternate function */ +void gpio_af_set(uint32_t gpio_periph, uint32_t alt_func_num, uint32_t pin); +/* lock GPIO pin bit */ +void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin); -/* toggle gpio pin status */ -void gpio_bit_toggle(uint32_t gpio_periph,uint32_t pin); -/* toggle gpio port status */ +/* toggle GPIO pin status */ +void gpio_bit_toggle(uint32_t gpio_periph, uint32_t pin); +/* toggle GPIO port status */ void gpio_port_toggle(uint32_t gpio_periph); #endif /* GD32F4XX_GPIO_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_i2c.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_i2c.h index f7e93d3357..121e42f497 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_i2c.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_i2c.h @@ -1,29 +1,56 @@ /*! - \file gd32f4xx_i2c.h - \brief definitions for the I2C + \file gd32f4xx_i2c.h + \brief definitions for the I2C + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2019-04-16, V2.0.1, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ + #ifndef GD32F4XX_I2C_H #define GD32F4XX_I2C_H #include "gd32f4xx.h" /* I2Cx(x=0,1,2) definitions */ -#define I2C0 I2C_BASE -#define I2C1 (I2C_BASE+0x400U) -#define I2C2 (I2C_BASE+0x800U) +#define I2C0 I2C_BASE /*!< I2C0 base address */ +#define I2C1 (I2C_BASE+0x400U) /*!< I2C1 base address */ +#define I2C2 (I2C_BASE+0x800U) /*!< I2C2 base address */ /* registers definitions */ #define I2C_CTL0(i2cx) REG32((i2cx) + 0x00U) /*!< I2C control register 0 */ #define I2C_CTL1(i2cx) REG32((i2cx) + 0x04U) /*!< I2C control register 1 */ -#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x08U) /*!< I2C slave address register 0*/ -#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0CU) /*!< I2C slave address register */ +#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x08U) /*!< I2C slave address register 0 */ +#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0CU) /*!< I2C slave address register 1 */ #define I2C_DATA(i2cx) REG32((i2cx) + 0x10U) /*!< I2C transfer buffer register */ #define I2C_STAT0(i2cx) REG32((i2cx) + 0x14U) /*!< I2C transfer status register 0 */ #define I2C_STAT1(i2cx) REG32((i2cx) + 0x18U) /*!< I2C transfer status register */ @@ -32,7 +59,6 @@ #define I2C_FCTL(i2cx) REG32((i2cx) + 0x24U) /*!< I2C filter control register */ #define I2C_SAMCS(i2cx) REG32((i2cx) + 0x80U) /*!< I2C SAM control and status register */ - /* bits definitions */ /* I2Cx_CTL0 */ #define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */ @@ -41,7 +67,7 @@ #define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */ #define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */ #define I2C_CTL0_GCEN BIT(6) /*!< general call enable */ -#define I2C_CTL0_DISSTRC BIT(7) /*!< clock stretching disable (slave mode) */ +#define I2C_CTL0_SS BIT(7) /*!< clock stretching disable (slave mode) */ #define I2C_CTL0_START BIT(8) /*!< start generation */ #define I2C_CTL0_STOP BIT(9) /*!< stop generation */ #define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */ @@ -52,7 +78,7 @@ /* I2Cx_CTL1 */ #define I2C_CTL1_I2CCLK BITS(0,5) /*!< I2CCLK[5:0] bits (peripheral clock frequency) */ -#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt inable */ +#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt enable */ #define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */ #define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */ #define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */ @@ -90,12 +116,12 @@ /* I2Cx_STAT1 */ #define I2C_STAT1_MASTER BIT(0) /*!< master/slave */ #define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */ -#define I2C_STAT1_TRS BIT(2) /*!< transmitter/receiver */ +#define I2C_STAT1_TR BIT(2) /*!< transmitter/receiver */ #define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */ #define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */ #define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */ #define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */ -#define I2C_STAT1_ECV BITS(8,15) /*!< packet error checking register */ +#define I2C_STAT1_PECV BITS(8,15) /*!< packet error checking value */ /* I2Cx_CKCFG */ #define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode (master mode) */ @@ -123,7 +149,6 @@ #define I2C_SAMCS_RFF BIT(14) /*!< rxframe fall flag, cleared by software write 0 */ #define I2C_SAMCS_RFR BIT(15) /*!< rxframe rise flag, cleared by software write 0 */ - /* constants definitions */ /* the digital noise filter can filter spikes's length */ @@ -146,6 +171,94 @@ typedef enum { I2C_DF_15PCLKS /*!< enable digital noise filter and the maximum filtered spiker's length 15 PCLK1 */ }i2c_digital_filter_enum; +/* constants definitions */ +/* define the I2C bit position and its register index offset */ +#define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0xFFFFU) >> 6))) +#define I2C_BIT_POS(val) ((uint32_t)(val) & 0x1FU) +#define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ + | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) +#define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22))) +#define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16) + +/* register offset */ +#define I2C_CTL1_REG_OFFSET 0x04U /*!< CTL1 register offset */ +#define I2C_STAT0_REG_OFFSET 0x14U /*!< STAT0 register offset */ +#define I2C_STAT1_REG_OFFSET 0x18U /*!< STAT1 register offset */ +#define I2C_SAMCS_REG_OFFSET 0x80U /*!< SAMCS register offset */ + +/* I2C flags */ +typedef enum +{ + /* flags in STAT0 register */ + I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */ + I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */ + I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ + I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */ + I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */ + I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving */ + I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */ + I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */ + I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */ + I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */ + I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */ + I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */ + I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */ + I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */ + /* flags in STAT1 register */ + I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */ + I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */ + I2C_FLAG_TRS = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */ + I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */ + I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */ + I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */ + I2C_FLAG_DUMOD = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U), /*!< dual flag in slave mode indicating which address is matched in dual-address mode */ + /* flags in SAMCS register */ + I2C_FLAG_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall flag */ + I2C_FLAG_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise flag */ + I2C_FLAG_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall flag */ + I2C_FLAG_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise flag */ +}i2c_flag_enum; + +/* I2C interrupt flags */ +typedef enum +{ + /* interrupt flags in CTL1 register */ + I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode interrupt flag */ + I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode interrupt flag */ + I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ + I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */ + I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */ + I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving interrupt flag */ + I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */ + I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */ + I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode interrupt flag */ + I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error interrupt flag */ + I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode interrupt flag */ + I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data interrupt flag */ + I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode interrupt flag */ + I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus Alert status interrupt flag */ + /* interrupt flags in SAMCS register */ + I2C_INT_FLAG_TFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 4U, I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall interrupt flag */ + I2C_INT_FLAG_TFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 5U, I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise interrupt flag */ + I2C_INT_FLAG_RFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 6U, I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall interrupt flag */ + I2C_INT_FLAG_RFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 7U, I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise interrupt flag */ +}i2c_interrupt_flag_enum; + +/* I2C interrupt enable or disable */ +typedef enum +{ + /* interrupt in CTL1 register */ + I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt enable */ + I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt enable */ + I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt enable */ + /* interrupt in SAMCS register */ + I2C_INT_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 4U), /*!< txframe fall interrupt enable */ + I2C_INT_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 5U), /*!< txframe rise interrupt enable */ + I2C_INT_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 6U), /*!< rxframe fall interrupt enable */ + I2C_INT_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 7U) /*!< rxframe rise interrupt enable */ +}i2c_interrupt_enum; + /* SMBus/I2C mode switch and SMBus type selection */ #define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */ #define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */ @@ -153,27 +266,28 @@ typedef enum { /* SMBus/I2C mode switch and SMBus type selection */ #define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */ #define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */ + /* I2C transfer direction */ -#define I2C_TRANSMITTER (~BIT(0)) /*!< transmitter */ -#define I2C_RECEIVER BIT(0) /*!< receiver */ +#define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */ +#define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */ /* whether or not to send an ACK */ -#define I2C_ACK_ENABLE ((uint8_t)0x01U) /*!< ACK will be sent */ -#define I2C_ACK_DISABLE ((uint8_t)0x00U) /*!< ACK will be not sent */ +#define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */ +#define I2C_ACK_ENABLE ((uint32_t)0x00000001U) /*!< ACK will be sent */ /* I2C POAP position*/ -#define I2C_ACKPOS_CURRENT ((uint8_t)0x01U) /*!< ACKEN bit decides whether to send ACK or not for the current */ -#define I2C_ACKPOS_NEXT ((uint8_t)0x00U) /*!< ACKEN bit decides whether to send ACK or not for the next byte */ +#define I2C_ACKPOS_NEXT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK for the next byte */ +#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000001U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */ /* I2C dual-address mode switch */ -#define I2C_DUADEN_DISABLE ((uint8_t)0x00U) /*!< dual-address mode disabled */ -#define I2C_DUADEN_ENABLE ((uint8_t)0x01U) /*!< dual-address mode enabled */ +#define I2C_DUADEN_DISABLE ((uint32_t)0x00000000U) /*!< dual-address mode disabled */ +#define I2C_DUADEN_ENABLE ((uint32_t)0x00000001U) /*!< dual-address mode enabled */ /* whether or not to stretch SCL low */ #define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U) /*!< SCL stretching is enabled */ -#define I2C_SCLSTRETCH_DISABLE I2C_CTL0_DISSTRC /*!< SCL stretching is disabled */ +#define I2C_SCLSTRETCH_DISABLE I2C_CTL0_SS /*!< SCL stretching is disabled */ -/* whether or not to response to a General Call */ +/* whether or not to response to a general call */ #define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */ #define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */ @@ -185,11 +299,11 @@ typedef enum { /* DMA mode switch */ #define I2C_DMA_ON I2C_CTL1_DMAON /*!< DMA mode enabled */ #define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< DMA mode disabled */ + /* flag indicating DMA last transfer */ #define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */ #define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */ - /* I2C PEC configure */ /* PEC enable */ #define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */ @@ -203,105 +317,78 @@ typedef enum { /* issue or not alert through SMBA pin */ #define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */ #define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */ + /* ARP protocol in SMBus switch */ #define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< ARP is enabled */ #define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< ARP is disabled */ -/* I2C state */ -/* I2C bit state */ -#define I2C_SBSEND BIT(0) /*!< start condition sent out in master mode */ -#define I2C_ADDSEND BIT(1) /*!< address is sent in master mode or received and matches in slave mode */ -#define I2C_BTC BIT(2) /*!< byte transmission finishes */ -#define I2C_ADD10SEND BIT(3) /*!< header of 10-bit address is sent in master mode */ -#define I2C_STPDET BIT(4) /*!< etop condition detected in slave mode */ -#define I2C_RBNE BIT(6) /*!< I2C_DATA is not Empty during receiving */ -#define I2C_TBE BIT(7) /*!< I2C_DATA is empty during transmitting */ -#define I2C_BERR BIT(8) /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */ -#define I2C_LOSTARB BIT(9) /*!< arbitration lost in master mode */ -#define I2C_AERR BIT(10) /*!< acknowledge error */ -#define I2C_OUERR BIT(11) /*!< over-run or under-run situation occurs in slave mode */ -#define I2C_PECERR BIT(12) /*!< PEC error when receiving data */ -#define I2C_SMBTO BIT(14) /*!< timeout signal in SMBus mode */ -#define I2C_SMBALT BIT(15) /*!< SMBus alert status */ -#define I2C_MASTER (BIT(0)|BIT(31)) /*!< a flag indicating whether I2C block is in master or slave mode */ -#define I2C_I2CBSY (BIT(1)|BIT(31)) /*!< busy flag */ -#define I2C_TRS (BIT(2)|BIT(31)) /*!< whether the I2C is a transmitter or a receiver */ -#define I2C_RXGC (BIT(4)|BIT(31)) /*!< general call address (00h) received */ -#define I2C_DEFSMB (BIT(5)|BIT(31)) /*!< default address of SMBus device */ -#define I2C_HSTSMB (BIT(6)|BIT(31)) /*!< SMBus host header detected in slave mode */ -#define I2C_DUMODF (BIT(7)|BIT(31)) /*!< dual flag in slave mode indicating which address is matched in dual-address mode */ +/* transmit I2C data */ +#define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) + +/* receive I2C data */ +#define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7) /* I2C duty cycle in fast mode */ -#define CKCFG_DTCY(regval) (BIT(14) & ((uint32_t)(regval) << 14)) -#define I2C_DTCY_2 CKCFG_DTCY(0) /*!< I2C fast mode Tlow/Thigh = 2 */ -#define I2C_DTCY_16_9 CKCFG_DTCY(1) /*!< I2C fast mode Tlow/Thigh = 16/9 */ +#define I2C_DTCY_2 ((uint32_t)0x00000000U) /*!< I2C fast mode Tlow/Thigh = 2 */ +#define I2C_DTCY_16_9 I2C_CKCFG_DTCY /*!< I2C fast mode Tlow/Thigh = 16/9 */ /* address mode for the I2C slave */ -#define SADDR0_ADDFORMAT(regval) (BIT(15) & ((regval) << 15)) -#define I2C_ADDFORMAT_7BITS SADDR0_ADDFORMAT(0) /*!< address:7 bits */ -#define I2C_ADDFORMAT_10BITS SADDR0_ADDFORMAT(1) /*!< address:10 bits */ +#define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address:7 bits */ +#define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address:10 bits */ /* function declarations */ /* reset I2C */ void i2c_deinit(uint32_t i2c_periph); -/* I2C clock configure */ -void i2c_clock_config(uint32_t i2c_periph,uint32_t clkspeed,uint32_t dutycyc); -/* I2C address configure */ -void i2c_mode_addr_config(uint32_t i2c_periph,uint32_t i2cmod,uint32_t addformat,uint32_t addr); +/* configure I2C clock */ +void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc); +/* configure I2C address */ +void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr); /* SMBus type selection */ -void i2c_smbus_type_config(uint32_t i2c_periph,uint32_t type); +void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type); /* whether or not to send an ACK */ -void i2c_ack_config(uint32_t i2c_periph,uint8_t ack); -/* I2C POAP position configure */ -void i2c_ackpos_config(uint32_t i2c_periph,uint8_t pos); -/* master send slave address */ -void i2c_master_addressing(uint32_t i2c_periph,uint8_t addr,uint32_t trandirection); -/* dual-address mode switch */ -void i2c_dualaddr_enable(uint32_t i2c_periph, uint8_t dualaddr); - -/* enable i2c */ +void i2c_ack_config(uint32_t i2c_periph, uint32_t ack); +/* configure I2C POAP position */ +void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos); +/* master sends slave address */ +void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection); +/* enable dual-address mode */ +void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr); +/* disable dual-address mode */ +void i2c_dualaddr_disable(uint32_t i2c_periph); +/* enable I2C */ void i2c_enable(uint32_t i2c_periph); -/* disable i2c */ +/* disable I2C */ void i2c_disable(uint32_t i2c_periph); + /* generate a START condition on I2C bus */ void i2c_start_on_bus(uint32_t i2c_periph); /* generate a STOP condition on I2C bus */ void i2c_stop_on_bus(uint32_t i2c_periph); -/* i2c transmit data function */ -void i2c_transmit_data(uint32_t i2c_periph,uint8_t data); -/* i2c receive data function */ -uint8_t i2c_receive_data(uint32_t i2c_periph); -/* I2C DMA mode enable */ -void i2c_dma_enable(uint32_t i2c_periph,uint32_t dmastste); -/* flag indicating DMA last transfer */ -void i2c_dma_last_transfer_enable(uint32_t i2c_periph,uint32_t dmalast); -/* whether to stretch SCL low when data is not ready in slave mode */ -void i2c_stretch_scl_low_config(uint32_t i2c_periph,uint32_t stretchpara ); -/* whether or not to response to a general call */ -void i2c_slave_response_to_gcall_config(uint32_t i2c_periph,uint32_t gcallpara); -/* software reset I2C */ +/* I2C transmit data function */ +void i2c_data_transmit(uint32_t i2c_periph, uint8_t data); +/* I2C receive data function */ +uint8_t i2c_data_receive(uint32_t i2c_periph); +/* enable I2C DMA mode */ +void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate); +/* configure whether next DMA EOT is DMA last transfer or not */ +void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast); +/* whether to stretch SCL low when data is not ready in slave mode */ +void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara); +/* whether or not to response to a general call */ +void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara); +/* software reset I2C */ void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset); -/* check i2c state */ -FlagStatus i2c_flag_get(uint32_t i2c_periph,uint32_t state); -/* clear i2c state */ -void i2c_flag_clear(uint32_t i2c_periph,uint32_t state); -/* enable i2c interrupt */ -void i2c_interrupt_enable(uint32_t i2c_periph,uint32_t inttype); -/* disable i2c interrupt */ -void i2c_interrupt_disable(uint32_t i2c_periph,uint32_t inttype); - /* I2C PEC calculation on or off */ -void i2c_pec_enable(uint32_t i2c_periph,uint32_t pecstate); +void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate); /* I2C whether to transfer PEC value */ -void i2c_pec_transfer_enable(uint32_t i2c_periph,uint32_t pecpara); -/* packet error checking value */ -uint8_t i2c_pec_value(uint32_t i2c_periph); - +void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara); +/* packet error checking value */ +uint8_t i2c_pec_value_get(uint32_t i2c_periph); /* I2C issue alert through SMBA pin */ -void i2c_smbus_alert_issue(uint32_t i2c_periph,uint32_t smbuspara); -/* I2C ARP protocol in SMBus switch */ -void i2c_smbus_arp_enable(uint32_t i2c_periph,uint32_t arpstate); +void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara); +/* I2C ARP protocol in SMBus switch */ +void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate); /* I2C analog noise filter disable */ void i2c_analog_noise_filter_disable(uint32_t i2c_periph); @@ -318,14 +405,18 @@ void i2c_sam_disable(uint32_t i2c_periph); void i2c_sam_timeout_enable(uint32_t i2c_periph); /* disable SAM_V interface timeout detect */ void i2c_sam_timeout_disable(uint32_t i2c_periph); -/* enable the specified I2C SAM interrupt */ -void i2c_sam_interrupt_enable(uint32_t i2c_periph,uint32_t inttype); -/* disable the specified I2C SAM interrupt */ -void i2c_sam_interrupt_disable(uint32_t i2c_periph,uint32_t inttype); -/* check i2c SAM state */ -FlagStatus i2c_sam_flag_get(uint32_t i2c_periph,uint32_t samstate); -/* clear i2c SAM state */ -void i2c_sam_flag_clear(uint32_t i2c_periph,uint32_t samstate); +/* check I2C flag is set or not */ +FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag); +/* clear I2C flag */ +void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag); +/* enable I2C interrupt */ +void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); +/* disable I2C interrupt */ +void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); +/* check I2C interrupt flag */ +FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); +/* clear I2C interrupt flag */ +void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); #endif /* GD32F4XX_I2C_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_ipa.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_ipa.h index d356ac8c3d..d9ae8ce33a 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_ipa.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_ipa.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_ipa.h - \brief definitions for the IPA + \file gd32f4xx_ipa.h + \brief definitions for the IPA + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_IPA_H @@ -24,7 +49,7 @@ #define IPA_INTC REG32(IPA + 0x08U) /*!< IPA interrupt flag clear register */ #define IPA_FMADDR REG32(IPA + 0x0CU) /*!< IPA foreground memory base address register */ #define IPA_FLOFF REG32(IPA + 0x10U) /*!< IPA foreground line offset register */ -#define IPA_BMADDR REG32(IPA + 0x14U) /*!< IPA background memory base address register */ +#define IPA_BMADDR REG32(IPA + 0x14U) /*!< IPA background memory base address register */ #define IPA_BLOFF REG32(IPA + 0x18U) /*!< IPA background line offset register */ #define IPA_FPCTL REG32(IPA + 0x1CU) /*!< IPA foreground pixel control register */ #define IPA_FPV REG32(IPA + 0x20U) /*!< IPA foreground pixel value register */ @@ -33,11 +58,11 @@ #define IPA_FLMADDR REG32(IPA + 0x2CU) /*!< IPA foreground LUT memory base address register */ #define IPA_BLMADDR REG32(IPA + 0x30U) /*!< IPA background LUT memory base address register */ #define IPA_DPCTL REG32(IPA + 0x34U) /*!< IPA destination pixel control register */ -#define IPA_DPV REG32(IPA + 0x38U) /*!< IPA destination pixel value register */ +#define IPA_DPV REG32(IPA + 0x38U) /*!< IPA destination pixel value register */ #define IPA_DMADDR REG32(IPA + 0x3CU) /*!< IPA destination memory base address register */ #define IPA_DLOFF REG32(IPA + 0x40U) /*!< IPA destination line offset register */ #define IPA_IMS REG32(IPA + 0x44U) /*!< IPA image size register */ -#define IPA_LM REG32(IPA + 0x48U) /*!< IPA line mark register */ +#define IPA_LM REG32(IPA + 0x48U) /*!< IPA line mark register */ #define IPA_ITCTL REG32(IPA + 0x4CU) /*!< IPA inter-timer control register */ /* IPA_CTL */ @@ -113,7 +138,7 @@ #define IPA_BLMADDR_BLMADDR BITS(0,31) /*!< background LUT memory base address */ /* IPA_DPCTL */ -#define IPA_DPCTL_DPF BITS(0,2) /*!< destination pixel control register */ +#define IPA_DPCTL_DPF BITS(0,2) /*!< destination pixel control register */ /* IPA_DPV */ /* destination pixel format ARGB8888 */ @@ -165,7 +190,7 @@ /* constants definitions */ /* IPA foreground parameter struct definitions */ typedef struct -{ +{ uint32_t foreground_memaddr; /*!< foreground memory base address */ uint32_t foreground_lineoff; /*!< foreground line offset */ uint32_t foreground_prealpha; /*!< foreground pre-defined alpha value */ @@ -174,25 +199,25 @@ typedef struct uint32_t foreground_prered; /*!< foreground pre-defined red value */ uint32_t foreground_pregreen; /*!< foreground pre-defined green value */ uint32_t foreground_preblue; /*!< foreground pre-defined blue value */ -}ipa_foreground_parameter_struct; +}ipa_foreground_parameter_struct; /* IPA background parameter struct definitions */ typedef struct -{ +{ uint32_t background_memaddr; /*!< background memory base address */ uint32_t background_lineoff; /*!< background line offset */ uint32_t background_prealpha; /*!< background pre-defined alpha value */ - uint32_t background_alpha_algorithm; /*!< background alpha value calculation algorithm */ + uint32_t background_alpha_algorithm; /*!< background alpha value calculation algorithm */ uint32_t background_pf; /*!< background pixel format */ uint32_t background_prered; /*!< background pre-defined red value */ uint32_t background_pregreen; /*!< background pre-defined green value */ uint32_t background_preblue; /*!< background pre-defined blue value */ -}ipa_background_parameter_struct; +}ipa_background_parameter_struct; /* IPA destination parameter struct definitions */ typedef struct { - uint32_t destination_memaddr; /*!< destination memory base address */ + uint32_t destination_memaddr; /*!< destination memory base address */ uint32_t destination_lineoff; /*!< destination line offset */ uint32_t destination_prealpha; /*!< destination pre-defined alpha value */ uint32_t destination_pf; /*!< destination pixel format */ @@ -200,17 +225,17 @@ typedef struct uint32_t destination_pregreen; /*!< destination pre-defined green value */ uint32_t destination_preblue; /*!< destination pre-defined blue value */ uint32_t image_width; /*!< width of the image to be processed */ - uint32_t image_height; /*!< height of the image to be processed */ -}ipa_destination_parameter_struct; + uint32_t image_height; /*!< height of the image to be processed */ +}ipa_destination_parameter_struct; /* destination pixel format */ -typedef enum +typedef enum { - IPA_DPF_ARGB8888, /*!< destination pixel format ARGB8888 */ - IPA_DPF_RGB888, /*!< destination pixel format RGB888 */ - IPA_DPF_RGB565, /*!< destination pixel format RGB565 */ - IPA_DPF_ARGB1555, /*!< destination pixel format ARGB1555 */ - IPA_DPF_ARGB4444 /*!< destination pixel format ARGB4444 */ + IPA_DPF_ARGB8888, /*!< destination pixel format ARGB8888 */ + IPA_DPF_RGB888, /*!< destination pixel format RGB888 */ + IPA_DPF_RGB565, /*!< destination pixel format RGB565 */ + IPA_DPF_ARGB1555, /*!< destination pixel format ARGB1555 */ + IPA_DPF_ARGB4444 /*!< destination pixel format ARGB4444 */ } ipa_dpf_enum; /* LUT pixel format */ @@ -218,30 +243,30 @@ typedef enum #define IPA_LUT_PF_RGB888 ((uint8_t)0x01U) /*!< LUT pixel format RGB888 */ /* Inter-timer */ -#define IPA_INTER_TIMER_DISABLE ((uint8_t)0x00U) /*!< Inter-timer disable */ -#define IPA_INTER_TIMER_ENABLE ((uint8_t)0x01U) /*!< Inter-timer enable */ +#define IPA_INTER_TIMER_DISABLE ((uint8_t)0x00U) /*!< inter-timer disable */ +#define IPA_INTER_TIMER_ENABLE ((uint8_t)0x01U) /*!< inter-timer enable */ /* IPA pixel format convert mode */ -#define CTL_PFCM(regval) (BITS(16,17) & ((regval) << 16)) +#define CTL_PFCM(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) #define IPA_FGTODE CTL_PFCM(0) /*!< foreground memory to destination memory without pixel format convert */ #define IPA_FGTODE_PF_CONVERT CTL_PFCM(1) /*!< foreground memory to destination memory with pixel format convert */ #define IPA_FGBGTODE CTL_PFCM(2) /*!< blending foreground and background memory to destination memory */ #define IPA_FILL_UP_DE CTL_PFCM(3) /*!< fill up destination memory with specific color */ /* foreground alpha value calculation algorithm */ -#define FPCTL_FAVCA(regval) (BITS(16,17) & ((regval) << 16)) +#define FPCTL_FAVCA(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) #define IPA_FG_ALPHA_MODE_0 FPCTL_FAVCA(0) /*!< no effect */ #define IPA_FG_ALPHA_MODE_1 FPCTL_FAVCA(1) /*!< FPDAV[7:0] is selected as the foreground alpha value */ #define IPA_FG_ALPHA_MODE_2 FPCTL_FAVCA(2) /*!< FPDAV[7:0] multiplied by read alpha value */ /* background alpha value calculation algorithm */ -#define BPCTL_BAVCA(regval) (BITS(16,17) & ((regval) << 16)) +#define BPCTL_BAVCA(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) #define IPA_BG_ALPHA_MODE_0 BPCTL_BAVCA(0) /*!< no effect */ #define IPA_BG_ALPHA_MODE_1 BPCTL_BAVCA(1) /*!< BPDAV[7:0] is selected as the background alpha value */ #define IPA_BG_ALPHA_MODE_2 BPCTL_BAVCA(2) /*!< BPDAV[7:0] multiplied by read alpha value */ /* foreground pixel format */ -#define FPCTL_PPF(regval) (BITS(0,3) & ((regval))) +#define FPCTL_PPF(regval) (BITS(0,3) & ((uint32_t)(regval))) #define FOREGROUND_PPF_ARGB8888 FPCTL_PPF(0) /*!< foreground pixel format ARGB8888 */ #define FOREGROUND_PPF_RGB888 FPCTL_PPF(1) /*!< foreground pixel format RGB888 */ #define FOREGROUND_PPF_RGB565 FPCTL_PPF(2) /*!< foreground pixel format RGB565 */ @@ -255,7 +280,7 @@ typedef enum #define FOREGROUND_PPF_A4 FPCTL_PPF(10) /*!< foreground pixel format A4 */ /* background pixel format */ -#define BPCTL_PPF(regval) (BITS(0,3) & ((regval))) +#define BPCTL_PPF(regval) (BITS(0,3) & ((uint32_t)(regval))) #define BACKGROUND_PPF_ARGB8888 BPCTL_PPF(0) /*!< background pixel format ARGB8888 */ #define BACKGROUND_PPF_RGB888 BPCTL_PPF(1) /*!< background pixel format RGB888 */ #define BACKGROUND_PPF_RGB565 BPCTL_PPF(2) /*!< background pixel format RGB565 */ @@ -268,53 +293,92 @@ typedef enum #define BACKGROUND_PPF_A8 BPCTL_PPF(9) /*!< background pixel format A8 */ #define BACKGROUND_PPF_A4 BPCTL_PPF(10) /*!< background pixel format A4 */ +/* IPA flags */ +#define IPA_FLAG_TAE IPA_INTF_TAEIF /*!< transfer access error interrupt flag */ +#define IPA_FLAG_FTF IPA_INTF_FTFIF /*!< full transfer finish interrupt flag */ +#define IPA_FLAG_TLM IPA_INTF_TLMIF /*!< transfer line mark interrupt flag */ +#define IPA_FLAG_LAC IPA_INTF_LACIF /*!< LUT access conflict interrupt flag */ +#define IPA_FLAG_LLF IPA_INTF_LLFIF /*!< LUT loading finish interrupt flag */ +#define IPA_FLAG_WCF IPA_INTF_WCFIF /*!< wrong configuration interrupt flag */ + +/* IPA interrupt enable or disable */ +#define IPA_INT_TAE IPA_CTL_TAEIE /*!< transfer access error interrupt */ +#define IPA_INT_FTF IPA_CTL_FTFIE /*!< full transfer finish interrupt */ +#define IPA_INT_TLM IPA_CTL_TLMIE /*!< transfer line mark interrupt */ +#define IPA_INT_LAC IPA_CTL_LACIE /*!< LUT access conflict interrupt */ +#define IPA_INT_LLF IPA_CTL_LLFIE /*!< LUT loading finish interrupt */ +#define IPA_INT_WCF IPA_CTL_WCFIE /*!< wrong configuration interrupt */ + +/* IPA interrupt flags */ +#define IPA_INT_FLAG_TAE IPA_INTF_TAEIF /*!< transfer access error interrupt flag */ +#define IPA_INT_FLAG_FTF IPA_INTF_FTFIF /*!< full transfer finish interrupt flag */ +#define IPA_INT_FLAG_TLM IPA_INTF_TLMIF /*!< transfer line mark interrupt flag */ +#define IPA_INT_FLAG_LAC IPA_INTF_LACIF /*!< LUT access conflict interrupt flag */ +#define IPA_INT_FLAG_LLF IPA_INTF_LLFIF /*!< LUT loading finish interrupt flag */ +#define IPA_INT_FLAG_WCF IPA_INTF_WCFIF /*!< wrong configuration interrupt flag */ /* function declarations */ - +/* functions enable or disable, pixel format convert mode set */ /* deinitialize IPA */ void ipa_deinit(void); -/* IPA transfer enable */ +/* enable IPA transfer */ void ipa_transfer_enable(void); -/* IPA transfer hang up enable */ +/* enable IPA transfer hang up */ void ipa_transfer_hangup_enable(void); -/* IPA transfer hang up disable */ +/* disable IPA transfer hang up */ void ipa_transfer_hangup_disable(void); -/* IPA transfer stop enable */ +/* enable IPA transfer stop */ void ipa_transfer_stop_enable(void); -/* IPA transfer stop disable */ +/* disable IPA transfer stop */ void ipa_transfer_stop_disable(void); -/* IPA foreground LUT loading enable */ +/* enable IPA foreground LUT loading */ void ipa_foreground_lut_loading_enable(void); -/* IPA background LUT loading enable */ +/* enable IPA background LUT loading */ void ipa_background_lut_loading_enable(void); -/* IPA transfer enable */ -void ipa_pixel_format_convert_mod(uint32_t pfcm); +/* set pixel format convert mode, the function is invalid when the IPA transfer is enabled */ +void ipa_pixel_format_convert_mode_set(uint32_t pfcm); +/* structure initialization, foreground, background, destination and LUT initialization */ +/* initialize the structure of IPA foreground parameter struct with the default values, it is + suggested that call this function after an ipa_foreground_parameter_struct structure is defined */ +void ipa_foreground_struct_para_init(ipa_foreground_parameter_struct* foreground_struct); /* initialize foreground parameters */ void ipa_foreground_init(ipa_foreground_parameter_struct* foreground_struct); +/* initialize the structure of IPA background parameter struct with the default values, it is + suggested that call this function after an ipa_background_parameter_struct structure is defined */ +void ipa_background_struct_para_init(ipa_background_parameter_struct* background_struct); /* initialize background parameters */ void ipa_background_init(ipa_background_parameter_struct* background_struct); +/* initialize the structure of IPA destination parameter struct with the default values, it is + suggested that call this function after an ipa_destination_parameter_struct structure is defined */ +void ipa_destination_struct_para_init(ipa_destination_parameter_struct* destination_struct); /* initialize destination parameters */ void ipa_destination_init(ipa_destination_parameter_struct* destination_struct); /* initialize IPA foreground LUT parameters */ -void ipa_foreground_lut_init(uint32_t fg_lut_num,uint8_t fg_lut_pf, uint32_t fg_lut_addr); +void ipa_foreground_lut_init(uint8_t fg_lut_num, uint8_t fg_lut_pf, uint32_t fg_lut_addr); /* initialize IPA background LUT parameters */ -void ipa_background_lut_init(uint32_t bg_lut_num,uint8_t bg_lut_pf, uint32_t bg_lut_addr); +void ipa_background_lut_init(uint8_t bg_lut_num, uint8_t bg_lut_pf, uint32_t bg_lut_addr); -/* configure line mark */ -void ipa_line_mark_config(uint32_t linenum); -/* Inter-timer enable or disable */ -void ipa_inter_timer_config(uint8_t timercfg); -/* number of clock cycles interval set */ -void ipa_interval_clock_num_config(uint32_t clk_num ); +/* configuration functions */ +/* configure IPA line mark */ +void ipa_line_mark_config(uint16_t line_num); +/* inter-timer enable or disable */ +void ipa_inter_timer_config(uint8_t timer_cfg); +/* configure the number of clock cycles interval */ +void ipa_interval_clock_num_config(uint8_t clk_num); -/* IPA interrupt enable */ -void ipa_interrupt_enable(uint32_t inttype); -/* IPA interrupt disable */ -void ipa_interrupt_disable(uint32_t inttype); +/* flag and interrupt functions */ +/* get IPA flag status in IPA_INTF register */ +FlagStatus ipa_flag_get(uint32_t flag); +/* clear IPA flag in IPA_INTF register */ +void ipa_flag_clear(uint32_t flag); +/* enable IPA interrupt */ +void ipa_interrupt_enable(uint32_t int_flag); +/* disable IPA interrupt */ +void ipa_interrupt_disable(uint32_t int_flag); /* get IPA interrupt flag */ -FlagStatus ipa_interrupt_flag_get(uint32_t intflag); +FlagStatus ipa_interrupt_flag_get(uint32_t int_flag); /* clear IPA interrupt flag */ -void ipa_interrupt_flag_clear(uint32_t intflag); +void ipa_interrupt_flag_clear(uint32_t int_flag); #endif /* GD32F4XX_IPA_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_iref.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_iref.h index 0b7b3224d9..4be9181ed8 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_iref.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_iref.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_iref.h - \brief definitions for the IREF + \file gd32f4xx_iref.h + \brief definitions for the IREF + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_IREF_H @@ -25,7 +50,7 @@ #define IREF_CTL_CSDT BITS(0,5) /*!< current step data */ #define IREF_CTL_SCMOD BIT(7) /*!< sink current mode */ #define IREF_CTL_CPT BITS(8,12) /*!< current precision trim */ -#define IREF_CTL_SSEL BIT(14) /*!< step selection */ +#define IREF_CTL_SSEL BIT(14) /*!< step selection */ #define IREF_CTL_CREN BIT(15) /*!< current reference enable */ /* constants definitions */ @@ -130,13 +155,13 @@ #define IREF_CUR_STEP_DATA_61 CTL_CSDT(61) /*!< IREF current step data 61 */ #define IREF_CUR_STEP_DATA_62 CTL_CSDT(62) /*!< IREF current step data 62 */ #define IREF_CUR_STEP_DATA_63 CTL_CSDT(63) /*!< IREF current step data 63 */ - + /* IREF mode selection */ #define IREF_STEP(regval) (BIT(14) & ((uint32_t)(regval) << 14)) #define IREF_MODE_LOW_POWER IREF_STEP(0) /*!< low power, 1uA step */ #define IREF_MODE_HIGH_CURRENT IREF_STEP(1) /*!< high current, 8uA step */ - -/* IREF sink current mode*/ + +/* IREF sink current mode*/ #define IREF_CURRENT(regval) (BIT(7) & ((uint32_t)(regval) << 7)) #define IREF_SOURCE_CURRENT IREF_CURRENT(0) /*!< IREF source current */ #define IREF_SINK_CURRENT IREF_CURRENT(1) /*!< IREF sink current */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_misc.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_misc.h index 2052abe9a0..21ae664c14 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_misc.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_misc.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_misc.h - \brief definitions for the MISC + \file gd32f4xx_misc.h + \brief definitions for the MISC + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_MISC_H diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_pmu.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_pmu.h index 74a857e96c..f19b1cb2ec 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_pmu.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_pmu.h @@ -1,14 +1,40 @@ /*! - \file gd32f4xx_pmu.h - \brief definitions for the PMU + \file gd32f4xx_pmu.h + \brief definitions for the PMU + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ + #ifndef GD32F4XX_PMU_H #define GD32F4XX_PMU_H @@ -52,14 +78,14 @@ /* constants definitions */ /* PMU low voltage detector threshold definitions */ #define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5)) -#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.2V */ +#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.1V */ #define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */ #define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */ -#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.5V */ -#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.6V */ -#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.7V */ -#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 2.8V */ -#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 2.9V */ +#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.6V */ +#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.7V */ +#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.9V */ +#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 3.0V */ +#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 3.1V */ /* PMU LDO output voltage select definitions */ #define CTL_LDOVS(regval) (BITS(14,15)&((uint32_t)(regval)<<14)) @@ -124,7 +150,7 @@ void pmu_deinit(void); /* select low voltage detector threshold */ -void pmu_lvd_select(uint32_t pmu_lvdt_n); +void pmu_lvd_select(uint32_t lvdt_n); /* LDO output voltage select */ void pmu_ldo_output_select(uint32_t ldo_output); /* PMU lvd disable */ @@ -148,7 +174,7 @@ void pmu_lowdriver_normalpower_config(uint32_t mode); /* PMU work at sleep mode */ void pmu_to_sleepmode(uint8_t sleepmodecmd); /* PMU work at deepsleep mode */ -void pmu_to_deepsleepmode(uint32_t pmu_ldo, uint8_t deepsleepmodecmd); +void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd); /* PMU work at standby mode */ void pmu_to_standbymode(uint8_t standbymodecmd); /* PMU wakeup pin enable */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_rcu.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_rcu.h index 6851c2e22f..0445df4eb0 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_rcu.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_rcu.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_rcu.h - \brief definitions for the RCU + \file gd32f4xx_rcu.h + \brief definitions for the RCU + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_RCU_H @@ -34,14 +59,14 @@ #define RCU_APB2EN REG32(RCU + 0x44U) /*!< APB2 enable register */ #define RCU_AHB1SPEN REG32(RCU + 0x50U) /*!< AHB1 sleep mode enable register */ #define RCU_AHB2SPEN REG32(RCU + 0x54U) /*!< AHB2 sleep mode enable register */ -#define RCU_AHB3SPEN REG32(RCU + 0x58U) /*!< AHB3 sleep mode enable register */ +#define RCU_AHB3SPEN REG32(RCU + 0x58U) /*!< AHB3 sleep mode enable register */ #define RCU_APB1SPEN REG32(RCU + 0x60U) /*!< APB1 sleep mode enable register */ #define RCU_APB2SPEN REG32(RCU + 0x64U) /*!< APB2 sleep mode enable register */ #define RCU_BDCTL REG32(RCU + 0x70U) /*!< backup domain control register */ #define RCU_RSTSCK REG32(RCU + 0x74U) /*!< reset source / clock register */ #define RCU_PLLSSCTL REG32(RCU + 0x80U) /*!< PLL clock spread spectrum control register */ -#define RCU_PLLI2S REG32(RCU + 0x84U) /*!< PLLI2S register */ -#define RCU_PLLSAI REG32(RCU + 0x88U) /*!< PLLSAI register */ +#define RCU_PLLI2S REG32(RCU + 0x84U) /*!< PLLI2S register */ +#define RCU_PLLSAI REG32(RCU + 0x88U) /*!< PLLSAI register */ #define RCU_CFG1 REG32(RCU + 0x8CU) /*!< clock configuration register 1 */ #define RCU_ADDCTL REG32(RCU + 0xC0U) /*!< Additional clock control register */ #define RCU_ADDINT REG32(RCU + 0xCCU) /*!< Additional clock interrupt register */ @@ -54,7 +79,7 @@ /* bits definitions */ /* RCU_CTL */ #define RCU_CTL_IRC16MEN BIT(0) /*!< internal high speed oscillator enable */ -#define RCU_CTL_IRC16MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ +#define RCU_CTL_IRC16MSTB BIT(1) /*!< IRC16M high speed internal oscillator stabilization flag */ #define RCU_CTL_IRC16MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ #define RCU_CTL_IRC16MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ #define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */ @@ -64,7 +89,7 @@ #define RCU_CTL_PLLEN BIT(24) /*!< PLL enable */ #define RCU_CTL_PLLSTB BIT(25) /*!< PLL Clock Stabilization Flag */ #define RCU_CTL_PLLI2SEN BIT(26) /*!< PLLI2S enable */ -#define RCU_CTL_PLLI2STB BIT(27) /*!< PLLI2S Clock Stabilization Flag */ +#define RCU_CTL_PLLI2SSTB BIT(27) /*!< PLLI2S Clock Stabilization Flag */ #define RCU_CTL_PLLSAIEN BIT(28) /*!< PLLSAI enable */ #define RCU_CTL_PLLSAISTB BIT(29) /*!< PLLSAI Clock Stabilization Flag */ @@ -123,7 +148,7 @@ #define RCU_AHB1RST_PGRST BIT(6) /*!< GPIO port G reset */ #define RCU_AHB1RST_PHRST BIT(7) /*!< GPIO port H reset */ #define RCU_AHB1RST_PIRST BIT(8) /*!< GPIO port I reset */ -#define RCU_AHB1RST_CRCRST BIT(12) /*!< CRC reset */ +#define RCU_AHB1RST_CRCRST BIT(12) /*!< CRC reset */ #define RCU_AHB1RST_DMA0RST BIT(21) /*!< DMA0 reset */ #define RCU_AHB1RST_DMA1RST BIT(22) /*!< DMA1 reset */ #define RCU_AHB1RST_IPARST BIT(23) /*!< IPA reset */ @@ -134,7 +159,7 @@ #define RCU_AHB2RST_DCIRST BIT(0) /*!< DCI reset */ #define RCU_AHB2RST_TRNGRST BIT(6) /*!< TRNG reset */ #define RCU_AHB2RST_USBFSRST BIT(7) /*!< USBFS reset */ - + /* RCU_AHB3RST */ #define RCU_AHB3RST_EXMCRST BIT(0) /*!< EXMC reset */ @@ -167,9 +192,9 @@ /* RCU_APB2RST */ #define RCU_APB2RST_TIMER0RST BIT(0) /*!< TIMER0 reset */ -#define RCU_APB2RST_TIMER7RST BIT(1) /*!< TIMER7 reset */ +#define RCU_APB2RST_TIMER7RST BIT(1) /*!< TIMER7 reset */ #define RCU_APB2RST_USART0RST BIT(4) /*!< USART0 reset */ -#define RCU_APB2RST_USART5RST BIT(5) /*!< USART5 reset */ +#define RCU_APB2RST_USART5RST BIT(5) /*!< USART5 reset */ #define RCU_APB2RST_ADCRST BIT(8) /*!< ADC reset */ #define RCU_APB2RST_SDIORST BIT(11) /*!< SDIO reset */ #define RCU_APB2RST_SPI0RST BIT(12) /*!< SPI0 reset */ @@ -361,11 +386,11 @@ #define RCU_RSTSCK_LPRSTF BIT(31) /*!< low-power reset flag */ /* RCU_PLLSSCTL */ -#define RCU_PLLSSCTL_MODCNT BITS(0,12) /*!< these bits configure PLL spread spectrum modulation - profile amplitude and frequency. the following criteria +#define RCU_PLLSSCTL_MODCNT BITS(0,12) /*!< these bits configure PLL spread spectrum modulation + profile amplitude and frequency. the following criteria must be met: MODSTEP*MODCNT=215-1 */ -#define RCU_PLLSSCTL_MODSTEP BITS(13,27) /*!< these bits configure PLL spread spectrum modulation - profile amplitude and frequency. the following criteria +#define RCU_PLLSSCTL_MODSTEP BITS(13,27) /*!< these bits configure PLL spread spectrum modulation + profile amplitude and frequency. the following criteria must be met: MODSTEP*MODCNT=215-1 */ #define RCU_PLLSSCTL_SS_TYPE BIT(30) /*!< PLL spread spectrum modulation type select */ #define RCU_PLLSSCTL_SSCGON BIT(31) /*!< PLL spread spectrum modulation enable */ @@ -438,7 +463,7 @@ #define ADD_APB1EN_REG_OFFSET 0xE4U /*!< APB1 additional enable register offset */ #define ADD_APB1SPEN_REG_OFFSET 0xE8U /*!< APB1 additional sleep mode enable register offset */ -/* peripherals reset */ +/* peripherals reset */ #define AHB1RST_REG_OFFSET 0x10U /*!< AHB1 reset register offset */ #define AHB2RST_REG_OFFSET 0x14U /*!< AHB2 reset register offset */ #define AHB3RST_REG_OFFSET 0x18U /*!< AHB3 reset register offset */ @@ -504,7 +529,7 @@ typedef enum RCU_TIMER6 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 5U), /*!< TIMER6 clock */ RCU_TIMER11 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 6U), /*!< TIMER11 clock */ RCU_TIMER12 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 7U), /*!< TIMER12 clock */ - RCU_TIMER13 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 8U), /*!< TIMER13 clock */ + RCU_TIMER13 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 8U), /*!< TIMER13 clock */ RCU_WWDGT = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 11U), /*!< WWDGT clock */ RCU_SPI1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 14U), /*!< SPI1 clock */ RCU_SPI2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 15U), /*!< SPI2 clock */ @@ -514,7 +539,7 @@ typedef enum RCU_UART4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 20U), /*!< UART4 clock */ RCU_I2C0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 21U), /*!< I2C0 clock */ RCU_I2C1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 22U), /*!< I2C1 clock */ - RCU_I2C2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 23U), /*!< I2C2 clock */ + RCU_I2C2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 23U), /*!< I2C2 clock */ RCU_CAN0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 25U), /*!< CAN0 clock */ RCU_CAN1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 26U), /*!< CAN1 clock */ RCU_PMU = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 28U), /*!< PMU clock */ @@ -540,7 +565,7 @@ typedef enum RCU_SPI4 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 20U), /*!< SPI4 clock */ RCU_SPI5 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 21U), /*!< SPI5 clock */ RCU_TLI = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 26U), /*!< TLI clock */ - /* APB2 additional peripherals */ + /* APB1 additional peripherals */ RCU_CTC = RCU_REGIDX_BIT(ADD_APB1EN_REG_OFFSET, 27U), /*!< CTC clock */ RCU_IREF = RCU_REGIDX_BIT(ADD_APB1EN_REG_OFFSET, 31U), /*!< IREF clock */ }rcu_periph_enum; @@ -588,7 +613,7 @@ typedef enum RCU_TIMER6_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 5U), /*!< TIMER6 clock */ RCU_TIMER11_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 6U), /*!< TIMER11 clock */ RCU_TIMER12_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 7U), /*!< TIMER12 clock */ - RCU_TIMER13_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 8U), /*!< TIMER13 clock */ + RCU_TIMER13_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 8U), /*!< TIMER13 clock */ RCU_WWDGT_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 11U), /*!< WWDGT clock */ RCU_SPI1_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 14U), /*!< SPI1 clock */ RCU_SPI2_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 15U), /*!< SPI2 clock */ @@ -598,7 +623,7 @@ typedef enum RCU_UART4_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 20U), /*!< UART4 clock */ RCU_I2C0_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 21U), /*!< I2C0 clock */ RCU_I2C1_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 22U), /*!< I2C1 clock */ - RCU_I2C2_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 23U), /*!< I2C2 clock */ + RCU_I2C2_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 23U), /*!< I2C2 clock */ RCU_CAN0_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 25U), /*!< CAN0 clock */ RCU_CAN1_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 26U), /*!< CAN1 clock */ RCU_PMU_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 28U), /*!< PMU clock */ @@ -644,8 +669,8 @@ typedef enum RCU_CRCRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 12U), /*!< CRC clock reset */ RCU_DMA0RST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 21U), /*!< DMA0 clock reset */ RCU_DMA1RST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 22U), /*!< DMA1 clock reset */ - RCU_IPAENRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 23U), /*!< IPA clock reset */ - RCU_ENETRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 25U), /*!< ENET clock reset */ + RCU_IPARST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 23U), /*!< IPA clock reset */ + RCU_ENETRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 25U), /*!< ENET clock reset */ RCU_USBHSRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 29U), /*!< USBHS clock reset */ /* AHB2 peripherals */ RCU_DCIRST = RCU_REGIDX_BIT(AHB2RST_REG_OFFSET, 0U), /*!< DCI clock reset */ @@ -662,7 +687,7 @@ typedef enum RCU_TIMER6RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 5U), /*!< TIMER6 clock reset */ RCU_TIMER11RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 6U), /*!< TIMER11 clock reset */ RCU_TIMER12RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 7U), /*!< TIMER12 clock reset */ - RCU_TIMER13RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 8U), /*!< TIMER13 clock reset */ + RCU_TIMER13RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 8U), /*!< TIMER13 clock reset */ RCU_WWDGTRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 11U), /*!< WWDGT clock reset */ RCU_SPI1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 14U), /*!< SPI1 clock reset */ RCU_SPI2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 15U), /*!< SPI2 clock reset */ @@ -672,7 +697,7 @@ typedef enum RCU_UART4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 20U), /*!< UART4 clock reset */ RCU_I2C0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 21U), /*!< I2C0 clock reset */ RCU_I2C1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 22U), /*!< I2C1 clock reset */ - RCU_I2C2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 23U), /*!< I2C2 clock reset */ + RCU_I2C2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 23U), /*!< I2C2 clock reset */ RCU_CAN0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 25U), /*!< CAN0 clock reset */ RCU_CAN1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 26U), /*!< CAN1 clock reset */ RCU_PMURST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 28U), /*!< PMU clock reset */ @@ -695,7 +720,7 @@ typedef enum RCU_SPI4RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 20U), /*!< SPI4 clock reset */ RCU_SPI5RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 21U), /*!< SPI5 clock reset */ RCU_TLIRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 26U), /*!< TLI clock reset */ - /* APB2 additional peripherals */ + /* APB1 additional peripherals */ RCU_CTCRST = RCU_REGIDX_BIT(ADD_APB1RST_REG_OFFSET, 27U), /*!< CTC clock reset */ RCU_IREFRST = RCU_REGIDX_BIT(ADD_APB1RST_REG_OFFSET, 31U) /*!< IREF clock reset */ }rcu_periph_reset_enum; @@ -727,7 +752,7 @@ typedef enum { RCU_INT_FLAG_IRC32KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 0U), /*!< IRC32K stabilization interrupt flag */ RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 1U), /*!< LXTAL stabilization interrupt flag */ - RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 2U), /*!< IRC8M stabilization interrupt flag */ + RCU_INT_FLAG_IRC16MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 2U), /*!< IRC16M stabilization interrupt flag */ RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 3U), /*!< HXTAL stabilization interrupt flag */ RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 4U), /*!< PLL stabilization interrupt flag */ RCU_INT_FLAG_PLLI2SSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 5U), /*!< PLLI2S stabilization interrupt flag */ @@ -755,7 +780,7 @@ typedef enum { RCU_INT_IRC32KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 8U), /*!< IRC32K stabilization interrupt */ RCU_INT_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 9U), /*!< LXTAL stabilization interrupt */ - RCU_INT_IRC16MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 10U), /*!< IRC8M stabilization interrupt */ + RCU_INT_IRC16MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 10U), /*!< IRC16M stabilization interrupt */ RCU_INT_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 11U), /*!< HXTAL stabilization interrupt */ RCU_INT_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 12U), /*!< PLL stabilization interrupt */ RCU_INT_PLLI2SSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 13U), /*!< PLLI2S stabilization interrupt */ @@ -890,7 +915,7 @@ typedef enum /* CKOUT1 Clock source selection */ #define CFG0_CKOUT1SEL(regval) (BITS(30,31) & ((uint32_t)(regval) << 30)) #define RCU_CKOUT1SRC_SYSTEMCLOCK CFG0_CKOUT1SEL(0) /*!< system clock selected */ -#define RCU_CKOUT1SRC_PLLI2SR CFG0_CKOUT1SEL(1) /*!< low speed crystal oscillator clock (LXTAL) selected */ +#define RCU_CKOUT1SRC_PLLI2SR CFG0_CKOUT1SEL(1) /*!< CK_PLLI2SR clock selected */ #define RCU_CKOUT1SRC_HXTAL CFG0_CKOUT1SEL(2) /*!< high speed crystal oscillator clock (HXTAL) selected */ #define RCU_CKOUT1SRC_PLLP CFG0_CKOUT1SEL(3) /*!< CK_PLLP clock selected */ @@ -938,13 +963,13 @@ typedef enum #define RCU_PLLSAIR_DIV16 CFG1_PLLSAIRDIV(3) /*!< CK_PLLSAIRDIV clock select CK_PLLSAIR/16 */ /* TIMER clock selection */ -#define RCU_TIMER_PSC_MUL2 ~RCU_CFG1_TIMERSEL /*!< if APB1PSC/APB2PSC in RCU_CFG0 register is 0b0xx(CK_APBx = CK_AHB) +#define RCU_TIMER_PSC_MUL2 ~RCU_CFG1_TIMERSEL /*!< if APB1PSC/APB2PSC in RCU_CFG0 register is 0b0xx(CK_APBx = CK_AHB) or 0b100(CK_APBx = CK_AHB/2), the TIMER clock is equal to CK_AHB(CK_TIMERx = CK_AHB). - or else, the TIMER clock is twice the corresponding APB clock (TIMER in APB1 domain: CK_TIMERx = 2 x CK_APB1; + or else, the TIMER clock is twice the corresponding APB clock (TIMER in APB1 domain: CK_TIMERx = 2 x CK_APB1; TIMER in APB2 domain: CK_TIMERx = 2 x CK_APB2) */ -#define RCU_TIMER_PSC_MUL4 RCU_CFG1_TIMERSEL /*!< if APB1PSC/APB2PSC in RCU_CFG0 register is 0b0xx(CK_APBx = CK_AHB), - 0b100(CK_APBx = CK_AHB/2), or 0b101(CK_APBx = CK_AHB/4), the TIMER clock is equal to CK_AHB(CK_TIMERx = CK_AHB). - or else, the TIMER clock is four timers the corresponding APB clock (TIMER in APB1 domain: CK_TIMERx = 4 x CK_APB1; +#define RCU_TIMER_PSC_MUL4 RCU_CFG1_TIMERSEL /*!< if APB1PSC/APB2PSC in RCU_CFG0 register is 0b0xx(CK_APBx = CK_AHB), + 0b100(CK_APBx = CK_AHB/2), or 0b101(CK_APBx = CK_AHB/4), the TIMER clock is equal to CK_AHB(CK_TIMERx = CK_AHB). + or else, the TIMER clock is four timers the corresponding APB clock (TIMER in APB1 domain: CK_TIMERx = 4 x CK_APB1; TIMER in APB2 domain: CK_TIMERx = 4 x CK_APB2) */ /* RCU_PLLSSCTL register bit define */ @@ -966,7 +991,7 @@ typedef enum /* The PLLP output frequency division factor from PLL VCO clock */ #define RCU_PLLP_DIV_MIN ((uint32_t)2U) /*!< PLLP_DIV min value */ #define RCU_PLLP_DIV_MAX ((uint32_t)8U) /*!< PLLP_DIV max value */ - + /* PLL Clock Source Selection */ #define RCU_PLLSRC_IRC16M ((uint32_t)0x00000000U) /*!< IRC16M clock selected as source clock of PLL, PLLSAI, PLLI2S */ #define RCU_PLLSRC_HXTAL RCU_PLL_PLLSEL /*!< HXTAL clock selected as source clock of PLL, PLLSAI, PLLI2S */ @@ -975,10 +1000,10 @@ typedef enum #define RCU_PLLQ_DIV_MIN ((uint32_t)2U) /*!< PLLQ_DIV min value */ #define RCU_PLLQ_DIV_MAX ((uint32_t)15U) /*!< PLLQ_DIV max value */ -#define CHECK_PLL_PSC_VALID(val) (((val) >= RCU_PLLPSC_DIV_MIN)&&((val) <= RCU_PLLPSC_DIV_MAX)) -#define CHECK_PLL_N_VALID(val, inc) (((val) >= (RCU_PLLN_MUL_MIN + (inc)))&&((val) <= RCU_PLLN_MUL_MAX)) -#define CHECK_PLL_P_VALID(val) (((val) == 2U) || ((val) == 4U) || ((val) == 6U) || ((val) == 8U)) -#define CHECK_PLL_Q_VALID(val) (((val) >= RCU_PLLQ_DIV_MIN)&&((val) <= RCU_PLLQ_DIV_MAX)) +#define CHECK_PLL_PSC_VALID(val) (((val) >= RCU_PLLPSC_DIV_MIN)&&((val) <= RCU_PLLPSC_DIV_MAX)) +#define CHECK_PLL_N_VALID(val, inc) (((val) >= (RCU_PLLN_MUL_MIN + (inc)))&&((val) <= RCU_PLLN_MUL_MAX)) +#define CHECK_PLL_P_VALID(val) (((val) == 2U) || ((val) == 4U) || ((val) == 6U) || ((val) == 8U)) +#define CHECK_PLL_Q_VALID(val) (((val) >= RCU_PLLQ_DIV_MIN)&&((val) <= RCU_PLLQ_DIV_MAX)) /* RCU_BDCTL register bit define */ /* LXTAL drive capability */ @@ -1033,7 +1058,7 @@ typedef enum #define CHECK_PLLSAI_R_VALID(val) (((val) >= RCU_PLLSAIR_DIV_MIN)&&((val) <= RCU_PLLSAIR_DIV_MAX)) /* RCU_ADDCTL register bit define */ -/* 48MHz clock selection */ +/* 48MHz clock selection */ #define RCU_CK48MSRC_PLL48M ((uint32_t)0x00000000U) /*!< CK48M source clock select PLL48M */ #define RCU_CK48MSRC_IRC48M RCU_ADDCTL_CK48MSEL /*!< CK48M source clock select IRC48M */ @@ -1086,11 +1111,13 @@ void rcu_ckout1_config(uint32_t ckout1_src, uint32_t ckout1_div); /* configure the PLL clock source selection and PLL multiply factor */ ErrStatus rcu_pll_config(uint32_t pll_src, uint32_t pll_psc, uint32_t pll_n, uint32_t pll_p, uint32_t pll_q); /* configure the PLLI2S clock */ -ErrStatus rcu_plli2s_config(uint32_t plli2s_n, uint32_t plli2s_q, uint32_t plli2s_r); +ErrStatus rcu_plli2s_config(uint32_t plli2s_n, uint32_t plli2s_r); /* configure the PLLSAI clock */ -ErrStatus rcu_pllsai_config(uint32_t pllsai_n, uint32_t pllsai_p, uint32_t pllsai_q, uint32_t pllsai_r); +ErrStatus rcu_pllsai_config(uint32_t pllsai_n, uint32_t pllsai_p, uint32_t pllsai_r); /* configure the RTC clock source selection */ void rcu_rtc_clock_config(uint32_t rtc_clock_source); +/* cconfigure the frequency division of RTC clock when HXTAL was selected as its clock source */ +void rcu_rtc_div_config(uint32_t rtc_div); /* configure the I2S clock source selection */ void rcu_i2s_clock_config(uint32_t i2s_clock_source); /* configure the CK48M clock selection */ @@ -1098,7 +1125,7 @@ void rcu_ck48m_clock_config(uint32_t ck48m_clock_source); /* configure the PLL48M clock selection */ void rcu_pll48m_clock_config(uint32_t pll48m_clock_source); /* configure the TIMER clock prescaler selection */ -void rcu_timer_clock_prescaler_config(uint32_t timer_clock_prescaler); +void rcu_timer_clock_prescaler_config(uint32_t timer_clock_prescaler); /* configure the TLI clock division selection */ void rcu_tli_clock_div_config(uint32_t pllsai_r_div); @@ -1110,11 +1137,11 @@ void rcu_all_reset_flag_clear(void); /* get the clock stabilization interrupt and ckm flags */ FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag); /* clear the interrupt flags */ -void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear); +void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag); /* enable the stabilization interrupt */ -void rcu_interrupt_enable(rcu_int_enum stab_int); +void rcu_interrupt_enable(rcu_int_enum interrupt); /* disable the stabilization interrupt */ -void rcu_interrupt_disable(rcu_int_enum stab_int); +void rcu_interrupt_disable(rcu_int_enum interrupt); /* configure the LXTAL drive capability */ void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap); @@ -1140,7 +1167,7 @@ void rcu_spread_spectrum_config(uint32_t spread_spectrum_type, uint32_t modstep, /* enable the spread spectrum modulation for the main PLL clock */ void rcu_spread_spectrum_enable(void); /* disable the spread spectrum modulation for the main PLL clock */ -void rcu_spread_spectrum_disable(void); +void rcu_spread_spectrum_disable(void); /* unlock the voltage key */ void rcu_voltage_key_unlock(void); /* set the deep sleep mode voltage */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_rtc.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_rtc.h index 27155a3076..75e66f236e 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_rtc.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_rtc.h @@ -1,14 +1,40 @@ /*! - \file gd32f4xx_rtc.h - \brief definitions for the RTC + \file gd32f4xx_rtc.c + \brief definitions for the RTC + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ + #ifndef GD32F4XX_RTC_H #define GD32F4XX_RTC_H @@ -254,7 +280,7 @@ typedef struct ControlStatus tamper_precharge_enable; /*!< RTC tamper precharge feature during a voltage level detection */ uint32_t tamper_precharge_time; /*!< RTC tamper precharge duration if precharge feature is enabled */ ControlStatus tamper_with_timestamp; /*!< RTC tamper time-stamp feature */ -}rtc_tamper_struct; +}rtc_tamper_struct; /* time register value */ #define TIME_SC(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_TIME_SC bit field */ @@ -380,7 +406,7 @@ typedef struct #define GET_DTS_DAY(regval) GET_BITS((regval),0,5) /*!< get value of RTC_DTS_DAY bit field */ #define DTS_MON(regval) (BITS(8,12) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_DTS_MON bit field */ -#define GET_DTS_MON(regval) GET_BITS((regval),8,11) /*!< get value of RTC_DTS_MON bit field */ +#define GET_DTS_MON(regval) GET_BITS((regval),8,12) /*!< get value of RTC_DTS_MON bit field */ #define DTS_DOW(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to RTC_DTS_DOW bit field */ #define GET_DTS_DOW(regval) GET_BITS((regval),13,15) /*!< get value of RTC_DTS_DOW bit field */ @@ -399,7 +425,7 @@ typedef struct #define RTC_CALIBRATION_PLUS_RESET ((uint32_t)0x00000000U) /*!< no effect */ /* tamp register value */ -#define TAMP_FREQ(regval) (BITS(8,10) & ((uint32_t)(regval) << 10)) /*!< write value to RTC_TAMP_FREQ bit field */ +#define TAMP_FREQ(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_TAMP_FREQ bit field */ #define RTC_FREQ_DIV32768 TAMP_FREQ(0) /*!< sample once every 32768 RTCCLK(1Hz if RTCCLK=32.768KHz) */ #define RTC_FREQ_DIV16384 TAMP_FREQ(1) /*!< sample once every 16384 RTCCLK(2Hz if RTCCLK=32.768KHz) */ #define RTC_FREQ_DIV8192 TAMP_FREQ(2) /*!< sample once every 8192 RTCCLK(4Hz if RTCCLK=32.768KHz) */ @@ -475,12 +501,12 @@ typedef struct #define RTC_WUT_RESET ((uint32_t)0x0000FFFFU) /*!< RTC_WUT register reset value */ /* RTC alarm */ -#define RTC_ALARM0 ((uint8_t)0x01U) /*!< RTC alarm 0 */ -#define RTC_ALARM1 ((uint8_t)0x02U) /*!< RTC alarm 1 */ +#define RTC_ALARM0 ((uint8_t)0x01U) /*!< RTC alarm 0 */ +#define RTC_ALARM1 ((uint8_t)0x02U) /*!< RTC alarm 1 */ /* RTC coarse calibration direction */ -#define CALIB_INCREASE ((uint8_t)0x01U) /*!< RTC coarse calibration increase */ -#define CALIB_DECREASE ((uint8_t)0x02U) /*!< RTC coarse calibration decrease */ +#define CALIB_INCREASE ((uint8_t)0x01U) /*!< RTC coarse calibration increase */ +#define CALIB_DECREASE ((uint8_t)0x02U) /*!< RTC coarse calibration decrease */ /* RTC wakeup timer clock */ #define CTL_WTCS(regval) (BITS(0,2) & ((regval)<< 0)) @@ -490,13 +516,30 @@ typedef struct #define WAKEUP_RTCCK_DIV2 CTL_WTCS(3) /*!< wakeup timer clock is RTC clock divided by 2 */ #define WAKEUP_CKSPRE CTL_WTCS(4) /*!< wakeup timer clock is ckapre */ #define WAKEUP_CKSPRE_2EXP16 CTL_WTCS(6) /*!< wakeup timer clock is ckapre and wakeup timer add 2exp16 */ - + /* RTC_AF pin */ #define RTC_AF0_TIMESTAMP ((uint32_t)0x00000000) /*!< RTC_AF0 use for timestamp */ #define RTC_AF1_TIMESTAMP RTC_TAMP_TSSEL /*!< RTC_AF1 use for timestamp */ #define RTC_AF0_TAMPER0 ((uint32_t)0x00000000) /*!< RTC_AF0 use for tamper0 */ #define RTC_AF1_TAMPER0 RTC_TAMP_TP0SEL /*!< RTC_AF1 use for tamper0 */ +/* RTC flags */ +#define RTC_FLAG_ALRM0W RTC_STAT_ALRM0WF /*!< alarm0 configuration can be write flag */ +#define RTC_FLAG_ALRM1W RTC_STAT_ALRM1WF /*!< alarm1 configuration can be write flag */ +#define RTC_FLAG_WTW RTC_STAT_WTWF /*!< wakeup timer can be write flag */ +#define RTC_FLAG_SOP RTC_STAT_SOPF /*!< shift function operation pending flag */ +#define RTC_FLAG_YCM RTC_STAT_YCM /*!< year configuration mark status flag */ +#define RTC_FLAG_RSYN RTC_STAT_RSYNF /*!< register synchronization flag */ +#define RTC_FLAG_INIT RTC_STAT_INITF /*!< initialization state flag */ +#define RTC_FLAG_ALRM0 RTC_STAT_ALRM0F /*!< alarm0 occurs flag */ +#define RTC_FLAG_ALRM1 RTC_STAT_ALRM1F /*!< alarm1 occurs flag */ +#define RTC_FLAG_WT RTC_STAT_WTF /*!< wakeup timer occurs flag */ +#define RTC_FLAG_TS RTC_STAT_TSF /*!< time-stamp flag */ +#define RTC_FLAG_TSOVR RTC_STAT_TSOVRF /*!< time-stamp overflow flag */ +#define RTC_FLAG_TP0 RTC_STAT_TP0F /*!< RTC tamper 0 detected flag */ +#define RTC_FLAG_TP1 RTC_STAT_TP1F /*!< RTC tamper 1 detected flag */ +#define RTC_STAT_SCP RTC_STAT_SCPF /*!< smooth calibration pending flag */ + /* function declarations */ /* reset most of the RTC registers */ ErrStatus rtc_deinit(void); diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_sdio.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_sdio.h index bd3b2c8fc6..a18214c023 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_sdio.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_sdio.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_sdio.h - \brief definitions for the SDIO + \file gd32f4xx_sdio.h + \brief definitions for the SDIO + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_SDIO_H @@ -179,7 +204,7 @@ #define SDIO_FLAG_SDIOINT BIT(22) /*!< SD I/O interrupt received flag */ #define SDIO_FLAG_ATAEND BIT(23) /*!< CE-ATA command completion signal received (only for CMD61) flag */ -/* SDIO interrupt flags */ +/* SDIO interrupt enable or disable */ #define SDIO_INT_CCRCERR BIT(0) /*!< SDIO CCRCERR interrupt */ #define SDIO_INT_DTCRCERR BIT(1) /*!< SDIO DTCRCERR interrupt */ #define SDIO_INT_CMDTMOUT BIT(2) /*!< SDIO CMDTMOUT interrupt */ @@ -205,6 +230,32 @@ #define SDIO_INT_SDIOINT BIT(22) /*!< SDIO SDIOINT interrupt */ #define SDIO_INT_ATAEND BIT(23) /*!< SDIO ATAEND interrupt */ +/* SDIO interrupt flags */ +#define SDIO_INT_FLAG_CCRCERR BIT(0) /*!< SDIO CCRCERR interrupt flag */ +#define SDIO_INT_FLAG_DTCRCERR BIT(1) /*!< SDIO DTCRCERR interrupt flag */ +#define SDIO_INT_FLAG_CMDTMOUT BIT(2) /*!< SDIO CMDTMOUT interrupt flag */ +#define SDIO_INT_FLAG_DTTMOUT BIT(3) /*!< SDIO DTTMOUT interrupt flag */ +#define SDIO_INT_FLAG_TXURE BIT(4) /*!< SDIO TXURE interrupt flag */ +#define SDIO_INT_FLAG_RXORE BIT(5) /*!< SDIO RXORE interrupt flag */ +#define SDIO_INT_FLAG_CMDRECV BIT(6) /*!< SDIO CMDRECV interrupt flag */ +#define SDIO_INT_FLAG_CMDSEND BIT(7) /*!< SDIO CMDSEND interrupt flag */ +#define SDIO_INT_FLAG_DTEND BIT(8) /*!< SDIO DTEND interrupt flag */ +#define SDIO_INT_FLAG_STBITE BIT(9) /*!< SDIO STBITE interrupt flag */ +#define SDIO_INT_FLAG_DTBLKEND BIT(10) /*!< SDIO DTBLKEND interrupt flag */ +#define SDIO_INT_FLAG_CMDRUN BIT(11) /*!< SDIO CMDRUN interrupt flag */ +#define SDIO_INT_FLAG_TXRUN BIT(12) /*!< SDIO TXRUN interrupt flag */ +#define SDIO_INT_FLAG_RXRUN BIT(13) /*!< SDIO RXRUN interrupt flag */ +#define SDIO_INT_FLAG_TFH BIT(14) /*!< SDIO TFH interrupt flag */ +#define SDIO_INT_FLAG_RFH BIT(15) /*!< SDIO RFH interrupt flag */ +#define SDIO_INT_FLAG_TFF BIT(16) /*!< SDIO TFF interrupt flag */ +#define SDIO_INT_FLAG_RFF BIT(17) /*!< SDIO RFF interrupt flag */ +#define SDIO_INT_FLAG_TFE BIT(18) /*!< SDIO TFE interrupt flag */ +#define SDIO_INT_FLAG_RFE BIT(19) /*!< SDIO RFE interrupt flag */ +#define SDIO_INT_FLAG_TXDTVAL BIT(20) /*!< SDIO TXDTVAL interrupt flag */ +#define SDIO_INT_FLAG_RXDTVAL BIT(21) /*!< SDIO RXDTVAL interrupt flag */ +#define SDIO_INT_FLAG_SDIOINT BIT(22) /*!< SDIO SDIOINT interrupt flag */ +#define SDIO_INT_FLAG_ATAEND BIT(23) /*!< SDIO ATAEND interrupt flag */ + /* SDIO power control */ #define PWRCTL_PWRCTL(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) #define SDIO_POWER_OFF PWRCTL_PWRCTL(0) /*!< SDIO power off */ @@ -275,6 +326,7 @@ #define SDIO_READWAITTYPE_CLK SDIO_DATACTL_RWTYPE /*!< read wait control by stopping SDIO_CLK */ /* function declarations */ +/* de/initialization functions, hardware clock, bus mode, power_state and SDIO clock configuration */ /* deinitialize the SDIO */ void sdio_deinit(void); /* configure the SDIO clock */ @@ -294,7 +346,7 @@ void sdio_clock_enable(void); /* disable SDIO_CLK clock output */ void sdio_clock_disable(void); -/* configure the command index, argument, response type, wait type and CSM to send command */ +/* configure the command index, argument, response type, wait type and CSM to send command functions */ /* configure the command and response */ void sdio_command_response_config(uint32_t cmd_index, uint32_t cmd_argument, uint32_t response_type); /* set the command state machine wait type */ @@ -308,7 +360,7 @@ uint8_t sdio_command_index_get(void); /* get the response for the last received command */ uint32_t sdio_response_get(uint32_t sdio_responsex); -/* configure the data timeout, length, block size, transfer mode, direction and DSM for data transfer */ +/* configure the data timeout, length, block size, transfer mode, direction and DSM for data transfer functions */ /* configure the data timeout, data length and data block size */ void sdio_data_config(uint32_t data_timeout, uint32_t data_length, uint32_t data_blocksize); /* configure the data transfer mode and direction */ @@ -330,6 +382,7 @@ void sdio_dma_enable(void); /* disable the DMA request for SDIO */ void sdio_dma_disable(void); +/* flag and interrupt functions */ /* get the flags state of SDIO */ FlagStatus sdio_flag_get(uint32_t flag); /* clear the pending flags of SDIO */ @@ -343,6 +396,7 @@ FlagStatus sdio_interrupt_flag_get(uint32_t int_flag); /* clear the interrupt pending flags of SDIO */ void sdio_interrupt_flag_clear(uint32_t int_flag); +/* SD I/O card functions */ /* enable the read wait mode(SD I/O only) */ void sdio_readwait_enable(void); /* disable the read wait mode(SD I/O only) */ @@ -362,6 +416,7 @@ void sdio_suspend_enable(void); /* disable the SD I/O suspend operation(SD I/O only) */ void sdio_suspend_disable(void); +/* CE-ATA functions */ /* enable the CE-ATA command(CE-ATA only) */ void sdio_ceata_command_enable(void); /* disable the CE-ATA command(CE-ATA only) */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_spi.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_spi.h index 422df94a6f..61bf8b1af2 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_spi.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_spi.h @@ -1,14 +1,40 @@ /*! - \file gd32f4xx_spi.h - \brief definitions for the SPI + \file gd32f4xx_spi.h + \brief definitions for the SPI + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ + #ifndef GD32F4XX_SPI_H #define GD32F4XX_SPI_H @@ -50,7 +76,7 @@ #define I2S_ADD_I2SPSC(i2sx_add) REG32((i2sx_add) + 0x20U) /*!< I2S_ADD I2S clock prescaler register */ /* bits definitions */ -/* SPIx_CTL0 */ +/* SPI_CTL0 */ #define SPI_CTL0_CKPH BIT(0) /*!< clock phase selection*/ #define SPI_CTL0_CKPL BIT(1) /*!< clock polarity selection */ #define SPI_CTL0_MSTMOD BIT(2) /*!< master mode enable */ @@ -66,7 +92,7 @@ #define SPI_CTL0_BDOEN BIT(14) /*!< bidirectional transmit output enable*/ #define SPI_CTL0_BDEN BIT(15) /*!< bidirectional enable */ -/* SPIx_CTL1 */ +/* SPI_CTL1 */ #define SPI_CTL1_DMAREN BIT(0) /*!< receive buffer dma enable */ #define SPI_CTL1_DMATEN BIT(1) /*!< transmit buffer dma enable */ #define SPI_CTL1_NSSDRV BIT(2) /*!< drive nss output */ @@ -75,16 +101,16 @@ #define SPI_CTL1_RBNEIE BIT(6) /*!< receive buffer not empty interrupt enable */ #define SPI_CTL1_TBEIE BIT(7) /*!< transmit buffer empty interrupt enable */ -/* SPIx_STAT */ +/* SPI_STAT */ #define SPI_STAT_RBNE BIT(0) /*!< receive buffer not empty */ #define SPI_STAT_TBE BIT(1) /*!< transmit buffer empty */ #define SPI_STAT_I2SCH BIT(2) /*!< I2S channel side */ #define SPI_STAT_TXURERR BIT(3) /*!< I2S transmission underrun error bit */ #define SPI_STAT_CRCERR BIT(4) /*!< SPI CRC error bit */ -#define SPI_STAT_CONFERR BIT(5) /*!< SPI configuration error */ -#define SPI_STAT_RXORERR BIT(6) /*!< SPI reception overrun error Bit */ -#define SPI_STAT_TRANS BIT(7) /*!< transmitting on-going Bit */ -#define SPI_STAT_FERR BIT(8) /*!< format error */ +#define SPI_STAT_CONFERR BIT(5) /*!< SPI configuration error bit */ +#define SPI_STAT_RXORERR BIT(6) /*!< SPI reception overrun error bit */ +#define SPI_STAT_TRANS BIT(7) /*!< transmitting on-going bit */ +#define SPI_STAT_FERR BIT(8) /*!< format error bit */ /* SPI_DATA */ #define SPI_DATA_DATA BITS(0,15) /*!< data transfer register */ @@ -96,9 +122,9 @@ #define SPI_RCRC_RCR BITS(0,15) /*!< RX CRC register */ /* SPI_TCRC */ -#define SPI_TCRC_TCR BITS(0,15) /*!< RX CRC register */ +#define SPI_TCRC_TCR BITS(0,15) /*!< TX CRC register */ -/* SPIx_I2SCTL */ +/* SPI_I2SCTL */ #define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */ #define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */ #define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */ @@ -108,12 +134,12 @@ #define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */ #define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */ -/* SPIx_I2S_PSC */ +/* SPI_I2S_PSC */ #define SPI_I2SPSC_DIV BITS(0,7) /*!< dividing factor for the prescaler */ #define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */ #define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */ -/* SPIx_SPI_QCTL(only SPI5) */ +/* SPI_SPI_QCTL(only SPI5) */ #define SPI_QCTL_QMOD BIT(0) /*!< quad-SPI mode enable */ #define SPI_QCTL_QRD BIT(1) /*!< quad-SPI mode read select */ #define SPI_QCTL_IO23_DRV BIT(2) /*!< drive SPI_IO2 and SPI_IO3 enable */ @@ -121,7 +147,7 @@ /* constants definitions */ /* SPI and I2S parameter struct definitions */ typedef struct -{ +{ uint32_t device_mode; /*!< SPI master or slave */ uint32_t trans_mode; /*!< SPI transtype */ uint32_t frame_size; /*!< SPI frame size */ @@ -131,32 +157,39 @@ typedef struct uint32_t prescale; /*!< SPI prescale factor */ }spi_parameter_struct; -/* SPI struct parameter options */ +/* SPI mode definitions */ #define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master */ #define SPI_SLAVE ((uint32_t)0x00000000U) /*!< SPI as slave */ -#define SPI_BIDIRECTIONAL_TEANSMIT SPI_CTL0_BDOEN /*!< SPI work in transmit-only mode */ -#define SPI_BIDIRECTIONAL_RECEIVE ~SPI_CTL0_BDOEN /*!< SPI work in receive-only mode */ +/* SPI bidirectional transfer direction */ +#define SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN /*!< SPI work in transmit-only mode */ +#define SPI_BIDIRECTIONAL_RECEIVE (~SPI_CTL0_BDOEN) /*!< SPI work in receive-only mode */ +/* SPI transmit type */ #define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U) /*!< SPI receive and send data at fullduplex communication */ #define SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO /*!< SPI only receive data */ #define SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN /*!< bidirectional receive data */ #define SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN) /*!< bidirectional transmit data*/ +/* SPI frame size */ #define SPI_FRAMESIZE_16BIT SPI_CTL0_FF16 /*!< SPI frame size is 16 bits */ #define SPI_FRAMESIZE_8BIT ((uint32_t)0x00000000U) /*!< SPI frame size is 8 bits */ +/* SPI NSS control mode */ #define SPI_NSS_SOFT SPI_CTL0_SWNSSEN /*!< SPI nss control by sofrware */ #define SPI_NSS_HARD ((uint32_t)0x00000000U) /*!< SPI nss control by hardware */ -#define SPI_ENDIAN_MSB ((uint32_t)0x00000000U) /*!< SPI transmit way is big endian:transmit MSB first */ -#define SPI_ENDIAN_LSB SPI_CTL0_LF /*!< SPI transmit way is little endian:transmit LSB first */ +/* SPI transmit way */ +#define SPI_ENDIAN_MSB ((uint32_t)0x00000000U) /*!< SPI transmit way is big endian: transmit MSB first */ +#define SPI_ENDIAN_LSB SPI_CTL0_LF /*!< SPI transmit way is little endian: transmit LSB first */ +/* SPI clock polarity and phase */ #define SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U) /*!< SPI clock polarity is low level and phase is first edge */ #define SPI_CK_PL_HIGH_PH_1EDGE SPI_CTL0_CKPL /*!< SPI clock polarity is high level and phase is first edge */ #define SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH /*!< SPI clock polarity is low level and phase is second edge */ #define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL|SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */ +/* SPI clock prescale factor */ #define CTL0_PSC(regval) (BITS(3,5)&((uint32_t)(regval)<<3)) #define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescale factor is 2 */ #define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescale factor is 4 */ @@ -167,118 +200,171 @@ typedef struct #define SPI_PSC_128 CTL0_PSC(6) /*!< SPI clock prescale factor is 128 */ #define SPI_PSC_256 CTL0_PSC(7) /*!< SPI clock prescale factor is 256 */ -/* I2S parameter options */ -#define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U) /*!< I2S audio sample rate is 8khz */ -#define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U) /*!< I2S audio sample rate is 11khz */ -#define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U) /*!< I2S audio sample rate is 16khz */ -#define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U) /*!< I2S audio sample rate is 22khz */ -#define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U) /*!< I2S audio sample rate is 32khz */ -#define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U) /*!< I2S audio sample rate is 44khz */ -#define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U) /*!< I2S audio sample rate is 48khz */ -#define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U) /*!< I2S audio sample rate is 96khz */ -#define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192khz */ +/* I2S audio sample rate */ +#define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U) /*!< I2S audio sample rate is 8KHz */ +#define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U) /*!< I2S audio sample rate is 11KHz */ +#define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U) /*!< I2S audio sample rate is 16KHz */ +#define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U) /*!< I2S audio sample rate is 22KHz */ +#define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U) /*!< I2S audio sample rate is 32KHz */ +#define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U) /*!< I2S audio sample rate is 44KHz */ +#define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U) /*!< I2S audio sample rate is 48KHz */ +#define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U) /*!< I2S audio sample rate is 96KHz */ +#define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */ +/* I2S frame format */ #define I2SCTL_DTLEN(regval) (BITS(1,2)&((uint32_t)(regval)<<1)) #define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */ #define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0)|SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */ #define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1)|SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */ #define I2S_FRAMEFORMAT_DT32B_CH32B (I2SCTL_DTLEN(2)|SPI_I2SCTL_CHLEN) /*!< I2S data length is 32 bit and channel length is 32 bit */ - + +/* I2S master clock output */ #define I2S_MCKOUT_DISABLE ((uint32_t)0x00000000U) /*!< I2S master clock output disable */ #define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN /*!< I2S master clock output enable */ - + +/* I2S operation mode */ #define I2SCTL_I2SOPMOD(regval) (BITS(8,9)&((uint32_t)(regval)<<8)) #define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */ #define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */ #define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */ #define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */ +/* I2S standard */ #define I2SCTL_I2SSTD(regval) (BITS(4,5)&((uint32_t)(regval)<<4)) #define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0) /*!< I2S phillips standard */ #define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */ #define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */ #define I2S_STD_PCMSHORT I2SCTL_I2SSTD(3) /*!< I2S PCM short standard */ -#define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3)|SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */ +#define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */ +/* I2S clock polarity */ #define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */ #define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */ -/* SPI dma constants definitions */ -#define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data DMA */ -#define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data DMA */ +/* SPI DMA constants definitions */ +#define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */ +#define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */ /* SPI CRC constants definitions */ #define SPI_CRC_TX ((uint8_t)0x00U) /*!< SPI transmit CRC value */ #define SPI_CRC_RX ((uint8_t)0x01U) /*!< SPI receive CRC value */ -/* SPI interrupt constants definitions */ +/* SPI/I2S interrupt enable/disable constants definitions */ #define SPI_I2S_INT_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt */ #define SPI_I2S_INT_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt */ -#define SPI_I2S_INT_RXORERR ((uint8_t)0x02U) /*!< overrun interrupt */ -#define SPI_INT_CONFERR ((uint8_t)0x03U) /*!< config error interrupt */ -#define SPI_INT_CRCERR ((uint8_t)0x04U) /*!< CRC error interrupt */ -#define I2S_INT_TXURERR ((uint8_t)0x05U) /*!< underrun error interrupt */ -#define SPI_I2S_INT_ERR ((uint8_t)0x06U) /*!< error interrupt */ -#define SPI_I2S_INT_FERR ((uint8_t)0x07U) /*!< format error interrupt */ +#define SPI_I2S_INT_ERR ((uint8_t)0x02U) /*!< error interrupt */ -/* SPI flag definitions */ +/* SPI/I2S interrupt flag constants definitions */ +#define SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt flag */ +#define SPI_I2S_INT_FLAG_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt flag */ +#define SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x02U) /*!< overrun interrupt flag */ +#define SPI_INT_FLAG_CONFERR ((uint8_t)0x03U) /*!< config error interrupt flag */ +#define SPI_INT_FLAG_CRCERR ((uint8_t)0x04U) /*!< CRC error interrupt flag */ +#define I2S_INT_FLAG_TXURERR ((uint8_t)0x05U) /*!< underrun error interrupt flag */ +#define SPI_I2S_INT_FLAG_FERR ((uint8_t)0x06U) /*!< format error interrupt flag */ + +/* SPI/I2S flag definitions */ #define SPI_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ #define SPI_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ #define SPI_FLAG_CRCERR SPI_STAT_CRCERR /*!< CRC error flag */ #define SPI_FLAG_CONFERR SPI_STAT_CONFERR /*!< mode config error flag */ -#define SPI_FLAG_RXORERR SPI_STAT_RXORERR /*!< receive overrun flag */ +#define SPI_FLAG_RXORERR SPI_STAT_RXORERR /*!< receive overrun error flag */ #define SPI_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ -#define SPI_FLAG_FERR SPI_STAT_FERR /*!< format error interrupt flag */ +#define SPI_FLAG_FERR SPI_STAT_FERR /*!< format error flag */ #define I2S_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ #define I2S_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ -#define I2S_FLAG_CH SPI_STAT_I2SCH /*!< transmit buffer empty interrupt */ +#define I2S_FLAG_CH SPI_STAT_I2SCH /*!< channel side flag */ #define I2S_FLAG_TXURERR SPI_STAT_TXURERR /*!< underrun error flag */ -#define I2S_FLAG_RXORERR SPI_STAT_RXORERR /*!< overrun flag */ +#define I2S_FLAG_RXORERR SPI_STAT_RXORERR /*!< overrun error flag */ #define I2S_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ -#define I2S_FLAG_FERR SPI_STAT_FERR /*!< format error interrupt flag */ +#define I2S_FLAG_FERR SPI_STAT_FERR /*!< format error flag */ /* function declarations */ -/* SPI and I2S reset */ +/* initialization functions */ +/* deinitialize SPI and I2S */ void spi_i2s_deinit(uint32_t spi_periph); -/* SPI parameter initialization */ +/* initialize the parameters of SPI struct with the default values */ +void spi_struct_para_init(spi_parameter_struct* spi_struct); +/* initialize SPI parameter */ void spi_init(uint32_t spi_periph,spi_parameter_struct* spi_struct); -/* SPI enable */ +/* enable SPI */ void spi_enable(uint32_t spi_periph); -/* SPI disable */ +/* disable SPI */ void spi_disable(uint32_t spi_periph); -/* I2S parameter initialization */ +/* initialize I2S parameter */ void i2s_init(uint32_t spi_periph,uint32_t i2s_mode,uint32_t i2s_standard,uint32_t i2s_ckpl); -/* I2S prescale configuration */ +/* configure I2S prescale */ void i2s_psc_config(uint32_t spi_periph,uint32_t i2s_audiosample,uint32_t i2s_frameformat,uint32_t i2s_mckout); -/* I2S enable */ +/* enable I2S */ void i2s_enable(uint32_t spi_periph); -/* I2S disable */ +/* disable I2S */ void i2s_disable(uint32_t spi_periph); -/* SPI nss output enable */ +/* NSS functions */ +/* enable SPI nss output */ void spi_nss_output_enable(uint32_t spi_periph); -/* SPI nss output disable */ +/* disable SPI nss output */ void spi_nss_output_disable(uint32_t spi_periph); /* SPI nss pin high level in software mode */ void spi_nss_internal_high(uint32_t spi_periph); /* SPI nss pin low level in software mode */ void spi_nss_internal_low(uint32_t spi_periph); -/* SPI dma enable */ +/* SPI DMA functions */ +/* enable SPI DMA */ void spi_dma_enable(uint32_t spi_periph,uint8_t spi_dma); -/* SPI dma disable */ +/* disable SPI DMA */ void spi_dma_disable(uint32_t spi_periph,uint8_t spi_dma); +/* SPI/I2S transfer configure functions */ /* configure SPI/I2S data frame format */ void spi_i2s_data_frame_format_config(uint32_t spi_periph,uint16_t frame_format); -/* transmit data */ +/* SPI transmit data */ void spi_i2s_data_transmit(uint32_t spi_periph,uint16_t data); -/* receive data */ +/* SPI receive data */ uint16_t spi_i2s_data_receive(uint32_t spi_periph); /* configure SPI bidirectional transfer direction */ void spi_bidirectional_transfer_config(uint32_t spi_periph,uint32_t transfer_direction); +/* SPI CRC functions */ +/* set SPI CRC polynomial */ +void spi_crc_polynomial_set(uint32_t spi_periph,uint16_t crc_poly); +/* get SPI CRC polynomial */ +uint16_t spi_crc_polynomial_get(uint32_t spi_periph); +/* turn on SPI CRC function */ +void spi_crc_on(uint32_t spi_periph); +/* turn off SPI CRC function */ +void spi_crc_off(uint32_t spi_periph); +/* SPI next data is CRC value */ +void spi_crc_next(uint32_t spi_periph); +/* get SPI CRC send value or receive value */ +uint16_t spi_crc_get(uint32_t spi_periph,uint8_t spi_crc); + +/* SPI TI mode functions */ +/* enable SPI TI mode */ +void spi_ti_mode_enable(uint32_t spi_periph); +/* disable SPI TI mode */ +void spi_ti_mode_disable(uint32_t spi_periph); + +/* configure i2s full duplex mode */ +void i2s_full_duplex_mode_config(uint32_t i2s_add_periph,uint32_t i2s_mode,uint32_t i2s_standard,uint32_t i2s_ckpl,uint32_t i2s_frameformat); + +/* quad wire SPI functions */ +/* enable quad wire SPI */ +void qspi_enable(uint32_t spi_periph); +/* disable quad wire SPI */ +void qspi_disable(uint32_t spi_periph); +/* enable quad wire SPI write */ +void qspi_write_enable(uint32_t spi_periph); +/* enable quad wire SPI read */ +void qspi_read_enable(uint32_t spi_periph); +/* enable quad wire SPI_IO2 and SPI_IO3 pin output */ +void qspi_io23_output_enable(uint32_t spi_periph); +/* disable quad wire SPI_IO2 and SPI_IO3 pin output */ +void qspi_io23_output_disable(uint32_t spi_periph); + +/* flag & interrupt functions */ /* enable SPI interrupt */ void spi_i2s_interrupt_enable(uint32_t spi_periph,uint8_t spi_i2s_int); /* disable SPI interrupt */ @@ -290,38 +376,4 @@ FlagStatus spi_i2s_flag_get(uint32_t spi_periph,uint32_t spi_i2s_flag); /* clear SPI CRC error flag status */ void spi_crc_error_clear(uint32_t spi_periph); -/* SPI CRC polynomial set */ -void spi_crc_polynomial_set(uint32_t spi_periph,uint16_t crc_poly); -/* SPI CRC polynomial get */ -uint16_t spi_crc_polynomial_get(uint32_t spi_periph); -/* SPI CRC function turn on */ -void spi_crc_on(uint32_t spi_periph); -/* SPI CRC function turn off */ -void spi_crc_off(uint32_t spi_periph); -/* SPI next data is CRC value */ -void spi_crc_next(uint32_t spi_periph); -/* get SPI CRC send value or receive value */ -uint16_t spi_crc_get(uint32_t spi_periph,uint8_t spi_crc); - -/* SPI TI mode enable */ -void spi_ti_mode_enable(uint32_t spi_periph); -/* SPI TI mode disable */ -void spi_ti_mode_disable(uint32_t spi_periph); - -/* configure i2s full duplex mode */ -void i2s_full_duplex_mode_config(uint32_t i2s_add_periph,uint32_t i2s_mode,uint32_t i2s_standard,uint32_t i2s_ckpl,uint32_t i2s_frameformat); - -/* quad wire SPI enable */ -void qspi_enable(uint32_t spi_periph); -/* quad wire SPI disable */ -void qspi_disable(uint32_t spi_periph); -/* quad wire SPI write enable */ -void qspi_write_enable(uint32_t spi_periph); -/* quad wire SPI read enable */ -void qspi_read_enable(uint32_t spi_periph); -/* quad wire SPI_IO2 and SPI_IO3 pin output enable */ -void qspi_io23_output_enable(uint32_t spi_periph); -/* quad wire SPI_IO2 and SPI_IO3 pin output disable */ -void qspi_io23_output_disable(uint32_t spi_periph); - #endif /* GD32F4XX_SPI_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_syscfg.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_syscfg.h index 42ae5599c7..047910478a 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_syscfg.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_syscfg.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_syscfg.h - \brief definitions for the SYSCFG + \file gd32f4xx_syscfg.h + \brief definitions for the SYSCFG + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_SYSCFG_H @@ -85,13 +110,13 @@ #define EXTISS3 ((uint8_t)0x03U) /*!< EXTI source select GPIOx pin 12~15 */ /* EXTI source select mask bits definition */ -#define EXTI_SS_MASK BITS(0,3) +#define EXTI_SS_MASK BITS(0,3) /*!< EXTI source select mask */ /* EXTI source select jumping step definition */ -#define EXTI_SS_JSTEP ((uint8_t)(0x04U)) +#define EXTI_SS_JSTEP ((uint8_t)(0x04U)) /*!< EXTI source select jumping step */ /* EXTI source select moving step definition */ -#define EXTI_SS_MSTEP(pin) (EXTI_SS_JSTEP*((pin)%EXTI_SS_JSTEP)) +#define EXTI_SS_MSTEP(pin) (EXTI_SS_JSTEP*((pin)%EXTI_SS_JSTEP)) /*!< EXTI source select moving step */ /* EXTI source port definitions */ #define EXTI_SOURCE_GPIOA ((uint8_t)0x00U) /*!< EXTI GPIOA configuration */ @@ -123,35 +148,33 @@ #define EXTI_SOURCE_PIN15 ((uint8_t)0x0FU) /*!< EXTI GPIO pin15 configuration */ /* ethernet PHY selection */ -#define SYSCFG_ENET_PHY_MII ((uint32_t)0x00000000U) -#define SYSCFG_ENET_PHY_RMII ((uint32_t)0x00800000U) +#define SYSCFG_ENET_PHY_MII ((uint32_t)0x00000000U) /*!< MII is selected for the Ethernet MAC */ +#define SYSCFG_ENET_PHY_RMII ((uint32_t)0x00800000U) /*!< RMII is selected for the Ethernet MAC */ /* I/O compensation cell enable/disable */ -#define SYSCFG_COMPENSATION_ENABLE ((uint32_t)0x00000001U) -#define SYSCFG_COMPENSATION_DISABLE ((uint32_t)0x00000000U) +#define SYSCFG_COMPENSATION_ENABLE ((uint32_t)0x00000001U) /*!< I/O compensation cell enable */ +#define SYSCFG_COMPENSATION_DISABLE ((uint32_t)0x00000000U) /*!< I/O compensation cell disable */ /* function declarations */ +/* initialization functions */ /* deinit syscfg module */ void syscfg_deinit(void); +/* function configuration */ /* configure the boot mode */ void syscfg_bootmode_config(uint8_t syscfg_bootmode); - -/* FMC memory mapping swap */ +/* configure FMC memory mapping swap */ void syscfg_fmc_swap_config(uint32_t syscfg_fmc_swap); - /* configure the EXMC swap */ -void syscfg_exmc_swap_config(uint32_t syscfg_exmc_swap); - +void syscfg_exmc_swap_config(uint32_t syscfg_exmc_swap); /* configure the GPIO pin as EXTI Line */ void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin); - /* configure the PHY interface for the ethernet MAC */ void syscfg_enet_phy_interface_config(uint32_t syscfg_enet_phy_interface); - /* configure the I/O compensation cell */ -void syscfg_compensation_config(uint32_t syscfg_compensation); +void syscfg_compensation_config(uint32_t syscfg_compensation); +/* interrupt & flag functions */ /* check the I/O compensation cell is ready or not */ FlagStatus syscfg_flag_get(void); diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_timer.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_timer.h index e856ec03ac..9da6e12bdd 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_timer.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_timer.h @@ -1,12 +1,38 @@ /*! - \file gd32f4xx_timer.h - \brief definitions for the TIMER + \file gd32f4xx_timer.h + \brief definitions for the TIMER + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + All rights reserved. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_TIMER_H @@ -66,8 +92,8 @@ #define TIMER_CTL0_CKDIV BITS(8,9) /*!< clock division */ /* TIMER_CTL1 */ -#define TIMER_CTL1_CCSE BIT(0) /*!< capture/compare control shadow register enable */ -#define TIMER_CTL1_CCUC BIT(2) /*!< capture/compare control shadow register update control */ +#define TIMER_CTL1_CCSE BIT(0) /*!< commutation control shadow enable */ +#define TIMER_CTL1_CCUC BIT(2) /*!< commutation control shadow register update control */ #define TIMER_CTL1_DMAS BIT(3) /*!< DMA request source selection */ #define TIMER_CTL1_MMC BITS(4,6) /*!< master mode control */ #define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection(hall mode selection) */ @@ -87,30 +113,30 @@ #define TIMER_SMCFG_ETPSC BITS(12,13) /*!< external trigger prescaler */ #define TIMER_SMCFG_SMC1 BIT(14) /*!< part of SMC for enable external clock mode 1 */ #define TIMER_SMCFG_ETP BIT(15) /*!< external trigger polarity */ - + /* TIMER_DMAINTEN */ #define TIMER_DMAINTEN_UPIE BIT(0) /*!< update interrupt enable */ -#define TIMER_DMAINTEN_CH0IE BIT(1) /*!< channel 0 interrupt enable */ -#define TIMER_DMAINTEN_CH1IE BIT(2) /*!< channel 1 interrupt enable */ -#define TIMER_DMAINTEN_CH2IE BIT(3) /*!< channel 2 interrupt enable */ -#define TIMER_DMAINTEN_CH3IE BIT(4) /*!< channel 3 interrupt enable */ -#define TIMER_DMAINTEN_CMTIE BIT(5) /*!< commutation DMA request enable */ +#define TIMER_DMAINTEN_CH0IE BIT(1) /*!< channel 0 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CH1IE BIT(2) /*!< channel 1 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CH2IE BIT(3) /*!< channel 2 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CH3IE BIT(4) /*!< channel 3 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CMTIE BIT(5) /*!< commutation interrupt request enable */ #define TIMER_DMAINTEN_TRGIE BIT(6) /*!< trigger interrupt enable */ #define TIMER_DMAINTEN_BRKIE BIT(7) /*!< break interrupt enable */ #define TIMER_DMAINTEN_UPDEN BIT(8) /*!< update DMA request enable */ -#define TIMER_DMAINTEN_CH0DEN BIT(8) /*!< channel 0 DMA request enable */ +#define TIMER_DMAINTEN_CH0DEN BIT(9) /*!< channel 0 DMA request enable */ #define TIMER_DMAINTEN_CH1DEN BIT(10) /*!< channel 1 DMA request enable */ #define TIMER_DMAINTEN_CH2DEN BIT(11) /*!< channel 2 DMA request enable */ #define TIMER_DMAINTEN_CH3DEN BIT(12) /*!< channel 3 DMA request enable */ -#define TIMER_DMAINTEN_CMTDEN BIT(13) /*!< channel control update DMA request enable */ +#define TIMER_DMAINTEN_CMTDEN BIT(13) /*!< commutation DMA request enable */ #define TIMER_DMAINTEN_TRGDEN BIT(14) /*!< trigger DMA request enable */ /* TIMER_INTF */ #define TIMER_INTF_UPIF BIT(0) /*!< update interrupt flag */ -#define TIMER_INTF_CH0IF BIT(1) /*!< channel 0 interrupt flag */ -#define TIMER_INTF_CH1IF BIT(2) /*!< channel 1 interrupt flag */ -#define TIMER_INTF_CH2IF BIT(3) /*!< channel 2 interrupt flag */ -#define TIMER_INTF_CH3IF BIT(4) /*!< channel 3 interrupt flag */ +#define TIMER_INTF_CH0IF BIT(1) /*!< channel 0 capture/compare interrupt flag */ +#define TIMER_INTF_CH1IF BIT(2) /*!< channel 1 capture/compare interrupt flag */ +#define TIMER_INTF_CH2IF BIT(3) /*!< channel 2 capture/compare interrupt flag */ +#define TIMER_INTF_CH3IF BIT(4) /*!< channel 3 capture/compare interrupt flag */ #define TIMER_INTF_CMTIF BIT(5) /*!< channel commutation interrupt flag */ #define TIMER_INTF_TRGIF BIT(6) /*!< trigger interrupt flag */ #define TIMER_INTF_BRKIF BIT(7) /*!< break interrupt flag */ @@ -166,20 +192,20 @@ #define TIMER_CHCTL1_CH3CAPFLT BITS(12,15) /*!< channel 3 input capture filter control */ /* TIMER_CHCTL2 */ -#define TIMER_CHCTL2_CH0EN BIT(0) /*!< channel 0 enable */ -#define TIMER_CHCTL2_CH0P BIT(1) /*!< channel 0 polarity */ +#define TIMER_CHCTL2_CH0EN BIT(0) /*!< channel 0 capture/compare function enable */ +#define TIMER_CHCTL2_CH0P BIT(1) /*!< channel 0 capture/compare function polarity */ #define TIMER_CHCTL2_CH0NEN BIT(2) /*!< channel 0 complementary output enable */ #define TIMER_CHCTL2_CH0NP BIT(3) /*!< channel 0 complementary output polarity */ -#define TIMER_CHCTL2_CH1EN BIT(4) /*!< channel 1 enable */ -#define TIMER_CHCTL2_CH1P BIT(5) /*!< channel 1 polarity */ +#define TIMER_CHCTL2_CH1EN BIT(4) /*!< channel 1 capture/compare function enable */ +#define TIMER_CHCTL2_CH1P BIT(5) /*!< channel 1 capture/compare function polarity */ #define TIMER_CHCTL2_CH1NEN BIT(6) /*!< channel 1 complementary output enable */ #define TIMER_CHCTL2_CH1NP BIT(7) /*!< channel 1 complementary output polarity */ -#define TIMER_CHCTL2_CH2EN BIT(8) /*!< channel 2 enable */ -#define TIMER_CHCTL2_CH2P BIT(9) /*!< channel 2 polarity */ +#define TIMER_CHCTL2_CH2EN BIT(8) /*!< channel 2 capture/compare function enable */ +#define TIMER_CHCTL2_CH2P BIT(9) /*!< channel 2 capture/compare function polarity */ #define TIMER_CHCTL2_CH2NEN BIT(10) /*!< channel 2 complementary output enable */ #define TIMER_CHCTL2_CH2NP BIT(11) /*!< channel 2 complementary output polarity */ -#define TIMER_CHCTL2_CH3EN BIT(12) /*!< channel 3 enable */ -#define TIMER_CHCTL2_CH3P BIT(13) /*!< channel 3 polarity */ +#define TIMER_CHCTL2_CH3EN BIT(12) /*!< channel 3 capture/compare function enable */ +#define TIMER_CHCTL2_CH3P BIT(13) /*!< channel 3 capture/compare function polarity */ /* TIMER_CNT */ #define TIMER_CNT_CNT16 BITS(0,15) /*!< 16 bit timer counter */ @@ -200,16 +226,16 @@ #define TIMER_CH0CV_CH0VAL32 BITS(0,31) /*!< 32 bit(TIMER1,TIMER4) capture/compare value of channel 0 */ /* TIMER_CH1CV */ -#define TIMER_CH1CV_CH0VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 1 */ -#define TIMER_CH1CV_CH0VAL32 BITS(0,31) /*!< 32 bit(TIMER1,TIMER4) capture/compare value of channel 1 */ +#define TIMER_CH1CV_CH1VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 1 */ +#define TIMER_CH1CV_CH1VAL32 BITS(0,31) /*!< 32 bit(TIMER1,TIMER4) capture/compare value of channel 1 */ /* TIMER_CH2CV */ -#define TIMER_CH2CV_CH0VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 2 */ -#define TIMER_CH2CV_CH0VAL32 BITS(0,31) /*!< 32 bit(TIMER1,TIMER4) capture/compare value of channel 2 */ +#define TIMER_CH2CV_CH2VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 2 */ +#define TIMER_CH2CV_CH2VAL32 BITS(0,31) /*!< 32 bit(TIMER1,TIMER4) capture/compare value of channel 2 */ /* TIMER_CH3CV */ -#define TIMER_CH3CV_CH0VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 3 */ -#define TIMER_CH3CV_CH0VAL32 BITS(0,31) /*!< 32 bit(TIMER1,TIMER4) capture/compare value of channel 3 */ +#define TIMER_CH3CV_CH3VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 3 */ +#define TIMER_CH3CV_CH3VAL32 BITS(0,31) /*!< 32 bit(TIMER1,TIMER4) capture/compare value of channel 3 */ /* TIMER_CCHP */ #define TIMER_CCHP_DTCFG BITS(0,7) /*!< dead time configure */ @@ -240,31 +266,31 @@ /* constants definitions */ /* TIMER init parameter struct definitions*/ typedef struct -{ +{ uint16_t prescaler; /*!< prescaler value */ uint16_t alignedmode; /*!< aligned mode */ uint16_t counterdirection; /*!< counter direction */ - uint32_t period; /*!< period value */ uint16_t clockdivision; /*!< clock division value */ + uint32_t period; /*!< period value */ uint8_t repetitioncounter; /*!< the counter repetition value */ }timer_parameter_struct; /* break parameter struct definitions*/ typedef struct -{ - uint16_t runoffstate; /*!< run mode off-state */ - uint32_t ideloffstate; /*!< idle mode off-state */ - uint16_t deadtime; /*!< delay time between the switching off and on of the outputs */ +{ + uint16_t runoffstate; /*!< run mode off-state */ + uint16_t ideloffstate; /*!< idle mode off-state */ + uint16_t deadtime; /*!< dead time */ uint16_t breakpolarity; /*!< break polarity */ - uint16_t outputautostate; /*!< output automatic enable */ - uint16_t protectmode; /*!< complementary register protect control */ - uint16_t breakstate; /*!< break enable */ + uint16_t outputautostate; /*!< output automatic enable */ + uint16_t protectmode; /*!< complementary register protect control */ + uint16_t breakstate; /*!< break enable */ }timer_break_parameter_struct; /* channel output parameter struct definitions */ typedef struct -{ - uint32_t outputstate; /*!< channel output state */ +{ + uint16_t outputstate; /*!< channel output state */ uint16_t outputnstate; /*!< channel complementary output state */ uint16_t ocpolarity; /*!< channel output polarity */ uint16_t ocnpolarity; /*!< channel complementary output polarity */ @@ -274,47 +300,59 @@ typedef struct /* channel input parameter struct definitions */ typedef struct -{ +{ uint16_t icpolarity; /*!< channel input polarity */ uint16_t icselection; /*!< channel input mode selection */ uint16_t icprescaler; /*!< channel input capture prescaler */ uint16_t icfilter; /*!< channel input capture filter control */ }timer_ic_parameter_struct; -/* TIMER interrupt source */ -#define TIMER_INT_UP ((uint32_t)0x00000001U) /*!< update interrupt */ -#define TIMER_INT_CH0 ((uint32_t)0x00000002U) /*!< channel 0 interrupt */ -#define TIMER_INT_CH1 ((uint32_t)0x00000004U) /*!< channel 1 interrupt */ -#define TIMER_INT_CH2 ((uint32_t)0x00000008U) /*!< channel 2 interrupt */ -#define TIMER_INT_CH3 ((uint32_t)0x00000010U) /*!< channel 3 interrupt */ -#define TIMER_INT_CMT ((uint32_t)0x00000020U) /*!< channel commutation interrupt flag */ -#define TIMER_INT_TRG ((uint32_t)0x00000040U) /*!< trigger interrupt */ -#define TIMER_INT_BRK ((uint32_t)0x00000080U) /*!< break interrupt */ +/* TIMER interrupt enable or disable */ +#define TIMER_INT_UP TIMER_DMAINTEN_UPIE /*!< update interrupt */ +#define TIMER_INT_CH0 TIMER_DMAINTEN_CH0IE /*!< channel 0 interrupt */ +#define TIMER_INT_CH1 TIMER_DMAINTEN_CH1IE /*!< channel 1 interrupt */ +#define TIMER_INT_CH2 TIMER_DMAINTEN_CH2IE /*!< channel 2 interrupt */ +#define TIMER_INT_CH3 TIMER_DMAINTEN_CH3IE /*!< channel 3 interrupt */ +#define TIMER_INT_CMT TIMER_DMAINTEN_CMTIE /*!< channel commutation interrupt flag */ +#define TIMER_INT_TRG TIMER_DMAINTEN_TRGIE /*!< trigger interrupt */ +#define TIMER_INT_BRK TIMER_DMAINTEN_BRKIE /*!< break interrupt */ /* TIMER flag */ -#define TIMER_FLAG_UP ((uint32_t)0x00000001U) /*!< update flag */ -#define TIMER_FLAG_CH0 ((uint32_t)0x00000002U) /*!< channel 0 flag */ -#define TIMER_FLAG_CH1 ((uint32_t)0x00000004U) /*!< channel 1 flag */ -#define TIMER_FLAG_CH2 ((uint32_t)0x00000008U) /*!< channel 2 flag */ -#define TIMER_FLAG_CH3 ((uint32_t)0x00000010U) /*!< channel 3 flag */ -#define TIMER_FLAG_CMT ((uint32_t)0x00000020U) /*!< channel control update flag */ -#define TIMER_FLAG_TRG ((uint32_t)0x00000040U) /*!< trigger flag */ -#define TIMER_FLAG_BRK ((uint32_t)0x00000080U) /*!< break flag */ -#define TIMER_FLAG_CH0OF ((uint32_t)0x00000200U) /*!< channel 0 overcapture flag */ -#define TIMER_FLAG_CH1OF ((uint32_t)0x00000400U) /*!< channel 1 overcapture flag */ -#define TIMER_FLAG_CH2OF ((uint32_t)0x00000800U) /*!< channel 2 overcapture flag */ -#define TIMER_FLAG_CH3OF ((uint32_t)0x00001000U) /*!< channel 3 overcapture flag */ +#define TIMER_FLAG_UP TIMER_INTF_UPIF /*!< update flag */ +#define TIMER_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 flag */ +#define TIMER_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 flag */ +#define TIMER_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 flag */ +#define TIMER_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 flag */ +#define TIMER_FLAG_CMT TIMER_INTF_CMTIF /*!< channel commutation flag */ +#define TIMER_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger flag */ +#define TIMER_FLAG_BRK TIMER_INTF_BRKIF /*!< break flag */ +#define TIMER_FLAG_CH0O TIMER_INTF_CH0OF /*!< channel 0 overcapture flag */ +#define TIMER_FLAG_CH1O TIMER_INTF_CH1OF /*!< channel 1 overcapture flag */ +#define TIMER_FLAG_CH2O TIMER_INTF_CH2OF /*!< channel 2 overcapture flag */ +#define TIMER_FLAG_CH3O TIMER_INTF_CH3OF /*!< channel 3 overcapture flag */ + +/* TIMER interrupt flag */ +#define TIMER_INT_FLAG_UP TIMER_INTF_UPIF /*!< update interrupt flag */ +#define TIMER_INT_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 interrupt flag */ +#define TIMER_INT_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 interrupt flag */ +#define TIMER_INT_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 interrupt flag */ +#define TIMER_INT_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 interrupt flag */ +#define TIMER_INT_FLAG_CMT TIMER_INTF_CMTIF /*!< channel commutation interrupt flag */ +#define TIMER_INT_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger interrupt flag */ +#define TIMER_INT_FLAG_BRK TIMER_INTF_BRKIF + + /* TIMER DMA source enable */ -#define TIMER_DMA_UPD ((uint16_t)0x0100U) /*!< update DMA enable */ -#define TIMER_DMA_CH0D ((uint16_t)0x0200U) /*!< channel 0 DMA enable */ -#define TIMER_DMA_CH1D ((uint16_t)0x0400U) /*!< channel 1 DMA enable */ -#define TIMER_DMA_CH2D ((uint16_t)0x0800U) /*!< channel 2 DMA enable */ -#define TIMER_DMA_CH3D ((uint16_t)0x1000U) /*!< channel 3 DMA enable */ -#define TIMER_DMA_CMTD ((uint16_t)0x2000U) /*!< commutation DMA request enable */ -#define TIMER_DMA_TRGD ((uint16_t)0x4000U) /*!< trigger DMA enable */ +#define TIMER_DMA_UPD ((uint16_t)TIMER_DMAINTEN_UPDEN) /*!< update DMA enable */ +#define TIMER_DMA_CH0D ((uint16_t)TIMER_DMAINTEN_CH0DEN) /*!< channel 0 DMA enable */ +#define TIMER_DMA_CH1D ((uint16_t)TIMER_DMAINTEN_CH1DEN) /*!< channel 1 DMA enable */ +#define TIMER_DMA_CH2D ((uint16_t)TIMER_DMAINTEN_CH2DEN) /*!< channel 2 DMA enable */ +#define TIMER_DMA_CH3D ((uint16_t)TIMER_DMAINTEN_CH3DEN) /*!< channel 3 DMA enable */ +#define TIMER_DMA_CMTD ((uint16_t)TIMER_DMAINTEN_CMTDEN) /*!< commutation DMA request enable */ +#define TIMER_DMA_TRGD ((uint16_t)TIMER_DMAINTEN_TRGDEN) /*!< trigger DMA enable */ -/* channel DMA request source selection */ +/* channel DMA request source selection */ #define TIMER_DMAREQUEST_UPDATEEVENT ((uint8_t)0x00U) /*!< DMA request of channel y is sent when update event occurs */ #define TIMER_DMAREQUEST_CHANNELEVENT ((uint8_t)0x01U) /*!< DMA request of channel y is sent when channel y event occurs */ @@ -380,12 +418,12 @@ typedef struct #define TIMER_COUNTER_CENTER_BOTH CTL0_CAM(3) /*!< center-aligned and counting up/down assert mode */ /* TIMER prescaler reload mode */ -#define TIMER_PSC_RELOAD_NOW ((uint8_t)0x00U) /*!< the prescaler is loaded right now */ -#define TIMER_PSC_RELOAD_UPDATE ((uint8_t)0x01U) /*!< the prescaler is loaded at the next update event */ +#define TIMER_PSC_RELOAD_NOW ((uint32_t)0x00000000U) /*!< the prescaler is loaded right now */ +#define TIMER_PSC_RELOAD_UPDATE ((uint32_t)0x00000001U) /*!< the prescaler is loaded at the next update event */ /* count direction */ #define TIMER_COUNTER_UP ((uint16_t)0x0000U) /*!< counter up direction */ -#define TIMER_COUNTER_DOWN ((uint16_t)0x0010U) /*!< counter down direction */ +#define TIMER_COUNTER_DOWN ((uint16_t)TIMER_CTL0_DIR) /*!< counter down direction */ /* specify division ratio between TIMER clock and dead-time and sampling clock */ #define CTL0_CKDIV(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) @@ -394,27 +432,27 @@ typedef struct #define TIMER_CKDIV_DIV4 CTL0_CKDIV(2) /*!< clock division value is 4, fDTS= fTIMER_CK/4 */ /* single pulse mode */ -#define TIMER_SP_MODE_SINGLE ((uint8_t)0x00U) /*!< single pulse mode */ -#define TIMER_SP_MODE_REPETITIVE ((uint8_t)0x01U) /*!< repetitive pulse mode */ +#define TIMER_SP_MODE_SINGLE ((uint32_t)0x00000000U) /*!< single pulse mode */ +#define TIMER_SP_MODE_REPETITIVE ((uint32_t)0x00000001U) /*!< repetitive pulse mode */ /* update source */ -#define TIMER_UPDATE_SRC_REGULAR ((uint8_t)0x00U) /*!< update generate only by counter overflow/underflow */ -#define TIMER_UPDATE_SRC_GLOBAL ((uint8_t)0x01U) /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */ +#define TIMER_UPDATE_SRC_REGULAR ((uint32_t)0x00000000U) /*!< update generate only by counter overflow/underflow */ +#define TIMER_UPDATE_SRC_GLOBAL ((uint32_t)0x00000001U) /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */ /* run mode off-state configure */ -#define TIMER_ROS_STATE_ENABLE ((uint32_t)0x00000800U) /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ -#define TIMER_ROS_STATE_DISABLE ((uint32_t)0x00000000U) /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are disabled */ +#define TIMER_ROS_STATE_ENABLE ((uint16_t)TIMER_CCHP_ROS) /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ +#define TIMER_ROS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are disabled */ -/* idle mode off-state configure */ -#define TIMER_IOS_STATE_ENABLE ((uint16_t)0x0400U) /*!< when POEN bit is reset, he channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ +/* idle mode off-state configure */ +#define TIMER_IOS_STATE_ENABLE ((uint16_t)TIMER_CCHP_IOS) /*!< when POEN bit is reset, the channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ #define TIMER_IOS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is reset, the channel output signals (CHx_O/CHx_ON) are disabled */ /* break input polarity */ #define TIMER_BREAK_POLARITY_LOW ((uint16_t)0x0000U) /*!< break input polarity is low */ -#define TIMER_BREAK_POLARITY_HIGH ((uint16_t)0x2000U) /*!< break input polarity is high */ +#define TIMER_BREAK_POLARITY_HIGH ((uint16_t)TIMER_CCHP_BRKP) /*!< break input polarity is high */ /* output automatic enable */ -#define TIMER_OUTAUTO_ENABLE ((uint16_t)0x4000U) /*!< output automatic enable */ +#define TIMER_OUTAUTO_ENABLE ((uint16_t)TIMER_CCHP_OAEN) /*!< output automatic enable */ #define TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000U) /*!< output automatic disable */ /* complementary register protect control */ @@ -425,10 +463,10 @@ typedef struct #define TIMER_CCHP_PROT_2 CCHP_PROT(3) /*!< PROT mode 2 */ /* break input enable */ -#define TIMER_BREAK_ENABLE ((uint16_t)0x1000U) /*!< break input enable */ +#define TIMER_BREAK_ENABLE ((uint16_t)TIMER_CCHP_BRKEN) /*!< break input enable */ #define TIMER_BREAK_DISABLE ((uint16_t)0x0000U) /*!< break input disable */ -/* TIMER channel y(y=0,1,2,3) */ +/* TIMER channel n(n=0,1,2,3) */ #define TIMER_CH_0 ((uint16_t)0x0000U) /*!< TIMER channel 0(TIMERx(x=0..4,7..13)) */ #define TIMER_CH_1 ((uint16_t)0x0001U) /*!< TIMER channel 1(TIMERx(x=0..4,7,8,11)) */ #define TIMER_CH_2 ((uint16_t)0x0002U) /*!< TIMER channel 2(TIMERx(x=0..4,7)) */ @@ -450,11 +488,11 @@ typedef struct #define TIMER_OCN_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel complementary output polarity is high */ #define TIMER_OCN_POLARITY_LOW ((uint16_t)0x0008U) /*!< channel complementary output polarity is low */ -/* idle state of channel output */ +/* idle state of channel output */ #define TIMER_OC_IDLE_STATE_HIGH ((uint16_t)0x0100) /*!< idle state of channel output is high */ #define TIMER_OC_IDLE_STATE_LOW ((uint16_t)0x0000) /*!< idle state of channel output is low */ -/* idle state of channel complementary output */ +/* idle state of channel complementary output */ #define TIMER_OCN_IDLE_STATE_HIGH ((uint16_t)0x0200U) /*!< idle state of channel complementary output is high */ #define TIMER_OCN_IDLE_STATE_LOW ((uint16_t)0x0000U) /*!< idle state of channel complementary output is low */ @@ -476,20 +514,20 @@ typedef struct #define TIMER_OC_FAST_ENABLE ((uint16_t)0x0004) /*!< channel output fast function enable */ #define TIMER_OC_FAST_DISABLE ((uint16_t)0x0000) /*!< channel output fast function disable */ -/* channel output compare clear enable. */ +/* channel output compare clear enable */ #define TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080U) /*!< channel output clear function enable */ #define TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000U) /*!< channel output clear function disable */ -/* channel control shadow register update control */ -#define TIMER_UPDATECTL_CCU ((uint8_t)0x00U) /*!< the shadow registers update by when CMTG bit is set */ -#define TIMER_UPDATECTL_CCUTRI ((uint8_t)0x01U) /*!< the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs */ +/* channel control shadow register update control */ +#define TIMER_UPDATECTL_CCU ((uint32_t)0x00000000U) /*!< the shadow registers are updated when CMTG bit is set */ +#define TIMER_UPDATECTL_CCUTRI ((uint32_t)0x00000001U) /*!< the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs */ /* channel input capture polarity */ #define TIMER_IC_POLARITY_RISING ((uint16_t)0x0000U) /*!< input capture rising edge */ #define TIMER_IC_POLARITY_FALLING ((uint16_t)0x0002U) /*!< input capture falling edge */ #define TIMER_IC_POLARITY_BOTH_EDGE ((uint16_t)0x000AU) /*!< input capture both edge */ -/* timer input capture selection */ +/* TIMER input capture selection */ #define TIMER_IC_SELECTION_DIRECTTI ((uint16_t)0x0001U) /*!< channel y is configured as input and icy is mapped on CIy */ #define TIMER_IC_SELECTION_INDIRECTTI ((uint16_t)0x0002U) /*!< channel y is configured as input and icy is mapped on opposite input */ #define TIMER_IC_SELECTION_ITS ((uint16_t)0x0003U) /*!< channel y is configured as input and icy is mapped on ITS */ @@ -502,28 +540,28 @@ typedef struct /* trigger selection */ #define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) -#define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */ -#define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */ -#define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */ -#define TIMER_SMCFG_TRGSEL_ITI3 SMCFG_TRGSEL(3) /*!< internal trigger 3 */ -#define TIMER_SMCFG_TRGSEL_CI0F_ED SMCFG_TRGSEL(4) /*!< TI0 Edge Detector */ -#define TIMER_SMCFG_TRGSEL_CI0FE0 SMCFG_TRGSEL(5) /*!< filtered TIMER input 0 */ -#define TIMER_SMCFG_TRGSEL_CI1FE1 SMCFG_TRGSEL(6) /*!< filtered TIMER input 1 */ -#define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7) /*!< external trigger */ +#define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */ +#define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */ +#define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */ +#define TIMER_SMCFG_TRGSEL_ITI3 SMCFG_TRGSEL(3) /*!< internal trigger 3 */ +#define TIMER_SMCFG_TRGSEL_CI0F_ED SMCFG_TRGSEL(4) /*!< TI0 Edge Detector */ +#define TIMER_SMCFG_TRGSEL_CI0FE0 SMCFG_TRGSEL(5) /*!< filtered TIMER input 0 */ +#define TIMER_SMCFG_TRGSEL_CI1FE1 SMCFG_TRGSEL(6) /*!< filtered TIMER input 1 */ +#define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7) /*!< external trigger */ /* master mode control */ #define CTL1_MMC(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) #define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0) /*!< the UPG bit as trigger output */ #define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1) /*!< the counter enable signal TIMER_CTL0_CEN as trigger output */ #define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2) /*!< update event as trigger output */ -#define TIMER_TRI_OUT_SRC_CC0 CTL1_MMC(3) /*!< a capture or a compare match occurred in channal0 as trigger output TRGO */ +#define TIMER_TRI_OUT_SRC_CH0 CTL1_MMC(3) /*!< a capture or a compare match occurred in channal0 as trigger output TRGO */ #define TIMER_TRI_OUT_SRC_O0CPRE CTL1_MMC(4) /*!< O0CPRE as trigger output */ #define TIMER_TRI_OUT_SRC_O1CPRE CTL1_MMC(5) /*!< O1CPRE as trigger output */ #define TIMER_TRI_OUT_SRC_O2CPRE CTL1_MMC(6) /*!< O2CPRE as trigger output */ #define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7) /*!< O3CPRE as trigger output */ /* slave mode control */ -#define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U)) +#define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U)) #define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */ #define TIMER_ENCODER_MODE0 SMCFG_SMC(1) /*!< encoder mode 0 */ #define TIMER_ENCODER_MODE1 SMCFG_SMC(2) /*!< encoder mode 1 */ @@ -533,9 +571,9 @@ typedef struct #define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6) /*!< event mode */ #define TIMER_SLAVE_MODE_EXTERNAL0 SMCFG_SMC(7) /*!< external clock mode 0 */ -/* master slave mode selection */ -#define TIMER_MASTER_SLAVE_MODE_ENABLE ((uint8_t)0x00U) /*!< master slave mode enable */ -#define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint8_t)0x01U) /*!< master slave mode disable */ +/* master slave mode selection */ +#define TIMER_MASTER_SLAVE_MODE_ENABLE ((uint32_t)0x00000000U) /*!< master slave mode enable */ +#define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint32_t)0x00000001U) /*!< master slave mode disable */ /* external trigger prescaler */ #define SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U)) @@ -548,19 +586,19 @@ typedef struct #define TIMER_ETP_FALLING TIMER_SMCFG_ETP /*!< active low or falling edge active */ #define TIMER_ETP_RISING ((uint32_t)0x00000000U) /*!< active high or rising edge active */ -/* channel 0 trigger input selection */ -#define TIMER_HALLINTERFACE_ENABLE ((uint8_t)0x00U) /*!< TIMER hall sensor mode enable */ -#define TIMER_HALLINTERFACE_DISABLE ((uint8_t)0x01U) /*!< TIMER hall sensor mode disable */ +/* channel 0 trigger input selection */ +#define TIMER_HALLINTERFACE_ENABLE ((uint32_t)0x00000000U) /*!< TIMER hall sensor mode enable */ +#define TIMER_HALLINTERFACE_DISABLE ((uint32_t)0x00000001U) /*!< TIMER hall sensor mode disable */ /* timer1 internal trigger input1 remap */ -#define TIMER1_IRMP(regval) (BITS(10, 11) & ((uint32_t)(regval) << 10U)) +#define TIMER1_IRMP(regval) (BITS(10, 11) & ((uint32_t)(regval) << 10U)) #define TIMER1_ITI1_RMP_TIMER7_TRGO TIMER1_IRMP(0) /*!< timer1 internal trigger input 1 remap to TIMER7_TRGO */ #define TIMER1_ITI1_RMP_ETHERNET_PTP TIMER1_IRMP(1) /*!< timer1 internal trigger input 1 remap to ethernet PTP */ #define TIMER1_ITI1_RMP_USB_FS_SOF TIMER1_IRMP(2) /*!< timer1 internal trigger input 1 remap to USB FS SOF */ #define TIMER1_ITI1_RMP_USB_HS_SOF TIMER1_IRMP(3) /*!< timer1 internal trigger input 1 remap to USB HS SOF */ /* timer4 channel 3 input remap */ -#define TIMER4_IRMP(regval) (BITS(6, 7) & ((uint32_t)(regval) << 6U)) +#define TIMER4_IRMP(regval) (BITS(6, 7) & ((uint32_t)(regval) << 6U)) #define TIMER4_CI3_RMP_GPIO TIMER4_IRMP(0) /*!< timer4 channel 3 input remap to GPIO pin */ #define TIMER4_CI3_RMP_IRC32K TIMER4_IRMP(1) /*!< timer4 channel 3 input remap to IRC32K */ #define TIMER4_CI3_RMP_LXTAL TIMER4_IRMP(2) /*!< timer4 channel 3 input remap to LXTAL */ @@ -572,19 +610,21 @@ typedef struct #define TIMER10_ITI1_RMP_RTC_HXTAL_DIV TIMER10_IRMP(2) /*!< timer10 internal trigger input1 remap HXTAL _DIV(clock used for RTC which is HXTAL clock divided by RTCDIV bits in RCU_CFG0 register) */ /* timerx(x=0,1,2,13,14,15,16) write cc register selection */ -#define TIMER_CCSEL_DISABLE ((uint16_t)0x0000U) /*!< write CC register selection disable */ -#define TIMER_CCSEL_ENABLE ((uint16_t)0x0002U) /*!< write CC register selection enable */ +#define TIMER_CHVSEL_ENABLE ((uint16_t)0x0002U) /*!< write CHxVAL register selection enable */ +#define TIMER_CHVSEL_DISABLE ((uint16_t)0x0000U) /*!< write CHxVAL register selection disable */ /* the output value selection */ -#define TIMER_OUTSEL_DISABLE ((uint16_t)0x0000U) /*!< output value selection disable */ #define TIMER_OUTSEL_ENABLE ((uint16_t)0x0001U) /*!< output value selection enable */ +#define TIMER_OUTSEL_DISABLE ((uint16_t)0x0000U) /*!< output value selection disable */ /* function declarations */ /* TIMER timebase*/ /* deinit a TIMER */ void timer_deinit(uint32_t timer_periph); +/* initialize TIMER init parameter struct */ +void timer_struct_para_init(timer_parameter_struct* initpara); /* initialize TIMER counter */ -void timer_init(uint32_t timer_periph, timer_parameter_struct* timer_initpara); +void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara); /* enable a TIMER */ void timer_enable(uint32_t timer_periph); /* disable a TIMER */ @@ -598,57 +638,59 @@ void timer_update_event_enable(uint32_t timer_periph); /* disable the update event */ void timer_update_event_disable(uint32_t timer_periph); /* set TIMER counter alignment mode */ -void timer_counter_alignment(uint32_t timer_periph,uint16_t timer_aligned); +void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned); /* set TIMER counter up direction */ void timer_counter_up_direction(uint32_t timer_periph); /* set TIMER counter down direction */ void timer_counter_down_direction(uint32_t timer_periph); /* configure TIMER prescaler */ -void timer_prescaler_config(uint32_t timer_periph,uint16_t timer_prescaler,uint8_t timer_pscreload); +void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload); /* configure TIMER repetition register value */ -void timer_repetition_value_config(uint32_t timer_periph,uint16_t timer_repetition); +void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition); /* configure TIMER autoreload register value */ -void timer_autoreload_value_config(uint32_t timer_periph,uint32_t timer_autoreload); +void timer_autoreload_value_config(uint32_t timer_periph,uint32_t autoreload); /* configure TIMER counter register value */ -void timer_counter_value_config(uint32_t timer_periph , uint32_t timer_counter); +void timer_counter_value_config(uint32_t timer_periph , uint32_t counter); /* read TIMER counter value */ uint32_t timer_counter_read(uint32_t timer_periph); /* read TIMER prescaler value */ uint16_t timer_prescaler_read(uint32_t timer_periph); /* configure TIMER single pulse mode */ -void timer_single_pulse_mode_config(uint32_t timer_periph,uint8_t timer_spmode); +void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode); /* configure TIMER update source */ -void timer_update_source_config(uint32_t timer_periph,uint8_t timer_update); +void timer_update_source_config(uint32_t timer_periph, uint32_t update); /* TIMER interrupt and flag*/ /* enable the TIMER interrupt */ -void timer_interrupt_enable(uint32_t timer_periph,uint32_t timer_interrupt); +void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt); /* disable the TIMER interrupt */ -void timer_interrupt_disable(uint32_t timer_periph,uint32_t timer_interrupt); +void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt); /* get timer interrupt flag */ -FlagStatus timer_interrupt_flag_get(uint32_t timer_periph,uint32_t timer_interrupt); +FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt); /* clear TIMER interrupt flag */ -void timer_interrupt_flag_clear(uint32_t timer_periph,uint32_t timer_interrupt); +void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt); /* get TIMER flags */ -FlagStatus timer_flag_get(uint32_t timer_periph , uint32_t timer_flag); +FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag); /* clear TIMER flags */ -void timer_flag_clear(uint32_t timer_periph , uint32_t timer_flag); +void timer_flag_clear(uint32_t timer_periph, uint32_t flag); /* timer DMA and event*/ /* enable the TIMER DMA */ -void timer_dma_enable(uint32_t timer_periph,uint16_t timer_dma); +void timer_dma_enable(uint32_t timer_periph, uint16_t dma); /* disable the TIMER DMA */ -void timer_dma_disable(uint32_t timer_periph,uint16_t timer_dma); +void timer_dma_disable(uint32_t timer_periph, uint16_t dma); /* channel DMA request source selection */ -void timer_channel_dma_request_source_select(uint32_t timer_periph,uint8_t dma_request); +void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request); /* configure the TIMER DMA transfer */ -void timer_dma_transfer_config(uint32_t timer_periph,uint32_t dma_baseaddr,uint32_t dma_lenth); +void timer_dma_transfer_config(uint32_t timer_periph,uint32_t dma_baseaddr, uint32_t dma_lenth); /* software generate events */ -void timer_event_software_generate(uint32_t timer_periph,uint16_t timer_event); +void timer_event_software_generate(uint32_t timer_periph, uint16_t event); -/* timer channel complementary protection */ +/* TIMER channel complementary protection */ +/* initialize TIMER break parameter struct */ +void timer_break_struct_para_init(timer_break_parameter_struct* breakpara); /* configure TIMER break function */ -void timer_break_config(uint32_t timer_periph,timer_break_parameter_struct* timer_bkdtpara); +void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara); /* enable TIMER break function */ void timer_break_enable(uint32_t timer_periph); /* disable TIMER break function */ @@ -657,79 +699,83 @@ void timer_break_disable(uint32_t timer_periph); void timer_automatic_output_enable(uint32_t timer_periph); /* disable TIMER output automatic function */ void timer_automatic_output_disable(uint32_t timer_periph); -/* configure TIMER primary output function */ -void timer_primary_output_config(uint32_t timer_periph,ControlStatus newvalue); -/* channel capture/compare control shadow register enable */ -void timer_channel_control_shadow_config(uint32_t timer_periph,ControlStatus newvalue); +/* enable or disable TIMER primary output function */ +void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue); +/* enable or disable channel capture/compare control shadow register */ +void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue); /* configure TIMER channel control shadow register update control */ -void timer_channel_control_shadow_update_config(uint32_t timer_periph,uint8_t timer_ccuctl); +void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl); /* TIMER channel output */ +/* initialize TIMER channel output parameter struct */ +void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara); /* configure TIMER channel output function */ -void timer_channel_output_config(uint32_t timer_periph,uint16_t timer_channel,timer_oc_parameter_struct* timer_ocpara); +void timer_channel_output_config(uint32_t timer_periph,uint16_t channel, timer_oc_parameter_struct* ocpara); /* configure TIMER channel output compare mode */ -void timer_channel_output_mode_config(uint32_t timer_periph,uint16_t timer_channel,uint16_t timer_ocmode); +void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel,uint16_t ocmode); /* configure TIMER channel output pulse value */ -void timer_channel_output_pulse_value_config(uint32_t timer_periph,uint16_t timer_channel,uint32_t timer_pluse); +void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse); /* configure TIMER channel output shadow function */ -void timer_channel_output_shadow_config(uint32_t timer_periph,uint16_t timer_channel,uint16_t timer_ocshadow); +void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow); /* configure TIMER channel output fast function */ -void timer_channel_output_fast_config(uint32_t timer_periph,uint16_t timer_channel,uint16_t timer_ocfast); +void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast); /* configure TIMER channel output clear function */ -void timer_channel_output_clear_config(uint32_t timer_periph,uint16_t timer_channel,uint16_t timer_occlear); +void timer_channel_output_clear_config(uint32_t timer_periph,uint16_t channel,uint16_t occlear); /* configure TIMER channel output polarity */ -void timer_channel_output_polarity_config(uint32_t timer_periph,uint16_t timer_channel,uint16_t timer_ocpolarity); +void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity); /* configure TIMER channel complementary output polarity */ -void timer_channel_complementary_output_polarity_config(uint32_t timer_periph,uint16_t timer_channel,uint16_t timer_ocnpolarity); +void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity); /* configure TIMER channel enable state */ -void timer_channel_output_state_config(uint32_t timer_periph,uint16_t timer_channel,uint32_t timer_state); +void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state); /* configure TIMER channel complementary output enable state */ -void timer_channel_complementary_output_state_config(uint32_t timer_periph,uint16_t timer_channel,uint16_t timer_ocnstate); +void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate); /* TIMER channel input */ +/* initialize TIMER channel input parameter struct */ +void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara); /* configure TIMER input capture parameter */ -void timer_input_capture_config(uint32_t timer_periph,uint16_t timer_channel,timer_ic_parameter_struct* timer_icpara); +void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara); /* configure TIMER channel input capture prescaler value */ -void timer_channel_input_capture_prescaler_config(uint32_t timer_periph,uint16_t timer_channel,uint16_t timer_prescaler); +void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler); /* read TIMER channel capture compare register value */ -uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph,uint16_t timer_channel); +uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel); /* configure TIMER input pwm capture function */ -void timer_input_pwm_capture_config(uint32_t timer_periph,uint16_t timer_channel,timer_ic_parameter_struct* timer_icpwm); +void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm); /* configure TIMER hall sensor mode */ -void timer_hall_mode_config(uint32_t timer_periph,uint8_t timer_hallmode); +void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode); /* TIMER master and slave */ /* select TIMER input trigger source */ -void timer_input_trigger_source_select(uint32_t timer_periph,uint32_t timer_intrigger); +void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger); /* select TIMER master mode output trigger source */ -void timer_master_output_trigger_source_select(uint32_t timer_periph,uint32_t timer_outrigger); +void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger); /* select TIMER slave mode */ -void timer_slave_mode_select(uint32_t timer_periph,uint32_t timer_slavemode); +void timer_slave_mode_select(uint32_t timer_periph,uint32_t slavemode); /* configure TIMER master slave mode */ -void timer_master_slave_mode_config(uint32_t timer_periph,uint8_t timer_masterslave); +void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave); /* configure TIMER external trigger input */ -void timer_external_trigger_config(uint32_t timer_periph,uint32_t timer_extprescaler,uint32_t timer_expolarity,uint32_t timer_extfilter); +void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); /* configure TIMER quadrature decoder mode */ -void timer_quadrature_decoder_mode_config(uint32_t timer_periph,uint32_t timer_decomode,uint16_t timer_ic0polarity,uint16_t timer_ic1polarity); +void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity); /* configure TIMER internal clock mode */ void timer_internal_clock_config(uint32_t timer_periph); /* configure TIMER the internal trigger as external clock input */ -void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t timer_intrigger); +void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger); /* configure TIMER the external trigger as external clock input */ -void timer_external_trigger_as_external_clock_config(uint32_t timer_periph,uint32_t timer_extrigger,uint16_t timer_expolarity,uint32_t timer_extfilter); +void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity,uint32_t extfilter); /* configure TIMER the external clock mode 0 */ -void timer_external_clock_mode0_config(uint32_t timer_periph,uint32_t timer_extprescaler,uint32_t timer_expolarity,uint32_t timer_extfilter); +void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); /* configure TIMER the external clock mode 1 */ -void timer_external_clock_mode1_config(uint32_t timer_periph,uint32_t timer_extprescaler,uint32_t timer_expolarity,uint32_t timer_extfilter); +void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); /* disable TIMER the external clock mode 1 */ void timer_external_clock_mode1_disable(uint32_t timer_periph); -/* configure TIMER1 channel 0 remap function */ -void timer_channel_remap_config(uint32_t timer_periph,uint32_t timer_remap); +/* configure TIMER channel remap function */ +void timer_channel_remap_config(uint32_t timer_periph,uint32_t remap); /* TIMER configure */ /* configure TIMER write CHxVAL register selection */ -void timer_write_cc_register_config(uint32_t timer_periph, uint16_t timer_ccsel); +void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel); /* configure TIMER output value selection */ -void timer_output_value_selection_config(uint32_t timer_periph, uint16_t timer_outsel); +void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel); #endif /* GD32F4XX_TIMER_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_tli.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_tli.h index f2f8f9d71e..8b1232fa17 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_tli.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_tli.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_tli.h - \brief definitions for the TLI + \file gd32f4xx_tli.h + \brief definitions for the TLI + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.1, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_TLI_H @@ -17,8 +42,8 @@ /* TLI definitions */ #define TLI TLI_BASE /*!< TLI base address */ /* TLI layer definitions */ -#define LAYER0 TLI_BASE /*!< Layer0 base address */ -#define LAYER1 (TLI_BASE+0x80) /*!< Layer1 base address */ +#define LAYER0 TLI_BASE /*!< TLI layer0 base address */ +#define LAYER1 (TLI_BASE+0x80) /*!< TLI layer1 base address */ /* registers definitions */ #define TLI_SPSZ REG32(TLI + 0x08U) /*!< TLI synchronous pulse size register */ @@ -45,8 +70,7 @@ #define TLI_LxFBADDR(layerx) REG32((layerx) + 0xACU) /*!< TLI layer x frame base address register */ #define TLI_LxFLLEN(layerx) REG32((layerx) + 0xB0U) /*!< TLI layer x frame line length register */ #define TLI_LxFTLN(layerx) REG32((layerx) + 0xB4U) /*!< TLI layer x frame total line number register */ -#define TLI_LxLUT(layerx) REG32((layerx) + 0xC4U) /*!< TLI ayer x Look Up Table register */ - +#define TLI_LxLUT(layerx) REG32((layerx) + 0xC4U) /*!< TLI layer x look up table register */ /* bits definitions */ /* TLI_SPSZ */ @@ -154,8 +178,8 @@ #define TLI_LxFBADDR_FBADD BITS(0,31) /*!< frame buffer base address */ /* TLI_LxFLLEN */ -#define TLI_LxFLLEN_FLL BITS(0,12) /*!< frame line length */ -#define TLI_LxFLLEN_STDOFF BITS(16,28) /*!< frame buffer stride offset */ +#define TLI_LxFLLEN_FLL BITS(0,13) /*!< frame line length */ +#define TLI_LxFLLEN_STDOFF BITS(16,29) /*!< frame buffer stride offset */ /* TLI_LxFTLN */ #define TLI_LxFTLN_FTLN BITS(0,10) /*!< frame total line number */ @@ -167,14 +191,13 @@ #define TLI_LxLUT_TADD BITS(24,31) /*!< look up table write address */ /* constants definitions */ - /* TLI parameter struct definitions */ typedef struct -{ - uint32_t synpsz_vpsz; /*!< size of the vertical synchronous pulse */ - uint32_t synpsz_hpsz; /*!< size of the horizontal synchronous pulse */ - uint32_t backpsz_vbpsz; /*!< size of the vertical back porch plus synchronous pulse */ - uint32_t backpsz_hbpsz; /*!< size of the horizontal back porch plus synchronous pulse */ +{ + uint16_t synpsz_vpsz; /*!< size of the vertical synchronous pulse */ + uint16_t synpsz_hpsz; /*!< size of the horizontal synchronous pulse */ + uint16_t backpsz_vbpsz; /*!< size of the vertical back porch plus synchronous pulse */ + uint16_t backpsz_hbpsz; /*!< size of the horizontal back porch plus synchronous pulse */ uint32_t activesz_vasz; /*!< size of the vertical active area width plus back porch and synchronous pulse */ uint32_t activesz_hasz; /*!< size of the horizontal active area width plus back porch and synchronous pulse */ uint32_t totalsz_vtsz; /*!< vertical total size of the display */ @@ -186,141 +209,168 @@ typedef struct uint32_t signalpolarity_vs; /*!< vertical pulse polarity selection */ uint32_t signalpolarity_de; /*!< data enable polarity selection */ uint32_t signalpolarity_pixelck; /*!< pixel clock polarity selection */ -}tli_parameter_struct; +}tli_parameter_struct; -/* TLI Layer parameter struct definitions */ +/* TLI layer parameter struct definitions */ typedef struct -{ - uint32_t layer_window_rightpos; /*!< window right position */ - uint32_t layer_window_leftpos; /*!< window left position */ - uint32_t layer_window_bottompos; /*!< window bottom position */ - uint32_t layer_window_toppos; /*!< window top position */ +{ + uint16_t layer_window_rightpos; /*!< window right position */ + uint16_t layer_window_leftpos; /*!< window left position */ + uint16_t layer_window_bottompos; /*!< window bottom position */ + uint16_t layer_window_toppos; /*!< window top position */ uint32_t layer_ppf; /*!< packeted pixel format */ - uint32_t layer_sa; /*!< specified alpha */ - uint32_t layer_default_alpha; /*!< the default color alpha */ - uint32_t layer_default_red; /*!< the default color red */ - uint32_t layer_default_green; /*!< the default color green */ - uint32_t layer_default_blue; /*!< the default color blue */ + uint8_t layer_sa; /*!< specified alpha */ + uint8_t layer_default_alpha; /*!< the default color alpha */ + uint8_t layer_default_red; /*!< the default color red */ + uint8_t layer_default_green; /*!< the default color green */ + uint8_t layer_default_blue; /*!< the default color blue */ uint32_t layer_acf1; /*!< alpha calculation factor 1 of blending method */ uint32_t layer_acf2; /*!< alpha calculation factor 2 of blending method */ uint32_t layer_frame_bufaddr; /*!< frame buffer base address */ - uint32_t layer_frame_buf_stride_offset; /*!< frame buffer stride offset */ - uint32_t layer_frame_line_length; /*!< frame line length */ - uint32_t layer_frame_total_line_number; /*!< frame total line number */ -}tli_layer_parameter_struct; + uint16_t layer_frame_buf_stride_offset; /*!< frame buffer stride offset */ + uint16_t layer_frame_line_length; /*!< frame line length */ + uint16_t layer_frame_total_line_number; /*!< frame total line number */ +}tli_layer_parameter_struct; /* TLI layer LUT parameter struct definitions */ typedef struct -{ +{ uint32_t layer_table_addr; /*!< look up table write address */ - uint32_t layer_lut_channel_red; /*!< red channel of a LUT entry */ - uint32_t layer_lut_channel_green; /*!< green channel of a LUT entry */ - uint32_t layer_lut_channel_blue; /*!< blue channel of a LUT entry */ -}tli_layer_lut_parameter_struct; + uint8_t layer_lut_channel_red; /*!< red channel of a LUT entry */ + uint8_t layer_lut_channel_green; /*!< green channel of a LUT entry */ + uint8_t layer_lut_channel_blue; /*!< blue channel of a LUT entry */ +}tli_layer_lut_parameter_struct; /* packeted pixel format */ -typedef enum +typedef enum { - LAYER_PPF_ARGB8888, /*!< layerx pixel format ARGB8888 */ - LAYER_PPF_RGB888, /*!< layerx pixel format RGB888 */ - LAYER_PPF_RGB565, /*!< layerx pixel format RGB565 */ - LAYER_PPF_ARGB1555, /*!< layerx pixel format ARGB1555 */ - LAYER_PPF_ARGB4444, /*!< layerx pixel format ARGB4444 */ - LAYER_PPF_L8, /*!< layerx pixel format L8 */ - LAYER_PPF_AL44, /*!< layerx pixel format AL44 */ - LAYER_PPF_AL88 /*!< layerx pixel format AL88 */ -} tli_layer_ppf_enum; + LAYER_PPF_ARGB8888, /*!< layerx pixel format ARGB8888 */ + LAYER_PPF_RGB888, /*!< layerx pixel format RGB888 */ + LAYER_PPF_RGB565, /*!< layerx pixel format RGB565 */ + LAYER_PPF_ARGB1555, /*!< layerx pixel format ARGB1555 */ + LAYER_PPF_ARGB4444, /*!< layerx pixel format ARGB4444 */ + LAYER_PPF_L8, /*!< layerx pixel format L8 */ + LAYER_PPF_AL44, /*!< layerx pixel format AL44 */ + LAYER_PPF_AL88 /*!< layerx pixel format AL88 */ +}tli_layer_ppf_enum; + +/* TLI flags */ +#define TLI_FLAG_VDE TLI_STAT_VDE /*!< current VDE status */ +#define TLI_FLAG_HDE TLI_STAT_HDE /*!< current HDE status */ +#define TLI_FLAG_VS TLI_STAT_VS /*!< current VS status of the TLI */ +#define TLI_FLAG_HS TLI_STAT_HS /*!< current HS status of the TLI */ +#define TLI_FLAG_LM BIT(0) | BIT(31) /*!< line mark interrupt flag */ +#define TLI_FLAG_FE BIT(1) | BIT(31) /*!< FIFO error interrupt flag */ +#define TLI_FLAG_TE BIT(2) | BIT(31) /*!< transaction error interrupt flag */ +#define TLI_FLAG_LCR BIT(3) | BIT(31) /*!< layer configuration reloaded interrupt flag */ + +/* TLI interrupt enable or disable */ +#define TLI_INT_LM BIT(0) /*!< line mark interrupt */ +#define TLI_INT_FE BIT(1) /*!< FIFO error interrupt */ +#define TLI_INT_TE BIT(2) /*!< transaction error interrupt */ +#define TLI_INT_LCR BIT(3) /*!< layer configuration reloaded interrupt */ + +/* TLI interrupt flag */ +#define TLI_INT_FLAG_LM BIT(0) /*!< line mark interrupt flag */ +#define TLI_INT_FLAG_FE BIT(1) /*!< FIFO error interrupt flag */ +#define TLI_INT_FLAG_TE BIT(2) /*!< transaction error interrupt flag */ +#define TLI_INT_FLAG_LCR BIT(3) /*!< layer configuration reloaded interrupt flag */ /* layer reload configure */ -#define TLI_FRAME_BLANK_RELOAD_EN ((uint8_t)0x00U) /*!< the layer configuration will be reloaded at frame blank */ -#define TLI_REQUEST_RELOAD_EN ((uint8_t)0x01U) /*!< the layer configuration will be reloaded after this bit sets */ +#define TLI_FRAME_BLANK_RELOAD_EN ((uint8_t)0x00U) /*!< the layer configuration will be reloaded at frame blank */ +#define TLI_REQUEST_RELOAD_EN ((uint8_t)0x01U) /*!< the layer configuration will be reloaded after this bit sets */ -/* dither Function */ -#define TLI_DITHER_DISABLE ((uint8_t)0x00U) /*!< dither function disable */ -#define TLI_DITHER_ENABLE ((uint8_t)0x01U) /*!< dither function enable */ +/* dither function */ +#define TLI_DITHER_DISABLE ((uint8_t)0x00U) /*!< dither function disable */ +#define TLI_DITHER_ENABLE ((uint8_t)0x01U) /*!< dither function enable */ /* horizontal pulse polarity selection */ - -#define TLI_HSYN_ACTLIVE_LOW ((uint32_t)0x00000000U) /*!< horizontal synchronous pulse active low */ -#define TLI_HSYN_ACTLIVE_HIGHT TLI_CTL_HPPS /*!< horizontal synchronous pulse active high */ - +#define TLI_HSYN_ACTLIVE_LOW ((uint32_t)0x00000000U) /*!< horizontal synchronous pulse active low */ +#define TLI_HSYN_ACTLIVE_HIGHT TLI_CTL_HPPS /*!< horizontal synchronous pulse active high */ /* vertical pulse polarity selection */ +#define TLI_VSYN_ACTLIVE_LOW ((uint32_t)0x00000000U) /*!< vertical synchronous pulse active low */ +#define TLI_VSYN_ACTLIVE_HIGHT TLI_CTL_VPPS /*!< vertical synchronous pulse active high */ -#define TLI_VSYN_ACTLIVE_LOW ((uint32_t)0x00000000U) /*!< vertical synchronous pulse active low */ -#define TLI_VSYN_ACTLIVE_HIGHT TLI_CTL_VPPS /*!< vertical synchronous pulse active high */ +/* pixel clock polarity selection */ +#define TLI_PIXEL_CLOCK_TLI ((uint32_t)0x00000000U) /*!< pixel clock is TLI clock */ +#define TLI_PIXEL_CLOCK_INVERTEDTLI TLI_CTL_CLKPS /*!< pixel clock is inverted TLI clock */ - -/* pixel Clock Polarity Selection */ - -#define TLI_PIXEL_CLOCK_TLI ((uint32_t)0x00000000U) /*!< pixel clock is TLI clock */ -#define TLI_PIXEL_CLOCK_INVERTEDTLI TLI_CTL_CLKPS /*!< pixel clock is inverted TLI clock */ - - -/* data Enable Polarity Selection */ - -#define TLI_DE_ACTLIVE_LOW ((uint32_t)0x00000000U) /*!< data enable active low */ -#define TLI_DE_ACTLIVE_HIGHT TLI_CTL_DEPS /*!< data enable active high */ +/* data enable polarity selection */ +#define TLI_DE_ACTLIVE_LOW ((uint32_t)0x00000000U) /*!< data enable active low */ +#define TLI_DE_ACTLIVE_HIGHT TLI_CTL_DEPS /*!< data enable active high */ /* alpha calculation factor 1 of blending method */ -#define LxBLEND_ACF1(regval) (BITS(8,10) & ((regval)<<8)) -#define LAYER_ACF1_SA LxBLEND_ACF1(4) /*!< normalization specified alpha */ -#define LAYER_ACF1_PASA LxBLEND_ACF1(6) /*!< normalization pixel alpha * normalization specified alpha */ +#define LxBLEND_ACF1(regval) (BITS(8,10) & ((uint32_t)(regval)<<8)) +#define LAYER_ACF1_SA LxBLEND_ACF1(4) /*!< normalization specified alpha */ +#define LAYER_ACF1_PASA LxBLEND_ACF1(6) /*!< normalization pixel alpha * normalization specified alpha */ + +/* alpha calculation factor 2 of blending method */ +#define LxBLEND_ACF2(regval) (BITS(0,2) & ((uint32_t)(regval))) +#define LAYER_ACF2_SA LxBLEND_ACF2(5) /*!< normalization specified alpha */ +#define LAYER_ACF2_PASA LxBLEND_ACF2(7) /*!< normalization pixel alpha * normalization specified alpha */ -/* alpha calculation factor 2 of blending method*/ -#define LxBLEND_ACF2(regval) (BITS(0,2) & ((regval))) -#define LAYER_ACF2_SA LxBLEND_ACF2(5) /*!< normalization specified alpha */ -#define LAYER_ACF2_PASA LxBLEND_ACF2(7) /*!< normalization pixel alpha x normalization specified alpha */ /* function declarations */ - -/* deinitialize TLI */ +/* initialization functions, TLI enable or disable, TLI reload mode configuration */ +/* deinitialize TLI registers */ void tli_deinit(void); +/* initialize the parameters of TLI parameter structure with the default values, it is suggested + that call this function after a tli_parameter_struct structure is defined */ +void tli_struct_para_init(tli_parameter_struct *tli_struct); /* initialize TLI */ void tli_init(tli_parameter_struct *tli_struct); -/* TLI dither function enable */ -void tli_dither_config(uint8_t ditherstat); +/* configure TLI dither function */ +void tli_dither_config(uint8_t dither_stat); /* enable TLI */ void tli_enable(void); /* disable TLI */ void tli_disable(void); -/* TLI reload mode config*/ -void tli_reload_config(uint8_t reloadmod); +/* configurate TLI reload mode */ +void tli_reload_config(uint8_t reload_mod); -/* TLI interrupt enable */ -void tli_interrupt_enable(uint32_t inttype); -/* TLI interrupt disable */ -void tli_interrupt_disable(uint32_t inttype); -/* get TLI interrupt flag */ -FlagStatus tli_interrupt_flag_get(uint32_t intflag); -/* clear TLI interrupt flag */ -void tli_interrupt_flag_clear(uint32_t intflag); +/* TLI layer configuration functions */ +/* initialize the parameters of TLI layer structure with the default values, it is suggested + that call this function after a tli_layer_parameter_struct structure is defined */ +void tli_layer_struct_para_init(tli_layer_parameter_struct *layer_struct); +/* initialize TLI layer */ +void tli_layer_init(uint32_t layerx,tli_layer_parameter_struct *layer_struct); +/* reconfigure window position */ +void tli_layer_window_offset_modify(uint32_t layerx,uint16_t offset_x,uint16_t offset_y); +/* initialize the parameters of TLI layer LUT structure with the default values, it is suggested + that call this function after a tli_layer_lut_parameter_struct structure is defined */ +void tli_lut_struct_para_init(tli_layer_lut_parameter_struct *lut_struct); +/* initialize TLI layer LUT */ +void tli_lut_init(uint32_t layerx,tli_layer_lut_parameter_struct *lut_struct); +/* initialize TLI layer color key */ +void tli_color_key_init(uint32_t layerx,uint8_t redkey,uint8_t greenkey,uint8_t bluekey); +/* enable TLI layer */ +void tli_layer_enable(uint32_t layerx); +/* disable TLI layer */ +void tli_layer_disable(uint32_t layerx); +/* enable TLI layer color keying */ +void tli_color_key_enable(uint32_t layerx); +/* disable TLI layer color keying */ +void tli_color_key_disable(uint32_t layerx); +/* enable TLI layer LUT */ +void tli_lut_enable(uint32_t layerx); +/* disable TLI layer LUT */ +void tli_lut_disable(uint32_t layerx); /* set line mark value */ -void tli_line_mark_set(uint32_t linenum); +void tli_line_mark_set(uint16_t line_num); /* get current displayed position */ uint32_t tli_current_pos_get(void); -/* get TLI state */ -FlagStatus tli_flag_get(uint32_t state); -/* TLI layer enable */ -void tli_layer_enable(uint32_t layerx); -/* TLI layer disable */ -void tli_layer_disable(uint32_t layerx); -/* TLI layer color keying enable */ -void tli_color_key_enable(uint32_t layerx); -/* TLI layer color keying disable */ -void tli_color_key_disable(uint32_t layerx); -/* TLI layer LUT enable */ -void tli_lut_enable(uint32_t layerx); -/* TLI layer LUT disable */ -void tli_lut_disable(uint32_t layerx); -/* TLI layer initialize */ -void tli_layer_init(uint32_t layerx,tli_layer_parameter_struct *layer_struct); -/* TLI layer initialize */ -void tli_layer_window_offset_modify(uint32_t layerx,uint32_t offset_x,uint32_t offset_y); -/* TLI layer lut initialize */ -void tli_lut_init(uint32_t layerx,tli_layer_lut_parameter_struct *lut_struct); -/* TLI layer key initialize */ -void tli_ckey_init(uint32_t layerx,uint32_t redkey,uint32_t greenkey,uint32_t bluekey); +/* flag and interrupt functions */ +/* enable TLI interrupt */ +void tli_interrupt_enable(uint32_t int_flag); +/* disable TLI interrupt */ +void tli_interrupt_disable(uint32_t int_flag); +/* get TLI interrupt flag */ +FlagStatus tli_interrupt_flag_get(uint32_t int_flag); +/* clear TLI interrupt flag */ +void tli_interrupt_flag_clear(uint32_t int_flag); +/* get TLI flag or state in TLI_INTF register or TLI_STAT register */ +FlagStatus tli_flag_get(uint32_t flag); #endif /* GD32F4XX_TLI_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_trng.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_trng.h index 7925b91af3..f321b15d28 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_trng.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_trng.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_trng.h - \brief definitions for the TRNG + \file gd32f4xx_trng.h + \brief definitions for the TRNG + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_TRNG_H @@ -14,13 +39,13 @@ #include "gd32f4xx.h" -/* EXTI definitions */ +/* TRNG definitions */ #define TRNG TRNG_BASE /* registers definitions */ -#define TRNG_CTL REG32(TRNG + 0x00U) /*!< interrupt enable register */ -#define TRNG_STAT REG32(TRNG + 0x04U) /*!< event enable register */ -#define TRNG_DATA REG32(TRNG + 0x08U) /*!< rising edge trigger enable register */ +#define TRNG_CTL REG32(TRNG + 0x00U) /*!< control register */ +#define TRNG_STAT REG32(TRNG + 0x04U) /*!< status register */ +#define TRNG_DATA REG32(TRNG + 0x08U) /*!< data register */ /* bits definitions */ /* TRNG_CTL */ @@ -40,7 +65,7 @@ /* constants definitions */ /* trng status flag */ typedef enum -{ +{ TRNG_FLAG_DRDY = TRNG_STAT_DRDY, /*!< random Data ready status */ TRNG_FLAG_CECS = TRNG_STAT_CECS, /*!< clock error current status */ TRNG_FLAG_SECS = TRNG_STAT_SECS /*!< seed error current status */ @@ -54,6 +79,7 @@ typedef enum }trng_int_flag_enum; /* function declarations */ +/* initialization functions */ /* deinitialize the TRNG */ void trng_deinit(void); /* enable the TRNG interface */ @@ -62,14 +88,14 @@ void trng_enable(void); void trng_disable(void); /* get the true random data */ uint32_t trng_get_true_random_data(void); + +/* flag & interrupt functions */ +/* trng interrupt enable */ +void trng_interrupt_enable(void); +/* trng interrupt disable */ +void trng_interrupt_disable(void); /* get the trng status flags */ FlagStatus trng_flag_get(trng_flag_enum flag); -/* clear the trng status flags */ -void trng_flag_clear(trng_flag_enum flag); -/* the trng interrupt enable */ -void trng_interrupt_enable(void); -/* the trng interrupt disable */ -void trng_interrupt_disable(void); /* get the trng interrupt flags */ FlagStatus trng_interrupt_flag_get(trng_int_flag_enum int_flag); /* clear the trng interrupt flags */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_usart.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_usart.h index 5350f5e5b5..3cd49d827f 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_usart.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_usart.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_usart.h - \brief definitions for the USART + \file gd32f4xx_usart.h + \brief definitions for the USART + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_USART_H @@ -14,8 +39,8 @@ #include "gd32f4xx.h" -/* USARTx(x=0,1) definitions */ -#define USART1 USART_BASE +/* USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) definitions */ +#define USART1 USART_BASE /*!< USART1 base address */ #define USART2 (USART_BASE+0x00000400U) /*!< USART2 base address */ #define UART3 (USART_BASE+0x00000800U) /*!< UART3 base address */ #define UART4 (USART_BASE+0x00000C00U) /*!< UART4 base address */ @@ -102,7 +127,7 @@ /* USARTx_GP */ #define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ #define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ - + /* USARTx_CTL3 */ #define USART_CTL3_RTEN BIT(0) /*!< receiver timeout enable */ #define USART_CTL3_SCRTNUM BITS(1,3) /*!< smartcard auto-retry number */ @@ -131,59 +156,85 @@ /* constants definitions */ /* define the USART bit position and its register index offset */ #define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define USART_REG_VAL(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 6))) +#define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & 0xFFFFU) >> 6))) #define USART_BIT_POS(val) ((uint32_t)(val) & 0x1FU) +#define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ + | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) +#define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22))) +#define USART_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16) /* register offset */ -#define STAT0_REG_OFFSET 0x00U /*!< STAT0 register offset */ -#define STAT1_REG_OFFSET 0x88U /*!< STAT1 register offset */ -#define CHC_REG_OFFSET 0xC0U /*!< CHC register offset */ -#define CTL0_REG_OFFSET 0x0CU /*!< CTL0 register offset */ -#define CTL1_REG_OFFSET 0x10U /*!< CTL1 register offset */ -#define CTL2_REG_OFFSET 0x14U /*!< CTL2 register offset */ -#define CTL3_REG_OFFSET 0x80U /*!< CTL2 register offset */ +#define USART_STAT0_REG_OFFSET 0x00U /*!< STAT0 register offset */ +#define USART_STAT1_REG_OFFSET 0x88U /*!< STAT1 register offset */ +#define USART_CTL0_REG_OFFSET 0x0CU /*!< CTL0 register offset */ +#define USART_CTL1_REG_OFFSET 0x10U /*!< CTL1 register offset */ +#define USART_CTL2_REG_OFFSET 0x14U /*!< CTL2 register offset */ +#define USART_CTL3_REG_OFFSET 0x80U /*!< CTL3 register offset */ +#define USART_CHC_REG_OFFSET 0xC0U /*!< CHC register offset */ /* USART flags */ typedef enum { /* flags in STAT0 register */ - USART_FLAG_CTSF = USART_REGIDX_BIT(STAT0_REG_OFFSET, 9U), /*!< CTS change flag */ - USART_FLAG_LBDF = USART_REGIDX_BIT(STAT0_REG_OFFSET, 8U), /*!< LIN break detected flag */ - USART_FLAG_TBE = USART_REGIDX_BIT(STAT0_REG_OFFSET, 7U), /*!< transmit data buffer empty */ - USART_FLAG_TC = USART_REGIDX_BIT(STAT0_REG_OFFSET, 6U), /*!< transmission complete */ - USART_FLAG_RBNE = USART_REGIDX_BIT(STAT0_REG_OFFSET, 5U), /*!< read data buffer not empty */ - USART_FLAG_IDLEF = USART_REGIDX_BIT(STAT0_REG_OFFSET, 4U), /*!< IDLE frame detected flag */ - USART_FLAG_ORERR = USART_REGIDX_BIT(STAT0_REG_OFFSET, 3U), /*!< overrun error */ - USART_FLAG_NERR = USART_REGIDX_BIT(STAT0_REG_OFFSET, 2U), /*!< noise error flag */ - USART_FLAG_FERR = USART_REGIDX_BIT(STAT0_REG_OFFSET, 1U), /*!< frame error flag */ - USART_FLAG_PERR = USART_REGIDX_BIT(STAT0_REG_OFFSET, 0U), /*!< parity error flag */ + USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 9U), /*!< CTS change flag */ + USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 8U), /*!< LIN break detected flag */ + USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 7U), /*!< transmit data buffer empty */ + USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 6U), /*!< transmission complete */ + USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 5U), /*!< read data buffer not empty */ + USART_FLAG_IDLE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 4U), /*!< IDLE frame detected flag */ + USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 3U), /*!< overrun error */ + USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 2U), /*!< noise error flag */ + USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 1U), /*!< frame error flag */ + USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 0U), /*!< parity error flag */ /* flags in STAT1 register */ - USART_FLAG_BSY = USART_REGIDX_BIT(STAT1_REG_OFFSET, 16U), /*!< busy flag */ - USART_FLAG_EBF = USART_REGIDX_BIT(STAT1_REG_OFFSET, 12U), /*!< end of block flag */ - USART_FLAG_RTF = USART_REGIDX_BIT(STAT1_REG_OFFSET, 11U), /*!< receiver timeout flag */ + USART_FLAG_BSY = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 16U), /*!< busy flag */ + USART_FLAG_EB = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 12U), /*!< end of block flag */ + USART_FLAG_RT = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 11U), /*!< receiver timeout flag */ /* flags in CHC register */ - USART_FLAG_EPERR = USART_REGIDX_BIT(CHC_REG_OFFSET, 8U), /*!< early parity error flag */ + USART_FLAG_EPERR = USART_REGIDX_BIT(USART_CHC_REG_OFFSET, 8U), /*!< early parity error flag */ }usart_flag_enum; /* USART interrupt flags */ typedef enum { /* interrupt flags in CTL0 register */ - USART_INT_PERRIE = USART_REGIDX_BIT(CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */ - USART_INT_TBEIE = USART_REGIDX_BIT(CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */ - USART_INT_TCIE = USART_REGIDX_BIT(CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */ - USART_INT_RBNEIE = USART_REGIDX_BIT(CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */ - USART_INT_IDLEIE = USART_REGIDX_BIT(CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */ + USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT0_REG_OFFSET, 0U), /*!< parity error interrupt and flag */ + USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */ + USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT0_REG_OFFSET, 6U), /*!< transmission complete interrupt and flag */ + USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and flag */ + USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT0_REG_OFFSET, 3U), /*!< read data buffer not empty interrupt and overrun error flag */ + USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt and flag */ /* interrupt flags in CTL1 register */ - USART_INT_LBDIE = USART_REGIDX_BIT(CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */ + USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT0_REG_OFFSET, 8U), /*!< LIN break detected interrupt and flag */ /* interrupt flags in CTL2 register */ - USART_INT_CTSIE = USART_REGIDX_BIT(CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */ - USART_INT_ERRIE = USART_REGIDX_BIT(CTL2_REG_OFFSET, 0U), /*!< error interrupt */ + USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT0_REG_OFFSET, 9U), /*!< CTS interrupt and flag */ + USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 3U), /*!< error interrupt and overrun error */ + USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 2U), /*!< error interrupt and noise error flag */ + USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 1U), /*!< error interrupt and frame error flag */ /* interrupt flags in CTL3 register */ - USART_INT_EBIE = USART_REGIDX_BIT(CTL3_REG_OFFSET, 5U), /*!< interrupt enable bit of end of block event */ - USART_INT_RTIE = USART_REGIDX_BIT(CTL3_REG_OFFSET, 4U), /*!< interrupt enable bit of receive timeout event */ + USART_INT_FLAG_EB = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 5U, USART_STAT1_REG_OFFSET, 12U), /*!< interrupt enable bit of end of block event and flag */ + USART_INT_FLAG_RT = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 4U, USART_STAT1_REG_OFFSET, 11U), /*!< interrupt enable bit of receive timeout event and flag */ }usart_interrupt_flag_enum; +/* USART interrupt flags */ +typedef enum +{ + /* interrupt in CTL0 register */ + USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */ + USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */ + USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */ + USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */ + USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */ + /* interrupt in CTL1 register */ + USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */ + /* interrupt in CTL2 register */ + USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */ + USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U), /*!< error interrupt */ + /* interrupt in CTL3 register */ + USART_INT_EB = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 5U), /*!< interrupt enable bit of end of block event */ + USART_INT_RT = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 4U), /*!< interrupt enable bit of receive timeout event */ +}usart_interrupt_enum; + /* USART invert configure */ typedef enum { @@ -211,8 +262,8 @@ typedef enum /* USART parity bits definitions */ #define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9)) #define USART_PM_NONE CTL0_PM(0) /*!< no parity */ -#define USART_PM_ODD CTL0_PM(2) /*!< odd parity */ -#define USART_PM_EVEN CTL0_PM(3) /*!< even parity */ +#define USART_PM_EVEN CTL0_PM(2) /*!< even parity */ +#define USART_PM_ODD CTL0_PM(3) /*!< odd parity */ /* USART wakeup method in mute mode */ #define CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11)) @@ -306,30 +357,6 @@ typedef enum #define USART_HCM_NONE CHC_HCM(0) /*!< nRTS signal equals to the rxne status register */ #define USART_HCM_EN CHC_HCM(1) /*!< nRTS signal is set when the last data bit has been sampled */ -/* interrupt enable in USART_CTL0 */ -#define USART_INTEN_PERRIE ((uint32_t)0x10000100U) /*!< parity error interrupt */ -#define USART_INTEN_TBEIE ((uint32_t)0x10000080U) /*!< transmitter buffer empty interrupt */ -#define USART_INTEN_TCIE ((uint32_t)0x10000040U) /*!< transmission complete interrupt */ -#define USART_INTEN_RBNEIE ((uint32_t)0x10000020U) /*!< read data buffer not empty interrupt and overrun error interrupt */ -#define USART_INTEN_IDLEIE ((uint32_t)0x10000010U) /*!< IDLE line detected interrupt */ - -/* interrupt enable flag in USART_CTL1 */ -#define USART_INTEN_LBDIE ((uint32_t)0x20000040U) /*!< LIN break detected interrupt */ - -/* interrupt enable flag in USART_CTL2 */ -#define USART_INTEN_ERRIE ((uint32_t)0x40000001U) /*!< error interrupt */ -#define USART_INTEN_CTSIE ((uint32_t)0x40000400U) /*!< CTS interrupt*/ - -/* interrupt enable flag in USART_CTL3 */ -#define USART_INTEN_RTIE ((uint32_t)0x80000010U) /*!< interrupt enable bit of receive timeout event */ -#define USART_INTEN_EBIE ((uint32_t)0x80000020U) /*!< interrupt enable bit of end of block event */ - -#define USART_INTEN_MASK ((uint32_t)0x00000FFFU) /*!< USART interrupt mask */ -#define USART_INTS_CTL0 ((uint32_t)0x10000000U) /*!< interrupt in USART_CTL0 */ -#define USART_INTS_CTL1 ((uint32_t)0x20000000U) /*!< interrupt in USART_CTL1 */ -#define USART_INTS_CTL2 ((uint32_t)0x40000000U) /*!< interrupt in USART_CTL2 */ -#define USART_INTS_CTL3 ((uint32_t)0x80000000U) /*!< interrupt in USART_CTL3 */ - /* function declarations */ /* initialization functions */ /* reset USART */ @@ -342,8 +369,6 @@ void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg); void usart_word_length_set(uint32_t usart_periph, uint32_t wlen); /* configure usart stop bit length */ void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen); - -/* USART normal mode communication */ /* enable usart */ void usart_enable(uint32_t usart_periph); /* disable usart */ @@ -352,6 +377,8 @@ void usart_disable(uint32_t usart_periph); void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig); /* configure USART receiver */ void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig); + +/* USART normal mode communication */ /* data is transmitted/received with the LSB/MSB first */ void usart_data_first_config(uint32_t usart_periph, uint32_t msbf); /* configure USART inverted */ @@ -382,43 +409,43 @@ void usart_mute_mode_disable(uint32_t usart_periph); void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmehtod); /* LIN mode communication */ -/* LIN mode enable */ +/* enable LIN mode */ void usart_lin_mode_enable(uint32_t usart_periph); -/* LIN mode disable */ +/* disable LIN mode */ void usart_lin_mode_disable(uint32_t usart_periph); /* LIN break detection length */ -void usart_lin_break_dection_length_config(uint32_t usart_periph, uint32_t lblen); +void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen); /* send break frame */ void usart_send_break(uint32_t usart_periph); /* half-duplex communication */ -/* half-duplex enable */ +/* enable half-duplex mode */ void usart_halfduplex_enable(uint32_t usart_periph); -/* half-duplex disable */ +/* disable half-duplex mode */ void usart_halfduplex_disable(uint32_t usart_periph); /* synchronous communication */ -/* clock enable */ +/* enable CK pin in synchronous mode */ void usart_synchronous_clock_enable(uint32_t usart_periph); -/* clock disable */ +/* disable CK pin in synchronous mode */ void usart_synchronous_clock_disable(uint32_t usart_periph); /* configure usart synchronous mode parameters */ void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl); /* smartcard communication */ -/* guard time value configure in smartcard mode */ -void usart_guard_time_config(uint32_t usart_periph,uint32_t gaut); -/* smartcard mode enable */ +/* configure guard time value in smartcard mode */ +void usart_guard_time_config(uint32_t usart_periph, uint32_t guat); +/* enable smartcard mode */ void usart_smartcard_mode_enable(uint32_t usart_periph); -/* smartcard mode disable */ +/* disable smartcard mode */ void usart_smartcard_mode_disable(uint32_t usart_periph); -/* NACK enable in smartcard mode */ +/* enable NACK in smartcard mode */ void usart_smartcard_mode_nack_enable(uint32_t usart_periph); -/* NACK disable in smartcard mode */ +/* disable NACK in smartcard mode */ void usart_smartcard_mode_nack_disable(uint32_t usart_periph); -/* smartcard auto-retry number configure */ +/* configure smartcard auto-retry number */ void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum); -/* block length configure */ +/* configure block length */ void usart_block_length_config(uint32_t usart_periph, uint32_t bl); /* IrDA communication */ @@ -427,7 +454,7 @@ void usart_irda_mode_enable(uint32_t usart_periph); /* disable IrDA mode */ void usart_irda_mode_disable(uint32_t usart_periph); /* configure the peripheral clock prescaler */ -void usart_prescaler_config(uint32_t usart_periph, uint32_t psc); +void usart_prescaler_config(uint32_t usart_periph, uint8_t psc); /* configure IrDA low-power */ void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp); @@ -445,23 +472,24 @@ void usart_parity_check_coherence_config(uint32_t usart_periph, uint32_t pcm); /* configure hardware flow control coherence mode */ void usart_hardware_flow_coherence_config(uint32_t usart_periph, uint32_t hcm); +/* DMA communication */ /* configure USART DMA for reception */ void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd); /* configure USART DMA for transmission */ void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd); -/* flag functions */ -/* get flag in STAT0/STAT1/CHC register */ +/* flag & interrupt functions */ +/* get flag in STAT0/STAT1 register */ FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag); -/* clear flag in STAT0/STAT1/CHC register */ +/* clear flag in STAT0/STAT1 register */ void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag); - -/* interrupt functions */ /* enable USART interrupt */ -void usart_interrupt_enable(uint32_t usart_periph, uint32_t int_flag); +void usart_interrupt_enable(uint32_t usart_periph, usart_interrupt_enum interrupt); /* disable USART interrupt */ -void usart_interrupt_disable(uint32_t usart_periph, uint32_t int_flag); -/* get USART interrupt enable flag */ -FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag); +void usart_interrupt_disable(uint32_t usart_periph, usart_interrupt_enum interrupt); +/* get USART interrupt and flag status */ +FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_enum int_flag); +/* clear interrupt flag in STAT0/STAT1 register */ +void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum int_flag); -#endif /* GD32F4XX_USART_H */ +#endif /* GD32F4XX_USART_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_wwdgt.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_wwdgt.h index d76cbce32c..525b9a6e5a 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_wwdgt.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_wwdgt.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_wwdgt.h - \brief definitions for the WWDGT + \file gd32f4xx_wwdgt.h + \brief definitions for the WWDGT + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_WWDGT_H diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_adc.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_adc.c index 73f89207ba..f249e6c840 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_adc.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_adc.c @@ -1,24 +1,67 @@ /*! - \file gd32f4xx_adc.c - \brief ADC driver + \file gd32f4xx_adc.c + \brief ADC driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_adc.h" -#define REGULAR_CHANNEL_LENGTH_OFFSET ((uint32_t)20U) -#define INSERTED_CHANNEL_LENGTH_OFFSET ((uint32_t)20U) -#define REGULAR_DISCONTINUOUS_NUMBER ((uint32_t)13U) #define REGULAR_TRIGGER_MODE ((uint32_t)28U) #define INSERTED_TRIGGER_MODE ((uint32_t)20U) +/* discontinuous mode macro*/ +#define ADC_CHANNEL_LENGTH_SUBTRACT_ONE ((uint8_t)1U) + +/* ADC regular channel macro */ +#define ADC_REGULAR_CHANNEL_RANK_SIX ((uint8_t)6U) +#define ADC_REGULAR_CHANNEL_RANK_TWELVE ((uint8_t)12U) +#define ADC_REGULAR_CHANNEL_RANK_SIXTEEN ((uint8_t)16U) +#define ADC_REGULAR_CHANNEL_RANK_LENGTH ((uint8_t)5U) + +/* ADC sampling time macro */ +#define ADC_CHANNEL_SAMPLE_TEN ((uint8_t)10U) +#define ADC_CHANNEL_SAMPLE_EIGHTEEN ((uint8_t)18U) +#define ADC_CHANNEL_SAMPLE_LENGTH ((uint8_t)3U) + +/* ADC inserted channel macro */ +#define ADC_INSERTED_CHANNEL_RANK_LENGTH ((uint8_t)5U) +#define ADC_INSERTED_CHANNEL_SHIFT_LENGTH ((uint8_t)15U) + +/* ADC inserted channel offset macro */ +#define ADC_OFFSET_LENGTH ((uint8_t)3U) +#define ADC_OFFSET_SHIFT_LENGTH ((uint8_t)4U) /*! - \brief ADC reset + \brief reset ADC \param[in] none \param[out] none \retval none @@ -29,189 +72,10 @@ void adc_deinit(void) rcu_periph_reset_disable(RCU_ADCRST); } -/*! - \brief enable ADC interface - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] none - \param[out] none - \retval none -*/ -void adc_enable(uint32_t adc_periph) -{ - if(RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)){ - ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ADCON; - } -} - -/*! - \brief disable ADC interface - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] none - \param[out] none - \retval none -*/ -void adc_disable(uint32_t adc_periph) -{ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ADCON); -} - -/*! - \brief ADC data alignment config - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] inserted_channel : insert channel select - \arg ADC_DATAALIGN_RIGHT: LSB alignment - \arg ADC_DATAALIGN_LEFT: MSB alignment - \param[out] none - \retval none -*/ -void adc_data_alignment_config(uint32_t adc_periph , uint8_t data_alignment) -{ - if(data_alignment){ - ADC_CTL1(adc_periph) |= ADC_CTL1_DAL; - }else{ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DAL); - } -} - -/*! - \brief ADC resolution config - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] resolution: ADC resolution - \arg ADC_RESOLUTION_12B: 12-bit ADC resolution - \arg ADC_RESOLUTION_10B: 10-bit ADC resolution - \arg ADC_RESOLUTION_8B: 8-bit ADC resolution - \arg ADC_RESOLUTION_6B: 6-bit ADC resolution - \param[out] none - \retval none -*/ -void adc_resolution_config(uint32_t adc_periph , uint32_t resolution) -{ - ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DRES); - ADC_CTL0(adc_periph) |= (uint32_t)resolution; -} - -/*! - \brief ADC calibration and reset calibration - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] none - \param[out] none - \retval none -*/ -void adc_calibration_enable(uint32_t adc_periph) -{ - /* reset the selected ADC1 calibration registers */ - ADC_CTL1(adc_periph) |= (uint32_t) ADC_CTL1_RSTCLB; - /* check the RSTCLB bit state */ - while((ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)){ - } - /* enable ADC calibration process */ - ADC_CTL1(adc_periph) |= ADC_CTL1_CLB; - /* check the CLB bit state */ - while((ADC_CTL1(adc_periph) & ADC_CTL1_CLB)){ - } -} - -/*! - \brief ADC discontinuous mode config - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_channel_group: select the channel group - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[in] length: number of conversions in discontinuous mode,the number can be 1..8 - for regular channel ,the number is no effect for inserted channel - \param[out] none - \retval none -*/ -void adc_discontinuous_mode_config(uint32_t adc_periph , uint8_t adc_channel_group , uint8_t length) -{ - ADC_CTL0(adc_periph) &= ~((uint32_t)( ADC_CTL0_DISRC | ADC_CTL0_DISIC )); - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: - /* config the number of conversions in discontinuous mode */ - ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DISNUM); - if((length <= 8U) && (length >= 1U)){ - ADC_CTL0(adc_periph) |= ((uint32_t)length - 1U) << REGULAR_DISCONTINUOUS_NUMBER; - } - ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISRC; - break; - case ADC_INSERTED_CHANNEL: - ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISIC; - break; - default: - break; - } -} - -/*! - \brief config end of conversion mode - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] end_selection: end of conversion mode - \arg ADC_EOC_SET_SEQUENCE: only at the end of a sequence of regular conversions, the EOC bit is set - \arg ADC_EOC_SET_CONVERSION: at the end of each regular conversion, the EOC bit is set. - \param[out] none - \retval none -*/ -void adc_end_of_conversion_config(uint32_t adc_periph , uint8_t end_selection) -{ - switch(end_selection){ - case ADC_EOC_SET_SEQUENCE: - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_EOCM); - break; - case ADC_EOC_SET_CONVERSION: - ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_EOCM); - break; - default: - break; - } -} - -/*! - \brief ADC special function enable or disable - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] function: select the function to config - \arg ADC_SCAN_MODE: scan mode select - \arg ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically - \arg ADC_CONTINUOUS_MODE: continuous mode select - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void adc_special_function_config(uint32_t adc_periph , uint8_t function , ControlStatus newvalue) -{ - if(newvalue){ - switch(function){ - case ADC_SCAN_MODE: - ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_SM; - break; - case ADC_INSERTED_CHANNEL_AUTO: - ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_ICA; - break; - case ADC_CONTINUOUS_MODE: - ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_CTN; - break; - default: - break; - } - }else{ - switch(function){ - case ADC_SCAN_MODE: - ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_SM); - break; - case ADC_INSERTED_CHANNEL_AUTO: - ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_ICA); - break; - case ADC_CONTINUOUS_MODE: - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_CTN); - break; - default: - break; - } - } -} - /*! \brief configure the ADC clock for all the ADCs \param[in] prescaler: configure ADCs prescaler ratio + only one parameter can be selected which is shown as below: \arg ADC_ADCCK_PCLK2_DIV2: PCLK2 div2 \arg ADC_ADCCK_PCLK2_DIV4: PCLK2 div4 \arg ADC_ADCCK_PCLK2_DIV6: PCLK2 div6 @@ -230,45 +94,320 @@ void adc_clock_config(uint32_t prescaler) } /*! - \brief configure the ADC clock for all the ADCs - \param[in] function: temperature sensor and internal reference voltage channel or VBAT channel + \brief enable or disable ADC special function + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] function: the function to config + only one parameter can be selected which is shown as below: + \arg ADC_SCAN_MODE: scan mode select + \arg ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically + \arg ADC_CONTINUOUS_MODE: continuous mode select + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void adc_special_function_config(uint32_t adc_periph , uint32_t function , ControlStatus newvalue) +{ + if(newvalue){ + if(0U != (function & ADC_SCAN_MODE)){ + /* enable scan mode */ + ADC_CTL0(adc_periph) |= ADC_SCAN_MODE; + } + if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){ + /* enable inserted channel group convert automatically */ + ADC_CTL0(adc_periph) |= ADC_INSERTED_CHANNEL_AUTO; + } + if(0U != (function & ADC_CONTINUOUS_MODE)){ + /* enable continuous mode */ + ADC_CTL1(adc_periph) |= ADC_CONTINUOUS_MODE; + } + }else{ + if(0U != (function & ADC_SCAN_MODE)){ + /* disable scan mode */ + ADC_CTL0(adc_periph) &= ~ADC_SCAN_MODE; + } + if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){ + /* disable inserted channel group convert automatically */ + ADC_CTL0(adc_periph) &= ~ADC_INSERTED_CHANNEL_AUTO; + } + if(0U != (function & ADC_CONTINUOUS_MODE)){ + /* disable continuous mode */ + ADC_CTL1(adc_periph) &= ~ADC_CONTINUOUS_MODE; + } + } +} + +/*! + \brief configure ADC data alignment + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] data_alignment: data alignment select + only one parameter can be selected which is shown as below: + \arg ADC_DATAALIGN_RIGHT: LSB alignment + \arg ADC_DATAALIGN_LEFT: MSB alignment + \param[out] none + \retval none +*/ +void adc_data_alignment_config(uint32_t adc_periph , uint32_t data_alignment) +{ + if(ADC_DATAALIGN_RIGHT != data_alignment){ + /* MSB alignment */ + ADC_CTL1(adc_periph) |= ADC_CTL1_DAL; + }else{ + /* LSB alignment */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DAL); + } +} + +/*! + \brief enable ADC interface + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none +*/ +void adc_enable(uint32_t adc_periph) +{ + if(RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)){ + /* enable ADC */ + ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ADCON; + } +} + +/*! + \brief disable ADC interface + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none +*/ +void adc_disable(uint32_t adc_periph) +{ + /* disable ADC */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ADCON); +} + +/*! + \brief ADC calibration and reset calibration + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none +*/ +void adc_calibration_enable(uint32_t adc_periph) +{ + /* reset the selected ADC calibration registers */ + ADC_CTL1(adc_periph) |= (uint32_t) ADC_CTL1_RSTCLB; + /* check the RSTCLB bit state */ + while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)){ + } + /* enable ADC calibration process */ + ADC_CTL1(adc_periph) |= ADC_CTL1_CLB; + /* check the CLB bit state */ + while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_CLB)){ + } +} + +/*! + \brief configure temperature sensor and internal reference voltage channel or VBAT channel function + \param[in] function: temperature sensor and internal reference voltage channel or VBAT channel + only one parameter can be selected which is shown as below: \arg ADC_VBAT_CHANNEL_SWITCH: channel 18 (1/4 voltate of external battery) switch of ADC0 \arg ADC_TEMP_VREF_CHANNEL_SWITCH: channel 16 (temperature sensor) and 17 (internal reference voltage) switch of ADC0 \param[in] newvalue: ENABLE or DISABLE \param[out] none \retval none */ -void adc_channel_16_to_18(uint8_t function,ControlStatus newvalue) +void adc_channel_16_to_18(uint32_t function, ControlStatus newvalue) { if(newvalue){ - switch(function){ - case ADC_VBAT_CHANNEL_SWITCH: - ADC_SYNCCTL |= (uint32_t)ADC_SYNCCTL_VBATEN; - break; - case ADC_TEMP_VREF_CHANNEL_SWITCH: - ADC_SYNCCTL |= (uint32_t)ADC_SYNCCTL_TSVREN; - break; - default: - break; + if(RESET != (function & ADC_VBAT_CHANNEL_SWITCH)){ + /* enable ADC0 Vbat channel */ + ADC_SYNCCTL |= ADC_VBAT_CHANNEL_SWITCH; + } + if(RESET != (function & ADC_TEMP_VREF_CHANNEL_SWITCH)){ + /* enable ADC0 Vref and Temperature channel */ + ADC_SYNCCTL |= ADC_TEMP_VREF_CHANNEL_SWITCH; } }else{ - switch(function){ - case ADC_VBAT_CHANNEL_SWITCH: - ADC_SYNCCTL &= ~((uint32_t)ADC_SYNCCTL_VBATEN); - break; - case ADC_TEMP_VREF_CHANNEL_SWITCH: - ADC_SYNCCTL &= ~((uint32_t)ADC_SYNCCTL_TSVREN); - break; - default: - break; + if(RESET != (function & ADC_VBAT_CHANNEL_SWITCH)){ + /* disable ADC0 Vbat channel */ + ADC_SYNCCTL &= ~ADC_VBAT_CHANNEL_SWITCH; + } + if(RESET != (function & ADC_TEMP_VREF_CHANNEL_SWITCH)){ + /* disable ADC0 Vref and Temperature channel */ + ADC_SYNCCTL &= ~ADC_TEMP_VREF_CHANNEL_SWITCH; } } } /*! - \brief config the length of regular channel group or inserted channel group + \brief configure ADC resolution + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] resolution: ADC resolution + only one parameter can be selected which is shown as below: + \arg ADC_RESOLUTION_12B: 12-bit ADC resolution + \arg ADC_RESOLUTION_10B: 10-bit ADC resolution + \arg ADC_RESOLUTION_8B: 8-bit ADC resolution + \arg ADC_RESOLUTION_6B: 6-bit ADC resolution + \param[out] none + \retval none +*/ +void adc_resolution_config(uint32_t adc_periph , uint32_t resolution) +{ + ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DRES); + ADC_CTL0(adc_periph) |= (uint32_t)resolution; +} + +/*! + \brief configure ADC oversample mode + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] mode: ADC oversampling mode + only one parameter can be selected which is shown as below: + \arg ADC_OVERSAMPLING_ALL_CONVERT: all oversampled conversions for a channel are done consecutively after a trigger + \arg ADC_OVERSAMPLING_ONE_CONVERT: each oversampled conversion for a channel needs a trigger + \param[in] shift: ADC oversampling shift + only one parameter can be selected which is shown as below: + \arg ADC_OVERSAMPLING_SHIFT_NONE: no oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_1B: 1-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_2B: 2-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_3B: 3-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_4B: 3-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_5B: 5-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_6B: 6-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_7B: 7-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_8B: 8-bit oversampling shift + \param[in] ratio: ADC oversampling ratio + only one parameter can be selected which is shown as below: + \arg ADC_OVERSAMPLING_RATIO_MUL2: oversampling ratio multiple 2 + \arg ADC_OVERSAMPLING_RATIO_MUL4: oversampling ratio multiple 4 + \arg ADC_OVERSAMPLING_RATIO_MUL8: oversampling ratio multiple 8 + \arg ADC_OVERSAMPLING_RATIO_MUL16: oversampling ratio multiple 16 + \arg ADC_OVERSAMPLING_RATIO_MUL32: oversampling ratio multiple 32 + \arg ADC_OVERSAMPLING_RATIO_MUL64: oversampling ratio multiple 64 + \arg ADC_OVERSAMPLING_RATIO_MUL128: oversampling ratio multiple 128 + \arg ADC_OVERSAMPLING_RATIO_MUL256: oversampling ratio multiple 256 + \param[out] none + \retval none +*/ +void adc_oversample_mode_config(uint32_t adc_periph , uint32_t mode , uint16_t shift , uint8_t ratio) +{ + if(ADC_OVERSAMPLING_ONE_CONVERT == mode){ + ADC_OVSAMPCTL(adc_periph) |= (uint32_t)ADC_OVSAMPCTL_TOVS; + }else{ + ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_TOVS); + } + /* config the shift and ratio */ + ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)(ADC_OVSAMPCTL_OVSR | ADC_OVSAMPCTL_OVSS)); + ADC_OVSAMPCTL(adc_periph) |= ((uint32_t)shift | (uint32_t)ratio); +} + +/*! + \brief enable ADC oversample mode + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none +*/ +void adc_oversample_mode_enable(uint32_t adc_periph) +{ + ADC_OVSAMPCTL(adc_periph) |= ADC_OVSAMPCTL_OVSEN; +} + +/*! + \brief disable ADC oversample mode + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none +*/ +void adc_oversample_mode_disable(uint32_t adc_periph) +{ + ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_OVSEN); +} + +/*! + \brief enable DMA request + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none +*/ +void adc_dma_mode_enable(uint32_t adc_periph) +{ + /* enable DMA request */ + ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_DMA); +} + +/*! + \brief disable DMA request + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none +*/ +void adc_dma_mode_disable(uint32_t adc_periph) +{ + /* disable DMA request */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DMA); +} + +/*! + \brief when DMA=1, the DMA engine issues a request at end of each regular conversion + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none +*/ +void adc_dma_request_after_last_enable(uint32_t adc_periph) +{ + ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_DDM); +} + +/*! + \brief the DMA engine is disabled after the end of transfer signal from DMA controller is detected + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none +*/ +void adc_dma_request_after_last_disable(uint32_t adc_periph) +{ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DDM); +} + +/*! + \brief configure ADC discontinuous mode \param[in] adc_periph: ADCx,x=0,1,2 \param[in] adc_channel_group: select the channel group + only one parameter can be selected which is shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \arg ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of regular & inserted channel + \param[in] length: number of conversions in discontinuous mode,the number can be 1..8 + for regular channel ,the number has no effect for inserted channel + \param[out] none + \retval none +*/ +void adc_discontinuous_mode_config(uint32_t adc_periph , uint8_t adc_channel_group , uint8_t length) +{ + /* disable discontinuous mode of regular & inserted channel */ + ADC_CTL0(adc_periph) &= ~((uint32_t)( ADC_CTL0_DISRC | ADC_CTL0_DISIC )); + switch(adc_channel_group){ + case ADC_REGULAR_CHANNEL: + /* config the number of conversions in discontinuous mode */ + ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DISNUM); + if((length <= 8U) && (length >= 1U)){ + ADC_CTL0(adc_periph) |= CTL0_DISNUM(((uint32_t)length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); + } + /* enable regular channel group discontinuous mode */ + ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISRC; + break; + case ADC_INSERTED_CHANNEL: + /* enable inserted channel group discontinuous mode */ + ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISIC; + break; + case ADC_CHANNEL_DISCON_DISABLE: + /* disable discontinuous mode of regular & inserted channel */ + default: + break; + } +} + +/*! + \brief configure the length of regular channel group or inserted channel group + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] adc_channel_group: select the channel group + only one parameter can be selected which is shown as below: \arg ADC_REGULAR_CHANNEL: regular channel group \arg ADC_INSERTED_CHANNEL: inserted channel group \param[in] length: the length of the channel @@ -282,14 +421,14 @@ void adc_channel_length_config(uint32_t adc_periph , uint8_t adc_channel_group , switch(adc_channel_group){ case ADC_REGULAR_CHANNEL: if((length >= 1U) && (length <= 16U)){ - ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL); - ADC_RSQ0(adc_periph) |= (uint32_t)((length-1U) << REGULAR_CHANNEL_LENGTH_OFFSET); + ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL); + ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length-ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); } break; case ADC_INSERTED_CHANNEL: if((length >= 1U) && (length <= 4U)){ - ADC_ISQ(adc_periph) &= ~((uint32_t)ADC_ISQ_IL); - ADC_ISQ(adc_periph) |= (uint32_t)((length-1U) << INSERTED_CHANNEL_LENGTH_OFFSET); + ADC_ISQ(adc_periph) &= ~((uint32_t)ADC_ISQ_IL); + ADC_ISQ(adc_periph) |= ISQ_IL((uint32_t)(length-ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); } break; default: @@ -298,12 +437,230 @@ void adc_channel_length_config(uint32_t adc_periph , uint8_t adc_channel_group , } /*! - \brief ADC external trigger enable + \brief configure ADC regular channel + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] rank: the regular group sequencer rank,this parameter must be between 0 to 15 + \param[in] adc_channel: the selected ADC channel + only one parameter can be selected which is shown as below: + \arg ADC_CHANNEL_x(x=0..18): ADC Channelx + \param[in] sample_time: the sample time value + only one parameter can be selected which is shown as below: + \arg ADC_SAMPLETIME_3: 3 cycles + \arg ADC_SAMPLETIME_15: 15 cycles + \arg ADC_SAMPLETIME_28: 28 cycles + \arg ADC_SAMPLETIME_56: 56 cycles + \arg ADC_SAMPLETIME_84: 84 cycles + \arg ADC_SAMPLETIME_112: 112 cycles + \arg ADC_SAMPLETIME_144: 144 cycles + \arg ADC_SAMPLETIME_480: 480 cycles + \param[out] none + \retval none +*/ +void adc_regular_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time) +{ + uint32_t rsq,sampt; + + /* ADC regular sequence config */ + if(rank < ADC_REGULAR_CHANNEL_RANK_SIX){ + /* the regular group sequence rank is smaller than six */ + rsq = ADC_RSQ2(adc_periph); + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*rank))); + /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ + rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*rank)); + ADC_RSQ2(adc_periph) = rsq; + }else if(rank < ADC_REGULAR_CHANNEL_RANK_TWELVE){ + /* the regular group sequence rank is smaller than twelve */ + rsq = ADC_RSQ1(adc_periph); + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_SIX)))); + /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ + rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_SIX))); + ADC_RSQ1(adc_periph) = rsq; + }else if(rank < ADC_REGULAR_CHANNEL_RANK_SIXTEEN){ + /* the regular group sequence rank is smaller than sixteen */ + rsq = ADC_RSQ0(adc_periph); + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_TWELVE)))); + /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ + rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_TWELVE))); + ADC_RSQ0(adc_periph) = rsq; + }else{ + } + + /* ADC sampling time config */ + if(adc_channel < ADC_CHANNEL_SAMPLE_TEN){ + /* the regular group sequence rank is smaller than ten */ + sampt = ADC_SAMPT1(adc_periph); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel))); + /* channel sample time set*/ + sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel)); + ADC_SAMPT1(adc_periph) = sampt; + }else if(adc_channel <= ADC_CHANNEL_SAMPLE_EIGHTEEN){ + /* the regular group sequence rank is smaller than eighteen */ + sampt = ADC_SAMPT0(adc_periph); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN)))); + /* channel sample time set*/ + sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN))); + ADC_SAMPT0(adc_periph) = sampt; + }else{ + } +} + +/*! + \brief configure ADC inserted channel + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] rank: the inserted group sequencer rank,this parameter must be between 0 to 3 + \param[in] adc_channel: the selected ADC channel + only one parameter can be selected which is shown as below: + \arg ADC_CHANNEL_x(x=0..18): ADC Channelx + \param[in] sample_time: The sample time value + only one parameter can be selected which is shown as below: + \arg ADC_SAMPLETIME_3: 3 cycles + \arg ADC_SAMPLETIME_15: 15 cycles + \arg ADC_SAMPLETIME_28: 28 cycles + \arg ADC_SAMPLETIME_56: 56 cycles + \arg ADC_SAMPLETIME_84: 84 cycles + \arg ADC_SAMPLETIME_112: 112 cycles + \arg ADC_SAMPLETIME_144: 144 cycles + \arg ADC_SAMPLETIME_480: 480 cycles + \param[out] none + \retval none +*/ +void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time) +{ + uint8_t inserted_length; + uint32_t isq,sampt; + + /* get inserted channel group length */ + inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U); + /* the channel number is written to these bits to select a channel as the nth conversion in the inserted channel group */ + if(rank < 4U){ + isq = ADC_ISQ(adc_periph); + isq &= ~((uint32_t)(ADC_ISQ_ISQN << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH-(inserted_length-rank)*ADC_INSERTED_CHANNEL_RANK_LENGTH))); + isq |= ((uint32_t)adc_channel << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH-(inserted_length-rank)*ADC_INSERTED_CHANNEL_RANK_LENGTH)); + ADC_ISQ(adc_periph) = isq; + } + + /* ADC sampling time config */ + if(adc_channel < ADC_CHANNEL_SAMPLE_TEN){ + /* the inserted group sequence rank is smaller than ten */ + sampt = ADC_SAMPT1(adc_periph); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel))); + /* channel sample time set*/ + sampt |= (uint32_t) sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel); + ADC_SAMPT1(adc_periph) = sampt; + }else if(adc_channel <= ADC_CHANNEL_SAMPLE_EIGHTEEN){ + /* the inserted group sequence rank is smaller than eighteen */ + sampt = ADC_SAMPT0(adc_periph); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel - ADC_CHANNEL_SAMPLE_TEN)))); + /* channel sample time set*/ + sampt |= ((uint32_t)sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel - ADC_CHANNEL_SAMPLE_TEN))); + ADC_SAMPT0(adc_periph) = sampt; + }else{ + } +} + +/*! + \brief configure ADC inserted channel offset + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] inserted_channel : insert channel select + only one parameter can be selected which is shown as below: + \arg ADC_INSERTED_CHANNEL_0: inserted channel0 + \arg ADC_INSERTED_CHANNEL_1: inserted channel1 + \arg ADC_INSERTED_CHANNEL_2: inserted channel2 + \arg ADC_INSERTED_CHANNEL_3: inserted channel3 + \param[in] offset : the offset data + \param[out] none + \retval none +*/ +void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_channel , uint16_t offset) +{ + uint8_t inserted_length; + uint32_t num = 0U; + + inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U); + num = ((uint32_t)ADC_OFFSET_LENGTH - ((uint32_t)inserted_length - (uint32_t)inserted_channel)); + + if(num <= ADC_OFFSET_LENGTH){ + /* calculate the offset of the register */ + num = num * ADC_OFFSET_SHIFT_LENGTH; + /* config the offset of the selected channels */ + REG32((adc_periph) + 0x14U + num) = IOFFX_IOFF((uint32_t)offset); + } +} + +/*! + \brief configure ADC external trigger source \param[in] adc_periph: ADCx,x=0,1,2 \param[in] adc_channel_group: select the channel group + only one parameter can be selected which is shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \param[in] external_trigger_source: regular or inserted group trigger source + for regular channel: + only one parameter can be selected which is shown as below: + \arg ADC_EXTTRIG_REGULAR_T0_CH0: external trigger timer 0 CC0 event select for regular channel + \arg ADC_EXTTRIG_REGULAR_T0_CH1: external trigger timer 0 CC1 event select for regular channel + \arg ADC_EXTTRIG_REGULAR_T0_CH2: external trigger timer 0 CC2 event select for regular channel + \arg ADC_EXTTRIG_REGULAR_T1_CH1: external trigger timer 1 CC1 event select for regular channel + \arg ADC_EXTTRIG_REGULAR_T1_CH2: external trigger timer 1 CC2 event select for regular channel + \arg ADC_EXTTRIG_REGULAR_T1_CH3: external trigger timer 1 CC3 event select for regular channel + \arg ADC_EXTTRIG_REGULAR_T1_TRGO: external trigger timer 1 TRGO event select for regular channel + \arg ADC_EXTTRIG_REGULAR_T2_CH0 : external trigger timer 2 CC0 event select for regular channel + \arg ADC_EXTTRIG_REGULAR_T2_TRGO : external trigger timer 2 TRGO event select for regular channel + \arg ADC_EXTTRIG_REGULAR_T3_CH3: external trigger timer 3 CC3 event select for regular channel + \arg ADC_EXTTRIG_REGULAR_T4_CH0: external trigger timer 4 CC0 event select for regular channel + \arg ADC_EXTTRIG_REGULAR_T4_CH1: external trigger timer 4 CC1 event select for regular channel + \arg ADC_EXTTRIG_REGULAR_T4_CH2: external trigger timer 4 CC2 event select for regular channel + \arg ADC_EXTTRIG_REGULAR_T7_CH0: external trigger timer 7 CC0 event select for regular channel + \arg ADC_EXTTRIG_REGULAR_T7_TRGO: external trigger timer 7 TRGO event select for regular channel + \arg ADC_EXTTRIG_REGULAR_EXTI_11: external trigger extiline 11 select for regular channel + for inserted channel: + only one parameter can be selected which is shown as below: + \arg ADC_EXTTRIG_INSERTED_T0_CH3: timer0 capture compare 3 + \arg ADC_EXTTRIG_INSERTED_T0_TRGO: timer0 TRGO event + \arg ADC_EXTTRIG_INSERTED_T1_CH0: timer1 capture compare 0 + \arg ADC_EXTTRIG_INSERTED_T1_TRGO: timer1 TRGO event + \arg ADC_EXTTRIG_INSERTED_T2_CH1: timer2 capture compare 1 + \arg ADC_EXTTRIG_INSERTED_T2_CH3: timer2 capture compare 3 + \arg ADC_EXTTRIG_INSERTED_T3_CH0: timer3 capture compare 0 + \arg ADC_EXTTRIG_INSERTED_T3_CH1: timer3 capture compare 1 + \arg ADC_EXTTRIG_INSERTED_T3_CH2: timer3 capture compare 2 + \arg ADC_EXTTRIG_INSERTED_T3_TRGO: timer3 capture compare TRGO + \arg ADC_EXTTRIG_INSERTED_T4_CH3: timer4 capture compare 3 + \arg ADC_EXTTRIG_INSERTED_T4_TRGO: timer4 capture compare TRGO + \arg ADC_EXTTRIG_INSERTED_T7_CH1: timer7 capture compare 1 + \arg ADC_EXTTRIG_INSERTED_T7_CH2: timer7 capture compare 2 + \arg ADC_EXTTRIG_INSERTED_T7_CH3: timer7 capture compare 3 + \arg ADC_EXTTRIG_INSERTED_EXTI_15: external interrupt line 15 + \param[out] none + \retval none +*/ +void adc_external_trigger_source_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t external_trigger_source) +{ + switch(adc_channel_group){ + case ADC_REGULAR_CHANNEL: + /* configure ADC regular group external trigger source */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSRC); + ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; + break; + case ADC_INSERTED_CHANNEL: + /* configure ADC inserted group external trigger source */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSIC); + ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; + break; + default: + break; + } +} + +/*! + \brief enable ADC external trigger + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] adc_channel_group: select the channel group + only one parameter can be selected which is shown as below: \arg ADC_REGULAR_CHANNEL: regular channel group \arg ADC_INSERTED_CHANNEL: inserted channel group \param[in] trigger_mode: external trigger mode + only one parameter can be selected which is shown as below: \arg EXTERNAL_TRIGGER_DISABLE: external trigger disable \arg EXTERNAL_TRIGGER_RISING: rising edge of external trigger \arg EXTERNAL_TRIGGER_FALLING: falling edge of external trigger @@ -315,10 +672,12 @@ void adc_external_trigger_config(uint32_t adc_periph , uint8_t adc_channel_group { switch(adc_channel_group){ case ADC_REGULAR_CHANNEL: + /* configure ADC regular channel group external trigger mode */ ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETMRC); ADC_CTL1(adc_periph) |= (uint32_t) (trigger_mode << REGULAR_TRIGGER_MODE); break; case ADC_INSERTED_CHANNEL: + /* configure ADC inserted channel group external trigger mode */ ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETMIC); ADC_CTL1(adc_periph) |= (uint32_t) (trigger_mode << INSERTED_TRIGGER_MODE); break; @@ -328,69 +687,10 @@ void adc_external_trigger_config(uint32_t adc_periph , uint8_t adc_channel_group } /*! - \brief ADC external trigger source config - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_channel_group: select the channel group - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[in] external_trigger_source: regular or inserted group trigger source - for regular channel: - \arg ADC_EXTTRIG_REGULAR_T0_CH0: external trigger timer 0 CC0 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T0_CH1: external trigger timer 0 CC1 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T0_CH2: external trigger timer 0 CC2 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T1_CH1: external trigger timer 1 CC1 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T1_CH2: external trigger timer 1 CC2 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T1_CH3: external trigger timer 1 CC3 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T1_TRGO: external trigger timer 1 TRGO event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T2_CH0 : external trigger timer 2 CC0 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T2_TRGO : external trigger timer 2 TRGO event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T3_CH3: external trigger timer 3 CC3 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T4_CH0: external trigger timer 4 CC0 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T4_CH1: external trigger timer 4 CC1 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T4_CH2: external trigger timer 4 CC2 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T7_CH0: external trigger timer 7 CC0 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T7_TRGO: external trigger timer 7 TRGO event select for regular channel - \arg ADC_EXTTRIG_REGULAR_EXTI_11: external trigger extiline 11 select for regular channel - for inserted channel: - \arg ADC_EXTTRIG_INSERTED_T0_CH3: timer0 capture compare 3 - \arg ADC_EXTTRIG_INSERTED_T0_TRGO: timer0 TRGO event - \arg ADC_EXTTRIG_INSERTED_T1_CH0: timer1 capture compare 0 - \arg ADC_EXTTRIG_INSERTED_T1_TRGO: timer1 TRGO event - \arg ADC_EXTTRIG_INSERTED_T2_CH1: timer2 capture compare 1 - \arg ADC_EXTTRIG_INSERTED_T2_CH3: timer2 capture compare 3 - \arg ADC_EXTTRIG_INSERTED_T3_CH0: timer3 capture compare 0 - \arg ADC_EXTTRIG_INSERTED_T3_CH1: timer3 capture compare 1 - \arg ADC_EXTTRIG_INSERTED_T3_CH2: timer3 capture compare 2 - \arg ADC_EXTTRIG_INSERTED_T3_TRGO: timer3 capture compare TRGO - \arg ADC_EXTTRIG_INSERTED_T4_CH3: timer4 capture compare 3 - \arg ADC_EXTTRIG_INSERTED_T4_TRGO: timer4 capture compare TRGO - \arg ADC_EXTTRIG_INSERTED_T7_CH1: timer7 capture compare 1 - \arg ADC_EXTTRIG_INSERTED_T7_CH2: timer7 capture compare 2 - \arg ADC_EXTTRIG_INSERTED_T7_CH3: timer7 capture compare 3 - \arg ADC_EXTTRIG_INSERTED_EXTI_15: external interrupt line 15 - \param[out] none - \retval none -*/ -void adc_external_trigger_source_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t external_trigger_source) -{ - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSRC); - ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; - break; - case ADC_INSERTED_CHANNEL: - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSIC); - ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; - break; - default: - break; - } -} - -/*! - \brief ADC software trigger enable + \brief enable ADC software trigger \param[in] adc_periph: ADCx,x=0,1,2 \param[in] adc_channel_group: select the channel group + only one parameter can be selected which is shown as below: \arg ADC_REGULAR_CHANNEL: regular channel group \arg ADC_INSERTED_CHANNEL: inserted channel group \param[out] none @@ -400,9 +700,11 @@ void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_channel_group { switch(adc_channel_group){ case ADC_REGULAR_CHANNEL: + /* enable ADC regular channel group software trigger */ ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_SWRCST; break; case ADC_INSERTED_CHANNEL: + /* enable ADC inserted channel group software trigger */ ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_SWICST; break; default: @@ -410,10 +712,199 @@ void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_channel_group } } +/*! + \brief configure end of conversion mode + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] end_selection: end of conversion mode + only one parameter can be selected which is shown as below: + \arg ADC_EOC_SET_SEQUENCE: only at the end of a sequence of regular conversions, the EOC bit is set.Overflow detection is disabled unless DMA=1. + \arg ADC_EOC_SET_CONVERSION: at the end of each regular conversion, the EOC bit is set.Overflow is detected automatically. + \param[out] none + \retval none +*/ +void adc_end_of_conversion_config(uint32_t adc_periph , uint8_t end_selection) +{ + switch(end_selection){ + case ADC_EOC_SET_SEQUENCE: + /* only at the end of a sequence of regular conversions, the EOC bit is set */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_EOCM); + break; + case ADC_EOC_SET_CONVERSION: + /* at the end of each regular conversion, the EOC bit is set.Overflow is detected automatically */ + ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_EOCM); + break; + default: + break; + } +} + +/*! + \brief read ADC regular group data register + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] none + \param[out] none + \retval the conversion value +*/ +uint16_t adc_regular_data_read(uint32_t adc_periph) +{ + return (uint16_t)(ADC_RDATA(adc_periph)); +} + +/*! + \brief read ADC inserted group data register + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] inserted_channel : insert channel select + only one parameter can be selected which is shown as below: + \arg ADC_INSERTED_CHANNEL_0: inserted Channel0 + \arg ADC_INSERTED_CHANNEL_1: inserted channel1 + \arg ADC_INSERTED_CHANNEL_2: inserted Channel2 + \arg ADC_INSERTED_CHANNEL_3: inserted Channel3 + \param[out] none + \retval the conversion value +*/ +uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel) +{ + uint32_t idata; + /* read the data of the selected channel */ + switch(inserted_channel){ + case ADC_INSERTED_CHANNEL_0: + /* read the data of channel 0 */ + idata = ADC_IDATA0(adc_periph); + break; + case ADC_INSERTED_CHANNEL_1: + /* read the data of channel 1 */ + idata = ADC_IDATA1(adc_periph); + break; + case ADC_INSERTED_CHANNEL_2: + /* read the data of channel 2 */ + idata = ADC_IDATA2(adc_periph); + break; + case ADC_INSERTED_CHANNEL_3: + /* read the data of channel 3 */ + idata = ADC_IDATA3(adc_periph); + break; + default: + idata = 0U; + break; + } + return (uint16_t)idata; +} + +/*! + \brief disable ADC analog watchdog single channel + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none +*/ +void adc_watchdog_single_channel_disable(uint32_t adc_periph ) +{ + ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_WDSC); +} + +/*! + \brief enable ADC analog watchdog single channel + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] adc_channel: the selected ADC channel + only one parameter can be selected which is shown as below: + \arg ADC_CHANNEL_x: ADC Channelx(x=0..18) + \param[out] none + \retval none +*/ +void adc_watchdog_single_channel_enable(uint32_t adc_periph , uint8_t adc_channel) +{ + ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_WDCHSEL); + + /* analog watchdog channel select */ + ADC_CTL0(adc_periph) |= (uint32_t)adc_channel; + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_WDSC; +} + +/*! + \brief configure ADC analog watchdog group channel + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] adc_channel_group: the channel group use analog watchdog + only one parameter can be selected which is shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group + \param[out] none + \retval none +*/ +void adc_watchdog_group_channel_enable(uint32_t adc_periph , uint8_t adc_channel_group) +{ + ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC)); + /* select the group */ + switch(adc_channel_group){ + case ADC_REGULAR_CHANNEL: + /* regular channel analog watchdog enable */ + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_RWDEN; + break; + case ADC_INSERTED_CHANNEL: + /* inserted channel analog watchdog enable */ + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_IWDEN; + break; + case ADC_REGULAR_INSERTED_CHANNEL: + /* regular and inserted channel analog watchdog enable */ + ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN); + break; + default: + break; + } +} + +/*! + \brief disable ADC analog watchdog + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] adc_channel_group: the channel group use analog watchdog + only one parameter can be selected which is shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group + \param[out] none + \retval none +*/ +void adc_watchdog_disable(uint32_t adc_periph , uint8_t adc_channel_group) +{ + /* select the group */ + switch(adc_channel_group){ + case ADC_REGULAR_CHANNEL: + /* disable ADC analog watchdog regular channel group */ + ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_RWDEN); + break; + case ADC_INSERTED_CHANNEL: + /* disable ADC analog watchdog inserted channel group */ + ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_IWDEN); + break; + case ADC_REGULAR_INSERTED_CHANNEL: + /* disable ADC analog watchdog regular and inserted channel group */ + ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN)); + break; + default: + break; + } +} + +/*! + \brief configure ADC analog watchdog threshold + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] low_threshold: analog watchdog low threshold,0..4095 + \param[in] high_threshold: analog watchdog high threshold,0..4095 + \param[out] none + \retval none +*/ +void adc_watchdog_threshold_config(uint32_t adc_periph , uint16_t low_threshold , uint16_t high_threshold) +{ + /* configure ADC analog watchdog low threshold */ + ADC_WDLT(adc_periph) = (uint32_t)WDLT_WDLT(low_threshold); + /* configure ADC analog watchdog high threshold */ + ADC_WDHT(adc_periph) = (uint32_t)WDHT_WDHT(high_threshold); +} + /*! \brief get the ADC flag bits \param[in] adc_periph: ADCx,x=0,1,2 \param[in] adc_flag: the adc flag bits + only one parameter can be selected which is shown as below: \arg ADC_FLAG_WDE: analog watchdog event flag \arg ADC_FLAG_EOC: end of group conversion flag \arg ADC_FLAG_EOIC: end of inserted group conversion flag @@ -425,10 +916,11 @@ void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_channel_group */ FlagStatus adc_flag_get(uint32_t adc_periph , uint32_t adc_flag) { - if(ADC_STAT(adc_periph) & adc_flag){ - return SET; - } - return RESET; + FlagStatus reval = RESET; + if(ADC_STAT(adc_periph) & adc_flag){ + reval = SET; + } + return reval; } @@ -436,6 +928,7 @@ FlagStatus adc_flag_get(uint32_t adc_periph , uint32_t adc_flag) \brief clear the ADC flag bits \param[in] adc_periph: ADCx,x=0,1,2 \param[in] adc_flag: the adc flag bits + only one parameter can be selected which is shown as below: \arg ADC_FLAG_WDE: analog watchdog event flag \arg ADC_FLAG_EOC: end of group conversion flag \arg ADC_FLAG_EOIC: end of inserted group conversion flag @@ -450,14 +943,47 @@ void adc_flag_clear(uint32_t adc_periph , uint32_t adc_flag) ADC_STAT(adc_periph) &= ~((uint32_t)adc_flag); } +/*! + \brief get the bit state of ADCx software start conversion + \param[in] adc_periph: ADCx, x=0,1,2 only one among these parameters can be selected + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph) +{ + FlagStatus reval = RESET; + if((uint32_t)RESET != (ADC_STAT(adc_periph) & ADC_STAT_STRC)){ + reval = SET; + } + return reval; +} + +/*! + \brief get the bit state of ADCx software inserted channel start conversion + \param[in] adc_periph: ADCx, x=0,1,2 only one among these parameters can be selected + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph) +{ + FlagStatus reval = RESET; + if((uint32_t)RESET != (ADC_STAT(adc_periph) & ADC_STAT_STIC)){ + reval = SET; + } + return reval; +} + /*! \brief get the ADC interrupt bits \param[in] adc_periph: ADCx,x=0,1,2 \param[in] adc_interrupt: the adc interrupt bits - \arg ADC_INT_WDE: analog watchdog interrupt - \arg ADC_INT_EOC: end of group conversion interrupt - \arg ADC_INT_EOIC: end of inserted group conversion interrupt - \arg ADC_INT_ROVF: regular data register overflow interrupt + only one parameter can be selected which is shown as below: + \arg ADC_INT_FLAG_WDE: analog watchdog interrupt + \arg ADC_INT_FLAG_EOC: end of group conversion interrupt + \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt + \arg ADC_INT_FLAG_ROVF: regular data register overflow interrupt \param[out] none \retval FlagStatus: SET or RESET */ @@ -467,25 +993,29 @@ FlagStatus adc_interrupt_flag_get(uint32_t adc_periph , uint32_t adc_interrupt) uint32_t state; /* check the interrupt bits */ switch(adc_interrupt){ - case ADC_INT_WDE: + case ADC_INT_FLAG_WDE: + /* get the ADC analog watchdog interrupt bits */ state = ADC_STAT(adc_periph) & ADC_STAT_WDE; if((ADC_CTL0(adc_periph) & ADC_CTL0_WDEIE) && state){ interrupt_flag = SET; } break; - case ADC_INT_EOC: + case ADC_INT_FLAG_EOC: + /* get the ADC end of group conversion interrupt bits */ state = ADC_STAT(adc_periph) & ADC_STAT_EOC; if((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state){ interrupt_flag = SET; } break; - case ADC_INT_EOIC: + case ADC_INT_FLAG_EOIC: + /* get the ADC end of inserted group conversion interrupt bits */ state = ADC_STAT(adc_periph) & ADC_STAT_EOIC; if((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state){ interrupt_flag = SET; } break; - case ADC_INT_ROVF: + case ADC_INT_FLAG_ROVF: + /* get the ADC regular data register overflow interrupt bits */ state = ADC_STAT(adc_periph) & ADC_STAT_ROVF; if((ADC_CTL0(adc_periph) & ADC_CTL0_ROVFIE) && state){ interrupt_flag = SET; @@ -500,11 +1030,12 @@ FlagStatus adc_interrupt_flag_get(uint32_t adc_periph , uint32_t adc_interrupt) /*! \brief clear the ADC flag \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_flag: the adc status flag - \arg ADC_INT_WDE: analog watchdog interrupt - \arg ADC_INT_EOC: end of group conversion interrupt - \arg ADC_INT_EOIC: end of inserted group conversion interrupt - \arg ADC_INT_ROVF: regular data register overflow interrupt + \param[in] adc_interrupt: the adc status flag + only one parameter can be selected which is shown as below: + \arg ADC_INT_FLAG_WDE: analog watchdog interrupt + \arg ADC_INT_FLAG_EOC: end of group conversion interrupt + \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt + \arg ADC_INT_FLAG_ROVF: regular data register overflow interrupt \param[out] none \retval none */ @@ -514,9 +1045,10 @@ void adc_interrupt_flag_clear(uint32_t adc_periph , uint32_t adc_interrupt) } /*! - \brief ADC interrupt enable + \brief enable ADC interrupt \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_flag: the adc interrupt flag + \param[in] adc_interrupt: the adc interrupt flag + only one parameter can be selected which is shown as below: \arg ADC_INT_WDE: analog watchdog interrupt flag \arg ADC_INT_EOC: end of group conversion interrupt flag \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag @@ -528,12 +1060,15 @@ void adc_interrupt_enable(uint32_t adc_periph , uint32_t adc_interrupt) { switch(adc_interrupt){ case ADC_INT_WDE: + /* enable analog watchdog interrupt */ ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_WDEIE; break; case ADC_INT_EOC: + /* enable end of group conversion interrupt */ ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOCIE; break; case ADC_INT_EOIC: + /* enable end of inserted group conversion interrupt */ ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOICIE; break; case ADC_INT_ROVF: @@ -545,9 +1080,10 @@ void adc_interrupt_enable(uint32_t adc_periph , uint32_t adc_interrupt) } /*! - \brief ADC interrupt disable + \brief disable ADC interrupt \param[in] adc_periph: ADCx,x=0,1,2 \param[in] adc_flag: the adc interrupt flag + only one parameter can be selected which is shown as below: \arg ADC_INT_WDE: analog watchdog interrupt flag \arg ADC_INT_EOC: end of group conversion interrupt flag \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag @@ -576,388 +1112,10 @@ void adc_interrupt_disable(uint32_t adc_periph , uint32_t adc_interrupt) } } -/*! - \brief ADC analog watchdog single channel disable - \param[in] adc_periph: ADCx,x=0,1,2 - \param[out] none - \retval none -*/ -void adc_watchdog_single_channel_disable(uint32_t adc_periph ) -{ - ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_WDSC); -} - -/*! - \brief ADC analog watchdog single channel enable - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_channel: the selected ADC channel - \arg ADC_CHANNEL_x: ADC Channelx(x=0..18) - \param[out] none - \retval none -*/ -void adc_watchdog_single_channel_enable(uint32_t adc_periph , uint8_t adc_channel) -{ - ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_WDCHSEL); - - ADC_CTL0(adc_periph) |= (uint32_t)adc_channel; - ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_WDSC; -} - -/*! - \brief adc analog watchdog group channel config - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_channel_group: the channel group use analog watchdog - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group - \param[out] none - \retval none -*/ -void adc_watchdog_enable(uint32_t adc_periph , uint8_t adc_channel_group) -{ - ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC)); - /* select the group */ - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: - ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_RWDEN; - break; - case ADC_INSERTED_CHANNEL: - ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_IWDEN; - break; - case ADC_REGULAR_INSERTED_CHANNEL: - ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN); - break; - default: - break; - } -} - -/*! - \brief ADC analog watchdog disable - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_channel_group: the channel group use analog watchdog - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group - \param[out] none - \retval none -*/ -void adc_watchdog_disable(uint32_t adc_periph , uint8_t adc_channel_group) -{ - /* select the group */ - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: - ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_RWDEN); - break; - case ADC_INSERTED_CHANNEL: - ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_IWDEN); - break; - case ADC_REGULAR_INSERTED_CHANNEL: - ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN)); - break; - default: - break; - } -} - -/*! - \brief ADC analog watchdog threshold config - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] low_threshold: analog watchdog low threshold,0..4095 - \param[in] high_threshold: analog watchdog high threshold,0..4095 - \param[out] none - \retval none -*/ -void adc_watchdog_threshold_config(uint32_t adc_periph , uint16_t low_threshold , uint16_t high_threshold) -{ - ADC_WDLT(adc_periph) = (uint32_t)low_threshold; - ADC_WDHT(adc_periph) = (uint32_t)high_threshold; -} - -/*! - \brief ADC regular channel config - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] rank: the regular group sequencer rank,this parameter must be between 0 to 15 - \param[in] adc_channel: the selected ADC channel - \arg ADC_CHANNEL_x(x=0..18): ADC Channelx - \param[in] sample_time: the sample time value - \arg ADC_SAMPLETIME_3: 3 cycles - \arg ADC_SAMPLETIME_15: 15 cycles - \arg ADC_SAMPLETIME_28: 28 cycles - \arg ADC_SAMPLETIME_56: 56 cycles - \arg ADC_SAMPLETIME_84: 84 cycles - \arg ADC_SAMPLETIME_112: 112 cycles - \arg ADC_SAMPLETIME_144: 144 cycles - \arg ADC_SAMPLETIME_480: 480 cycles - \param[out] none - \retval none -*/ -void adc_regular_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time) -{ - uint32_t rsq,sampt; - - /* ADC regular sequence config */ - if(rank < 6U){ - rsq = ADC_RSQ2(adc_periph); - rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*rank))); - rsq |= ((uint32_t)adc_channel << (5U*rank)); - ADC_RSQ2(adc_periph) = rsq; - }else if(rank < 12U){ - rsq = ADC_RSQ1(adc_periph); - rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*(rank-6U)))); - rsq |= ((uint32_t)adc_channel << (5U*(rank-6U))); - ADC_RSQ1(adc_periph) = rsq; - }else if(rank < 16U){ - rsq = ADC_RSQ0(adc_periph); - rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*(rank-12U)))); - rsq |= ((uint32_t)adc_channel << (5U*(rank-12U))); - ADC_RSQ0(adc_periph) = rsq; - }else{ - } - - /* ADC sampling time config */ - if(adc_channel < 10U){ - sampt = ADC_SAMPT1(adc_periph); - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*adc_channel))); - sampt |= (uint32_t)(sample_time << (3U*adc_channel)); - ADC_SAMPT1(adc_periph) = sampt; - }else if(adc_channel < 19U){ - sampt = ADC_SAMPT0(adc_periph); - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*(adc_channel-10U)))); - sampt |= (uint32_t)(sample_time << (3U*(adc_channel-10U))); - ADC_SAMPT0(adc_periph) = sampt; - }else{ - } -} - -/*! - \brief ADC regular group data register read - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] none - \param[out] none - \retval the conversion value -*/ -uint16_t adc_regular_data_read(uint32_t adc_periph) -{ - return (uint16_t)(ADC_RDATA(adc_periph)); -} - -/*! - \brief ADC inserted channel config - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] rank: the inserted group sequencer rank,this parameter must be between 0 to 3 - \param[in] adc_channel: the selected ADC channel - \arg ADC_CHANNEL_x(x=0..18): ADC Channelx - \param[in] sample_time: The sample time value - \arg ADC_SAMPLETIME_3: 3 cycles - \arg ADC_SAMPLETIME_15: 15 cycles - \arg ADC_SAMPLETIME_28: 28 cycles - \arg ADC_SAMPLETIME_56: 56 cycles - \arg ADC_SAMPLETIME_84: 84 cycles - \arg ADC_SAMPLETIME_112: 112 cycles - \arg ADC_SAMPLETIME_144: 144 cycles - \arg ADC_SAMPLETIME_480: 480 cycles - \param[out] none - \retval none -*/ -void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint8_t sample_time) -{ - uint8_t inserted_length; - uint32_t isq,sampt; - - inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U); - if(rank < 4U){ - isq = ADC_ISQ(adc_periph); - isq &= ~((uint32_t)(ADC_ISQ_ISQN << (15U-(inserted_length-rank)*5U))); - isq |= ((uint32_t)adc_channel << (15U-(inserted_length-rank)*5U)); - ADC_ISQ(adc_periph) = isq; - } - - if(adc_channel < 10U){ - sampt = ADC_SAMPT1(adc_periph); - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*adc_channel))); - sampt |= (uint32_t) sample_time << (3U*adc_channel); - ADC_SAMPT1(adc_periph) = sampt; - }else if(adc_channel < 19U){ - sampt = ADC_SAMPT0(adc_periph); - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*(adc_channel-10U)))); - sampt |= ((uint32_t)sample_time << (3U*(adc_channel-10U))); - ADC_SAMPT0(adc_periph) = sampt; - }else{ - } -} - -/*! - \brief ADC inserted channel offset config - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] inserted_channel : insert channel select - \arg ADC_INSERTED_CHANNEL_0: inserted channel0 - \arg ADC_INSERTED_CHANNEL_1: inserted channel1 - \arg ADC_INSERTED_CHANNEL_2: inserted channel2 - \arg ADC_INSERTED_CHANNEL_3: inserted channel3 - \param[in] offset : the offset data - \param[out] none - \retval the conversion value -*/ -void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_channel , uint16_t offset) -{ - /* config the offset of the selected channels */ - if(ADC_INSERTED_CHANNEL_0 == inserted_channel){ - ADC_IOFF0(adc_periph) = (uint32_t)offset; - }else if(ADC_INSERTED_CHANNEL_1 == inserted_channel){ - ADC_IOFF1(adc_periph) = (uint32_t)offset; - }else if(ADC_INSERTED_CHANNEL_2 == inserted_channel){ - ADC_IOFF2(adc_periph) = (uint32_t)offset; - }else if(ADC_INSERTED_CHANNEL_3 == inserted_channel){ - ADC_IOFF3(adc_periph) = (uint32_t)offset; - }else{ - } -} - -/*! - \brief ADC inserted group data register read - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] inserted_channel : insert channel select - \arg ADC_INSERTED_CHANNEL_0: inserted Channel0 - \arg ADC_INSERTED_CHANNEL_1: inserted channel1 - \arg ADC_INSERTED_CHANNEL_2: inserted Channel2 - \arg ADC_INSERTED_CHANNEL_3: inserted Channel3 - \param[out] none - \retval the conversion value -*/ -uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel) -{ - uint32_t idata; - /* read the data of the selected channel */ - switch(inserted_channel){ - case ADC_INSERTED_CHANNEL_0: - idata = ADC_IDATA0(adc_periph); - break; - case ADC_INSERTED_CHANNEL_1: - idata = ADC_IDATA1(adc_periph); - break; - case ADC_INSERTED_CHANNEL_2: - idata = ADC_IDATA2(adc_periph); - break; - case ADC_INSERTED_CHANNEL_3: - idata = ADC_IDATA3(adc_periph); - break; - default: - idata = 0U; - break; - } - return (uint16_t)idata; -} - -/*! - \brief DMA request enable - \param[in] adc_periph: ADCx,x=0,1,2 - \param[out] none - \retval none -*/ -void adc_dma_mode_enable(uint32_t adc_periph) -{ - ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_DMA); -} - -/*! - \brief DMA request disable - \param[in] adc_periph: ADCx,x=0,1,2 - \param[out] none - \retval none -*/ -void adc_dma_mode_disable(uint32_t adc_periph) -{ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DMA); -} - -/*! - \brief when DMA=1, the DMA engine issues a request at end of each regular conversion - \param[in] adc_periph: ADCx,x=0,1,2 - \param[out] none - \retval none -*/ -void adc_dma_request_after_last_enable(uint32_t adc_periph) -{ - ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_DDM); -} - -/*! - \brief the DMA engine is disabled after the end of transfer signal from DMA controller is detected - \param[in] adc_periph: ADCx,x=0,1,2 - \param[out] none - \retval none -*/ -void adc_dma_request_after_last_disable(uint32_t adc_periph) -{ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DDM); -} - -/*! - \brief ADC oversample mode config - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] mode: ADC oversampling mode - \arg ADC_OVERSAMPLING_ALL_CONVERT: all oversampled conversions for a channel are done consecutively after a trigger - \arg ADC_OVERSAMPLING_ONE_CONVERT: each oversampled conversion for a channel needs a trigger - \param[in] shift: ADC oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_NONE: no oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_1B: 1-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_2B: 2-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_3B: 3-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_4B: 3-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_5B: 5-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_6B: 6-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_7B: 7-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_8B: 8-bit oversampling shift - \param[in] ratio: ADC oversampling ratio - \arg ADC_OVERSAMPLING_RATIO_MUL2: oversampling ratio multiple 2 - \arg ADC_OVERSAMPLING_RATIO_MUL4: oversampling ratio multiple 4 - \arg ADC_OVERSAMPLING_RATIO_MUL8: oversampling ratio multiple 8 - \arg ADC_OVERSAMPLING_RATIO_MUL16: oversampling ratio multiple 16 - \arg ADC_OVERSAMPLING_RATIO_MUL32: oversampling ratio multiple 32 - \arg ADC_OVERSAMPLING_RATIO_MUL64: oversampling ratio multiple 64 - \arg ADC_OVERSAMPLING_RATIO_MUL128: oversampling ratio multiple 128 - \arg ADC_OVERSAMPLING_RATIO_MUL256: oversampling ratio multiple 256 - \param[out] none - \retval none -*/ -void adc_oversample_mode_config(uint32_t adc_periph , uint8_t mode , uint16_t shift , uint8_t ratio) -{ - if(ADC_OVERSAMPLING_ONE_CONVERT == mode){ - ADC_OVSAMPCTL(adc_periph) |= (uint32_t)ADC_OVSAMPCTL_TOVS; - }else{ - ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_TOVS); - } - /* config the shift and ratio */ - ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)(ADC_OVSAMPCTL_OVSR | ADC_OVSAMPCTL_OVSS)); - ADC_OVSAMPCTL(adc_periph) |= ((uint32_t)shift | (uint32_t)ratio); -} - -/*! - \brief ADC oversample mode enable - \param[in] adc_periph: ADCx,x=0,1,2 - \param[out] none - \retval none -*/ -void adc_oversample_mode_enable(uint32_t adc_periph) -{ - ADC_OVSAMPCTL(adc_periph) |= ADC_OVSAMPCTL_OVSEN; -} - -/*! - \brief ADC oversample mode disable - \param[in] adc_periph: ADCx,x=0,1,2 - \param[out] none - \retval none -*/ -void adc_oversample_mode_disable(uint32_t adc_periph) -{ - ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_OVSEN); -} - /*! \brief configure the ADC sync mode - \param[in] sync_mode: ADC sync mode + \param[in] sync_mode: ADC sync mode + only one parameter can be selected which is shown as below: \arg ADC_SYNC_MODE_INDEPENDENT: all the ADCs work independently \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL: ADC0 and ADC1 work in combined regular parallel & inserted parallel mode \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION: ADC0 and ADC1 work in combined regular parallel & trigger rotation mode @@ -982,7 +1140,8 @@ void adc_sync_mode_config(uint32_t sync_mode) /*! \brief configure the delay between 2 sampling phases in ADC sync modes - \param[in] sample_delay: the delay between 2 sampling phases in ADC sync modes + \param[in] sample_delay: the delay between 2 sampling phases in ADC sync modes + only one parameter can be selected which is shown as below: \arg ADC_SYNC_DELAY_xCYCLE: x=5..20,the delay between 2 sampling phases in ADC sync modes is x ADC clock cycles \param[out] none \retval none @@ -996,9 +1155,10 @@ void adc_sync_delay_config(uint32_t sample_delay) /*! \brief configure ADC sync DMA mode selection \param[in] dma_mode: ADC sync DMA mode + only one parameter can be selected which is shown as below: \arg ADC_SYNC_DMA_DISABLE: ADC sync DMA disabled - \arg ADC_SYNC_DMA_MODE0: ADC sync DMA disabled - \arg ADC_SYNC_DMA_MODE1: ADC sync DMA disabled + \arg ADC_SYNC_DMA_MODE0: ADC sync DMA mode 0 + \arg ADC_SYNC_DMA_MODE1: ADC sync DMA mode 1 \param[out] none \retval none */ @@ -1031,7 +1191,7 @@ void adc_sync_dma_request_after_last_disable(void) } /*! - \brief ADC sync regular data register read + \brief read ADC sync regular data register \param[in] none \param[out] none \retval sync regular data diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_can.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_can.c index eb03822acf..5eb2974739 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_can.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_can.c @@ -1,18 +1,47 @@ /*! - \file gd32f4xx_can.c - \brief CAN driver + \file gd32f4xx_can.c + \brief CAN driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2019-11-27, V2.0.1, firmware for GD32F4xx + \version 2020-07-14, V2.0.2, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_can.h" +#define CAN_ERROR_HANDLE(s) do{}while(1) + /*! - \brief deinitialize CAN + \brief deinitialize CAN \param[in] can_periph \arg CANx(x=0,1) \param[out] none @@ -29,22 +58,101 @@ void can_deinit(uint32_t can_periph) } } +/*! + \brief initialize CAN parameter struct with a default value + \param[in] type: the type of CAN parameter struct + only one parameter can be selected which is shown as below: + \arg CAN_INIT_STRUCT: the CAN initial struct + \arg CAN_FILTER_STRUCT: the CAN filter struct + \arg CAN_TX_MESSAGE_STRUCT: the CAN TX message struct + \arg CAN_RX_MESSAGE_STRUCT: the CAN RX message struct + \param[in] p_struct: the pointer of the specific struct + \param[out] none + \retval none +*/ +void can_struct_para_init(can_struct_type_enum type, void* p_struct) +{ + uint8_t i; + + /* get type of the struct */ + switch(type){ + /* used for can_init() */ + case CAN_INIT_STRUCT: + ((can_parameter_struct*)p_struct)->auto_bus_off_recovery = DISABLE; + ((can_parameter_struct*)p_struct)->no_auto_retrans = DISABLE; + ((can_parameter_struct*)p_struct)->auto_wake_up = DISABLE; + ((can_parameter_struct*)p_struct)->prescaler = 0x03FFU; + ((can_parameter_struct*)p_struct)->rec_fifo_overwrite = DISABLE; + ((can_parameter_struct*)p_struct)->resync_jump_width = CAN_BT_SJW_1TQ; + ((can_parameter_struct*)p_struct)->time_segment_1 = CAN_BT_BS1_3TQ; + ((can_parameter_struct*)p_struct)->time_segment_2 = CAN_BT_BS2_1TQ; + ((can_parameter_struct*)p_struct)->time_triggered = DISABLE; + ((can_parameter_struct*)p_struct)->trans_fifo_order = DISABLE; + ((can_parameter_struct*)p_struct)->working_mode = CAN_NORMAL_MODE; + + break; + /* used for can_filter_init() */ + case CAN_FILTER_STRUCT: + ((can_filter_parameter_struct*)p_struct)->filter_bits = CAN_FILTERBITS_32BIT; + ((can_filter_parameter_struct*)p_struct)->filter_enable = DISABLE; + ((can_filter_parameter_struct*)p_struct)->filter_fifo_number = CAN_FIFO0; + ((can_filter_parameter_struct*)p_struct)->filter_list_high = 0x0000U; + ((can_filter_parameter_struct*)p_struct)->filter_list_low = 0x0000U; + ((can_filter_parameter_struct*)p_struct)->filter_mask_high = 0x0000U; + ((can_filter_parameter_struct*)p_struct)->filter_mask_low = 0x0000U; + ((can_filter_parameter_struct*)p_struct)->filter_mode = CAN_FILTERMODE_MASK; + ((can_filter_parameter_struct*)p_struct)->filter_number = 0U; + + break; + /* used for can_message_transmit() */ + case CAN_TX_MESSAGE_STRUCT: + for(i = 0U; i < 8U; i++){ + ((can_trasnmit_message_struct*)p_struct)->tx_data[i] = 0U; + } + + ((can_trasnmit_message_struct*)p_struct)->tx_dlen = 0u; + ((can_trasnmit_message_struct*)p_struct)->tx_efid = 0U; + ((can_trasnmit_message_struct*)p_struct)->tx_ff = (uint8_t)CAN_FF_STANDARD; + ((can_trasnmit_message_struct*)p_struct)->tx_ft = (uint8_t)CAN_FT_DATA; + ((can_trasnmit_message_struct*)p_struct)->tx_sfid = 0U; + + break; + /* used for can_message_receive() */ + case CAN_RX_MESSAGE_STRUCT: + for(i = 0U; i < 8U; i++){ + ((can_receive_message_struct*)p_struct)->rx_data[i] = 0U; + } + + ((can_receive_message_struct*)p_struct)->rx_dlen = 0U; + ((can_receive_message_struct*)p_struct)->rx_efid = 0U; + ((can_receive_message_struct*)p_struct)->rx_ff = (uint8_t)CAN_FF_STANDARD; + ((can_receive_message_struct*)p_struct)->rx_fi = 0U; + ((can_receive_message_struct*)p_struct)->rx_ft = (uint8_t)CAN_FT_DATA; + ((can_receive_message_struct*)p_struct)->rx_sfid = 0U; + + break; + + default: + CAN_ERROR_HANDLE("parameter is invalid \r\n"); + } +} + /*! \brief initialize CAN \param[in] can_periph \arg CANx(x=0,1) - \param[in] can_parameter_struct: parameters for CAN initializtion - can_mode: CAN_NORMAL_MODE, CAN_LOOPBACK_MODE, CAN_SILENT_MODE, CAN_SILENT_LOOPBACK_MODE - can_sjw: CAN_BT_SJW_xTQ(x=1, 2, 3, 4) - can_bs1: CAN_BT_BS1_xTQ(1..16) - can_bs2: CAN_BT_BS2_xTQ(1..8) - can_ttc: ENABLE or DISABLE - can_abor: ENABLE or DISABLE - can_awu: ENABLE or DISABLE - can_ard: ENABLE or DISABLE - can_rfod: ENABLE or DISABLE - can_tfo: ENABLE or DISABLE - can_psc: 0x0001 - 0x03FF + \param[in] can_parameter_init: parameters for CAN initializtion + \arg working_mode: CAN_NORMAL_MODE, CAN_LOOPBACK_MODE, CAN_SILENT_MODE, CAN_SILENT_LOOPBACK_MODE + \arg resync_jump_width: CAN_BT_SJW_xTQ(x=1, 2, 3, 4) + \arg time_segment_1: CAN_BT_BS1_xTQ(1..16) + \arg time_segment_2: CAN_BT_BS2_xTQ(1..8) + \arg time_triggered: ENABLE or DISABLE + \arg auto_bus_off_recovery: ENABLE or DISABLE + \arg auto_wake_up: ENABLE or DISABLE + \arg no_auto_retrans: ENABLE or DISABLE + \arg rec_fifo_overwrite: ENABLE or DISABLE + \arg trans_fifo_order: ENABLE or DISABLE + \arg prescaler: 0x0001 - 0x0400 \param[out] none \retval ErrStatus: SUCCESS or ERROR */ @@ -52,19 +160,19 @@ ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init { uint32_t timeout = CAN_TIMEOUT; ErrStatus flag = ERROR; - + /* disable sleep mode */ CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD; /* enable initialize mode */ CAN_CTL(can_periph) |= CAN_CTL_IWMOD; /* wait ACK */ - while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (timeout)){ + while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){ timeout--; } /* check initialize working success */ if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){ flag = ERROR; - } else { + }else{ /* set the bit timing register */ CAN_BT(can_periph) = (BT_MODE((uint32_t)can_parameter_init->working_mode) | \ BT_SJW((uint32_t)can_parameter_init->resync_jump_width) | \ @@ -89,64 +197,64 @@ ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init }else{ CAN_CTL(can_periph) &= ~CAN_CTL_AWU; } - /* automatic retransmission mode */ - if(ENABLE == can_parameter_init->auto_retrans){ + /* automatic retransmission mode disable*/ + if(ENABLE == can_parameter_init->no_auto_retrans){ CAN_CTL(can_periph) |= CAN_CTL_ARD; }else{ CAN_CTL(can_periph) &= ~CAN_CTL_ARD; } - /* receive fifo overwrite mode */ + /* receive fifo overwrite mode */ if(ENABLE == can_parameter_init->rec_fifo_overwrite){ CAN_CTL(can_periph) |= CAN_CTL_RFOD; }else{ CAN_CTL(can_periph) &= ~CAN_CTL_RFOD; - } + } /* transmit fifo order */ if(ENABLE == can_parameter_init->trans_fifo_order){ CAN_CTL(can_periph) |= CAN_CTL_TFO; }else{ CAN_CTL(can_periph) &= ~CAN_CTL_TFO; - } + } /* disable initialize mode */ CAN_CTL(can_periph) &= ~CAN_CTL_IWMOD; timeout = CAN_TIMEOUT; /* wait the ACK */ - while((CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (timeout)){ + while((CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){ timeout--; } /* check exit initialize mode */ if(CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)){ flag = SUCCESS; } - } + } return flag; } /*! - \brief initialize CAN filter - \param[in] can_filter_parameter_struct: struct for CAN filter initialization - can_filter_list_high: 0x0000 - 0xFFFF - can_filter_list_low: 0x0000 - 0xFFFF - can_filter_mask_high: 0x0000 - 0xFFFF - can_filter_mask_low: 0x0000 - 0xFFFF - can_filter_fifo_number: CAN_FIFO0, CAN_FIFO1 - can_filter_number: 0 - 27 - can_filter_mode: CAN_FILTERMODE_MASK, CAN_FILTERMODE_LIST - can_filter_bits: CAN_FILTERBITS_32BIT, CAN_FILTERBITS_16BIT - can_filter_enable: ENABLE or DISABLE + \brief initialize CAN filter + \param[in] can_filter_parameter_init: struct for CAN filter initialization + \arg filter_list_high: 0x0000 - 0xFFFF + \arg filter_list_low: 0x0000 - 0xFFFF + \arg filter_mask_high: 0x0000 - 0xFFFF + \arg filter_mask_low: 0x0000 - 0xFFFF + \arg filter_fifo_number: CAN_FIFO0, CAN_FIFO1 + \arg filter_number: 0 - 27 + \arg filter_mode: CAN_FILTERMODE_MASK, CAN_FILTERMODE_LIST + \arg filter_bits: CAN_FILTERBITS_32BIT, CAN_FILTERBITS_16BIT + \arg filter_enable: ENABLE or DISABLE \param[out] none \retval none */ void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init) { uint32_t val = 0U; - + val = ((uint32_t)1) << (can_filter_parameter_init->filter_number); /* filter lock disable */ CAN_FCTL(CAN0) |= CAN_FCTL_FLD; /* disable filter */ CAN_FW(CAN0) &= ~(uint32_t)val; - + /* filter 16 bits */ if(CAN_FILTERBITS_16BIT == can_filter_parameter_init->filter_bits){ /* set filter 16 bits */ @@ -173,7 +281,7 @@ void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init) FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | FDATA_MASK_LOW((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS); } - + /* filter mode */ if(CAN_FILTERMODE_MASK == can_filter_parameter_init->filter_mode){ /* mask mode */ @@ -182,24 +290,24 @@ void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init) /* list mode */ CAN_FMCFG(CAN0) |= (uint32_t)val; } - + /* filter FIFO */ if(CAN_FIFO0 == (can_filter_parameter_init->filter_fifo_number)){ /* FIFO0 */ CAN_FAFIFO(CAN0) &= ~(uint32_t)val; } - + if(CAN_FIFO1 == can_filter_parameter_init->filter_fifo_number){ /* FIFO1 */ CAN_FAFIFO(CAN0) |= (uint32_t)val; } - + /* filter working */ if(ENABLE == can_filter_parameter_init->filter_enable){ - + CAN_FW(CAN0) |= (uint32_t)val; } - + /* filter lock enable */ CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD; } @@ -266,11 +374,11 @@ void can_debug_freeze_disable(uint32_t can_periph) void can_time_trigger_mode_enable(uint32_t can_periph) { uint8_t mailbox_number; - + /* enable the tcc mode */ CAN_CTL(can_periph) |= CAN_CTL_TTC; /* enable time stamp */ - for(mailbox_number=0U; mailbox_number<3U; mailbox_number++){ + for(mailbox_number = 0U; mailbox_number < 3U; mailbox_number++){ CAN_TMP(can_periph, mailbox_number) |= CAN_TMP_TSEN; } } @@ -284,29 +392,29 @@ void can_time_trigger_mode_enable(uint32_t can_periph) */ void can_time_trigger_mode_disable(uint32_t can_periph) { - uint8_t mailbox_number; - + uint8_t mailbox_number; + /* disable the TCC mode */ CAN_CTL(can_periph) &= ~CAN_CTL_TTC; /* reset TSEN bits */ - for(mailbox_number=0U; mailbox_number<3U; mailbox_number++){ + for(mailbox_number = 0U; mailbox_number < 3U; mailbox_number++){ CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_TSEN; } } /*! - \brief CAN transmit message + \brief transmit CAN message \param[in] can_periph \arg CANx(x=0,1) - \param[in] can_trasnmit_message_struct: struct for CAN transmit message - can_rx_sfid: 0x00000000 - 0x000007FF - can_rx_efid: 0x00000000 - 0x1FFFFFFF - can_rx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED - can_rx_ft: CAN_FT_DATA, CAN_FT_REMOTE - can_rx_dlenc: 1 - 7 - can_rx_data[]: 0x00 - 0xFF + \param[in] transmit_message: struct for CAN transmit message + \arg tx_sfid: 0x00000000 - 0x000007FF + \arg tx_efid: 0x00000000 - 0x1FFFFFFF + \arg tx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED + \arg tx_ft: CAN_FT_DATA, CAN_FT_REMOTE + \arg tx_dlen: 0 - 8 + \arg tx_data[]: 0x00 - 0xFF \param[out] none - \retval none + \retval mailbox_number */ uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message) { @@ -322,10 +430,11 @@ uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* t }else{ mailbox_number = CAN_NOMAILBOX; } + /* return no mailbox empty */ if(CAN_NOMAILBOX == mailbox_number){ return CAN_NOMAILBOX; } - + CAN_TMI(can_periph, mailbox_number) &= CAN_TMI_TEN; if(CAN_FF_STANDARD == transmit_message->tx_ff){ /* set transmit mailbox standard identifier */ @@ -357,10 +466,11 @@ uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* t } /*! - \brief CAN transmit state + \brief get CAN transmit state \param[in] can_periph \arg CANx(x=0,1) \param[in] mailbox_number + only one parameter can be selected which is shown as below: \arg CAN_MAILBOX(x=0,1,2) \param[out] none \retval can_transmit_state_enum @@ -369,14 +479,18 @@ can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox { can_transmit_state_enum state = CAN_TRANSMIT_FAILED; uint32_t val = 0U; - + + /* check selected mailbox state */ switch(mailbox_number){ + /* mailbox0 */ case CAN_MAILBOX0: val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0); break; + /* mailbox1 */ case CAN_MAILBOX1: val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1); break; + /* mailbox2 */ case CAN_MAILBOX2: val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2); break; @@ -384,32 +498,36 @@ can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox val = CAN_TRANSMIT_FAILED; break; } + switch(val){ - /* transmit pending */ - case (CAN_STATE_PENDING): + /* transmit pending */ + case (CAN_STATE_PENDING): state = CAN_TRANSMIT_PENDING; break; /* transmit failed */ - case (CAN_TSTAT_MTF0 | CAN_TSTAT_TME0): + case (CAN_TSTAT_MTF0 | CAN_TSTAT_TME0): state = CAN_TRANSMIT_FAILED; break; - case (CAN_TSTAT_MTF1 | CAN_TSTAT_TME1): + case (CAN_TSTAT_MTF1 | CAN_TSTAT_TME1): state = CAN_TRANSMIT_FAILED; break; - case (CAN_TSTAT_MTF2 | CAN_TSTAT_TME2): + case (CAN_TSTAT_MTF2 | CAN_TSTAT_TME2): state = CAN_TRANSMIT_FAILED; break; /* transmit succeeded */ case (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0): state = CAN_TRANSMIT_OK; break; + /* mailbox1 transmit succeeded */ case (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1): state = CAN_TRANSMIT_OK; break; + /* mailbox2 transmit succeeded */ case (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2): state = CAN_TRANSMIT_OK; break; - default: + /* transmit failed */ + default: state = CAN_TRANSMIT_FAILED; break; } @@ -417,10 +535,11 @@ can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox } /*! - \brief CAN stop transmission + \brief stop CAN transmission \param[in] can_periph \arg CANx(x=0,1) \param[in] mailbox_number + only one parameter can be selected which is shown as below: \arg CAN_MAILBOXx(x=0,1,2) \param[out] none \retval none @@ -429,12 +548,18 @@ void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number) { if(CAN_MAILBOX0 == mailbox_number){ CAN_TSTAT(can_periph) |= CAN_TSTAT_MST0; + while(CAN_TSTAT_MST0 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST0)){ + } }else if(CAN_MAILBOX1 == mailbox_number){ CAN_TSTAT(can_periph) |= CAN_TSTAT_MST1; + while(CAN_TSTAT_MST1 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST1)){ + } }else if(CAN_MAILBOX2 == mailbox_number){ CAN_TSTAT(can_periph) |= CAN_TSTAT_MST2; + while(CAN_TSTAT_MST2 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST2)){ + } }else{ - /* illegal parameter*/ + /* illegal parameters */ } } @@ -443,15 +568,15 @@ void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number) \param[in] can_periph \arg CANx(x=0,1) \param[in] fifo_number - \arg CAN_FIFO0x(x=0,1) - \param[out] can_receive_message_struct: struct for CAN receive message - can_rx_sfid: 0x00000000 - 0x000007FF - can_rx_efid: 0x00000000 - 0x1FFFFFFF - can_rx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED - can_rx_ft: CAN_FT_DATA, CAN_FT_REMOTE - can_rx_dlenc: 1 - 7 - can_rx_data[]: 0x00 - 0xFF - can_rx_fi: 0 - 27 + \arg CAN_FIFOx(x=0,1) + \param[out] receive_message: struct for CAN receive message + \arg rx_sfid: 0x00000000 - 0x000007FF + \arg rx_efid: 0x00000000 - 0x1FFFFFFF + \arg rx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED + \arg rx_ft: CAN_FT_DATA, CAN_FT_REMOTE + \arg rx_dlen: 0 - 8 + \arg rx_data[]: 0x00 - 0xFF + \arg rx_fi: 0 - 27 \retval none */ void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message) @@ -460,29 +585,29 @@ void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_m receive_message->rx_ff = (uint8_t)(CAN_RFIFOMI_FF & CAN_RFIFOMI(can_periph, fifo_number)); if(CAN_FF_STANDARD == receive_message->rx_ff){ /* get standard identifier */ - receive_message -> rx_sfid = (uint32_t)(RFIFOMI_SFID(CAN_RFIFOMI(can_periph, fifo_number))); + receive_message->rx_sfid = (uint32_t)(GET_RFIFOMI_SFID(CAN_RFIFOMI(can_periph, fifo_number))); }else{ /* get extended identifier */ - receive_message -> rx_efid = (uint32_t)(RFIFOMI_EFID(CAN_RFIFOMI(can_periph, fifo_number))); + receive_message->rx_efid = (uint32_t)(GET_RFIFOMI_EFID(CAN_RFIFOMI(can_periph, fifo_number))); } - + /* get frame type */ - receive_message -> rx_ft = (uint8_t)(CAN_RFIFOMI_FT & CAN_RFIFOMI(can_periph, fifo_number)); - /* get recevie data length */ - receive_message -> rx_dlen = (uint8_t)(RFIFOMP_DLENC(CAN_RFIFOMP(can_periph, fifo_number))); + receive_message->rx_ft = (uint8_t)(CAN_RFIFOMI_FT & CAN_RFIFOMI(can_periph, fifo_number)); /* filtering index */ - receive_message -> rx_fi = (uint8_t)(RFIFOMP_FI(CAN_RFIFOMP(can_periph, fifo_number))); - + receive_message->rx_fi = (uint8_t)(GET_RFIFOMP_FI(CAN_RFIFOMP(can_periph, fifo_number))); + /* get recevie data length */ + receive_message->rx_dlen = (uint8_t)(GET_RFIFOMP_DLENC(CAN_RFIFOMP(can_periph, fifo_number))); + /* receive data */ - receive_message -> rx_data[0] = (uint8_t)(RFIFOMDATA0_DB0(CAN_RFIFOMDATA0(can_periph, fifo_number))); - receive_message -> rx_data[1] = (uint8_t)(RFIFOMDATA0_DB1(CAN_RFIFOMDATA0(can_periph, fifo_number))); - receive_message -> rx_data[2] = (uint8_t)(RFIFOMDATA0_DB2(CAN_RFIFOMDATA0(can_periph, fifo_number))); - receive_message -> rx_data[3] = (uint8_t)(RFIFOMDATA0_DB3(CAN_RFIFOMDATA0(can_periph, fifo_number))); - receive_message -> rx_data[4] = (uint8_t)(RFIFOMDATA1_DB4(CAN_RFIFOMDATA1(can_periph, fifo_number))); - receive_message -> rx_data[5] = (uint8_t)(RFIFOMDATA1_DB5(CAN_RFIFOMDATA1(can_periph, fifo_number))); - receive_message -> rx_data[6] = (uint8_t)(RFIFOMDATA1_DB6(CAN_RFIFOMDATA1(can_periph, fifo_number))); - receive_message -> rx_data[7] = (uint8_t)(RFIFOMDATA1_DB7(CAN_RFIFOMDATA1(can_periph, fifo_number))); - + receive_message -> rx_data[0] = (uint8_t)(GET_RFIFOMDATA0_DB0(CAN_RFIFOMDATA0(can_periph, fifo_number))); + receive_message -> rx_data[1] = (uint8_t)(GET_RFIFOMDATA0_DB1(CAN_RFIFOMDATA0(can_periph, fifo_number))); + receive_message -> rx_data[2] = (uint8_t)(GET_RFIFOMDATA0_DB2(CAN_RFIFOMDATA0(can_periph, fifo_number))); + receive_message -> rx_data[3] = (uint8_t)(GET_RFIFOMDATA0_DB3(CAN_RFIFOMDATA0(can_periph, fifo_number))); + receive_message -> rx_data[4] = (uint8_t)(GET_RFIFOMDATA1_DB4(CAN_RFIFOMDATA1(can_periph, fifo_number))); + receive_message -> rx_data[5] = (uint8_t)(GET_RFIFOMDATA1_DB5(CAN_RFIFOMDATA1(can_periph, fifo_number))); + receive_message -> rx_data[6] = (uint8_t)(GET_RFIFOMDATA1_DB6(CAN_RFIFOMDATA1(can_periph, fifo_number))); + receive_message -> rx_data[7] = (uint8_t)(GET_RFIFOMDATA1_DB7(CAN_RFIFOMDATA1(can_periph, fifo_number))); + /* release FIFO */ if(CAN_FIFO0 == fifo_number){ CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0; @@ -495,7 +620,9 @@ void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_m \brief release FIFO0 \param[in] can_periph \arg CANx(x=0,1) - \arg CAN_FIFO0x(x=0,1) + \param[in] fifo_number + only one parameter can be selected which is shown as below: + \arg CAN_FIFOx(x=0,1) \param[out] none \retval none */ @@ -506,7 +633,8 @@ void can_fifo_release(uint32_t can_periph, uint8_t fifo_number) }else if(CAN_FIFO1 == fifo_number){ CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1; }else{ - /* illegal parameter */ + /* illegal parameters */ + CAN_ERROR_HANDLE("CAN FIFO NUM is invalid \r\n"); } } @@ -514,20 +642,24 @@ void can_fifo_release(uint32_t can_periph, uint8_t fifo_number) \brief CAN receive message length \param[in] can_periph \arg CANx(x=0,1) - \arg CAN_FIFO0x(x=0,1) + \param[in] fifo_number + only one parameter can be selected which is shown as below: + \arg CAN_FIFOx(x=0,1) \param[out] none \retval message length */ -uint8_t can_receive_message_length(uint32_t can_periph, uint8_t fifo_number) +uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number) { uint8_t val = 0U; - + if(CAN_FIFO0 == fifo_number){ - val = (uint8_t)(CAN_RFIFO0(can_periph) & CAN_RFIFO_RFL0_MASK); - }else if(CAN_FIFO0 == fifo_number){ - val = (uint8_t)(CAN_RFIFO1(can_periph) & CAN_RFIFO_RFL0_MASK); + /* FIFO0 */ + val = (uint8_t)(CAN_RFIFO0(can_periph) & CAN_RFIF_RFL_MASK); + }else if(CAN_FIFO1 == fifo_number){ + /* FIFO1 */ + val = (uint8_t)(CAN_RFIFO1(can_periph) & CAN_RFIF_RFL_MASK); }else{ - /* illegal parameter */ + /* illegal parameters */ } return val; } @@ -537,25 +669,26 @@ uint8_t can_receive_message_length(uint32_t can_periph, uint8_t fifo_number) \param[in] can_periph \arg CANx(x=0,1) \param[in] can_working_mode - \arg CAN_INITIALIZE_MODE - \arg CAN_NORMAL_MODE - \arg CAN_SLEEP_MODE + only one parameter can be selected which is shown as below: + \arg CAN_MODE_INITIALIZE + \arg CAN_MODE_NORMAL + \arg CAN_MODE_SLEEP \param[out] none \retval ErrStatus: SUCCESS or ERROR */ ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode) { ErrStatus flag = ERROR; - /* timeout for IWS or also for SLPWS bits*/ - uint32_t timeout = CAN_TIMEOUT; - + /* timeout for IWS or also for SLPWS bits */ + uint32_t timeout = CAN_TIMEOUT; + if(CAN_MODE_INITIALIZE == working_mode){ /* disable sleep mode */ CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_SLPWMOD); /* set initialize mode */ CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_IWMOD; /* wait the acknowledge */ - while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (timeout != 0U)){ + while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){ timeout--; } if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){ @@ -567,7 +700,7 @@ ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode) /* enter normal mode */ CAN_CTL(can_periph) &= ~(uint32_t)(CAN_CTL_SLPWMOD | CAN_CTL_IWMOD); /* wait the acknowledge */ - while((0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) && (timeout != 0U)){ + while((0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) && (0U != timeout)){ timeout--; } if(0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))){ @@ -581,10 +714,10 @@ ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode) /* set sleep mode */ CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_SLPWMOD; /* wait the acknowledge */ - while((CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (timeout != 0U)){ + while((CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0U != timeout)){ timeout--; } - if (CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){ + if(CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){ flag = ERROR; }else{ flag = SUCCESS; @@ -592,7 +725,7 @@ ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode) }else{ flag = ERROR; } - return flag; + return flag; } /*! @@ -606,13 +739,14 @@ ErrStatus can_wakeup(uint32_t can_periph) { ErrStatus flag = ERROR; uint32_t timeout = CAN_TIMEOUT; - + /* wakeup */ CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD; - - while((0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (timeout != 0x00U)){ + + while((0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0x00U != timeout)){ timeout--; } + /* check state */ if(0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){ flag = ERROR; }else{ @@ -627,66 +761,76 @@ ErrStatus can_wakeup(uint32_t can_periph) \arg CANx(x=0,1) \param[out] none \retval can_error_enum + \arg CAN_ERROR_NONE: no error + \arg CAN_ERROR_FILL: fill error + \arg CAN_ERROR_FORMATE: format error + \arg CAN_ERROR_ACK: ACK error + \arg CAN_ERROR_BITRECESSIVE: bit recessive + \arg CAN_ERROR_BITDOMINANTER: bit dominant error + \arg CAN_ERROR_CRC: CRC error + \arg CAN_ERROR_SOFTWARECFG: software configure */ can_error_enum can_error_get(uint32_t can_periph) { can_error_enum error; error = CAN_ERROR_NONE; - + /* get error type */ - error = (can_error_enum)((CAN_ERR(can_periph) & CAN_ERR_ERRN) >> 4U); + error = (can_error_enum)(GET_ERR_ERRN(CAN_ERR(can_periph))); return error; } /*! - \brief CAN receive error number + \brief get CAN receive error number \param[in] can_periph \arg CANx(x=0,1) \param[out] none \retval error number */ -uint8_t can_receive_error_number(uint32_t can_periph) +uint8_t can_receive_error_number_get(uint32_t can_periph) { uint8_t val; - - val = (uint8_t)((CAN_ERR(can_periph) & CAN_ERR_RECNT) >> 24U); + + /* get error count */ + val = (uint8_t)(GET_ERR_RECNT(CAN_ERR(can_periph))); return val; } /*! - \brief CAN transmit error number + \brief get CAN transmit error number \param[in] can_periph \arg CANx(x=0,1) \param[out] none \retval error number */ -uint8_t can_transmit_error_number(uint32_t can_periph) +uint8_t can_transmit_error_number_get(uint32_t can_periph) { uint8_t val; - - val = (uint8_t)((CAN_ERR(can_periph) & CAN_ERR_TECNT) >> 16U); + + val = (uint8_t)(GET_ERR_TECNT(CAN_ERR(can_periph))); return val; } /*! - \brief enable CAN interrupt + \brief enable CAN interrupt \param[in] can_periph \arg CANx(x=0,1) - \param[in] interrupt - \arg CAN_INTEN_TMEIE - \arg CAN_INTEN_RFNEIE0 - \arg CAN_INTEN_RFFIE0 - \arg CAN_INTEN_RFOIE0 - \arg CAN_INTEN_RFNEIE1 - \arg CAN_INTEN_RFFIE1 - \arg CAN_INTEN_RFOIE1 - \arg CAN_INTEN_WERRIE - \arg CAN_INTEN_PERRIE - \arg CAN_INTEN_BOIE - \arg CAN_INTEN_ERRNIE - \arg CAN_INTEN_ERRIE - \arg CAN_INTEN_WUIE - \arg CAN_INTEN_SLPWIE + \param[in] interrupt + one or more parameters can be selected which are shown as below: + \arg CAN_INT_TME: transmit mailbox empty interrupt enable + \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable + \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable + \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable + \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable + \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable + \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable + \arg CAN_INT_WERR: warning error interrupt enable + \arg CAN_INT_PERR: passive error interrupt enable + \arg CAN_INT_BO: bus-off interrupt enable + \arg CAN_INT_ERRN: error number interrupt enable + \arg CAN_INT_ERR: error interrupt enable + \arg CAN_INT_WU: wakeup interrupt enable + \arg CAN_INT_SLPW: sleep working interrupt enable \param[out] none \retval none */ @@ -696,24 +840,25 @@ void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt) } /*! - \brief disable CAN interrupt + \brief disable CAN interrupt \param[in] can_periph \arg CANx(x=0,1) \param[in] interrupt - \arg CAN_INTEN_TMEIE - \arg CAN_INTEN_RFNEIE0 - \arg CAN_INTEN_RFFIE0 - \arg CAN_INTEN_RFOIE0 - \arg CAN_INTEN_RFNEIE1 - \arg CAN_INTEN_RFFIE1 - \arg CAN_INTEN_RFOIE1 - \arg CAN_INTEN_WERRIE - \arg CAN_INTEN_PERRIE - \arg CAN_INTEN_BOIE - \arg CAN_INTEN_ERRNIE - \arg CAN_INTEN_ERRIE - \arg CAN_INTEN_WUIE - \arg CAN_INTEN_SLPWIE + one or more parameters can be selected which are shown as below: + \arg CAN_INT_TME: transmit mailbox empty interrupt enable + \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable + \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable + \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable + \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable + \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable + \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable + \arg CAN_INT_WERR: warning error interrupt enable + \arg CAN_INT_PERR: passive error interrupt enable + \arg CAN_INT_BO: bus-off interrupt enable + \arg CAN_INT_ERRN: error number interrupt enable + \arg CAN_INT_ERR: error interrupt enable + \arg CAN_INT_WU: wakeup interrupt enable + \arg CAN_INT_SLPW: sleep working interrupt enable \param[out] none \retval none */ @@ -728,24 +873,46 @@ void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt) \arg CANx(x=0,1) \param[in] flag: CAN flags, refer to can_flag_enum only one parameter can be selected which is shown as below: - \arg CAN_FLAG_MTE2 - \arg CAN_FLAG_MTE1 - \arg CAN_FLAG_MTE0 - \arg CAN_FLAG_MTF2 - \arg CAN_FLAG_MTF1 - \arg CAN_FLAG_MTF0 - \arg CAN_FLAG_RFO0 - \arg CAN_FLAG_RFF0 - \arg CAN_FLAG_RFO1 - \arg CAN_FLAG_RFF1 - \arg CAN_FLAG_BOERR - \arg CAN_FLAG_PERR - \arg CAN_FLAG_WERR + \arg CAN_FLAG_RXL: RX level + \arg CAN_FLAG_LASTRX: last sample value of RX pin + \arg CAN_FLAG_RS: receiving state + \arg CAN_FLAG_TS: transmitting state + \arg CAN_FLAG_SLPIF: status change flag of entering sleep working mode + \arg CAN_FLAG_WUIF: status change flag of wakeup from sleep working mode + \arg CAN_FLAG_ERRIF: error flag + \arg CAN_FLAG_SLPWS: sleep working state + \arg CAN_FLAG_IWS: initial working state + \arg CAN_FLAG_TMLS2: transmit mailbox 2 last sending in Tx FIFO + \arg CAN_FLAG_TMLS1: transmit mailbox 1 last sending in Tx FIFO + \arg CAN_FLAG_TMLS0: transmit mailbox 0 last sending in Tx FIFO + \arg CAN_FLAG_TME2: transmit mailbox 2 empty + \arg CAN_FLAG_TME1: transmit mailbox 1 empty + \arg CAN_FLAG_TME0: transmit mailbox 0 empty + \arg CAN_FLAG_MTE2: mailbox 2 transmit error + \arg CAN_FLAG_MTE1: mailbox 1 transmit error + \arg CAN_FLAG_MTE0: mailbox 0 transmit error + \arg CAN_FLAG_MAL2: mailbox 2 arbitration lost + \arg CAN_FLAG_MAL1: mailbox 1 arbitration lost + \arg CAN_FLAG_MAL0: mailbox 0 arbitration lost + \arg CAN_FLAG_MTFNERR2: mailbox 2 transmit finished with no error + \arg CAN_FLAG_MTFNERR1: mailbox 1 transmit finished with no error + \arg CAN_FLAG_MTFNERR0: mailbox 0 transmit finished with no error + \arg CAN_FLAG_MTF2: mailbox 2 transmit finished + \arg CAN_FLAG_MTF1: mailbox 1 transmit finished + \arg CAN_FLAG_MTF0: mailbox 0 transmit finished + \arg CAN_FLAG_RFO0: receive FIFO0 overfull + \arg CAN_FLAG_RFF0: receive FIFO0 full + \arg CAN_FLAG_RFO1: receive FIFO1 overfull + \arg CAN_FLAG_RFF1: receive FIFO1 full + \arg CAN_FLAG_BOERR: bus-off error + \arg CAN_FLAG_PERR: passive error + \arg CAN_FLAG_WERR: warning error \param[out] none \retval FlagStatus: SET or RESET */ FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag) -{ +{ + /* get flag and interrupt enable state */ if(RESET != (CAN_REG_VAL(can_periph, flag) & BIT(CAN_BIT_POS(flag)))){ return SET; }else{ @@ -755,26 +922,35 @@ FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag) /*! \brief clear CAN flag state - \param[in] can_periph + \param[in] can_periph \arg CANx(x=0,1) \param[in] flag: CAN flags, refer to can_flag_enum only one parameter can be selected which is shown as below: - \arg CAN_FLAG_MTE2 - \arg CAN_FLAG_MTE1 - \arg CAN_FLAG_MTE0 - \arg CAN_FLAG_MTF2 - \arg CAN_FLAG_MTF1 - \arg CAN_FLAG_MTF0 - \arg CAN_FLAG_RFO0 - \arg CAN_FLAG_RFF0 - \arg CAN_FLAG_RFO1 - \arg CAN_FLAG_RFF1 + \arg CAN_FLAG_SLPIF: status change flag of entering sleep working mode + \arg CAN_FLAG_WUIF: status change flag of wakeup from sleep working mode + \arg CAN_FLAG_ERRIF: error flag + \arg CAN_FLAG_MTE2: mailbox 2 transmit error + \arg CAN_FLAG_MTE1: mailbox 1 transmit error + \arg CAN_FLAG_MTE0: mailbox 0 transmit error + \arg CAN_FLAG_MAL2: mailbox 2 arbitration lost + \arg CAN_FLAG_MAL1: mailbox 1 arbitration lost + \arg CAN_FLAG_MAL0: mailbox 0 arbitration lost + \arg CAN_FLAG_MTFNERR2: mailbox 2 transmit finished with no error + \arg CAN_FLAG_MTFNERR1: mailbox 1 transmit finished with no error + \arg CAN_FLAG_MTFNERR0: mailbox 0 transmit finished with no error + \arg CAN_FLAG_MTF2: mailbox 2 transmit finished + \arg CAN_FLAG_MTF1: mailbox 1 transmit finished + \arg CAN_FLAG_MTF0: mailbox 0 transmit finished + \arg CAN_FLAG_RFO0: receive FIFO0 overfull + \arg CAN_FLAG_RFF0: receive FIFO0 full + \arg CAN_FLAG_RFO1: receive FIFO1 overfull + \arg CAN_FLAG_RFF1: receive FIFO1 full \param[out] none \retval none */ void can_flag_clear(uint32_t can_periph, can_flag_enum flag) { - CAN_REG_VAL(can_periph, flag) |= BIT(CAN_BIT_POS(flag)); + CAN_REG_VAL(can_periph, flag) = BIT(CAN_BIT_POS(flag)); } /*! @@ -783,62 +959,43 @@ void can_flag_clear(uint32_t can_periph, can_flag_enum flag) \arg CANx(x=0,1) \param[in] flag: CAN interrupt flags, refer to can_interrupt_flag_enum only one parameter can be selected which is shown as below: - \arg CAN_INT_SLPIF - \arg CAN_INT_WUIF - \arg CAN_INT_ERRIF + \arg CAN_INT_FLAG_SLPIF: status change interrupt flag of sleep working mode entering + \arg CAN_INT_FLAG_WUIF: status change interrupt flag of wakeup from sleep working mode + \arg CAN_INT_FLAG_ERRIF: error interrupt flag + \arg CAN_INT_FLAG_MTF2: mailbox 2 transmit finished interrupt flag + \arg CAN_INT_FLAG_MTF1: mailbox 1 transmit finished interrupt flag + \arg CAN_INT_FLAG_MTF0: mailbox 0 transmit finished interrupt flag + \arg CAN_INT_FLAG_RFO0: receive FIFO0 overfull interrupt flag + \arg CAN_INT_FLAG_RFF0: receive FIFO0 full interrupt flag + \arg CAN_INT_FLAG_RFL0: receive FIFO0 not empty interrupt flag + \arg CAN_INT_FLAG_RFO1: receive FIFO1 overfull interrupt flag + \arg CAN_INT_FLAG_RFF1: receive FIFO1 full interrupt flag + \arg CAN_INT_FLAG_RFL1: receive FIFO1 not empty interrupt flag + \arg CAN_INT_FLAG_ERRN: error number interrupt flag + \arg CAN_INT_FLAG_BOERR: bus-off error interrupt flag + \arg CAN_INT_FLAG_PERR: passive error interrupt flag + \arg CAN_INT_FLAG_WERR: warning error interrupt flag \param[out] none \retval FlagStatus: SET or RESET */ FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag) -{ - FlagStatus inten = RESET; - FlagStatus temp = RESET; - FlagStatus status1 = RESET; - FlagStatus status2 = RESET; - - switch(flag){ - /* get the status of sleep working interrupt enable bit */ - case CAN_INT_SLPIF: - inten = (FlagStatus)(CAN_INTEN(can_periph) & CAN_INTEN_SLPWIE); - break; - /* get the status of wakeup interrupt enable bit */ - case CAN_INT_WUIF: - inten = (FlagStatus)(CAN_INTEN(can_periph) & CAN_INTEN_WUIE); - break; - /* get the status of error falgs and its enable bit */ - case CAN_INT_ERRIF: - /* check if the BOERR bit in CAN_ERR register and BOIE bit in CAN_INTEN register are set */ - status1 = (FlagStatus)(CAN_INTEN(can_periph) & CAN_INTEN_BOIE); - status2 = (FlagStatus)(CAN_ERR(can_periph) & CAN_ERR_BOERR); - if((RESET != status1) && (RESET != status2)){ - inten = SET; - } - /* check if the WERR bit in CAN_ERR register and WERRIE bit in CAN_INTEN register are set */ - status1 = (FlagStatus)(CAN_INTEN(can_periph) & CAN_INTEN_WERRIE); - status2 = (FlagStatus)(CAN_ERR(can_periph) & CAN_ERR_WERR); - if((RESET != status1) && (RESET != status2)){ - inten = SET; - } - /* check if the PERR bit in CAN_ERR register and PERRIE bit in CAN_INTEN register are set */ - status1 = (FlagStatus)(CAN_INTEN(can_periph) & CAN_INTEN_PERRIE); - status2 = (FlagStatus)(CAN_ERR(can_periph) & CAN_ERR_PERR); - if((RESET != status1) && (RESET != status2)){ - inten = SET; - } - /* check if the ERRN bit in CAN_ERR register and ERRNIE bit in CAN_INTEN register are set */ - status1 = (FlagStatus)(CAN_INTEN(can_periph) & CAN_INTEN_ERRNIE); - status2 = (FlagStatus)(CAN_ERR(can_periph) & CAN_ERR_ERRN); - if((RESET != status1) && (RESET != status2)){ - inten = SET; - } - break; - default: - break; +{ + uint32_t ret1 = RESET; + uint32_t ret2 = RESET; + + /* get the staus of interrupt flag */ + if (flag == CAN_INT_FLAG_RFF0) { + ret1 = can_receive_message_length_get(can_periph, CAN_FIFO0); + } else if (flag == CAN_INT_FLAG_RFF1) { + ret1 = can_receive_message_length_get(can_periph, CAN_FIFO1); + } else if (flag == CAN_INT_FLAG_ERRN) { + ret1 = can_error_get(can_periph); + } else { + ret1 = CAN_REG_VALS(can_periph, flag) & BIT(CAN_BIT_POS0(flag)); } - /* get the interrupt flag */ - temp = (FlagStatus)(CAN_REG_VAL(can_periph, flag) & BIT(CAN_BIT_POS(flag))); - /* check the interrupt enable bit and corresponding flag bit are set */ - if((RESET != inten) && (RESET != temp)){ + /* get the staus of interrupt enale bit */ + ret2 = CAN_INTEN(can_periph) & BIT(CAN_BIT_POS1(flag)); + if(ret1 && ret2){ return SET; }else{ return RESET; @@ -851,13 +1008,20 @@ FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum f \arg CANx(x=0,1) \param[in] flag: CAN interrupt flags, refer to can_interrupt_flag_enum only one parameter can be selected which is shown as below: - \arg CAN_INT_SLPIF - \arg CAN_INT_WUIF - \arg CAN_INT_ERRIF + \arg CAN_INT_FLAG_SLPIF: status change interrupt flag of sleep working mode entering + \arg CAN_INT_FLAG_WUIF: status change interrupt flag of wakeup from sleep working mode + \arg CAN_INT_FLAG_ERRIF: error interrupt flag + \arg CAN_INT_FLAG_MTF2: mailbox 2 transmit finished interrupt flag + \arg CAN_INT_FLAG_MTF1: mailbox 1 transmit finished interrupt flag + \arg CAN_INT_FLAG_MTF0: mailbox 0 transmit finished interrupt flag + \arg CAN_INT_FLAG_RFO0: receive FIFO0 overfull interrupt flag + \arg CAN_INT_FLAG_RFF0: receive FIFO0 full interrupt flag + \arg CAN_INT_FLAG_RFO1: receive FIFO1 overfull interrupt flag + \arg CAN_INT_FLAG_RFF1: receive FIFO1 full interrupt flag \param[out] none \retval none */ void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag) { - CAN_REG_VAL(can_periph, flag) |= BIT(CAN_BIT_POS(flag)); + CAN_REG_VALS(can_periph, flag) = BIT(CAN_BIT_POS0(flag)); } diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_crc.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_crc.c index e51d8dc483..bfe79cb9aa 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_crc.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_crc.c @@ -1,16 +1,43 @@ /*! - \file gd32f4xx_crc.c - \brief CRC driver + \file gd32f4xx_crc.c + \brief CRC driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_crc.h" +#define CRC_DATA_RESET_VALUE ((uint32_t)0xFFFFFFFFU) +#define CRC_FDATA_RESET_VALUE ((uint32_t)0x00000000U) /*! \brief deinit CRC calculation unit \param[in] none @@ -19,13 +46,13 @@ */ void crc_deinit(void) { - CRC_DATA = (uint32_t)0xFFFFFFFFU; - CRC_FDATA = (uint32_t)0x00000000U; - CRC_CTL = CRC_CTL_RST; + CRC_DATA = CRC_DATA_RESET_VALUE; + CRC_FDATA = CRC_FDATA_RESET_VALUE; + CRC_CTL = (uint32_t)CRC_CTL_RST; } /*! - \brief reset data register to the value of initializaiton data register + \brief reset data register(CRC_DATA) to the value of 0xFFFFFFFF \param[in] none \param[out] none \retval none @@ -36,7 +63,7 @@ void crc_data_register_reset(void) } /*! - \brief read the data register + \brief read the value of the data register \param[in] none \param[out] none \retval 32-bit value of the data register @@ -49,7 +76,7 @@ uint32_t crc_data_register_read(void) } /*! - \brief read the free data register + \brief read the value of the free data register \param[in] none \param[out] none \retval 8-bit value of the free data register @@ -62,8 +89,8 @@ uint8_t crc_free_data_register_read(void) } /*! - \brief write the free data register - \param[in] free_data: specify 8-bit data + \brief write data to the free data register + \param[in] free_data: specified 8-bit data \param[out] none \retval none */ @@ -73,10 +100,10 @@ void crc_free_data_register_write(uint8_t free_data) } /*! - \brief CRC calculate a 32-bit data - \param[in] sdata: specify 32-bit data + \brief calculate the CRC value of a 32-bit data + \param[in] sdata: specified 32-bit data \param[out] none - \retval 32-bit CRC calculate value + \retval 32-bit value calculated by CRC */ uint32_t crc_single_data_calculate(uint32_t sdata) { @@ -85,11 +112,11 @@ uint32_t crc_single_data_calculate(uint32_t sdata) } /*! - \brief CRC calculate a 32-bit data array - \param[in] array: pointer to an array of 32 bit data words + \brief calculate the CRC value of an array of 32-bit values + \param[in] array: pointer to an array of 32-bit values \param[in] size: size of the array \param[out] none - \retval 32-bit CRC calculate value + \retval 32-bit value calculated by CRC */ uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size) { diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_ctc.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_ctc.c index 34431164a3..ab67c4ad73 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_ctc.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_ctc.c @@ -1,18 +1,49 @@ /*! - \file gd32f4xx_ctc.c - \brief CTC driver + \file gd32f4xx_ctc.c + \brief CTC driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_ctc.h" #define CTC_FLAG_MASK ((uint32_t)0x00000700U) +/* CTC register bit offset */ +#define CTC_TRIMVALUE_OFFSET ((uint32_t)8U) +#define CTC_TRIM_VALUE_OFFSET ((uint32_t)8U) +#define CTC_REFCAP_OFFSET ((uint32_t)16U) +#define CTC_LIMIT_VALUE_OFFSET ((uint32_t)16U) + /*! \brief reset CTC clock trim controller \param[in] none @@ -27,17 +58,40 @@ void ctc_deinit(void) } /*! - \brief configure the IRC48M trim value - \param[in] ctc_trim_value: 8-bit IRC48M trim value + \brief enable CTC trim counter + \param[in] none \param[out] none \retval none */ -void ctc_irc48m_trim_value_config(uint8_t ctc_trim_value) +void ctc_counter_enable(void) +{ + CTC_CTL0 |= (uint32_t)CTC_CTL0_CNTEN; +} + +/*! + \brief disable CTC trim counter + \param[in] none + \param[out] none + \retval none +*/ +void ctc_counter_disable(void) +{ + CTC_CTL0 &= (uint32_t)(~CTC_CTL0_CNTEN); +} + +/*! + \brief configure the IRC48M trim value + \param[in] ctc_trim_value: 8-bit IRC48M trim value + \arg 0x00 - 0x3F + \param[out] none + \retval none +*/ +void ctc_irc48m_trim_value_config(uint8_t trim_value) { /* clear TRIMVALUE bits */ CTC_CTL0 &= (~(uint32_t)CTC_CTL0_TRIMVALUE); /* set TRIMVALUE bits */ - CTC_CTL0 |= ((uint32_t)ctc_trim_value << 8); + CTC_CTL0 |= ((uint32_t)trim_value << CTC_TRIM_VALUE_OFFSET); } /*! @@ -53,86 +107,68 @@ void ctc_software_refsource_pulse_generate(void) /*! \brief configure hardware automatically trim mode - \param[in] ctc_hardmode: + \param[in] hardmode: + only one parameter can be selected which is shown as below: \arg CTC_HARDWARE_TRIM_MODE_ENABLE: hardware automatically trim mode enable \arg CTC_HARDWARE_TRIM_MODE_DISABLE: hardware automatically trim mode disable \param[out] none \retval none */ -void ctc_hardware_trim_mode_config(uint32_t ctc_hardmode) +void ctc_hardware_trim_mode_config(uint32_t hardmode) { CTC_CTL0 &= (uint32_t)(~CTC_CTL0_AUTOTRIM); - CTC_CTL0 |= (uint32_t)ctc_hardmode; -} - -/*! - \brief enable CTC counter - \param[in] none - \param[out] none - \retval none -*/ -void ctc_counter_enable(void) -{ - CTC_CTL0 |= (uint32_t)CTC_CTL0_CNTEN; -} - -/*! - \brief disable CTC counter - \param[in] none - \param[out] none - \retval none -*/ -void ctc_counter_disable(void) -{ - CTC_CTL0 &= (uint32_t)(~CTC_CTL0_CNTEN); + CTC_CTL0 |= (uint32_t)hardmode; } /*! \brief configure reference signal source polarity - \param[in] ctc_polarity: + \param[in] polarity: + only one parameter can be selected which is shown as below: \arg CTC_REFSOURCE_POLARITY_FALLING: reference signal source polarity is falling edge \arg CTC_REFSOURCE_POLARITY_RISING: reference signal source polarity is rising edge \param[out] none \retval none */ -void ctc_refsource_polarity_config(uint32_t ctc_polarity) +void ctc_refsource_polarity_config(uint32_t polarity) { CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPOL); - CTC_CTL1 |= (uint32_t)ctc_polarity; + CTC_CTL1 |= (uint32_t)polarity; } /*! \brief select USBFS or USBHS SOF signal - \param[in] ctc_usbsof: + \param[in] usbsof: \arg CTC_USBSOFSEL_USBHS: USBHS SOF signal is selected \arg CTC_USBSOFSEL_USBFS: USBFS SOF signal is selected \param[out] none \retval none */ -void ctc_usbsof_signal_select(uint32_t ctc_usbsof) +void ctc_usbsof_signal_select(uint32_t usbsof) { CTC_CTL1 &= (uint32_t)(~CTC_CTL1_USBSOFSEL); - CTC_CTL1 |= (uint32_t)ctc_usbsof; + CTC_CTL1 |= (uint32_t)usbsof; } /*! \brief select reference signal source - \param[in] ctc_refs: + \param[in] refs: + only one parameter can be selected which is shown as below: \arg CTC_REFSOURCE_GPIO: GPIO is selected - \arg CTC_REFSOURCE_LXTAL: LXTAL is clock selected + \arg CTC_REFSOURCE_LXTAL: LXTAL is selected \arg CTC_REFSOURCE_USBSOF: USBSOF is selected \param[out] none \retval none */ -void ctc_refsource_signal_select(uint32_t ctc_refs) +void ctc_refsource_signal_select(uint32_t refs) { CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFSEL); - CTC_CTL1 |= (uint32_t)ctc_refs; + CTC_CTL1 |= (uint32_t)refs; } /*! \brief configure reference signal source prescaler - \param[in] ctc_prescaler: + \param[in] prescaler: + only one parameter can be selected which is shown as below: \arg CTC_REFSOURCE_PSC_OFF: reference signal not divided \arg CTC_REFSOURCE_PSC_DIV2: reference signal divided by 2 \arg CTC_REFSOURCE_PSC_DIV4: reference signal divided by 4 @@ -144,34 +180,36 @@ void ctc_refsource_signal_select(uint32_t ctc_refs) \param[out] none \retval none */ -void ctc_refsource_prescaler_config(uint32_t ctc_prescaler) +void ctc_refsource_prescaler_config(uint32_t prescaler) { CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPSC); - CTC_CTL1 |= (uint32_t)ctc_prescaler; + CTC_CTL1 |= (uint32_t)prescaler; } /*! \brief configure clock trim base limit value - \param[in] ctc_limit_value: 8-bit clock trim base limit value + \param[in] limit_value: 8-bit clock trim base limit value + \arg 0x00 - 0xFF \param[out] none \retval none */ -void ctc_clock_limit_value_config(uint8_t ctc_limit_value) +void ctc_clock_limit_value_config(uint8_t limit_value) { CTC_CTL1 &= (uint32_t)(~CTC_CTL1_CKLIM); - CTC_CTL1 |= (uint32_t)((uint32_t)ctc_limit_value << 16); + CTC_CTL1 |= (uint32_t)((uint32_t)limit_value << CTC_LIMIT_VALUE_OFFSET); } /*! \brief configure CTC counter reload value - \param[in] ctc_reload_value: 16-bit CTC counter reload value + \param[in] reload_value: 16-bit CTC counter reload value + \arg 0x0000 - 0xFFFF \param[out] none \retval none */ -void ctc_counter_reload_value_config(uint16_t ctc_reload_value) +void ctc_counter_reload_value_config(uint16_t reload_value) { CTC_CTL1 &= (uint32_t)(~CTC_CTL1_RLVALUE); - CTC_CTL1 |= (uint32_t)ctc_reload_value; + CTC_CTL1 |= (uint32_t)reload_value; } /*! @@ -183,7 +221,7 @@ void ctc_counter_reload_value_config(uint16_t ctc_reload_value) uint16_t ctc_counter_capture_value_read(void) { uint16_t capture_value = 0U; - capture_value = (uint16_t)((CTC_STAT & CTC_STAT_REFCAP)>> 16); + capture_value = (uint16_t)((CTC_STAT & CTC_STAT_REFCAP)>> CTC_REFCAP_OFFSET); return (capture_value); } @@ -226,65 +264,71 @@ uint16_t ctc_counter_reload_value_read(void) uint8_t ctc_irc48m_trim_value_read(void) { uint8_t trim_value = 0U; - trim_value = (uint8_t)((CTC_CTL0 & CTC_CTL0_TRIMVALUE) >> 8); + trim_value = (uint8_t)((CTC_CTL0 & CTC_CTL0_TRIMVALUE) >> CTC_TRIMVALUE_OFFSET); return (trim_value); } /*! \brief enable the CTC interrupt - \param[in] ctc_interrupt: CTC interrupt enable - \arg CTC_INT_CKOKIE: clock trim OK interrupt enable - \arg CTC_INT_CKWARNIE: clock trim warning interrupt enable - \arg CTC_INT_ERRIE: error interrupt enable - \arg CTC_INT_EREFIE: expect reference interrupt enable + \param[in] interrupt: CTC interrupt enable + one or more parameters can be selected which are shown as below: + \arg CTC_INT_CKOK: clock trim OK interrupt enable + \arg CTC_INT_CKWARN: clock trim warning interrupt enable + \arg CTC_INT_ERR: error interrupt enable + \arg CTC_INT_EREF: expect reference interrupt enable \param[out] none \retval none */ -void ctc_interrupt_enable(uint32_t ctc_interrupt) +void ctc_interrupt_enable(uint32_t interrupt) { - CTC_CTL0 |= (uint32_t)ctc_interrupt; + CTC_CTL0 |= (uint32_t)interrupt; } /*! \brief disable the CTC interrupt - \param[in] ctc_interrupt: CTC interrupt enable source - \arg CTC_INT_CKOKIE: clock trim OK interrupt enable - \arg CTC_INT_CKWARNIE: clock trim warning interrupt enable - \arg CTC_INT_ERRIE: error interrupt enable - \arg CTC_INT_EREFIE: expect reference interrupt enable + \param[in] interrupt: CTC interrupt enable source + one or more parameters can be selected which are shown as below: + \arg CTC_INT_CKOK: clock trim OK interrupt enable + \arg CTC_INT_CKWARN: clock trim warning interrupt enable + \arg CTC_INT_ERR: error interrupt enable + \arg CTC_INT_EREF: expect reference interrupt enable \param[out] none \retval none */ -void ctc_interrupt_disable(uint32_t ctc_interrupt) +void ctc_interrupt_disable(uint32_t interrupt) { - CTC_CTL0 &= (uint32_t)(~ctc_interrupt); + CTC_CTL0 &= (uint32_t)(~interrupt); } /*! \brief get CTC interrupt flag - \param[in] ctc_interrupt: the CTC interrupt flag - \arg CTC_INT_CKOK: clock trim OK interrupt - \arg CTC_INT_CKWARN: clock trim warning interrupt - \arg CTC_INT_ERR: error interrupt - \arg CTC_INT_EREF: expect reference interrupt - \arg CTC_INT_CKERR: clock trim error bit interrupt - \arg CTC_INT_REFMISS: reference sync pulse miss interrupt - \arg CTC_INT_TRIMERR: trim value error interrupt + \param[in] int_flag: the CTC interrupt flag + only one parameter can be selected which is shown as below: + \arg CTC_INT_FLAG_CKOK: clock trim OK interrupt + \arg CTC_INT_FLAG_CKWARN: clock trim warning interrupt + \arg CTC_INT_FLAG_ERR: error interrupt + \arg CTC_INT_FLAG_EREF: expect reference interrupt + \arg CTC_INT_FLAG_CKERR: clock trim error bit interrupt + \arg CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt + \arg CTC_INT_FLAG_TRIMERR: trim value error interrupt \param[out] none \retval FlagStatus: SET or RESET */ -FlagStatus ctc_interrupt_flag_get(uint32_t ctc_interrupt) +FlagStatus ctc_interrupt_flag_get(uint32_t int_flag) { - uint32_t interrupt = 0U, intenable = 0U; + uint32_t interrupt_flag = 0U, intenable = 0U; - if(ctc_interrupt & CTC_FLAG_MASK){ - intenable = CTC_CTL0 & CTC_INT_ERRIE; + /* check whether the interrupt is enabled */ + if(RESET != (int_flag & CTC_FLAG_MASK)){ + intenable = CTC_CTL0 & CTC_CTL0_ERRIE; }else{ - intenable = CTC_CTL0 & ctc_interrupt; + intenable = CTC_CTL0 & int_flag; } - interrupt = CTC_STAT & ctc_interrupt; - if(interrupt && intenable){ + /* get interrupt flag status */ + interrupt_flag = CTC_STAT & int_flag; + + if(interrupt_flag && intenable){ return SET; }else{ return RESET; @@ -293,32 +337,34 @@ FlagStatus ctc_interrupt_flag_get(uint32_t ctc_interrupt) /*! \brief clear CTC interrupt flag - \param[in] ctc_interrupt: the CTC interrupt flag - \arg CTC_INT_CKOK: clock trim OK interrupt - \arg CTC_INT_CKWARN: clock trim warning interrupt - \arg CTC_INT_ERR: error interrupt - \arg CTC_INT_EREF: expect reference interrupt - \arg CTC_INT_CKERR: clock trim error bit interrupt - \arg CTC_INT_REFMISS: reference sync pulse miss interrupt - \arg CTC_INT_TRIMERR: trim value error interrupt + \param[in] int_flag: the CTC interrupt flag + only one parameter can be selected which is shown as below: + \arg CTC_INT_FLAG_CKOK: clock trim OK interrupt + \arg CTC_INT_FLAG_CKWARN: clock trim warning interrupt + \arg CTC_INT_FLAG_ERR: error interrupt + \arg CTC_INT_FLAG_EREF: expect reference interrupt + \arg CTC_INT_FLAG_CKERR: clock trim error bit interrupt + \arg CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt + \arg CTC_INT_FLAG_TRIMERR: trim value error interrupt \param[out] none \retval none -*/ -void ctc_interrupt_flag_clear(uint32_t ctc_interrupt) +*/ +void ctc_interrupt_flag_clear(uint32_t int_flag) { - if(ctc_interrupt & CTC_FLAG_MASK){ + if(RESET != (int_flag & CTC_FLAG_MASK)){ CTC_INTC |= CTC_INTC_ERRIC; }else{ - CTC_INTC |= ctc_interrupt; + CTC_INTC |= int_flag; } } /*! \brief get CTC flag - \param[in] ctc_flag: the CTC flag + \param[in] flag: the CTC flag + only one parameter can be selected which is shown as below: \arg CTC_FLAG_CKOK: clock trim OK flag - \arg CTC_FLAG_CKWARN: clock trim warning flag - \arg CTC_FLAG_ERR: error flag + \arg CTC_FLAG_CKWARN: clock trim warning flag + \arg CTC_FLAG_ERR: error flag \arg CTC_FLAG_EREF: expect reference flag \arg CTC_FLAG_CKERR: clock trim error bit \arg CTC_FLAG_REFMISS: reference sync pulse miss @@ -326,9 +372,9 @@ void ctc_interrupt_flag_clear(uint32_t ctc_interrupt) \param[out] none \retval FlagStatus: SET or RESET */ -FlagStatus ctc_flag_get(uint32_t ctc_flag) +FlagStatus ctc_flag_get(uint32_t flag) { - if(RESET != (CTC_STAT & ctc_flag)){ + if(RESET != (CTC_STAT & flag)){ return SET; }else{ return RESET; @@ -337,10 +383,11 @@ FlagStatus ctc_flag_get(uint32_t ctc_flag) /*! \brief clear CTC flag - \param[in] ctc_flag: the CTC flag + \param[in] flag: the CTC flag + only one parameter can be selected which is shown as below: \arg CTC_FLAG_CKOK: clock trim OK flag - \arg CTC_FLAG_CKWARN: clock trim warning flag - \arg CTC_FLAG_ERR: error flag + \arg CTC_FLAG_CKWARN: clock trim warning flag + \arg CTC_FLAG_ERR: error flag \arg CTC_FLAG_EREF: expect reference flag \arg CTC_FLAG_CKERR: clock trim error bit \arg CTC_FLAG_REFMISS: reference sync pulse miss @@ -348,11 +395,11 @@ FlagStatus ctc_flag_get(uint32_t ctc_flag) \param[out] none \retval none */ -void ctc_flag_clear(uint32_t ctc_flag) +void ctc_flag_clear(uint32_t flag) { - if(ctc_flag & CTC_FLAG_MASK){ + if(RESET != (flag & CTC_FLAG_MASK)){ CTC_INTC |= CTC_INTC_ERRIC; }else{ - CTC_INTC |= ctc_flag; + CTC_INTC |= flag; } } diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dac.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dac.c index 2204d08c21..3a5dd52cdd 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dac.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dac.c @@ -1,16 +1,46 @@ /*! - \file gd32f4xx_dac.c - \brief DAC driver + \file gd32f4xx_dac.c + \brief DAC driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_dac.h" +/* DAC register bit offset */ +#define DAC1_REG_OFFSET ((uint32_t)16U) +#define DH_12BIT_OFFSET ((uint32_t)16U) +#define DH_8BIT_OFFSET ((uint32_t)8U) + /*! \brief deinitialize DAC \param[in] none @@ -25,8 +55,7 @@ void dac_deinit(void) /*! \brief enable DAC - \param[in] dac_periph - \arg DACx(x =0,1) + \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ @@ -37,12 +66,11 @@ void dac_enable(uint32_t dac_periph) }else{ DAC_CTL |= DAC_CTL_DEN1; } -} +} /*! \brief disable DAC - \param[in] dac_periph - \arg DACx(x =0,1) + \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ @@ -57,8 +85,7 @@ void dac_disable(uint32_t dac_periph) /*! \brief enable DAC DMA function - \param[in] dac_periph - \arg DACx(x=0,1) + \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ @@ -73,8 +100,7 @@ void dac_dma_enable(uint32_t dac_periph) /*! \brief disable DAC DMA function - \param[in] dac_periph - \arg DACx(x=0,1) + \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ @@ -89,8 +115,7 @@ void dac_dma_disable(uint32_t dac_periph) /*! \brief enable DAC output buffer - \param[in] dac_periph - \arg DACx(x =0,1) + \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ @@ -105,8 +130,7 @@ void dac_output_buffer_enable(uint32_t dac_periph) /*! \brief disable DAC output buffer - \param[in] dac_periph - \arg DACx(x =0,1) + \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ @@ -119,10 +143,79 @@ void dac_output_buffer_disable(uint32_t dac_periph) } } +/*! + \brief get DAC output value + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval DAC output data +*/ +uint16_t dac_output_value_get(uint32_t dac_periph) +{ + uint16_t data = 0U; + if(DAC0 == dac_periph){ + /* store the DAC0 output value */ + data = (uint16_t)DAC0_DO; + }else{ + /* store the DAC1 output value */ + data = (uint16_t)DAC1_DO; + } + return data; +} + +/*! + \brief set the DAC specified data holding register value + \param[in] dac_periph: DACx(x = 0,1) + \param[in] dac_align: data alignment + only one parameter can be selected which is shown as below: + \arg DAC_ALIGN_8B_R: data right 8 bit alignment + \arg DAC_ALIGN_12B_R: data right 12 bit alignment + \arg DAC_ALIGN_12B_L: data left 12 bit alignment + \param[in] data: data to be loaded + \param[out] none + \retval none +*/ +void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data) +{ + if(DAC0 == dac_periph){ + switch(dac_align){ + /* data right 12 bit alignment */ + case DAC_ALIGN_12B_R: + DAC0_R12DH = data; + break; + /* data left 12 bit alignment */ + case DAC_ALIGN_12B_L: + DAC0_L12DH = data; + break; + /* data right 8 bit alignment */ + case DAC_ALIGN_8B_R: + DAC0_R8DH = data; + break; + default: + break; + } + }else{ + switch(dac_align){ + /* data right 12 bit alignment */ + case DAC_ALIGN_12B_R: + DAC1_R12DH = data; + break; + /* data left 12 bit alignment */ + case DAC_ALIGN_12B_L: + DAC1_L12DH = data; + break; + /* data right 8 bit alignment */ + case DAC_ALIGN_8B_R: + DAC1_R8DH = data; + break; + default: + break; + } + } +} + /*! \brief enable DAC trigger - \param[in] dac_periph - \arg DACx(x =0,1) + \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ @@ -137,8 +230,7 @@ void dac_trigger_enable(uint32_t dac_periph) /*! \brief disable DAC trigger - \param[in] dac_periph - \arg DACx(x =0,1) + \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ @@ -151,74 +243,11 @@ void dac_trigger_disable(uint32_t dac_periph) } } -/*! - \brief enable DAC software trigger - \param[in] dac_periph - \arg DACx(x =0,1) - \retval none -*/ -void dac_software_trigger_enable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_SWT |= DAC_SWT_SWTR0; - }else{ - DAC_SWT |= DAC_SWT_SWTR1; - } -} - -/*! - \brief disable DAC software trigger - \param[in] dac_periph - \arg DACx(x =0,1) - \param[out] none - \retval none -*/ -void dac_software_trigger_disable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_SWT &= ~DAC_SWT_SWTR0; - }else{ - DAC_SWT &= ~DAC_SWT_SWTR1; - } -} - -/*! - \brief enable DAC interrupt(DAC0 DMA underrun interrupt) - \param[in] dac_periph - \arg DACx(x=0,1) - \param[out] none - \retval none -*/ -void dac_interrupt_enable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL |= DAC_CTL_DDUDRIE0; - }else{ - DAC_CTL |= DAC_CTL_DDUDRIE1; - } -} - -/*! - \brief disable DAC interrupt(DAC0 DMA underrun interrupt) - \param[in] dac_periph - \arg DACx(x=0,1) - \param[out] none - \retval none -*/ -void dac_interrupt_disable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL &= ~DAC_CTL_DDUDRIE0; - }else{ - DAC_CTL &= ~DAC_CTL_DDUDRIE1; - } -} - /*! \brief set DAC trigger source - \param[in] dac_periph - \arg DACx(x =0,1) + \param[in] dac_periph: DACx(x = 0,1) \param[in] triggersource: external triggers of DAC + only one parameter can be selected which is shown as below: \arg DAC_TRIGGER_T1_TRGO: TIMER1 TRGO \arg DAC_TRIGGER_T3_TRGO: TIMER3 TRGO \arg DAC_TRIGGER_T4_TRGO: TIMER4 TRGO @@ -233,19 +262,50 @@ void dac_interrupt_disable(uint32_t dac_periph) void dac_trigger_source_config(uint32_t dac_periph,uint32_t triggersource) { if(DAC0 == dac_periph){ + /* configure DAC0 trigger source */ DAC_CTL &= ~DAC_CTL_DTSEL0; DAC_CTL |= triggersource; }else{ + /* configure DAC1 trigger source */ DAC_CTL &= ~DAC_CTL_DTSEL1; - DAC_CTL |= (triggersource << 16); + DAC_CTL |= (triggersource << DAC1_REG_OFFSET); + } +} + +/*! + \brief enable DAC software trigger + \param[in] dac_periph: DACx(x = 0,1) + \retval none +*/ +void dac_software_trigger_enable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph){ + DAC_SWT |= DAC_SWT_SWTR0; + }else{ + DAC_SWT |= DAC_SWT_SWTR1; + } +} + +/*! + \brief disable DAC software trigger + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval none +*/ +void dac_software_trigger_disable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph){ + DAC_SWT &= ~DAC_SWT_SWTR0; + }else{ + DAC_SWT &= ~DAC_SWT_SWTR1; } } /*! \brief configure DAC wave mode - \param[in] dac_periph - \arg DACx(x=0,1) - \param[in] wave_mode + \param[in] dac_periph: DACx(x = 0,1) + \param[in] wave_mode: noise wave mode + only one parameter can be selected which is shown as below: \arg DAC_WAVE_DISABLE: wave disable \arg DAC_WAVE_MODE_LFSR: LFSR noise mode \arg DAC_WAVE_MODE_TRIANGLE: triangle noise mode @@ -255,19 +315,21 @@ void dac_trigger_source_config(uint32_t dac_periph,uint32_t triggersource) void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode) { if(DAC0 == dac_periph){ + /* configure DAC0 wave mode */ DAC_CTL &= ~DAC_CTL_DWM0; DAC_CTL |= wave_mode; }else{ + /* configure DAC1 wave mode */ DAC_CTL &= ~DAC_CTL_DWM1; - DAC_CTL |= wave_mode << 16; + DAC_CTL |= (wave_mode << DAC1_REG_OFFSET); } } /*! \brief configure DAC wave bit width - \param[in] dac_periph - \arg DACx(x=0,1) - \param[in] bit_width + \param[in] dac_periph: DACx(x = 0,1) + \param[in] bit_width: noise wave bit width + only one parameter can be selected which is shown as below: \arg DAC_WAVE_BIT_WIDTH_1: bit width of the wave signal is 1 \arg DAC_WAVE_BIT_WIDTH_2: bit width of the wave signal is 2 \arg DAC_WAVE_BIT_WIDTH_3: bit width of the wave signal is 3 @@ -286,19 +348,21 @@ void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode) void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width) { if(DAC0 == dac_periph){ + /* configure DAC0 wave bit width */ DAC_CTL &= ~DAC_CTL_DWBW0; DAC_CTL |= bit_width; }else{ + /* configure DAC1 wave bit width */ DAC_CTL &= ~DAC_CTL_DWBW1; - DAC_CTL |= bit_width << 16; + DAC_CTL |= (bit_width << DAC1_REG_OFFSET); } } /*! \brief configure DAC LFSR noise mode - \param[in] dac_periph - \arg DACx(x=0,1) - \param[in] unmask_bits + \param[in] dac_periph: DACx(x = 0,1) + \param[in] unmask_bits: unmask LFSR bits in DAC LFSR noise mode + only one parameter can be selected which is shown as below: \arg DAC_LFSR_BIT0: unmask the LFSR bit0 \arg DAC_LFSR_BITS1_0: unmask the LFSR bits[1:0] \arg DAC_LFSR_BITS2_0: unmask the LFSR bits[2:0] @@ -317,19 +381,21 @@ void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width) void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits) { if(DAC0 == dac_periph){ + /* configure DAC0 LFSR noise mode */ DAC_CTL &= ~DAC_CTL_DWBW0; DAC_CTL |= unmask_bits; }else{ + /* configure DAC1 LFSR noise mode */ DAC_CTL &= ~DAC_CTL_DWBW1; - DAC_CTL |= unmask_bits << 16; + DAC_CTL |= (unmask_bits << DAC1_REG_OFFSET); } } /*! \brief configure DAC triangle noise mode - \param[in] dac_periph - \arg DACx(x=0,1) - \param[in] amplitude + \param[in] dac_periph: DACx(x = 0,1) + \param[in] amplitude: triangle amplitude in DAC triangle noise mode + only one parameter can be selected which is shown as below: \arg DAC_TRIANGLE_AMPLITUDE_1: triangle amplitude is 1 \arg DAC_TRIANGLE_AMPLITUDE_3: triangle amplitude is 3 \arg DAC_TRIANGLE_AMPLITUDE_7: triangle amplitude is 7 @@ -348,32 +414,16 @@ void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits) void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude) { if(DAC0 == dac_periph){ + /* configure DAC0 triangle noise mode */ DAC_CTL &= ~DAC_CTL_DWBW0; DAC_CTL |= amplitude; }else{ + /* configure DAC1 triangle noise mode */ DAC_CTL &= ~DAC_CTL_DWBW1; - DAC_CTL |= amplitude << 16; + DAC_CTL |= (amplitude << DAC1_REG_OFFSET); } } -/*! - \brief get DAC output value - \param[in] dac_periph - \arg DACx(x=0,1) - \param[out] none - \retval DAC output data -*/ -uint16_t dac_output_value_get(uint32_t dac_periph) -{ - uint16_t data = 0U; - if(DAC0 == dac_periph){ - data = (uint16_t)DAC0_DO; - }else{ - data = (uint16_t)DAC1_DO; - } - return data; -} - /*! \brief enable DAC concurrent mode \param[in] none @@ -410,7 +460,7 @@ void dac_concurrent_software_trigger_enable(void) { uint32_t swt = 0U; swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1; - DAC_SWT |= (swt); + DAC_SWT |= (swt); } /*! @@ -452,6 +502,42 @@ void dac_concurrent_output_buffer_disable(void) DAC_CTL |= (ctl); } +/*! + \brief set DAC concurrent mode data holding register value + \param[in] dac_align: data alignment + only one parameter can be selected which is shown as below: + \arg DAC_ALIGN_8B_R: data right 8b alignment + \arg DAC_ALIGN_12B_R: data right 12b alignment + \arg DAC_ALIGN_12B_L: data left 12b alignment + \param[in] data0: data to be loaded + \param[in] data1: data to be loaded + \param[out] none + \retval none +*/ +void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1) +{ + uint32_t data = 0U; + switch(dac_align){ + /* data right 12b alignment */ + case DAC_ALIGN_12B_R: + data = ((uint32_t)data1 << DH_12BIT_OFFSET) | data0; + DACC_R12DH = data; + break; + /* data left 12b alignment */ + case DAC_ALIGN_12B_L: + data = ((uint32_t)data1 << DH_12BIT_OFFSET) | data0; + DACC_L12DH = data; + break; + /* data right 8b alignment */ + case DAC_ALIGN_8B_R: + data = ((uint32_t)data1 << DH_8BIT_OFFSET) | data0; + DACC_R8DH = data; + break; + default: + break; + } +} + /*! \brief enable DAC concurrent interrupt funcution \param[in] none @@ -479,97 +565,40 @@ void dac_concurrent_interrupt_disable(void) } /*! - \brief set the DAC specified data holding register value - \param[in] dac_periph - \arg DACx(x=0,1) - \param[in] dac_align - \arg DAC_ALIGN_8B_R: data right 8b alignment - \arg DAC_ALIGN_12B_R: data right 12b alignment - \arg DAC_ALIGN_12B_L: data left 12b alignment - \param[in] data: data to be loaded + \brief enable DAC interrupt(DAC DMA underrun interrupt) + \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ -void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data) +void dac_interrupt_enable(uint32_t dac_periph) { if(DAC0 == dac_periph){ - switch(dac_align){ - /* data right 12b alignment */ - case DAC_ALIGN_12B_R: - DAC0_R12DH = data; - break; - /* data left 12b alignment */ - case DAC_ALIGN_12B_L: - DAC0_L12DH = data; - break; - /* data right 8b alignment */ - case DAC_ALIGN_8B_R: - DAC0_R8DH = data; - break; - default: - break; - } + DAC_CTL |= DAC_CTL_DDUDRIE0; }else{ - switch(dac_align){ - /* data right 12b alignment */ - case DAC_ALIGN_12B_R: - DAC1_R12DH = data; - break; - /* data left 12b alignment */ - case DAC_ALIGN_12B_L: - DAC1_L12DH = data; - break; - /* data right 8b alignment */ - case DAC_ALIGN_8B_R: - DAC1_R8DH = data; - break; - default: - break; - } + DAC_CTL |= DAC_CTL_DDUDRIE1; } } /*! - \brief set DAC concurrent mode data holding register value - \param[in] dac_align - \arg DAC_ALIGN_8B_R: data right 8b alignment - \arg DAC_ALIGN_12B_R: data right 12b alignment - \arg DAC_ALIGN_12B_L: data left 12b alignment - \param[in] data0: data to be loaded - \param[in] data1: data to be loaded + \brief disable DAC interrupt(DAC DMA underrun interrupt) + \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ -void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1) +void dac_interrupt_disable(uint32_t dac_periph) { - uint32_t data = 0U; - switch(dac_align){ - /* data right 12b alignment */ - case DAC_ALIGN_12B_R: - data = ((uint32_t)data1 << 16) | data0; - DACC_R12DH = data; - break; - /* data left 12b alignment */ - case DAC_ALIGN_12B_L: - data = ((uint32_t)data1 << 16) | data0; - DACC_L12DH = data; - break; - /* data right 8b alignment */ - case DAC_ALIGN_8B_R: - data = ((uint32_t)data1 << 8) | data0; - DACC_R8DH = data; - break; - default: - break; + if(DAC0 == dac_periph){ + DAC_CTL &= ~DAC_CTL_DDUDRIE0; + }else{ + DAC_CTL &= ~DAC_CTL_DDUDRIE1; } } /*! - \brief get the specified DAC flag(DAC DMA underrun flag) - \param[in] dac_periph - \arg DACx(x=0,1) + \brief get the specified DAC flag (DAC DMA underrun flag) + \param[in] dac_periph: DACx(x = 0,1) \param[out] none - \retval the state of dac bit(SET or RESET) + \retval FlagStatus: SET or RESET */ FlagStatus dac_flag_get(uint32_t dac_periph) { @@ -589,9 +618,8 @@ FlagStatus dac_flag_get(uint32_t dac_periph) } /*! - \brief clear the specified DAC flag(DAC DMA underrun flag) - \param[in] dac_periph - \arg DACx(x=0,1) + \brief clear the specified DAC flag (DAC DMA underrun flag) + \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ @@ -605,16 +633,16 @@ void dac_flag_clear(uint32_t dac_periph) } /*! - \brief get the specified DAC interrupt flag(DAC DMA underrun interrupt flag) - \param[in] dac_periph - \arg DACx(x=0,1) + \brief get the specified DAC interrupt flag (DAC DMA underrun interrupt flag) + \param[in] dac_periph: DACx(x = 0,1) \param[out] none - \retval the state of DAC interrupt flag(SET or RESET) + \retval FlagStatus: SET or RESET */ FlagStatus dac_interrupt_flag_get(uint32_t dac_periph) { FlagStatus temp_flag = RESET; uint32_t ddudr_flag = 0U, ddudrie_flag = 0U; + if(DAC0 == dac_periph){ /* check the DMA underrun flag and DAC DMA underrun interrupt enable flag */ ddudr_flag = DAC_STAT & DAC_STAT_DDUDR0; @@ -634,9 +662,8 @@ FlagStatus dac_interrupt_flag_get(uint32_t dac_periph) } /*! - \brief clear the specified DAC interrupt flag(DAC DMA underrun interrupt flag) - \param[in] dac_periph - \arg DACx(x=0,1) + \brief clear the specified DAC interrupt flag (DAC DMA underrun interrupt flag) + \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dbg.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dbg.c index a017c7e3e5..a408136ea4 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dbg.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dbg.c @@ -1,16 +1,55 @@ /*! - \file gd32f4xx_dbg.c - \brief DBG driver + \file gd32f4xx_dbg.c + \brief DBG driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_dbg.h" +#define DBG_RESET_VAL 0x00000000U + +/*! + \brief deinitialize the DBG + \param[in] none + \param[out] none + \retval none +*/ +void dbg_deinit(void) +{ + DBG_CTL0 = DBG_RESET_VAL; + DBG_CTL1 = DBG_RESET_VAL; +} + /*! \brief read DBG_ID code register \param[in] none @@ -55,32 +94,69 @@ void dbg_low_power_disable(uint32_t dbg_low_power) /*! \brief enable peripheral behavior when the mcu is in debug mode \param[in] dbg_periph: dbg_periph_enum - \param[out] none + only one parameter can be selected which is shown as below: + \arg DBG_TIMER1_HOLD: hold TIMER1 counter when core is halted + \arg DBG_TIMER2_HOLD: hold TIMER2 counter when core is halted + \arg DBG_TIMER3_HOLD: hold TIMER3 counter when core is halted + \arg DBG_TIMER4_HOLD: hold TIMER4 counter when core is halted + \arg DBG_TIMER5_HOLD: hold TIMER5 counter when core is halted + \arg DBG_TIMER6_HOLD: hold TIMER6 counter when core is halted + \arg DBG_TIMER11_HOLD: hold TIMER11 counter when core is halted + \arg DBG_TIMER12_HOLD: hold TIMER12 counter when core is halted + \arg DBG_TIMER13_HOLD: hold TIMER13 counter when core is halted + \arg DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted + \arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted + \arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted + \arg DBG_I2C0_HOLD: hold I2C0 smbus when core is halted + \arg DBG_I2C1_HOLD: hold I2C1 smbus when core is halted + \arg DBG_I2C2_HOLD: hold I2C2 smbus when core is halted + \arg DBG_CAN0_HOLD: debug CAN0 kept when core is halted + \arg DBG_CAN1_HOLD: debug CAN1 kept when core is halted + \arg DBG_TIMER0_HOLD: hold TIMER0 counter when core is halted + \arg DBG_TIMER7_HOLD: hold TIMER7 counter when core is halted + \arg DBG_TIMER8_HOLD: hold TIMER8 counter when core is halted + \arg DBG_TIMER9_HOLD: hold TIMER9 counter when core is halted + \arg DBG_TIMER10_HOLD: hold TIMER10 counter when core is halted + \arg \param[out] none \retval none */ void dbg_periph_enable(dbg_periph_enum dbg_periph) { - if(RESET == ((uint32_t)dbg_periph & BIT(30))){ - DBG_CTL1 |= (uint32_t)dbg_periph; - }else{ - DBG_CTL2 |= ((uint32_t)dbg_periph & (~BIT(30))); - } - + DBG_REG_VAL(dbg_periph) |= BIT(DBG_BIT_POS(dbg_periph)); } /*! \brief disable peripheral behavior when the mcu is in debug mode \param[in] dbg_periph: dbg_periph_enum + only one parameter can be selected which is shown as below: + \arg DBG_TIMER1_HOLD: hold TIMER1 counter when core is halted + \arg DBG_TIMER2_HOLD: hold TIMER2 counter when core is halted + \arg DBG_TIMER3_HOLD: hold TIMER3 counter when core is halted + \arg DBG_TIMER4_HOLD: hold TIMER4 counter when core is halted + \arg DBG_TIMER5_HOLD: hold TIMER5 counter when core is halted + \arg DBG_TIMER6_HOLD: hold TIMER6 counter when core is halted + \arg DBG_TIMER11_HOLD: hold TIMER11 counter when core is halted + \arg DBG_TIMER12_HOLD: hold TIMER12 counter when core is halted + \arg DBG_TIMER13_HOLD: hold TIMER13 counter when core is halted + \arg DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted + \arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted + \arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted + \arg DBG_I2C0_HOLD: hold I2C0 smbus when core is halted + \arg DBG_I2C1_HOLD: hold I2C1 smbus when core is halted + \arg DBG_I2C2_HOLD: hold I2C2 smbus when core is halted + \arg DBG_CAN0_HOLD: debug CAN0 kept when core is halted + \arg DBG_CAN1_HOLD: debug CAN1 kept when core is halted + \arg DBG_TIMER0_HOLD: hold TIMER0 counter when core is halted + \arg DBG_TIMER7_HOLD: hold TIMER7 counter when core is halted + \arg DBG_TIMER8_HOLD: hold TIMER8 counter when core is halted + \arg DBG_TIMER9_HOLD: hold TIMER9 counter when core is halted + \arg DBG_TIMER10_HOLD: hold TIMER10 counter when core is halted \param[out] none \retval none */ void dbg_periph_disable(dbg_periph_enum dbg_periph) { - if(RESET == ((uint32_t)dbg_periph & BIT(30))){ - DBG_CTL1 &= ~(uint32_t)dbg_periph; - }else{ - DBG_CTL2 &= ~((uint32_t)dbg_periph & (~BIT(30))); - } + DBG_REG_VAL(dbg_periph) &= ~BIT(DBG_BIT_POS(dbg_periph)); } /*! @@ -106,9 +182,9 @@ void dbg_trace_pin_disable(void) } /*! - \brief trace pin mode selection + \brief trace pin mode selection \param[in] trace_mode: - \arg TRACE_MODE_ASYNC: trace pin used for async mode + \arg TRACE_MODE_ASYNC: trace pin used for async mode \arg TRACE_MODE_SYNC_DATASIZE_1: trace pin used for sync mode and data size is 1 \arg TRACE_MODE_SYNC_DATASIZE_2: trace pin used for sync mode and data size is 2 \arg TRACE_MODE_SYNC_DATASIZE_4: trace pin used for sync mode and data size is 4 diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dci.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dci.c index 2984ff11f7..a1ddcab384 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dci.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dci.c @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_dci.c - \brief DCI driver + \file gd32f4xx_dci.c + \brief DCI driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_dci.h" @@ -25,11 +50,11 @@ void dci_deinit(void) /*! \brief initialize DCI registers - \param[in] dci_struct: DCI parameter initialization stuct + \param[in] dci_struct: DCI parameter initialization structure members of the structure and the member values are shown as below: capture_mode : DCI_CAPTURE_MODE_CONTINUOUS, DCI_CAPTURE_MODE_SNAPSHOT colck_polarity : DCI_CK_POLARITY_FALLING, DCI_CK_POLARITY_RISING - hsync_polarity : DCI_HSYNC_POLARITY_LOW, DCI_HSYNC_POLARITY_HIGH + hsync_polarity : DCI_HSYNC_POLARITY_LOW, DCI_HSYNC_POLARITY_HIGH vsync_polarity : DCI_VSYNC_POLARITY_LOW, DCI_VSYNC_POLARITY_HIGH frame_rate : DCI_FRAME_RATE_ALL, DCI_FRAME_RATE_1_2, DCI_FRAME_RATE_1_4 interface_format: DCI_INTERFACE_FORMAT_8BITS, DCI_INTERFACE_FORMAT_10BITS, @@ -39,10 +64,10 @@ void dci_deinit(void) */ void dci_init(dci_parameter_struct* dci_struct) { - uint32_t reg =0U; + uint32_t reg = 0U; /* disable capture function and DCI */ DCI_CTL &= ~(DCI_CTL_CAP | DCI_CTL_DCIEN); - /* config DCI parameter */ + /* configure DCI parameter */ reg |= dci_struct->capture_mode; reg |= dci_struct->clock_polarity; reg |= dci_struct->hsync_polarity; @@ -54,18 +79,18 @@ void dci_init(dci_parameter_struct* dci_struct) } /*! - \brief enable DCI function + \brief enable DCI function \param[in] none \param[out] none \retval none */ void dci_enable(void) { - DCI_CTL |= DCI_CTL_DCIEN; + DCI_CTL |= DCI_CTL_DCIEN; } /*! - \brief disable DCI function + \brief disable DCI function \param[in] none \param[out] none \retval none @@ -76,7 +101,7 @@ void dci_disable(void) } /*! - \brief enable DCI capture + \brief enable DCI capture \param[in] none \param[out] none \retval none @@ -87,7 +112,7 @@ void dci_capture_enable(void) } /*! - \brief disable DCI capture + \brief disable DCI capture \param[in] none \param[out] none \retval none @@ -98,7 +123,7 @@ void dci_capture_disable(void) } /*! - \brief enable DCI jpeg mode + \brief enable DCI jpeg mode \param[in] none \param[out] none \retval none @@ -109,7 +134,7 @@ void dci_jpeg_enable(void) } /*! - \brief disable DCI jpeg mode + \brief disable DCI jpeg mode \param[in] none \param[out] none \retval none @@ -142,11 +167,11 @@ void dci_crop_window_disable(void) } /*! - \brief config DCI cropping window + \brief configure DCI cropping window \param[in] start_x: window horizontal start position \param[in] start_y: window vertical start position - \param[in] size_height: window horizontal size - \param[in] size_width: window vertical size + \param[in] size_width: window horizontal size + \param[in] size_height: window vertical size \param[out] none \retval none */ @@ -157,28 +182,28 @@ void dci_crop_window_config(uint16_t start_x, uint16_t start_y, uint16_t size_wi } /*! - \brief enable sync codes function + \brief enable embedded synchronous mode \param[in] none \param[out] none \retval none */ -void dci_sync_codes_enable(void) +void dci_embedded_sync_enable(void) { DCI_CTL |= DCI_CTL_ESM; } /*! - \brief disable sync codes function + \brief disble embedded synchronous mode \param[in] none \param[out] none \retval none */ -void dci_sync_codes_disable(void) +void dci_embedded_sync_disable(void) { DCI_CTL &= ~DCI_CTL_ESM; } /*! - \brief config sync codes + \brief config synchronous codes in embedded synchronous mode \param[in] frame_start: frame start code in embedded synchronous mode \param[in] line_start: line start code in embedded synchronous mode \param[in] line_end: line end code in embedded synchronous mode @@ -192,7 +217,7 @@ void dci_sync_codes_config(uint8_t frame_start, uint8_t line_start, uint8_t line } /*! - \brief config sync codes unmask + \brief config synchronous codes unmask in embedded synchronous mode \param[in] frame_start: frame start code unmask bits in embedded synchronous mode \param[in] line_start: line start code unmask bits in embedded synchronous mode \param[in] line_end: line end code unmask bits in embedded synchronous mode @@ -202,7 +227,7 @@ void dci_sync_codes_config(uint8_t frame_start, uint8_t line_start, uint8_t line */ void dci_sync_codes_unmask_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end) { - DCI_SCUMSK = ((uint32_t)frame_start | ((uint32_t)line_start<<8) | ((uint32_t)line_end<<16) | ((uint32_t)frame_end<<24)); + DCI_SCUMSK = ((uint32_t)frame_start | ((uint32_t)line_start<<8) | ((uint32_t)line_end<<16) | ((uint32_t)frame_end<<24)); } /*! @@ -216,13 +241,46 @@ uint32_t dci_data_read(void) return DCI_DATA; } +/*! + \brief get specified flag + \param[in] flag: + \arg DCI_FLAG_HS: HS line status + \arg DCI_FLAG_VS: VS line status + \arg DCI_FLAG_FV:FIFO valid + \arg DCI_FLAG_EF: end of frame flag + \arg DCI_FLAG_OVR: FIFO overrun flag + \arg DCI_FLAG_ESE: embedded synchronous error flag + \arg DCI_FLAG_VSYNC: vsync flag + \arg DCI_FLAG_EL: end of line flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus dci_flag_get(uint32_t flag) +{ + uint32_t stat = 0U; + + if(flag >> 31){ + /* get flag status from DCI_STAT1 register */ + stat = DCI_STAT1; + }else{ + /* get flag status from DCI_STAT0 register */ + stat = DCI_STAT0; + } + + if(flag & stat){ + return SET; + }else{ + return RESET; + } +} + /*! \brief enable specified DCI interrupt \param[in] interrupt: \arg DCI_INT_EF: end of frame interrupt \arg DCI_INT_OVR: FIFO overrun interrupt - \arg DCI_INT_ESE: embedded synchronous error interrupt - \arg DCI_INT_VS: vsync interrupt + \arg DCI_INT_ESE: embedded synchronous error interrupt + \arg DCI_INT_VSYNC: vsync interrupt \arg DCI_INT_EL: end of line interrupt \param[out] none \retval none @@ -237,8 +295,8 @@ void dci_interrupt_enable(uint32_t interrupt) \param[in] interrupt: \arg DCI_INT_EF: end of frame interrupt \arg DCI_INT_OVR: FIFO overrun interrupt - \arg DCI_INT_ESE: embedded synchronous error interrupt - \arg DCI_INT_VS: vsync interrupt + \arg DCI_INT_ESE: embedded synchronous error interrupt + \arg DCI_INT_VSYNC: vsync interrupt \arg DCI_INT_EL: end of line interrupt \param[out] none \retval none @@ -249,93 +307,39 @@ void dci_interrupt_disable(uint32_t interrupt) } /*! - \brief clear specified interrupt - \param[in] interrupt: + \brief clear specified interrupt flag + \param[in] int_flag: \arg DCI_INT_EF: end of frame interrupt \arg DCI_INT_OVR: FIFO overrun interrupt - \arg DCI_INT_ESE: embedded synchronous error interrupt - \arg DCI_INT_VS: vsync interrupt + \arg DCI_INT_ESE: embedded synchronous error interrupt + \arg DCI_INT_VSYNC: vsync interrupt \arg DCI_INT_EL: end of line interrupt \param[out] none \retval none */ -void dci_interrupt_clear(uint32_t interrupt) +void dci_interrupt_flag_clear(uint32_t int_flag) { - DCI_INTC |= interrupt; -} - -/*! - \brief get specified flag - \param[in] flag: - \arg DCI_FLAG_HS: HS line status - \arg DCI_FLAG_VS: VS line status - \arg DCI_FLAG_FV:FIFO valid - \arg DCI_FLAG_EFF: end of frame flag - \arg DCI_FLAG_OVRF: FIFO overrun flag - \arg DCI_FLAG_ESEF: embedded synchronous error flag - \arg DCI_FLAG_VSF: vsync flag - \arg DCI_FLAG_ELF: end of line flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus dci_flag_get(uint32_t flag) -{ - uint32_t ret = 0U; - - switch(flag){ - /* get flag status from DCI_STAT0 register */ - case DCI_FLAG_HS: - ret = (DCI_STAT0 & DCI_STAT0_HS); - break; - case DCI_FLAG_VS: - ret = (DCI_STAT0 & DCI_STAT0_VS); - break; - case DCI_FLAG_FV: - ret = (DCI_STAT0 & DCI_STAT0_FV); - break; - /* get flag status from DCI_STAT1 register */ - case DCI_FLAG_EFF: - ret = (DCI_STAT1 & DCI_STAT1_EFF); - break; - case DCI_FLAG_OVRF: - ret = (DCI_STAT1 & DCI_STAT1_OVRF); - break; - case DCI_FLAG_ESEF: - ret = (DCI_STAT1 & DCI_STAT1_ESEF); - break; - case DCI_FLAG_VSF: - ret = (DCI_STAT1 & DCI_STAT1_VSF); - break; - case DCI_FLAG_ELF: - ret = (DCI_STAT1 & DCI_STAT1_ELF); - break; - default : - break; - } - - if(RESET == ret){ - return RESET; - }else{ - return SET; - } + DCI_INTC |= int_flag; } /*! \brief get specified interrupt flag - \param[in] interrupt: - \arg DCI_INT_EF: end of frame interrupt - \arg DCI_INT_OVR: FIFO overrun interrupt - \arg DCI_INT_ESE: embedded synchronous error interrupt - \arg DCI_INT_VS: vsync interrupt - \arg DCI_INT_EL: end of line interrupt + \param[in] int_flag: + \arg DCI_INT_FLAG_EF: end of frame interrupt flag + \arg DCI_INT_FLAG_OVR: FIFO overrun interrupt flag + \arg DCI_INT_FLAG_ESE: embedded synchronous error interrupt flag + \arg DCI_INT_FLAG_VSYNC: vsync interrupt flag + \arg DCI_INT_FLAG_EL: end of line interrupt flag \param[out] none \retval FlagStatus: SET or RESET */ -FlagStatus dci_interrupt_flag_get(uint32_t interrupt) +FlagStatus dci_interrupt_flag_get(uint32_t int_flag) { - if(RESET == (DCI_INTF & interrupt)){ + if(RESET == (DCI_INTF & int_flag)){ return RESET; }else{ return SET; } } + + diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dma.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dma.c index c7f5ce9a70..d8bd7be2d7 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dma.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dma.c @@ -1,14 +1,40 @@ /*! - \file gd32f4xx_dma.c - \brief DMA driver + \file gd32f4xx_dma.c + \brief DMA driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ + #include "gd32f4xx_dma.h" /* DMA register bit offset */ @@ -23,7 +49,7 @@ \param[out] none \retval none */ -void dma_deinit(uint32_t dma_periph,dma_channel_enum channelx) +void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx) { /* disable DMA a channel */ DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_CHEN; @@ -37,10 +63,54 @@ void dma_deinit(uint32_t dma_periph,dma_channel_enum channelx) if(channelx < DMA_CH4){ DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE,channelx); }else{ + channelx -= (dma_channel_enum)4; DMA_INTC1(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE,channelx); } } +/*! + \brief initialize the DMA single data mode parameters struct with the default values + \param[in] init_struct: the initialization data needed to initialize DMA channel + \param[out] none + \retval none +*/ +void dma_single_data_para_struct_init(dma_single_data_parameter_struct* init_struct) +{ + /* set the DMA struct with the default values */ + init_struct->periph_addr = 0U; + init_struct->periph_inc = DMA_PERIPH_INCREASE_DISABLE; + init_struct->memory0_addr = 0U; + init_struct->memory_inc = DMA_MEMORY_INCREASE_DISABLE; + init_struct->periph_memory_width = 0U; + init_struct->circular_mode = DMA_CIRCULAR_MODE_DISABLE; + init_struct->direction = DMA_PERIPH_TO_MEMORY; + init_struct->number = 0U; + init_struct->priority = DMA_PRIORITY_LOW; +} + +/*! + \brief initialize the DMA multi data mode parameters struct with the default values + \param[in] init_struct: the initialization data needed to initialize DMA channel + \param[out] none + \retval none +*/ +void dma_multi_data_para_struct_init(dma_multi_data_parameter_struct* init_struct) +{ + /* set the DMA struct with the default values */ + init_struct->periph_addr = 0U; + init_struct->periph_width = 0U; + init_struct->periph_inc = DMA_PERIPH_INCREASE_DISABLE; + init_struct->memory0_addr = 0U; + init_struct->memory_width = 0U; + init_struct->memory_inc = DMA_MEMORY_INCREASE_DISABLE; + init_struct->memory_burst_width = 0U; + init_struct->periph_burst_width = 0U; + init_struct->circular_mode = DMA_CIRCULAR_MODE_DISABLE; + init_struct->direction = DMA_PERIPH_TO_MEMORY; + init_struct->number = 0U; + init_struct->priority = DMA_PRIORITY_LOW; +} + /*! \brief initialize DMA single data mode \param[in] dma_periph: DMAx(x=0,1) @@ -49,57 +119,57 @@ void dma_deinit(uint32_t dma_periph,dma_channel_enum channelx) \arg DMA_CHx(x=0..7) \param[in] init_struct: the data needed to initialize DMA single data mode periph_addr: peripheral base address - periph_memory_width: DMA_PERIPH_WIDTH_8BIT,DMA_PERIPH_WIDTH_16BIT,DMA_PERIPH_WIDTH_32BIT - periph_inc: DMA_PERIPH_INCREASE_ENABLE,DMA_PERIPH_INCREASE_DISABLE,DMA_PERIPH_INCREASE_FIX + periph_inc: DMA_PERIPH_INCREASE_ENABLE,DMA_PERIPH_INCREASE_DISABLE,DMA_PERIPH_INCREASE_FIX memory0_addr: memory base address memory_inc: DMA_MEMORY_INCREASE_ENABLE,DMA_MEMORY_INCREASE_DISABLE + periph_memory_width: DMA_PERIPH_WIDTH_8BIT,DMA_PERIPH_WIDTH_16BIT,DMA_PERIPH_WIDTH_32BIT + circular_mode: DMA_CIRCULAR_MODE_ENABLE,DMA_CIRCULAR_MODE_DISABLE direction: DMA_PERIPH_TO_MEMORY,DMA_MEMORY_TO_PERIPH,DMA_MEMORY_TO_MEMORY number: the number of remaining data to be transferred by the DMA priority: DMA_PRIORITY_LOW,DMA_PRIORITY_MEDIUM,DMA_PRIORITY_HIGH,DMA_PRIORITY_ULTRA_HIGH - circular_mode: DMA_CIRCULAR_MODE_ENABLE,DMA_CIRCULAR_MODE_DISABLE \param[out] none \retval none */ -void dma_single_data_mode_init(uint32_t dma_periph,dma_channel_enum channelx,dma_single_data_parameter_struct init_struct) +void dma_single_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dma_single_data_parameter_struct* init_struct) { uint32_t ctl; - + /* select single data mode */ DMA_CHFCTL(dma_periph,channelx) &= ~DMA_CHXFCTL_MDMEN; - + /* configure peripheral base address */ - DMA_CHPADDR(dma_periph,channelx) = init_struct.periph_addr; - + DMA_CHPADDR(dma_periph,channelx) = init_struct->periph_addr; + /* configure memory base address */ - DMA_CHM0ADDR(dma_periph,channelx) = init_struct.memory0_addr; - + DMA_CHM0ADDR(dma_periph,channelx) = init_struct->memory0_addr; + /* configure the number of remaining data to be transferred */ - DMA_CHCNT(dma_periph,channelx) = init_struct.number; - + DMA_CHCNT(dma_periph,channelx) = init_struct->number; + /* configure peripheral and memory transfer width,channel priotity,transfer mode */ ctl = DMA_CHCTL(dma_periph,channelx); ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO | DMA_CHXCTL_TM); - ctl |= (init_struct.periph_memory_width | (init_struct.periph_memory_width << 2) | init_struct.priority | init_struct.direction); + ctl |= (init_struct->periph_memory_width | (init_struct->periph_memory_width << 2) | init_struct->priority | init_struct->direction); DMA_CHCTL(dma_periph,channelx) = ctl; /* configure peripheral increasing mode */ - if(DMA_PERIPH_INCREASE_ENABLE == init_struct.periph_inc){ + if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc){ DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PNAGA; - }else if(DMA_PERIPH_INCREASE_DISABLE == init_struct.periph_inc){ + }else if(DMA_PERIPH_INCREASE_DISABLE == init_struct->periph_inc){ DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_PNAGA; }else{ DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PAIF; } /* configure memory increasing mode */ - if(DMA_MEMORY_INCREASE_ENABLE == init_struct.memory_inc){ + if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc){ DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_MNAGA; }else{ DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_MNAGA; } /* configure DMA circular mode */ - if(DMA_CIRCULAR_MODE_ENABLE == init_struct.circular_mode){ + if(DMA_CIRCULAR_MODE_ENABLE == init_struct->circular_mode){ DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_CMEN; }else{ DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_CMEN; @@ -115,60 +185,60 @@ void dma_single_data_mode_init(uint32_t dma_periph,dma_channel_enum channelx,dma \param[in] dma_multi_data_parameter_struct: the data needed to initialize DMA multi data mode periph_addr: peripheral base address periph_width: DMA_PERIPH_WIDTH_8BIT,DMA_PERIPH_WIDTH_16BIT,DMA_PERIPH_WIDTH_32BIT - periph_inc: DMA_PERIPH_INCREASE_ENABLE,DMA_PERIPH_INCREASE_DISABLE,DMA_PERIPH_INCREASE_FIX + periph_inc: DMA_PERIPH_INCREASE_ENABLE,DMA_PERIPH_INCREASE_DISABLE,DMA_PERIPH_INCREASE_FIX memory0_addr: memory0 base address memory_width: DMA_MEMORY_WIDTH_8BIT,DMA_MEMORY_WIDTH_16BIT,DMA_MEMORY_WIDTH_32BIT memory_inc: DMA_MEMORY_INCREASE_ENABLE,DMA_MEMORY_INCREASE_DISABLE - direction: DMA_PERIPH_TO_MEMORY,DMA_MEMORY_TO_PERIPH,DMA_MEMORY_TO_MEMORY - number: the number of remaining data to be transferred by the DMA - priority: DMA_PRIORITY_LOW,DMA_PRIORITY_MEDIUM,DMA_PRIORITY_HIGH,DMA_PRIORITY_ULTRA_HIGH - circular_mode: DMA_CIRCULAR_MODE_ENABLE,DMA_CIRCULAR_MODE_DISABLE memory_burst_width: DMA_MEMORY_BURST_SINGLE,DMA_MEMORY_BURST_4_BEAT,DMA_MEMORY_BURST_8_BEAT,DMA_MEMORY_BURST_16_BEAT periph_burst_width: DMA_PERIPH_BURST_SINGLE,DMA_PERIPH_BURST_4_BEAT,DMA_PERIPH_BURST_8_BEAT,DMA_PERIPH_BURST_16_BEAT critical_value: DMA_FIFO_1_WORD,DMA_FIFO_2_WORD,DMA_FIFO_3_WORD,DMA_FIFO_4_WORD + circular_mode: DMA_CIRCULAR_MODE_ENABLE,DMA_CIRCULAR_MODE_DISABLE + direction: DMA_PERIPH_TO_MEMORY,DMA_MEMORY_TO_PERIPH,DMA_MEMORY_TO_MEMORY + number: the number of remaining data to be transferred by the DMA + priority: DMA_PRIORITY_LOW,DMA_PRIORITY_MEDIUM,DMA_PRIORITY_HIGH,DMA_PRIORITY_ULTRA_HIGH \param[out] none \retval none */ -void dma_multi_data_mode_init(uint32_t dma_periph,dma_channel_enum channelx,dma_multi_data_parameter_struct init_struct) +void dma_multi_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dma_multi_data_parameter_struct* init_struct) { uint32_t ctl; - + /* select multi data mode and configure FIFO critical value */ - DMA_CHFCTL(dma_periph,channelx) |= (DMA_CHXFCTL_MDMEN | init_struct.critical_value); - + DMA_CHFCTL(dma_periph,channelx) |= (DMA_CHXFCTL_MDMEN | init_struct->critical_value); + /* configure peripheral base address */ - DMA_CHPADDR(dma_periph,channelx) = init_struct.periph_addr; - + DMA_CHPADDR(dma_periph,channelx) = init_struct->periph_addr; + /* configure memory base address */ - DMA_CHM0ADDR(dma_periph,channelx) = init_struct.memory0_addr; - + DMA_CHM0ADDR(dma_periph,channelx) = init_struct->memory0_addr; + /* configure the number of remaining data to be transferred */ - DMA_CHCNT(dma_periph,channelx) = init_struct.number; - + DMA_CHCNT(dma_periph,channelx) = init_struct->number; + /* configure peripheral and memory transfer width,channel priotity,transfer mode,peripheral and memory burst transfer width */ ctl = DMA_CHCTL(dma_periph,channelx); ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO | DMA_CHXCTL_TM | DMA_CHXCTL_PBURST | DMA_CHXCTL_MBURST); - ctl |= (init_struct.periph_width | (init_struct.memory_width ) | init_struct.priority | init_struct.direction | init_struct.memory_burst_width | init_struct.periph_burst_width); + ctl |= (init_struct->periph_width | (init_struct->memory_width ) | init_struct->priority | init_struct->direction | init_struct->memory_burst_width | init_struct->periph_burst_width); DMA_CHCTL(dma_periph,channelx) = ctl; /* configure peripheral increasing mode */ - if(DMA_PERIPH_INCREASE_ENABLE == init_struct.periph_inc){ + if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc){ DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PNAGA; - }else if(DMA_PERIPH_INCREASE_DISABLE == init_struct.periph_inc){ + }else if(DMA_PERIPH_INCREASE_DISABLE == init_struct->periph_inc){ DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_PNAGA; }else{ DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PAIF; } /* configure memory increasing mode */ - if(DMA_MEMORY_INCREASE_ENABLE == init_struct.memory_inc){ + if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc){ DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_MNAGA; }else{ DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_MNAGA; } /* configure DMA circular mode */ - if(DMA_CIRCULAR_MODE_ENABLE == init_struct.circular_mode){ + if(DMA_CIRCULAR_MODE_ENABLE == init_struct->circular_mode){ DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_CMEN; }else{ DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_CMEN; @@ -176,21 +246,464 @@ void dma_multi_data_mode_init(uint32_t dma_periph,dma_channel_enum channelx,dma_ } /*! - \brief get DMA flag is set or not + \brief set DMA peripheral base address + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set peripheral base address + \arg DMA_CHx(x=0..7) + \param[in] address: peripheral base address + \param[out] none + \retval none +*/ +void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address) +{ + DMA_CHPADDR(dma_periph,channelx) = address; +} + +/*! + \brief set DMA Memory0 base address + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set Memory base address + \arg DMA_CHx(x=0..7) + \param[in] memory_flag: DMA_MEMORY_x(x=0,1) + \param[in] address: Memory base address + \param[out] none + \retval none +*/ +void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t memory_flag, uint32_t address) +{ + if(memory_flag){ + DMA_CHM1ADDR(dma_periph,channelx) = address; + }else{ + DMA_CHM0ADDR(dma_periph,channelx) = address; + } +} + +/*! + \brief set the number of remaining data to be transferred by the DMA + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set number + \arg DMA_CHx(x=0..7) + \param[in] number: the number of remaining data to be transferred by the DMA + \param[out] none + \retval none +*/ +void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number) +{ + DMA_CHCNT(dma_periph,channelx) = number; +} + +/*! + \brief get the number of remaining data to be transferred by the DMA + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set number + \arg DMA_CHx(x=0..7) + \param[out] none + \retval uint32_t: the number of remaining data to be transferred by the DMA +*/ +uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx) +{ + return (uint32_t)DMA_CHCNT(dma_periph,channelx); +} + +/*! + \brief configure priority level of DMA channel + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] priority: priority Level of this channel + only one parameter can be selected which is shown as below: + \arg DMA_PRIORITY_LOW: low priority + \arg DMA_PRIORITY_MEDIUM: medium priority + \arg DMA_PRIORITY_HIGH: high priority + \arg DMA_PRIORITY_ULTRA_HIGH: ultra high priority + \param[out] none + \retval none +*/ +void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority) +{ + uint32_t ctl; + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(dma_periph,channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_PRIO; + ctl |= priority; + DMA_CHCTL(dma_periph,channelx) = ctl; +} + +/*! + \brief configure transfer burst beats of memory + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] mbeat: transfer burst beats + \arg DMA_MEMORY_BURST_SINGLE: memory transfer single burst + \arg DMA_MEMORY_BURST_4_BEAT: memory transfer 4-beat burst + \arg DMA_MEMORY_BURST_8_BEAT: memory transfer 8-beat burst + \arg DMA_MEMORY_BURST_16_BEAT: memory transfer 16-beat burst + \param[out] none + \retval none +*/ +void dma_memory_burst_beats_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t mbeat) +{ + uint32_t ctl; + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(dma_periph,channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_MBURST; + ctl |= mbeat; + DMA_CHCTL(dma_periph,channelx) = ctl; +} + +/*! + \brief configure transfer burst beats of peripheral + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] pbeat: transfer burst beats + only one parameter can be selected which is shown as below: + \arg DMA_PERIPH_BURST_SINGLE: peripheral transfer single burst + \arg DMA_PERIPH_BURST_4_BEAT: peripheral transfer 4-beat burst + \arg DMA_PERIPH_BURST_8_BEAT: peripheral transfer 8-beat burst + \arg DMA_PERIPH_BURST_16_BEAT: peripheral transfer 16-beat burst + \param[out] none + \retval none +*/ +void dma_periph_burst_beats_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t pbeat) +{ + uint32_t ctl; + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(dma_periph,channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_PBURST; + ctl |= pbeat; + DMA_CHCTL(dma_periph,channelx) = ctl; +} + +/*! + \brief configure transfer data size of memory + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] msize: transfer data size of memory + only one parameter can be selected which is shown as below: + \arg DMA_MEMORY_WIDTH_8BIT: transfer data size of memory is 8-bit + \arg DMA_MEMORY_WIDTH_16BIT: transfer data size of memory is 16-bit + \arg DMA_MEMORY_WIDTH_32BIT: transfer data size of memory is 32-bit + \param[out] none + \retval none +*/ +void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t msize) +{ + uint32_t ctl; + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(dma_periph,channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_MWIDTH; + ctl |= msize; + DMA_CHCTL(dma_periph,channelx) = ctl; +} + +/*! + \brief configure transfer data size of peripheral + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] msize: transfer data size of peripheral + only one parameter can be selected which is shown as below: + \arg DMA_PERIPHERAL_WIDTH_8BIT: transfer data size of peripheral is 8-bit + \arg DMA_PERIPHERAL_WIDTH_16BIT: transfer data size of peripheral is 16-bit + \arg DMA_PERIPHERAL_WIDTH_32BIT: transfer data size of peripheral is 32-bit + \param[out] none + \retval none +*/ +void dma_periph_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t psize) +{ + uint32_t ctl; + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(dma_periph,channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_PWIDTH; + ctl |= psize; + DMA_CHCTL(dma_periph,channelx) = ctl; +} + +/*! + \brief configure memory address generation generation_algorithm + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] generation_algorithm: the address generation algorithm + only one parameter can be selected which is shown as below: + \arg DMA_MEMORY_INCREASE_ENABLE: next address of memory is increasing address mode + \arg DMA_MEMORY_INCREASE_DISABLE: next address of memory is fixed address mode + \param[out] none + \retval none +*/ +void dma_memory_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm) +{ + if(DMA_MEMORY_INCREASE_ENABLE == generation_algorithm){ + DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_MNAGA; + }else{ + DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_MNAGA; + } +} + +/*! + \brief configure peripheral address generation_algorithm + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] generation_algorithm: the address generation algorithm + only one parameter can be selected which is shown as below: + \arg DMA_PERIPH_INCREASE_ENABLE: next address of peripheral is increasing address mode + \arg DMA_PERIPH_INCREASE_DISABLE: next address of peripheral is fixed address mode + \arg DMA_PERIPH_INCREASE_FIX: increasing steps of peripheral address is fixed + \param[out] none + \retval none +*/ +void dma_peripheral_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm) +{ + if(DMA_PERIPH_INCREASE_ENABLE == generation_algorithm){ + DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PNAGA; + }else if(DMA_PERIPH_INCREASE_DISABLE == generation_algorithm){ + DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_PNAGA; + }else{ + DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PNAGA; + DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PAIF; + } +} + +/*! + \brief enable DMA circulation mode + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[out] none + \retval none +*/ +void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx) +{ + DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_CMEN; +} + +/*! + \brief disable DMA circulation mode + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[out] none + \retval none +*/ +void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx) +{ + DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_CMEN; +} + +/*! + \brief enable DMA channel + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[out] none + \retval none +*/ +void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx) +{ + DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_CHEN; +} + +/*! + \brief disable DMA channel + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[out] none + \retval none +*/ +void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx) +{ + DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_CHEN; +} + +/*! + \brief configure the direction of data transfer on the channel + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] direction: specify the direction of data transfer + only one parameter can be selected which is shown as below: + \arg DMA_PERIPH_TO_MEMORY: read from peripheral and write to memory + \arg DMA_MEMORY_TO_PERIPH: read from memory and write to peripheral + \arg DMA_MEMORY_TO_MEMORY: read from memory and write to memory + \param[out] none + \retval none +*/ +void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t direction) +{ + uint32_t ctl; + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(dma_periph,channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_TM; + ctl |= direction; + + DMA_CHCTL(dma_periph,channelx) = ctl; +} + +/*! + \brief DMA switch buffer mode config + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] memory1_addr: memory1 base address + \param[in] memory_select: DMA_MEMORY_0 or DMA_MEMORY_1 + \param[out] none + \retval none +*/ +void dma_switch_buffer_mode_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t memory1_addr, uint32_t memory_select) +{ + /* configure memory1 base address */ + DMA_CHM1ADDR(dma_periph,channelx) = memory1_addr; + + if(DMA_MEMORY_0 == memory_select){ + DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_MBS; + }else{ + DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_MBS; + } +} + +/*! + \brief DMA using memory get + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[out] none + \retval the using memory +*/ +uint32_t dma_using_memory_get(uint32_t dma_periph, dma_channel_enum channelx) +{ + if((DMA_CHCTL(dma_periph,channelx)) & DMA_CHXCTL_MBS){ + return DMA_MEMORY_1; + }else{ + return DMA_MEMORY_0; + } +} + +/*! + \brief DMA channel peripheral select + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] sub_periph: specify DMA channel peripheral + \arg DMA_SUBPERIx(x=0..7) + \param[out] none + \retval none +*/ +void dma_channel_subperipheral_select(uint32_t dma_periph, dma_channel_enum channelx, dma_subperipheral_enum sub_periph) +{ + uint32_t ctl; + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(dma_periph,channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_PERIEN; + ctl |= ((uint32_t)sub_periph << CHXCTL_PERIEN_OFFSET); + + DMA_CHCTL(dma_periph,channelx) = ctl; +} + +/*! + \brief DMA flow controller configure + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] controller: specify DMA flow controler + only one parameter can be selected which is shown as below: + \arg DMA_FLOW_CONTROLLER_DMA: DMA is the flow controller + \arg DMA_FLOW_CONTROLLER_PERI: peripheral is the flow controller + \param[out] none + \retval none +*/ +void dma_flow_controller_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t controller) +{ + if(DMA_FLOW_CONTROLLER_DMA == controller){ + DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_TFCS; + }else{ + DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_TFCS; + } +} + +/*! + \brief DMA switch buffer mode enable + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void dma_switch_buffer_mode_enable(uint32_t dma_periph, dma_channel_enum channelx, ControlStatus newvalue) +{ + if(ENABLE == newvalue){ + /* switch buffer mode enable */ + DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_SBMEN; + }else{ + /* switch buffer mode disable */ + DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_SBMEN; + } +} + +/*! + \brief DMA FIFO status get + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[out] none + \retval the using memory +*/ +uint32_t dma_fifo_status_get(uint32_t dma_periph, dma_channel_enum channelx) +{ + return (DMA_CHFCTL(dma_periph,channelx) & DMA_CHXFCTL_FCNT); +} + +/*! + \brief get DMA flag is set or not \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel to get flag \arg DMA_CHx(x=0..7) \param[in] flag: specify get which flag - \arg DMA_INTF_FEEIF: FIFO error and exception flag - \arg DMA_INTF_SDEIF: single data mode exception flag - \arg DMA_INTF_TAEIF: transfer access error flag - \arg DMA_INTF_HTFIF: half transfer finish flag - \arg DMA_INTF_FTFIF: full transger finish flag + only one parameter can be selected which is shown as below: + \arg DMA_FLAG_FEE: FIFO error and exception flag + \arg DMA_FLAG_SDE: single data mode exception flag + \arg DMA_FLAG_TAE: transfer access error flag + \arg DMA_FLAG_HTF: half transfer finish flag + \arg DMA_FLAG_FTF: full transger finish flag \param[out] none \retval FlagStatus: SET or RESET */ -FlagStatus dma_flag_get(uint32_t dma_periph,dma_channel_enum channelx,uint32_t flag) +FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) { if(channelx < DMA_CH4){ if(DMA_INTF0(dma_periph) & DMA_FLAG_ADD(flag,channelx)){ @@ -215,15 +728,16 @@ FlagStatus dma_flag_get(uint32_t dma_periph,dma_channel_enum channelx,uint32_t f \param[in] channelx: specify which DMA channel to get flag \arg DMA_CHx(x=0..7) \param[in] flag: specify get which flag - \arg DMA_INTF_FEEIF: FIFO error and exception flag - \arg DMA_INTF_SDEIF: single data mode exception flag - \arg DMA_INTF_TAEIF: transfer access error flag - \arg DMA_INTF_HTFIF: half transfer finish flag - \arg DMA_INTF_FTFIF: full transger finish flag + only one parameter can be selected which is shown as below: + \arg DMA_FLAG_FEE: FIFO error and exception flag + \arg DMA_FLAG_SDE: single data mode exception flag + \arg DMA_FLAG_TAE: transfer access error flag + \arg DMA_FLAG_HTF: half transfer finish flag + \arg DMA_FLAG_FTF: full transger finish flag \param[out] none \retval none */ -void dma_flag_clear(uint32_t dma_periph,dma_channel_enum channelx,uint32_t flag) +void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) { if(channelx < DMA_CH4){ DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(flag,channelx); @@ -234,21 +748,22 @@ void dma_flag_clear(uint32_t dma_periph,dma_channel_enum channelx,uint32_t flag) } /*! - \brief get DMA interrupt flag is set or not + \brief get DMA interrupt flag is set or not \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel to get interrupt flag \arg DMA_CHx(x=0..7) \param[in] interrupt: specify get which flag - \arg DMA_INTF_FEEIF: FIFO error and exception flag - \arg DMA_INTF_SDEIF: single data mode exception flag - \arg DMA_INTF_TAEIF: transfer access error flag - \arg DMA_INTF_HTFIF: half transfer finish flag - \arg DMA_INTF_FTFIF: full transger finish flag + only one parameter can be selected which is shown as below: + \arg DMA_INT_FLAG_FEE: FIFO error and exception flag + \arg DMA_INT_FLAG_SDE: single data mode exception flag + \arg DMA_INT_FLAG_TAE: transfer access error flag + \arg DMA_INT_FLAG_HTF: half transfer finish flag + \arg DMA_INT_FLAG_FTF: full transger finish flag \param[out] none \retval FlagStatus: SET or RESET */ -FlagStatus dma_interrupt_flag_get(uint32_t dma_periph,dma_channel_enum channelx,uint32_t interrupt) +FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt) { uint32_t interrupt_enable = 0U,interrupt_flag = 0U; dma_channel_enum channel_flag_offset = channelx; @@ -304,7 +819,7 @@ FlagStatus dma_interrupt_flag_get(uint32_t dma_periph,dma_channel_enum channelx, break; } } - + if(interrupt_flag && interrupt_enable){ return SET; }else{ @@ -319,15 +834,16 @@ FlagStatus dma_interrupt_flag_get(uint32_t dma_periph,dma_channel_enum channelx, \param[in] channelx: specify which DMA channel to clear interrupt flag \arg DMA_CHx(x=0..7) \param[in] interrupt: specify get which flag - \arg DMA_INTC_FEEIFC: clear FIFO error and exception flag - \arg DMA_INTC_SDEIFC: clear single data mode exception flag - \arg DMA_INTC_TAEIFC: clear transfer access error flag - \arg DMA_INTC_HTFIFC: clear half transfer finish flag - \arg DMA_INTC_FTFIFC: clear full transger finish flag + only one parameter can be selected which is shown as below: + \arg DMA_INT_FLAG_FEE: FIFO error and exception flag + \arg DMA_INT_FLAG_SDE: single data mode exception flag + \arg DMA_INT_FLAG_TAE: transfer access error flag + \arg DMA_INT_FLAG_HTF: half transfer finish flag + \arg DMA_INT_FLAG_FTF: full transger finish flag \param[out] none \retval none */ -void dma_interrupt_flag_clear(uint32_t dma_periph,dma_channel_enum channelx,uint32_t interrupt) +void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt) { if(channelx < DMA_CH4){ DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(interrupt,channelx); @@ -341,9 +857,10 @@ void dma_interrupt_flag_clear(uint32_t dma_periph,dma_channel_enum channelx,uint \brief enable DMA interrupt \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel \arg DMA_CHx(x=0..7) \param[in] source: specify which interrupt to enbale + one or more parameters can be selected which are shown as below: \arg DMA_CHXCTL_SDEIE: single data mode exception interrupt enable \arg DMA_CHXCTL_TAEIE: tranfer access error interrupt enable \arg DMA_CHXCTL_HTFIE: half transfer finish interrupt enable @@ -352,7 +869,7 @@ void dma_interrupt_flag_clear(uint32_t dma_periph,dma_channel_enum channelx,uint \param[out] none \retval none */ -void dma_interrupt_enable(uint32_t dma_periph,dma_channel_enum channelx,uint32_t source) +void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) { if(DMA_CHXFCTL_FEEIE != source){ DMA_CHCTL(dma_periph,channelx) |= source; @@ -365,9 +882,10 @@ void dma_interrupt_enable(uint32_t dma_periph,dma_channel_enum channelx,uint32_t \brief disable DMA interrupt \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel \arg DMA_CHx(x=0..7) \param[in] source: specify which interrupt to disbale + one or more parameters can be selected which are shown as below: \arg DMA_CHXCTL_SDEIE: single data mode exception interrupt enable \arg DMA_CHXCTL_TAEIE: tranfer access error interrupt enable \arg DMA_CHXCTL_HTFIE: half transfer finish interrupt enable @@ -376,7 +894,7 @@ void dma_interrupt_enable(uint32_t dma_periph,dma_channel_enum channelx,uint32_t \param[out] none \retval none */ -void dma_interrupt_disable(uint32_t dma_periph,dma_channel_enum channelx,uint32_t source) +void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) { if(DMA_CHXFCTL_FEEIE != source){ DMA_CHCTL(dma_periph,channelx) &= ~source; @@ -385,436 +903,3 @@ void dma_interrupt_disable(uint32_t dma_periph,dma_channel_enum channelx,uint32_ } } -/*! - \brief set DMA peripheral base address - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to set peripheral base address - \arg DMA_CHx(x=0..7) - \param[in] address: peripheral base address - \param[out] none - \retval none -*/ -void dma_periph_address_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t address) -{ - DMA_CHPADDR(dma_periph,channelx) = address; -} - -/*! - \brief set DMA Memory0 base address - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to set Memory base address - \arg DMA_CHx(x=0..7) - \param[in] memory_flag: DMA_MEMORY_x(x=0,1) - \param[in] address: Memory base address - \param[out] none - \retval none -*/ -void dma_memory_address_config(uint32_t dma_periph,dma_channel_enum channelx,uint8_t memory_flag,uint32_t address) -{ - if(memory_flag){ - DMA_CHM1ADDR(dma_periph,channelx) = address; - }else{ - DMA_CHM0ADDR(dma_periph,channelx) = address; - } -} - -/*! - \brief set the number of remaining data to be transferred by the DMA - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to set number - \arg DMA_CHx(x=0..7) - \param[in] number: the number of remaining data to be transferred by the DMA - \param[out] none - \retval none -*/ -void dma_transfer_number_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t number) -{ - DMA_CHCNT(dma_periph,channelx) = number; -} - -/*! - \brief get the number of remaining data to be transferred by the DMA - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to set number - \arg DMA_CHx(x=0..7) - \param[out] none - \retval uint32_t: the number of remaining data to be transferred by the DMA -*/ -uint32_t dma_transfer_number_get(uint32_t dma_periph,dma_channel_enum channelx) -{ - return (uint32_t)DMA_CHCNT(dma_periph,channelx); -} - -/*! - \brief configure priority level of DMA channel - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[in] priority: priority Level of this channel - \arg DMA_PRIORITY_LOW: low priority - \arg DMA_PRIORITY_MEDIUM: medium priority - \arg DMA_PRIORITY_HIGH: high priority - \arg DMA_PRIORITY_ULTRA_HIGH: ultra high priority - \param[out] none - \retval none -*/ -void dma_priority_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t priority) -{ - uint32_t ctl; - /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(dma_periph,channelx); - /* assign regiser */ - ctl &= ~DMA_CHXCTL_PRIO; - ctl |= priority; - DMA_CHCTL(dma_periph,channelx) = ctl; -} - -/*! - \brief configure transfer burst beats of memory - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[in] mbeat: transfer burst beats - \arg DMA_MEMORY_BURST_SINGLE: memory transfer single burst - \arg DMA_MEMORY_BURST_4_BEAT: memory transfer 4-beat burst - \arg DMA_MEMORY_BURST_8_BEAT: memory transfer 8-beat burst - \arg DMA_MEMORY_BURST_16_BEAT: memory transfer 16-beat burst - \param[out] none - \retval none -*/ -void dma_memory_burst_beats_config (uint32_t dma_periph,dma_channel_enum channelx,uint32_t mbeat) -{ - uint32_t ctl; - /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(dma_periph,channelx); - /* assign regiser */ - ctl &= ~DMA_CHXCTL_MBURST; - ctl |= mbeat; - DMA_CHCTL(dma_periph,channelx) = ctl; -} - -/*! - \brief configure transfer burst beats of peripheral - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[in] pbeat: transfer burst beats - \arg DMA_PERIPH_BURST_SINGLE: peripheral transfer single burst - \arg DMA_PERIPH_BURST_4_BEAT: peripheral transfer 4-beat burst - \arg DMA_PERIPH_BURST_8_BEAT: peripheral transfer 8-beat burst - \arg DMA_PERIPH_BURST_16_BEAT: peripheral transfer 16-beat burst - \param[out] none - \retval none -*/ -void dma_periph_burst_beats_config (uint32_t dma_periph,dma_channel_enum channelx,uint32_t pbeat) -{ - uint32_t ctl; - /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(dma_periph,channelx); - /* assign regiser */ - ctl &= ~DMA_CHXCTL_PBURST; - ctl |= pbeat; - DMA_CHCTL(dma_periph,channelx) = ctl; -} - -/*! - \brief configure transfer data size of memory - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[in] msize: transfer data size of memory - \arg DMA_MEMORY_WIDTH_8BIT: transfer data size of memory is 8-bit - \arg DMA_MEMORY_WIDTH_16BIT: transfer data size of memory is 16-bit - \arg DMA_MEMORY_WIDTH_32BIT: transfer data size of memory is 32-bit - \param[out] none - \retval none -*/ -void dma_memory_width_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t msize) -{ - uint32_t ctl; - /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(dma_periph,channelx); - /* assign regiser */ - ctl &= ~DMA_CHXCTL_MWIDTH; - ctl |= msize; - DMA_CHCTL(dma_periph,channelx) = ctl; -} - -/*! - \brief configure transfer data size of peripheral - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[in] msize: transfer data size of peripheral - \arg DMA_PERIPHERAL_WIDTH_8BIT: transfer data size of peripheral is 8-bit - \arg DMA_PERIPHERAL_WIDTH_16BIT: transfer data size of peripheral is 16-bit - \arg DMA_PERIPHERAL_WIDTH_32BIT: transfer data size of peripheral is 32-bit - \param[out] none - \retval none -*/ -void dma_periph_width_config (uint32_t dma_periph,dma_channel_enum channelx,uint32_t psize) -{ - uint32_t ctl; - /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(dma_periph,channelx); - /* assign regiser */ - ctl &= ~DMA_CHXCTL_PWIDTH; - ctl |= psize; - DMA_CHCTL(dma_periph,channelx) = ctl; -} - -/*! - \brief configure memory address generation generation_algorithm - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[in] generation_algorithm: the address generation algorithm - \arg DMA_MEMORY_INCREASE_ENABLE: next address of memory is increasing address mode - \arg DMA_MEMORY_INCREASE_DISABLE: next address of memory is fixed address mode - \param[out] none - \retval none -*/ -void dma_memory_address_generation_config(uint32_t dma_periph,dma_channel_enum channelx,uint8_t generation_algorithm) -{ - if(DMA_MEMORY_INCREASE_ENABLE == generation_algorithm){ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_MNAGA; - }else{ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_MNAGA; - } -} - -/*! - \brief configure peripheral address generation generation_algorithm - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[in] generation_algorithm: the address generation algorithm - \arg DMA_PERIPH_INCREASE_ENABLE: next address of peripheral is increasing address mode - \arg DMA_PERIPH_INCREASE_DISABLE: next address of peripheral is fixed address mode - \arg DMA_PERIPH_INCREASE_FIX: increasing steps of peripheral address is fixed - \param[out] none - \retval none -*/ -void dma_peripheral_address_generation_config(uint32_t dma_periph,dma_channel_enum channelx,uint8_t generation_algorithm) -{ - if(DMA_PERIPH_INCREASE_ENABLE == generation_algorithm){ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PNAGA; - }else if(DMA_PERIPH_INCREASE_DISABLE == generation_algorithm){ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_PNAGA; - }else{ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PNAGA; - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PAIF; - } -} - -/*! - \brief enable DMA circulation mode - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[out] none - \retval none -*/ -void dma_circulation_enable(uint32_t dma_periph,dma_channel_enum channelx) -{ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_CMEN; -} - -/*! - \brief disable DMA circulation mode - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[out] none - \retval none -*/ -void dma_circulation_disable(uint32_t dma_periph,dma_channel_enum channelx) -{ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_CMEN; -} - -/*! - \brief configure the direction of data transfer on the channel - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[in] direction: specify the direction of data transfer - \arg DMA_PERIPH_TO_MEMORY: read from peripheral and write to memory - \arg DMA_MEMORY_TO_PERIPH: read from memory and write to peripheral - \arg DMA_MEMORY_TO_MEMORY: read from memory and write to memory - \param[out] none - \retval none -*/ -void dma_transfer_direction_config(uint32_t dma_periph,dma_channel_enum channelx,uint8_t direction) -{ - uint32_t ctl; - /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(dma_periph,channelx); - /* assign regiser */ - ctl &= ~DMA_CHXCTL_TM; - ctl |= direction; - - DMA_CHCTL(dma_periph,channelx) = ctl; -} - -/*! - \brief enable DMA channel - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[out] none - \retval none -*/ -void dma_channel_enable(uint32_t dma_periph,dma_channel_enum channelx) -{ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_CHEN; -} - -/*! - \brief disable DMA channel - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[out] none - \retval none -*/ -void dma_channel_disable(uint32_t dma_periph,dma_channel_enum channelx) -{ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_CHEN; -} - -/*! - \brief DMA channel peripheral select - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[in] sub_periph: specify DMA channel peripheral - \arg DMA_SUBPERIx(x=0..7) - \param[out] none - \retval none -*/ -void dma_channel_subperipheral_select(uint32_t dma_periph,dma_channel_enum channelx,dma_subperipheral_enum sub_periph) -{ - uint32_t ctl; - /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(dma_periph,channelx); - /* assign regiser */ - ctl &= ~DMA_CHXCTL_PERIEN; - ctl |= ((uint32_t)sub_periph << CHXCTL_PERIEN_OFFSET); - - DMA_CHCTL(dma_periph,channelx) = ctl; -} - -/*! - \brief DMA switch buffer mode config - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[in] memory1_addr: memory1 base address - \param[in] memory_select: DMA_MEMORY_0 or DMA_MEMORY_1 - \param[out] none - \retval none -*/ -void dma_switch_buffer_mode_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t memory1_addr,uint32_t memory_select) -{ - /* configure memory1 base address */ - DMA_CHM1ADDR(dma_periph,channelx) = memory1_addr; - - if(DMA_MEMORY_0 == memory_select){ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_MBS; - }else{ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_MBS; - } -} - -/*! - \brief DMA switch buffer mode enable - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void dma_switch_buffer_mode_enable(uint32_t dma_periph,dma_channel_enum channelx,ControlStatus newvalue) -{ - if(ENABLE == newvalue){ - /* switch buffer mode enable */ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_SBMEN; - }else{ - /* switch buffer mode disable */ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_SBMEN; - } -} - -/*! - \brief DMA using memory get - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[out] none - \retval the using memory -*/ -uint32_t dma_using_memory_get(uint32_t dma_periph,dma_channel_enum channelx) -{ - if((DMA_CHCTL(dma_periph,channelx)) & DMA_CHXCTL_MBS){ - return DMA_MEMORY_1; - }else{ - return DMA_MEMORY_0; - } -} - -/*! - \brief DMA flow controller configure - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[in] controller: specify DMA flow controler - \arg DMA_FLOW_CONTROLLER_DMA: DMA is the flow controller - \arg DMA_FLOW_CONTROLLER_PERI: peripheral is the flow controller - \param[out] none - \retval none -*/ -void dma_flow_controller_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t controller) -{ - if(DMA_FLOW_CONTROLLER_DMA == controller){ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_TFCS; - }else{ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_TFCS; - } -} - -/*! - \brief DMA FIFO status get - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[out] none - \retval the using memory -*/ -uint32_t dma_fifo_status_get(uint32_t dma_periph,dma_channel_enum channelx) -{ - return (DMA_CHFCTL(dma_periph,channelx) & DMA_CHXFCTL_FCNT); -} diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_enet.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_enet.c index 55ed8a9145..456e476fd8 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_enet.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_enet.c @@ -1,24 +1,49 @@ /*! - \file gd32f4xx_enet.c - \brief ENET driver + \file gd32f4xx_enet.c + \brief ENET driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.1, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_enet.h" #if defined (__CC_ARM) /*!< ARM compiler */ -__align(4) +__align(4) enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM]; /*!< ENET RxDMA descriptor */ -__align(4) +__align(4) enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM]; /*!< ENET TxDMA descriptor */ -__align(4) +__align(4) uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE]; /*!< ENET receive buffer */ -__align(4) +__align(4) uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE]; /*!< ENET transmit buffer */ #elif defined ( __ICCARM__ ) /*!< IAR compiler */ @@ -31,15 +56,11 @@ uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE]; /*!< ENET receive bu #pragma data_alignment=4 uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE]; /*!< ENET transmit buffer */ -#elif defined ( __GNUC__ ) -__attribute__((aligned(4))) -enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM]; /*!< ENET RxDMA descriptor */ -__attribute__((aligned(4))) -enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM]; /*!< ENET TxDMA descriptor */ -__attribute__((aligned(4))) -uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE]; /*!< ENET receive buffer */ -__attribute__((aligned(4))) -uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE]; /*!< ENET transmit buffer */ +#elif defined (__GNUC__) /* GNU Compiler */ +enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM] __attribute__ ((aligned (4))); /*!< ENET RxDMA descriptor */ +enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM] __attribute__ ((aligned (4))); /*!< ENET TxDMA descriptor */ +uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE] __attribute__ ((aligned (4))); /*!< ENET receive buffer */ +uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE] __attribute__ ((aligned (4))); /*!< ENET transmit buffer */ #endif /* __CC_ARM */ @@ -53,19 +74,31 @@ enet_descriptors_struct *dma_current_ptp_rxdesc = NULL; /* init structure parameters for ENET initialization */ static enet_initpara_struct enet_initpara ={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; - +static uint32_t enet_unknow_err = 0U; /* array of register offset for debug information get */ static const uint16_t enet_reg_tab[] = { 0x0000, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018, 0x001C, 0x0028, 0x002C, 0x0034, 0x0038, 0x003C, 0x0040, 0x0044, 0x0048, 0x004C, 0x0050, 0x0054, 0x0058, 0x005C, 0x1080, - -0x0100, 0x0104, 0x0108, 0x010C, 0x0110, 0x014C, 0x0150, 0x0168, 0x0194, 0x0198, 0x01C4, - -0x0700, 0x0704,0x0708, 0x070C, 0x0710, 0x0714, 0x0718, 0x071C, 0x0720, 0x0728, 0x072C, - + +0x0100, 0x0104, 0x0108, 0x010C, 0x0110, 0x014C, 0x0150, 0x0168, 0x0194, 0x0198, 0x01C4, + +0x0700, 0x0704,0x0708, 0x070C, 0x0710, 0x0714, 0x0718, 0x071C, 0x0720, 0x0728, 0x072C, + 0x1000, 0x1004, 0x1008, 0x100C, 0x1010, 0x1014, 0x1018, 0x101C, 0x1020, 0x1024, 0x1048, 0x104C, 0x1050, 0x1054}; +/* initialize ENET peripheral with generally concerned parameters, call it by enet_init() */ +static void enet_default_init(void); +#ifdef USE_DELAY +/* user can provide more timing precise _ENET_DELAY_ function */ +#define _ENET_DELAY_ delay_ms +#else +/* insert a delay time */ +static void enet_delay(uint32_t ncount); +/* default _ENET_DELAY_ function with less precise timing */ +#define _ENET_DELAY_ enet_delay +#endif + /*! \brief deinitialize the ENET, and reset structure parameters for ENET initialization @@ -82,16 +115,16 @@ void enet_deinit(void) /*! \brief configure the parameters which are usually less cared for initialization - note -- this function must be called before enet_init(), otherwise + note -- this function must be called before enet_init(), otherwise configuration will be no effect - \param[in] option: different function option, which is related to several parameters, - only one parameter can be selected which is shown as below, refer to enet_option_enum + \param[in] option: different function option, which is related to several parameters, refer to enet_option_enum + only one parameter can be selected which is shown as below \arg FORWARD_OPTION: choose to configure the frame forward related parameters \arg DMABUS_OPTION: choose to configure the DMA bus mode related parameters \arg DMA_MAXBURST_OPTION: choose to configure the DMA max burst related parameters \arg DMA_ARBITRATION_OPTION: choose to configure the DMA arbitration related parameters \arg STORE_OPTION: choose to configure the store forward mode related parameters - \arg DMA_OPTION: choose to configure the DMA descriptor related parameters + \arg DMA_OPTION: choose to configure the DMA descriptor related parameters \arg VLAN_OPTION: choose to configure vlan related parameters \arg FLOWCTL_OPTION: choose to configure flow control related parameters \arg HASHH_OPTION: choose to configure hash high @@ -100,8 +133,8 @@ void enet_deinit(void) \arg HALFDUPLEX_OPTION: choose to configure halfduplex mode related parameters \arg TIMER_OPTION: choose to configure time counter related parameters \arg INTERFRAMEGAP_OPTION: choose to configure the inter frame gap related parameters - \param[in] para: the related parameters according to the option - all the related parameters should be configured which are shown as below + \param[in] para: the related parameters according to the option + all the related parameters should be configured which are shown as below FORWARD_OPTION related parameters: - ENET_AUTO_PADCRC_DROP_ENABLE/ ENET_AUTO_PADCRC_DROP_DISABLE ; - ENET_TYPEFRAME_CRC_DROP_ENABLE/ ENET_TYPEFRAME_CRC_DROP_DISABLE ; @@ -110,7 +143,7 @@ void enet_deinit(void) DMABUS_OPTION related parameters: - ENET_ADDRESS_ALIGN_ENABLE/ ENET_ADDRESS_ALIGN_DISABLE ; - ENET_FIXED_BURST_ENABLE/ ENET_FIXED_BURST_DISABLE ; - - ENET_MIXED_BURST_ENABLE/ ENET_MIXED_BURST_DISABLE ; + - ENET_MIXED_BURST_ENABLE/ ENET_MIXED_BURST_DISABLE ; DMA_MAXBURST_OPTION related parameters: - ENET_RXDP_1BEAT/ ENET_RXDP_2BEAT/ ENET_RXDP_4BEAT/ ENET_RXDP_8BEAT/ ENET_RXDP_16BEAT/ ENET_RXDP_32BEAT/ @@ -146,7 +179,7 @@ void enet_deinit(void) FLOWCTL_OPTION related parameters: - MAC_FCTL_PTM(regval) ; - ENET_ZERO_QUANTA_PAUSE_ENABLE/ ENET_ZERO_QUANTA_PAUSE_DISABLE ; - - ENET_PAUSETIME_MINUS4/ ENET_PAUSETIME_MINUS28/ + - ENET_PAUSETIME_MINUS4/ ENET_PAUSETIME_MINUS28/ ENET_PAUSETIME_MINUS144/ENET_PAUSETIME_MINUS256 ; - ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT/ ENET_UNIQUE_PAUSEDETECT ; - ENET_RX_FLOWCONTROL_ENABLE/ ENET_RX_FLOWCONTROL_DISABLE ; @@ -180,7 +213,7 @@ void enet_deinit(void) ENET_INTERFRAMEGAP_80BIT/ ENET_INTERFRAMEGAP_72BIT/ ENET_INTERFRAMEGAP_64BIT/ ENET_INTERFRAMEGAP_56BIT/ ENET_INTERFRAMEGAP_48BIT/ ENET_INTERFRAMEGAP_40BIT . - \param[out] none + \param[out] none \retval none */ void enet_initpara_config(enet_option_enum option, uint32_t para) @@ -214,11 +247,11 @@ void enet_initpara_config(enet_option_enum option, uint32_t para) case DMA_OPTION: /* choose to configure dma_function, and save the configuration parameters */ enet_initpara.option_enable |= (uint32_t)DMA_OPTION; - + #ifndef SELECT_DESCRIPTORS_ENHANCED_MODE para &= ~ENET_ENHANCED_DESCRIPTOR; -#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ - +#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ + enet_initpara.dma_function = para; break; case VLAN_OPTION: @@ -254,7 +287,7 @@ void enet_initpara_config(enet_option_enum option, uint32_t para) case TIMER_OPTION: /* choose to configure timer_config, and save the configuration parameters */ enet_initpara.option_enable |= (uint32_t)TIMER_OPTION; - enet_initpara.timer_config = para; + enet_initpara.timer_config = para; break; case INTERFRAMEGAP_OPTION: /* choose to configure interframegap, and save the configuration parameters */ @@ -262,34 +295,34 @@ void enet_initpara_config(enet_option_enum option, uint32_t para) enet_initpara.interframegap = para; break; default: - break; - } -} + break; + } +} /*! - \brief initialize ENET peripheral with generally concerned parameters and the less cared + \brief initialize ENET peripheral with generally concerned parameters and the less cared parameters - \param[in] mediamode: PHY mode and mac loopback configurations, only one parameter can be selected - which is shown as below, refer to enet_mediamode_enum + \param[in] mediamode: PHY mode and mac loopback configurations, refer to enet_mediamode_enum + only one parameter can be selected which is shown as below \arg ENET_AUTO_NEGOTIATION: PHY auto negotiation \arg ENET_100M_FULLDUPLEX: 100Mbit/s, full-duplex \arg ENET_100M_HALFDUPLEX: 100Mbit/s, half-duplex \arg ENET_10M_FULLDUPLEX: 10Mbit/s, full-duplex \arg ENET_10M_HALFDUPLEX: 10Mbit/s, half-duplex \arg ENET_LOOPBACKMODE: MAC in loopback mode at the MII - \param[in] checksum: IP frame checksum offload function, only one parameter can be selected - which is shown as below, refer to enet_mediamode_enum + \param[in] checksum: IP frame checksum offload function, refer to enet_mediamode_enum + only one parameter can be selected which is shown as below \arg ENET_NO_AUTOCHECKSUM: disable IP frame checksum function \arg ENET_AUTOCHECKSUM_DROP_FAILFRAMES: enable IP frame checksum function \arg ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES: enable IP frame checksum function, and the received frame with only payload error but no other errors will not be dropped - \param[in] recept: frame filter function, only one parameter can be selected - which is shown as below, refer to enet_frmrecept_enum + \param[in] recept: frame filter function, refer to enet_frmrecept_enum + only one parameter can be selected which is shown as below \arg ENET_PROMISCUOUS_MODE: promiscuous mode enabled \arg ENET_RECEIVEALL: all received frame are forwarded to application \arg ENET_BROADCAST_FRAMES_PASS: the address filters pass all received broadcast frames \arg ENET_BROADCAST_FRAMES_DROP: the address filters filter all incoming broadcast frames - \param[out] none + \param[out] none \retval ErrStatus: ERROR or SUCCESS */ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum, enet_frmrecept_enum recept) @@ -297,19 +330,19 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum uint32_t reg_value=0U, reg_temp = 0U, temp = 0U; uint32_t media_temp = 0U; uint32_t timeout = 0U; - uint16_t phy_value = 0U; + uint16_t phy_value = 0U; ErrStatus phy_state= ERROR, enet_state = ERROR; - + /* PHY interface configuration, configure SMI clock and reset PHY chip */ if(ERROR == enet_phy_config()){ _ENET_DELAY_(PHY_RESETDELAY); if(ERROR == enet_phy_config()){ return enet_state; - } + } } /* initialize ENET peripheral with generally concerned parameters */ enet_default_init(); - + /* 1st, configure mediamode */ media_temp = (uint32_t)mediamode; /* if is PHY auto negotiation */ @@ -317,7 +350,7 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum /* wait for PHY_LINKED_STATUS bit be set */ do{ enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value); - phy_value &= PHY_LINKED_STATUS; + phy_value &= PHY_LINKED_STATUS; timeout++; }while((RESET == phy_value) && (timeout < PHY_READ_TO)); /* return ERROR due to timeout */ @@ -326,7 +359,7 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum } /* reset timeout counter */ timeout = 0U; - + /* enable auto-negotiation */ phy_value = PHY_AUTONEGOTIATION; phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value); @@ -334,22 +367,22 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum /* return ERROR due to write timeout */ return enet_state; } - + /* wait for the PHY_AUTONEGO_COMPLETE bit be set */ do{ enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value); phy_value &= PHY_AUTONEGO_COMPLETE; timeout++; - }while((RESET == phy_value) && (timeout < (uint32_t)PHY_READ_TO)); + }while((RESET == phy_value) && (timeout < (uint32_t)PHY_READ_TO)); /* return ERROR due to timeout */ if(PHY_READ_TO == timeout){ return enet_state; } /* reset timeout counter */ timeout = 0U; - + /* read the result of the auto-negotiation */ - enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_SR, &phy_value); + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_SR, &phy_value); /* configure the duplex mode of MAC following the auto-negotiation result */ if((uint16_t)RESET != (phy_value & PHY_DUPLEX_STATUS)){ media_temp = ENET_MODE_FULLDUPLEX; @@ -361,7 +394,7 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum media_temp |= ENET_SPEEDMODE_10M; }else{ media_temp |= ENET_SPEEDMODE_100M; - } + } }else{ phy_value = (uint16_t)((media_temp & ENET_MAC_CFG_DPM) >> 3); phy_value |= (uint16_t)((media_temp & ENET_MAC_CFG_SPD) >> 1); @@ -371,7 +404,7 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum return enet_state; } /* PHY configuration need some time */ - _ENET_DELAY_(PHY_CONFIGDELAY); + _ENET_DELAY_(PHY_CONFIGDELAY); } /* after configuring the PHY, use mediamode to configure registers */ reg_value = ENET_MAC_CFG; @@ -379,27 +412,27 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum reg_value &= (~(ENET_MAC_CFG_SPD |ENET_MAC_CFG_DPM |ENET_MAC_CFG_LBM)); reg_value |= media_temp; ENET_MAC_CFG = reg_value; - - + + /* 2st, configure checksum */ if(RESET != ((uint32_t)checksum & ENET_CHECKSUMOFFLOAD_ENABLE)){ ENET_MAC_CFG |= ENET_CHECKSUMOFFLOAD_ENABLE; - + reg_value = ENET_DMA_CTL; /* configure ENET_DMA_CTL register */ reg_value &= ~ENET_DMA_CTL_DTCERFD; reg_value |= ((uint32_t)checksum & ENET_DMA_CTL_DTCERFD); ENET_DMA_CTL = reg_value; } - + /* 3rd, configure recept */ ENET_MAC_FRMF |= (uint32_t)recept; - + /* 4th, configure different function options */ /* configure forward_frame related registers */ if(RESET != (enet_initpara.option_enable & (uint32_t)FORWARD_OPTION)){ reg_temp = enet_initpara.forward_frame; - + reg_value = ENET_MAC_CFG; temp = reg_temp; /* configure ENET_MAC_CFG register */ @@ -407,7 +440,7 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum temp &= (ENET_MAC_CFG_TFCD | ENET_MAC_CFG_APCD); reg_value |= temp; ENET_MAC_CFG = reg_value; - + reg_value = ENET_DMA_CTL; temp = reg_temp; /* configure ENET_DMA_CTL register */ @@ -420,7 +453,7 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum /* configure dmabus_mode related registers */ if(RESET != (enet_initpara.option_enable & (uint32_t)DMABUS_OPTION)){ temp = enet_initpara.dmabus_mode; - + reg_value = ENET_DMA_BCTL; /* configure ENET_DMA_BCTL register */ reg_value &= ~(ENET_DMA_BCTL_AA | ENET_DMA_BCTL_FB \ @@ -430,31 +463,31 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum } /* configure dma_maxburst related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_MAXBURST_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_MAXBURST_OPTION)){ temp = enet_initpara.dma_maxburst; - + reg_value = ENET_DMA_BCTL; /* configure ENET_DMA_BCTL register */ - reg_value &= ~(ENET_DMA_BCTL_RXDP| ENET_DMA_BCTL_PGBL | ENET_DMA_BCTL_UIP); + reg_value &= ~(ENET_DMA_BCTL_RXDP| ENET_DMA_BCTL_PGBL | ENET_DMA_BCTL_UIP); reg_value |= temp; ENET_DMA_BCTL = reg_value; } /* configure dma_arbitration related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_ARBITRATION_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_ARBITRATION_OPTION)){ temp = enet_initpara.dma_arbitration; - + reg_value = ENET_DMA_BCTL; /* configure ENET_DMA_BCTL register */ reg_value &= ~(ENET_DMA_BCTL_RTPR | ENET_DMA_BCTL_DAB); reg_value |= temp; ENET_DMA_BCTL = reg_value; } - + /* configure store_forward_mode related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)STORE_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)STORE_OPTION)){ temp = enet_initpara.store_forward_mode; - + reg_value = ENET_DMA_CTL; /* configure ENET_DMA_CTL register */ reg_value &= ~(ENET_DMA_CTL_RSFD | ENET_DMA_CTL_TSFD| ENET_DMA_CTL_RTHC| ENET_DMA_CTL_TTHC); @@ -463,9 +496,9 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum } /* configure dma_function related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_OPTION)){ reg_temp = enet_initpara.dma_function; - + reg_value = ENET_DMA_CTL; temp = reg_temp; /* configure ENET_DMA_CTL register */ @@ -473,7 +506,7 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum temp &= (ENET_DMA_CTL_DAFRF | ENET_DMA_CTL_OSF); reg_value |= temp; ENET_DMA_CTL = reg_value; - + reg_value = ENET_DMA_BCTL; temp = reg_temp; /* configure ENET_DMA_BCTL register */ @@ -484,9 +517,9 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum } /* configure vlan_config related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)VLAN_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)VLAN_OPTION)){ reg_temp = enet_initpara.vlan_config; - + reg_value = ENET_MAC_VLT; /* configure ENET_MAC_VLT register */ reg_value &= ~(ENET_MAC_VLT_VLTI | ENET_MAC_VLT_VLTC); @@ -495,9 +528,9 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum } /* configure flow_control related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)FLOWCTL_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)FLOWCTL_OPTION)){ reg_temp = enet_initpara.flow_control; - + reg_value = ENET_MAC_FCTL; temp = reg_temp; /* configure ENET_MAC_FCTL register */ @@ -507,7 +540,7 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum | ENET_MAC_FCTL_UPFDT |ENET_MAC_FCTL_RFCEN |ENET_MAC_FCTL_TFCEN); reg_value |= temp; ENET_MAC_FCTL = reg_value; - + reg_value = ENET_MAC_FCTH; temp = reg_temp; /* configure ENET_MAC_FCTH register */ @@ -515,22 +548,22 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum temp &= ((ENET_MAC_FCTH_RFA | ENET_MAC_FCTH_RFD )<<8); reg_value |= (temp >> 8); ENET_MAC_FCTH = reg_value; - } - + } + /* configure hashtable_high related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)HASHH_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)HASHH_OPTION)){ ENET_MAC_HLH = enet_initpara.hashtable_high; - } + } /* configure hashtable_low related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)HASHL_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)HASHL_OPTION)){ ENET_MAC_HLL = enet_initpara.hashtable_low; - } + } /* configure framesfilter_mode related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)FILTER_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)FILTER_OPTION)){ reg_temp = enet_initpara.framesfilter_mode; - + reg_value = ENET_MAC_FRMF; /* configure ENET_MAC_FRMF register */ reg_value &= ~(ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT | ENET_MAC_FRMF_DAIFLT \ @@ -538,41 +571,41 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum | ENET_MAC_FRMF_HUF | ENET_MAC_FRMF_PCFRM); reg_value |= reg_temp; ENET_MAC_FRMF = reg_value; - } + } /* configure halfduplex_param related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)HALFDUPLEX_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)HALFDUPLEX_OPTION)){ reg_temp = enet_initpara.halfduplex_param; - + reg_value = ENET_MAC_CFG; /* configure ENET_MAC_CFG register */ reg_value &= ~(ENET_MAC_CFG_CSD | ENET_MAC_CFG_ROD | ENET_MAC_CFG_RTD \ | ENET_MAC_CFG_BOL | ENET_MAC_CFG_DFC); reg_value |= reg_temp; ENET_MAC_CFG = reg_value; - } + } /* configure timer_config related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)TIMER_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)TIMER_OPTION)){ reg_temp = enet_initpara.timer_config; - + reg_value = ENET_MAC_CFG; /* configure ENET_MAC_CFG register */ reg_value &= ~(ENET_MAC_CFG_WDD | ENET_MAC_CFG_JBD); reg_value |= reg_temp; ENET_MAC_CFG = reg_value; - } - + } + /* configure interframegap related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)INTERFRAMEGAP_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)INTERFRAMEGAP_OPTION)){ reg_temp = enet_initpara.interframegap; - + reg_value = ENET_MAC_CFG; /* configure ENET_MAC_CFG register */ reg_value &= ~ENET_MAC_CFG_IGBS; reg_value |= reg_temp; ENET_MAC_CFG = reg_value; - } + } enet_state = SUCCESS; return enet_state; @@ -589,21 +622,21 @@ ErrStatus enet_software_reset(void) uint32_t timeout = 0U; ErrStatus enet_state = ERROR; uint32_t dma_flag; - + /* reset all core internal registers located in CLK_TX and CLK_RX */ ENET_DMA_BCTL |= ENET_DMA_BCTL_SWR; - + /* wait for reset operation complete */ do{ dma_flag = (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR); timeout++; }while((RESET != dma_flag) && (ENET_DELAY_TO != timeout)); - /* reset operation complete */ + /* reset operation complete */ if(RESET == (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR)){ enet_state = SUCCESS; } - + return enet_state; } @@ -617,15 +650,15 @@ uint32_t enet_rxframe_size_get(void) { uint32_t size = 0U; uint32_t status; - + /* get rdes0 information of current RxDMA descriptor */ status = dma_current_rxdesc->status; - + /* if the desciptor is owned by DMA */ if((uint32_t)RESET != (status & ENET_RDES0_DAV)){ return 0U; } - + /* if has any error, or the frame uses two or more descriptors */ if((((uint32_t)RESET) != (status & ENET_RDES0_ERRS)) || (((uint32_t)RESET) == (status & ENET_RDES0_LDES)) || @@ -633,7 +666,7 @@ uint32_t enet_rxframe_size_get(void) /* drop current receive frame */ enet_rxframe_drop(); - return 0U; + return 1U; } #ifdef SELECT_DESCRIPTORS_ENHANCED_MODE /* if is an ethernet-type frame, and IP frame payload error occurred */ @@ -642,18 +675,18 @@ uint32_t enet_rxframe_size_get(void) /* drop current receive frame */ enet_rxframe_drop(); - return 0U; + return 1U; } -#else +#else /* if is an ethernet-type frame, and IP frame payload error occurred */ if((((uint32_t)RESET) != (status & ENET_RDES0_FRMT)) && (((uint32_t)RESET) != (status & ENET_RDES0_PCERR))){ /* drop current receive frame */ enet_rxframe_drop(); - return 0U; - } -#endif + return 1U; + } +#endif /* if CPU owns current descriptor, no error occured, the frame uses only one descriptor */ if((((uint32_t)RESET) == (status & ENET_RDES0_DAV)) && (((uint32_t)RESET) == (status & ENET_RDES0_ERRS)) && @@ -661,22 +694,27 @@ uint32_t enet_rxframe_size_get(void) (((uint32_t)RESET) != (status & ENET_RDES0_FDES))){ /* get the size of the received data including CRC */ size = GET_RDES0_FRML(status); - /* substract the CRC size */ + /* substract the CRC size */ size = size - 4U; - - /* if is a type frame, and CRC is not included in forwarding frame */ + + /* if is a type frame, and CRC is not included in forwarding frame */ if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (status & ENET_RDES0_FRMT))){ size = size + 4U; } + }else{ + enet_unknow_err++; + enet_rxframe_drop(); + + return 1U; } - - /* return packet size */ + + /* return packet size */ return size; } /*! \brief initialize the DMA Tx/Rx descriptors's parameters in chain mode - \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum only one parameter can be selected which is shown as below \arg ENET_DMA_TX: DMA Tx descriptors \arg ENET_DMA_RX: DMA Rx descriptors @@ -688,7 +726,7 @@ void enet_descriptors_chain_init(enet_dmadirection_enum direction) uint32_t num = 0U, count = 0U, maxsize = 0U; uint32_t desc_status = 0U, desc_bufsize = 0U; enet_descriptors_struct *desc, *desc_tab; - uint8_t *buf; + uint8_t *buf; /* if want to initialize DMA Tx descriptors */ if (ENET_DMA_TX == direction){ @@ -697,58 +735,58 @@ void enet_descriptors_chain_init(enet_dmadirection_enum direction) buf = &tx_buff[0][0]; count = ENET_TXBUF_NUM; maxsize = ENET_TXBUF_SIZE; - + /* select chain mode */ desc_status = ENET_TDES0_TCHM; - + /* configure DMA Tx descriptor table address register */ ENET_DMA_TDTADDR = (uint32_t)desc_tab; dma_current_txdesc = desc_tab; - }else{ + }else{ /* if want to initialize DMA Rx descriptors */ /* save a copy of the DMA Rx descriptors */ desc_tab = rxdesc_tab; buf = &rx_buff[0][0]; count = ENET_RXBUF_NUM; maxsize = ENET_RXBUF_SIZE; - + /* enable receiving */ desc_status = ENET_RDES0_DAV; /* select receive chained mode and set buffer1 size */ desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE; - + /* configure DMA Rx descriptor table address register */ ENET_DMA_RDTADDR = (uint32_t)desc_tab; - dma_current_rxdesc = desc_tab; + dma_current_rxdesc = desc_tab; } dma_current_ptp_rxdesc = NULL; dma_current_ptp_txdesc = NULL; - - /* configure each descriptor */ + + /* configure each descriptor */ for(num=0U; num < count; num++){ /* get the pointer to the next descriptor of the descriptor table */ desc = desc_tab + num; /* configure descriptors */ - desc->status = desc_status; + desc->status = desc_status; desc->control_buffer_size = desc_bufsize; desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - + /* if is not the last descriptor */ if(num < (count - 1U)){ /* configure the next descriptor address */ desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U); }else{ - /* when it is the last descriptor, the next descriptor address - equals to first descriptor address in descriptor table */ - desc->buffer2_next_desc_addr = (uint32_t) desc_tab; + /* when it is the last descriptor, the next descriptor address + equals to first descriptor address in descriptor table */ + desc->buffer2_next_desc_addr = (uint32_t) desc_tab; } - } + } } /*! \brief initialize the DMA Tx/Rx descriptors's parameters in ring mode - \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum only one parameter can be selected which is shown as below \arg ENET_DMA_TX: DMA Tx descriptors \arg ENET_DMA_RX: DMA Rx descriptors @@ -761,20 +799,20 @@ void enet_descriptors_ring_init(enet_dmadirection_enum direction) uint32_t desc_status = 0U, desc_bufsize = 0U; enet_descriptors_struct *desc; enet_descriptors_struct *desc_tab; - uint8_t *buf; - + uint8_t *buf; + /* configure descriptor skip length */ ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL; ENET_DMA_BCTL |= DMA_BCTL_DPSL(0); - + /* if want to initialize DMA Tx descriptors */ if (ENET_DMA_TX == direction){ /* save a copy of the DMA Tx descriptors */ desc_tab = txdesc_tab; buf = &tx_buff[0][0]; count = ENET_TXBUF_NUM; - maxsize = ENET_TXBUF_SIZE; - + maxsize = ENET_TXBUF_SIZE; + /* configure DMA Tx descriptor table address register */ ENET_DMA_TDTADDR = (uint32_t)desc_tab; dma_current_txdesc = desc_tab; @@ -784,41 +822,41 @@ void enet_descriptors_ring_init(enet_dmadirection_enum direction) desc_tab = rxdesc_tab; buf = &rx_buff[0][0]; count = ENET_RXBUF_NUM; - maxsize = ENET_RXBUF_SIZE; - + maxsize = ENET_RXBUF_SIZE; + /* enable receiving */ desc_status = ENET_RDES0_DAV; /* set buffer1 size */ desc_bufsize = ENET_RXBUF_SIZE; - + /* configure DMA Rx descriptor table address register */ ENET_DMA_RDTADDR = (uint32_t)desc_tab; - dma_current_rxdesc = desc_tab; + dma_current_rxdesc = desc_tab; } dma_current_ptp_rxdesc = NULL; dma_current_ptp_txdesc = NULL; - - /* configure each descriptor */ + + /* configure each descriptor */ for(num=0U; num < count; num++){ /* get the pointer to the next descriptor of the descriptor table */ desc = desc_tab + num; /* configure descriptors */ - desc->status = desc_status; - desc->control_buffer_size = desc_bufsize; - desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - + desc->status = desc_status; + desc->control_buffer_size = desc_bufsize; + desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); + /* when it is the last descriptor */ if(num == (count - 1U)){ if (ENET_DMA_TX == direction){ - /* configure transmit end of ring mode */ + /* configure transmit end of ring mode */ desc->status |= ENET_TDES0_TERM; }else{ /* configure receive end of ring mode */ desc->control_buffer_size |= ENET_RDES1_RERM; } } - } + } } /*! @@ -831,46 +869,46 @@ void enet_descriptors_ring_init(enet_dmadirection_enum direction) ErrStatus enet_frame_receive(uint8_t *buffer, uint32_t bufsize) { uint32_t offset = 0U, size = 0U; - + /* the descriptor is busy due to own by the DMA */ if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){ - return ERROR; + return ERROR; } - + /* if buffer pointer is null, indicates that users has copied data in application */ if(NULL != buffer){ /* if no error occurs, and the frame uses only one descriptor */ - if((((uint32_t)RESET) == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && - (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && - (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_FDES))){ + if((((uint32_t)RESET) == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && + (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && + (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_FDES))){ /* get the frame length except CRC */ size = GET_RDES0_FRML(dma_current_rxdesc->status); size = size - 4U; - - /* if is a type frame, and CRC is not included in forwarding frame */ + + /* if is a type frame, and CRC is not included in forwarding frame */ if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))){ size = size + 4U; } - + /* to avoid situation that the frame size exceeds the buffer length */ if(size > bufsize){ return ERROR; } - + /* copy data from Rx buffer to application buffer */ for(offset = 0U; offsetbuffer1_addr) + offset)); } - + }else{ /* return ERROR */ return ERROR; } } /* enable reception, descriptor is owned by DMA */ - dma_current_rxdesc->status = ENET_RDES0_DAV; - + dma_current_rxdesc->status = ENET_RDES0_DAV; + /* check Rx buffer unavailable flag status */ if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){ /* clear RBU flag */ @@ -878,22 +916,22 @@ ErrStatus enet_frame_receive(uint8_t *buffer, uint32_t bufsize) /* resume DMA reception by writing to the RPEN register*/ ENET_DMA_RPEN = 0U; } - - /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ + + /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ /* chained mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ - dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr); - }else{ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ + dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr); + }else{ /* ring mode */ if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); - }else{ + dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); + }else{ /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL))); + dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL))); } } - + return SUCCESS; } @@ -909,52 +947,52 @@ ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length) { uint32_t offset = 0U; uint32_t dma_tbu_flag, dma_tu_flag; - + /* the descriptor is busy due to own by the DMA */ if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){ return ERROR; } - + /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ if(length > ENET_MAX_FRAME_SIZE){ return ERROR; - } - + } + /* if buffer pointer is null, indicates that users has handled data in application */ - if(NULL != buffer){ + if(NULL != buffer){ /* copy frame data from application buffer to Tx buffer */ for(offset = 0U; offset < length; offset++){ (*(__IO uint8_t *) (uint32_t)((dma_current_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); } } - + /* set the frame length */ dma_current_txdesc->control_buffer_size = length; - /* set the segment of frame, frame is transmitted in one descriptor */ + /* set the segment of frame, frame is transmitted in one descriptor */ dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; /* enable the DMA transmission */ dma_current_txdesc->status |= ENET_TDES0_DAV; - + /* check Tx buffer unavailable flag status */ - dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); + dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); - + if ((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){ /* clear TBU and TU flag */ ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); /* resume DMA transmission by writing to the TPEN register*/ ENET_DMA_TPEN = 0U; } - - /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table*/ + + /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table*/ /* chained mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){ - dma_current_txdesc = (enet_descriptors_struct*) (dma_current_txdesc->buffer2_next_desc_addr); - }else{ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){ + dma_current_txdesc = (enet_descriptors_struct*) (dma_current_txdesc->buffer2_next_desc_addr); + }else{ /* ring mode */ if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){ /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR); + dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR); }else{ /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ dma_current_txdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL))); @@ -966,7 +1004,7 @@ ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length) /*! \brief configure the transmit IP frame checksum offload calculation and insertion - \param[in] desc: the descriptor pointer which users want to configure + \param[in] desc: the descriptor pointer which users want to configure, refer to enet_descriptors_struct \param[in] checksum: IP frame checksum configuration only one parameter can be selected which is shown as below \arg ENET_CHECKSUM_DISABLE: checksum insertion disabled @@ -1007,18 +1045,18 @@ void enet_disable(void) } /*! - \brief configure MAC address - \param[in] mac_addr: select which MAC address will be set, - only one parameter can be selected which is shown as below + \brief configure MAC address + \param[in] mac_addr: select which MAC address will be set, refer to enet_macaddress_enum + only one parameter can be selected which is shown as below \arg ENET_MAC_ADDRESS0: set MAC address 0 filter \arg ENET_MAC_ADDRESS1: set MAC address 1 filter \arg ENET_MAC_ADDRESS2: set MAC address 2 filter \arg ENET_MAC_ADDRESS3: set MAC address 3 filter \param[in] paddr: the buffer pointer which stores the MAC address - (little-ending store, such as MAC address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa}) + (little-ending store, such as MAC address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa}) \param[out] none \retval none -*/ +*/ void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[]) { REG32(ENET_ADDRH_BASE + (uint32_t)mac_addr) = ENET_SET_MACADDRH(paddr); @@ -1026,17 +1064,17 @@ void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[]) } /*! - \brief get MAC address - \param[in] mac_addr: select which MAC address will be get, + \brief get MAC address + \param[in] mac_addr: select which MAC address will be get, refer to enet_macaddress_enum only one parameter can be selected which is shown as below \arg ENET_MAC_ADDRESS0: get MAC address 0 filter \arg ENET_MAC_ADDRESS1: get MAC address 1 filter \arg ENET_MAC_ADDRESS2: get MAC address 2 filter \arg ENET_MAC_ADDRESS3: get MAC address 3 filter \param[out] paddr: the buffer pointer which is stored the MAC address - (little-ending store, such as mac address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa}) + (little-ending store, such as mac address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa}) \retval none -*/ +*/ void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[]) { paddr[0] = ENET_GET_MACADDR(mac_addr, 0U); @@ -1048,12 +1086,12 @@ void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[]) } /*! - \brief get the ENET MAC/MSC/PTP/DMA status flag + \brief get the ENET MAC/MSC/PTP/DMA status flag \param[in] enet_flag: ENET status flag, refer to enet_flag_enum, only one parameter can be selected which is shown as below - \arg ENET_MAC_FLAG_MPKR: magic packet received flag + \arg ENET_MAC_FLAG_MPKR: magic packet received flag \arg ENET_MAC_FLAG_WUFR: wakeup frame received flag - \arg ENET_MAC_FLAG_FLOWCONTROL: flow control status flag + \arg ENET_MAC_FLAG_FLOWCONTROL: flow control status flag \arg ENET_MAC_FLAG_WUM: WUM status flag \arg ENET_MAC_FLAG_MSC: MSC status flag \arg ENET_MAC_FLAG_MSCR: MSC receive status flag @@ -1101,7 +1139,7 @@ FlagStatus enet_flag_get(enet_flag_enum enet_flag) } /*! - \brief clear the ENET DMA status flag + \brief clear the ENET DMA status flag \param[in] enet_flag: ENET DMA flag clear, refer to enet_flag_clear_enum only one parameter can be selected which is shown as below \arg ENET_DMA_FLAG_TS_CLR: transmit status flag clear @@ -1129,8 +1167,8 @@ void enet_flag_clear(enet_flag_clear_enum enet_flag) } /*! - \brief enable ENET MAC/MSC/DMA interrupt - \param[in] enet_int: ENET interrupt, + \brief enable ENET MAC/MSC/DMA interrupt + \param[in] enet_int: ENET interrupt,, refer to enet_int_enum only one parameter can be selected which is shown as below \arg ENET_MAC_INT_WUMIM: WUM interrupt mask \arg ENET_MAC_INT_TMSTIM: timestamp trigger interrupt mask @@ -1170,8 +1208,8 @@ void enet_interrupt_enable(enet_int_enum enet_int) } /*! - \brief disable ENET MAC/MSC/DMA interrupt - \param[in] enet_int: ENET interrupt, + \brief disable ENET MAC/MSC/DMA interrupt + \param[in] enet_int: ENET interrupt, refer to enet_int_enum only one parameter can be selected which is shown as below \arg ENET_MAC_INT_WUMIM: WUM interrupt mask \arg ENET_MAC_INT_TMSTIM: timestamp trigger interrupt mask @@ -1211,8 +1249,8 @@ void enet_interrupt_disable(enet_int_enum enet_int) } /*! - \brief get ENET MAC/MSC/DMA interrupt flag - \param[in] int_flag: ENET interrupt flag, + \brief get ENET MAC/MSC/DMA interrupt flag + \param[in] int_flag: ENET interrupt flag, refer to enet_int_flag_enum only one parameter can be selected which is shown as below \arg ENET_MAC_INT_FLAG_WUM: WUM status flag \arg ENET_MAC_INT_FLAG_MSC: MSC status flag @@ -1256,8 +1294,8 @@ FlagStatus enet_interrupt_flag_get(enet_int_flag_enum int_flag) } /*! - \brief clear ENET DMA interrupt flag - \param[in] int_flag_clear: clear ENET interrupt flag, + \brief clear ENET DMA interrupt flag + \param[in] int_flag_clear: clear ENET interrupt flag, refer to enet_int_flag_clear_enum only one parameter can be selected which is shown as below \arg ENET_DMA_INT_FLAG_TS_CLR: transmit status flag \arg ENET_DMA_INT_FLAG_TPS_CLR: transmit process stopped status flag @@ -1303,7 +1341,7 @@ void enet_tx_enable(void) \retval none */ void enet_tx_disable(void) -{ +{ ENET_DMA_CTL &= ~ENET_DMA_CTL_STE; enet_txfifo_flush(); ENET_MAC_CFG &= ~ENET_MAC_CFG_TEN; @@ -1334,10 +1372,10 @@ void enet_rx_disable(void) } /*! - \brief put registers value into the application buffer + \brief put registers value into the application buffer \param[in] type: register type which will be get, refer to enet_registers_type_enum, only one parameter can be selected which is shown as below - \arg ALL_MAC_REG: get the registers within the offset scope between ENET_MAC_CFG and ENET_MAC_FCTH + \arg ALL_MAC_REG: get the registers within the offset scope between ENET_MAC_CFG and ENET_MAC_FCTH \arg ALL_MSC_REG: get the registers within the offset scope between ENET_MSC_CTL and ENET_MSC_RGUFCNT \arg ALL_PTP_REG: get the registers within the offset scope between ENET_PTP_TSCTL and ENET_PTP_PPSCTL \arg ALL_DMA_REG: get the registers within the offset scope between ENET_DMA_BCTL and ENET_DMA_CRBADDR @@ -1348,37 +1386,37 @@ void enet_rx_disable(void) void enet_registers_get(enet_registers_type_enum type, uint32_t *preg, uint32_t num) { uint32_t offset = 0U, max = 0U, limit = 0U; - + offset = (uint32_t)type; max = (uint32_t)type + num; limit = sizeof(enet_reg_tab)/sizeof(uint16_t); - + /* prevent element in this array is out of range */ - if(max > limit){ + if(max > limit){ max = limit; } - + for(; offset < max; offset++){ /* get value of the corresponding register */ - *preg = REG32((ENET) + enet_reg_tab[offset]); + *preg = REG32((ENET) + enet_reg_tab[offset]); preg++; } -} +} /*! \brief get the enet debug status from the debug register - \param[in] mac_debug: enet debug status, + \param[in] mac_debug: enet debug status only one parameter can be selected which is shown as below \arg ENET_MAC_RECEIVER_NOT_IDLE: MAC receiver is not in idle state \arg ENET_RX_ASYNCHRONOUS_FIFO_STATE: Rx asynchronous FIFO status - \arg ENET_RXFIFO_NOT_WRITING: RxFIFO is not doing write operation + \arg ENET_RXFIFO_WRITING: RxFIFO is doing write operation \arg ENET_RXFIFO_READ_STATUS: RxFIFO read operation status \arg ENET_RXFIFO_STATE: RxFIFO state \arg ENET_MAC_TRANSMITTER_NOT_IDLE: MAC transmitter is not in idle state \arg ENET_MAC_TRANSMITTER_STATUS: status of MAC transmitter \arg ENET_PAUSE_CONDITION_STATUS: pause condition status \arg ENET_TXFIFO_READ_STATUS: TxFIFO read operation status - \arg ENET_TXFIFO_NOT_WRITING: TxFIFO is not doing write operation + \arg ENET_TXFIFO_WRITING: TxFIFO is doing write operation \arg ENET_TXFIFO_NOT_EMPTY: TxFIFO is not empty \arg ENET_TXFIFO_FULL: TxFIFO is full \param[out] none @@ -1387,7 +1425,7 @@ void enet_registers_get(enet_registers_type_enum type, uint32_t *preg, uint32_t uint32_t enet_debug_status_get(uint32_t mac_debug) { uint32_t temp_state = 0U; - + switch(mac_debug){ case ENET_RX_ASYNCHRONOUS_FIFO_STATE: temp_state = GET_MAC_DBG_RXAFS(ENET_MAC_DBG); @@ -1408,14 +1446,14 @@ uint32_t enet_debug_status_get(uint32_t mac_debug) if(RESET != (ENET_MAC_DBG & mac_debug)){ temp_state = 0x1U; } - break; + break; } return temp_state; } /*! - \brief enable the MAC address filter - \param[in] mac_addr: select which MAC address will be enable + \brief enable the MAC address filter + \param[in] mac_addr: select which MAC address will be enable, refer to enet_macaddress_enum \arg ENET_MAC_ADDRESS1: enable MAC address 1 filter \arg ENET_MAC_ADDRESS2: enable MAC address 2 filter \arg ENET_MAC_ADDRESS3: enable MAC address 3 filter @@ -1428,8 +1466,8 @@ void enet_address_filter_enable(enet_macaddress_enum mac_addr) } /*! - \brief disable the MAC address filter - \param[in] mac_addr: select which MAC address will be disable, + \brief disable the MAC address filter + \param[in] mac_addr: select which MAC address will be disable, refer to enet_macaddress_enum only one parameter can be selected which is shown as below \arg ENET_MAC_ADDRESS1: disable MAC address 1 filter \arg ENET_MAC_ADDRESS2: disable MAC address 2 filter @@ -1443,21 +1481,21 @@ void enet_address_filter_disable(enet_macaddress_enum mac_addr) } /*! - \brief configure the MAC address filter - \param[in] mac_addr: select which MAC address will be configured, + \brief configure the MAC address filter + \param[in] mac_addr: select which MAC address will be configured, refer to enet_macaddress_enum only one parameter can be selected which is shown as below \arg ENET_MAC_ADDRESS1: configure MAC address 1 filter \arg ENET_MAC_ADDRESS2: configure MAC address 2 filter \arg ENET_MAC_ADDRESS3: configure MAC address 3 filter - \param[in] addr_mask: select which MAC address bytes will be mask, + \param[in] addr_mask: select which MAC address bytes will be mask one or more parameters can be selected which are shown as below \arg ENET_ADDRESS_MASK_BYTE0: mask ENET_MAC_ADDR1L[7:0] bits - \arg ENET_ADDRESS_MASK_BYTE1: mask ENET_MAC_ADDR1L[15:8] bits + \arg ENET_ADDRESS_MASK_BYTE1: mask ENET_MAC_ADDR1L[15:8] bits \arg ENET_ADDRESS_MASK_BYTE2: mask ENET_MAC_ADDR1L[23:16] bits \arg ENET_ADDRESS_MASK_BYTE3: mask ENET_MAC_ADDR1L [31:24] bits \arg ENET_ADDRESS_MASK_BYTE4: mask ENET_MAC_ADDR1H [7:0] bits \arg ENET_ADDRESS_MASK_BYTE5: mask ENET_MAC_ADDR1H [15:8] bits - \param[in] filter_type: select which MAC address filter type will be selected, + \param[in] filter_type: select which MAC address filter type will be selected only one parameter can be selected which is shown as below \arg ENET_ADDRESS_FILTER_SA: The MAC address is used to compared with the SA field of the received frame \arg ENET_ADDRESS_FILTER_DA: The MAC address is used to compared with the DA field of the received frame @@ -1467,7 +1505,7 @@ void enet_address_filter_disable(enet_macaddress_enum mac_addr) void enet_address_filter_config(enet_macaddress_enum mac_addr, uint32_t addr_mask, uint32_t filter_type) { uint32_t reg; - + /* get the address filter register value which is to be configured */ reg = REG32(ENET_ADDRH_BASE + mac_addr); @@ -1482,21 +1520,21 @@ void enet_address_filter_config(enet_macaddress_enum mac_addr, uint32_t addr_mas \param[in] none \param[out] none \retval ErrStatus: SUCCESS or ERROR -*/ +*/ ErrStatus enet_phy_config(void) { uint32_t ahbclk; uint32_t reg; uint16_t phy_value; ErrStatus enet_state = ERROR; - + /* clear the previous MDC clock */ reg = ENET_MAC_PHY_CTL; reg &= ~ENET_MAC_PHY_CTL_CLR; /* get the HCLK frequency */ ahbclk = rcu_clock_freq_get(CK_AHB); - + /* configure MDC clock according to HCLK frequency range */ if(ENET_RANGE(ahbclk, 20000000U, 35000000U)){ reg |= ENET_MDC_HCLK_DIV16; @@ -1507,7 +1545,7 @@ ErrStatus enet_phy_config(void) }else if(ENET_RANGE(ahbclk, 100000000U, 150000000U)){ reg |= ENET_MDC_HCLK_DIV62; }else if((ENET_RANGE(ahbclk, 150000000U, 200000000U))||(200000000U == ahbclk)){ - reg |= ENET_MDC_HCLK_DIV102; + reg |= ENET_MDC_HCLK_DIV102; }else{ return enet_state; } @@ -1518,9 +1556,9 @@ ErrStatus enet_phy_config(void) if(ERROR == (enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value))){ return enet_state; } - /* PHY reset need some time */ + /* PHY reset need some time */ _ENET_DELAY_(ENET_DELAY_TO); - + /* check whether PHY reset is complete */ if(ERROR == (enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &phy_value))){ return enet_state; @@ -1530,18 +1568,18 @@ ErrStatus enet_phy_config(void) if(RESET == (phy_value & PHY_RESET)){ enet_state = SUCCESS; } - + return enet_state; } /*! \brief write to / read from a PHY register - \param[in] direction: only one parameter can be selected which is shown as below + \param[in] direction: only one parameter can be selected which is shown as below, refer to enet_phydirection_enum \arg ENET_PHY_WRITE: write data to phy register \arg ENET_PHY_READ: read data from phy register - \param[in] phy_address: 0x0 - 0x1F - \param[in] phy_reg: 0x0 - 0x1F - \param[in] pvalue: the value will be written to the PHY register in ENET_PHY_WRITE direction + \param[in] phy_address: 0x0000 - 0x001F + \param[in] phy_reg: 0x0000 - 0x001F + \param[in] pvalue: the value will be written to the PHY register in ENET_PHY_WRITE direction \param[out] pvalue: the value will be read from the PHY register in ENET_PHY_READ direction \retval ErrStatus: SUCCESS or ERROR */ @@ -1551,16 +1589,16 @@ ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_add uint32_t timeout = 0U; ErrStatus enet_state = ERROR; - /* configure ENET_MAC_PHY_CTL with write/read operation */ + /* configure ENET_MAC_PHY_CTL with write/read operation */ reg = ENET_MAC_PHY_CTL; reg &= ~(ENET_MAC_PHY_CTL_PB | ENET_MAC_PHY_CTL_PW | ENET_MAC_PHY_CTL_PR | ENET_MAC_PHY_CTL_PA); - reg |= (direction | MAC_PHY_CTL_PR(phy_reg) | MAC_PHY_CTL_PA(phy_address) | ENET_MAC_PHY_CTL_PB); + reg |= (direction | MAC_PHY_CTL_PR(phy_reg) | MAC_PHY_CTL_PA(phy_address) | ENET_MAC_PHY_CTL_PB); /* if do the write operation, write value to the register */ if(ENET_PHY_WRITE == direction){ - ENET_MAC_PHY_DATA = *pvalue; + ENET_MAC_PHY_DATA = *pvalue; } - + /* do PHY write/read operation, and wait the operation complete */ ENET_MAC_PHY_CTL = reg; do{ @@ -1569,16 +1607,16 @@ ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_add } while((RESET != phy_flag) && (ENET_DELAY_TO != timeout)); - /* write/read operation complete */ + /* write/read operation complete */ if(RESET == (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB)){ enet_state = SUCCESS; } - /* if do the read operation, get value from the register */ + /* if do the read operation, get value from the register */ if(ENET_PHY_READ == direction){ - *pvalue = (uint16_t)ENET_MAC_PHY_DATA; + *pvalue = (uint16_t)ENET_MAC_PHY_DATA; } - + return enet_state; } @@ -1594,7 +1632,7 @@ ErrStatus enet_phyloopback_enable(void) ErrStatus phy_state = ERROR; /* get the PHY configuration to update it */ - enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); /* enable the PHY loopback mode */ temp_phy |= PHY_LOOPBACK; @@ -1617,7 +1655,7 @@ ErrStatus enet_phyloopback_disable(void) ErrStatus phy_state = ERROR; /* get the PHY configuration to update it */ - enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); /* disable the PHY loopback mode */ temp_phy &= (uint16_t)~PHY_LOOPBACK; @@ -1630,7 +1668,7 @@ ErrStatus enet_phyloopback_disable(void) /*! \brief enable ENET forward feature - \param[in] feature: the feature of ENET forward mode, + \param[in] feature: the feature of ENET forward mode one or more parameters can be selected which are shown as below \arg ENET_AUTO_PADCRC_DROP: the function of the MAC strips the Pad/FCS field on received frames \arg ENET_TYPEFRAME_CRC_DROP: the function that FCS field(last 4 bytes) of frame will be dropped before forwarding @@ -1642,17 +1680,17 @@ ErrStatus enet_phyloopback_disable(void) void enet_forward_feature_enable(uint32_t feature) { uint32_t mask; - + mask = (feature & (~(ENET_FORWARD_ERRFRAMES | ENET_FORWARD_UNDERSZ_GOODFRAMES))); ENET_MAC_CFG |= mask; - + mask = (feature & (~(ENET_AUTO_PADCRC_DROP | ENET_TYPEFRAME_CRC_DROP))); ENET_DMA_CTL |= (mask >> 2); } /*! \brief disable ENET forward feature - \param[in] feature: the feature of ENET forward mode, + \param[in] feature: the feature of ENET forward mode one or more parameters can be selected which are shown as below \arg ENET_AUTO_PADCRC_DROP: the automatic zero-quanta generation function \arg ENET_TYPEFRAME_CRC_DROP: the flow control operation in the MAC @@ -1664,17 +1702,17 @@ void enet_forward_feature_enable(uint32_t feature) void enet_forward_feature_disable(uint32_t feature) { uint32_t mask; - + mask = (feature & (~(ENET_FORWARD_ERRFRAMES | ENET_FORWARD_UNDERSZ_GOODFRAMES))); ENET_MAC_CFG &= ~mask; - + mask = (feature & (~(ENET_AUTO_PADCRC_DROP | ENET_TYPEFRAME_CRC_DROP))); ENET_DMA_CTL &= ~(mask >> 2); } - -/*! + +/*! \brief enable ENET fliter feature - \param[in] feature: the feature of ENET fliter mode, + \param[in] feature: the feature of ENET fliter mode one or more parameters can be selected which are shown as below \arg ENET_SRC_FILTER: filter source address function \arg ENET_SRC_FILTER_INVERSE: inverse source address filtering result function @@ -1693,7 +1731,7 @@ void enet_fliter_feature_enable(uint32_t feature) /*! \brief disable ENET fliter feature - \param[in] feature: the feature of ENET fliter mode, + \param[in] feature: the feature of ENET fliter mode one or more parameters can be selected which are shown as below \arg ENET_SRC_FILTER: filter source address function \arg ENET_SRC_FILTER_INVERSE: inverse source address filtering result function @@ -1717,8 +1755,8 @@ void enet_fliter_feature_disable(uint32_t feature) \param[out] none \retval ErrStatus: ERROR or SUCCESS */ -ErrStatus enet_pauseframe_generate(void) -{ +ErrStatus enet_pauseframe_generate(void) +{ ErrStatus enet_state =ERROR; uint32_t temp = 0U; @@ -1728,16 +1766,16 @@ ErrStatus enet_pauseframe_generate(void) ENET_MAC_FCTL |= ENET_MAC_FCTL_FLCBBKPA; enet_state = SUCCESS; } - return enet_state; + return enet_state; } /*! \brief configure the pause frame detect type - \param[in] detect: pause frame detect type, + \param[in] detect: pause frame detect type only one parameter can be selected which is shown as below \arg ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT: besides the unique multicast address, MAC can also use the MAC0 address to detecting pause frame - \arg ENET_UNIQUE_PAUSEDETECT: only the unique multicast address for pause frame which is specified + \arg ENET_UNIQUE_PAUSEDETECT: only the unique multicast address for pause frame which is specified in IEEE802.3 can be detected \param[out] none \retval none @@ -1751,9 +1789,9 @@ void enet_pauseframe_detect_config(uint32_t detect) /*! \brief configure the pause frame parameters \param[in] pausetime: pause time in transmit pause control frame - \param[in] pause_threshold: the threshold of the pause timer for retransmitting frames automatically, - this value must make sure to be less than configured pause time, only one parameter can be - selected which is shown as below + \param[in] pause_threshold: the threshold of the pause timer for retransmitting frames automatically + this value must make sure to be less than configured pause time + only one parameter can be selected which is shown as below \arg ENET_PAUSETIME_MINUS4: pause time minus 4 slot times \arg ENET_PAUSETIME_MINUS28: pause time minus 28 slot times \arg ENET_PAUSETIME_MINUS144: pause time minus 144 slot times @@ -1769,9 +1807,9 @@ void enet_pauseframe_config(uint32_t pausetime, uint32_t pause_threshold) /*! \brief configure the threshold of the flow control(deactive and active threshold) - \param[in] deactive: the threshold of the deactive flow control, this value - should always be less than active flow control value, only one - parameter can be selected which is shown as below + \param[in] deactive: the threshold of the deactive flow control + this value should always be less than active flow control value + only one parameter can be selected which is shown as below \arg ENET_DEACTIVE_THRESHOLD_256BYTES: threshold level is 256 bytes \arg ENET_DEACTIVE_THRESHOLD_512BYTES: threshold level is 512 bytes \arg ENET_DEACTIVE_THRESHOLD_768BYTES: threshold level is 768 bytes @@ -1779,8 +1817,8 @@ void enet_pauseframe_config(uint32_t pausetime, uint32_t pause_threshold) \arg ENET_DEACTIVE_THRESHOLD_1280BYTES: threshold level is 1280 bytes \arg ENET_DEACTIVE_THRESHOLD_1536BYTES: threshold level is 1536 bytes \arg ENET_DEACTIVE_THRESHOLD_1792BYTES: threshold level is 1792 bytes - \param[in] active: the threshold of the active flow control, only one parameter - can be selected which is shown as below + \param[in] active: the threshold of the active flow control + only one parameter can be selected which is shown as below \arg ENET_ACTIVE_THRESHOLD_256BYTES: threshold level is 256 bytes \arg ENET_ACTIVE_THRESHOLD_512BYTES: threshold level is 512 bytes \arg ENET_ACTIVE_THRESHOLD_768BYTES: threshold level is 768 bytes @@ -1793,7 +1831,7 @@ void enet_pauseframe_config(uint32_t pausetime, uint32_t pause_threshold) */ void enet_flowcontrol_threshold_config(uint32_t deactive, uint32_t active) { - ENET_MAC_FCTH = ((deactive | active) >> 8); + ENET_MAC_FCTH = ((deactive | active) >> 8); } /*! @@ -1838,8 +1876,8 @@ void enet_flowcontrol_feature_disable(uint32_t feature) /*! \brief get the dma transmit/receive process state - \param[in] direction: choose the direction of dma process which users want to check, - refer to enet_dmadirection_enum, only one parameter can be selected which is shown as below + \param[in] direction: choose the direction of dma process which users want to check, refer to enet_dmadirection_enum + only one parameter can be selected which is shown as below \arg ENET_DMA_TX: dma transmit process \arg ENET_DMA_RX: dma receive process \param[out] none @@ -1857,10 +1895,10 @@ uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction) } /*! - \brief poll the DMA transmission/reception enable by writing any value to the + \brief poll the DMA transmission/reception enable by writing any value to the ENET_DMA_TPEN/ENET_DMA_RPEN register, this will make the DMA to resume transmission/reception - \param[in] direction: choose the direction of DMA process which users want to resume, - refer to enet_dmadirection_enum, only one parameter can be selected which is shown as below + \param[in] direction: choose the direction of DMA process which users want to resume, refer to enet_dmadirection_enum + only one parameter can be selected which is shown as below \arg ENET_DMA_TX: DMA transmit process \arg ENET_DMA_RX: DMA receive process \param[out] none @@ -1876,7 +1914,7 @@ void enet_dmaprocess_resume(enet_dmadirection_enum direction) } /*! - \brief check and recover the Rx process + \brief check and recover the Rx process \param[in] none \param[out] none \retval none @@ -1885,11 +1923,11 @@ void enet_rxprocess_check_recovery(void) { uint32_t status; - /* get DAV information of current RxDMA descriptor */ + /* get DAV information of current RxDMA descriptor */ status = dma_current_rxdesc->status; status &= ENET_RDES0_DAV; - - /* if current descriptor is owned by DMA, but the descriptor address mismatches with + + /* if current descriptor is owned by DMA, but the descriptor address mismatches with receive descriptor address pointer updated by RxDMA controller */ if((ENET_DMA_CRDADDR != ((uint32_t)dma_current_rxdesc)) && (ENET_RDES0_DAV == status)){ @@ -1908,25 +1946,25 @@ ErrStatus enet_txfifo_flush(void) uint32_t flush_state; uint32_t timeout = 0U; ErrStatus enet_state = ERROR; - + /* set the FTF bit for flushing transmit FIFO */ - ENET_DMA_CTL |= ENET_DMA_CTL_FTF; + ENET_DMA_CTL |= ENET_DMA_CTL_FTF; /* wait until the flush operation completes */ do{ - flush_state = ENET_DMA_CTL & ENET_DMA_CTL_FTF; + flush_state = ENET_DMA_CTL & ENET_DMA_CTL_FTF; timeout++; }while((RESET != flush_state) && (timeout < ENET_DELAY_TO)); /* return ERROR due to timeout */ if(RESET == flush_state){ enet_state = SUCCESS; } - + return enet_state; } /*! \brief get the transmit/receive address of current descriptor, or current buffer, or descriptor table - \param[in] addr_get: choose the address which users want to get, refer to enet_desc_reg_enum, + \param[in] addr_get: choose the address which users want to get, refer to enet_desc_reg_enum only one parameter can be selected which is shown as below \arg ENET_RX_DESC_TABLE: the start address of the receive descriptor table \arg ENET_RX_CURRENT_DESC: the start descriptor address of the current receive descriptor read by @@ -1936,7 +1974,7 @@ ErrStatus enet_txfifo_flush(void) \arg ENET_TX_CURRENT_DESC: the start descriptor address of the current transmit descriptor read by the TxDMA controller \arg ENET_TX_CURRENT_BUFFER: the current transmit buffer address being read by the TxDMA controller - \param[out] none + \param[out] none \retval address value */ uint32_t enet_current_desc_address_get(enet_desc_reg_enum addr_get) @@ -1950,7 +1988,7 @@ uint32_t enet_current_desc_address_get(enet_desc_reg_enum addr_get) /*! \brief get the Tx or Rx descriptor information \param[in] desc: the descriptor pointer which users want to get information - \param[in] info_get: the descriptor information type which is selected, + \param[in] info_get: the descriptor information type which is selected, refer to enet_descstate_enum only one parameter can be selected which is shown as below \arg RXDESC_BUFFER_1_SIZE: receive buffer 1 size \arg RXDESC_BUFFER_2_SIZE: receive buffer 2 size @@ -1971,25 +2009,30 @@ uint32_t enet_desc_information_get(enet_descriptors_struct *desc, enet_descstate break; case RXDESC_BUFFER_2_SIZE: reval = GET_RDES1_RB2S(desc->control_buffer_size); - break; - case RXDESC_FRAME_LENGTH: + break; + case RXDESC_FRAME_LENGTH: reval = GET_RDES0_FRML(desc->status); - reval = reval - 4U; - - /* if is a type frame, and CRC is not included in forwarding frame */ - if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (desc->status & ENET_RDES0_FRMT))){ - reval = reval + 4U; - } + if(reval > 4U){ + reval = reval - 4U; + + /* if is a type frame, and CRC is not included in forwarding frame */ + if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (desc->status & ENET_RDES0_FRMT))){ + reval = reval + 4U; + } + }else{ + reval = 0U; + } + break; - case RXDESC_BUFFER_1_ADDR: - reval = desc->buffer1_addr; + case RXDESC_BUFFER_1_ADDR: + reval = desc->buffer1_addr; break; - case TXDESC_BUFFER_1_ADDR: - reval = desc->buffer1_addr; + case TXDESC_BUFFER_1_ADDR: + reval = desc->buffer1_addr; break; - case TXDESC_COLLISION_COUNT: + case TXDESC_COLLISION_COUNT: reval = GET_TDES0_COCNT(desc->status); - break; + break; default: break; } @@ -2006,7 +2049,7 @@ uint32_t enet_desc_information_get(enet_descriptors_struct *desc, enet_descstate void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop) { uint32_t temp_counter = 0U; - + temp_counter = ENET_DMA_MFBOCNT; *rxfifo_drop = GET_DMA_MFBOCNT_MSFA(temp_counter); *rxdma_drop = GET_DMA_MFBOCNT_MSFC(temp_counter); @@ -2015,9 +2058,9 @@ void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop) /*! \brief get the bit flag of ENET DMA descriptor \param[in] desc: the descriptor pointer which users want to get flag - \param[in] desc_flag: the bit flag of ENET DMA descriptor, + \param[in] desc_flag: the bit flag of ENET DMA descriptor only one parameter can be selected which is shown as below - \arg ENET_TDES0_DB: deferred + \arg ENET_TDES0_DB: deferred \arg ENET_TDES0_UFE: underflow error \arg ENET_TDES0_EXD: excessive deferral \arg ENET_TDES0_VFRM: VLAN frame @@ -2030,18 +2073,18 @@ void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop) \arg ENET_TDES0_JT: jabber timeout \arg ENET_TDES0_ES: error summary \arg ENET_TDES0_IPHE: IP header error - \arg ENET_TDES0_TTMSS: transmit timestamp status + \arg ENET_TDES0_TTMSS: transmit timestamp status \arg ENET_TDES0_TCHM: the second address chained mode \arg ENET_TDES0_TERM: transmit end of ring mode \arg ENET_TDES0_TTSEN: transmit timestamp function enable - \arg ENET_TDES0_DPAD: disable adding pad + \arg ENET_TDES0_DPAD: disable adding pad \arg ENET_TDES0_DCRC: disable CRC \arg ENET_TDES0_FSG: first segment \arg ENET_TDES0_LSG: last segment \arg ENET_TDES0_INTC: interrupt on completion \arg ENET_TDES0_DAV: DAV bit - - \arg ENET_RDES0_PCERR: payload checksum error + + \arg ENET_RDES0_PCERR: payload checksum error \arg ENET_RDES0_EXSV: extended status valid \arg ENET_RDES0_CERR: CRC error \arg ENET_RDES0_DBERR: dribble bit error @@ -2054,11 +2097,11 @@ void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop) \arg ENET_RDES0_LDES: last descriptor \arg ENET_RDES0_FDES: first descriptor \arg ENET_RDES0_VTAG: VLAN tag - \arg ENET_RDES0_OERR: overflow error + \arg ENET_RDES0_OERR: overflow error \arg ENET_RDES0_LERR: length error \arg ENET_RDES0_SAFF: SA filter fail \arg ENET_RDES0_DERR: descriptor error - \arg ENET_RDES0_ERRS: error summary + \arg ENET_RDES0_ERRS: error summary \arg ENET_RDES0_DAFF: destination address filter fail \arg ENET_RDES0_DAV: descriptor available \param[out] none @@ -2067,7 +2110,7 @@ void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop) FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag) { FlagStatus enet_flag = RESET; - + if ((uint32_t)RESET != (desc->status & desc_flag)){ enet_flag = SET; } @@ -2078,20 +2121,20 @@ FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag) /*! \brief set the bit flag of ENET DMA descriptor \param[in] desc: the descriptor pointer which users want to set flag - \param[in] desc_flag: the bit flag of ENET DMA descriptor, + \param[in] desc_flag: the bit flag of ENET DMA descriptor only one parameter can be selected which is shown as below \arg ENET_TDES0_VFRM: VLAN frame \arg ENET_TDES0_FRMF: frame flushed \arg ENET_TDES0_TCHM: the second address chained mode \arg ENET_TDES0_TERM: transmit end of ring mode \arg ENET_TDES0_TTSEN: transmit timestamp function enable - \arg ENET_TDES0_DPAD: disable adding pad + \arg ENET_TDES0_DPAD: disable adding pad \arg ENET_TDES0_DCRC: disable CRC \arg ENET_TDES0_FSG: first segment \arg ENET_TDES0_LSG: last segment \arg ENET_TDES0_INTC: interrupt on completion \arg ENET_TDES0_DAV: DAV bit - \arg ENET_RDES0_DAV: descriptor available + \arg ENET_RDES0_DAV: descriptor available \param[out] none \retval none */ @@ -2103,20 +2146,20 @@ void enet_desc_flag_set(enet_descriptors_struct *desc, uint32_t desc_flag) /*! \brief clear the bit flag of ENET DMA descriptor \param[in] desc: the descriptor pointer which users want to clear flag - \param[in] desc_flag: the bit flag of ENET DMA descriptor, + \param[in] desc_flag: the bit flag of ENET DMA descriptor only one parameter can be selected which is shown as below \arg ENET_TDES0_VFRM: VLAN frame \arg ENET_TDES0_FRMF: frame flushed \arg ENET_TDES0_TCHM: the second address chained mode \arg ENET_TDES0_TERM: transmit end of ring mode \arg ENET_TDES0_TTSEN: transmit timestamp function enable - \arg ENET_TDES0_DPAD: disable adding pad + \arg ENET_TDES0_DPAD: disable adding pad \arg ENET_TDES0_DCRC: disable CRC \arg ENET_TDES0_FSG: first segment \arg ENET_TDES0_LSG: last segment \arg ENET_TDES0_INTC: interrupt on completion \arg ENET_TDES0_DAV: DAV bit - \arg ENET_RDES0_DAV: descriptor available + \arg ENET_RDES0_DAV: descriptor available \param[out] none \retval none */ @@ -2126,7 +2169,7 @@ void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag) } /*! - \brief when receiving completed, set RS bit in ENET_DMA_STAT register will immediately set + \brief when receiving completed, set RS bit in ENET_DMA_STAT register will immediately set \param[in] desc: the descriptor pointer which users want to configure \param[out] none \retval none @@ -2137,9 +2180,9 @@ void enet_rx_desc_immediate_receive_complete_interrupt(enet_descriptors_struct * } /*! - \brief when receiving completed, set RS bit in ENET_DMA_STAT register will is set after a configurable delay time + \brief when receiving completed, set RS bit in ENET_DMA_STAT register will is set after a configurable delay time \param[in] desc: the descriptor pointer which users want to configure - \param[in] delay_time: delay a time of 256*delay_time HCLK, this value must be between 0 and 0xFF + \param[in] delay_time: delay a time of 256*delay_time HCLK(0x00000000 - 0x000000FF) \param[out] none \retval none */ @@ -2158,10 +2201,10 @@ void enet_rx_desc_delay_receive_complete_interrupt(enet_descriptors_struct *desc void enet_rxframe_drop(void) { /* enable reception, descriptor is owned by DMA */ - dma_current_rxdesc->status = ENET_RDES0_DAV; - + dma_current_rxdesc->status = ENET_RDES0_DAV; + /* chained mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ if(NULL != dma_current_ptp_rxdesc){ dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->buffer2_next_desc_addr); /* if it is the last ptp descriptor */ @@ -2175,9 +2218,9 @@ void enet_rxframe_drop(void) }else{ dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr); } - + }else{ - /* ring mode */ + /* ring mode */ if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ /* if is the last descriptor in table, the next descriptor is the table header */ dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); @@ -2196,9 +2239,9 @@ void enet_rxframe_drop(void) /*! \brief enable DMA feature - \param[in] feature: the feature of DMA mode, + \param[in] feature: the feature of DMA mode one or more parameters can be selected which are shown as below - \arg ENET_FLUSH_RXFRAME: RxDMA flushes frames function + \arg ENET_NO_FLUSH_RXFRAME: RxDMA does not flushes frames function \arg ENET_SECONDFRAME_OPT: TxDMA controller operate on second frame function \param[out] none \retval none @@ -2210,9 +2253,9 @@ void enet_dma_feature_enable(uint32_t feature) /*! \brief disable DMA feature - \param[in] feature: the feature of DMA mode, + \param[in] feature: the feature of DMA mode one or more parameters can be selected which are shown as below - \arg ENET_FLUSH_RXFRAME: RxDMA flushes frames function + \arg ENET_NO_FLUSH_RXFRAME: RxDMA does not flushes frames function \arg ENET_SECONDFRAME_OPT: TxDMA controller operate on second frame function \param[out] none \retval none @@ -2226,7 +2269,7 @@ void enet_dma_feature_disable(uint32_t feature) /*! \brief get the bit of extended status flag in ENET DMA descriptor \param[in] desc: the descriptor pointer which users want to get the extended status flag - \param[in] desc_status: the extended status want to get, + \param[in] desc_status: the extended status want to get only one parameter can be selected which is shown as below \arg ENET_RDES4_IPPLDT: IP frame payload type \arg ENET_RDES4_IPHERR: IP frame header error @@ -2243,7 +2286,7 @@ void enet_dma_feature_disable(uint32_t feature) uint32_t enet_rx_desc_enhanced_status_get(enet_descriptors_struct *desc, uint32_t desc_status) { uint32_t reval = 0xFFFFFFFFU; - + switch (desc_status){ case ENET_RDES4_IPPLDT: reval = GET_RDES4_IPPLDT(desc->extended_status); @@ -2256,9 +2299,9 @@ uint32_t enet_rx_desc_enhanced_status_get(enet_descriptors_struct *desc, uint32_ reval = 1U; }else{ reval = 0U; - } + } } - + return reval; } @@ -2275,7 +2318,7 @@ void enet_desc_select_enhanced_mode(void) /*! \brief initialize the DMA Tx/Rx descriptors's parameters in enhanced chain mode with ptp function - \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum only one parameter can be selected which is shown as below \arg ENET_DMA_TX: DMA Tx descriptors \arg ENET_DMA_RX: DMA Rx descriptors @@ -2288,18 +2331,18 @@ void enet_ptp_enhanced_descriptors_chain_init(enet_dmadirection_enum direction) uint32_t desc_status = 0U, desc_bufsize = 0U; enet_descriptors_struct *desc, *desc_tab; uint8_t *buf; - + /* if want to initialize DMA Tx descriptors */ if (ENET_DMA_TX == direction){ /* save a copy of the DMA Tx descriptors */ desc_tab = txdesc_tab; buf = &tx_buff[0][0]; count = ENET_TXBUF_NUM; - maxsize = ENET_TXBUF_SIZE; - + maxsize = ENET_TXBUF_SIZE; + /* select chain mode, and enable transmit timestamp function */ desc_status = ENET_TDES0_TCHM | ENET_TDES0_TTSEN; - + /* configure DMA Tx descriptor table address register */ ENET_DMA_TDTADDR = (uint32_t)desc_tab; dma_current_txdesc = desc_tab; @@ -2309,43 +2352,43 @@ void enet_ptp_enhanced_descriptors_chain_init(enet_dmadirection_enum direction) desc_tab = rxdesc_tab; buf = &rx_buff[0][0]; count = ENET_RXBUF_NUM; - maxsize = ENET_RXBUF_SIZE; - + maxsize = ENET_RXBUF_SIZE; + /* enable receiving */ desc_status = ENET_RDES0_DAV; /* select receive chained mode and set buffer1 size */ desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE; - + /* configure DMA Rx descriptor table address register */ ENET_DMA_RDTADDR = (uint32_t)desc_tab; - dma_current_rxdesc = desc_tab; + dma_current_rxdesc = desc_tab; } - - /* configuration each descriptor */ + + /* configuration each descriptor */ for(num = 0U; num < count; num++){ /* get the pointer to the next descriptor of the descriptor table */ desc = desc_tab + num; /* configure descriptors */ - desc->status = desc_status; + desc->status = desc_status; desc->control_buffer_size = desc_bufsize; desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - + /* if is not the last descriptor */ if(num < (count - 1U)){ /* configure the next descriptor address */ desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U); }else{ - /* when it is the last descriptor, the next descriptor address - equals to first descriptor address in descriptor table */ - desc->buffer2_next_desc_addr = (uint32_t)desc_tab; + /* when it is the last descriptor, the next descriptor address + equals to first descriptor address in descriptor table */ + desc->buffer2_next_desc_addr = (uint32_t)desc_tab; } - } + } } /*! \brief initialize the DMA Tx/Rx descriptors's parameters in enhanced ring mode with ptp function - \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum only one parameter can be selected which is shown as below \arg ENET_DMA_TX: DMA Tx descriptors \arg ENET_DMA_RX: DMA Rx descriptors @@ -2358,23 +2401,23 @@ void enet_ptp_enhanced_descriptors_ring_init(enet_dmadirection_enum direction) uint32_t desc_status = 0U, desc_bufsize = 0U; enet_descriptors_struct *desc; enet_descriptors_struct *desc_tab; - uint8_t *buf; - + uint8_t *buf; + /* configure descriptor skip length */ ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL; ENET_DMA_BCTL |= DMA_BCTL_DPSL(0); - + /* if want to initialize DMA Tx descriptors */ if (ENET_DMA_TX == direction){ /* save a copy of the DMA Tx descriptors */ desc_tab = txdesc_tab; buf = &tx_buff[0][0]; count = ENET_TXBUF_NUM; - maxsize = ENET_TXBUF_SIZE; + maxsize = ENET_TXBUF_SIZE; /* select ring mode, and enable transmit timestamp function */ desc_status = ENET_TDES0_TTSEN; - + /* configure DMA Tx descriptor table address register */ ENET_DMA_TDTADDR = (uint32_t)desc_tab; dma_current_txdesc = desc_tab; @@ -2384,43 +2427,43 @@ void enet_ptp_enhanced_descriptors_ring_init(enet_dmadirection_enum direction) desc_tab = rxdesc_tab; buf = &rx_buff[0][0]; count = ENET_RXBUF_NUM; - maxsize = ENET_RXBUF_SIZE; - + maxsize = ENET_RXBUF_SIZE; + /* enable receiving */ desc_status = ENET_RDES0_DAV; /* set buffer1 size */ desc_bufsize = ENET_RXBUF_SIZE; - + /* configure DMA Rx descriptor table address register */ ENET_DMA_RDTADDR = (uint32_t)desc_tab; - dma_current_rxdesc = desc_tab; + dma_current_rxdesc = desc_tab; } - - /* configure each descriptor */ + + /* configure each descriptor */ for(num=0U; num < count; num++){ /* get the pointer to the next descriptor of the descriptor table */ desc = desc_tab + num; /* configure descriptors */ - desc->status = desc_status; - desc->control_buffer_size = desc_bufsize; - desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - + desc->status = desc_status; + desc->control_buffer_size = desc_bufsize; + desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); + /* when it is the last descriptor */ if(num == (count - 1U)){ if (ENET_DMA_TX == direction){ - /* configure transmit end of ring mode */ + /* configure transmit end of ring mode */ desc->status |= ENET_TDES0_TERM; }else{ /* configure receive end of ring mode */ desc->control_buffer_size |= ENET_RDES1_RERM; } } - } + } } /*! - \brief receive a packet data with timestamp values to application buffer, when the DMA is in enhanced mode + \brief receive a packet data with timestamp values to application buffer, when the DMA is in enhanced mode \param[in] bufsize: the size of buffer which is the parameter in function \param[out] buffer: pointer to the application buffer note -- if the input is NULL, user should copy data in application by himself @@ -2433,26 +2476,26 @@ ErrStatus enet_ptpframe_receive_enhanced_mode(uint8_t *buffer, uint32_t bufsize, uint32_t offset = 0U, size = 0U; uint32_t timeout = 0U; uint32_t rdes0_tsv_flag; - + /* the descriptor is busy due to own by the DMA */ if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){ - return ERROR; + return ERROR; } - + /* if buffer pointer is null, indicates that users has copied data in application */ if(NULL != buffer){ - /* if no error occurs, and the frame uses only one descriptor */ - if(((uint32_t)RESET == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && - ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && - ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_FDES))){ + /* if no error occurs, and the frame uses only one descriptor */ + if(((uint32_t)RESET == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && + ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && + ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_FDES))){ /* get the frame length except CRC */ size = GET_RDES0_FRML(dma_current_rxdesc->status) - 4U; - /* if is a type frame, and CRC is not included in forwarding frame */ + /* if is a type frame, and CRC is not included in forwarding frame */ if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))){ size = size + 4U; } - + /* to avoid situation that the frame size exceeds the buffer length */ if(size > bufsize){ return ERROR; @@ -2465,22 +2508,22 @@ ErrStatus enet_ptpframe_receive_enhanced_mode(uint8_t *buffer, uint32_t bufsize, }else{ return ERROR; } - } - + } + /* if timestamp pointer is null, indicates that users don't care timestamp in application */ if(NULL != timestamp){ /* wait for ENET_RDES0_TSV flag to be set, the timestamp value is taken and write to the RDES6 and RDES7 */ - do{ + do{ rdes0_tsv_flag = (dma_current_rxdesc->status & ENET_RDES0_TSV); timeout++; }while ((RESET == rdes0_tsv_flag) && (timeout < ENET_DELAY_TO)); - + /* return ERROR due to timeout */ if(ENET_DELAY_TO == timeout){ return ERROR; } - + /* clear the ENET_RDES0_TSV flag */ dma_current_rxdesc->status &= ~ENET_RDES0_TSV; /* get the timestamp value of the received frame */ @@ -2490,7 +2533,7 @@ ErrStatus enet_ptpframe_receive_enhanced_mode(uint8_t *buffer, uint32_t bufsize, /* enable reception, descriptor is owned by DMA */ dma_current_rxdesc->status = ENET_RDES0_DAV; - + /* check Rx buffer unavailable flag status */ if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){ /* Clear RBU flag */ @@ -2498,33 +2541,32 @@ ErrStatus enet_ptpframe_receive_enhanced_mode(uint8_t *buffer, uint32_t bufsize, /* resume DMA reception by writing to the RPEN register*/ ENET_DMA_RPEN = 0; } - - /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ + + /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ /* chained mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ - dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr); - }else{ - /* ring mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ + dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr); + }else{ + /* ring mode */ if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); - }else{ + dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); + }else{ /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_rxdesc = (enet_descriptors_struct*) ((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + dma_current_rxdesc = (enet_descriptors_struct*) ((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); } } - + return SUCCESS; } /*! - \brief send data with timestamp values in application buffer as a transmit packet, when the DMA is in enhanced mode + \brief send data with timestamp values in application buffer as a transmit packet, when the DMA is in enhanced mode \param[in] buffer: pointer on the application buffer note -- if the input is NULL, user should copy data in application by himself \param[in] length: the length of frame data to be transmitted \param[out] timestamp: pointer to the table which stores the timestamp high and low note -- if the input is NULL, timestamp is ignored - \param[out] none \retval ErrStatus: SUCCESS or ERROR */ ErrStatus enet_ptpframe_transmit_enhanced_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]) @@ -2532,17 +2574,17 @@ ErrStatus enet_ptpframe_transmit_enhanced_mode(uint8_t *buffer, uint32_t length, uint32_t offset = 0; uint32_t dma_tbu_flag, dma_tu_flag; uint32_t tdes0_ttmss_flag; - uint32_t timeout = 0; - + uint32_t timeout = 0; + /* the descriptor is busy due to own by the DMA */ if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){ return ERROR; } - + /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ if(length > ENET_MAX_FRAME_SIZE){ return ERROR; - } + } /* if buffer pointer is null, indicates that users has handled data in application */ if(NULL != buffer){ @@ -2553,22 +2595,22 @@ ErrStatus enet_ptpframe_transmit_enhanced_mode(uint8_t *buffer, uint32_t length, } /* set the frame length */ dma_current_txdesc->control_buffer_size = length; - /* set the segment of frame, frame is transmitted in one descriptor */ + /* set the segment of frame, frame is transmitted in one descriptor */ dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; /* enable the DMA transmission */ dma_current_txdesc->status |= ENET_TDES0_DAV; /* check Tx buffer unavailable flag status */ - dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); + dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); - + if ((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){ /* Clear TBU and TU flag */ ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); /* resume DMA transmission by writing to the TPEN register*/ ENET_DMA_TPEN = 0; } - + /* if timestamp pointer is null, indicates that users don't care timestamp in application */ if(NULL != timestamp){ /* wait for ENET_TDES0_TTMSS flag to be set, a timestamp was captured */ @@ -2576,12 +2618,12 @@ ErrStatus enet_ptpframe_transmit_enhanced_mode(uint8_t *buffer, uint32_t length, tdes0_ttmss_flag = (dma_current_txdesc->status & ENET_TDES0_TTMSS); timeout++; }while((RESET == tdes0_ttmss_flag) && (timeout < ENET_DELAY_TO)); - + /* return ERROR due to timeout */ if(ENET_DELAY_TO == timeout){ return ERROR; } - + /* clear the ENET_TDES0_TTMSS flag */ dma_current_txdesc->status &= ~ENET_TDES0_TTMSS; /* get the timestamp value of the transmit frame */ @@ -2589,16 +2631,16 @@ ErrStatus enet_ptpframe_transmit_enhanced_mode(uint8_t *buffer, uint32_t length, timestamp[1] = dma_current_txdesc->timestamp_high; } - /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table*/ + /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table*/ /* chained mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){ - dma_current_txdesc = (enet_descriptors_struct*) (dma_current_txdesc->buffer2_next_desc_addr); + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){ + dma_current_txdesc = (enet_descriptors_struct*) (dma_current_txdesc->buffer2_next_desc_addr); }else{ - /* ring mode */ + /* ring mode */ if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){ /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR); - }else{ + dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR); + }else{ /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ dma_current_txdesc = (enet_descriptors_struct*) ((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); } @@ -2622,7 +2664,7 @@ void enet_desc_select_normal_mode(void) /*! \brief initialize the DMA Tx/Rx descriptors's parameters in normal chain mode with PTP function - \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum only one parameter can be selected which is shown as below \arg ENET_DMA_TX: DMA Tx descriptors \arg ENET_DMA_RX: DMA Rx descriptors @@ -2636,18 +2678,18 @@ void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, en uint32_t desc_status = 0U, desc_bufsize = 0U; enet_descriptors_struct *desc, *desc_tab; uint8_t *buf; - + /* if want to initialize DMA Tx descriptors */ if (ENET_DMA_TX == direction){ /* save a copy of the DMA Tx descriptors */ desc_tab = txdesc_tab; buf = &tx_buff[0][0]; count = ENET_TXBUF_NUM; - maxsize = ENET_TXBUF_SIZE; - + maxsize = ENET_TXBUF_SIZE; + /* select chain mode, and enable transmit timestamp function */ desc_status = ENET_TDES0_TCHM | ENET_TDES0_TTSEN; - + /* configure DMA Tx descriptor table address register */ ENET_DMA_TDTADDR = (uint32_t)desc_tab; dma_current_txdesc = desc_tab; @@ -2658,50 +2700,50 @@ void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, en desc_tab = rxdesc_tab; buf = &rx_buff[0][0]; count = ENET_RXBUF_NUM; - maxsize = ENET_RXBUF_SIZE; - + maxsize = ENET_RXBUF_SIZE; + /* enable receiving */ desc_status = ENET_RDES0_DAV; /* select receive chained mode and set buffer1 size */ desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE; - + /* configure DMA Rx descriptor table address register */ ENET_DMA_RDTADDR = (uint32_t)desc_tab; dma_current_rxdesc = desc_tab; - dma_current_ptp_rxdesc = desc_ptptab; + dma_current_ptp_rxdesc = desc_ptptab; } - - /* configure each descriptor */ + + /* configure each descriptor */ for(num = 0U; num < count; num++){ /* get the pointer to the next descriptor of the descriptor table */ desc = desc_tab + num; /* configure descriptors */ - desc->status = desc_status; + desc->status = desc_status; desc->control_buffer_size = desc_bufsize; desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - + /* if is not the last descriptor */ if(num < (count - 1U)){ /* configure the next descriptor address */ desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U); }else{ - /* when it is the last descriptor, the next descriptor address - equals to first descriptor address in descriptor table */ - desc->buffer2_next_desc_addr = (uint32_t)desc_tab; + /* when it is the last descriptor, the next descriptor address + equals to first descriptor address in descriptor table */ + desc->buffer2_next_desc_addr = (uint32_t)desc_tab; } /* set desc_ptptab equal to desc_tab */ (&desc_ptptab[num])->buffer1_addr = desc->buffer1_addr; (&desc_ptptab[num])->buffer2_next_desc_addr = desc->buffer2_next_desc_addr; - } - /* when it is the last ptp descriptor, preserve the first descriptor + } + /* when it is the last ptp descriptor, preserve the first descriptor address of desc_ptptab in ptp descriptor status */ (&desc_ptptab[num-1U])->status = (uint32_t)desc_ptptab; } /*! \brief initialize the DMA Tx/Rx descriptors's parameters in normal ring mode with PTP function - \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum only one parameter can be selected which is shown as below \arg ENET_DMA_TX: DMA Tx descriptors \arg ENET_DMA_RX: DMA Rx descriptors @@ -2719,18 +2761,18 @@ void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, ene /* configure descriptor skip length */ ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL; ENET_DMA_BCTL |= DMA_BCTL_DPSL(0); - + /* if want to initialize DMA Tx descriptors */ if (ENET_DMA_TX == direction){ /* save a copy of the DMA Tx descriptors */ desc_tab = txdesc_tab; buf = &tx_buff[0][0]; count = ENET_TXBUF_NUM; - maxsize = ENET_TXBUF_SIZE; - + maxsize = ENET_TXBUF_SIZE; + /* select ring mode, and enable transmit timestamp function */ desc_status = ENET_TDES0_TTSEN; - + /* configure DMA Tx descriptor table address register */ ENET_DMA_TDTADDR = (uint32_t)desc_tab; dma_current_txdesc = desc_tab; @@ -2741,33 +2783,33 @@ void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, ene desc_tab = rxdesc_tab; buf = &rx_buff[0][0]; count = ENET_RXBUF_NUM; - maxsize = ENET_RXBUF_SIZE; - + maxsize = ENET_RXBUF_SIZE; + /* enable receiving */ desc_status = ENET_RDES0_DAV; /* select receive ring mode and set buffer1 size */ desc_bufsize = (uint32_t)ENET_RXBUF_SIZE; - + /* configure DMA Rx descriptor table address register */ ENET_DMA_RDTADDR = (uint32_t)desc_tab; dma_current_rxdesc = desc_tab; - dma_current_ptp_rxdesc = desc_ptptab; + dma_current_ptp_rxdesc = desc_ptptab; } - - /* configure each descriptor */ + + /* configure each descriptor */ for(num = 0U; num < count; num++){ /* get the pointer to the next descriptor of the descriptor table */ desc = desc_tab + num; /* configure descriptors */ - desc->status = desc_status; + desc->status = desc_status; desc->control_buffer_size = desc_bufsize; desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - + /* when it is the last descriptor */ if(num == (count - 1U)){ if (ENET_DMA_TX == direction){ - /* configure transmit end of ring mode */ + /* configure transmit end of ring mode */ desc->status |= ENET_TDES0_TERM; }else{ /* configure receive end of ring mode */ @@ -2777,43 +2819,43 @@ void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, ene /* set desc_ptptab equal to desc_tab */ (&desc_ptptab[num])->buffer1_addr = desc->buffer1_addr; (&desc_ptptab[num])->buffer2_next_desc_addr = desc->buffer2_next_desc_addr; - } - /* when it is the last ptp descriptor, preserve the first descriptor + } + /* when it is the last ptp descriptor, preserve the first descriptor address of desc_ptptab in ptp descriptor status */ (&desc_ptptab[num-1U])->status = (uint32_t)desc_ptptab; } /*! - \brief receive a packet data with timestamp values to application buffer, when the DMA is in normal mode + \brief receive a packet data with timestamp values to application buffer, when the DMA is in normal mode \param[in] bufsize: the size of buffer which is the parameter in function - \param[out] timestamp: pointer to the table which stores the timestamp high and low \param[out] buffer: pointer to the application buffer note -- if the input is NULL, user should copy data in application by himself + \param[out] timestamp: pointer to the table which stores the timestamp high and low \retval ErrStatus: SUCCESS or ERROR */ ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]) { uint32_t offset = 0U, size = 0U; - + /* the descriptor is busy due to own by the DMA */ if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){ return ERROR; } - + /* if buffer pointer is null, indicates that users has copied data in application */ if(NULL != buffer){ /* if no error occurs, and the frame uses only one descriptor */ if(((uint32_t)RESET == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_FDES))){ - + /* get the frame length except CRC */ size = GET_RDES0_FRML(dma_current_rxdesc->status) - 4U; /* if is a type frame, and CRC is not included in forwarding frame */ if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))){ size = size + 4U; } - + /* to avoid situation that the frame size exceeds the buffer length */ if(size > bufsize){ return ERROR; @@ -2823,7 +2865,7 @@ ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, u for(offset = 0U; offset < size; offset++){ (*(buffer + offset)) = (*(__IO uint8_t *)(uint32_t)((dma_current_ptp_rxdesc->buffer1_addr) + offset)); } - + }else{ return ERROR; } @@ -2834,10 +2876,10 @@ ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, u dma_current_rxdesc->buffer1_addr = dma_current_ptp_rxdesc ->buffer1_addr ; dma_current_rxdesc->buffer2_next_desc_addr = dma_current_ptp_rxdesc ->buffer2_next_desc_addr; - + /* enable reception, descriptor is owned by DMA */ dma_current_rxdesc->status = ENET_RDES0_DAV; - + /* check Rx buffer unavailable flag status */ if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){ /* clear RBU flag */ @@ -2845,9 +2887,9 @@ ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, u /* resume DMA reception by writing to the RPEN register*/ ENET_DMA_RPEN = 0U; } - - /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ + + /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ /* chained mode */ if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->buffer2_next_desc_addr); @@ -2860,16 +2902,16 @@ ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, u dma_current_ptp_rxdesc++; } }else{ - /* ring mode */ + /* ring mode */ if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ /* if is the last descriptor in table, the next descriptor is the table header */ dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); /* RDES2 and RDES3 will not be covered by buffer address, so do not need to preserve a new table, use the same table with RxDMA descriptor */ - dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); + dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); }else{ /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); dma_current_ptp_rxdesc ++; } } @@ -2878,7 +2920,7 @@ ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, u } /*! - \brief send data with timestamp values in application buffer as a transmit packet, when the DMA is in normal mode + \brief send data with timestamp values in application buffer as a transmit packet, when the DMA is in normal mode \param[in] buffer: pointer on the application buffer note -- if the input is NULL, user should copy data in application by himself \param[in] length: the length of frame data to be transmitted @@ -2889,8 +2931,8 @@ ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, u ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]) { uint32_t offset = 0U, timeout = 0U; - uint32_t dma_tbu_flag, dma_tu_flag, tdes0_ttmss_flag; - + uint32_t dma_tbu_flag, dma_tu_flag, tdes0_ttmss_flag; + /* the descriptor is busy due to own by the DMA */ if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){ return ERROR; @@ -2900,7 +2942,7 @@ ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, u if(length > ENET_MAX_FRAME_SIZE){ return ERROR; } - + /* if buffer pointer is null, indicates that users has handled data in application */ if(NULL != buffer){ /* copy frame data from application buffer to Tx buffer */ @@ -2914,31 +2956,31 @@ ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, u dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; /* enable the DMA transmission */ dma_current_txdesc->status |= ENET_TDES0_DAV; - + /* check Tx buffer unavailable flag status */ - dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); + dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); - + if((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){ /* clear TBU and TU flag */ ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); /* resume DMA transmission by writing to the TPEN register*/ ENET_DMA_TPEN = 0U; } - + /* if timestamp pointer is null, indicates that users don't care timestamp in application */ if(NULL != timestamp){ /* wait for ENET_TDES0_TTMSS flag to be set, a timestamp was captured */ - do{ + do{ tdes0_ttmss_flag = (dma_current_txdesc->status & ENET_TDES0_TTMSS); timeout++; }while((RESET == tdes0_ttmss_flag) && (timeout < ENET_DELAY_TO)); - + /* return ERROR due to timeout */ if(ENET_DELAY_TO == timeout){ return ERROR; - } - + } + /* clear the ENET_TDES0_TTMSS flag */ dma_current_txdesc->status &= ~ENET_TDES0_TTMSS; /* get the timestamp value of the transmit frame */ @@ -2948,12 +2990,12 @@ ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, u dma_current_txdesc->buffer1_addr = dma_current_ptp_txdesc ->buffer1_addr ; dma_current_txdesc->buffer2_next_desc_addr = dma_current_ptp_txdesc ->buffer2_next_desc_addr; - /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table */ + /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table */ /* chained mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){ dma_current_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->buffer2_next_desc_addr); /* if it is the last ptp descriptor */ - if(0U != dma_current_ptp_txdesc->status){ + if(0U != dma_current_ptp_txdesc->status){ /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ dma_current_ptp_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->status); }else{ @@ -2961,17 +3003,17 @@ ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, u dma_current_ptp_txdesc++; } }else{ - /* ring mode */ + /* ring mode */ if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){ /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR); + dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR); /* TDES2 and TDES3 will not be covered by buffer address, so do not need to preserve a new table, use the same table with TxDMA descriptor */ dma_current_ptp_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->status); }else{ /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_txdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); - dma_current_ptp_txdesc ++; + dma_current_txdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + dma_current_ptp_txdesc ++; } } return SUCCESS; @@ -2980,7 +3022,7 @@ ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, u #endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ /*! - \brief wakeup frame filter register pointer reset + \brief wakeup frame filter register pointer reset \param[in] none \param[out] none \retval none @@ -2991,7 +3033,7 @@ void enet_wum_filter_register_pointer_reset(void) } /*! - \brief set the remote wakeup frame registers + \brief set the remote wakeup frame registers \param[in] pdata: pointer to buffer data which is written to remote wakeup frame registers (8 words total) \param[out] none \retval none @@ -2999,7 +3041,7 @@ void enet_wum_filter_register_pointer_reset(void) void enet_wum_filter_config(uint32_t pdata[]) { uint32_t num = 0U; - + /* configure ENET_MAC_RWFF register */ for(num = 0U; num < ETH_WAKEUP_REGISTER_LENGTH; num++){ ENET_MAC_RWFF = pdata[num]; @@ -3007,8 +3049,9 @@ void enet_wum_filter_config(uint32_t pdata[]) } /*! - \brief enable wakeup management features - \param[in] feature: one or more parameters can be selected which are shown as below + \brief enable wakeup management features + \param[in] feature: the wake up type which is selected + one or more parameters can be selected which are shown as below \arg ENET_WUM_POWER_DOWN: power down mode \arg ENET_WUM_MAGIC_PACKET_FRAME: enable a wakeup event due to magic packet reception \arg ENET_WUM_WAKE_UP_FRAME: enable a wakeup event due to wakeup frame reception @@ -3022,8 +3065,9 @@ void enet_wum_feature_enable(uint32_t feature) } /*! - \brief disable wakeup management features - \param[in] feature: one or more parameters can be selected which are shown as below + \brief disable wakeup management features + \param[in] feature: the wake up type which is selected + one or more parameters can be selected which are shown as below \arg ENET_WUM_MAGIC_PACKET_FRAME: enable a wakeup event due to magic packet reception \arg ENET_WUM_WAKE_UP_FRAME: enable a wakeup event due to wakeup frame reception \arg ENET_WUM_GLOBAL_UNICAST: any received unicast frame passed filter is considered to be a wakeup frame @@ -3036,8 +3080,8 @@ void enet_wum_feature_disable(uint32_t feature) } /*! - \brief reset the MAC statistics counters - \param[in] none + \brief reset the MAC statistics counters + \param[in] none \param[out] none \retval none */ @@ -3049,7 +3093,8 @@ void enet_msc_counters_reset(void) /*! \brief enable the MAC statistics counter features - \param[in] feature: one or more parameters can be selected which are shown as below + \param[in] feature: the feature of MAC statistics counter + one or more parameters can be selected which are shown as below \arg ENET_MSC_COUNTER_STOP_ROLLOVER: counter stop rollover \arg ENET_MSC_RESET_ON_READ: reset on read \arg ENET_MSC_COUNTERS_FREEZE: MSC counter freeze @@ -3063,7 +3108,8 @@ void enet_msc_feature_enable(uint32_t feature) /*! \brief disable the MAC statistics counter features - \param[in] feature: one or more parameters can be selected which are shown as below + \param[in] feature: the feature of MAC statistics counter + one or more parameters can be selected which are shown as below \arg ENET_MSC_COUNTER_STOP_ROLLOVER: counter stop rollover \arg ENET_MSC_RESET_ON_READ: reset on read \arg ENET_MSC_COUNTERS_FREEZE: MSC counter freeze @@ -3076,8 +3122,8 @@ void enet_msc_feature_disable(uint32_t feature) } /*! - \brief configure MAC statistics counters preset mode - \param[in] mode: MSC counters preset mode, refer to enet_msc_preset_enum, + \brief configure MAC statistics counters preset mode + \param[in] mode: MSC counters preset mode, refer to enet_msc_preset_enum only one parameter can be selected which is shown as below \arg ENET_MSC_PRESET_NONE: do not preset MSC counter \arg ENET_MSC_PRESET_HALF: preset all MSC counters to almost-half(0x7FFF FFF0) value @@ -3092,8 +3138,8 @@ void enet_msc_counters_preset_config(enet_msc_preset_enum mode) } /*! - \brief get MAC statistics counter - \param[in] counter: MSC counters which is selected, refer to enet_msc_counter_enum, + \brief get MAC statistics counter + \param[in] counter: MSC counters which is selected, refer to enet_msc_counter_enum only one parameter can be selected which is shown as below \arg ENET_MSC_TX_SCCNT: MSC transmitted good frames after a single collision counter \arg ENET_MSC_TX_MSCCNT: MSC transmitted good frames after more than a single collision counter @@ -3107,9 +3153,9 @@ void enet_msc_counters_preset_config(enet_msc_preset_enum mode) uint32_t enet_msc_counters_get(enet_msc_counter_enum counter) { uint32_t reval; - + reval = REG32((ENET + (uint32_t)counter)); - + return reval; } @@ -3153,7 +3199,8 @@ void enet_ptp_feature_disable(uint32_t feature) /*! \brief configure the PTP timestamp function - \param[in] func: only one parameter can be selected which is shown as below + \param[in] func: the function of PTP timestamp + only one parameter can be selected which is shown as below \arg ENET_CKNT_ORDINARY: type of ordinary clock node type for timestamp \arg ENET_CKNT_BOUNDARY: type of boundary clock node type for timestamp \arg ENET_CKNT_END_TO_END: type of end-to-end transparent clock node type for timestamp @@ -3168,7 +3215,7 @@ void enet_ptp_feature_disable(uint32_t feature) \arg ENET_SNOOPING_PTP_VERSION_2: version 2 \arg ENET_SNOOPING_PTP_VERSION_1: version 1 \arg ENET_EVENT_TYPE_MESSAGES_SNAPSHOT: only event type messages are taken snapshot - \arg ENET_ALL_TYPE_MESSAGES_SNAPSHOT: all type messages are taken snapshot except announce, + \arg ENET_ALL_TYPE_MESSAGES_SNAPSHOT: all type messages are taken snapshot except announce, management and signaling message \arg ENET_MASTER_NODE_MESSAGE_SNAPSHOT: snapshot is only take for master node message \arg ENET_SLAVE_NODE_MESSAGE_SNAPSHOT: snapshot is only taken for slave node message @@ -3189,10 +3236,10 @@ ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func) ENET_PTP_TSCTL &= ~ENET_PTP_TSCTL_CKNT; ENET_PTP_TSCTL |= (uint32_t)func; break; - case ENET_PTP_ADDEND_UPDATE: + case ENET_PTP_ADDEND_UPDATE: /* this bit must be read as zero before application set it */ do{ - temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSARU; + temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSARU; timeout++; }while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); /* return ERROR due to timeout */ @@ -3200,12 +3247,12 @@ ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func) enet_state = ERROR; }else{ ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSARU; - } + } break; case ENET_PTP_SYSTIME_UPDATE: /* both the TMSSTU and TMSSTI bits must be read as zero before application set this bit */ do{ - temp_state = ENET_PTP_TSCTL & (ENET_PTP_TSCTL_TMSSTU | ENET_PTP_TSCTL_TMSSTI); + temp_state = ENET_PTP_TSCTL & (ENET_PTP_TSCTL_TMSSTU | ENET_PTP_TSCTL_TMSSTI); timeout++; }while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); /* return ERROR due to timeout */ @@ -3213,12 +3260,12 @@ ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func) enet_state = ERROR; }else{ ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTU; - } - break; + } + break; case ENET_PTP_SYSTIME_INIT: /* this bit must be read as zero before application set it */ do{ - temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSSTI; + temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSSTI; timeout++; }while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); /* return ERROR due to timeout */ @@ -3226,16 +3273,16 @@ ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func) enet_state = ERROR; }else{ ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTI; - } - break; - default: - temp_config = (uint32_t)func & (~BIT(31)); - if(RESET != ((uint32_t)func & BIT(31))){ - ENET_PTP_TSCTL |= temp_config; - }else{ - ENET_PTP_TSCTL &= ~temp_config; } - break; + break; + default: + temp_config = (uint32_t)func & (~BIT(31)); + if(RESET != ((uint32_t)func & BIT(31))){ + ENET_PTP_TSCTL |= temp_config; + }else{ + ENET_PTP_TSCTL &= ~temp_config; + } + break; } return enet_state; @@ -3243,8 +3290,7 @@ ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func) /*! \brief configure system time subsecond increment value - \param[in] subsecond: the value will be added to the subsecond value of system time, - this value must be between 0 and 0xFF + \param[in] subsecond: the value will be added to the subsecond value of system time(0x00000000 - 0x000000FF) \param[out] none \retval none */ @@ -3266,12 +3312,12 @@ void enet_ptp_timestamp_addend_config(uint32_t add) /*! \brief initialize or add/subtract to second of the system time - \param[in] sign: timestamp update positive or negative sign, + \param[in] sign: timestamp update positive or negative sign only one parameter can be selected which is shown as below \arg ENET_PTP_ADD_TO_TIME: timestamp update value is added to system time \arg ENET_PTP_SUBSTRACT_FROM_TIME: timestamp update value is subtracted from system time \param[in] second: initializing or adding/subtracting to second of the system time - \param[in] subsecond: the current subsecond of the system time + \param[in] subsecond: the current subsecond of the system time with 0.46 ns accuracy if required accuracy is 20 ns \param[out] none \retval none @@ -3279,7 +3325,7 @@ void enet_ptp_timestamp_addend_config(uint32_t add) void enet_ptp_timestamp_update_config(uint32_t sign, uint32_t second, uint32_t subsecond) { ENET_PTP_TSUH = second; - ENET_PTP_TSUL = sign | PTP_TSUL_TMSUSS(subsecond); + ENET_PTP_TSUL = sign | PTP_TSUL_TMSUSS(subsecond); } /*! @@ -3298,7 +3344,7 @@ void enet_ptp_expected_time_config(uint32_t second, uint32_t nanosecond) /*! \brief get the current system time \param[in] none - \param[out] systime_struct: pointer to a enet_ptp_systime_struct structure which contains + \param[out] systime_struct: pointer to a enet_ptp_systime_struct structure which contains parameters of PTP system time members of the structure and the member values are shown as below: second: 0x0 - 0xFFFF FFFF @@ -3311,9 +3357,9 @@ void enet_ptp_system_time_get(enet_ptp_systime_struct *systime_struct) uint32_t temp_sec = 0U, temp_subs = 0U; /* get the value of sysytem time registers */ - temp_sec = (uint32_t)ENET_PTP_TSH; + temp_sec = (uint32_t)ENET_PTP_TSH; temp_subs = (uint32_t)ENET_PTP_TSL; - + /* get sysytem time and construct the enet_ptp_systime_struct structure */ systime_struct->second = temp_sec; systime_struct->subsecond = GET_PTP_TSL_STMSS(temp_subs); @@ -3322,18 +3368,18 @@ void enet_ptp_system_time_get(enet_ptp_systime_struct *systime_struct) /*! \brief configure the PPS output frequency - \param[in] freq: PPS output frequency, + \param[in] freq: PPS output frequency only one parameter can be selected which is shown as below \arg ENET_PPSOFC_1HZ: PPS output 1Hz frequency - \arg ENET_PPSOFC_2HZ: PPS output 2Hz frequency - \arg ENET_PPSOFC_4HZ: PPS output 4Hz frequency - \arg ENET_PPSOFC_8HZ: PPS output 8Hz frequency - \arg ENET_PPSOFC_16HZ: PPS output 16Hz frequency - \arg ENET_PPSOFC_32HZ: PPS output 32Hz frequency + \arg ENET_PPSOFC_2HZ: PPS output 2Hz frequency + \arg ENET_PPSOFC_4HZ: PPS output 4Hz frequency + \arg ENET_PPSOFC_8HZ: PPS output 8Hz frequency + \arg ENET_PPSOFC_16HZ: PPS output 16Hz frequency + \arg ENET_PPSOFC_32HZ: PPS output 32Hz frequency \arg ENET_PPSOFC_64HZ: PPS output 64Hz frequency \arg ENET_PPSOFC_128HZ: PPS output 128Hz frequency \arg ENET_PPSOFC_256HZ: PPS output 256Hz frequency - \arg ENET_PPSOFC_512HZ: PPS output 512Hz frequency + \arg ENET_PPSOFC_512HZ: PPS output 512Hz frequency \arg ENET_PPSOFC_1024HZ: PPS output 1024Hz frequency \arg ENET_PPSOFC_2048HZ: PPS output 2048Hz frequency \arg ENET_PPSOFC_4096HZ: PPS output 4096Hz frequency @@ -3362,7 +3408,7 @@ void enet_initpara_reset(void) enet_initpara.dma_maxburst = 0U; enet_initpara.dma_arbitration = 0U; enet_initpara.store_forward_mode = 0U; - enet_initpara.dma_function = 0U; + enet_initpara.dma_function = 0U; enet_initpara.vlan_config = 0U; enet_initpara.flow_control = 0U; enet_initpara.hashtable_high = 0U; @@ -3371,10 +3417,10 @@ void enet_initpara_reset(void) enet_initpara.halfduplex_param = 0U; enet_initpara.timer_config = 0U; enet_initpara.interframegap = 0U; -} +} /*! - \brief initialize ENET peripheral with generally concerned parameters, call it by enet_init() + \brief initialize ENET peripheral with generally concerned parameters, call it by enet_init() \param[in] none \param[out] none \retval none @@ -3396,7 +3442,7 @@ static void enet_default_init(void) | ENET_AUTO_PADCRC_DROP_DISABLE \ | ENET_CHECKSUMOFFLOAD_DISABLE; ENET_MAC_CFG = reg_value; - + /* configure ENET_MAC_FRMF register */ ENET_MAC_FRMF = ENET_SRC_FILTER_DISABLE |ENET_DEST_FILTER_INVERSE_DISABLE \ |ENET_MULTICAST_FILTER_PERFECT |ENET_UNICAST_FILTER_PERFECT \ @@ -3405,7 +3451,7 @@ static void enet_default_init(void) /* configure ENET_MAC_HLH, ENET_MAC_HLL register */ ENET_MAC_HLH = 0x0U; - + ENET_MAC_HLL = 0x0U; /* configure ENET_MAC_FCTL, ENET_MAC_FCTH register */ @@ -3414,13 +3460,13 @@ static void enet_default_init(void) reg_value |= MAC_FCTL_PTM(0) |ENET_ZERO_QUANTA_PAUSE_DISABLE \ |ENET_PAUSETIME_MINUS4 |ENET_UNIQUE_PAUSEDETECT \ |ENET_RX_FLOWCONTROL_DISABLE |ENET_TX_FLOWCONTROL_DISABLE; - ENET_MAC_FCTL = reg_value; - + ENET_MAC_FCTL = reg_value; + ENET_MAC_FCTH = ENET_DEACTIVE_THRESHOLD_512BYTES |ENET_ACTIVE_THRESHOLD_1536BYTES; - + /* configure ENET_MAC_VLT register */ ENET_MAC_VLT = ENET_VLANTAGCOMPARISON_16BIT |MAC_VLT_VLTI(0); - + /* DMA */ /* configure ENET_DMA_CTL register */ reg_value = ENET_DMA_CTL; @@ -3429,8 +3475,8 @@ static void enet_default_init(void) |ENET_FLUSH_RXFRAME_ENABLE |ENET_TX_MODE_STOREFORWARD \ |ENET_TX_THRESHOLD_64BYTES |ENET_RX_THRESHOLD_64BYTES \ |ENET_FORWARD_ERRFRAMES_DISABLE |ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE \ - |ENET_SECONDFRAME_OPT_DISABLE; - ENET_DMA_CTL = reg_value; + |ENET_SECONDFRAME_OPT_DISABLE; + ENET_DMA_CTL = reg_value; /* configure ENET_DMA_BCTL register */ reg_value = ENET_DMA_BCTL; @@ -3439,7 +3485,7 @@ static void enet_default_init(void) |ENET_RXDP_32BEAT |ENET_PGBL_32BEAT |ENET_RXTX_DIFFERENT_PGBL \ |ENET_FIXED_BURST_ENABLE |ENET_MIXED_BURST_DISABLE \ |ENET_NORMAL_DESCRIPTOR; - ENET_DMA_BCTL = reg_value; + ENET_DMA_BCTL = reg_value; } #ifndef USE_DELAY @@ -3451,8 +3497,8 @@ static void enet_default_init(void) */ static void enet_delay(uint32_t ncount) { - uint32_t delay_time = 0U; - + __IO uint32_t delay_time = 0U; + for(delay_time = ncount; delay_time != 0U; delay_time--){ } } diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_exmc.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_exmc.c index a3049a7448..e225258eb5 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_exmc.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_exmc.c @@ -1,33 +1,58 @@ /*! - \file gd32f4xx_exmc.c - \brief EXMC driver + \file gd32f4xx_exmc.c + \brief EXMC driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_exmc.h" /* EXMC bank0 register reset value */ -#define BANK0_SNCTL_REGION_RESET ((uint32_t)0x000030DAU) +#define BANK0_SNCTL_RESET ((uint32_t)0x000030DAU) #define BANK0_SNTCFG_RESET ((uint32_t)0x0FFFFFFFU) #define BANK0_SNWTCFG_RESET ((uint32_t)0x0FFFFFFFU) -/* EXMC bank1/2 register reset mask*/ -#define BANK1_2_NPCTL_RESET ((uint32_t)0x00000018U) -#define BANK1_2_NPINTEN_RESET ((uint32_t)0x00000040U) -#define BANK1_2_NPCTCFG_RESET ((uint32_t)0xFCFCFCFCU) -#define BANK1_2_NPATCFG_RESET ((uint32_t)0xFCFCFCFCU) +/* EXMC bank1/2 register reset mask */ +#define BANK1_2_NPCTL_RESET ((uint32_t)0x00000008U) +#define BANK1_2_NPINTEN_RESET ((uint32_t)0x00000042U) +#define BANK1_2_NPCTCFG_RESET ((uint32_t)0xFFFFFFFFU) +#define BANK1_2_NPATCFG_RESET ((uint32_t)0xFFFFFFFFU) -/* EXMC bank3 register reset mask*/ -#define BANK3_NPCTL_RESET ((uint32_t)0x00000018U) -#define BANK3_NPINTEN_RESET ((uint32_t)0x00000000U) -#define BANK3_NPCTCFG_RESET ((uint32_t)0xFCFCFCFCU) -#define BANK3_NPATCFG_RESET ((uint32_t)0xFCFCFCFCU) -#define BANK3_PIOTCFG3_RESET ((uint32_t)0xFCFCFCFCU) +/* EXMC bank3 register reset mask */ +#define BANK3_NPCTL_RESET ((uint32_t)0x00000008U) +#define BANK3_NPINTEN_RESET ((uint32_t)0x00000040U) +#define BANK3_NPCTCFG_RESET ((uint32_t)0xFFFFFFFFU) +#define BANK3_NPATCFG_RESET ((uint32_t)0xFFFFFFFFU) +#define BANK3_PIOTCFG3_RESET ((uint32_t)0xFFFFFFFFU) /* EXMC SDRAM device register reset mask */ #define SDRAM_DEVICE_SDCTL_RESET ((uint32_t)0x000002D0U) @@ -64,13 +89,13 @@ #define NPCTCFG_COMHLD_OFFSET ((uint32_t)16U) #define NPCTCFG_COMHIZ_OFFSET ((uint32_t)24U) -#define NPATCFG_COMWAIT_OFFSET ((uint32_t)8U) -#define NPATCFG_COMHLD_OFFSET ((uint32_t)16U) -#define NPATCFG_COMHIZ_OFFSET ((uint32_t)24U) +#define NPATCFG_ATTWAIT_OFFSET ((uint32_t)8U) +#define NPATCFG_ATTHLD_OFFSET ((uint32_t)16U) +#define NPATCFG_ATTHIZ_OFFSET ((uint32_t)24U) -#define PIOTCFG_COMWAIT_OFFSET ((uint32_t)8U) -#define PIOTCFG_COMHLD_OFFSET ((uint32_t)16U) -#define PIOTCFG_COMHIZ_OFFSET ((uint32_t)24U) +#define PIOTCFG_IOWAIT_OFFSET ((uint32_t)8U) +#define PIOTCFG_IOHLD_OFFSET ((uint32_t)16U) +#define PIOTCFG_IOHIZ_OFFSET ((uint32_t)24U) #define SDCTL_WPEN_OFFSET ((uint32_t)9U) #define SDCTL_BRSTRD_OFFSET ((uint32_t)12U) @@ -96,11 +121,12 @@ #define SRCMD_RWAITCYCLE_OFFSET ((uint32_t)16U) #define SWCMD_WWAITCYCLE_OFFSET ((uint32_t)16U) -#define INTEN_INTEN_OFFSET ((uint32_t)3U) +#define INTEN_INTS_OFFSET ((uint32_t)3U) /*! \brief deinitialize EXMC NOR/SRAM region \param[in] exmc_norsram_region: select the region of bank0 + only one parameter can be selected which is shown as below: \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) \param[out] none \retval none @@ -108,101 +134,20 @@ void exmc_norsram_deinit(uint32_t exmc_norsram_region) { /* reset the registers */ - EXMC_SNCTL(exmc_norsram_region) = BANK0_SNCTL_REGION_RESET; + EXMC_SNCTL(exmc_norsram_region) = BANK0_SNCTL_RESET; EXMC_SNTCFG(exmc_norsram_region) = BANK0_SNTCFG_RESET; EXMC_SNWTCFG(exmc_norsram_region) = BANK0_SNWTCFG_RESET; } /*! - \brief initialize EXMC NOR/SRAM region - \param[in] exmc_norsram_parameter_struct: configure the EXMC NOR/SRAM parameter - norsram_region: EXMC_BANK0_NORSRAM_REGIONx,x=0..3 - write_mode: EXMC_ASYN_WRITE,EXMC_SYN_WRITE - extended_mode: ENABLE or DISABLE - asyn_wait: ENABLE or DISABLE - nwait_signal: ENABLE or DISABLE - memory_write: ENABLE or DISABLE - nwait_config: EXMC_NWAIT_CONFIG_BEFORE,EXMC_NWAIT_CONFIG_DURING - wrap_burst_mode: ENABLE or DISABLE - nwait_polarity: EXMC_NWAIT_POLARITY_LOW,EXMC_NWAIT_POLARITY_HIGH - burst_mode: ENABLE or DISABLE - databus_width: EXMC_NOR_DATABUS_WIDTH_8B,EXMC_NOR_DATABUS_WIDTH_16B - memory_type: EXMC_MEMORY_TYPE_SRAM,EXMC_MEMORY_TYPE_PSRAM,EXMC_MEMORY_TYPE_NOR - address_data_mux: ENABLE or DISABLE - read_write_timing: struct exmc_norsram_timing_parameter_struct set the time - write_timing: struct exmc_norsram_timing_parameter_struct set the time - \param[out] none - \retval none -*/ -void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct) -{ - uint32_t snctl = 0x00000000U,sntcfg = 0x00000000U,snwtcfg = 0x00000000U; - - /* get the register value */ - snctl = EXMC_SNCTL(exmc_norsram_init_struct->norsram_region); - - /* clear relative bits */ - snctl &= ((uint32_t)~(EXMC_SNCTL_EXMODEN | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_SBRSTEN | - EXMC_SNCTL_NRWTPOL | EXMC_SNCTL_WRAPEN | EXMC_SNCTL_NRWTCFG | EXMC_SNCTL_WREN | - EXMC_SNCTL_NRWTEN | EXMC_SNCTL_EXMODEN | EXMC_SNCTL_ASYNCWAIT | EXMC_SNCTL_SYNCWR | - EXMC_SNCTL_NRBKEN)); - - snctl = (uint32_t)(exmc_norsram_init_struct->address_data_mux << SNCTL_NRMUX_OFFSET) | - exmc_norsram_init_struct->memory_type | - exmc_norsram_init_struct->databus_width | - (exmc_norsram_init_struct->burst_mode << SNCTL_SBRSTEN_OFFSET) | - exmc_norsram_init_struct->nwait_polarity | - (exmc_norsram_init_struct->wrap_burst_mode << SNCTL_WRAPEN_OFFSET) | - exmc_norsram_init_struct->nwait_config | - (exmc_norsram_init_struct->memory_write << SNCTL_WREN_OFFSET) | - (exmc_norsram_init_struct->nwait_signal << SNCTL_NRWTEN_OFFSET) | - (exmc_norsram_init_struct->extended_mode << SNCTL_EXMODEN_OFFSET) | - (exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET) | - exmc_norsram_init_struct->write_mode; - - sntcfg = (uint32_t)exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime | - (exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime << SNTCFG_AHLD_OFFSET) | - (exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime << SNTCFG_DSET_OFFSET) | - (exmc_norsram_init_struct->read_write_timing->bus_latency << SNTCFG_BUSLAT_OFFSET) | - exmc_norsram_init_struct->read_write_timing->syn_clk_division | - exmc_norsram_init_struct->read_write_timing->syn_data_latency | - exmc_norsram_init_struct->read_write_timing->asyn_access_mode; - - /* nor flash access enable */ - if(EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type) - { - snctl |= (uint32_t)EXMC_SNCTL_NREN; - } - - /* extended mode configure */ - if(ENABLE == exmc_norsram_init_struct->extended_mode) - { - snwtcfg = (uint32_t)exmc_norsram_init_struct->write_timing->asyn_address_setuptime | - (exmc_norsram_init_struct->write_timing->asyn_address_holdtime << SNTCFG_AHLD_OFFSET )| - (exmc_norsram_init_struct->write_timing->asyn_data_setuptime << SNTCFG_DSET_OFFSET) | - (exmc_norsram_init_struct->write_timing->bus_latency << SNTCFG_BUSLAT_OFFSET) | - exmc_norsram_init_struct->write_timing->asyn_access_mode; - } - else - { - snwtcfg = BANK0_SNWTCFG_RESET; - } - - /* configure the registers */ - EXMC_SNCTL(exmc_norsram_init_struct->norsram_region) = snctl; - EXMC_SNTCFG(exmc_norsram_init_struct->norsram_region) = sntcfg; - EXMC_SNWTCFG(exmc_norsram_init_struct->norsram_region) = snwtcfg; -} - -/*! - \brief initialize the struct exmc_norsram_parameter_struct + \brief initialize exmc_norsram_parameter_struct with the default values \param[in] none \param[out] exmc_norsram_init_struct: the initialized struct exmc_norsram_parameter_struct pointer \retval none */ -void exmc_norsram_parameter_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct) +void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct) { - /* configure the structure with default value */ + /* configure the structure with default values */ exmc_norsram_init_struct->norsram_region = EXMC_BANK0_NORSRAM_REGION0; exmc_norsram_init_struct->address_data_mux = ENABLE; exmc_norsram_init_struct->memory_type = EXMC_MEMORY_TYPE_SRAM; @@ -217,7 +162,7 @@ void exmc_norsram_parameter_init(exmc_norsram_parameter_struct* exmc_norsram_ini exmc_norsram_init_struct->asyn_wait = DISABLE; exmc_norsram_init_struct->write_mode = EXMC_ASYN_WRITE; - /* read/write timing configure */ + /* configure read/write timing */ exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime = 0xFU; exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime = 0xFU; exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime = 0xFFU; @@ -235,45 +180,100 @@ void exmc_norsram_parameter_init(exmc_norsram_parameter_struct* exmc_norsram_ini } /*! - \brief consecutive clock configure - \param[in] clock_mode: specifie when the clock is generated - \arg EXMC_CLOCK_SYN_MODE: the clock is generated only during synchronous access - \arg EXMC_CLOCK_UNCONDITIONALLY: the clock is generated unconditionally + \brief initialize EXMC NOR/SRAM region + \param[in] exmc_norsram_parameter_struct: configure the EXMC NOR/SRAM parameter + norsram_region: EXMC_BANK0_NORSRAM_REGIONx, x=0..3 + write_mode: EXMC_ASYN_WRITE, EXMC_SYN_WRITE + extended_mode: ENABLE or DISABLE + asyn_wait: ENABLE or DISABLE + nwait_signal: ENABLE or DISABLE + memory_write: ENABLE or DISABLE + nwait_config: EXMC_NWAIT_CONFIG_BEFORE, EXMC_NWAIT_CONFIG_DURING + wrap_burst_mode: ENABLE or DISABLE + nwait_polarity: EXMC_NWAIT_POLARITY_LOW, EXMC_NWAIT_POLARITY_HIGH + burst_mode: ENABLE or DISABLE + databus_width: EXMC_NOR_DATABUS_WIDTH_8B, EXMC_NOR_DATABUS_WIDTH_16B + memory_type: EXMC_MEMORY_TYPE_SRAM, EXMC_MEMORY_TYPE_PSRAM, EXMC_MEMORY_TYPE_NOR + address_data_mux: ENABLE or DISABLE + read_write_timing: struct exmc_norsram_timing_parameter_struct set the time + asyn_access_mode: EXMC_ACCESS_MODE_A, EXMC_ACCESS_MODE_B, EXMC_ACCESS_MODE_C, EXMC_ACCESS_MODE_D + syn_data_latency: EXMC_DATALAT_x_CLK, x=2..17 + syn_clk_division: EXMC_SYN_CLOCK_RATIO_x_CLK, x=2..16 + bus_latency: 0x0U~0xFU + asyn_data_setuptime: 0x01U~0xFFU + asyn_address_holdtime: 0x1U~0xFU + asyn_address_setuptime: 0x0U~0xFU + write_timing: struct exmc_norsram_timing_parameter_struct set the time + asyn_access_mode: EXMC_ACCESS_MODE_A, EXMC_ACCESS_MODE_B, EXMC_ACCESS_MODE_C, EXMC_ACCESS_MODE_D + syn_data_latency: EXMC_DATALAT_x_CLK, x=2..17 + syn_clk_division: EXMC_SYN_CLOCK_RATIO_x_CLK, x=2..16 + bus_latency: 0x0U~0xFU + asyn_data_setuptime: 0x01U~0xFFU + asyn_address_holdtime: 0x1U~0xFU + asyn_address_setuptime: 0x0U~0xFU \param[out] none \retval none */ -void exmc_norsram_consecutive_clock_config(uint32_t clock_mode) +void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct) { - if (EXMC_CLOCK_UNCONDITIONALLY == clock_mode){ - EXMC_SNCTL(EXMC_BANK0_NORSRAM_REGION0) |= EXMC_CLOCK_UNCONDITIONALLY; - }else{ - EXMC_SNCTL(EXMC_BANK0_NORSRAM_REGION0) &= ~EXMC_CLOCK_UNCONDITIONALLY; + uint32_t snctl = 0x00000000U,sntcfg = 0x00000000U,snwtcfg = 0x00000000U; + + /* get the register value */ + snctl = EXMC_SNCTL(exmc_norsram_init_struct->norsram_region); + + /* clear relative bits */ + snctl &= ((uint32_t)~(EXMC_SNCTL_NREN | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_SBRSTEN | + EXMC_SNCTL_NRWTPOL | EXMC_SNCTL_WRAPEN | EXMC_SNCTL_NRWTCFG | EXMC_SNCTL_WREN | + EXMC_SNCTL_NRWTEN | EXMC_SNCTL_EXMODEN | EXMC_SNCTL_ASYNCWAIT | EXMC_SNCTL_SYNCWR | + EXMC_SNCTL_NRMUX )); + + snctl |= (uint32_t)(exmc_norsram_init_struct->address_data_mux << SNCTL_NRMUX_OFFSET) | + exmc_norsram_init_struct->memory_type | + exmc_norsram_init_struct->databus_width | + (exmc_norsram_init_struct->burst_mode << SNCTL_SBRSTEN_OFFSET) | + exmc_norsram_init_struct->nwait_polarity | + (exmc_norsram_init_struct->wrap_burst_mode << SNCTL_WRAPEN_OFFSET) | + exmc_norsram_init_struct->nwait_config | + (exmc_norsram_init_struct->memory_write << SNCTL_WREN_OFFSET) | + (exmc_norsram_init_struct->nwait_signal << SNCTL_NRWTEN_OFFSET) | + (exmc_norsram_init_struct->extended_mode << SNCTL_EXMODEN_OFFSET) | + (exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET) | + exmc_norsram_init_struct->write_mode; + + sntcfg = (uint32_t)exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime | + (exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime << SNTCFG_AHLD_OFFSET) | + (exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime << SNTCFG_DSET_OFFSET) | + (exmc_norsram_init_struct->read_write_timing->bus_latency << SNTCFG_BUSLAT_OFFSET) | + exmc_norsram_init_struct->read_write_timing->syn_clk_division | + exmc_norsram_init_struct->read_write_timing->syn_data_latency | + exmc_norsram_init_struct->read_write_timing->asyn_access_mode; + + /* nor flash access enable */ + if(EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type){ + snctl |= (uint32_t)EXMC_SNCTL_NREN; } -} -/*! - \brief CRAM page size configure - \param[in] page_size: CRAM page size - \arg EXMC_CRAM_AUTO_SPLIT: the clock is generated only during synchronous access - \arg EXMC_CRAM_PAGE_SIZE_128_BYTES: page size is 128 bytes - \arg EXMC_CRAM_PAGE_SIZE_256_BYTES: page size is 256 bytes - \arg EXMC_CRAM_PAGE_SIZE_512_BYTES: page size is 512 bytes - \arg EXMC_CRAM_PAGE_SIZE_1024_BYTES: page size is 1024 bytes - \param[out] none - \retval none -*/ -void exmc_norsram_page_size_config(uint32_t page_size) -{ - /* reset the bits */ - EXMC_SNCTL(EXMC_BANK0_NORSRAM_REGION0) &= ~EXMC_SNCTL_CPS; + /* extended mode configure */ + if(ENABLE == exmc_norsram_init_struct->extended_mode){ + snwtcfg = (uint32_t)exmc_norsram_init_struct->write_timing->asyn_address_setuptime | + (exmc_norsram_init_struct->write_timing->asyn_address_holdtime << SNTCFG_AHLD_OFFSET )| + (exmc_norsram_init_struct->write_timing->asyn_data_setuptime << SNTCFG_DSET_OFFSET) | + (exmc_norsram_init_struct->write_timing->bus_latency << SNTCFG_BUSLAT_OFFSET) | + exmc_norsram_init_struct->write_timing->asyn_access_mode; + }else{ + snwtcfg = BANK0_SNWTCFG_RESET; + } - /* set the CPS bits */ - EXMC_SNCTL(EXMC_BANK0_NORSRAM_REGION0) |= page_size; + /* configure the registers */ + EXMC_SNCTL(exmc_norsram_init_struct->norsram_region) = snctl; + EXMC_SNTCFG(exmc_norsram_init_struct->norsram_region) = sntcfg; + EXMC_SNWTCFG(exmc_norsram_init_struct->norsram_region) = snwtcfg; } /*! \brief enable EXMC NOR/PSRAM bank region \param[in] exmc_norsram_region: specifie the region of NOR/PSRAM bank + only one parameter can be selected which is shown as below: \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) \param[out] none \retval none @@ -286,6 +286,7 @@ void exmc_norsram_enable(uint32_t exmc_norsram_region) /*! \brief disable EXMC NOR/PSRAM bank region \param[in] exmc_norsram_region: specifie the region of NOR/PSRAM Bank + only one parameter can be selected which is shown as below: \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) \param[out] none \retval none @@ -298,6 +299,7 @@ void exmc_norsram_disable(uint32_t exmc_norsram_region) /*! \brief deinitialize EXMC NAND bank \param[in] exmc_nand_bank: select the bank of NAND + only one parameter can be selected which is shown as below: \arg EXMC_BANKx_NAND(x=1..2) \param[out] none \retval none @@ -311,6 +313,32 @@ void exmc_nand_deinit(uint32_t exmc_nand_bank) EXMC_NPATCFG(exmc_nand_bank) = BANK1_2_NPATCFG_RESET; } +/*! + \brief initialize exmc_norsram_parameter_struct with the default values + \param[in] none + \param[out] the initialized struct exmc_norsram_parameter_struct pointer + \retval none +*/ +void exmc_nand_struct_para_init(exmc_nand_parameter_struct* exmc_nand_init_struct) +{ + /* configure the structure with default values */ + exmc_nand_init_struct->nand_bank = EXMC_BANK1_NAND; + exmc_nand_init_struct->wait_feature = DISABLE; + exmc_nand_init_struct->databus_width = EXMC_NAND_DATABUS_WIDTH_8B; + exmc_nand_init_struct->ecc_logic = DISABLE; + exmc_nand_init_struct->ecc_size = EXMC_ECC_SIZE_256BYTES; + exmc_nand_init_struct->ctr_latency = 0x0U; + exmc_nand_init_struct->atr_latency = 0x0U; + exmc_nand_init_struct->common_space_timing->setuptime = 0xFCU; + exmc_nand_init_struct->common_space_timing->waittime = 0xFCU; + exmc_nand_init_struct->common_space_timing->holdtime = 0xFCU; + exmc_nand_init_struct->common_space_timing->databus_hiztime = 0xFCU; + exmc_nand_init_struct->attribute_space_timing->setuptime = 0xFCU; + exmc_nand_init_struct->attribute_space_timing->waittime = 0xFCU; + exmc_nand_init_struct->attribute_space_timing->holdtime = 0xFCU; + exmc_nand_init_struct->attribute_space_timing->databus_hiztime = 0xFCU; +} + /*! \brief initialize EXMC NAND bank \param[in] exmc_nand_parameter_struct: configure the EXMC NAND parameter @@ -322,14 +350,22 @@ void exmc_nand_deinit(uint32_t exmc_nand_bank) databus_width: EXMC_NAND_DATABUS_WIDTH_8B,EXMC_NAND_DATABUS_WIDTH_16B wait_feature: ENABLE or DISABLE common_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time + databus_hiztime: 0x01U~0xFFU + holdtime: 0x01U~0xFEU + waittime: 0x02U~0xFFU + setuptime: 0x01U~0xFFU attribute_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time + databus_hiztime: 0x00U~0xFEU + holdtime: 0x01U~0xFEU + waittime: 0x02U~0xFFU + setuptime: 0x01U~0xFFU \param[out] none \retval none */ void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct) { uint32_t npctl = 0x00000000U, npctcfg = 0x00000000U, npatcfg = 0x00000000U; - + npctl = (uint32_t)(exmc_nand_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET)| EXMC_NPCTL_NDTP | exmc_nand_init_struct->databus_width | @@ -338,15 +374,15 @@ void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct) exmc_nand_init_struct->ctr_latency | exmc_nand_init_struct->atr_latency; - npctcfg = (uint32_t)(exmc_nand_init_struct->common_space_timing->setuptime - 1U) | - ((exmc_nand_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) | - (exmc_nand_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET)| - ((exmc_nand_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET); + npctcfg = (uint32_t)((exmc_nand_init_struct->common_space_timing->setuptime - 1U) & EXMC_NPCTCFG_COMSET ) | + (((exmc_nand_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT ) | + ((exmc_nand_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD ) | + (((exmc_nand_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ ); - npatcfg = (uint32_t)(exmc_nand_init_struct->attribute_space_timing->setuptime - 1U) | - ((exmc_nand_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_COMWAIT_OFFSET) | - (exmc_nand_init_struct->attribute_space_timing->holdtime << NPATCFG_COMHLD_OFFSET)| - (exmc_nand_init_struct->attribute_space_timing->databus_hiztime << NPATCFG_COMHIZ_OFFSET); + npatcfg = (uint32_t)((exmc_nand_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET ) | + (((exmc_nand_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT ) | + ((exmc_nand_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD ) | + ((exmc_nand_init_struct->attribute_space_timing->databus_hiztime << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ ); /* EXMC_BANK1_NAND or EXMC_BANK2_NAND initialize */ EXMC_NPCTL(exmc_nand_init_struct->nand_bank) = npctl; @@ -354,35 +390,10 @@ void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct) EXMC_NPATCFG(exmc_nand_init_struct->nand_bank) = npatcfg; } -/*! - \brief initialize the struct exmc_norsram_parameter_struct - \param[in] none - \param[out] the initialized struct exmc_norsram_parameter_struct pointer - \retval none -*/ -void exmc_nand_parameter_init(exmc_nand_parameter_struct* exmc_nand_init_struct) -{ - /* configure the structure with default value */ - exmc_nand_init_struct->nand_bank = EXMC_BANK1_NAND; - exmc_nand_init_struct->wait_feature = DISABLE; - exmc_nand_init_struct->databus_width = EXMC_NAND_DATABUS_WIDTH_8B; - exmc_nand_init_struct->ecc_logic = DISABLE; - exmc_nand_init_struct->ecc_size = EXMC_ECC_SIZE_256BYTES; - exmc_nand_init_struct->ctr_latency = 0x0U; - exmc_nand_init_struct->atr_latency = 0x0U; - exmc_nand_init_struct->common_space_timing->setuptime = 0xfcU; - exmc_nand_init_struct->common_space_timing->waittime = 0xfcU; - exmc_nand_init_struct->common_space_timing->holdtime = 0xfcU; - exmc_nand_init_struct->common_space_timing->databus_hiztime = 0xfcU; - exmc_nand_init_struct->attribute_space_timing->setuptime = 0xfcU; - exmc_nand_init_struct->attribute_space_timing->waittime = 0xfcU; - exmc_nand_init_struct->attribute_space_timing->holdtime = 0xfcU; - exmc_nand_init_struct->attribute_space_timing->databus_hiztime = 0xfcU; -} - /*! \brief enable NAND bank \param[in] exmc_nand_bank: specifie the NAND bank + only one parameter can be selected which is shown as below: \arg EXMC_BANKx_NAND(x=1,2) \param[out] none \retval none @@ -395,6 +406,7 @@ void exmc_nand_enable(uint32_t exmc_nand_bank) /*! \brief disable NAND bank \param[in] exmc_nand_bank: specifie the NAND bank + only one parameter can be selected which is shown as below: \arg EXMC_BANKx_NAND(x=1,2) \param[out] none \retval none @@ -404,40 +416,6 @@ void exmc_nand_disable(uint32_t exmc_nand_bank) EXMC_NPCTL(exmc_nand_bank) &= ~EXMC_NPCTL_NDBKEN; } -/*! - \brief enable or disable the EXMC NAND ECC function - \param[in] exmc_nand_bank: specifie the NAND bank - \arg EXMC_BANKx_NAND(x=1,2) - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void exmc_nand_ecc_config(uint32_t exmc_nand_bank, ControlStatus newvalue) -{ - if (ENABLE == newvalue) - { - /* enable the selected NAND bank ECC function */ - EXMC_NPCTL(exmc_nand_bank) |= EXMC_NPCTL_ECCEN; - } - else - { - /* disable the selected NAND bank ECC function */ - EXMC_NPCTL(exmc_nand_bank) &= ~EXMC_NPCTL_ECCEN; - } -} - -/*! - \brief get the EXMC ECC value - \param[in] exmc_nand_bank: specifie the NAND bank - \arg EXMC_BANKx_NAND(x=1,2) - \param[out] none - \retval the error correction code(ECC) value -*/ -uint32_t exmc_ecc_get(uint32_t exmc_nand_bank) -{ - return(EXMC_NECC(exmc_nand_bank)); -} - /*! \brief deinitialize EXMC PC card bank \param[in] none @@ -455,53 +433,14 @@ void exmc_pccard_deinit(void) } /*! - \brief initialize EXMC PC card bank - \param[in] exmc_pccard_parameter_struct: configure the EXMC NAND parameter - atr_latency: EXMC_ALE_RE_DELAY_x_HCLK,x=1..16 - ctr_latency: EXMC_CLE_RE_DELAY_x_HCLK,x=1..16 - wait_feature: ENABLE or DISABLE - common_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time - attribute_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time - io_space_timing: exmc_nand_pccard_timing_parameter_struct set the time - \param[out] none - \retval none -*/ -void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct) -{ - /* configure the EXMC bank3 PC card control register */ - EXMC_NPCTL3 = (uint32_t)(exmc_pccard_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET) | - EXMC_NAND_DATABUS_WIDTH_16B | - exmc_pccard_init_struct->ctr_latency | - exmc_pccard_init_struct->atr_latency ; - - /* configure the EXMC bank3 PC card common space timing configuration register */ - EXMC_NPCTCFG3 = (uint32_t)(exmc_pccard_init_struct->common_space_timing->setuptime - 1U) | - ((exmc_pccard_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) | - (exmc_pccard_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET)| - ((exmc_pccard_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET); - - /* configure the EXMC bank3 PC card attribute space timing configuration register */ - EXMC_NPATCFG3 = (uint32_t)(exmc_pccard_init_struct->attribute_space_timing->setuptime - 1U) | - ((exmc_pccard_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_COMWAIT_OFFSET) | - (exmc_pccard_init_struct->attribute_space_timing->holdtime << NPATCFG_COMHLD_OFFSET)| - (exmc_pccard_init_struct->attribute_space_timing->databus_hiztime << NPATCFG_COMHIZ_OFFSET); - - /* configure the EXMC bank3 PC card io space timing configuration register */ - EXMC_PIOTCFG3 = (uint32_t)(exmc_pccard_init_struct->io_space_timing->setuptime - 1U) | - ((exmc_pccard_init_struct->io_space_timing->waittime - 1U) << PIOTCFG_COMWAIT_OFFSET) | - (exmc_pccard_init_struct->io_space_timing->holdtime << PIOTCFG_COMHLD_OFFSET)| - (exmc_pccard_init_struct->io_space_timing->databus_hiztime << PIOTCFG_COMHIZ_OFFSET); -} - -/*! - \brief initialize the struct exmc_pccard_parameter_struct + \brief initialize exmc_pccard_parameter_struct with the default values \param[in] none \param[out] the initialized struct exmc_pccard_parameter_struct pointer \retval none */ -void exmc_pccard_parameter_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct) +void exmc_pccard_struct_para_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct) { - /* configure the structure with default value */ + /* configure the structure with default values */ exmc_pccard_init_struct->wait_feature = DISABLE; exmc_pccard_init_struct->ctr_latency = 0x0U; exmc_pccard_init_struct->atr_latency = 0x0U; @@ -519,6 +458,57 @@ void exmc_pccard_parameter_init(exmc_pccard_parameter_struct* exmc_pccard_init_s exmc_pccard_init_struct->io_space_timing->databus_hiztime = 0xFCU; } +/*! + \brief initialize EXMC PC card bank + \param[in] exmc_pccard_parameter_struct: configure the EXMC NAND parameter + atr_latency: EXMC_ALE_RE_DELAY_x_HCLK,x=1..16 + ctr_latency: EXMC_CLE_RE_DELAY_x_HCLK,x=1..16 + wait_feature: ENABLE or DISABLE + common_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time + databus_hiztime: 0x01U~0xFFU + holdtime: 0x01U~0xFEU + waittime: 0x02U~0xFFU + setuptime: 0x01U~0xFFU + attribute_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time + databus_hiztime: 0x00U~0xFEU + holdtime: 0x01U~0xFEU + waittime: 0x02U~0xFFU + setuptime: 0x01U~0xFFU + io_space_timing: exmc_nand_pccard_timing_parameter_struct set the time + databus_hiztime: 0x00U~0xFFU + holdtime: 0x01U~0xFFU + waittime: 0x02U~0x100U + setuptime: 0x01U~0x100U + \param[out] none + \retval none +*/ +void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct) +{ + /* configure the EXMC bank3 PC card control register */ + EXMC_NPCTL3 = (uint32_t)(exmc_pccard_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET) | + EXMC_NAND_DATABUS_WIDTH_16B | + exmc_pccard_init_struct->ctr_latency | + exmc_pccard_init_struct->atr_latency ; + + /* configure the EXMC bank3 PC card common space timing configuration register */ + EXMC_NPCTCFG3 = (uint32_t)((exmc_pccard_init_struct->common_space_timing->setuptime - 1U) & EXMC_NPCTCFG_COMSET ) | + (((exmc_pccard_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT ) | + ((exmc_pccard_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD ) | + (((exmc_pccard_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ ); + + /* configure the EXMC bank3 PC card attribute space timing configuration register */ + EXMC_NPATCFG3 = (uint32_t)((exmc_pccard_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET ) | + (((exmc_pccard_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT ) | + ((exmc_pccard_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD ) | + ((exmc_pccard_init_struct->attribute_space_timing->databus_hiztime << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ); + + /* configure the EXMC bank3 PC card io space timing configuration register */ + EXMC_PIOTCFG3 = (uint32_t)((exmc_pccard_init_struct->io_space_timing->setuptime - 1U) & EXMC_PIOTCFG3_IOSET ) | + (((exmc_pccard_init_struct->io_space_timing->waittime - 1U) << PIOTCFG_IOWAIT_OFFSET) & EXMC_PIOTCFG3_IOWAIT ) | + ((exmc_pccard_init_struct->io_space_timing->holdtime << PIOTCFG_IOHLD_OFFSET) & EXMC_PIOTCFG3_IOHLD ) | + ((exmc_pccard_init_struct->io_space_timing->databus_hiztime << PIOTCFG_IOHIZ_OFFSET) & EXMC_PIOTCFG3_IOHIZ ); +} + /*! \brief enable PC Card Bank \param[in] none @@ -543,6 +533,9 @@ void exmc_pccard_disable(void) /*! \brief deinitialize EXMC SDRAM device + \param[in] exmc_sdram_device: select the SRAM device + only one parameter can be selected which is shown as below: + \arg EXMC_SDRAM_DEVICEx(x=0, 1) \param[in] none \param[out] none \retval none @@ -558,93 +551,14 @@ void exmc_sdram_deinit(uint32_t exmc_sdram_device) } /*! - \brief initialize EXMC SDRAM device - \param[in] exmc_sdram_parameter_struct: configure the EXMC SDRAM parameter - sdram_device: EXMC_SDRAM_DEVICE0,EXMC_SDRAM_DEVICE1 - pipeline_read_delay: EXMC_PIPELINE_DELAY_x_HCLK,x=0..2 - brust_read_switch: ENABLE or DISABLE - sdclock_config: EXMC_SDCLK_DISABLE,EXMC_SDCLK_PERIODS_2_HCLK,EXMC_SDCLK_PERIODS_3_HCLK - write_protection: ENABLE or DISABLE - cas_latency: EXMC_CAS_LATENCY_x_SDCLK,x=1..3 - internal_bank_number: EXMC_SDRAM_2_INTER_BANK,EXMC_SDRAM_4_INTER_BANK - data_width: EXMC_SDRAM_DATABUS_WIDTH_8B,EXMC_SDRAM_DATABUS_WIDTH_16B,EXMC_SDRAM_DATABUS_WIDTH_32B - row_address_width: EXMC_SDRAM_ROW_ADDRESS_x,x=11..13 - column_address_width: EXMC_SDRAM_COW_ADDRESS_x,x=8..11 - timing: exmc_sdram_timing_parameter_struct set the time - \param[out] none - \retval none -*/ -void exmc_sdram_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct) -{ - uint32_t sdctl0, sdctl1, sdtcfg0, sdtcfg1; - - /* configuration EXMC_SDCTL0 or EXMC_SDCTL1 */ - if(EXMC_SDRAM_DEVICE0 == exmc_sdram_init_struct->sdram_device){ - /* configuration EXMC_SDCTL0 */ - EXMC_SDCTL(EXMC_SDRAM_DEVICE0) = (uint32_t)exmc_sdram_init_struct->column_address_width | - exmc_sdram_init_struct->row_address_width | - exmc_sdram_init_struct->data_width | - exmc_sdram_init_struct->internal_bank_number | - exmc_sdram_init_struct->cas_latency | - (exmc_sdram_init_struct->write_protection << SDCTL_WPEN_OFFSET)| - exmc_sdram_init_struct->sdclock_config | - (exmc_sdram_init_struct->brust_read_switch << SDCTL_BRSTRD_OFFSET)| - exmc_sdram_init_struct->pipeline_read_delay; - - /* configuration EXMC_SDTCFG0 */ - EXMC_SDTCFG(EXMC_SDRAM_DEVICE0) = (uint32_t)((exmc_sdram_init_struct->timing->load_mode_register_delay)-1U) | - (((exmc_sdram_init_struct->timing->exit_selfrefresh_delay)-1U) << SDTCFG_XSRD_OFFSET) | - (((exmc_sdram_init_struct->timing->row_address_select_delay)-1U) << SDTCFG_RASD_OFFSET) | - (((exmc_sdram_init_struct->timing->auto_refresh_delay)-1U) << SDTCFG_ARFD_OFFSET) | - (((exmc_sdram_init_struct->timing->write_recovery_delay)-1U) << SDTCFG_WRD_OFFSET) | - (((exmc_sdram_init_struct->timing->row_precharge_delay)-1U) << SDTCFG_RPD_OFFSET) | - (((exmc_sdram_init_struct->timing->row_to_column_delay)-1U) << SDTCFG_RCD_OFFSET); - }else{ - /* configuration EXMC_SDCTL0 and EXMC_SDCTL1 */ - /* some bits in the EXMC_SDCTL1 register are reserved */ - sdctl0 = EXMC_SDCTL(EXMC_SDRAM_DEVICE0) & (~( EXMC_SDCTL_PIPED | EXMC_SDCTL_BRSTRD | EXMC_SDCTL_SDCLK )); - - sdctl0 |= (uint32_t)exmc_sdram_init_struct->sdclock_config | - exmc_sdram_init_struct->brust_read_switch | - exmc_sdram_init_struct->pipeline_read_delay; - - sdctl1 = (uint32_t)exmc_sdram_init_struct->column_address_width | - exmc_sdram_init_struct->row_address_width | - exmc_sdram_init_struct->data_width | - exmc_sdram_init_struct->internal_bank_number | - exmc_sdram_init_struct->cas_latency | - exmc_sdram_init_struct->write_protection ; - - EXMC_SDCTL(EXMC_SDRAM_DEVICE0) = sdctl0; - EXMC_SDCTL(EXMC_SDRAM_DEVICE1) = sdctl1; - - /* configuration EXMC_SDTCFG0 and EXMC_SDTCFG1 */ - /* some bits in the EXMC_SDTCFG1 register are reserved */ - sdtcfg0 = EXMC_SDTCFG(EXMC_SDRAM_DEVICE0) & (~(EXMC_SDTCFG_RPD | EXMC_SDTCFG_WRD | EXMC_SDTCFG_ARFD)); - - sdtcfg0 |= (uint32_t)(((exmc_sdram_init_struct->timing->auto_refresh_delay)-1U) << SDTCFG_ARFD_OFFSET) | - (((exmc_sdram_init_struct->timing->row_precharge_delay)-1U) << SDTCFG_RPD_OFFSET) | - (((exmc_sdram_init_struct->timing->write_recovery_delay)-1U) << SDTCFG_WRD_OFFSET); - - sdtcfg1 = (uint32_t)((exmc_sdram_init_struct->timing->load_mode_register_delay)-1U) | - (((exmc_sdram_init_struct->timing->exit_selfrefresh_delay)-1U) << SDTCFG_XSRD_OFFSET) | - (((exmc_sdram_init_struct->timing->row_address_select_delay)-1U) << SDTCFG_RASD_OFFSET) | - (((exmc_sdram_init_struct->timing->row_to_column_delay)-1U) << SDTCFG_RCD_OFFSET); - - EXMC_SDTCFG(EXMC_SDRAM_DEVICE0) = sdtcfg0; - EXMC_SDTCFG(EXMC_SDRAM_DEVICE1) = sdtcfg1; - } -} - -/*! - \brief initialize the struct exmc_pccard_parameter_struct + \brief initialize exmc_sdram_parameter_struct with the default values \param[in] none \param[out] the initialized struct exmc_pccard_parameter_struct pointer \retval none */ -void exmc_sdram_parameter_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct) +void exmc_sdram_struct_para_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct) { - /* configure the structure with default value */ + /* configure the structure with default values */ exmc_sdram_init_struct->sdram_device = EXMC_SDRAM_DEVICE0; exmc_sdram_init_struct->column_address_width = EXMC_SDRAM_COW_ADDRESS_8; exmc_sdram_init_struct->row_address_width = EXMC_SDRAM_ROW_ADDRESS_11; @@ -666,118 +580,88 @@ void exmc_sdram_parameter_init(exmc_sdram_parameter_struct* exmc_sdram_init_stru } /*! - \brief configure the SDRAM memory command - \param[in] the struct exmc_sdram_command_parameter_struct pointer + \brief initialize EXMC SDRAM device + \param[in] exmc_sdram_parameter_struct: configure the EXMC SDRAM parameter + sdram_device: EXMC_SDRAM_DEVICE0,EXMC_SDRAM_DEVICE1 + pipeline_read_delay: EXMC_PIPELINE_DELAY_x_HCLK,x=0..2 + brust_read_switch: ENABLE or DISABLE + sdclock_config: EXMC_SDCLK_DISABLE,EXMC_SDCLK_PERIODS_2_HCLK,EXMC_SDCLK_PERIODS_3_HCLK + write_protection: ENABLE or DISABLE + cas_latency: EXMC_CAS_LATENCY_x_SDCLK,x=1..3 + internal_bank_number: EXMC_SDRAM_2_INTER_BANK,EXMC_SDRAM_4_INTER_BANK + data_width: EXMC_SDRAM_DATABUS_WIDTH_8B,EXMC_SDRAM_DATABUS_WIDTH_16B,EXMC_SDRAM_DATABUS_WIDTH_32B + row_address_width: EXMC_SDRAM_ROW_ADDRESS_x,x=11..13 + column_address_width: EXMC_SDRAM_COW_ADDRESS_x,x=8..11 + timing: exmc_sdram_timing_parameter_struct set the time + row_to_column_delay: 1U~16U + row_precharge_delay: 1U~16U + write_recovery_delay: 1U~16U + auto_refresh_delay: 1U~16U + row_address_select_delay: 1U~16U + exit_selfrefresh_delay: 1U~16U + load_mode_register_delay: 1U~16U \param[out] none \retval none */ -void exmc_sdram_command_config(exmc_sdram_command_parameter_struct* exmc_sdram_command_init_struct) +void exmc_sdram_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct) { - /* configure command register */ - EXMC_SDCMD = (uint32_t)((exmc_sdram_command_init_struct->command) | - (exmc_sdram_command_init_struct->bank_select) | - ((exmc_sdram_command_init_struct->auto_refresh_number)) | - ((exmc_sdram_command_init_struct->mode_register_content)<sdram_device){ + /* configuration EXMC_SDCTL0 */ + EXMC_SDCTL(EXMC_SDRAM_DEVICE0) = (uint32_t)exmc_sdram_init_struct->column_address_width | + exmc_sdram_init_struct->row_address_width | + exmc_sdram_init_struct->data_width | + exmc_sdram_init_struct->internal_bank_number | + exmc_sdram_init_struct->cas_latency | + (exmc_sdram_init_struct->write_protection << SDCTL_WPEN_OFFSET)| + exmc_sdram_init_struct->sdclock_config | + (exmc_sdram_init_struct->brust_read_switch << SDCTL_BRSTRD_OFFSET)| + exmc_sdram_init_struct->pipeline_read_delay; -/*! - \brief set the number of successive auto-refresh command - \param[in] exmc_number: the number SDRAM clock cycles unit between two successive auto-refresh commands - \param[out] none - \retval none -*/ -void exmc_sdram_autorefresh_number_set(uint32_t exmc_number) -{ - uint32_t sdcmd; - sdcmd = EXMC_SDCMD & (~EXMC_SDCMD_NARF); - EXMC_SDCMD = sdcmd | (uint32_t)((exmc_number << SDCMD_NARF_OFFSET) & EXMC_SDCMD_NARF) ; -} - -/*! - \brief config the write protection function - \param[in] exmc_sdram_device: specifie the SDRAM device - \arg EXMC_SDRAM_DEVICEx(x=0,1) - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void exmc_sdram_write_protection_config(uint32_t exmc_sdram_device, ControlStatus newvalue) -{ - if (ENABLE == newvalue){ - EXMC_SDCTL(exmc_sdram_device) |= (uint32_t)EXMC_SDCTL_WPEN; + /* configuration EXMC_SDTCFG0 */ + EXMC_SDTCFG(EXMC_SDRAM_DEVICE0) = (uint32_t)((exmc_sdram_init_struct->timing->load_mode_register_delay)-1U) | + (((exmc_sdram_init_struct->timing->exit_selfrefresh_delay)-1U) << SDTCFG_XSRD_OFFSET) | + (((exmc_sdram_init_struct->timing->row_address_select_delay)-1U) << SDTCFG_RASD_OFFSET) | + (((exmc_sdram_init_struct->timing->auto_refresh_delay)-1U) << SDTCFG_ARFD_OFFSET) | + (((exmc_sdram_init_struct->timing->write_recovery_delay)-1U) << SDTCFG_WRD_OFFSET) | + (((exmc_sdram_init_struct->timing->row_precharge_delay)-1U) << SDTCFG_RPD_OFFSET) | + (((exmc_sdram_init_struct->timing->row_to_column_delay)-1U) << SDTCFG_RCD_OFFSET); }else{ - EXMC_SDCTL(exmc_sdram_device) &= ~((uint32_t)EXMC_SDCTL_WPEN); - } + /* configuration EXMC_SDCTL0 and EXMC_SDCTL1 */ + /* some bits in the EXMC_SDCTL1 register are reserved */ + sdctl0 = EXMC_SDCTL(EXMC_SDRAM_DEVICE0) & (~( EXMC_SDCTL_PIPED | EXMC_SDCTL_BRSTRD | EXMC_SDCTL_SDCLK )); -} + sdctl0 |= (uint32_t)exmc_sdram_init_struct->sdclock_config | + exmc_sdram_init_struct->brust_read_switch | + exmc_sdram_init_struct->pipeline_read_delay; -/*! - \brief get the status of SDRAM device0 or device1 - \param[in] exmc_sdram_device: specifie the SDRAM device - \arg EXMC_SDRAM_DEVICEx(x=0,1) - \param[out] none - \retval the status of SDRAM device -*/ -uint32_t exmc_sdram_bankstatus_get(uint32_t exmc_sdram_device) -{ - uint32_t sdstat = 0U; + sdctl1 = (uint32_t)exmc_sdram_init_struct->column_address_width | + exmc_sdram_init_struct->row_address_width | + exmc_sdram_init_struct->data_width | + exmc_sdram_init_struct->internal_bank_number | + exmc_sdram_init_struct->cas_latency | + exmc_sdram_init_struct->write_protection ; - if(EXMC_SDRAM_DEVICE0 == exmc_sdram_device) - { - sdstat = ((uint32_t)(EXMC_SDSTAT & EXMC_SDSDAT_STA0) >> SDSTAT_STA0_OFFSET); - } - else - { - sdstat = ((uint32_t)(EXMC_SDSTAT & EXMC_SDSDAT_STA1) >> SDSTAT_STA1_OFFSET); - } + EXMC_SDCTL(EXMC_SDRAM_DEVICE0) = sdctl0; + EXMC_SDCTL(EXMC_SDRAM_DEVICE1) = sdctl1; - return sdstat; -} + /* configuration EXMC_SDTCFG0 and EXMC_SDTCFG1 */ + /* some bits in the EXMC_SDTCFG1 register are reserved */ + sdtcfg0 = EXMC_SDTCFG(EXMC_SDRAM_DEVICE0) & (~(EXMC_SDTCFG_RPD | EXMC_SDTCFG_WRD | EXMC_SDTCFG_ARFD)); -/*! - \brief configure the delayed sample clock of read data - \param[in] delay_cell: SDRAM the delayed sample clock of read data - \arg EXMC_SDRAM_x_DELAY_CELL(x=0..15) - \param[in] extra_hclk: sample cycle of read data - \arg EXMC_SDRAM_READSAMPLE_x_EXTRAHCLK(x=0,1) - \param[out] none - \retval none -*/ -void exmc_sdram_readsample_config(uint32_t delay_cell, uint32_t extra_hclk) -{ - uint32_t sdrsctl = 0U; - - sdrsctl = EXMC_SDRSCTL & (~(EXMC_SDRSCTL_SDSC | EXMC_SDRSCTL_SSCR)); - sdrsctl |= (uint32_t)(delay_cell & EXMC_SDRSCTL_SDSC) | - ((extra_hclk << SDRSCTL_SSCR_OFFSET) & EXMC_SDRSCTL_SSCR); - EXMC_SDRSCTL = sdrsctl; -} + sdtcfg0 |= (uint32_t)(((exmc_sdram_init_struct->timing->auto_refresh_delay)-1U) << SDTCFG_ARFD_OFFSET) | + (((exmc_sdram_init_struct->timing->row_precharge_delay)-1U) << SDTCFG_RPD_OFFSET) | + (((exmc_sdram_init_struct->timing->write_recovery_delay)-1U) << SDTCFG_WRD_OFFSET); -/*! - \brief enable or disable read sample - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void exmc_sdram_readsample_enable(ControlStatus newvalue) -{ - if (ENABLE == newvalue){ - EXMC_SDRSCTL |= EXMC_SDRSCTL_RSEN; - }else{ - EXMC_SDRSCTL &= (uint32_t)(~EXMC_SDRSCTL_RSEN); + sdtcfg1 = (uint32_t)((exmc_sdram_init_struct->timing->load_mode_register_delay)-1U) | + (((exmc_sdram_init_struct->timing->exit_selfrefresh_delay)-1U) << SDTCFG_XSRD_OFFSET) | + (((exmc_sdram_init_struct->timing->row_address_select_delay)-1U) << SDTCFG_RASD_OFFSET) | + (((exmc_sdram_init_struct->timing->row_to_column_delay)-1U) << SDTCFG_RCD_OFFSET); + + EXMC_SDTCFG(EXMC_SDRAM_DEVICE0) = sdtcfg0; + EXMC_SDTCFG(EXMC_SDRAM_DEVICE1) = sdtcfg1; } } @@ -797,10 +681,25 @@ void exmc_sqpipsram_deinit(void) EXMC_SIDH = BANK0_SQPI_SIDH_RESET; } +/*! + \brief initialize exmc_sqpipsram_parameter_struct with the default values + \param[in] the struct exmc_sqpipsram_parameter_struct pointer + \param[out] none + \retval none +*/ +void exmc_sqpipsram_struct_para_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_struct) +{ + /* configure the structure with default values */ + exmc_sqpipsram_init_struct->sample_polarity = EXMC_SQPIPSRAM_SAMPLE_RISING_EDGE; + exmc_sqpipsram_init_struct->id_length = EXMC_SQPIPSRAM_ID_LENGTH_64B; + exmc_sqpipsram_init_struct->address_bits = EXMC_SQPIPSRAM_ADDR_LENGTH_24B; + exmc_sqpipsram_init_struct->command_bits = EXMC_SQPIPSRAM_COMMAND_LENGTH_8B; +} + /*! \brief initialize EXMC SQPIPSRAM \param[in] exmc_sqpipsram_parameter_struct: configure the EXMC SQPIPSRAM parameter - sample_polarity: EXMC_SDRAM_SAMPLE_RISING_EDGE,EXMC_SDRAM_SAMPLE_FALLING_EDGE + sample_polarity: EXMC_SQPIPSRAM_SAMPLE_RISING_EDGE,EXMC_SQPIPSRAM_SAMPLE_FALLING_EDGE id_length: EXMC_SQPIPSRAM_ID_LENGTH_xB,x=8,16,32,64 address_bits: EXMC_SQPIPSRAM_ADDR_LENGTH_xB,x=1..26 command_bits: EXMC_SQPIPSRAM_COMMAND_LENGTH_xB,x=4,8,16 @@ -817,23 +716,209 @@ void exmc_sqpipsram_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_st } /*! - \brief initialize the struct exmc_sqpipsram_parameter_struct - \param[in] the struct exmc_sqpipsram_parameter_struct pointer + \brief configure consecutive clock + \param[in] clock_mode: specifie when the clock is generated + only one parameter can be selected which is shown as below: + \arg EXMC_CLOCK_SYN_MODE: the clock is generated only during synchronous access + \arg EXMC_CLOCK_UNCONDITIONALLY: the clock is generated unconditionally \param[out] none \retval none */ -void exmc_sqpipsram_parameter_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_struct) +void exmc_norsram_consecutive_clock_config(uint32_t clock_mode) { - /* configure the structure with default value */ - exmc_sqpipsram_init_struct->sample_polarity = EXMC_SDRAM_SAMPLE_RISING_EDGE; - exmc_sqpipsram_init_struct->id_length = EXMC_SQPIPSRAM_ID_LENGTH_64B; - exmc_sqpipsram_init_struct->address_bits = EXMC_SQPIPSRAM_ADDR_LENGTH_24B; - exmc_sqpipsram_init_struct->command_bits = EXMC_SQPIPSRAM_COMMAND_LENGTH_8B; + if (EXMC_CLOCK_UNCONDITIONALLY == clock_mode){ + EXMC_SNCTL(EXMC_BANK0_NORSRAM_REGION0) |= EXMC_CLOCK_UNCONDITIONALLY; + }else{ + EXMC_SNCTL(EXMC_BANK0_NORSRAM_REGION0) &= ~EXMC_CLOCK_UNCONDITIONALLY; + } +} + +/*! + \brief configure CRAM page size + \param[in] exmc_norsram_region: select the region of bank0 + only one parameter can be selected which is shown as below: + \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) + \param[in] page_size: CRAM page size + only one parameter can be selected which is shown as below: + \arg EXMC_CRAM_AUTO_SPLIT: the clock is generated only during synchronous access + \arg EXMC_CRAM_PAGE_SIZE_128_BYTES: page size is 128 bytes + \arg EXMC_CRAM_PAGE_SIZE_256_BYTES: page size is 256 bytes + \arg EXMC_CRAM_PAGE_SIZE_512_BYTES: page size is 512 bytes + \arg EXMC_CRAM_PAGE_SIZE_1024_BYTES: page size is 1024 bytes + \param[out] none + \retval none +*/ +void exmc_norsram_page_size_config(uint32_t exmc_norsram_region, uint32_t page_size) +{ + /* reset the bits */ + EXMC_SNCTL(exmc_norsram_region) &= ~EXMC_SNCTL_CPS; + + /* set the CPS bits */ + EXMC_SNCTL(exmc_norsram_region) |= page_size; +} + +/*! + \brief enable or disable the EXMC NAND ECC function + \param[in] exmc_nand_bank: specifie the NAND bank + only one parameter can be selected which is shown as below: + \arg EXMC_BANKx_NAND(x=1,2) + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void exmc_nand_ecc_config(uint32_t exmc_nand_bank, ControlStatus newvalue) +{ + if (ENABLE == newvalue){ + /* enable the selected NAND bank ECC function */ + EXMC_NPCTL(exmc_nand_bank) |= EXMC_NPCTL_ECCEN; + }else{ + /* disable the selected NAND bank ECC function */ + EXMC_NPCTL(exmc_nand_bank) &= ~EXMC_NPCTL_ECCEN; + } +} + +/*! + \brief get the EXMC ECC value + \param[in] exmc_nand_bank: specifie the NAND bank + only one parameter can be selected which is shown as below: + \arg EXMC_BANKx_NAND(x=1,2) + \param[out] none + \retval the error correction code(ECC) value +*/ +uint32_t exmc_ecc_get(uint32_t exmc_nand_bank) +{ + return(EXMC_NECC(exmc_nand_bank)); +} + +/*! + \brief enable or disable read sample + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void exmc_sdram_readsample_enable(ControlStatus newvalue) +{ + if (ENABLE == newvalue){ + EXMC_SDRSCTL |= EXMC_SDRSCTL_RSEN; + }else{ + EXMC_SDRSCTL &= (uint32_t)(~EXMC_SDRSCTL_RSEN); + } +} + +/*! + \brief configure the delayed sample clock of read data + \param[in] delay_cell: SDRAM the delayed sample clock of read data + only one parameter can be selected which is shown as below: + \arg EXMC_SDRAM_x_DELAY_CELL(x=0..15) + \param[in] extra_hclk: sample cycle of read data + only one parameter can be selected which is shown as below: + \arg EXMC_SDRAM_READSAMPLE_x_EXTRAHCLK(x=0,1) + \param[out] none + \retval none +*/ +void exmc_sdram_readsample_config(uint32_t delay_cell, uint32_t extra_hclk) +{ + uint32_t sdrsctl = 0U; + + /* reset the bits */ + sdrsctl = EXMC_SDRSCTL & (~(EXMC_SDRSCTL_SDSC | EXMC_SDRSCTL_SSCR)); + /* set the bits */ + sdrsctl |= (uint32_t)(delay_cell & EXMC_SDRSCTL_SDSC) | + ((extra_hclk << SDRSCTL_SSCR_OFFSET) & EXMC_SDRSCTL_SSCR); + EXMC_SDRSCTL = sdrsctl; +} + +/*! + \brief configure the SDRAM memory command + \param[in] exmc_sdram_command_init_struct: initialize EXMC SDRAM command + mode_register_content: + auto_refresh_number: EXMC_SDRAM_AUTO_REFLESH_x_SDCLK, x=1..15 + bank_select: EXMC_SDRAM_DEVICE0_SELECT, EXMC_SDRAM_DEVICE1_SELECT, EXMC_SDRAM_DEVICE0_1_SELECT + command: EXMC_SDRAM_NORMAL_OPERATION, EXMC_SDRAM_CLOCK_ENABLE, EXMC_SDRAM_PRECHARGE_ALL, + EXMC_SDRAM_AUTO_REFRESH, EXMC_SDRAM_LOAD_MODE_REGISTER, EXMC_SDRAM_SELF_REFRESH, + EXMC_SDRAM_POWERDOWN_ENTRY + \param[out] none + \retval none +*/ +void exmc_sdram_command_config(exmc_sdram_command_parameter_struct* exmc_sdram_command_init_struct) +{ + /* configure command register */ + EXMC_SDCMD = (uint32_t)((exmc_sdram_command_init_struct->command) | + (exmc_sdram_command_init_struct->bank_select) | + ((exmc_sdram_command_init_struct->auto_refresh_number)) | + ((exmc_sdram_command_init_struct->mode_register_content)<> SDSTAT_STA0_OFFSET); + }else{ + sdstat = ((uint32_t)(EXMC_SDSTAT & EXMC_SDSDAT_STA1) >> SDSTAT_STA1_OFFSET); + } + + return sdstat; } /*! \brief set the read command \param[in] read_command_mode: configure SPI PSRAM read command mode + only one parameter can be selected which is shown as below: \arg EXMC_SQPIPSRAM_READ_MODE_DISABLE: not SPI mode \arg EXMC_SQPIPSRAM_READ_MODE_SPI: SPI mode \arg EXMC_SQPIPSRAM_READ_MODE_SQPI: SQPI mode @@ -843,10 +928,10 @@ void exmc_sqpipsram_parameter_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsr \param[out] none \retval none */ -void exmc_sqpipsram_read_command_set(uint32_t read_command_mode,uint32_t read_wait_cycle,uint32_t read_command_code) +void exmc_sqpipsram_read_command_set(uint32_t read_command_mode,uint32_t read_wait_cycle, uint32_t read_command_code) { uint32_t srcmd; - + srcmd = (uint32_t) read_command_mode | ((read_wait_cycle << SRCMD_RWAITCYCLE_OFFSET) & EXMC_SRCMD_RWAITCYCLE) | ((read_command_code & EXMC_SRCMD_RCMD)); @@ -856,6 +941,7 @@ void exmc_sqpipsram_read_command_set(uint32_t read_command_mode,uint32_t read_wa /*! \brief set the write command \param[in] write_command_mode: configure SPI PSRAM write command mode + only one parameter can be selected which is shown as below: \arg EXMC_SQPIPSRAM_WRITE_MODE_DISABLE: not SPI mode \arg EXMC_SQPIPSRAM_WRITE_MODE_SPI: SPI mode \arg EXMC_SQPIPSRAM_WRITE_MODE_SQPI: SQPI mode @@ -865,10 +951,10 @@ void exmc_sqpipsram_read_command_set(uint32_t read_command_mode,uint32_t read_wa \param[out] none \retval none */ -void exmc_sqpipsram_write_command_set(uint32_t write_command_mode,uint32_t write_wait_cycle,uint32_t write_command_code) +void exmc_sqpipsram_write_command_set(uint32_t write_command_mode,uint32_t write_wait_cycle, uint32_t write_command_code) { uint32_t swcmd; - + swcmd = (uint32_t) write_command_mode | ((write_wait_cycle << SWCMD_WWAITCYCLE_OFFSET) & EXMC_SWCMD_WWAITCYCLE) | ((write_command_code & EXMC_SWCMD_WCMD)); @@ -922,6 +1008,7 @@ uint32_t exmc_sqpipsram_high_id_get(void) /*! \brief get the bit value of EXMC send write command bit or read ID command \param[in] send_command_flag: the send command flag + only one parameter can be selected which is shown as below: \arg EXMC_SEND_COMMAND_FLAG_RDID: EXMC_SRCMD_RDID flag bit \arg EXMC_SEND_COMMAND_FLAG_SC: EXMC_SWCMD_SC flag bit \param[out] none @@ -930,14 +1017,14 @@ uint32_t exmc_sqpipsram_high_id_get(void) FlagStatus exmc_sqpipsram_send_command_state_get(uint32_t send_command_flag) { uint32_t flag = 0x00000000U; - + if(EXMC_SEND_COMMAND_FLAG_RDID == send_command_flag){ flag = EXMC_SRCMD; }else if(EXMC_SEND_COMMAND_FLAG_SC == send_command_flag){ flag = EXMC_SWCMD; }else{ } - + if (flag & send_command_flag){ /* flag is set */ return SET; @@ -948,14 +1035,74 @@ FlagStatus exmc_sqpipsram_send_command_state_get(uint32_t send_command_flag) } /*! - \brief check EXMC flag is set or not + \brief enable EXMC interrupt + \param[in] exmc_bank: specifies the NAND bank,PC card bank or SDRAM device + only one parameter can be selected which is shown as below: + \arg EXMC_BANK1_NAND: the NAND bank1 + \arg EXMC_BANK2_NAND: the NAND bank2 + \arg EXMC_BANK3_PCCARD: the PC card bank + \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 + \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 + \param[in] interrupt: specify get which interrupt flag + only one parameter can be selected which is shown as below: + \arg EXMC_NAND_PCCARD_INT_FLAG_RISE: rising edge interrupt and flag + \arg EXMC_NAND_PCCARD_INT_FLAG_LEVEL: high-level interrupt and flag + \arg EXMC_NAND_PCCARD_INT_FLAG_FALL: falling edge interrupt and flag + \arg EXMC_SDRAM_INT_FLAG_REFRESH: refresh error interrupt and flag + \param[out] none + \retval none +*/ +void exmc_interrupt_enable(uint32_t exmc_bank, uint32_t interrupt) +{ + if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)){ + /* NAND bank1,bank2 or PC card bank3 */ + EXMC_NPINTEN(exmc_bank) |= interrupt; + }else{ + /* SDRAM device0 or device1 */ + EXMC_SDARI |= EXMC_SDARI_REIE; + } +} + +/*! + \brief disable EXMC interrupt \param[in] exmc_bank: specifies the NAND bank , PC card bank or SDRAM device + only one parameter can be selected which is shown as below: + \arg EXMC_BANK1_NAND: the NAND bank1 + \arg EXMC_BANK2_NAND: the NAND bank2 + \arg EXMC_BANK3_PCCARD: the PC card bank + \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 + \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 + \param[in] interrupt: specify get which interrupt flag + only one parameter can be selected which is shown as below: + \arg EXMC_NAND_PCCARD_INT_FLAG_RISE: rising edge interrupt and flag + \arg EXMC_NAND_PCCARD_INT_FLAG_LEVEL: high-level interrupt and flag + \arg EXMC_NAND_PCCARD_INT_FLAG_FALL: falling edge interrupt and flag + \arg EXMC_SDRAM_INT_FLAG_REFRESH: refresh error interrupt and flag + \param[out] none + \retval none +*/ +void exmc_interrupt_disable(uint32_t exmc_bank, uint32_t interrupt) +{ + if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)){ + /* NAND bank1,bank2 or PC card bank3 */ + EXMC_NPINTEN(exmc_bank) &= ~interrupt; + }else{ + /* SDRAM device0 or device1 */ + EXMC_SDARI &= ~EXMC_SDARI_REIE; + } +} + +/*! + \brief get EXMC flag status + \param[in] exmc_bank: specifies the NAND bank , PC card bank or SDRAM device + only one parameter can be selected which is shown as below: \arg EXMC_BANK1_NAND: the NAND bank1 \arg EXMC_BANK2_NAND: the NAND bank2 \arg EXMC_BANK3_PCCARD: the PC Card bank \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 - \param[in] flag: specify get which flag + \param[in] flag: EXMC status and flag + only one parameter can be selected which is shown as below: \arg EXMC_NAND_PCCARD_FLAG_RISE: interrupt rising edge status \arg EXMC_NAND_PCCARD_FLAG_LEVEL: interrupt high-level status \arg EXMC_NAND_PCCARD_FLAG_FALL: interrupt falling edge status @@ -976,7 +1123,7 @@ FlagStatus exmc_flag_get(uint32_t exmc_bank,uint32_t flag) /* SDRAM device0 or device1 */ status = EXMC_SDSTAT; } - + if ((status & flag) != (uint32_t)flag ){ /* flag is reset */ return RESET; @@ -987,14 +1134,16 @@ FlagStatus exmc_flag_get(uint32_t exmc_bank,uint32_t flag) } /*! - \brief clear EXMC a channel flag + \brief clear EXMC flag status \param[in] exmc_bank: specifie the NAND bank , PCCARD bank or SDRAM device + only one parameter can be selected which is shown as below: \arg EXMC_BANK1_NAND: the NAND bank1 \arg EXMC_BANK2_NAND: the NAND bank2 \arg EXMC_BANK3_PCCARD: the PC card bank \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 - \param[in] flag: specify get which flag + \param[in] flag: EXMC status and flag + only one parameter can be selected which is shown as below: \arg EXMC_NAND_PCCARD_FLAG_RISE: interrupt rising edge status \arg EXMC_NAND_PCCARD_FLAG_LEVEL: interrupt high-level status \arg EXMC_NAND_PCCARD_FLAG_FALL: interrupt falling edge status @@ -1004,7 +1153,7 @@ FlagStatus exmc_flag_get(uint32_t exmc_bank,uint32_t flag) \param[out] none \retval none */ -void exmc_flag_clear(uint32_t exmc_bank,uint32_t flag) +void exmc_flag_clear(uint32_t exmc_bank, uint32_t flag) { if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)){ /* NAND bank1,bank2 or PC card bank3 */ @@ -1012,40 +1161,42 @@ void exmc_flag_clear(uint32_t exmc_bank,uint32_t flag) }else{ /* SDRAM device0 or device1 */ EXMC_SDSTAT &= ~flag; - } + } } /*! - \brief check EXMC interrupt flag is set or not + \brief get EXMC interrupt flag \param[in] exmc_bank: specifies the NAND bank , PC card bank or SDRAM device + only one parameter can be selected which is shown as below: \arg EXMC_BANK1_NAND: the NAND bank1 \arg EXMC_BANK2_NAND: the NAND bank2 \arg EXMC_BANK3_PCCARD: the PC card bank \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 - \param[in] interrupt_source: specify get which interrupt flag - \arg EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge - \arg EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level - \arg EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge - \arg EXMC_SDRAM_INT_REFRESH: interrupt source of refresh error + \param[in] interrupt: EXMC interrupt flag + only one parameter can be selected which is shown as below: + \arg EXMC_NAND_PCCARD_INT_FLAG_RISE: rising edge interrupt and flag + \arg EXMC_NAND_PCCARD_INT_FLAG_LEVEL: high-level interrupt and flag + \arg EXMC_NAND_PCCARD_INT_FLAG_FALL: falling edge interrupt and flag + \arg EXMC_SDRAM_INT_FLAG_REFRESH: refresh error interrupt and flag \param[out] none \retval FlagStatus: SET or RESET */ -FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank,uint32_t interrupt_source) +FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank, uint32_t interrupt) { uint32_t status = 0x00000000U,interrupt_enable = 0x00000000U,interrupt_state = 0x00000000U; if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)){ /* NAND bank1,bank2 or PC card bank3 */ status = EXMC_NPINTEN(exmc_bank); - interrupt_enable = (status & (interrupt_source >> INTEN_INTEN_OFFSET)); + interrupt_state = (status & (interrupt >> INTEN_INTS_OFFSET)); }else{ /* SDRAM device0 or device1 */ status = EXMC_SDARI; - interrupt_enable = (EXMC_SDSTAT & EXMC_SDSDAT_REIF); + interrupt_state = (EXMC_SDSTAT & EXMC_SDSDAT_REIF); } - interrupt_state = (status & interrupt_source); + interrupt_enable = (status & interrupt); if ((interrupt_enable) && (interrupt_state)){ /* interrupt flag is set */ @@ -1057,82 +1208,30 @@ FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank,uint32_t interrupt_source) } /*! - \brief clear EXMC one channel interrupt flag + \brief clear EXMC interrupt flag \param[in] exmc_bank: specifies the NAND bank , PC card bank or SDRAM device + only one parameter can be selected which is shown as below: \arg EXMC_BANK1_NAND: the NAND bank1 \arg EXMC_BANK2_NAND: the NAND bank2 \arg EXMC_BANK3_PCCARD: the PC card bank \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 - \param[in] interrupt_source: specify get which interrupt flag - \arg EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge - \arg EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level - \arg EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge - \arg EXMC_SDRAM_INT_REFRESH: interrupt source of refresh error + \param[in] interrupt: EXMC interrupt flag + only one parameter can be selected which is shown as below: + \arg EXMC_NAND_PCCARD_INT_FLAG_RISE: rising edge interrupt and flag + \arg EXMC_NAND_PCCARD_INT_FLAG_LEVEL: high-level interrupt and flag + \arg EXMC_NAND_PCCARD_INT_FLAG_FALL: falling edge interrupt and flag + \arg EXMC_SDRAM_INT_FLAG_REFRESH: refresh error interrupt and flag \param[out] none \retval none */ -void exmc_interrupt_flag_clear(uint32_t exmc_bank,uint32_t interrupt_source) +void exmc_interrupt_flag_clear(uint32_t exmc_bank, uint32_t interrupt) { if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)){ /* NAND bank1,bank2 or PC card bank3 */ - EXMC_NPINTEN(exmc_bank) &= ~(interrupt_source >> INTEN_INTEN_OFFSET); + EXMC_NPINTEN(exmc_bank) &= ~(interrupt >> INTEN_INTS_OFFSET); }else{ /* SDRAM device0 or device1 */ EXMC_SDARI |= EXMC_SDARI_REC; } } - -/*! - \brief enable EXMC interrupt - \param[in] exmc_bank: specifies the NAND bank,PC card bank or SDRAM device - \arg EXMC_BANK1_NAND: the NAND bank1 - \arg EXMC_BANK2_NAND: the NAND bank2 - \arg EXMC_BANK3_PCCARD: the PC card bank - \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 - \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 - \param[in] interrupt_source: specify get which interrupt flag - \arg EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge - \arg EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level - \arg EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge - \arg EXMC_SDRAM_INT_REFRESH: interrupt source of refresh error - \param[out] none - \retval none -*/ -void exmc_interrupt_enable(uint32_t exmc_bank,uint32_t interrupt_source) -{ - if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)){ - /* NAND bank1,bank2 or PC card bank3 */ - EXMC_NPINTEN(exmc_bank) |= interrupt_source; - }else{ - /* SDRAM device0 or device1 */ - EXMC_SDARI |= EXMC_SDARI_REIE; - } -} - -/*! - \brief disable EXMC interrupt - \param[in] exmc_bank: specifies the NAND bank , PC card bank or SDRAM device - \arg EXMC_BANK1_NAND: the NAND bank1 - \arg EXMC_BANK2_NAND: the NAND bank2 - \arg EXMC_BANK3_PCCARD: the PC card bank - \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 - \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 - \param[in] interrupt_source: specify get which interrupt flag - \arg EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge - \arg EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level - \arg EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge - \arg EXMC_SDRAM_INT_REFRESH: interrupt source of refresh error - \param[out] none - \retval none -*/ -void exmc_interrupt_disable(uint32_t exmc_bank,uint32_t interrupt_source) -{ - if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)){ - /* NAND bank1,bank2 or PC card bank3 */ - EXMC_NPINTEN(exmc_bank) &= ~interrupt_source; - }else{ - /* SDRAM device0 or device1 */ - EXMC_SDARI &= ~EXMC_SDARI_REIE; - } -} diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_exti.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_exti.c index 24bffea316..a3eacb0202 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_exti.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_exti.c @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_exti.c - \brief EXTI driver + \file gd32f4xx_exti.c + \brief EXTI driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.1, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_exti.h" @@ -41,6 +66,7 @@ void exti_deinit(void) \arg EXTI_TRIG_RISING: rising edge trigger \arg EXTI_TRIG_FALLING: falling trigger \arg EXTI_TRIG_BOTH: rising and falling trigger + \arg EXTI_TRIG_NONE: without rising edge or falling edge trigger \param[out] none \retval none */ @@ -53,7 +79,7 @@ void exti_init(exti_line_enum linex, \ EXTI_EVEN &= ~(uint32_t)linex; EXTI_RTEN &= ~(uint32_t)linex; EXTI_FTEN &= ~(uint32_t)linex; - + /* set the EXTI mode and enable the interrupts or events from EXTI line x */ switch(mode){ case EXTI_INTERRUPT: @@ -65,7 +91,7 @@ void exti_init(exti_line_enum linex, \ default: break; } - + /* set the EXTI trigger type */ switch(trig_type){ case EXTI_TRIG_RISING: @@ -80,6 +106,7 @@ void exti_init(exti_line_enum linex, \ EXTI_RTEN |= (uint32_t)linex; EXTI_FTEN |= (uint32_t)linex; break; + case EXTI_TRIG_NONE: default: break; } @@ -98,19 +125,6 @@ void exti_interrupt_enable(exti_line_enum linex) EXTI_INTEN |= (uint32_t)linex; } -/*! - \brief enable the events from EXTI line x - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..22): EXTI line x - \param[out] none - \retval none -*/ -void exti_event_enable(exti_line_enum linex) -{ - EXTI_EVEN |= (uint32_t)linex; -} - /*! \brief disable the interrupt from EXTI line x \param[in] linex: EXTI line number, refer to exti_line_enum @@ -124,6 +138,19 @@ void exti_interrupt_disable(exti_line_enum linex) EXTI_INTEN &= ~(uint32_t)linex; } +/*! + \brief enable the events from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..22): EXTI line x + \param[out] none + \retval none +*/ +void exti_event_enable(exti_line_enum linex) +{ + EXTI_EVEN |= (uint32_t)linex; +} + /*! \brief disable the events from EXTI line x \param[in] linex: EXTI line number, refer to exti_line_enum @@ -137,71 +164,6 @@ void exti_event_disable(exti_line_enum linex) EXTI_EVEN &= ~(uint32_t)linex; } -/*! - \brief get EXTI lines flag - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..22): EXTI line x - \param[out] none - \retval FlagStatus: status of flag (RESET or SET) -*/ -FlagStatus exti_flag_get(exti_line_enum linex) -{ - if(RESET != (EXTI_PD & (uint32_t)linex)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear EXTI lines pending flag - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..22): EXTI line x - \param[out] none - \retval none -*/ -void exti_flag_clear(exti_line_enum linex) -{ - EXTI_PD = (uint32_t)linex; -} - -/*! - \brief get EXTI lines flag when the interrupt flag is set - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..22): EXTI line x - \param[out] none - \retval FlagStatus: status of flag (RESET or SET) -*/ -FlagStatus exti_interrupt_flag_get(exti_line_enum linex) -{ - uint32_t flag_left, flag_right; - - flag_left = EXTI_PD & (uint32_t)linex; - flag_right = EXTI_INTEN & (uint32_t)linex; - - if((RESET != flag_left) && (RESET != flag_right)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear EXTI lines pending flag - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..22): EXTI line x - \param[out] none - \retval none -*/ -void exti_interrupt_flag_clear(exti_line_enum linex) -{ - EXTI_PD = (uint32_t)linex; -} - /*! \brief enable EXTI software interrupt event \param[in] linex: EXTI line number, refer to exti_line_enum @@ -227,3 +189,69 @@ void exti_software_interrupt_disable(exti_line_enum linex) { EXTI_SWIEV &= ~(uint32_t)linex; } + +/*! + \brief get EXTI lines flag + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..22): EXTI line x + \param[out] none + \retval FlagStatus: status of flag (RESET or SET) +*/ +FlagStatus exti_flag_get(exti_line_enum linex) +{ + if(RESET != (EXTI_PD & (uint32_t)linex)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear EXTI lines pending flag + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..22): EXTI line x + \param[out] none + \retval none +*/ +void exti_flag_clear(exti_line_enum linex) +{ + EXTI_PD = (uint32_t)linex; +} + +/*! + \brief get EXTI lines flag when the interrupt flag is set + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..22): EXTI line x + \param[out] none + \retval FlagStatus: status of flag (RESET or SET) +*/ +FlagStatus exti_interrupt_flag_get(exti_line_enum linex) +{ + uint32_t flag_left, flag_right; + + flag_left = EXTI_PD & (uint32_t)linex; + flag_right = EXTI_INTEN & (uint32_t)linex; + + if((RESET != flag_left) && (RESET != flag_right)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear EXTI lines pending flag + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..22): EXTI line x + \param[out] none + \retval none +*/ +void exti_interrupt_flag_clear(exti_line_enum linex) +{ + EXTI_PD = (uint32_t)linex; +} + diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_fmc.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_fmc.c index 2bfc2f1caa..4e2b0db9a5 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_fmc.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_fmc.c @@ -1,19 +1,46 @@ /*! - \file gd32f4xx_fmc.c - \brief FMC driver + \file gd32f4xx_fmc.c + \brief FMC driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ + #include "gd32f4xx_fmc.h" /*! \brief set the wait state counter value - \param[in] wscntwait state counter value + \param[in] wscnt: wait state counter value + only one parameter can be selected which is shown as below: \arg WS_WSCNT_0: FMC 0 wait \arg WS_WSCNT_1: FMC 1 wait \arg WS_WSCNT_2: FMC 2 wait @@ -36,7 +63,7 @@ void fmc_wscnt_set(uint32_t wscnt) { uint32_t reg; - + reg = FMC_WS; /* set the wait state counter value */ reg &= ~FMC_WC_WSCNT; @@ -73,58 +100,64 @@ void fmc_lock(void) /*! \brief erase sector \param[in] fmc_sector: select the sector to erase - \arg CTL_SECTOR_NUMBER_0: sector 0 - \arg CTL_SECTOR_NUMBER_1: sector 1 - \arg CTL_SECTOR_NUMBER_2: sector 2 - \arg CTL_SECTOR_NUMBER_3: sector 3 - \arg CTL_SECTOR_NUMBER_4: sector 4 - \arg CTL_SECTOR_NUMBER_5: sector 5 - \arg CTL_SECTOR_NUMBER_6: sector 6 - \arg CTL_SECTOR_NUMBER_7: sector 7 - \arg CTL_SECTOR_NUMBER_8: sector 8 - \arg CTL_SECTOR_NUMBER_9: sector 9 - \arg CTL_SECTOR_NUMBER_10: sector 10 - \arg CTL_SECTOR_NUMBER_11: sector 11 - \arg CTL_SECTOR_NUMBER_12: sector 12 - \arg CTL_SECTOR_NUMBER_13: sector 13 - \arg CTL_SECTOR_NUMBER_14: sector 14 - \arg CTL_SECTOR_NUMBER_15: sector 15 - \arg CTL_SECTOR_NUMBER_16: sector 16 - \arg CTL_SECTOR_NUMBER_17: sector 17 - \arg CTL_SECTOR_NUMBER_18: sector 18 - \arg CTL_SECTOR_NUMBER_19: sector 19 - \arg CTL_SECTOR_NUMBER_20: sector 20 - \arg CTL_SECTOR_NUMBER_21: sector 21 - \arg CTL_SECTOR_NUMBER_22: sector 22 - \arg CTL_SECTOR_NUMBER_23: sector 23 - \arg CTL_SECTOR_NUMBER_24: sector 24 - \arg CTL_SECTOR_NUMBER_25: sector 25 - \arg CTL_SECTOR_NUMBER_26: sector 26 - \arg CTL_SECTOR_NUMBER_27: sector 27 - \arg CTL_SECTOR_NUMBER_28: sector 28 - \arg CTL_SECTOR_NUMBER_29: sector 29 - \arg CTL_SECTOR_NUMBER_30: sector 30 + only one parameter can be selected which is shown as below: + \arg CTL_SECTOR_NUMBER_0: sector 0 + \arg CTL_SECTOR_NUMBER_1: sector 1 + \arg CTL_SECTOR_NUMBER_2: sector 2 + \arg CTL_SECTOR_NUMBER_3: sector 3 + \arg CTL_SECTOR_NUMBER_4: sector 4 + \arg CTL_SECTOR_NUMBER_5: sector 5 + \arg CTL_SECTOR_NUMBER_6: sector 6 + \arg CTL_SECTOR_NUMBER_7: sector 7 + \arg CTL_SECTOR_NUMBER_8: sector 8 + \arg CTL_SECTOR_NUMBER_9: sector 9 + \arg CTL_SECTOR_NUMBER_10: sector 10 + \arg CTL_SECTOR_NUMBER_11: sector 11 + \arg CTL_SECTOR_NUMBER_12: sector 12 + \arg CTL_SECTOR_NUMBER_13: sector 13 + \arg CTL_SECTOR_NUMBER_14: sector 14 + \arg CTL_SECTOR_NUMBER_15: sector 15 + \arg CTL_SECTOR_NUMBER_16: sector 16 + \arg CTL_SECTOR_NUMBER_17: sector 17 + \arg CTL_SECTOR_NUMBER_18: sector 18 + \arg CTL_SECTOR_NUMBER_19: sector 19 + \arg CTL_SECTOR_NUMBER_20: sector 20 + \arg CTL_SECTOR_NUMBER_21: sector 21 + \arg CTL_SECTOR_NUMBER_22: sector 22 + \arg CTL_SECTOR_NUMBER_23: sector 23 + \arg CTL_SECTOR_NUMBER_24: sector 24 + \arg CTL_SECTOR_NUMBER_25: sector 25 + \arg CTL_SECTOR_NUMBER_26: sector 26 + \arg CTL_SECTOR_NUMBER_27: sector 27 \param[out] none - \retval fmc_state_enum + \retval state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_RDDERR: read D-bus protection error + \arg FMC_PGSERR: program sequence error + \arg FMC_PGMERR: program size not match error + \arg FMC_WPERR: erase/program protection error + \arg FMC_OPERR: operation error + \arg FMC_PGERR: program error */ fmc_state_enum fmc_sector_erase(uint32_t fmc_sector) { fmc_state_enum fmc_state = FMC_READY; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ + fmc_state = fmc_ready_wait(); + + if(FMC_READY == fmc_state){ /* start sector erase */ FMC_CTL &= ~FMC_CTL_SN; FMC_CTL |= (FMC_CTL_SER | fmc_sector); FMC_CTL |= FMC_CTL_START; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - + fmc_state = fmc_ready_wait(); + /* reset the SER bit */ FMC_CTL &= (~FMC_CTL_SER); - FMC_CTL &= ~FMC_CTL_SN; + FMC_CTL &= ~FMC_CTL_SN; } /* return the FMC state */ @@ -135,21 +168,29 @@ fmc_state_enum fmc_sector_erase(uint32_t fmc_sector) \brief erase whole chip \param[in] none \param[out] none - \retval fmc_state_enum + \retval state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_RDDERR: read D-bus protection error + \arg FMC_PGSERR: program sequence error + \arg FMC_PGMERR: program size not match error + \arg FMC_WPERR: erase/program protection error + \arg FMC_OPERR: operation error + \arg FMC_PGERR: program error */ fmc_state_enum fmc_mass_erase(void) { fmc_state_enum fmc_state = FMC_READY; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + fmc_state = fmc_ready_wait(); - if(FMC_READY == fmc_state){ - /* start whole chip erase */ + if(FMC_READY == fmc_state){ + /* start whole chip erase */ FMC_CTL |= (FMC_CTL_MER0 | FMC_CTL_MER1); FMC_CTL |= FMC_CTL_START; - + /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + fmc_state = fmc_ready_wait(); /* reset the MER bits */ FMC_CTL &= ~(FMC_CTL_MER0 | FMC_CTL_MER1); @@ -163,21 +204,29 @@ fmc_state_enum fmc_mass_erase(void) \brief erase all FMC sectors in bank0 \param[in] none \param[out] none - \retval fmc_state_enum + \retval state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_RDDERR: read D-bus protection error + \arg FMC_PGSERR: program sequence error + \arg FMC_PGMERR: program size not match error + \arg FMC_WPERR: erase/program protection error + \arg FMC_OPERR: operation error + \arg FMC_PGERR: program error */ fmc_state_enum fmc_bank0_erase(void) { fmc_state_enum fmc_state = FMC_READY; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + fmc_state = fmc_ready_wait(); if(FMC_READY == fmc_state){ /* start FMC bank0 erase */ FMC_CTL |= FMC_CTL_MER0; FMC_CTL |= FMC_CTL_START; - + /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + fmc_state = fmc_ready_wait(); /* reset the MER0 bit */ FMC_CTL &= (~FMC_CTL_MER0); @@ -191,21 +240,29 @@ fmc_state_enum fmc_bank0_erase(void) \brief erase all FMC sectors in bank1 \param[in] none \param[out] none - \retval fmc_state_enum + \retval state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_RDDERR: read D-bus protection error + \arg FMC_PGSERR: program sequence error + \arg FMC_PGMERR: program size not match error + \arg FMC_WPERR: erase/program protection error + \arg FMC_OPERR: operation error + \arg FMC_PGERR: program error */ fmc_state_enum fmc_bank1_erase(void) { fmc_state_enum fmc_state = FMC_READY; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - + fmc_state = fmc_ready_wait(); + if(FMC_READY == fmc_state){ /* start FMC bank1 erase */ FMC_CTL |= FMC_CTL_MER1; FMC_CTL |= FMC_CTL_START; - + /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + fmc_state = fmc_ready_wait(); /* reset the MER1 bit */ FMC_CTL &= (~FMC_CTL_MER1); @@ -218,31 +275,39 @@ fmc_state_enum fmc_bank1_erase(void) /*! \brief program a word at the corresponding address \param[in] address: address to program - \param[in] data: word to program + \param[in] data: word to program(0x00000000 - 0xFFFFFFFF) \param[out] none - \retval fmc_state_enum + \retval state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_RDDERR: read D-bus protection error + \arg FMC_PGSERR: program sequence error + \arg FMC_PGMERR: program size not match error + \arg FMC_WPERR: erase/program protection error + \arg FMC_OPERR: operation error + \arg FMC_PGERR: program error */ fmc_state_enum fmc_word_program(uint32_t address, uint32_t data) { fmc_state_enum fmc_state = FMC_READY; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - + fmc_state = fmc_ready_wait(); + if(FMC_READY == fmc_state){ /* set the PG bit to start program */ FMC_CTL &= ~FMC_CTL_PSZ; FMC_CTL |= CTL_PSZ_WORD; - FMC_CTL |= FMC_CTL_PG; - + FMC_CTL |= FMC_CTL_PG; + REG32(address) = data; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - + fmc_state = fmc_ready_wait(); + /* reset the PG bit */ - FMC_CTL &= ~FMC_CTL_PG; - } - + FMC_CTL &= ~FMC_CTL_PG; + } + /* return the FMC state */ return fmc_state; } @@ -250,31 +315,39 @@ fmc_state_enum fmc_word_program(uint32_t address, uint32_t data) /*! \brief program a half word at the corresponding address \param[in] address: address to program - \param[in] data: halfword to program + \param[in] data: halfword to program(0x0000 - 0xFFFF) \param[out] none - \retval fmc_state_enum + \retval state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_RDDERR: read D-bus protection error + \arg FMC_PGSERR: program sequence error + \arg FMC_PGMERR: program size not match error + \arg FMC_WPERR: erase/program protection error + \arg FMC_OPERR: operation error + \arg FMC_PGERR: program error */ fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data) { fmc_state_enum fmc_state = FMC_READY; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ + fmc_state = fmc_ready_wait(); + + if(FMC_READY == fmc_state){ /* set the PG bit to start program */ FMC_CTL &= ~FMC_CTL_PSZ; FMC_CTL |= CTL_PSZ_HALF_WORD; - FMC_CTL |= FMC_CTL_PG; - + FMC_CTL |= FMC_CTL_PG; + REG16(address) = data; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - + fmc_state = fmc_ready_wait(); + /* reset the PG bit */ - FMC_CTL &= ~FMC_CTL_PG; - } - + FMC_CTL &= ~FMC_CTL_PG; + } + /* return the FMC state */ return fmc_state; } @@ -282,31 +355,39 @@ fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data) /*! \brief program a byte at the corresponding address \param[in] address: address to program - \param[in] data: byte to program + \param[in] data: byte to program(0x00 - 0xFF) \param[out] none - \retval fmc_state_enum + \retval state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_RDDERR: read D-bus protection error + \arg FMC_PGSERR: program sequence error + \arg FMC_PGMERR: program size not match error + \arg FMC_WPERR: erase/program protection error + \arg FMC_OPERR: operation error + \arg FMC_PGERR: program error */ fmc_state_enum fmc_byte_program(uint32_t address, uint8_t data) { fmc_state_enum fmc_state = FMC_READY; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - + fmc_state = fmc_ready_wait(); + if(FMC_READY == fmc_state){ /* set the PG bit to start program */ FMC_CTL &= ~FMC_CTL_PSZ; FMC_CTL |= CTL_PSZ_BYTE; FMC_CTL |= FMC_CTL_PG; - + REG8(address) = data; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - + fmc_state = fmc_ready_wait(); + /* reset the PG bit */ - FMC_CTL &= ~FMC_CTL_PG; - } - + FMC_CTL &= ~FMC_CTL_PG; + } + /* return the FMC state */ return fmc_state; } @@ -335,7 +416,7 @@ void ob_unlock(void) void ob_lock(void) { /* reset the OB_LK bit */ - FMC_OBCTL0 &= ~FMC_OBCTL0_OB_LK; + FMC_OBCTL0 |= FMC_OBCTL0_OB_LK; } /*! @@ -346,178 +427,183 @@ void ob_lock(void) */ void ob_start(void) { + fmc_state_enum fmc_state = FMC_READY; /* set the OB_START bit in OBCTL0 register */ FMC_OBCTL0 |= FMC_OBCTL0_OB_START; + fmc_state = fmc_ready_wait(); + if(FMC_READY != fmc_state){ + while(1){ + } + } } /*! - \brief enable write protection - \param[in] ob_wp: specify sector to be write protected - \arg OB_WPx(x=0..11): write protect specify sector - \arg OB_WP_ALL: write protect all sector + \brief erase option byte + \param[in] none \param[out] none \retval none */ -void ob_write_protection0_enable(uint32_t ob_wp) +void ob_erase(void) { + uint32_t reg, reg1; fmc_state_enum fmc_state = FMC_READY; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + fmc_state = fmc_ready_wait(); if(FMC_READY == fmc_state){ - FMC_OBCTL0 &= (~((uint32_t)ob_wp << 16)); - } -} + reg = FMC_OBCTL0; + reg1 = FMC_OBCTL1; -/*! - \brief disable write protection - \param[in] ob_wp: specify sector to be write protected - \arg OB_WPx(x=0..11): write protect specify sector - \arg OB_WP_ALL: write protect all sector - \param[out] none - \retval none -*/ -void ob_write_protection0_disable(uint32_t ob_wp) -{ - fmc_state_enum fmc_state = FMC_READY; - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the OB_FWDGT, OB_DEEPSLEEP and OB_STDBY, set according to ob_fwdgt ,ob_deepsleep and ob_stdby */ + reg |= (FMC_OBCTL0_NWDG_HW | FMC_OBCTL0_NRST_DPSLP | FMC_OBCTL0_NRST_STDBY); + /* reset the BOR level */ + reg |= FMC_OBCTL0_BOR_TH; + /* reset option byte boot bank value */ + reg &= ~FMC_OBCTL0_BB; + /* reset option byte dbs value */ + reg &= ~FMC_OBCTL0_DBS; - if(FMC_READY == fmc_state){ - FMC_OBCTL0 |= ((uint32_t)ob_wp << 16); + /* reset drp and wp value */ + reg |= FMC_OBCTL0_WP0; + reg &= (~FMC_OBCTL0_DRP); + FMC_OBCTL0 = reg; + + reg1 |= FMC_OBCTL1_WP1; + FMC_OBCTL1 = reg1; + + FMC_OBCTL0 = reg; } } /*! \brief enable write protection \param[in] ob_wp: specify sector to be write protected - \arg OB_WPx(x=12..30): write protect specify sector - \arg OB_WP_ALL: write protect all sector + one or more parameters can be selected which are shown as below: + \arg OB_WP_x(x=0..22):sector x(x = 0,1,2...22) + \arg OB_WP_23_27: sector23~27 + \arg OB_WP_ALL: all sector \param[out] none \retval none */ -void ob_write_protection1_enable(uint32_t ob_wp) +void ob_write_protection_enable(uint32_t ob_wp) { + uint32_t reg0 = FMC_OBCTL0; + uint32_t reg1 = FMC_OBCTL1; fmc_state_enum fmc_state = FMC_READY; + if(RESET != (FMC_OBCTL0 & FMC_OBCTL0_DRP)){ + while(1){ + } + } /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + fmc_state = fmc_ready_wait(); if(FMC_READY == fmc_state){ - FMC_OBCTL1 &= (~((uint32_t)ob_wp << 16)); + reg0 &= (~((uint32_t)ob_wp << 16)); + reg1 &= (~(ob_wp & 0xFFFF0000U)); + FMC_OBCTL0 = reg0; + FMC_OBCTL1 = reg1; } } /*! \brief disable write protection \param[in] ob_wp: specify sector to be write protected - \arg OB_WPx(x=12..30): write protect specify sector - \arg OB_WP_ALL: write protect all sector + one or more parameters can be selected which are shown as below: + \arg OB_WP_x(x=0..22):sector x(x = 0,1,2...22) + \arg OB_WP_23_27: sector23~27 + \arg OB_WP_ALL: all sector \param[out] none \retval none */ -void ob_write_protection1_disable(uint32_t ob_wp) +void ob_write_protection_disable(uint32_t ob_wp) { + uint32_t reg0 = FMC_OBCTL0; + uint32_t reg1 = FMC_OBCTL1; fmc_state_enum fmc_state = FMC_READY; + if(RESET != (FMC_OBCTL0 & FMC_OBCTL0_DRP)){ + while(1){ + } + } /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + fmc_state = fmc_ready_wait(); if(FMC_READY == fmc_state){ - FMC_OBCTL1 |= ((uint32_t)ob_wp << 16); + reg0 |= ((uint32_t)ob_wp << 16); + reg1 |= (ob_wp & 0xFFFF0000U); + FMC_OBCTL0 = reg0; + FMC_OBCTL1 = reg1; } } -/*! - \brief configure the protection mode - \param[in] ob_drp: configure the protection mode of WPx bits - \arg OB_DRP_DISABLE: the WPx bits used as erase/program protection of each sector - \arg OB_DRP_ENABLE: the WPx bits used as erase/program protection and D-bus read protection of each sector - \param[out] none - \retval none -*/ -void ob_drp_config(uint32_t ob_drp) -{ - FMC_OBCTL0 &= ~FMC_OBCTL0_DRP; - FMC_OBCTL0 |= ob_drp; -} /*! \brief enable erase/program protection and D-bus read protection - \param[in] ob_drp: enable the WPx bits used as erase/program protection and D-bus read protection of each sector - \arg OB_DRPx(x=0..11): erase/program protection and D-bus read protection of specify sector - \arg OB_DRP_ALL: erase/program protection and D-bus read protection of all sector + \param[in] ob_drp: enable the WPx bits used as erase/program protection and D-bus read protection of each sector + one or more parameters can be selected which are shown as below: + \arg OB_DRP_x(x=0..22): sector x(x = 0,1,2...22) + \arg OB_DRP_23_27: sector23~27 + \arg OB_DRP_ALL: all sector \param[out] none \retval none */ -void ob_drp0_enable(uint32_t ob_drp) +void ob_drp_enable(uint32_t ob_drp) { + uint32_t reg0 = FMC_OBCTL0; + uint32_t reg1 = FMC_OBCTL1; fmc_state_enum fmc_state = FMC_READY; + uint32_t drp_state = FMC_OBCTL0 & FMC_OBCTL0_DRP; + uint32_t wp0_state = FMC_OBCTL0 & FMC_OBCTL0_WP0; + uint32_t wp1_state = FMC_OBCTL1 & FMC_OBCTL1_WP1; + /*disable write protection before enable D-bus read protection*/ + if((RESET != drp_state) && ((FMC_OBCTL0_WP0 != wp0_state) && (FMC_OBCTL1_WP1 != wp1_state))){ + while(1){ + } + } /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + fmc_state = fmc_ready_wait(); if(FMC_READY == fmc_state){ - FMC_OBCTL0 |= ((uint32_t)ob_drp << 16); + reg0 &= ~FMC_OBCTL0_WP0; + reg1 &= ~FMC_OBCTL1_WP1; + reg0 |= ((uint32_t)ob_drp << 16); + reg1 |= ((uint32_t)ob_drp & 0xFFFF0000U); + FMC_OBCTL0 = reg0; + FMC_OBCTL1 = reg1; + FMC_OBCTL0 |= FMC_OBCTL0_DRP; } } /*! \brief disable erase/program protection and D-bus read protection \param[in] ob_drp: disable the WPx bits used as erase/program protection and D-bus read protection of each sector - \arg OB_DRPx(x=0..11): erase/program protection and D-bus read protection of specify sector - \arg OB_DRP_ALL: erase/program protection and D-bus read protection of all sector + one or more parameters can be selected which are shown as below: + \arg OB_DRP_x(x=0..22): sector x(x = 0,1,2...22) + \arg OB_DRP_23_27: sector23~27 + \arg OB_DRP_ALL: all sector \param[out] none \retval none */ -void ob_drp0_disable(uint32_t ob_drp) +void ob_drp_disable(uint32_t ob_drp) { + uint32_t reg0 = FMC_OBCTL0; + uint32_t reg1 = FMC_OBCTL1; fmc_state_enum fmc_state = FMC_READY; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + fmc_state = fmc_ready_wait(); if(FMC_READY == fmc_state){ - FMC_OBCTL0 &= (~((uint32_t)ob_drp << 16)); - } -} + reg0 |= FMC_OBCTL0_WP0; + reg0 &= (~FMC_OBCTL0_DRP); + FMC_OBCTL0 = reg0; -/*! - \brief enable erase/program protection and D-bus read protection - \param[in] ob_drp: enable the WPx bits used as erase/program protection and D-bus read protection of each sector - \arg OB_DRPx(x=12..30): erase/program protection and D-bus read protection of specify sector - \arg OB_DRP_ALL: erase/program protection and D-bus read protection of all sector - \param[out] none - \retval none -*/ -void ob_drp1_enable(uint32_t ob_drp) -{ - fmc_state_enum fmc_state = FMC_READY; - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - FMC_OBCTL1 |= ((uint32_t)ob_drp << 16); - } -} - -/*! - \brief disable erase/program protection and D-bus read protection - \param[in] ob_drp: disable the WPx bits used as erase/program protection and D-bus read protection of each sector - \arg OB_DRPx(x=12..30): erase/program protection and D-bus read protection of specify sector - \arg OB_DRP_ALL: erase/program protection and D-bus read protection of all sector - \param[out] none - \retval none -*/ -void ob_drp1_disable(uint32_t ob_drp) -{ - fmc_state_enum fmc_state = FMC_READY; - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - FMC_OBCTL1 &= (~((uint32_t)ob_drp << 16)); + reg1 |= FMC_OBCTL1_WP1; + FMC_OBCTL1 = reg1; } } /*! \brief configure security protection level \param[in] ob_spc: specify security protection level + only one parameter can be selected which is shown as below: \arg FMC_NSPC: no security protection \arg FMC_LSPC: low security protection \arg FMC_HSPC: high security protection @@ -528,29 +614,33 @@ void ob_security_protection_config(uint8_t ob_spc) { fmc_state_enum fmc_state = FMC_READY; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + fmc_state = fmc_ready_wait(); if(FMC_READY == fmc_state){ uint32_t reg; - + reg = FMC_OBCTL0; /* reset the OBCTL0_SPC, set according to ob_spc */ reg &= ~FMC_OBCTL0_SPC; - FMC_OBCTL0 |= ((uint32_t)ob_spc << 8); + reg |= ((uint32_t)ob_spc << 8); + FMC_OBCTL0 = reg; } } /*! - \brief program the FMC user option byte + \brief program the FMC user option byte \param[in] ob_fwdgt: option byte watchdog value + only one parameter can be selected which is shown as below: \arg OB_FWDGT_SW: software free watchdog \arg OB_FWDGT_HW: hardware free watchdog \param[in] ob_deepsleep: option byte deepsleep reset value + only one parameter can be selected which is shown as below: \arg OB_DEEPSLEEP_NRST: no reset when entering deepsleep mode - \arg OB_DEEPSLEEP_RST: generate a reset instead of entering deepsleep mode + \arg OB_DEEPSLEEP_RST: generate a reset instead of entering deepsleep mode \param[in] ob_stdby:option byte standby reset value + only one parameter can be selected which is shown as below: \arg OB_STDBY_NRST: no reset when entering standby mode - \arg OB_STDBY_RST: generate a reset instead of entering standby mode + \arg OB_STDBY_RST: generate a reset instead of entering standby mode \param[out] none \retval none */ @@ -559,11 +649,11 @@ void ob_user_write(uint32_t ob_fwdgt, uint32_t ob_deepsleep, uint32_t ob_stdby) fmc_state_enum fmc_state = FMC_READY; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - + fmc_state = fmc_ready_wait(); + if(FMC_READY == fmc_state){ uint32_t reg; - + reg = FMC_OBCTL0; /* reset the OB_FWDGT, OB_DEEPSLEEP and OB_STDBY, set according to ob_fwdgt ,ob_deepsleep and ob_stdby */ reg &= ~(FMC_OBCTL0_NWDG_HW | FMC_OBCTL0_NRST_DPSLP | FMC_OBCTL0_NRST_STDBY); @@ -574,17 +664,18 @@ void ob_user_write(uint32_t ob_fwdgt, uint32_t ob_deepsleep, uint32_t ob_stdby) /*! \brief program the option byte BOR threshold value \param[in] ob_bor_th: user option byte + only one parameter can be selected which is shown as below: \arg OB_BOR_TH_VALUE3: BOR threshold value 3 \arg OB_BOR_TH_VALUE2: BOR threshold value 2 \arg OB_BOR_TH_VALUE1: BOR threshold value 1 - \arg OB_BOR_TH_OFF: no BOR function. + \arg OB_BOR_TH_OFF: no BOR function \param[out] none \retval none */ void ob_user_bor_threshold(uint32_t ob_bor_th) { uint32_t reg; - + reg = FMC_OBCTL0; /* set the BOR level */ reg &= ~FMC_OBCTL0_BOR_TH; @@ -594,6 +685,7 @@ void ob_user_bor_threshold(uint32_t ob_bor_th) /*! \brief configure the option byte boot bank value \param[in] boot_mode: specifies the option byte boot bank value + only one parameter can be selected which is shown as below: \arg OB_BB_DISABLE: boot from bank0 \arg OB_BB_ENABLE: boot from bank1 or bank0 if bank1 is void \param[out] none @@ -602,7 +694,7 @@ void ob_user_bor_threshold(uint32_t ob_bor_th) void ob_boot_mode_config(uint32_t boot_mode) { uint32_t reg; - + reg = FMC_OBCTL0; /* set option byte boot bank value */ reg &= ~FMC_OBCTL0_BB; @@ -613,7 +705,7 @@ void ob_boot_mode_config(uint32_t boot_mode) \brief get the FMC user option byte \param[in] none \param[out] none - \retval the FMC user option byte values: ob_fwdgt(Bit0), ob_deepsleep(Bit1), ob_stdby(Bit2). + \retval the FMC user option byte values: ob_fwdgt(Bit0), ob_deepsleep(Bit1), ob_stdby(Bit2) */ uint8_t ob_user_get(void) { @@ -677,7 +769,7 @@ uint16_t ob_drp1_get(void) FlagStatus ob_spc_get(void) { FlagStatus spc_state = RESET; - + if (((uint8_t)(FMC_OBCTL0 >> 8)) != (uint8_t)FMC_NSPC){ spc_state = SET; }else{ @@ -700,9 +792,10 @@ uint8_t ob_user_bor_threshold_get(void) /*! \brief enable FMC interrupt - \param[in] the FMC interrupt source - \arg FMC_INTEN_END: enable FMC end of program interrupt - \arg FMC_INTEN_ERR: enable FMC error interrupt + \param[in] fmc_int: the FMC interrupt source + only one parameter can be selected which is shown as below: + \arg FMC_INT_END: enable FMC end of program interrupt + \arg FMC_INT_ERR: enable FMC error interrupt \param[out] none \retval none */ @@ -713,9 +806,10 @@ void fmc_interrupt_enable(uint32_t fmc_int) /*! \brief disable FMC interrupt - \param[in] the FMC interrupt source - \arg FMC_INTEN_END: disable FMC end of program interrupt - \arg FMC_INTEN_ERR: disable FMC error interrupt + \param[in] fmc_int: the FMC interrupt source + only one parameter can be selected which is shown as below: + \arg FMC_INT_END: disable FMC end of program interrupt + \arg FMC_INT_ERR: disable FMC error interrupt \param[out] none \retval none */ @@ -727,12 +821,13 @@ void fmc_interrupt_disable(uint32_t fmc_int) /*! \brief get flag set or reset \param[in] fmc_flag: check FMC flag - \arg FMC_FLAG_BUSY: FMC busy flag + only one parameter can be selected which is shown as below: + \arg FMC_FLAG_BUSY: FMC busy flag bit \arg FMC_FLAG_RDDERR: FMC read D-bus protection error flag bit \arg FMC_FLAG_PGSERR: FMC program sequence error flag bit \arg FMC_FLAG_PGMERR: FMC program size not match error flag bit \arg FMC_FLAG_WPERR: FMC Erase/Program protection error flag bit - \arg FMC_FLAG_OPERR: FMC operation error flag bit + \arg FMC_FLAG_OPERR: FMC operation error flag bit \arg FMC_FLAG_END: FMC end of operation flag bit \param[out] none \retval FlagStatus: SET or RESET @@ -743,17 +838,18 @@ FlagStatus fmc_flag_get(uint32_t fmc_flag) return SET; } /* return the state of corresponding FMC flag */ - return RESET; + return RESET; } /*! \brief clear the FMC pending flag \param[in] FMC_flag: clear FMC flag + only one parameter can be selected which is shown as below: \arg FMC_FLAG_RDDERR: FMC read D-bus protection error flag bit \arg FMC_FLAG_PGSERR: FMC program sequence error flag bit \arg FMC_FLAG_PGMERR: FMC program size not match error flag bit \arg FMC_FLAG_WPERR: FMC erase/program protection error flag bit - \arg FMC_FLAG_OPERR: FMC operation error flag bit + \arg FMC_FLAG_OPERR: FMC operation error flag bit \arg FMC_FLAG_END: FMC end of operation flag bit \param[out] none \retval none @@ -768,23 +864,31 @@ void fmc_flag_clear(uint32_t fmc_flag) \brief get the FMC state \param[in] none \param[out] none - \retval fmc_state_enum + \retval state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_RDDERR: read D-bus protection error + \arg FMC_PGSERR: program sequence error + \arg FMC_PGMERR: program size not match error + \arg FMC_WPERR: erase/program protection error + \arg FMC_OPERR: operation error + \arg FMC_PGERR: program error */ fmc_state_enum fmc_state_get(void) { fmc_state_enum fmc_state = FMC_READY; - + if((FMC_STAT & FMC_FLAG_BUSY) == FMC_FLAG_BUSY){ fmc_state = FMC_BUSY; }else{ - if((FMC_STAT & FMC_FLAG_WPERR) != (uint32_t)0x00){ + if((FMC_STAT & FMC_FLAG_WPERR) != (uint32_t)0x00){ fmc_state = FMC_WPERR; }else{ - if((FMC_STAT & FMC_FLAG_RDDERR) != (uint32_t)0x00){ + if((FMC_STAT & FMC_FLAG_RDDERR) != (uint32_t)0x00){ fmc_state = FMC_RDDERR; }else{ if((FMC_STAT & (uint32_t)0xEF) != (uint32_t)0x00){ - fmc_state = FMC_PGERR; + fmc_state = FMC_PGERR; }else{ if((FMC_STAT & FMC_FLAG_OPERR) != (uint32_t)0x00){ fmc_state = FMC_OPERR; @@ -801,24 +905,28 @@ fmc_state_enum fmc_state_get(void) /*! \brief check whether FMC is ready or not - \param[in] count: FMC_TIMEOUT_COUNT + \param[in] none \param[out] none - \retval fmc_state_enum + \retval state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_RDDERR: read D-bus protection error + \arg FMC_PGSERR: program sequence error + \arg FMC_PGMERR: program size not match error + \arg FMC_WPERR: erase/program protection error + \arg FMC_OPERR: operation error + \arg FMC_PGERR: program error */ -fmc_state_enum fmc_ready_wait(uint32_t count) +fmc_state_enum fmc_ready_wait(void) { fmc_state_enum fmc_state = FMC_BUSY; - + /* wait for FMC ready */ do{ /* get FMC state */ fmc_state = fmc_state_get(); - count--; - }while((FMC_BUSY == fmc_state) && ((uint32_t)RESET != count)); - - if(FMC_BUSY == fmc_state){ - fmc_state = FMC_TOERR; - } + }while(FMC_BUSY == fmc_state); + /* return the FMC state */ return fmc_state; } diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_fwdgt.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_fwdgt.c index 4762344417..04e2c5b99d 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_fwdgt.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_fwdgt.c @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_fwdgt.c - \brief FWDGT driver + \file gd32f4xx_fwdgt.c + \brief FWDGT driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_fwdgt.h" @@ -16,6 +41,17 @@ /* write value to FWDGT_RLD_RLD bit field */ #define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) +/*! + \brief enable write access to FWDGT_PSC and FWDGT_RLD + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_write_enable(void) +{ + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; +} + /*! \brief disable write access to FWDGT_PSC and FWDGT_RLD \param[in] none @@ -27,6 +63,17 @@ void fwdgt_write_disable(void) FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE; } +/*! + \brief start the free watchdog timer counter + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_enable(void) +{ + FWDGT_CTL = FWDGT_KEY_ENABLE; +} + /*! \brief reload the counter of FWDGT \param[in] none @@ -38,22 +85,11 @@ void fwdgt_counter_reload(void) FWDGT_CTL = FWDGT_KEY_RELOAD; } -/*! - \brief start the free watchdog timer counter - \param[in] none - \param[out] none - \retval none -*/ -void fwdgt_enable(void) -{ - FWDGT_CTL = FWDGT_KEY_ENABLE; -} - - /*! \brief configure counter reload value, and prescaler divider value \param[in] reload_value: specify reload value(0x0000 - 0x0FFF) \param[in] prescaler_div: FWDGT prescaler value + only one parameter can be selected which is shown as below: \arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4 \arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8 \arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16 @@ -68,15 +104,15 @@ ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div) { uint32_t timeout = FWDGT_PSC_TIMEOUT; uint32_t flag_status = RESET; - + /* enable write access to FWDGT_PSC,and FWDGT_RLD */ FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; - + /* wait until the PUD flag to be reset */ do{ flag_status = FWDGT_STAT & FWDGT_STAT_PUD; }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); - + if ((uint32_t)RESET != flag_status){ return ERROR; } @@ -89,13 +125,13 @@ ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div) do{ flag_status = FWDGT_STAT & FWDGT_STAT_RUD; }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); - + if ((uint32_t)RESET != flag_status){ return ERROR; } - + FWDGT_RLD = RLD_RLD(reload_value); - + /* reload the counter */ FWDGT_CTL = FWDGT_KEY_RELOAD; @@ -104,7 +140,8 @@ ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div) /*! \brief get flag state of FWDGT - \param[in] flag: flag to get + \param[in] flag: flag to get + only one parameter can be selected which is shown as below: \arg FWDGT_STAT_PUD: a write operation to FWDGT_PSC register is on going \arg FWDGT_STAT_RUD: a write operation to FWDGT_RLD register is on going \param[out] none @@ -112,7 +149,7 @@ ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div) */ FlagStatus fwdgt_flag_get(uint16_t flag) { - if(FWDGT_STAT & flag){ + if(RESET != (FWDGT_STAT & flag)){ return SET; } diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_gpio.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_gpio.c index ccce538926..d3693abb17 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_gpio.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_gpio.c @@ -1,19 +1,46 @@ /*! - \file gd32f4xx_gpio.c - \brief GPIO driver + \file gd32f4xx_gpio.c + \brief GPIO driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_gpio.h" /*! \brief reset GPIO port - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) \param[out] none \retval none */ @@ -71,22 +98,26 @@ void gpio_deinit(uint32_t gpio_periph) } /*! - \brief set GPIO output mode - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,I) - \param[in] mode: gpio pin mode + \brief set GPIO mode + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] mode: GPIO pin mode \arg GPIO_MODE_INPUT: input mode \arg GPIO_MODE_OUTPUT: output mode \arg GPIO_MODE_AF: alternate function mode \arg GPIO_MODE_ANALOG: analog mode - \param[in] pull_up_down: gpio pin with pull-up or pull-down resistor - \arg GPIO_PUPD_NONE: without weak pull-up and pull-down resistors - \arg GPIO_PUPD_PULLUP: with weak pull-up resistor - \arg GPIO_PUPD_PULLDOWN:with weak pull-down resistor - \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[in] pull_up_down: GPIO pin with pull-up or pull-down resistor + \arg GPIO_PUPD_NONE: floating mode, no pull-up and pull-down resistors + \arg GPIO_PUPD_PULLUP: with pull-up resistor + \arg GPIO_PUPD_PULLDOWN:with pull-down resistor + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL \param[out] none \retval none */ -void gpio_mode_set(uint32_t gpio_periph,uint32_t mode,uint32_t pull_up_down,uint32_t pin) +void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, uint32_t pin) { uint16_t i; uint32_t ctl, pupd; @@ -114,25 +145,29 @@ void gpio_mode_set(uint32_t gpio_periph,uint32_t mode,uint32_t pull_up_down,uint /*! \brief set GPIO output type and speed - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,I) - \param[in] otype: gpio pin output mode + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] otype: GPIO pin output mode \arg GPIO_OTYPE_PP: push pull mode \arg GPIO_OTYPE_OD: open drain mode - \param[in] speed: gpio pin output max speed - \arg GPIO_OSPEED_2MHZ: output max speed 2M - \arg GPIO_OSPEED_25MHZ: output max speed 25M - \arg GPIO_OSPEED_50MHZ: output max speed 50M - \arg GPIO_OSPEED_200MHZ: output max speed 200M - \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[in] speed: GPIO pin output max speed + \arg GPIO_OSPEED_2MHZ: output max speed 2MHz + \arg GPIO_OSPEED_25MHZ: output max speed 25MHz + \arg GPIO_OSPEED_50MHZ: output max speed 50MHz + \arg GPIO_OSPEED_200MHZ: output max speed 200MHz + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL \param[out] none \retval none */ -void gpio_output_options_set(uint32_t gpio_periph,uint8_t otype,uint32_t speed,uint32_t pin) +void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin) { uint16_t i; uint32_t ospeedr; - if(0x1U == otype){ + if(GPIO_OTYPE_OD == otype){ GPIO_OMODE(gpio_periph) |= (uint32_t)pin; }else{ GPIO_OMODE(gpio_periph) &= (uint32_t)(~pin); @@ -153,40 +188,52 @@ void gpio_output_options_set(uint32_t gpio_periph,uint8_t otype,uint32_t speed,u } /*! - \brief set GPIO pin - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,I) - \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \brief set GPIO pin bit + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL \param[out] none \retval none */ -void gpio_bit_set(uint32_t gpio_periph,uint32_t pin) +void gpio_bit_set(uint32_t gpio_periph, uint32_t pin) { GPIO_BOP(gpio_periph) = (uint32_t)pin; } /*! - \brief reset GPIO pin - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,I) - \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \brief reset GPIO pin bit + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL \param[out] none \retval none */ -void gpio_bit_reset(uint32_t gpio_periph,uint32_t pin) +void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin) { GPIO_BC(gpio_periph) = (uint32_t)pin; } /*! \brief write data to the specified GPIO pin - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,I) - \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[in] bitvalue: SET or RESET + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[in] bit_value: SET or RESET \arg RESET: clear the port pin \arg SET: set the port pin \param[out] none \retval none */ -void gpio_bit_write(uint32_t gpio_periph,uint32_t pin,bit_status bit_value) +void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value) { if(RESET != bit_value){ GPIO_BOP(gpio_periph) = (uint32_t)pin; @@ -197,27 +244,33 @@ void gpio_bit_write(uint32_t gpio_periph,uint32_t pin,bit_status bit_value) /*! \brief write data to the specified GPIO port - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,I) - \param[in] data: specify the value to be written to the port output data register + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] data: specify the value to be written to the port output control register \param[out] none \retval none */ -void gpio_port_write(uint32_t gpio_periph,uint16_t data) +void gpio_port_write(uint32_t gpio_periph, uint16_t data) { GPIO_OCTL(gpio_periph) = (uint32_t)data; } /*! \brief get GPIO pin input status - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,I) - \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL \param[out] none - \retval input state of gpio pin: SET or RESET + \retval input status of GPIO pin: SET or RESET */ -FlagStatus gpio_input_bit_get(uint32_t gpio_periph,uint32_t pin) +FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin) { if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph)&(pin))){ - return SET; + return SET; }else{ return RESET; } @@ -225,23 +278,29 @@ FlagStatus gpio_input_bit_get(uint32_t gpio_periph,uint32_t pin) /*! \brief get GPIO all pins input status - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) \param[out] none - \retval input state of gpio all pins + \retval input status of GPIO all pins */ uint16_t gpio_input_port_get(uint32_t gpio_periph) { - return (uint16_t)(GPIO_ISTAT(gpio_periph)); + return ((uint16_t)GPIO_ISTAT(gpio_periph)); } /*! \brief get GPIO pin output status - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,I) - \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL \param[out] none - \retval output state of gpio pin: SET or RESET + \retval output status of GPIO pin: SET or RESET */ -FlagStatus gpio_output_bit_get(uint32_t gpio_periph,uint32_t pin) +FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin) { if((uint32_t)RESET !=(GPIO_OCTL(gpio_periph)&(pin))){ return SET; @@ -252,9 +311,11 @@ FlagStatus gpio_output_bit_get(uint32_t gpio_periph,uint32_t pin) /*! \brief get GPIO all pins output status - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) \param[out] none - \retval output state of gpio all pins + \retval output status of GPIO all pins */ uint16_t gpio_output_port_get(uint32_t gpio_periph) { @@ -263,29 +324,33 @@ uint16_t gpio_output_port_get(uint32_t gpio_periph) /*! \brief set GPIO alternate function - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,I) - \param[in] alt_func_num: gpio pin af function + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] alt_func_num: GPIO pin af function \arg GPIO_AF_0: SYSTEM \arg GPIO_AF_1: TIMER0, TIMER1 \arg GPIO_AF_2: TIMER2, TIMER3, TIMER4 \arg GPIO_AF_3: TIMER7, TIMER8, TIMER9, TIMER10 \arg GPIO_AF_4: I2C0, I2C1, I2C2 \arg GPIO_AF_5: SPI0, SPI1, SPI2, SPI3, SPI4, SPI5 - \arg GPIO_AF_6: SPI1, SPI2, SAI0 + \arg GPIO_AF_6: SPI1, SPI2, SAI0 \arg GPIO_AF_7: USART0, USART1, USART2 \arg GPIO_AF_8: UART3, UART4, USART5, UART6, UART7 - \arg GPIO_AF_9: CAN0,CAN1, TLI, TIMER11, TIMER12, TIMER13 + \arg GPIO_AF_9: CAN0, CAN1, TLI, TIMER11, TIMER12, TIMER13 \arg GPIO_AF_10: USB_FS, USB_HS \arg GPIO_AF_11: ENET - \arg GPIO_AF_12: FMC, SDIO, USB_HS + \arg GPIO_AF_12: EXMC, SDIO, USB_HS \arg GPIO_AF_13: DCI \arg GPIO_AF_14: TLI \arg GPIO_AF_15: EVENTOUT - \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL \param[out] none \retval none */ -void gpio_af_set(uint32_t gpio_periph,uint32_t alt_func_num,uint32_t pin) +void gpio_af_set(uint32_t gpio_periph, uint32_t alt_func_num, uint32_t pin) { uint16_t i; uint32_t afrl, afrh; @@ -314,18 +379,22 @@ void gpio_af_set(uint32_t gpio_periph,uint32_t alt_func_num,uint32_t pin) } /*! - \brief lock GPIO pin - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,I) - \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \brief lock GPIO pin bit + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL \param[out] none \retval none */ -void gpio_pin_lock(uint32_t gpio_periph,uint32_t pin) +void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin) { uint32_t lock = 0x00010000U; lock |= pin; - /* lock key writing sequence: write 1->write 0->write 1-> read 0-> read 1 */ + /* lock key writing sequence: write 1->write 0->write 1->read 0->read 1 */ GPIO_LOCK(gpio_periph) = (uint32_t)lock; GPIO_LOCK(gpio_periph) = (uint32_t)pin; GPIO_LOCK(gpio_periph) = (uint32_t)lock; @@ -334,20 +403,27 @@ void gpio_pin_lock(uint32_t gpio_periph,uint32_t pin) } /*! - \brief toggle GPIO pin - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,I) - \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \brief toggle GPIO pin status + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL \param[out] none \retval none */ -void gpio_bit_toggle(uint32_t gpio_periph,uint32_t pin) +void gpio_bit_toggle(uint32_t gpio_periph, uint32_t pin) { GPIO_TG(gpio_periph) = (uint32_t)pin; } /*! - \brief toggle GPIO port - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,I) + \brief toggle GPIO port status + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[out] none \retval none */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_i2c.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_i2c.c index 79480b63e5..c3ac50c178 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_i2c.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_i2c.c @@ -1,19 +1,51 @@ /*! - \file gd32f4xx_i2c.c - \brief I2C driver + \file gd32f4xx_i2c.c + \brief I2C driver + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2019-04-16, V2.0.2, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_i2c.h" -#define I2CCLK_MAX 0x3fU /*!< i2cclk max value */ -#define I2C_STATE_MASK 0x0000FFFFU /*!< i2c state mask */ +/* I2C register bit mask */ +#define I2CCLK_MAX ((uint32_t)0x00000032U) /*!< i2cclk maximum value */ +#define I2CCLK_MIN ((uint32_t)0x00000002U) /*!< i2cclk minimum value */ +#define I2C_FLAG_MASK ((uint32_t)0x0000FFFFU) /*!< i2c flag mask */ +#define I2C_ADDRESS_MASK ((uint32_t)0x000003FFU) /*!< i2c address mask */ +#define I2C_ADDRESS2_MASK ((uint32_t)0x000000FEU) /*!< the second i2c address mask */ + +/* I2C register bit offset */ +#define STAT1_PECV_OFFSET ((uint32_t)8U) /* bit offset of PECV in I2C_STAT1 */ /*! \brief reset I2C @@ -25,202 +57,229 @@ void i2c_deinit(uint32_t i2c_periph) { switch(i2c_periph){ case I2C0: + /* reset I2C0 */ rcu_periph_reset_enable(RCU_I2C0RST); rcu_periph_reset_disable(RCU_I2C0RST); break; case I2C1: + /* reset I2C1 */ rcu_periph_reset_enable(RCU_I2C1RST); rcu_periph_reset_disable(RCU_I2C1RST); break; case I2C2: + /* reset I2C2 */ rcu_periph_reset_enable(RCU_I2C2RST); rcu_periph_reset_disable(RCU_I2C2RST); break; default: break; - } } /*! - \brief I2C clock configure + \brief configure I2C clock \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] clkspeed: i2c clock speed + \param[in] clkspeed: I2C clock speed, supports standard mode (up to 100 kHz), fast mode (up to 400 kHz) \param[in] dutycyc: duty cycle in fast mode - \arg I2C_DTCY_2: T_low/T_high=2 + only one parameter can be selected which is shown as below: + \arg I2C_DTCY_2: T_low/T_high=2 \arg I2C_DTCY_16_9: T_low/T_high=16/9 \param[out] none \retval none */ -void i2c_clock_config(uint32_t i2c_periph,uint32_t clkspeed,uint32_t dutycyc) +void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc) { - uint32_t pclk1,clkc,i2cclk,risetime; + uint32_t pclk1, clkc, freq, risetime; + uint32_t temp; + pclk1 = rcu_clock_freq_get(CK_APB1); - /* I2C Peripheral clock frequency */ - i2cclk=((pclk1)/(uint32_t)(1000000)); - if(i2cclk >= I2CCLK_MAX){ - i2cclk = I2CCLK_MAX; + /* I2C peripheral clock frequency */ + freq = (uint32_t)(pclk1/1000000U); + if(freq >= I2CCLK_MAX){ + freq = I2CCLK_MAX; } - - I2C_CTL1(i2c_periph) |= (I2C_CTL1_I2CCLK & i2cclk) ; - + temp = I2C_CTL1(i2c_periph); + temp &= ~I2C_CTL1_I2CCLK; + temp |= freq; + + I2C_CTL1(i2c_periph) = temp; + if(100000U >= clkspeed){ - /* standard mode the maximum SCL rise time in standard mode is 1000ns */ + /* the maximum SCL rise time is 1000ns in standard mode */ risetime = (uint32_t)((pclk1/1000000U)+1U); if(risetime >= I2CCLK_MAX){ - I2C_RT(i2c_periph) |= I2CCLK_MAX; + I2C_RT(i2c_periph) = I2CCLK_MAX; }else{ - I2C_RT(i2c_periph) |= (uint32_t)((pclk1/1000000U)+1U); + I2C_RT(i2c_periph) = risetime; } clkc = (uint32_t)(pclk1/(clkspeed*2U)); if(clkc < 0x04U){ - /* The CLKC in standard mode minmum value is 4*/ + /* the CLKC in standard mode minmum value is 4 */ clkc = 0x04U; } - I2C_CKCFG(i2c_periph) |= (I2C_CKCFG_CLKC & clkc); - }else{ - /* fast mode the maximum SCL rise time in standard mode is 300ns */ - I2C_RT(i2c_periph) |= (uint16_t)(((i2cclk*(uint16_t)300)/(uint16_t)1000)+(uint16_t)1); + I2C_CKCFG(i2c_periph) |= (I2C_CKCFG_CLKC & clkc); + + }else if(400000U >= clkspeed){ + /* the maximum SCL rise time is 300ns in fast mode */ + I2C_RT(i2c_periph) = (uint32_t)(((freq*(uint32_t)300U)/(uint32_t)1000U)+(uint32_t)1U); if(I2C_DTCY_2 == dutycyc){ - /* I2C_DutyCycle == 2 */ - clkc = (uint16_t)(pclk1/(clkspeed*3U)); - } else{ - /* I2C_DutyCycle == 16/9 */ - clkc = (uint16_t)(pclk1/(clkspeed*25U)); + /* I2C duty cycle is 2 */ + clkc = (uint32_t)(pclk1/(clkspeed*3U)); + I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY; + }else{ + /* I2C duty cycle is 16/9 */ + clkc = (uint32_t)(pclk1/(clkspeed*25U)); I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY; } - if((clkc & I2C_CKCFG_CLKC) == 0U){ - /* The CLKC in standard mode minmum value is 1*/ - clkc |= (uint16_t)0x0001; + if(0U == (clkc & I2C_CKCFG_CLKC)){ + /* the CLKC in fast mode minmum value is 1 */ + clkc |= 0x0001U; } + I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST; I2C_CKCFG(i2c_periph) |= clkc; + }else{ } } /*! - \brief I2C address configure + \brief configure I2C address \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] i2cmod: - \arg I2C_I2CMODE_ENABLE: I2C mode + \param[in] mode: + only one parameter can be selected which is shown as below: + \arg I2C_I2CMODE_ENABLE: I2C mode \arg I2C_SMBUSMODE_ENABLE: SMBus mode \param[in] addformat: 7bits or 10bits - \arg I2C_ADDFORMAT_7BITS: 7bits + only one parameter can be selected which is shown as below: + \arg I2C_ADDFORMAT_7BITS: 7bits \arg I2C_ADDFORMAT_10BITS: 10bits \param[in] addr: I2C address \param[out] none \retval none */ -void i2c_mode_addr_config(uint32_t i2c_periph,uint32_t i2cmod,uint32_t addformat,uint32_t addr) +void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr) { /* SMBus/I2C mode selected */ uint32_t ctl = 0U; + ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_SMBEN); - ctl |= i2cmod; + ctl &= ~(I2C_CTL0_SMBEN); + ctl |= mode; I2C_CTL0(i2c_periph) = ctl; /* configure address */ - I2C_SADDR0(i2c_periph) = (addformat|addr); - + addr = addr & I2C_ADDRESS_MASK; + I2C_SADDR0(i2c_periph) = (addformat | addr); } /*! \brief SMBus type selection \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] ack: + \param[in] type: + only one parameter can be selected which is shown as below: \arg I2C_SMBUS_DEVICE: device \arg I2C_SMBUS_HOST: host \param[out] none \retval none */ -void i2c_smbus_type_config(uint32_t i2c_periph,uint32_t type) +void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type) { if(I2C_SMBUS_HOST == type){ - I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBSEL; + I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBSEL; }else{ - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_SMBSEL); - } + I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_SMBSEL); + } } /*! \brief whether or not to send an ACK \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] ack: - \arg I2C_ACK_ENABLE: ACK will be sent - \arg I2C_ACK_DISABLE: ACK will not be sent - \param[out] none - \retval none -*/ -void i2c_ack_config(uint32_t i2c_periph,uint8_t ack) -{ - if(I2C_ACK_ENABLE == ack){ - I2C_CTL0(i2c_periph) |= I2C_CTL0_ACKEN; - }else{ - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_ACKEN); - } -} - -/*! - \brief I2C POAP position configure - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] pos: - \arg I2C_ACK_ENABLE: ACK will be sent + only one parameter can be selected which is shown as below: + \arg I2C_ACK_ENABLE: ACK will be sent \arg I2C_ACK_DISABLE: ACK will not be sent \param[out] none \retval none */ -void i2c_ackpos_config(uint32_t i2c_periph,uint8_t pos) +void i2c_ack_config(uint32_t i2c_periph, uint32_t ack) { - /* configure i2c POAP position */ - if(I2C_ACKPOS_NEXT == pos){ - I2C_CTL0(i2c_periph) |= I2C_CTL0_POAP; + if(I2C_ACK_ENABLE == ack){ + I2C_CTL0(i2c_periph) |= I2C_CTL0_ACKEN; }else{ - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_POAP); - } - + I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_ACKEN); + } } /*! - \brief master send slave address + \brief configure I2C POAP position \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] addr: slave address - \param[in] trandirection: transmitter or receiver - \arg I2C_TRANSMITTER: transmitter - \arg I2C_RECEIVER: receiver + \param[in] pos: + only one parameter can be selected which is shown as below: + \arg I2C_ACKPOS_CURRENT: whether to send ACK or not for the current + \arg I2C_ACKPOS_NEXT: whether to send ACK or not for the next byte \param[out] none \retval none */ -void i2c_master_addressing(uint32_t i2c_periph,uint8_t addr,uint32_t trandirection) +void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos) { - if(I2C_TRANSMITTER==trandirection){ - addr = (uint8_t)((uint32_t)addr & I2C_TRANSMITTER); + /* configure I2C POAP position */ + if(I2C_ACKPOS_NEXT == pos){ + I2C_CTL0(i2c_periph) |= I2C_CTL0_POAP; }else{ - addr = (uint8_t)((uint32_t)addr|I2C_RECEIVER); + I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_POAP); } +} + +/*! + \brief master sends slave address + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] addr: slave address + \param[in] trandirection: transmitter or receiver + only one parameter can be selected which is shown as below: + \arg I2C_TRANSMITTER: transmitter + \arg I2C_RECEIVER: receiver + \param[out] none + \retval none +*/ +void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection) +{ + /* master is a transmitter or a receiver */ + if(I2C_TRANSMITTER == trandirection){ + addr = addr & I2C_TRANSMITTER; + }else{ + addr = addr | I2C_RECEIVER; + } + /* send slave address */ I2C_DATA(i2c_periph) = addr; } /*! - \brief dual-address mode switch + \brief enable dual-address mode \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] dualaddr: - \arg I2C_DUADEN_DISABLE: dual-address mode disabled - \arg I2C_DUADEN_ENABLE: dual-address mode enabled + \param[in] addr: the second address in dual-address mode \param[out] none \retval none */ -void i2c_dualaddr_enable(uint32_t i2c_periph,uint8_t dualaddr) +void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr) { - if(I2C_DUADEN_ENABLE == dualaddr){ - I2C_SADDR1(i2c_periph) |= I2C_SADDR1_DUADEN; - }else{ - I2C_SADDR1(i2c_periph) &= ~(I2C_SADDR1_DUADEN); - } + /* configure address */ + addr = addr & I2C_ADDRESS2_MASK; + I2C_SADDR1(i2c_periph) = (I2C_SADDR1_DUADEN | addr); } /*! - \brief enable i2c - \param[in] i2c_periph: I2Cx(x=0,1,2) + \brief disable dual-address mode + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[out] none + \retval none +*/ +void i2c_dualaddr_disable(uint32_t i2c_periph) +{ + I2C_SADDR1(i2c_periph) &= ~(I2C_SADDR1_DUADEN); +} + +/*! + \brief enable I2C + \param[in] i2c_periph: I2Cx(x=0,1,2) \param[out] none \retval none */ @@ -230,15 +289,14 @@ void i2c_enable(uint32_t i2c_periph) } /*! - \brief disable i2c - \param[in] i2c_periph: I2Cx(x=0,1,2) + \brief disable I2C + \param[in] i2c_periph: I2Cx(x=0,1,2) \param[out] none \retval none */ void i2c_disable(uint32_t i2c_periph) { I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_I2CEN); - } /*! @@ -264,91 +322,96 @@ void i2c_stop_on_bus(uint32_t i2c_periph) } /*! - \brief i2c transmit data function + \brief I2C transmit data function \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] data: data of transmission + \param[in] data: data of transmission \param[out] none \retval none */ -void i2c_transmit_data(uint32_t i2c_periph,uint8_t data) +void i2c_data_transmit(uint32_t i2c_periph, uint8_t data) { - I2C_DATA(i2c_periph) = data; + I2C_DATA(i2c_periph) = DATA_TRANS(data); } /*! - \brief i2c receive data function + \brief I2C receive data function \param[in] i2c_periph: I2Cx(x=0,1,2) \param[out] none \retval data of received */ -uint8_t i2c_receive_data(uint32_t i2c_periph) +uint8_t i2c_data_receive(uint32_t i2c_periph) { - return (uint8_t)I2C_DATA(i2c_periph); + return (uint8_t)DATA_RECV(I2C_DATA(i2c_periph)); } /*! - \brief I2C DMA mode enable + \brief enable I2C DMA mode \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] dmastste: - \arg I2C_DMA_ON: DMA mode enabled - \arg I2C_DMA_OFF: DMA mode disabled + \param[in] dmastate: + only one parameter can be selected which is shown as below: + \arg I2C_DMA_ON: DMA mode enable + \arg I2C_DMA_OFF: DMA mode disable \param[out] none \retval none */ -void i2c_dma_enable(uint32_t i2c_periph,uint32_t dmastste) +void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate) { - /* configure i2c DMA function */ + /* configure I2C DMA function */ uint32_t ctl = 0U; - ctl = I2C_CTL1(i2c_periph); - ctl &= ~(I2C_CTL1_DMAON); - ctl |= dmastste; - I2C_CTL1(i2c_periph) = ctl; + ctl = I2C_CTL1(i2c_periph); + ctl &= ~(I2C_CTL1_DMAON); + ctl |= dmastate; + I2C_CTL1(i2c_periph) = ctl; } /*! - \brief flag indicating DMA last transfer + \brief configure whether next DMA EOT is DMA last transfer or not \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] dmastste: + \param[in] dmalast: + only one parameter can be selected which is shown as below: \arg I2C_DMALST_ON: next DMA EOT is the last transfer \arg I2C_DMALST_OFF: next DMA EOT is not the last transfer \param[out] none \retval none */ -void i2c_dma_last_transfer_enable(uint32_t i2c_periph,uint32_t dmalast) +void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast) { /* configure DMA last transfer */ uint32_t ctl = 0U; + ctl = I2C_CTL1(i2c_periph); - ctl &= ~(I2C_CTL1_DMALST); + ctl &= ~(I2C_CTL1_DMALST); ctl |= dmalast; I2C_CTL1(i2c_periph) = ctl; - } /*! - \brief whether to stretch SCL low when data is not ready in slave mode + \brief whether to stretch SCL low when data is not ready in slave mode \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] stretchpara: + only one parameter can be selected which is shown as below: \arg I2C_SCLSTRETCH_ENABLE: SCL stretching is enabled \arg I2C_SCLSTRETCH_DISABLE: SCL stretching is disabled \param[out] none \retval none */ -void i2c_stretch_scl_low_config(uint32_t i2c_periph,uint32_t stretchpara) +void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara) { /* configure I2C SCL strerching enable or disable */ uint32_t ctl = 0U; + ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_DISSTRC); + ctl &= ~(I2C_CTL0_SS); ctl |= stretchpara; I2C_CTL0(i2c_periph) = ctl; } /*! - \brief whether or not to response to a general Cal + \brief whether or not to response to a general call \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] gcallpara: + only one parameter can be selected which is shown as below: \arg I2C_GCEN_ENABLE: slave will response to a general call \arg I2C_GCEN_DISABLE: slave will not response to a general call \param[out] none @@ -358,16 +421,18 @@ void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara) { /* configure slave response to a general call enable or disable */ uint32_t ctl = 0U; + ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_GCEN); + ctl &= ~(I2C_CTL0_GCEN); ctl |= gcallpara; I2C_CTL0(i2c_periph) = ctl; } /*! - \brief software reset I2C + \brief software reset I2C \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] sreset: + only one parameter can be selected which is shown as below: \arg I2C_SRESET_SET: I2C is under reset \arg I2C_SRESET_RESET: I2C is not under reset \param[out] none @@ -377,134 +442,30 @@ void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset) { /* modify CTL0 and configure software reset I2C state */ uint32_t ctl = 0U; + ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_SRESET); + ctl &= ~(I2C_CTL0_SRESET); ctl |= sreset; I2C_CTL0(i2c_periph) = ctl; } -/*! - \brief check i2c state - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] state: - \arg I2C_SBSEND: start condition send out - \arg I2C_ADDSEND: address is sent in master mode or received and matches in slave mode - \arg I2C_BTC: byte transmission finishes - \arg I2C_ADD10SEND: header of 10-bit address is sent in master mode - \arg I2C_STPDET: etop condition detected in slave mode - \arg I2C_RBNE: I2C_DATA is not Empty during receiving - \arg I2C_TBE: I2C_DATA is empty during transmitting - \arg I2C_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus - \arg I2C_LOSTARB: arbitration lost in master mode - \arg I2C_AERR: acknowledge error - \arg I2C_OUERR: over-run or under-run situation occurs in slave mode - \arg I2C_PECERR: PEC error when receiving data - \arg I2C_SMBTO: timeout signal in SMBus mode - \arg I2C_SMBALT: SMBus alert status - \arg I2C_MASTER: a flag indicating whether I2C block is in master or slave mode - \arg I2C_I2CBSY: busy flag - \arg I2C_TRS: whether the I2C is a transmitter or a receiver - \arg I2C_RXGC: general call address (00h) received - \arg I2C_DEFSMB: default address of SMBus device - \arg I2C_HSTSMB: SMBus host header detected in slave mode - \arg I2C_DUMODF: dual flag in slave mode indicating which address is matched in dual-address mode - \param[out] none - \retval state of i2c -*/ -FlagStatus i2c_flag_get(uint32_t i2c_periph,uint32_t state ) -{ - uint32_t reg = 0U; - FlagStatus regstate = RESET; - /* get the state in which register */ - reg = (BIT(31) & state); - if((BIT(31) == reg)){ - if((I2C_STAT1(i2c_periph)&(state & I2C_STATE_MASK))){ - regstate = SET; - }else{ - regstate = RESET; - } - }else{ - if((I2C_STAT0(i2c_periph)&(state & I2C_STATE_MASK))){ - regstate = SET; - }else{ - regstate = RESET; - } - } - /* return the state */ - return regstate; -} - -/*! - \brief clear i2c state - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] state: state type - \@arg I2C_STAT0_SMBALT: SMBus Alert status - \@arg I2C_STAT0_SMBTO: timeout signal in SMBus mode - \@arg I2C_STAT0_PECERR: PEC error when receiving data - \@arg I2C_STAT0_OUERR: over-run or under-run situation occurs in slave mode - \@arg I2C_STAT0_AERR: acknowledge error - \@arg I2C_STAT0_LOSTARB: arbitration lost in master mode - \@arg I2C_STAT0_BERR: a bus error - \@arg I2C_STAT0_ADDSEND: cleared by reading I2C_STAT0 and reading I2C_STAT1 - \param[out] none - \retval none -*/ -void i2c_flag_clear(uint32_t i2c_periph,uint32_t state) -{ - if(I2C_STAT0_ADDSEND == state){ - /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ - I2C_STAT0(i2c_periph); - I2C_STAT1(i2c_periph); - }else{ - I2C_STAT0(i2c_periph) &= ~(state); - } -} - -/*! - \brief enable i2c interrupt - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] inttype: interrupt type - \arg I2C_CTL1_ERRIE: error interrupt enable - \arg I2C_CTL1_EVIE: event interrupt enable - \arg I2C_CTL1_BUFIE: buffer interrupt enable - \param[out] none - \retval none -*/ -void i2c_interrupt_enable(uint32_t i2c_periph,uint32_t inttype) -{ - I2C_CTL1(i2c_periph) |= (inttype); -} - -/*! - \brief disable i2c interrupt - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] inttype: interrupt type - \arg I2C_CTL1_ERRIE: error interrupt enable - \arg I2C_CTL1_EVIE: event interrupt enable - \arg I2C_CTL1_BUFIE: buffer interrupt enable - \param[out] none - \retval none -*/ -void i2c_interrupt_disable(uint32_t i2c_periph,uint32_t inttype) -{ - I2C_CTL1(i2c_periph) &= ~(inttype); -} - /*! \brief I2C PEC calculation on or off \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] pecpara: - \arg I2C_PEC_ENABLE: PEC calculation on - \arg I2C_PEC_DISABLE: PEC calculation off + \param[in] pecstate: + only one parameter can be selected which is shown as below: + \arg I2C_PEC_ENABLE: PEC calculation on + \arg I2C_PEC_DISABLE: PEC calculation off \param[out] none \retval none */ -void i2c_pec_enable(uint32_t i2c_periph,uint32_t pecstate) +void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate) { /* on/off PEC calculation */ uint32_t ctl = 0U; + ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_PECEN); + ctl &= ~(I2C_CTL0_PECEN); ctl |= pecstate; I2C_CTL0(i2c_periph) = ctl; } @@ -513,66 +474,72 @@ void i2c_pec_enable(uint32_t i2c_periph,uint32_t pecstate) \brief I2C whether to transfer PEC value \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] pecpara: - \arg I2C_PECTRANS_ENABLE: transfer PEC - \arg I2C_PECTRANS_DISABLE: not transfer PEC + only one parameter can be selected which is shown as below: + \arg I2C_PECTRANS_ENABLE: transfer PEC + \arg I2C_PECTRANS_DISABLE: not transfer PEC \param[out] none \retval none */ -void i2c_pec_transfer_enable(uint32_t i2c_periph,uint32_t pecpara) +void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara) { /* whether to transfer PEC */ uint32_t ctl = 0U; + ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_PECTRANS); + ctl &= ~(I2C_CTL0_PECTRANS); ctl |= pecpara; I2C_CTL0(i2c_periph) = ctl; } /*! - \brief packet error checking value + \brief get packet error checking value \param[in] i2c_periph: I2Cx(x=0,1,2) \param[out] none \retval PEC value */ -uint8_t i2c_pec_value(uint32_t i2c_periph) +uint8_t i2c_pec_value_get(uint32_t i2c_periph) { - return (uint8_t)((I2C_STAT1(i2c_periph) &I2C_STAT1_ECV)>>8); + return (uint8_t)((I2C_STAT1(i2c_periph) & I2C_STAT1_PECV)>>STAT1_PECV_OFFSET); } /*! - \brief I2C issue alert through SMBA pin + \brief I2C issue alert through SMBA pin \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] smbuspara: - \arg I2C_SALTSEND_ENABLE: issue alert through SMBA pin - \arg I2C_SALTSEND_DISABLE: not issue alert through SMBA pin + only one parameter can be selected which is shown as below: + \arg I2C_SALTSEND_ENABLE: issue alert through SMBA pin + \arg I2C_SALTSEND_DISABLE: not issue alert through SMBA pin \param[out] none \retval none */ -void i2c_smbus_alert_issue(uint32_t i2c_periph,uint32_t smbuspara) +void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara) { /* issue alert through SMBA pin configure*/ uint32_t ctl = 0U; + ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_SALT); + ctl &= ~(I2C_CTL0_SALT); ctl |= smbuspara; I2C_CTL0(i2c_periph) = ctl; } /*! - \brief I2C ARP protocol in SMBus switch enable or disable + \brief enable or disable I2C ARP protocol in SMBus switch \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] smbuspara: - \arg I2C_ARP_ENABLE: ARP is enabled - \arg I2C_ARP_DISABLE: ARP is disabled + \param[in] arpstate: + only one parameter can be selected which is shown as below: + \arg I2C_ARP_ENABLE: enable ARP + \arg I2C_ARP_DISABLE: disable ARP \param[out] none \retval none */ -void i2c_smbus_arp_enable(uint32_t i2c_periph,uint32_t arpstate) +void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate) { /* enable or disable I2C ARP protocol*/ uint32_t ctl = 0U; + ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_ARPEN); + ctl &= ~(I2C_CTL0_ARPEN); ctl |= arpstate; I2C_CTL0(i2c_periph) = ctl; } @@ -585,7 +552,7 @@ void i2c_smbus_arp_enable(uint32_t i2c_periph,uint32_t arpstate) */ void i2c_analog_noise_filter_disable(uint32_t i2c_periph) { - I2C_FCTL(i2c_periph) |= I2C_FCTL_AFD; + I2C_FCTL(i2c_periph) |= I2C_FCTL_AFD; } /*! @@ -596,19 +563,19 @@ void i2c_analog_noise_filter_disable(uint32_t i2c_periph) */ void i2c_analog_noise_filter_enable(uint32_t i2c_periph) { - I2C_FCTL(i2c_periph) &= ~(I2C_FCTL_AFD); + I2C_FCTL(i2c_periph) &= ~(I2C_FCTL_AFD); } /*! \brief digital noise filter configuration \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] dfilterpara: refer to enum i2c_gcall_config_enum + \param[in] dfilterpara: refer to enum i2c_digital_filter_enum \param[out] none \retval none */ void i2c_digital_noise_filter_config(uint32_t i2c_periph,i2c_digital_filter_enum dfilterpara) { - I2C_FCTL(i2c_periph) |= dfilterpara; + I2C_FCTL(i2c_periph) |= dfilterpara; } /*! @@ -619,7 +586,7 @@ void i2c_digital_noise_filter_config(uint32_t i2c_periph,i2c_digital_filter_enum */ void i2c_sam_enable(uint32_t i2c_periph) { - I2C_SAMCS(i2c_periph) |= I2C_SAMCS_SAMEN; + I2C_SAMCS(i2c_periph) |= I2C_SAMCS_SAMEN; } /*! @@ -630,7 +597,7 @@ void i2c_sam_enable(uint32_t i2c_periph) */ void i2c_sam_disable(uint32_t i2c_periph) { - I2C_SAMCS(i2c_periph) &= ~(I2C_SAMCS_SAMEN); + I2C_SAMCS(i2c_periph) &= ~(I2C_SAMCS_SAMEN); } /*! @@ -641,7 +608,7 @@ void i2c_sam_disable(uint32_t i2c_periph) */ void i2c_sam_timeout_enable(uint32_t i2c_periph) { - I2C_SAMCS(i2c_periph) |= I2C_SAMCS_STOEN; + I2C_SAMCS(i2c_periph) |= I2C_SAMCS_STOEN; } /*! @@ -652,79 +619,201 @@ void i2c_sam_timeout_enable(uint32_t i2c_periph) */ void i2c_sam_timeout_disable(uint32_t i2c_periph) { - I2C_SAMCS(i2c_periph) &= ~(I2C_SAMCS_STOEN); + I2C_SAMCS(i2c_periph) &= ~(I2C_SAMCS_STOEN); } /*! - \brief enable the specified I2C SAM interrupt + \brief check I2C flag is set or not \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] inttype: interrupt type - \@arg I2C_SAMCS_TFFIE: txframe fall interrupt - \@arg I2C_SAMCS_TFRIE: txframe rise interrupt - \@arg I2C_SAMCS_RFFIE: rxframe fall interrupt - \@arg I2C_SAMCS_RFRIE: rxframe rise interrupt - \param[out] none - \retval none -*/ -void i2c_sam_interrupt_enable(uint32_t i2c_periph,uint32_t inttype) -{ - I2C_SAMCS(i2c_periph) |= (inttype); -} - -/*! - \brief disable i2c interrupt - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] inttype: interrupt type - \@arg I2C_SAMCS_TFFIE: txframe fall interrupt - \@arg I2C_SAMCS_TFRIE: txframe rise interrupt - \@arg I2C_SAMCS_RFFIE: rxframe fall interrupt - \@arg I2C_SAMCS_RFRIE: rxframe rise interrupt + \param[in] flag: I2C flags, refer to i2c_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_FLAG_SBSEND: start condition send out + \arg I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode + \arg I2C_FLAG_BTC: byte transmission finishes + \arg I2C_FLAG_ADD10SEND: header of 10-bit address is sent in master mode + \arg I2C_FLAG_STPDET: stop condition detected in slave mode + \arg I2C_FLAG_RBNE: I2C_DATA is not Empty during receiving + \arg I2C_FLAG_TBE: I2C_DATA is empty during transmitting + \arg I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus + \arg I2C_FLAG_LOSTARB: arbitration lost in master mode + \arg I2C_FLAG_AERR: acknowledge error + \arg I2C_FLAG_OUERR: overrun or underrun situation occurs in slave mode + \arg I2C_FLAG_PECERR: PEC error when receiving data + \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode + \arg I2C_FLAG_SMBALT: SMBus alert status + \arg I2C_FLAG_MASTER: a flag indicating whether I2C block is in master or slave mode + \arg I2C_FLAG_I2CBSY: busy flag + \arg I2C_FLAG_TRS: whether the I2C is a transmitter or a receiver + \arg I2C_FLAG_RXGC: general call address (00h) received + \arg I2C_FLAG_DEFSMB: default address of SMBus device + \arg I2C_FLAG_HSTSMB: SMBus host header detected in slave mode + \arg I2C_FLAG_DUMOD: dual flag in slave mode indicating which address is matched in dual-address mode + \arg I2C_FLAG_TFF: txframe fall flag + \arg I2C_FLAG_TFR: txframe rise flag + \arg I2C_FLAG_RFF: rxframe fall flag + \arg I2C_FLAG_RFR: rxframe rise flag \param[out] none - \retval none + \retval FlagStatus: SET or RESET */ -void i2c_sam_interrupt_disable(uint32_t i2c_periph,uint32_t inttype) +FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag) { - I2C_SAMCS(i2c_periph) &= ~(inttype); -} - -/*! - \brief check i2c SAM state - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] samstate: state type - \@arg I2C_SAMCS_TXF: level of txframe signal - \@arg I2C_SAMCS_RXF: level of rxframe signal - \@arg I2C_SAMCS_TFF: txframe fall flag - \@arg I2C_SAMCS_TFR: txframe rise flag - \@arg I2C_SAMCS_RFF: rxframe fall flag - \@arg I2C_SAMCS_RFR: rxframe rise flag - \param[out] none - \retval state of i2c SAM -*/ -FlagStatus i2c_sam_flag_get(uint32_t i2c_periph,uint32_t samstate) -{ - FlagStatus reg = RESET; - if(I2C_SAMCS(i2c_periph)&samstate){ - reg =SET; + if(RESET != (I2C_REG_VAL(i2c_periph, flag) & BIT(I2C_BIT_POS(flag)))){ + return SET; }else{ - reg =RESET; + return RESET; } - return reg; } /*! - \brief clear i2c SAM state + \brief clear I2C flag \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] samstate: state type - \@arg I2C_SAMCS_TFF: txframe fall flag - \@arg I2C_SAMCS_TFR: txframe rise flag - \@arg I2C_SAMCS_RFF: rxframe fall flag - \@arg I2C_SAMCS_RFR: rxframe rise flag + \param[in] flag: I2C flags, refer to i2c_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_FLAG_SMBALT: SMBus Alert status + \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode + \arg I2C_FLAG_PECERR: PEC error when receiving data + \arg I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode + \arg I2C_FLAG_AERR: acknowledge error + \arg I2C_FLAG_LOSTARB: arbitration lost in master mode + \arg I2C_FLAG_BERR: a bus error + \arg I2C_FLAG_ADDSEND: cleared by reading I2C_STAT0 and reading I2C_STAT1 + \arg I2C_FLAG_TFF: txframe fall flag + \arg I2C_FLAG_TFR: txframe rise flag + \arg I2C_FLAG_RFF: rxframe fall flag + \arg I2C_FLAG_RFR: rxframe rise flag \param[out] none \retval none */ -void i2c_sam_flag_clear(uint32_t i2c_periph,uint32_t samstate) +void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag) { - I2C_SAMCS(i2c_periph) &= ~(samstate); - + if(I2C_FLAG_ADDSEND == flag){ + /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ + I2C_STAT0(i2c_periph); + I2C_STAT1(i2c_periph); + }else{ + I2C_REG_VAL(i2c_periph, flag) &= ~BIT(I2C_BIT_POS(flag)); + } } +/*! + \brief enable I2C interrupt + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] interrupt: I2C interrupts, refer to i2c_interrupt_enum + only one parameter can be selected which is shown as below: + \arg I2C_INT_ERR: error interrupt enable + \arg I2C_INT_EV: event interrupt enable + \arg I2C_INT_BUF: buffer interrupt enable + \arg I2C_INT_TFF: txframe fall interrupt enable + \arg I2C_INT_TFR: txframe rise interrupt enable + \arg I2C_INT_RFF: rxframe fall interrupt enable + \arg I2C_INT_RFR: rxframe rise interrupt enable + \param[out] none + \retval none +*/ +void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) +{ + I2C_REG_VAL(i2c_periph, interrupt) |= BIT(I2C_BIT_POS(interrupt)); +} + +/*! + \brief disable I2C interrupt + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] interrupt: I2C interrupts, refer to i2c_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_INT_ERR: error interrupt enable + \arg I2C_INT_EV: event interrupt enable + \arg I2C_INT_BUF: buffer interrupt enable + \arg I2C_INT_TFF: txframe fall interrupt enable + \arg I2C_INT_TFR: txframe rise interrupt enable + \arg I2C_INT_RFF: rxframe fall interrupt enable + \arg I2C_INT_RFR: rxframe rise interrupt enable + \param[out] none + \retval none +*/ +void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) +{ + I2C_REG_VAL(i2c_periph, interrupt) &= ~BIT(I2C_BIT_POS(interrupt)); +} + +/*! + \brief check I2C interrupt flag + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_INT_FLAG_SBSEND: start condition sent out in master mode interrupt flag + \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag + \arg I2C_INT_FLAG_BTC: byte transmission finishes + \arg I2C_INT_FLAG_ADD10SEND: header of 10-bit address is sent in master mode interrupt flag + \arg I2C_INT_FLAG_STPDET: etop condition detected in slave mode interrupt flag + \arg I2C_INT_FLAG_RBNE: I2C_DATA is not Empty during receiving interrupt flag + \arg I2C_INT_FLAG_TBE: I2C_DATA is empty during transmitting interrupt flag + \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag + \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag + \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag + \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag + \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag + \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag + \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag + \arg I2C_INT_FLAG_TFF: txframe fall interrupt flag + \arg I2C_INT_FLAG_TFR: txframe rise interrupt flag + \arg I2C_INT_FLAG_RFF: rxframe fall interrupt flag + \arg I2C_INT_FLAG_RFR: rxframe rise interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) +{ + uint32_t intenable = 0U, flagstatus = 0U, bufie; + + /* check BUFIE */ + bufie = I2C_CTL1(i2c_periph)&I2C_CTL1_BUFIE; + + /* get the interrupt enable bit status */ + intenable = (I2C_REG_VAL(i2c_periph, int_flag) & BIT(I2C_BIT_POS(int_flag))); + /* get the corresponding flag bit status */ + flagstatus = (I2C_REG_VAL2(i2c_periph, int_flag) & BIT(I2C_BIT_POS2(int_flag))); + + if((I2C_INT_FLAG_RBNE == int_flag) || (I2C_INT_FLAG_TBE == int_flag)){ + if(intenable && bufie){ + intenable = 1U; + }else{ + intenable = 0U; + } + } + if((0U != flagstatus) && (0U != intenable)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear I2C interrupt flag + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag + \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag + \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag + \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag + \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag + \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag + \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag + \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag + \arg I2C_INT_FLAG_TFF: txframe fall interrupt flag + \arg I2C_INT_FLAG_TFR: txframe rise interrupt flag + \arg I2C_INT_FLAG_RFF: rxframe fall interrupt flag + \arg I2C_INT_FLAG_RFR: rxframe rise interrupt flag + \param[out] none + \retval none +*/ +void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) +{ + if(I2C_INT_FLAG_ADDSEND == int_flag){ + /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ + I2C_STAT0(i2c_periph); + I2C_STAT1(i2c_periph); + }else{ + I2C_REG_VAL2(i2c_periph, int_flag) &= ~BIT(I2C_BIT_POS2(int_flag)); + } +} diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_ipa.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_ipa.c index d50b473ab9..5afcc48e0d 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_ipa.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_ipa.c @@ -1,30 +1,57 @@ /*! - \file gd32f4xx_ipa.c - \brief IPA driver + \file gd32f4xx_ipa.c + \brief IPA driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_ipa.h" +#define IPA_DEFAULT_VALUE 0x00000000U + /*! - \brief deinitialize IPA registers + \brief deinitialize IPA registers \param[in] none \param[out] none \retval none */ void ipa_deinit(void) { - rcu_periph_reset_enable(RCU_IPAENRST); - rcu_periph_reset_disable(RCU_IPAENRST); + rcu_periph_reset_enable(RCU_IPARST); + rcu_periph_reset_disable(RCU_IPARST); } /*! - \brief IPA transfer enable + \brief enable IPA transfer \param[in] none \param[out] none \retval none @@ -35,8 +62,8 @@ void ipa_transfer_enable(void) } /*! - \brief IPA transfer hang up enable - \param[in] none. + \brief enable IPA transfer hang up + \param[in] none \param[out] none \retval none */ @@ -46,8 +73,8 @@ void ipa_transfer_hangup_enable(void) } /*! - \brief IPA transfer hang up disable - \param[in] none. + \brief disable IPA transfer hang up + \param[in] none \param[out] none \retval none */ @@ -57,8 +84,8 @@ void ipa_transfer_hangup_disable(void) } /*! - \brief IPA transfer stop enable - \param[in] none. + \brief enable IPA transfer stop + \param[in] none \param[out] none \retval none */ @@ -68,8 +95,8 @@ void ipa_transfer_stop_enable(void) } /*! - \brief IPA transfer stop disable - \param[in] none. + \brief disable IPA transfer stop + \param[in] none \param[out] none \retval none */ @@ -78,8 +105,8 @@ void ipa_transfer_stop_disable(void) IPA_CTL &= ~(IPA_CTL_TST); } /*! - \brief IPA foreground LUT loading enable - \param[in] none. + \brief enable IPA foreground LUT loading + \param[in] none \param[out] none \retval none */ @@ -89,8 +116,8 @@ void ipa_foreground_lut_loading_enable(void) } /*! - \brief IPA background LUT loading enable - \param[in] none. + \brief enable IPA background LUT loading + \param[in] none \param[out] none \retval none */ @@ -100,94 +127,217 @@ void ipa_background_lut_loading_enable(void) } /*! - \brief Pixel format convert mode - \param[in] pfcm: - \arg IPA_FGTODE: foreground memory to destination memory without pixel format convert - \arg IPA_FGTODE_PF_CONVERT: foreground memory to destination memory with pixel format convert - \arg IPA_FGBGTODE: blending foreground and background memory to destination memory - \arg IPA_FILL_UP_DE: fill up destination memory with specific color + \brief set pixel format convert mode, the function is invalid when the IPA transfer is enabled + \param[in] pfcm: pixel format convert mode + only one parameter can be selected which is shown as below: + \arg IPA_FGTODE: foreground memory to destination memory without pixel format convert + \arg IPA_FGTODE_PF_CONVERT: foreground memory to destination memory with pixel format convert + \arg IPA_FGBGTODE: blending foreground and background memory to destination memory + \arg IPA_FILL_UP_DE: fill up destination memory with specific color \param[out] none \retval none */ -void ipa_pixel_format_convert_mod(uint32_t pfcm) +void ipa_pixel_format_convert_mode_set(uint32_t pfcm) { IPA_CTL |= pfcm; } /*! - \brief initialize foreground parameters - \param[in] foreground_struct: the data needed to initialize fore. + \brief initialize the structure of IPA foreground parameter struct with the default values, it is + suggested that call this function after an ipa_foreground_parameter_struct structure is defined + \param[in] none + \param[out] foreground_struct: the data needed to initialize foreground foreground_memaddr: foreground memory base address foreground_lineoff: foreground line offset - foreground_prealpha: foreground pre-defined alpha value + foreground_prealpha: foreground pre-defined alpha value foreground_alpha_algorithm: IPA_FG_ALPHA_MODE_0,IPA_FG_ALPHA_MODE_1,IPA_FG_ALPHA_MODE_2 - foreground_pf: foreground pixel format + foreground_pf: foreground pixel format(FOREGROUND_PPF_ARGB8888,FOREGROUND_PPF_RGB888,FOREGROUND_PPF_RGB565, + FOREGROUND_PPF_ARG1555,FOREGROUND_PPF_ARGB4444,FOREGROUND_PPF_L8,FOREGROUND_PPF_AL44, + FOREGROUND_PPF_AL88,FOREGROUND_PPF_L4,FOREGROUND_PPF_A8,FOREGROUND_PPF_A4) foreground_prered: foreground pre-defined red value - foreground_pregreen: foreground pre-defined green value + foreground_pregreen: foreground pre-defined green value + foreground_preblue: foreground pre-defined blue value + \retval none +*/ +void ipa_foreground_struct_para_init(ipa_foreground_parameter_struct* foreground_struct) +{ + /* initialize the struct parameters with default values */ + foreground_struct->foreground_memaddr = IPA_DEFAULT_VALUE; + foreground_struct->foreground_lineoff = IPA_DEFAULT_VALUE; + foreground_struct->foreground_prealpha = IPA_DEFAULT_VALUE; + foreground_struct->foreground_alpha_algorithm = IPA_FG_ALPHA_MODE_0; + foreground_struct->foreground_pf = FOREGROUND_PPF_ARGB8888; + foreground_struct->foreground_prered = IPA_DEFAULT_VALUE; + foreground_struct->foreground_pregreen = IPA_DEFAULT_VALUE; + foreground_struct->foreground_preblue = IPA_DEFAULT_VALUE; +} + +/*! + \brief initialize foreground parameters + \param[in] foreground_struct: the data needed to initialize foreground + foreground_memaddr: foreground memory base address + foreground_lineoff: foreground line offset + foreground_prealpha: foreground pre-defined alpha value + foreground_alpha_algorithm: IPA_FG_ALPHA_MODE_0,IPA_FG_ALPHA_MODE_1,IPA_FG_ALPHA_MODE_2 + foreground_pf: foreground pixel format(FOREGROUND_PPF_ARGB8888,FOREGROUND_PPF_RGB888,FOREGROUND_PPF_RGB565, + FOREGROUND_PPF_ARG1555,FOREGROUND_PPF_ARGB4444,FOREGROUND_PPF_L8,FOREGROUND_PPF_AL44, + FOREGROUND_PPF_AL88,FOREGROUND_PPF_L4,FOREGROUND_PPF_A8,FOREGROUND_PPF_A4) + foreground_prered: foreground pre-defined red value + foreground_pregreen: foreground pre-defined green value foreground_preblue: foreground pre-defined blue value \param[out] none \retval none */ void ipa_foreground_init(ipa_foreground_parameter_struct* foreground_struct) { + FlagStatus tempflag = RESET; + if(RESET != (IPA_CTL & IPA_CTL_TEN)){ + tempflag = SET; + /* reset the TEN in order to configure the following bits */ + IPA_CTL &= ~IPA_CTL_TEN; + } + /* foreground memory base address configuration */ IPA_FMADDR &= ~(IPA_FMADDR_FMADDR); IPA_FMADDR = foreground_struct->foreground_memaddr; /* foreground line offset configuration */ IPA_FLOFF &= ~(IPA_FLOFF_FLOFF); IPA_FLOFF = foreground_struct->foreground_lineoff; - /* foreground pixel format pre-defined alpha, alpha calculation algorithm configuration */ - IPA_FPCTL &= ~(IPA_FPCTL_FAVCA|IPA_FPCTL_FAVCA|IPA_FPCTL_FPF); + /* foreground pixel format pre-defined alpha, alpha calculation algorithm configuration */ + IPA_FPCTL &= ~(IPA_FPCTL_FPDAV|IPA_FPCTL_FAVCA|IPA_FPCTL_FPF); IPA_FPCTL |= (foreground_struct->foreground_prealpha<<24U); IPA_FPCTL |= foreground_struct->foreground_alpha_algorithm; IPA_FPCTL |= foreground_struct->foreground_pf; - /* foreground pre-defined red green blue configuration */ + /* foreground pre-defined red green blue configuration */ IPA_FPV &= ~(IPA_FPV_FPDRV|IPA_FPV_FPDGV|IPA_FPV_FPDBV); - IPA_FPV |= ((foreground_struct->foreground_prered<<16U)|(foreground_struct->foreground_pregreen<<8U)|(foreground_struct->foreground_preblue)); + IPA_FPV |= ((foreground_struct->foreground_prered<<16U)|(foreground_struct->foreground_pregreen<<8U) + |(foreground_struct->foreground_preblue)); + + if(SET == tempflag){ + /* restore the state of TEN */ + IPA_CTL |= IPA_CTL_TEN; + } } /*! - \brief initialize background parameters - \param[in] background_struct: the data needed to initialize fore. + \brief initialize the structure of IPA background parameter struct with the default values, it is + suggested that call this function after an ipa_background_parameter_struct structure is defined + \param[in] none + \param[out] background_struct: the data needed to initialize background background_memaddr: background memory base address background_lineoff: background line offset - background_prealpha: background pre-defined alpha value - background_alpha_algorithm: IPA_BG_ALPHA_MODE_0,IPA_FG_ALPHA_MODE_1,IPA_FG_ALPHA_MODE_2 - background_pf: background pixel format + background_prealpha: background pre-defined alpha value + background_alpha_algorithm: IPA_BG_ALPHA_MODE_0,IPA_BG_ALPHA_MODE_1,IPA_BG_ALPHA_MODE_2 + background_pf: background pixel format(BACKGROUND_PPF_ARGB8888,BACKGROUND_PPF_RGB888,BACKGROUND_PPF_RGB565, + BACKGROUND_PPF_ARG1555,BACKGROUND_PPF_ARGB4444,BACKGROUND_PPF_L8,BACKGROUND_PPF_AL44, + BACKGROUND_PPF_AL88,BACKGROUND_PPF_L4,BACKGROUND_PPF_A8,BACKGROUND_PPF_A4) background_prered: background pre-defined red value - background_pregreen: background pre-defined green value + background_pregreen: background pre-defined green value + background_preblue: background pre-defined blue value + \retval none +*/ +void ipa_background_struct_para_init(ipa_background_parameter_struct* background_struct) +{ + /* initialize the struct parameters with default values */ + background_struct->background_memaddr = IPA_DEFAULT_VALUE; + background_struct->background_lineoff = IPA_DEFAULT_VALUE; + background_struct->background_prealpha = IPA_DEFAULT_VALUE; + background_struct->background_alpha_algorithm = IPA_BG_ALPHA_MODE_0; + background_struct->background_pf = BACKGROUND_PPF_ARGB8888; + background_struct->background_prered = IPA_DEFAULT_VALUE; + background_struct->background_pregreen = IPA_DEFAULT_VALUE; + background_struct->background_preblue = IPA_DEFAULT_VALUE; +} + +/*! + \brief initialize background parameters + \param[in] background_struct: the data needed to initialize background + background_memaddr: background memory base address + background_lineoff: background line offset + background_prealpha: background pre-defined alpha value + background_alpha_algorithm: IPA_BG_ALPHA_MODE_0,IPA_FG_ALPHA_MODE_1,IPA_FG_ALPHA_MODE_2 + background_pf: background pixel format(BACKGROUND_PPF_ARGB8888,BACKGROUND_PPF_RGB888,BACKGROUND_PPF_RGB565, + BACKGROUND_PPF_ARG1555,BACKGROUND_PPF_ARGB4444,BACKGROUND_PPF_L8,BACKGROUND_PPF_AL44, + BACKGROUND_PPF_AL88,BACKGROUND_PPF_L4,BACKGROUND_PPF_A8,BACKGROUND_PPF_A4) + background_prered: background pre-defined red value + background_pregreen: background pre-defined green value background_preblue: background pre-defined blue value \param[out] none \retval none */ void ipa_background_init(ipa_background_parameter_struct* background_struct) { + FlagStatus tempflag = RESET; + if(RESET != (IPA_CTL & IPA_CTL_TEN)){ + tempflag = SET; + /* reset the TEN in order to configure the following bits */ + IPA_CTL &= ~IPA_CTL_TEN; + } + /* background memory base address configuration */ IPA_BMADDR &= ~(IPA_BMADDR_BMADDR); IPA_BMADDR = background_struct->background_memaddr; /* background line offset configuration */ IPA_BLOFF &= ~(IPA_BLOFF_BLOFF); - IPA_BLOFF =background_struct->background_lineoff; - /* background pixel format pre-defined alpha, alpha calculation algorithm configuration */ - IPA_BPCTL &= ~(IPA_BPCTL_BAVCA|IPA_BPCTL_BAVCA|IPA_BPCTL_BPF); + IPA_BLOFF = background_struct->background_lineoff; + /* background pixel format pre-defined alpha, alpha calculation algorithm configuration */ + IPA_BPCTL &= ~(IPA_BPCTL_BPDAV|IPA_BPCTL_BAVCA|IPA_BPCTL_BPF); IPA_BPCTL |= (background_struct->background_prealpha<<24U); IPA_BPCTL |= background_struct->background_alpha_algorithm; - IPA_BPCTL |= background_struct->background_pf; - /* background pre-defined red green blue configuration */ + IPA_BPCTL |= background_struct->background_pf; + /* background pre-defined red green blue configuration */ IPA_BPV &= ~(IPA_BPV_BPDRV|IPA_BPV_BPDGV|IPA_BPV_BPDBV); - IPA_BPV |= ((background_struct->background_prered<<16U)|(background_struct->background_pregreen<<8U)|(background_struct->background_preblue)); + IPA_BPV |= ((background_struct->background_prered<<16U)|(background_struct->background_pregreen<<8U) + |(background_struct->background_preblue)); + + if(SET == tempflag){ + /* restore the state of TEN */ + IPA_CTL |= IPA_CTL_TEN; + } } /*! - \brief initialize destination parameters - \param[in] destination_struct: the data needed to initialize tli. - destination_pf: refer to ipa_dpf_enum + \brief initialize the structure of IPA destination parameter struct with the default values, it is + suggested that call this function after an ipa_destination_parameter_struct structure is defined + \param[in] none + \param[out] destination_struct: the data needed to initialize destination parameter + destination_pf: IPA_DPF_ARGB8888,IPA_DPF_RGB888,IPA_DPF_RGB565,IPA_DPF_ARGB1555, + IPA_DPF_ARGB4444,refer to ipa_dpf_enum destination_lineoff: destination line offset - destination_prealpha: destination pre-defined alpha value + destination_prealpha: destination pre-defined alpha value destination_prered: destination pre-defined red value destination_pregreen: destination pre-defined green value destination_preblue: destination pre-defined blue value - destination_memaddr: destination memory base address + destination_memaddr: destination memory base address + image_width: width of the image to be processed + image_height: height of the image to be processed + \retval none +*/ +void ipa_destination_struct_para_init(ipa_destination_parameter_struct* destination_struct) +{ + /* initialize the struct parameters with default values */ + destination_struct->destination_pf = IPA_DPF_ARGB8888; + destination_struct->destination_lineoff = IPA_DEFAULT_VALUE; + destination_struct->destination_prealpha = IPA_DEFAULT_VALUE; + destination_struct->destination_prered = IPA_DEFAULT_VALUE; + destination_struct->destination_pregreen = IPA_DEFAULT_VALUE; + destination_struct->destination_preblue = IPA_DEFAULT_VALUE; + destination_struct->destination_memaddr = IPA_DEFAULT_VALUE; + destination_struct->image_width = IPA_DEFAULT_VALUE; + destination_struct->image_height = IPA_DEFAULT_VALUE; +} + +/*! + \brief initialize destination parameters + \param[in] destination_struct: the data needed to initialize destination parameters + destination_pf: IPA_DPF_ARGB8888,IPA_DPF_RGB888,IPA_DPF_RGB565,IPA_DPF_ARGB1555, + IPA_DPF_ARGB4444,refer to ipa_dpf_enum + destination_lineoff: destination line offset + destination_prealpha: destination pre-defined alpha value + destination_prered: destination pre-defined red value + destination_pregreen: destination pre-defined green value + destination_preblue: destination pre-defined blue value + destination_memaddr: destination memory base address image_width: width of the image to be processed image_height: height of the image to be processed \param[out] none @@ -196,6 +346,13 @@ void ipa_background_init(ipa_background_parameter_struct* background_struct) void ipa_destination_init(ipa_destination_parameter_struct* destination_struct) { uint32_t destination_pixelformat; + FlagStatus tempflag = RESET; + if(RESET != (IPA_CTL & IPA_CTL_TEN)){ + tempflag = SET; + /* reset the TEN in order to configure the following bits */ + IPA_CTL &= ~IPA_CTL_TEN; + } + /* destination pixel format configuration */ IPA_DPCTL &= ~(IPA_DPCTL_DPF); IPA_DPCTL = destination_struct->destination_pf; @@ -230,36 +387,48 @@ void ipa_destination_init(ipa_destination_parameter_struct* destination_struct) /* destination pixel format ARGB4444 */ case IPA_DPF_ARGB4444: IPA_DPV &= ~(IPA_DPV_DPDBV_4|(IPA_DPV_DPDGV_4)|(IPA_DPV_DPDRV_4)|(IPA_DPV_DPDAV_4)); - IPA_DPV = (destination_struct->destination_preblue|(destination_struct->destination_pregreen<<5U) - |(destination_struct->destination_prered<<10U) - |(destination_struct->destination_prealpha<<15U)); + IPA_DPV = (destination_struct->destination_preblue|(destination_struct->destination_pregreen<<4U) + |(destination_struct->destination_prered<<8U) + |(destination_struct->destination_prealpha<<12U)); break; default: break; } /* destination memory base address configuration */ IPA_DMADDR &= ~(IPA_DMADDR_DMADDR); - IPA_DMADDR =destination_struct->destination_memaddr; - /* destination line offset configuration */ + IPA_DMADDR = destination_struct->destination_memaddr; + /* destination line offset configuration */ IPA_DLOFF &= ~(IPA_DLOFF_DLOFF); IPA_DLOFF =destination_struct->destination_lineoff; - /* image size configuration */ + /* image size configuration */ IPA_IMS &= ~(IPA_IMS_HEIGHT|IPA_IMS_WIDTH); - IPA_IMS |= ((destination_struct->image_width<<16)|(destination_struct->image_height)); + IPA_IMS |= ((destination_struct->image_width<<16U)|(destination_struct->image_height)); + + if(SET == tempflag){ + /* restore the state of TEN */ + IPA_CTL |= IPA_CTL_TEN; + } } /*! - \brief initialize IPA foreground LUT parameters - \param[in] fg_lut_num: foreground LUT number of pixel. - \param[in] fg_lut_pf: foreground LUT pixel format,IPA_LUT_PF_ARGB8888,IPA_LUT_PF_RGB888. - \param[in] fg_lut_addr: foreground LUT memory base address. + \brief initialize IPA foreground LUT parameters + \param[in] fg_lut_num: foreground LUT number of pixel + \param[in] fg_lut_pf: foreground LUT pixel format(IPA_LUT_PF_ARGB8888, IPA_LUT_PF_RGB888) + \param[in] fg_lut_addr: foreground LUT memory base address \param[out] none \retval none */ -void ipa_foreground_lut_init(uint32_t fg_lut_num,uint8_t fg_lut_pf, uint32_t fg_lut_addr) +void ipa_foreground_lut_init(uint8_t fg_lut_num, uint8_t fg_lut_pf, uint32_t fg_lut_addr) { + FlagStatus tempflag = RESET; + if(RESET != (IPA_FPCTL & IPA_FPCTL_FLLEN)){ + tempflag = SET; + /* reset the FLLEN in order to configure the following bits */ + IPA_FPCTL &= ~IPA_FPCTL_FLLEN; + } + /* foreground LUT number of pixel configuration */ - IPA_FPCTL |= (fg_lut_num<<8U); + IPA_FPCTL |= ((uint32_t)fg_lut_num<<8U); /* foreground LUT pixel format configuration */ if(IPA_LUT_PF_RGB888 == fg_lut_pf){ IPA_FPCTL |= IPA_FPCTL_FLPF; @@ -269,20 +438,32 @@ void ipa_foreground_lut_init(uint32_t fg_lut_num,uint8_t fg_lut_pf, uint32_t fg_ /* foreground LUT memory base address configuration */ IPA_FLMADDR &= ~(IPA_FLMADDR_FLMADDR); IPA_FLMADDR = fg_lut_addr; + + if(SET == tempflag){ + /* restore the state of FLLEN */ + IPA_FPCTL |= IPA_FPCTL_FLLEN; + } } /*! - \brief initialize IPA background LUT parameters - \param[in] bg_lut_num: background LUT number of pixel. - \param[in] bg_lut_pf: background LUT pixel format, IPA_LUT_PF_ARGB8888,IPA_LUT_PF_RGB888. - \param[in] bg_lut_addr: background LUT memory base address. + \brief initialize IPA background LUT parameters + \param[in] bg_lut_num: background LUT number of pixel + \param[in] bg_lut_pf: background LUT pixel format(IPA_LUT_PF_ARGB8888, IPA_LUT_PF_RGB888) + \param[in] bg_lut_addr: background LUT memory base address \param[out] none \retval none */ -void ipa_background_lut_init(uint32_t bg_lut_num,uint8_t bg_lut_pf, uint32_t bg_lut_addr) +void ipa_background_lut_init(uint8_t bg_lut_num, uint8_t bg_lut_pf, uint32_t bg_lut_addr) { + FlagStatus tempflag = RESET; + if(RESET != (IPA_BPCTL & IPA_BPCTL_BLLEN)){ + tempflag = SET; + /* reset the BLLEN in order to configure the following bits */ + IPA_BPCTL &= ~IPA_BPCTL_BLLEN; + } + /* background LUT number of pixel configuration */ - IPA_BPCTL|=(bg_lut_num<<8U); + IPA_BPCTL |= ((uint32_t)bg_lut_num<<8U); /* background LUT pixel format configuration */ if(IPA_LUT_PF_RGB888 == bg_lut_pf){ IPA_BPCTL |= IPA_BPCTL_BLPF; @@ -292,29 +473,34 @@ void ipa_background_lut_init(uint32_t bg_lut_num,uint8_t bg_lut_pf, uint32_t bg_ /* background LUT memory base address configuration */ IPA_BLMADDR &= ~(IPA_BLMADDR_BLMADDR); IPA_BLMADDR = bg_lut_addr; + + if(SET == tempflag){ + /* restore the state of BLLEN */ + IPA_BPCTL |= IPA_BPCTL_BLLEN; + } } /*! - \brief configure line mark - \param[in] linenum: line number. + \brief configure IPA line mark + \param[in] line_num: line number \param[out] none \retval none */ -void ipa_line_mark_config(uint32_t linenum) +void ipa_line_mark_config(uint16_t line_num) { IPA_LM &= ~(IPA_LM_LM); - IPA_LM = linenum; + IPA_LM = line_num; } /*! - \brief Inter-timer enable or disable - \param[in] timercfg: IPA_INTER_TIMER_ENABLE,IPA_INTER_TIMER_DISABLE + \brief inter-timer enable or disable + \param[in] timer_cfg: IPA_INTER_TIMER_ENABLE,IPA_INTER_TIMER_DISABLE \param[out] none \retval none */ -void ipa_inter_timer_config(uint8_t timercfg) +void ipa_inter_timer_config(uint8_t timer_cfg) { - if(IPA_INTER_TIMER_ENABLE == timercfg){ + if(IPA_INTER_TIMER_ENABLE == timer_cfg){ IPA_ITCTL |= IPA_ITCTL_ITEN; }else{ IPA_ITCTL &= ~(IPA_ITCTL_ITEN); @@ -322,68 +508,34 @@ void ipa_inter_timer_config(uint8_t timercfg) } /*! - \brief number of clock cycles interval set - \param[in] clk_num: the number of clock cycles. + \brief configure the number of clock cycles interval + \param[in] clk_num: the number of clock cycles \param[out] none \retval none */ -void ipa_interval_clock_num_config(uint32_t clk_num ) +void ipa_interval_clock_num_config(uint8_t clk_num) { + /* NCCI[7:0] bits have no meaning if ITEN is '0' */ IPA_ITCTL &= ~(IPA_ITCTL_NCCI); - IPA_ITCTL |= (clk_num<<8U); + IPA_ITCTL |= ((uint32_t)clk_num<<8U); } /*! - \brief IPA interrupt enable - \param[in] inttype: IPA interrupt bits. - \arg IPA_CTL_TAEIE: transfer access error interrupt - \arg IPA_CTL_FTFIE: full transfer finish interrupt - \arg IPA_CTL_TLMIE: transfer line mark interrupt - \arg IPA_CTL_LACIE: LUT access conflict interrupt - \arg IPA_CTL_LLFIE: LUT loading finish interrupt - \arg IPA_CTL_WCFIE: wrong configuration interrupt + \brief get IPA flag status in IPA_INTF register + \param[in] flag: IPA flags + one or more parameters can be selected which are shown as below: + \arg IPA_FLAG_TAE: transfer access error interrupt flag + \arg IPA_FLAG_FTF: full transfer finish interrupt flag + \arg IPA_FLAG_TLM: transfer line mark interrupt flag + \arg IPA_FLAG_LAC: LUT access conflict interrupt flag + \arg IPA_FLAG_LLF: LUT loading finish interrupt flag + \arg IPA_FLAG_WCF: wrong configuration interrupt flag \param[out] none \retval none */ -void ipa_interrupt_enable(uint32_t inttype) +FlagStatus ipa_flag_get(uint32_t flag) { - IPA_CTL |= (inttype); -} - -/*! - \brief IPA interrupt disable - \param[in] inttype: IPA interrupt bits. - \arg IPA_CTL_TAEIE: transfer access error interrupt - \arg IPA_CTL_FTFIE: full transfer finish interrupt - \arg IPA_CTL_TLMIE: transfer line mark interrupt - \arg IPA_CTL_LACIE: LUT access conflict interrupt - \arg IPA_CTL_LLFIE: LUT loading finish interrupt - \arg IPA_CTL_WCFIE: wrong configuration interrupt - \param[out] none - \retval none -*/ -void ipa_interrupt_disable(uint32_t inttype) -{ - IPA_CTL &= ~(inttype); -} - -/*! - \brief get IPA interrupt flag - \param[in] intflag: tli interrupt flag bits. - \arg IPA_INTF_TAEIF: transfer access error interrupt flag - \arg IPA_INTF_FTFIF: full transfer finish interrupt flag - \arg IPA_INTF_TLMIF: transfer line mark interrupt flag - \arg IPA_INTF_LACIF: LUT access conflict interrupt flag - \arg IPA_INTF_LLFIF: LUT loading finish interrupt flag - \arg IPA_INTF_WCFIF: wrong configuration interrupt flag - \param[out] none - \retval none -*/ -FlagStatus ipa_interrupt_flag_get(uint32_t intflag) -{ - uint32_t state; - state = IPA_INTF; - if(state & intflag){ + if(RESET != (IPA_INTF & flag)){ return SET; }else{ return RESET; @@ -391,19 +543,95 @@ FlagStatus ipa_interrupt_flag_get(uint32_t intflag) } /*! - \brief clear IPA interrupt flag - \param[in] intflag: tli interrupt flag bits. - \arg IPA_INTC_TAEIFC: transfer access error interrupt flag - \arg IPA_INTC_FTFIFC: full transfer finish interrupt flag - \arg IPA_INTC_TLMIFC: transfer line mark interrupt flag - \arg IPA_INTC_LACIFC: LUT access conflict interrupt flag - \arg IPA_INTC_LLFIFC: LUT loading finish interrupt flag - \arg IPA_INTC_WCFIFC: wrong configuration interrupt flag + \brief clear IPA flag in IPA_INTF register + \param[in] flag: IPA flags + one or more parameters can be selected which are shown as below: + \arg IPA_FLAG_TAE: transfer access error interrupt flag + \arg IPA_FLAG_FTF: full transfer finish interrupt flag + \arg IPA_FLAG_TLM: transfer line mark interrupt flag + \arg IPA_FLAG_LAC: LUT access conflict interrupt flag + \arg IPA_FLAG_LLF: LUT loading finish interrupt flag + \arg IPA_FLAG_WCF: wrong configuration interrupt flag \param[out] none \retval none */ -void ipa_interrupt_flag_clear(uint32_t intflag) +void ipa_flag_clear(uint32_t flag) { - IPA_INTC |= (intflag); + IPA_INTC |= (flag); } +/*! + \brief enable IPA interrupt + \param[in] int_flag: IPA interrupt flags + one or more parameters can be selected which are shown as below: + \arg IPA_INT_TAE: transfer access error interrupt + \arg IPA_INT_FTF: full transfer finish interrupt + \arg IPA_INT_TLM: transfer line mark interrupt + \arg IPA_INT_LAC: LUT access conflict interrupt + \arg IPA_INT_LLF: LUT loading finish interrupt + \arg IPA_INT_WCF: wrong configuration interrupt + \param[out] none + \retval none +*/ +void ipa_interrupt_enable(uint32_t int_flag) +{ + IPA_CTL |= (int_flag); +} + +/*! + \brief disable IPA interrupt + \param[in] int_flag: IPA interrupt flags + one or more parameters can be selected which are shown as below: + \arg IPA_INT_TAE: transfer access error interrupt + \arg IPA_INT_FTF: full transfer finish interrupt + \arg IPA_INT_TLM: transfer line mark interrupt + \arg IPA_INT_LAC: LUT access conflict interrupt + \arg IPA_INT_LLF: LUT loading finish interrupt + \arg IPA_INT_WCF: wrong configuration interrupt + \param[out] none + \retval none +*/ +void ipa_interrupt_disable(uint32_t int_flag) +{ + IPA_CTL &= ~(int_flag); +} + +/*! + \brief get IPA interrupt flag + \param[in] int_flag: IPA interrupt flag flags + one or more parameters can be selected which are shown as below: + \arg IPA_INT_FLAG_TAE: transfer access error interrupt flag + \arg IPA_INT_FLAG_FTF: full transfer finish interrupt flag + \arg IPA_INT_FLAG_TLM: transfer line mark interrupt flag + \arg IPA_INT_FLAG_LAC: LUT access conflict interrupt flag + \arg IPA_INT_FLAG_LLF: LUT loading finish interrupt flag + \arg IPA_INT_FLAG_WCF: wrong configuration interrupt flag + \param[out] none + \retval none +*/ +FlagStatus ipa_interrupt_flag_get(uint32_t int_flag) +{ + if(0U != (IPA_INTF & int_flag)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear IPA interrupt flag + \param[in] int_flag: IPA interrupt flag flags + one or more parameters can be selected which are shown as below: + \arg IPA_INT_FLAG_TAE: transfer access error interrupt flag + \arg IPA_INT_FLAG_FTF: full transfer finish interrupt flag + \arg IPA_INT_FLAG_TLM: transfer line mark interrupt flag + \arg IPA_INT_FLAG_LAC: LUT access conflict interrupt flag + \arg IPA_INT_FLAG_LLF: LUT loading finish interrupt flag + \arg IPA_INT_FLAG_WCF: wrong configuration interrupt flag + \param[out] none + \retval none +*/ +void ipa_interrupt_flag_clear(uint32_t int_flag) +{ + IPA_INTC |= (int_flag); +} diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_iref.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_iref.c index 237fc2ee75..218a070ef4 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_iref.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_iref.c @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_iref.c - \brief IREF driver + \file gd32f4xx_iref.c + \brief IREF driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_iref.h" @@ -87,7 +112,7 @@ void iref_sink_set(uint32_t sinkmode) } /*! - \brief set IREF step data + \brief set IREF step data \param[in] stepdata \arg IREF_CUR_STEP_DATA_X:(x=0..63): step*x \param[out] none diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_misc.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_misc.c index 1649929a4b..c826722f13 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_misc.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_misc.c @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_misc.c - \brief MISC driver + \file gd32f4xx_misc.c + \brief MISC driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_misc.h" @@ -36,7 +61,7 @@ void nvic_priority_group_set(uint32_t nvic_prigroup) \param[out] none \retval none */ -void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, +void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority) { uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U; @@ -57,6 +82,9 @@ void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, temp_pre=4U; temp_sub=0x0U; }else{ + nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2); + temp_pre=2U; + temp_sub=0x2U; } /* get the temp_priority to fill the NVIC->IP register */ temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre); @@ -96,10 +124,10 @@ void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset) /*! \brief set the state of the low power mode \param[in] lowpower_mode: the low power mode state - \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power + \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power mode by exiting from ISR \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode - \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up + \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up by all the enable and disable interrupts \param[out] none \retval none @@ -112,10 +140,10 @@ void system_lowpower_set(uint8_t lowpower_mode) /*! \brief reset the state of the low power mode \param[in] lowpower_mode: the low power mode state - \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power + \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power mode by exiting from ISR \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode - \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be + \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be woke up by the enable interrupts \param[out] none \retval none diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_pmu.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_pmu.c index 267e4c32fd..05f4cd7c3a 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_pmu.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_pmu.c @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_pmu.c - \brief PMU driver + \file gd32f4xx_pmu.c + \brief PMU driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_pmu.h" @@ -26,37 +51,37 @@ void pmu_deinit(void) /*! \brief select low voltage detector threshold - \param[in] pmu_lvdt_n: - \arg PMU_LVDT_0: voltage threshold is 2.2V + \param[in] lvdt_n: + \arg PMU_LVDT_0: voltage threshold is 2.1V \arg PMU_LVDT_1: voltage threshold is 2.3V \arg PMU_LVDT_2: voltage threshold is 2.4V - \arg PMU_LVDT_3: voltage threshold is 2.5V - \arg PMU_LVDT_4: voltage threshold is 2.6V - \arg PMU_LVDT_5: voltage threshold is 2.7V - \arg PMU_LVDT_6: voltage threshold is 2.8V - \arg PMU_LVDT_7: voltage threshold is 2.9V + \arg PMU_LVDT_3: voltage threshold is 2.6V + \arg PMU_LVDT_4: voltage threshold is 2.7V + \arg PMU_LVDT_5: voltage threshold is 2.9V + \arg PMU_LVDT_6: voltage threshold is 3.0V + \arg PMU_LVDT_7: voltage threshold is 3.1V \param[out] none \retval none */ -void pmu_lvd_select(uint32_t pmu_lvdt_n) +void pmu_lvd_select(uint32_t lvdt_n) { /* disable LVD */ PMU_CTL &= ~PMU_CTL_LVDEN; /* clear LVDT bits */ PMU_CTL &= ~PMU_CTL_LVDT; /* set LVDT bits according to pmu_lvdt_n */ - PMU_CTL |= pmu_lvdt_n; + PMU_CTL |= lvdt_n; /* enable LVD */ PMU_CTL |= PMU_CTL_LVDEN; } /*! - \brief LDO output voltage select + \brief select LDO output voltage this bit set by software when the main PLL closed, before closing PLL, change the system clock to IRC16M or HXTAL \param[in] ldo_output: \arg PMU_LDOVS_LOW: low-driver mode enable in deep-sleep mode - \arg PMU_LDOVS_MID: low-driver mode disable in deep-sleep mode - \arg PMU_LDOVS_HIGH: low-driver mode disable in deep-sleep mode + \arg PMU_LDOVS_MID: mid-driver mode disable in deep-sleep mode + \arg PMU_LDOVS_HIGH: high-driver mode disable in deep-sleep mode \param[out] none \retval none */ @@ -67,10 +92,10 @@ void pmu_ldo_output_select(uint32_t ldo_output) } /*! - \brief low-driver mode enable in deep-sleep mode + \brief enable low-driver mode in deep-sleep mode \param[in] lowdr_mode: - \arg PMU_LOWDRIVER_ENABLE: low-driver mode enable in deep-sleep mode - \arg PMU_LOWDRIVER_DISABLE: low-driver mode disable in deep-sleep mode + \arg PMU_LOWDRIVER_ENABLE: enable low-driver mode in deep-sleep mode + \arg PMU_LOWDRIVER_DISABLE: disable low-driver mode in deep-sleep mode \param[out] none \retval none */ @@ -81,11 +106,11 @@ void pmu_low_driver_mode_enable(uint32_t lowdr_mode) } /*! - \brief high-driver mode switch + \brief switch high-driver mode this bit set by software only when IRC16M or HXTAL used as system clock \param[in] highdr_switch: - \arg PMU_HIGHDR_SWITCH_NONE: no high-driver mode switch - \arg PMU_HIGHDR_SWITCH_EN: high-driver mode switch + \arg PMU_HIGHDR_SWITCH_NONE: disable high-driver mode switch + \arg PMU_HIGHDR_SWITCH_EN: enable high-driver mode switch \param[out] none \retval none */ @@ -150,8 +175,8 @@ void pmu_lowdriver_lowpower_config(uint32_t mode) /*! \brief low-driver mode when use normal power LDO \param[in] mode: - \arg PMU_NORMALDR_NORMALPWR: normal driver when use low power LDO - \arg PMU_LOWDR_NORMALPWR: low-driver mode enabled when LDEN is 11 and use low power LDO + \arg PMU_NORMALDR_NORMALPWR: normal driver when use normal power LDO + \arg PMU_LOWDR_NORMALPWR: low-driver mode enabled when LDEN is 11 and use normal power LDO \param[out] none \retval none */ @@ -173,7 +198,7 @@ void pmu_to_sleepmode(uint8_t sleepmodecmd) { /* clear sleepdeep bit of Cortex-M4 system control register */ SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); - + /* select WFI or WFE command to enter sleep mode */ if(WFI_CMD == sleepmodecmd){ __WFI(); @@ -184,26 +209,37 @@ void pmu_to_sleepmode(uint8_t sleepmodecmd) /*! \brief PMU work at deepsleep mode - \param[in] pmu_ldo + \param[in] ldo \arg PMU_LDO_NORMAL: LDO normal work when pmu enter deepsleep mode \arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode - \param[in] deepsleepmodecmd: + \param[in] deepsleepmodecmd: \arg WFI_CMD: use WFI command \arg WFE_CMD: use WFE command \param[out] none \retval none */ -void pmu_to_deepsleepmode(uint32_t pmu_ldo,uint8_t deepsleepmodecmd) +void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd) { + static uint32_t reg_snap[ 4 ]; /* clear stbmod and ldolp bits */ PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP)); - + /* set ldolp bit according to pmu_ldo */ - PMU_CTL |= pmu_ldo; - + PMU_CTL |= ldo; + /* set sleepdeep bit of Cortex-M4 system control register */ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - + + reg_snap[ 0 ] = REG32( 0xE000E010U ); + reg_snap[ 1 ] = REG32( 0xE000E100U ); + reg_snap[ 2 ] = REG32( 0xE000E104U ); + reg_snap[ 3 ] = REG32( 0xE000E108U ); + + REG32( 0xE000E010U ) &= 0x00010004U; + REG32( 0xE000E180U ) = 0XFF7FF831U; + REG32( 0xE000E184U ) = 0XBFFFF8FFU; + REG32( 0xE000E188U ) = 0xFFFFEFFFU; + /* select WFI or WFE command to enter deepsleep mode */ if(WFI_CMD == deepsleepmodecmd){ __WFI(); @@ -212,6 +248,12 @@ void pmu_to_deepsleepmode(uint32_t pmu_ldo,uint8_t deepsleepmodecmd) __WFE(); __WFE(); } + + REG32( 0xE000E010U ) = reg_snap[ 0 ] ; + REG32( 0xE000E100U ) = reg_snap[ 1 ] ; + REG32( 0xE000E104U ) = reg_snap[ 2 ] ; + REG32( 0xE000E108U ) = reg_snap[ 3 ] ; + /* reset sleepdeep bit of Cortex-M4 system control register */ SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); } @@ -231,10 +273,10 @@ void pmu_to_standbymode(uint8_t standbymodecmd) /* set stbmod bit */ PMU_CTL |= PMU_CTL_STBMOD; - + /* reset wakeup flag */ PMU_CTL |= PMU_CTL_WURST; - + /* select WFI or WFE command to enter standby mode */ if(WFI_CMD == standbymodecmd){ __WFI(); @@ -282,25 +324,26 @@ void pmu_flag_reset(uint32_t flag_reset) } /*! - \brief get flag status + \brief get flag state \param[in] pmu_flag: - \arg PMU_FLAG_WAKEUP: wakeup flag status - \arg PMU_FLAG_STANDBY: standby flag status - \arg PMU_FLAG_LVD: lvd flag status + \arg PMU_FLAG_WAKEUP: wakeup flag + \arg PMU_FLAG_STANDBY: standby flag + \arg PMU_FLAG_LVD: lvd flag \arg PMU_FLAG_BLDORF: backup SRAM LDO ready flag \arg PMU_FLAG_LDOVSRF: LDO voltage select ready flag \arg PMU_FLAG_HDRF: high-driver ready flag \arg PMU_FLAG_HDSRF: high-driver switch ready flag - \arg PMU_FLAG_LDRF: low-driver mode ready flag + \arg PMU_FLAG_LDRF: low-driver mode ready flag \param[out] none - \retval FlagStatus SET or RESET + \retval FlagStatus: SET or RESET */ -FlagStatus pmu_flag_get(uint32_t pmu_flag ) +FlagStatus pmu_flag_get(uint32_t pmu_flag) { if(PMU_CS & pmu_flag){ return SET; + }else{ + return RESET; } - return RESET; } /*! diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_rcu.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_rcu.c index e37b9f9808..aecc895a09 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_rcu.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_rcu.c @@ -1,21 +1,52 @@ /*! - \file gd32f4xx_rcu.c - \brief RCU driver + \file gd32f4xx_rcu.c + \brief RCU driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.1, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_rcu.h" -#define SEL_IRC16M 0U -#define SEL_HXTAL 1U -#define SEL_PLLP 2U -#define OSC_STARTUP_TIMEOUT ((uint16_t)0xfffffU) -#define LXTAL_STARTUP_TIMEOUT ((uint16_t)0x3ffffffU) +/* define clock source */ +#define SEL_IRC16M ((uint16_t)0U) /* IRC16M is selected as CK_SYS */ +#define SEL_HXTAL ((uint16_t)1U) /* HXTAL is selected as CK_SYS */ +#define SEL_PLLP ((uint16_t)2U) /* PLLP is selected as CK_SYS */ +/* define startup timeout count */ +#define OSC_STARTUP_TIMEOUT ((uint32_t)0x000fffffU) +#define LXTAL_STARTUP_TIMEOUT ((uint32_t)0x0fffffffU) + +/* RCU IRC16M adjust value mask and offset*/ +#define RCU_IRC16M_ADJUST_MASK ((uint8_t)0x1FU) +#define RCU_IRC16M_ADJUST_OFFSET ((uint32_t)3U) /*! \brief deinitialize the RCU @@ -33,8 +64,9 @@ void rcu_deinit(void) RCU_CFG0_RTCDIV | RCU_CFG0_CKOUT0SEL | RCU_CFG0_I2SSEL | RCU_CFG0_CKOUT0DIV | RCU_CFG0_CKOUT1DIV | RCU_CFG0_CKOUT1SEL); /* reset CTL register */ - RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN | RCU_CTL_PLLI2SEN | - RCU_CTL_PLLSAIEN | RCU_CTL_HXTALBPS); + RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN | RCU_CTL_PLLI2SEN + | RCU_CTL_PLLSAIEN); + RCU_CTL &= ~(RCU_CTL_HXTALBPS); /* reset PLL register */ RCU_PLL = 0x24003010U; /* reset PLLI2S register */ @@ -44,7 +76,7 @@ void rcu_deinit(void) /* reset INT register */ RCU_INT = 0x00000000U; /* reset CFG1 register */ - RCU_CFG1 &= ~(RCU_CFG1_PLLSAIRDIV | RCU_CFG1_TIMERSEL); + RCU_CFG1 &= ~(RCU_CFG1_PLLSAIRDIV | RCU_CFG1_TIMERSEL); } /*! @@ -236,7 +268,7 @@ void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph) \arg RCU_GPIOxRST (x=A,B,C,D,E,F,G,H,I): reset GPIO ports \arg RCU_CRCRST: reset CRC \arg RCU_DMAxRST (x=0,1): reset DMA - \arg RCU_IPAENRST: reset IPA + \arg RCU_IPARST: reset IPA \arg RCU_ENETRST: reset ENET \arg RCU_USBHSRST: reset USBHS \arg RCU_DCIRST: reset DCI @@ -273,7 +305,7 @@ void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset) \arg RCU_GPIOxRST (x=A,B,C,D,E,F,G,H,I): reset GPIO ports \arg RCU_CRCRST: reset CRC \arg RCU_DMAxRST (x=0,1): reset DMA - \arg RCU_IPAENRST: reset IPA + \arg RCU_IPARST: reset IPA \arg RCU_ENETRST: reset ENET \arg RCU_USBHSRST: reset USBHS \arg RCU_DCIRST: reset DCI @@ -338,7 +370,7 @@ void rcu_bkp_reset_disable(void) void rcu_system_clock_source_config(uint32_t ck_sys) { uint32_t reg; - + reg = RCU_CFG0; /* reset the SCS bits and set according to ck_sys */ reg &= ~RCU_CFG0_SCS; @@ -370,9 +402,9 @@ uint32_t rcu_system_clock_source_get(void) void rcu_ahb_clock_config(uint32_t ck_ahb) { uint32_t reg; - + reg = RCU_CFG0; - /* reset the AHBPS bits and set according to ck_ahb */ + /* reset the AHBPSC bits and set according to ck_ahb */ reg &= ~RCU_CFG0_AHBPSC; RCU_CFG0 = (reg | ck_ahb); } @@ -392,9 +424,9 @@ void rcu_ahb_clock_config(uint32_t ck_ahb) void rcu_apb1_clock_config(uint32_t ck_apb1) { uint32_t reg; - + reg = RCU_CFG0; - /* reset the APB1PS and set according to ck_apb1 */ + /* reset the APB1PSC and set according to ck_apb1 */ reg &= ~RCU_CFG0_APB1PSC; RCU_CFG0 = (reg | ck_apb1); } @@ -414,9 +446,9 @@ void rcu_apb1_clock_config(uint32_t ck_apb1) void rcu_apb2_clock_config(uint32_t ck_apb2) { uint32_t reg; - + reg = RCU_CFG0; - /* reset the APB2PS and set according to ck_apb2 */ + /* reset the APB2PSC and set according to ck_apb2 */ reg &= ~RCU_CFG0_APB2PSC; RCU_CFG0 = (reg | ck_apb2); } @@ -429,7 +461,7 @@ void rcu_apb2_clock_config(uint32_t ck_apb2) \arg RCU_CKOUT0SRC_LXTAL: LXTAL selected \arg RCU_CKOUT0SRC_HXTAL: HXTAL selected \arg RCU_CKOUT0SRC_PLLP: PLLP selected - \param[in] ckout0_div: CK_OUT0 divider + \param[in] ckout0_div: CK_OUT0 divider \arg RCU_CKOUT0_DIVx(x=1,2,3,4,5): CK_OUT0 is divided by x \param[out] none \retval none @@ -437,7 +469,7 @@ void rcu_apb2_clock_config(uint32_t ck_apb2) void rcu_ckout0_config(uint32_t ckout0_src, uint32_t ckout0_div) { uint32_t reg; - + reg = RCU_CFG0; /* reset the CKOUT0SRC, CKOUT0DIV and set according to ckout0_src and ckout0_div */ reg &= ~(RCU_CFG0_CKOUT0SEL | RCU_CFG0_CKOUT0DIV ); @@ -451,8 +483,8 @@ void rcu_ckout0_config(uint32_t ckout0_src, uint32_t ckout0_div) \arg RCU_CKOUT1SRC_SYSTEMCLOCK: system clock selected \arg RCU_CKOUT1SRC_PLLI2SR: PLLI2SR selected \arg RCU_CKOUT1SRC_HXTAL: HXTAL selected - \arg RCU_CKOUT1SRC_PLLP: PLLP selected - \param[in] ckout1_div: CK_OUT1 divider + \arg RCU_CKOUT1SRC_PLLP: PLLP selected + \param[in] ckout1_div: CK_OUT1 divider \arg RCU_CKOUT1_DIVx(x=1,2,3,4,5): CK_OUT1 is divided by x \param[out] none \retval none @@ -460,7 +492,7 @@ void rcu_ckout0_config(uint32_t ckout0_src, uint32_t ckout0_div) void rcu_ckout1_config(uint32_t ckout1_src, uint32_t ckout1_div) { uint32_t reg; - + reg = RCU_CFG0; /* reset the CKOUT1SRC, CKOUT1DIV and set according to ckout1_src and ckout1_div */ reg &= ~(RCU_CFG0_CKOUT1SEL | RCU_CFG0_CKOUT1DIV); @@ -468,7 +500,7 @@ void rcu_ckout1_config(uint32_t ckout1_src, uint32_t ckout1_div) } /*! - \brief configure the main PLL clock + \brief configure the main PLL clock \param[in] pll_src: PLL clock source selection \arg RCU_PLLSRC_IRC16M: select IRC16M as PLL source clock \arg RCU_PLLSRC_HXTAL: select HXTAL as PLL source clock @@ -487,7 +519,7 @@ ErrStatus rcu_pll_config(uint32_t pll_src, uint32_t pll_psc, uint32_t pll_n, uin { uint32_t ss_modulation_inc; uint32_t ss_modulation_reg; - + ss_modulation_inc = 0U; ss_modulation_reg = RCU_PLLSSCTL; @@ -499,9 +531,9 @@ ErrStatus rcu_pll_config(uint32_t pll_src, uint32_t pll_psc, uint32_t pll_n, uin ss_modulation_inc += RCU_SS_MODULATION_CENTER_INC; } } - + /* check the function parameter */ - if(CHECK_PLL_PSC_VALID(pll_psc) && CHECK_PLL_N_VALID(pll_n,ss_modulation_inc) && + if(CHECK_PLL_PSC_VALID(pll_psc) && CHECK_PLL_N_VALID(pll_n,ss_modulation_inc) && CHECK_PLL_P_VALID(pll_p) && CHECK_PLL_Q_VALID(pll_q)){ RCU_PLL = pll_psc | (pll_n << 6) | (((pll_p >> 1) - 1U) << 16) | (pll_src) | (pll_q << 24); @@ -509,60 +541,55 @@ ErrStatus rcu_pll_config(uint32_t pll_src, uint32_t pll_psc, uint32_t pll_n, uin /* return status */ return ERROR; } - + /* return status */ return SUCCESS; } /*! - \brief configure the PLLI2S clock + \brief configure the PLLI2S clock \param[in] plli2s_n: the PLLI2S VCO clock multi factor \arg this parameter should be selected between 50 and 500 - \param[in] plli2s_q: the PLLI2S Q output frequency division factor from PLLI2S VCO clock - \arg this parameter should be selected between 2 and 15 \param[in] plli2s_r: the PLLI2S R output frequency division factor from PLLI2S VCO clock \arg this parameter should be selected between 2 and 7 \param[out] none \retval ErrStatus: SUCCESS or ERROR */ -ErrStatus rcu_plli2s_config(uint32_t plli2s_n, uint32_t plli2s_q, uint32_t plli2s_r) +ErrStatus rcu_plli2s_config(uint32_t plli2s_n, uint32_t plli2s_r) { /* check the function parameter */ - if(CHECK_PLLI2S_N_VALID(plli2s_n) && CHECK_PLLI2S_Q_VALID(plli2s_q) && CHECK_PLLI2S_R_VALID(plli2s_r)){ - RCU_PLLI2S = (plli2s_n << 6) | (plli2s_q << 24) | (plli2s_r << 28); + if(CHECK_PLLI2S_N_VALID(plli2s_n) && CHECK_PLLI2S_R_VALID(plli2s_r)){ + RCU_PLLI2S = (plli2s_n << 6) | (plli2s_r << 28); }else{ /* return status */ return ERROR; } - + /* return status */ - return SUCCESS; + return SUCCESS; } /*! - \brief configure the PLLSAI clock + \brief configure the PLLSAI clock \param[in] pllsai_n: the PLLSAI VCO clock multi factor \arg this parameter should be selected between 50 and 500 \param[in] pllsai_p: the PLLSAI P output frequency division factor from PLL VCO clock \arg this parameter should be selected 2,4,6,8 - \param[in] pllsai_q: the PLLSAI Q output frequency division factor from PLL VCO clock - \arg this parameter should be selected between 2 and 15 \param[in] pllsai_r: the PLLSAI R output frequency division factor from PLL VCO clock \arg this parameter should be selected between 2 and 7 \param[out] none \retval ErrStatus: SUCCESS or ERROR */ -ErrStatus rcu_pllsai_config(uint32_t pllsai_n, uint32_t pllsai_p, uint32_t pllsai_q, uint32_t pllsai_r) +ErrStatus rcu_pllsai_config(uint32_t pllsai_n, uint32_t pllsai_p, uint32_t pllsai_r) { /* check the function parameter */ - if(CHECK_PLLSAI_N_VALID(pllsai_n) && CHECK_PLLSAI_P_VALID(pllsai_p) && - CHECK_PLLSAI_Q_VALID(pllsai_q) && CHECK_PLLSAI_R_VALID(pllsai_r)){ - RCU_PLLSAI = (pllsai_n << 6U) | (((pllsai_p >> 1U) - 1U) << 16U) | (pllsai_q << 24U) | (pllsai_r << 28U); + if(CHECK_PLLSAI_N_VALID(pllsai_n) && CHECK_PLLSAI_P_VALID(pllsai_p) && CHECK_PLLSAI_R_VALID(pllsai_r)){ + RCU_PLLSAI = (pllsai_n << 6U) | (((pllsai_p >> 1U) - 1U) << 16U) | (pllsai_r << 28U); }else{ /* return status */ return ERROR; } - + /* return status */ return SUCCESS; } @@ -581,13 +608,33 @@ ErrStatus rcu_pllsai_config(uint32_t pllsai_n, uint32_t pllsai_p, uint32_t pllsa void rcu_rtc_clock_config(uint32_t rtc_clock_source) { uint32_t reg; - - reg = RCU_BDCTL; + + reg = RCU_BDCTL; /* reset the RTCSRC bits and set according to rtc_clock_source */ reg &= ~RCU_BDCTL_RTCSRC; RCU_BDCTL = (reg | rtc_clock_source); } +/*! + \brief configure the frequency division of RTC clock when HXTAL was selected as its clock source + \param[in] rtc_div: RTC clock frequency division + only one parameter can be selected which is shown as below: + \arg RCU_RTC_HXTAL_NONE: no clock for RTC + \arg RCU_RTC_HXTAL_DIVx: RTCDIV clock select CK_HXTAL/x, x = 2....31 + \param[out] none + \retval none +*/ +void rcu_rtc_div_config(uint32_t rtc_div) +{ + uint32_t reg; + + reg = RCU_CFG0; + /* reset the RTCDIV bits and set according to rtc_div value */ + reg &= ~RCU_CFG0_RTCDIV; + RCU_CFG0 = (reg | rtc_div); +} + + /*! \brief configure the I2S clock source selection \param[in] i2s_clock_source: I2S clock source selection @@ -600,8 +647,8 @@ void rcu_rtc_clock_config(uint32_t rtc_clock_source) void rcu_i2s_clock_config(uint32_t i2s_clock_source) { uint32_t reg; - - reg = RCU_CFG0; + + reg = RCU_CFG0; /* reset the I2SSEL bit and set according to i2s_clock_source */ reg &= ~RCU_CFG0_I2SSEL; RCU_CFG0 = (reg | i2s_clock_source); @@ -619,9 +666,9 @@ void rcu_i2s_clock_config(uint32_t i2s_clock_source) void rcu_ck48m_clock_config(uint32_t ck48m_clock_source) { uint32_t reg; - + reg = RCU_ADDCTL; - /* reset the I2SSEL bit and set according to i2s_clock_source */ + /* reset the CK48MSEL bit and set according to i2s_clock_source */ reg &= ~RCU_ADDCTL_CK48MSEL; RCU_ADDCTL = (reg | ck48m_clock_source); } @@ -638,7 +685,7 @@ void rcu_ck48m_clock_config(uint32_t ck48m_clock_source) void rcu_pll48m_clock_config(uint32_t pll48m_clock_source) { uint32_t reg; - + reg = RCU_ADDCTL; /* reset the PLL48MSEL bit and set according to pll48m_clock_source */ reg &= ~RCU_ADDCTL_PLL48MSEL; @@ -649,13 +696,13 @@ void rcu_pll48m_clock_config(uint32_t pll48m_clock_source) \brief configure the TIMER clock prescaler selection \param[in] timer_clock_prescaler: TIMER clock selection only one parameter can be selected which is shown as below: - \arg RCU_TIMER_PSC_MUL2: if APB1PSC/APB2PSC in RCU_CFG0 register is 0b0xx(CK_APBx = CK_AHB) + \arg RCU_TIMER_PSC_MUL2: if APB1PSC/APB2PSC in RCU_CFG0 register is 0b0xx(CK_APBx = CK_AHB) or 0b100(CK_APBx = CK_AHB/2), the TIMER clock is equal to CK_AHB(CK_TIMERx = CK_AHB). - or else, the TIMER clock is twice the corresponding APB clock (TIMER in APB1 domain: CK_TIMERx = 2 x CK_APB1; + or else, the TIMER clock is twice the corresponding APB clock (TIMER in APB1 domain: CK_TIMERx = 2 x CK_APB1; TIMER in APB2 domain: CK_TIMERx = 2 x CK_APB2) - \arg RCU_TIMER_PSC_MUL4: if APB1PSC/APB2PSC in RCU_CFG0 register is 0b0xx(CK_APBx = CK_AHB), - 0b100(CK_APBx = CK_AHB/2), or 0b101(CK_APBx = CK_AHB/4), the TIMER clock is equal to CK_AHB(CK_TIMERx = CK_AHB). - or else, the TIMER clock is four timers the corresponding APB clock (TIMER in APB1 domain: CK_TIMERx = 4 x CK_APB1; + \arg RCU_TIMER_PSC_MUL4: if APB1PSC/APB2PSC in RCU_CFG0 register is 0b0xx(CK_APBx = CK_AHB), + 0b100(CK_APBx = CK_AHB/2), or 0b101(CK_APBx = CK_AHB/4), the TIMER clock is equal to CK_AHB(CK_TIMERx = CK_AHB). + or else, the TIMER clock is four timers the corresponding APB clock (TIMER in APB1 domain: CK_TIMERx = 4 x CK_APB1; TIMER in APB2 domain: CK_TIMERx = 4 x CK_APB2) \param[out] none \retval none @@ -681,7 +728,7 @@ void rcu_timer_clock_prescaler_config(uint32_t timer_clock_prescaler) void rcu_tli_clock_div_config(uint32_t pllsai_r_div) { uint32_t reg; - + reg = RCU_CFG1; /* reset the PLLSAIRDIV bit and set according to pllsai_r_div */ reg &= ~RCU_CFG1_PLLSAIRDIV; @@ -735,9 +782,9 @@ void rcu_all_reset_flag_clear(void) \brief get the clock stabilization interrupt and ckm flags \param[in] int_flag: interrupt and ckm flags, refer to rcu_int_flag_enum only one parameter can be selected which is shown as below: - \arg RCU_INT_FLAG_IRC32KSTB: IRC40K stabilization interrupt flag + \arg RCU_INT_FLAG_IRC32KSTB: IRC32K stabilization interrupt flag \arg RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag - \arg RCU_INT_FLAG_IRC8MSTB: IRC8M stabilization interrupt flag + \arg RCU_INT_FLAG_IRC16MSTB: IRC16M stabilization interrupt flag \arg RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag \arg RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag \arg RCU_INT_FLAG_PLLI2SSTB: PLLI2S stabilization interrupt flag @@ -759,7 +806,7 @@ FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag) /*! \brief clear the interrupt flags - \param[in] int_flag_clear: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum + \param[in] int_flag: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum only one parameter can be selected which is shown as below: \arg RCU_INT_FLAG_IRC32KSTB_CLR: IRC32K stabilization interrupt flag clear \arg RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear @@ -773,14 +820,14 @@ FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag) \param[out] none \retval none */ -void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear) +void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag) { - RCU_REG_VAL(int_flag_clear) |= BIT(RCU_BIT_POS(int_flag_clear)); + RCU_REG_VAL(int_flag) |= BIT(RCU_BIT_POS(int_flag)); } /*! \brief enable the stabilization interrupt - \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum + \param[in] interrupt: clock stabilization interrupt, refer to rcu_int_enum Only one parameter can be selected which is shown as below: \arg RCU_INT_IRC32KSTB: IRC32K stabilization interrupt enable \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable @@ -793,15 +840,15 @@ void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear) \param[out] none \retval none */ -void rcu_interrupt_enable(rcu_int_enum stab_int) +void rcu_interrupt_enable(rcu_int_enum interrupt) { - RCU_REG_VAL(stab_int) |= BIT(RCU_BIT_POS(stab_int)); + RCU_REG_VAL(interrupt) |= BIT(RCU_BIT_POS(interrupt)); } /*! \brief disable the stabilization interrupt - \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum + \param[in] interrupt: clock stabilization interrupt, refer to rcu_int_enum only one parameter can be selected which is shown as below: \arg RCU_INT_IRC32KSTB: IRC32K stabilization interrupt disable \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt disable @@ -814,9 +861,9 @@ void rcu_interrupt_enable(rcu_int_enum stab_int) \param[out] none \retval none */ -void rcu_interrupt_disable(rcu_int_enum stab_int) +void rcu_interrupt_disable(rcu_int_enum interrupt) { - RCU_REG_VAL(stab_int) &= ~BIT(RCU_BIT_POS(stab_int)); + RCU_REG_VAL(interrupt) &= ~BIT(RCU_BIT_POS(interrupt)); } /*! @@ -831,9 +878,9 @@ void rcu_interrupt_disable(rcu_int_enum stab_int) void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap) { uint32_t reg; - + reg = RCU_BDCTL; - + /* reset the LXTALDRI bits and set according to lxtal_dricap */ reg &= ~RCU_BDCTL_LXTALDRI; RCU_BDCTL = (reg | lxtal_dricap); @@ -859,7 +906,7 @@ ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci) uint32_t stb_cnt = 0U; ErrStatus reval = ERROR; FlagStatus osci_stat = RESET; - + switch(osci){ /* wait HXTAL stable */ case RCU_HXTAL: @@ -867,7 +914,7 @@ ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci) osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB); stb_cnt++; } - + /* check whether flag is set */ if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)){ reval = SUCCESS; @@ -879,31 +926,31 @@ ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci) osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB); stb_cnt++; } - + /* check whether flag is set */ if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)){ reval = SUCCESS; } break; - /* wait IRC16M stable */ + /* wait IRC16M stable */ case RCU_IRC16M: while((RESET == osci_stat) && (IRC16M_STARTUP_TIMEOUT != stb_cnt)){ osci_stat = rcu_flag_get(RCU_FLAG_IRC16MSTB); stb_cnt++; } - + /* check whether flag is set */ if(RESET != rcu_flag_get(RCU_FLAG_IRC16MSTB)){ reval = SUCCESS; } break; - /* wait IRC48M stable */ + /* wait IRC48M stable */ case RCU_IRC48M: while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ osci_stat = rcu_flag_get(RCU_FLAG_IRC48MSTB); stb_cnt++; } - + /* check whether flag is set */ if (RESET != rcu_flag_get(RCU_FLAG_IRC48MSTB)){ reval = SUCCESS; @@ -915,19 +962,19 @@ ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci) osci_stat = rcu_flag_get(RCU_FLAG_IRC32KSTB); stb_cnt++; } - + /* check whether flag is set */ if(RESET != rcu_flag_get(RCU_FLAG_IRC32KSTB)){ reval = SUCCESS; } break; - /* wait PLL stable */ + /* wait PLL stable */ case RCU_PLL_CK: while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ osci_stat = rcu_flag_get(RCU_FLAG_PLLSTB); stb_cnt++; } - + /* check whether flag is set */ if(RESET != rcu_flag_get(RCU_FLAG_PLLSTB)){ reval = SUCCESS; @@ -939,29 +986,29 @@ ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci) osci_stat = rcu_flag_get(RCU_FLAG_PLLI2SSTB); stb_cnt++; } - + /* check whether flag is set */ if(RESET != rcu_flag_get(RCU_FLAG_PLLI2SSTB)){ reval = SUCCESS; } break; - /* wait PLLSAI stable */ + /* wait PLLSAI stable */ case RCU_PLLSAI_CK: while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ osci_stat = rcu_flag_get(RCU_FLAG_PLLSAISTB); stb_cnt++; } - + /* check whether flag is set */ if(RESET != rcu_flag_get(RCU_FLAG_PLLSAISTB)){ reval = SUCCESS; } break; - + default: break; } - + /* return value */ return reval; } @@ -1010,8 +1057,8 @@ void rcu_osci_off(rcu_osci_type_enum osci) \brief enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it \param[in] osci: oscillator types, refer to rcu_osci_type_enum only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: HXTAL - \arg RCU_LXTAL: LXTAL + \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) + \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) \param[out] none \retval none */ @@ -1020,7 +1067,7 @@ void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci) uint32_t reg; switch(osci){ - /* enable HXTAL to bypass mode */ + /* enable HXTAL to bypass mode */ case RCU_HXTAL: reg = RCU_CTL; RCU_CTL &= ~RCU_CTL_HXTALEN; @@ -1037,7 +1084,7 @@ void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci) case RCU_IRC32K: case RCU_PLL_CK: case RCU_PLLI2S_CK: - case RCU_PLLSAI_CK: + case RCU_PLLSAI_CK: break; default: break; @@ -1048,17 +1095,17 @@ void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci) \brief disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it \param[in] osci: oscillator types, refer to rcu_osci_type_enum only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: HXTAL - \arg RCU_LXTAL: LXTAL + \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) + \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) \param[out] none \retval none */ void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci) { uint32_t reg; - + switch(osci){ - /* disable HXTAL to bypass mode */ + /* disable HXTAL to bypass mode */ case RCU_HXTAL: reg = RCU_CTL; RCU_CTL &= ~RCU_CTL_HXTALEN; @@ -1075,7 +1122,7 @@ void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci) case RCU_IRC32K: case RCU_PLL_CK: case RCU_PLLI2S_CK: - case RCU_PLLSAI_CK: + case RCU_PLLSAI_CK: break; default: break; @@ -1108,17 +1155,18 @@ void rcu_hxtal_clock_monitor_disable(void) /*! \brief set the IRC16M adjust value \param[in] irc16m_adjval: IRC16M adjust value, must be between 0 and 0x1F + \arg 0x00 - 0x1F \param[out] none \retval none */ void rcu_irc16m_adjust_value_set(uint32_t irc16m_adjval) { uint32_t reg; - + reg = RCU_CTL; /* reset the IRC16MADJ bits and set according to irc16m_adjval */ reg &= ~RCU_CTL_IRC16MADJ; - RCU_CTL = (reg | ((irc16m_adjval & 0x1FU) << 3)); + RCU_CTL = (reg | ((irc16m_adjval & RCU_IRC16M_ADJUST_MASK) << RCU_IRC16M_ADJUST_OFFSET)); } /*! @@ -1144,7 +1192,7 @@ void rcu_voltage_key_unlock(void) \retval none */ void rcu_deepsleep_voltage_set(uint32_t dsvol) -{ +{ dsvol &= RCU_DSV_DSLPVS; RCU_DSV = dsvol; } @@ -1155,16 +1203,16 @@ void rcu_deepsleep_voltage_set(uint32_t dsvol) \arg RCU_SS_TYPE_CENTER: center spread type is selected \arg RCU_SS_TYPE_DOWN: down spread type is selected \param[in] modstep: configure PLL spread spectrum modulation profile amplitude and frequency - \arg This parameter should be selected between 0 and 7FFF.The following criteria must be met: MODSTEP*MODCNT=215-1 + \arg This parameter should be selected between 0 and 7FFF.The following criteria must be met: MODSTEP*MODCNT <=2^15-1 \param[in] modcnt: configure PLL spread spectrum modulation profile amplitude and frequency - \arg This parameter should be selected between 0 and 1FFF.The following criteria must be met: MODSTEP*MODCNT=215-1 + \arg This parameter should be selected between 0 and 1FFF.The following criteria must be met: MODSTEP*MODCNT <=2^15-1 \param[out] none \retval none */ void rcu_spread_spectrum_config(uint32_t spread_spectrum_type, uint32_t modstep, uint32_t modcnt) { uint32_t reg; - + reg = RCU_PLLSSCTL; /* reset the RCU_PLLSSCTL register bits */ reg &= ~(RCU_PLLSSCTL_MODCNT | RCU_PLLSSCTL_MODSTEP | RCU_PLLSSCTL_SS_TYPE); @@ -1209,7 +1257,7 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) uint32_t sws, ck_freq = 0U; uint32_t cksys_freq, ahb_freq, apb1_freq, apb2_freq; uint32_t pllpsc, plln, pllsel, pllp, ck_src, idx, clk_exp; - + /* exponent of AHB, APB1 and APB2 clock divider */ const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; const uint8_t apb1_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; @@ -1231,7 +1279,7 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) pllpsc = GET_BITS(RCU_PLL, 0U, 5U); plln = GET_BITS(RCU_PLL, 6U, 14U); pllp = (GET_BITS(RCU_PLL, 16U, 17U) + 1U) * 2U; - /* PLL clock source selection, HXTAL or IRC8M/2 */ + /* PLL clock source selection, HXTAL or IRC16M/2 */ pllsel = (RCU_PLL & RCU_PLL_PLLSEL); if (RCU_PLLSRC_HXTAL == pllsel) { ck_src = HXTAL_VALUE; @@ -1249,17 +1297,17 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) idx = GET_BITS(RCU_CFG0, 4, 7); clk_exp = ahb_exp[idx]; ahb_freq = cksys_freq >> clk_exp; - + /* calculate APB1 clock frequency */ idx = GET_BITS(RCU_CFG0, 10, 12); clk_exp = apb1_exp[idx]; apb1_freq = ahb_freq >> clk_exp; - + /* calculate APB2 clock frequency */ idx = GET_BITS(RCU_CFG0, 13, 15); clk_exp = apb2_exp[idx]; apb2_freq = ahb_freq >> clk_exp; - + /* return the clocks frequency */ switch(clock){ case CK_SYS: diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_rtc.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_rtc.c index 8e2713ceb1..12ee6c3207 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_rtc.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_rtc.c @@ -1,14 +1,40 @@ /*! - \file gd32f4xx_rtc.c - \brief RTC driver + \file gd32f4xx_rtc.c + \brief RTC driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ + #include "gd32f4xx_rtc.h" /* RTC timeout value */ @@ -42,7 +68,7 @@ ErrStatus rtc_deinit(void) error_status = rtc_init_mode_enter(); if(ERROR != error_status){ - /* reset RTC_CTL register, but RTC_CTL[20] */ + /* reset RTC_CTL register, but RTC_CTL[2��0] */ RTC_CTL &= (RTC_REGISTER_RESET | RTC_CTL_WTCS); /* before reset RTC_TIME and RTC_DATE, BPSHAD bit in RTC_CTL should be reset as the condition. in order to read calendar from shadow register, not the real registers being reset */ @@ -50,7 +76,7 @@ ErrStatus rtc_deinit(void) RTC_DATE = RTC_DATE_RESET; RTC_PSC = RTC_PSC_RESET; - /* only when RTC_CTL_WTEN=0 and RTC_STAT_WTWF=1 can write RTC_CTL[20] */ + /* only when RTC_CTL_WTEN=0 and RTC_STAT_WTWF=1 can write RTC_CTL[2��0] */ /* wait until the WTWF flag to be set */ do{ flag_status = RTC_STAT & RTC_STAT_WTWF; @@ -63,7 +89,7 @@ ErrStatus rtc_deinit(void) RTC_WUT = RTC_WUT_RESET; RTC_COSC = RTC_REGISTER_RESET; /* to write RTC_ALRMxSS register, ALRMxEN bit in RTC_CTL register should be reset as the condition */ - RTC_ALRM0TD = RTC_REGISTER_RESET; + RTC_ALRM0TD = RTC_REGISTER_RESET; RTC_ALRM1TD = RTC_REGISTER_RESET; RTC_ALRM0SS = RTC_REGISTER_RESET; RTC_ALRM1SS = RTC_REGISTER_RESET; @@ -71,9 +97,9 @@ ErrStatus rtc_deinit(void) at the same time, RTC_STAT_SOPF bit is reset, as the condition to reset RTC_SHIFTCTL register later */ RTC_STAT = RTC_STAT_RESET; /* reset RTC_SHIFTCTL and RTC_HRFC register, this can be done without the init mode */ - RTC_SHIFTCTL = RTC_REGISTER_RESET; + RTC_SHIFTCTL = RTC_REGISTER_RESET; RTC_HRFC = RTC_REGISTER_RESET; - error_status = rtc_register_sync_wait(); + error_status = rtc_register_sync_wait(); } } @@ -85,7 +111,7 @@ ErrStatus rtc_deinit(void) /*! \brief initialize RTC registers - \param[in] rtc_initpara_struct: pointer to a rtc_parameter_struct structure which contains + \param[in] rtc_initpara_struct: pointer to a rtc_parameter_struct structure which contains parameters for initialization of the rtc peripheral members of the structure and the member values are shown as below: year: 0x0 - 0x99(BCD format) @@ -112,13 +138,13 @@ ErrStatus rtc_init(rtc_parameter_struct* rtc_initpara_struct) reg_date = (DATE_YR(rtc_initpara_struct->year) | \ DATE_DOW(rtc_initpara_struct->day_of_week) | \ DATE_MON(rtc_initpara_struct->month) | \ - DATE_DAY(rtc_initpara_struct->date)); - + DATE_DAY(rtc_initpara_struct->date)); + reg_time = (rtc_initpara_struct->am_pm| \ TIME_HR(rtc_initpara_struct->hour) | \ TIME_MN(rtc_initpara_struct->minute) | \ - TIME_SC(rtc_initpara_struct->second)); - + TIME_SC(rtc_initpara_struct->second)); + /* 1st: disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; @@ -126,7 +152,7 @@ ErrStatus rtc_init(rtc_parameter_struct* rtc_initpara_struct) /* 2nd: enter init mode */ error_status = rtc_init_mode_enter(); - if(ERROR != error_status){ + if(ERROR != error_status){ RTC_PSC = (uint32_t)(PSC_FACTOR_A(rtc_initpara_struct->factor_asyn)| \ PSC_FACTOR_S(rtc_initpara_struct->factor_syn)); @@ -135,11 +161,11 @@ ErrStatus rtc_init(rtc_parameter_struct* rtc_initpara_struct) RTC_CTL &= (uint32_t)(~RTC_CTL_CS); RTC_CTL |= rtc_initpara_struct->display_format; - - /* 3rd: exit init mode */ + + /* 3rd: exit init mode */ rtc_init_mode_exit(); - - /* 4th: wait the RSYNF flag to set */ + + /* 4th: wait the RSYNF flag to set */ error_status = rtc_register_sync_wait(); } @@ -162,15 +188,15 @@ ErrStatus rtc_init_mode_enter(void) ErrStatus error_status = ERROR; /* check whether it has been in init mode */ - if ((uint32_t)RESET == (RTC_STAT & RTC_STAT_INITF)){ + if ((uint32_t)RESET == (RTC_STAT & RTC_STAT_INITF)){ RTC_STAT |= RTC_STAT_INITM; - + /* wait until the INITF flag to be set */ do{ flag_status = RTC_STAT & RTC_STAT_INITF; }while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); - if ((uint32_t)RESET != flag_status){ + if ((uint32_t)RESET != flag_status){ error_status = SUCCESS; } }else{ @@ -191,7 +217,7 @@ void rtc_init_mode_exit(void) } /*! - \brief wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow + \brief wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow registers are updated \param[in] none \param[out] none @@ -216,13 +242,13 @@ ErrStatus rtc_register_sync_wait(void) flag_status = RTC_STAT & RTC_STAT_RSYNF; }while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); - if ((uint32_t)RESET != flag_status){ + if ((uint32_t)RESET != flag_status){ error_status = SUCCESS; } - + /* enable the write protection */ RTC_WPK = RTC_LOCK_KEY; - }else{ + }else{ error_status = SUCCESS; } @@ -232,7 +258,7 @@ ErrStatus rtc_register_sync_wait(void) /*! \brief get current time and date \param[in] none - \param[out] rtc_initpara_struct: pointer to a rtc_parameter_struct structure which contains + \param[out] rtc_initpara_struct: pointer to a rtc_parameter_struct structure which contains parameters for initialization of the rtc peripheral members of the structure and the member values are shown as below: year: 0x0 - 0x99(BCD format) @@ -254,22 +280,22 @@ void rtc_current_time_get(rtc_parameter_struct* rtc_initpara_struct) { uint32_t temp_tr = 0U, temp_dr = 0U, temp_pscr = 0U, temp_ctlr = 0U; - temp_tr = (uint32_t)RTC_TIME; + temp_tr = (uint32_t)RTC_TIME; temp_dr = (uint32_t)RTC_DATE; temp_pscr = (uint32_t)RTC_PSC; temp_ctlr = (uint32_t)RTC_CTL; - + /* get current time and construct rtc_parameter_struct structure */ rtc_initpara_struct->year = (uint8_t)GET_DATE_YR(temp_dr); rtc_initpara_struct->month = (uint8_t)GET_DATE_MON(temp_dr); rtc_initpara_struct->date = (uint8_t)GET_DATE_DAY(temp_dr); - rtc_initpara_struct->day_of_week = (uint8_t)GET_DATE_DOW(temp_dr); + rtc_initpara_struct->day_of_week = (uint8_t)GET_DATE_DOW(temp_dr); rtc_initpara_struct->hour = (uint8_t)GET_TIME_HR(temp_tr); rtc_initpara_struct->minute = (uint8_t)GET_TIME_MN(temp_tr); rtc_initpara_struct->second = (uint8_t)GET_TIME_SC(temp_tr); rtc_initpara_struct->factor_asyn = (uint16_t)GET_PSC_FACTOR_A(temp_pscr); rtc_initpara_struct->factor_syn = (uint16_t)GET_PSC_FACTOR_S(temp_pscr); - rtc_initpara_struct->am_pm = (uint32_t)(temp_pscr & RTC_TIME_PM); + rtc_initpara_struct->am_pm = (uint32_t)(temp_pscr & RTC_TIME_PM); rtc_initpara_struct->display_format = (uint32_t)(temp_ctlr & RTC_CTL_CS); } @@ -293,7 +319,7 @@ uint32_t rtc_subsecond_get(void) /*! \brief configure RTC alarm \param[in] rtc_alarm: RTC_ALARM0 or RTC_ALARM1 - \param[in] rtc_alarm_time: pointer to a rtc_alarm_struct structure which contains + \param[in] rtc_alarm_time: pointer to a rtc_alarm_struct structure which contains parameters for RTC alarm configuration members of the structure and the member values are shown as below: alarm_mask: RTC_ALARM_NONE_MASK, RTC_ALARM_DATE_MASK, RTC_ALARM_HOUR_MASK @@ -327,7 +353,7 @@ void rtc_alarm_config(uint8_t rtc_alarm, rtc_alarm_struct* rtc_alarm_time) if(RTC_ALARM0 == rtc_alarm){ RTC_ALRM0TD = (uint32_t)reg_alrmtd; - + }else{ RTC_ALRM1TD = (uint32_t)reg_alrmtd; } @@ -363,12 +389,12 @@ void rtc_alarm_subsecond_config(uint8_t rtc_alarm, uint32_t mask_subsecond, uint { /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; + RTC_WPK = RTC_UNLOCK_KEY2; if(RTC_ALARM0 == rtc_alarm){ - RTC_ALRM0SS = mask_subsecond | subsecond; + RTC_ALRM0SS = mask_subsecond | subsecond; }else{ - RTC_ALRM1SS = mask_subsecond | subsecond; + RTC_ALRM1SS = mask_subsecond | subsecond; } /* enable the write protection */ RTC_WPK = RTC_LOCK_KEY; @@ -377,7 +403,7 @@ void rtc_alarm_subsecond_config(uint8_t rtc_alarm, uint32_t mask_subsecond, uint /*! \brief get RTC alarm \param[in] rtc_alarm: RTC_ALARM0 or RTC_ALARM1 - \param[out] rtc_alarm_time: pointer to a rtc_alarm_struct structure which contains + \param[out] rtc_alarm_time: pointer to a rtc_alarm_struct structure which contains parameters for RTC alarm configuration members of the structure and the member values are shown as below: alarm_mask: RTC_ALARM_NONE_MASK, RTC_ALARM_DATE_MASK, RTC_ALARM_HOUR_MASK @@ -403,13 +429,13 @@ void rtc_alarm_get(uint8_t rtc_alarm, rtc_alarm_struct* rtc_alarm_time) reg_alrmtd = RTC_ALRM1TD; } /* get alarm parameters and construct the rtc_alarm_struct structure */ - rtc_alarm_time->alarm_mask = reg_alrmtd & RTC_ALARM_ALL_MASK; + rtc_alarm_time->alarm_mask = reg_alrmtd & RTC_ALARM_ALL_MASK; rtc_alarm_time->am_pm = (uint32_t)(reg_alrmtd & RTC_ALRMXTD_PM); rtc_alarm_time->weekday_or_date = (uint32_t)(reg_alrmtd & RTC_ALRMXTD_DOWS); rtc_alarm_time->alarm_day = (uint8_t)GET_ALRMTD_DAY(reg_alrmtd); rtc_alarm_time->alarm_hour = (uint8_t)GET_ALRMTD_HR(reg_alrmtd); rtc_alarm_time->alarm_minute = (uint8_t)GET_ALRMTD_MN(reg_alrmtd); - rtc_alarm_time->alarm_second = (uint8_t)GET_ALRMTD_SC(reg_alrmtd); + rtc_alarm_time->alarm_second = (uint8_t)GET_ALRMTD_SC(reg_alrmtd); } /*! @@ -463,23 +489,23 @@ ErrStatus rtc_alarm_disable(uint8_t rtc_alarm) /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; - + /* clear the state of alarm */ if(RTC_ALARM0 == rtc_alarm){ - RTC_CTL &= (uint32_t)(~RTC_CTL_ALRM0EN); + RTC_CTL &= (uint32_t)(~RTC_CTL_ALRM0EN); /* wait until ALRM0WF flag to be set after the alarm is disabled */ do{ flag_status = RTC_STAT & RTC_STAT_ALRM0WF; - }while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); + }while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); }else{ - RTC_CTL &= (uint32_t)(~RTC_CTL_ALRM1EN); + RTC_CTL &= (uint32_t)(~RTC_CTL_ALRM1EN); /* wait until ALRM1WF flag to be set after the alarm is disabled */ do{ flag_status = RTC_STAT & RTC_STAT_ALRM1WF; }while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); } - - if ((uint32_t)RESET != flag_status){ + + if ((uint32_t)RESET != flag_status){ error_status = SUCCESS; } @@ -506,7 +532,7 @@ void rtc_timestamp_enable(uint32_t edge) /* new configuration */ reg_ctl |= (uint32_t)(edge | RTC_CTL_TSEN); - + /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; @@ -528,7 +554,7 @@ void rtc_timestamp_disable(void) /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; - + /* clear the TSEN bit */ RTC_CTL &= (uint32_t)(~ RTC_CTL_TSEN); @@ -539,7 +565,7 @@ void rtc_timestamp_disable(void) /*! \brief get RTC timestamp time and date \param[in] none - \param[out] rtc_timestamp: pointer to a rtc_timestamp_struct structure which contains + \param[out] rtc_timestamp: pointer to a rtc_timestamp_struct structure which contains parameters for RTC time-stamp configuration members of the structure and the member values are shown as below: timestamp_month: RTC_JAN, RTC_FEB, RTC_MAR, RTC_APR, RTC_MAY, RTC_JUN, @@ -560,7 +586,7 @@ void rtc_timestamp_get(rtc_timestamp_struct* rtc_timestamp) /* get the value of time_stamp registers */ temp_tts = (uint32_t)RTC_TTS; temp_dts = (uint32_t)RTC_DTS; - + /* get timestamp time and construct the rtc_timestamp_struct structure */ rtc_timestamp->am_pm = (uint32_t)(temp_tts & RTC_TTS_PM); rtc_timestamp->timestamp_month = (uint8_t)GET_DTS_MON(temp_dts); @@ -583,7 +609,7 @@ uint32_t rtc_timestamp_subsecond_get(void) } /*! - \brief RTC time-stamp mapping + \brief RTC time-stamp mapping \param[in] rtc_af: \arg RTC_AF0_TIMESTAMP: RTC_AF0 use for timestamp \arg RTC_AF1_TIMESTAMP: RTC_AF1 use for timestamp @@ -598,13 +624,19 @@ void rtc_timestamp_pin_map(uint32_t rtc_af) /*! \brief enable RTC tamper - \param[in] rtc_tamper: pointer to a rtc_tamper_struct structure which contains + \param[in] rtc_tamper: pointer to a rtc_tamper_struct structure which contains parameters for RTC tamper configuration members of the structure and the member values are shown as below: + detecting tamper event can using edge mode or level mode + (1) using edge mode configuration: tamper_source: RTC_TAMPER0, RTC_TAMPER1 tamper_trigger: RTC_TAMPER_TRIGGER_EDGE_RISING, RTC_TAMPER_TRIGGER_EDGE_FALLING - RTC_TAMPER_TRIGGER_LEVEL_LOW, RTC_TAMPER_TRIGGER_LEVEL_HIGH - tamper_filter: RTC_FLT_EDGE, RTC_FLT_2S, RTC_FLT_4S, RTC_FLT_8S + tamper_filter: RTC_FLT_EDGE + tamper_with_timestamp: DISABLE, ENABLE + (2) using level mode configuration: + tamper_source: RTC_TAMPER0, RTC_TAMPER1 + tamper_trigger:RTC_TAMPER_TRIGGER_LEVEL_LOW, RTC_TAMPER_TRIGGER_LEVEL_HIGH + tamper_filter: RTC_FLT_2S, RTC_FLT_4S, RTC_FLT_8S tamper_sample_frequency: RTC_FREQ_DIV32768, RTC_FREQ_DIV16384, RTC_FREQ_DIV8192, RTC_FREQ_DIV4096, RTC_FREQ_DIV2048, RTC_FREQ_DIV1024, RTC_FREQ_DIV512, RTC_FREQ_DIV256 @@ -617,40 +649,46 @@ void rtc_timestamp_pin_map(uint32_t rtc_af) void rtc_tamper_enable(rtc_tamper_struct* rtc_tamper) { /* disable tamper */ - RTC_TAMP &= (uint32_t)~(rtc_tamper->tamper_source); + RTC_TAMP &= (uint32_t)~(rtc_tamper->tamper_source); /* tamper filter must be used when the tamper source is voltage level detection */ RTC_TAMP &= (uint32_t)~RTC_TAMP_FLT; - + /* the tamper source is voltage level detection */ - if((uint32_t)(rtc_tamper->tamper_filter) != RTC_FLT_EDGE ){ + if((uint32_t)(rtc_tamper->tamper_filter) != RTC_FLT_EDGE ){ RTC_TAMP &= (uint32_t)~(RTC_TAMP_DISPU | RTC_TAMP_PRCH | RTC_TAMP_FREQ | RTC_TAMP_FLT); /* check if the tamper pin need precharge, if need, then configure the precharge time */ if(DISABLE == rtc_tamper->tamper_precharge_enable){ - RTC_TAMP |= (uint32_t)RTC_TAMP_DISPU; + RTC_TAMP |= (uint32_t)RTC_TAMP_DISPU; }else{ RTC_TAMP |= (uint32_t)(rtc_tamper->tamper_precharge_time); } RTC_TAMP |= (uint32_t)(rtc_tamper->tamper_sample_frequency); RTC_TAMP |= (uint32_t)(rtc_tamper->tamper_filter); + + /* configure the tamper trigger */ + RTC_TAMP &= ((uint32_t)~((rtc_tamper->tamper_source) << RTC_TAMPER_TRIGGER_POS)); + if(RTC_TAMPER_TRIGGER_LEVEL_LOW != rtc_tamper->tamper_trigger){ + RTC_TAMP |= (uint32_t)((rtc_tamper->tamper_source)<< RTC_TAMPER_TRIGGER_POS); + } + }else{ + + /* configure the tamper trigger */ + RTC_TAMP &= ((uint32_t)~((rtc_tamper->tamper_source) << RTC_TAMPER_TRIGGER_POS)); + if(RTC_TAMPER_TRIGGER_EDGE_RISING != rtc_tamper->tamper_trigger){ + RTC_TAMP |= (uint32_t)((rtc_tamper->tamper_source)<< RTC_TAMPER_TRIGGER_POS); + } } - - RTC_TAMP &= (uint32_t)~RTC_TAMP_TPTS; - - if(DISABLE != rtc_tamper->tamper_with_timestamp){ + + RTC_TAMP &= (uint32_t)~RTC_TAMP_TPTS; + if(DISABLE != rtc_tamper->tamper_with_timestamp){ /* the tamper event also cause a time-stamp event */ RTC_TAMP |= (uint32_t)RTC_TAMP_TPTS; - } - - /* configure the tamper trigger */ - RTC_TAMP &= ((uint32_t)~((rtc_tamper->tamper_source) << RTC_TAMPER_TRIGGER_POS)); - if(RTC_TAMPER_TRIGGER_EDGE_RISING != rtc_tamper->tamper_trigger){ - RTC_TAMP |= (uint32_t)((rtc_tamper->tamper_source)<< RTC_TAMPER_TRIGGER_POS); - } + } /* enable tamper */ - RTC_TAMP |= (uint32_t)(rtc_tamper->tamper_source); + RTC_TAMP |= (uint32_t)(rtc_tamper->tamper_source); } /*! @@ -664,12 +702,12 @@ void rtc_tamper_enable(rtc_tamper_struct* rtc_tamper) void rtc_tamper_disable(uint32_t source) { /* disable tamper */ - RTC_TAMP &= (uint32_t)~source; + RTC_TAMP &= (uint32_t)~source; } /*! - \brief RTC tamper0 mapping + \brief RTC tamper0 mapping \param[in] rtc_af: \arg RTC_AF0_TAMPER0: RTC_AF0 use for tamper0 \arg RTC_AF1_TAMPER0: RTC_AF1 use for tamper0 @@ -681,30 +719,31 @@ void rtc_tamper0_pin_map(uint32_t rtc_af) RTC_TAMP &= ~(RTC_TAMP_TP0EN | RTC_TAMP_TP0SEL); RTC_TAMP |= rtc_af; } + /*! \brief enable specified RTC interrupt \param[in] interrupt: specify which interrupt source to be enabled \arg RTC_INT_TIMESTAMP: timestamp interrupt \arg RTC_INT_ALARM0: alarm0 interrupt \arg RTC_INT_ALARM1: alarm1 interrupt - \arg RTC_INT_TAMP: tamp interrupt + \arg RTC_INT_TAMP: tamper detection interrupt \arg RTC_INT_WAKEUP: wakeup timer interrupt \param[out] none \retval none */ void rtc_interrupt_enable(uint32_t interrupt) -{ +{ /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; - + /* enable the interrupts in RTC_CTL register */ RTC_CTL |= (uint32_t)(interrupt & (uint32_t)~RTC_TAMP_TPIE); /* enable the interrupts in RTC_TAMP register */ RTC_TAMP |= (uint32_t)(interrupt & RTC_TAMP_TPIE); - + /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; + RTC_WPK = RTC_LOCK_KEY; } /*! @@ -713,17 +752,17 @@ void rtc_interrupt_enable(uint32_t interrupt) \arg RTC_INT_TIMESTAMP: timestamp interrupt \arg RTC_INT_ALARM0: alarm interrupt \arg RTC_INT_ALARM1: alarm interrupt - \arg RTC_INT_TAMP: tamp interrupt + \arg RTC_INT_TAMP: tamper detection interrupt \arg RTC_INT_WAKEUP: wakeup timer interrupt \param[out] none \retval none */ void rtc_interrupt_disable(uint32_t interrupt) -{ +{ /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; - + /* disable the interrupts in RTC_CTL register */ RTC_CTL &= (uint32_t)~(interrupt & (uint32_t)~RTC_TAMP_TPIE); /* disable the interrupts in RTC_TAMP register */ @@ -736,28 +775,28 @@ void rtc_interrupt_disable(uint32_t interrupt) /*! \brief check specified flag \param[in] flag: specify which flag to check - \arg RTC_STAT_RECPF: recalibration pending flag - \arg RTC_STAT_TP1F: tamper 1 event flag - \arg RTC_STAT_TP0F: tamper 0 event flag - \arg RTC_STAT_TSOVRF: time-stamp overflow event flag - \arg RTC_STAT_TSF: time-stamp event flag - \arg RTC_STAT_ALRM0F: alarm0 event flag - \arg RTC_STAT_ALRM1F: alarm1 event flag - \arg RTC_STAT_WTF: wakeup timer event flag - \arg RTC_STAT_INITF: init mode event flag - \arg RTC_STAT_RSYNF: time and date registers synchronized event flag - \arg RTC_STAT_YCM: year parameter configured event flag - \arg RTC_STAT_SOPF: shift operation pending flag - \arg RTC_STAT_ALRM0WF: alarm0 writen available flag - \arg RTC_STAT_ALRM1WF: alarm1 writen available flag - \arg RTC_STAT_WTWF: wakeup timer writen available flag + \arg RTC_STAT_SCP: smooth calibration pending flag + \arg RTC_FLAG_TP1: RTC tamper 1 detected flag + \arg RTC_FLAG_TP0: RTC tamper 0 detected flag + \arg RTC_FLAG_TSOVR: time-stamp overflow flag + \arg RTC_FLAG_TS: time-stamp flag + \arg RTC_FLAG_ALARM0: alarm0 occurs flag + \arg RTC_FLAG_ALARM1: alarm1 occurs flag + \arg RTC_FLAG_WT: wakeup timer occurs flag + \arg RTC_FLAG_INIT: initialization state flag + \arg RTC_FLAG_RSYN: register synchronization flag + \arg RTC_FLAG_YCM: year configuration mark status flag + \arg RTC_FLAG_SOP: shift function operation pending flag + \arg RTC_FLAG_ALRM0W: alarm0 configuration can be write flag + \arg RTC_FLAG_ALRM1W: alarm1 configuration can be write flag + \arg RTC_FLAG_WTW: wakeup timer can be write flag \param[out] none \retval FlagStatus: SET or RESET */ FlagStatus rtc_flag_get(uint32_t flag) { FlagStatus flag_state = RESET; - + if ((uint32_t)RESET != (RTC_STAT & flag)){ flag_state = SET; } @@ -766,21 +805,20 @@ FlagStatus rtc_flag_get(uint32_t flag) /*! \brief clear specified flag - \param[in] flag: specify which flag to clear - \arg RTC_STAT_TP1F: tamper 1 event flag - \arg RTC_STAT_TP0F: tamper 0 event flag - \arg RTC_STAT_TSOVRF: time-stamp overflow event flag - \arg RTC_STAT_TSF: time-stamp event flag - \arg RTC_STAT_WTF: time-stamp event flag - \arg RTC_STAT_ALRM0F: alarm0 event flag - \arg RTC_STAT_ALRM1F: alarm1 event flag - \arg RTC_STAT_RSYNF: time and date registers synchronized event flag + \arg RTC_FLAG_TP1: RTC tamper 1 detected flag + \arg RTC_FLAG_TP0: RTC tamper 0 detected flag + \arg RTC_FLAG_TSOVR: time-stamp overflow flag + \arg RTC_FLAG_TS: time-stamp flag + \arg RTC_FLAG_WT: wakeup timer occurs flag + \arg RTC_FLAG_ALARM0: alarm0 occurs flag + \arg RTC_FLAG_ALARM1: alarm1 occurs flag + \arg RTC_FLAG_RSYN: register synchronization flag \param[out] none \retval none */ void rtc_flag_clear(uint32_t flag) { - RTC_STAT &= (uint32_t)(~flag); + RTC_STAT &= (uint32_t)(~flag); } /*! @@ -818,10 +856,10 @@ void rtc_alarm_output_config(uint32_t source, uint32_t mode) /*! \brief configure rtc calibration output source \param[in] source: specify signal to output - \arg RTC_CALIBRATION_512HZ: when the LSE freqency is 32768Hz and the RTC_PSC + \arg RTC_CALIBRATION_512HZ: when the LSE freqency is 32768Hz and the RTC_PSC is the default value, output 512Hz signal - \arg RTC_CALIBRATION_1HZ: when the LSE freqency is 32768Hz and the RTC_PSC - is the default value, output 512Hz signal + \arg RTC_CALIBRATION_1HZ: when the LSE freqency is 32768Hz and the RTC_PSC + is the default value, output 1Hz signal \param[out] none \retval none */ @@ -852,7 +890,7 @@ void rtc_hour_adjust(uint32_t operation) /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; - + RTC_CTL |= (uint32_t)(operation); /* enable the write protection */ @@ -877,17 +915,17 @@ ErrStatus rtc_second_adjust(uint32_t add, uint32_t minus) /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; - - /* check if a shift operation is ongoing */ + + /* check if a shift operation is ongoing */ do{ flag_status = RTC_STAT & RTC_STAT_SOPF; }while((--time_index > 0U) && ((uint32_t)RESET != flag_status)); - + /* check if the function of reference clock detection is disabled */ temp = RTC_CTL & RTC_CTL_REFEN; - if((RESET == flag_status) && (RESET == temp)){ + if((RESET == flag_status) && (RESET == temp)){ RTC_SHIFTCTL = (uint32_t)(add | SHIFTCTL_SFS(minus)); - error_status = rtc_register_sync_wait(); + error_status = rtc_register_sync_wait(); } /* enable the write protection */ @@ -903,7 +941,7 @@ ErrStatus rtc_second_adjust(uint32_t add, uint32_t minus) \retval none */ void rtc_bypass_shadow_enable(void) -{ +{ /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; @@ -921,7 +959,7 @@ void rtc_bypass_shadow_enable(void) \retval none */ void rtc_bypass_shadow_disable(void) -{ +{ /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; @@ -941,7 +979,7 @@ void rtc_bypass_shadow_disable(void) ErrStatus rtc_refclock_detection_enable(void) { ErrStatus error_status = ERROR; - + /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; @@ -970,7 +1008,7 @@ ErrStatus rtc_refclock_detection_enable(void) ErrStatus rtc_refclock_detection_disable(void) { ErrStatus error_status = ERROR; - + /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; @@ -978,7 +1016,7 @@ ErrStatus rtc_refclock_detection_disable(void) /* enter init mode */ error_status = rtc_init_mode_enter(); - if(ERROR != error_status){ + if(ERROR != error_status){ RTC_CTL &= (uint32_t)~RTC_CTL_REFEN; /* exit init mode */ rtc_init_mode_exit(); @@ -1000,7 +1038,7 @@ void rtc_wakeup_enable(void) { /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; + RTC_WPK = RTC_UNLOCK_KEY2; RTC_CTL |= RTC_CTL_WTEN; @@ -1041,12 +1079,12 @@ ErrStatus rtc_wakeup_disable(void) /*! \brief set RTC auto wakeup timer clock \param[in] wakeup_clock: - \arg WAKEUP_RTCCK_DIV16: RTC auto wakeup timer clock is RTC clock divided by 16 - \arg WAKEUP_RTCCK_DIV8: RTC auto wakeup timer clock is RTC clock divided by 8 - \arg WAKEUP_RTCCK_DIV4: RTC auto wakeup timer clock is RTC clock divided by 4 - \arg WAKEUP_RTCCK_DIV2: RTC auto wakeup timer clock is RTC clock divided by 2 + \arg WAKEUP_RTCCK_DIV16: RTC auto wakeup timer clock is RTC clock divided by 16 + \arg WAKEUP_RTCCK_DIV8: RTC auto wakeup timer clock is RTC clock divided by 8 + \arg WAKEUP_RTCCK_DIV4: RTC auto wakeup timer clock is RTC clock divided by 4 + \arg WAKEUP_RTCCK_DIV2: RTC auto wakeup timer clock is RTC clock divided by 2 \arg WAKEUP_CKSPRE: RTC auto wakeup timer clock is ckspre - \arg WAKEUP_CKSPRE_2EXP16: RTC auto wakeup timer clock is ckspre and wakeup timer add 2exp16 + \arg WAKEUP_CKSPRE_2EXP16: RTC auto wakeup timer clock is ckspre and wakeup timer add 2exp16 \param[out] none \retval ErrStatus: ERROR or SUCCESS */ @@ -1057,8 +1095,8 @@ ErrStatus rtc_wakeup_clock_set(uint8_t wakeup_clock) uint32_t flag_status = RESET; /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - /* only when RTC_CTL_WTEN=0 and RTC_STAT_WTWF=1 can write RTC_CTL[20] */ + RTC_WPK = RTC_UNLOCK_KEY2; + /* only when RTC_CTL_WTEN=0 and RTC_STAT_WTWF=1 can write RTC_CTL[2��0] */ /* wait until the WTWF flag to be set */ do{ flag_status = RTC_STAT & RTC_STAT_WTWF; @@ -1073,7 +1111,7 @@ ErrStatus rtc_wakeup_clock_set(uint8_t wakeup_clock) } /* enable the write protection */ RTC_WPK = RTC_LOCK_KEY; - + return error_status; } @@ -1136,16 +1174,16 @@ ErrStatus rtc_smooth_calibration_config(uint32_t window, uint32_t plus, uint32_t volatile uint32_t time_index = RTC_HRFC_TIMEOUT; ErrStatus error_status = ERROR; uint32_t flag_status = RESET; - + /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* check if a smooth calibration operation is ongoing */ + RTC_WPK = RTC_UNLOCK_KEY2; + + /* check if a smooth calibration operation is ongoing */ do{ flag_status = RTC_STAT & RTC_STAT_SCPF; }while((--time_index > 0U) && ((uint32_t)RESET != flag_status)); - + if((uint32_t)RESET == flag_status){ RTC_HRFC = (uint32_t)(window | plus | HRFC_CMSK(minus)); error_status = SUCCESS; @@ -1172,12 +1210,12 @@ ErrStatus rtc_coarse_calibration_enable(void) /* enter init mode */ error_status = rtc_init_mode_enter(); - if(ERROR != error_status){ + if(ERROR != error_status){ RTC_CTL |= (uint32_t)RTC_CTL_CCEN; /* exit init mode */ rtc_init_mode_exit(); } - + /* enable the write protection */ RTC_WPK = RTC_LOCK_KEY; return error_status; @@ -1194,24 +1232,24 @@ ErrStatus rtc_coarse_calibration_disable(void) ErrStatus error_status = ERROR; /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; + RTC_WPK = RTC_UNLOCK_KEY2; /* enter init mode */ error_status = rtc_init_mode_enter(); - if(ERROR != error_status){ + if(ERROR != error_status){ RTC_CTL &= (uint32_t)~RTC_CTL_CCEN; /* exit init mode */ rtc_init_mode_exit(); } - + /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; + RTC_WPK = RTC_LOCK_KEY; return error_status; } /*! \brief config coarse calibration direction and step - \param[in] direction: CALIB_INCREASE or CALIB_DECREASE + \param[in] direction: CALIB_INCREASE or CALIB_DECREASE \param[in] step: 0x00-0x1F COSD=0: 0x00:+0 PPM @@ -1234,11 +1272,11 @@ ErrStatus rtc_coarse_calibration_config(uint8_t direction, uint8_t step) /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; - + /* enter init mode */ error_status = rtc_init_mode_enter(); - if(ERROR != error_status){ + if(ERROR != error_status){ if(CALIB_DECREASE == direction){ RTC_COSC |= (uint32_t)RTC_COSC_COSD; }else{ @@ -1249,9 +1287,9 @@ ErrStatus rtc_coarse_calibration_config(uint8_t direction, uint8_t step) /* exit init mode */ rtc_init_mode_exit(); } - + /* enable the write protection */ RTC_WPK = RTC_LOCK_KEY; - + return error_status; } diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_sdio.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_sdio.c index f7b26358b5..d1d0a0be32 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_sdio.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_sdio.c @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_sdio.c - \brief SDIO driver + \file gd32f4xx_sdio.c + \brief SDIO driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.1, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_sdio.h" @@ -26,12 +51,15 @@ void sdio_deinit(void) /*! \brief configure the SDIO clock \param[in] clock_edge: SDIO_CLK clock edge + only one parameter can be selected which is shown as below: \arg SDIO_SDIOCLKEDGE_RISING: select the rising edge of the SDIOCLK to generate SDIO_CLK \arg SDIO_SDIOCLKEDGE_FALLING: select the falling edge of the SDIOCLK to generate SDIO_CLK \param[in] clock_bypass: clock bypass + only one parameter can be selected which is shown as below: \arg SDIO_CLOCKBYPASS_ENABLE: clock bypass \arg SDIO_CLOCKBYPASS_DISABLE: no bypass \param[in] clock_powersave: SDIO_CLK clock dynamic switch on/off for power saving + only one parameter can be selected which is shown as below: \arg SDIO_CLOCKPWRSAVE_ENABLE: SDIO_CLK closed when bus is idle \arg SDIO_CLOCKPWRSAVE_DISABLE: SDIO_CLK clock is always on \param[in] clock_division: clock division, less than 512 @@ -79,6 +107,7 @@ void sdio_hardware_clock_disable(void) /*! \brief set different SDIO card bus mode \param[in] bus_mode: SDIO card bus mode + only one parameter can be selected which is shown as below: \arg SDIO_BUSMODE_1BIT: 1-bit SDIO card bus mode \arg SDIO_BUSMODE_4BIT: 4-bit SDIO card bus mode \arg SDIO_BUSMODE_8BIT: 8-bit SDIO card bus mode @@ -95,6 +124,7 @@ void sdio_bus_mode_set(uint32_t bus_mode) /*! \brief set the SDIO power state \param[in] power_state: SDIO power state + only one parameter can be selected which is shown as below: \arg SDIO_POWER_ON: SDIO power on \arg SDIO_POWER_OFF: SDIO power off \param[out] none @@ -105,7 +135,6 @@ void sdio_power_state_set(uint32_t power_state) SDIO_PWRCTL = power_state; } -/* get the SDIO power state */ /*! \brief get the SDIO power state \param[in] none @@ -146,6 +175,7 @@ void sdio_clock_disable(void) \param[in] cmd_index: command index, refer to the related specifications \param[in] cmd_argument: command argument, refer to the related specifications \param[in] response_type: response type + only one parameter can be selected which is shown as below: \arg SDIO_RESPONSETYPE_NO: no response \arg SDIO_RESPONSETYPE_SHORT: short response \arg SDIO_RESPONSETYPE_LONG: long response @@ -155,6 +185,8 @@ void sdio_clock_disable(void) void sdio_command_response_config(uint32_t cmd_index, uint32_t cmd_argument, uint32_t response_type) { uint32_t cmd_config = 0U; + /* disable the CSM */ + SDIO_CMDCTL &= ~SDIO_CMDCTL_CSMEN; /* reset the command index, command argument and response type */ SDIO_CMDAGMT &= ~SDIO_CMDAGMT_CMDAGMT; SDIO_CMDAGMT = cmd_argument; @@ -168,6 +200,7 @@ void sdio_command_response_config(uint32_t cmd_index, uint32_t cmd_argument, uin /*! \brief set the command state machine wait type \param[in] wait_type: wait type + only one parameter can be selected which is shown as below: \arg SDIO_WAITTYPE_NO: not wait interrupt \arg SDIO_WAITTYPE_INTERRUPT: wait interrupt \arg SDIO_WAITTYPE_DATAEND: wait the end of data transfer @@ -218,6 +251,7 @@ uint8_t sdio_command_index_get(void) /*! \brief get the response for the last received command \param[in] sdio_responsex: SDIO response + only one parameter can be selected which is shown as below: \arg SDIO_RESPONSE0: card response[31:0]/card response[127:96] \arg SDIO_RESPONSE1: card response[95:64] \arg SDIO_RESPONSE2: card response[63:32] @@ -252,6 +286,7 @@ uint32_t sdio_response_get(uint32_t sdio_responsex) \param[in] data_timeout: data timeout period in card bus clock periods \param[in] data_length: number of data bytes to be transferred \param[in] data_blocksize: size of data block for block transfer + only one parameter can be selected which is shown as below: \arg SDIO_DATABLOCKSIZE_1BYTE: block size = 1 byte \arg SDIO_DATABLOCKSIZE_2BYTES: block size = 2 bytes \arg SDIO_DATABLOCKSIZE_4BYTES: block size = 4 bytes @@ -285,9 +320,11 @@ void sdio_data_config(uint32_t data_timeout, uint32_t data_length, uint32_t data /*! \brief configure the data transfer mode and direction \param[in] transfer_mode: mode of data transfer + only one parameter can be selected which is shown as below: \arg SDIO_TRANSMODE_BLOCK: block transfer \arg SDIO_TRANSMODE_STREAM: stream transfer or SDIO multibyte transfer \param[in] transfer_direction: data transfer direction, read or write + only one parameter can be selected which is shown as below: \arg SDIO_TRANSDIRECTION_TOCARD: write data to card \arg SDIO_TRANSDIRECTION_TOSDIO: read data from card \param[out] none @@ -394,6 +431,7 @@ void sdio_dma_disable(void) /*! \brief get the flags state of SDIO \param[in] flag: flags state of SDIO + one or more parameters can be selected which are shown as below: \arg SDIO_FLAG_CCRCERR: command response received (CRC check failed) flag \arg SDIO_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag \arg SDIO_FLAG_CMDTMOUT: command response timeout flag @@ -433,6 +471,7 @@ FlagStatus sdio_flag_get(uint32_t flag) /*! \brief clear the pending flags of SDIO \param[in] flag: flags state of SDIO + one or more parameters can be selected which are shown as below: \arg SDIO_FLAG_CCRCERR: command response received (CRC check failed) flag \arg SDIO_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag \arg SDIO_FLAG_CMDTMOUT: command response timeout flag @@ -457,6 +496,7 @@ void sdio_flag_clear(uint32_t flag) /*! \brief enable the SDIO interrupt \param[in] int_flag: interrupt flags state of SDIO + one or more parameters can be selected which are shown as below: \arg SDIO_INT_CCRCERR: SDIO CCRCERR interrupt \arg SDIO_INT_DTCRCERR: SDIO DTCRCERR interrupt \arg SDIO_INT_CMDTMOUT: SDIO CMDTMOUT interrupt @@ -492,6 +532,7 @@ void sdio_interrupt_enable(uint32_t int_flag) /*! \brief disable the SDIO interrupt \param[in] int_flag: interrupt flags state of SDIO + one or more parameters can be selected which are shown as below: \arg SDIO_INT_CCRCERR: SDIO CCRCERR interrupt \arg SDIO_INT_DTCRCERR: SDIO DTCRCERR interrupt \arg SDIO_INT_CMDTMOUT: SDIO CMDTMOUT interrupt @@ -527,30 +568,31 @@ void sdio_interrupt_disable(uint32_t int_flag) /*! \brief get the interrupt flags state of SDIO \param[in] int_flag: interrupt flags state of SDIO - \arg SDIO_INT_CCRCERR: SDIO CCRCERR interrupt - \arg SDIO_INT_DTCRCERR: SDIO DTCRCERR interrupt - \arg SDIO_INT_CMDTMOUT: SDIO CMDTMOUT interrupt - \arg SDIO_INT_DTTMOUT: SDIO DTTMOUT interrupt - \arg SDIO_INT_TXURE: SDIO TXURE interrupt - \arg SDIO_INT_RXORE: SDIO RXORE interrupt - \arg SDIO_INT_CMDRECV: SDIO CMDRECV interrupt - \arg SDIO_INT_CMDSEND: SDIO CMDSEND interrupt - \arg SDIO_INT_DTEND: SDIO DTEND interrupt - \arg SDIO_INT_STBITE: SDIO STBITE interrupt - \arg SDIO_INT_DTBLKEND: SDIO DTBLKEND interrupt - \arg SDIO_INT_CMDRUN: SDIO CMDRUN interrupt - \arg SDIO_INT_TXRUN: SDIO TXRUN interrupt - \arg SDIO_INT_RXRUN: SDIO RXRUN interrupt - \arg SDIO_INT_TFH: SDIO TFH interrupt - \arg SDIO_INT_RFH: SDIO RFH interrupt - \arg SDIO_INT_TFF: SDIO TFF interrupt - \arg SDIO_INT_RFF: SDIO RFF interrupt - \arg SDIO_INT_TFE: SDIO TFE interrupt - \arg SDIO_INT_RFE: SDIO RFE interrupt - \arg SDIO_INT_TXDTVAL: SDIO TXDTVAL interrupt - \arg SDIO_INT_RXDTVAL: SDIO RXDTVAL interrupt - \arg SDIO_INT_SDIOINT: SDIO SDIOINT interrupt - \arg SDIO_INT_ATAEND: SDIO ATAEND interrupt + one or more parameters can be selected which are shown as below: + \arg SDIO_INT_FLAG_CCRCERR: SDIO CCRCERR interrupt flag + \arg SDIO_INT_FLAG_DTCRCERR: SDIO DTCRCERR interrupt flag + \arg SDIO_INT_FLAG_CMDTMOUT: SDIO CMDTMOUT interrupt flag + \arg SDIO_INT_FLAG_DTTMOUT: SDIO DTTMOUT interrupt flag + \arg SDIO_INT_FLAG_TXURE: SDIO TXURE interrupt flag + \arg SDIO_INT_FLAG_RXORE: SDIO RXORE interrupt flag + \arg SDIO_INT_FLAG_CMDRECV: SDIO CMDRECV interrupt flag + \arg SDIO_INT_FLAG_CMDSEND: SDIO CMDSEND interrupt flag + \arg SDIO_INT_FLAG_DTEND: SDIO DTEND interrupt flag + \arg SDIO_INT_FLAG_STBITE: SDIO STBITE interrupt flag + \arg SDIO_INT_FLAG_DTBLKEND: SDIO DTBLKEND interrupt flag + \arg SDIO_INT_FLAG_CMDRUN: SDIO CMDRUN interrupt flag + \arg SDIO_INT_FLAG_TXRUN: SDIO TXRUN interrupt flag + \arg SDIO_INT_FLAG_RXRUN: SDIO RXRUN interrupt flag + \arg SDIO_INT_FLAG_TFH: SDIO TFH interrupt flag + \arg SDIO_INT_FLAG_RFH: SDIO RFH interrupt flag + \arg SDIO_INT_FLAG_TFF: SDIO TFF interrupt flag + \arg SDIO_INT_FLAG_RFF: SDIO RFF interrupt flag + \arg SDIO_INT_FLAG_TFE: SDIO TFE interrupt flag + \arg SDIO_INT_FLAG_RFE: SDIO RFE interrupt flag + \arg SDIO_INT_FLAG_TXDTVAL: SDIO TXDTVAL interrupt flag + \arg SDIO_INT_FLAG_RXDTVAL: SDIO RXDTVAL interrupt flag + \arg SDIO_INT_FLAG_SDIOINT: SDIO SDIOINT interrupt flag + \arg SDIO_INT_FLAG_ATAEND: SDIO ATAEND interrupt flag \param[out] none \retval FlagStatus: SET or RESET */ @@ -566,19 +608,20 @@ FlagStatus sdio_interrupt_flag_get(uint32_t int_flag) /*! \brief clear the interrupt pending flags of SDIO \param[in] int_flag: interrupt flags state of SDIO - \arg SDIO_INT_CCRCERR: command response received (CRC check failed) flag - \arg SDIO_INT_DTCRCERR: data block sent/received (CRC check failed) flag - \arg SDIO_INT_CMDTMOUT: command response timeout flag - \arg SDIO_INT_DTTMOUT: data timeout flag - \arg SDIO_INT_TXURE: transmit FIFO underrun error occurs flag - \arg SDIO_INT_RXORE: received FIFO overrun error occurs flag - \arg SDIO_INT_CMDRECV: command response received (CRC check passed) flag - \arg SDIO_INT_CMDSEND: command sent (no response required) flag - \arg SDIO_INT_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag - \arg SDIO_INT_STBITE: start bit error in the bus flag - \arg SDIO_INT_DTBLKEND: data block sent/received (CRC check passed) flag - \arg SDIO_INT_SDIOINT: SD I/O interrupt received flag - \arg SDIO_INT_ATAEND: CE-ATA command completion signal received (only for CMD61) flag + one or more parameters can be selected which are shown as below: + \arg SDIO_INT_FLAG_CCRCERR: command response received (CRC check failed) flag + \arg SDIO_INT_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag + \arg SDIO_INT_FLAG_CMDTMOUT: command response timeout flag + \arg SDIO_INT_FLAG_DTTMOUT: data timeout flag + \arg SDIO_INT_FLAG_TXURE: transmit FIFO underrun error occurs flag + \arg SDIO_INT_FLAG_RXORE: received FIFO overrun error occurs flag + \arg SDIO_INT_FLAG_CMDRECV: command response received (CRC check passed) flag + \arg SDIO_INT_FLAG_CMDSEND: command sent (no response required) flag + \arg SDIO_INT_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag + \arg SDIO_INT_FLAG_STBITE: start bit error in the bus flag + \arg SDIO_INT_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag + \arg SDIO_INT_FLAG_SDIOINT: SD I/O interrupt received flag + \arg SDIO_INT_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag \param[out] none \retval none */ @@ -634,6 +677,7 @@ void sdio_stop_readwait_disable(void) /*! \brief set the read wait type(SD I/O only) \param[in] readwait_type: SD I/O read wait type + only one parameter can be selected which is shown as below: \arg SDIO_READWAITTYPE_CLK: read wait control by stopping SDIO_CLK \arg SDIO_READWAITTYPE_DAT2: read wait control using SDIO_DAT[2] \param[out] none diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_spi.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_spi.c index c5947cf174..3f842251fc 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_spi.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_spi.c @@ -1,23 +1,53 @@ /*! - \file gd32f4xx_spi.c - \brief SPI driver + \file gd32f4xx_spi.c + \brief SPI driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.1, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ + #include "gd32f4xx_spi.h" #include "gd32f4xx_rcu.h" -#define SPI_INIT_MASK ((uint32_t)0x00003040U) -#define I2S_INIT_MASK ((uint32_t)0x0000F047U) -#define I2S_FULL_DUPLEX_MASK ((uint32_t)0x0000F040U) +/* SPI/I2S parameter initialization mask */ +#define SPI_INIT_MASK ((uint32_t)0x00003040U) /*!< SPI parameter initialization mask */ +#define I2S_INIT_MASK ((uint32_t)0x0000F047U) /*!< I2S parameter initialization mask */ +#define I2S_FULL_DUPLEX_MASK ((uint32_t)0x00000480U) /*!< I2S full duples mode configure parameter initialization mask */ + +/* default value */ +#define SPI_I2SPSC_DEFAULT_VALUE ((uint32_t)0x00000002U) /*!< default value of SPI_I2SPSC register */ /*! - \brief SPI and I2S reset + \brief deinitialize SPI and I2S \param[in] spi_periph: SPIx(x=0,1,2,3,4,5),include I2S1_ADD and I2S2_ADD \param[out] none \retval none @@ -26,7 +56,7 @@ void spi_i2s_deinit(uint32_t spi_periph) { switch(spi_periph){ case SPI0: - /* reset SPI0 and I2S0 */ + /* reset SPI0 */ rcu_periph_reset_enable(RCU_SPI0RST); rcu_periph_reset_disable(RCU_SPI0RST); break; @@ -41,12 +71,12 @@ void spi_i2s_deinit(uint32_t spi_periph) rcu_periph_reset_disable(RCU_SPI2RST); break; case SPI3: - /* reset SPI3 and I2S3 */ + /* reset SPI3 */ rcu_periph_reset_enable(RCU_SPI3RST); rcu_periph_reset_disable(RCU_SPI3RST); break; case SPI4: - /* reset SPI4 and I2S4 */ + /* reset SPI4 */ rcu_periph_reset_enable(RCU_SPI4RST); rcu_periph_reset_disable(RCU_SPI4RST); break; @@ -61,41 +91,58 @@ void spi_i2s_deinit(uint32_t spi_periph) } /*! - \brief SPI parameter initialization + \brief initialize the parameters of SPI struct with default values + \param[in] none + \param[out] spi_parameter_struct: the initialized struct spi_parameter_struct pointer + \retval none +*/ +void spi_struct_para_init(spi_parameter_struct *spi_struct) +{ + /* configure the structure with default value */ + spi_struct->device_mode = SPI_SLAVE; + spi_struct->trans_mode = SPI_TRANSMODE_FULLDUPLEX; + spi_struct->frame_size = SPI_FRAMESIZE_8BIT; + spi_struct->nss = SPI_NSS_HARD; + spi_struct->clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; + spi_struct->prescale = SPI_PSC_2; + spi_struct->endian = SPI_ENDIAN_MSB; +} +/*! + \brief initialize SPI parameter \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[in] spi_struct: SPI parameter initialization stuct - members of the structure and the member values are shown as below: - device_mode : SPI_MASTER, SPI_SLAVE. - trans_mode : SPI_TRANSMODE_FULLDUPLEX, SPI_TRANSMODE_RECEIVEONLY, - SPI_TRANSMODE_BDRECEIVE, SPI_TRANSMODE_BDTRANSMIT - frame_size : SPI_FRAMESIZE_16BIT, SPI_FRAMESIZE_8BIT - nss: : SPI_NSS_SOFT, SPI_NSS_HARD - endian : SPI_ENDIAN_MSB, SPI_ENDIAN_LSB - clock_polarity_phase : SPI_CK_PL_LOW_PH_1EDGE, SPI_CK_PL_HIGH_PH_1EDGE - SPI_CK_PL_LOW_PH_2EDGE, SPI_CK_PL_HIGH_PH_2EDGE - prescale : SPI_PSC_n (n=2,4,8,16,32,64,128,256) + \param[in] spi_struct: SPI parameter initialization stuct members of the structure + and the member values are shown as below: + device_mode: SPI_MASTER, SPI_SLAVE. + trans_mode: SPI_TRANSMODE_FULLDUPLEX, SPI_TRANSMODE_RECEIVEONLY, + SPI_TRANSMODE_BDRECEIVE, SPI_TRANSMODE_BDTRANSMIT + frame_size: SPI_FRAMESIZE_16BIT, SPI_FRAMESIZE_8BIT + nss: SPI_NSS_SOFT, SPI_NSS_HARD + endian: SPI_ENDIAN_MSB, SPI_ENDIAN_LSB + clock_polarity_phase: SPI_CK_PL_LOW_PH_1EDGE, SPI_CK_PL_HIGH_PH_1EDGE + SPI_CK_PL_LOW_PH_2EDGE, SPI_CK_PL_HIGH_PH_2EDGE + prescale: SPI_PSC_n (n=2,4,8,16,32,64,128,256) \param[out] none \retval none */ void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct) -{ +{ uint32_t reg = 0U; reg = SPI_CTL0(spi_periph); reg &= SPI_INIT_MASK; - /* (1) select SPI as master or slave */ + /* select SPI as master or slave */ reg |= spi_struct->device_mode; - /* (2) select SPI transfer mode */ + /* select SPI transfer mode */ reg |= spi_struct->trans_mode; - /* (3) select SPI frame size */ + /* select SPI frame size */ reg |= spi_struct->frame_size; - /* (4) select SPI nss use hardware or software */ + /* select SPI nss use hardware or software */ reg |= spi_struct->nss; - /* (5) select SPI LSB or MSB */ + /* select SPI LSB or MSB */ reg |= spi_struct->endian; - /* (6) select SPI polarity and phase */ + /* select SPI polarity and phase */ reg |= spi_struct->clock_polarity_phase; - /* (7) select SPI prescale to adjust transmit speed */ + /* select SPI prescale to adjust transmit speed */ reg |= spi_struct->prescale; /* write to SPI_CTL0 register */ @@ -105,7 +152,7 @@ void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct) } /*! - \brief SPI enable + \brief enable SPI \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[out] none \retval none @@ -116,7 +163,7 @@ void spi_enable(uint32_t spi_periph) } /*! - \brief SPI disable + \brief disable SPI \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[out] none \retval none @@ -127,24 +174,69 @@ void spi_disable(uint32_t spi_periph) } /*! - \brief I2S prescale config - \param[in] spi_periph: SPIx(x=0,1,2,3,4) - \param[in] audiosample: - \arg I2S_AUDIOSAMPLE_8K: audio sample rate is 8khz - \arg I2S_AUDIOSAMPLE_11K: audio sample rate is 11khz - \arg I2S_AUDIOSAMPLE_16K: audio sample rate is 16khz - \arg I2S_AUDIOSAMPLE_22K: audio sample rate is 22khz - \arg I2S_AUDIOSAMPLE_32K: audio sample rate is 32khz - \arg I2S_AUDIOSAMPLE_44K: audio sample rate is 44khz - \arg I2S_AUDIOSAMPLE_48K: audio sample rate is 48khz - \arg I2S_AUDIOSAMPLE_96K: audio sample rate is 96khz - \arg I2S_AUDIOSAMPLE_192K: audio sample rate is 192khz - \param[in] frameformat: + \brief initialize I2S parameter + \param[in] spi_periph: SPIx(x=1,2) + \param[in] i2s_mode: I2S operation mode + only one parameter can be selected which is shown as below: + \arg I2S_MODE_SLAVETX : I2S slave transmit mode + \arg I2S_MODE_SLAVERX : I2S slave receive mode + \arg I2S_MODE_MASTERTX : I2S master transmit mode + \arg I2S_MODE_MASTERRX : I2S master receive mode + \param[in] i2s_standard: I2S standard + only one parameter can be selected which is shown as below: + \arg I2S_STD_PHILLIPS : I2S phillips standard + \arg I2S_STD_MSB : I2S MSB standard + \arg I2S_STD_LSB : I2S LSB standard + \arg I2S_STD_PCMSHORT : I2S PCM short standard + \arg I2S_STD_PCMLONG : I2S PCM long standard + \param[in] i2s_ckpl: I2S idle state clock polarity + only one parameter can be selected which is shown as below: + \arg I2S_CKPL_LOW : I2S clock polarity low level + \arg I2S_CKPL_HIGH : I2S clock polarity high level + \param[out] none + \retval none +*/ +void i2s_init(uint32_t spi_periph, uint32_t i2s_mode, uint32_t i2s_standard, uint32_t i2s_ckpl) +{ + uint32_t reg= 0U; + reg = SPI_I2SCTL(spi_periph); + reg &= I2S_INIT_MASK; + + /* enable I2S mode */ + reg |= (uint32_t)SPI_I2SCTL_I2SSEL; + /* select I2S mode */ + reg |= (uint32_t)i2s_mode; + /* select I2S standard */ + reg |= (uint32_t)i2s_standard; + /* select I2S polarity */ + reg |= (uint32_t)i2s_ckpl; + + /* write to SPI_I2SCTL register */ + SPI_I2SCTL(spi_periph) = (uint32_t)reg; +} + +/*! + \brief configure I2S prescale + \param[in] spi_periph: SPIx(x=1,2) + \param[in] i2s_audiosample: I2S audio sample rate + only one parameter can be selected which is shown as below: + \arg I2S_AUDIOSAMPLE_8K: audio sample rate is 8KHz + \arg I2S_AUDIOSAMPLE_11K: audio sample rate is 11KHz + \arg I2S_AUDIOSAMPLE_16K: audio sample rate is 16KHz + \arg I2S_AUDIOSAMPLE_22K: audio sample rate is 22KHz + \arg I2S_AUDIOSAMPLE_32K: audio sample rate is 32KHz + \arg I2S_AUDIOSAMPLE_44K: audio sample rate is 44KHz + \arg I2S_AUDIOSAMPLE_48K: audio sample rate is 48KHz + \arg I2S_AUDIOSAMPLE_96K: audio sample rate is 96KHz + \arg I2S_AUDIOSAMPLE_192K: audio sample rate is 192KHz + \param[in] i2s_frameformat: I2S data length and channel length + only one parameter can be selected which is shown as below: \arg I2S_FRAMEFORMAT_DT16B_CH16B: I2S data length is 16 bit and channel length is 16 bit \arg I2S_FRAMEFORMAT_DT16B_CH32B: I2S data length is 16 bit and channel length is 32 bit \arg I2S_FRAMEFORMAT_DT24B_CH32B: I2S data length is 24 bit and channel length is 32 bit \arg I2S_FRAMEFORMAT_DT32B_CH32B: I2S data length is 32 bit and channel length is 32 bit - \param[in] mckout: + \param[in] i2s_mckout: I2S master clock output + only one parameter can be selected which is shown as below: \arg I2S_MCKOUT_ENABLE: I2S master clock output enable \arg I2S_MCKOUT_DISABLE: I2S master clock output disable \param[out] none @@ -152,8 +244,8 @@ void spi_disable(uint32_t spi_periph) */ void i2s_psc_config(uint32_t spi_periph, uint32_t i2s_audiosample, uint32_t i2s_frameformat, uint32_t i2s_mckout) { - uint32_t temp_div = 2U, temp_of = 0U; - uint32_t temp = 0U; + uint32_t i2sdiv = 2U, i2sof = 0U; + uint32_t clks = 0U; uint32_t i2sclock = 0U; #ifndef I2S_EXTERNAL_CLOCK_IN @@ -161,7 +253,7 @@ void i2s_psc_config(uint32_t spi_periph, uint32_t i2s_audiosample, uint32_t i2s_ #endif /* I2S_EXTERNAL_CLOCK_IN */ /* deinit SPI_I2SPSC register */ - SPI_I2SPSC(spi_periph) = 0x0002U; + SPI_I2SPSC(spi_periph) = SPI_I2SPSC_DEFAULT_VALUE; #ifdef I2S_EXTERNAL_CLOCK_IN rcu_i2s_clock_config(RCU_I2SSRC_I2S_CKIN); @@ -201,28 +293,28 @@ void i2s_psc_config(uint32_t spi_periph, uint32_t i2s_audiosample, uint32_t i2s_ /* config the prescaler depending on the mclk output state, the frame format and audio sample rate */ if(I2S_MCKOUT_ENABLE == i2s_mckout){ - temp = (uint32_t)(((i2sclock / 256U) * 10U) / i2s_audiosample); + clks = (uint32_t)(((i2sclock / 256U) * 10U) / i2s_audiosample); }else{ if(I2S_FRAMEFORMAT_DT16B_CH16B == i2s_frameformat){ - temp = (uint32_t)(((i2sclock / 32U) *10U ) / i2s_audiosample); + clks = (uint32_t)(((i2sclock / 32U) *10U ) / i2s_audiosample); }else{ - temp = (uint32_t)(((i2sclock / 64U) *10U ) / i2s_audiosample); + clks = (uint32_t)(((i2sclock / 64U) *10U ) / i2s_audiosample); } } /* remove the floating point */ - temp = (temp + 5U) / 10U; - temp_of = (temp & 0x00000001U); - temp_div = ((temp - temp_of) / 2U); - temp_of = (temp_of << 8); + clks = (clks + 5U) / 10U; + i2sof = (clks & 0x00000001U); + i2sdiv = ((clks - i2sof) / 2U); + i2sof = (i2sof << 8U); /* set the default values */ - if((temp_div< 2U) || (temp_div > 255U)){ - temp_div = 2U; - temp_of = 0U; + if((i2sdiv< 2U) || (i2sdiv > 255U)){ + i2sdiv = 2U; + i2sof = 0U; } /* configure SPI_I2SPSC */ - SPI_I2SPSC(spi_periph) = (uint32_t)(temp_div | temp_of | i2s_mckout); + SPI_I2SPSC(spi_periph) = (uint32_t)(i2sdiv | i2sof | i2s_mckout); /* clear SPI_I2SCTL_DTLEN and SPI_I2SCTL_CHLEN bits */ SPI_I2SCTL(spi_periph) &= (uint32_t)(~(SPI_I2SCTL_DTLEN|SPI_I2SCTL_CHLEN)); @@ -231,47 +323,8 @@ void i2s_psc_config(uint32_t spi_periph, uint32_t i2s_audiosample, uint32_t i2s_ } /*! - \brief I2S parameter configuration - \param[in] spi_periph: SPIx(x=0,1,2,3,4) - \param[in] i2s_mode: - \arg I2S_MODE_SLAVETX : I2S slave transmit mode - \arg I2S_MODE_SLAVERX : I2S slave receive mode - \arg I2S_MODE_MASTERTX : I2S master transmit mode - \arg I2S_MODE_MASTERRX : I2S master receive mode - \param[in] i2s_std: - \arg I2S_STD_PHILLIPS : I2S phillips standard - \arg I2S_STD_MSB : I2S MSB standard - \arg I2S_STD_LSB : I2S LSB standard - \arg I2S_STD_PCMSHORT : I2S PCM short standard - \arg I2S_STD_PCMLONG : I2S PCM long standard - \param[in] i2s_ckpl: - \arg I2S_CKPL_LOW : I2S clock polarity low level - \arg I2S_CKPL_HIGH : I2S clock polarity high level - \param[out] none - \retval none -*/ -void i2s_init(uint32_t spi_periph, uint32_t i2s_mode, uint32_t i2s_standard, uint32_t i2s_ckpl) -{ - uint32_t reg= 0U; - reg = SPI_I2SCTL(spi_periph); - reg &= I2S_INIT_MASK; - - /* enable I2S mode */ - reg |= (uint32_t)SPI_I2SCTL_I2SSEL; - /* select I2S mode */ - reg |= (uint32_t)i2s_mode; - /* select I2S standard */ - reg |= (uint32_t)i2s_standard; - /* select I2S polarity */ - reg |= (uint32_t)i2s_ckpl; - - /* write to SPI_I2SCTL register */ - SPI_I2SCTL(spi_periph) = (uint32_t)reg; -} - -/*! - \brief I2S enable - \param[in] spi_periph: SPIx(x=0,1,2,3,4) + \brief enable I2S + \param[in] spi_periph: SPIx(x=1,2) \param[out] none \retval none */ @@ -281,8 +334,8 @@ void i2s_enable(uint32_t spi_periph) } /*! - \brief I2S disable - \param[in] spi_periph: SPIx(x=0,1,2,3,4) + \brief disable I2S + \param[in] spi_periph: SPIx(x=1,2) \param[out] none \retval none */ @@ -292,7 +345,7 @@ void i2s_disable(uint32_t spi_periph) } /*! - \brief SPI nss output enable + \brief enable SPI nss output \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[out] none \retval none @@ -303,7 +356,7 @@ void spi_nss_output_enable(uint32_t spi_periph) } /*! - \brief SPI nss output disable + \brief disable SPI nss output \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[out] none \retval none @@ -336,11 +389,12 @@ void spi_nss_internal_low(uint32_t spi_periph) } /*! - \brief SPI dma send or receive enable + \brief enable SPI DMA send or receive \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[in] spi_dma: - \arg SPI_DMA_TRANSMIT: enable DMA transmit - \arg SPI_DMA_RECEIVE: enable DMA receive + \param[in] spi_dma: SPI DMA mode + only one parameter can be selected which is shown as below: + \arg SPI_DMA_TRANSMIT: SPI transmit data use DMA + \arg SPI_DMA_RECEIVE: SPI receive data use DMA \param[out] none \retval none */ @@ -354,11 +408,12 @@ void spi_dma_enable(uint32_t spi_periph, uint8_t spi_dma) } /*! - \brief SPI dma send or receive diable + \brief diable SPI DMA send or receive \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[in] spi_dma: - \arg SPI_DMA_TRANSMIT: disable DMA transmit - \arg SPI_DMA_RECEIVE: disable DMA receive + \param[in] spi_dma: SPI DMA mode + only one parameter can be selected which is shown as below: + \arg SPI_DMA_TRANSMIT: SPI transmit data use DMA + \arg SPI_DMA_RECEIVE: SPI receive data use DMA \param[out] none \retval none */ @@ -374,7 +429,8 @@ void spi_dma_disable(uint32_t spi_periph, uint8_t spi_dma) /*! \brief configure SPI/I2S data frame format \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[in] frame_format: + \param[in] frame_format: SPI frame size + only one parameter can be selected which is shown as below: \arg SPI_FRAMESIZE_16BIT: SPI frame size is 16 bits \arg SPI_FRAMESIZE_8BIT: SPI frame size is 8 bits \param[out] none @@ -384,7 +440,7 @@ void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format { /* clear SPI_CTL0_FF16 bit */ SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16); - /* confige SPI_CTL0_FF16 bit */ + /* configure SPI_CTL0_FF16 bit */ SPI_CTL0(spi_periph) |= (uint32_t)frame_format; } @@ -401,7 +457,7 @@ void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data) } /*! - \brief receive data + \brief SPI receive data \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[out] none \retval 16-bit data @@ -414,16 +470,17 @@ uint16_t spi_i2s_data_receive(uint32_t spi_periph) /*! \brief configure SPI bidirectional transfer direction \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[in] transfer_direction: - \arg SPI_BIDIRECTIONAL_TEANSMIT: SPI work in transmit-only mode + \param[in] transfer_direction: SPI transfer direction + only one parameter can be selected which is shown as below: + \arg SPI_BIDIRECTIONAL_TRANSMIT: SPI work in transmit-only mode \arg SPI_BIDIRECTIONAL_RECEIVE: SPI work in receive-only mode \retval none */ void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction) { - if(SPI_BIDIRECTIONAL_TEANSMIT == transfer_direction){ + if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction){ /* set the transmit only mode */ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TEANSMIT; + SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT; }else{ /* set the receive only mode */ SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE; @@ -431,188 +488,7 @@ void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_di } /*! - \brief SPI and I2S interrupt enable - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[in] spi_i2s_int: - \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt - \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt - \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, - transmission underrun error and format error interrupt - \param[out] none - \retval none -*/ -void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t spi_i2s_int) -{ - switch(spi_i2s_int){ - case SPI_I2S_INT_TBE: - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE; - break; - case SPI_I2S_INT_RBNE: - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_RBNEIE; - break; - case SPI_I2S_INT_ERR: - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE; - break; - default: - break; - } -} - -/*! - \brief SPI and I2S interrupt disable - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[in] spi_i2s_int: - \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt - \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt - \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, - transmission underrun error and format error interrupt - \param[out] none - \retval none -*/ -void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t spi_i2s_int) -{ - switch(spi_i2s_int){ - case SPI_I2S_INT_TBE : - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE); - break; - case SPI_I2S_INT_RBNE : - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RBNEIE); - break; - case SPI_I2S_INT_ERR : - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE); - break; - default : - break; - } -} - -/*! - \brief get interrupt flag status - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[in] spi_i2s_int: - \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt - \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt - \arg SPI_I2S_INT_RXORERR: overrun interrupt - \arg SPI_INT_CONFERR: config error interrupt - \arg SPI_INT_CRCERR: CRC error interrupt - \arg I2S_INT_TXURERR: underrun error interrupt - \arg SPI_I2S_INT_FERR: format error interrupt - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t spi_i2s_int) -{ - uint32_t reg1 = SPI_STAT(spi_periph); - uint32_t reg2 = SPI_CTL1(spi_periph); - - uint32_t temp1 = 0U; - uint32_t temp2 = 0U; - - switch(spi_i2s_int){ - case SPI_I2S_INT_TBE : - temp1 = reg1 & SPI_STAT_TBE; - temp2 = reg2 & SPI_CTL1_TBEIE; - break; - case SPI_I2S_INT_RBNE : - temp1 = reg1 & SPI_STAT_RBNE; - temp2 = reg2 & SPI_CTL1_RBNEIE; - break; - case SPI_I2S_INT_RXORERR : - temp1 = reg1 & SPI_STAT_RXORERR; - temp2 = reg2 & SPI_CTL1_ERRIE; - break; - case SPI_INT_CONFERR : - temp1 = reg1 & SPI_STAT_CONFERR; - temp2 = reg2 & SPI_CTL1_ERRIE; - break; - case SPI_INT_CRCERR : - temp1 = reg1 & SPI_STAT_CRCERR; - temp2 = reg2 & SPI_CTL1_ERRIE; - break; - case I2S_INT_TXURERR : - temp1 = reg1 & SPI_STAT_TXURERR; - temp2 = reg2 & SPI_CTL1_ERRIE; - break; - case SPI_I2S_INT_FERR : - temp1 = reg1 & SPI_STAT_FERR; - temp2 = reg2 & SPI_CTL1_ERRIE; - break; - default : - break; - } - - if(temp1 && temp2){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief get flag status - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[in] spi_i2s_flag: - \arg SPI_FLAG_TBE: transmit buffer empty flag - \arg SPI_FLAG_RBNE: receive buffer not empty flag - \arg SPI_FLAG_TRANS: transmit on-going flag - \arg SPI_FLAG_RXORERR: receive Overrun flag - \arg SPI_FLAG_CONFERR: mode config error flag - \arg SPI_FLAG_CRCERR: CRC error flag - \arg SPI_FLAG_FERR: format error interrupt flag - \arg I2S_FLAG_TBE: transmit buffer empty flag - \arg I2S_FLAG_RBNE: receive buffer not empty flag - \arg I2S_FLAG_TRANS: transmit on-going flag - \arg I2S_FLAG_RXORERR: overrun flag - \arg I2S_FLAG_TXURERR: underrun error flag - \arg I2S_FLAG_CH: channel side flag - \arg I2S_FLAG_FERR: format error interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t spi_i2s_flag) -{ - if(SPI_STAT(spi_periph) & spi_i2s_flag){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear SPI CRC error flag status - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[out] none - \retval none -*/ -void spi_crc_error_clear(uint32_t spi_periph) -{ - SPI_STAT(spi_periph) &= (uint32_t)(~SPI_FLAG_CRCERR); -} - -/*! - \brief CRC function turn on - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[out] none - \retval none -*/ -void spi_crc_on(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; -} - -/*! - \brief CRC function turn off - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[out] none - \retval none -*/ -void spi_crc_off(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCEN); -} - -/*! - \brief CRC polynomial set + \brief set SPI CRC polynomial \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] crc_poly: CRC polynomial value \param[out] none @@ -628,7 +504,7 @@ void spi_crc_polynomial_set(uint32_t spi_periph,uint16_t crc_poly) } /*! - \brief get SPI CRC polynomial + \brief get SPI CRC polynomial \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[out] none \retval 16-bit CRC polynomial @@ -638,6 +514,28 @@ uint16_t spi_crc_polynomial_get(uint32_t spi_periph) return ((uint16_t)SPI_CRCPOLY(spi_periph)); } +/*! + \brief turn on CRC function + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[out] none + \retval none +*/ +void spi_crc_on(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; +} + +/*! + \brief turn off CRC function + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[out] none + \retval none +*/ +void spi_crc_off(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCEN); +} + /*! \brief SPI next data is CRC value \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) @@ -652,7 +550,8 @@ void spi_crc_next(uint32_t spi_periph) /*! \brief get SPI CRC send value or receive value \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[in] spi_crc: + \param[in] spi_crc: SPI crc value + only one parameter can be selected which is shown as below: \arg SPI_CRC_TX: get transmit crc value \arg SPI_CRC_RX: get receive crc value \param[out] none @@ -692,18 +591,18 @@ void spi_ti_mode_disable(uint32_t spi_periph) /*! \brief configure i2s full duplex mode \param[in] i2s_add_periph: I2Sx_ADD(x=1,2) - \param[in] i2s_mode: + \param[in] i2s_mode: \arg I2S_MODE_SLAVETX : I2S slave transmit mode \arg I2S_MODE_SLAVERX : I2S slave receive mode \arg I2S_MODE_MASTERTX : I2S master transmit mode \arg I2S_MODE_MASTERRX : I2S master receive mode - \param[in] i2s_standard: + \param[in] i2s_standard: \arg I2S_STD_PHILLIPS : I2S phillips standard \arg I2S_STD_MSB : I2S MSB standard \arg I2S_STD_LSB : I2S LSB standard \arg I2S_STD_PCMSHORT : I2S PCM short standard \arg I2S_STD_PCMLONG : I2S PCM long standard - \param[in] i2s_ckpl: + \param[in] i2s_ckpl: \arg I2S_CKPL_LOW : I2S clock polarity low level \arg I2S_CKPL_HIGH : I2S clock polarity high level \param[in] i2s_frameformat: @@ -720,7 +619,7 @@ void i2s_full_duplex_mode_config(uint32_t i2s_add_periph, uint32_t i2s_mode, uin uint32_t reg = 0U, tmp = 0U; reg = I2S_ADD_I2SCTL(i2s_add_periph); - reg &= I2S_FULL_DUPLEX_MASK; + reg &= I2S_FULL_DUPLEX_MASK; /* get the mode of the extra I2S module I2Sx_ADD */ if((I2S_MODE_MASTERTX == i2s_mode) || (I2S_MODE_SLAVETX == i2s_mode)){ @@ -730,7 +629,7 @@ void i2s_full_duplex_mode_config(uint32_t i2s_add_periph, uint32_t i2s_mode, uin } /* enable I2S mode */ - reg |= (uint32_t)SPI_I2SCTL_I2SSEL; + reg |= (uint32_t)SPI_I2SCTL_I2SSEL; /* select I2S mode */ reg |= (uint32_t)tmp; /* select I2S standard */ @@ -745,7 +644,7 @@ void i2s_full_duplex_mode_config(uint32_t i2s_add_periph, uint32_t i2s_mode, uin } /*! - \brief quad wire SPI enable + \brief enable quad wire SPI \param[in] spi_periph: SPIx(only x=5) \param[out] none \retval none @@ -756,7 +655,7 @@ void qspi_enable(uint32_t spi_periph) } /*! - \brief quad wire SPI disable + \brief disable quad wire SPI \param[in] spi_periph: SPIx(only x=5) \param[out] none \retval none @@ -767,7 +666,7 @@ void qspi_disable(uint32_t spi_periph) } /*! - \brief quad wire SPI write enable + \brief enable quad wire SPI write \param[in] spi_periph: SPIx(only x=5) \param[out] none \retval none @@ -778,7 +677,7 @@ void qspi_write_enable(uint32_t spi_periph) } /*! - \brief quad wire SPI read enable + \brief enable quad wire SPI read \param[in] spi_periph: SPIx(only x=5) \param[out] none \retval none @@ -789,7 +688,7 @@ void qspi_read_enable(uint32_t spi_periph) } /*! - \brief SPI_IO2 and SPI_IO3 pin output enable + \brief enable SPI_IO2 and SPI_IO3 pin output \param[in] spi_periph: SPIx(only x=5) \param[out] none \retval none @@ -800,7 +699,7 @@ void qspi_io23_output_enable(uint32_t spi_periph) } /*! - \brief SPI_IO2 and SPI_IO3 pin output disable + \brief disable SPI_IO2 and SPI_IO3 pin output \param[in] spi_periph: SPIx(only x=5) \param[out] none \retval none @@ -809,3 +708,175 @@ void qspi_io23_output_enable(uint32_t spi_periph) { SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_IO23_DRV); } + +/*! + \brief enable SPI and I2S interrupt + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[in] spi_i2s_int: SPI/I2S interrupt + only one parameter can be selected which is shown as below: + \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt + \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt + \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, + transmission underrun error and format error interrupt + \param[out] none + \retval none +*/ +void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t spi_i2s_int) +{ + switch(spi_i2s_int){ + /* SPI/I2S transmit buffer empty interrupt */ + case SPI_I2S_INT_TBE: + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE; + break; + /* SPI/I2S receive buffer not empty interrupt */ + case SPI_I2S_INT_RBNE: + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_RBNEIE; + break; + /* SPI/I2S error */ + case SPI_I2S_INT_ERR: + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE; + break; + default: + break; + } +} + +/*! + \brief disable SPI and I2S interrupt + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[in] spi_i2s_int: SPI/I2S interrupt + only one parameter can be selected which is shown as below: + \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt + \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt + \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, + transmission underrun error and format error interrupt + \param[out] none + \retval none +*/ +void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t spi_i2s_int) +{ + switch(spi_i2s_int){ + /* SPI/I2S transmit buffer empty interrupt */ + case SPI_I2S_INT_TBE : + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE); + break; + /* SPI/I2S receive buffer not empty interrupt */ + case SPI_I2S_INT_RBNE : + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RBNEIE); + break; + /* SPI/I2S error */ + case SPI_I2S_INT_ERR : + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE); + break; + default : + break; + } +} + +/*! + \brief get SPI and I2S interrupt flag status + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[in] spi_i2s_int: SPI/I2S interrupt flag status + \arg SPI_I2S_INT_FLAG_TBE: transmit buffer empty interrupt flag + \arg SPI_I2S_INT_FLAG_RBNE: receive buffer not empty interrupt flag + \arg SPI_I2S_INT_FLAG_RXORERR: overrun interrupt flag + \arg SPI_INT_FLAG_CONFERR: config error interrupt flag + \arg SPI_INT_FLAG_CRCERR: CRC error interrupt flag + \arg I2S_INT_FLAG_TXURERR: underrun error interrupt flag + \arg SPI_I2S_INT_FLAG_FERR: format error interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t spi_i2s_int) +{ + uint32_t reg1 = SPI_STAT(spi_periph); + uint32_t reg2 = SPI_CTL1(spi_periph); + + switch(spi_i2s_int){ + /* SPI/I2S transmit buffer empty interrupt */ + case SPI_I2S_INT_FLAG_TBE : + reg1 = reg1 & SPI_STAT_TBE; + reg2 = reg2 & SPI_CTL1_TBEIE; + break; + /* SPI/I2S receive buffer not empty interrupt */ + case SPI_I2S_INT_FLAG_RBNE : + reg1 = reg1 & SPI_STAT_RBNE; + reg2 = reg2 & SPI_CTL1_RBNEIE; + break; + /* SPI/I2S overrun interrupt */ + case SPI_I2S_INT_FLAG_RXORERR : + reg1 = reg1 & SPI_STAT_RXORERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* SPI config error interrupt */ + case SPI_INT_FLAG_CONFERR : + reg1 = reg1 & SPI_STAT_CONFERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* SPI CRC error interrupt */ + case SPI_INT_FLAG_CRCERR : + reg1 = reg1 & SPI_STAT_CRCERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* I2S underrun error interrupt */ + case I2S_INT_FLAG_TXURERR : + reg1 = reg1 & SPI_STAT_TXURERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* SPI/I2S format error interrupt */ + case SPI_I2S_INT_FLAG_FERR : + reg1 = reg1 & SPI_STAT_FERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + default : + break; + } + /*get SPI/I2S interrupt flag status */ + if(reg1 && reg2){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief get SPI and I2S flag status + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[in] spi_i2s_flag: SPI/I2S flag status + \arg SPI_FLAG_TBE: transmit buffer empty flag + \arg SPI_FLAG_RBNE: receive buffer not empty flag + \arg SPI_FLAG_TRANS: transmit on-going flag + \arg SPI_FLAG_RXORERR: receive overrun error flag + \arg SPI_FLAG_CONFERR: mode config error flag + \arg SPI_FLAG_CRCERR: CRC error flag + \arg SPI_FLAG_FERR: format error flag + \arg I2S_FLAG_TBE: transmit buffer empty flag + \arg I2S_FLAG_RBNE: receive buffer not empty flag + \arg I2S_FLAG_TRANS: transmit on-going flag + \arg I2S_FLAG_RXORERR: overrun error flag + \arg I2S_FLAG_TXURERR: underrun error flag + \arg I2S_FLAG_CH: channel side flag + \arg I2S_FLAG_FERR: format error flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t spi_i2s_flag) +{ + if(SPI_STAT(spi_periph) & spi_i2s_flag){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear SPI CRC error flag status + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[out] none + \retval none +*/ +void spi_crc_error_clear(uint32_t spi_periph) +{ + SPI_STAT(spi_periph) &= (uint32_t)(~SPI_FLAG_CRCERR); +} + diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_syscfg.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_syscfg.c index d834462aba..6fa0a776d0 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_syscfg.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_syscfg.c @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_syscfg.c - \brief SYSCFG driver + \file gd32f4xx_syscfg.c + \brief SYSCFG driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_syscfg.h" @@ -24,8 +49,9 @@ void syscfg_deinit(void) } /*! - \brief configure the boot mode + \brief configure the boot mode \param[in] syscfg_bootmode: selects the memory remapping + only one parameter can be selected which is shown as below: \arg SYSCFG_BOOTMODE_FLASH: main flash memory (0x08000000~0x083BFFFF) is mapped at address 0x00000000 \arg SYSCFG_BOOTMODE_BOOTLOADER: boot loader (0x1FFF0000 - 0x1FFF77FF) is mapped at address 0x00000000 \arg SYSCFG_BOOTMODE_EXMC_SRAM: SRAM/NOR 0 and 1 of EXMC (0x60000000~0x67FFFFFF) is mapped at address 0x00000000 @@ -44,6 +70,7 @@ void syscfg_bootmode_config(uint8_t syscfg_bootmode) /*! \brief FMC memory mapping swap \param[in] syscfg_fmc_swap: selects the interal flash bank swapping + only one parameter can be selected which is shown as below: \arg SYSCFG_FMC_SWP_BANK0: bank 0 is mapped at address 0x08000000 and bank 1 is mapped at address 0x08100000 \arg SYSCFG_FMC_SWP_BANK1: bank 1 is mapped at address 0x08000000 and bank 0 is mapped at address 0x08100000 \param[out] none @@ -61,6 +88,7 @@ void syscfg_fmc_swap_config(uint32_t syscfg_fmc_swap) /*! \brief EXMC memory mapping swap \param[in] syscfg_exmc_swap: selects the memories in EXMC swapping + only one parameter can be selected which is shown as below: \arg SYSCFG_EXMC_SWP_ENABLE: SDRAM bank 0 and bank 1 are swapped with NAND bank 1 and PC card \arg SYSCFG_EXMC_SWP_DISABLE: no memory mapping swap \param[out] none @@ -79,8 +107,10 @@ void syscfg_exmc_swap_config(uint32_t syscfg_exmc_swap) /*! \brief configure the GPIO pin as EXTI Line \param[in] exti_port: specify the GPIO port used in EXTI + only one parameter can be selected which is shown as below: \arg EXTI_SOURCE_GPIOx(x = A,B,C,D,E,F,G,H,I): EXTI GPIO port \param[in] exti_pin: specify the EXTI line + only one parameter can be selected which is shown as below: \arg EXTI_SOURCE_PINx(x = 0..15): EXTI GPIO pin \param[out] none \retval none @@ -123,15 +153,16 @@ void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin) /*! \brief configure the PHY interface for the ethernet MAC \param[in] syscfg_enet_phy_interface: specifies the media interface mode. + only one parameter can be selected which is shown as below: \arg SYSCFG_ENET_PHY_MII: MII mode is selected - \arg SYSCFG_ENET_PHY_RMII: RMII mode is selected + \arg SYSCFG_ENET_PHY_RMII: RMII mode is selected \param[out] none \retval none */ void syscfg_enet_phy_interface_config(uint32_t syscfg_enet_phy_interface) -{ +{ uint32_t reg; - + reg = SYSCFG_CFG1; /* reset the ENET_PHY_SEL bit and set according to syscfg_enet_phy_interface */ reg &= ~SYSCFG_CFG1_ENET_PHY_SEL; @@ -141,12 +172,13 @@ void syscfg_enet_phy_interface_config(uint32_t syscfg_enet_phy_interface) /*! \brief configure the I/O compensation cell \param[in] syscfg_compensation: specifies the I/O compensation cell mode + only one parameter can be selected which is shown as below: \arg SYSCFG_COMPENSATION_ENABLE: I/O compensation cell is enabled \arg SYSCFG_COMPENSATION_DISABLE: I/O compensation cell is disabled \param[out] none \retval none */ -void syscfg_compensation_config(uint32_t syscfg_compensation) +void syscfg_compensation_config(uint32_t syscfg_compensation) { uint32_t reg; diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_timer.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_timer.c index 04c8fab0d3..e312680222 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_timer.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_timer.c @@ -1,14 +1,40 @@ /*! - \file gd32f4xx_timer.c - \brief TIMER driver + \file gd32f4xx_timer.c + \brief TIMER driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ + #include "gd32f4xx_timer.h" /*! @@ -95,10 +121,27 @@ void timer_deinit(uint32_t timer_periph) } } +/*! + \brief initialize TIMER init parameter struct with a default value + \param[in] initpara: init parameter struct + \param[out] none + \retval none +*/ +void timer_struct_para_init(timer_parameter_struct* initpara) +{ + /* initialize the init parameter struct member with the default value */ + initpara->prescaler = 0U; + initpara->alignedmode = TIMER_COUNTER_EDGE; + initpara->counterdirection = TIMER_COUNTER_UP; + initpara->period = 65535U; + initpara->clockdivision = TIMER_CKDIV_DIV1; + initpara->repetitioncounter = 0U; +} + /*! \brief initialize TIMER counter \param[in] timer_periph: TIMERx(x=0..13) - \param[in] timer_initpara: init parameter struct + \param[in] initpara: init parameter struct prescaler: prescaler value of the counter clock,0~65535 alignedmode: TIMER_COUNTER_EDGE,TIMER_COUNTER_CENTER_DOWN,TIMER_COUNTER_CENTER_UP,TIMER_COUNTER_CENTER_BOTH counterdirection: TIMER_COUNTER_UP,TIMER_COUNTER_DOWN @@ -108,31 +151,31 @@ void timer_deinit(uint32_t timer_periph) \param[out] none \retval none */ -void timer_init(uint32_t timer_periph, timer_parameter_struct* timer_initpara) +void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara) { /* configure the counter prescaler value */ - TIMER_PSC(timer_periph) = (uint16_t)timer_initpara->prescaler; + TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler; /* configure the counter direction and aligned mode */ if((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph) || (TIMER3 == timer_periph) || (TIMER4 == timer_periph) || (TIMER7 == timer_periph)){ TIMER_CTL0(timer_periph) &= ~(uint32_t)(TIMER_CTL0_DIR|TIMER_CTL0_CAM); - TIMER_CTL0(timer_periph) |= (uint32_t)timer_initpara->alignedmode; - TIMER_CTL0(timer_periph) |= (uint32_t)timer_initpara->counterdirection; + TIMER_CTL0(timer_periph) |= (uint32_t)initpara->alignedmode; + TIMER_CTL0(timer_periph) |= (uint32_t)initpara->counterdirection; } /* configure the autoreload value */ - TIMER_CAR(timer_periph) = (uint32_t)timer_initpara->period; + TIMER_CAR(timer_periph) = (uint32_t)initpara->period; if((TIMER5 != timer_periph) && (TIMER6 != timer_periph)){ /* reset the CKDIV bit */ TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CKDIV; - TIMER_CTL0(timer_periph) |= (uint32_t)timer_initpara->clockdivision; + TIMER_CTL0(timer_periph) |= (uint32_t)initpara->clockdivision; } if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ /* configure the repetition counter value */ - TIMER_CREP(timer_periph) = (uint32_t)timer_initpara->repetitioncounter; + TIMER_CREP(timer_periph) = (uint32_t)initpara->repetitioncounter; } /* generate an update event */ @@ -208,7 +251,8 @@ void timer_update_event_disable(uint32_t timer_periph) /*! \brief set TIMER counter alignment mode \param[in] timer_periph: TIMERx(x=0..4,7) - \param[in] timer_aligned: + \param[in] aligned: + only one parameter can be selected which is shown as below: \arg TIMER_COUNTER_EDGE: edge-aligned mode \arg TIMER_COUNTER_CENTER_DOWN: center-aligned and counting down assert mode \arg TIMER_COUNTER_CENTER_UP: center-aligned and counting up assert mode @@ -216,10 +260,10 @@ void timer_update_event_disable(uint32_t timer_periph) \param[out] none \retval none */ -void timer_counter_alignment(uint32_t timer_periph,uint16_t timer_aligned) +void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned) { TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CAM; - TIMER_CTL0(timer_periph) |= (uint32_t)timer_aligned; + TIMER_CTL0(timer_periph) |= (uint32_t)aligned; } /*! @@ -247,18 +291,19 @@ void timer_counter_down_direction(uint32_t timer_periph) /*! \brief configure TIMER prescaler \param[in] timer_periph: TIMERx(x=0..13) - \param[in] timer_prescaler: prescaler value - \param[in] timer_pscreload: prescaler reload mode + \param[in] prescaler: prescaler value,0~65535 + \param[in] pscreload: prescaler reload mode + only one parameter can be selected which is shown as below: \arg TIMER_PSC_RELOAD_NOW: the prescaler is loaded right now \arg TIMER_PSC_RELOAD_UPDATE: the prescaler is loaded at the next update event \param[out] none \retval none */ -void timer_prescaler_config(uint32_t timer_periph,uint16_t timer_prescaler,uint8_t timer_pscreload) +void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload) { - TIMER_PSC(timer_periph) = (uint32_t)timer_prescaler; - - if(TIMER_PSC_RELOAD_NOW == timer_pscreload){ + TIMER_PSC(timer_periph) = (uint32_t)prescaler; + + if(TIMER_PSC_RELOAD_NOW == pscreload){ TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; } } @@ -266,37 +311,37 @@ void timer_prescaler_config(uint32_t timer_periph,uint16_t timer_prescaler,uint8 /*! \brief configure TIMER repetition register value \param[in] timer_periph: TIMERx(x=0,7) - \param[in] timer_repetition: the counter repetition value,0~255 + \param[in] repetition: the counter repetition value,0~255 \param[out] none \retval none */ -void timer_repetition_value_config(uint32_t timer_periph,uint16_t timer_repetition) +void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition) { - TIMER_CREP(timer_periph) = (uint32_t)timer_repetition; -} - + TIMER_CREP(timer_periph) = (uint32_t)repetition; +} + /*! \brief configure TIMER autoreload register value \param[in] timer_periph: TIMERx(x=0..13) - \param[in] timer_autoreload: the counter auto-reload value + \param[in] autoreload: the counter auto-reload value \param[out] none \retval none -*/ -void timer_autoreload_value_config(uint32_t timer_periph,uint32_t timer_autoreload) +*/ +void timer_autoreload_value_config(uint32_t timer_periph,uint32_t autoreload) { - TIMER_CAR(timer_periph) = (uint32_t)timer_autoreload; + TIMER_CAR(timer_periph) = (uint32_t)autoreload; } /*! \brief configure TIMER counter register value \param[in] timer_periph: TIMERx(x=0..13) - \param[in] timer_counter: the counter value + \param[in] counter: the counter value,0~65535 \param[out] none \retval none -*/ -void timer_counter_value_config(uint32_t timer_periph , uint32_t timer_counter) +*/ +void timer_counter_value_config(uint32_t timer_periph , uint32_t counter) { - TIMER_CNT(timer_periph) = (uint32_t)timer_counter; + TIMER_CNT(timer_periph) = (uint32_t)counter; } /*! @@ -304,7 +349,7 @@ void timer_counter_value_config(uint32_t timer_periph , uint32_t timer_counter) \param[in] timer_periph: TIMERx(x=0..13) \param[out] none \retval counter value -*/ +*/ uint32_t timer_counter_read(uint32_t timer_periph) { uint32_t count_value = 0U; @@ -317,56 +362,61 @@ uint32_t timer_counter_read(uint32_t timer_periph) \param[in] timer_periph: TIMERx(x=0..13) \param[out] none \retval prescaler register value -*/ +*/ uint16_t timer_prescaler_read(uint32_t timer_periph) { uint16_t prescaler_value = 0U; - prescaler_value = (uint16_t)(TIMER_CAR(timer_periph)); + prescaler_value = (uint16_t)(TIMER_PSC(timer_periph)); return (prescaler_value); } /*! \brief configure TIMER single pulse mode \param[in] timer_periph: TIMERx(x=0..8,11) - \param[in] timer_spmode: + \param[in] spmode: + only one parameter can be selected which is shown as below: \arg TIMER_SP_MODE_SINGLE: single pulse mode \arg TIMER_SP_MODE_REPETITIVE: repetitive pulse mode \param[out] none \retval none */ -void timer_single_pulse_mode_config(uint32_t timer_periph,uint8_t timer_spmode) +void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode) { - if(TIMER_SP_MODE_SINGLE == timer_spmode){ + if(TIMER_SP_MODE_SINGLE == spmode){ TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM; - }else if(TIMER_SP_MODE_REPETITIVE == timer_spmode){ + }else if(TIMER_SP_MODE_REPETITIVE == spmode){ TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM); }else{ + /* illegal parameters */ } } /*! - \brief configure TIMER update source + \brief configure TIMER update source \param[in] timer_periph: TIMERx(x=0..13) - \param[in] timer_update: + \param[in] update: + only one parameter can be selected which is shown as below: \arg TIMER_UPDATE_SRC_GLOBAL: update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger \arg TIMER_UPDATE_SRC_REGULAR: update generate only by counter overflow/underflow \param[out] none \retval none */ -void timer_update_source_config(uint32_t timer_periph,uint8_t timer_update) +void timer_update_source_config(uint32_t timer_periph, uint32_t update) { - if(TIMER_UPDATE_SRC_REGULAR == timer_update){ + if(TIMER_UPDATE_SRC_REGULAR == update){ TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS; - }else if(timer_update == TIMER_UPDATE_SRC_GLOBAL){ + }else if(TIMER_UPDATE_SRC_GLOBAL == update){ TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS; }else{ + /* illegal parameters */ } } /*! \brief enable the TIMER interrupt - \param[in] timer_periph: please refer to the following parameters - \param[in] timer_interrupt: timer interrupt enable source + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: timer interrupt enable source + only one parameter can be selected which is shown as below: \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13) \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4,7..13) \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4,7,8,11) @@ -378,15 +428,16 @@ void timer_update_source_config(uint32_t timer_periph,uint8_t timer_update) \param[out] none \retval none */ -void timer_interrupt_enable(uint32_t timer_periph,uint32_t timer_interrupt) +void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt) { - TIMER_DMAINTEN(timer_periph) |= (uint32_t) timer_interrupt; + TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt; } /*! \brief disable the TIMER interrupt \param[in] timer_periph: please refer to the following parameters - \param[in] timer_interrupt: timer interrupt source enable + \param[in] interrupt: timer interrupt source enable + only one parameter can be selected which is shown as below: \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13) \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4,7..13) \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4,7,8,11) @@ -398,31 +449,32 @@ void timer_interrupt_enable(uint32_t timer_periph,uint32_t timer_interrupt) \param[out] none \retval none */ -void timer_interrupt_disable(uint32_t timer_periph,uint32_t timer_interrupt) +void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt) { - TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)timer_interrupt); + TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt); } /*! \brief get timer interrupt flag \param[in] timer_periph: please refer to the following parameters - \param[in] timer_interrupt: the timer interrupt bits - \arg TIMER_INT_UP: update interrupt flag,TIMERx(x=0..13) - \arg TIMER_INT_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13) - \arg TIMER_INT_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7) - \arg TIMER_INT_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7) - \arg TIMER_INT_CMT: channel commutation interrupt flag,TIMERx(x=0,7) - \arg TIMER_INT_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11) - \arg TIMER_INT_BRK: break interrupt flag,TIMERx(x=0,7) + \param[in] interrupt: the timer interrupt bits + only one parameter can be selected which is shown as below: + \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13) + \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13) + \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7) + \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7) + \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7) + \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11) + \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7) \param[out] none \retval FlagStatus: SET or RESET */ -FlagStatus timer_interrupt_flag_get(uint32_t timer_periph,uint32_t timer_interrupt) +FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt) { uint32_t val; - val = (TIMER_DMAINTEN(timer_periph) & timer_interrupt); - if((RESET != (TIMER_INTF(timer_periph) & timer_interrupt) ) && (RESET != val)){ + val = (TIMER_DMAINTEN(timer_periph) & interrupt); + if((RESET != (TIMER_INTF(timer_periph) & interrupt) ) && (RESET != val)){ return SET; }else{ return RESET; @@ -432,34 +484,36 @@ FlagStatus timer_interrupt_flag_get(uint32_t timer_periph,uint32_t timer_interru /*! \brief clear TIMER interrupt flag \param[in] timer_periph: please refer to the following parameters - \param[in] timer_interrupt: the timer interrupt bits - \arg TIMER_INT_UP: update interrupt flag,TIMERx(x=0..13) - \arg TIMER_INT_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13) - \arg TIMER_INT_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7) - \arg TIMER_INT_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7) - \arg TIMER_INT_CMT: channel commutation interrupt flag,TIMERx(x=0,7) - \arg TIMER_INT_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11) - \arg TIMER_INT_BRK: break interrupt flag,TIMERx(x=0,7) + \param[in] interrupt: the timer interrupt bits + only one parameter can be selected which is shown as below: + \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13) + \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13) + \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7) + \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7) + \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7) + \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11) + \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7) \param[out] none \retval none */ -void timer_interrupt_flag_clear(uint32_t timer_periph,uint32_t timer_interrupt) +void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt) { - TIMER_INTF(timer_periph) &= (~(uint32_t)timer_interrupt); + TIMER_INTF(timer_periph) = (~(uint32_t)interrupt); } /*! \brief get TIMER flags \param[in] timer_periph: please refer to the following parameters - \param[in] timer_flag: the timer interrupt flags + \param[in] flag: the timer interrupt flags + only one parameter can be selected which is shown as below: \arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13) \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13) \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11) \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7) \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7) - \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) + \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7) + \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7) \arg TIMER_FLAG_CH0OF: channel 0 overcapture flag,TIMERx(x=0..4,7..11) \arg TIMER_FLAG_CH1OF: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11) @@ -468,9 +522,9 @@ void timer_interrupt_flag_clear(uint32_t timer_periph,uint32_t timer_interrupt) \param[out] none \retval FlagStatus: SET or RESET */ -FlagStatus timer_flag_get(uint32_t timer_periph , uint32_t timer_flag) +FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag) { - if(RESET != (TIMER_INTF(timer_periph) & timer_flag)){ + if(RESET != (TIMER_INTF(timer_periph) & flag)){ return SET; }else{ return RESET; @@ -480,14 +534,15 @@ FlagStatus timer_flag_get(uint32_t timer_periph , uint32_t timer_flag) /*! \brief clear TIMER flags \param[in] timer_periph: please refer to the following parameters - \param[in] timer_flag: the timer interrupt flags + \param[in] flag: the timer interrupt flags + only one parameter can be selected which is shown as below: \arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13) \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13) \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11) \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7) \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7) - \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) + \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7) + \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7) \arg TIMER_FLAG_CH0OF: channel 0 overcapture flag,TIMERx(x=0..4,7..11) \arg TIMER_FLAG_CH1OF: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11) @@ -496,72 +551,77 @@ FlagStatus timer_flag_get(uint32_t timer_periph , uint32_t timer_flag) \param[out] none \retval none */ -void timer_flag_clear(uint32_t timer_periph , uint32_t timer_flag) +void timer_flag_clear(uint32_t timer_periph, uint32_t flag) { - TIMER_INTF(timer_periph) &= (~(uint32_t)timer_flag); + TIMER_INTF(timer_periph) = (~(uint32_t)flag); } /*! \brief enable the TIMER DMA - \param[in] timer_periph: TIMERx(x=0,1,2,5,14,15,16) - \param[in] timer_dma: timer DMA source enable - \arg TIMER_DMA_UPD: update DMA enable,TIMERx(x=0..7) - \arg TIMER_DMA_CH0D: channel 0 DMA enable,TIMERx(x=0..4,7) - \arg TIMER_DMA_CH1D: channel 1 DMA enable,TIMERx(x=0..4,7) - \arg TIMER_DMA_CH2D: channel 2 DMA enable,TIMERx(x=0..4,7) - \arg TIMER_DMA_CH3D: channel 3 DMA enable,TIMERx(x=0..4,7) - \arg TIMER_DMA_CMTD: commutation DMA request enable,TIMERx(x=0,7) - \arg TIMER_DMA_TRGD: trigger DMA enable,TIMERx(x=0..4,7) + \param[in] timer_periph: please refer to the following parameters + \param[in] dma: specify which DMA to enable + one or more parameters can be selected which is shown as below: + \arg TIMER_DMA_UPD: update DMA,TIMERx(x=0..7) + \arg TIMER_DMA_CH0D: channel 0 DMA request,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH1D: channel 1 DMA request,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH2D: channel 2 DMA request,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH3D: channel 3 DMA request,TIMERx(x=0..4,7) + \arg TIMER_DMA_CMTD: commutation DMA request,TIMERx(x=0,7) + \arg TIMER_DMA_TRGD: trigger DMA request,TIMERx(x=0..4,7) \param[out] none \retval none */ -void timer_dma_enable(uint32_t timer_periph,uint16_t timer_dma) +void timer_dma_enable(uint32_t timer_periph, uint16_t dma) { - TIMER_DMAINTEN(timer_periph) |= (uint32_t) timer_dma; + TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma; } /*! \brief disable the TIMER DMA \param[in] timer_periph: please refer to the following parameters - \param[in] timer_dma: timer DMA source enable - \arg TIMER_DMA_UPD: update DMA enable,TIMERx(x=0..7) - \arg TIMER_DMA_CH0D: channel 0 DMA enable,TIMERx(x=0..4,7) - \arg TIMER_DMA_CH1D: channel 1 DMA enable,TIMERx(x=0..4,7) - \arg TIMER_DMA_CH2D: channel 2 DMA enable,TIMERx(x=0..4,7) - \arg TIMER_DMA_CH3D: channel 3 DMA enable,TIMERx(x=0..4,7) - \arg TIMER_DMA_CMTD: commutation DMA request enable,TIMERx(x=0,7) - \arg TIMER_DMA_TRGD: trigger DMA enable,TIMERx(x=0..4,7) + \param[in] dma: specify which DMA to disable + one or more parameters can be selected which are shown as below: + \arg TIMER_DMA_UPD: update DMA,TIMERx(x=0..7) + \arg TIMER_DMA_CH0D: channel 0 DMA request,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH1D: channel 1 DMA request,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH2D: channel 2 DMA request,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH3D: channel 3 DMA request,TIMERx(x=0..4,7) + \arg TIMER_DMA_CMTD: commutation DMA request ,TIMERx(x=0,7) + \arg TIMER_DMA_TRGD: trigger DMA request,TIMERx(x=0..4,7) \param[out] none \retval none */ -void timer_dma_disable(uint32_t timer_periph,uint16_t timer_dma) +void timer_dma_disable(uint32_t timer_periph, uint16_t dma) { - TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(timer_dma)); + TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma)); } /*! \brief channel DMA request source selection \param[in] timer_periph: TIMERx(x=0..4,7) \param[in] dma_request: channel DMA request source selection + only one parameter can be selected which is shown as below: \arg TIMER_DMAREQUEST_CHANNELEVENT: DMA request of channel y is sent when channel y event occurs - \arg TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel y is sent when update event occurs + \arg TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel y is sent when update event occurs \param[out] none \retval none */ -void timer_channel_dma_request_source_select(uint32_t timer_periph,uint8_t dma_request) +void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request) { if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request){ TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS; }else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request){ TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS; }else{ + /* illegal parameters */ } } /*! \brief configure the TIMER DMA transfer \param[in] timer_periph: please refer to the following parameters - \param[in] dma_baseaddr: + \param[in] dma_baseaddr: + only one parameter can be selected which is shown as below: \arg TIMER_DMACFG_DMATA_CTL0: DMA transfer address is TIMER_CTL0,TIMERx(x=0..4,7) \arg TIMER_DMACFG_DMATA_CTL1: DMA transfer address is TIMER_CTL1,TIMERx(x=0..4,7) \arg TIMER_DMACFG_DMATA_SMCFG: DMA transfer address is TIMER_SMCFG,TIMERx(x=0..4,7) @@ -579,44 +639,64 @@ void timer_channel_dma_request_source_select(uint32_t timer_periph,uint8_t dma_r \arg TIMER_DMACFG_DMATA_CH1CV: DMA transfer address is TIMER_CH1CV,TIMERx(x=0..4,7) \arg TIMER_DMACFG_DMATA_CH2CV: DMA transfer address is TIMER_CH2CV,TIMERx(x=0..4,7) \arg TIMER_DMACFG_DMATA_CH3CV: DMA transfer address is TIMER_CH3CV,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CCHP: DMA transfer address is TIMER_CCHP,TIMERx(x=0,7) + \arg TIMER_DMACFG_DMATA_CCHP: DMA transfer address is TIMER_CCHP,TIMERx(x=0..4,7) \arg TIMER_DMACFG_DMATA_DMACFG: DMA transfer address is TIMER_DMACFG,TIMERx(x=0..4,7) \arg TIMER_DMACFG_DMATA_DMATB: DMA transfer address is TIMER_DMATB,TIMERx(x=0..4,7) \param[in] dma_lenth: + only one parameter can be selected which is shown as below: \arg TIMER_DMACFG_DMATC_xTRANSFER(x=1..18): DMA transfer x time \param[out] none \retval none */ -void timer_dma_transfer_config(uint32_t timer_periph,uint32_t dma_baseaddr,uint32_t dma_lenth) +void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth) { TIMER_DMACFG(timer_periph) &= (~(uint32_t)(TIMER_DMACFG_DMATA | TIMER_DMACFG_DMATC)); TIMER_DMACFG(timer_periph) |= (uint32_t)(dma_baseaddr | dma_lenth); } /*! - \brief software generate events + \brief software generate events \param[in] timer_periph: please refer to the following parameters - \param[in] timer_event: the timer software event generation sources + \param[in] event: the timer software event generation sources + one or more parameters can be selected which are shown as below: \arg TIMER_EVENT_SRC_UPG: update event,TIMERx(x=0..13) - \arg TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation,TIMERx(x=0..4,7..13) + \arg TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation,TIMERx(x=0..4,7..13) \arg TIMER_EVENT_SRC_CH1G: channel 1 capture or compare event generation,TIMERx(x=0..4,7,8,11) - \arg TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation,TIMERx(x=0..4,7) - \arg TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation,TIMERx(x=0..4,7) - \arg TIMER_EVENT_SRC_CMTG: channel commutation event generation,TIMERx(x=0,7) + \arg TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation,TIMERx(x=0..4,7) + \arg TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation,TIMERx(x=0..4,7) + \arg TIMER_EVENT_SRC_CMTG: channel commutation event generation,TIMERx(x=0,7) \arg TIMER_EVENT_SRC_TRGG: trigger event generation,TIMERx(x=0..4,7,8,11) \arg TIMER_EVENT_SRC_BRKG: break event generation,TIMERx(x=0,7) \param[out] none \retval none */ -void timer_event_software_generate(uint32_t timer_periph,uint16_t timer_event) +void timer_event_software_generate(uint32_t timer_periph, uint16_t event) { - TIMER_SWEVG(timer_periph) |= (uint32_t)timer_event; + TIMER_SWEVG(timer_periph) |= (uint32_t)event; } /*! - \brief configure TIMER break function + \brief initialize TIMER break parameter struct with a default value + \param[in] breakpara: TIMER break parameter struct + \param[out] none + \retval none +*/ +void timer_break_struct_para_init(timer_break_parameter_struct* breakpara) +{ + /* initialize the break parameter struct member with the default value */ + breakpara->runoffstate = TIMER_ROS_STATE_DISABLE; + breakpara->ideloffstate = TIMER_IOS_STATE_DISABLE; + breakpara->deadtime = 0U; + breakpara->breakpolarity = TIMER_BREAK_POLARITY_LOW; + breakpara->outputautostate = TIMER_OUTAUTO_DISABLE; + breakpara->protectmode = TIMER_CCHP_PROT_OFF; + breakpara->breakstate = TIMER_BREAK_DISABLE; +} + +/*! + \brief configure TIMER break function \param[in] timer_periph: TIMERx(x=0,7) - \param[in] timer_bkdtpara: TIMER break parameter struct + \param[in] breakpara: TIMER break parameter struct runoffstate: TIMER_ROS_STATE_ENABLE,TIMER_ROS_STATE_DISABLE ideloffstate: TIMER_IOS_STATE_ENABLE,TIMER_IOS_STATE_DISABLE deadtime: 0~255 @@ -627,15 +707,15 @@ void timer_event_software_generate(uint32_t timer_periph,uint16_t timer_event) \param[out] none \retval none */ -void timer_break_config(uint32_t timer_periph,timer_break_parameter_struct* timer_bkdtpara) +void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara) { - TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(timer_bkdtpara->runoffstate))| - ((uint32_t)(timer_bkdtpara->ideloffstate))| - ((uint32_t)(timer_bkdtpara->deadtime))| - ((uint32_t)(timer_bkdtpara->breakpolarity))| - ((uint32_t)(timer_bkdtpara->outputautostate)) | - ((uint32_t)(timer_bkdtpara->protectmode))| - ((uint32_t)(timer_bkdtpara->breakstate))) ; + TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate))| + ((uint32_t)(breakpara->ideloffstate))| + ((uint32_t)(breakpara->deadtime))| + ((uint32_t)(breakpara->breakpolarity))| + ((uint32_t)(breakpara->outputautostate)) | + ((uint32_t)(breakpara->protectmode))| + ((uint32_t)(breakpara->breakstate))) ; } /*! @@ -689,7 +769,7 @@ void timer_automatic_output_disable(uint32_t timer_periph) \param[out] none \retval none */ -void timer_primary_output_config(uint32_t timer_periph,ControlStatus newvalue) +void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue) { if(ENABLE == newvalue){ TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN; @@ -699,13 +779,13 @@ void timer_primary_output_config(uint32_t timer_periph,ControlStatus newvalue) } /*! - \brief channel capture/compare control shadow register enable + \brief enable or disable channel capture/compare control shadow register \param[in] timer_periph: TIMERx(x=0,7) - \param[in] newvalue: ENABLE or DISABLE + \param[in] newvalue: ENABLE or DISABLE \param[out] none \retval none */ -void timer_channel_control_shadow_config(uint32_t timer_periph,ControlStatus newvalue) +void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue) { if(ENABLE == newvalue){ TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE; @@ -717,31 +797,51 @@ void timer_channel_control_shadow_config(uint32_t timer_periph,ControlStatus new /*! \brief configure TIMER channel control shadow register update control \param[in] timer_periph: TIMERx(x=0,7) - \param[in] timer_ccuctl: channel control shadow register update control + \param[in] ccuctl: channel control shadow register update control + only one parameter can be selected which is shown as below: \arg TIMER_UPDATECTL_CCU: the shadow registers update by when CMTG bit is set - \arg TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs + \arg TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs \param[out] none \retval none -*/ -void timer_channel_control_shadow_update_config(uint32_t timer_periph,uint8_t timer_ccuctl) +*/ +void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl) { - if(TIMER_UPDATECTL_CCU == timer_ccuctl){ + if(TIMER_UPDATECTL_CCU == ccuctl){ TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC); - }else if(TIMER_UPDATECTL_CCUTRI == timer_ccuctl){ + }else if(TIMER_UPDATECTL_CCUTRI == ccuctl){ TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC; }else{ + /* illegal parameters */ } } +/*! + \brief initialize TIMER channel output parameter struct with a default value + \param[in] ocpara: TIMER channel n output parameter struct + \param[out] none + \retval none +*/ +void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara) +{ + /* initialize the channel output parameter struct member with the default value */ + ocpara->outputstate = (uint16_t)TIMER_CCX_DISABLE; + ocpara->outputnstate = TIMER_CCXN_DISABLE; + ocpara->ocpolarity = TIMER_OC_POLARITY_HIGH; + ocpara->ocnpolarity = TIMER_OCN_POLARITY_HIGH; + ocpara->ocidlestate = TIMER_OC_IDLE_STATE_LOW; + ocpara->ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; +} + /*! \brief configure TIMER channel output function \param[in] timer_periph: please refer to the following parameters - \param[in] timer_channel: + \param[in] channel: + only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4,7..13)) \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4,7,8,11)) \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4,7)) \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4,7)) - \param[in] timer_ocpara: TIMER channeln output parameter struct + \param[in] ocpara: TIMER channeln output parameter struct outputstate: TIMER_CCX_ENABLE,TIMER_CCX_DISABLE outputnstate: TIMER_CCXN_ENABLE,TIMER_CCXN_DISABLE ocpolarity: TIMER_OC_POLARITY_HIGH,TIMER_OC_POLARITY_LOW @@ -751,120 +851,120 @@ void timer_channel_control_shadow_update_config(uint32_t timer_periph,uint8_t ti \param[out] none \retval none */ -void timer_channel_output_config(uint32_t timer_periph,uint16_t timer_channel,timer_oc_parameter_struct* timer_ocpara) +void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara) { - switch(timer_channel){ + switch(channel){ /* configure TIMER_CH_0 */ case TIMER_CH_0: /* reset the CH0EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH0MS; /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)timer_ocpara->outputstate; + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputstate; /* reset the CH0P bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); /* set the CH0P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)timer_ocpara->ocpolarity; + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocpolarity; if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ /* reset the CH0NEN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); /* set the CH0NEN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)timer_ocpara->outputnstate; + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputnstate; /* reset the CH0NP bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); /* set the CH0NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)timer_ocpara->ocnpolarity; + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocnpolarity; /* reset the ISO0 bit */ TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0); /* set the ISO0 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)timer_ocpara->ocidlestate; + TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate; /* reset the ISO0N bit */ TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N); /* set the ISO0N bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)timer_ocpara->ocnidlestate; + TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate; } - TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH0MS; break; /* configure TIMER_CH_1 */ case TIMER_CH_1: /* reset the CH1EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH1MS; /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)(timer_ocpara->outputstate<< 4U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputstate << 4U); /* reset the CH1P bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); /* set the CH1P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(timer_ocpara->ocpolarity)<< 4U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 4U); if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ /* reset the CH1NEN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); /* set the CH1NEN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(timer_ocpara->outputnstate)<< 4U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 4U); /* reset the CH1NP bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); /* set the CH1NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(timer_ocpara->ocnpolarity)<< 4U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 4U); /* reset the ISO1 bit */ TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1); /* set the ISO1 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(timer_ocpara->ocidlestate)<< 2U); + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 2U); /* reset the ISO1N bit */ TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1N); /* set the ISO1N bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(timer_ocpara->ocnidlestate)<< 2U); + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 2U); } - TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH1MS; break; /* configure TIMER_CH_2 */ case TIMER_CH_2: /* reset the CH2EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); + TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH2MS; /* set the CH2EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)(timer_ocpara->outputstate<< 8U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputstate << 8U); /* reset the CH2P bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); /* set the CH2P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(timer_ocpara->ocpolarity)<< 8U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 8U); if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ /* reset the CH2NEN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); /* set the CH2NEN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(timer_ocpara->outputnstate)<< 8U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 8U); /* reset the CH2NP bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); /* set the CH2NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(timer_ocpara->ocnpolarity)<< 8U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 8U); /* reset the ISO2 bit */ TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2); /* set the ISO2 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(timer_ocpara->ocidlestate)<< 4U); + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 4U); /* reset the ISO2N bit */ TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2N); /* set the ISO2N bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(timer_ocpara->ocnidlestate)<< 4U); + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 4U); } - TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH2MS; break; /* configure TIMER_CH_3 */ case TIMER_CH_3: /* reset the CH3EN bit */ TIMER_CHCTL2(timer_periph) &=(~(uint32_t)TIMER_CHCTL2_CH3EN); + TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH3MS; /* set the CH3EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)(timer_ocpara->outputstate<< 12U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputstate << 12U); /* reset the CH3P bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); /* set the CH3P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(timer_ocpara->ocpolarity)<< 12U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 12U); if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ /* reset the ISO3 bit */ TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO3); /* set the ISO3 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(timer_ocpara->ocidlestate)<< 6U); + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 6U); } - TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH3MS; break; default: break; @@ -874,12 +974,14 @@ void timer_channel_output_config(uint32_t timer_periph,uint16_t timer_channel,ti /*! \brief configure TIMER channel output compare mode \param[in] timer_periph: please refer to the following parameters - \param[in] timer_channel: + \param[in] channel: + only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] timer_ocmode: channel output compare mode + \param[in] ocmode: channel output compare mode + only one parameter can be selected which is shown as below: \arg TIMER_OC_MODE_TIMING: timing mode \arg TIMER_OC_MODE_ACTIVE: active mode \arg TIMER_OC_MODE_INACTIVE: inactive mode @@ -891,28 +993,28 @@ void timer_channel_output_config(uint32_t timer_periph,uint16_t timer_channel,ti \param[out] none \retval none */ -void timer_channel_output_mode_config(uint32_t timer_periph,uint16_t timer_channel,uint16_t timer_ocmode) +void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode) { - switch(timer_channel){ + switch(channel){ /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCTL); - TIMER_CHCTL0(timer_periph) |= (uint32_t)timer_ocmode; + TIMER_CHCTL0(timer_periph) |= (uint32_t)ocmode; break; /* configure TIMER_CH_1 */ case TIMER_CH_1: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCTL); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(timer_ocmode)<< 8U); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U); break; /* configure TIMER_CH_2 */ case TIMER_CH_2: TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCTL); - TIMER_CHCTL1(timer_periph) |= (uint32_t)timer_ocmode; + TIMER_CHCTL1(timer_periph) |= (uint32_t)ocmode; break; /* configure TIMER_CH_3 */ case TIMER_CH_3: TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(timer_ocmode)<< 8U); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U); break; default: break; @@ -922,29 +1024,34 @@ void timer_channel_output_mode_config(uint32_t timer_periph,uint16_t timer_chann /*! \brief configure TIMER channel output pulse value \param[in] timer_periph: please refer to the following parameters - \param[in] timer_channel: + \param[in] channel: + only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] timer_pluse: channel output pulse value + \param[in] pulse: channel output pulse value,0~65535 \param[out] none \retval none */ -void timer_channel_output_pulse_value_config(uint32_t timer_periph,uint16_t timer_channel,uint32_t timer_pluse) +void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse) { - switch(timer_channel){ + switch(channel){ + /* configure TIMER_CH_0 */ case TIMER_CH_0: - TIMER_CH0CV(timer_periph) = (uint32_t)timer_pluse; + TIMER_CH0CV(timer_periph) = (uint32_t)pulse; break; + /* configure TIMER_CH_1 */ case TIMER_CH_1: - TIMER_CH1CV(timer_periph) = (uint32_t)timer_pluse; + TIMER_CH1CV(timer_periph) = (uint32_t)pulse; break; + /* configure TIMER_CH_2 */ case TIMER_CH_2: - TIMER_CH2CV(timer_periph) = (uint32_t)timer_pluse; + TIMER_CH2CV(timer_periph) = (uint32_t)pulse; break; + /* configure TIMER_CH_3 */ case TIMER_CH_3: - TIMER_CH3CV(timer_periph) = (uint32_t)timer_pluse; + TIMER_CH3CV(timer_periph) = (uint32_t)pulse; break; default: break; @@ -954,39 +1061,41 @@ void timer_channel_output_pulse_value_config(uint32_t timer_periph,uint16_t time /*! \brief configure TIMER channel output shadow function \param[in] timer_periph: please refer to the following parameters - \param[in] timer_channel: + \param[in] channel: + only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] timer_ocshadow: channel output shadow state + \param[in] ocshadow: channel output shadow state + only one parameter can be selected which is shown as below: \arg TIMER_OC_SHADOW_ENABLE: channel output shadow state enable \arg TIMER_OC_SHADOW_DISABLE: channel output shadow state disable \param[out] none \retval none */ -void timer_channel_output_shadow_config(uint32_t timer_periph,uint16_t timer_channel,uint16_t timer_ocshadow) +void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow) { - switch(timer_channel){ + switch(channel){ /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMSEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)timer_ocshadow; + TIMER_CHCTL0(timer_periph) |= (uint32_t)ocshadow; break; /* configure TIMER_CH_1 */ case TIMER_CH_1: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMSEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(timer_ocshadow) << 8U); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); break; /* configure TIMER_CH_2 */ case TIMER_CH_2: TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMSEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)timer_ocshadow; + TIMER_CHCTL1(timer_periph) |= (uint32_t)ocshadow; break; /* configure TIMER_CH_3 */ case TIMER_CH_3: TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMSEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(timer_ocshadow) << 8U); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); break; default: break; @@ -996,39 +1105,41 @@ void timer_channel_output_shadow_config(uint32_t timer_periph,uint16_t timer_cha /*! \brief configure TIMER channel output fast function \param[in] timer_periph: please refer to the following parameters - \param[in] timer_channel: + \param[in] channel: + only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] timer_ocfast: channel output fast function + \param[in] ocfast: channel output fast function + only one parameter can be selected which is shown as below: \arg TIMER_OC_FAST_ENABLE: channel output fast function enable \arg TIMER_OC_FAST_DISABLE: channel output fast function disable \param[out] none \retval none */ -void timer_channel_output_fast_config(uint32_t timer_periph,uint16_t timer_channel,uint16_t timer_ocfast) +void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast) { - switch(timer_channel){ + switch(channel){ /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMFEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)timer_ocfast; + TIMER_CHCTL0(timer_periph) |= (uint32_t)ocfast; break; /* configure TIMER_CH_1 */ case TIMER_CH_1: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMFEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)timer_ocfast << 8U); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); break; /* configure TIMER_CH_2 */ case TIMER_CH_2: TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMFEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)timer_ocfast; + TIMER_CHCTL1(timer_periph) |= (uint32_t)ocfast; break; /* configure TIMER_CH_3 */ case TIMER_CH_3: TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMFEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)timer_ocfast << 8U); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); break; default: break; @@ -1037,40 +1148,42 @@ void timer_channel_output_fast_config(uint32_t timer_periph,uint16_t timer_chann /*! \brief configure TIMER channel output clear function - \param[in] timer_periph: TIMERx(x=0..4,7) - \param[in] timer_channel: - \arg TIMER_CH_0: TIMER channel0 - \arg TIMER_CH_1: TIMER channel1 - \arg TIMER_CH_2: TIMER channel2 - \arg TIMER_CH_3: TIMER channel3 - \param[in] timer_occlear: channel output clear function + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] occlear: channel output clear function + only one parameter can be selected which is shown as below: \arg TIMER_OC_CLEAR_ENABLE: channel output clear function enable \arg TIMER_OC_CLEAR_DISABLE: channel output clear function disable \param[out] none \retval none */ -void timer_channel_output_clear_config(uint32_t timer_periph,uint16_t timer_channel,uint16_t timer_occlear) +void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear) { - switch(timer_channel){ + switch(channel){ /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)timer_occlear; + TIMER_CHCTL0(timer_periph) |= (uint32_t)occlear; break; /* configure TIMER_CH_1 */ case TIMER_CH_1: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)timer_occlear << 8U); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); break; /* configure TIMER_CH_2 */ case TIMER_CH_2: TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)timer_occlear; + TIMER_CHCTL1(timer_periph) |= (uint32_t)occlear; break; /* configure TIMER_CH_3 */ case TIMER_CH_3: TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)timer_occlear << 8U); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); break; default: break; @@ -1078,41 +1191,43 @@ void timer_channel_output_clear_config(uint32_t timer_periph,uint16_t timer_chan } /*! - \brief configure TIMER channel output polarity + \brief configure TIMER channel output polarity \param[in] timer_periph: please refer to the following parameters - \param[in] timer_channel: + \param[in] channel: + only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] timer_ocpolarity: channel output polarity + \param[in] ocpolarity: channel output polarity + only one parameter can be selected which is shown as below: \arg TIMER_OC_POLARITY_HIGH: channel output polarity is high \arg TIMER_OC_POLARITY_LOW: channel output polarity is low \param[out] none \retval none */ -void timer_channel_output_polarity_config(uint32_t timer_periph,uint16_t timer_channel,uint16_t timer_ocpolarity) +void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity) { - switch(timer_channel){ + switch(channel){ /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)timer_ocpolarity; + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpolarity; break; /* configure TIMER_CH_1 */ case TIMER_CH_1: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)timer_ocpolarity << 4U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 4U); break; /* configure TIMER_CH_2 */ case TIMER_CH_2: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)timer_ocpolarity << 8U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 8U); break; /* configure TIMER_CH_3 */ case TIMER_CH_3: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)timer_ocpolarity << 12U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 12U); break; default: break; @@ -1120,35 +1235,37 @@ void timer_channel_output_polarity_config(uint32_t timer_periph,uint16_t timer_c } /*! - \brief configure TIMER channel complementary output polarity - \param[in] timer_periph: TIMERx(x=0,7) - \param[in] timer_channel: + \brief configure TIMER channel complementary output polarity + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) - \param[in] timer_ocnpolarity: channel complementary output polarity + \param[in] ocnpolarity: channel complementary output polarity + only one parameter can be selected which is shown as below: \arg TIMER_OCN_POLARITY_HIGH: channel complementary output polarity is high \arg TIMER_OCN_POLARITY_LOW: channel complementary output polarity is low \param[out] none \retval none */ -void timer_channel_complementary_output_polarity_config(uint32_t timer_periph,uint16_t timer_channel,uint16_t timer_ocnpolarity) +void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity) { - switch(timer_channel){ + switch(channel){ /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); - TIMER_CHCTL2(timer_periph) |= (uint32_t)timer_ocnpolarity; + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnpolarity; break; /* configure TIMER_CH_1 */ case TIMER_CH_1: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)timer_ocnpolarity << 4U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 4U); break; /* configure TIMER_CH_2 */ case TIMER_CH_2: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)timer_ocnpolarity << 8U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 8U); break; default: break; @@ -1158,39 +1275,41 @@ void timer_channel_complementary_output_polarity_config(uint32_t timer_periph,ui /*! \brief configure TIMER channel enable state \param[in] timer_periph: please refer to the following parameters - \param[in] timer_channel: + \param[in] channel: + only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] timer_state: TIMER channel enable state - \arg TIMER_CCX_ENABLE: channel enable - \arg TIMER_CCX_DISABLE: channel disable + \param[in] state: TIMER channel enable state + only one parameter can be selected which is shown as below: + \arg TIMER_CCX_ENABLE: channel enable + \arg TIMER_CCX_DISABLE: channel disable \param[out] none \retval none */ -void timer_channel_output_state_config(uint32_t timer_periph,uint16_t timer_channel,uint32_t timer_state) +void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state) { - switch(timer_channel){ + switch(channel){ /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)timer_state; + TIMER_CHCTL2(timer_periph) |= (uint32_t)state; break; /* configure TIMER_CH_1 */ case TIMER_CH_1: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)timer_state << 4U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 4U); break; /* configure TIMER_CH_2 */ case TIMER_CH_2: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)timer_state << 8U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 8U); break; /* configure TIMER_CH_3 */ case TIMER_CH_3: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)timer_state << 12U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 12U); break; default: break; @@ -1200,33 +1319,35 @@ void timer_channel_output_state_config(uint32_t timer_periph,uint16_t timer_chan /*! \brief configure TIMER channel complementary output enable state \param[in] timer_periph: TIMERx(x=0,7) - \param[in] timer_channel: + \param[in] channel: + only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel0 \arg TIMER_CH_1: TIMER channel1 \arg TIMER_CH_2: TIMER channel2 - \param[in] timer_ocnstate: TIMER channel complementary output enable state - \arg TIMER_CCXN_ENABLE: channel complementary enable - \arg TIMER_CCXN_DISABLE: channel complementary disable + \param[in] ocnstate: TIMER channel complementary output enable state + only one parameter can be selected which is shown as below: + \arg TIMER_CCXN_ENABLE: channel complementary enable + \arg TIMER_CCXN_DISABLE: channel complementary disable \param[out] none \retval none */ -void timer_channel_complementary_output_state_config(uint32_t timer_periph,uint16_t timer_channel,uint16_t timer_ocnstate) +void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate) { - switch(timer_channel){ + switch(channel){ /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)timer_ocnstate; + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnstate; break; /* configure TIMER_CH_1 */ case TIMER_CH_1: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)timer_ocnstate << 4U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 4U); break; /* configure TIMER_CH_2 */ case TIMER_CH_2: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)timer_ocnstate << 8U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 8U); break; default: break; @@ -1234,14 +1355,30 @@ void timer_channel_complementary_output_state_config(uint32_t timer_periph,uint1 } /*! - \brief configure TIMER input capture parameter + \brief initialize TIMER channel input parameter struct with a default value + \param[in] icpara: TIMER channel intput parameter struct + \param[out] none + \retval none +*/ +void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara) +{ + /* initialize the channel input parameter struct member with the default value */ + icpara->icpolarity = TIMER_IC_POLARITY_RISING; + icpara->icselection = TIMER_IC_SELECTION_DIRECTTI; + icpara->icprescaler = TIMER_IC_PSC_DIV1; + icpara->icfilter = 0U; +} + +/*! + \brief configure TIMER input capture parameter \param[in] timer_periph: please refer to the following parameters - \param[in] timer_channel: + \param[in] channel: + only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] timer_icpara: TIMER channel intput parameter struct + \param[in] icpara: TIMER channel intput parameter struct icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING,TIMER_IC_POLARITY_BOTH_EDGE icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI,TIMER_IC_SELECTION_ITS icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8 @@ -1249,9 +1386,9 @@ void timer_channel_complementary_output_state_config(uint32_t timer_periph,uint1 \param[out] none \retval none */ -void timer_input_capture_config(uint32_t timer_periph,uint16_t timer_channel,timer_ic_parameter_struct* timer_icpara) +void timer_input_capture_config(uint32_t timer_periph,uint16_t channel, timer_ic_parameter_struct* icpara) { - switch(timer_channel){ + switch(channel){ /* configure TIMER_CH_0 */ case TIMER_CH_0: /* reset the CH0EN bit */ @@ -1259,18 +1396,18 @@ void timer_input_capture_config(uint32_t timer_periph,uint16_t timer_channel,tim /* reset the CH0P and CH0NP bits */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)(timer_icpara->icpolarity); + TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpara->icpolarity); /* reset the CH0MS bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); - TIMER_CHCTL0(timer_periph) |= (uint32_t)(timer_icpara->icselection); + TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpara->icselection); /* reset the CH0CAPFLT bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(timer_icpara->icfilter) << 4U); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); /* set the CH0EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; break; - + /* configure TIMER_CH_1 */ case TIMER_CH_1: /* reset the CH1EN bit */ @@ -1278,13 +1415,13 @@ void timer_input_capture_config(uint32_t timer_periph,uint16_t timer_channel,tim /* reset the CH1P and CH1NP bits */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(timer_icpara->icpolarity)<< 4U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 4U); /* reset the CH1MS bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(timer_icpara->icselection)<< 8U); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U); /* reset the CH1CAPFLT bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(timer_icpara->icfilter)<< 12U); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); /* set the CH1EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; @@ -1296,15 +1433,15 @@ void timer_input_capture_config(uint32_t timer_periph,uint16_t timer_channel,tim /* reset the CH2P and CH2NP bits */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH2P|TIMER_CHCTL2_CH2NP)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(timer_icpara->icpolarity)<< 8U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 8U); /* reset the CH2MS bit */ TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2MS); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(timer_icpara->icselection)); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection)); /* reset the CH2CAPFLT bit */ TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPFLT); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(timer_icpara->icfilter)<< 4U); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); /* set the CH2EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH2EN; @@ -1316,15 +1453,15 @@ void timer_input_capture_config(uint32_t timer_periph,uint16_t timer_channel,tim /* reset the CH3P bits */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH3P)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(timer_icpara->icpolarity)<< 12U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 12U); /* reset the CH3MS bit */ TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3MS); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(timer_icpara->icselection)<< 8U); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U); /* reset the CH3CAPFLT bit */ TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPFLT); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(timer_icpara->icfilter)<< 12U); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); /* set the CH3EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH3EN; @@ -1333,18 +1470,20 @@ void timer_input_capture_config(uint32_t timer_periph,uint16_t timer_channel,tim break; } /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph,timer_channel,(uint16_t)(timer_icpara->icprescaler)); + timer_channel_input_capture_prescaler_config(timer_periph, channel, (uint16_t)(icpara->icprescaler)); } /*! \brief configure TIMER channel input capture prescaler value \param[in] timer_periph: please refer to the following parameters - \param[in] timer_channel: + \param[in] channel: + only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] timer_prescaler: channel input capture prescaler value + \param[in] prescaler: channel input capture prescaler value + only one parameter can be selected which is shown as below: \arg TIMER_IC_PSC_DIV1: no prescaler \arg TIMER_IC_PSC_DIV2: divided by 2 \arg TIMER_IC_PSC_DIV4: divided by 4 @@ -1352,28 +1491,28 @@ void timer_input_capture_config(uint32_t timer_periph,uint16_t timer_channel,tim \param[out] none \retval none */ -void timer_channel_input_capture_prescaler_config(uint32_t timer_periph,uint16_t timer_channel,uint16_t timer_prescaler) +void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler) { - switch(timer_channel){ + switch(channel){ /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPPSC); - TIMER_CHCTL0(timer_periph) |= (uint32_t)timer_prescaler; + TIMER_CHCTL0(timer_periph) |= (uint32_t)prescaler; break; /* configure TIMER_CH_1 */ case TIMER_CH_1: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPPSC); - TIMER_CHCTL0(timer_periph) |= ((uint32_t)timer_prescaler << 8U); + TIMER_CHCTL0(timer_periph) |= ((uint32_t)prescaler << 8U); break; /* configure TIMER_CH_2 */ case TIMER_CH_2: TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPPSC); - TIMER_CHCTL1(timer_periph) |= (uint32_t)timer_prescaler; + TIMER_CHCTL1(timer_periph) |= (uint32_t)prescaler; break; /* configure TIMER_CH_3 */ case TIMER_CH_3: TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPPSC); - TIMER_CHCTL1(timer_periph) |= ((uint32_t)timer_prescaler << 8U); + TIMER_CHCTL1(timer_periph) |= ((uint32_t)prescaler << 8U); break; default: break; @@ -1383,7 +1522,8 @@ void timer_channel_input_capture_prescaler_config(uint32_t timer_periph,uint16_t /*! \brief read TIMER channel capture compare register value \param[in] timer_periph: please refer to the following parameters - \param[in] timer_channel: + \param[in] channel: + only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) @@ -1391,20 +1531,24 @@ void timer_channel_input_capture_prescaler_config(uint32_t timer_periph,uint16_t \param[out] none \retval channel capture compare register value */ -uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph,uint16_t timer_channel) +uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel) { uint32_t count_value = 0U; - switch(timer_channel){ + switch(channel){ + /* read TIMER channel 0 capture compare register value */ case TIMER_CH_0: count_value = TIMER_CH0CV(timer_periph); break; + /* read TIMER channel 1 capture compare register value */ case TIMER_CH_1: count_value = TIMER_CH1CV(timer_periph); break; + /* read TIMER channel 2 capture compare register value */ case TIMER_CH_2: count_value = TIMER_CH2CV(timer_periph); break; + /* read TIMER channel 3 capture compare register value */ case TIMER_CH_3: count_value = TIMER_CH3CV(timer_periph); break; @@ -1415,12 +1559,13 @@ uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph,uint16_ } /*! - \brief configure TIMER input pwm capture function + \brief configure TIMER input pwm capture function \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] timer_channel: + \param[in] channel: + only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel0 \arg TIMER_CH_1: TIMER channel1 - \param[in] timer_icpwm:TIMER channel intput pwm parameter struct + \param[in] icpwm:TIMER channel intput pwm parameter struct icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8 @@ -1428,80 +1573,82 @@ uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph,uint16_ \param[out] none \retval none */ -void timer_input_pwm_capture_config(uint32_t timer_periph,uint16_t timer_channel,timer_ic_parameter_struct* timer_icpwm) +void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm) { uint16_t icpolarity = 0x0U; uint16_t icselection = 0x0U; - if(TIMER_IC_POLARITY_RISING == timer_icpwm->icpolarity){ + /* Set channel input polarity */ + if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity){ icpolarity = TIMER_IC_POLARITY_FALLING; }else{ icpolarity = TIMER_IC_POLARITY_RISING; } - if(TIMER_IC_SELECTION_DIRECTTI == timer_icpwm->icselection){ + /* Set channel input mode selection */ + if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection){ icselection = TIMER_IC_SELECTION_INDIRECTTI; }else{ icselection = TIMER_IC_SELECTION_DIRECTTI; } - if(TIMER_CH_0 == timer_channel){ + if(TIMER_CH_0 == channel){ /* reset the CH0EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); /* reset the CH0P and CH0NP bits */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); /* set the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)(timer_icpwm->icpolarity); + TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpwm->icpolarity); /* reset the CH0MS bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); /* set the CH0MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)(timer_icpwm->icselection); + TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpwm->icselection); /* reset the CH0CAPFLT bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); /* set the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= ((uint32_t)(timer_icpwm->icfilter) << 4U); + TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); /* set the CH0EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_0,(uint16_t)(timer_icpwm->icprescaler)); + timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_0,(uint16_t)(icpwm->icprescaler)); /* reset the CH1EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); /* reset the CH1P and CH1NP bits */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); /* set the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity<< 4U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity << 4U); /* reset the CH1MS bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); /* set the CH1MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection<< 8U); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection << 8U); /* reset the CH1CAPFLT bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); /* set the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(timer_icpwm->icfilter)<< 12U); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U); /* set the CH1EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_1,(uint16_t)(timer_icpwm->icprescaler)); + timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_1,(uint16_t)(icpwm->icprescaler)); }else{ /* reset the CH1EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); /* reset the CH1P and CH1NP bits */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); /* set the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(timer_icpwm->icpolarity)<< 4U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icpolarity) << 4U); /* reset the CH1MS bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); /* set the CH1MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(timer_icpwm->icselection)<< 8U); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icselection) << 8U); /* reset the CH1CAPFLT bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); /* set the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(timer_icpwm->icfilter)<< 12U); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U); /* set the CH1EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_1,(uint16_t)(timer_icpwm->icprescaler)); + timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler)); /* reset the CH0EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); @@ -1516,168 +1663,180 @@ void timer_input_pwm_capture_config(uint32_t timer_periph,uint16_t timer_channel /* reset the CH0CAPFLT bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); /* set the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= ((uint32_t)(timer_icpwm->icfilter) << 4U); + TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); /* set the CH0EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_0,(uint16_t)(timer_icpwm->icprescaler)); + timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler)); } } /*! \brief configure TIMER hall sensor mode \param[in] timer_periph: TIMERx(x=0..4,7) - \param[in] timer_hallmode: + \param[in] hallmode: + only one parameter can be selected which is shown as below: \arg TIMER_HALLINTERFACE_ENABLE: TIMER hall sensor mode enable \arg TIMER_HALLINTERFACE_DISABLE: TIMER hall sensor mode disable \param[out] none \retval none */ -void timer_hall_mode_config(uint32_t timer_periph,uint8_t timer_hallmode) +void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode) { - if(TIMER_HALLINTERFACE_ENABLE == timer_hallmode){ + if(TIMER_HALLINTERFACE_ENABLE == hallmode){ TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S; - }else if(TIMER_HALLINTERFACE_DISABLE == timer_hallmode){ + }else if(TIMER_HALLINTERFACE_DISABLE == hallmode){ TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S; }else{ + /* illegal parameters */ } } /*! - \brief select TIMER input trigger source - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] timer_intrigger: - \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0 - \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1 - \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2 - \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3 - \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 Edge Detector - \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0 - \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1 - \arg TIMER_SMCFG_TRGSEL_ETIFP: external trigger + \brief select TIMER input trigger source + \param[in] timer_periph: please refer to the following parameters + \param[in] intrigger: + only one parameter can be selected which is shown as below: + \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0(TIMERx(x=0..4,7,8,11)) + \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2(TIMERx(x=0..4,7,8,11)) + \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3(TIMERx(x=0..4,7,8,11)) + \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector(TIMERx(x=0..4,7,8,11)) + \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0(TIMERx(x=0..4,7,8,11)) + \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_SMCFG_TRGSEL_ETIFP: external trigger(TIMERx(x=0..4,7,8,11)) \param[out] none \retval none */ -void timer_input_trigger_source_select(uint32_t timer_periph,uint32_t timer_intrigger) +void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger) { TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_TRGS); - TIMER_SMCFG(timer_periph) |= (uint32_t)timer_intrigger; + TIMER_SMCFG(timer_periph) |= (uint32_t)intrigger; } /*! - \brief select TIMER master mode output trigger source + \brief select TIMER master mode output trigger source \param[in] timer_periph: TIMERx(x=0..7) - \param[in] timer_outrigger: - \arg TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output - \arg TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal TIMER_CTL0_CEN as trigger output - \arg TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output - \arg TIMER_TRI_OUT_SRC_CC0: a capture or a compare match occurred in channal0 as trigger output TRGO - \arg TIMER_TRI_OUT_SRC_O0CPRE: O0CPRE as trigger output - \arg TIMER_TRI_OUT_SRC_O1CPRE: O1CPRE as trigger output - \arg TIMER_TRI_OUT_SRC_O2CPRE: O2CPRE as trigger output - \arg TIMER_TRI_OUT_SRC_O3CPRE: O3CPRE as trigger output + \param[in] outrigger: + only one parameter can be selected which is shown as below: + \arg TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output(TIMERx(x=0..7,9,10,12,13)) + \arg TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal TIMER_CTL0_CEN as trigger output(TIMERx(x=0..7,9,10,12,13)) + \arg TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output(TIMERx(x=0..7,9,10,12,13)) + \arg TIMER_TRI_OUT_SRC_CH0: a capture or a compare match occurred in channal0 as trigger output TRGO(TIMERx(x=0..4,7,9,10,12,13)) + \arg TIMER_TRI_OUT_SRC_O0CPRE: O0CPRE as trigger output(TIMERx(x=0..4,7,9,10,12,13)) + \arg TIMER_TRI_OUT_SRC_O1CPRE: O1CPRE as trigger output(TIMERx(x=0..4,7)) + \arg TIMER_TRI_OUT_SRC_O2CPRE: O2CPRE as trigger output(TIMERx(x=0..4,7)) + \arg TIMER_TRI_OUT_SRC_O3CPRE: O3CPRE as trigger output(TIMERx(x=0..4,7)) \param[out] none \retval none */ -void timer_master_output_trigger_source_select(uint32_t timer_periph,uint32_t timer_outrigger) +void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger) { TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_MMC); - TIMER_CTL1(timer_periph) |= (uint32_t)timer_outrigger; + TIMER_CTL1(timer_periph) |= (uint32_t)outrigger; } /*! - \brief select TIMER slave mode + \brief select TIMER slave mode \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] timer_slavemode: - \arg TIMER_SLAVE_MODE_DISABLE: slave mode disable - \arg TIMER_ENCODER_MODE0: encoder mode 0 - \arg TIMER_ENCODER_MODE1: encoder mode 1 - \arg TIMER_ENCODER_MODE2: encoder mode 2 - \arg TIMER_SLAVE_MODE_RESTART: restart mode - \arg TIMER_SLAVE_MODE_PAUSE: pause mode - \arg TIMER_SLAVE_MODE_EVENT: event mode - \arg TIMER_SLAVE_MODE_EXTERNAL0: external clock mode 0. + \param[in] slavemode: + only one parameter can be selected which is shown as below: + \arg TIMER_SLAVE_MODE_DISABLE: slave mode disable(TIMERx(x=0..4,7,8,11)) + \arg TIMER_ENCODER_MODE0: encoder mode 0(TIMERx(x=0..4,7)) + \arg TIMER_ENCODER_MODE1: encoder mode 1(TIMERx(x=0..4,7)) + \arg TIMER_ENCODER_MODE2: encoder mode 2(TIMERx(x=0..4,7)) + \arg TIMER_SLAVE_MODE_RESTART: restart mode(TIMERx(x=0..4,7,8,11)) + \arg TIMER_SLAVE_MODE_PAUSE: pause mode(TIMERx(x=0..4,7,8,11)) + \arg TIMER_SLAVE_MODE_EVENT: event mode(TIMERx(x=0..4,7,8,11)) + \arg TIMER_SLAVE_MODE_EXTERNAL0: external clock mode 0.(TIMERx(x=0..4,7,8,11)) \param[out] none \retval none */ -void timer_slave_mode_select(uint32_t timer_periph,uint32_t timer_slavemode) +void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode) { TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); - TIMER_SMCFG(timer_periph) |= (uint32_t)timer_slavemode; + TIMER_SMCFG(timer_periph) |= (uint32_t)slavemode; } /*! - \brief configure TIMER master slave mode + \brief configure TIMER master slave mode \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] timer_masterslave: + \param[in] masterslave: + only one parameter can be selected which is shown as below: \arg TIMER_MASTER_SLAVE_MODE_ENABLE: master slave mode enable \arg TIMER_MASTER_SLAVE_MODE_DISABLE: master slave mode disable \param[out] none \retval none -*/ -void timer_master_slave_mode_config(uint32_t timer_periph,uint8_t timer_masterslave) +*/ +void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave) { - if(TIMER_MASTER_SLAVE_MODE_ENABLE == timer_masterslave){ + if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave){ TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM; - }else if(TIMER_MASTER_SLAVE_MODE_DISABLE == timer_masterslave){ + }else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave){ TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM; }else{ + /* illegal parameters */ } } /*! \brief configure TIMER external trigger input \param[in] timer_periph: TIMERx(x=0..4,7) - \param[in] timer_extprescaler: + \param[in] extprescaler: + only one parameter can be selected which is shown as below: \arg TIMER_EXT_TRI_PSC_OFF: no divided \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 - \param[in] timer_expolarity: + \param[in] extpolarity: + only one parameter can be selected which is shown as below: \arg TIMER_ETP_FALLING: active low or falling edge active \arg TIMER_ETP_RISING: active high or rising edge active - \param[in] timer_extfilter: a value between 0 and 15 + \param[in] extfilter: a value between 0 and 15 \param[out] none \retval none */ -void timer_external_trigger_config(uint32_t timer_periph,uint32_t timer_extprescaler, - uint32_t timer_expolarity,uint32_t timer_extfilter) +void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, + uint32_t extpolarity, uint32_t extfilter) { - TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_ETP|TIMER_SMCFG_ETPSC|TIMER_SMCFG_ETFC)); - TIMER_SMCFG(timer_periph) |= (uint32_t)(timer_extprescaler|timer_expolarity); - TIMER_SMCFG(timer_periph) |= (uint32_t)(timer_extfilter<< 8U); + TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_ETP | TIMER_SMCFG_ETPSC | TIMER_SMCFG_ETFC)); + TIMER_SMCFG(timer_periph) |= (uint32_t)(extprescaler | extpolarity); + TIMER_SMCFG(timer_periph) |= (uint32_t)(extfilter << 8U); } /*! \brief configure TIMER quadrature decoder mode \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] timer_decomode: + \param[in] decomode: + only one parameter can be selected which is shown as below: \arg TIMER_ENCODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level \arg TIMER_ENCODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level \arg TIMER_ENCODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input - \param[in] timer_ic0polarity: + \param[in] ic0polarity: + only one parameter can be selected which is shown as below: \arg TIMER_IC_POLARITY_RISING: capture rising edge \arg TIMER_IC_POLARITY_FALLING: capture falling edge - \param[in] timer_ic1polarity: + \param[in] ic1polarity: + only one parameter can be selected which is shown as below: \arg TIMER_IC_POLARITY_RISING: capture rising edge \arg TIMER_IC_POLARITY_FALLING: capture falling edge \param[out] none \retval none */ -void timer_quadrature_decoder_mode_config(uint32_t timer_periph,uint32_t timer_decomode, - uint16_t timer_ic0polarity,uint16_t timer_ic1polarity) +void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, + uint16_t ic0polarity, uint16_t ic1polarity) { TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); - TIMER_SMCFG(timer_periph) |= (uint32_t)timer_decomode; + TIMER_SMCFG(timer_periph) |= (uint32_t)decomode; TIMER_CHCTL0(timer_periph) &= (uint32_t)(((~(uint32_t)TIMER_CHCTL0_CH0MS))&((~(uint32_t)TIMER_CHCTL0_CH1MS))); - TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI|((uint32_t)TIMER_IC_SELECTION_DIRECTTI<< 8U)); + TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI|((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U)); TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); - TIMER_CHCTL2(timer_periph) |= ((uint32_t)timer_ic0polarity|((uint32_t)timer_ic1polarity<< 4U)); + TIMER_CHCTL2(timer_periph) |= ((uint32_t)ic0polarity|((uint32_t)ic1polarity << 4U)); } /*! @@ -1694,7 +1853,8 @@ void timer_internal_clock_config(uint32_t timer_periph) /*! \brief configure TIMER the internal trigger as external clock input \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] timer_intrigger: + \param[in] intrigger: + only one parameter can be selected which is shown as below: \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0 \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1 \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2 @@ -1702,9 +1862,9 @@ void timer_internal_clock_config(uint32_t timer_periph) \param[out] none \retval none */ -void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t timer_intrigger) +void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger) { - timer_input_trigger_source_select(timer_periph,timer_intrigger); + timer_input_trigger_source_select(timer_periph, intrigger); TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; } @@ -1712,35 +1872,37 @@ void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint /*! \brief configure TIMER the external trigger as external clock input \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] timer_extrigger: - \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 Edge Detector + \param[in] extrigger: + only one parameter can be selected which is shown as below: + \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0 \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1 - \param[in] timer_expolarity: - \arg TIMER_IC_POLARITY_RISING: active low or falling edge active - \arg TIMER_IC_POLARITY_FALLING: active high or rising edge active - \param[in] timer_extfilter: a value between 0 and 15 + \param[in] extpolarity: + only one parameter can be selected which is shown as below: + \arg TIMER_IC_POLARITY_RISING: active high or rising edge active + \arg TIMER_IC_POLARITY_FALLING: active low or falling edge active + \param[in] extfilter: a value between 0 and 15 \param[out] none \retval none */ -void timer_external_trigger_as_external_clock_config(uint32_t timer_periph,uint32_t timer_extrigger, - uint16_t timer_expolarity,uint32_t timer_extfilter) +void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, + uint16_t extpolarity, uint32_t extfilter) { - if(TIMER_SMCFG_TRGSEL_CI1FE1 == timer_extrigger){ + if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger){ /* reset the CH1EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); /* reset the CH1NP bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); /* set the CH1NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)timer_expolarity << 4U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)extpolarity << 4U); /* reset the CH1MS bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); /* set the CH1MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI<< 8U); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U); /* reset the CH1CAPFLT bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); /* set the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)(timer_extfilter<< 8U); + TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 12U); /* set the CH1EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; }else{ @@ -1749,7 +1911,7 @@ void timer_external_trigger_as_external_clock_config(uint32_t timer_periph,uint3 /* reset the CH0P and CH0NP bits */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); /* set the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)timer_expolarity; + TIMER_CHCTL2(timer_periph) |= (uint32_t)extpolarity; /* reset the CH0MS bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); /* set the CH0MS bit */ @@ -1757,12 +1919,12 @@ void timer_external_trigger_as_external_clock_config(uint32_t timer_periph,uint3 /* reset the CH0CAPFLT bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)timer_extfilter; + TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 4U); /* set the CH0EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; } /* select TIMER input trigger source */ - timer_input_trigger_source_select(timer_periph,timer_extrigger); + timer_input_trigger_source_select(timer_periph,extrigger); /* reset the SMC bit */ TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); /* set the SMC bit */ @@ -1772,23 +1934,25 @@ void timer_external_trigger_as_external_clock_config(uint32_t timer_periph,uint3 /*! \brief configure TIMER the external clock mode0 \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] timer_extprescaler: + \param[in] extprescaler: + only one parameter can be selected which is shown as below: \arg TIMER_EXT_TRI_PSC_OFF: no divided \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 - \param[in] timer_expolarity: + \param[in] extpolarity: + only one parameter can be selected which is shown as below: \arg TIMER_ETP_FALLING: active low or falling edge active \arg TIMER_ETP_RISING: active high or rising edge active - \param[in] timer_extfilter: a value between 0 and 15 + \param[in] extfilter: a value between 0 and 15 \param[out] none \retval none */ -void timer_external_clock_mode0_config(uint32_t timer_periph,uint32_t timer_extprescaler, - uint32_t timer_expolarity,uint32_t timer_extfilter) +void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, + uint32_t extpolarity, uint32_t extfilter) { /* configure TIMER external trigger input */ - timer_external_trigger_config(timer_periph,timer_extprescaler,timer_expolarity,timer_extfilter); + timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter); /* reset the SMC bit,TRGS bit */ TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_SMC | TIMER_SMCFG_TRGS)); @@ -1799,23 +1963,25 @@ void timer_external_clock_mode0_config(uint32_t timer_periph,uint32_t timer_extp /*! \brief configure TIMER the external clock mode1 \param[in] timer_periph: TIMERx(x=0..4,7) - \param[in] timer_extprescaler: + \param[in] extprescaler: + only one parameter can be selected which is shown as below: \arg TIMER_EXT_TRI_PSC_OFF: no divided \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 - \param[in] timer_expolarity: + \param[in] extpolarity: + only one parameter can be selected which is shown as below: \arg TIMER_ETP_FALLING: active low or falling edge active \arg TIMER_ETP_RISING: active high or rising edge active - \param[in] timer_extfilter: a value between 0 and 15 + \param[in] extfilter: a value between 0 and 15 \param[out] none \retval none */ -void timer_external_clock_mode1_config(uint32_t timer_periph,uint32_t timer_extprescaler, - uint32_t timer_expolarity,uint32_t timer_extfilter) +void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, + uint32_t extpolarity, uint32_t extfilter) { /* configure TIMER external trigger input */ - timer_external_trigger_config(timer_periph,timer_extprescaler,timer_expolarity,timer_extfilter); + timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter); TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_SMC1; } @@ -1832,9 +1998,10 @@ void timer_external_clock_mode1_disable(uint32_t timer_periph) } /*! - \brief configure TIMER1 channel0 remap function + \brief configure TIMER channel remap function \param[in] timer_periph: TIMERx(x=1,4,10) - \param[in] timer_remap: + \param[in] remap: + only one parameter can be selected which is shown as below: \arg TIMER1_ITI1_RMP_TIMER7_TRGO: timer1 internal trigger input1 remap to TIMER7_TRGO \arg TIMER1_ITI1_RMP_ETHERNET_PTP: timer1 internal trigger input1 remap to ethernet PTP \arg TIMER1_ITI1_RMP_USB_FS_SOF: timer1 internal trigger input1 remap to USB FS SOF @@ -1842,51 +2009,55 @@ void timer_external_clock_mode1_disable(uint32_t timer_periph) \arg TIMER4_CI3_RMP_GPIO: timer4 channel 3 input remap to GPIO pin \arg TIMER4_CI3_RMP_IRC32K: timer4 channel 3 input remap to IRC32K \arg TIMER4_CI3_RMP_LXTAL: timer4 channel 3 input remap to LXTAL - \arg TIMER4_CI3_RMP_RTC_WAKEUP_INT: timer4 channel 3 input remap to RTC wakeup interrupt + \arg TIMER4_CI3_RMP_RTC_WAKEUP_INT: timer4 channel 3 input remap to RTC wakeup interrupt \arg TIMER10_ITI1_RMP_GPIO: timer10 internal trigger input1 remap based on GPIO setting \arg TIMER10_ITI1_RMP_RTC_HXTAL_DIV: timer10 internal trigger input1 remap HXTAL _DIV(clock used for RTC which is HXTAL clock divided by RTCDIV bits in RCU_CFG0 register) \param[out] none \retval none */ -void timer_channel_remap_config(uint32_t timer_periph,uint32_t timer_remap) +void timer_channel_remap_config(uint32_t timer_periph, uint32_t remap) { - TIMER_IRMP(timer_periph) = (uint32_t)timer_remap; + TIMER_IRMP(timer_periph) = (uint32_t)remap; } /*! \brief configure TIMER write CHxVAL register selection \param[in] timer_periph: TIMERx(x=0,1,2,13,14,15,16) - \param[in] timer_ccsel: - \arg TIMER_CCSEL_DISABLE: no effect - \arg TIMER_CCSEL_ENABLE: if write the CHxVAL register, the write value is same as the CHxVAL value, the write access ignored + \param[in] ccsel: + only one parameter can be selected which is shown as below: + \arg TIMER_CHVSEL_DISABLE: no effect + \arg TIMER_CHVSEL_ENABLE: when write the CHxVAL register, if the write value is same as the CHxVAL value, the write access is ignored \param[out] none \retval none */ -void timer_write_cc_register_config(uint32_t timer_periph, uint16_t timer_ccsel) +void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel) { - if(TIMER_CCSEL_ENABLE == timer_ccsel){ + if(TIMER_CHVSEL_ENABLE == ccsel){ TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_CHVSEL; - }else if(TIMER_CCSEL_DISABLE == timer_ccsel){ + }else if(TIMER_CHVSEL_DISABLE == ccsel){ TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_CHVSEL; }else{ + /* illegal parameters */ } } /*! \brief configure TIMER output value selection \param[in] timer_periph: TIMERx(x=0,7) - \param[in] timer_outsel: + \param[in] outsel: + only one parameter can be selected which is shown as below: \arg TIMER_OUTSEL_DISABLE: no effect \arg TIMER_OUTSEL_ENABLE: if POEN and IOS is 0, the output disabled \param[out] none \retval none */ -void timer_output_value_selection_config(uint32_t timer_periph, uint16_t timer_outsel) +void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel) { - if(TIMER_OUTSEL_ENABLE == timer_outsel){ + if(TIMER_OUTSEL_ENABLE == outsel){ TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_OUTSEL; - }else if(TIMER_OUTSEL_DISABLE == timer_outsel){ + }else if(TIMER_OUTSEL_DISABLE == outsel){ TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_OUTSEL; }else{ + /* illegal parameters */ } } diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_tli.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_tli.c index dfa65744ba..9d719bb29b 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_tli.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_tli.c @@ -1,18 +1,46 @@ /*! - \file gd32f4xx_tli.c - \brief TLI driver + \file gd32f4xx_tli.c + \brief TLI driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.1, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_tli.h" +#define TLI_DEFAULT_VALUE 0x00000000U +#define TLI_OPAQUE_VALUE 0x000000FFU + /*! - \brief deinitialize TLI registers + \brief deinitialize TLI registers \param[in] none \param[out] none \retval none @@ -24,15 +52,57 @@ void tli_deinit(void) } /*! - \brief initialize TLI display timing parameters - \param[in] tli_struct: the data needed to initialize tli. + \brief initialize the parameters of TLI parameter structure with the default values, it is suggested + that call this function after a tli_parameter_struct structure is defined + \param[in] none + \param[out] tli_struct: the data needed to initialize TLI synpsz_vpsz: size of the vertical synchronous pulse synpsz_hpsz: size of the horizontal synchronous pulse - backpsz_vbpsz: size of the vertical back porch plus synchronous pulse + backpsz_vbpsz: size of the vertical back porch plus synchronous pulse backpsz_hbpsz: size of the horizontal back porch plus synchronous pulse activesz_vasz: size of the vertical active area width plus back porch and synchronous pulse activesz_hasz: size of the horizontal active area width plus back porch and synchronous pulse - totalsz_vtsz: vertical total size of the display, including active area, back porch, synchronous + totalsz_vtsz: vertical total size of the display, including active area, back porch, synchronous + totalsz_htsz: vorizontal total size of the display, including active area, back porch, synchronous + backcolor_red: background value red + backcolor_green: background value green + backcolor_blue: background value blue + signalpolarity_hs: TLI_HSYN_ACTLIVE_LOW,TLI_HSYN_ACTLIVE_HIGHT + signalpolarity_vs: TLI_VSYN_ACTLIVE_LOW,TLI_VSYN_ACTLIVE_HIGHT + signalpolarity_de: TLI_DE_ACTLIVE_LOW,TLI_DE_ACTLIVE_HIGHT + signalpolarity_pixelck: TLI_PIXEL_CLOCK_TLI,TLI_PIXEL_CLOCK_INVERTEDTLI + \retval none +*/ +void tli_struct_para_init(tli_parameter_struct *tli_struct) +{ + /* initialize the struct parameters with default values */ + tli_struct->synpsz_vpsz = TLI_DEFAULT_VALUE; + tli_struct->synpsz_hpsz = TLI_DEFAULT_VALUE; + tli_struct->backpsz_vbpsz = TLI_DEFAULT_VALUE; + tli_struct->backpsz_hbpsz = TLI_DEFAULT_VALUE; + tli_struct->activesz_vasz = TLI_DEFAULT_VALUE; + tli_struct->activesz_hasz = TLI_DEFAULT_VALUE; + tli_struct->totalsz_vtsz = TLI_DEFAULT_VALUE; + tli_struct->totalsz_htsz = TLI_DEFAULT_VALUE; + tli_struct->backcolor_red = TLI_DEFAULT_VALUE; + tli_struct->backcolor_green = TLI_DEFAULT_VALUE; + tli_struct->backcolor_blue = TLI_DEFAULT_VALUE; + tli_struct->signalpolarity_hs = TLI_HSYN_ACTLIVE_LOW; + tli_struct->signalpolarity_vs = TLI_VSYN_ACTLIVE_LOW; + tli_struct->signalpolarity_de = TLI_DE_ACTLIVE_LOW; + tli_struct->signalpolarity_pixelck = TLI_PIXEL_CLOCK_TLI; +} + +/*! + \brief initialize TLI display timing parameters + \param[in] tli_struct: the data needed to initialize TLI + synpsz_vpsz: size of the vertical synchronous pulse + synpsz_hpsz: size of the horizontal synchronous pulse + backpsz_vbpsz: size of the vertical back porch plus synchronous pulse + backpsz_hbpsz: size of the horizontal back porch plus synchronous pulse + activesz_vasz: size of the vertical active area width plus back porch and synchronous pulse + activesz_hasz: size of the horizontal active area width plus back porch and synchronous pulse + totalsz_vtsz: vertical total size of the display, including active area, back porch, synchronous totalsz_htsz: vorizontal total size of the display, including active area, back porch, synchronous backcolor_red: background value red backcolor_green: background value green @@ -48,19 +118,19 @@ void tli_init(tli_parameter_struct *tli_struct) { /* synchronous pulse size configuration */ TLI_SPSZ &= ~(TLI_SPSZ_VPSZ|TLI_SPSZ_HPSZ); - TLI_SPSZ = (tli_struct->synpsz_vpsz|(tli_struct->synpsz_hpsz<<16U)); + TLI_SPSZ = (uint32_t)((uint32_t)tli_struct->synpsz_vpsz|((uint32_t)tli_struct->synpsz_hpsz<<16U)); /* back-porch size configuration */ TLI_BPSZ &= ~(TLI_BPSZ_VBPSZ|TLI_BPSZ_HBPSZ); - TLI_BPSZ = (tli_struct->backpsz_vbpsz|(tli_struct->backpsz_hbpsz<<16U)); - /* active size configuration */ + TLI_BPSZ = (uint32_t)((uint32_t)tli_struct->backpsz_vbpsz|((uint32_t)tli_struct->backpsz_hbpsz<<16U)); + /* active size configuration */ TLI_ASZ &= ~(TLI_ASZ_VASZ|TLI_ASZ_HASZ); TLI_ASZ = (tli_struct->activesz_vasz|(tli_struct->activesz_hasz<<16U)); - /* total size configuration */ + /* total size configuration */ TLI_TSZ &= ~(TLI_TSZ_VTSZ|TLI_TSZ_HTSZ); TLI_TSZ = (tli_struct->totalsz_vtsz|(tli_struct->totalsz_htsz<<16U)); - /* background color configuration */ + /* background color configuration */ TLI_BGC &= ~(TLI_BGC_BVB|(TLI_BGC_BVG)|(TLI_BGC_BVR)); - TLI_BGC = (tli_struct->backcolor_blue|(tli_struct->backcolor_green<<8U)|(tli_struct->backcolor_red<<16U)); + TLI_BGC = (tli_struct->backcolor_blue|(tli_struct->backcolor_green<<8U)|(tli_struct->backcolor_red<<16U)); TLI_CTL &= ~(TLI_CTL_HPPS|TLI_CTL_VPPS|TLI_CTL_DEPS|TLI_CTL_CLKPS); TLI_CTL |= (tli_struct->signalpolarity_hs|tli_struct->signalpolarity_vs|\ tli_struct->signalpolarity_de|tli_struct->signalpolarity_pixelck); @@ -68,14 +138,17 @@ void tli_init(tli_parameter_struct *tli_struct) } /*! - \brief dither function configure - \param[in] ditherstat: TLI_DITHER_ENABLE,TLI_DITHER_DISABLE + \brief configure TLI dither function + \param[in] dither_stat + only one parameter can be selected which is shown as below: + \arg TLI_DITHER_ENABLE + \arg TLI_DITHER_DISABLE \param[out] none \retval none */ -void tli_dither_config(uint8_t ditherstat) +void tli_dither_config(uint8_t dither_stat) { - if(TLI_DITHER_ENABLE == ditherstat){ + if(TLI_DITHER_ENABLE == dither_stat){ TLI_CTL |= TLI_CTL_DFEN; }else{ TLI_CTL &= ~(TLI_CTL_DFEN); @@ -83,8 +156,8 @@ void tli_dither_config(uint8_t ditherstat) } /*! - \brief TLI enable - \param[in] none. + \brief enable TLI + \param[in] none \param[out] none \retval none */ @@ -94,215 +167,89 @@ void tli_enable(void) } /*! - \brief TLI disable - \param[in] none. + \brief disable TLI + \param[in] none \param[out] none \retval none */ void tli_disable(void) { - TLI_CTL &= ~(TLI_CTL_DFEN); + TLI_CTL &= ~(TLI_CTL_TLIEN); } /*! - \brief TLI reload layer configure - \param[in] reloadmod: TLI_FRAME_BLANK_RELOAD_EN,TLI_REQUEST_RELOAD_EN + \brief configure TLI reload mode + \param[in] reload_mod + only one parameter can be selected which is shown as below: + \arg TLI_FRAME_BLANK_RELOAD_EN + \arg TLI_REQUEST_RELOAD_EN \param[out] none \retval none */ -void tli_reload_config(uint8_t reloadmod) +void tli_reload_config(uint8_t reload_mod) { - if(TLI_FRAME_BLANK_RELOAD_EN == reloadmod){ + if(TLI_FRAME_BLANK_RELOAD_EN == reload_mod){ + /* the layer configuration will be reloaded at frame blank */ TLI_RL |= TLI_RL_FBR; }else{ + /* the layer configuration will be reloaded after this bit sets */ TLI_RL |= TLI_RL_RQR; } } /*! - \brief TLI interrupt enable - \param[in] inttype: TLI interrupt bits. - \arg TLI_INTEN_LMIE: line mark interrupt - \arg TLI_INTEN_FEIE: FIFO error interrupt - \arg TLI_INTEN_TEIE: transaction error interrupt - \arg TLI_INTEN_LCRIE: layer configuration reloaded interrupt - \param[out] none + \brief initialize the parameters of TLI layer structure with the default values, it is suggested + that call this function after a tli_layer_parameter_struct structure is defined + \param[in] none + \param[out] layer_struct: TLI Layer parameter struct + layer_window_rightpos: window right position + layer_window_leftpos: window left position + layer_window_bottompos: window bottom position + layer_window_toppos: window top position + layer_ppf: LAYER_PPF_ARGB8888,LAYER_PPF_RGB888,LAYER_PPF_RGB565, + LAYER_PPF_ARG1555,LAYER_PPF_ARGB4444,LAYER_PPF_L8, + LAYER_PPF_AL44,LAYER_PPF_AL88 + layer_sa: specified alpha + layer_default_alpha: the default color alpha + layer_default_red: the default color red + layer_default_green: the default color green + layer_default_blue: the default color blue + layer_acf1: LAYER_ACF1_SA,LAYER_ACF1_PASA + layer_acf2: LAYER_ACF2_SA,LAYER_ACF2_PASA + layer_frame_bufaddr: frame buffer base address + layer_frame_buf_stride_offset: frame buffer stride offset + layer_frame_line_length: frame line length + layer_frame_total_line_number: frame total line number \retval none */ -void tli_interrupt_enable(uint32_t inttype) +void tli_layer_struct_para_init(tli_layer_parameter_struct *layer_struct) { - TLI_INTEN |= (inttype); + /* initialize the struct parameters with default values */ + layer_struct->layer_window_rightpos = TLI_DEFAULT_VALUE; + layer_struct->layer_window_leftpos = TLI_DEFAULT_VALUE; + layer_struct->layer_window_bottompos = TLI_DEFAULT_VALUE; + layer_struct->layer_window_toppos = TLI_DEFAULT_VALUE; + layer_struct->layer_ppf = LAYER_PPF_ARGB8888; + layer_struct->layer_sa = TLI_OPAQUE_VALUE; + layer_struct->layer_default_alpha = TLI_DEFAULT_VALUE; + layer_struct->layer_default_red = TLI_DEFAULT_VALUE; + layer_struct->layer_default_green = TLI_DEFAULT_VALUE; + layer_struct->layer_default_blue = TLI_DEFAULT_VALUE; + layer_struct->layer_acf1 = LAYER_ACF1_PASA; + layer_struct->layer_acf2 = LAYER_ACF2_PASA; + layer_struct->layer_frame_bufaddr = TLI_DEFAULT_VALUE; + layer_struct->layer_frame_buf_stride_offset = TLI_DEFAULT_VALUE; + layer_struct->layer_frame_line_length = TLI_DEFAULT_VALUE; + layer_struct->layer_frame_total_line_number = TLI_DEFAULT_VALUE; } /*! - \brief TLI interrupt disable - \param[in] inttype: TLI interrupt bits. - \arg TLI_INTEN_LMIE: line mark interrupt - \arg TLI_INTEN_FEIE: FIFO error interrupt - \arg TLI_INTEN_TEIE: transaction error interrupt - \arg TLI_INTEN_LCRIE: layer configuration reloaded interrupt - \param[out] none - \retval none -*/ -void tli_interrupt_disable(uint32_t inttype) -{ - TLI_INTEN &= ~(inttype); -} - -/*! - \brief get TLI interrupt flag - \param[in] intflag: TLI interrupt flag bits. - \arg TLI_INTF_LMF: line mark flag - \arg TLI_INTF_FEF: FIFO error flag - \arg TLI_INTF_TEF: transaction error flag - \arg TLI_INTF_LCRF: layer configuration reloaded flag - \param[out] none - \retval none -*/ -FlagStatus tli_interrupt_flag_get(uint32_t intflag) -{ - uint32_t state; - state = TLI_INTF; - if(state & intflag){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear TLI interrupt flag - \param[in] intflag: TLI interrupt flag bits. - \arg TLI_INTC_LMC: line mark flag - \arg TLI_INTC_FEC: FIFO error flag - \arg TLI_INTC_TEC: transaction error flag - \arg TLI_INTC_LCRC: layer configuration reloaded flag - \param[out] none - \retval none -*/ -void tli_interrupt_flag_clear(uint32_t intflag) -{ - TLI_INTC |= (intflag); -} - -/*! - \brief set line mark value - \param[in] linenum: line number. - \param[out] none - \retval none -*/ -void tli_line_mark_set(uint32_t linenum) -{ - TLI_LM &= ~(TLI_LM_LM); - TLI_LM = linenum; -} - -/*! - \brief get current displayed position - \param[in] none - \param[out] none - \retval none -*/ -uint32_t tli_current_pos_get(void) -{ - return TLI_CPPOS; -} - - -/*! - \brief get TLI state - \param[in] state: TLI state. - \arg TLI_STAT_VDE: current VDE state - \arg TLI_STAT_HDE: current HDE state - \arg TLI_STAT_VS: current vs state - \arg TLI_STAT_HS: current hs state - \param[out] none - \retval none -*/ -FlagStatus tli_flag_get(uint32_t state) -{ - uint32_t stat; - stat = TLI_STAT; - if(state & stat){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief TLI layer enable - \param[in] layerx: LAYERx(x=0,1). - \param[out] none - \retval none -*/ -void tli_layer_enable(uint32_t layerx) -{ - TLI_LxCTL(layerx) |= TLI_LxCTL_LEN; -} - -/*! - \brief TLI layer disable - \param[in] layerx: LAYERx(x=0,1). - \param[out] none - \retval none -*/ -void tli_layer_disable(uint32_t layerx) -{ - TLI_LxCTL(layerx) &= ~(TLI_LxCTL_LEN); -} - -/*! - \brief TLI layer color keying enable - \param[in] layerx: LAYERx(x=0,1). - \param[out] none - \retval none -*/ -void tli_color_key_enable(uint32_t layerx) -{ - TLI_LxCTL(layerx) |= TLI_LxCTL_CKEYEN; -} - -/*! - \brief TLI layer color keying disable - \param[in] layerx: LAYERx(x=0,1). - \param[out] none - \retval none -*/ -void tli_color_key_disable(uint32_t layerx) -{ - TLI_LxCTL(layerx) &= ~(TLI_LxCTL_CKEYEN); -} - -/*! - \brief TLI layer LUT enable - \param[in] layerx: LAYERx(x=0,1). - \param[out] none - \retval none -*/ -void tli_lut_enable(uint32_t layerx) -{ - TLI_LxCTL(layerx) |= TLI_LxCTL_LUTEN; -} - -/*! - \brief TLI layer LUT disable - \param[in] layerx: LAYERx(x=0,1). - \param[out] none - \retval none -*/ -void tli_lut_disable(uint32_t layerx) -{ - TLI_LxCTL(layerx) &= ~(TLI_LxCTL_LUTEN); -} - -/*! - \brief TLI layer initialize + \brief initialize TLI layer \param[in] layerx: LAYERx(x=0,1) \param[in] layer_struct: TLI Layer parameter struct layer_window_rightpos: window right position layer_window_leftpos: window left position - layer_window_bottompos: window bottom position + layer_window_bottompos: window bottom position layer_window_toppos: window top position layer_ppf: LAYER_PPF_ARGB8888,LAYER_PPF_RGB888,LAYER_PPF_RGB565, LAYER_PPF_ARG1555,LAYER_PPF_ARGB4444,LAYER_PPF_L8, @@ -325,10 +272,10 @@ void tli_layer_init(uint32_t layerx,tli_layer_parameter_struct *layer_struct) { /* configure layer window horizontal position */ TLI_LxHPOS(layerx) &= ~(TLI_LxHPOS_WLP|(TLI_LxHPOS_WRP)); - TLI_LxHPOS(layerx) = (layer_struct->layer_window_leftpos | (layer_struct->layer_window_rightpos<<16U)); + TLI_LxHPOS(layerx) = (uint32_t)((uint32_t)layer_struct->layer_window_leftpos|((uint32_t)layer_struct->layer_window_rightpos<<16U)); /* configure layer window vertical position */ TLI_LxVPOS(layerx) &= ~(TLI_LxVPOS_WTP|(TLI_LxVPOS_WBP)); - TLI_LxVPOS(layerx) = (layer_struct->layer_window_toppos |(layer_struct->layer_window_bottompos<<16U)); + TLI_LxVPOS(layerx) = (uint32_t)((uint32_t)layer_struct->layer_window_toppos|((uint32_t)layer_struct->layer_window_bottompos<<16U)); /* configure layer packeted pixel format */ TLI_LxPPF(layerx) &= ~(TLI_LxPPF_PPF); TLI_LxPPF(layerx) = layer_struct->layer_ppf; @@ -337,9 +284,9 @@ void tli_layer_init(uint32_t layerx,tli_layer_parameter_struct *layer_struct) TLI_LxSA(layerx) = layer_struct->layer_sa; /* configure layer default color */ TLI_LxDC(layerx) &= ~(TLI_LxDC_DCB|(TLI_LxDC_DCG)|(TLI_LxDC_DCR)|(TLI_LxDC_DCA)); - TLI_LxDC(layerx) = (layer_struct->layer_default_blue |(layer_struct->layer_default_green<<8U) - |(layer_struct->layer_default_red<<16U) - |(layer_struct->layer_default_alpha<<24U)); + TLI_LxDC(layerx) = (uint32_t)((uint32_t)layer_struct->layer_default_blue|((uint32_t)layer_struct->layer_default_green<<8U) + |((uint32_t)layer_struct->layer_default_red<<16U) + |((uint32_t)layer_struct->layer_default_alpha<<24U)); /* configure layer alpha calculation factors */ TLI_LxBLEND(layerx) &= ~(TLI_LxBLEND_ACF2|(TLI_LxBLEND_ACF1)); @@ -349,54 +296,52 @@ void tli_layer_init(uint32_t layerx,tli_layer_parameter_struct *layer_struct) TLI_LxFBADDR(layerx) = (layer_struct->layer_frame_bufaddr); /* configure layer frame line length */ TLI_LxFLLEN(layerx) &= ~(TLI_LxFLLEN_FLL|(TLI_LxFLLEN_STDOFF)); - TLI_LxFLLEN(layerx) = (layer_struct->layer_frame_line_length|(layer_struct->layer_frame_buf_stride_offset<<16U)); - /* configure layer frame buffer base address */ - TLI_LxFBADDR(layerx) &= ~(TLI_LxFBADDR_FBADD); - TLI_LxFBADDR(layerx) = (layer_struct->layer_frame_bufaddr); + TLI_LxFLLEN(layerx) = (uint32_t)((uint32_t)layer_struct->layer_frame_line_length|((uint32_t)layer_struct->layer_frame_buf_stride_offset<<16U)); /* configure layer frame total line number */ - TLI_LxFTLN(layerx) &= ~(TLI_LxFTLN_FTLN); - TLI_LxFTLN(layerx) = (layer_struct->layer_frame_total_line_number); + TLI_LxFTLN(layerx) &= ~(TLI_LxFTLN_FTLN); + TLI_LxFTLN(layerx) = (uint32_t)(layer_struct->layer_frame_total_line_number); } /*! - \brief reconfigure window position - \param[in] layerx: LAYERx(x=0,1). - \param[in] offset_x: new horizontal offset . - \param[in] offset_y: new vertical offset. + \brief reconfigure window position + \param[in] layerx: LAYERx(x=0,1) + \param[in] offset_x: new horizontal offset + \param[in] offset_y: new vertical offset \param[out] none \retval none */ -void tli_layer_window_offset_modify(uint32_t layerx,uint32_t offset_x,uint32_t offset_y) +void tli_layer_window_offset_modify(uint32_t layerx,uint16_t offset_x,uint16_t offset_y) { /* configure window start position */ - uint32_t layer_ppf,line_length,line_num,hstart,vstart; + uint32_t layer_ppf, line_num, hstart, vstart; + uint32_t line_length = 0U; TLI_LxHPOS(layerx) &= ~(TLI_LxHPOS_WLP|(TLI_LxHPOS_WRP)); TLI_LxVPOS(layerx) &= ~(TLI_LxVPOS_WTP|(TLI_LxVPOS_WBP)); - hstart = offset_x+(((TLI_BPSZ & TLI_BPSZ_HBPSZ)>>16U)+1U); - vstart = offset_y+((TLI_BPSZ & TLI_BPSZ_VBPSZ)+1U); + hstart = (uint32_t)offset_x+(((TLI_BPSZ & TLI_BPSZ_HBPSZ)>>16U)+1U); + vstart = (uint32_t)offset_y+((TLI_BPSZ & TLI_BPSZ_VBPSZ)+1U); line_num = (TLI_LxFTLN(layerx) & TLI_LxFTLN_FTLN); layer_ppf = (TLI_LxPPF(layerx) & TLI_LxPPF_PPF); /* the bytes of a line equal TLI_LxFLLEN_FLL bits value minus 3 */ switch(layer_ppf){ case LAYER_PPF_ARGB8888: - /* each pixel includes 4bytes,when pixel format is ARGB8888 */ + /* each pixel includes 4bytes, when pixel format is ARGB8888 */ line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL)-3U)/4U); break; case LAYER_PPF_RGB888: - /* each pixel includes 3bytes,when pixel format is RGB888 */ + /* each pixel includes 3bytes, when pixel format is RGB888 */ line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL)-3U)/3U); break; case LAYER_PPF_RGB565: case LAYER_PPF_ARGB1555: case LAYER_PPF_ARGB4444: case LAYER_PPF_AL88: - /* each pixel includes 2bytes,when pixel format is RGB565,ARG1555,ARGB4444 or AL88 */ + /* each pixel includes 2bytes, when pixel format is RGB565,ARG1555,ARGB4444 or AL88 */ line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL)-3U)/2U); break; case LAYER_PPF_L8: case LAYER_PPF_AL44: - /* each pixel includes 1byte,when pixel format is L8 or AL44 */ + /* each pixel includes 1byte, when pixel format is L8 or AL44 */ line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL)-3U)); break; default: @@ -405,39 +350,249 @@ void tli_layer_window_offset_modify(uint32_t layerx,uint32_t offset_x,uint32_t o /* reconfigure window position */ TLI_LxHPOS(layerx) = (hstart|((hstart+line_length-1U)<<16U)); TLI_LxVPOS(layerx) = (vstart|((vstart+line_num-1U)<<16U)); - - } /*! - \brief TLI layer lut initialize + \brief initialize the parameters of TLI layer LUT structure with the default values, it is suggested + that call this function after a tli_layer_lut_parameter_struct structure is defined + \param[in] none + \param[out] lut_struct: TLI layer LUT parameter struct + layer_table_addr: look up table write address + layer_lut_channel_red: red channel of a LUT entry + layer_lut_channel_green: green channel of a LUT entry + layer_lut_channel_blue: blue channel of a LUT entry + \retval none +*/ +void tli_lut_struct_para_init(tli_layer_lut_parameter_struct *lut_struct) +{ + /* initialize the struct parameters with default values */ + lut_struct->layer_table_addr = TLI_DEFAULT_VALUE; + lut_struct->layer_lut_channel_red = TLI_DEFAULT_VALUE; + lut_struct->layer_lut_channel_green = TLI_DEFAULT_VALUE; + lut_struct->layer_lut_channel_blue = TLI_DEFAULT_VALUE; +} + +/*! + \brief initialize TLI layer LUT \param[in] layerx: LAYERx(x=0,1) \param[in] lut_struct: TLI layer LUT parameter struct - layer_table_addr: window right position - layer_lut_channel_red: window left position - layer_window_bottompos: window bottom position - layer_window_toppos: window top position + layer_table_addr: look up table write address + layer_lut_channel_red: red channel of a LUT entry + layer_lut_channel_green: green channel of a LUT entry + layer_lut_channel_blue: blue channel of a LUT entry \param[out] none \retval none */ void tli_lut_init(uint32_t layerx,tli_layer_lut_parameter_struct *lut_struct) { TLI_LxLUT(layerx) &= ~(TLI_LxLUT_TB|TLI_LxLUT_TG|TLI_LxLUT_TR|TLI_LxLUT_TADD); - TLI_LxLUT(layerx) = ((lut_struct->layer_lut_channel_blue)|(lut_struct->layer_lut_channel_green<<8) - |(lut_struct->layer_lut_channel_red<<16 - |(lut_struct->layer_table_addr<<24))); + TLI_LxLUT(layerx) = (uint32_t)(((uint32_t)lut_struct->layer_lut_channel_blue)|((uint32_t)lut_struct->layer_lut_channel_green<<8U) + |((uint32_t)lut_struct->layer_lut_channel_red<<16U + |((uint32_t)lut_struct->layer_table_addr<<24U))); } /*! - \brief TLI layer key initialize - \param[in] layerx: LAYERx(x=0,1). - \param[in] redkey: color key red. - \param[in] greenkey: color key green - \param[in] bluekey: color key blue. + \brief initialize TLI layer color key + \param[in] layerx: LAYERx(x=0,1) + \param[in] redkey: color key red + \param[in] greenkey: color key green + \param[in] bluekey: color key blue \param[out] none \retval none */ -void tli_ckey_init(uint32_t layerx,uint32_t redkey,uint32_t greenkey,uint32_t bluekey) +void tli_color_key_init(uint32_t layerx,uint8_t redkey,uint8_t greenkey,uint8_t bluekey) { - TLI_LxCKEY(layerx) = ((bluekey)|(greenkey<<8U)|(redkey<<16U)); + TLI_LxCKEY(layerx) = (((uint32_t)bluekey)|((uint32_t)greenkey<<8U)|((uint32_t)redkey<<16U)); +} + +/*! + \brief enable TLI layer + \param[in] layerx: LAYERx(x=0,1) + \param[out] none + \retval none +*/ +void tli_layer_enable(uint32_t layerx) +{ + TLI_LxCTL(layerx) |= TLI_LxCTL_LEN; +} + +/*! + \brief disable TLI layer + \param[in] layerx: LAYERx(x=0,1) + \param[out] none + \retval none +*/ +void tli_layer_disable(uint32_t layerx) +{ + TLI_LxCTL(layerx) &= ~(TLI_LxCTL_LEN); +} + +/*! + \brief enable TLI layer color keying + \param[in] layerx: LAYERx(x=0,1) + \param[out] none + \retval none +*/ +void tli_color_key_enable(uint32_t layerx) +{ + TLI_LxCTL(layerx) |= TLI_LxCTL_CKEYEN; +} + +/*! + \brief disable TLI layer color keying + \param[in] layerx: LAYERx(x=0,1) + \param[out] none + \retval none +*/ +void tli_color_key_disable(uint32_t layerx) +{ + TLI_LxCTL(layerx) &= ~(TLI_LxCTL_CKEYEN); +} + +/*! + \brief enable TLI layer LUT + \param[in] layerx: LAYERx(x=0,1) + \param[out] none + \retval none +*/ +void tli_lut_enable(uint32_t layerx) +{ + TLI_LxCTL(layerx) |= TLI_LxCTL_LUTEN; +} + +/*! + \brief disable TLI layer LUT + \param[in] layerx: LAYERx(x=0,1) + \param[out] none + \retval none +*/ +void tli_lut_disable(uint32_t layerx) +{ + TLI_LxCTL(layerx) &= ~(TLI_LxCTL_LUTEN); +} + +/*! + \brief set line mark value + \param[in] line_num: line number + \param[out] none + \retval none +*/ +void tli_line_mark_set(uint16_t line_num) +{ + TLI_LM &= ~(TLI_LM_LM); + TLI_LM = (uint32_t)line_num; +} + +/*! + \brief get current displayed position + \param[in] none + \param[out] none + \retval position of current pixel +*/ +uint32_t tli_current_pos_get(void) +{ + return TLI_CPPOS; +} + +/*! + \brief enable TLI interrupt + \param[in] int_flag: TLI interrupt flags + one or more parameters can be selected which are shown as below: + \arg TLI_INT_LM: line mark interrupt + \arg TLI_INT_FE: FIFO error interrupt + \arg TLI_INT_TE: transaction error interrupt + \arg TLI_INT_LCR: layer configuration reloaded interrupt + \param[out] none + \retval none +*/ +void tli_interrupt_enable(uint32_t int_flag) +{ + TLI_INTEN |= (int_flag); +} + +/*! + \brief disable TLI interrupt + \param[in] int_flag: TLI interrupt flags + one or more parameters can be selected which are shown as below: + \arg TLI_INT_LM: line mark interrupt + \arg TLI_INT_FE: FIFO error interrupt + \arg TLI_INT_TE: transaction error interrupt + \arg TLI_INT_LCR: layer configuration reloaded interrupt + \param[out] none + \retval none +*/ +void tli_interrupt_disable(uint32_t int_flag) +{ + TLI_INTEN &= ~(int_flag); +} + +/*! + \brief get TLI interrupt flag + \param[in] int_flag: TLI interrupt flags + one or more parameters can be selected which are shown as below: + \arg TLI_INT_FLAG_LM: line mark interrupt flag + \arg TLI_INT_FLAG_FE: FIFO error interrupt flag + \arg TLI_INT_FLAG_TE: transaction error interrupt flag + \arg TLI_INT_FLAG_LCR: layer configuration reloaded interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus tli_interrupt_flag_get(uint32_t int_flag) +{ + uint32_t state; + state = TLI_INTF; + if(state & int_flag){ + state = TLI_INTEN; + if(state & int_flag){ + return SET; + } + } + return RESET; +} + +/*! + \brief clear TLI interrupt flag + \param[in] int_flag: TLI interrupt flags + one or more parameters can be selected which are shown as below: + \arg TLI_INT_FLAG_LM: line mark interrupt flag + \arg TLI_INT_FLAG_FE: FIFO error interrupt flag + \arg TLI_INT_FLAG_TE: transaction error interrupt flag + \arg TLI_INT_FLAG_LCR: layer configuration reloaded interrupt flag + \param[out] none + \retval none +*/ +void tli_interrupt_flag_clear(uint32_t int_flag) +{ + TLI_INTC |= (int_flag); +} + +/*! + \brief get TLI flag or state in TLI_INTF register or TLI_STAT register + \param[in] flag: TLI flags or states + only one parameter can be selected which is shown as below: + \arg TLI_FLAG_VDE: current VDE state + \arg TLI_FLAG_HDE: current HDE state + \arg TLI_FLAG_VS: current VS status of the TLI + \arg TLI_FLAG_HS: current HS status of the TLI + \arg TLI_FLAG_LM: line mark interrupt flag + \arg TLI_FLAG_FE: FIFO error interrupt flag + \arg TLI_FLAG_TE: transaction error interrupt flag + \arg TLI_FLAG_LCR: layer configuration reloaded interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus tli_flag_get(uint32_t flag) +{ + uint32_t stat; + /* choose which register to get flag or state */ + if(flag >> 31U){ + stat = TLI_INTF; + }else{ + stat = TLI_STAT; + } + if(flag & stat){ + return SET; + }else{ + return RESET; + } } diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_trng.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_trng.c index f0defdcd51..8c86bb832e 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_trng.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_trng.c @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_trng.c - \brief TRNG driver + \file gd32f4xx_trng.c + \brief TRNG driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_trng.h" @@ -56,6 +81,28 @@ uint32_t trng_get_true_random_data(void) return (TRNG_DATA); } +/*! + \brief enable the TRNG interrupt + \param[in] none + \param[out] none + \retval none +*/ +void trng_interrupt_enable(void) +{ + TRNG_CTL |= TRNG_CTL_IE; +} + +/*! + \brief disable the TRNG interrupt + \param[in] none + \param[out] none + \retval none +*/ +void trng_interrupt_disable(void) +{ + TRNG_CTL &= ~TRNG_CTL_IE; +} + /*! \brief get the trng status flags \param[in] flag: trng status flag, refer to trng_flag_enum @@ -75,42 +122,6 @@ FlagStatus trng_flag_get(trng_flag_enum flag) } } -/*! - \brief clear the trng status flags - \param[in] flag: the special status flag - only one parameter can be selected which is shown as below: - \arg TRNG_FLAG_CECS: Clock error current status - \arg TRNG_FLAG_SECS: Seed error current status - \param[out] none - \retval none -*/ -void trng_flag_clear(trng_flag_enum flag) -{ - TRNG_STAT &= ~(uint32_t)flag; -} - -/*! - \brief enable the TRNG interrupt - \param[in] none - \param[out] none - \retval none -*/ -void trng_interrupt_enable(void) -{ - TRNG_CTL |= TRNG_CTL_IE; -} - -/*! - \brief disable the TRNG interrupt - \param[in] none - \param[out] none - \retval none -*/ -void trng_interrupt_disable(void) -{ - TRNG_CTL &= ~TRNG_CTL_IE; -} - /*! \brief get the trng interrupt flags \param[in] int_flag: trng interrupt flag, refer to trng_int_flag_enum diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_usart.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_usart.c index 945e60bc73..1b864e3b96 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_usart.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_usart.c @@ -1,18 +1,49 @@ /*! - \file gd32f4xx_usart.c - \brief USART driver + \file gd32f4xx_usart.c + \brief USART driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ + #include "gd32f4xx_usart.h" +/* USART register bit offset */ +#define GP_GUAT_OFFSET ((uint32_t)8U) /* bit offset of GUAT in USART_GP */ +#define CTL3_SCRTNUM_OFFSET ((uint32_t)1U) /* bit offset of SCRTNUM in USART_CTL3 */ +#define RT_BL_OFFSET ((uint32_t)24U) /* bit offset of BL in USART_RT */ + /*! - \brief reset USART/UART + \brief reset USART/UART \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[out] none \retval none @@ -63,7 +94,7 @@ void usart_deinit(uint32_t usart_periph) \param[in] baudval: baud rate value \param[out] none \retval none -*/ +*/ void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval) { uint32_t uclk=0U, intdiv=0U, fradiv=0U, udiv=0U; @@ -100,24 +131,25 @@ void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval) /* when oversampling by 8, configure the value of USART_BAUD */ udiv = ((2U*uclk) + baudval/2U)/baudval; intdiv = udiv & 0xfff0U; - fradiv = udiv & 0x7U; - USART_BAUD(usart_periph) |= ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); + fradiv = (udiv>>1U) & 0x7U; + USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); }else{ /* when oversampling by 16, configure the value of USART_BAUD */ udiv = (uclk+baudval/2U)/baudval; intdiv = udiv & 0xfff0U; fradiv = udiv & 0xfU; - USART_BAUD(usart_periph) |= ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); - } + USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); + } } /*! \brief configure USART parity function \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[in] paritycfg: configure USART parity + only one parameter can be selected which is shown as below: \arg USART_PM_NONE: no parity + \arg USART_PM_EVEN: even parity \arg USART_PM_ODD: odd parity - \arg USART_PM_EVEN: even parity \param[out] none \retval none */ @@ -133,6 +165,7 @@ void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg) \brief configure USART word length \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[in] wlen: USART word length configure + only one parameter can be selected which is shown as below: \arg USART_WL_8BIT: 8 bits \arg USART_WL_9BIT: 9 bits \param[out] none @@ -150,17 +183,18 @@ void usart_word_length_set(uint32_t usart_periph, uint32_t wlen) \brief configure USART stop bit length \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[in] stblen: USART stop bit configure + only one parameter can be selected which is shown as below: \arg USART_STB_1BIT: 1 bit - \arg USART_STB_0_5BIT: 0.5 bit + \arg USART_STB_0_5BIT: 0.5 bit(not available for UARTx(x=3,4,6,7)) \arg USART_STB_2BIT: 2 bits - \arg USART_STB_1_5BIT: 1.5 bits + \arg USART_STB_1_5BIT: 1.5 bits(not available for UARTx(x=3,4,6,7)) \param[out] none \retval none */ void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen) { /* clear USART_CTL1 STB bits */ - USART_CTL1(usart_periph) &= ~USART_CTL1_STB; + USART_CTL1(usart_periph) &= ~USART_CTL1_STB; /* configure USART stop bits */ USART_CTL1(usart_periph) |= stblen; } @@ -189,7 +223,8 @@ void usart_disable(uint32_t usart_periph) /*! \brief configure USART transmitter \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[in] rtconfig: enable or disable USART transmitter + \param[in] txconfig: enable or disable USART transmitter + only one parameter can be selected which is shown as below: \arg USART_TRANSMIT_ENABLE: enable USART transmission \arg USART_TRANSMIT_DISABLE: enable USART transmission \param[out] none @@ -198,7 +233,7 @@ void usart_disable(uint32_t usart_periph) void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig) { uint32_t ctl = 0U; - + ctl = USART_CTL0(usart_periph); ctl &= ~USART_CTL0_TEN; ctl |= txconfig; @@ -209,7 +244,8 @@ void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig) /*! \brief configure USART receiver \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[in] rtconfig: enable or disable USART receiver + \param[in] rxconfig: enable or disable USART receiver + only one parameter can be selected which is shown as below: \arg USART_RECEIVE_ENABLE: enable USART reception \arg USART_RECEIVE_DISABLE: disable USART reception \param[out] none @@ -218,7 +254,7 @@ void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig) void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig) { uint32_t ctl = 0U; - + ctl = USART_CTL0(usart_periph); ctl &= ~USART_CTL0_REN; ctl |= rxconfig; @@ -230,6 +266,7 @@ void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig) \brief data is transmitted/received with the LSB/MSB first \param[in] usart_periph: USARTx(x=0,1,2,5) \param[in] msbf: LSB/MSB + only one parameter can be selected which is shown as below: \arg USART_MSBF_LSB: LSB first \arg USART_MSBF_MSB: MSB first \param[out] none @@ -237,14 +274,20 @@ void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig) */ void usart_data_first_config(uint32_t usart_periph, uint32_t msbf) { - USART_CTL3(usart_periph) &= ~(USART_CTL3_MSBF); - USART_CTL3(usart_periph) |= msbf; + uint32_t ctl = 0U; + + ctl = USART_CTL3(usart_periph); + ctl &= ~(USART_CTL3_MSBF); + ctl |= msbf; + /* configure data transmitted/received mode */ + USART_CTL3(usart_periph) = ctl; } /*! \brief configure USART inversion \param[in] usart_periph: USARTx(x=0,1,2,5) \param[in] invertpara: refer to enum USART_INVERT_CONFIG + only one parameter can be selected which is shown as below: \arg USART_DINV_ENABLE: data bit level inversion \arg USART_DINV_DISABLE: data bit level not inversion \arg USART_TXPIN_ENABLE: TX pin level inversion @@ -256,7 +299,7 @@ void usart_data_first_config(uint32_t usart_periph, uint32_t msbf) */ void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara) { - /* inverted or not the specified siginal */ + /* inverted or not the specified siginal */ switch(invertpara){ case USART_DINV_ENABLE: USART_CTL3(usart_periph) |= USART_CTL3_DINV; @@ -282,9 +325,10 @@ void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara) } /*! - \brief configure the USART oversample mode + \brief configure the USART oversample mode \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[in] oversamp: oversample value + only one parameter can be selected which is shown as below: \arg USART_OVSMOD_8: 8 bits \arg USART_OVSMOD_16: 16 bits \param[out] none @@ -301,6 +345,7 @@ void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp) \brief configure sample bit method \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[in] obsm: sample bit + only one parameter can be selected which is shown as below: \arg USART_OSB_1bit: 1 bit \arg USART_OSB_3bit: 3 bits \param[out] none @@ -308,7 +353,7 @@ void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp) */ void usart_sample_bit_config(uint32_t usart_periph, uint32_t obsm) { - USART_CTL2(usart_periph) &= ~(USART_CTL2_OSB); + USART_CTL2(usart_periph) &= ~(USART_CTL2_OSB); USART_CTL2(usart_periph) |= obsm; } @@ -350,7 +395,7 @@ void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rti /*! \brief USART transmit data function \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[in] data: data of transmission + \param[in] data: data of transmission \param[out] none \retval none */ @@ -367,7 +412,7 @@ void usart_data_transmit(uint32_t usart_periph, uint32_t data) */ uint16_t usart_data_receive(uint32_t usart_periph) { - return (uint16_t)(USART_DATA(usart_periph) & (uint16_t)USART_DATA_DATA); + return (uint16_t)(GET_BITS(USART_DATA(usart_periph), 0U, 8U)); } /*! @@ -384,7 +429,7 @@ void usart_address_config(uint32_t usart_periph, uint8_t addr) } /*! - \brief receiver in mute mode + \brief enable mute mode \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[out] none \retval none @@ -395,7 +440,7 @@ void usart_mute_mode_enable(uint32_t usart_periph) } /*! - \brief receiver in active mode + \brief disable mute mode \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[out] none \retval none @@ -409,6 +454,7 @@ void usart_mute_mode_disable(uint32_t usart_periph) \brief configure wakeup method in mute mode \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[in] wmehtod: two method be used to enter or exit the mute mode + only one parameter can be selected which is shown as below: \arg USART_WM_IDLE: idle line \arg USART_WM_ADDR: address mask \param[out] none @@ -427,7 +473,7 @@ void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmehtod) \retval none */ void usart_lin_mode_enable(uint32_t usart_periph) -{ +{ USART_CTL1(usart_periph) |= USART_CTL1_LMEN; } @@ -438,7 +484,7 @@ void usart_lin_mode_enable(uint32_t usart_periph) \retval none */ void usart_lin_mode_disable(uint32_t usart_periph) -{ +{ USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN); } @@ -446,12 +492,13 @@ void usart_lin_mode_disable(uint32_t usart_periph) \brief configure lin break frame length \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[in] lblen: lin break frame length + only one parameter can be selected which is shown as below: \arg USART_LBLEN_10B: 10 bits \arg USART_LBLEN_11B: 11 bits \param[out] none \retval none */ -void usart_lin_break_dection_length_config(uint32_t usart_periph, uint32_t lblen) +void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen) { USART_CTL1(usart_periph) &= ~(USART_CTL1_LBLEN); USART_CTL1(usart_periph) |= (USART_CTL1_LBLEN & lblen); @@ -475,7 +522,7 @@ void usart_send_break(uint32_t usart_periph) \retval none */ void usart_halfduplex_enable(uint32_t usart_periph) -{ +{ USART_CTL2(usart_periph) |= USART_CTL2_HDEN; } @@ -486,7 +533,7 @@ void usart_halfduplex_enable(uint32_t usart_periph) \retval none */ void usart_halfduplex_disable(uint32_t usart_periph) -{ +{ USART_CTL2(usart_periph) &= ~(USART_CTL2_HDEN); } @@ -516,13 +563,16 @@ void usart_synchronous_clock_disable(uint32_t usart_periph) \brief configure USART synchronous mode parameters \param[in] usart_periph: USARTx(x=0,1,2,5) \param[in] clen: CK length - \arg USART_CLEN_NONE: there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame + only one parameter can be selected which is shown as below: + \arg USART_CLEN_NONE: there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame \arg USART_CLEN_EN: there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame \param[in] cph: clock phase - \arg USART_CPH_1CK: first clock transition is the first data capture edge + only one parameter can be selected which is shown as below: + \arg USART_CPH_1CK: first clock transition is the first data capture edge \arg USART_CPH_2CK: second clock transition is the first data capture edge - \param[in] cpl: clock polarity - \arg USART_CPL_LOW: steady low value on CK pin + \param[in] cpl: clock polarity + only one parameter can be selected which is shown as below: + \arg USART_CPL_LOW: steady low value on CK pin \arg USART_CPL_HIGH: steady high value on CK pin \param[out] none \retval none @@ -530,26 +580,27 @@ void usart_synchronous_clock_disable(uint32_t usart_periph) void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl) { uint32_t ctl = 0U; - + /* read USART_CTL1 register */ ctl = USART_CTL1(usart_periph); + ctl &= ~(USART_CTL1_CLEN | USART_CTL1_CPH | USART_CTL1_CPL); /* set CK length, CK phase, CK polarity */ ctl |= (USART_CTL1_CLEN & clen) | (USART_CTL1_CPH & cph) | (USART_CTL1_CPL & cpl); - USART_CTL1(usart_periph) |= ctl; + USART_CTL1(usart_periph) = ctl; } /*! \brief configure guard time value in smartcard mode \param[in] usart_periph: USARTx(x=0,1,2,5) - \param[in] gaut: guard time value + \param[in] guat: guard time value, 0-0xFF \param[out] none \retval none */ -void usart_guard_time_config(uint32_t usart_periph,uint32_t gaut) +void usart_guard_time_config(uint32_t usart_periph,uint32_t guat) { USART_GP(usart_periph) &= ~(USART_GP_GUAT); - USART_GP(usart_periph) |= (USART_GP_GUAT & ((gaut)<<8)); + USART_GP(usart_periph) |= (USART_GP_GUAT & ((guat)<irqn); /* disable interrupt */ - usart_interrupt_disable(uart->uart_periph, USART_INTEN_RBNEIE); + usart_interrupt_disable(uart->uart_periph, USART_INT_RBNE); break; case RT_DEVICE_CTRL_SET_INT: /* enable rx irq */ NVIC_EnableIRQ(uart->irqn); /* enable interrupt */ - usart_interrupt_enable(uart->uart_periph, USART_INTEN_RBNEIE); + usart_interrupt_enable(uart->uart_periph, USART_INT_RBNE); break; } @@ -430,7 +430,7 @@ static void uart_isr(struct rt_serial_device *serial) RT_ASSERT(uart != RT_NULL); /* UART in mode Receiver -------------------------------------------------*/ - if ((usart_interrupt_flag_get(uart->uart_periph, USART_INT_RBNEIE) != RESET) && + if ((usart_interrupt_flag_get(uart->uart_periph, USART_INT_FLAG_RBNE) != RESET) && (usart_flag_get(uart->uart_periph, USART_FLAG_RBNE) != RESET)) { rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); diff --git a/bsp/gd32450z-eval/rtconfig.py b/bsp/gd32450z-eval/rtconfig.py index f137cf5a65..1f01ffe88b 100644 --- a/bsp/gd32450z-eval/rtconfig.py +++ b/bsp/gd32450z-eval/rtconfig.py @@ -38,7 +38,7 @@ if PLATFORM == 'gcc': OBJDUMP = PREFIX + 'objdump' OBJCPY = PREFIX + 'objcopy' - DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -DGD32F450' CFLAGS = DEVICE + ' -Dgcc' # -D' + PART_TYPE AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-gd32.map,-cref,-u,Reset_Handler -T gd32_rom.ld' diff --git a/bsp/imxrt/imxrt1064-nxp-evk/board/Kconfig b/bsp/imxrt/imxrt1064-nxp-evk/board/Kconfig index 5c660b91c7..cd35ef35a3 100644 --- a/bsp/imxrt/imxrt1064-nxp-evk/board/Kconfig +++ b/bsp/imxrt/imxrt1064-nxp-evk/board/Kconfig @@ -32,6 +32,81 @@ menu "On-chip Peripheral Drivers" config BSP_USING_LPUART1 bool "Enable LPUART1" default y + config BSP_USING_LPUART2 + bool "Enable LPUART2" + default n + config BSP_USING_LPUART3 + bool "Enable LPUART3" + default n + config BSP_USING_LPUART4 + bool "Enable LPUART4" + default n + config BSP_USING_LPUART5 + bool "Enable LPUART5" + default n + config BSP_USING_LPUART6 + bool "Enable LPUART6" + default n + config BSP_USING_LPUART7 + bool "Enable LPUART7" + default n + config BSP_USING_LPUART8 + bool "Enable LPUART8" + default n + endif + + menuconfig BSP_USING_I2C + bool "Enable I2C" + select RT_USING_I2C + default n + if BSP_USING_I2C + config BSP_USING_I2C1 + bool "Enable LPI2C1" + default n + config BSP_USING_I2C3 + bool "Enable LPI2C3" + default n + config BSP_USING_I2C4 + bool "Enable LPI2C4" + default n + endif + + menuconfig BSP_USING_LCD + bool "Enable LCD" + default n + if BSP_USING_LCD + config LCD_WIDTH + int "width" + default 480 + + config LCD_HEIGHT + int "height" + default 272 + + config LCD_HFP + int "HFP" + default 4 + config LCD_VFP + int "VFP" + default 4 + config LCD_HBP + int "HBP" + default 8 + config LCD_VBP + int "VBP" + default 2 + config LCD_HSW + int "HSW" + default 40 + config LCD_VSW + int "VSW" + default 10 + config LCD_BL_PIN + int "Backlight ctrl pin" + default 63 + config LCD_RST_PIN + int "Reset pin" + default 2 endif endmenu diff --git a/bsp/imxrt/imxrt1064-nxp-evk/board/board.c b/bsp/imxrt/imxrt1064-nxp-evk/board/board.c index 603cd856c5..f4c0b7c05f 100644 --- a/bsp/imxrt/imxrt1064-nxp-evk/board/board.c +++ b/bsp/imxrt/imxrt1064-nxp-evk/board/board.c @@ -253,6 +253,411 @@ void imxrt_uart_pins_init(void) } #endif /* BSP_USING_LPUART */ +#ifdef BSP_USING_I2C +static void imxrt_i2c_pins_init(void) +{ +#ifdef BSP_USING_I2C1 + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, /* GPIO_AD_B1_00 is configured as LPI2C1_SCL */ + 1U); /* Software Input On Field: Force input path of pad GPIO_AD_B1_00 */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, /* GPIO_AD_B1_01 is configured as LPI2C1_SDA */ + 1U); /* Software Input On Field: Force input path of pad GPIO_AD_B1_01 */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, /* GPIO_AD_B1_00 PAD functional properties : */ + 0xD8B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Enabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 22K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, /* GPIO_AD_B1_01 PAD functional properties : */ + 0xD8B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Enabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 22K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ +#endif + +#ifdef BSP_USING_I2C3 + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL, /* GPIO_AD_B1_00 is configured as LPI2C1_SCL */ + 1U); /* Software Input On Field: Force input path of pad GPIO_AD_B1_00 */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA, /* GPIO_AD_B1_01 is configured as LPI2C1_SDA */ + 1U); /* Software Input On Field: Force input path of pad GPIO_AD_B1_01 */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL, /* GPIO_AD_B1_00 PAD functional properties : */ + 0xD8B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Enabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 22K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA, /* GPIO_AD_B1_01 PAD functional properties : */ + 0xD8B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Enabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 22K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ +#endif + +#ifdef BSP_USING_I2C4 + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL, /* GPIO_AD_B1_00 is configured as LPI2C1_SCL */ + 1U); /* Software Input On Field: Force input path of pad GPIO_AD_B1_00 */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA, /* GPIO_AD_B1_01 is configured as LPI2C1_SDA */ + 1U); /* Software Input On Field: Force input path of pad GPIO_AD_B1_01 */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL, /* GPIO_AD_B1_00 PAD functional properties : */ + 0xD8B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Enabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 22K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA, /* GPIO_AD_B1_01 PAD functional properties : */ + 0xD8B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Enabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 22K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ +#endif +} +#endif /* BSP_USING_I2C */ + +#ifdef BSP_USING_LCD +static void imxrt_lcd_pins_init(void) +{ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_02_GPIO1_IO02, /* GPIO_AD_B0_02 is configured as GPIO1_IO02 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_15_GPIO2_IO31, /* GPIO_B1_15 is configured as GPIO2_IO31 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B0_00_LCD_CLK, /* GPIO_B0_00 is configured as LCD_CLK */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B0_01_LCD_ENABLE, /* GPIO_B0_01 is configured as LCD_ENABLE */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B0_02_LCD_HSYNC, /* GPIO_B0_02 is configured as LCD_HSYNC */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B0_03_LCD_VSYNC, /* GPIO_B0_03 is configured as LCD_VSYNC */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B0_04_LCD_DATA00, /* GPIO_B0_04 is configured as LCD_DATA00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B0_05_LCD_DATA01, /* GPIO_B0_05 is configured as LCD_DATA01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B0_06_LCD_DATA02, /* GPIO_B0_06 is configured as LCD_DATA02 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B0_07_LCD_DATA03, /* GPIO_B0_07 is configured as LCD_DATA03 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B0_08_LCD_DATA04, /* GPIO_B0_08 is configured as LCD_DATA04 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B0_09_LCD_DATA05, /* GPIO_B0_09 is configured as LCD_DATA05 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B0_10_LCD_DATA06, /* GPIO_B0_10 is configured as LCD_DATA06 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B0_11_LCD_DATA07, /* GPIO_B0_11 is configured as LCD_DATA07 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B0_12_LCD_DATA08, /* GPIO_B0_12 is configured as LCD_DATA08 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B0_13_LCD_DATA09, /* GPIO_B0_13 is configured as LCD_DATA09 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B0_14_LCD_DATA10, /* GPIO_B0_14 is configured as LCD_DATA10 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B0_15_LCD_DATA11, /* GPIO_B0_15 is configured as LCD_DATA11 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_00_LCD_DATA12, /* GPIO_B1_00 is configured as LCD_DATA12 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_01_LCD_DATA13, /* GPIO_B1_01 is configured as LCD_DATA13 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_02_LCD_DATA14, /* GPIO_B1_02 is configured as LCD_DATA14 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_03_LCD_DATA15, /* GPIO_B1_03 is configured as LCD_DATA15 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */x + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_02_GPIO1_IO02, /* GPIO_AD_B0_02 PAD functional properties : */ + 0x10B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_15_GPIO2_IO31, /* GPIO_B1_15 PAD functional properties : */ + 0x10B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */ + 0x10B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */ + 0x10B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B0_00_LCD_CLK, /* GPIO_B0_00 PAD functional properties : */ + 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B0_01_LCD_ENABLE, /* GPIO_B0_01 PAD functional properties : */ + 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B0_02_LCD_HSYNC, /* GPIO_B0_02 PAD functional properties : */ + 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B0_03_LCD_VSYNC, /* GPIO_B0_03 PAD functional properties : */ + 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B0_04_LCD_DATA00, /* GPIO_B0_04 PAD functional properties : */ + 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B0_05_LCD_DATA01, /* GPIO_B0_05 PAD functional properties : */ + 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B0_06_LCD_DATA02, /* GPIO_B0_06 PAD functional properties : */ + 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B0_07_LCD_DATA03, /* GPIO_B0_07 PAD functional properties : */ + 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B0_08_LCD_DATA04, /* GPIO_B0_08 PAD functional properties : */ + 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B0_09_LCD_DATA05, /* GPIO_B0_09 PAD functional properties : */ + 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B0_10_LCD_DATA06, /* GPIO_B0_10 PAD functional properties : */ + 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B0_11_LCD_DATA07, /* GPIO_B0_11 PAD functional properties : */ + 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B0_12_LCD_DATA08, /* GPIO_B0_12 PAD functional properties : */ + 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B0_13_LCD_DATA09, /* GPIO_B0_13 PAD functional properties : */ + 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B0_14_LCD_DATA10, /* GPIO_B0_14 PAD functional properties : */ + 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B0_15_LCD_DATA11, /* GPIO_B0_15 PAD functional properties : */ + 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_00_LCD_DATA12, /* GPIO_B1_00 PAD functional properties : */ + 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_01_LCD_DATA13, /* GPIO_B1_01 PAD functional properties : */ + 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_02_LCD_DATA14, /* GPIO_B1_02 PAD functional properties : */ + 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_03_LCD_DATA15, /* GPIO_B1_03 PAD functional properties : */ + 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Enabled */ +} + +#endif + #ifdef BSP_USING_ETH void imxrt_enet_pins_init(void) { @@ -468,6 +873,10 @@ void rt_hw_board_init() imxrt_uart_pins_init(); #endif +#ifdef BSP_USING_I2C + imxrt_i2c_pins_init(); +#endif + #ifdef BSP_USING_ETH imxrt_enet_pins_init(); #endif @@ -476,6 +885,10 @@ void rt_hw_board_init() imxrt_phy_pins_init(); #endif +#ifdef BSP_USING_LCD + imxrt_lcd_pins_init(); +#endif + #ifdef BSP_USING_DMA imxrt_dma_init(); #endif diff --git a/bsp/imxrt/libraries/drivers/drv_i2c.c b/bsp/imxrt/libraries/drivers/drv_i2c.c index 117b29f3d3..1920c0d502 100644 --- a/bsp/imxrt/libraries/drivers/drv_i2c.c +++ b/bsp/imxrt/libraries/drivers/drv_i2c.c @@ -221,7 +221,7 @@ static rt_size_t imxrt_i2c_mst_xfer(struct rt_i2c_bus_device *bus, { if (imxrt_i2c->msg[i].flags & RT_I2C_RD) { - if (LPI2C_MasterStart(imxrt_i2c->I2C, imxrt_i2c->msg[i].addr, kLPI2C_Write) != kStatus_Success) + if (LPI2C_MasterStart(imxrt_i2c->I2C, imxrt_i2c->msg[i].addr, kLPI2C_Read) != kStatus_Success) { i = 0; break; @@ -231,12 +231,6 @@ static rt_size_t imxrt_i2c_mst_xfer(struct rt_i2c_bus_device *bus, { } - if (LPI2C_MasterRepeatedStart(imxrt_i2c->I2C, imxrt_i2c->msg[i].addr, kLPI2C_Read) != kStatus_Success) - { - i = 0; - break; - } - if (LPI2C_MasterReceive(imxrt_i2c->I2C, imxrt_i2c->msg[i].buf, imxrt_i2c->msg[i].len) != kStatus_Success) { i = 0; diff --git a/bsp/juicevm/SConscript b/bsp/juicevm/SConscript old mode 100755 new mode 100644 diff --git a/bsp/k210/driver/board.c b/bsp/k210/driver/board.c index 3343da0fb7..d9c9279dca 100644 --- a/bsp/k210/driver/board.c +++ b/bsp/k210/driver/board.c @@ -1,10 +1,11 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes + *2021-06-10 xiaoyu implement rt_hw_us_delay() */ #include @@ -117,3 +118,19 @@ void rt_hw_cpu_reset(void) } MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reset machine); + +/** + * This function will delay for some us. + * + * @param us the delay time of us + */ +void rt_hw_us_delay(rt_uint32_t usec) +{ + rt_uint32_t cycle = read_cycle(); + rt_uint32_t nop_all = usec * sysctl_clock_get_freq(SYSCTL_CLOCK_CPU) / 1000000UL; + while (1) + { + if(read_cycle() - cycle >= nop_all) + break; + } +} diff --git a/bsp/k210/driver/drv_gpio.c b/bsp/k210/driver/drv_gpio.c index a6eaaf197d..05ca8fd934 100644 --- a/bsp/k210/driver/drv_gpio.c +++ b/bsp/k210/driver/drv_gpio.c @@ -180,10 +180,10 @@ static rt_err_t drv_pin_attach_irq(struct rt_device *device, rt_int32_t pin, switch (mode) { case PIN_IRQ_MODE_RISING: - irq_table[pin_channel].edge = GPIO_PE_FALLING; + irq_table[pin_channel].edge = GPIO_PE_RISING; break; case PIN_IRQ_MODE_FALLING: - irq_table[pin_channel].edge = GPIO_PE_RISING; + irq_table[pin_channel].edge = GPIO_PE_FALLING; break; case PIN_IRQ_MODE_RISING_FALLING: irq_table[pin_channel].edge = GPIO_PE_BOTH; diff --git a/bsp/lm3s9b9x/rtconfig.h b/bsp/lm3s9b9x/rtconfig.h index b961c26d6f..741899fb34 100644 --- a/bsp/lm3s9b9x/rtconfig.h +++ b/bsp/lm3s9b9x/rtconfig.h @@ -89,6 +89,7 @@ /* SECTION: lwip, a lighwight TCP/IP protocol stack */ /* Using lighweight TCP/IP protocol stack*/ #define RT_USING_LWIP +#define RT_USING_LWIP203 /* Trace LwIP protocol*/ /* #define RT_LWIP_DEBUG */ diff --git a/bsp/lpc176x/rtconfig.h b/bsp/lpc176x/rtconfig.h index 5096b2f71d..c15fc48ee5 100644 --- a/bsp/lpc176x/rtconfig.h +++ b/bsp/lpc176x/rtconfig.h @@ -157,6 +157,7 @@ //
#define RT_USING_LWIP +#define RT_USING_LWIP203 // #define RT_LWIP_ICMP // diff --git a/bsp/mini2440/.config b/bsp/mini2440/.config index 1e1372162c..3acbaf11a0 100644 --- a/bsp/mini2440/.config +++ b/bsp/mini2440/.config @@ -24,6 +24,12 @@ CONFIG_IDLE_THREAD_STACK_SIZE=256 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set CONFIG_RT_DEBUG=y # CONFIG_RT_DEBUG_COLOR is not set # CONFIG_RT_DEBUG_INIT_CONFIG is not set @@ -56,6 +62,7 @@ CONFIG_RT_USING_MEMHEAP=y CONFIG_RT_USING_SMALL_MEM=y # CONFIG_RT_USING_SLAB is not set # CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set # CONFIG_RT_USING_MEMTRACE is not set CONFIG_RT_USING_HEAP=y @@ -68,7 +75,7 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart" -CONFIG_RT_VER_NUM=0x40003 +CONFIG_RT_VER_NUM=0x40004 CONFIG_ARCH_ARM=y # CONFIG_RT_USING_CPU_FFS is not set CONFIG_ARCH_ARM_ARM9=y @@ -127,6 +134,11 @@ CONFIG_RT_DFS_ELM_WORD_ACCESS=y # CONFIG_RT_DFS_ELM_USE_LFN_2 is not set CONFIG_RT_DFS_ELM_USE_LFN_3=y CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y +# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set +CONFIG_RT_DFS_ELM_LFN_UNICODE=0 CONFIG_RT_DFS_ELM_MAX_LFN=255 CONFIG_RT_DFS_ELM_DRIVES=2 CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 @@ -135,8 +147,6 @@ CONFIG_RT_DFS_ELM_REENTRANT=y CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DFS_ROMFS is not set CONFIG_RT_USING_DFS_RAMFS=y -# CONFIG_RT_USING_DFS_UFFS is not set -# CONFIG_RT_USING_DFS_JFFS2 is not set # CONFIG_RT_USING_DFS_NFS is not set # @@ -148,14 +158,18 @@ CONFIG_RT_USING_SYSTEM_WORKQUEUE=y CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set CONFIG_RT_SERIAL_USING_DMA=y CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set # CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set @@ -193,9 +207,11 @@ CONFIG_PTHREAD_NUM_MAX=8 CONFIG_RT_USING_POSIX=y CONFIG_RT_USING_POSIX_MMAP=y CONFIG_RT_USING_POSIX_TERMIOS=y +# CONFIG_RT_USING_POSIX_GETLINE is not set CONFIG_RT_USING_POSIX_AIO=y CONFIG_RT_USING_MODULE=y CONFIG_RT_USING_CUSTOM_DLMODULE=y +CONFIG_RT_LIBC_FIXED_TIMEZONE=8 # # Network @@ -205,6 +221,7 @@ CONFIG_RT_USING_CUSTOM_DLMODULE=y # Socket abstraction layer # CONFIG_RT_USING_SAL=y +CONFIG_SAL_INTERNET_CHECK=y # # protocol stack implement @@ -231,8 +248,10 @@ CONFIG_NETDEV_IPV6=0 CONFIG_RT_USING_LWIP=y # CONFIG_RT_USING_LWIP141 is not set # CONFIG_RT_USING_LWIP202 is not set -CONFIG_RT_USING_LWIP210=y +CONFIG_RT_USING_LWIP203=y +# CONFIG_RT_USING_LWIP212 is not set # CONFIG_RT_USING_LWIP_IPV6 is not set +CONFIG_RT_LWIP_MEM_ALIGNMENT=4 CONFIG_RT_LWIP_IGMP=y CONFIG_RT_LWIP_ICMP=y # CONFIG_RT_LWIP_SNMP is not set @@ -274,6 +293,7 @@ CONFIG_SO_REUSE=1 CONFIG_LWIP_SO_RCVTIMEO=1 CONFIG_LWIP_SO_SNDTIMEO=1 CONFIG_LWIP_SO_RCVBUF=1 +CONFIG_LWIP_SO_LINGER=0 CONFIG_RT_LWIP_NETIF_LOOPBACK=y CONFIG_LWIP_NETIF_LOOPBACK=1 CONFIG_RT_LWIP_STATS=y @@ -300,8 +320,14 @@ CONFIG_YMODEM_USING_CRC_TABLE=y CONFIG_YMODEM_USING_FILE_TRANSFER=y # CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_RT_LINK is not set # CONFIG_RT_USING_LWP is not set +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + # # RT-Thread online packages # @@ -309,12 +335,15 @@ CONFIG_YMODEM_USING_FILE_TRANSFER=y # # IoT - internet of things # +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set # CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set # CONFIG_PKG_USING_MYMQTT is not set # CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set @@ -341,6 +370,7 @@ CONFIG_YMODEM_USING_FILE_TRANSFER=y # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set # CONFIG_PKG_USING_PPP_DEVICE is not set # CONFIG_PKG_USING_AT_DEVICE is not set # CONFIG_PKG_USING_ATSRV_SOCKET is not set @@ -353,7 +383,7 @@ CONFIG_YMODEM_USING_FILE_TRANSFER=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set # CONFIG_PKG_USING_JIOT-C-SDK is not set # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set # CONFIG_PKG_USING_JOYLINK is not set @@ -365,8 +395,6 @@ CONFIG_YMODEM_USING_FILE_TRANSFER=y # CONFIG_PKG_USING_LIBRWS is not set # CONFIG_PKG_USING_TCPSERVER is not set # CONFIG_PKG_USING_PROTOBUF_C is not set -# CONFIG_PKG_USING_ONNX_PARSER is not set -# CONFIG_PKG_USING_ONNX_BACKEND is not set # CONFIG_PKG_USING_DLT645 is not set # CONFIG_PKG_USING_QXWZ is not set # CONFIG_PKG_USING_SMTP_CLIENT is not set @@ -375,6 +403,18 @@ CONFIG_YMODEM_USING_FILE_TRANSFER=y # CONFIG_PKG_USING_CAPNP is not set # CONFIG_PKG_USING_RT_CJSON_TOOLS is not set # CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set # # security packages @@ -383,6 +423,7 @@ CONFIG_YMODEM_USING_FILE_TRANSFER=y # CONFIG_PKG_USING_libsodium is not set # CONFIG_PKG_USING_TINYCRYPT is not set # CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set # # language packages @@ -399,6 +440,11 @@ CONFIG_YMODEM_USING_FILE_TRANSFER=y # CONFIG_PKG_USING_STEMWIN is not set # CONFIG_PKG_USING_WAVPLAYER is not set # CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set # # tools packages @@ -410,13 +456,36 @@ CONFIG_YMODEM_USING_FILE_TRANSFER=y # CONFIG_PKG_USING_RDB is not set # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set # CONFIG_PKG_USING_ADBD is not set # CONFIG_PKG_USING_COREMARK is not set # CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set # CONFIG_PKG_USING_NR_MICRO_SHELL is not set # CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set # CONFIG_PKG_USING_LUNAR_CALENDAR is not set # CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set # # system packages @@ -425,21 +494,47 @@ CONFIG_YMODEM_USING_FILE_TRANSFER=y # CONFIG_PKG_USING_PERSIMMON is not set # CONFIG_PKG_USING_CAIRO is not set # CONFIG_PKG_USING_PIXMAN is not set -# CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set # CONFIG_PKG_USING_CMSIS is not set # CONFIG_PKG_USING_DFS_YAFFS is not set # CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_THREAD_POOL is not set # CONFIG_PKG_USING_ROBOTS is not set # CONFIG_PKG_USING_EV is not set # CONFIG_PKG_USING_SYSWATCH is not set # CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set # CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set # # peripheral libraries and drivers @@ -448,6 +543,7 @@ CONFIG_YMODEM_USING_FILE_TRANSFER=y # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set # CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_U8G2 is not set @@ -458,6 +554,8 @@ CONFIG_YMODEM_USING_FILE_TRANSFER=y # CONFIG_PKG_USING_LEDBLINK is not set # CONFIG_PKG_USING_LITTLED is not set # CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set # CONFIG_PKG_USING_WM_LIBRARIES is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set # CONFIG_PKG_USING_INFRARED is not set @@ -475,12 +573,49 @@ CONFIG_YMODEM_USING_FILE_TRANSFER=y # CONFIG_PKG_USING_RPLIDAR is not set # CONFIG_PKG_USING_AS608 is not set # CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set # CONFIG_PKG_USING_EMBARC_BSP is not set # CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set # CONFIG_PKG_USING_MAX7219 is not set # CONFIG_PKG_USING_BEEP is not set # CONFIG_PKG_USING_EASYBLINK is not set # CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set # # miscellaneous packages @@ -490,10 +625,12 @@ CONFIG_YMODEM_USING_FILE_TRANSFER=y # CONFIG_PKG_USING_FASTLZ is not set # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set # CONFIG_PKG_USING_MULTIBUTTON is not set # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set # CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set # CONFIG_PKG_USING_KENDRYTE_DEMO is not set @@ -510,10 +647,22 @@ CONFIG_YMODEM_USING_FILE_TRANSFER=y # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set # CONFIG_PKG_USING_HELLO is not set # CONFIG_PKG_USING_VI is not set -# CONFIG_PKG_USING_NNOM is not set -# CONFIG_PKG_USING_LIBANN is not set -# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_KI is not set # CONFIG_PKG_USING_ARMv7M_DWT is not set # CONFIG_PKG_USING_VT100 is not set -# CONFIG_PKG_USING_ULAPACK is not set # CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set diff --git a/bsp/mini2440/project.uvproj b/bsp/mini2440/project.uvproj index be1302e35a..860d5fe806 100644 --- a/bsp/mini2440/project.uvproj +++ b/bsp/mini2440/project.uvproj @@ -341,9 +341,9 @@ 0 --diag_suppress=870 - RT_USING_ARM_LIBC + RT_USING_ARM_LIBC, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND - .;..\..\include;applications;.;drivers;..\..\libcpu\arm\common;..\..\libcpu\arm\s3c24x0;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;..\..\components\libc\compilers\common;..\..\components\libc\pthreads;..\..\components\libc\time;..\..\components\net\lwip-2.0.2\src;..\..\components\net\lwip-2.0.2\src\include;..\..\components\net\lwip-2.0.2\src\include\ipv4;..\..\components\net\lwip-2.0.2\src\arch\include;..\..\components\net\lwip-2.0.2\src\include\netif;..\..\components\net\lwip-2.0.2\src\include\posix + applications;.;..\..\components\cplusplus;..\..\libcpu\arm\common;..\..\libcpu\arm\s3c24x0;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;drivers;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\dfs\filesystems\ramfs;..\..\components\finsh;.;..\..\include;..\..\components\libc\aio;..\..\components\libc\compilers\armlibc;..\..\components\libc\compilers\common;..\..\components\libc\compilers\common\none-gcc;..\..\components\libc\mmap;..\..\components\libc\pthreads;..\..\components\libc\termios;..\..\components\net\lwip-2.0.3\src;..\..\components\net\lwip-2.0.3\src\include;..\..\components\net\lwip-2.0.3\src\include\ipv4;..\..\components\net\lwip-2.0.3\src\arch\include;..\..\components\net\lwip-2.0.3\src\include\netif;..\..\components\net\netdev\include;..\..\components\net\sal_socket\include;..\..\components\net\sal_socket\include\socket;..\..\components\net\sal_socket\impl;..\..\components\net\sal_socket\include\dfs_net;..\..\components\net\sal_socket\include\dfs_net\sys_select;..\..\components\net\sal_socket\include\socket\sys_socket;..\..\examples\utest\testcases\kernel;..\..\components\utilities\ymodem @@ -380,178 +380,63 @@ - - Kernel - - - clock.c - 1 - ..\..\src\clock.c - - - - - components.c - 1 - ..\..\src\components.c - - - - - cpu.c - 1 - ..\..\src\cpu.c - - - - - device.c - 1 - ..\..\src\device.c - - - - - idle.c - 1 - ..\..\src\idle.c - - - - - ipc.c - 1 - ..\..\src\ipc.c - - - - - irq.c - 1 - ..\..\src\irq.c - - - - - kservice.c - 1 - ..\..\src\kservice.c - - - - - mem.c - 1 - ..\..\src\mem.c - - - - - mempool.c - 1 - ..\..\src\mempool.c - - - - - object.c - 1 - ..\..\src\object.c - - - - - scheduler.c - 1 - ..\..\src\scheduler.c - - - - - signal.c - 1 - ..\..\src\signal.c - - - - - thread.c - 1 - ..\..\src\thread.c - - - - - timer.c - 1 - ..\..\src\timer.c - - - Applications - application.c + mnt.c 1 - applications\application.c + applications\mnt.c - startup.c + main.c 1 - applications\startup.c + applications\main.c - Drivers + CPlusPlus - board.c - 1 - drivers\board.c + cxx_Thread.cpp + 8 + ..\..\components\cplusplus\cxx_Thread.cpp - led.c - 1 - drivers\led.c + cxx_crt.cpp + 8 + ..\..\components\cplusplus\cxx_crt.cpp - console.c + crt_init.c 1 - drivers\console.c + ..\..\components\cplusplus\crt_init.c - sdcard.c - 1 - drivers\sdcard.c + cxx_Semaphore.cpp + 8 + ..\..\components\cplusplus\cxx_Semaphore.cpp - dm9000.c - 1 - drivers\dm9000.c + cxx_Mutex.cpp + 8 + ..\..\components\cplusplus\cxx_Mutex.cpp - cpu - - - backtrace.c - 1 - ..\..\libcpu\arm\common\backtrace.c - - + CPU div0.c @@ -568,16 +453,9 @@ - s3c24x0_cpu.c + backtrace.c 1 - ..\..\libcpu\arm\s3c24x0\cpu.c - - - - - interrupt.c - 1 - ..\..\libcpu\arm\s3c24x0\interrupt.c + ..\..\libcpu\arm\common\backtrace.c @@ -587,41 +465,6 @@ ..\..\libcpu\arm\s3c24x0\mmu.c - - - rtc.c - 1 - ..\..\libcpu\arm\s3c24x0\rtc.c - - - - - serial.c - 1 - ..\..\libcpu\arm\s3c24x0\serial.c - - - - - stack.c - 1 - ..\..\libcpu\arm\s3c24x0\stack.c - - - - - system_clock.c - 1 - ..\..\libcpu\arm\s3c24x0\system_clock.c - - - - - trap.c - 1 - ..\..\libcpu\arm\s3c24x0\trap.c - - context_rvds.S @@ -636,63 +479,46 @@ ..\..\libcpu\arm\s3c24x0\start_rvds.S - - - Filesystem - dfs.c + stack.c 1 - ..\..\components\dfs\src\dfs.c + ..\..\libcpu\arm\s3c24x0\stack.c - dfs_file.c + cpu.c 1 - ..\..\components\dfs\src\dfs_file.c + ..\..\libcpu\arm\s3c24x0\cpu.c - dfs_fs.c + system_clock.c 1 - ..\..\components\dfs\src\dfs_fs.c + ..\..\libcpu\arm\s3c24x0\system_clock.c - dfs_posix.c + interrupt.c 1 - ..\..\components\dfs\src\dfs_posix.c + ..\..\libcpu\arm\s3c24x0\interrupt.c - devfs.c + rtc.c 1 - ..\..\components\dfs\filesystems\devfs\devfs.c + ..\..\libcpu\arm\s3c24x0\rtc.c - dfs_elm.c + trap.c 1 - ..\..\components\dfs\filesystems\elmfat\dfs_elm.c - - - - - ff.c - 1 - ..\..\components\dfs\filesystems\elmfat\ff.c - - - - - cc936.c - 1 - ..\..\components\dfs\filesystems\elmfat\option\cc936.c + ..\..\libcpu\arm\s3c24x0\trap.c @@ -700,9 +526,51 @@ DeviceDrivers - completion.c + pin.c 1 - ..\..\components\drivers\src\completion.c + ..\..\components\drivers\misc\pin.c + + + + + mmc.c + 1 + ..\..\components\drivers\sdio\mmc.c + + + + + sd.c + 1 + ..\..\components\drivers\sdio\sd.c + + + + + block_dev.c + 1 + ..\..\components\drivers\sdio\block_dev.c + + + + + sdio.c + 1 + ..\..\components\drivers\sdio\sdio.c + + + + + mmcsd_core.c + 1 + ..\..\components\drivers\sdio\mmcsd_core.c + + + + + serial.c + 1 + ..\..\components\drivers\serial\serial.c @@ -714,23 +582,9 @@ - pipe.c + completion.c 1 - ..\..\components\drivers\src\pipe.c - - - - - ringblk_buf.c - 1 - ..\..\components\drivers\src\ringblk_buf.c - - - - - ringbuffer.c - 1 - ..\..\components\drivers\src\ringbuffer.c + ..\..\components\drivers\src\completion.c @@ -740,6 +594,27 @@ ..\..\components\drivers\src\waitqueue.c + + + ringblk_buf.c + 1 + ..\..\components\drivers\src\ringblk_buf.c + + + + + pipe.c + 1 + ..\..\components\drivers\src\pipe.c + + + + + ringbuffer.c + 1 + ..\..\components\drivers\src\ringbuffer.c + + workqueue.c @@ -748,50 +623,133 @@ + + Drivers + + + dm9000.c + 1 + drivers\dm9000.c + + + + + s3cmci.c + 1 + drivers\s3cmci.c + + + + + key.c + 1 + drivers\key.c + + + + + led.c + 1 + drivers\led.c + + + + + uart.c + 1 + drivers\uart.c + + + + + board.c + 1 + drivers\board.c + + + + + Filesystem + + + dfs_posix.c + 1 + ..\..\components\dfs\src\dfs_posix.c + + + + + dfs_file.c + 1 + ..\..\components\dfs\src\dfs_file.c + + + + + select.c + 1 + ..\..\components\dfs\src\select.c + + + + + dfs.c + 1 + ..\..\components\dfs\src\dfs.c + + + + + poll.c + 1 + ..\..\components\dfs\src\poll.c + + + + + dfs_fs.c + 1 + ..\..\components\dfs\src\dfs_fs.c + + + + + devfs.c + 1 + ..\..\components\dfs\filesystems\devfs\devfs.c + + + + + ff.c + 1 + ..\..\components\dfs\filesystems\elmfat\ff.c + + + + + ffunicode.c + 1 + ..\..\components\dfs\filesystems\elmfat\ffunicode.c + + + + + dfs_elm.c + 1 + ..\..\components\dfs\filesystems\elmfat\dfs_elm.c + + + + + dfs_ramfs.c + 1 + ..\..\components\dfs\filesystems\ramfs\dfs_ramfs.c + + + finsh - - - shell.c - 1 - ..\..\components\finsh\shell.c - - - - - cmd.c - 1 - ..\..\components\finsh\cmd.c - - - - - finsh_compiler.c - 1 - ..\..\components\finsh\finsh_compiler.c - - - - - finsh_error.c - 1 - ..\..\components\finsh\finsh_error.c - - - - - finsh_heap.c - 1 - ..\..\components\finsh\finsh_heap.c - - - - - finsh_init.c - 1 - ..\..\components\finsh\finsh_init.c - - finsh_node.c @@ -799,13 +757,6 @@ ..\..\components\finsh\finsh_node.c - - - finsh_ops.c - 1 - ..\..\components\finsh\finsh_ops.c - - finsh_parser.c @@ -815,9 +766,9 @@ - finsh_var.c + msh.c 1 - ..\..\components\finsh\finsh_var.c + ..\..\components\finsh\msh.c @@ -827,6 +778,62 @@ ..\..\components\finsh\finsh_vm.c + + + msh_file.c + 1 + ..\..\components\finsh\msh_file.c + + + + + shell.c + 1 + ..\..\components\finsh\shell.c + + + + + finsh_var.c + 1 + ..\..\components\finsh\finsh_var.c + + + + + finsh_compiler.c + 1 + ..\..\components\finsh\finsh_compiler.c + + + + + finsh_ops.c + 1 + ..\..\components\finsh\finsh_ops.c + + + + + finsh_heap.c + 1 + ..\..\components\finsh\finsh_heap.c + + + + + finsh_error.c + 1 + ..\..\components\finsh\finsh_error.c + + + + + cmd.c + 1 + ..\..\components\finsh\cmd.c + + finsh_token.c @@ -834,21 +841,129 @@ ..\..\components\finsh\finsh_token.c + + + finsh_init.c + 1 + ..\..\components\finsh\finsh_init.c + + + + + Kernel + + + mem.c + 1 + ..\..\src\mem.c + + + + + clock.c + 1 + ..\..\src\clock.c + + + + + scheduler.c + 1 + ..\..\src\scheduler.c + + + + + irq.c + 1 + ..\..\src\irq.c + + + + + device.c + 1 + ..\..\src\device.c + + + + + object.c + 1 + ..\..\src\object.c + + + + + thread.c + 1 + ..\..\src\thread.c + + + + + components.c + 1 + ..\..\src\components.c + + + + + kservice.c + 1 + ..\..\src\kservice.c + + + + + ipc.c + 1 + ..\..\src\ipc.c + + + + + memheap.c + 1 + ..\..\src\memheap.c + + + + + mempool.c + 1 + ..\..\src\mempool.c + + + + + timer.c + 1 + ..\..\src\timer.c + + + + + idle.c + 1 + ..\..\src\idle.c + + libc - libc.c + posix_aio.c 1 - ..\..\components\libc\compilers\armlibc\libc.c + ..\..\components\libc\aio\posix_aio.c - mem_std.c + libc.c 1 - ..\..\components\libc\compilers\armlibc\mem_std.c + ..\..\components\libc\compilers\armlibc\libc.c @@ -860,9 +975,44 @@ - stubs.c + syscalls.c 1 - ..\..\components\libc\compilers\armlibc\stubs.c + ..\..\components\libc\compilers\armlibc\syscalls.c + + + + + mem_std.c + 1 + ..\..\components\libc\compilers\armlibc\mem_std.c + + + + + libc_syms.c + 1 + ..\..\components\libc\compilers\armlibc\libc_syms.c + + + + + unistd.c + 1 + ..\..\components\libc\compilers\common\unistd.c + + + + + delay.c + 1 + ..\..\components\libc\compilers\common\delay.c + + + + + stdlib.c + 1 + ..\..\components\libc\compilers\common\stdlib.c @@ -872,49 +1022,11 @@ ..\..\components\libc\compilers\common\time.c - - - pthreads - mqueue.c + posix_mmap.c 1 - ..\..\components\libc\pthreads\mqueue.c - - - - - pthread.c - 1 - ..\..\components\libc\pthreads\pthread.c - - - - - pthread_attr.c - 1 - ..\..\components\libc\pthreads\pthread_attr.c - - - - - pthread_barrier.c - 1 - ..\..\components\libc\pthreads\pthread_barrier.c - - - - - pthread_cond.c - 1 - ..\..\components\libc\pthreads\pthread_cond.c - - - - - pthread_mutex.c - 1 - ..\..\components\libc\pthreads\pthread_mutex.c + ..\..\components\libc\mmap\posix_mmap.c @@ -924,6 +1036,13 @@ ..\..\components\libc\pthreads\pthread_rwlock.c + + + pthread_cond.c + 1 + ..\..\components\libc\pthreads\pthread_cond.c + + pthread_spin.c @@ -933,9 +1052,9 @@ - pthread_tls.c + pthread_attr.c 1 - ..\..\components\libc\pthreads\pthread_tls.c + ..\..\components\libc\pthreads\pthread_attr.c @@ -945,6 +1064,20 @@ ..\..\components\libc\pthreads\sched.c + + + pthread.c + 1 + ..\..\components\libc\pthreads\pthread.c + + + + + pthread_barrier.c + 1 + ..\..\components\libc\pthreads\pthread_barrier.c + + semaphore.c @@ -954,271 +1087,361 @@ - clock_time.c + pthread_tls.c 1 - ..\..\components\libc\time\clock_time.c + ..\..\components\libc\pthreads\pthread_tls.c - posix_sleep.c + mqueue.c 1 - ..\..\components\libc\time\posix_sleep.c + ..\..\components\libc\pthreads\mqueue.c + + + + + pthread_mutex.c + 1 + ..\..\components\libc\pthreads\pthread_mutex.c + + + + + posix_termios.c + 1 + ..\..\components\libc\termios\posix_termios.c lwIP - - - sys_arch.c - 1 - ..\..\components\net\lwip-2.0.2\src\arch\sys_arch.c - - - - - api_lib.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\api_lib.c - - - - - api_msg.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\api_msg.c - - - - - err.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\err.c - - - - - netbuf.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\netbuf.c - - netdb.c 1 - ..\..\components\net\lwip-2.0.2\src\api\netdb.c - - - - - netifapi.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\netifapi.c - - - - - sockets.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\sockets.c - - - - - tcpip.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\tcpip.c - - - - - def.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\def.c - - - - - dns.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\dns.c - - - - - inet_chksum.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\inet_chksum.c - - - - - init.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\init.c + ..\..\components\net\lwip-2.0.3\src\api\netdb.c ip.c 1 - ..\..\components\net\lwip-2.0.2\src\core\ip.c - - - - - memp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\memp.c - - - - - netif.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\netif.c - - - - - pbuf.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\pbuf.c - - - - - raw.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\raw.c - - - - - stats.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\stats.c - - - - - sys.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\sys.c - - - - - tcp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\tcp.c - - - - - tcp_in.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\tcp_in.c - - - - - tcp_out.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\tcp_out.c - - - - - timeouts.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\timeouts.c - - - - - udp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\udp.c - - - - - ethernet.c - 1 - ..\..\components\net\lwip-2.0.2\src\netif\ethernet.c - - - - - ethernetif.c - 1 - ..\..\components\net\lwip-2.0.2\src\netif\ethernetif.c - - - - - lowpan6.c - 1 - ..\..\components\net\lwip-2.0.2\src\netif\lowpan6.c + ..\..\components\net\lwip-2.0.3\src\core\ip.c autoip.c 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\autoip.c + ..\..\components\net\lwip-2.0.3\src\core\ipv4\autoip.c - dhcp.c + ethernet.c 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\dhcp.c + ..\..\components\net\lwip-2.0.3\src\netif\ethernet.c - etharp.c + netif.c 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\etharp.c + ..\..\components\net\lwip-2.0.3\src\core\netif.c - icmp.c + sys.c 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\icmp.c + ..\..\components\net\lwip-2.0.3\src\core\sys.c - igmp.c + sockets.c 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\igmp.c + ..\..\components\net\lwip-2.0.3\src\api\sockets.c - ip4.c + netifapi.c 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4.c + ..\..\components\net\lwip-2.0.3\src\api\netifapi.c + + + + + tcpip.c + 1 + ..\..\components\net\lwip-2.0.3\src\api\tcpip.c ip4_addr.c 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_addr.c + ..\..\components\net\lwip-2.0.3\src\core\ipv4\ip4_addr.c + + + + + dhcp.c + 1 + ..\..\components\net\lwip-2.0.3\src\core\ipv4\dhcp.c + + + + + init.c + 1 + ..\..\components\net\lwip-2.0.3\src\core\init.c + + + + + ethernetif.c + 1 + ..\..\components\net\lwip-2.0.3\src\netif\ethernetif.c + + + + + etharp.c + 1 + ..\..\components\net\lwip-2.0.3\src\core\ipv4\etharp.c + + + + + memp.c + 1 + ..\..\components\net\lwip-2.0.3\src\core\memp.c + + + + + ip4.c + 1 + ..\..\components\net\lwip-2.0.3\src\core\ipv4\ip4.c + + + + + netbuf.c + 1 + ..\..\components\net\lwip-2.0.3\src\api\netbuf.c + + + + + raw.c + 1 + ..\..\components\net\lwip-2.0.3\src\core\raw.c ip4_frag.c 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_frag.c + ..\..\components\net\lwip-2.0.3\src\core\ipv4\ip4_frag.c + + + + + tcp_out.c + 1 + ..\..\components\net\lwip-2.0.3\src\core\tcp_out.c + + + + + lowpan6.c + 1 + ..\..\components\net\lwip-2.0.3\src\netif\lowpan6.c + + + + + icmp.c + 1 + ..\..\components\net\lwip-2.0.3\src\core\ipv4\icmp.c + + + + + api_lib.c + 1 + ..\..\components\net\lwip-2.0.3\src\api\api_lib.c + + + + + inet_chksum.c + 1 + ..\..\components\net\lwip-2.0.3\src\core\inet_chksum.c + + + + + stats.c + 1 + ..\..\components\net\lwip-2.0.3\src\core\stats.c + + + + + err.c + 1 + ..\..\components\net\lwip-2.0.3\src\api\err.c + + + + + tcp_in.c + 1 + ..\..\components\net\lwip-2.0.3\src\core\tcp_in.c + + + + + dns.c + 1 + ..\..\components\net\lwip-2.0.3\src\core\dns.c + + + + + sys_arch.c + 1 + ..\..\components\net\lwip-2.0.3\src\arch\sys_arch.c + + + + + timeouts.c + 1 + ..\..\components\net\lwip-2.0.3\src\core\timeouts.c + + + + + igmp.c + 1 + ..\..\components\net\lwip-2.0.3\src\core\ipv4\igmp.c + + + + + udp.c + 1 + ..\..\components\net\lwip-2.0.3\src\core\udp.c + + + + + pbuf.c + 1 + ..\..\components\net\lwip-2.0.3\src\core\pbuf.c + + + + + def.c + 1 + ..\..\components\net\lwip-2.0.3\src\core\def.c + + + + + api_msg.c + 1 + ..\..\components\net\lwip-2.0.3\src\api\api_msg.c + + + + + ping.c + 1 + ..\..\components\net\lwip-2.0.3\src\apps\ping\ping.c + + + + + tcp.c + 1 + ..\..\components\net\lwip-2.0.3\src\core\tcp.c + + + + + SAL + + + netdev.c + 1 + ..\..\components\net\netdev\src\netdev.c + + + + + netdev_ipaddr.c + 1 + ..\..\components\net\netdev\src\netdev_ipaddr.c + + + + + net_sockets.c + 1 + ..\..\components\net\sal_socket\socket\net_sockets.c + + + + + sal_socket.c + 1 + ..\..\components\net\sal_socket\src\sal_socket.c + + + + + af_inet_lwip.c + 1 + ..\..\components\net\sal_socket\impl\af_inet_lwip.c + + + + + net_netdb.c + 1 + ..\..\components\net\sal_socket\socket\net_netdb.c + + + + + dfs_net.c + 1 + ..\..\components\net\sal_socket\dfs_net\dfs_net.c + + + + + Utilities + + + ry_sy.c + 1 + ..\..\components\utilities\ymodem\ry_sy.c + + + + + ymodem.c + 1 + ..\..\components\utilities\ymodem\ymodem.c diff --git a/bsp/mini2440/rtconfig.h b/bsp/mini2440/rtconfig.h index 37c215bdd0..4cbb6227f6 100644 --- a/bsp/mini2440/rtconfig.h +++ b/bsp/mini2440/rtconfig.h @@ -21,6 +21,9 @@ #define RT_USING_TIMER_SOFT #define RT_TIMER_THREAD_PRIO 4 #define RT_TIMER_THREAD_STACK_SIZE 512 + +/* kservice optimization */ + #define RT_DEBUG /* Inter-Thread communication */ @@ -44,7 +47,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart" -#define RT_VER_NUM 0x40003 +#define RT_VER_NUM 0x40004 #define ARCH_ARM #define ARCH_ARM_ARM9 @@ -89,6 +92,8 @@ #define RT_DFS_ELM_WORD_ACCESS #define RT_DFS_ELM_USE_LFN_3 #define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_LFN_UNICODE_0 +#define RT_DFS_ELM_LFN_UNICODE 0 #define RT_DFS_ELM_MAX_LFN 255 #define RT_DFS_ELM_DRIVES 2 #define RT_DFS_ELM_MAX_SECTOR_SIZE 512 @@ -104,6 +109,7 @@ #define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048 #define RT_SYSTEM_WORKQUEUE_PRIORITY 23 #define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 #define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_PIN @@ -128,12 +134,14 @@ #define RT_USING_POSIX_AIO #define RT_USING_MODULE #define RT_USING_CUSTOM_DLMODULE +#define RT_LIBC_FIXED_TIMEZONE 8 /* Network */ /* Socket abstraction layer */ #define RT_USING_SAL +#define SAL_INTERNET_CHECK /* protocol stack implement */ @@ -153,7 +161,8 @@ /* light weight TCP/IP stack */ #define RT_USING_LWIP -#define RT_USING_LWIP210 +#define RT_USING_LWIP203 +#define RT_LWIP_MEM_ALIGNMENT 4 #define RT_LWIP_IGMP #define RT_LWIP_ICMP #define RT_LWIP_DNS @@ -189,6 +198,7 @@ #define LWIP_SO_RCVTIMEO 1 #define LWIP_SO_SNDTIMEO 1 #define LWIP_SO_RCVBUF 1 +#define LWIP_SO_LINGER 0 #define RT_LWIP_NETIF_LOOPBACK #define LWIP_NETIF_LOOPBACK 1 #define RT_LWIP_STATS @@ -206,6 +216,9 @@ #define YMODEM_USING_CRC_TABLE #define YMODEM_USING_FILE_TRANSFER +/* RT-Thread Utestcases */ + + /* RT-Thread online packages */ /* IoT - internet of things */ @@ -237,13 +250,22 @@ /* system packages */ +/* Micrium: Micrium software products porting for RT-Thread */ + + /* peripheral libraries and drivers */ +/* AI packages */ + + /* miscellaneous packages */ /* samples: kernel and components samples */ +/* entertainment: terminal games and other interesting software packages */ + + #endif diff --git a/bsp/nrf5x/libraries/drivers/drv_uart.c b/bsp/nrf5x/libraries/drivers/drv_uart.c index 8ee6992f02..217d5fc3db 100644 --- a/bsp/nrf5x/libraries/drivers/drv_uart.c +++ b/bsp/nrf5x/libraries/drivers/drv_uart.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2020-04-28 xckhmf Modify for + * 2021-06-26 supperthomas fix rt_hw_uart_init * */ #include @@ -236,7 +237,7 @@ static struct rt_uart_ops _uart_ops = { _uart_getc }; -void rt_hw_uart_init(void) +int rt_hw_uart_init(void) { struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; @@ -249,5 +250,4 @@ void rt_hw_uart_init(void) #endif /* BSP_USING_UART0 */ } - #endif /* BSP_USING_UART */ diff --git a/bsp/nrf5x/libraries/drivers/drv_uart.h b/bsp/nrf5x/libraries/drivers/drv_uart.h index da37eff016..3bf9a2c9b6 100644 --- a/bsp/nrf5x/libraries/drivers/drv_uart.h +++ b/bsp/nrf5x/libraries/drivers/drv_uart.h @@ -11,9 +11,7 @@ #define UART0_RB_SIZE 1024 -// #define USE_UART0_1 0 - -void rt_hw_uart_init(void); +int rt_hw_uart_init(void); #endif diff --git a/bsp/nrf5x/nrf52832/.config b/bsp/nrf5x/nrf52832/.config index dcc634dfbc..5936d29741 100644 --- a/bsp/nrf5x/nrf52832/.config +++ b/bsp/nrf5x/nrf52832/.config @@ -23,6 +23,12 @@ CONFIG_IDLE_THREAD_STACK_SIZE=256 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set CONFIG_RT_DEBUG=y # CONFIG_RT_DEBUG_COLOR is not set # CONFIG_RT_DEBUG_INIT_CONFIG is not set @@ -54,6 +60,7 @@ CONFIG_RT_USING_MEMPOOL=y # CONFIG_RT_USING_NOHEAP is not set CONFIG_RT_USING_SMALL_MEM=y # CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_USERHEAP is not set # CONFIG_RT_USING_MEMTRACE is not set CONFIG_RT_USING_HEAP=y @@ -66,7 +73,7 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" -CONFIG_RT_VER_NUM=0x40003 +CONFIG_RT_VER_NUM=0x40004 # CONFIG_RT_USING_CPU_FFS is not set # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set @@ -105,7 +112,16 @@ CONFIG_FINSH_ARG_MAX=10 # # Device virtual file system # -# CONFIG_RT_USING_DFS is not set +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=4 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 +CONFIG_DFS_FD_MAX=16 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set # # Device Drivers @@ -114,6 +130,8 @@ CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 # CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set # CONFIG_RT_SERIAL_USING_DMA is not set CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_CAN is not set @@ -125,7 +143,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_PWM is not set -# CONFIG_RT_USING_MTD_NOR is not set +CONFIG_RT_USING_MTD_NOR=y # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_PM is not set # CONFIG_RT_USING_RTC is not set @@ -151,7 +169,13 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_LIBC=y # CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_USING_POSIX=y +# CONFIG_RT_USING_POSIX_MMAP is not set +# CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_GETLINE is not set +# CONFIG_RT_USING_POSIX_AIO is not set # CONFIG_RT_USING_MODULE is not set +CONFIG_RT_LIBC_FIXED_TIMEZONE=8 # # Network @@ -188,6 +212,12 @@ CONFIG_RT_USING_LIBC=y # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_RT_LINK is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set # # RT-Thread online packages @@ -196,12 +226,15 @@ CONFIG_RT_USING_LIBC=y # # IoT - internet of things # +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set # CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set # CONFIG_PKG_USING_MYMQTT is not set # CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set @@ -228,6 +261,7 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set # CONFIG_PKG_USING_PPP_DEVICE is not set # CONFIG_PKG_USING_AT_DEVICE is not set # CONFIG_PKG_USING_ATSRV_SOCKET is not set @@ -240,7 +274,7 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set # CONFIG_PKG_USING_JIOT-C-SDK is not set # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set # CONFIG_PKG_USING_JOYLINK is not set @@ -252,8 +286,6 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_LIBRWS is not set # CONFIG_PKG_USING_TCPSERVER is not set # CONFIG_PKG_USING_PROTOBUF_C is not set -# CONFIG_PKG_USING_ONNX_PARSER is not set -# CONFIG_PKG_USING_ONNX_BACKEND is not set # CONFIG_PKG_USING_DLT645 is not set # CONFIG_PKG_USING_QXWZ is not set # CONFIG_PKG_USING_SMTP_CLIENT is not set @@ -262,6 +294,18 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_CAPNP is not set # CONFIG_PKG_USING_RT_CJSON_TOOLS is not set # CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set # # security packages @@ -270,6 +314,7 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_libsodium is not set # CONFIG_PKG_USING_TINYCRYPT is not set # CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set # # language packages @@ -286,6 +331,13 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_STEMWIN is not set # CONFIG_PKG_USING_WAVPLAYER is not set # CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set # # tools packages @@ -294,38 +346,125 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_EASYFLASH is not set # CONFIG_PKG_USING_EASYLOGGER is not set # CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set # CONFIG_PKG_USING_RDB is not set # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set # CONFIG_PKG_USING_ADBD is not set # CONFIG_PKG_USING_COREMARK is not set # CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set # CONFIG_PKG_USING_NR_MICRO_SHELL is not set # CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set # CONFIG_PKG_USING_LUNAR_CALENDAR is not set # CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set # # system packages # + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set # CONFIG_PKG_USING_GUIENGINE is not set # CONFIG_PKG_USING_CAIRO is not set # CONFIG_PKG_USING_PIXMAN is not set -# CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set -# CONFIG_PKG_USING_FAL is not set +CONFIG_PKG_USING_FAL=y +CONFIG_PKG_FAL_PATH="/packages/system/fal" +CONFIG_FAL_DEBUG_CONFIG=y +CONFIG_FAL_DEBUG=1 +CONFIG_FAL_PART_HAS_TABLE_CFG=y +# CONFIG_FAL_USING_SFUD_PORT is not set +CONFIG_PKG_USING_FAL_V00500=y +# CONFIG_PKG_USING_FAL_V00400 is not set +# CONFIG_PKG_USING_FAL_V00300 is not set +# CONFIG_PKG_USING_FAL_V00200 is not set +# CONFIG_PKG_USING_FAL_V00100 is not set +# CONFIG_PKG_USING_FAL_LATEST_VERSION is not set +CONFIG_PKG_FAL_VER="v0.5.0" +CONFIG_PKG_FAL_VER_NUM=0x00500 +# CONFIG_PKG_USING_FLASHDB is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set # CONFIG_PKG_USING_CMSIS is not set # CONFIG_PKG_USING_DFS_YAFFS is not set -# CONFIG_PKG_USING_LITTLEFS is not set +CONFIG_PKG_USING_LITTLEFS=y +CONFIG_PKG_LITTLEFS_PATH="/packages/system/littlefs" +# CONFIG_PKG_USING_LITTLEFS_V090 is not set +# CONFIG_PKG_USING_LITTLEFS_V170 is not set +# CONFIG_PKG_USING_LITTLEFS_V172 is not set +# CONFIG_PKG_USING_LITTLEFS_V201 is not set +# CONFIG_PKG_USING_LITTLEFS_V205 is not set +# CONFIG_PKG_USING_LITTLEFS_V214 is not set +# CONFIG_PKG_USING_LITTLEFS_V220 is not set +# CONFIG_PKG_USING_LITTLEFS_V221 is not set +# CONFIG_PKG_USING_LITTLEFS_V230 is not set +CONFIG_PKG_USING_LITTLEFS_LATEST_VERSION=y +CONFIG_LFS_READ_SIZE=256 +CONFIG_LFS_PROG_SIZE=256 +CONFIG_LFS_BLOCK_SIZE=4096 +CONFIG_LFS_CACHE_SIZE=256 +CONFIG_LFS_BLOCK_CYCLES=-1 +# CONFIG_DFS_LFS_READONLY is not set +CONFIG_LFS_THREADSAFE=y +CONFIG_LFS_LOOKAHEAD_MAX=128 +CONFIG_PKG_LITTLEFS_VER="latest" +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_THREAD_POOL is not set # CONFIG_PKG_USING_ROBOTS is not set # CONFIG_PKG_USING_EV is not set # CONFIG_PKG_USING_SYSWATCH is not set # CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set # CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set # # peripheral libraries and drivers @@ -334,6 +473,7 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set # CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_U8G2 is not set @@ -347,13 +487,12 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_NRF5X_SDK is not set CONFIG_PKG_USING_NRFX=y CONFIG_PKG_NRFX_PATH="/packages/peripherals/nrfx" -CONFIG_PKG_USING_NRFX_V210=y -# CONFIG_PKG_USING_NRFX_LATEST_VERSION is not set -CONFIG_PKG_NRFX_VER="v2.1.0" +# CONFIG_PKG_USING_NRFX_V210 is not set +CONFIG_PKG_USING_NRFX_LATEST_VERSION=y +CONFIG_PKG_NRFX_VER="latest" # CONFIG_PKG_USING_WM_LIBRARIES is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set # CONFIG_PKG_USING_INFRARED is not set -# CONFIG_PKG_USING_ROSSERIAL is not set # CONFIG_PKG_USING_AGILE_BUTTON is not set # CONFIG_PKG_USING_AGILE_LED is not set # CONFIG_PKG_USING_AT24CXX is not set @@ -367,6 +506,7 @@ CONFIG_PKG_NRFX_VER="v2.1.0" # CONFIG_PKG_USING_RPLIDAR is not set # CONFIG_PKG_USING_AS608 is not set # CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set # CONFIG_PKG_USING_EMBARC_BSP is not set # CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set # CONFIG_PKG_USING_MULTI_RTIMER is not set @@ -374,6 +514,44 @@ CONFIG_PKG_NRFX_VER="v2.1.0" # CONFIG_PKG_USING_BEEP is not set # CONFIG_PKG_USING_EASYBLINK is not set # CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set # # miscellaneous packages @@ -383,10 +561,12 @@ CONFIG_PKG_NRFX_VER="v2.1.0" # CONFIG_PKG_USING_FASTLZ is not set # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set # CONFIG_PKG_USING_MULTIBUTTON is not set # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set # CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set # CONFIG_PKG_USING_KENDRYTE_DEMO is not set @@ -403,13 +583,25 @@ CONFIG_PKG_NRFX_VER="v2.1.0" # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set # CONFIG_PKG_USING_HELLO is not set # CONFIG_PKG_USING_VI is not set -# CONFIG_PKG_USING_NNOM is not set -# CONFIG_PKG_USING_LIBANN is not set -# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_KI is not set # CONFIG_PKG_USING_ARMv7M_DWT is not set # CONFIG_PKG_USING_VT100 is not set -# CONFIG_PKG_USING_ULAPACK is not set # CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set # # Hardware Drivers Config @@ -440,16 +632,18 @@ CONFIG_BSP_USING_UART0=y CONFIG_NRFX_UART0_ENABLED=1 CONFIG_BSP_UART0_RX_PIN=8 CONFIG_BSP_UART0_TX_PIN=6 +# CONFIG_BSP_USING_I2C is not set # CONFIG_BSP_USING_SPI is not set -# CONFIG_BSP_USING_ON_CHIP_FLASH is not set +CONFIG_BSP_USING_ON_CHIP_FLASH=y +CONFIG_BSP_USING_ON_CHIP_FS=y # # On-chip flash config # CONFIG_MCU_FLASH_START_ADDRESS=0x00000000 -CONFIG_MCU_FLASH_SIZE_KB=1024 +CONFIG_MCU_FLASH_SIZE_KB=512 CONFIG_MCU_SRAM_START_ADDRESS=0x20000000 -CONFIG_MCU_SRAM_SIZE_KB=256 +CONFIG_MCU_SRAM_SIZE_KB=64 CONFIG_MCU_FLASH_PAGE_SIZE=0x1000 # CONFIG_BSP_USING_WDT is not set # CONFIG_BSP_USING_ONCHIP_RTC is not set diff --git a/bsp/nrf5x/nrf52832/.vscode/launch.json b/bsp/nrf5x/nrf52832/.vscode/launch.json index c3a54b371b..9bcc1a8d86 100644 --- a/bsp/nrf5x/nrf52832/.vscode/launch.json +++ b/bsp/nrf5x/nrf52832/.vscode/launch.json @@ -2,14 +2,15 @@ "version": "0.2.0", "configurations": [ { - "type": "cortex-debug", - "request": "launch", - "servertype": "jlink", "cwd": "${workspaceRoot}", "executable": "rt-thread.elf", - "name": "Cortex Debug", - "device": "nrf52", - "interface": "swd" - } + "name": "Debug MAX", + "request": "launch", + "type": "cortex-debug", + "servertype": "jlink", + "interface": "swd", + "device": "NRF52832_XXAA", + "runToMain": true + }, ] } \ No newline at end of file diff --git a/bsp/nrf5x/nrf52832/applications/SConscript b/bsp/nrf5x/nrf52832/applications/SConscript index fc2501998c..644eec02bf 100644 --- a/bsp/nrf5x/nrf52832/applications/SConscript +++ b/bsp/nrf5x/nrf52832/applications/SConscript @@ -1,11 +1,17 @@ -Import('RTT_ROOT') -Import('rtconfig') from building import * -cwd = os.path.join(str(Dir('#')), 'applications') -src = Glob('*.c') -CPPPATH = [cwd, str(Dir('#'))] +cwd = GetCurrentDir() + +src = Split(''' +main.c +''') + +if GetDepend(['BSP_USING_ON_CHIP_FS']): + src += ['mnt.c'] + + +CPPPATH = [str(Dir('#')), cwd] group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) -Return('group') +Return('group') \ No newline at end of file diff --git a/bsp/nrf5x/nrf52832/applications/application.c b/bsp/nrf5x/nrf52832/applications/main.c similarity index 100% rename from bsp/nrf5x/nrf52832/applications/application.c rename to bsp/nrf5x/nrf52832/applications/main.c diff --git a/bsp/nrf5x/nrf52832/applications/mnt.c b/bsp/nrf5x/nrf52832/applications/mnt.c new file mode 100644 index 0000000000..c7e4d10235 --- /dev/null +++ b/bsp/nrf5x/nrf52832/applications/mnt.c @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * on chip filesystem support + * Change Logs: + * Date Author Notes + * 2021-06-27 Chenyingchun first version + */ +#include "board.h" +#include +#include + +#ifdef BSP_USING_ON_CHIP_FS + +#ifndef PKG_USING_FAL +#error "if you want to use on chip filesystem, you need to enable FAL package()" +#endif + +#ifndef RT_USING_DFS +#error "if you want to use on chip filesystem, you need to enable DFS componment" +#endif + +#ifndef BSP_USING_ON_CHIP_FLASH +#error "if you want to use on chip filesystem, you need to enable on-chip flash" +#endif + +#ifndef RT_USING_MTD_NOR +#error "if you want to use on chip filesystem, you need to enable mtd nor" +#endif + +#ifndef PKG_USING_LITTLEFS +#error "if you want to use on chip filesystem, you need to enable littlefs" +#endif + +#include "fal.h" +#include + +#define LOG_TAG "drv.fs" +#define DBG_LVL DBG_LOG +#include + +#define FS_PARTITION_NAME ON_CHIP_PARTION_NAME + +/** + * @brief on chip filesystem init + * @param void + * @retval 0: filesystem init success, -1: filesystem init failed + */ + +static int on_chip_fs_init(void) +{ + int result = 0; + + fal_init(); + + struct rt_device *flash_dev = fal_mtd_nor_device_create(FS_PARTITION_NAME); + + if (flash_dev == NULL) + { + LOG_E("Can't create a block device on '%s' partition.", FS_PARTITION_NAME); + result = -1; + goto err; + } + else + { + LOG_D("Create a block device on the %s partition of flash successful.", FS_PARTITION_NAME); + } + + if (rt_device_find(FS_PARTITION_NAME) != RT_NULL) + { + int mkfs_res = dfs_mkfs("lfs", FS_PARTITION_NAME); + + if (mkfs_res != 0) + { + LOG_E("dfs_mkfs error, errno = %d", rt_get_errno()); + result = -1; + goto err; + } + + if (dfs_mount(FS_PARTITION_NAME, "/", "lfs", 0, 0) == RT_EOK) + { + LOG_D("onchip elm filesystem mount to '/'"); + } + else + { + LOG_E("onchip elm filesystem mount to '/' failed!"); + result = -1; + goto err; + } + } + else + { + LOG_E("find filesystem portion failed"); + } +err: + return result; +} + +INIT_ENV_EXPORT(on_chip_fs_init); + +#endif /* BSP_USING_ON_CHIP_FS */ diff --git a/bsp/nrf5x/nrf52832/board/Kconfig b/bsp/nrf5x/nrf52832/board/Kconfig index 98cf53014b..416722fd64 100644 --- a/bsp/nrf5x/nrf52832/board/Kconfig +++ b/bsp/nrf5x/nrf52832/board/Kconfig @@ -341,6 +341,10 @@ menu "On-chip Peripheral Drivers" select PKG_USING_FAL bool "Enable on-chip FLASH" default n + + config BSP_USING_ON_CHIP_FS + bool "Enable on-chip filesystem" + default n menu "On-chip flash config" @@ -351,7 +355,7 @@ menu "On-chip Peripheral Drivers" config MCU_FLASH_SIZE_KB int "MCU FLASH SIZE, MAX size 1024 KB" range 1 1024 - default 1024 + default 512 config MCU_SRAM_START_ADDRESS hex "MCU RAM START ADDRESS" @@ -360,7 +364,7 @@ menu "On-chip Peripheral Drivers" config MCU_SRAM_SIZE_KB int "MCU RAM SIZE, MAX size 256 KB" range 1 256 - default 256 + default 64 config MCU_FLASH_PAGE_SIZE hex "MCU FLASH PAGE SIZE, please not change,nrfx default is 0x1000" diff --git a/bsp/nrf5x/nrf52832/board/board.c b/bsp/nrf5x/nrf52832/board/board.c index 0b3a436530..26fcf8e7bb 100644 --- a/bsp/nrf5x/nrf52832/board/board.c +++ b/bsp/nrf5x/nrf52832/board/board.c @@ -49,6 +49,40 @@ void SysTick_Configuration(void) } +/** + * The time delay function. + * + * @param microseconds. + */ +void rt_hw_us_delay(rt_uint32_t us) +{ + rt_uint32_t ticks; + rt_uint32_t told, tnow, tcnt = 0; + rt_uint32_t reload = SysTick->LOAD; + + ticks = us * reload / (1000000 / RT_TICK_PER_SECOND); + told = SysTick->VAL; + while (1) + { + tnow = SysTick->VAL; + if (tnow != told) + { + if (tnow < told) + { + tcnt += told - tnow; + } + else + { + tcnt += reload - tnow + told; + } + told = tnow; + if (tcnt >= ticks) + { + break; + } + } + } +} void rt_hw_board_init(void) { diff --git a/bsp/nrf5x/nrf52832/board/fal_cfg.h b/bsp/nrf5x/nrf52832/board/fal_cfg.h new file mode 100644 index 0000000000..089adcf465 --- /dev/null +++ b/bsp/nrf5x/nrf52832/board/fal_cfg.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-06-26 chenyingchun the first version + */ + +#ifndef _FAL_CFG_H_ +#define _FAL_CFG_H_ + +#include +#include + +#define ON_CHIP_FLASH_DEV_NAME "mcu_onchip_flash" +#define ON_CHIP_PARTION_NAME "filesystem" + +/* ===================== Flash device Configuration ========================= */ +extern const struct fal_flash_dev mcu_onchip_flash; + +/* flash device table */ +#define FAL_FLASH_DEV_TABLE \ + { \ + &mcu_onchip_flash, \ + } +/* ====================== Partition Configuration ========================== */ +#ifdef FAL_PART_HAS_TABLE_CFG +/* partition table */ +#define FAL_PART_TABLE \ + { \ + {FAL_PART_MAGIC_WORD, ON_CHIP_PARTION_NAME, ON_CHIP_FLASH_DEV_NAME, 224 * 1024, 120 * 1024, 0}, \ + } +#endif /* FAL_PART_HAS_TABLE_CFG */ + +#endif /* _FAL_CFG_H_ */ diff --git a/bsp/nrf5x/nrf52832/board/linker_scripts/link.lds b/bsp/nrf5x/nrf52832/board/linker_scripts/link.lds index b1d21b531b..f4cf7ebbf7 100644 --- a/bsp/nrf5x/nrf52832/board/linker_scripts/link.lds +++ b/bsp/nrf5x/nrf52832/board/linker_scripts/link.lds @@ -1,16 +1,130 @@ /* Linker script to configure memory regions. */ -SEARCH_DIR(.) -GROUP(-lgcc -lc -lnosys) - MEMORY { - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 - RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x10000 - CODE_RAM (rwx) : ORIGIN = 0x800000, LENGTH = 0x10000 + ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 /* 512K FLASH */ + RAM (rw) : ORIGIN = 0x20000000, LENGTH = 0x10000 /* 64K RAM */ } +ENTRY(Reset_Handler) +_system_stack_size = 0x200; -INCLUDE "packages/nrfx-v2.1.0/mdk/nrf_common.ld" +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + . = ALIGN(4); + + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + + _etext = .; + } > ROM = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > ROM + __exidx_end = .; + + /* .data section which is used for initialized data */ + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >RAM + + .stack : + { + . = ALIGN(4); + _sstack = .; + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >RAM + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > RAM + __bss_end = .; + + _end = .; + + PROVIDE(__etext = __exidx_end); + PROVIDE(__data_start__ = _sdata); + PROVIDE(__bss_start__ = __bss_start); + PROVIDE(__bss_end__ = __bss_end); + PROVIDE(__StackTop = _estack); +} diff --git a/bsp/nrf5x/nrf52832/rtconfig.h b/bsp/nrf5x/nrf52832/rtconfig.h index 2626384351..ee2691d102 100644 --- a/bsp/nrf5x/nrf52832/rtconfig.h +++ b/bsp/nrf5x/nrf52832/rtconfig.h @@ -19,6 +19,9 @@ #define RT_USING_TIMER_SOFT #define RT_TIMER_THREAD_PRIO 4 #define RT_TIMER_THREAD_STACK_SIZE 512 + +/* kservice optimization */ + #define RT_DEBUG /* Inter-Thread communication */ @@ -41,7 +44,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart0" -#define RT_VER_NUM 0x40003 +#define RT_VER_NUM 0x40004 /* RT-Thread Components */ @@ -77,6 +80,7 @@ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 #define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_PIN @@ -86,6 +90,7 @@ /* POSIX layer and C standard library */ #define RT_USING_LIBC +#define RT_LIBC_FIXED_TIMEZONE 8 /* Network */ @@ -107,6 +112,9 @@ /* Utilities */ +/* RT-Thread Utestcases */ + + /* RT-Thread online packages */ /* IoT - internet of things */ @@ -141,7 +149,7 @@ /* peripheral libraries and drivers */ #define PKG_USING_NRFX -#define PKG_USING_NRFX_V210 +#define PKG_USING_NRFX_LATEST_VERSION /* miscellaneous packages */ @@ -175,9 +183,9 @@ /* On-chip flash config */ #define MCU_FLASH_START_ADDRESS 0x00000000 -#define MCU_FLASH_SIZE_KB 1024 +#define MCU_FLASH_SIZE_KB 512 #define MCU_SRAM_START_ADDRESS 0x20000000 -#define MCU_SRAM_SIZE_KB 256 +#define MCU_SRAM_SIZE_KB 64 #define MCU_FLASH_PAGE_SIZE 0x1000 #define BLE_STACK_USING_NULL diff --git a/bsp/nrf5x/nrf52832/rtconfig.py b/bsp/nrf5x/nrf52832/rtconfig.py index e8a959bc85..805feeae54 100644 --- a/bsp/nrf5x/nrf52832/rtconfig.py +++ b/bsp/nrf5x/nrf52832/rtconfig.py @@ -34,17 +34,26 @@ if PLATFORM == 'gcc': CC = PREFIX + 'gcc' AS = PREFIX + 'gcc' AR = PREFIX + 'ar' + CXX= PREFIX + 'g++' LINK = PREFIX + 'gcc' TARGET_EXT = 'elf' SIZE = PREFIX + 'size' OBJDUMP = PREFIX + 'objdump' OBJCPY = PREFIX + 'objcopy' + STRIP = PREFIX + 'strip' DEVICE = ' -mcpu=cortex-m4 -mthumb -ffunction-sections -fdata-sections' CFLAGS = DEVICE AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + CXXFLAGS = CFLAGS + M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC ' + M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC' + M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' +\ + ' -shared -fPIC -nostartfiles -nostdlib -static-libgcc' + M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n' + CPATH = '' LPATH = '' diff --git a/bsp/nrf5x/nrf52840/.config b/bsp/nrf5x/nrf52840/.config index 10441fdb08..1f53828ede 100644 --- a/bsp/nrf5x/nrf52840/.config +++ b/bsp/nrf5x/nrf52840/.config @@ -3,6 +3,57 @@ # RT-Thread Configuration # +# +# Hardware Drivers Config +# +CONFIG_SOC_NRF52840=y +CONFIG_SOC_NORDIC=y +CONFIG_BSP_BOARD_PCA_10056=y +# CONFIG_BSP_BOARD_ARDUINO_NANO_33_BLE is not set + +# +# Onboard Peripheral Drivers +# +CONFIG_BSP_USING_JLINK_TO_USART=y +CONFIG_RT_BSP_LED_PIN=13 +# CONFIG_BSP_USING_QSPI_FLASH is not set + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +CONFIG_NRFX_USING_UART=y +# CONFIG_NRFX_USING_UARTE is not set +CONFIG_BSP_USING_UART0=y +CONFIG_BSP_UART0_RX_PIN=8 +CONFIG_BSP_UART0_TX_PIN=6 +# CONFIG_BSP_USING_SAADC is not set +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_PWM is not set +# CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_ONCHIP_RTC is not set +# CONFIG_BSP_USING_ON_CHIP_FLASH is not set + +# +# MCU flash config +# +CONFIG_MCU_FLASH_START_ADDRESS=0x00000000 +CONFIG_MCU_FLASH_SIZE_KB=1024 +CONFIG_MCU_SRAM_START_ADDRESS=0x20000000 +CONFIG_MCU_SRAM_SIZE_KB=256 +CONFIG_MCU_FLASH_PAGE_SIZE=0x1000 +CONFIG_BLE_STACK_USING_NULL=y +# CONFIG_BSP_USING_SOFTDEVICE is not set +# CONFIG_BSP_USING_NIMBLE is not set +CONFIG_NRFX_CLOCK_ENABLED=1 +CONFIG_NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY=7 +CONFIG_NRFX_CLOCK_CONFIG_LF_SRC=1 +CONFIG_NRFX_UART_ENABLED=1 +CONFIG_NRFX_UART0_ENABLED=1 +CONFIG_NRFX_GPIOTE_ENABLED=1 + # # RT-Thread Kernel # @@ -15,7 +66,7 @@ CONFIG_RT_THREAD_PRIORITY_32=y # CONFIG_RT_THREAD_PRIORITY_256 is not set CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=100 -CONFIG_RT_USING_OVERFLOW_CHECK=y +# CONFIG_RT_USING_OVERFLOW_CHECK is not set CONFIG_RT_USING_HOOK=y CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 @@ -23,18 +74,13 @@ CONFIG_IDLE_THREAD_STACK_SIZE=256 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 -CONFIG_RT_DEBUG=y -# CONFIG_RT_DEBUG_COLOR is not set -# CONFIG_RT_DEBUG_INIT_CONFIG is not set -# CONFIG_RT_DEBUG_THREAD_CONFIG is not set -# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set -# CONFIG_RT_DEBUG_IPC_CONFIG is not set -# CONFIG_RT_DEBUG_TIMER_CONFIG is not set -# CONFIG_RT_DEBUG_IRQ_CONFIG is not set -# CONFIG_RT_DEBUG_MEM_CONFIG is not set -# CONFIG_RT_DEBUG_SLAB_CONFIG is not set -# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set -# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_DEBUG is not set # # Inter-Thread communication @@ -42,8 +88,8 @@ CONFIG_RT_DEBUG=y CONFIG_RT_USING_SEMAPHORE=y CONFIG_RT_USING_MUTEX=y CONFIG_RT_USING_EVENT=y -CONFIG_RT_USING_MAILBOX=y -CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MAILBOX is not set +# CONFIG_RT_USING_MESSAGEQUEUE is not set # CONFIG_RT_USING_SIGNALS is not set # @@ -54,6 +100,7 @@ CONFIG_RT_USING_MEMPOOL=y # CONFIG_RT_USING_NOHEAP is not set CONFIG_RT_USING_SMALL_MEM=y # CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_USERHEAP is not set # CONFIG_RT_USING_MEMTRACE is not set CONFIG_RT_USING_HEAP=y @@ -66,7 +113,7 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" -CONFIG_RT_VER_NUM=0x40003 +CONFIG_RT_VER_NUM=0x40004 # CONFIG_RT_USING_CPU_FFS is not set # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set @@ -99,7 +146,7 @@ CONFIG_FINSH_CMD_SIZE=80 # CONFIG_FINSH_USING_AUTH is not set CONFIG_FINSH_USING_MSH=y CONFIG_FINSH_USING_MSH_DEFAULT=y -CONFIG_FINSH_USING_MSH_ONLY=y +# CONFIG_FINSH_USING_MSH_ONLY is not set CONFIG_FINSH_ARG_MAX=10 # @@ -149,9 +196,9 @@ CONFIG_RT_USING_PIN=y # # POSIX layer and C standard library # -CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_LIBC is not set # CONFIG_RT_USING_PTHREADS is not set -# CONFIG_RT_USING_MODULE is not set +# CONFIG_RT_LIBC_USING_TIME is not set # # Network @@ -188,6 +235,12 @@ CONFIG_RT_USING_LIBC=y # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_RT_LINK is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set # # RT-Thread online packages @@ -256,8 +309,6 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_LIBRWS is not set # CONFIG_PKG_USING_TCPSERVER is not set # CONFIG_PKG_USING_PROTOBUF_C is not set -# CONFIG_PKG_USING_ONNX_PARSER is not set -# CONFIG_PKG_USING_ONNX_BACKEND is not set # CONFIG_PKG_USING_DLT645 is not set # CONFIG_PKG_USING_QXWZ is not set # CONFIG_PKG_USING_SMTP_CLIENT is not set @@ -271,6 +322,13 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_PDULIB is not set # CONFIG_PKG_USING_BTSTACK is not set # CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set # # security packages @@ -296,7 +354,13 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_STEMWIN is not set # CONFIG_PKG_USING_WAVPLAYER is not set # CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set # CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set # # tools packages @@ -305,12 +369,16 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_EASYFLASH is not set # CONFIG_PKG_USING_EASYLOGGER is not set # CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set # CONFIG_PKG_USING_RDB is not set # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set # CONFIG_PKG_USING_ADBD is not set # CONFIG_PKG_USING_COREMARK is not set # CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set # CONFIG_PKG_USING_NR_MICRO_SHELL is not set # CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set # CONFIG_PKG_USING_LUNAR_CALENDAR is not set @@ -318,14 +386,48 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_GPS_RMC is not set # CONFIG_PKG_USING_URLENCODE is not set # CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set # # system packages # + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set # CONFIG_PKG_USING_GUIENGINE is not set # CONFIG_PKG_USING_CAIRO is not set # CONFIG_PKG_USING_PIXMAN is not set -# CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_FAL is not set # CONFIG_PKG_USING_FLASHDB is not set @@ -335,6 +437,9 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_CMSIS is not set # CONFIG_PKG_USING_DFS_YAFFS is not set # CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_THREAD_POOL is not set # CONFIG_PKG_USING_ROBOTS is not set # CONFIG_PKG_USING_EV is not set @@ -344,11 +449,12 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_RAMDISK is not set # CONFIG_PKG_USING_MININI is not set # CONFIG_PKG_USING_QBOOT is not set -# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set -# CONFIG_PKG_USING_UC_CRC is not set -# CONFIG_PKG_USING_UC_CLK is not set -# CONFIG_PKG_USING_UC_COMMON is not set # CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set # # peripheral libraries and drivers @@ -357,6 +463,7 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set # CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_U8G2 is not set @@ -370,13 +477,12 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_NRF5X_SDK is not set CONFIG_PKG_USING_NRFX=y CONFIG_PKG_NRFX_PATH="/packages/peripherals/nrfx" -CONFIG_PKG_USING_NRFX_V210=y -# CONFIG_PKG_USING_NRFX_LATEST_VERSION is not set -CONFIG_PKG_NRFX_VER="v2.1.0" +# CONFIG_PKG_USING_NRFX_V210 is not set +CONFIG_PKG_USING_NRFX_LATEST_VERSION=y +CONFIG_PKG_NRFX_VER="latest" # CONFIG_PKG_USING_WM_LIBRARIES is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set # CONFIG_PKG_USING_INFRARED is not set -# CONFIG_PKG_USING_ROSSERIAL is not set # CONFIG_PKG_USING_AGILE_BUTTON is not set # CONFIG_PKG_USING_AGILE_LED is not set # CONFIG_PKG_USING_AT24CXX is not set @@ -407,6 +513,35 @@ CONFIG_PKG_NRFX_VER="v2.1.0" # CONFIG_PKG_USING_WK2124 is not set # CONFIG_PKG_USING_LY68L6400 is not set # CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set # # miscellaneous packages @@ -416,10 +551,12 @@ CONFIG_PKG_NRFX_VER="v2.1.0" # CONFIG_PKG_USING_FASTLZ is not set # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set # CONFIG_PKG_USING_MULTIBUTTON is not set # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set # CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set # CONFIG_PKG_USING_KENDRYTE_DEMO is not set @@ -436,63 +573,22 @@ CONFIG_PKG_NRFX_VER="v2.1.0" # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set # CONFIG_PKG_USING_HELLO is not set # CONFIG_PKG_USING_VI is not set -# CONFIG_PKG_USING_NNOM is not set -# CONFIG_PKG_USING_LIBANN is not set -# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_KI is not set # CONFIG_PKG_USING_ARMv7M_DWT is not set # CONFIG_PKG_USING_VT100 is not set -# CONFIG_PKG_USING_TETRIS is not set -# CONFIG_PKG_USING_ULAPACK is not set # CONFIG_PKG_USING_UKAL is not set # CONFIG_PKG_USING_CRCLIB is not set + +# +# entertainment: terminal games and other interesting software packages +# # CONFIG_PKG_USING_THREES is not set # CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_ACLOCK is not set # CONFIG_PKG_USING_LWGPS is not set -# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set - -# -# Hardware Drivers Config -# -CONFIG_SOC_NRF52840=y -CONFIG_NRFX_CLOCK_ENABLED=1 -CONFIG_NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY=7 -CONFIG_NRFX_CLOCK_CONFIG_LF_SRC=1 -CONFIG_SOC_NORDIC=y - -# -# Onboard Peripheral Drivers -# -CONFIG_BSP_USING_JLINK_TO_USART=y -# CONFIG_BSP_USING_QSPI_FLASH is not set - -# -# On-chip Peripheral Drivers -# -CONFIG_BSP_USING_GPIO=y -CONFIG_NRFX_GPIOTE_ENABLED=1 -# CONFIG_BSP_USING_SAADC is not set -# CONFIG_BSP_USING_PWM is not set -CONFIG_BSP_USING_UART=y -CONFIG_NRFX_USING_UART=y -# CONFIG_NRFX_USING_UARTE is not set -CONFIG_NRFX_UART_ENABLED=1 -CONFIG_BSP_USING_UART0=y -CONFIG_NRFX_UART0_ENABLED=1 -CONFIG_BSP_UART0_RX_PIN=8 -CONFIG_BSP_UART0_TX_PIN=6 -# CONFIG_BSP_USING_SPI is not set -# CONFIG_BSP_USING_ON_CHIP_FLASH is not set - -# -# On-chip flash config -# -CONFIG_MCU_FLASH_START_ADDRESS=0x00000000 -CONFIG_MCU_FLASH_SIZE_KB=1024 -CONFIG_MCU_SRAM_START_ADDRESS=0x20000000 -CONFIG_MCU_SRAM_SIZE_KB=256 -CONFIG_MCU_FLASH_PAGE_SIZE=0x1000 -# CONFIG_BSP_USING_WDT is not set -# CONFIG_BSP_USING_ONCHIP_RTC is not set -CONFIG_BLE_STACK_USING_NULL=y -# CONFIG_BSP_USING_SOFTDEVICE is not set -# CONFIG_BSP_USING_NIMBLE is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set diff --git a/bsp/nrf5x/nrf52840/.vscode/launch.json b/bsp/nrf5x/nrf52840/.vscode/launch.json new file mode 100644 index 0000000000..0d61dd7de6 --- /dev/null +++ b/bsp/nrf5x/nrf52840/.vscode/launch.json @@ -0,0 +1,16 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "cwd": "${workspaceRoot}", + "executable": "rt-thread.elf", + "name": "Debug MAX", + "request": "launch", + "type": "cortex-debug", + "servertype": "jlink", + "interface": "swd", + "device": "NRF52840_XXAA", + "runToMain": true + }, + ] +} \ No newline at end of file diff --git a/bsp/nrf5x/nrf52840/Kconfig b/bsp/nrf5x/nrf52840/Kconfig index 3640eaa0ed..56d486baed 100644 --- a/bsp/nrf5x/nrf52840/Kconfig +++ b/bsp/nrf5x/nrf52840/Kconfig @@ -14,8 +14,9 @@ config PKGS_DIR string option env="PKGS_ROOT" default "packages" - + +source "board/Kconfig" source "$RTT_DIR/Kconfig" source "$PKGS_DIR/Kconfig" -source "board/Kconfig" + diff --git a/bsp/nrf5x/nrf52840/README.md b/bsp/nrf5x/nrf52840/README.md index c3a4a95f9f..99b6882b2b 100644 --- a/bsp/nrf5x/nrf52840/README.md +++ b/bsp/nrf5x/nrf52840/README.md @@ -2,7 +2,22 @@ ## 简介 -该文件夹主要存放所有主芯片为nRF52840的板级支持包。目前默认支持的开发板是官方[PCA10056](https://www.nordicsemi.com/Software-and-tools/Development-Kits/nRF52840-DK) +该文件夹主要存放所有主芯片为nRF52840的板级支持包。 + +目前支持的开发板如下 + +| 支持开发板型号 | 开发板上外设 | 备注 | +| ------------------------------------------------------------ | --------------------------- | ----------------------------------- | +| [PCA10056](https://www.nordicsemi.com/Software-and-tools/Development-Kits/nRF52840-DK) | QSPI FLASH, 4 button，4 LED | UART0 | +| [ARDUINO NANO 33 BLE](https://store.arduino.cc/usa/nano-33-ble-sense-with-headers) | 3 LED | 需要连接jlink shell采用RTT 方式交互 | +| | | | + +相关开发板资料原理图整理在[BSP_BOARD_NRF52840](https://github.com/supperthomas/BSP_BOARD_NRF52840) + +选择开发板请使用`menuconfig` -> `Hardware Driver Config` -> `Select Bsp board` + +选择对应的开发板 + 本文主要内容如下： - 开发板资源介绍 diff --git a/bsp/nrf5x/nrf52840/applications/application.c b/bsp/nrf5x/nrf52840/applications/application.c index f2cae69ed1..791e2af007 100644 --- a/bsp/nrf5x/nrf52840/applications/application.c +++ b/bsp/nrf5x/nrf52840/applications/application.c @@ -6,25 +6,24 @@ * Change Logs: * Date Author Notes * 2020-04-29 supperthomas first version + * 2021-06-26 supperthomas fix led * */ #include #include -#define DK_BOARD_LED_1 13 -#define DK_BOARD_LED_2 14 int main(void) { int count = 1; - rt_pin_mode(DK_BOARD_LED_1, PIN_MODE_OUTPUT); + rt_pin_mode(RT_BSP_LED_PIN, PIN_MODE_OUTPUT); while (count++) { - rt_pin_write(DK_BOARD_LED_1, PIN_HIGH); + rt_pin_write(RT_BSP_LED_PIN, PIN_HIGH); rt_thread_mdelay(500); - rt_pin_write(DK_BOARD_LED_1, PIN_LOW); + rt_pin_write(RT_BSP_LED_PIN, PIN_LOW); rt_thread_mdelay(500); } return RT_EOK; diff --git a/bsp/nrf5x/nrf52840/board/Kconfig b/bsp/nrf5x/nrf52840/board/Kconfig index 71e7595048..0a332f8bf0 100644 --- a/bsp/nrf5x/nrf52840/board/Kconfig +++ b/bsp/nrf5x/nrf52840/board/Kconfig @@ -2,37 +2,45 @@ menu "Hardware Drivers Config" config SOC_NRF52840 bool - config SOC_NRF52840 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN default y - config NRFX_CLOCK_ENABLED - int - default 1 - config NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY - int - default 7 - config NRFX_CLOCK_CONFIG_LF_SRC - int - default 1 - config SOC_NORDIC bool - config SOC_NORDIC default y +choice + prompt "Select BSP board " + default BSP_BOARD_PCA_10056 + + config BSP_BOARD_PCA_10056 + select BSP_USING_UART + select BSP_USING_UART0 + bool "NRF52840 pca10056 " + + config BSP_BOARD_ARDUINO_NANO_33_BLE + bool "Arduino Nano 33 BLE (Sense)" +endchoice + menu "Onboard Peripheral Drivers" config BSP_USING_JLINK_TO_USART bool "Enable JLINK TO USART (uart0|RX_PIN:8|TX_PIN:6)" - select BSP_USING_UART - select BSP_USING_UART0 default y + depends on BSP_BOARD_PCA_10056 + + config RT_BSP_LED_PIN + int + default 13 if BSP_BOARD_PCA_10056 + default 16 if BSP_BOARD_ARDUINO_NANO_33_BLE + depends on BSP_USING_GPIO + menuconfig BSP_USING_QSPI_FLASH select PKG_USING_FAL bool "Enable QSPI FLASH(MX25R64 8MB)" default n + depends on BSP_BOARD_PCA_10056 if BSP_USING_QSPI_FLASH config NRFX_QSPI_ENABLED @@ -68,135 +76,17 @@ menu "Onboard Peripheral Drivers" endif endmenu + menu "On-chip Peripheral Drivers" + config BSP_USING_GPIO bool "Enable GPIO" select RT_USING_PIN default y - if BSP_USING_GPIO - config NRFX_GPIOTE_ENABLED - int - default 1 - endif - config BSP_USING_SAADC - bool "Enable SAADC" - select RT_USING_ADC - default n - if BSP_USING_SAADC - config NRFX_SAADC_ENABLED - int - default 1 - endif - menuconfig BSP_USING_PWM - bool "Enable PWM" - select RT_USING_PWM - default n - if BSP_USING_PWM - config NRFX_PWM_ENABLED - int - default 1 - config BSP_USING_PWM0 - bool "Enable PWM0 bus" - default y - if BSP_USING_PWM0 - config NRFX_PWM0_ENABLED - int - default 1 - config BSP_USING_PWM0_CH0 - int "PWM0 channel 0 pin number set" - range 0 47 - default 13 - config BSP_USING_PWM0_CH1 - int "PWM0 channel 1 pin number set" - range 0 47 - default 14 - config BSP_USING_PWM0_CH2 - int "PWM0 channel 2 pin number set" - range 0 47 - default 15 - config BSP_USING_PWM0_CH3 - int "PWM0 channel 3 pin number set" - range 0 47 - default 16 - endif - config BSP_USING_PWM1 - bool "Enable PWM1 bus" - default n - if BSP_USING_PWM1 - config NRFX_PWM1_ENABLED - int - default 1 - config BSP_USING_PWM1_CH0 - int "PWM1 channel 0 pin number set" - range 0 47 - default 13 - config BSP_USING_PWM1_CH1 - int "PWM1 channel 1 pin number set" - range 0 47 - default 14 - config BSP_USING_PWM1_CH2 - int "PWM1 channel 2 pin number set" - range 0 47 - default 15 - config BSP_USING_PWM1_CH3 - int "PWM1 channel 3 pin number set" - range 0 47 - default 16 - endif - config BSP_USING_PWM2 - bool "Enable PWM2 bus" - default n - if BSP_USING_PWM2 - config NRFX_PWM2_ENABLED - int - default 1 - config BSP_USING_PWM2_CH0 - int "PWM2 channel 0 pin number set" - range 0 47 - default 13 - config BSP_USING_PWM2_CH1 - int "PWM2 channel 1 pin number set" - range 0 47 - default 14 - config BSP_USING_PWM2_CH2 - int "PWM2 channel 2 pin number set" - range 0 47 - default 15 - config BSP_USING_PWM2_CH3 - int "PWM2 channel 3 pin number set" - range 0 47 - default 16 - endif - config BSP_USING_PWM3 - bool "Enable PWM3 bus" - default n - if BSP_USING_PWM3 - config NRFX_PWM3_ENABLED - int - default 1 - config BSP_USING_PWM3_CH0 - int "PWM3 channel 0 pin number set" - range 0 47 - default 13 - config BSP_USING_PWM3_CH1 - int "PWM3 channel 1 pin number set" - range 0 47 - default 14 - config BSP_USING_PWM3_CH2 - int "PWM3 channel 2 pin number set" - range 0 47 - default 15 - config BSP_USING_PWM3_CH3 - int "PWM3 channel 3 pin number set" - range 0 47 - default 16 - endif - endif - config BSP_USING_UART bool "Enable UART" - default y + default n select RT_USING_SERIAL if BSP_USING_UART choice @@ -212,17 +102,10 @@ menu "On-chip Peripheral Drivers" endchoice endif if BSP_USING_UART&&NRFX_USING_UART - config NRFX_UART_ENABLED - int - default 1 - config BSP_USING_UART0 bool "Enable UART0" default y if BSP_USING_UART0 - config NRFX_UART0_ENABLED - int - default 1 config BSP_UART0_RX_PIN int "uart0 rx pin number" range 0 31 @@ -271,21 +154,21 @@ menu "On-chip Peripheral Drivers" default 5 endif endif - config BSP_USING_I2C + + config BSP_USING_SAADC + bool "Enable ADC" + select RT_USING_ADC + default n + + menuconfig BSP_USING_I2C bool "Enable I2C" select RT_USING_I2C default n if BSP_USING_I2C - config NRFX_TWIM_ENABLED - int - default 1 config BSP_USING_I2C0 bool "Enable I2C0 bus" - default n + default y if BSP_USING_I2C0 - config NRFX_TWIM0_ENABLED - int - default 1 config BSP_I2C0_SCL_PIN int "i2c0 scl pin number" range 0 31 @@ -299,9 +182,6 @@ menu "On-chip Peripheral Drivers" bool "Enable I2C1 bus" default n if BSP_USING_I2C1 - config NRFX_TWIM1_ENABLED - int - default 1 config BSP_I2C1_SCL_PIN int "i2c1 scl pin number" range 0 31 @@ -312,15 +192,13 @@ menu "On-chip Peripheral Drivers" default 2 endif endif - config BSP_USING_SPI + + menuconfig BSP_USING_SPI bool "Enable SPI" select RT_USING_SPI default n if BSP_USING_SPI - config NRFX_SPI_ENABLED - int - default 1 config BSP_USING_SPI0 bool "Enable SPI0 bus" default y @@ -350,9 +228,6 @@ menu "On-chip Peripheral Drivers" bool "Enable SPI1 bus" default n if BSP_USING_SPI1 - config NRFX_SPI1_ENABLED - int "Enable SPI1 instance" - default 1 config BSP_SPI1_SCK_PIN int "SPI0 sck pin number set" range 0 47 @@ -375,9 +250,6 @@ menu "On-chip Peripheral Drivers" bool "Enable SPI2 bus" default n if BSP_USING_SPI2 - config NRFX_SPI2_ENABLED - int "Enable SPI2 instance" - default 1 config BSP_SPI2_SCK_PIN int "SPI0 sck pin number set" range 0 47 @@ -397,12 +269,119 @@ menu "On-chip Peripheral Drivers" endif endif + + menuconfig BSP_USING_PWM + bool "Enable PWM" + select RT_USING_PWM + default n + if BSP_USING_PWM + config BSP_USING_PWM0 + bool "Enable PWM0 bus" + default y + if BSP_USING_PWM0 + config BSP_USING_PWM0_CH0 + int "PWM0 channel 0 pin number set" + range 0 47 + default 13 + config BSP_USING_PWM0_CH1 + int "PWM0 channel 1 pin number set" + range 0 47 + default 14 + config BSP_USING_PWM0_CH2 + int "PWM0 channel 2 pin number set" + range 0 47 + default 15 + config BSP_USING_PWM0_CH3 + int "PWM0 channel 3 pin number set" + range 0 47 + default 16 + endif + config BSP_USING_PWM1 + bool "Enable PWM1 bus" + default n + if BSP_USING_PWM1 + config NRFX_PWM1_ENABLED + int + default 1 + config BSP_USING_PWM1_CH0 + int "PWM1 channel 0 pin number set" + range 0 47 + default 13 + config BSP_USING_PWM1_CH1 + int "PWM1 channel 1 pin number set" + range 0 47 + default 14 + config BSP_USING_PWM1_CH2 + int "PWM1 channel 2 pin number set" + range 0 47 + default 15 + config BSP_USING_PWM1_CH3 + int "PWM1 channel 3 pin number set" + range 0 47 + default 16 + endif + config BSP_USING_PWM2 + bool "Enable PWM2 bus" + default n + if BSP_USING_PWM2 + config BSP_USING_PWM2_CH0 + int "PWM2 channel 0 pin number set" + range 0 47 + default 13 + config BSP_USING_PWM2_CH1 + int "PWM2 channel 1 pin number set" + range 0 47 + default 14 + config BSP_USING_PWM2_CH2 + int "PWM2 channel 2 pin number set" + range 0 47 + default 15 + config BSP_USING_PWM2_CH3 + int "PWM2 channel 3 pin number set" + range 0 47 + default 16 + endif + config BSP_USING_PWM3 + bool "Enable PWM3 bus" + default n + if BSP_USING_PWM3 + config BSP_USING_PWM3_CH0 + int "PWM3 channel 0 pin number set" + range 0 47 + default 13 + config BSP_USING_PWM3_CH1 + int "PWM3 channel 1 pin number set" + range 0 47 + default 14 + config BSP_USING_PWM3_CH2 + int "PWM3 channel 2 pin number set" + range 0 47 + default 15 + config BSP_USING_PWM3_CH3 + int "PWM3 channel 3 pin number set" + range 0 47 + default 16 + endif + endif + + config BSP_USING_WDT + bool "Enable WDT" + select RT_USING_WDT + default n + + menuconfig BSP_USING_ONCHIP_RTC + bool "Enable RTC" + select RT_USING_RTC + select RT_USING_LIBC + default n + + config BSP_USING_ON_CHIP_FLASH select PKG_USING_FAL bool "Enable on-chip FLASH" default n - menu "On-chip flash config" + menu "MCU flash config" config MCU_FLASH_START_ADDRESS hex "MCU FLASH START ADDRESS" @@ -410,71 +389,20 @@ menu "On-chip Peripheral Drivers" config MCU_FLASH_SIZE_KB int "MCU FLASH SIZE, MAX size 1024 KB" - range 1 1024 - default 1024 + default 1024 config MCU_SRAM_START_ADDRESS hex "MCU RAM START ADDRESS" default 0x20000000 - config MCU_SRAM_SIZE_KB - int "MCU RAM SIZE, MAX size 256 KB" - range 1 256 + config MCU_SRAM_SIZE_KB + int "MCU RAM SIZE" default 256 config MCU_FLASH_PAGE_SIZE hex "MCU FLASH PAGE SIZE, please not change,nrfx default is 0x1000" - range 0x1000 0x1000 default 0x1000 endmenu - config BSP_USING_WDT - bool "Enable WDT" - select RT_USING_WDT - default n - if BSP_USING_WDT - config NRFX_WDT_ENABLED - int - default 1 - config NRFX_WDT0_ENABLED - int - default 1 - config NRFX_WDT_CONFIG_NO_IRQ - int - default 1 - endif - - menuconfig BSP_USING_ONCHIP_RTC - bool "Enable RTC" - select RT_USING_RTC - select RT_USING_LIBC - default n - if BSP_USING_ONCHIP_RTC - config NRFX_CLOCK_ENABLED - int - default 1 - config NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY - int - default 7 - config NRFX_RTC_ENABLED - int - default 1 - config NRFX_RTC0_ENABLED - int - default 1 - config NRFX_RTC1_ENABLED - int - default 1 - config NRFX_RTC2_ENABLED - int - default 1 - config RTC_INSTANCE_ID - int - default 2 - config RTC_INSTANCE_ID - int "select RTC instance id, must be 0, 1, 2" - range 0 2 - default 2 - endif endmenu @@ -497,6 +425,166 @@ config BSP_USING_NIMBLE bool "use nimble stack(iot)" endchoice +if SOC_NORDIC + config NRFX_CLOCK_ENABLED + int + default 1 + config NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY + int + default 7 + config NRFX_CLOCK_CONFIG_LF_SRC + int + default 1 +endif + +if BSP_USING_UART + config NRFX_USING_UART + bool + default y + + config NRFX_UART_ENABLED + int + default 1 +if BSP_USING_UART0 + config NRFX_UART0_ENABLED + int + default 1 +endif + +if NRFX_USING_UART + config NRFX_UART_ENABLED + int + default 1 +endif + +if NRFX_USING_UARTE + config NRFX_UARTE0_ENABLED + int + default 1 +endif + + +endif + +if BSP_USING_GPIO + config NRFX_GPIOTE_ENABLED + int + default 1 +endif + +if BSP_USING_SAADC + config NRFX_SAADC_ENABLED + int + default 1 +endif + +if BSP_USING_I2C + config NRFX_TWIM_ENABLED + int + default 1 + if BSP_USING_I2C0 + config NRFX_TWIM0_ENABLED + int + default 1 + endif + + if BSP_USING_I2C1 + config NRFX_TWIM1_ENABLED + int + default 1 + endif +endif + +if BSP_USING_SPI + config NRFX_SPI_ENABLED + int + default 1 + + if BSP_USING_SPI0 + config NRFX_SPI0_ENABLED + int + default 1 + endif + + if BSP_USING_SPI1 + config NRFX_SPI1_ENABLED + int + default 1 + endif + + if BSP_USING_SPI2 + config NRFX_SPI2_ENABLED + int + default 1 + endif +endif + +if BSP_USING_PWM + config NRFX_PWM_ENABLED + int + default 1 + if BSP_USING_PWM0 + config NRFX_PWM0_ENABLED + int + default 1 + endif + if BSP_USING_PWM1 + config NRFX_PWM1_ENABLED + int + default 1 + endif + if BSP_USING_PWM2 + config NRFX_PWM2_ENABLED + int + default 1 + endif + if BSP_USING_PWM3 + config NRFX_PWM3_ENABLED + int + default 1 + endif + +endif + +if BSP_USING_WDT + config NRFX_WDT_ENABLED + int + default 1 + config NRFX_WDT0_ENABLED + int + default 1 + config NRFX_WDT_CONFIG_NO_IRQ + int + default 1 +endif + +if BSP_USING_ONCHIP_RTC + config NRFX_CLOCK_ENABLED + int + default 1 + config NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY + int + default 7 + config NRFX_RTC_ENABLED + int + default 1 + config NRFX_RTC0_ENABLED + int + default 1 + config NRFX_RTC1_ENABLED + int + default 1 + config NRFX_RTC2_ENABLED + int + default 1 + config RTC_INSTANCE_ID + int + default 2 + config RTC_INSTANCE_ID + int + range 0 2 + default 2 +endif endmenu diff --git a/bsp/nrf5x/nrf52840/board/SConscript b/bsp/nrf5x/nrf52840/board/SConscript index 27bcddd310..d74f1a8861 100644 --- a/bsp/nrf5x/nrf52840/board/SConscript +++ b/bsp/nrf5x/nrf52840/board/SConscript @@ -5,7 +5,6 @@ from building import * cwd = GetCurrentDir() src = Glob('*.c') CPPPATH = [cwd] -define = ['USE_APP_CONFIG'] -group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH,CPPDEFINES = define) +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/bsp/nrf5x/nrf52840/board/app_config.h b/bsp/nrf5x/nrf52840/board/app_config.h deleted file mode 100644 index 67db2eb886..0000000000 --- a/bsp/nrf5x/nrf52840/board/app_config.h +++ /dev/null @@ -1,4 +0,0 @@ -#ifndef APP_CONFIG_H -#define APP_CONFIG_H - -#endif //APP_CONFIG_H diff --git a/bsp/nrf5x/nrf52840/board/board.c b/bsp/nrf5x/nrf52840/board/board.c index 2cb94fb6fa..7adafe36fe 100644 --- a/bsp/nrf5x/nrf52840/board/board.c +++ b/bsp/nrf5x/nrf52840/board/board.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2020-04-29 supperthomas first version + * 2020-04-29 supperthomas fix component init * */ #include @@ -72,6 +73,7 @@ void rt_hw_board_init(void) rt_components_board_init(); #endif + #ifdef BSP_USING_SOFTDEVICE extern uint32_t Image$$RW_IRAM1$$Base; uint32_t const *const m_ram_start = &Image$$RW_IRAM1$$Base; diff --git a/bsp/nrf5x/nrf52840/board/board.h b/bsp/nrf5x/nrf52840/board/board.h index a3ccadfa36..edfb0b635a 100644 --- a/bsp/nrf5x/nrf52840/board/board.h +++ b/bsp/nrf5x/nrf52840/board/board.h @@ -1,3 +1,13 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-19 supperthomas first version + * + */ #ifndef _BOARD_H_ #define _BOARD_H_ diff --git a/bsp/nrf5x/nrf52840/board/linker_scripts/link.lds b/bsp/nrf5x/nrf52840/board/linker_scripts/link.lds index 9a9609eed7..e699e0079a 100644 --- a/bsp/nrf5x/nrf52840/board/linker_scripts/link.lds +++ b/bsp/nrf5x/nrf52840/board/linker_scripts/link.lds @@ -7,10 +7,153 @@ MEMORY { FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x100000 RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x40000 - CODE_RAM (rwx) : ORIGIN = 0x800000, LENGTH = 0x10000 } -INCLUDE "packages/nrfx-v2.1.0/mdk/nrf_common.ld" +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(4); + + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + PROVIDE(end = .); + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + /* Check if text sections + data exceeds FLASH limit */ + DataInitFlashUsed = __bss_start__ - __data_start__; + CodeFlashUsed = __etext - ORIGIN(FLASH); + TotalFlashUsed = CodeFlashUsed + DataInitFlashUsed; + ASSERT(TotalFlashUsed <= LENGTH(FLASH), "region FLASH overflowed with .data and user data") + +} + diff --git a/bsp/nrf5x/nrf52840/board/sdk_config.h b/bsp/nrf5x/nrf52840/board/sdk_config.h index d62c024da3..25fa4938fa 100644 --- a/bsp/nrf5x/nrf52840/board/sdk_config.h +++ b/bsp/nrf5x/nrf52840/board/sdk_config.h @@ -43,9 +43,6 @@ #ifndef SDK_CONFIG_H #define SDK_CONFIG_H // <<< Use Configuration Wizard in Context Menu >>>\n -#ifdef USE_APP_CONFIG -#include "app_config.h" -#endif // nRF_BLE #include diff --git a/bsp/nrf5x/nrf52840/project.uvoptx b/bsp/nrf5x/nrf52840/project.uvoptx index ff162faafb..7bc32642ff 100644 --- a/bsp/nrf5x/nrf52840/project.uvoptx +++ b/bsp/nrf5x/nrf52840/project.uvoptx @@ -10,7 +10,7 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc + *.txt; *.h; *.inc; *.md *.plm *.cpp 0 @@ -73,7 +73,7 @@ 0 - 1 + 0 0 1 @@ -182,7 +182,7 @@ - Kernel + Applications 0 0 0 @@ -194,182 +194,6 @@ 0 0 0 - ..\..\..\src\clock.c - clock.c - 0 - 0 - - - 1 - 2 - 1 - 0 - 0 - 0 - ..\..\..\src\components.c - components.c - 0 - 0 - - - 1 - 3 - 1 - 0 - 0 - 0 - ..\..\..\src\device.c - device.c - 0 - 0 - - - 1 - 4 - 1 - 0 - 0 - 0 - ..\..\..\src\idle.c - idle.c - 0 - 0 - - - 1 - 5 - 1 - 0 - 0 - 0 - ..\..\..\src\ipc.c - ipc.c - 0 - 0 - - - 1 - 6 - 1 - 0 - 0 - 0 - ..\..\..\src\irq.c - irq.c - 0 - 0 - - - 1 - 7 - 1 - 0 - 0 - 0 - ..\..\..\src\kservice.c - kservice.c - 0 - 0 - - - 1 - 8 - 1 - 0 - 0 - 0 - ..\..\..\src\mem.c - mem.c - 0 - 0 - - - 1 - 9 - 1 - 0 - 0 - 0 - ..\..\..\src\mempool.c - mempool.c - 0 - 0 - - - 1 - 10 - 1 - 0 - 0 - 0 - ..\..\..\src\object.c - object.c - 0 - 0 - - - 1 - 11 - 1 - 0 - 0 - 0 - ..\..\..\src\scheduler.c - scheduler.c - 0 - 0 - - - 1 - 12 - 1 - 0 - 0 - 0 - ..\..\..\src\signal.c - signal.c - 0 - 0 - - - 1 - 13 - 1 - 0 - 0 - 0 - ..\..\..\src\thread.c - thread.c - 0 - 0 - - - 1 - 14 - 1 - 0 - 0 - 0 - ..\..\..\src\timer.c - timer.c - 0 - 0 - - - - - Applications - 0 - 0 - 0 - 0 - - 2 - 15 - 1 - 0 - 0 - 0 applications\application.c application.c 0 @@ -378,522 +202,14 @@ - Drivers + CPU 0 0 0 0 - 3 - 16 - 1 - 0 - 0 - 0 - board\board.c - board.c - 0 - 0 - - - 3 - 17 - 1 - 0 - 0 - 0 - ..\libraries\drivers\drv_uart.c - drv_uart.c - 0 - 0 - - - - - nrfx - 0 - 0 - 0 - 0 - - 4 - 18 - 1 - 0 - 0 - 0 - packages\nrfx-v2.1.0\drivers\src\nrfx_adc.c - nrfx_adc.c - 0 - 0 - - - 4 - 19 - 1 - 0 - 0 - 0 - packages\nrfx-v2.1.0\drivers\src\nrfx_clock.c - nrfx_clock.c - 0 - 0 - - - 4 - 20 - 1 - 0 - 0 - 0 - packages\nrfx-v2.1.0\drivers\src\nrfx_comp.c - nrfx_comp.c - 0 - 0 - - - 4 - 21 - 1 - 0 - 0 - 0 - packages\nrfx-v2.1.0\drivers\src\nrfx_dppi.c - nrfx_dppi.c - 0 - 0 - - - 4 - 22 - 1 - 0 - 0 - 0 - packages\nrfx-v2.1.0\drivers\src\nrfx_egu.c - nrfx_egu.c - 0 - 0 - - - 4 - 23 - 1 - 0 - 0 - 0 - packages\nrfx-v2.1.0\drivers\src\nrfx_gpiote.c - nrfx_gpiote.c - 0 - 0 - - - 4 - 24 - 1 - 0 - 0 - 0 - packages\nrfx-v2.1.0\drivers\src\nrfx_i2s.c - nrfx_i2s.c - 0 - 0 - - - 4 - 25 - 1 - 0 - 0 - 0 - packages\nrfx-v2.1.0\drivers\src\nrfx_ipc.c - nrfx_ipc.c - 0 - 0 - - - 4 - 26 - 1 - 0 - 0 - 0 - packages\nrfx-v2.1.0\drivers\src\nrfx_lpcomp.c - nrfx_lpcomp.c - 0 - 0 - - - 4 - 27 - 1 - 0 - 0 - 0 - packages\nrfx-v2.1.0\drivers\src\nrfx_nfct.c - nrfx_nfct.c - 0 - 0 - - - 4 - 28 - 1 - 0 - 0 - 0 - packages\nrfx-v2.1.0\drivers\src\nrfx_nvmc.c - nrfx_nvmc.c - 0 - 0 - - - 4 - 29 - 1 - 0 - 0 - 0 - packages\nrfx-v2.1.0\drivers\src\nrfx_pdm.c - nrfx_pdm.c - 0 - 0 - - - 4 - 30 - 1 - 0 - 0 - 0 - packages\nrfx-v2.1.0\drivers\src\nrfx_power.c - nrfx_power.c - 0 - 0 - - - 4 - 31 - 1 - 0 - 0 - 0 - packages\nrfx-v2.1.0\drivers\src\nrfx_ppi.c - nrfx_ppi.c - 0 - 0 - - - 4 - 32 - 1 - 0 - 0 - 0 - packages\nrfx-v2.1.0\drivers\src\nrfx_pwm.c - nrfx_pwm.c - 0 - 0 - - - 4 - 33 - 1 - 0 - 0 - 0 - packages\nrfx-v2.1.0\drivers\src\nrfx_qdec.c - nrfx_qdec.c - 0 - 0 - - - 4 - 34 - 1 - 0 - 0 - 0 - packages\nrfx-v2.1.0\drivers\src\nrfx_qspi.c - nrfx_qspi.c - 0 - 0 - - - 4 - 35 - 1 - 0 - 0 - 0 - packages\nrfx-v2.1.0\drivers\src\nrfx_rng.c - nrfx_rng.c - 0 - 0 - - - 4 - 36 - 1 - 0 - 0 - 0 - packages\nrfx-v2.1.0\drivers\src\nrfx_rtc.c - nrfx_rtc.c - 0 - 0 - - - 4 - 37 - 1 - 0 - 0 - 0 - packages\nrfx-v2.1.0\drivers\src\nrfx_saadc.c - nrfx_saadc.c - 0 - 0 - - - 4 - 38 - 1 - 0 - 0 - 0 - packages\nrfx-v2.1.0\drivers\src\nrfx_spi.c - nrfx_spi.c - 0 - 0 - - - 4 - 39 - 1 - 0 - 0 - 0 - packages\nrfx-v2.1.0\drivers\src\nrfx_spim.c - nrfx_spim.c - 0 - 0 - - - 4 - 40 - 1 - 0 - 0 - 0 - packages\nrfx-v2.1.0\drivers\src\nrfx_spis.c - nrfx_spis.c - 0 - 0 - - - 4 - 41 - 1 - 0 - 0 - 0 - packages\nrfx-v2.1.0\drivers\src\nrfx_systick.c - nrfx_systick.c - 0 - 0 - - - 4 - 42 - 1 - 0 - 0 - 0 - packages\nrfx-v2.1.0\drivers\src\nrfx_temp.c - nrfx_temp.c - 0 - 0 - - - 4 - 43 - 1 - 0 - 0 - 0 - packages\nrfx-v2.1.0\drivers\src\nrfx_timer.c - nrfx_timer.c - 0 - 0 - - - 4 - 44 - 1 - 0 - 0 - 0 - packages\nrfx-v2.1.0\drivers\src\nrfx_twi.c - nrfx_twi.c - 0 - 0 - - - 4 - 45 - 1 - 0 - 0 - 0 - packages\nrfx-v2.1.0\drivers\src\nrfx_twi_twim.c - nrfx_twi_twim.c - 0 - 0 - - - 4 - 46 - 1 - 0 - 0 - 0 - packages\nrfx-v2.1.0\drivers\src\nrfx_twim.c - nrfx_twim.c - 0 - 0 - - - 4 - 47 - 1 - 0 - 0 - 0 - packages\nrfx-v2.1.0\drivers\src\nrfx_twis.c - nrfx_twis.c - 0 - 0 - - - 4 - 48 - 1 - 0 - 0 - 0 - packages\nrfx-v2.1.0\drivers\src\nrfx_uart.c - nrfx_uart.c - 0 - 0 - - - 4 - 49 - 1 - 0 - 0 - 0 - packages\nrfx-v2.1.0\drivers\src\nrfx_uarte.c - nrfx_uarte.c - 0 - 0 - - - 4 - 50 - 1 - 0 - 0 - 0 - packages\nrfx-v2.1.0\drivers\src\nrfx_usbd.c - nrfx_usbd.c - 0 - 0 - - - 4 - 51 - 1 - 0 - 0 - 0 - packages\nrfx-v2.1.0\drivers\src\nrfx_usbreg.c - nrfx_usbreg.c - 0 - 0 - - - 4 - 52 - 1 - 0 - 0 - 0 - packages\nrfx-v2.1.0\drivers\src\nrfx_wdt.c - nrfx_wdt.c - 0 - 0 - - - 4 - 53 - 1 - 0 - 0 - 0 - packages\nrfx-v2.1.0\mdk\system_nrf52840.c - system_nrf52840.c - 0 - 0 - - - 4 - 54 - 2 - 0 - 0 - 0 - packages\nrfx-v2.1.0\mdk\arm_startup_nrf52840.s - arm_startup_nrf52840.s - 0 - 0 - - - - - cpu - 0 - 0 - 0 - 0 - - 5 - 55 - 1 - 0 - 0 - 0 - ..\..\..\libcpu\arm\common\backtrace.c - backtrace.c - 0 - 0 - - - 5 - 56 - 1 - 0 - 0 - 0 - ..\..\..\libcpu\arm\common\div0.c - div0.c - 0 - 0 - - - 5 - 57 + 2 + 2 1 0 0 @@ -904,8 +220,32 @@ 0 - 5 - 58 + 2 + 3 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\div0.c + div0.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\backtrace.c + backtrace.c + 0 + 0 + + + 2 + 5 1 0 0 @@ -916,8 +256,8 @@ 0 - 5 - 59 + 2 + 6 2 0 0 @@ -936,8 +276,8 @@ 0 0 - 6 - 60 + 3 + 7 1 0 0 @@ -948,8 +288,8 @@ 0 - 6 - 61 + 3 + 8 1 0 0 @@ -960,44 +300,20 @@ 0 - 6 - 62 + 3 + 9 1 0 0 0 - ..\..\..\components\drivers\src\completion.c - completion.c + ..\..\..\components\drivers\src\workqueue.c + workqueue.c 0 0 - 6 - 63 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\src\dataqueue.c - dataqueue.c - 0 - 0 - - - 6 - 64 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\src\pipe.c - pipe.c - 0 - 0 - - - 6 - 65 + 3 + 10 1 0 0 @@ -1008,20 +324,20 @@ 0 - 6 - 66 + 3 + 11 1 0 0 0 - ..\..\..\components\drivers\src\ringbuffer.c - ringbuffer.c + ..\..\..\components\drivers\src\completion.c + completion.c 0 0 - 6 - 67 + 3 + 12 1 0 0 @@ -1032,14 +348,82 @@ 0 - 6 - 68 + 3 + 13 1 0 0 0 - ..\..\..\components\drivers\src\workqueue.c - workqueue.c + ..\..\..\components\drivers\src\pipe.c + pipe.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\dataqueue.c + dataqueue.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\ringbuffer.c + ringbuffer.c + 0 + 0 + + + + + Drivers + 0 + 0 + 0 + 0 + + 4 + 16 + 1 + 0 + 0 + 0 + board\board.c + board.c + 0 + 0 + + + 4 + 17 + 1 + 0 + 0 + 0 + ..\libraries\drivers\drv_gpio.c + drv_gpio.c + 0 + 0 + + + 4 + 18 + 1 + 0 + 0 + 0 + ..\libraries\drivers\drv_uart.c + drv_uart.c 0 0 @@ -1052,20 +436,44 @@ 0 0 - 7 - 69 + 5 + 19 1 0 0 0 - ..\..\..\components\finsh\shell.c - shell.c + ..\..\..\components\finsh\finsh_vm.c + finsh_vm.c 0 0 - 7 - 70 + 5 + 20 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\msh.c + msh.c + 0 + 0 + + + 5 + 21 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\finsh_parser.c + finsh_parser.c + 0 + 0 + + + 5 + 22 1 0 0 @@ -1076,70 +484,726 @@ 0 - 7 - 71 + 5 + 23 1 0 0 0 - ..\..\..\components\finsh\msh.c - msh.c + ..\..\..\components\finsh\finsh_node.c + finsh_node.c + 0 + 0 + + + 5 + 24 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\shell.c + shell.c + 0 + 0 + + + 5 + 25 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\finsh_var.c + finsh_var.c + 0 + 0 + + + 5 + 26 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\finsh_compiler.c + finsh_compiler.c + 0 + 0 + + + 5 + 27 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\finsh_heap.c + finsh_heap.c + 0 + 0 + + + 5 + 28 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\finsh_ops.c + finsh_ops.c + 0 + 0 + + + 5 + 29 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\finsh_error.c + finsh_error.c + 0 + 0 + + + 5 + 30 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\finsh_token.c + finsh_token.c + 0 + 0 + + + 5 + 31 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\finsh_init.c + finsh_init.c 0 0 - libc + Kernel 0 0 0 0 - 8 + 6 + 32 + 1 + 0 + 0 + 0 + ..\..\..\src\scheduler.c + scheduler.c + 0 + 0 + + + 6 + 33 + 1 + 0 + 0 + 0 + ..\..\..\src\device.c + device.c + 0 + 0 + + + 6 + 34 + 1 + 0 + 0 + 0 + ..\..\..\src\kservice.c + kservice.c + 0 + 0 + + + 6 + 35 + 1 + 0 + 0 + 0 + ..\..\..\src\mem.c + mem.c + 0 + 0 + + + 6 + 36 + 1 + 0 + 0 + 0 + ..\..\..\src\clock.c + clock.c + 0 + 0 + + + 6 + 37 + 1 + 0 + 0 + 0 + ..\..\..\src\timer.c + timer.c + 0 + 0 + + + 6 + 38 + 1 + 0 + 0 + 0 + ..\..\..\src\irq.c + irq.c + 0 + 0 + + + 6 + 39 + 1 + 0 + 0 + 0 + ..\..\..\src\ipc.c + ipc.c + 0 + 0 + + + 6 + 40 + 1 + 0 + 0 + 0 + ..\..\..\src\mempool.c + mempool.c + 0 + 0 + + + 6 + 41 + 1 + 0 + 0 + 0 + ..\..\..\src\object.c + object.c + 0 + 0 + + + 6 + 42 + 1 + 0 + 0 + 0 + ..\..\..\src\thread.c + thread.c + 0 + 0 + + + 6 + 43 + 1 + 0 + 0 + 0 + ..\..\..\src\components.c + components.c + 0 + 0 + + + 6 + 44 + 1 + 0 + 0 + 0 + ..\..\..\src\idle.c + idle.c + 0 + 0 + + + + + nrfx + 0 + 0 + 0 + 0 + + 7 + 45 + 1 + 0 + 0 + 0 + packages\nrfx-latest\drivers\src\nrfx_qdec.c + nrfx_qdec.c + 0 + 0 + + + 7 + 46 + 1 + 0 + 0 + 0 + packages\nrfx-latest\drivers\src\nrfx_systick.c + nrfx_systick.c + 0 + 0 + + + 7 + 47 + 1 + 0 + 0 + 0 + packages\nrfx-latest\drivers\src\nrfx_dppi.c + nrfx_dppi.c + 0 + 0 + + + 7 + 48 + 1 + 0 + 0 + 0 + packages\nrfx-latest\drivers\src\nrfx_pdm.c + nrfx_pdm.c + 0 + 0 + + + 7 + 49 + 1 + 0 + 0 + 0 + packages\nrfx-latest\drivers\src\nrfx_ipc.c + nrfx_ipc.c + 0 + 0 + + + 7 + 50 + 1 + 0 + 0 + 0 + packages\nrfx-latest\drivers\src\nrfx_twi_twim.c + nrfx_twi_twim.c + 0 + 0 + + + 7 + 51 + 1 + 0 + 0 + 0 + packages\nrfx-latest\drivers\src\nrfx_egu.c + nrfx_egu.c + 0 + 0 + + + 7 + 52 + 1 + 0 + 0 + 0 + packages\nrfx-latest\drivers\src\nrfx_qspi.c + nrfx_qspi.c + 0 + 0 + + + 7 + 53 + 1 + 0 + 0 + 0 + packages\nrfx-latest\drivers\src\nrfx_spis.c + nrfx_spis.c + 0 + 0 + + + 7 + 54 + 1 + 0 + 0 + 0 + packages\nrfx-latest\drivers\src\nrfx_lpcomp.c + nrfx_lpcomp.c + 0 + 0 + + + 7 + 55 + 1 + 0 + 0 + 0 + packages\nrfx-latest\drivers\src\nrfx_temp.c + nrfx_temp.c + 0 + 0 + + + 7 + 56 + 1 + 0 + 0 + 0 + packages\nrfx-latest\drivers\src\nrfx_wdt.c + nrfx_wdt.c + 0 + 0 + + + 7 + 57 + 1 + 0 + 0 + 0 + packages\nrfx-latest\drivers\src\nrfx_twim.c + nrfx_twim.c + 0 + 0 + + + 7 + 58 + 2 + 0 + 0 + 0 + packages\nrfx-latest\mdk\arm_startup_nrf52840.s + arm_startup_nrf52840.s + 0 + 0 + + + 7 + 59 + 1 + 0 + 0 + 0 + packages\nrfx-latest\drivers\src\nrfx_power.c + nrfx_power.c + 0 + 0 + + + 7 + 60 + 1 + 0 + 0 + 0 + packages\nrfx-latest\drivers\src\nrfx_timer.c + nrfx_timer.c + 0 + 0 + + + 7 + 61 + 1 + 0 + 0 + 0 + packages\nrfx-latest\drivers\src\nrfx_nvmc.c + nrfx_nvmc.c + 0 + 0 + + + 7 + 62 + 1 + 0 + 0 + 0 + packages\nrfx-latest\drivers\src\nrfx_ppi.c + nrfx_ppi.c + 0 + 0 + + + 7 + 63 + 1 + 0 + 0 + 0 + packages\nrfx-latest\drivers\src\nrfx_spim.c + nrfx_spim.c + 0 + 0 + + + 7 + 64 + 1 + 0 + 0 + 0 + packages\nrfx-latest\drivers\src\nrfx_comp.c + nrfx_comp.c + 0 + 0 + + + 7 + 65 + 1 + 0 + 0 + 0 + packages\nrfx-latest\drivers\src\nrfx_rtc.c + nrfx_rtc.c + 0 + 0 + + + 7 + 66 + 1 + 0 + 0 + 0 + packages\nrfx-latest\drivers\src\nrfx_twi.c + nrfx_twi.c + 0 + 0 + + + 7 + 67 + 1 + 0 + 0 + 0 + packages\nrfx-latest\drivers\src\nrfx_usbreg.c + nrfx_usbreg.c + 0 + 0 + + + 7 + 68 + 1 + 0 + 0 + 0 + packages\nrfx-latest\drivers\src\nrfx_clock.c + nrfx_clock.c + 0 + 0 + + + 7 + 69 + 1 + 0 + 0 + 0 + packages\nrfx-latest\drivers\src\nrfx_i2s.c + nrfx_i2s.c + 0 + 0 + + + 7 + 70 + 1 + 0 + 0 + 0 + packages\nrfx-latest\drivers\src\nrfx_twis.c + nrfx_twis.c + 0 + 0 + + + 7 + 71 + 1 + 0 + 0 + 0 + packages\nrfx-latest\drivers\src\nrfx_adc.c + nrfx_adc.c + 0 + 0 + + + 7 72 1 0 0 0 - ..\..\..\components\libc\compilers\armlibc\libc.c - libc.c + packages\nrfx-latest\drivers\src\nrfx_rng.c + nrfx_rng.c 0 0 - 8 + 7 73 1 0 0 0 - ..\..\..\components\libc\compilers\armlibc\mem_std.c - mem_std.c + packages\nrfx-latest\drivers\src\nrfx_usbd.c + nrfx_usbd.c 0 0 - 8 + 7 74 1 0 0 0 - ..\..\..\components\libc\compilers\armlibc\stubs.c - stubs.c + packages\nrfx-latest\drivers\src\nrfx_uart.c + nrfx_uart.c 0 0 - 8 + 7 75 1 0 0 0 - ..\..\..\components\libc\compilers\common\time.c - time.c + packages\nrfx-latest\mdk\system_nrf52840.c + system_nrf52840.c + 0 + 0 + + + 7 + 76 + 1 + 0 + 0 + 0 + packages\nrfx-latest\drivers\src\nrfx_saadc.c + nrfx_saadc.c + 0 + 0 + + + 7 + 77 + 1 + 0 + 0 + 0 + packages\nrfx-latest\drivers\src\nrfx_nfct.c + nrfx_nfct.c + 0 + 0 + + + 7 + 78 + 1 + 0 + 0 + 0 + packages\nrfx-latest\drivers\src\nrfx_gpiote.c + nrfx_gpiote.c + 0 + 0 + + + 7 + 79 + 1 + 0 + 0 + 0 + packages\nrfx-latest\drivers\src\nrfx_spi.c + nrfx_spi.c + 0 + 0 + + + 7 + 80 + 1 + 0 + 0 + 0 + packages\nrfx-latest\drivers\src\nrfx_uarte.c + nrfx_uarte.c + 0 + 0 + + + 7 + 81 + 1 + 0 + 0 + 0 + packages\nrfx-latest\drivers\src\nrfx_pwm.c + nrfx_pwm.c 0 0 diff --git a/bsp/nrf5x/nrf52840/project.uvprojx b/bsp/nrf5x/nrf52840/project.uvprojx index b1bf5b73cf..69017ec490 100644 --- a/bsp/nrf5x/nrf52840/project.uvprojx +++ b/bsp/nrf5x/nrf52840/project.uvprojx @@ -10,13 +10,13 @@ rtthread 0x4 ARM-ADS - 5060750::V5.06 update 6 (build 750)::ARMCC + 5060422::V5.06 update 4 (build 422)::ARMCC 0 nRF52840_xxAA Nordic Semiconductor - NordicSemiconductor.nRF_DeviceFamilyPack.8.32.1 + NordicSemiconductor.nRF_DeviceFamilyPack.8.38.0 http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/ IRAM(0x20000000,0x40000) IROM(0x00000000,0x100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -185,6 +185,7 @@ 0 2 0 + 0 0 0 8 @@ -336,9 +337,9 @@ 0 --reduce_paths - NRF52840_XXAA, USE_APP_CONFIG, RT_USING_ARM_LIBC + NRF52840_XXAA, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND - .;..\..\..\include;applications;.;board;..\libraries\drivers;packages\nrfx-v2.1.0;packages\nrfx-v2.1.0\drivers;packages\nrfx-v2.1.0\drivers\include;packages\nrfx-v2.1.0\mdk;packages\nrfx-v2.1.0\hal;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\armlibc;..\..\..\components\libc\compilers\common;..\libraries\cmsis\include + applications;.;..\libraries\cmsis\include;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;..\libraries\drivers;..\..\..\components\finsh;.;..\..\..\include;..\..\..\components\libc\compilers\common;..\..\..\components\libc\compilers\common\none-gcc;packages\nrfx-latest;packages\nrfx-latest\drivers;packages\nrfx-latest\drivers\include;packages\nrfx-latest\mdk;packages\nrfx-latest\hal;packages\SEGGER_RTT-v1.1.0;packages\SEGGER_RTT-v1.1.0\RTT;..\..\..\examples\utest\testcases\kernel @@ -351,16 +352,16 @@ 0 0 0 - 0 + 4 - --cpreproc_opts=-DBLE_STACK_SUPPORT_REQD,-DNRF_SD_BLE_API_VERSION=4,-DS132,-DSOFTDEVICE_PRESENT,-DSWI_DISABLE0,-DCONFIG_GPIO_AS_PINRESET,-DNRF52,-DNRF52832_XXAA,-DNRF52_PAN_12,-DNRF52_PAN_15,-DNRF52_PAN_20,-DNRF52_PAN_31,-DNRF52_PAN_36,-DNRF52_PAN_51,-DNRF52_PAN_54,-DNRF52_PAN_55,-DNRF52_PAN_58,-DNRF52_PAN_64,-DNRF52_PAN_74 + - 1 + 0 0 0 0 @@ -369,7 +370,7 @@ 0x00000000 0x20000000 - + .\board\linker_scripts\link.sct @@ -379,81 +380,6 @@ - - Kernel - - - clock.c - 1 - ..\..\..\src\clock.c - - - components.c - 1 - ..\..\..\src\components.c - - - device.c - 1 - ..\..\..\src\device.c - - - idle.c - 1 - ..\..\..\src\idle.c - - - ipc.c - 1 - ..\..\..\src\ipc.c - - - irq.c - 1 - ..\..\..\src\irq.c - - - kservice.c - 1 - ..\..\..\src\kservice.c - - - mem.c - 1 - ..\..\..\src\mem.c - - - mempool.c - 1 - ..\..\..\src\mempool.c - - - object.c - 1 - ..\..\..\src\object.c - - - scheduler.c - 1 - ..\..\..\src\scheduler.c - - - signal.c - 1 - ..\..\..\src\signal.c - - - thread.c - 1 - ..\..\..\src\thread.c - - - timer.c - 1 - ..\..\..\src\timer.c - - - Applications @@ -465,217 +391,12 @@ - Drivers + CPU - board.c + showmem.c 1 - board\board.c - - - drv_uart.c - 1 - ..\libraries\drivers\drv_uart.c - - - - - nrfx - - - nrfx_adc.c - 1 - packages\nrfx-v2.1.0\drivers\src\nrfx_adc.c - - - nrfx_clock.c - 1 - packages\nrfx-v2.1.0\drivers\src\nrfx_clock.c - - - nrfx_comp.c - 1 - packages\nrfx-v2.1.0\drivers\src\nrfx_comp.c - - - nrfx_dppi.c - 1 - packages\nrfx-v2.1.0\drivers\src\nrfx_dppi.c - - - nrfx_egu.c - 1 - packages\nrfx-v2.1.0\drivers\src\nrfx_egu.c - - - nrfx_gpiote.c - 1 - packages\nrfx-v2.1.0\drivers\src\nrfx_gpiote.c - - - nrfx_i2s.c - 1 - packages\nrfx-v2.1.0\drivers\src\nrfx_i2s.c - - - nrfx_ipc.c - 1 - packages\nrfx-v2.1.0\drivers\src\nrfx_ipc.c - - - nrfx_lpcomp.c - 1 - packages\nrfx-v2.1.0\drivers\src\nrfx_lpcomp.c - - - nrfx_nfct.c - 1 - packages\nrfx-v2.1.0\drivers\src\nrfx_nfct.c - - - nrfx_nvmc.c - 1 - packages\nrfx-v2.1.0\drivers\src\nrfx_nvmc.c - - - nrfx_pdm.c - 1 - packages\nrfx-v2.1.0\drivers\src\nrfx_pdm.c - - - nrfx_power.c - 1 - packages\nrfx-v2.1.0\drivers\src\nrfx_power.c - - - nrfx_ppi.c - 1 - packages\nrfx-v2.1.0\drivers\src\nrfx_ppi.c - - - nrfx_pwm.c - 1 - packages\nrfx-v2.1.0\drivers\src\nrfx_pwm.c - - - nrfx_qdec.c - 1 - packages\nrfx-v2.1.0\drivers\src\nrfx_qdec.c - - - nrfx_qspi.c - 1 - packages\nrfx-v2.1.0\drivers\src\nrfx_qspi.c - - - nrfx_rng.c - 1 - packages\nrfx-v2.1.0\drivers\src\nrfx_rng.c - - - nrfx_rtc.c - 1 - packages\nrfx-v2.1.0\drivers\src\nrfx_rtc.c - - - nrfx_saadc.c - 1 - packages\nrfx-v2.1.0\drivers\src\nrfx_saadc.c - - - nrfx_spi.c - 1 - packages\nrfx-v2.1.0\drivers\src\nrfx_spi.c - - - nrfx_spim.c - 1 - packages\nrfx-v2.1.0\drivers\src\nrfx_spim.c - - - nrfx_spis.c - 1 - packages\nrfx-v2.1.0\drivers\src\nrfx_spis.c - - - nrfx_systick.c - 1 - packages\nrfx-v2.1.0\drivers\src\nrfx_systick.c - - - nrfx_temp.c - 1 - packages\nrfx-v2.1.0\drivers\src\nrfx_temp.c - - - nrfx_timer.c - 1 - packages\nrfx-v2.1.0\drivers\src\nrfx_timer.c - - - nrfx_twi.c - 1 - packages\nrfx-v2.1.0\drivers\src\nrfx_twi.c - - - nrfx_twi_twim.c - 1 - packages\nrfx-v2.1.0\drivers\src\nrfx_twi_twim.c - - - nrfx_twim.c - 1 - packages\nrfx-v2.1.0\drivers\src\nrfx_twim.c - - - nrfx_twis.c - 1 - packages\nrfx-v2.1.0\drivers\src\nrfx_twis.c - - - nrfx_uart.c - 1 - packages\nrfx-v2.1.0\drivers\src\nrfx_uart.c - - - nrfx_uarte.c - 1 - packages\nrfx-v2.1.0\drivers\src\nrfx_uarte.c - - - nrfx_usbd.c - 1 - packages\nrfx-v2.1.0\drivers\src\nrfx_usbd.c - - - nrfx_usbreg.c - 1 - packages\nrfx-v2.1.0\drivers\src\nrfx_usbreg.c - - - nrfx_wdt.c - 1 - packages\nrfx-v2.1.0\drivers\src\nrfx_wdt.c - - - system_nrf52840.c - 1 - packages\nrfx-v2.1.0\mdk\system_nrf52840.c - - - arm_startup_nrf52840.s - 2 - packages\nrfx-v2.1.0\mdk\arm_startup_nrf52840.s - - - - - cpu - - - backtrace.c - 1 - ..\..\..\libcpu\arm\common\backtrace.c + ..\..\..\libcpu\arm\common\showmem.c div0.c @@ -683,9 +404,9 @@ ..\..\..\libcpu\arm\common\div0.c - showmem.c + backtrace.c 1 - ..\..\..\libcpu\arm\common\showmem.c + ..\..\..\libcpu\arm\common\backtrace.c cpuport.c @@ -713,19 +434,9 @@ ..\..\..\components\drivers\serial\serial.c - completion.c + workqueue.c 1 - ..\..\..\components\drivers\src\completion.c - - - dataqueue.c - 1 - ..\..\..\components\drivers\src\dataqueue.c - - - pipe.c - 1 - ..\..\..\components\drivers\src\pipe.c + ..\..\..\components\drivers\src\workqueue.c ringblk_buf.c @@ -733,9 +444,9 @@ ..\..\..\components\drivers\src\ringblk_buf.c - ringbuffer.c + completion.c 1 - ..\..\..\components\drivers\src\ringbuffer.c + ..\..\..\components\drivers\src\completion.c waitqueue.c @@ -743,9 +454,39 @@ ..\..\..\components\drivers\src\waitqueue.c - workqueue.c + pipe.c 1 - ..\..\..\components\drivers\src\workqueue.c + ..\..\..\components\drivers\src\pipe.c + + + dataqueue.c + 1 + ..\..\..\components\drivers\src\dataqueue.c + + + ringbuffer.c + 1 + ..\..\..\components\drivers\src\ringbuffer.c + + + + + Drivers + + + board.c + 1 + board\board.c + + + drv_gpio.c + 1 + ..\libraries\drivers\drv_gpio.c + + + drv_uart.c + 1 + ..\libraries\drivers\drv_uart.c @@ -753,9 +494,19 @@ finsh - shell.c + finsh_vm.c 1 - ..\..\..\components\finsh\shell.c + ..\..\..\components\finsh\finsh_vm.c + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + finsh_parser.c + 1 + ..\..\..\components\finsh\finsh_parser.c cmd.c @@ -763,34 +514,309 @@ ..\..\..\components\finsh\cmd.c - msh.c + finsh_node.c 1 - ..\..\..\components\finsh\msh.c + ..\..\..\components\finsh\finsh_node.c + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + finsh_var.c + 1 + ..\..\..\components\finsh\finsh_var.c + + + finsh_compiler.c + 1 + ..\..\..\components\finsh\finsh_compiler.c + + + finsh_heap.c + 1 + ..\..\..\components\finsh\finsh_heap.c + + + finsh_ops.c + 1 + ..\..\..\components\finsh\finsh_ops.c + + + finsh_error.c + 1 + ..\..\..\components\finsh\finsh_error.c + + + finsh_token.c + 1 + ..\..\..\components\finsh\finsh_token.c + + + finsh_init.c + 1 + ..\..\..\components\finsh\finsh_init.c - libc + Kernel - libc.c + scheduler.c 1 - ..\..\..\components\libc\compilers\armlibc\libc.c + ..\..\..\src\scheduler.c - mem_std.c + device.c 1 - ..\..\..\components\libc\compilers\armlibc\mem_std.c + ..\..\..\src\device.c - stubs.c + kservice.c 1 - ..\..\..\components\libc\compilers\armlibc\stubs.c + ..\..\..\src\kservice.c - time.c + mem.c 1 - ..\..\..\components\libc\compilers\common\time.c + ..\..\..\src\mem.c + + + clock.c + 1 + ..\..\..\src\clock.c + + + timer.c + 1 + ..\..\..\src\timer.c + + + irq.c + 1 + ..\..\..\src\irq.c + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + object.c + 1 + ..\..\..\src\object.c + + + thread.c + 1 + ..\..\..\src\thread.c + + + components.c + 1 + ..\..\..\src\components.c + + + idle.c + 1 + ..\..\..\src\idle.c + + + + + nrfx + + + nrfx_qdec.c + 1 + packages\nrfx-latest\drivers\src\nrfx_qdec.c + + + nrfx_systick.c + 1 + packages\nrfx-latest\drivers\src\nrfx_systick.c + + + nrfx_dppi.c + 1 + packages\nrfx-latest\drivers\src\nrfx_dppi.c + + + nrfx_pdm.c + 1 + packages\nrfx-latest\drivers\src\nrfx_pdm.c + + + nrfx_ipc.c + 1 + packages\nrfx-latest\drivers\src\nrfx_ipc.c + + + nrfx_twi_twim.c + 1 + packages\nrfx-latest\drivers\src\nrfx_twi_twim.c + + + nrfx_egu.c + 1 + packages\nrfx-latest\drivers\src\nrfx_egu.c + + + nrfx_qspi.c + 1 + packages\nrfx-latest\drivers\src\nrfx_qspi.c + + + nrfx_spis.c + 1 + packages\nrfx-latest\drivers\src\nrfx_spis.c + + + nrfx_lpcomp.c + 1 + packages\nrfx-latest\drivers\src\nrfx_lpcomp.c + + + nrfx_temp.c + 1 + packages\nrfx-latest\drivers\src\nrfx_temp.c + + + nrfx_wdt.c + 1 + packages\nrfx-latest\drivers\src\nrfx_wdt.c + + + nrfx_twim.c + 1 + packages\nrfx-latest\drivers\src\nrfx_twim.c + + + arm_startup_nrf52840.s + 2 + packages\nrfx-latest\mdk\arm_startup_nrf52840.s + + + nrfx_power.c + 1 + packages\nrfx-latest\drivers\src\nrfx_power.c + + + nrfx_timer.c + 1 + packages\nrfx-latest\drivers\src\nrfx_timer.c + + + nrfx_nvmc.c + 1 + packages\nrfx-latest\drivers\src\nrfx_nvmc.c + + + nrfx_ppi.c + 1 + packages\nrfx-latest\drivers\src\nrfx_ppi.c + + + nrfx_spim.c + 1 + packages\nrfx-latest\drivers\src\nrfx_spim.c + + + nrfx_comp.c + 1 + packages\nrfx-latest\drivers\src\nrfx_comp.c + + + nrfx_rtc.c + 1 + packages\nrfx-latest\drivers\src\nrfx_rtc.c + + + nrfx_twi.c + 1 + packages\nrfx-latest\drivers\src\nrfx_twi.c + + + nrfx_usbreg.c + 1 + packages\nrfx-latest\drivers\src\nrfx_usbreg.c + + + nrfx_clock.c + 1 + packages\nrfx-latest\drivers\src\nrfx_clock.c + + + nrfx_i2s.c + 1 + packages\nrfx-latest\drivers\src\nrfx_i2s.c + + + nrfx_twis.c + 1 + packages\nrfx-latest\drivers\src\nrfx_twis.c + + + nrfx_adc.c + 1 + packages\nrfx-latest\drivers\src\nrfx_adc.c + + + nrfx_rng.c + 1 + packages\nrfx-latest\drivers\src\nrfx_rng.c + + + nrfx_usbd.c + 1 + packages\nrfx-latest\drivers\src\nrfx_usbd.c + + + nrfx_uart.c + 1 + packages\nrfx-latest\drivers\src\nrfx_uart.c + + + system_nrf52840.c + 1 + packages\nrfx-latest\mdk\system_nrf52840.c + + + nrfx_saadc.c + 1 + packages\nrfx-latest\drivers\src\nrfx_saadc.c + + + nrfx_nfct.c + 1 + packages\nrfx-latest\drivers\src\nrfx_nfct.c + + + nrfx_gpiote.c + 1 + packages\nrfx-latest\drivers\src\nrfx_gpiote.c + + + nrfx_spi.c + 1 + packages\nrfx-latest\drivers\src\nrfx_spi.c + + + nrfx_uarte.c + 1 + packages\nrfx-latest\drivers\src\nrfx_uarte.c + + + nrfx_pwm.c + 1 + packages\nrfx-latest\drivers\src\nrfx_pwm.c diff --git a/bsp/nrf5x/nrf52840/rtconfig.h b/bsp/nrf5x/nrf52840/rtconfig.h index 9f8dc015dd..df606fc98e 100644 --- a/bsp/nrf5x/nrf52840/rtconfig.h +++ b/bsp/nrf5x/nrf52840/rtconfig.h @@ -4,6 +4,41 @@ /* Automatically generated file; DO NOT EDIT. */ /* RT-Thread Configuration */ +/* Hardware Drivers Config */ + +#define SOC_NRF52840 +#define SOC_NORDIC +#define BSP_BOARD_PCA_10056 + +/* Onboard Peripheral Drivers */ + +#define BSP_USING_JLINK_TO_USART +#define RT_BSP_LED_PIN 13 + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define NRFX_USING_UART +#define BSP_USING_UART0 +#define BSP_UART0_RX_PIN 8 +#define BSP_UART0_TX_PIN 6 + +/* MCU flash config */ + +#define MCU_FLASH_START_ADDRESS 0x00000000 +#define MCU_FLASH_SIZE_KB 1024 +#define MCU_SRAM_START_ADDRESS 0x20000000 +#define MCU_SRAM_SIZE_KB 256 +#define MCU_FLASH_PAGE_SIZE 0x1000 +#define BLE_STACK_USING_NULL +#define NRFX_CLOCK_ENABLED 1 +#define NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#define NRFX_CLOCK_CONFIG_LF_SRC 1 +#define NRFX_UART_ENABLED 1 +#define NRFX_UART0_ENABLED 1 +#define NRFX_GPIOTE_ENABLED 1 + /* RT-Thread Kernel */ #define RT_NAME_MAX 8 @@ -11,7 +46,6 @@ #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 #define RT_TICK_PER_SECOND 100 -#define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 @@ -19,15 +53,15 @@ #define RT_USING_TIMER_SOFT #define RT_TIMER_THREAD_PRIO 4 #define RT_TIMER_THREAD_STACK_SIZE 512 -#define RT_DEBUG + +/* kservice optimization */ + /* Inter-Thread communication */ #define RT_USING_SEMAPHORE #define RT_USING_MUTEX #define RT_USING_EVENT -#define RT_USING_MAILBOX -#define RT_USING_MESSAGEQUEUE /* Memory Management */ @@ -41,7 +75,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart0" -#define RT_VER_NUM 0x40003 +#define RT_VER_NUM 0x40004 /* RT-Thread Components */ @@ -66,7 +100,6 @@ #define FINSH_CMD_SIZE 80 #define FINSH_USING_MSH #define FINSH_USING_MSH_DEFAULT -#define FINSH_USING_MSH_ONLY #define FINSH_ARG_MAX 10 /* Device virtual file system */ @@ -85,7 +118,6 @@ /* POSIX layer and C standard library */ -#define RT_USING_LIBC /* Network */ @@ -107,6 +139,9 @@ /* Utilities */ +/* RT-Thread Utestcases */ + + /* RT-Thread online packages */ /* IoT - internet of things */ @@ -137,11 +172,19 @@ /* system packages */ +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + /* peripheral libraries and drivers */ #define PKG_USING_NRFX -#define PKG_USING_NRFX_V210 +#define PKG_USING_NRFX_LATEST_VERSION + +/* AI packages */ + /* miscellaneous packages */ @@ -149,37 +192,7 @@ /* samples: kernel and components samples */ -/* Hardware Drivers Config */ +/* entertainment: terminal games and other interesting software packages */ -#define SOC_NRF52840 -#define NRFX_CLOCK_ENABLED 1 -#define NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#define NRFX_CLOCK_CONFIG_LF_SRC 1 -#define SOC_NORDIC - -/* Onboard Peripheral Drivers */ - -#define BSP_USING_JLINK_TO_USART - -/* On-chip Peripheral Drivers */ - -#define BSP_USING_GPIO -#define NRFX_GPIOTE_ENABLED 1 -#define BSP_USING_UART -#define NRFX_USING_UART -#define NRFX_UART_ENABLED 1 -#define BSP_USING_UART0 -#define NRFX_UART0_ENABLED 1 -#define BSP_UART0_RX_PIN 8 -#define BSP_UART0_TX_PIN 6 - -/* On-chip flash config */ - -#define MCU_FLASH_START_ADDRESS 0x00000000 -#define MCU_FLASH_SIZE_KB 1024 -#define MCU_SRAM_START_ADDRESS 0x20000000 -#define MCU_SRAM_SIZE_KB 256 -#define MCU_FLASH_PAGE_SIZE 0x1000 -#define BLE_STACK_USING_NULL #endif diff --git a/bsp/nrf5x/nrf52840/rtconfig.py b/bsp/nrf5x/nrf52840/rtconfig.py index 4ef29e332f..c809814516 100644 --- a/bsp/nrf5x/nrf52840/rtconfig.py +++ b/bsp/nrf5x/nrf52840/rtconfig.py @@ -40,7 +40,7 @@ if PLATFORM == 'gcc': OBJDUMP = PREFIX + 'objdump' OBJCPY = PREFIX + 'objcopy' - DEVICE = ' -mcpu=cortex-m4 -mthumb -ffunction-sections -fdata-sections' + DEVICE = ' -mcpu='+CPU + ' -mthumb -ffunction-sections -fdata-sections' CFLAGS = DEVICE AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' diff --git a/bsp/nrf5x/nrf52840/template.uvoptx b/bsp/nrf5x/nrf52840/template.uvoptx index f567bf47e8..94da3c0c18 100644 --- a/bsp/nrf5x/nrf52840/template.uvoptx +++ b/bsp/nrf5x/nrf52840/template.uvoptx @@ -10,7 +10,7 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc + *.txt; *.h; *.inc; *.md *.plm *.cpp 0 diff --git a/bsp/nrf5x/nrf52840/template.uvprojx b/bsp/nrf5x/nrf52840/template.uvprojx index 62c5997a13..33ed1f7c16 100644 --- a/bsp/nrf5x/nrf52840/template.uvprojx +++ b/bsp/nrf5x/nrf52840/template.uvprojx @@ -16,7 +16,7 @@ nRF52840_xxAA Nordic Semiconductor - NordicSemiconductor.nRF_DeviceFamilyPack.8.32.1 + NordicSemiconductor.nRF_DeviceFamilyPack.8.38.0 http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/ IRAM(0x20000000,0x40000) IROM(0x00000000,0x100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -185,6 +185,7 @@ 0 2 0 + 0 0 0 8 @@ -336,7 +337,7 @@ 0 --reduce_paths - BLE_STACK_SUPPORT_REQD NRF_SD_BLE_API_VERSION=4 S140 SOFTDEVICE_PRESENT SWI_DISABLE0 CONFIG_GPIO_AS_PINRESET NRF52 NRF52832_XXAA NRF52_PAN_12 NRF52_PAN_15 NRF52_PAN_20 NRF52_PAN_31 NRF52_PAN_36 NRF52_PAN_51 NRF52_PAN_54 NRF52_PAN_55 NRF52_PAN_58 NRF52_PAN_64 NRF52_PAN_74 + @@ -351,16 +352,16 @@ 0 0 0 - 0 + 4 - --cpreproc_opts=-DBLE_STACK_SUPPORT_REQD,-DNRF_SD_BLE_API_VERSION=4,-DS132,-DSOFTDEVICE_PRESENT,-DSWI_DISABLE0,-DCONFIG_GPIO_AS_PINRESET,-DNRF52,-DNRF52832_XXAA,-DNRF52_PAN_12,-DNRF52_PAN_15,-DNRF52_PAN_20,-DNRF52_PAN_31,-DNRF52_PAN_36,-DNRF52_PAN_51,-DNRF52_PAN_54,-DNRF52_PAN_55,-DNRF52_PAN_58,-DNRF52_PAN_64,-DNRF52_PAN_74 + - 1 + 0 0 0 0 @@ -369,7 +370,7 @@ 0x00000000 0x20000000 - + .\board\linker_scripts\link.sct --diag_suppress 6330 diff --git a/bsp/qemu-vexpress-a9/drivers/board.c b/bsp/qemu-vexpress-a9/drivers/board.c index e236c68b80..84af3c1ccd 100644 --- a/bsp/qemu-vexpress-a9/drivers/board.c +++ b/bsp/qemu-vexpress-a9/drivers/board.c @@ -55,3 +55,8 @@ void rt_hw_board_init(void) rt_hw_ipi_handler_install(RT_SCHEDULE_IPI, rt_scheduler_ipi_handler); #endif } + +void rt_hw_us_delay(rt_uint32_t us) +{ + +} diff --git a/bsp/qemu-vexpress-a9/drivers/drv_smc911x.c b/bsp/qemu-vexpress-a9/drivers/drv_smc911x.c index 2b2253328d..9d52b258af 100644 --- a/bsp/qemu-vexpress-a9/drivers/drv_smc911x.c +++ b/bsp/qemu-vexpress-a9/drivers/drv_smc911x.c @@ -33,16 +33,6 @@ struct eth_device_smc911x }; static struct eth_device_smc911x _emac; -int udelay(int value) -{ - return 0; -} - -int mdelay(int value) -{ - return 0; -} - #if defined (CONFIG_SMC911X_32_BIT) rt_inline uint32_t smc911x_reg_read(struct eth_device_smc911x *dev, uint32_t offset) { diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_eth.c b/bsp/raspberry-pi/raspi4-32/driver/drv_eth.c index 58683b422d..163f58c150 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/drv_eth.c +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_eth.c @@ -1,6 +1,6 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2020, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -19,8 +19,6 @@ #include "raspi4.h" #include "drv_eth.h" -//#define ETH_RX_POLL - #define DBG_LEVEL DBG_LOG #include #define LOG_TAG "drv.eth" @@ -28,13 +26,12 @@ static int link_speed = 0; static int link_flag = 0; -#define RECV_CACHE_BUF (1024) -#define SEND_DATA_NO_CACHE (0x08200000) -#define RECV_DATA_NO_CACHE (0x08400000) -#define DMA_DISC_ADDR_SIZE (4 * 1024 *1024) +#define RECV_CACHE_BUF (2048) +#define SEND_CACHE_BUF (2048) +#define DMA_DISC_ADDR_SIZE (2 * 1024 *1024) -#define RX_DESC_BASE (MAC_REG + GENET_RX_OFF) -#define TX_DESC_BASE (MAC_REG + GENET_TX_OFF) +#define RX_DESC_BASE (mac_reg_base_addr + GENET_RX_OFF) +#define TX_DESC_BASE (mac_reg_base_addr + GENET_TX_OFF) #define MAX_ADDR_LEN (6) @@ -48,11 +45,11 @@ static rt_thread_t link_thread_tid = RT_NULL; #define LINK_THREAD_PRIORITY (20) #define LINK_THREAD_TIMESLICE (10) + static rt_uint32_t tx_index = 0; static rt_uint32_t rx_index = 0; static rt_uint32_t index_flag = 0; -static rt_uint32_t send_cache_pbuf[RECV_CACHE_BUF]; struct rt_eth_dev { @@ -63,11 +60,12 @@ struct rt_eth_dev int state; int index; struct rt_timer link_timer; - struct rt_timer rx_poll_timer; void *priv; }; static struct rt_eth_dev eth_dev; -static struct rt_semaphore sem_lock; + +static struct rt_semaphore send_finsh_sem_lock; + static struct rt_semaphore link_ack; static inline rt_uint32_t read32(void *addr) @@ -80,13 +78,18 @@ static inline void write32(void *addr, rt_uint32_t value) (*((volatile unsigned int*)(addr))) = value; } + + + static void eth_rx_irq(int irq, void *param) { -#ifndef ETH_RX_POLL rt_uint32_t val = 0; - val = read32(MAC_REG + GENET_INTRL2_CPU_STAT); - val &= ~read32(MAC_REG + GENET_INTRL2_CPU_STAT_MASK); - write32(MAC_REG + GENET_INTRL2_CPU_CLEAR, val); + + val = read32(mac_reg_base_addr + GENET_INTRL2_CPU_STAT); + val &= ~read32(mac_reg_base_addr + GENET_INTRL2_CPU_STAT_MASK); + + write32(mac_reg_base_addr + GENET_INTRL2_CPU_CLEAR, val); + if (val & GENET_IRQ_RXDMA_DONE) { eth_device_ready(ð_dev.parent); @@ -94,11 +97,8 @@ static void eth_rx_irq(int irq, void *param) if (val & GENET_IRQ_TXDMA_DONE) { - //todo + rt_sem_release(&send_finsh_sem_lock); } -#else - eth_device_ready(ð_dev.parent); -#endif } /* We only support RGMII (as used on the RPi4). */ @@ -109,10 +109,11 @@ static int bcmgenet_interface_set(void) { case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII_RXID: - write32(MAC_REG + SYS_PORT_CTRL, PORT_MODE_EXT_GPHY); + write32(mac_reg_base_addr + SYS_PORT_CTRL, PORT_MODE_EXT_GPHY); break; + default: - rt_kprintf("unknown phy mode: %d\n", MAC_REG); + rt_kprintf("unknown phy mode: %d\n", mac_reg_base_addr); return -1; } return 0; @@ -121,44 +122,48 @@ static int bcmgenet_interface_set(void) static void bcmgenet_umac_reset(void) { rt_uint32_t reg; - reg = read32(MAC_REG + SYS_RBUF_FLUSH_CTRL); + reg = read32(mac_reg_base_addr + SYS_RBUF_FLUSH_CTRL); reg |= BIT(1); - write32((MAC_REG + SYS_RBUF_FLUSH_CTRL), reg); + write32((mac_reg_base_addr + SYS_RBUF_FLUSH_CTRL), reg); reg &= ~BIT(1); - write32((MAC_REG + SYS_RBUF_FLUSH_CTRL), reg); + write32((mac_reg_base_addr + SYS_RBUF_FLUSH_CTRL), reg); DELAY_MICROS(10); - write32((MAC_REG + SYS_RBUF_FLUSH_CTRL), 0); + + write32((mac_reg_base_addr + SYS_RBUF_FLUSH_CTRL), 0); DELAY_MICROS(10); - write32(MAC_REG + UMAC_CMD, 0); - write32(MAC_REG + UMAC_CMD, (CMD_SW_RESET | CMD_LCL_LOOP_EN)); + + write32(mac_reg_base_addr + UMAC_CMD, 0); + write32(mac_reg_base_addr + UMAC_CMD, (CMD_SW_RESET | CMD_LCL_LOOP_EN)); DELAY_MICROS(2); - write32(MAC_REG + UMAC_CMD, 0); + + write32(mac_reg_base_addr + UMAC_CMD, 0); /* clear tx/rx counter */ - write32(MAC_REG + UMAC_MIB_CTRL, MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT); - write32(MAC_REG + UMAC_MIB_CTRL, 0); - write32(MAC_REG + UMAC_MAX_FRAME_LEN, ENET_MAX_MTU_SIZE); + write32(mac_reg_base_addr + UMAC_MIB_CTRL, MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT); + write32(mac_reg_base_addr + UMAC_MIB_CTRL, 0); + write32(mac_reg_base_addr + UMAC_MAX_FRAME_LEN, ENET_MAX_MTU_SIZE); + /* init rx registers, enable ip header optimization */ - reg = read32(MAC_REG + RBUF_CTRL); + reg = read32(mac_reg_base_addr + RBUF_CTRL); reg |= RBUF_ALIGN_2B; - write32(MAC_REG + RBUF_CTRL, reg); - write32(MAC_REG + RBUF_TBUF_SIZE_CTRL, 1); + write32(mac_reg_base_addr + RBUF_CTRL, reg); + write32(mac_reg_base_addr + RBUF_TBUF_SIZE_CTRL, 1); } static void bcmgenet_disable_dma(void) { rt_uint32_t tdma_reg = 0, rdma_reg = 0; - tdma_reg = read32(MAC_REG + TDMA_REG_BASE + DMA_CTRL); + tdma_reg = read32(mac_reg_base_addr + TDMA_REG_BASE + DMA_CTRL); tdma_reg &= ~(1UL << DMA_EN); - write32(MAC_REG + TDMA_REG_BASE + DMA_CTRL, tdma_reg); - rdma_reg = read32(MAC_REG + RDMA_REG_BASE + DMA_CTRL); + write32(mac_reg_base_addr + TDMA_REG_BASE + DMA_CTRL, tdma_reg); + rdma_reg = read32(mac_reg_base_addr + RDMA_REG_BASE + DMA_CTRL); rdma_reg &= ~(1UL << DMA_EN); - write32(MAC_REG + RDMA_REG_BASE + DMA_CTRL, rdma_reg); - write32(MAC_REG + UMAC_TX_FLUSH, 1); + write32(mac_reg_base_addr + RDMA_REG_BASE + DMA_CTRL, rdma_reg); + write32(mac_reg_base_addr + UMAC_TX_FLUSH, 1); DELAY_MICROS(100); - write32(MAC_REG + UMAC_TX_FLUSH, 0); + write32(mac_reg_base_addr + UMAC_TX_FLUSH, 0); } static void bcmgenet_enable_dma(void) @@ -167,10 +172,10 @@ static void bcmgenet_enable_dma(void) rt_uint32_t dma_ctrl = 0; dma_ctrl = (1 << (DEFAULT_Q + DMA_RING_BUF_EN_SHIFT)) | DMA_EN; - write32(MAC_REG + TDMA_REG_BASE + DMA_CTRL, dma_ctrl); + write32(mac_reg_base_addr + TDMA_REG_BASE + DMA_CTRL, dma_ctrl); - reg = read32(MAC_REG + RDMA_REG_BASE + DMA_CTRL); - write32(MAC_REG + RDMA_REG_BASE + DMA_CTRL, dma_ctrl | reg); + reg = read32(mac_reg_base_addr + RDMA_REG_BASE + DMA_CTRL); + write32(mac_reg_base_addr + RDMA_REG_BASE + DMA_CTRL, dma_ctrl | reg); } static int bcmgenet_mdio_write(rt_uint32_t addr, rt_uint32_t reg, rt_uint32_t value) @@ -178,16 +183,16 @@ static int bcmgenet_mdio_write(rt_uint32_t addr, rt_uint32_t reg, rt_uint32_t va int count = 10000; rt_uint32_t val; val = MDIO_WR | (addr << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT) | (0xffff & value); - write32(MAC_REG + MDIO_CMD, val); + write32(mac_reg_base_addr + MDIO_CMD, val); - rt_uint32_t reg_val = read32(MAC_REG + MDIO_CMD); + rt_uint32_t reg_val = read32(mac_reg_base_addr + MDIO_CMD); reg_val = reg_val | MDIO_START_BUSY; - write32(MAC_REG + MDIO_CMD, reg_val); + write32(mac_reg_base_addr + MDIO_CMD, reg_val); - while ((read32(MAC_REG + MDIO_CMD) & MDIO_START_BUSY) && (--count)) + while ((read32(mac_reg_base_addr + MDIO_CMD) & MDIO_START_BUSY) && (--count)) DELAY_MICROS(1); - reg_val = read32(MAC_REG + MDIO_CMD); + reg_val = read32(mac_reg_base_addr + MDIO_CMD); return reg_val & 0xffff; } @@ -199,32 +204,31 @@ static int bcmgenet_mdio_read(rt_uint32_t addr, rt_uint32_t reg) rt_uint32_t reg_val = 0; val = MDIO_RD | (addr << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT); - write32(MAC_REG + MDIO_CMD, val); + write32(mac_reg_base_addr + MDIO_CMD, val); - reg_val = read32(MAC_REG + MDIO_CMD); + reg_val = read32(mac_reg_base_addr + MDIO_CMD); reg_val = reg_val | MDIO_START_BUSY; - write32(MAC_REG + MDIO_CMD, reg_val); + write32(mac_reg_base_addr + MDIO_CMD, reg_val); - while ((read32(MAC_REG + MDIO_CMD) & MDIO_START_BUSY) && (--count)) + while ((read32(mac_reg_base_addr + MDIO_CMD) & MDIO_START_BUSY) && (--count)) DELAY_MICROS(1); - reg_val = read32(MAC_REG + MDIO_CMD); + reg_val = read32(mac_reg_base_addr + MDIO_CMD); return reg_val & 0xffff; } static int bcmgenet_gmac_write_hwaddr(void) { - //{0xdc,0xa6,0x32,0x28,0x22,0x50}; rt_uint8_t addr[6]; rt_uint32_t reg; bcm271x_mbox_hardware_get_mac_address(&addr[0]); reg = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3]; - write32(MAC_REG + UMAC_MAC0, reg); + write32(mac_reg_base_addr + UMAC_MAC0, reg); reg = addr[4] << 8 | addr[5]; - write32(MAC_REG + UMAC_MAC1, reg); + write32(mac_reg_base_addr + UMAC_MAC1, reg); return 0; } @@ -250,10 +254,8 @@ static void bcmgenet_mdio_init(void) rt_uint32_t ret = 0; /*get ethernet uid*/ ret = get_ethernet_uid(); - if (ret == 0) - { - return; - } + if (ret == 0) return; + /* reset phy */ bcmgenet_mdio_write(1, BCM54213PE_MII_CONTROL, MII_CONTROL_PHY_RESET); /* read control reg */ @@ -280,34 +282,34 @@ static void bcmgenet_mdio_init(void) static void rx_ring_init(void) { - write32(MAC_REG + RDMA_REG_BASE + DMA_SCB_BURST_SIZE, DMA_MAX_BURST_LENGTH); - write32(MAC_REG + RDMA_RING_REG_BASE + DMA_START_ADDR, 0x0); - write32(MAC_REG + RDMA_READ_PTR, 0x0); - write32(MAC_REG + RDMA_WRITE_PTR, 0x0); - write32(MAC_REG + RDMA_RING_REG_BASE + DMA_END_ADDR, RX_DESCS * DMA_DESC_SIZE / 4 - 1); + write32(mac_reg_base_addr + RDMA_REG_BASE + DMA_SCB_BURST_SIZE, DMA_MAX_BURST_LENGTH); + write32(mac_reg_base_addr + RDMA_RING_REG_BASE + DMA_START_ADDR, 0x0); + write32(mac_reg_base_addr + RDMA_READ_PTR, 0x0); + write32(mac_reg_base_addr + RDMA_WRITE_PTR, 0x0); + write32(mac_reg_base_addr + RDMA_RING_REG_BASE + DMA_END_ADDR, RX_DESCS * DMA_DESC_SIZE / 4 - 1); - write32(MAC_REG + RDMA_PROD_INDEX, 0x0); - write32(MAC_REG + RDMA_CONS_INDEX, 0x0); - write32(MAC_REG + RDMA_RING_REG_BASE + DMA_RING_BUF_SIZE, (RX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH); - write32(MAC_REG + RDMA_XON_XOFF_THRESH, DMA_FC_THRESH_VALUE); - write32(MAC_REG + RDMA_REG_BASE + DMA_RING_CFG, 1 << DEFAULT_Q); + write32(mac_reg_base_addr + RDMA_PROD_INDEX, 0x0); + write32(mac_reg_base_addr + RDMA_CONS_INDEX, 0x0); + write32(mac_reg_base_addr + RDMA_RING_REG_BASE + DMA_RING_BUF_SIZE, (RX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH); + write32(mac_reg_base_addr + RDMA_XON_XOFF_THRESH, DMA_FC_THRESH_VALUE); + write32(mac_reg_base_addr + RDMA_REG_BASE + DMA_RING_CFG, 1 << DEFAULT_Q); } static void tx_ring_init(void) { - write32(MAC_REG + TDMA_REG_BASE + DMA_SCB_BURST_SIZE, DMA_MAX_BURST_LENGTH); - write32(MAC_REG + TDMA_RING_REG_BASE + DMA_START_ADDR, 0x0); - write32(MAC_REG + TDMA_READ_PTR, 0x0); - write32(MAC_REG + TDMA_READ_PTR, 0x0); - write32(MAC_REG + TDMA_READ_PTR, 0x0); - write32(MAC_REG + TDMA_WRITE_PTR, 0x0); - write32(MAC_REG + TDMA_RING_REG_BASE + DMA_END_ADDR, TX_DESCS * DMA_DESC_SIZE / 4 - 1); - write32(MAC_REG + TDMA_PROD_INDEX, 0x0); - write32(MAC_REG + TDMA_CONS_INDEX, 0x0); - write32(MAC_REG + TDMA_RING_REG_BASE + DMA_MBUF_DONE_THRESH, 0x1); - write32(MAC_REG + TDMA_FLOW_PERIOD, 0x0); - write32(MAC_REG + TDMA_RING_REG_BASE + DMA_RING_BUF_SIZE, (TX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH); - write32(MAC_REG + TDMA_REG_BASE + DMA_RING_CFG, 1 << DEFAULT_Q); + write32(mac_reg_base_addr + TDMA_REG_BASE + DMA_SCB_BURST_SIZE, DMA_MAX_BURST_LENGTH); + write32(mac_reg_base_addr + TDMA_RING_REG_BASE + DMA_START_ADDR, 0x0); + write32(mac_reg_base_addr + TDMA_READ_PTR, 0x0); + write32(mac_reg_base_addr + TDMA_READ_PTR, 0x0); + write32(mac_reg_base_addr + TDMA_READ_PTR, 0x0); + write32(mac_reg_base_addr + TDMA_WRITE_PTR, 0x0); + write32(mac_reg_base_addr + TDMA_RING_REG_BASE + DMA_END_ADDR, TX_DESCS * DMA_DESC_SIZE / 4 - 1); + write32(mac_reg_base_addr + TDMA_PROD_INDEX, 0x0); + write32(mac_reg_base_addr + TDMA_CONS_INDEX, 0x0); + write32(mac_reg_base_addr + TDMA_RING_REG_BASE + DMA_MBUF_DONE_THRESH, 0x1); + write32(mac_reg_base_addr + TDMA_FLOW_PERIOD, 0x0); + write32(mac_reg_base_addr + TDMA_RING_REG_BASE + DMA_RING_BUF_SIZE, (TX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH); + write32(mac_reg_base_addr + TDMA_REG_BASE + DMA_RING_CFG, 1 << DEFAULT_Q); } static void rx_descs_init(void) @@ -346,14 +348,14 @@ static int bcmgenet_adjust_link(void) return -1; } - rt_uint32_t reg1 = read32(MAC_REG + EXT_RGMII_OOB_CTRL); + rt_uint32_t reg1 = read32(mac_reg_base_addr + EXT_RGMII_OOB_CTRL); //reg1 &= ~(1UL << OOB_DISABLE); //rt_kprintf("OOB_DISABLE is %d\n", OOB_DISABLE); reg1 |= (RGMII_LINK | RGMII_MODE_EN | ID_MODE_DIS); - write32(MAC_REG + EXT_RGMII_OOB_CTRL, reg1); + write32(mac_reg_base_addr + EXT_RGMII_OOB_CTRL, reg1); DELAY_MICROS(1000); - write32(MAC_REG + UMAC_CMD, speed << CMD_SPEED_SHIFT); + write32(mac_reg_base_addr + UMAC_CMD, speed << CMD_SPEED_SHIFT); return 0; } @@ -391,28 +393,28 @@ static int bcmgenet_gmac_eth_start(void) } /* wait tx index clear */ - while ((read32(MAC_REG + TDMA_CONS_INDEX) != 0) && (--count)) + while ((read32(mac_reg_base_addr + TDMA_CONS_INDEX) != 0) && (--count)) DELAY_MICROS(1); - tx_index = read32(MAC_REG + TDMA_CONS_INDEX); - write32(MAC_REG + TDMA_PROD_INDEX, tx_index); + tx_index = read32(mac_reg_base_addr + TDMA_CONS_INDEX); + write32(mac_reg_base_addr + TDMA_PROD_INDEX, tx_index); - index_flag = read32(MAC_REG + RDMA_PROD_INDEX); + index_flag = read32(mac_reg_base_addr + RDMA_PROD_INDEX); - rx_index = index_flag % 256; + rx_index = index_flag % RX_DESCS; - write32(MAC_REG + RDMA_CONS_INDEX, index_flag); - write32(MAC_REG + RDMA_PROD_INDEX, index_flag); + write32(mac_reg_base_addr + RDMA_CONS_INDEX, index_flag); + write32(mac_reg_base_addr + RDMA_PROD_INDEX, index_flag); /* Enable Rx/Tx */ rt_uint32_t rx_tx_en; - rx_tx_en = read32(MAC_REG + UMAC_CMD); - + rx_tx_en = read32(mac_reg_base_addr + UMAC_CMD); rx_tx_en |= (CMD_TX_EN | CMD_RX_EN); - write32(MAC_REG + UMAC_CMD, rx_tx_en); - //IRQ - write32(MAC_REG + GENET_INTRL2_CPU_CLEAR_MASK, GENET_IRQ_TXDMA_DONE | GENET_IRQ_RXDMA_DONE); + write32(mac_reg_base_addr + UMAC_CMD, rx_tx_en); + + // eanble IRQ for TxDMA done and RxDMA done + write32(mac_reg_base_addr + GENET_INTRL2_CPU_CLEAR_MASK, GENET_IRQ_TXDMA_DONE | GENET_IRQ_RXDMA_DONE); return 0; } @@ -422,18 +424,16 @@ static rt_uint32_t bcmgenet_gmac_eth_recv(rt_uint8_t **packetp) { void* desc_base; rt_uint32_t length = 0, addr = 0; - rt_uint32_t prod_index = read32(MAC_REG + RDMA_PROD_INDEX); - //get next - if(prod_index == index_flag) + rt_uint32_t prod_index = read32(mac_reg_base_addr + RDMA_PROD_INDEX); + if(prod_index == index_flag) //no buff { cur_recv_cnt = index_flag; index_flag = 0x7fffffff; - //no buff return 0; } else { - if(prev_recv_cnt == prod_index) + if(prev_recv_cnt == (prod_index & 0xffff)) //no new buff { return 0; } @@ -446,14 +446,20 @@ static rt_uint32_t bcmgenet_gmac_eth_recv(rt_uint8_t **packetp) * This would actually not be needed if we don't program * RBUF_ALIGN_2B */ + + //Convert to memory address + addr = addr + eth_recv_no_cache - RECV_DATA_NO_CACHE; + rt_hw_cpu_dcache_invalidate(addr,length); + *packetp = (rt_uint8_t *)(addr + RX_BUF_OFFSET); rx_index = rx_index + 1; - if(rx_index >= 256) + if(rx_index >= RX_DESCS) { rx_index = 0; } - write32(MAC_REG + RDMA_CONS_INDEX, cur_recv_cnt); + + write32(mac_reg_base_addr + RDMA_CONS_INDEX, cur_recv_cnt); cur_recv_cnt = cur_recv_cnt + 1; @@ -463,54 +469,43 @@ static rt_uint32_t bcmgenet_gmac_eth_recv(rt_uint8_t **packetp) } prev_recv_cnt = cur_recv_cnt; - return length; + return length - RX_BUF_OFFSET; } } -static int bcmgenet_gmac_eth_send(void *packet, int length) + +static int bcmgenet_gmac_eth_send(rt_uint32_t packet, int length,struct pbuf *p) { + rt_ubase_t level; void *desc_base = (TX_DESC_BASE + tx_index * DMA_DESC_SIZE); + pbuf_copy_partial(p, (void*)(packet + tx_index * SEND_CACHE_BUF), p->tot_len, 0); rt_uint32_t len_stat = length << DMA_BUFLENGTH_SHIFT; - - rt_uint32_t prod_index, cons; - rt_uint32_t tries = 100; - - prod_index = read32(MAC_REG + TDMA_PROD_INDEX); - len_stat |= 0x3F << DMA_TX_QTAG_SHIFT; len_stat |= DMA_TX_APPEND_CRC | DMA_SOP | DMA_EOP; + rt_hw_cpu_dcache_clean((void*)(packet + tx_index * SEND_CACHE_BUF),length); - write32((desc_base + DMA_DESC_ADDRESS_LO), SEND_DATA_NO_CACHE); + rt_uint32_t prod_index; + + prod_index = read32(mac_reg_base_addr + TDMA_PROD_INDEX); + + write32((desc_base + DMA_DESC_ADDRESS_LO), SEND_DATA_NO_CACHE + tx_index * SEND_CACHE_BUF); write32((desc_base + DMA_DESC_ADDRESS_HI), 0); write32((desc_base + DMA_DESC_LENGTH_STATUS), len_stat); - tx_index = tx_index + 1; + tx_index ++; + if(tx_index >= TX_DESCS) + { + tx_index = 0; + } prod_index = prod_index + 1; - if (prod_index == 0xe000) + if (prod_index > 0xffff) { - write32(MAC_REG + TDMA_PROD_INDEX, 0); prod_index = 0; } - if (tx_index == 256) - { - tx_index = 0; - } - /* Start Transmisson */ - write32(MAC_REG + TDMA_PROD_INDEX, prod_index); - - do - { - cons = read32(MAC_REG + TDMA_CONS_INDEX); - } while ((cons & 0xffff) < prod_index && --tries); - - if (!tries) - { - rt_kprintf("send err! tries is %d\n", tries); - return -1; - } + write32(mac_reg_base_addr + TDMA_PROD_INDEX, prod_index); return 0; } @@ -519,8 +514,10 @@ static void link_task_entry(void *param) struct eth_device *eth_device = (struct eth_device *)param; RT_ASSERT(eth_device != RT_NULL); struct rt_eth_dev *dev = ð_dev; + //start mdio bcmgenet_mdio_init(); + //start timer link rt_timer_init(&dev->link_timer, "link_timer", link_irq, @@ -535,7 +532,7 @@ static void link_task_entry(void *param) rt_timer_stop(&dev->link_timer); //set mac - bcmgenet_gmac_write_hwaddr(); + // bcmgenet_gmac_write_hwaddr(); bcmgenet_gmac_write_hwaddr(); //check link speed @@ -555,20 +552,13 @@ static void link_task_entry(void *param) rt_kprintf("Support link mode Speed 10M\n"); } - bcmgenet_gmac_eth_start(); - //irq or poll -#ifdef ETH_RX_POLL - rt_timer_init(&dev->rx_poll_timer, "rx_poll_timer", - eth_rx_irq, - NULL, - 1, - RT_TIMER_FLAG_PERIODIC); - rt_timer_start(&dev->rx_poll_timer); -#else + //Convert to memory address + bcmgenet_gmac_eth_start(); + rt_hw_interrupt_install(ETH_IRQ, eth_rx_irq, NULL, "eth_irq"); rt_hw_interrupt_umask(ETH_IRQ); -#endif + link_flag = 1; } @@ -579,7 +569,7 @@ static rt_err_t bcmgenet_eth_init(rt_device_t device) /* Read GENET HW version */ rt_uint8_t major = 0; - hw_reg = read32(MAC_REG + SYS_REV_CTRL); + hw_reg = read32(mac_reg_base_addr + SYS_REV_CTRL); major = (hw_reg >> 24) & 0x0f; if (major != 6) { @@ -599,12 +589,12 @@ static rt_err_t bcmgenet_eth_init(rt_device_t device) } /* rbuf clear */ - write32(MAC_REG + SYS_RBUF_FLUSH_CTRL, 0); + write32(mac_reg_base_addr + SYS_RBUF_FLUSH_CTRL, 0); /* disable MAC while updating its registers */ - write32(MAC_REG + UMAC_CMD, 0); + write32(mac_reg_base_addr + UMAC_CMD, 0); /* issue soft reset with (rg)mii loopback to ensure a stable rxclk */ - write32(MAC_REG + UMAC_CMD, CMD_SW_RESET | CMD_LCL_LOOP_EN); + write32(mac_reg_base_addr + UMAC_CMD, CMD_SW_RESET | CMD_LCL_LOOP_EN); link_thread_tid = rt_thread_create("link", link_task_entry, (void *)device, LINK_THREAD_STACK_SIZE, @@ -633,36 +623,29 @@ static rt_err_t bcmgenet_eth_control(rt_device_t dev, int cmd, void *args) rt_err_t rt_eth_tx(rt_device_t device, struct pbuf *p) { - rt_uint32_t sendbuf = (rt_uint32_t)SEND_DATA_NO_CACHE; - /* lock eth device */ if (link_flag == 1) { - rt_sem_take(&sem_lock, RT_WAITING_FOREVER); - pbuf_copy_partial(p, (void *)&send_cache_pbuf[0], p->tot_len, 0); - rt_memcpy((void *)sendbuf, send_cache_pbuf, p->tot_len); - - bcmgenet_gmac_eth_send((void *)sendbuf, p->tot_len); - rt_sem_release(&sem_lock); + bcmgenet_gmac_eth_send((rt_uint32_t)eth_send_no_cache, p->tot_len,p); + rt_sem_take(&send_finsh_sem_lock,RT_WAITING_FOREVER); } + return RT_EOK; } -char recv_data[RX_BUF_LENGTH]; struct pbuf *rt_eth_rx(rt_device_t device) { int recv_len = 0; - rt_uint32_t addr_point[8]; + rt_uint8_t* addr_point = RT_NULL; struct pbuf *pbuf = RT_NULL; if (link_flag == 1) { - rt_sem_take(&sem_lock, RT_WAITING_FOREVER); - recv_len = bcmgenet_gmac_eth_recv((rt_uint8_t **)&addr_point[0]); + recv_len = bcmgenet_gmac_eth_recv(&addr_point); if (recv_len > 0) { pbuf = pbuf_alloc(PBUF_LINK, recv_len, PBUF_RAM); - rt_memcpy(pbuf->payload, (char *)addr_point[0], recv_len); + if(pbuf) + rt_memcpy(pbuf->payload, addr_point, recv_len); } - rt_sem_release(&sem_lock); } return pbuf; } @@ -670,16 +653,14 @@ struct pbuf *rt_eth_rx(rt_device_t device) int rt_hw_eth_init(void) { rt_uint8_t mac_addr[6]; - - rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO); + rt_sem_init(&send_finsh_sem_lock,"send_finsh_sem_lock",TX_DESCS,RT_IPC_FLAG_FIFO); rt_sem_init(&link_ack, "link_ack", 0, RT_IPC_FLAG_FIFO); - memset(ð_dev, 0, sizeof(eth_dev)); - memset((void *)SEND_DATA_NO_CACHE, 0, sizeof(DMA_DISC_ADDR_SIZE)); - memset((void *)RECV_DATA_NO_CACHE, 0, sizeof(DMA_DISC_ADDR_SIZE)); + memset((void *)eth_send_no_cache, 0, DMA_DISC_ADDR_SIZE); + memset((void *)eth_recv_no_cache, 0, DMA_DISC_ADDR_SIZE); bcm271x_mbox_hardware_get_mac_address(&mac_addr[0]); - eth_dev.iobase = MAC_REG; + eth_dev.iobase = mac_reg_base_addr; eth_dev.name = "e0"; eth_dev.dev_addr[0] = mac_addr[0]; eth_dev.dev_addr[1] = mac_addr[1]; diff --git a/bsp/sam7x/rtconfig.h b/bsp/sam7x/rtconfig.h index ae74c2535e..432f347569 100644 --- a/bsp/sam7x/rtconfig.h +++ b/bsp/sam7x/rtconfig.h @@ -79,6 +79,7 @@ /* SECTION: lwip, a lighwight TCP/IP protocol stack */ /* Using lighweight TCP/IP protocol stack*/ #define RT_USING_LWIP +#define RT_USING_LWIP203 /* Trace LwIP protocol*/ /* #define RT_LWIP_DEBUG */ diff --git a/bsp/stm32/README.md b/bsp/stm32/README.md index 1c355c2d1d..570604a8ba 100644 --- a/bsp/stm32/README.md +++ b/bsp/stm32/README.md @@ -26,6 +26,7 @@ STM32 系列 BSP 目前支持情况如下表所示： | [stm32f401-st-nucleo](stm32f401-st-nucleo) | ST 官方 STM32F401 Nucleo-64 开发板 | | [stm32f405-smdz-breadfruit](stm32f405-smdz-breadfruit) | 三木电子 SM1432F405 开发板 | | [stm32f407-atk-explorer](stm32f407-atk-explorer) | 正点原子 F407 探索者开发板 | +| [stm32f407-robomaster-c](stm32f407-robomaster-c) | 大疆公司 RoboMaster C型开发板 | | [stm32f407-st-discovery](stm32f407-st-discovery) | ST 官方 STM32F407-discovery 开发板 | | [stm32f410-st-nucleo](stm32f410-st-nucleo) | ST 官方 STM32F410-Nucleo-64 开发板 | | [stm32f411-atk-nano](stm32f411-atk-nano/) | 正点原子 F411 NANO 开发板 | diff --git a/bsp/stm32/libraries/HAL_Drivers/SConscript b/bsp/stm32/libraries/HAL_Drivers/SConscript index e41a1f0141..dabcc7002c 100644 --- a/bsp/stm32/libraries/HAL_Drivers/SConscript +++ b/bsp/stm32/libraries/HAL_Drivers/SConscript @@ -12,7 +12,10 @@ if GetDepend(['RT_USING_PIN']): src += ['drv_gpio.c'] if GetDepend(['RT_USING_SERIAL']): - src += ['drv_usart.c'] + if GetDepend(['RT_USING_SERIAL_V2']): + src += ['drv_usart_v2.c'] + else: + src += ['drv_usart.c'] if GetDepend(['RT_USING_HWTIMER']): src += ['drv_hwtimer.c'] diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l4/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l4/dma_config.h index 0762f9048d..0064309f2e 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/l4/dma_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/l4/dma_config.h @@ -127,6 +127,17 @@ extern "C" { #endif /* DMA1 channel7 */ +#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE) +#define UART2_DMA_TX_IRQHandler DMA1_Channel7_IRQHandler +#define UART2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define UART2_TX_DMA_INSTANCE DMA1_Channel7 +#if defined(DMAMUX1) /* for L4+ */ +#define UART2_TX_DMA_REQUEST DMA_REQUEST_USART2_TX +#else /* for L4 */ +#define UART2_TX_DMA_REQUEST DMA_REQUEST_2 +#endif /* DMAMUX1 */ +#define UART2_TX_DMA_IRQ DMA1_Channel7_IRQn +#endif /* DMA2 channel1 */ #if defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE) diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_common.c b/bsp/stm32/libraries/HAL_Drivers/drv_common.c index 74007b6e88..678e4ebadb 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_common.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_common.c @@ -12,8 +12,12 @@ #include "board.h" #ifdef RT_USING_SERIAL +#ifdef RT_USING_SERIAL_V2 +#include "drv_usart_v2.h" +#else #include "drv_usart.h" #endif +#endif #ifdef RT_USING_FINSH #include @@ -113,16 +117,32 @@ void _Error_Handler(char *s, int num) */ void rt_hw_us_delay(rt_uint32_t us) { - rt_uint32_t start, now, delta, reload, us_tick; - start = SysTick->VAL; - reload = SysTick->LOAD; - us_tick = SystemCoreClock / 1000000UL; - do + rt_uint32_t ticks; + rt_uint32_t told, tnow, tcnt = 0; + rt_uint32_t reload = SysTick->LOAD; + + ticks = us * reload / (1000000 / RT_TICK_PER_SECOND); + told = SysTick->VAL; + while (1) { - now = SysTick->VAL; - delta = start >= now ? start - now : reload + start - now; + tnow = SysTick->VAL; + if (tnow != told) + { + if (tnow < told) + { + tcnt += told - tnow; + } + else + { + tcnt += reload - tnow + told; + } + told = tnow; + if (tcnt >= ticks) + { + break; + } + } } - while (delta < us_tick * us); } /** diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_eth.c b/bsp/stm32/libraries/HAL_Drivers/drv_eth.c index 0506f6495c..41e86b5134 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_eth.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_eth.c @@ -11,11 +11,10 @@ * 2019-09-03 xiaofan optimize link change detection process */ -#include "board.h" #include "drv_config.h" -#include -#include "lwipopts.h" #include "drv_eth.h" +#include +#include /* * Emac driver uses CubeMX tool to generate emac and phy's configuration, diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_lcd.c b/bsp/stm32/libraries/HAL_Drivers/drv_lcd.c index 5d170016b8..96c61835e6 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_lcd.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_lcd.c @@ -108,11 +108,11 @@ void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc) void LTDC_IRQHandler(void) { - rt_enter_critical(); + rt_interrupt_enter(); HAL_LTDC_IRQHandler(&LtdcHandle); - rt_exit_critical(); + rt_interrupt_leave(); } rt_err_t stm32_lcd_init(struct drv_lcd_device *lcd) diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_rtc.c b/bsp/stm32/libraries/HAL_Drivers/drv_rtc.c index 88c96aa5b8..15968a178c 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_rtc.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_rtc.c @@ -8,6 +8,7 @@ * 2018-12-04 balanceTWK first version * 2020-10-14 Dozingfiretruck Porting for stm32wbxx * 2021-02-05 Meco Man fix the problem of mixing local time and UTC time + * 2021-07-05 iysheng implement RTC framework V2.0 */ #include "board.h" @@ -25,8 +26,6 @@ #define BKUP_REG_DATA 0xA5A5 -static struct rt_device rtc; - static RTC_HandleTypeDef RTC_Handler; RT_WEAK uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) @@ -102,34 +101,6 @@ static rt_err_t set_rtc_time_stamp(time_t time_stamp) return RT_EOK; } -static void rt_rtc_init(void) -{ -#if !defined(SOC_SERIES_STM32H7) && !defined(SOC_SERIES_STM32WL) && !defined(SOC_SERIES_STM32WB) - __HAL_RCC_PWR_CLK_ENABLE(); -#endif - - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; -#ifdef BSP_RTC_USING_LSI -#ifdef SOC_SERIES_STM32WB -RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI1; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; - RCC_OscInitStruct.LSEState = RCC_LSE_OFF; - RCC_OscInitStruct.LSIState = RCC_LSI_ON; -#else - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; - RCC_OscInitStruct.LSEState = RCC_LSE_OFF; - RCC_OscInitStruct.LSIState = RCC_LSI_ON; -#endif -#else - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; - RCC_OscInitStruct.LSEState = RCC_LSE_ON; - RCC_OscInitStruct.LSIState = RCC_LSI_OFF; -#endif - HAL_RCC_OscConfig(&RCC_OscInitStruct); -} - #ifdef SOC_SERIES_STM32F1 /* update RTC_BKP_DRx*/ static void rt_rtc_f1_bkp_update(void) @@ -160,7 +131,7 @@ static void rt_rtc_f1_bkp_update(void) } #endif -static rt_err_t rt_rtc_config(struct rt_device *dev) +static rt_err_t rt_rtc_config(void) { RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; @@ -234,81 +205,90 @@ static rt_err_t rt_rtc_config(struct rt_device *dev) return RT_EOK; } -static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args) +static rt_err_t stm32_rtc_init(void) +{ +#if !defined(SOC_SERIES_STM32H7) && !defined(SOC_SERIES_STM32WL) && !defined(SOC_SERIES_STM32WB) + __HAL_RCC_PWR_CLK_ENABLE(); +#endif + + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; +#ifdef BSP_RTC_USING_LSI +#ifdef SOC_SERIES_STM32WB +RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI1; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.LSEState = RCC_LSE_OFF; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; +#else + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.LSEState = RCC_LSE_OFF; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; +#endif +#else + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.LSIState = RCC_LSI_OFF; +#endif + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + if (rt_rtc_config() != RT_EOK) + { + LOG_E("rtc init failed."); + return -RT_ERROR; + } + + return RT_EOK; +} + +static rt_err_t stm32_rtc_get_secs(void *args) +{ + *(rt_uint32_t *)args = get_rtc_timestamp(); + LOG_D("RTC: get rtc_time %x\n", *(rt_uint32_t *)args); + + return RT_EOK; +} + +static rt_err_t stm32_rtc_set_secs(void *args) { rt_err_t result = RT_EOK; - RT_ASSERT(dev != RT_NULL); - switch (cmd) - { - case RT_DEVICE_CTRL_RTC_GET_TIME: - *(rt_uint32_t *)args = get_rtc_timestamp(); - LOG_D("RTC: get rtc_time %x\n", *(rt_uint32_t *)args); - break; - case RT_DEVICE_CTRL_RTC_SET_TIME: - if (set_rtc_time_stamp(*(rt_uint32_t *)args)) - { - result = -RT_ERROR; - } - LOG_D("RTC: set rtc_time %x\n", *(rt_uint32_t *)args); - break; + if (set_rtc_time_stamp(*(rt_uint32_t *)args)) + { + result = -RT_ERROR; } + LOG_D("RTC: set rtc_time %x\n", *(rt_uint32_t *)args); return result; } -#ifdef RT_USING_DEVICE_OPS -const static struct rt_device_ops rtc_ops = +static const struct rt_rtc_ops stm32_rtc_ops = { + stm32_rtc_init, + stm32_rtc_get_secs, /* get_secs */ + stm32_rtc_set_secs, /* set secs */ RT_NULL, RT_NULL, RT_NULL, RT_NULL, - RT_NULL, - rt_rtc_control }; -#endif -static rt_err_t rt_hw_rtc_register(rt_device_t device, const char *name, rt_uint32_t flag) -{ - RT_ASSERT(device != RT_NULL); +static rt_rtc_dev_t stm32_rtc_dev; - rt_rtc_init(); - if (rt_rtc_config(device) != RT_EOK) - { - return -RT_ERROR; - } -#ifdef RT_USING_DEVICE_OPS - device->ops = &rtc_ops; -#else - device->init = RT_NULL; - device->open = RT_NULL; - device->close = RT_NULL; - device->read = RT_NULL; - device->write = RT_NULL; - device->control = rt_rtc_control; -#endif - device->type = RT_Device_Class_RTC; - device->rx_indicate = RT_NULL; - device->tx_complete = RT_NULL; - device->user_data = RT_NULL; - - /* register a character device */ - return rt_device_register(device, name, flag); -} - -int rt_hw_rtc_init(void) +static int rt_hw_rtc_init(void) { rt_err_t result; - result = rt_hw_rtc_register(&rtc, "rtc", RT_DEVICE_FLAG_RDWR); + + stm32_rtc_dev.ops = &stm32_rtc_ops; + result = rt_rtc_dev_register(&stm32_rtc_dev, "rtc", RT_DEVICE_FLAG_RDWR, RT_NULL); if (result != RT_EOK) { LOG_E("rtc register err code: %d", result); return result; } LOG_D("rtc init success"); + return RT_EOK; } INIT_DEVICE_EXPORT(rt_hw_rtc_init); - #endif /* BSP_USING_ONCHIP_RTC */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_usart_v2.c b/bsp/stm32/libraries/HAL_Drivers/drv_usart_v2.c new file mode 100644 index 0000000000..1f84d848a0 --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drv_usart_v2.c @@ -0,0 +1,1138 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-06-01 KyleChan first version + */ + +#include "board.h" +#include "drv_usart_v2.h" + +#ifdef RT_USING_SERIAL_V2 + +//#define DRV_DEBUG +#define DBG_TAG "drv.usart" +#ifdef DRV_DEBUG +#define DBG_LVL DBG_LOG +#else +#define DBG_LVL DBG_INFO +#endif /* DRV_DEBUG */ +#include + +#if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && \ + !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5) && !defined(BSP_USING_UART6) && \ + !defined(BSP_USING_UART7) && !defined(BSP_USING_UART8) && !defined(BSP_USING_LPUART1) + #error "Please define at least one BSP_USING_UARTx" + /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */ +#endif + +#ifdef RT_SERIAL_USING_DMA + static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag); +#endif + +enum +{ +#ifdef BSP_USING_UART1 + UART1_INDEX, +#endif + +#ifdef BSP_USING_UART2 + UART2_INDEX, +#endif + +#ifdef BSP_USING_UART3 + UART3_INDEX, +#endif + +#ifdef BSP_USING_UART4 + UART4_INDEX, +#endif + +#ifdef BSP_USING_UART5 + UART5_INDEX, +#endif + +#ifdef BSP_USING_UART6 + UART6_INDEX, +#endif + +#ifdef BSP_USING_UART7 + UART7_INDEX, +#endif + +#ifdef BSP_USING_UART8 + UART8_INDEX, +#endif + +#ifdef BSP_USING_LPUART1 + LPUART1_INDEX, +#endif +}; + +static struct stm32_uart_config uart_config[] = +{ +#ifdef BSP_USING_UART1 + UART1_CONFIG, +#endif + +#ifdef BSP_USING_UART2 + UART2_CONFIG, +#endif + +#ifdef BSP_USING_UART3 + UART3_CONFIG, +#endif + +#ifdef BSP_USING_UART4 + UART4_CONFIG, +#endif +#ifdef BSP_USING_UART5 + UART5_CONFIG, +#endif +#ifdef BSP_USING_UART6 + UART6_CONFIG, +#endif +#ifdef BSP_USING_UART7 + UART7_CONFIG, +#endif +#ifdef BSP_USING_UART8 + UART8_CONFIG, +#endif +#ifdef BSP_USING_LPUART1 + LPUART1_CONFIG, +#endif +}; + + +static struct stm32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0}; + +static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct stm32_uart *uart; + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + uart = rt_container_of(serial, struct stm32_uart, serial); + + uart->handle.Instance = uart->config->Instance; + uart->handle.Init.BaudRate = cfg->baud_rate; + uart->handle.Init.HwFlowCtl = UART_HWCONTROL_NONE; + uart->handle.Init.Mode = UART_MODE_TX_RX; + uart->handle.Init.OverSampling = UART_OVERSAMPLING_16; + + if(uart->handle.Instance == USART3) + { + uart->handle.Init.HwFlowCtl = UART_HWCONTROL_RTS_CTS; + } + + switch (cfg->data_bits) + { + case DATA_BITS_8: + if (cfg->parity == PARITY_ODD || cfg->parity == PARITY_EVEN) + uart->handle.Init.WordLength = UART_WORDLENGTH_9B; + else + uart->handle.Init.WordLength = UART_WORDLENGTH_8B; + break; + case DATA_BITS_9: + uart->handle.Init.WordLength = UART_WORDLENGTH_9B; + break; + default: + uart->handle.Init.WordLength = UART_WORDLENGTH_8B; + break; + } + + switch (cfg->stop_bits) + { + case STOP_BITS_1: + uart->handle.Init.StopBits = UART_STOPBITS_1; + break; + case STOP_BITS_2: + uart->handle.Init.StopBits = UART_STOPBITS_2; + break; + default: + uart->handle.Init.StopBits = UART_STOPBITS_1; + break; + } + + switch (cfg->parity) + { + case PARITY_NONE: + uart->handle.Init.Parity = UART_PARITY_NONE; + break; + case PARITY_ODD: + uart->handle.Init.Parity = UART_PARITY_ODD; + break; + case PARITY_EVEN: + uart->handle.Init.Parity = UART_PARITY_EVEN; + break; + default: + uart->handle.Init.Parity = UART_PARITY_NONE; + break; + } + +#ifdef RT_SERIAL_USING_DMA + uart->dma_rx.remaining_cnt = serial->config.rx_bufsz; +#endif + + if (HAL_UART_Init(&uart->handle) != HAL_OK) + { + return -RT_ERROR; + } + + return RT_EOK; +} + +static rt_err_t stm32_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct stm32_uart *uart; + + rt_ubase_t ctrl_arg = (rt_ubase_t)arg; + + RT_ASSERT(serial != RT_NULL); + uart = rt_container_of(serial, struct stm32_uart, serial); + + if(ctrl_arg & (RT_DEVICE_FLAG_RX_BLOCKING | RT_DEVICE_FLAG_RX_NON_BLOCKING)) + { + if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_RX) + ctrl_arg = RT_DEVICE_FLAG_DMA_RX; + else + ctrl_arg = RT_DEVICE_FLAG_INT_RX; + } + else if(ctrl_arg & (RT_DEVICE_FLAG_TX_BLOCKING | RT_DEVICE_FLAG_TX_NON_BLOCKING)) + { + if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_TX) + ctrl_arg = RT_DEVICE_FLAG_DMA_TX; + else + ctrl_arg = RT_DEVICE_FLAG_INT_TX; + } + + switch (cmd) + { + /* disable interrupt */ + case RT_DEVICE_CTRL_CLR_INT: + + NVIC_DisableIRQ(uart->config->irq_type); + if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) + __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_RXNE); + else if (ctrl_arg == RT_DEVICE_FLAG_INT_TX) + __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_TXE); +#ifdef RT_SERIAL_USING_DMA + else if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) + { + __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_RXNE); + + HAL_NVIC_DisableIRQ(uart->config->dma_rx->dma_irq); + if (HAL_DMA_Abort(&(uart->dma_rx.handle)) != HAL_OK) + { + RT_ASSERT(0); + } + + if (HAL_DMA_DeInit(&(uart->dma_rx.handle)) != HAL_OK) + { + RT_ASSERT(0); + } + } + else if(ctrl_arg == RT_DEVICE_FLAG_DMA_TX) + { + __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_TC); + + HAL_NVIC_DisableIRQ(uart->config->dma_tx->dma_irq); + if (HAL_DMA_DeInit(&(uart->dma_tx.handle)) != HAL_OK) + { + RT_ASSERT(0); + } + } +#endif + break; + + case RT_DEVICE_CTRL_SET_INT: + + HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0); + HAL_NVIC_EnableIRQ(uart->config->irq_type); + + if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) + __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_RXNE); + else if (ctrl_arg == RT_DEVICE_FLAG_INT_TX) + __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_TXE); + break; + + case RT_DEVICE_CTRL_CONFIG: + if (ctrl_arg & (RT_DEVICE_FLAG_DMA_RX | RT_DEVICE_FLAG_DMA_TX)) + { + +#ifdef RT_SERIAL_USING_DMA + stm32_dma_config(serial, ctrl_arg); +#endif + } + else + stm32_control(serial, RT_DEVICE_CTRL_SET_INT, (void *)ctrl_arg); + break; + + case RT_DEVICE_CHECK_OPTMODE: + { + if (ctrl_arg & RT_DEVICE_FLAG_DMA_TX) + return RT_SERIAL_TX_BLOCKING_NO_BUFFER; + else + return RT_SERIAL_TX_BLOCKING_BUFFER; + } + case RT_DEVICE_CTRL_CLOSE: + if (HAL_UART_DeInit(&(uart->handle)) != HAL_OK ) + { + RT_ASSERT(0) + } + break; + + } + return RT_EOK; +} + +static int stm32_putc(struct rt_serial_device *serial, char c) +{ + struct stm32_uart *uart; + RT_ASSERT(serial != RT_NULL); + + uart = rt_container_of(serial, struct stm32_uart, serial); + while (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) == RESET); + UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC); + UART_SET_TDR(&uart->handle, c); + + return 1; +} + +static int stm32_getc(struct rt_serial_device *serial) +{ + int ch; + struct stm32_uart *uart; + RT_ASSERT(serial != RT_NULL); + uart = rt_container_of(serial, struct stm32_uart, serial); + + ch = -1; + if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET) + ch = UART_GET_RDR(&uart->handle); + return ch; +} + +static rt_size_t stm32_transmit(struct rt_serial_device *serial, + rt_uint8_t *buf, + rt_size_t size, + rt_uint32_t tx_flag) +{ + struct stm32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(buf != RT_NULL); + uart = rt_container_of(serial, struct stm32_uart, serial); + + if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_TX) + { + HAL_UART_Transmit_DMA(&uart->handle, buf, size); + return size; + } + + stm32_control(serial, RT_DEVICE_CTRL_SET_INT, (void *)tx_flag); + + return size; +} + +#ifdef RT_SERIAL_USING_DMA +static void dma_recv_isr(struct rt_serial_device *serial, rt_uint8_t isr_flag) +{ + struct stm32_uart *uart; + rt_base_t level; + rt_size_t recv_len, counter; + + RT_ASSERT(serial != RT_NULL); + uart = rt_container_of(serial, struct stm32_uart, serial); + + level = rt_hw_interrupt_disable(); + recv_len = 0; + counter = __HAL_DMA_GET_COUNTER(&(uart->dma_rx.handle)); + + switch (isr_flag) + { + case UART_RX_DMA_IT_IDLE_FLAG: + if (counter <= uart->dma_rx.remaining_cnt) + recv_len = uart->dma_rx.remaining_cnt - counter; + else + recv_len = serial->config.rx_bufsz + uart->dma_rx.remaining_cnt - counter; + break; + + case UART_RX_DMA_IT_HT_FLAG: + if (counter < uart->dma_rx.remaining_cnt) + recv_len = uart->dma_rx.remaining_cnt - counter; + break; + + case UART_RX_DMA_IT_TC_FLAG: + if(counter >= uart->dma_rx.remaining_cnt) + recv_len = serial->config.rx_bufsz + uart->dma_rx.remaining_cnt - counter; + + default: + break; + } + + if (recv_len) + { + uart->dma_rx.remaining_cnt = counter; + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8)); + } + rt_hw_interrupt_enable(level); + +} +#endif /* RT_SERIAL_USING_DMA */ + + +/** + * Uart common interrupt process. This need add to uart ISR. + * + * @param serial serial device + */ +static void uart_isr(struct rt_serial_device *serial) +{ + struct stm32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + uart = rt_container_of(serial, struct stm32_uart, serial); + /* If the Read data register is not empty and the RXNE interrupt is enabled （RDR） */ + if ((__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET) && + (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_RXNE) != RESET)) + { + struct rt_serial_rx_fifo *rx_fifo; + rx_fifo = (struct rt_serial_rx_fifo *) serial->serial_rx; + RT_ASSERT(rx_fifo != RT_NULL); + + rt_ringbuffer_putchar(&(rx_fifo->rb), UART_GET_RDR(&uart->handle)); + + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); + } + /* If the Transmit data register is empty and the TXE interrupt enable is enabled （TDR）*/ + else if ((__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TXE) != RESET) && + (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_TXE)) != RESET) + { + struct rt_serial_tx_fifo *tx_fifo; + tx_fifo = (struct rt_serial_tx_fifo *) serial->serial_tx; + RT_ASSERT(tx_fifo != RT_NULL); + + rt_uint8_t put_char = 0; + if (rt_ringbuffer_getchar(&(tx_fifo->rb), &put_char)) + { + UART_SET_TDR(&uart->handle, put_char); + } + else + { + __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_TXE); + __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_TC); + } + } + else if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) && + (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_TC) != RESET)) + { + if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_TX) + { + /* The HAL_UART_TxCpltCallback will be triggered */ + HAL_UART_IRQHandler(&(uart->handle)); + } + else + { + /* Transmission complete interrupt disable ( CR1 Register) */ + __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_TC); + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE); + } + /* Clear Transmission complete interrupt flag ( ISR Register ) */ + UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC); + } + +#ifdef RT_SERIAL_USING_DMA + else if ((uart->uart_dma_flag) && (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_IDLE) != RESET) + && (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_IDLE) != RESET)) + { + dma_recv_isr(serial, UART_RX_DMA_IT_IDLE_FLAG); + __HAL_UART_CLEAR_IDLEFLAG(&uart->handle); + } +#endif + else + { + if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_ORE) != RESET) + { + LOG_E("(%s) serial device Overrun error!", serial->parent.parent.name); + __HAL_UART_CLEAR_OREFLAG(&uart->handle); + } + if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_NE) != RESET) + { + __HAL_UART_CLEAR_NEFLAG(&uart->handle); + } + if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_FE) != RESET) + { + __HAL_UART_CLEAR_FEFLAG(&uart->handle); + } + if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_PE) != RESET) + { + __HAL_UART_CLEAR_PEFLAG(&uart->handle); + } +#if !defined(SOC_SERIES_STM32L4) && !defined(SOC_SERIES_STM32WL) && !defined(SOC_SERIES_STM32F7) && !defined(SOC_SERIES_STM32F0) \ + && !defined(SOC_SERIES_STM32L0) && !defined(SOC_SERIES_STM32G0) && !defined(SOC_SERIES_STM32H7) \ + && !defined(SOC_SERIES_STM32G4) && !defined(SOC_SERIES_STM32MP1) && !defined(SOC_SERIES_STM32WB) + if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_LBD) != RESET) + { + UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_LBD); + } +#endif + if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_CTS) != RESET) + { + UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_CTS); + } + if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TXE) != RESET) + { + UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TXE); + } + if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) != RESET) + { + UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC); + } + if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET) + { + UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_RXNE); + } + } +} + +#if defined(BSP_USING_UART1) +void USART1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART1_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA) +void UART1_DMA_RX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma_rx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA) */ +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA) +void UART1_DMA_TX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma_tx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA) */ +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +void USART2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART2_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA) +void UART2_DMA_RX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART2_INDEX].dma_rx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA) */ +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA) +void UART2_DMA_TX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART2_INDEX].dma_tx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA) */ +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +void USART3_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART3_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_RX_USING_DMA) +void UART3_DMA_RX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART3_INDEX].dma_rx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART3_RX_USING_DMA) */ +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_TX_USING_DMA) +void UART3_DMA_TX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART3_INDEX].dma_tx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_UART_USING_DMA_TX) && defined(BSP_UART3_TX_USING_DMA) */ +#endif /* BSP_USING_UART3*/ + +#if defined(BSP_USING_UART4) +void UART4_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART4_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_RX_USING_DMA) +void UART4_DMA_RX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART4_INDEX].dma_rx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART4_RX_USING_DMA) */ + +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_TX_USING_DMA) +void UART4_DMA_TX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART4_INDEX].dma_tx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_UART_USING_DMA_TX) && defined(BSP_UART4_TX_USING_DMA) */ +#endif /* BSP_USING_UART4*/ + +#if defined(BSP_USING_UART5) +void UART5_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART5_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA) +void UART5_DMA_RX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART5_INDEX].dma_rx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA) */ +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_TX_USING_DMA) +void UART5_DMA_TX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART5_INDEX].dma_tx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_TX_USING_DMA) */ +#endif /* BSP_USING_UART5*/ + +#if defined(BSP_USING_UART6) +void USART6_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART6_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA) +void UART6_DMA_RX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART6_INDEX].dma_rx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA) */ +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_TX_USING_DMA) +void UART6_DMA_TX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART6_INDEX].dma_tx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_TX_USING_DMA) */ +#endif /* BSP_USING_UART6*/ + +#if defined(BSP_USING_UART7) +void UART7_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART7_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_RX_USING_DMA) +void UART7_DMA_RX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART7_INDEX].dma_rx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_RX_USING_DMA) */ +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_TX_USING_DMA) +void UART7_DMA_TX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART7_INDEX].dma_tx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_TX_USING_DMA) */ +#endif /* BSP_USING_UART7*/ + +#if defined(BSP_USING_UART8) +void UART8_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART8_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_RX_USING_DMA) +void UART8_DMA_RX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART8_INDEX].dma_rx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_RX_USING_DMA) */ +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_TX_USING_DMA) +void UART8_DMA_TX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART8_INDEX].dma_tx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_TX_USING_DMA) */ +#endif /* BSP_USING_UART8*/ + +#if defined(BSP_USING_LPUART1) +void LPUART1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[LPUART1_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_LPUART1_RX_USING_DMA) +void LPUART1_DMA_RX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[LPUART1_INDEX].dma_rx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_LPUART1_RX_USING_DMA) */ +#endif /* BSP_USING_LPUART1*/ +static void stm32_uart_get_config(void) +{ + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; +#ifdef BSP_USING_UART1 + uart_obj[UART1_INDEX].serial.config = config; + uart_obj[UART1_INDEX].uart_dma_flag = 0; + + uart_obj[UART1_INDEX].serial.config.rx_bufsz = BSP_UART1_RX_BUFSIZE; + uart_obj[UART1_INDEX].serial.config.tx_bufsz = BSP_UART1_TX_BUFSIZE; + +#ifdef BSP_UART1_RX_USING_DMA + uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart1_dma_rx = UART1_DMA_RX_CONFIG; + uart_config[UART1_INDEX].dma_rx = &uart1_dma_rx; +#endif + +#ifdef BSP_UART1_TX_USING_DMA + uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart1_dma_tx = UART1_DMA_TX_CONFIG; + uart_config[UART1_INDEX].dma_tx = &uart1_dma_tx; +#endif +#endif + +#ifdef BSP_USING_UART2 + uart_obj[UART2_INDEX].serial.config = config; + uart_obj[UART2_INDEX].uart_dma_flag = 0; + + uart_obj[UART2_INDEX].serial.config.rx_bufsz = BSP_UART2_RX_BUFSIZE; + uart_obj[UART2_INDEX].serial.config.tx_bufsz = BSP_UART2_TX_BUFSIZE; + +#ifdef BSP_UART2_RX_USING_DMA + uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart2_dma_rx = UART2_DMA_RX_CONFIG; + uart_config[UART2_INDEX].dma_rx = &uart2_dma_rx; +#endif + +#ifdef BSP_UART2_TX_USING_DMA + uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart2_dma_tx = UART2_DMA_TX_CONFIG; + uart_config[UART2_INDEX].dma_tx = &uart2_dma_tx; +#endif +#endif + +#ifdef BSP_USING_UART3 + uart_obj[UART3_INDEX].serial.config = config; + uart_obj[UART3_INDEX].uart_dma_flag = 0; + + uart_obj[UART3_INDEX].serial.config.rx_bufsz = BSP_UART3_RX_BUFSIZE; + uart_obj[UART3_INDEX].serial.config.tx_bufsz = BSP_UART3_TX_BUFSIZE; + +#ifdef BSP_UART3_RX_USING_DMA + uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart3_dma_rx = UART3_DMA_RX_CONFIG; + uart_config[UART3_INDEX].dma_rx = &uart3_dma_rx; +#endif + +#ifdef BSP_UART3_TX_USING_DMA + uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart3_dma_tx = UART3_DMA_TX_CONFIG; + uart_config[UART3_INDEX].dma_tx = &uart3_dma_tx; +#endif +#endif + +#ifdef BSP_USING_UART4 + uart_obj[UART4_INDEX].serial.config = config; + uart_obj[UART4_INDEX].uart_dma_flag = 0; + + uart_obj[UART4_INDEX].serial.config.rx_bufsz = BSP_UART4_RX_BUFSIZE; + uart_obj[UART4_INDEX].serial.config.tx_bufsz = BSP_UART4_TX_BUFSIZE; + +#ifdef BSP_UART4_RX_USING_DMA + uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart4_dma_rx = UART4_DMA_RX_CONFIG; + uart_config[UART4_INDEX].dma_rx = &uart4_dma_rx; +#endif + +#ifdef BSP_UART4_TX_USING_DMA + uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart4_dma_tx = UART4_DMA_TX_CONFIG; + uart_config[UART4_INDEX].dma_tx = &uart4_dma_tx; +#endif +#endif +} + +#ifdef RT_SERIAL_USING_DMA +static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag) +{ + struct rt_serial_rx_fifo *rx_fifo; + DMA_HandleTypeDef *DMA_Handle; + struct dma_config *dma_config; + struct stm32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + uart = rt_container_of(serial, struct stm32_uart, serial); + + if (RT_DEVICE_FLAG_DMA_RX == flag) + { + DMA_Handle = &uart->dma_rx.handle; + dma_config = uart->config->dma_rx; + } + else if (RT_DEVICE_FLAG_DMA_TX == flag) + { + DMA_Handle = &uart->dma_tx.handle; + dma_config = uart->config->dma_tx; + } + LOG_D("%s dma config start", uart->config->name); + + { + rt_uint32_t tmpreg = 0x00U; +#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) \ + || defined(SOC_SERIES_STM32L0) + /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ + SET_BIT(RCC->AHBENR, dma_config->dma_rcc); + tmpreg = READ_BIT(RCC->AHBENR, dma_config->dma_rcc); +#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) \ + || defined(SOC_SERIES_STM32G4)|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32WB) + /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ + SET_BIT(RCC->AHB1ENR, dma_config->dma_rcc); + tmpreg = READ_BIT(RCC->AHB1ENR, dma_config->dma_rcc); +#elif defined(SOC_SERIES_STM32MP1) + /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ + SET_BIT(RCC->MP_AHB2ENSETR, dma_config->dma_rcc); + tmpreg = READ_BIT(RCC->MP_AHB2ENSETR, dma_config->dma_rcc); +#endif + +#if defined(DMAMUX1) && (defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)) + /* enable DMAMUX clock for L4+ and G4 */ + __HAL_RCC_DMAMUX1_CLK_ENABLE(); +#elif defined(SOC_SERIES_STM32MP1) + __HAL_RCC_DMAMUX_CLK_ENABLE(); +#endif + + UNUSED(tmpreg); /* To avoid compiler warnings */ + } + + if (RT_DEVICE_FLAG_DMA_RX == flag) + { + __HAL_LINKDMA(&(uart->handle), hdmarx, uart->dma_rx.handle); + } + else if (RT_DEVICE_FLAG_DMA_TX == flag) + { + __HAL_LINKDMA(&(uart->handle), hdmatx, uart->dma_tx.handle); + } + +#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32L0) + DMA_Handle->Instance = dma_config->Instance; +#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) + DMA_Handle->Instance = dma_config->Instance; + DMA_Handle->Init.Channel = dma_config->channel; +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)\ + || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1) + DMA_Handle->Instance = dma_config->Instance; + DMA_Handle->Init.Request = dma_config->request; +#endif + DMA_Handle->Init.PeriphInc = DMA_PINC_DISABLE; + DMA_Handle->Init.MemInc = DMA_MINC_ENABLE; + DMA_Handle->Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + DMA_Handle->Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + + if (RT_DEVICE_FLAG_DMA_RX == flag) + { + DMA_Handle->Init.Direction = DMA_PERIPH_TO_MEMORY; + DMA_Handle->Init.Mode = DMA_CIRCULAR; + } + else if (RT_DEVICE_FLAG_DMA_TX == flag) + { + DMA_Handle->Init.Direction = DMA_MEMORY_TO_PERIPH; + DMA_Handle->Init.Mode = DMA_NORMAL; + } + + DMA_Handle->Init.Priority = DMA_PRIORITY_MEDIUM; +#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1) + DMA_Handle->Init.FIFOMode = DMA_FIFOMODE_DISABLE; +#endif + if (HAL_DMA_DeInit(DMA_Handle) != HAL_OK) + { + RT_ASSERT(0); + } + + if (HAL_DMA_Init(DMA_Handle) != HAL_OK) + { + RT_ASSERT(0); + } + + /* enable interrupt */ + if (flag == RT_DEVICE_FLAG_DMA_RX) + { + rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; + RT_ASSERT(rx_fifo != RT_NULL); + /* Start DMA transfer */ + if (HAL_UART_Receive_DMA(&(uart->handle), rx_fifo->buffer, serial->config.rx_bufsz) != HAL_OK) + { + /* Transfer error in reception process */ + RT_ASSERT(0); + } + CLEAR_BIT(uart->handle.Instance->CR3, USART_CR3_EIE); + __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_IDLE); + } + + /* DMA irq should set in DMA TX mode, or HAL_UART_TxCpltCallback function will not be called */ + HAL_NVIC_SetPriority(dma_config->dma_irq, 0, 0); + HAL_NVIC_EnableIRQ(dma_config->dma_irq); + + HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0); + HAL_NVIC_EnableIRQ(uart->config->irq_type); + + LOG_D("%s dma %s instance: %x", uart->config->name, flag == RT_DEVICE_FLAG_DMA_RX ? "RX" : "TX", DMA_Handle->Instance); + LOG_D("%s dma config done", uart->config->name); +} + +/** + * @brief UART error callbacks + * @param huart: UART handle + * @note This example shows a simple way to report transfer error, and you can + * add your own implementation. + * @retval None + */ +void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +{ + RT_ASSERT(huart != NULL); + struct stm32_uart *uart = (struct stm32_uart *)huart; + LOG_D("%s: %s %d\n", __FUNCTION__, uart->config->name, huart->ErrorCode); + UNUSED(uart); +} + +/** + * @brief Rx Transfer completed callback + * @param huart: UART handle + * @note This example shows a simple way to report end of DMA Rx transfer, and + * you can add your own implementation. + * @retval None + */ +void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) +{ + struct stm32_uart *uart; + RT_ASSERT(huart != NULL); + uart = (struct stm32_uart *)huart; + dma_recv_isr(&uart->serial, UART_RX_DMA_IT_TC_FLAG); +} + +/** + * @brief Rx Half transfer completed callback + * @param huart: UART handle + * @note This example shows a simple way to report end of DMA Rx Half transfer, + * and you can add your own implementation. + * @retval None + */ +void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + struct stm32_uart *uart; + RT_ASSERT(huart != NULL); + uart = (struct stm32_uart *)huart; + dma_recv_isr(&uart->serial, UART_RX_DMA_IT_HT_FLAG); +} + +/** + * @brief HAL_UART_TxCpltCallback + * @param huart: UART handle + * @note This callback can be called by two functions, first in UART_EndTransmit_IT when + * UART Tx complete and second in UART_DMATransmitCplt function in DMA Circular mode. + * @retval None + */ +void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +{ + struct stm32_uart *uart; + struct rt_serial_device *serial; + rt_size_t trans_total_index; + rt_base_t level; + + RT_ASSERT(huart != NULL); + uart = (struct stm32_uart *)huart; + serial = &uart->serial; + RT_ASSERT(serial != RT_NULL); + + level = rt_hw_interrupt_disable(); + trans_total_index = __HAL_DMA_GET_COUNTER(&(uart->dma_tx.handle)); + rt_hw_interrupt_enable(level); + + if (trans_total_index) return; + + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DMADONE); + +} +#endif /* RT_SERIAL_USING_DMA */ + +static const struct rt_uart_ops stm32_uart_ops = +{ + .configure = stm32_configure, + .control = stm32_control, + .putc = stm32_putc, + .getc = stm32_getc, + .transmit = stm32_transmit +}; + +int rt_hw_usart_init(void) +{ + rt_err_t result = 0; + rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct stm32_uart); + + stm32_uart_get_config(); + for (int i = 0; i < obj_num; i++) + { + /* init UART object */ + uart_obj[i].config = &uart_config[i]; + uart_obj[i].serial.ops = &stm32_uart_ops; + /* register UART device */ + result = rt_hw_serial_register(&uart_obj[i].serial, + uart_obj[i].config->name, + RT_DEVICE_FLAG_RDWR, + NULL); + RT_ASSERT(result == RT_EOK); + } + + return result; +} + +#endif /* RT_USING_SERIAL_V2 */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_usart_v2.h b/bsp/stm32/libraries/HAL_Drivers/drv_usart_v2.h new file mode 100644 index 0000000000..9cab81bbff --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drv_usart_v2.h @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-06-01 KyleChan first version + */ + +#ifndef __DRV_USART_V2_H__ +#define __DRV_USART_V2_H__ + +#include +#include +#include +#include +#include +#include + +int rt_hw_usart_init(void); + +#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \ + || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) \ + || defined(SOC_SERIES_STM32G4) +#define UART_SET_TDR(__HANDLE__, __DATA__) ((__HANDLE__)->Instance->TDR = (__DATA__)) +#define UART_GET_RDR(__HANDLE__) ((__HANDLE__)->Instance->RDR & 0xFF) + +#else +#define UART_SET_TDR(__HANDLE__, __DATA__) ((__HANDLE__)->Instance->DR = (__DATA__)) +#define UART_GET_RDR(__HANDLE__) ((__HANDLE__)->Instance->DR & 0xFF) +#endif + + +#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F2) \ + || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) \ + || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB) +#define UART_INSTANCE_CLEAR_FUNCTION __HAL_UART_CLEAR_FLAG +#elif defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) \ + || defined(SOC_SERIES_STM32MP1) +#define UART_INSTANCE_CLEAR_FUNCTION __HAL_UART_CLEAR_IT +#endif + +#define UART_RX_DMA_IT_IDLE_FLAG 0x00 +#define UART_RX_DMA_IT_HT_FLAG 0x01 +#define UART_RX_DMA_IT_TC_FLAG 0x02 + + +/* stm32 config class */ +struct stm32_uart_config +{ + const char *name; + USART_TypeDef *Instance; + IRQn_Type irq_type; + +#ifdef RT_SERIAL_USING_DMA + struct dma_config *dma_rx; + struct dma_config *dma_tx; +#endif +}; + +/* stm32 uart dirver class */ +struct stm32_uart +{ + UART_HandleTypeDef handle; + struct stm32_uart_config *config; + +#ifdef RT_SERIAL_USING_DMA + struct + { + DMA_HandleTypeDef handle; + rt_size_t remaining_cnt; + } dma_rx; + struct + { + DMA_HandleTypeDef handle; + } dma_tx; +#endif + rt_uint16_t uart_dma_flag; + struct rt_serial_device serial; +}; + +#endif /* __DRV_USART_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_usbh.c b/bsp/stm32/libraries/HAL_Drivers/drv_usbh.c index ad65accd07..9486e1a56d 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_usbh.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_usbh.c @@ -197,6 +197,8 @@ static struct uhcd_ops _uhcd_ops = static rt_err_t stm32_hcd_init(rt_device_t device) { + HAL_StatusTypeDef state; + HCD_HandleTypeDef *hhcd = (HCD_HandleTypeDef *)device->user_data; hhcd->Instance = USB_OTG_FS; hhcd->Init.Host_channels = 8; @@ -204,7 +206,11 @@ static rt_err_t stm32_hcd_init(rt_device_t device) hhcd->Init.dma_enable = DISABLE; hhcd->Init.phy_itface = HCD_PHY_EMBEDDED; hhcd->Init.Sof_enable = DISABLE; - RT_ASSERT(HAL_HCD_Init(hhcd) == HAL_OK); + state = HAL_HCD_Init(hhcd); + if (state != HAL_OK) + { + return -RT_ERROR; + } HAL_HCD_Start(hhcd); #ifdef USBH_USING_CONTROLLABLE_POWER rt_pin_mode(USBH_POWER_PIN, PIN_MODE_OUTPUT); diff --git a/bsp/stm32/libraries/templates/stm32f0xx/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/libraries/templates/stm32f0xx/board/CubeMX_Config/CubeMX_Config.ioc index 1094ab3d37..976274a19f 100644 --- a/bsp/stm32/libraries/templates/stm32f0xx/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/libraries/templates/stm32f0xx/board/CubeMX_Config/CubeMX_Config.ioc @@ -31,20 +31,22 @@ NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false NVIC.SVC_IRQn=true\:0\:0\:false\:false\:true\:false NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false -PA10.Mode=Synchronous -PA10.Signal=USART1_RX -PA13.Mode=Serial_Wire -PA13.Signal=SYS_SWDIO -PA14.Mode=Serial_Wire -PA14.Signal=SYS_SWCLK +PA2.GPIOParameters=GPIO_PuPd +PA2.GPIO_PuPd=GPIO_PULLUP PA2.Mode=Asynchronous PA2.Signal=USART2_TX +PA3.GPIOParameters=GPIO_PuPd +PA3.GPIO_PuPd=GPIO_PULLUP PA3.Mode=Asynchronous PA3.Signal=USART2_RX -PA8.Mode=Synchronous -PA8.Signal=USART1_CK -PA9.Mode=Synchronous +PA9.GPIOParameters=GPIO_PuPd +PA9.GPIO_PuPd=GPIO_PULLUP +PA9.Mode=Asynchronous PA9.Signal=USART1_TX +PA10.GPIOParameters=GPIO_PuPd +PA10.GPIO_PuPd=GPIO_PULLUP +PA10.Mode=Asynchronous +PA10.Signal=USART1_RX PCC.Checker=false PCC.Line=STM32F0x1 PCC.MCU=STM32F091R(B-C)Tx diff --git a/bsp/stm32/libraries/templates/stm32f0xx/board/CubeMX_Config/Src/stm32f0xx_hal_msp.c b/bsp/stm32/libraries/templates/stm32f0xx/board/CubeMX_Config/Src/stm32f0xx_hal_msp.c index 8bdf8316f9..d8fd04634f 100644 --- a/bsp/stm32/libraries/templates/stm32f0xx/board/CubeMX_Config/Src/stm32f0xx_hal_msp.c +++ b/bsp/stm32/libraries/templates/stm32f0xx/board/CubeMX_Config/Src/stm32f0xx_hal_msp.c @@ -2,12 +2,12 @@ /** ****************************************************************************** * File Name : stm32f0xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** ** This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether + * USER CODE END. Other portions of this file, whether * inserted by the user or by software development tools * are owned by their respective copyright owners. * @@ -52,7 +52,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -114,12 +114,11 @@ void HAL_USART_MspInit(USART_HandleTypeDef* husart) /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PA8 ------> USART1_CK PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -152,15 +151,15 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART2 GPIO Configuration + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; GPIO_InitStruct.Alternate = GPIO_AF1_USART2; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); @@ -189,11 +188,11 @@ void HAL_USART_MspDeInit(USART_HandleTypeDef* husart) /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration + + /**USART1 GPIO Configuration PA8 ------> USART1_CK PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10); @@ -221,10 +220,9 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART2_CLK_DISABLE(); - - /**USART2 GPIO Configuration + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3); diff --git a/bsp/stm32/libraries/templates/stm32f10x/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/libraries/templates/stm32f10x/board/CubeMX_Config/CubeMX_Config.ioc index ebb24e61e1..fc443045df 100644 --- a/bsp/stm32/libraries/templates/stm32f10x/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/libraries/templates/stm32f10x/board/CubeMX_Config/CubeMX_Config.ioc @@ -33,14 +33,18 @@ NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false NVIC.USART1_IRQn=true\:0\:0\:false\:false\:true\:true NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false +PA9.GPIOParameters=GPIO_PuPd +PA9.GPIO_PuPd=GPIO_PULLUP +PA9.Mode=Asynchronous +PA9.Signal=USART1_TX +PA10.GPIOParameters=GPIO_PuPd +PA10.GPIO_PuPd=GPIO_PULLUP PA10.Mode=Asynchronous PA10.Signal=USART1_RX PA13.Mode=Serial_Wire PA13.Signal=SYS_JTMS-SWDIO PA14.Mode=Serial_Wire PA14.Signal=SYS_JTCK-SWCLK -PA9.Mode=Asynchronous -PA9.Signal=USART1_TX PCC.Checker=false PCC.Line=STM32F103 PCC.MCU=STM32F103R(8-B)Tx diff --git a/bsp/stm32/libraries/templates/stm32f10x/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c b/bsp/stm32/libraries/templates/stm32f10x/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c index 990a7ba098..7c454fe98f 100644 --- a/bsp/stm32/libraries/templates/stm32f10x/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c +++ b/bsp/stm32/libraries/templates/stm32f10x/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c @@ -2,12 +2,12 @@ /** ****************************************************************************** * File Name : stm32f1xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** ** This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether + * USER CODE END. Other portions of this file, whether * inserted by the user or by software development tools * are owned by their respective copyright owners. * @@ -52,7 +52,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -92,7 +92,7 @@ void HAL_MspInit(void) /* System interrupt init*/ - /**NOJTAG: JTAG-DP Disabled and SW-DP Enabled + /**NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); @@ -117,11 +117,10 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -130,7 +129,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) GPIO_InitStruct.Pin = GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); /* USART1 interrupt Init */ @@ -158,10 +157,9 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); diff --git a/bsp/stm32/libraries/templates/stm32f2xx/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/libraries/templates/stm32f2xx/board/CubeMX_Config/CubeMX_Config.ioc index 020f6ec89f..d61f038985 100644 --- a/bsp/stm32/libraries/templates/stm32f2xx/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/libraries/templates/stm32f2xx/board/CubeMX_Config/CubeMX_Config.ioc @@ -35,16 +35,24 @@ NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +PA9.GPIOParameters=GPIO_PuPd +PA9.GPIO_PuPd=GPIO_PULLUP +PA9.Mode=Asynchronous +PA9.Signal=USART1_TX +PA10.GPIOParameters=GPIO_PuPd +PA10.GPIO_PuPd=GPIO_PULLUP PA10.Mode=Asynchronous PA10.Signal=USART1_RX PA13.Mode=Serial_Wire PA13.Signal=SYS_JTMS-SWDIO PA14.Mode=Serial_Wire PA14.Signal=SYS_JTCK-SWCLK -PA9.Mode=Asynchronous -PA9.Signal=USART1_TX +PC6.GPIOParameters=GPIO_PuPd +PC6.GPIO_PuPd=GPIO_PULLUP PC6.Mode=Asynchronous PC6.Signal=USART6_TX +PC7.GPIOParameters=GPIO_PuPd +PC7.GPIO_PuPd=GPIO_PULLUP PC7.Mode=Asynchronous PC7.Signal=USART6_RX PCC.Checker=false diff --git a/bsp/stm32/libraries/templates/stm32f2xx/board/CubeMX_Config/Src/stm32f2xx_hal_msp.c b/bsp/stm32/libraries/templates/stm32f2xx/board/CubeMX_Config/Src/stm32f2xx_hal_msp.c index 14b4f29801..b82ce057a6 100644 --- a/bsp/stm32/libraries/templates/stm32f2xx/board/CubeMX_Config/Src/stm32f2xx_hal_msp.c +++ b/bsp/stm32/libraries/templates/stm32f2xx/board/CubeMX_Config/Src/stm32f2xx_hal_msp.c @@ -2,7 +2,7 @@ /** ****************************************************************************** * File Name : stm32f2xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** * @attention @@ -32,7 +32,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -93,11 +93,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -117,11 +117,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART6_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART6_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); - /**USART6 GPIO Configuration + /**USART6 GPIO Configuration PC6 ------> USART6_TX - PC7 ------> USART6_RX + PC7 ------> USART6_RX */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -152,10 +152,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration + + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); @@ -170,10 +170,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART6_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART6_CLK_DISABLE(); - - /**USART6 GPIO Configuration + + /**USART6 GPIO Configuration PC6 ------> USART6_TX - PC7 ------> USART6_RX + PC7 ------> USART6_RX */ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_6|GPIO_PIN_7); diff --git a/bsp/stm32/libraries/templates/stm32f4xx/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/libraries/templates/stm32f4xx/board/CubeMX_Config/CubeMX_Config.ioc index 819eb4c535..af20b2f559 100644 --- a/bsp/stm32/libraries/templates/stm32f4xx/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/libraries/templates/stm32f4xx/board/CubeMX_Config/CubeMX_Config.ioc @@ -33,14 +33,18 @@ NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false NVIC.USART1_IRQn=true\:0\:0\:false\:false\:true\:true NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false +PA9.GPIOParameters=GPIO_PuPd +PA9.GPIO_PuPd=GPIO_PULLUP +PA9.Mode=Asynchronous +PA9.Signal=USART1_TX +PA10.GPIOParameters=GPIO_PuPd +PA10.GPIO_PuPd=GPIO_PULLUP PA10.Mode=Asynchronous PA10.Signal=USART1_RX PA13.Mode=Serial_Wire PA13.Signal=SYS_JTMS-SWDIO PA14.Mode=Serial_Wire PA14.Signal=SYS_JTCK-SWCLK -PA9.Mode=Asynchronous -PA9.Signal=USART1_TX PCC.Checker=false PCC.Line=STM32F407/417 PCC.MCU=STM32F407Z(E-G)Tx diff --git a/bsp/stm32/libraries/templates/stm32f4xx/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c b/bsp/stm32/libraries/templates/stm32f4xx/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c index e00b8556d6..5317e6153f 100644 --- a/bsp/stm32/libraries/templates/stm32f4xx/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c +++ b/bsp/stm32/libraries/templates/stm32f4xx/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c @@ -2,12 +2,12 @@ /** ****************************************************************************** * File Name : stm32f4xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** ** This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether + * USER CODE END. Other portions of this file, whether * inserted by the user or by software development tools * are owned by their respective copyright owners. * @@ -52,7 +52,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -114,11 +114,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -154,10 +154,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration + + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); diff --git a/bsp/stm32/libraries/templates/stm32f7xx/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/libraries/templates/stm32f7xx/board/CubeMX_Config/CubeMX_Config.ioc index f448b00af0..48a95f7173 100644 --- a/bsp/stm32/libraries/templates/stm32f7xx/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/libraries/templates/stm32f7xx/board/CubeMX_Config/CubeMX_Config.ioc @@ -32,12 +32,14 @@ NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false -PA10.Locked=true -PA10.Mode=Asynchronous -PA10.Signal=USART1_RX -PA9.Locked=true +PA9.GPIOParameters=GPIO_PuPd +PA9.GPIO_PuPd=GPIO_PULLUP PA9.Mode=Asynchronous PA9.Signal=USART1_TX +PA10.GPIOParameters=GPIO_PuPd +PA10.GPIO_PuPd=GPIO_PULLUP +PA10.Mode=Asynchronous +PA10.Signal=USART1_RX PCC.Checker=false PCC.Line=STM32F7x7 PCC.MCU=STM32F767I(G-I)Tx diff --git a/bsp/stm32/libraries/templates/stm32f7xx/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c b/bsp/stm32/libraries/templates/stm32f7xx/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c index 14389e19c8..5d95c709fb 100644 --- a/bsp/stm32/libraries/templates/stm32f7xx/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c +++ b/bsp/stm32/libraries/templates/stm32f7xx/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c @@ -2,12 +2,12 @@ /** ****************************************************************************** * File Name : stm32f7xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** ** This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether + * USER CODE END. Other portions of this file, whether * inserted by the user or by software development tools * are owned by their respective copyright owners. * @@ -52,7 +52,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -114,15 +114,15 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF7_USART1; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); @@ -151,10 +151,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration + + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); diff --git a/bsp/stm32/libraries/templates/stm32h7xx/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/libraries/templates/stm32h7xx/board/CubeMX_Config/CubeMX_Config.ioc index 9e9e62d7db..714cc55bde 100644 --- a/bsp/stm32/libraries/templates/stm32h7xx/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/libraries/templates/stm32h7xx/board/CubeMX_Config/CubeMX_Config.ioc @@ -34,16 +34,18 @@ NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false NVIC.USART1_IRQn=true\:0\:0\:false\:false\:true\:true NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false -PA10.Locked=true +PA9.GPIOParameters=GPIO_PuPd +PA9.GPIO_PuPd=GPIO_PULLUP +PA9.Mode=Asynchronous +PA9.Signal=USART1_TX +PA10.GPIOParameters=GPIO_PuPd +PA10.GPIO_PuPd=GPIO_PULLUP PA10.Mode=Asynchronous PA10.Signal=USART1_RX PA13\ (JTMS/SWDIO).Mode=Serial_Wire PA13\ (JTMS/SWDIO).Signal=SYS_JTMS-SWDIO PA14\ (JTCK/SWCLK).Mode=Serial_Wire PA14\ (JTCK/SWCLK).Signal=SYS_JTCK-SWCLK -PA9.Locked=true -PA9.Mode=Asynchronous -PA9.Signal=USART1_TX PCC.Checker=false PCC.Line=STM32H743/753 PCC.MCU=STM32H743IITx diff --git a/bsp/stm32/libraries/templates/stm32h7xx/board/CubeMX_Config/Src/stm32h7xx_hal_msp.c b/bsp/stm32/libraries/templates/stm32h7xx/board/CubeMX_Config/Src/stm32h7xx_hal_msp.c index 5068dde011..552069eb52 100644 --- a/bsp/stm32/libraries/templates/stm32h7xx/board/CubeMX_Config/Src/stm32h7xx_hal_msp.c +++ b/bsp/stm32/libraries/templates/stm32h7xx/board/CubeMX_Config/Src/stm32h7xx_hal_msp.c @@ -2,12 +2,12 @@ /** ****************************************************************************** * File Name : stm32h7xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** ** This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether + * USER CODE END. Other portions of this file, whether * inserted by the user or by software development tools * are owned by their respective copyright owners. * @@ -52,7 +52,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -113,15 +113,15 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Alternate = GPIO_AF7_USART1; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); @@ -153,10 +153,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration + + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); diff --git a/bsp/stm32/libraries/templates/stm32l1xx/board/CubeMX_Config/Src/stm32l1xx_hal_msp.c b/bsp/stm32/libraries/templates/stm32l1xx/board/CubeMX_Config/Src/stm32l1xx_hal_msp.c index 395a337aac..b0a59f2049 100644 --- a/bsp/stm32/libraries/templates/stm32l1xx/board/CubeMX_Config/Src/stm32l1xx_hal_msp.c +++ b/bsp/stm32/libraries/templates/stm32l1xx/board/CubeMX_Config/Src/stm32l1xx_hal_msp.c @@ -2,7 +2,7 @@ /** ****************************************************************************** * File Name : stm32l1xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** * @attention @@ -32,7 +32,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -138,12 +138,12 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**SPI1 GPIO Configuration + /**SPI1 GPIO Configuration PA5 ------> SPI1_SCK PA6 ------> SPI1_MISO - PA7 ------> SPI1_MOSI + PA7 ------> SPI1_MOSI */ GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -174,11 +174,11 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI1_CLK_DISABLE(); - - /**SPI1 GPIO Configuration + + /**SPI1 GPIO Configuration PA5 ------> SPI1_SCK PA6 ------> SPI1_MISO - PA7 ------> SPI1_MOSI + PA7 ------> SPI1_MOSI */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7); @@ -205,11 +205,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -232,11 +232,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART2 GPIO Configuration + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -270,10 +270,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration + + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); @@ -290,10 +290,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART2_CLK_DISABLE(); - - /**USART2 GPIO Configuration + + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3); diff --git a/bsp/stm32/libraries/templates/stm32l4xx/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/libraries/templates/stm32l4xx/board/CubeMX_Config/CubeMX_Config.ioc index 7cc72b8dbf..63350ae9c7 100644 --- a/bsp/stm32/libraries/templates/stm32l4xx/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/libraries/templates/stm32l4xx/board/CubeMX_Config/CubeMX_Config.ioc @@ -33,14 +33,18 @@ NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false NVIC.USART1_IRQn=true\:0\:0\:false\:false\:true\:true NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false +PA9.GPIOParameters=GPIO_PuPd +PA9.GPIO_PuPd=GPIO_PULLUP +PA9.Mode=Asynchronous +PA9.Signal=USART1_TX +PA10.GPIOParameters=GPIO_PuPd +PA10.GPIO_PuPd=GPIO_PULLUP PA10.Mode=Asynchronous PA10.Signal=USART1_RX PA13\ (JTMS-SWDIO).Mode=Serial_Wire PA13\ (JTMS-SWDIO).Signal=SYS_JTMS-SWDIO PA14\ (JTCK-SWCLK).Mode=Serial_Wire PA14\ (JTCK-SWCLK).Signal=SYS_JTCK-SWCLK -PA9.Mode=Asynchronous -PA9.Signal=USART1_TX PCC.Checker=true PCC.Line=STM32L4x5 PCC.MCU=STM32L475V(C-E-G)Tx diff --git a/bsp/stm32/libraries/templates/stm32l4xx/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c b/bsp/stm32/libraries/templates/stm32l4xx/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c index c973d3d2c1..656979eb4d 100644 --- a/bsp/stm32/libraries/templates/stm32l4xx/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c +++ b/bsp/stm32/libraries/templates/stm32l4xx/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c @@ -2,12 +2,12 @@ /** ****************************************************************************** * File Name : stm32l4xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** ** This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether + * USER CODE END. Other portions of this file, whether * inserted by the user or by software development tools * are owned by their respective copyright owners. * @@ -52,7 +52,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -114,15 +114,15 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF7_USART1; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); @@ -154,10 +154,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration + + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); diff --git a/bsp/stm32/libraries/templates/stm32mp1xx/board/CubeMX_Config/CM4/Src/stm32mp1xx_hal_msp.c b/bsp/stm32/libraries/templates/stm32mp1xx/board/CubeMX_Config/CM4/Src/stm32mp1xx_hal_msp.c index efb81996fa..1fe94b4913 100644 --- a/bsp/stm32/libraries/templates/stm32mp1xx/board/CubeMX_Config/CM4/Src/stm32mp1xx_hal_msp.c +++ b/bsp/stm32/libraries/templates/stm32mp1xx/board/CubeMX_Config/CM4/Src/stm32mp1xx_hal_msp.c @@ -2,7 +2,7 @@ /** ****************************************************************************** * File Name : stm32mp1xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** * @attention @@ -33,7 +33,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -59,7 +59,7 @@ /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ - + void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); /** * Initializes the Global MSP. @@ -77,11 +77,11 @@ void HAL_MspInit(void) /* USER CODE BEGIN MspInit 1 */ if(IS_ENGINEERING_BOOT_MODE()) { -#if defined(BSP_USING_ADC) || defined(BSP_USING_DAC) +#if defined(BSP_USING_ADC) || defined(BSP_USING_DAC) /* Configure PMIC */ BSP_PMIC_Init(); BSP_PMIC_InitRegulators(); - + __HAL_RCC_VREF_CLK_ENABLE(); HAL_SYSCFG_VREFBUF_HighImpedanceConfig(SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE); HAL_SYSCFG_EnableVREFBUF(); @@ -107,7 +107,7 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) /* USER CODE END ADC2_MspInit 0 */ if(IS_ENGINEERING_BOOT_MODE()) { - /** Initializes the peripherals clock + /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PER; @@ -120,10 +120,10 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) /* Peripheral clock enable */ __HAL_RCC_ADC12_CLK_ENABLE(); - + __HAL_RCC_GPIOF_CLK_ENABLE(); - /**ADC2 GPIO Configuration - PF14 ------> ADC2_INP6 + /**ADC2 GPIO Configuration + PF14 ------> ADC2_INP6 */ GPIO_InitStruct.Pin = GPIO_PIN_14; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; @@ -150,9 +150,9 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) /* USER CODE END ADC2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_ADC12_CLK_DISABLE(); - - /**ADC2 GPIO Configuration - PF14 ------> ADC2_INP6 + + /**ADC2 GPIO Configuration + PF14 ------> ADC2_INP6 */ HAL_GPIO_DeInit(GPIOF, GPIO_PIN_14); @@ -179,10 +179,10 @@ void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac) /* USER CODE END DAC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_DAC12_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**DAC1 GPIO Configuration - PA4 ------> DAC1_OUT1 + /**DAC1 GPIO Configuration + PA4 ------> DAC1_OUT1 */ GPIO_InitStruct.Pin = GPIO_PIN_4; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; @@ -210,9 +210,9 @@ void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac) /* USER CODE END DAC1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_DAC12_CLK_DISABLE(); - - /**DAC1 GPIO Configuration - PA4 ------> DAC1_OUT1 + + /**DAC1 GPIO Configuration + PA4 ------> DAC1_OUT1 */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_4); @@ -292,7 +292,7 @@ void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef* hlptim) /* USER CODE END LPTIM1_MspInit 0 */ if(IS_ENGINEERING_BOOT_MODE()) { - /** Initializes the peripherals clock + /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPTIM1; PeriphClkInit.Lptim1ClockSelection = RCC_LPTIM1CLKSOURCE_PCLK1; @@ -320,7 +320,7 @@ void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef* hlptim) if(IS_ENGINEERING_BOOT_MODE()) { - /** Initializes the peripherals clock + /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPTIM23; PeriphClkInit.Lptim23ClockSelection = RCC_LPTIM23CLKSOURCE_PCLK3; @@ -348,7 +348,7 @@ void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef* hlptim) if(IS_ENGINEERING_BOOT_MODE()) { - /** Initializes the peripherals clock + /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPTIM23; PeriphClkInit.Lptim23ClockSelection = RCC_LPTIM23CLKSOURCE_PCLK3; @@ -376,7 +376,7 @@ void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef* hlptim) if(IS_ENGINEERING_BOOT_MODE()) { - /** Initializes the peripherals clock + /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPTIM45; PeriphClkInit.Lptim45ClockSelection = RCC_LPTIM45CLKSOURCE_PCLK3; @@ -404,7 +404,7 @@ void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef* hlptim) if(IS_ENGINEERING_BOOT_MODE()) { - /** Initializes the peripherals clock + /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPTIM45; PeriphClkInit.Lptim45ClockSelection = RCC_LPTIM45CLKSOURCE_PCLK3; @@ -525,7 +525,7 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI5_MspInit 0 */ if(IS_ENGINEERING_BOOT_MODE()) { - /** Initializes the peripherals clock + /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SPI45; PeriphClkInit.Spi45ClockSelection = RCC_SPI45CLKSOURCE_PCLK2; @@ -538,11 +538,11 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* Peripheral clock enable */ __HAL_RCC_SPI5_CLK_ENABLE(); - + __HAL_RCC_GPIOF_CLK_ENABLE(); - /**SPI5 GPIO Configuration + /**SPI5 GPIO Configuration PF9 ------> SPI5_MOSI - PF7 ------> SPI5_SCK + PF7 ------> SPI5_SCK */ GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -573,10 +573,10 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI5_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI5_CLK_DISABLE(); - - /**SPI5 GPIO Configuration + + /**SPI5 GPIO Configuration PF9 ------> SPI5_MOSI - PF7 ------> SPI5_SCK + PF7 ------> SPI5_SCK */ HAL_GPIO_DeInit(GPIOF, GPIO_PIN_9|GPIO_PIN_7); @@ -650,10 +650,10 @@ void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) /* USER CODE BEGIN TIM4_MspPostInit 0 */ /* USER CODE END TIM4_MspPostInit 0 */ - + __HAL_RCC_GPIOD_CLK_ENABLE(); - /**TIM4 GPIO Configuration - PD13 ------> TIM4_CH2 + /**TIM4 GPIO Configuration + PD13 ------> TIM4_CH2 */ GPIO_InitStruct.Pin = GPIO_PIN_13; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -740,7 +740,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END UART4_MspInit 0 */ if(IS_ENGINEERING_BOOT_MODE()) { - /** Initializes the peripherals clock + /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_UART24; PeriphClkInit.Uart24ClockSelection = RCC_UART24CLKSOURCE_HSI; @@ -753,23 +753,23 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* Peripheral clock enable */ __HAL_RCC_UART4_CLK_ENABLE(); - + __HAL_RCC_GPIOG_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); - /**UART4 GPIO Configuration + /**UART4 GPIO Configuration PG11 ------> UART4_TX - PB2 ------> UART4_RX + PB2 ------> UART4_RX */ GPIO_InitStruct.Pin = STLINK_RX_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Alternate = GPIO_AF6_UART4; HAL_GPIO_Init(STLINK_RX_GPIO_Port, &GPIO_InitStruct); GPIO_InitStruct.Pin = STLINK_TX_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Alternate = GPIO_AF8_UART4; HAL_GPIO_Init(STLINK_TX_GPIO_Port, &GPIO_InitStruct); @@ -785,7 +785,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) if(IS_ENGINEERING_BOOT_MODE()) { - /** Initializes the peripherals clock + /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_UART35; PeriphClkInit.Uart35ClockSelection = RCC_UART35CLKSOURCE_PCLK1; @@ -798,22 +798,22 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* Peripheral clock enable */ __HAL_RCC_USART3_CLK_ENABLE(); - + __HAL_RCC_GPIOB_CLK_ENABLE(); - /**USART3 GPIO Configuration + /**USART3 GPIO Configuration PB10 ------> USART3_TX - PB12 ------> USART3_RX + PB12 ------> USART3_RX */ GPIO_InitStruct.Pin = GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Alternate = GPIO_AF7_USART3; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); GPIO_InitStruct.Pin = GPIO_PIN_12; GPIO_InitStruct.Mode = GPIO_MODE_AF; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Alternate = GPIO_AF8_USART3; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); @@ -839,10 +839,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END UART4_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_UART4_CLK_DISABLE(); - - /**UART4 GPIO Configuration + + /**UART4 GPIO Configuration PG11 ------> UART4_TX - PB2 ------> UART4_RX + PB2 ------> UART4_RX */ HAL_GPIO_DeInit(STLINK_RX_GPIO_Port, STLINK_RX_Pin); @@ -859,10 +859,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART3_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART3_CLK_DISABLE(); - - /**USART3 GPIO Configuration + + /**USART3 GPIO Configuration PB10 ------> USART3_TX - PB12 ------> USART3_RX + PB12 ------> USART3_RX */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_10|GPIO_PIN_12); @@ -908,12 +908,12 @@ void HAL_I2C_MspInit(I2C_HandleTypeDef *hI2c) { GPIO_InitTypeDef GPIO_InitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - + if(hI2c->Instance == I2C4) { if(IS_ENGINEERING_BOOT_MODE()) { - /*** Configure the I2C peripheral clock ***/ + /*** Configure the I2C peripheral clock ***/ PeriphClkInit.I2c46ClockSelection = RCC_I2C46CLKSOURCE_HSI; PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C46; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) @@ -935,11 +935,11 @@ void HAL_I2C_MspInit(I2C_HandleTypeDef *hI2c) /* Enable I2C clock */ __HAL_RCC_I2C4_CLK_ENABLE(); - /* Force the I2C peripheral clock reset */ + /* Force the I2C peripheral clock reset */ __HAL_RCC_I2C4_FORCE_RESET(); - /* Release the I2C peripheral clock reset */ + /* Release the I2C peripheral clock reset */ __HAL_RCC_I2C4_RELEASE_RESET(); - + HAL_NVIC_SetPriority(I2C4_ER_IRQn, 0, 1); HAL_NVIC_EnableIRQ(I2C4_ER_IRQn); HAL_NVIC_SetPriority(I2C4_EV_IRQn, 0, 2); @@ -955,7 +955,7 @@ void HAL_I2C_MspInit(I2C_HandleTypeDef *hI2c) void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hI2c) { GPIO_InitTypeDef GPIO_InitStruct = {0}; - + if(hI2c->Instance == I2C4) { /* Configure I2C Tx, Rx as alternate function */ diff --git a/bsp/stm32/libraries/templates/stm32wbxx/board/CubeMX_Config/Src/stm32wbxx_hal_msp.c b/bsp/stm32/libraries/templates/stm32wbxx/board/CubeMX_Config/Src/stm32wbxx_hal_msp.c index 9e31cfedd8..98fd3fc9a5 100644 --- a/bsp/stm32/libraries/templates/stm32wbxx/board/CubeMX_Config/Src/stm32wbxx_hal_msp.c +++ b/bsp/stm32/libraries/templates/stm32wbxx/board/CubeMX_Config/Src/stm32wbxx_hal_msp.c @@ -98,7 +98,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Alternate = GPIO_AF7_USART1; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); diff --git a/bsp/stm32/stm32f072-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f072-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc index e62fa13da5..1009ded5e2 100644 --- a/bsp/stm32/stm32f072-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32f072-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc @@ -44,7 +44,7 @@ PA14.Signal=SYS_SWCLK PA2.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode PA2.GPIO_Label=USART_TX PA2.GPIO_Mode=GPIO_MODE_AF_PP -PA2.GPIO_PuPd=GPIO_NOPULL +PA2.GPIO_PuPd=GPIO_PULLUP PA2.GPIO_Speed=GPIO_SPEED_FREQ_LOW PA2.Locked=true PA2.Mode=Asynchronous @@ -52,7 +52,7 @@ PA2.Signal=USART2_TX PA3.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode PA3.GPIO_Label=USART_RX PA3.GPIO_Mode=GPIO_MODE_AF_PP -PA3.GPIO_PuPd=GPIO_NOPULL +PA3.GPIO_PuPd=GPIO_PULLUP PA3.GPIO_Speed=GPIO_SPEED_FREQ_LOW PA3.Locked=true PA3.Mode=Asynchronous diff --git a/bsp/stm32/stm32f072-st-nucleo/board/CubeMX_Config/Src/stm32f0xx_hal_msp.c b/bsp/stm32/stm32f072-st-nucleo/board/CubeMX_Config/Src/stm32f0xx_hal_msp.c index 907465857b..7fd27fea17 100644 --- a/bsp/stm32/stm32f072-st-nucleo/board/CubeMX_Config/Src/stm32f0xx_hal_msp.c +++ b/bsp/stm32/stm32f072-st-nucleo/board/CubeMX_Config/Src/stm32f0xx_hal_msp.c @@ -2,12 +2,12 @@ /** ****************************************************************************** * File Name : stm32f0xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** ** This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether + * USER CODE END. Other portions of this file, whether * inserted by the user or by software development tools * are owned by their respective copyright owners. * @@ -52,7 +52,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -113,15 +113,15 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART2 GPIO Configuration + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ GPIO_InitStruct.Pin = USART_TX_Pin|USART_RX_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Alternate = GPIO_AF1_USART2; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); @@ -148,10 +148,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART2_CLK_DISABLE(); - - /**USART2 GPIO Configuration + + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ HAL_GPIO_DeInit(GPIOA, USART_TX_Pin|USART_RX_Pin); diff --git a/bsp/stm32/stm32f091-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f091-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc index 75eb3b8646..d1e0132661 100644 --- a/bsp/stm32/stm32f091-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32f091-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc @@ -37,9 +37,9 @@ Mcu.Pin4=PA3 Mcu.Pin5=PA6 Mcu.Pin6=PA7 Mcu.Pin7=PB11 -Mcu.Pin8=PA8 -Mcu.Pin9=PA9 -Mcu.PinsNb=21 +Mcu.Pin8=PA9 +Mcu.Pin9=PA10 +Mcu.PinsNb=20 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32F091RCTx @@ -52,23 +52,29 @@ NVIC.SVC_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true PA0.Mode=IN0 PA0.Signal=ADC_IN0 -PA10.Mode=Synchronous +PA10.GPIOParameters=GPIO_PuPd +PA10.GPIO_PuPd=GPIO_PULLUP +PA10.Mode=Asynchronous PA10.Signal=USART1_RX PA13.Mode=Serial_Wire PA13.Signal=SYS_SWDIO PA14.Mode=Serial_Wire PA14.Signal=SYS_SWCLK +PA2.GPIOParameters=GPIO_PuPd +PA2.GPIO_PuPd=GPIO_PULLUP PA2.Mode=Asynchronous PA2.Signal=USART2_TX +PA3.GPIOParameters=GPIO_PuPd +PA3.GPIO_PuPd=GPIO_PULLUP PA3.Mode=Asynchronous PA3.Signal=USART2_RX PA6.Mode=Full_Duplex_Master PA6.Signal=SPI1_MISO PA7.Mode=Full_Duplex_Master PA7.Signal=SPI1_MOSI -PA8.Mode=Synchronous -PA8.Signal=USART1_CK -PA9.Mode=Synchronous +PA9.GPIOParameters=GPIO_PuPd +PA9.GPIO_PuPd=GPIO_PULLUP +PA9.Mode=Asynchronous PA9.Signal=USART1_TX PB11.Signal=S_TIM2_CH4 PB3.Locked=true @@ -147,8 +153,8 @@ SPI1.Mode=SPI_MODE_MASTER SPI1.VirtualType=VM_MASTER TIM2.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4 TIM2.IPParameters=Channel-PWM Generation4 CH4 -USART1.IPParameters=VirtualMode-Synchronous -USART1.VirtualMode-Synchronous=VM_SYNC +USART1.IPParameters=VirtualMode-Asynchronous +USART1.VirtualMode-Asynchronous=VM_ASYNC USART2.IPParameters=VirtualMode-Asynchronous USART2.VirtualMode-Asynchronous=VM_ASYNC VP_IWDG_VS_IWDG.Mode=IWDG_Activate diff --git a/bsp/stm32/stm32f091-st-nucleo/board/CubeMX_Config/Src/stm32f0xx_hal_msp.c b/bsp/stm32/stm32f091-st-nucleo/board/CubeMX_Config/Src/stm32f0xx_hal_msp.c index 112b9931e2..700fcc0dfd 100644 --- a/bsp/stm32/stm32f091-st-nucleo/board/CubeMX_Config/Src/stm32f0xx_hal_msp.c +++ b/bsp/stm32/stm32f091-st-nucleo/board/CubeMX_Config/Src/stm32f0xx_hal_msp.c @@ -2,12 +2,12 @@ /** ****************************************************************************** * File Name : stm32f0xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** ** This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether + * USER CODE END. Other portions of this file, whether * inserted by the user or by software development tools * are owned by their respective copyright owners. * @@ -52,7 +52,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -78,7 +78,7 @@ /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ - + void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); /** * Initializes the Global MSP. @@ -115,10 +115,10 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) /* USER CODE END ADC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_ADC1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**ADC GPIO Configuration - PA0 ------> ADC_IN0 + /**ADC GPIO Configuration + PA0 ------> ADC_IN0 */ GPIO_InitStruct.Pin = GPIO_PIN_0; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; @@ -147,9 +147,9 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) /* USER CODE END ADC1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_ADC1_CLK_DISABLE(); - - /**ADC GPIO Configuration - PA0 ------> ADC_IN0 + + /**ADC GPIO Configuration + PA0 ------> ADC_IN0 */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_0); @@ -220,13 +220,13 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); - /**SPI1 GPIO Configuration + /**SPI1 GPIO Configuration PA6 ------> SPI1_MISO PA7 ------> SPI1_MOSI - PB3 ------> SPI1_SCK + PB3 ------> SPI1_SCK */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -264,11 +264,11 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI1_CLK_DISABLE(); - - /**SPI1 GPIO Configuration + + /**SPI1 GPIO Configuration PA6 ------> SPI1_MISO PA7 ------> SPI1_MOSI - PB3 ------> SPI1_SCK + PB3 ------> SPI1_SCK */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_6|GPIO_PIN_7); @@ -344,10 +344,10 @@ void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) /* USER CODE BEGIN TIM2_MspPostInit 0 */ /* USER CODE END TIM2_MspPostInit 0 */ - + __HAL_RCC_GPIOB_CLK_ENABLE(); - /**TIM2 GPIO Configuration - PB11 ------> TIM2_CH4 + /**TIM2 GPIO Configuration + PB11 ------> TIM2_CH4 */ GPIO_InitStruct.Pin = GPIO_PIN_11; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -417,43 +417,6 @@ void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base) } -/** -* @brief USART MSP Initialization -* This function configures the hardware resources used in this example -* @param husart: USART handle pointer -* @retval None -*/ -void HAL_USART_MspInit(USART_HandleTypeDef* husart) -{ - GPIO_InitTypeDef GPIO_InitStruct = {0}; - if(husart->Instance==USART1) - { - /* USER CODE BEGIN USART1_MspInit 0 */ - - /* USER CODE END USART1_MspInit 0 */ - /* Peripheral clock enable */ - __HAL_RCC_USART1_CLK_ENABLE(); - - __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART1 GPIO Configuration - PA8 ------> USART1_CK - PA9 ------> USART1_TX - PA10 ------> USART1_RX - */ - GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF1_USART1; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /* USER CODE BEGIN USART1_MspInit 1 */ - - /* USER CODE END USART1_MspInit 1 */ - } - -} - /** * @brief UART MSP Initialization * This function configures the hardware resources used in this example @@ -463,22 +426,46 @@ void HAL_USART_MspInit(USART_HandleTypeDef* husart) void HAL_UART_MspInit(UART_HandleTypeDef* huart) { GPIO_InitTypeDef GPIO_InitStruct = {0}; - if(huart->Instance==USART2) + if(huart->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspInit 0 */ + + /* USER CODE END USART1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_USART1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USART1 GPIO Configuration + PA9 ------> USART1_TX + PA10 ------> USART1_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF1_USART1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN USART1_MspInit 1 */ + + /* USER CODE END USART1_MspInit 1 */ + } + else if(huart->Instance==USART2) { /* USER CODE BEGIN USART2_MspInit 0 */ /* USER CODE END USART2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART2 GPIO Configuration + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; GPIO_InitStruct.Alternate = GPIO_AF1_USART2; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); @@ -490,36 +477,6 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) } -/** -* @brief USART MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param husart: USART handle pointer -* @retval None -*/ -void HAL_USART_MspDeInit(USART_HandleTypeDef* husart) -{ - if(husart->Instance==USART1) - { - /* USER CODE BEGIN USART1_MspDeInit 0 */ - - /* USER CODE END USART1_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration - PA8 ------> USART1_CK - PA9 ------> USART1_TX - PA10 ------> USART1_RX - */ - HAL_GPIO_DeInit(GPIOA, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10); - - /* USER CODE BEGIN USART1_MspDeInit 1 */ - - /* USER CODE END USART1_MspDeInit 1 */ - } - -} - /** * @brief UART MSP De-Initialization * This function freeze the hardware resources used in this example @@ -528,17 +485,35 @@ void HAL_USART_MspDeInit(USART_HandleTypeDef* husart) */ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) { - if(huart->Instance==USART2) + if(huart->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspDeInit 0 */ + + /* USER CODE END USART1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART1_CLK_DISABLE(); + + /**USART1 GPIO Configuration + PA9 ------> USART1_TX + PA10 ------> USART1_RX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); + + /* USER CODE BEGIN USART1_MspDeInit 1 */ + + /* USER CODE END USART1_MspDeInit 1 */ + } + else if(huart->Instance==USART2) { /* USER CODE BEGIN USART2_MspDeInit 0 */ /* USER CODE END USART2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART2_CLK_DISABLE(); - - /**USART2 GPIO Configuration + + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3); diff --git a/bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c b/bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c index a38a7f26b1..e113c72475 100644 --- a/bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c +++ b/bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c @@ -2,12 +2,12 @@ /** ****************************************************************************** * File Name : stm32f1xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** ** This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether + * USER CODE END. Other portions of this file, whether * inserted by the user or by software development tools * are owned by their respective copyright owners. * @@ -52,7 +52,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -78,7 +78,7 @@ /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ - + void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); /** * Initializes the Global MSP. @@ -94,7 +94,7 @@ void HAL_MspInit(void) /* System interrupt init*/ - /**NOJTAG: JTAG-DP Disabled and SW-DP Enabled + /**NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); @@ -120,10 +120,10 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) /* USER CODE END ADC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_ADC1_CLK_ENABLE(); - + __HAL_RCC_GPIOB_CLK_ENABLE(); - /**ADC1 GPIO Configuration - PB1 ------> ADC1_IN9 + /**ADC1 GPIO Configuration + PB1 ------> ADC1_IN9 */ GPIO_InitStruct.Pin = GPIO_PIN_1; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; @@ -153,9 +153,9 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) /* USER CODE END ADC1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_ADC1_CLK_DISABLE(); - - /**ADC1 GPIO Configuration - PB1 ------> ADC1_IN9 + + /**ADC1 GPIO Configuration + PB1 ------> ADC1_IN9 */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_1); @@ -233,12 +233,12 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI2_CLK_ENABLE(); - + __HAL_RCC_GPIOB_CLK_ENABLE(); - /**SPI2 GPIO Configuration + /**SPI2 GPIO Configuration PB13 ------> SPI2_SCK PB14 ------> SPI2_MISO - PB15 ------> SPI2_MOSI + PB15 ------> SPI2_MOSI */ GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -274,11 +274,11 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI2_CLK_DISABLE(); - - /**SPI2 GPIO Configuration + + /**SPI2 GPIO Configuration PB13 ------> SPI2_SCK PB14 ------> SPI2_MISO - PB15 ------> SPI2_MOSI + PB15 ------> SPI2_MOSI */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15); @@ -343,11 +343,11 @@ void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) /* USER CODE BEGIN TIM3_MspPostInit 0 */ /* USER CODE END TIM3_MspPostInit 0 */ - + __HAL_RCC_GPIOC_CLK_ENABLE(); - /**TIM3 GPIO Configuration + /**TIM3 GPIO Configuration PC6 ------> TIM3_CH1 - PC7 ------> TIM3_CH2 + PC7 ------> TIM3_CH2 */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -424,11 +424,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -437,7 +437,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) GPIO_InitStruct.Pin = GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); /* USART1 interrupt Init */ @@ -465,10 +465,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration + + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); diff --git a/bsp/stm32/stm32f103-atk-warshipv3/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f103-atk-warshipv3/board/CubeMX_Config/CubeMX_Config.ioc index ab50887fd8..80c986136d 100644 --- a/bsp/stm32/stm32f103-atk-warshipv3/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32f103-atk-warshipv3/board/CubeMX_Config/CubeMX_Config.ioc @@ -95,12 +95,16 @@ OSC_IN.Mode=HSE-External-Oscillator OSC_IN.Signal=RCC_OSC_IN OSC_OUT.Mode=HSE-External-Oscillator OSC_OUT.Signal=RCC_OSC_OUT +PA10.GPIOParameters=GPIO_PuPd +PA10.GPIO_PuPd=GPIO_PULLUP PA10.Mode=Asynchronous PA10.Signal=USART1_RX PA13.Mode=Serial_Wire PA13.Signal=SYS_JTMS-SWDIO PA14.Mode=Serial_Wire PA14.Signal=SYS_JTCK-SWCLK +PA9.GPIOParameters=GPIO_PuPd +PA9.GPIO_PuPd=GPIO_PULLUP PA9.Mode=Asynchronous PA9.Signal=USART1_TX PC10.Mode=SD_4_bits_Wide_bus @@ -121,14 +125,6 @@ PC8.Mode=SD_4_bits_Wide_bus PC8.Signal=SDIO_D0 PC9.Mode=SD_4_bits_Wide_bus PC9.Signal=SDIO_D1 -PCC.Checker=false -PCC.Line=STM32F103 -PCC.MCU=STM32F103Z(C-D-E)Tx -PCC.PartNumber=STM32F103ZETx -PCC.Seq0=0 -PCC.Series=STM32F1 -PCC.Temperature=25 -PCC.Vdd=3.3 PD0.Signal=FSMC_D2_DA2 PD1.Signal=FSMC_D3_DA3 PD10.Signal=FSMC_D15_DA15 @@ -184,7 +180,7 @@ ProjectManager.CustomerFirmwarePackage= ProjectManager.DefaultFWLocation=true ProjectManager.DeletePrevious=true ProjectManager.DeviceId=STM32F103ZETx -ProjectManager.FirmwarePackage=STM32Cube FW_F1 V1.8.0 +ProjectManager.FirmwarePackage=STM32Cube FW_F1 V1.8.4 ProjectManager.FreePins=false ProjectManager.HalAssertFull=false ProjectManager.HeapSize=0x200 @@ -197,11 +193,12 @@ ProjectManager.PreviousToolchain= ProjectManager.ProjectBuild=false ProjectManager.ProjectFileName=CubeMX_Config.ioc ProjectManager.ProjectName=CubeMX_Config +ProjectManager.RegisterCallBack= ProjectManager.StackSize=0x400 ProjectManager.TargetToolchain=MDK-ARM V5 ProjectManager.ToolChainLocation= ProjectManager.UnderRoot=false -ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_FSMC_Init-FSMC-false-HAL-true,5-MX_TIM3_Init-TIM3-false-HAL-true +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_FSMC_Init-FSMC-false-HAL-true,5-MX_TIM3_Init-TIM3-false-HAL-true,6-MX_SDIO_SD_Init-SDIO-false-HAL-true RCC.ADCFreqValue=36000000 RCC.AHBFreq_Value=72000000 RCC.APB1CLKDivider=RCC_HCLK_DIV2 diff --git a/bsp/stm32/stm32f103-atk-warshipv3/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c b/bsp/stm32/stm32f103-atk-warshipv3/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c index 5a7f5eedf6..f852a2c104 100644 --- a/bsp/stm32/stm32f103-atk-warshipv3/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c +++ b/bsp/stm32/stm32f103-atk-warshipv3/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c @@ -2,7 +2,7 @@ /** ****************************************************************************** * File Name : stm32f1xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** * @attention @@ -32,7 +32,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -72,7 +72,7 @@ void HAL_MspInit(void) /* System interrupt init*/ - /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled + /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); @@ -97,18 +97,18 @@ void HAL_SD_MspInit(SD_HandleTypeDef* hsd) /* USER CODE END SDIO_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SDIO_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); - /**SDIO GPIO Configuration + /**SDIO GPIO Configuration PC8 ------> SDIO_D0 PC9 ------> SDIO_D1 PC10 ------> SDIO_D2 PC11 ------> SDIO_D3 PC12 ------> SDIO_CK - PD2 ------> SDIO_CMD + PD2 ------> SDIO_CMD */ - GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 |GPIO_PIN_12; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; @@ -141,16 +141,16 @@ void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) /* USER CODE END SDIO_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SDIO_CLK_DISABLE(); - - /**SDIO GPIO Configuration + + /**SDIO GPIO Configuration PC8 ------> SDIO_D0 PC9 ------> SDIO_D1 PC10 ------> SDIO_D2 PC11 ------> SDIO_D3 PC12 ------> SDIO_CK - PD2 ------> SDIO_CMD + PD2 ------> SDIO_CMD */ - HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 |GPIO_PIN_12); HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); @@ -178,11 +178,11 @@ void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* htim_encoder) /* USER CODE END TIM3_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM3_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); - /**TIM3 GPIO Configuration + /**TIM3 GPIO Configuration PC6 ------> TIM3_CH1 - PC7 ------> TIM3_CH2 + PC7 ------> TIM3_CH2 */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; @@ -213,10 +213,10 @@ void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef* htim_encoder) /* USER CODE END TIM3_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_TIM3_CLK_DISABLE(); - - /**TIM3 GPIO Configuration + + /**TIM3 GPIO Configuration PC6 ------> TIM3_CH1 - PC7 ------> TIM3_CH2 + PC7 ------> TIM3_CH2 */ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_6|GPIO_PIN_7); @@ -243,11 +243,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -256,7 +256,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) GPIO_InitStruct.Pin = GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); /* USER CODE BEGIN USART1_MspInit 1 */ @@ -281,10 +281,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration + + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); @@ -294,73 +294,6 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) } } -/** -* @brief CAN MSP Initialization -* This function configures the hardware resources used in this example -* @param hcan: CAN handle pointer -* @retval None -*/ -void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan) -{ - GPIO_InitTypeDef GPIO_InitStruct = {0}; - if(hcan->Instance==CAN1) - { - /* USER CODE BEGIN CAN1_MspInit 0 */ - - /* USER CODE END CAN1_MspInit 0 */ - /* Peripheral clock enable */ - __HAL_RCC_CAN1_CLK_ENABLE(); - - __HAL_RCC_GPIOA_CLK_ENABLE(); - /**CAN GPIO Configuration - PA11 ------> CAN_RX - PA12 ------> CAN_TX - */ - GPIO_InitStruct.Pin = GPIO_PIN_11; - GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = GPIO_PIN_12; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /* USER CODE BEGIN CAN1_MspInit 1 */ - - /* USER CODE END CAN1_MspInit 1 */ - } - -} -/** -* @brief CAN MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param hcan: CAN handle pointer -* @retval None -*/ -void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) -{ - if(hcan->Instance==CAN1) - { - /* USER CODE BEGIN CAN1_MspDeInit 0 */ - - /* USER CODE END CAN1_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_CAN1_CLK_DISABLE(); - - /**CAN GPIO Configuration - PA11 ------> CAN_RX - PA12 ------> CAN_TX - */ - HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11|GPIO_PIN_12); - - /* USER CODE BEGIN CAN1_MspDeInit 1 */ - - /* USER CODE END CAN1_MspDeInit 1 */ - } - -} - static uint32_t FSMC_Initialized = 0; @@ -376,8 +309,8 @@ static void HAL_FSMC_MspInit(void){ /* Peripheral clock enable */ __HAL_RCC_FSMC_CLK_ENABLE(); - - /** FSMC GPIO Configuration + + /** FSMC GPIO Configuration PF0 ------> FSMC_A0 PF1 ------> FSMC_A1 PF2 ------> FSMC_A2 @@ -419,28 +352,28 @@ static void HAL_FSMC_MspInit(void){ PE0 ------> FSMC_NBL0 PE1 ------> FSMC_NBL1 */ - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 - |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_13 + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_13 |GPIO_PIN_14|GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 - |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 + GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 + |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 - |GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15 + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + |GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15 |GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; @@ -473,8 +406,8 @@ static void HAL_FSMC_MspDeInit(void){ FSMC_DeInitialized = 1; /* Peripheral clock enable */ __HAL_RCC_FSMC_CLK_DISABLE(); - - /** FSMC GPIO Configuration + + /** FSMC GPIO Configuration PF0 ------> FSMC_A0 PF1 ------> FSMC_A1 PF2 ------> FSMC_A2 @@ -516,19 +449,19 @@ static void HAL_FSMC_MspDeInit(void){ PE0 ------> FSMC_NBL0 PE1 ------> FSMC_NBL1 */ - HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 - |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_13 + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_13 |GPIO_PIN_14|GPIO_PIN_15); - HAL_GPIO_DeInit(GPIOG, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_10); - HAL_GPIO_DeInit(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 - |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 + HAL_GPIO_DeInit(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 + |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1); - HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 - |GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15 + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + |GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15 |GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5); /* USER CODE BEGIN FSMC_MspDeInit 1 */ diff --git a/bsp/stm32/stm32f103-blue-pill/README.md b/bsp/stm32/stm32f103-blue-pill/README.md index 8911c66fc1..e7627e64a1 100644 --- a/bsp/stm32/stm32f103-blue-pill/README.md +++ b/bsp/stm32/stm32f103-blue-pill/README.md @@ -238,6 +238,12 @@ Each peripheral supporting condition for this BSP is as follows: +### 3.9 How to create RT-Studio Project + +- [RT-Thread RTOS Tutorial #3 | Advanced Skills - YouTube](https://www.youtube.com/watch?v=k4-ArvvIiR8) + + + ## 4 **Advanced Features** This BSP only enables GPIO and USART1 by default. If you need more advanced features such as SPI, ADC, or to add software packages, you need to configure the BSP with RT-Thread [ENV tool](https://www.rt-thread.io/download.html?download=Env), as follows: @@ -292,7 +298,7 @@ Re-plug the USB cable and you will find a new serial (virtual com, 115200, 8-N-1 ### 4.2 How to extend Blue Pill board’s Flash space -According to ST official datasheet, STM32F103C8 has 64KB of Flash. However, STM32F103C8 and STM32F103CB use the same type of silicon die, which means STM32F103C8 also has 128KB ROM in theory, but ST locked the high 64KB. Basically, to force the debugger to download program can unlock the high 64KB. There is a good news that **Keil5 will help you to unlock the Blue Pill Board high 64KB block** if you use Blue Pill Board BSP as a template to create your project. You just need to press the "Flash Download" button as usual. What you only need to remember is that Blue Pill board has 128KB of Flash rather than 64KB. +According to ST official datasheet, STM32F103C8 has 64KB of Flash. However, STM32F103C8 and STM32F103CB use the same type of silicon die, which means STM32F103C8 also has 128KB ROM in theory, but ST locked the high 64KB. Basically, to force the debugger to download program can unlock the high 64KB. There is a good news that **Keil5 / IAR / RT-Studio will help you to unlock the Blue Pill Board high 64KB block** if you use this Blue Pill Board BSP as a template to create your project. You just need to press the "Flash Download" button as usual. What you only need to remember is that Blue Pill board has 128KB of Flash rather than 64KB. @@ -309,8 +315,7 @@ According to ST official datasheet, STM32F103C8 has 64KB of Flash. However, STM3 ## 6 Maintained By -Meco Man @ RT-Thread Community +[Meco Man](https://github.com/mysterywolf) @ RT-Thread Community jiantingman@foxmail.com -https://github.com/mysterywolf diff --git a/bsp/stm32/stm32f103-blue-pill/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f103-blue-pill/board/CubeMX_Config/CubeMX_Config.ioc index d9aadc3758..f3db8820e8 100644 --- a/bsp/stm32/stm32f103-blue-pill/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32f103-blue-pill/board/CubeMX_Config/CubeMX_Config.ioc @@ -57,6 +57,8 @@ NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false PA1.Signal=ADCx_IN1 +PA10.GPIOParameters=GPIO_PuPd +PA10.GPIO_PuPd=GPIO_PULLUP PA10.Mode=Asynchronous PA10.Signal=USART1_RX PA11.Mode=Device @@ -67,8 +69,12 @@ PA13.Mode=Serial_Wire PA13.Signal=SYS_JTMS-SWDIO PA14.Mode=Serial_Wire PA14.Signal=SYS_JTCK-SWCLK +PA2.GPIOParameters=GPIO_PuPd +PA2.GPIO_PuPd=GPIO_PULLUP PA2.Mode=Asynchronous PA2.Signal=USART2_TX +PA3.GPIOParameters=GPIO_PuPd +PA3.GPIO_PuPd=GPIO_PULLUP PA3.Mode=Asynchronous PA3.Signal=USART2_RX PA5.Mode=Full_Duplex_Master @@ -77,6 +83,8 @@ PA6.Mode=Full_Duplex_Master PA6.Signal=SPI1_MISO PA7.Mode=Full_Duplex_Master PA7.Signal=SPI1_MOSI +PA9.GPIOParameters=GPIO_PuPd +PA9.GPIO_PuPd=GPIO_PULLUP PA9.Mode=Asynchronous PA9.Signal=USART1_TX PC13-TAMPER-RTC.GPIOParameters=GPIO_Speed,PinState,GPIO_ModeDefaultOutputPP @@ -103,7 +111,7 @@ ProjectManager.CustomerFirmwarePackage= ProjectManager.DefaultFWLocation=true ProjectManager.DeletePrevious=true ProjectManager.DeviceId=STM32F103C8Tx -ProjectManager.FirmwarePackage=STM32Cube FW_F1 V1.8.3 +ProjectManager.FirmwarePackage=STM32Cube FW_F1 V1.8.4 ProjectManager.FreePins=false ProjectManager.HalAssertFull=false ProjectManager.HeapSize=0x200 diff --git a/bsp/stm32/stm32f103-blue-pill/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c b/bsp/stm32/stm32f103-blue-pill/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c index d48771f71d..a6d94ecced 100644 --- a/bsp/stm32/stm32f103-blue-pill/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c +++ b/bsp/stm32/stm32f103-blue-pill/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c @@ -2,7 +2,7 @@ /** ****************************************************************************** * File Name : stm32f1xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** * @attention @@ -32,7 +32,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -287,7 +287,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) GPIO_InitStruct.Pin = GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); /* USER CODE BEGIN USART1_MspInit 1 */ @@ -314,7 +314,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) GPIO_InitStruct.Pin = GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); /* USER CODE BEGIN USART2_MspInit 1 */ diff --git a/bsp/stm32/stm32f103-dofly-M3S/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f103-dofly-M3S/board/CubeMX_Config/CubeMX_Config.ioc index e897be5421..80ad293e6c 100644 --- a/bsp/stm32/stm32f103-dofly-M3S/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32f103-dofly-M3S/board/CubeMX_Config/CubeMX_Config.ioc @@ -57,6 +57,12 @@ OSC_IN.Mode=HSE-External-Oscillator OSC_IN.Signal=RCC_OSC_IN OSC_OUT.Mode=HSE-External-Oscillator OSC_OUT.Signal=RCC_OSC_OUT +PA9.GPIOParameters=GPIO_PuPd +PA9.GPIO_PuPd=GPIO_PULLUP +PA9.Mode=Asynchronous +PA9.Signal=USART1_TX +PA10.GPIOParameters=GPIO_PuPd +PA10.GPIO_PuPd=GPIO_PULLUP PA10.Mode=Asynchronous PA10.Signal=USART1_RX PA13.Mode=Serial_Wire @@ -69,8 +75,6 @@ PA6.Mode=Full_Duplex_Master PA6.Signal=SPI1_MISO PA7.Mode=Full_Duplex_Master PA7.Signal=SPI1_MOSI -PA9.Mode=Asynchronous -PA9.Signal=USART1_TX PB13.Mode=Full_Duplex_Master PB13.Signal=SPI2_SCK PB14.Mode=Full_Duplex_Master diff --git a/bsp/stm32/stm32f103-dofly-M3S/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c b/bsp/stm32/stm32f103-dofly-M3S/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c index 1efbf77d5e..e076325291 100644 --- a/bsp/stm32/stm32f103-dofly-M3S/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c +++ b/bsp/stm32/stm32f103-dofly-M3S/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c @@ -2,7 +2,7 @@ /** ****************************************************************************** * File Name : stm32f1xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** * @attention @@ -32,7 +32,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -72,7 +72,7 @@ void HAL_MspInit(void) /* System interrupt init*/ - /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled + /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); @@ -97,18 +97,18 @@ void HAL_SD_MspInit(SD_HandleTypeDef* hsd) /* USER CODE END SDIO_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SDIO_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); - /**SDIO GPIO Configuration + /**SDIO GPIO Configuration PC8 ------> SDIO_D0 PC9 ------> SDIO_D1 PC10 ------> SDIO_D2 PC11 ------> SDIO_D3 PC12 ------> SDIO_CK - PD2 ------> SDIO_CMD + PD2 ------> SDIO_CMD */ - GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 |GPIO_PIN_12; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; @@ -141,16 +141,16 @@ void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) /* USER CODE END SDIO_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SDIO_CLK_DISABLE(); - - /**SDIO GPIO Configuration + + /**SDIO GPIO Configuration PC8 ------> SDIO_D0 PC9 ------> SDIO_D1 PC10 ------> SDIO_D2 PC11 ------> SDIO_D3 PC12 ------> SDIO_CK - PD2 ------> SDIO_CMD + PD2 ------> SDIO_CMD */ - HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 |GPIO_PIN_12); HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); @@ -178,12 +178,12 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**SPI1 GPIO Configuration + /**SPI1 GPIO Configuration PA5 ------> SPI1_SCK PA6 ------> SPI1_MISO - PA7 ------> SPI1_MOSI + PA7 ------> SPI1_MOSI */ GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -206,12 +206,12 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI2_CLK_ENABLE(); - + __HAL_RCC_GPIOB_CLK_ENABLE(); - /**SPI2 GPIO Configuration + /**SPI2 GPIO Configuration PB13 ------> SPI2_SCK PB14 ------> SPI2_MISO - PB15 ------> SPI2_MOSI + PB15 ------> SPI2_MOSI */ GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -234,12 +234,12 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI3_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI3_CLK_ENABLE(); - + __HAL_RCC_GPIOB_CLK_ENABLE(); - /**SPI3 GPIO Configuration + /**SPI3 GPIO Configuration PB3 ------> SPI3_SCK PB4 ------> SPI3_MISO - PB5 ------> SPI3_MOSI + PB5 ------> SPI3_MOSI */ GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_5; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -273,11 +273,11 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI1_CLK_DISABLE(); - - /**SPI1 GPIO Configuration + + /**SPI1 GPIO Configuration PA5 ------> SPI1_SCK PA6 ------> SPI1_MISO - PA7 ------> SPI1_MOSI + PA7 ------> SPI1_MOSI */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7); @@ -292,11 +292,11 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI2_CLK_DISABLE(); - - /**SPI2 GPIO Configuration + + /**SPI2 GPIO Configuration PB13 ------> SPI2_SCK PB14 ------> SPI2_MISO - PB15 ------> SPI2_MOSI + PB15 ------> SPI2_MOSI */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15); @@ -311,11 +311,11 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI3_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI3_CLK_DISABLE(); - - /**SPI3 GPIO Configuration + + /**SPI3 GPIO Configuration PB3 ------> SPI3_SCK PB4 ------> SPI3_MISO - PB5 ------> SPI3_MOSI + PB5 ------> SPI3_MOSI */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5); @@ -342,11 +342,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -355,7 +355,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) GPIO_InitStruct.Pin = GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); /* USER CODE BEGIN USART1_MspInit 1 */ @@ -380,10 +380,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration + + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); diff --git a/bsp/stm32/stm32f103-dofly-lyc8/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f103-dofly-lyc8/board/CubeMX_Config/CubeMX_Config.ioc index e2768b2045..fcd3cd934e 100644 --- a/bsp/stm32/stm32f103-dofly-lyc8/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32f103-dofly-lyc8/board/CubeMX_Config/CubeMX_Config.ioc @@ -34,14 +34,18 @@ NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false +PA9.GPIOParameters=GPIO_PuPd +PA9.GPIO_PuPd=GPIO_PULLUP +PA9.Mode=Asynchronous +PA9.Signal=USART1_TX +PA10.GPIOParameters=GPIO_PuPd +PA10.GPIO_PuPd=GPIO_PULLUP PA10.Mode=Asynchronous PA10.Signal=USART1_RX PA13.Mode=Serial_Wire PA13.Signal=SYS_JTMS-SWDIO PA14.Mode=Serial_Wire PA14.Signal=SYS_JTCK-SWCLK -PA9.Mode=Asynchronous -PA9.Signal=USART1_TX PC14-OSC32_IN.Mode=LSE-External-Oscillator PC14-OSC32_IN.Signal=RCC_OSC32_IN PC15-OSC32_OUT.Mode=LSE-External-Oscillator diff --git a/bsp/stm32/stm32f103-dofly-lyc8/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c b/bsp/stm32/stm32f103-dofly-lyc8/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c index b22009fcdb..87bfedec78 100644 --- a/bsp/stm32/stm32f103-dofly-lyc8/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c +++ b/bsp/stm32/stm32f103-dofly-lyc8/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c @@ -2,12 +2,12 @@ /** ****************************************************************************** * File Name : stm32f1xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** ** This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether + * USER CODE END. Other portions of this file, whether * inserted by the user or by software development tools * are owned by their respective copyright owners. * @@ -52,7 +52,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -92,7 +92,7 @@ void HAL_MspInit(void) /* System interrupt init*/ - /**NOJTAG: JTAG-DP Disabled and SW-DP Enabled + /**NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); @@ -118,11 +118,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -131,7 +131,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) GPIO_InitStruct.Pin = GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); /* USER CODE BEGIN USART1_MspInit 1 */ @@ -158,10 +158,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration + + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c b/bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c index c27983df23..1f33ad7e90 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c +++ b/bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c @@ -2,12 +2,12 @@ /** ****************************************************************************** * File Name : stm32f1xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** ** This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether + * USER CODE END. Other portions of this file, whether * inserted by the user or by software development tools * are owned by their respective copyright owners. * @@ -52,7 +52,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -78,7 +78,7 @@ /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ - + void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); /** * Initializes the Global MSP. @@ -94,7 +94,7 @@ void HAL_MspInit(void) /* System interrupt init*/ - /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled + /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); @@ -119,10 +119,10 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) /* USER CODE END ADC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_ADC1_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); - /**ADC1 GPIO Configuration - PC1 ------> ADC1_IN11 + /**ADC1 GPIO Configuration + PC1 ------> ADC1_IN11 */ GPIO_InitStruct.Pin = GPIO_PIN_1; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; @@ -150,9 +150,9 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) /* USER CODE END ADC1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_ADC1_CLK_DISABLE(); - - /**ADC1 GPIO Configuration - PC1 ------> ADC1_IN11 + + /**ADC1 GPIO Configuration + PC1 ------> ADC1_IN11 */ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1); @@ -179,11 +179,11 @@ void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan) /* USER CODE END CAN1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_CAN1_CLK_ENABLE(); - + __HAL_RCC_GPIOB_CLK_ENABLE(); - /**CAN GPIO Configuration + /**CAN GPIO Configuration PB8 ------> CAN_RX - PB9 ------> CAN_TX + PB9 ------> CAN_TX */ GPIO_InitStruct.Pin = GPIO_PIN_8; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; @@ -219,10 +219,10 @@ void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) /* USER CODE END CAN1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_CAN1_CLK_DISABLE(); - - /**CAN GPIO Configuration + + /**CAN GPIO Configuration PB8 ------> CAN_RX - PB9 ------> CAN_TX + PB9 ------> CAN_TX */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_8|GPIO_PIN_9); @@ -296,18 +296,18 @@ void HAL_SD_MspInit(SD_HandleTypeDef* hsd) /* USER CODE END SDIO_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SDIO_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); - /**SDIO GPIO Configuration + /**SDIO GPIO Configuration PC8 ------> SDIO_D0 PC9 ------> SDIO_D1 PC10 ------> SDIO_D2 PC11 ------> SDIO_D3 PC12 ------> SDIO_CK - PD2 ------> SDIO_CMD + PD2 ------> SDIO_CMD */ - GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 |GPIO_PIN_12; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; @@ -340,16 +340,16 @@ void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) /* USER CODE END SDIO_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SDIO_CLK_DISABLE(); - - /**SDIO GPIO Configuration + + /**SDIO GPIO Configuration PC8 ------> SDIO_D0 PC9 ------> SDIO_D1 PC10 ------> SDIO_D2 PC11 ------> SDIO_D3 PC12 ------> SDIO_CK - PD2 ------> SDIO_CMD + PD2 ------> SDIO_CMD */ - HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 |GPIO_PIN_12); HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); @@ -377,12 +377,12 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**SPI1 GPIO Configuration + /**SPI1 GPIO Configuration PA5 ------> SPI1_SCK PA6 ------> SPI1_MISO - PA7 ------> SPI1_MOSI + PA7 ------> SPI1_MOSI */ GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -405,12 +405,12 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI2_CLK_ENABLE(); - + __HAL_RCC_GPIOB_CLK_ENABLE(); - /**SPI2 GPIO Configuration + /**SPI2 GPIO Configuration PB13 ------> SPI2_SCK PB14 ------> SPI2_MISO - PB15 ------> SPI2_MOSI + PB15 ------> SPI2_MOSI */ GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -444,11 +444,11 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI1_CLK_DISABLE(); - - /**SPI1 GPIO Configuration + + /**SPI1 GPIO Configuration PA5 ------> SPI1_SCK PA6 ------> SPI1_MISO - PA7 ------> SPI1_MOSI + PA7 ------> SPI1_MOSI */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7); @@ -463,11 +463,11 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI2_CLK_DISABLE(); - - /**SPI2 GPIO Configuration + + /**SPI2 GPIO Configuration PB13 ------> SPI2_SCK PB14 ------> SPI2_MISO - PB15 ------> SPI2_MOSI + PB15 ------> SPI2_MOSI */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15); @@ -541,12 +541,12 @@ void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) /* USER CODE BEGIN TIM3_MspPostInit 0 */ /* USER CODE END TIM3_MspPostInit 0 */ - + __HAL_RCC_GPIOB_CLK_ENABLE(); - /**TIM3 GPIO Configuration + /**TIM3 GPIO Configuration PB0 ------> TIM3_CH3 PB1 ------> TIM3_CH4 - PB5 ------> TIM3_CH2 + PB5 ------> TIM3_CH2 */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_5; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -632,11 +632,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -645,7 +645,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) GPIO_InitStruct.Pin = GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); /* USART1 interrupt Init */ @@ -662,11 +662,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART2 GPIO Configuration + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ GPIO_InitStruct.Pin = GPIO_PIN_2; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -675,7 +675,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) GPIO_InitStruct.Pin = GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); /* USER CODE BEGIN USART2_MspInit 1 */ @@ -689,11 +689,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART3_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART3_CLK_ENABLE(); - + __HAL_RCC_GPIOB_CLK_ENABLE(); - /**USART3 GPIO Configuration + /**USART3 GPIO Configuration PB10 ------> USART3_TX - PB11 ------> USART3_RX + PB11 ------> USART3_RX */ GPIO_InitStruct.Pin = GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -702,7 +702,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) GPIO_InitStruct.Pin = GPIO_PIN_11; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); /* USER CODE BEGIN USART3_MspInit 1 */ @@ -727,10 +727,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration + + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); @@ -747,10 +747,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART2_CLK_DISABLE(); - - /**USART2 GPIO Configuration + + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3); @@ -765,10 +765,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART3_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART3_CLK_DISABLE(); - - /**USART3 GPIO Configuration + + /**USART3 GPIO Configuration PB10 ------> USART3_TX - PB11 ------> USART3_RX + PB11 ------> USART3_RX */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_10|GPIO_PIN_11); diff --git a/bsp/stm32/stm32f103-gizwits-gokitv21/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f103-gizwits-gokitv21/board/CubeMX_Config/CubeMX_Config.ioc index 360fb08070..54b134346f 100644 --- a/bsp/stm32/stm32f103-gizwits-gokitv21/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32f103-gizwits-gokitv21/board/CubeMX_Config/CubeMX_Config.ioc @@ -34,6 +34,10 @@ NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +PA9.GPIOParameters=GPIO_PuPd +PA9.GPIO_PuPd=GPIO_PULLUP +PA9.Mode=Asynchronous +PA9.Signal=USART1_TX PA10.GPIOParameters=GPIO_PuPd PA10.GPIO_PuPd=GPIO_PULLUP PA10.Mode=Asynchronous @@ -42,8 +46,6 @@ PA13.Mode=Serial_Wire PA13.Signal=SYS_JTMS-SWDIO PA14.Mode=Serial_Wire PA14.Signal=SYS_JTCK-SWCLK -PA9.Mode=Asynchronous -PA9.Signal=USART1_TX PC14-OSC32_IN.Mode=LSE-External-Oscillator PC14-OSC32_IN.Signal=RCC_OSC32_IN PC15-OSC32_OUT.Mode=LSE-External-Oscillator diff --git a/bsp/stm32/stm32f103-gizwits-gokitv21/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c b/bsp/stm32/stm32f103-gizwits-gokitv21/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c index 12171ceb42..3ee3a6eac5 100644 --- a/bsp/stm32/stm32f103-gizwits-gokitv21/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c +++ b/bsp/stm32/stm32f103-gizwits-gokitv21/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c @@ -2,7 +2,7 @@ /** ****************************************************************************** * File Name : stm32f1xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** * @attention @@ -32,7 +32,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -72,7 +72,7 @@ void HAL_MspInit(void) /* System interrupt init*/ - /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled + /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); @@ -97,11 +97,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -117,7 +117,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 1 */ } - + if(huart->Instance==USART2) { /* USER CODE BEGIN USART2_MspInit 0 */ @@ -125,11 +125,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART2 GPIO Configuration + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ GPIO_InitStruct.Pin = GPIO_PIN_2; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -163,10 +163,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration + + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); @@ -181,10 +181,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART2_CLK_DISABLE(); - - /**USART2 GPIO Configuration + + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3); diff --git a/bsp/stm32/stm32f103-hw100k-ibox/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f103-hw100k-ibox/board/CubeMX_Config/CubeMX_Config.ioc index 64b78b0f82..7f72f094c7 100644 --- a/bsp/stm32/stm32f103-hw100k-ibox/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32f103-hw100k-ibox/board/CubeMX_Config/CubeMX_Config.ioc @@ -68,14 +68,24 @@ OSC_IN.Mode=HSE-External-Oscillator OSC_IN.Signal=RCC_OSC_IN OSC_OUT.Mode=HSE-External-Oscillator OSC_OUT.Signal=RCC_OSC_OUT +PA9.GPIOParameters=GPIO_PuPd +PA9.GPIO_PuPd=GPIO_PULLUP +PA9.Mode=Asynchronous +PA9.Signal=USART1_TX +PA10.GPIOParameters=GPIO_PuPd +PA10.GPIO_PuPd=GPIO_PULLUP PA10.Mode=Asynchronous PA10.Signal=USART1_RX PA13.Mode=Serial_Wire PA13.Signal=SYS_JTMS-SWDIO PA14.Mode=Serial_Wire PA14.Signal=SYS_JTCK-SWCLK +PA2.GPIOParameters=GPIO_PuPd +PA2.GPIO_PuPd=GPIO_PULLUP PA2.Mode=Asynchronous PA2.Signal=USART2_TX +PA3.GPIOParameters=GPIO_PuPd +PA3.GPIO_PuPd=GPIO_PULLUP PA3.Mode=Asynchronous PA3.Signal=USART2_RX PA5.Mode=Full_Duplex_Master @@ -84,10 +94,12 @@ PA6.Mode=Full_Duplex_Master PA6.Signal=SPI1_MISO PA7.Mode=Full_Duplex_Master PA7.Signal=SPI1_MOSI -PA9.Mode=Asynchronous -PA9.Signal=USART1_TX +PB10.GPIOParameters=GPIO_PuPd +PB10.GPIO_PuPd=GPIO_PULLUP PB10.Mode=Asynchronous PB10.Signal=USART3_TX +PB11.GPIOParameters=GPIO_PuPd +PB11.GPIO_PuPd=GPIO_PULLUP PB11.Mode=Asynchronous PB11.Signal=USART3_RX PB13.Mode=Full_Duplex_Master diff --git a/bsp/stm32/stm32f103-hw100k-ibox/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c b/bsp/stm32/stm32f103-hw100k-ibox/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c index a70b36e9dc..18d600fd55 100644 --- a/bsp/stm32/stm32f103-hw100k-ibox/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c +++ b/bsp/stm32/stm32f103-hw100k-ibox/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c @@ -2,12 +2,12 @@ /** ****************************************************************************** * File Name : stm32f1xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** ** This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether + * USER CODE END. Other portions of this file, whether * inserted by the user or by software development tools * are owned by their respective copyright owners. * @@ -52,7 +52,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -92,7 +92,7 @@ void HAL_MspInit(void) /* System interrupt init*/ - /**NOJTAG: JTAG-DP Disabled and SW-DP Enabled + /**NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); @@ -118,11 +118,11 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) /* USER CODE END ADC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_ADC1_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); - /**ADC1 GPIO Configuration + /**ADC1 GPIO Configuration PC0 ------> ADC1_IN10 - PC1 ------> ADC1_IN11 + PC1 ------> ADC1_IN11 */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; @@ -152,10 +152,10 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) /* USER CODE END ADC1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_ADC1_CLK_DISABLE(); - - /**ADC1 GPIO Configuration + + /**ADC1 GPIO Configuration PC0 ------> ADC1_IN10 - PC1 ------> ADC1_IN11 + PC1 ------> ADC1_IN11 */ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_0|GPIO_PIN_1); @@ -233,12 +233,12 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**SPI1 GPIO Configuration + /**SPI1 GPIO Configuration PA5 ------> SPI1_SCK PA6 ------> SPI1_MISO - PA7 ------> SPI1_MOSI + PA7 ------> SPI1_MOSI */ GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -261,12 +261,12 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI2_CLK_ENABLE(); - + __HAL_RCC_GPIOB_CLK_ENABLE(); - /**SPI2 GPIO Configuration + /**SPI2 GPIO Configuration PB13 ------> SPI2_SCK PB14 ------> SPI2_MISO - PB15 ------> SPI2_MOSI + PB15 ------> SPI2_MOSI */ GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -302,11 +302,11 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI1_CLK_DISABLE(); - - /**SPI1 GPIO Configuration + + /**SPI1 GPIO Configuration PA5 ------> SPI1_SCK PA6 ------> SPI1_MISO - PA7 ------> SPI1_MOSI + PA7 ------> SPI1_MOSI */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7); @@ -321,11 +321,11 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI2_CLK_DISABLE(); - - /**SPI2 GPIO Configuration + + /**SPI2 GPIO Configuration PB13 ------> SPI2_SCK PB14 ------> SPI2_MISO - PB15 ------> SPI2_MOSI + PB15 ------> SPI2_MOSI */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15); @@ -353,11 +353,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END UART4_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_UART4_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); - /**UART4 GPIO Configuration + /**UART4 GPIO Configuration PC10 ------> UART4_TX - PC11 ------> UART4_RX + PC11 ------> UART4_RX */ GPIO_InitStruct.Pin = GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -366,7 +366,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) GPIO_InitStruct.Pin = GPIO_PIN_11; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); /* USER CODE BEGIN UART4_MspInit 1 */ @@ -380,11 +380,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -393,7 +393,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) GPIO_InitStruct.Pin = GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); /* USER CODE BEGIN USART1_MspInit 1 */ @@ -407,11 +407,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART2 GPIO Configuration + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ GPIO_InitStruct.Pin = GPIO_PIN_2; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -420,7 +420,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) GPIO_InitStruct.Pin = GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); /* USER CODE BEGIN USART2_MspInit 1 */ @@ -434,11 +434,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART3_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART3_CLK_ENABLE(); - + __HAL_RCC_GPIOB_CLK_ENABLE(); - /**USART3 GPIO Configuration + /**USART3 GPIO Configuration PB10 ------> USART3_TX - PB11 ------> USART3_RX + PB11 ------> USART3_RX */ GPIO_InitStruct.Pin = GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -447,7 +447,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) GPIO_InitStruct.Pin = GPIO_PIN_11; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); /* USER CODE BEGIN USART3_MspInit 1 */ @@ -474,10 +474,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END UART4_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_UART4_CLK_DISABLE(); - - /**UART4 GPIO Configuration + + /**UART4 GPIO Configuration PC10 ------> UART4_TX - PC11 ------> UART4_RX + PC11 ------> UART4_RX */ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_10|GPIO_PIN_11); @@ -492,10 +492,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration + + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); @@ -510,10 +510,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART2_CLK_DISABLE(); - - /**USART2 GPIO Configuration + + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3); @@ -528,10 +528,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART3_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART3_CLK_DISABLE(); - - /**USART3 GPIO Configuration + + /**USART3 GPIO Configuration PB10 ------> USART3_TX - PB11 ------> USART3_RX + PB11 ------> USART3_RX */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_10|GPIO_PIN_11); diff --git a/bsp/stm32/stm32f103-onenet-nbiot/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f103-onenet-nbiot/board/CubeMX_Config/CubeMX_Config.ioc index bea3e97feb..aa311f47f2 100644 --- a/bsp/stm32/stm32f103-onenet-nbiot/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32f103-onenet-nbiot/board/CubeMX_Config/CubeMX_Config.ioc @@ -43,34 +43,42 @@ NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false -PA10.Locked=true +PA9.GPIOParameters=GPIO_PuPd +PA9.GPIO_PuPd=GPIO_PULLUP +PA9.Mode=Asynchronous +PA9.Signal=USART1_TX +PA10.GPIOParameters=GPIO_PuPd +PA10.GPIO_PuPd=GPIO_PULLUP PA10.Mode=Asynchronous PA10.Signal=USART1_RX PA13.Mode=Serial_Wire PA13.Signal=SYS_JTMS-SWDIO PA14.Mode=Serial_Wire PA14.Signal=SYS_JTCK-SWCLK -PA2.Locked=true +PA2.GPIOParameters=GPIO_PuPd +PA2.GPIO_PuPd=GPIO_PULLUP PA2.Mode=Asynchronous PA2.Signal=USART2_TX -PA3.Locked=true +PA3.GPIOParameters=GPIO_PuPd +PA3.GPIO_PuPd=GPIO_PULLUP PA3.Mode=Asynchronous PA3.Signal=USART2_RX -PA9.Locked=true -PA9.Mode=Asynchronous -PA9.Signal=USART1_TX -PB10.Locked=true +PB10.GPIOParameters=GPIO_PuPd +PB10.GPIO_PuPd=GPIO_PULLUP PB10.Mode=Asynchronous PB10.Signal=USART3_TX -PB11.Locked=true +PB11.GPIOParameters=GPIO_PuPd +PB11.GPIO_PuPd=GPIO_PULLUP PB11.Mode=Asynchronous PB11.Signal=USART3_RX -PC10.Locked=true +PC10.GPIOParameters=GPIO_PuPd +PC10.GPIO_PuPd=GPIO_PULLUP PC10.Mode=Asynchronous -PC10.Signal=UART4_TX -PC11.Locked=true +PC10.Signal=USART4_TX +PC11.GPIOParameters=GPIO_PuPd +PC11.GPIO_PuPd=GPIO_PULLUP PC11.Mode=Asynchronous -PC11.Signal=UART4_RX +PC11.Signal=USART4_RX PD0-OSC_IN.Locked=true PD0-OSC_IN.Mode=HSE-External-Oscillator PD0-OSC_IN.Signal=RCC_OSC_IN diff --git a/bsp/stm32/stm32f103-onenet-nbiot/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c b/bsp/stm32/stm32f103-onenet-nbiot/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c index d2471dd6da..e35fce1d80 100644 --- a/bsp/stm32/stm32f103-onenet-nbiot/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c +++ b/bsp/stm32/stm32f103-onenet-nbiot/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c @@ -2,7 +2,7 @@ /** ****************************************************************************** * File Name : stm32f1xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** * @attention @@ -32,7 +32,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -72,7 +72,7 @@ void HAL_MspInit(void) /* System interrupt init*/ - /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled + /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); @@ -97,11 +97,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END UART4_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_UART4_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); - /**UART4 GPIO Configuration + /**UART4 GPIO Configuration PC10 ------> UART4_TX - PC11 ------> UART4_RX + PC11 ------> UART4_RX */ GPIO_InitStruct.Pin = GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -110,7 +110,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) GPIO_InitStruct.Pin = GPIO_PIN_11; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); /* USER CODE BEGIN UART4_MspInit 1 */ @@ -124,11 +124,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -137,7 +137,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) GPIO_InitStruct.Pin = GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); /* USER CODE BEGIN USART1_MspInit 1 */ @@ -151,11 +151,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART2 GPIO Configuration + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ GPIO_InitStruct.Pin = GPIO_PIN_2; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -164,7 +164,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) GPIO_InitStruct.Pin = GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); /* USER CODE BEGIN USART2_MspInit 1 */ @@ -178,11 +178,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART3_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART3_CLK_ENABLE(); - + __HAL_RCC_GPIOB_CLK_ENABLE(); - /**USART3 GPIO Configuration + /**USART3 GPIO Configuration PB10 ------> USART3_TX - PB11 ------> USART3_RX + PB11 ------> USART3_RX */ GPIO_InitStruct.Pin = GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -191,7 +191,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) GPIO_InitStruct.Pin = GPIO_PIN_11; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); /* USER CODE BEGIN USART3_MspInit 1 */ @@ -216,10 +216,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END UART4_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_UART4_CLK_DISABLE(); - - /**UART4 GPIO Configuration + + /**UART4 GPIO Configuration PC10 ------> UART4_TX - PC11 ------> UART4_RX + PC11 ------> UART4_RX */ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_10|GPIO_PIN_11); @@ -234,10 +234,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration + + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); @@ -252,10 +252,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART2_CLK_DISABLE(); - - /**USART2 GPIO Configuration + + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3); @@ -270,10 +270,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART3_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART3_CLK_DISABLE(); - - /**USART3 GPIO Configuration + + /**USART3 GPIO Configuration PB10 ------> USART3_TX - PB11 ------> USART3_RX + PB11 ------> USART3_RX */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_10|GPIO_PIN_11); diff --git a/bsp/stm32/stm32f103-yf-ufun/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f103-yf-ufun/board/CubeMX_Config/CubeMX_Config.ioc index 8f0ebe34a9..7a1bec1345 100644 --- a/bsp/stm32/stm32f103-yf-ufun/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32f103-yf-ufun/board/CubeMX_Config/CubeMX_Config.ioc @@ -47,6 +47,12 @@ NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false PA0-WKUP.Signal=S_TIM2_CH1_ETR PA1.Signal=S_TIM2_CH2 +PA9.GPIOParameters=GPIO_PuPd +PA9.GPIO_PuPd=GPIO_PULLUP +PA9.Mode=Asynchronous +PA9.Signal=USART1_TX +PA10.GPIOParameters=GPIO_PuPd +PA10.GPIO_PuPd=GPIO_PULLUP PA10.Mode=Asynchronous PA10.Signal=USART1_RX PA13.Mode=Serial_Wire @@ -54,8 +60,6 @@ PA13.Signal=SYS_JTMS-SWDIO PA14.Mode=Serial_Wire PA14.Signal=SYS_JTCK-SWCLK PA2.Signal=S_TIM2_CH3 -PA9.Mode=Asynchronous -PA9.Signal=USART1_TX PC10.Mode=SD_4_bits_Wide_bus PC10.Signal=SDIO_D2 PC11.Mode=SD_4_bits_Wide_bus diff --git a/bsp/stm32/stm32f103-yf-ufun/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c b/bsp/stm32/stm32f103-yf-ufun/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c index 67d2da43eb..6d50c1c47d 100644 --- a/bsp/stm32/stm32f103-yf-ufun/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c +++ b/bsp/stm32/stm32f103-yf-ufun/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c @@ -2,12 +2,12 @@ /** ****************************************************************************** * File Name : stm32f1xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** ** This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether + * USER CODE END. Other portions of this file, whether * inserted by the user or by software development tools * are owned by their respective copyright owners. * @@ -52,7 +52,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -78,7 +78,7 @@ /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ - + void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); /** * Initializes the Global MSP. @@ -94,7 +94,7 @@ void HAL_MspInit(void) /* System interrupt init*/ - /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled + /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); @@ -119,18 +119,18 @@ void HAL_SD_MspInit(SD_HandleTypeDef* hsd) /* USER CODE END SDIO_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SDIO_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); - /**SDIO GPIO Configuration + /**SDIO GPIO Configuration PC8 ------> SDIO_D0 PC9 ------> SDIO_D1 PC10 ------> SDIO_D2 PC11 ------> SDIO_D3 PC12 ------> SDIO_CK - PD2 ------> SDIO_CMD + PD2 ------> SDIO_CMD */ - GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 |GPIO_PIN_12; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; @@ -163,16 +163,16 @@ void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) /* USER CODE END SDIO_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SDIO_CLK_DISABLE(); - - /**SDIO GPIO Configuration + + /**SDIO GPIO Configuration PC8 ------> SDIO_D0 PC9 ------> SDIO_D1 PC10 ------> SDIO_D2 PC11 ------> SDIO_D3 PC12 ------> SDIO_CK - PD2 ------> SDIO_CMD + PD2 ------> SDIO_CMD */ - HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 |GPIO_PIN_12); HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); @@ -214,12 +214,12 @@ void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) /* USER CODE BEGIN TIM2_MspPostInit 0 */ /* USER CODE END TIM2_MspPostInit 0 */ - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**TIM2 GPIO Configuration + /**TIM2 GPIO Configuration PA0-WKUP ------> TIM2_CH1 PA1 ------> TIM2_CH2 - PA2 ------> TIM2_CH3 + PA2 ------> TIM2_CH3 */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -269,11 +269,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -282,7 +282,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) GPIO_InitStruct.Pin = GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); /* USER CODE BEGIN USART1_MspInit 1 */ @@ -305,10 +305,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration + + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); diff --git a/bsp/stm32/stm32f107-uc-eval/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c b/bsp/stm32/stm32f107-uc-eval/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c index 03106e9008..6df0958bbd 100644 --- a/bsp/stm32/stm32f107-uc-eval/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c +++ b/bsp/stm32/stm32f107-uc-eval/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c @@ -2,12 +2,12 @@ /** ****************************************************************************** * File Name : stm32f1xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** ** This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether + * USER CODE END. Other portions of this file, whether * inserted by the user or by software development tools * are owned by their respective copyright owners. * @@ -52,7 +52,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -92,7 +92,7 @@ void HAL_MspInit(void) /* System interrupt init*/ - /**NOJTAG: JTAG-DP Disabled and SW-DP Enabled + /**NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); @@ -118,11 +118,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); - + __HAL_RCC_GPIOD_CLK_ENABLE(); - /**USART2 GPIO Configuration + /**USART2 GPIO Configuration PD5 ------> USART2_TX - PD6 ------> USART2_RX + PD6 ------> USART2_RX */ GPIO_InitStruct.Pin = GPIO_PIN_5; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -131,7 +131,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) GPIO_InitStruct.Pin = GPIO_PIN_6; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); __HAL_AFIO_REMAP_USART2_ENABLE(); @@ -163,10 +163,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART2_CLK_DISABLE(); - - /**USART2 GPIO Configuration + + /**USART2 GPIO Configuration PD5 ------> USART2_TX - PD6 ------> USART2_RX + PD6 ------> USART2_RX */ HAL_GPIO_DeInit(GPIOD, GPIO_PIN_5|GPIO_PIN_6); diff --git a/bsp/stm32/stm32f207-st-nucleo/board/CubeMX_Config/Core/Src/stm32f2xx_hal_msp.c b/bsp/stm32/stm32f207-st-nucleo/board/CubeMX_Config/Core/Src/stm32f2xx_hal_msp.c index 24b027c37b..a4a60ffeb9 100644 --- a/bsp/stm32/stm32f207-st-nucleo/board/CubeMX_Config/Core/Src/stm32f2xx_hal_msp.c +++ b/bsp/stm32/stm32f207-st-nucleo/board/CubeMX_Config/Core/Src/stm32f2xx_hal_msp.c @@ -101,7 +101,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) */ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF7_USART3; HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); diff --git a/bsp/stm32/stm32f401-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f401-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc index e04e99534f..171ed0f617 100644 --- a/bsp/stm32/stm32f401-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32f401-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc @@ -42,11 +42,13 @@ PA13.Mode=Serial_Wire PA13.Signal=SYS_JTMS-SWDIO PA14.Mode=Serial_Wire PA14.Signal=SYS_JTCK-SWCLK -PA2.GPIOParameters=GPIO_Speed +PA2.GPIOParameters=GPIO_Speed,GPIO_PuPd +PA2.GPIO_PuPd=GPIO_PULLUP PA2.GPIO_Speed=GPIO_SPEED_FREQ_LOW PA2.Mode=Asynchronous PA2.Signal=USART2_TX -PA3.GPIOParameters=GPIO_Speed +PA3.GPIOParameters=GPIO_Speed,GPIO_PuPd +PA3.GPIO_PuPd=GPIO_PULLUP PA3.GPIO_Speed=GPIO_SPEED_FREQ_LOW PA3.Mode=Asynchronous PA3.Signal=USART2_RX @@ -61,14 +63,6 @@ PC14-OSC32_IN.Mode=LSE-External-Oscillator PC14-OSC32_IN.Signal=RCC_OSC32_IN PC15-OSC32_OUT.Mode=LSE-External-Oscillator PC15-OSC32_OUT.Signal=RCC_OSC32_OUT -PCC.Checker=false -PCC.Line=STM32F401 -PCC.MCU=STM32F401R(D-E)Tx -PCC.PartNumber=STM32F401RETx -PCC.Seq0=0 -PCC.Series=STM32F4 -PCC.Temperature=25 -PCC.Vdd=null PH0\ -\ OSC_IN.Mode=HSE-External-Clock-Source PH0\ -\ OSC_IN.Signal=RCC_OSC_IN PH1\ -\ OSC_OUT.Mode=HSE-External-Clock-Source diff --git a/bsp/stm32/stm32f401-st-nucleo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c b/bsp/stm32/stm32f401-st-nucleo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c index 62e369862b..b263fd4998 100644 --- a/bsp/stm32/stm32f401-st-nucleo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c +++ b/bsp/stm32/stm32f401-st-nucleo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c @@ -2,12 +2,12 @@ /** ****************************************************************************** * File Name : stm32f4xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** ** This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether + * USER CODE END. Other portions of this file, whether * inserted by the user or by software development tools * are owned by their respective copyright owners. * @@ -52,7 +52,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -113,12 +113,12 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**SPI1 GPIO Configuration + /**SPI1 GPIO Configuration PA5 ------> SPI1_SCK PA6 ------> SPI1_MISO - PA7 ------> SPI1_MOSI + PA7 ------> SPI1_MOSI */ GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -149,11 +149,11 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI1_CLK_DISABLE(); - - /**SPI1 GPIO Configuration + + /**SPI1 GPIO Configuration PA5 ------> SPI1_SCK PA6 ------> SPI1_MISO - PA7 ------> SPI1_MOSI + PA7 ------> SPI1_MOSI */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7); @@ -180,11 +180,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART2 GPIO Configuration + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -215,10 +215,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART2_CLK_DISABLE(); - - /**USART2 GPIO Configuration + + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3); diff --git a/bsp/stm32/stm32f405-smdz-breadfruit/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f405-smdz-breadfruit/board/CubeMX_Config/CubeMX_Config.ioc index b4aeaf68c1..8ae3a1bccd 100644 --- a/bsp/stm32/stm32f405-smdz-breadfruit/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32f405-smdz-breadfruit/board/CubeMX_Config/CubeMX_Config.ioc @@ -32,8 +32,12 @@ NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false +PA2.GPIOParameters=GPIO_PuPd +PA2.GPIO_PuPd=GPIO_PULLUP PA2.Mode=Asynchronous PA2.Signal=USART2_TX +PA3.GPIOParameters=GPIO_PuPd +PA3.GPIO_PuPd=GPIO_PULLUP PA3.Mode=Asynchronous PA3.Signal=USART2_RX PC14-OSC32_IN.Mode=LSE-External-Oscillator diff --git a/bsp/stm32/stm32f405-smdz-breadfruit/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c b/bsp/stm32/stm32f405-smdz-breadfruit/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c index 0b13484aba..ecc0b6d703 100644 --- a/bsp/stm32/stm32f405-smdz-breadfruit/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c +++ b/bsp/stm32/stm32f405-smdz-breadfruit/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c @@ -2,12 +2,12 @@ /** ****************************************************************************** * File Name : stm32f4xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** ** This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether + * USER CODE END. Other portions of this file, whether * inserted by the user or by software development tools * are owned by their respective copyright owners. * @@ -52,7 +52,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -114,11 +114,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART2 GPIO Configuration + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -151,10 +151,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART2_CLK_DISABLE(); - - /**USART2 GPIO Configuration + + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3); diff --git a/bsp/stm32/stm32f407-armfly-v5/.config b/bsp/stm32/stm32f407-armfly-v5/.config new file mode 100644 index 0000000000..13a4d62a3a --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/.config @@ -0,0 +1,351 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x40000 +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M4=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +CONFIG_FINSH_USING_MSH_ONLY=y +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +# CONFIG_RT_USING_DFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_MTD is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set + +# +# Using WiFi +# +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +# CONFIG_RT_USING_LIBC is not set +# CONFIG_RT_USING_PTHREADS is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# Modbus master and slave stack +# +# CONFIG_RT_USING_MODBUS is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_LOGTRACE is not set +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set + +# +# ARM CMSIS +# +# CONFIG_RT_USING_CMSIS_OS is not set +# CONFIG_RT_USING_RTT_CMSIS is not set +# CONFIG_RT_USING_LWP is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOTKIT is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +CONFIG_SOC_FAMILY_STM32=y +CONFIG_SOC_SERIES_STM32F4=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_STM32F407ZG=y + +# +# Onboard Peripheral Drivers +# + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART1=y +# CONFIG_BSP_UART1_RX_USING_DMA is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_I2C1 is not set + +# +# Board extended module Drivers +# diff --git a/bsp/stm32/stm32f407-armfly-v5/.gitignore b/bsp/stm32/stm32f407-armfly-v5/.gitignore new file mode 100644 index 0000000000..7221bde019 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/.gitignore @@ -0,0 +1,42 @@ +*.pyc +*.map +*.dblite +*.elf +*.bin +*.hex +*.axf +*.exe +*.pdb +*.idb +*.ilk +*.old +build +Debug +documentation/html +packages/ +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +.DS_Stor* +.config 3 +.config 4 +.config 5 +Midea-X1 +*.uimg +GPATH +GRTAGS +GTAGS +.vscode +JLinkLog.txt +JLinkSettings.ini +DebugConfig/ +RTE/ +settings/ +*.uvguix* +cconfig.h diff --git a/bsp/stm32/stm32f407-armfly-v5/Kconfig b/bsp/stm32/stm32f407-armfly-v5/Kconfig new file mode 100644 index 0000000000..8cbc7b71a8 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/Kconfig @@ -0,0 +1,21 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "../libraries/Kconfig" +source "board/Kconfig" diff --git a/bsp/stm32/stm32f407-armfly-v5/README.md b/bsp/stm32/stm32f407-armfly-v5/README.md new file mode 100644 index 0000000000..4f2f74f36b --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/README.md @@ -0,0 +1,125 @@ +# STM32F429 armfly-v5 开发板 BSP 说明 + +## 简介 + +本文档为 STM32F429 armfly-v5 开发板的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +armfly-v5 STM32F407 是安富莱推出的一款基于 ARM Cortex-M4 内核的开发板，最高主频为 168Mhz，该开发板具有丰富的板载资源，可以充分发挥 STM32F407 的芯片性能。 + +开发板外观如下图所示： + +![board](figures/board.png) + +该开发板常用 **板载资源** 如下： + +- MCU：STM32F407IGT6，主频 168MHz，1024KB FLASH ，196KB RAM +- 外部 RAM：IS61WV102416BLL-10TL（SRAM，20MB，16bit） +- 外部 FLASH：W25Q64BVSSIG（SPI，8MB）、HY27UF081G2A（NAND，128MB） +- 常用外设 + - LED：4个， LED1 - LED4 + - 按键：4个，k1（PI8），K2（PC13），k3（PI11），五向摇杆 +- 常用接口：USB 转串口、SD 卡接口、以太网接口、LCD 接口 +- 调试接口，SWD + +开发板更多详细信息请参考【安富莱】 [STM32 v5开发板介绍](http://www.armbbs.cn/forum.php?mod=viewthread&tid=1285)。 + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :----------------- | :----------: | :------------------------------------- | +| USB 转串口 | 支持 | UART1/2 | +| SPI Flash | 支持 | W25Q64BVSSIG 8M FLASH SPI3 | +| MPU6050 | 支持 | 软件 I2C2 | +| SD卡 | 支持 | | +| CAN | 暂不支持 | | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | PA0, PA1... PK15 ---> PIN: 0, 1...176 | +| UART | 支持 | UART1 | +| SPI | 支持 | SPI3 | +| I2C | 支持 | 软件 I2C2 | +| ADC | 支持 | | +| RTC | 支持 | 支持外部晶振和内部低速时钟 | +| WDT | 支持 | | +| FLASH | 支持 | 已适配 [FAL](https://github.com/RT-Thread-packages/fal) | +| SDIO | 支持 | | +| PWM | 支持 | | +| USB Device | 暂不支持 | 即将支持 | +| USB Host | 暂不支持 | 即将支持 | +| **扩展模块** | **支持情况** | **备注** | +| ad7606 | 暂不支持 | | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为开发者提供 MDK4、MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用数据线连接开发板到 PC，打开电源开关。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 STLink 仿真器下载程序，在通过 STLink 连接开发板的基础上，点击下载按钮即可下载程序到开发板 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，【这里写开发板运行起来之后的现象，如：LED 闪烁等】。 + +连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.2 build Jul 13 2020 + 2006 - 2019 Copyright by rt-thread team +msh > +``` +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口1 的功能，如果需使用 SD 卡、Flash 等更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。 + +本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 + +## 注意事项 + +- 暂无 + +## 联系人信息 + +维护人: + +- [Dozingfiretruck](https://gitee.com/Dozingfiretruck), 邮箱： \ No newline at end of file diff --git a/bsp/stm32/stm32f407-armfly-v5/SConscript b/bsp/stm32/stm32f407-armfly-v5/SConscript new file mode 100644 index 0000000000..20f7689c53 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/stm32/stm32f407-armfly-v5/SConstruct b/bsp/stm32/stm32f407-armfly-v5/SConstruct new file mode 100644 index 0000000000..945cb55a52 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/SConstruct @@ -0,0 +1,60 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rt-thread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +stm32_library = 'STM32F4xx_HAL' +rtconfig.BSP_LIBRARY_TYPE = stm32_library + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, stm32_library, 'SConscript'))) + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/stm32/stm32f407-armfly-v5/applications/SConscript b/bsp/stm32/stm32f407-armfly-v5/applications/SConscript new file mode 100644 index 0000000000..6f66f7ab73 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/applications/SConscript @@ -0,0 +1,12 @@ +import rtconfig +from building import * + +cwd = GetCurrentDir() +CPPPATH = [cwd, str(Dir('#'))] +src = Split(""" +main.c +""") + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/stm32/stm32f407-armfly-v5/applications/main.c b/bsp/stm32/stm32f407-armfly-v5/applications/main.c new file mode 100644 index 0000000000..297573866c --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/applications/main.c @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-13 Dozingfiretruck first version + */ + +#include +#include +#include + +/* defined the LED4 pin: PC2 */ +#define LED0_PIN GET_PIN(C, 2) + +int main(void) +{ + int count = 1; + /* set LED0 pin mode to output */ + rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); + + while (count++) + { + rt_pin_write(LED0_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED0_PIN, PIN_LOW); + rt_thread_mdelay(500); + } + + return RT_EOK; +} diff --git a/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/.mxproject new file mode 100644 index 0000000000..4638fb8888 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/.mxproject @@ -0,0 +1,19 @@ +[PreviousGenFiles] +HeaderPath=C:/Users/qq147/Desktop/rt-thread/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Inc +HeaderFiles=stm32f4xx_it.h;stm32f4xx_hal_conf.h;main.h; +SourcePath=C:/Users/qq147/Desktop/rt-thread/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Src +SourceFiles=stm32f4xx_it.c;stm32f4xx_hal_msp.c;main.c; + +[PreviousLibFiles] +LibFiles=Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rng.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rng.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rng.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h; + +[PreviousUsedIarFiles] +SourceFiles=..\Src\main.c;..\Src\stm32f4xx_it.c;..\Src\stm32f4xx_hal_msp.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;..\\Src/system_stm32f4xx.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;..\\Src/system_stm32f4xx.c;..\Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;; +HeaderPath=..\Drivers\STM32F4xx_HAL_Driver\Inc;..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F4xx\Include;..\Drivers\CMSIS\Include;..\Inc; +CDefines=USE_HAL_DRIVER;STM32F407xx;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[PreviousUsedKeilFiles] +SourceFiles=..\Src\main.c;..\Src\stm32f4xx_it.c;..\Src\stm32f4xx_hal_msp.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rng.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;..\\Src/system_stm32f4xx.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rng.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;..\\Src/system_stm32f4xx.c;..\Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;; +HeaderPath=..\Drivers\STM32F4xx_HAL_Driver\Inc;..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F4xx\Include;..\Drivers\CMSIS\Include;..\Inc; +CDefines=USE_HAL_DRIVER;STM32F407xx;USE_HAL_DRIVER;USE_HAL_DRIVER; + diff --git a/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/CubeMX_Config.ioc new file mode 100644 index 0000000000..6821275340 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/CubeMX_Config.ioc @@ -0,0 +1,242 @@ +#MicroXplorer Configuration settings - do not modify +ADC1.Channel-3\#ChannelRegularConversion=ADC_CHANNEL_9 +ADC1.IPParameters=Rank-3\#ChannelRegularConversion,master,Channel-3\#ChannelRegularConversion,SamplingTime-3\#ChannelRegularConversion,NbrOfConversionFlag +ADC1.NbrOfConversionFlag=1 +ADC1.Rank-3\#ChannelRegularConversion=1 +ADC1.SamplingTime-3\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES +ADC1.master=1 +File.Version=6 +GPIO.groupedBy=Group By Peripherals +I2S2.ErrorAudioFreq=-0.27 % +I2S2.FullDuplexMode=I2S_FULLDUPLEXMODE_ENABLE +I2S2.IPParameters=Instance,VirtualMode,FullDuplexMode,RealAudioFreq,ErrorAudioFreq +I2S2.Instance=SPI$Index +I2S2.RealAudioFreq=7.978 KHz +I2S2.VirtualMode=I2S_MODE_MASTER +KeepUserPlacement=false +Mcu.Family=STM32F4 +Mcu.IP0=ADC1 +Mcu.IP1=I2S2 +Mcu.IP10=TIM10 +Mcu.IP11=TIM11 +Mcu.IP12=TIM13 +Mcu.IP13=TIM14 +Mcu.IP14=USART1 +Mcu.IP15=USART2 +Mcu.IP2=IWDG +Mcu.IP3=NVIC +Mcu.IP4=RCC +Mcu.IP5=RNG +Mcu.IP6=RTC +Mcu.IP7=SDIO +Mcu.IP8=SPI3 +Mcu.IP9=SYS +Mcu.IPNb=16 +Mcu.Name=STM32F407I(E-G)Tx +Mcu.Package=LQFP176 +Mcu.Pin0=PC14-OSC32_IN +Mcu.Pin1=PC15-OSC32_OUT +Mcu.Pin10=PB15 +Mcu.Pin11=PC6 +Mcu.Pin12=PC8 +Mcu.Pin13=PC9 +Mcu.Pin14=PA9 +Mcu.Pin15=PA10 +Mcu.Pin16=PA13 +Mcu.Pin17=PI2 +Mcu.Pin18=PA14 +Mcu.Pin19=PC10 +Mcu.Pin2=PF6 +Mcu.Pin20=PC11 +Mcu.Pin21=PC12 +Mcu.Pin22=PD2 +Mcu.Pin23=PB3 +Mcu.Pin24=PB4 +Mcu.Pin25=PB5 +Mcu.Pin26=VP_IWDG_VS_IWDG +Mcu.Pin27=VP_RNG_VS_RNG +Mcu.Pin28=VP_RTC_VS_RTC_Activate +Mcu.Pin29=VP_SYS_VS_Systick +Mcu.Pin3=PH0-OSC_IN +Mcu.Pin30=VP_TIM10_VS_ClockSourceINT +Mcu.Pin31=VP_TIM11_VS_ClockSourceINT +Mcu.Pin32=VP_TIM13_VS_ClockSourceINT +Mcu.Pin33=VP_TIM14_VS_ClockSourceINT +Mcu.Pin4=PH1-OSC_OUT +Mcu.Pin5=PA2 +Mcu.Pin6=PA3 +Mcu.Pin7=PB1 +Mcu.Pin8=PB12 +Mcu.Pin9=PB13 +Mcu.PinsNb=34 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32F407IGTx +MxCube.Version=5.6.1 +MxDb.Version=DB.5.0.60 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +PA9.GPIOParameters=GPIO_PuPd +PA9.GPIO_PuPd=GPIO_PULLUP +PA9.Mode=Asynchronous +PA9.Signal=USART1_TX +PA10.GPIOParameters=GPIO_PuPd +PA10.GPIO_PuPd=GPIO_PULLUP +PA10.Mode=Asynchronous +PA10.Signal=USART1_RX +PA13.Mode=Serial_Wire +PA13.Signal=SYS_JTMS-SWDIO +PA14.Mode=Serial_Wire +PA14.Signal=SYS_JTCK-SWCLK +PA2.GPIOParameters=GPIO_PuPd +PA2.GPIO_PuPd=GPIO_PULLUP +PA2.Mode=Asynchronous +PA2.Signal=USART2_TX +PA3.GPIOParameters=GPIO_PuPd +PA3.GPIO_PuPd=GPIO_PULLUP +PA3.Mode=Asynchronous +PA3.Signal=USART2_RX +PB1.Signal=ADCx_IN9 +PB12.Mode=Full_Duplex_Master +PB12.Signal=I2S2_WS +PB13.Locked=true +PB13.Mode=Full_Duplex_Master +PB13.Signal=I2S2_CK +PB15.Mode=Full_Duplex_Master +PB15.Signal=I2S2_SD +PB3.Mode=Full_Duplex_Master +PB3.Signal=SPI3_SCK +PB4.Mode=Full_Duplex_Master +PB4.Signal=SPI3_MISO +PB5.Mode=Full_Duplex_Master +PB5.Signal=SPI3_MOSI +PC10.Mode=SD_4_bits_Wide_bus +PC10.Signal=SDIO_D2 +PC11.Mode=SD_4_bits_Wide_bus +PC11.Signal=SDIO_D3 +PC12.Mode=SD_4_bits_Wide_bus +PC12.Signal=SDIO_CK +PC14-OSC32_IN.Mode=LSE-External-Oscillator +PC14-OSC32_IN.Signal=RCC_OSC32_IN +PC15-OSC32_OUT.Mode=LSE-External-Oscillator +PC15-OSC32_OUT.Signal=RCC_OSC32_OUT +PC6.Mode=Master_Clock_Activated +PC6.Signal=I2S2_MCK +PC8.Mode=SD_4_bits_Wide_bus +PC8.Signal=SDIO_D0 +PC9.Mode=SD_4_bits_Wide_bus +PC9.Signal=SDIO_D1 +PD2.Mode=SD_4_bits_Wide_bus +PD2.Signal=SDIO_CMD +PF6.Signal=S_TIM10_CH1 +PH0-OSC_IN.Mode=HSE-External-Oscillator +PH0-OSC_IN.Signal=RCC_OSC_IN +PH1-OSC_OUT.Mode=HSE-External-Oscillator +PH1-OSC_OUT.Signal=RCC_OSC_OUT +PI2.Locked=true +PI2.Mode=Full_Duplex_Master +PI2.Signal=I2S2_ext_SD +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=false +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32F407IGTx +ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.25.0 +ProjectManager.FreePins=false +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=0 +ProjectManager.MainLocation=Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=CubeMX_Config.ioc +ProjectManager.ProjectName=CubeMX_Config +ProjectManager.StackSize=0x400 +ProjectManager.TargetToolchain=MDK-ARM V5.27 +ProjectManager.ToolChainLocation= +ProjectManager.UnderRoot=false +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_ADC1_Init-ADC1-false-HAL-true,5-MX_I2S2_Init-I2S2-false-HAL-true,6-MX_IWDG_Init-IWDG-false-HAL-true,7-MX_RTC_Init-RTC-false-HAL-true,8-MX_SDIO_SD_Init-SDIO-false-HAL-true,9-MX_SPI3_Init-SPI3-false-HAL-true,10-MX_TIM10_Init-TIM10-false-HAL-true,11-MX_TIM11_Init-TIM11-false-HAL-true,12-MX_TIM13_Init-TIM13-false-HAL-true,13-MX_TIM14_Init-TIM14-false-HAL-true,14-MX_RNG_Init-RNG-false-HAL-true,15-MX_USART2_UART_Init-USART2-false-HAL-true +RCC.48MHZClocksFreq_Value=48000000 +RCC.AHBFreq_Value=168000000 +RCC.APB1CLKDivider=RCC_HCLK_DIV4 +RCC.APB1Freq_Value=42000000 +RCC.APB1TimFreq_Value=84000000 +RCC.APB2CLKDivider=RCC_HCLK_DIV2 +RCC.APB2Freq_Value=84000000 +RCC.APB2TimFreq_Value=168000000 +RCC.CortexFreq_Value=168000000 +RCC.EthernetFreq_Value=168000000 +RCC.FCLKCortexFreq_Value=168000000 +RCC.FamilyName=M +RCC.HCLKFreq_Value=168000000 +RCC.HSE_VALUE=25000000 +RCC.HSI_VALUE=16000000 +RCC.I2SClocksFreq_Value=96000000 +RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,PLLSourceVirtual,RCC_RTC_Clock_Source,RCC_RTC_Clock_SourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VcooutputI2S +RCC.LSI_VALUE=32000 +RCC.MCO2PinFreq_Value=168000000 +RCC.PLLCLKFreq_Value=168000000 +RCC.PLLM=25 +RCC.PLLN=336 +RCC.PLLQ=7 +RCC.PLLQCLKFreq_Value=48000000 +RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE +RCC.RCC_RTC_Clock_Source=RCC_RTCCLKSOURCE_LSE +RCC.RCC_RTC_Clock_SourceVirtual=RCC_RTCCLKSOURCE_LSE +RCC.RTCFreq_Value=32768 +RCC.RTCHSEDivFreq_Value=12500000 +RCC.SYSCLKFreq_VALUE=168000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +RCC.VCOI2SOutputFreq_Value=192000000 +RCC.VCOInputFreq_Value=1000000 +RCC.VCOOutputFreq_Value=336000000 +RCC.VcooutputI2S=96000000 +SH.ADCx_IN9.0=ADC1_IN9,IN9 +SH.ADCx_IN9.ConfNb=1 +SH.S_TIM10_CH1.0=TIM10_CH1,PWM Generation1 CH1 +SH.S_TIM10_CH1.ConfNb=1 +SPI3.CalculateBaudRate=21.0 MBits/s +SPI3.Direction=SPI_DIRECTION_2LINES +SPI3.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate +SPI3.Mode=SPI_MODE_MASTER +SPI3.VirtualType=VM_MASTER +TIM10.Channel=TIM_CHANNEL_1 +TIM10.IPParameters=Channel +USART1.IPParameters=VirtualMode +USART1.VirtualMode=VM_ASYNC +USART2.IPParameters=VirtualMode +USART2.VirtualMode=VM_ASYNC +VP_IWDG_VS_IWDG.Mode=IWDG_Activate +VP_IWDG_VS_IWDG.Signal=IWDG_VS_IWDG +VP_RNG_VS_RNG.Mode=RNG_Activate +VP_RNG_VS_RNG.Signal=RNG_VS_RNG +VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled +VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate +VP_SYS_VS_Systick.Mode=SysTick +VP_SYS_VS_Systick.Signal=SYS_VS_Systick +VP_TIM10_VS_ClockSourceINT.Mode=Enable_Timer +VP_TIM10_VS_ClockSourceINT.Signal=TIM10_VS_ClockSourceINT +VP_TIM11_VS_ClockSourceINT.Mode=Enable_Timer +VP_TIM11_VS_ClockSourceINT.Signal=TIM11_VS_ClockSourceINT +VP_TIM13_VS_ClockSourceINT.Mode=Enable_Timer +VP_TIM13_VS_ClockSourceINT.Signal=TIM13_VS_ClockSourceINT +VP_TIM14_VS_ClockSourceINT.Mode=Enable_Timer +VP_TIM14_VS_ClockSourceINT.Signal=TIM14_VS_ClockSourceINT +board=custom diff --git a/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Inc/main.h b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Inc/main.h new file mode 100644 index 0000000000..71f8e09516 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Inc/main.h @@ -0,0 +1,73 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h new file mode 100644 index 0000000000..9638f92d62 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h @@ -0,0 +1,443 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_conf_template.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32f4xx_hal_conf.h. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_CONF_H +#define __STM32F4xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED + + #define HAL_ADC_MODULE_ENABLED +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_CAN_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_DAC_MODULE_ENABLED */ +/* #define HAL_DCMI_MODULE_ENABLED */ +/* #define HAL_DMA2D_MODULE_ENABLED */ +/* #define HAL_ETH_MODULE_ENABLED */ +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_PCCARD_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +/* #define HAL_SDRAM_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ +/* #define HAL_I2C_MODULE_ENABLED */ +#define HAL_I2S_MODULE_ENABLED +#define HAL_IWDG_MODULE_ENABLED +/* #define HAL_LTDC_MODULE_ENABLED */ +#define HAL_RNG_MODULE_ENABLED +#define HAL_RTC_MODULE_ENABLED +/* #define HAL_SAI_MODULE_ENABLED */ +#define HAL_SD_MODULE_ENABLED +/* #define HAL_MMC_MODULE_ENABLED */ +#define HAL_SPI_MODULE_ENABLED +#define HAL_TIM_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +/* #define HAL_PCD_MODULE_ENABLED */ +/* #define HAL_HCD_MODULE_ENABLED */ +/* #define HAL_DSI_MODULE_ENABLED */ +/* #define HAL_QSPI_MODULE_ENABLED */ +/* #define HAL_QSPI_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_FMPI2C_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +/* #define HAL_DFSDM_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000U) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the External audio frequency in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 1U +#define INSTRUCTION_CACHE_ENABLE 1U +#define DATA_CACHE_ENABLE 1U + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2U +#define MAC_ADDR1 0U +#define MAC_ADDR2 0U +#define MAC_ADDR3 0U +#define MAC_ADDR4 0U +#define MAC_ADDR5 0U + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* DP83848_PHY_ADDRESS Address*/ +#define DP83848_PHY_ADDRESS 0x01U +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY ((uint32_t)0x000000FFU) +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) + +#define PHY_READ_TO ((uint32_t)0x0000FFFFU) +#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU) + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ +#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ + +#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f4xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32f4xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f4xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f4xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f4xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f4xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f4xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f4xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32f4xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED +#include "stm32f4xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32f4xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f4xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32f4xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32f4xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f4xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32f4xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32f4xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_PCCARD_MODULE_ENABLED + #include "stm32f4xx_hal_pccard.h" +#endif /* HAL_PCCARD_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32f4xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f4xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f4xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f4xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32f4xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f4xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32f4xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f4xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32f4xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32f4xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32f4xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f4xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f4xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f4xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f4xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f4xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f4xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f4xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f4xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32f4xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32f4xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32f4xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32f4xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_FMPI2C_MODULE_ENABLED + #include "stm32f4xx_hal_fmpi2c.h" +#endif /* HAL_FMPI2C_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32f4xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32f4xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32f4xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_CONF_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Inc/stm32f4xx_it.h b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Inc/stm32f4xx_it.h new file mode 100644 index 0000000000..ab2ae38f21 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Inc/stm32f4xx_it.h @@ -0,0 +1,69 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f4xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_IT_H +#define __STM32F4xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Src/main.c b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Src/main.c new file mode 100644 index 0000000000..b2659cd456 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Src/main.c @@ -0,0 +1,708 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +ADC_HandleTypeDef hadc1; + +I2S_HandleTypeDef hi2s2; + +IWDG_HandleTypeDef hiwdg; + +RNG_HandleTypeDef hrng; + +RTC_HandleTypeDef hrtc; + +SD_HandleTypeDef hsd; + +SPI_HandleTypeDef hspi3; + +TIM_HandleTypeDef htim10; +TIM_HandleTypeDef htim11; +TIM_HandleTypeDef htim13; +TIM_HandleTypeDef htim14; + +UART_HandleTypeDef huart1; +UART_HandleTypeDef huart2; + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +static void MX_GPIO_Init(void); +static void MX_USART1_UART_Init(void); +static void MX_ADC1_Init(void); +static void MX_I2S2_Init(void); +static void MX_IWDG_Init(void); +static void MX_RTC_Init(void); +static void MX_SDIO_SD_Init(void); +static void MX_SPI3_Init(void); +static void MX_TIM10_Init(void); +static void MX_TIM11_Init(void); +static void MX_TIM13_Init(void); +static void MX_TIM14_Init(void); +static void MX_RNG_Init(void); +static void MX_USART2_UART_Init(void); +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_USART1_UART_Init(); + MX_ADC1_Init(); + MX_I2S2_Init(); + MX_IWDG_Init(); + MX_RTC_Init(); + MX_SDIO_SD_Init(); + MX_SPI3_Init(); + MX_TIM10_Init(); + MX_TIM11_Init(); + MX_TIM13_Init(); + MX_TIM14_Init(); + MX_RNG_Init(); + MX_USART2_UART_Init(); + /* USER CODE BEGIN 2 */ + + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + } + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE + |RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 25; + RCC_OscInitStruct.PLL.PLLN = 336; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 7; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) + { + Error_Handler(); + } + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2S|RCC_PERIPHCLK_RTC; + PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; + PeriphClkInitStruct.PLLI2S.PLLI2SR = 2; + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } +} + +/** + * @brief ADC1 Initialization Function + * @param None + * @retval None + */ +static void MX_ADC1_Init(void) +{ + + /* USER CODE BEGIN ADC1_Init 0 */ + + /* USER CODE END ADC1_Init 0 */ + + ADC_ChannelConfTypeDef sConfig = {0}; + + /* USER CODE BEGIN ADC1_Init 1 */ + + /* USER CODE END ADC1_Init 1 */ + /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion) + */ + hadc1.Instance = ADC1; + hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; + hadc1.Init.Resolution = ADC_RESOLUTION_12B; + hadc1.Init.ScanConvMode = DISABLE; + hadc1.Init.ContinuousConvMode = DISABLE; + hadc1.Init.DiscontinuousConvMode = DISABLE; + hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; + hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; + hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; + hadc1.Init.NbrOfConversion = 1; + hadc1.Init.DMAContinuousRequests = DISABLE; + hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; + if (HAL_ADC_Init(&hadc1) != HAL_OK) + { + Error_Handler(); + } + /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time. + */ + sConfig.Channel = ADC_CHANNEL_9; + sConfig.Rank = 1; + sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; + if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN ADC1_Init 2 */ + + /* USER CODE END ADC1_Init 2 */ + +} + +/** + * @brief I2S2 Initialization Function + * @param None + * @retval None + */ +static void MX_I2S2_Init(void) +{ + + /* USER CODE BEGIN I2S2_Init 0 */ + + /* USER CODE END I2S2_Init 0 */ + + /* USER CODE BEGIN I2S2_Init 1 */ + + /* USER CODE END I2S2_Init 1 */ + hi2s2.Instance = SPI2; + hi2s2.Init.Mode = I2S_MODE_MASTER_TX; + hi2s2.Init.Standard = I2S_STANDARD_PHILIPS; + hi2s2.Init.DataFormat = I2S_DATAFORMAT_16B; + hi2s2.Init.MCLKOutput = I2S_MCLKOUTPUT_ENABLE; + hi2s2.Init.AudioFreq = I2S_AUDIOFREQ_8K; + hi2s2.Init.CPOL = I2S_CPOL_LOW; + hi2s2.Init.ClockSource = I2S_CLOCK_PLL; + hi2s2.Init.FullDuplexMode = I2S_FULLDUPLEXMODE_ENABLE; + if (HAL_I2S_Init(&hi2s2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN I2S2_Init 2 */ + + /* USER CODE END I2S2_Init 2 */ + +} + +/** + * @brief IWDG Initialization Function + * @param None + * @retval None + */ +static void MX_IWDG_Init(void) +{ + + /* USER CODE BEGIN IWDG_Init 0 */ + + /* USER CODE END IWDG_Init 0 */ + + /* USER CODE BEGIN IWDG_Init 1 */ + + /* USER CODE END IWDG_Init 1 */ + hiwdg.Instance = IWDG; + hiwdg.Init.Prescaler = IWDG_PRESCALER_4; + hiwdg.Init.Reload = 4095; + if (HAL_IWDG_Init(&hiwdg) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN IWDG_Init 2 */ + + /* USER CODE END IWDG_Init 2 */ + +} + +/** + * @brief RNG Initialization Function + * @param None + * @retval None + */ +static void MX_RNG_Init(void) +{ + + /* USER CODE BEGIN RNG_Init 0 */ + + /* USER CODE END RNG_Init 0 */ + + /* USER CODE BEGIN RNG_Init 1 */ + + /* USER CODE END RNG_Init 1 */ + hrng.Instance = RNG; + if (HAL_RNG_Init(&hrng) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN RNG_Init 2 */ + + /* USER CODE END RNG_Init 2 */ + +} + +/** + * @brief RTC Initialization Function + * @param None + * @retval None + */ +static void MX_RTC_Init(void) +{ + + /* USER CODE BEGIN RTC_Init 0 */ + + /* USER CODE END RTC_Init 0 */ + + /* USER CODE BEGIN RTC_Init 1 */ + + /* USER CODE END RTC_Init 1 */ + /** Initialize RTC Only + */ + hrtc.Instance = RTC; + hrtc.Init.HourFormat = RTC_HOURFORMAT_24; + hrtc.Init.AsynchPrediv = 127; + hrtc.Init.SynchPrediv = 255; + hrtc.Init.OutPut = RTC_OUTPUT_DISABLE; + hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; + hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; + if (HAL_RTC_Init(&hrtc) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN RTC_Init 2 */ + + /* USER CODE END RTC_Init 2 */ + +} + +/** + * @brief SDIO Initialization Function + * @param None + * @retval None + */ +static void MX_SDIO_SD_Init(void) +{ + + /* USER CODE BEGIN SDIO_Init 0 */ + + /* USER CODE END SDIO_Init 0 */ + + /* USER CODE BEGIN SDIO_Init 1 */ + + /* USER CODE END SDIO_Init 1 */ + hsd.Instance = SDIO; + hsd.Init.ClockEdge = SDIO_CLOCK_EDGE_RISING; + hsd.Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE; + hsd.Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE; + hsd.Init.BusWide = SDIO_BUS_WIDE_1B; + hsd.Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE; + hsd.Init.ClockDiv = 0; + if (HAL_SD_Init(&hsd) != HAL_OK) + { + Error_Handler(); + } + if (HAL_SD_ConfigWideBusOperation(&hsd, SDIO_BUS_WIDE_4B) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SDIO_Init 2 */ + + /* USER CODE END SDIO_Init 2 */ + +} + +/** + * @brief SPI3 Initialization Function + * @param None + * @retval None + */ +static void MX_SPI3_Init(void) +{ + + /* USER CODE BEGIN SPI3_Init 0 */ + + /* USER CODE END SPI3_Init 0 */ + + /* USER CODE BEGIN SPI3_Init 1 */ + + /* USER CODE END SPI3_Init 1 */ + /* SPI3 parameter configuration*/ + hspi3.Instance = SPI3; + hspi3.Init.Mode = SPI_MODE_MASTER; + hspi3.Init.Direction = SPI_DIRECTION_2LINES; + hspi3.Init.DataSize = SPI_DATASIZE_8BIT; + hspi3.Init.CLKPolarity = SPI_POLARITY_LOW; + hspi3.Init.CLKPhase = SPI_PHASE_1EDGE; + hspi3.Init.NSS = SPI_NSS_SOFT; + hspi3.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + hspi3.Init.FirstBit = SPI_FIRSTBIT_MSB; + hspi3.Init.TIMode = SPI_TIMODE_DISABLE; + hspi3.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + hspi3.Init.CRCPolynomial = 10; + if (HAL_SPI_Init(&hspi3) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SPI3_Init 2 */ + + /* USER CODE END SPI3_Init 2 */ + +} + +/** + * @brief TIM10 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM10_Init(void) +{ + + /* USER CODE BEGIN TIM10_Init 0 */ + + /* USER CODE END TIM10_Init 0 */ + + TIM_OC_InitTypeDef sConfigOC = {0}; + + /* USER CODE BEGIN TIM10_Init 1 */ + + /* USER CODE END TIM10_Init 1 */ + htim10.Instance = TIM10; + htim10.Init.Prescaler = 0; + htim10.Init.CounterMode = TIM_COUNTERMODE_UP; + htim10.Init.Period = 0; + htim10.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim10.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim10) != HAL_OK) + { + Error_Handler(); + } + if (HAL_TIM_PWM_Init(&htim10) != HAL_OK) + { + Error_Handler(); + } + sConfigOC.OCMode = TIM_OCMODE_PWM1; + sConfigOC.Pulse = 0; + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + if (HAL_TIM_PWM_ConfigChannel(&htim10, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM10_Init 2 */ + + /* USER CODE END TIM10_Init 2 */ + HAL_TIM_MspPostInit(&htim10); + +} + +/** + * @brief TIM11 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM11_Init(void) +{ + + /* USER CODE BEGIN TIM11_Init 0 */ + + /* USER CODE END TIM11_Init 0 */ + + /* USER CODE BEGIN TIM11_Init 1 */ + + /* USER CODE END TIM11_Init 1 */ + htim11.Instance = TIM11; + htim11.Init.Prescaler = 0; + htim11.Init.CounterMode = TIM_COUNTERMODE_UP; + htim11.Init.Period = 0; + htim11.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim11.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim11) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM11_Init 2 */ + + /* USER CODE END TIM11_Init 2 */ + +} + +/** + * @brief TIM13 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM13_Init(void) +{ + + /* USER CODE BEGIN TIM13_Init 0 */ + + /* USER CODE END TIM13_Init 0 */ + + /* USER CODE BEGIN TIM13_Init 1 */ + + /* USER CODE END TIM13_Init 1 */ + htim13.Instance = TIM13; + htim13.Init.Prescaler = 0; + htim13.Init.CounterMode = TIM_COUNTERMODE_UP; + htim13.Init.Period = 0; + htim13.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim13.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim13) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM13_Init 2 */ + + /* USER CODE END TIM13_Init 2 */ + +} + +/** + * @brief TIM14 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM14_Init(void) +{ + + /* USER CODE BEGIN TIM14_Init 0 */ + + /* USER CODE END TIM14_Init 0 */ + + /* USER CODE BEGIN TIM14_Init 1 */ + + /* USER CODE END TIM14_Init 1 */ + htim14.Instance = TIM14; + htim14.Init.Prescaler = 0; + htim14.Init.CounterMode = TIM_COUNTERMODE_UP; + htim14.Init.Period = 0; + htim14.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim14.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim14) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM14_Init 2 */ + + /* USER CODE END TIM14_Init 2 */ + +} + +/** + * @brief USART1 Initialization Function + * @param None + * @retval None + */ +static void MX_USART1_UART_Init(void) +{ + + /* USER CODE BEGIN USART1_Init 0 */ + + /* USER CODE END USART1_Init 0 */ + + /* USER CODE BEGIN USART1_Init 1 */ + + /* USER CODE END USART1_Init 1 */ + huart1.Instance = USART1; + huart1.Init.BaudRate = 115200; + huart1.Init.WordLength = UART_WORDLENGTH_8B; + huart1.Init.StopBits = UART_STOPBITS_1; + huart1.Init.Parity = UART_PARITY_NONE; + huart1.Init.Mode = UART_MODE_TX_RX; + huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart1.Init.OverSampling = UART_OVERSAMPLING_16; + if (HAL_UART_Init(&huart1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART1_Init 2 */ + + /* USER CODE END USART1_Init 2 */ + +} + +/** + * @brief USART2 Initialization Function + * @param None + * @retval None + */ +static void MX_USART2_UART_Init(void) +{ + + /* USER CODE BEGIN USART2_Init 0 */ + + /* USER CODE END USART2_Init 0 */ + + /* USER CODE BEGIN USART2_Init 1 */ + + /* USER CODE END USART2_Init 1 */ + huart2.Instance = USART2; + huart2.Init.BaudRate = 115200; + huart2.Init.WordLength = UART_WORDLENGTH_8B; + huart2.Init.StopBits = UART_STOPBITS_1; + huart2.Init.Parity = UART_PARITY_NONE; + huart2.Init.Mode = UART_MODE_TX_RX; + huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart2.Init.OverSampling = UART_OVERSAMPLING_16; + if (HAL_UART_Init(&huart2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART2_Init 2 */ + + /* USER CODE END USART2_Init 2 */ + +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOI_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + + /* USER CODE END Error_Handler_Debug */ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c new file mode 100644 index 0000000000..5f62b1806d --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c @@ -0,0 +1,721 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * File Name : stm32f4xx_hal_msp.c + * Description : This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + /** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); + + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/** +* @brief ADC MSP Initialization +* This function configures the hardware resources used in this example +* @param hadc: ADC handle pointer +* @retval None +*/ +void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hadc->Instance==ADC1) + { + /* USER CODE BEGIN ADC1_MspInit 0 */ + + /* USER CODE END ADC1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_ADC1_CLK_ENABLE(); + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**ADC1 GPIO Configuration + PB1 ------> ADC1_IN9 + */ + GPIO_InitStruct.Pin = GPIO_PIN_1; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN ADC1_MspInit 1 */ + + /* USER CODE END ADC1_MspInit 1 */ + } + +} + +/** +* @brief ADC MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hadc: ADC handle pointer +* @retval None +*/ +void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) +{ + if(hadc->Instance==ADC1) + { + /* USER CODE BEGIN ADC1_MspDeInit 0 */ + + /* USER CODE END ADC1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_ADC1_CLK_DISABLE(); + + /**ADC1 GPIO Configuration + PB1 ------> ADC1_IN9 + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_1); + + /* USER CODE BEGIN ADC1_MspDeInit 1 */ + + /* USER CODE END ADC1_MspDeInit 1 */ + } + +} + +/** +* @brief I2S MSP Initialization +* This function configures the hardware resources used in this example +* @param hi2s: I2S handle pointer +* @retval None +*/ +void HAL_I2S_MspInit(I2S_HandleTypeDef* hi2s) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hi2s->Instance==SPI2) + { + /* USER CODE BEGIN SPI2_MspInit 0 */ + + /* USER CODE END SPI2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI2_CLK_ENABLE(); + + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOI_CLK_ENABLE(); + /**I2S2 GPIO Configuration + PB12 ------> I2S2_WS + PB13 ------> I2S2_CK + PB15 ------> I2S2_SD + PC6 ------> I2S2_MCK + PI2 ------> I2S2_ext_SD + */ + GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_15; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF6_I2S2ext; + HAL_GPIO_Init(GPIOI, &GPIO_InitStruct); + + /* USER CODE BEGIN SPI2_MspInit 1 */ + + /* USER CODE END SPI2_MspInit 1 */ + } + +} + +/** +* @brief I2S MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hi2s: I2S handle pointer +* @retval None +*/ +void HAL_I2S_MspDeInit(I2S_HandleTypeDef* hi2s) +{ + if(hi2s->Instance==SPI2) + { + /* USER CODE BEGIN SPI2_MspDeInit 0 */ + + /* USER CODE END SPI2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI2_CLK_DISABLE(); + + /**I2S2 GPIO Configuration + PB12 ------> I2S2_WS + PB13 ------> I2S2_CK + PB15 ------> I2S2_SD + PC6 ------> I2S2_MCK + PI2 ------> I2S2_ext_SD + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_15); + + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_6); + + HAL_GPIO_DeInit(GPIOI, GPIO_PIN_2); + + /* USER CODE BEGIN SPI2_MspDeInit 1 */ + + /* USER CODE END SPI2_MspDeInit 1 */ + } + +} + +/** +* @brief RNG MSP Initialization +* This function configures the hardware resources used in this example +* @param hrng: RNG handle pointer +* @retval None +*/ +void HAL_RNG_MspInit(RNG_HandleTypeDef* hrng) +{ + if(hrng->Instance==RNG) + { + /* USER CODE BEGIN RNG_MspInit 0 */ + + /* USER CODE END RNG_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_RNG_CLK_ENABLE(); + /* USER CODE BEGIN RNG_MspInit 1 */ + + /* USER CODE END RNG_MspInit 1 */ + } + +} + +/** +* @brief RNG MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hrng: RNG handle pointer +* @retval None +*/ +void HAL_RNG_MspDeInit(RNG_HandleTypeDef* hrng) +{ + if(hrng->Instance==RNG) + { + /* USER CODE BEGIN RNG_MspDeInit 0 */ + + /* USER CODE END RNG_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_RNG_CLK_DISABLE(); + /* USER CODE BEGIN RNG_MspDeInit 1 */ + + /* USER CODE END RNG_MspDeInit 1 */ + } + +} + +/** +* @brief RTC MSP Initialization +* This function configures the hardware resources used in this example +* @param hrtc: RTC handle pointer +* @retval None +*/ +void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) +{ + if(hrtc->Instance==RTC) + { + /* USER CODE BEGIN RTC_MspInit 0 */ + + /* USER CODE END RTC_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_RTC_ENABLE(); + /* USER CODE BEGIN RTC_MspInit 1 */ + + /* USER CODE END RTC_MspInit 1 */ + } + +} + +/** +* @brief RTC MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hrtc: RTC handle pointer +* @retval None +*/ +void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) +{ + if(hrtc->Instance==RTC) + { + /* USER CODE BEGIN RTC_MspDeInit 0 */ + + /* USER CODE END RTC_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_RTC_DISABLE(); + /* USER CODE BEGIN RTC_MspDeInit 1 */ + + /* USER CODE END RTC_MspDeInit 1 */ + } + +} + +/** +* @brief SD MSP Initialization +* This function configures the hardware resources used in this example +* @param hsd: SD handle pointer +* @retval None +*/ +void HAL_SD_MspInit(SD_HandleTypeDef* hsd) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hsd->Instance==SDIO) + { + /* USER CODE BEGIN SDIO_MspInit 0 */ + + /* USER CODE END SDIO_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SDIO_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + /**SDIO GPIO Configuration + PC8 ------> SDIO_D0 + PC9 ------> SDIO_D1 + PC10 ------> SDIO_D2 + PC11 ------> SDIO_D3 + PC12 ------> SDIO_CK + PD2 ------> SDIO_CMD + */ + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + |GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_SDIO; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_SDIO; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* USER CODE BEGIN SDIO_MspInit 1 */ + + /* USER CODE END SDIO_MspInit 1 */ + } + +} + +/** +* @brief SD MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hsd: SD handle pointer +* @retval None +*/ +void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) +{ + if(hsd->Instance==SDIO) + { + /* USER CODE BEGIN SDIO_MspDeInit 0 */ + + /* USER CODE END SDIO_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SDIO_CLK_DISABLE(); + + /**SDIO GPIO Configuration + PC8 ------> SDIO_D0 + PC9 ------> SDIO_D1 + PC10 ------> SDIO_D2 + PC11 ------> SDIO_D3 + PC12 ------> SDIO_CK + PD2 ------> SDIO_CMD + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + |GPIO_PIN_12); + + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); + + /* USER CODE BEGIN SDIO_MspDeInit 1 */ + + /* USER CODE END SDIO_MspDeInit 1 */ + } + +} + +/** +* @brief SPI MSP Initialization +* This function configures the hardware resources used in this example +* @param hspi: SPI handle pointer +* @retval None +*/ +void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hspi->Instance==SPI3) + { + /* USER CODE BEGIN SPI3_MspInit 0 */ + + /* USER CODE END SPI3_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI3_CLK_ENABLE(); + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**SPI3 GPIO Configuration + PB3 ------> SPI3_SCK + PB4 ------> SPI3_MISO + PB5 ------> SPI3_MOSI + */ + GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF6_SPI3; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN SPI3_MspInit 1 */ + + /* USER CODE END SPI3_MspInit 1 */ + } + +} + +/** +* @brief SPI MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hspi: SPI handle pointer +* @retval None +*/ +void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) +{ + if(hspi->Instance==SPI3) + { + /* USER CODE BEGIN SPI3_MspDeInit 0 */ + + /* USER CODE END SPI3_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI3_CLK_DISABLE(); + + /**SPI3 GPIO Configuration + PB3 ------> SPI3_SCK + PB4 ------> SPI3_MISO + PB5 ------> SPI3_MOSI + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5); + + /* USER CODE BEGIN SPI3_MspDeInit 1 */ + + /* USER CODE END SPI3_MspDeInit 1 */ + } + +} + +/** +* @brief TIM_Base MSP Initialization +* This function configures the hardware resources used in this example +* @param htim_base: TIM_Base handle pointer +* @retval None +*/ +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) +{ + if(htim_base->Instance==TIM10) + { + /* USER CODE BEGIN TIM10_MspInit 0 */ + + /* USER CODE END TIM10_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM10_CLK_ENABLE(); + /* USER CODE BEGIN TIM10_MspInit 1 */ + + /* USER CODE END TIM10_MspInit 1 */ + } + else if(htim_base->Instance==TIM11) + { + /* USER CODE BEGIN TIM11_MspInit 0 */ + + /* USER CODE END TIM11_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM11_CLK_ENABLE(); + /* USER CODE BEGIN TIM11_MspInit 1 */ + + /* USER CODE END TIM11_MspInit 1 */ + } + else if(htim_base->Instance==TIM13) + { + /* USER CODE BEGIN TIM13_MspInit 0 */ + + /* USER CODE END TIM13_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM13_CLK_ENABLE(); + /* USER CODE BEGIN TIM13_MspInit 1 */ + + /* USER CODE END TIM13_MspInit 1 */ + } + else if(htim_base->Instance==TIM14) + { + /* USER CODE BEGIN TIM14_MspInit 0 */ + + /* USER CODE END TIM14_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM14_CLK_ENABLE(); + /* USER CODE BEGIN TIM14_MspInit 1 */ + + /* USER CODE END TIM14_MspInit 1 */ + } + +} + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(htim->Instance==TIM10) + { + /* USER CODE BEGIN TIM10_MspPostInit 0 */ + + /* USER CODE END TIM10_MspPostInit 0 */ + + __HAL_RCC_GPIOF_CLK_ENABLE(); + /**TIM10 GPIO Configuration + PF6 ------> TIM10_CH1 + */ + GPIO_InitStruct.Pin = GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF3_TIM10; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + /* USER CODE BEGIN TIM10_MspPostInit 1 */ + + /* USER CODE END TIM10_MspPostInit 1 */ + } + +} +/** +* @brief TIM_Base MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param htim_base: TIM_Base handle pointer +* @retval None +*/ +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base) +{ + if(htim_base->Instance==TIM10) + { + /* USER CODE BEGIN TIM10_MspDeInit 0 */ + + /* USER CODE END TIM10_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM10_CLK_DISABLE(); + /* USER CODE BEGIN TIM10_MspDeInit 1 */ + + /* USER CODE END TIM10_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM11) + { + /* USER CODE BEGIN TIM11_MspDeInit 0 */ + + /* USER CODE END TIM11_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM11_CLK_DISABLE(); + /* USER CODE BEGIN TIM11_MspDeInit 1 */ + + /* USER CODE END TIM11_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM13) + { + /* USER CODE BEGIN TIM13_MspDeInit 0 */ + + /* USER CODE END TIM13_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM13_CLK_DISABLE(); + /* USER CODE BEGIN TIM13_MspDeInit 1 */ + + /* USER CODE END TIM13_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM14) + { + /* USER CODE BEGIN TIM14_MspDeInit 0 */ + + /* USER CODE END TIM14_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM14_CLK_DISABLE(); + /* USER CODE BEGIN TIM14_MspDeInit 1 */ + + /* USER CODE END TIM14_MspDeInit 1 */ + } + +} + +/** +* @brief UART MSP Initialization +* This function configures the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspInit(UART_HandleTypeDef* huart) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(huart->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspInit 0 */ + + /* USER CODE END USART1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_USART1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USART1 GPIO Configuration + PA9 ------> USART1_TX + PA10 ------> USART1_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN USART1_MspInit 1 */ + + /* USER CODE END USART1_MspInit 1 */ + } + else if(huart->Instance==USART2) + { + /* USER CODE BEGIN USART2_MspInit 0 */ + + /* USER CODE END USART2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_USART2_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USART2 GPIO Configuration + PA2 ------> USART2_TX + PA3 ------> USART2_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART2; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN USART2_MspInit 1 */ + + /* USER CODE END USART2_MspInit 1 */ + } + +} + +/** +* @brief UART MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) +{ + if(huart->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspDeInit 0 */ + + /* USER CODE END USART1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART1_CLK_DISABLE(); + + /**USART1 GPIO Configuration + PA9 ------> USART1_TX + PA10 ------> USART1_RX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); + + /* USER CODE BEGIN USART1_MspDeInit 1 */ + + /* USER CODE END USART1_MspDeInit 1 */ + } + else if(huart->Instance==USART2) + { + /* USER CODE BEGIN USART2_MspDeInit 0 */ + + /* USER CODE END USART2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART2_CLK_DISABLE(); + + /**USART2 GPIO Configuration + PA2 ------> USART2_TX + PA3 ------> USART2_RX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3); + + /* USER CODE BEGIN USART2_MspDeInit 1 */ + + /* USER CODE END USART2_MspDeInit 1 */ + } + +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Src/stm32f4xx_it.c b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Src/stm32f4xx_it.c new file mode 100644 index 0000000000..84413fb5f2 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Src/stm32f4xx_it.c @@ -0,0 +1,203 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f4xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32f4xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ + +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M4 Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn 0 */ + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32F4xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32f4xx.s). */ +/******************************************************************************/ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Src/system_stm32f4xx.c b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Src/system_stm32f4xx.c new file mode 100644 index 0000000000..bcb2b9f4a5 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Src/system_stm32f4xx.c @@ -0,0 +1,727 @@ +/** + ****************************************************************************** + * @file system_stm32f4xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f4xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx_system + * @{ + */ + +/** @addtogroup STM32F4xx_System_Private_Includes + * @{ + */ + + +#include "stm32f4xx.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ + || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) +/* #define DATA_IN_ExtSRAM */ +#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\ + STM32F412Zx || STM32F412Vx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +/* #define DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ + STM32F479xx */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +uint32_t SystemCoreClock = 16000000; +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes + * @{ + */ + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting, vector table location and External memory + * configuration. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value + * depends on the application requirements), user has to ensure that HSE_VALUE + * is same as the real frequency of the crystal used. Otherwise, this function + * may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f4xx.s before jump to main. + * This function configures the external memories (SRAM/SDRAM) + * This SRAM/SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + __IO uint32_t tmp = 0x00; + + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register __IO uint32_t index; + + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */ + RCC->AHB1ENR |= 0x000001F8; + + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0xCCCCCCCC; + GPIOF->AFR[1] = 0xCCCCCCCC; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0xCCCCCCCC; + GPIOG->AFR[1] = 0xCCCCCCCC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xAAAAAAAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0xAAAAAAAA; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x00000000; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00000000; + +/*-- FMC Configuration -------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + FMC_Bank5_6->SDCR[0] = 0x000019E4; + FMC_Bank5_6->SDTR[0] = 0x01115351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ + FMC_Bank5_6->SDCMR = 0x00000073; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ + FMC_Bank5_6->SDCMR = 0x00046014; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001011; + FMC_Bank1->BTCR[3] = 0x00000201; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#if defined(STM32F469xx) || defined(STM32F479xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001091; + FMC_Bank1->BTCR[3] = 0x00110212; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F469xx || STM32F479xx */ + + (void)(tmp); +} +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ +#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f4xx.s before jump to main. + * This function configures the external memories (SRAM/SDRAM) + * This SRAM/SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + __IO uint32_t tmp = 0x00; +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +#if defined (DATA_IN_ExtSDRAM) + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register __IO uint32_t index; + +#if defined(STM32F446xx) + /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface + clock */ + RCC->AHB1ENR |= 0x0000007D; +#else + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface + clock */ + RCC->AHB1ENR |= 0x000001F8; +#endif /* STM32F446xx */ + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); + +#if defined(STM32F446xx) + /* Connect PAx pins to FMC Alternate function */ + GPIOA->AFR[0] |= 0xC0000000; + GPIOA->AFR[1] |= 0x00000000; + /* Configure PDx pins in Alternate function mode */ + GPIOA->MODER |= 0x00008000; + /* Configure PDx pins speed to 50 MHz */ + GPIOA->OSPEEDR |= 0x00008000; + /* Configure PDx pins Output type to push-pull */ + GPIOA->OTYPER |= 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOA->PUPDR |= 0x00000000; + + /* Connect PCx pins to FMC Alternate function */ + GPIOC->AFR[0] |= 0x00CC0000; + GPIOC->AFR[1] |= 0x00000000; + /* Configure PDx pins in Alternate function mode */ + GPIOC->MODER |= 0x00000A00; + /* Configure PDx pins speed to 50 MHz */ + GPIOC->OSPEEDR |= 0x00000A00; + /* Configure PDx pins Output type to push-pull */ + GPIOC->OTYPER |= 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOC->PUPDR |= 0x00000000; +#endif /* STM32F446xx */ + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x000000CC; + GPIOD->AFR[1] = 0xCC000CCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xA02A000A; + /* Configure PDx pins speed to 50 MHz */ + GPIOD->OSPEEDR = 0xA02A000A; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00000CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA800A; + /* Configure PEx pins speed to 50 MHz */ + GPIOE->OSPEEDR = 0xAAAA800A; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0xCCCCCCCC; + GPIOF->AFR[1] = 0xCCCCCCCC; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0xCCCCCCCC; + GPIOG->AFR[1] = 0xCCCCCCCC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xAAAAAAAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0xAAAAAAAA; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x00000000; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00000000; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +/*-- FMC Configuration -------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + /* Configure and enable SDRAM bank1 */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCR[0] = 0x00001954; +#else + FMC_Bank5_6->SDCR[0] = 0x000019E4; +#endif /* STM32F446xx */ + FMC_Bank5_6->SDTR[0] = 0x01115351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCMR = 0x000000F3; +#else + FMC_Bank5_6->SDCMR = 0x00000073; +#endif /* STM32F446xx */ + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCMR = 0x00044014; +#else + FMC_Bank5_6->SDCMR = 0x00046014; +#endif /* STM32F446xx */ + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; +#if defined(STM32F446xx) + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1)); +#else + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); +#endif /* STM32F446xx */ + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); +#endif /* DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ + || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) + +#if defined(DATA_IN_ExtSRAM) +/*-- GPIOs Configuration -----------------------------------------------------*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR |= 0x00000078; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0x00CCCCCC; + GPIOF->AFR[1] = 0xCCCC0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA000AAA; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xFF000FFF; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0x00CCCCCC; + GPIOG->AFR[1] = 0x000000C0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00085AAA; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000CAFFF; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FMC/FSMC Configuration --------------------------------------------------*/ + /* Enable the FMC/FSMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001011; + FMC_Bank1->BTCR[3] = 0x00000201; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#if defined(STM32F469xx) || defined(STM32F479xx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001091; + FMC_Bank1->BTCR[3] = 0x00110212; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F469xx || STM32F479xx */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\ + || defined(STM32F412Zx) || defined(STM32F412Vx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN); + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001011; + FSMC_Bank1->BTCR[3] = 0x00000201; + FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */ + +#endif /* DATA_IN_ExtSRAM */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ + STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */ + (void)(tmp); +} +#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f407-armfly-v5/board/Kconfig b/bsp/stm32/stm32f407-armfly-v5/board/Kconfig new file mode 100644 index 0000000000..7c6b8a97f0 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/Kconfig @@ -0,0 +1,199 @@ +menu "Hardware Drivers Config" + +config SOC_STM32F407IG + bool + select SOC_SERIES_STM32F4 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "Onboard Peripheral Drivers" + + config BSP_USING_RS232_TO_USART + bool "Enable RS232 TO USART (uart1)" + select BSP_USING_UART + select BSP_USING_UART1 + default y + + config BSP_USING_SPI_FLASH + bool "Enable SPI FLASH (W25Q64 spi3)" + select BSP_USING_SPI + select BSP_USING_SPI3 + select RT_USING_SFUD + select RT_SFUD_USING_SFDP + default n + + config BSP_USING_SDCARD + bool "Enable SDCARD (sdio)" + select BSP_USING_SDIO + select RT_USING_DFS + select RT_USING_DFS_ELMFAT + default n + + config BSP_USING_MPU6050 + bool "Enable MPU6050(i2c2)" + select BSP_USING_I2C2 + select PKG_USING_SENSORS_DRIVERS + select PKG_USING_MPU6XXX + select PKG_USING_MPU6XXX_SAMPLE + select PKG_USING_MPU6XXX_LATEST_VERSION + default n + +endmenu + +menu "On-chip Peripheral Drivers" + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART1 + bool "Enable UART1" + default y + + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART2 + bool "Enable UART2" + default y + + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + endif + + config BSP_USING_ON_CHIP_FLASH + bool "Enable on-chip FLASH" + default n + + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI3 + bool "Enable SPI3 BUS" + default n + + config BSP_SPI3_TX_USING_DMA + bool "Enable SPI3 TX DMA" + depends on BSP_USING_SPI3 + default n + + config BSP_SPI3_RX_USING_DMA + bool "Enable SPI3 RX DMA" + depends on BSP_USING_SPI3 + select BSP_SPI3_TX_USING_DMA + default n + endif + + menuconfig BSP_USING_I2C2 + bool "Enable I2C2 BUS (software simulation)" + default n + select RT_USING_I2C + select RT_USING_I2C_BITOPS + select RT_USING_PIN + if BSP_USING_I2C2 + comment "Notice: PH4 --> 116; PH5 --> 117" + config BSP_I2C2_SCL_PIN + int "i2c2 scl pin number" + range 1 143 + default 116 + config BSP_I2C2_SDA_PIN + int "I2C2 sda pin number" + range 1 143 + default 117 + endif + + menuconfig BSP_USING_TIM + bool "Enable timer" + default n + select RT_USING_HWTIMER + if BSP_USING_TIM + config BSP_USING_TIM11 + bool "Enable TIM11" + default n + + config BSP_USING_TIM13 + bool "Enable TIM13" + default n + + config BSP_USING_TIM14 + bool "Enable TIM14" + default n + endif + + menuconfig BSP_USING_PWM + bool "Enable pwm" + default n + select RT_USING_PWM + if BSP_USING_PWM + menuconfig BSP_USING_PWM10 + bool "Enable timer10 output pwm" + default n + if BSP_USING_PWM10 + config BSP_USING_PWM10_CH1 + bool "Enable PWM10 channel1" + default n + endif + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC + if BSP_USING_ADC + config BSP_USING_ADC1 + bool "Enable ADC1" + default n + endif + + menuconfig BSP_USING_ONCHIP_RTC + bool "Enable RTC" + select RT_USING_RTC + select RT_USING_LIBC + default n + if BSP_USING_ONCHIP_RTC + choice + prompt "Select clock source" + default BSP_RTC_USING_LSE + + config BSP_RTC_USING_LSE + bool "RTC USING LSE" + + config BSP_RTC_USING_LSI + bool "RTC USING LSI" + endchoice + endif + + config BSP_USING_WDT + bool "Enable Watchdog Timer" + select RT_USING_WDT + default n + + config BSP_USING_SDIO + bool "Enable SDIO" + select RT_USING_SDIO + select RT_USING_DFS + default n + + source "../libraries/HAL_Drivers/Kconfig" + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/stm32/stm32f407-armfly-v5/board/SConscript b/bsp/stm32/stm32f407-armfly-v5/board/SConscript new file mode 100644 index 0000000000..2528db7cee --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/SConscript @@ -0,0 +1,44 @@ +import os +import rtconfig +from building import * + +Import('SDK_LIB') + +cwd = GetCurrentDir() + +# add general drivers +src = Split(''' +board.c +CubeMX_Config/Src/stm32f4xx_hal_msp.c +''') + +if GetDepend(['BSP_USING_SPI_FLASH']): + src += Glob('ports/spi_flash_init.c') + +if GetDepend(['BSP_USING_SDCARD']): + src += Glob('ports/sdcard_port.c') + +path = [cwd] +path += [cwd + '/CubeMX_Config/Inc'] +path += [cwd + '/ports'] + +startup_path_prefix = SDK_LIB + +if rtconfig.CROSS_TOOL == 'gcc': + src += [startup_path_prefix + '/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f407xx.s'] +elif rtconfig.CROSS_TOOL == 'keil': + src += [startup_path_prefix + '/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f407xx.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src += [startup_path_prefix + '/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f407xx.s'] + +# STM32F405xx) || STM32F415xx) || STM32F407xx) || STM32F417xx) +# STM32F427xx) || STM32F437xx) || STM32F429xx) || STM32F439xx) +# STM32F401xC) || STM32F401xE) || STM32F410Tx) || STM32F410Cx) +# STM32F410Rx) || STM32F411xE) || STM32F446xx) || STM32F469xx) +# STM32F479xx) || STM32F412Cx) || STM32F412Rx) || STM32F412Vx) +# STM32F412Zx) || STM32F413xx) || STM32F423xx) +# You can select chips from the list above +CPPDEFINES = ['STM32F407xx'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/stm32/stm32f407-armfly-v5/board/board.c b/bsp/stm32/stm32f407-armfly-v5/board/board.c new file mode 100644 index 0000000000..e64882e5e1 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/board.c @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-13 Dozingfiretruck first version + */ + +#include "board.h" + +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE + |RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 25; + RCC_OscInitStruct.PLL.PLLN = 336; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 7; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) + { + Error_Handler(); + } + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2S|RCC_PERIPHCLK_RTC; + PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; + PeriphClkInitStruct.PLLI2S.PLLI2SR = 2; + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } +} diff --git a/bsp/stm32/stm32f407-armfly-v5/board/board.h b/bsp/stm32/stm32f407-armfly-v5/board/board.h new file mode 100644 index 0000000000..68016d18bd --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/board.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-13 Dozingfiretruck first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include +#include "drv_common.h" +#include "drv_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000) +#define STM32_FLASH_SIZE (1024 * 1024) +#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE)) + +#define STM32_SRAM_SIZE 128 +#define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) + +#if defined(__CC_ARM) || defined(__CLANG_ARM) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="CSTACK" +#define HEAP_BEGIN (__segment_end("CSTACK")) +#else +extern int __bss_end; +#define HEAP_BEGIN (&__bss_end) +#endif + +#define HEAP_END STM32_SRAM_END + +void SystemClock_Config(void); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/bsp/stm32/stm32f407-armfly-v5/board/linker_scripts/link.icf b/bsp/stm32/stm32f407-armfly-v5/board/linker_scripts/link.icf new file mode 100644 index 0000000000..067691151f --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/linker_scripts/link.icf @@ -0,0 +1,28 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x0400; +define symbol __ICFEDIT_size_heap__ = 0x0000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, last block CSTACK}; diff --git a/bsp/stm32/stm32f407-armfly-v5/board/linker_scripts/link.lds b/bsp/stm32/stm32f407-armfly-v5/board/linker_scripts/link.lds new file mode 100644 index 0000000000..00a1f08cf1 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/linker_scripts/link.lds @@ -0,0 +1,157 @@ +/* + * linker script for STM32F4xx with GNU ld + * bernard.xiong 2009-10-14 + */ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + ROM (rx) : ORIGIN = 0x08000000, LENGTH = 1024k /* 1024KB flash */ + RAM (rw) : ORIGIN = 0x20000000, LENGTH = 128k /* 128KB sram */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x200; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(4); + + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + + _etext = .; + } > ROM = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > ROM + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >RAM + + .stack : + { + . = ALIGN(4); + _sstack = .; + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >RAM + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > RAM + __bss_end = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/stm32/stm32f407-armfly-v5/board/linker_scripts/link.sct b/bsp/stm32/stm32f407-armfly-v5/board/linker_scripts/link.sct new file mode 100644 index 0000000000..0d7c47992d --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/linker_scripts/link.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x00100000 { ; load region size_region + ER_IROM1 0x08000000 0x00100000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00020000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/stm32/stm32f407-armfly-v5/board/ports/fal_cfg.h b/bsp/stm32/stm32f407-armfly-v5/board/ports/fal_cfg.h new file mode 100644 index 0000000000..20bcf9e11a --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/ports/fal_cfg.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-13 Dozingfiretruck first version + */ + +#ifndef _FAL_CFG_H_ +#define _FAL_CFG_H_ + +#include +#include + +#define FLASH_SIZE_GRANULARITY_16K (4 * 16 * 1024) +#define FLASH_SIZE_GRANULARITY_64K (64 * 1024) +#define FLASH_SIZE_GRANULARITY_128K (7 * 128 * 1024) + +#define STM32_FLASH_START_ADRESS_16K STM32_FLASH_START_ADRESS +#define STM32_FLASH_START_ADRESS_64K (STM32_FLASH_START_ADRESS_16K + FLASH_SIZE_GRANULARITY_16K) +#define STM32_FLASH_START_ADRESS_128K (STM32_FLASH_START_ADRESS_64K + FLASH_SIZE_GRANULARITY_64K) + +extern const struct fal_flash_dev stm32_onchip_flash_16k; +extern const struct fal_flash_dev stm32_onchip_flash_64k; +extern const struct fal_flash_dev stm32_onchip_flash_128k; + +/* flash device table */ +#define FAL_FLASH_DEV_TABLE \ +{ \ + &stm32_onchip_flash_16k, \ + &stm32_onchip_flash_64k, \ + &stm32_onchip_flash_128k, \ +} +/* ====================== Partition Configuration ========================== */ +#ifdef FAL_PART_HAS_TABLE_CFG + +/* partition table */ +#define FAL_PART_TABLE \ +{ \ + {FAL_PART_MAGIC_WROD, "bootloader", "onchip_flash_16k", 0 , FLASH_SIZE_GRANULARITY_16K , 0}, \ + {FAL_PART_MAGIC_WROD, "param", "onchip_flash_64k", 0 , FLASH_SIZE_GRANULARITY_64K , 0}, \ + {FAL_PART_MAGIC_WROD, "app", "onchip_flash_128k", 0 , FLASH_SIZE_GRANULARITY_128K, 0}, \ +} + +#endif /* FAL_PART_HAS_TABLE_CFG */ +#endif /* _FAL_CFG_H_ */ diff --git a/bsp/stm32/stm32f407-armfly-v5/board/ports/sdcard_port.c b/bsp/stm32/stm32f407-armfly-v5/board/ports/sdcard_port.c new file mode 100644 index 0000000000..5eead223c3 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/ports/sdcard_port.c @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-13 Dozingfiretruck first version + */ + +#include + +#ifdef BSP_USING_SDCARD + +#include +#include +#include + +#define DBG_TAG "app.card" +#define DBG_LVL DBG_INFO +#include + +void sd_mount(void *parameter) +{ + while (1) + { + rt_thread_mdelay(500); + if(rt_device_find("sd0") != RT_NULL) + { + if (dfs_mount("sd0", "/", "elm", 0, 0) == RT_EOK) + { + LOG_I("sd card mount to '/'"); + break; + } + else + { + LOG_W("sd card mount to '/' failed!"); + } + } + } +} + +int stm32_sdcard_mount(void) +{ + rt_thread_t tid; + + tid = rt_thread_create("sd_mount", sd_mount, RT_NULL, + 1024, RT_THREAD_PRIORITY_MAX - 2, 20); + if (tid != RT_NULL) + { + rt_thread_startup(tid); + } + else + { + LOG_E("create sd_mount thread err!"); + } + return RT_EOK; +} +INIT_APP_EXPORT(stm32_sdcard_mount); + +#endif /* BSP_USING_SDCARD */ + diff --git a/bsp/stm32/stm32f407-armfly-v5/board/ports/spi_flash_init.c b/bsp/stm32/stm32f407-armfly-v5/board/ports/spi_flash_init.c new file mode 100644 index 0000000000..9aa8f95c13 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/ports/spi_flash_init.c @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-13 Dozingfiretruck first version + */ + +#include +#include "spi_flash.h" +#include "spi_flash_sfud.h" +#include "drv_spi.h" + +#if defined(BSP_USING_SPI_FLASH) +static int rt_hw_spi_flash_init(void) +{ + __HAL_RCC_GPIOF_CLK_ENABLE(); + rt_hw_spi_device_attach("spi3", "spi30", GPIOF, GPIO_PIN_8); + + if (RT_NULL == rt_sfud_flash_probe("W25Q64", "spi30")) + { + return -RT_ERROR; + }; + + return RT_EOK; +} +INIT_COMPONENT_EXPORT(rt_hw_spi_flash_init); +#endif + diff --git a/bsp/stm32/stm32f407-armfly-v5/figures/board.png b/bsp/stm32/stm32f407-armfly-v5/figures/board.png new file mode 100644 index 0000000000..94de91c012 Binary files /dev/null and b/bsp/stm32/stm32f407-armfly-v5/figures/board.png differ diff --git a/bsp/stm32/stm32f407-armfly-v5/project.ewd b/bsp/stm32/stm32f407-armfly-v5/project.ewd new file mode 100644 index 0000000000..e94c83ed06 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/project.ewd @@ -0,0 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$PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rtc.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rtc_ex.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sai.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sai_ex.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sd.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sdram.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_smartcard.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spdifrx.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spi.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sram.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_usart.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_wwdg.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_fmc.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_fsmc.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_sdmmc.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_usb.c + + + diff --git a/bsp/stm32/stm32f407-armfly-v5/project.eww b/bsp/stm32/stm32f407-armfly-v5/project.eww new file mode 100644 index 0000000000..c2cb02eb1e --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\project.ewp + + + + + diff --git a/bsp/stm32/stm32f407-armfly-v5/project.uvopt b/bsp/stm32/stm32f407-armfly-v5/project.uvopt new file mode 100644 index 0000000000..b53d69d5df --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/project.uvopt @@ -0,0 +1,162 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 25000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 6 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U30000299 -O207 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 + + + 0 + UL2CM3 + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + diff --git a/bsp/stm32/stm32f407-armfly-v5/project.uvoptx b/bsp/stm32/stm32f407-armfly-v5/project.uvoptx new file mode 100644 index 0000000000..f8c4606a9e --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/project.uvoptx @@ -0,0 +1,191 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024.FLM -FS08000000 -FL0100000 -FP0($$Device:STM32F407ZGTx$CMSIS\Flash\STM32F4xx_1024.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407ZGTx$CMSIS\Flash\STM32F4xx_1024.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 2 + 10000000 + + + + + + Source Group 1 + 0 + 0 + 0 + 0 + + + diff --git a/bsp/stm32/stm32f407-armfly-v5/project.uvproj b/bsp/stm32/stm32f407-armfly-v5/project.uvproj new file mode 100644 index 0000000000..a2c80e0594 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/project.uvproj @@ -0,0 +1,1189 @@ + + + 1.1 +
### uVision Project, (C) Keil Software
+ + + rt-thread + 0x4 + ARM-ADS + + + STM32F407ZG + STMicroelectronics + IRAM(0x20000000-0x2001FFFF) IRAM2(0x10000000-0x1000FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(25000000) CPUTYPE("Cortex-M4") FPU2 + + "Startup\ST\STM32F4xx\startup_stm32f40_41xxx.s" ("STM32F40/41xxx Startup Code") + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000) + 6105 + stm32f4xx.h + + + + + + + -DSTM32F40_41xxx + + + SFD\ST\STM32F4xx\STM32F40x.sfr + 0 + 0 + + + + ST\STM32F4xx\ + ST\STM32F4xx\ + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU -REMAP + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 0 + + 0 + 6 + + + + + + + + + + + + + + Segger\JL2CM3.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 1 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + + + USE_HAL_DRIVER, STM32F407xx + + applications;.;board;board\CubeMX_Config\Inc;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\include;..\..\..\libcpu\arm\cortex-m4;..\..\..\libcpu\arm\common;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Inc;..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Include;..\libraries\STM32F4xx_HAL\CMSIS\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + Drivers + + + board.c + 1 + board\board.c + + + + + stm32f4xx_hal_msp.c + 1 + board\CubeMX_Config\Src\stm32f4xx_hal_msp.c + + + + + startup_stm32f407xx.s + 2 + ..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Source\Templates\arm\startup_stm32f407xx.s + + + + + drv_gpio.c + 1 + ..\libraries\HAL_Drivers\drv_gpio.c + + + + + drv_usart.c + 1 + ..\libraries\HAL_Drivers\drv_usart.c + + + + + drv_common.c + 1 + ..\libraries\HAL_Drivers\drv_common.c + + + + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + + + components.c + 1 + ..\..\..\src\components.c + + + + + device.c + 1 + ..\..\..\src\device.c + + + + + idle.c + 1 + ..\..\..\src\idle.c + + + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + + + irq.c + 1 + ..\..\..\src\irq.c + + + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + + + mem.c + 1 + ..\..\..\src\mem.c + + + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + + + object.c + 1 + ..\..\..\src\object.c + + + + + scheduler.c + 1 + ..\..\..\src\scheduler.c + + + + + signal.c + 1 + ..\..\..\src\signal.c + + + + + thread.c + 1 + ..\..\..\src\thread.c + + + + + timer.c + 1 + ..\..\..\src\timer.c + + + + + CORTEX-M4 + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m4\cpuport.c + + + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m4\context_rvds.S + + + + + backtrace.c + 1 + ..\..\..\libcpu\arm\common\backtrace.c + + + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + + + DeviceDrivers + + + pin.c + 1 + ..\..\..\components\drivers\misc\pin.c + + + + + serial.c + 1 + ..\..\..\components\drivers\serial\serial.c + + + + + completion.c + 1 + ..\..\..\components\drivers\src\completion.c + + + + + dataqueue.c + 1 + ..\..\..\components\drivers\src\dataqueue.c + + + + + pipe.c + 1 + ..\..\..\components\drivers\src\pipe.c + + + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\src\ringblk_buf.c + + + + + ringbuffer.c + 1 + ..\..\..\components\drivers\src\ringbuffer.c + + + + + waitqueue.c + 1 + ..\..\..\components\drivers\src\waitqueue.c + + + + + workqueue.c + 1 + ..\..\..\components\drivers\src\workqueue.c + + + + + finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + + + symbol.c + 1 + ..\..\..\components\finsh\symbol.c + + + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + + + msh_cmd.c + 1 + ..\..\..\components\finsh\msh_cmd.c + + + + + msh_file.c + 1 + ..\..\..\components\finsh\msh_file.c + + + + + STM32_HAL + + + system_stm32f4xx.c + 1 + ..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c + + + + + stm32f4xx_hal.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c + + + + + stm32f4xx_hal_adc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_adc.c + + + + + stm32f4xx_hal_adc_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_adc_ex.c + + + + + stm32f4xx_hal_can.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_can.c + + + + + stm32f4xx_hal_cec.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cec.c + + + + + stm32f4xx_hal_cortex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c + + + + + stm32f4xx_hal_crc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_crc.c + + + + + stm32f4xx_hal_cryp.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp.c + + + + + stm32f4xx_hal_cryp_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp_ex.c + + + + + stm32f4xx_hal_dac.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dac.c + + + + + stm32f4xx_hal_dac_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dac_ex.c + + + + + stm32f4xx_hal_dcmi.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dcmi.c + + + + + stm32f4xx_hal_dcmi_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dcmi_ex.c + + + + + stm32f4xx_hal_dfsdm.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dfsdm.c + + + + + stm32f4xx_hal_dma.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c + + + + + stm32f4xx_hal_dma2d.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma2d.c + + + + + stm32f4xx_hal_dma_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c + + + + + stm32f4xx_hal_dsi.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dsi.c + + + + + stm32f4xx_hal_eth.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_eth.c + + + + + stm32f4xx_hal_flash.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c + + + + + stm32f4xx_hal_flash_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c + + + + + stm32f4xx_hal_flash_ramfunc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c + + + + + stm32f4xx_hal_fmpi2c.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_fmpi2c.c + + + + + stm32f4xx_hal_fmpi2c_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_fmpi2c_ex.c + + + + + stm32f4xx_hal_gpio.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c + + + + + stm32f4xx_hal_hash.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_hash.c + + + + + stm32f4xx_hal_hash_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_hash_ex.c + + + + + stm32f4xx_hal_hcd.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_hcd.c + + + + + stm32f4xx_hal_i2c.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c.c + + + + + stm32f4xx_hal_i2c_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c_ex.c + + + + + stm32f4xx_hal_i2s.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2s.c + + + + + stm32f4xx_hal_i2s_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2s_ex.c + + + + + stm32f4xx_hal_irda.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_irda.c + + + + + stm32f4xx_hal_iwdg.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_iwdg.c + + + + + stm32f4xx_hal_lptim.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_lptim.c + + + + + stm32f4xx_hal_ltdc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_ltdc.c + + + + + stm32f4xx_hal_ltdc_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_ltdc_ex.c + + + + + stm32f4xx_hal_nand.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_nand.c + + + + + stm32f4xx_hal_nor.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_nor.c + + + + + stm32f4xx_hal_pccard.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pccard.c + + + + + stm32f4xx_hal_pcd.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pcd.c + + + + + stm32f4xx_hal_pcd_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pcd_ex.c + + + + + stm32f4xx_hal_pwr.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c + + + + + stm32f4xx_hal_pwr_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c + + + + + stm32f4xx_hal_qspi.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_qspi.c + + + + + stm32f4xx_hal_rcc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c + + + + + stm32f4xx_hal_rcc_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c + + + + + stm32f4xx_hal_rng.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rng.c + + + + + stm32f4xx_hal_rtc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rtc.c + + + + + stm32f4xx_hal_rtc_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rtc_ex.c + + + + + stm32f4xx_hal_sai.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sai.c + + + + + stm32f4xx_hal_sai_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sai_ex.c + + + + + stm32f4xx_hal_sd.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sd.c + + + + + stm32f4xx_hal_sdram.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sdram.c + + + + + stm32f4xx_hal_smartcard.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_smartcard.c + + + + + stm32f4xx_hal_spdifrx.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spdifrx.c + + + + + stm32f4xx_hal_spi.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spi.c + + + + + stm32f4xx_hal_sram.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sram.c + + + + + stm32f4xx_hal_tim.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c + + + + + stm32f4xx_hal_tim_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c + + + + + stm32f4xx_hal_uart.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c + + + + + stm32f4xx_hal_usart.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_usart.c + + + + + stm32f4xx_hal_wwdg.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_wwdg.c + + + + + stm32f4xx_ll_fmc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_fmc.c + + + + + stm32f4xx_ll_fsmc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_fsmc.c + + + + + stm32f4xx_ll_sdmmc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_sdmmc.c + + + + + stm32f4xx_ll_usb.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_usb.c + + + + + + + diff --git a/bsp/stm32/stm32f407-armfly-v5/project.uvprojx b/bsp/stm32/stm32f407-armfly-v5/project.uvprojx new file mode 100644 index 0000000000..793a467224 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/project.uvprojx @@ -0,0 +1,753 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + STM32F407IGTx + STMicroelectronics + Keil.STM32F4xx_DFP.2.14.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IRAM2(0x10000000,0x00010000) IROM(0x08000000,0x00100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407IGTx$CMSIS\Flash\STM32F4xx_1024.FLM)) + 0 + $$Device:STM32F407IGTx$Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h + + + + + + + + + + $$Device:STM32F407IGTx$CMSIS\SVD\STM32F40x.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4101 + + 1 + STLink\ST-LINKIII-KEIL_SWO.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + USE_HAL_DRIVER, STM32F407xx + + .;..\..\..\include;applications;.;board;board\CubeMX_Config\Inc;board\ports;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\common;..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Inc;..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Include;..\libraries\STM32F4xx_HAL\CMSIS\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + components.c + 1 + ..\..\..\src\components.c + + + device.c + 1 + ..\..\..\src\device.c + + + idle.c + 1 + ..\..\..\src\idle.c + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + irq.c + 1 + ..\..\..\src\irq.c + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + mem.c + 1 + ..\..\..\src\mem.c + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + object.c + 1 + ..\..\..\src\object.c + + + scheduler.c + 1 + ..\..\..\src\scheduler.c + + + signal.c + 1 + ..\..\..\src\signal.c + + + thread.c + 1 + ..\..\..\src\thread.c + + + timer.c + 1 + ..\..\..\src\timer.c + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + Drivers + + + board.c + 1 + board\board.c + + + stm32f4xx_hal_msp.c + 1 + board\CubeMX_Config\Src\stm32f4xx_hal_msp.c + + + startup_stm32f407xx.s + 2 + ..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Source\Templates\arm\startup_stm32f407xx.s + + + drv_gpio.c + 1 + ..\libraries\HAL_Drivers\drv_gpio.c + + + drv_usart.c + 1 + ..\libraries\HAL_Drivers\drv_usart.c + + + drv_hwtimer.c + 1 + ..\libraries\HAL_Drivers\drv_hwtimer.c + + + drv_common.c + 1 + ..\libraries\HAL_Drivers\drv_common.c + + + + + cpu + + + backtrace.c + 1 + ..\..\..\libcpu\arm\common\backtrace.c + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m4\cpuport.c + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m4\context_rvds.S + + + + + DeviceDrivers + + + hwtimer.c + 1 + ..\..\..\components\drivers\hwtimer\hwtimer.c + + + pin.c + 1 + ..\..\..\components\drivers\misc\pin.c + + + serial.c + 1 + ..\..\..\components\drivers\serial\serial.c + + + completion.c + 1 + ..\..\..\components\drivers\src\completion.c + + + dataqueue.c + 1 + ..\..\..\components\drivers\src\dataqueue.c + + + pipe.c + 1 + ..\..\..\components\drivers\src\pipe.c + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\src\ringblk_buf.c + + + ringbuffer.c + 1 + ..\..\..\components\drivers\src\ringbuffer.c + + + waitqueue.c + 1 + ..\..\..\components\drivers\src\waitqueue.c + + + workqueue.c + 1 + ..\..\..\components\drivers\src\workqueue.c + + + + + finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + + + libc + + + time.c + 1 + ..\..\..\components\libc\compilers\common\time.c + + + + + STM32_HAL + + + system_stm32f4xx.c + 1 + ..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c + + + stm32f4xx_hal.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c + + + stm32f4xx_hal_cec.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cec.c + + + stm32f4xx_hal_cortex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c + + + stm32f4xx_hal_crc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_crc.c + + + stm32f4xx_hal_cryp.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp.c + + + stm32f4xx_hal_cryp_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp_ex.c + + + stm32f4xx_hal_dma.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c + + + stm32f4xx_hal_dma_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c + + + stm32f4xx_hal_pwr.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c + + + stm32f4xx_hal_pwr_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c + + + stm32f4xx_hal_rcc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c + + + stm32f4xx_hal_rcc_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c + + + stm32f4xx_hal_rng.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rng.c + + + stm32f4xx_hal_gpio.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c + + + stm32f4xx_hal_uart.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c + + + stm32f4xx_hal_usart.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_usart.c + + + stm32f4xx_hal_tim.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c + + + stm32f4xx_hal_tim_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c + + + stm32f4xx_hal_lptim.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_lptim.c + + + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/bsp/stm32/stm32f407-armfly-v5/rtconfig.h b/bsp/stm32/stm32f407-armfly-v5/rtconfig.h new file mode 100644 index 0000000000..7d83eb4f99 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/rtconfig.h @@ -0,0 +1,173 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_DEBUG +#define RT_DEBUG_COLOR + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x40000 +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M4 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_USING_MSH_ONLY +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA +#define RT_USING_PIN + +/* Using WiFi */ + + +/* Using USB */ + + +/* POSIX layer and C standard library */ + + +/* Network */ + +/* Socket abstraction layer */ + + +/* light weight TCP/IP stack */ + + +/* Modbus master and slave stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* ARM CMSIS */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* peripheral libraries and drivers */ + + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + +#define SOC_FAMILY_STM32 +#define SOC_SERIES_STM32F4 + +/* Hardware Drivers Config */ + +#define SOC_STM32F407ZG + +/* Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART1 + +/* Board extended module Drivers */ + + +#endif diff --git a/bsp/stm32/stm32f407-armfly-v5/rtconfig.py b/bsp/stm32/stm32f407-armfly-v5/rtconfig.py new file mode 100644 index 0000000000..00d5d737ac --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/rtconfig.py @@ -0,0 +1,150 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv4_sp' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu VFPv4_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/stm32/stm32f407-armfly-v5/template.ewp b/bsp/stm32/stm32f407-armfly-v5/template.ewp new file mode 100644 index 0000000000..21c66ca0d0 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/template.ewp @@ -0,0 +1,2031 @@ + + + 3 + + rt-thread + + ARM + + 1 + + General + 3 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 20 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 20 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + diff --git a/bsp/stm32/stm32f407-armfly-v5/template.eww b/bsp/stm32/stm32f407-armfly-v5/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/stm32/stm32f407-armfly-v5/template.uvopt b/bsp/stm32/stm32f407-armfly-v5/template.uvopt new file mode 100644 index 0000000000..5cc5956b4f --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/template.uvopt @@ -0,0 +1,199 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 25000000 + + 1 + 1 + 1 + 0 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 255 + + + 0 + Datasheet + DATASHTS\ST\STM32F4xx\DM00037051.pdf + + + 1 + Reference Manual + DATASHTS\ST\STM32F4xx\DM00031020.pdf + + + 2 + Technical Reference Manual + datashts\arm\cortex_m4\r0p1\DDI0439C_CORTEX_M4_R0P1_TRM.PDF + + + 3 + Generic User Guide + datashts\arm\cortex_m4\r0p1\DUI0553A_CORTEX_M4_DGUG.PDF + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + UL2CM3 + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000) + + + 0 + JL2CM3 + -U30000299 -O207 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + diff --git a/bsp/stm32/stm32f407-armfly-v5/template.uvoptx b/bsp/stm32/stm32f407-armfly-v5/template.uvoptx new file mode 100644 index 0000000000..904af41f77 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/template.uvoptx @@ -0,0 +1,187 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 24000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0STM32F4xx_1024 -FL0100000 -FS08000000 -FP0($$Device:STM32F407IGTx$CMSIS\Flash\STM32F4xx_1024.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 10000000 + + + + + + Source Group 1 + 0 + 0 + 0 + 0 + + + diff --git a/bsp/stm32/stm32f407-armfly-v5/template.uvproj b/bsp/stm32/stm32f407-armfly-v5/template.uvproj new file mode 100644 index 0000000000..73d0b32956 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/template.uvproj @@ -0,0 +1,438 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 0 + + + STM32F407IG + STMicroelectronics + IRAM(0x20000000-0x2001FFFF) IRAM2(0x10000000-0x1000FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(25000000) CPUTYPE("Cortex-M4") FPU2 + + "Startup\ST\STM32F4xx\startup_stm32f40_41xxx.s" ("STM32F40/41xxx Startup Code") + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000) + 6104 + stm32f4xx.h + + + + + + + -DSTM32F40_41xxx + + + SFD\ST\STM32F4xx\STM32F40x.sfr + 0 + 0 + + + + ST\STM32F4xx\ + ST\STM32F4xx\ + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU -REMAP + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + + 0 + 6 + + + + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4101 + + 1 + STLink\ST-LINKIII-KEIL_SWO.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/bsp/stm32/stm32f407-armfly-v5/template.uvprojx b/bsp/stm32/stm32f407-armfly-v5/template.uvprojx new file mode 100644 index 0000000000..4c3ec18c73 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/template.uvprojx @@ -0,0 +1,411 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + STM32F407IGTx + STMicroelectronics + Keil.STM32F4xx_DFP.2.14.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IRAM2(0x10000000,0x00010000) IROM(0x08000000,0x00100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407IGTx$CMSIS\Flash\STM32F4xx_1024.FLM)) + 0 + $$Device:STM32F407IGTx$Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h + + + + + + + + + + $$Device:STM32F407IGTx$CMSIS\SVD\STM32F40x.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4101 + + 1 + STLink\ST-LINKIII-KEIL_SWO.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Source Group 1 + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/CubeMX_Config.ioc index 02fb59d94c..8115bf0687 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/CubeMX_Config.ioc @@ -136,6 +136,12 @@ NVIC.USART1_IRQn=true\:0\:0\:false\:false\:true\:true\:true NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false PA1.Mode=RMII PA1.Signal=ETH_REF_CLK +PA9.GPIOParameters=GPIO_PuPd +PA9.GPIO_PuPd=GPIO_PULLUP +PA9.Mode=Asynchronous +PA9.Signal=USART1_TX +PA10.GPIOParameters=GPIO_PuPd +PA10.GPIO_PuPd=GPIO_PULLUP PA10.Mode=Asynchronous PA10.Signal=USART1_RX PA11.Mode=Device_Only @@ -154,10 +160,12 @@ PA5.Locked=true PA5.Signal=COMP_DAC2_group PA7.Mode=RMII PA7.Signal=ETH_CRS_DV -PA9.Mode=Asynchronous -PA9.Signal=USART1_TX +PB10.GPIOParameters=GPIO_PuPd +PB10.GPIO_PuPd=GPIO_PULLUP PB10.Mode=Asynchronous PB10.Signal=USART3_TX +PB11.GPIOParameters=GPIO_PuPd +PB11.GPIO_PuPd=GPIO_PULLUP PB11.Mode=Asynchronous PB11.Signal=USART3_RX PB13.Mode=Full_Duplex_Master diff --git a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c index 08cc9f847e..34dd1ba7c7 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c +++ b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c @@ -2,12 +2,12 @@ /** ****************************************************************************** * File Name : stm32f4xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** ** This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether + * USER CODE END. Other portions of this file, whether * inserted by the user or by software development tools * are owned by their respective copyright owners. * @@ -52,7 +52,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -741,7 +741,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) */ GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF7_USART1; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); @@ -768,7 +768,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) */ GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF7_USART3; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); diff --git a/bsp/stm32/stm32f407-robomaster-c/.config b/bsp/stm32/stm32f407-robomaster-c/.config new file mode 100644 index 0000000000..4d8ccbfd5d --- /dev/null +++ b/bsp/stm32/stm32f407-robomaster-c/.config @@ -0,0 +1,564 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x40004 +CONFIG_ARCH_ARM=y +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M4=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +CONFIG_FINSH_USING_MSH_ONLY=y +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +# CONFIG_RT_USING_DFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +# CONFIG_RT_USING_LIBC is not set +# CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_LIBC_USING_TIME=y +CONFIG_RT_LIBC_FIXED_TIMEZONE=8 + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_LWP is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set +CONFIG_SOC_FAMILY_STM32=y +CONFIG_SOC_SERIES_STM32F4=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_STM32F407IG=y + +# +# Onboard Peripheral Drivers +# + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART1=y +# CONFIG_BSP_UART1_RX_USING_DMA is not set +# CONFIG_BSP_USING_RNG is not set +# CONFIG_BSP_USING_UDID is not set + +# +# Board extended module Drivers +# diff --git a/bsp/stm32/stm32f407-robomaster-c/.gitignore b/bsp/stm32/stm32f407-robomaster-c/.gitignore new file mode 100644 index 0000000000..7221bde019 --- /dev/null +++ b/bsp/stm32/stm32f407-robomaster-c/.gitignore @@ -0,0 +1,42 @@ +*.pyc +*.map +*.dblite +*.elf +*.bin +*.hex +*.axf +*.exe +*.pdb +*.idb +*.ilk +*.old +build +Debug +documentation/html +packages/ +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +.DS_Stor* +.config 3 +.config 4 +.config 5 +Midea-X1 +*.uimg +GPATH +GRTAGS +GTAGS +.vscode +JLinkLog.txt +JLinkSettings.ini +DebugConfig/ +RTE/ +settings/ +*.uvguix* +cconfig.h diff --git a/bsp/stm32/stm32f407-robomaster-c/Kconfig b/bsp/stm32/stm32f407-robomaster-c/Kconfig new file mode 100644 index 0000000000..8cbc7b71a8 --- /dev/null +++ b/bsp/stm32/stm32f407-robomaster-c/Kconfig @@ -0,0 +1,21 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "../libraries/Kconfig" +source "board/Kconfig" diff --git a/bsp/stm32/stm32f407-robomaster-c/README.md b/bsp/stm32/stm32f407-robomaster-c/README.md new file mode 100644 index 0000000000..c4f2eceb48 --- /dev/null +++ b/bsp/stm32/stm32f407-robomaster-c/README.md @@ -0,0 +1,120 @@ +# STM32F407 Robomaster 开发板C型 BSP 说明 + +## 简介 + +本文档为 STM32F407 Robomaster 开发板C型 的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +Robomaster 开发板C型 是大疆创新科技有限公司推出的一款基于 ARM Cortex-M4 内核的开发板。开发板主控芯片为 STM32F407IGH6TR，最高主频为 168Mhz，拥有丰富的扩展接口和通信接口。板载IMU传感器，可配合RoboMaster出品的M3508、 M2006直流无刷减速电机、UWB模块以及妙算等产品使用，亦可配合DJI飞控SDK使用。 + +开发板外观如下图所示： + +image-20210630111114846 + +> 开发板 C 型具有如下外设： + +该开发板常用 **板载资源** 如下： + +- MCU: STM32F407IGH6TR, 168MHz Freq, 1024KB FLASH, 192KB RAM(含64KB CCM RAM)。 +- 调试接口：SWD +- 常用外设：用户自定义 LED、按键、蜂鸣器、六轴惯性测量单元和磁力计、电压检测 ADC。 +- 常用接口：5V 接口、BOOT 配置接口、micro USB 接口、可配置 I/O 接口、UART 接口、CAN 总线接口、PWM 接口、DBUS接口、数字摄像头 FPC 接口。 + +开发板的用户手册：[RoboMaster 开发板 C 型用户手册.pdf](https://rm-static.djicdn.com/tem/35228/RoboMaster%20%20%E5%BC%80%E5%8F%91%E6%9D%BF%20C%20%E5%9E%8B%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C.pdf) + +开发板更多详细信息请参考 RoboMaster官网：[RoboMaster开发板 C 型](https://www.robomaster.com/zh-CN/products/components/general/development-board-type-c/info) + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :----------- | :----------: | :----------------------------------- | +| BMI088 | 暂不支持 | 六轴惯性测量单元（有软件包） | +| IST8310 | 暂不支持 | 三轴磁力计 | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | PA0, PA1... PH1 ---> PIN: 0, 1...144 | +| UART | 支持 | UART1, UART3(DBUS), UART6 | +| CAN | 下阶段支持 | CAN1, CAN2 | +| PWM | 下阶段支持 | | +| SPI | 下阶段支持 | BMI088, 用户SPI接口 | +| I2C | 下阶段支持 | IST8310, 用户 I2C 接口 | +| USB | 暂不支持 | | +| **扩展模块** | **支持情况** | **备注** | +| 无 | | | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用[ENV 工具](https://docs.rt-thread.org/#/development-tools/env/env)对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +将准备好的 ST-Link/JLink/DapLink 与开发板连接，开发板上的调试接口为 MX1.25 4Pin。C板上没有电源指示灯，供电可以选用：调试接口的 3.3V 输入，micro USB 接口供电，XT30 电源输入。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 ST-LINK 下载程序，点击下载按钮即可下载程序到开发板。 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，LED 会以蓝光进行周期性闪烁。 + +此 BSP 的 FinSH 默认使用串口 1 (C板外壳上标有UART2的4Pin接口)，在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.4 build Jun 30 2021 + 2006 - 2021 Copyright by rt-thread team +msh > +``` +> 终端工具推荐使用 [MobaXterm](https://mobaxterm.mobatek.net/) 或 [Xshell](https://www.netsarang.com/en/free-for-home-school/)，均有免费的个人版本 + +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口 2 的功能，更多高级功能需要利用 ENV 工具对 BSP 进行配置，步骤如下： + +1. 在 BSP 下打开 env 工具。 + +2. 输入 `menuconfig` 命令配置工程，配置好之后保存退出。 + +3. 输入 `pkgs --update` 命令更新软件包。 + +4. 输入 `scons --target=mdk4/mdk5/iar` 命令重新生成工程。 + +本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32 系列 BSP 外设驱动使用教程. md)。 + +## 注意事项 + +- 部分外设需通过 XT30 或 USB 接口供电才能正常使用，包括 CAN、舵机5V供电、IMU恒温电路等 +- 目前 scons 支持生成 cmake 配置文件，可以使用 CLion 进行 C板 的程序开发，推荐同学们尝试。详细步骤可参见：[在 Clion 中调试 rt-thread 工程](https://club.rt-thread.org/ask/article/2840.html)，C板的 openOCD 配置文件推荐选用 `stm32f4discovery.cfg` ，并将该配置文件的最后一行改为 `reset_config none` + +## 联系人信息 + +维护人: + +- [crazt](https://github.com/CraztTnspt) ，邮箱： \ No newline at end of file diff --git a/bsp/stm32/stm32f407-robomaster-c/SConscript b/bsp/stm32/stm32f407-robomaster-c/SConscript new file mode 100644 index 0000000000..20f7689c53 --- /dev/null +++ b/bsp/stm32/stm32f407-robomaster-c/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/stm32/stm32f407-robomaster-c/SConstruct b/bsp/stm32/stm32f407-robomaster-c/SConstruct new file mode 100644 index 0000000000..945cb55a52 --- /dev/null +++ b/bsp/stm32/stm32f407-robomaster-c/SConstruct @@ -0,0 +1,60 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rt-thread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +stm32_library = 'STM32F4xx_HAL' +rtconfig.BSP_LIBRARY_TYPE = stm32_library + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, stm32_library, 'SConscript'))) + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/stm32/stm32f407-robomaster-c/applications/SConscript b/bsp/stm32/stm32f407-robomaster-c/applications/SConscript new file mode 100644 index 0000000000..1381e63e13 --- /dev/null +++ b/bsp/stm32/stm32f407-robomaster-c/applications/SConscript @@ -0,0 +1,10 @@ +import rtconfig +from building import * + +cwd = GetCurrentDir() +CPPPATH = [cwd, str(Dir('#'))] +src = Glob('*.c') + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/stm32/stm32f407-robomaster-c/applications/main.c b/bsp/stm32/stm32f407-robomaster-c/applications/main.c new file mode 100644 index 0000000000..a4e03550f6 --- /dev/null +++ b/bsp/stm32/stm32f407-robomaster-c/applications/main.c @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-06 SummerGift first version + * 2021-06-30 crazt modify for robomaster C board + */ + +#include +#include +#include + +/* defined the LED Blue pin: PB1 */ +#define LED_B_PIN GET_PIN(H, 10) + +int main(void) +{ + int count = 1; + /* set LED Blue pin mode to output */ + rt_pin_mode(LED_B_PIN, PIN_MODE_OUTPUT); + + while (count++) + { + rt_pin_write(LED_B_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED_B_PIN, PIN_LOW); + rt_thread_mdelay(500); + } + + return RT_EOK; +} diff --git a/bsp/stm32/stm32f407-robomaster-c/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32f407-robomaster-c/board/CubeMX_Config/.mxproject new file mode 100644 index 0000000000..98680a9f77 --- /dev/null +++ b/bsp/stm32/stm32f407-robomaster-c/board/CubeMX_Config/.mxproject @@ -0,0 +1,14 @@ +[PreviousLibFiles] +LibFiles=Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h; + +[PreviousUsedKeilFiles] +SourceFiles=..\Src\main.c;..\Src\stm32f4xx_it.c;..\Src\stm32f4xx_hal_msp.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;..\\Src/system_stm32f4xx.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;..\\Src/system_stm32f4xx.c;..\Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;; +HeaderPath=..\Drivers\STM32F4xx_HAL_Driver\Inc;..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F4xx\Include;..\Drivers\CMSIS\Include;..\Inc; +CDefines=USE_HAL_DRIVER;STM32F407xx;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[PreviousGenFiles] +HeaderPath=C:/CraztDoc/RTT/github_repo/rt-thread/bsp/stm32/stm32f407-robomaster-c/board/CubeMX_Config/Inc +HeaderFiles=stm32f4xx_it.h;stm32f4xx_hal_conf.h;main.h; +SourcePath=C:/CraztDoc/RTT/github_repo/rt-thread/bsp/stm32/stm32f407-robomaster-c/board/CubeMX_Config/Src +SourceFiles=stm32f4xx_it.c;stm32f4xx_hal_msp.c;main.c; + diff --git a/bsp/stm32/stm32f407-robomaster-c/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f407-robomaster-c/board/CubeMX_Config/CubeMX_Config.ioc new file mode 100644 index 0000000000..f7c753af0a --- /dev/null +++ b/bsp/stm32/stm32f407-robomaster-c/board/CubeMX_Config/CubeMX_Config.ioc @@ -0,0 +1,120 @@ +#MicroXplorer Configuration settings - do not modify +File.Version=6 +GPIO.groupedBy= +KeepUserPlacement=false +Mcu.Family=STM32F4 +Mcu.IP0=NVIC +Mcu.IP1=RCC +Mcu.IP2=SYS +Mcu.IP3=USART1 +Mcu.IPNb=4 +Mcu.Name=STM32F407I(E-G)Hx +Mcu.Package=UFBGA176 +Mcu.Pin0=PA14 +Mcu.Pin1=PA13 +Mcu.Pin2=PB7 +Mcu.Pin3=PA9 +Mcu.Pin4=PH0-OSC_IN +Mcu.Pin5=PH1-OSC_OUT +Mcu.Pin6=VP_SYS_VS_Systick +Mcu.PinsNb=7 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32F407IGHx +MxCube.Version=6.1.2 +MxDb.Version=DB.6.0.10 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +PA13.Mode=Serial_Wire +PA13.Signal=SYS_JTMS-SWDIO +PA14.Mode=Serial_Wire +PA14.Signal=SYS_JTCK-SWCLK +PA9.GPIOParameters=GPIO_PuPd +PA9.GPIO_PuPd=GPIO_PULLUP +PA9.Mode=Asynchronous +PA9.Signal=USART1_TX +PB7.GPIOParameters=GPIO_PuPd +PB7.GPIO_PuPd=GPIO_PULLUP +PB7.Mode=Asynchronous +PB7.Signal=USART1_RX +PH0-OSC_IN.Mode=HSE-External-Oscillator +PH0-OSC_IN.Signal=RCC_OSC_IN +PH1-OSC_OUT.Mode=HSE-External-Oscillator +PH1-OSC_OUT.Signal=RCC_OSC_OUT +PinOutPanel.CurrentBGAView=Top +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=false +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32F407IGHx +ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.25.2 +ProjectManager.FreePins=false +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=0 +ProjectManager.MainLocation=Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=CubeMX_Config.ioc +ProjectManager.ProjectName=CubeMX_Config +ProjectManager.RegisterCallBack= +ProjectManager.StackSize=0x400 +ProjectManager.TargetToolchain=MDK-ARM V5 +ProjectManager.ToolChainLocation= +ProjectManager.UnderRoot=false +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false +RCC.48MHZClocksFreq_Value=84000000 +RCC.AHBFreq_Value=168000000 +RCC.APB1CLKDivider=RCC_HCLK_DIV4 +RCC.APB1Freq_Value=42000000 +RCC.APB1TimFreq_Value=84000000 +RCC.APB2CLKDivider=RCC_HCLK_DIV2 +RCC.APB2Freq_Value=84000000 +RCC.APB2TimFreq_Value=168000000 +RCC.CortexFreq_Value=168000000 +RCC.EthernetFreq_Value=168000000 +RCC.FCLKCortexFreq_Value=168000000 +RCC.FamilyName=M +RCC.HCLKFreq_Value=168000000 +RCC.HSE_VALUE=12000000 +RCC.HSI_VALUE=16000000 +RCC.I2SClocksFreq_Value=192000000 +RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSE_VALUE,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQCLKFreq_Value,PLLSourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VcooutputI2S +RCC.LSE_VALUE=32768 +RCC.LSI_VALUE=32000 +RCC.MCO2PinFreq_Value=168000000 +RCC.PLLCLKFreq_Value=168000000 +RCC.PLLM=6 +RCC.PLLN=168 +RCC.PLLQCLKFreq_Value=84000000 +RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE +RCC.RTCFreq_Value=32000 +RCC.RTCHSEDivFreq_Value=6000000 +RCC.SYSCLKFreq_VALUE=168000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +RCC.VCOI2SOutputFreq_Value=384000000 +RCC.VCOInputFreq_Value=2000000 +RCC.VCOOutputFreq_Value=336000000 +RCC.VcooutputI2S=192000000 +USART1.IPParameters=VirtualMode +USART1.VirtualMode=VM_ASYNC +VP_SYS_VS_Systick.Mode=SysTick +VP_SYS_VS_Systick.Signal=SYS_VS_Systick +board=custom diff --git a/bsp/stm32/stm32f407-robomaster-c/board/CubeMX_Config/Inc/main.h b/bsp/stm32/stm32f407-robomaster-c/board/CubeMX_Config/Inc/main.h new file mode 100644 index 0000000000..b905d54bd5 --- /dev/null +++ b/bsp/stm32/stm32f407-robomaster-c/board/CubeMX_Config/Inc/main.h @@ -0,0 +1,71 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f407-robomaster-c/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h b/bsp/stm32/stm32f407-robomaster-c/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h new file mode 100644 index 0000000000..5986f8f9c9 --- /dev/null +++ b/bsp/stm32/stm32f407-robomaster-c/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h @@ -0,0 +1,486 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_conf_template.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32f4xx_hal_conf.h. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_CONF_H +#define __STM32F4xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED + + /* #define HAL_ADC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_CAN_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_DAC_MODULE_ENABLED */ +/* #define HAL_DCMI_MODULE_ENABLED */ +/* #define HAL_DMA2D_MODULE_ENABLED */ +/* #define HAL_ETH_MODULE_ENABLED */ +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_PCCARD_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +/* #define HAL_SDRAM_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ +/* #define HAL_I2C_MODULE_ENABLED */ +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_LTDC_MODULE_ENABLED */ +/* #define HAL_RNG_MODULE_ENABLED */ +/* #define HAL_RTC_MODULE_ENABLED */ +/* #define HAL_SAI_MODULE_ENABLED */ +/* #define HAL_SD_MODULE_ENABLED */ +/* #define HAL_MMC_MODULE_ENABLED */ +/* #define HAL_SPI_MODULE_ENABLED */ +/* #define HAL_TIM_MODULE_ENABLED */ +#define HAL_UART_MODULE_ENABLED +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +/* #define HAL_PCD_MODULE_ENABLED */ +/* #define HAL_HCD_MODULE_ENABLED */ +/* #define HAL_DSI_MODULE_ENABLED */ +/* #define HAL_QSPI_MODULE_ENABLED */ +/* #define HAL_QSPI_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_FMPI2C_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +/* #define HAL_DFSDM_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)12000000U) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the External audio frequency in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 1U +#define INSTRUCTION_CACHE_ENABLE 1U +#define DATA_CACHE_ENABLE 1U + +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ +#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ +#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ +#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ +#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */ +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ +#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ +#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ +#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2U +#define MAC_ADDR1 0U +#define MAC_ADDR2 0U +#define MAC_ADDR3 0U +#define MAC_ADDR4 0U +#define MAC_ADDR5 0U + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* DP83848_PHY_ADDRESS Address*/ +#define DP83848_PHY_ADDRESS 0x01U +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY ((uint32_t)0x000000FFU) +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) + +#define PHY_READ_TO ((uint32_t)0x0000FFFFU) +#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU) + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ +#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ + +#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f4xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f4xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32f4xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f4xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f4xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f4xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f4xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #include "stm32f4xx_hal_can_legacy.h" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f4xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32f4xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32f4xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f4xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32f4xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32f4xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f4xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32f4xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32f4xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_PCCARD_MODULE_ENABLED + #include "stm32f4xx_hal_pccard.h" +#endif /* HAL_PCCARD_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32f4xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f4xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32f4xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f4xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f4xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32f4xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f4xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32f4xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f4xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32f4xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32f4xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f4xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f4xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f4xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f4xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f4xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f4xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f4xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f4xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32f4xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32f4xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32f4xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32f4xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_FMPI2C_MODULE_ENABLED + #include "stm32f4xx_hal_fmpi2c.h" +#endif /* HAL_FMPI2C_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32f4xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32f4xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32f4xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32f4xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f407-robomaster-c/board/CubeMX_Config/Inc/stm32f4xx_it.h b/bsp/stm32/stm32f407-robomaster-c/board/CubeMX_Config/Inc/stm32f4xx_it.h new file mode 100644 index 0000000000..e80dbbd8c1 --- /dev/null +++ b/bsp/stm32/stm32f407-robomaster-c/board/CubeMX_Config/Inc/stm32f4xx_it.h @@ -0,0 +1,69 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f4xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_IT_H +#define __STM32F4xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f407-robomaster-c/board/CubeMX_Config/Src/main.c b/bsp/stm32/stm32f407-robomaster-c/board/CubeMX_Config/Src/main.c new file mode 100644 index 0000000000..3df243a8fa --- /dev/null +++ b/bsp/stm32/stm32f407-robomaster-c/board/CubeMX_Config/Src/main.c @@ -0,0 +1,233 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +UART_HandleTypeDef huart1; + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +static void MX_GPIO_Init(void); +static void MX_USART1_UART_Init(void); +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_USART1_UART_Init(); + /* USER CODE BEGIN 2 */ + + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + } + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 6; + RCC_OscInitStruct.PLL.PLLN = 168; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 4; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) + { + Error_Handler(); + } +} + +/** + * @brief USART1 Initialization Function + * @param None + * @retval None + */ +static void MX_USART1_UART_Init(void) +{ + + /* USER CODE BEGIN USART1_Init 0 */ + + /* USER CODE END USART1_Init 0 */ + + /* USER CODE BEGIN USART1_Init 1 */ + + /* USER CODE END USART1_Init 1 */ + huart1.Instance = USART1; + huart1.Init.BaudRate = 115200; + huart1.Init.WordLength = UART_WORDLENGTH_8B; + huart1.Init.StopBits = UART_STOPBITS_1; + huart1.Init.Parity = UART_PARITY_NONE; + huart1.Init.Mode = UART_MODE_TX_RX; + huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart1.Init.OverSampling = UART_OVERSAMPLING_16; + if (HAL_UART_Init(&huart1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART1_Init 2 */ + + /* USER CODE END USART1_Init 2 */ + +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + { + } + /* USER CODE END Error_Handler_Debug */ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f407-robomaster-c/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c b/bsp/stm32/stm32f407-robomaster-c/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c new file mode 100644 index 0000000000..f2ac99095c --- /dev/null +++ b/bsp/stm32/stm32f407-robomaster-c/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c @@ -0,0 +1,159 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f4xx_hal_msp.c + * @brief This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); + + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/** +* @brief UART MSP Initialization +* This function configures the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspInit(UART_HandleTypeDef* huart) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(huart->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspInit 0 */ + + /* USER CODE END USART1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_USART1_CLK_ENABLE(); + + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USART1 GPIO Configuration + PB7 ------> USART1_RX + PA9 ------> USART1_TX + */ + GPIO_InitStruct.Pin = GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART1; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN USART1_MspInit 1 */ + + /* USER CODE END USART1_MspInit 1 */ + } + +} + +/** +* @brief UART MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) +{ + if(huart->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspDeInit 0 */ + + /* USER CODE END USART1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART1_CLK_DISABLE(); + + /**USART1 GPIO Configuration + PB7 ------> USART1_RX + PA9 ------> USART1_TX + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_7); + + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9); + + /* USER CODE BEGIN USART1_MspDeInit 1 */ + + /* USER CODE END USART1_MspDeInit 1 */ + } + +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f407-robomaster-c/board/CubeMX_Config/Src/stm32f4xx_it.c b/bsp/stm32/stm32f407-robomaster-c/board/CubeMX_Config/Src/stm32f4xx_it.c new file mode 100644 index 0000000000..fe4ffc9dbf --- /dev/null +++ b/bsp/stm32/stm32f407-robomaster-c/board/CubeMX_Config/Src/stm32f4xx_it.c @@ -0,0 +1,205 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f4xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32f4xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ + +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M4 Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + { + } + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn 0 */ + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32F4xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32f4xx.s). */ +/******************************************************************************/ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f407-robomaster-c/board/CubeMX_Config/Src/system_stm32f4xx.c b/bsp/stm32/stm32f407-robomaster-c/board/CubeMX_Config/Src/system_stm32f4xx.c new file mode 100644 index 0000000000..449d1d9c0a --- /dev/null +++ b/bsp/stm32/stm32f407-robomaster-c/board/CubeMX_Config/Src/system_stm32f4xx.c @@ -0,0 +1,727 @@ +/** + ****************************************************************************** + * @file system_stm32f4xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f4xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx_system + * @{ + */ + +/** @addtogroup STM32F4xx_System_Private_Includes + * @{ + */ + + +#include "stm32f4xx.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ + || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) +/* #define DATA_IN_ExtSRAM */ +#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\ + STM32F412Zx || STM32F412Vx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +/* #define DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ + STM32F479xx */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +uint32_t SystemCoreClock = 16000000; +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes + * @{ + */ + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting, vector table location and External memory + * configuration. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value + * depends on the application requirements), user has to ensure that HSE_VALUE + * is same as the real frequency of the crystal used. Otherwise, this function + * may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f4xx.s before jump to main. + * This function configures the external memories (SRAM/SDRAM) + * This SRAM/SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + __IO uint32_t tmp = 0x00; + + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register __IO uint32_t index; + + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */ + RCC->AHB1ENR |= 0x000001F8; + + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0xCCCCCCCC; + GPIOF->AFR[1] = 0xCCCCCCCC; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0xCCCCCCCC; + GPIOG->AFR[1] = 0xCCCCCCCC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xAAAAAAAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0xAAAAAAAA; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x00000000; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00000000; + +/*-- FMC Configuration -------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + FMC_Bank5_6->SDCR[0] = 0x000019E4; + FMC_Bank5_6->SDTR[0] = 0x01115351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ + FMC_Bank5_6->SDCMR = 0x00000073; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ + FMC_Bank5_6->SDCMR = 0x00046014; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001011; + FMC_Bank1->BTCR[3] = 0x00000201; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#if defined(STM32F469xx) || defined(STM32F479xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001091; + FMC_Bank1->BTCR[3] = 0x00110212; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F469xx || STM32F479xx */ + + (void)(tmp); +} +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ +#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f4xx.s before jump to main. + * This function configures the external memories (SRAM/SDRAM) + * This SRAM/SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + __IO uint32_t tmp = 0x00; +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +#if defined (DATA_IN_ExtSDRAM) + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register __IO uint32_t index; + +#if defined(STM32F446xx) + /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface + clock */ + RCC->AHB1ENR |= 0x0000007D; +#else + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface + clock */ + RCC->AHB1ENR |= 0x000001F8; +#endif /* STM32F446xx */ + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); + +#if defined(STM32F446xx) + /* Connect PAx pins to FMC Alternate function */ + GPIOA->AFR[0] |= 0xC0000000; + GPIOA->AFR[1] |= 0x00000000; + /* Configure PDx pins in Alternate function mode */ + GPIOA->MODER |= 0x00008000; + /* Configure PDx pins speed to 50 MHz */ + GPIOA->OSPEEDR |= 0x00008000; + /* Configure PDx pins Output type to push-pull */ + GPIOA->OTYPER |= 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOA->PUPDR |= 0x00000000; + + /* Connect PCx pins to FMC Alternate function */ + GPIOC->AFR[0] |= 0x00CC0000; + GPIOC->AFR[1] |= 0x00000000; + /* Configure PDx pins in Alternate function mode */ + GPIOC->MODER |= 0x00000A00; + /* Configure PDx pins speed to 50 MHz */ + GPIOC->OSPEEDR |= 0x00000A00; + /* Configure PDx pins Output type to push-pull */ + GPIOC->OTYPER |= 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOC->PUPDR |= 0x00000000; +#endif /* STM32F446xx */ + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x000000CC; + GPIOD->AFR[1] = 0xCC000CCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xA02A000A; + /* Configure PDx pins speed to 50 MHz */ + GPIOD->OSPEEDR = 0xA02A000A; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00000CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA800A; + /* Configure PEx pins speed to 50 MHz */ + GPIOE->OSPEEDR = 0xAAAA800A; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0xCCCCCCCC; + GPIOF->AFR[1] = 0xCCCCCCCC; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0xCCCCCCCC; + GPIOG->AFR[1] = 0xCCCCCCCC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xAAAAAAAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0xAAAAAAAA; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x00000000; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00000000; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +/*-- FMC Configuration -------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + /* Configure and enable SDRAM bank1 */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCR[0] = 0x00001954; +#else + FMC_Bank5_6->SDCR[0] = 0x000019E4; +#endif /* STM32F446xx */ + FMC_Bank5_6->SDTR[0] = 0x01115351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCMR = 0x000000F3; +#else + FMC_Bank5_6->SDCMR = 0x00000073; +#endif /* STM32F446xx */ + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCMR = 0x00044014; +#else + FMC_Bank5_6->SDCMR = 0x00046014; +#endif /* STM32F446xx */ + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; +#if defined(STM32F446xx) + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1)); +#else + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); +#endif /* STM32F446xx */ + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); +#endif /* DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ + || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) + +#if defined(DATA_IN_ExtSRAM) +/*-- GPIOs Configuration -----------------------------------------------------*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR |= 0x00000078; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0x00CCCCCC; + GPIOF->AFR[1] = 0xCCCC0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA000AAA; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xFF000FFF; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0x00CCCCCC; + GPIOG->AFR[1] = 0x000000C0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00085AAA; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000CAFFF; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FMC/FSMC Configuration --------------------------------------------------*/ + /* Enable the FMC/FSMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001011; + FMC_Bank1->BTCR[3] = 0x00000201; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#if defined(STM32F469xx) || defined(STM32F479xx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001091; + FMC_Bank1->BTCR[3] = 0x00110212; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F469xx || STM32F479xx */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\ + || defined(STM32F412Zx) || defined(STM32F412Vx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN); + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001011; + FSMC_Bank1->BTCR[3] = 0x00000201; + FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */ + +#endif /* DATA_IN_ExtSRAM */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ + STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */ + (void)(tmp); +} +#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f407-robomaster-c/board/Kconfig b/bsp/stm32/stm32f407-robomaster-c/board/Kconfig new file mode 100644 index 0000000000..cf0200cbaa --- /dev/null +++ b/bsp/stm32/stm32f407-robomaster-c/board/Kconfig @@ -0,0 +1,44 @@ +menu "Hardware Drivers Config" + +config SOC_STM32F407IG + bool + select SOC_SERIES_STM32F4 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "Onboard Peripheral Drivers" + +endmenu + +menu "On-chip Peripheral Drivers" + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART1 + bool "Enable UART1" + default y + + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + endif + + source "../libraries/HAL_Drivers/Kconfig" + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/stm32/stm32f407-robomaster-c/board/SConscript b/bsp/stm32/stm32f407-robomaster-c/board/SConscript new file mode 100644 index 0000000000..091f29472a --- /dev/null +++ b/bsp/stm32/stm32f407-robomaster-c/board/SConscript @@ -0,0 +1,37 @@ +import os +import rtconfig +from building import * + +Import('SDK_LIB') + +cwd = GetCurrentDir() + +# add general drivers +src = Split(''' +board.c +CubeMX_Config/Src/stm32f4xx_hal_msp.c +''') + +path = [cwd] +path += [cwd + '/CubeMX_Config/Inc'] + +startup_path_prefix = SDK_LIB + +if rtconfig.CROSS_TOOL == 'gcc': + src += [startup_path_prefix + '/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f407xx.s'] +elif rtconfig.CROSS_TOOL == 'keil': + src += [startup_path_prefix + '/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f407xx.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src += [startup_path_prefix + '/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f407xx.s'] + +# STM32F405xx) || STM32F415xx) || STM32F407xx) || STM32F417xx) +# STM32F427xx) || STM32F437xx) || STM32F429xx) || STM32F439xx) +# STM32F401xC) || STM32F401xE) || STM32F410Tx) || STM32F410Cx) +# STM32F410Rx) || STM32F411xE) || STM32F446xx) || STM32F469xx) +# STM32F479xx) || STM32F412Cx) || STM32F412Rx) || STM32F412Vx) +# STM32F412Zx) || STM32F413xx) || STM32F423xx) +# You can select chips from the list above +CPPDEFINES = ['STM32F407xx'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/stm32/stm32f407-robomaster-c/board/board.c b/bsp/stm32/stm32f407-robomaster-c/board/board.c new file mode 100644 index 0000000000..d544465866 --- /dev/null +++ b/bsp/stm32/stm32f407-robomaster-c/board/board.c @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-06 SummerGift first version + * 2021-06-30 crazt modify for robomaster C board + */ + +#include "board.h" + +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 6; + RCC_OscInitStruct.PLL.PLLN = 168; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 4; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) + { + Error_Handler(); + } +} diff --git a/bsp/stm32/stm32f407-robomaster-c/board/board.h b/bsp/stm32/stm32f407-robomaster-c/board/board.h new file mode 100644 index 0000000000..25e4852c4c --- /dev/null +++ b/bsp/stm32/stm32f407-robomaster-c/board/board.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-5 SummerGift first version + * 2021-06-30 crazt modify for robomaster C board + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include +#include "drv_common.h" +#include "drv_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000) +#define STM32_FLASH_SIZE (1024 * 1024) +#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE)) + +#define STM32_SRAM_SIZE 128 +#define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) + +#if defined(__CC_ARM) || defined(__CLANG_ARM) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="CSTACK" +#define HEAP_BEGIN (__segment_end("CSTACK")) +#else +extern int __bss_end; +#define HEAP_BEGIN (&__bss_end) +#endif + +#define HEAP_END STM32_SRAM_END + +void SystemClock_Config(void); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/bsp/stm32/stm32f407-robomaster-c/board/linker_scripts/link.icf b/bsp/stm32/stm32f407-robomaster-c/board/linker_scripts/link.icf new file mode 100644 index 0000000000..067691151f --- /dev/null +++ b/bsp/stm32/stm32f407-robomaster-c/board/linker_scripts/link.icf @@ -0,0 +1,28 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x0400; +define symbol __ICFEDIT_size_heap__ = 0x0000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, last block CSTACK}; diff --git a/bsp/stm32/stm32f407-robomaster-c/board/linker_scripts/link.lds b/bsp/stm32/stm32f407-robomaster-c/board/linker_scripts/link.lds new file mode 100644 index 0000000000..50169db320 --- /dev/null +++ b/bsp/stm32/stm32f407-robomaster-c/board/linker_scripts/link.lds @@ -0,0 +1,157 @@ +/* + * linker script for STM32F4xx with GNU ld + * bernard.xiong 2009-10-14 + */ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + ROM (rx) : ORIGIN = 0x08000000, LENGTH = 1024k /* 1024KB flash */ + RAM (rw) : ORIGIN = 0x20000000, LENGTH = 128k /* 128K sram */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x200; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(4); + + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + + _etext = .; + } > ROM = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > ROM + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >RAM + + .stack : + { + . = ALIGN(4); + _sstack = .; + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >RAM + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > RAM + __bss_end = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/stm32/stm32f407-robomaster-c/board/linker_scripts/link.sct b/bsp/stm32/stm32f407-robomaster-c/board/linker_scripts/link.sct new file mode 100644 index 0000000000..0d7c47992d --- /dev/null +++ b/bsp/stm32/stm32f407-robomaster-c/board/linker_scripts/link.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x00100000 { ; load region size_region + ER_IROM1 0x08000000 0x00100000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00020000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/stm32/stm32f407-robomaster-c/figures/board.png b/bsp/stm32/stm32f407-robomaster-c/figures/board.png new file mode 100644 index 0000000000..39d13173ed Binary files /dev/null and b/bsp/stm32/stm32f407-robomaster-c/figures/board.png differ diff --git a/bsp/stm32/stm32f407-robomaster-c/project.ewd b/bsp/stm32/stm32f407-robomaster-c/project.ewd new file mode 100644 index 0000000000..102e51f67a --- /dev/null +++ b/bsp/stm32/stm32f407-robomaster-c/project.ewd @@ -0,0 +1,2966 @@ + + + 3 + + rt-thread + + ARM + + 1 + + C-SPY + 2 + + 30 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\components\finsh\msh.c + + + $PROJ_DIR$\..\..\..\components\finsh\cmd.c + + + + Kernel + + $PROJ_DIR$\..\..\..\src\device.c + + + $PROJ_DIR$\..\..\..\src\ipc.c + + + $PROJ_DIR$\..\..\..\src\kservice.c + + + $PROJ_DIR$\..\..\..\src\idle.c + + + $PROJ_DIR$\..\..\..\src\clock.c + + + $PROJ_DIR$\..\..\..\src\mem.c + + + $PROJ_DIR$\..\..\..\src\scheduler.c + + + $PROJ_DIR$\..\..\..\src\object.c + + + $PROJ_DIR$\..\..\..\src\irq.c + + + $PROJ_DIR$\..\..\..\src\timer.c + + + $PROJ_DIR$\..\..\..\src\mempool.c + + + $PROJ_DIR$\..\..\..\src\thread.c + + + $PROJ_DIR$\..\..\..\src\components.c + + + + libc + + $PROJ_DIR$\..\..\..\components\libc\compilers\common\time.c + + + + Libraries + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp_ex.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rng.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_usart.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cec.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_crc.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c + + + + utestcases + + diff --git a/bsp/stm32/stm32f407-robomaster-c/project.eww b/bsp/stm32/stm32f407-robomaster-c/project.eww new file mode 100644 index 0000000000..c2cb02eb1e --- /dev/null +++ b/bsp/stm32/stm32f407-robomaster-c/project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\project.ewp + + + + + diff --git a/bsp/stm32/stm32f407-robomaster-c/project.uvopt b/bsp/stm32/stm32f407-robomaster-c/project.uvopt new file mode 100644 index 0000000000..b53d69d5df --- /dev/null +++ b/bsp/stm32/stm32f407-robomaster-c/project.uvopt @@ -0,0 +1,162 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 25000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 6 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U30000299 -O207 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 + + + 0 + UL2CM3 + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + diff --git a/bsp/stm32/stm32f407-robomaster-c/project.uvoptx b/bsp/stm32/stm32f407-robomaster-c/project.uvoptx new file mode 100644 index 0000000000..01c3739c9d --- /dev/null +++ b/bsp/stm32/stm32f407-robomaster-c/project.uvoptx @@ -0,0 +1,913 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + ST-LINKIII-KEIL_SWO + -U0674FF504955857567053730 -O206 -SF10000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP (ARM Core") -D00(2BA01477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024.FLM -FS08000000 -FL0100000 -FP0($$Device:STM32F407IGHx$CMSIS\Flash\STM32F4xx_1024.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0STM32F4xx_1024 -FL0100000 -FS08000000 -FP0($$Device:STM32F407IGHx$CMSIS\Flash\STM32F4xx_1024.FLM) + + + 0 + JL2CM3 + -U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024.FLM -FS08000000 -FL0100000 -FP0($$Device:STM32F407IGHx$CMSIS\Flash\STM32F4xx_1024.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 10000000 + + + + + + Applications + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + applications\main.c + main.c + 0 + 0 + + + + + CPU + 0 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\div0.c + div0.c + 0 + 0 + + + 2 + 3 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\backtrace.c + backtrace.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\showmem.c + showmem.c + 0 + 0 + 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..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c + stm32f4xx_hal_rcc_ex.c + 0 + 0 + + + 8 + 46 + 1 + 0 + 0 + 0 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_usart.c + stm32f4xx_hal_usart.c + 0 + 0 + + + 8 + 47 + 1 + 0 + 0 + 0 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cec.c + stm32f4xx_hal_cec.c + 0 + 0 + + + 8 + 48 + 1 + 0 + 0 + 0 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c + stm32f4xx_hal_rcc.c + 0 + 0 + + + 8 + 49 + 1 + 0 + 0 + 0 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c + stm32f4xx_hal_dma_ex.c + 0 + 0 + + + 8 + 50 + 1 + 0 + 0 + 0 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c + stm32f4xx_hal_pwr.c + 0 + 0 + + + 8 + 51 + 1 + 0 + 0 + 0 + ..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c + system_stm32f4xx.c + 0 + 0 + + + 8 + 52 + 1 + 0 + 0 + 0 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_crc.c + stm32f4xx_hal_crc.c + 0 + 0 + + + 8 + 53 + 1 + 0 + 0 + 0 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c + stm32f4xx_hal_cortex.c + 0 + 0 + + + 8 + 54 + 1 + 0 + 0 + 0 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp.c + stm32f4xx_hal_cryp.c + 0 + 0 + + + 8 + 55 + 1 + 0 + 0 + 0 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c + stm32f4xx_hal_gpio.c + 0 + 0 + + + + diff --git a/bsp/stm32/stm32f407-robomaster-c/project.uvproj b/bsp/stm32/stm32f407-robomaster-c/project.uvproj new file mode 100644 index 0000000000..a2c80e0594 --- /dev/null +++ b/bsp/stm32/stm32f407-robomaster-c/project.uvproj @@ -0,0 +1,1189 @@ + + + 1.1 +
### uVision Project, (C) Keil Software
+ + + rt-thread + 0x4 + ARM-ADS + + + STM32F407ZG + STMicroelectronics + IRAM(0x20000000-0x2001FFFF) IRAM2(0x10000000-0x1000FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(25000000) CPUTYPE("Cortex-M4") FPU2 + + "Startup\ST\STM32F4xx\startup_stm32f40_41xxx.s" ("STM32F40/41xxx Startup Code") + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000) + 6105 + stm32f4xx.h + + + + + + + -DSTM32F40_41xxx + + + SFD\ST\STM32F4xx\STM32F40x.sfr + 0 + 0 + + + + ST\STM32F4xx\ + ST\STM32F4xx\ + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU -REMAP + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 0 + + 0 + 6 + + + + + + + + + + + + + + Segger\JL2CM3.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 1 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + + + USE_HAL_DRIVER, STM32F407xx + + applications;.;board;board\CubeMX_Config\Inc;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\include;..\..\..\libcpu\arm\cortex-m4;..\..\..\libcpu\arm\common;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Inc;..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Include;..\libraries\STM32F4xx_HAL\CMSIS\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + Drivers + + + board.c + 1 + board\board.c + + + + + stm32f4xx_hal_msp.c + 1 + board\CubeMX_Config\Src\stm32f4xx_hal_msp.c + + + + + startup_stm32f407xx.s + 2 + ..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Source\Templates\arm\startup_stm32f407xx.s + + + + + drv_gpio.c + 1 + ..\libraries\HAL_Drivers\drv_gpio.c + + + + + drv_usart.c + 1 + ..\libraries\HAL_Drivers\drv_usart.c + + + + + drv_common.c + 1 + ..\libraries\HAL_Drivers\drv_common.c + + + + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + + + components.c + 1 + ..\..\..\src\components.c + + + + + device.c + 1 + ..\..\..\src\device.c + + + + + idle.c + 1 + ..\..\..\src\idle.c + + + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + + + irq.c + 1 + ..\..\..\src\irq.c + + + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + + + mem.c + 1 + ..\..\..\src\mem.c + + + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + + + object.c + 1 + ..\..\..\src\object.c + + + + + scheduler.c + 1 + ..\..\..\src\scheduler.c + + + + + signal.c + 1 + ..\..\..\src\signal.c + + + + + thread.c + 1 + ..\..\..\src\thread.c + + + + + timer.c + 1 + ..\..\..\src\timer.c + + + + + CORTEX-M4 + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m4\cpuport.c + + + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m4\context_rvds.S + + + + + backtrace.c + 1 + ..\..\..\libcpu\arm\common\backtrace.c + + + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + + + DeviceDrivers + + + pin.c + 1 + ..\..\..\components\drivers\misc\pin.c + + + + + serial.c + 1 + ..\..\..\components\drivers\serial\serial.c + + + + + completion.c + 1 + ..\..\..\components\drivers\src\completion.c + + + + + dataqueue.c + 1 + ..\..\..\components\drivers\src\dataqueue.c + + + + + pipe.c + 1 + ..\..\..\components\drivers\src\pipe.c + + + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\src\ringblk_buf.c + + + + + ringbuffer.c + 1 + ..\..\..\components\drivers\src\ringbuffer.c + + + + + waitqueue.c + 1 + ..\..\..\components\drivers\src\waitqueue.c + + + + + workqueue.c + 1 + ..\..\..\components\drivers\src\workqueue.c + + + + + finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + + + symbol.c + 1 + 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1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c + + + + + stm32f4xx_hal_dma2d.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma2d.c + + + + + stm32f4xx_hal_dma_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c + + + + + stm32f4xx_hal_dsi.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dsi.c + + + + + stm32f4xx_hal_eth.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_eth.c + + + + + stm32f4xx_hal_flash.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c + + + + + stm32f4xx_hal_flash_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c + + + + + stm32f4xx_hal_flash_ramfunc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c + + + + + stm32f4xx_hal_fmpi2c.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_fmpi2c.c + + + + + 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+ + + stm32f4xx_hal_pcd_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pcd_ex.c + + + + + stm32f4xx_hal_pwr.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c + + + + + stm32f4xx_hal_pwr_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c + + + + + stm32f4xx_hal_qspi.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_qspi.c + + + + + stm32f4xx_hal_rcc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c + + + + + stm32f4xx_hal_rcc_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c + + + + + stm32f4xx_hal_rng.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rng.c + + + + + stm32f4xx_hal_rtc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rtc.c + + + + + stm32f4xx_hal_rtc_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rtc_ex.c + + + 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new file mode 100644 index 0000000000..0fd6eafce1 --- /dev/null +++ b/bsp/stm32/stm32f407-robomaster-c/project.uvprojx @@ -0,0 +1,707 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + STM32F407IGHx + STMicroelectronics + Keil.STM32F4xx_DFP.2.15.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IRAM2(0x10000000,0x00010000) IROM(0x08000000,0x00100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407IGHx$CMSIS\Flash\STM32F4xx_1024.FLM)) + 0 + $$Device:STM32F407IGHx$Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h + + + + + + + + + + $$Device:STM32F407IGHx$CMSIS\SVD\STM32F40x.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + 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__CLK_TCK=RT_TICK_PER_SECOND + + applications;.;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;board\CubeMX_Config\Inc;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\components\finsh;.;..\..\..\include;..\..\..\components\libc\compilers\common;..\..\..\components\libc\compilers\common\none-gcc;..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Inc;..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Include;..\libraries\STM32F4xx_HAL\CMSIS\Include;..\..\..\examples\utest\testcases\kernel + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + CPU + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + backtrace.c + 1 + ..\..\..\libcpu\arm\common\backtrace.c + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m4\cpuport.c + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m4\context_rvds.S + + + + + DeviceDrivers + + + pin.c + 1 + ..\..\..\components\drivers\misc\pin.c + + + serial.c + 1 + ..\..\..\components\drivers\serial\serial.c + + + dataqueue.c + 1 + ..\..\..\components\drivers\src\dataqueue.c + + + pipe.c + 1 + ..\..\..\components\drivers\src\pipe.c + + + workqueue.c + 1 + ..\..\..\components\drivers\src\workqueue.c + + + waitqueue.c + 1 + ..\..\..\components\drivers\src\waitqueue.c + + + ringbuffer.c + 1 + ..\..\..\components\drivers\src\ringbuffer.c + + + completion.c + 1 + ..\..\..\components\drivers\src\completion.c + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\src\ringblk_buf.c + + + + + Drivers + + + stm32f4xx_hal_msp.c + 1 + board\CubeMX_Config\Src\stm32f4xx_hal_msp.c + + + startup_stm32f407xx.s + 2 + ..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Source\Templates\arm\startup_stm32f407xx.s + + + board.c + 1 + board\board.c + + + drv_gpio.c + 1 + ..\libraries\HAL_Drivers\drv_gpio.c + + + drv_usart.c + 1 + ..\libraries\HAL_Drivers\drv_usart.c + + + drv_common.c + 1 + ..\libraries\HAL_Drivers\drv_common.c + + + + + finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + + + Kernel + + + object.c + 1 + ..\..\..\src\object.c + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + clock.c + 1 + ..\..\..\src\clock.c + + + irq.c + 1 + ..\..\..\src\irq.c + + + timer.c + 1 + ..\..\..\src\timer.c + + + idle.c + 1 + ..\..\..\src\idle.c + + + thread.c + 1 + ..\..\..\src\thread.c + + + device.c + 1 + ..\..\..\src\device.c + + + mem.c + 1 + ..\..\..\src\mem.c + + + components.c + 1 + ..\..\..\src\components.c + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + scheduler.c + 1 + ..\..\..\src\scheduler.c + + + + + libc + + + time.c + 1 + ..\..\..\components\libc\compilers\common\time.c + + + + + Libraries + + + stm32f4xx_hal_uart.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c + + + stm32f4xx_hal_cryp_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp_ex.c + + + stm32f4xx_hal_pwr_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c + + + stm32f4xx_hal_rng.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rng.c + + + stm32f4xx_hal_dma.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c + + + stm32f4xx_hal.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c + + + stm32f4xx_hal_rcc_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c + + + stm32f4xx_hal_usart.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_usart.c + + + stm32f4xx_hal_cec.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cec.c + + + stm32f4xx_hal_rcc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c + + + stm32f4xx_hal_dma_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c + + + stm32f4xx_hal_pwr.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c + + + system_stm32f4xx.c + 1 + ..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c + + + stm32f4xx_hal_crc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_crc.c + + + stm32f4xx_hal_cortex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c + + + stm32f4xx_hal_cryp.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp.c + + + stm32f4xx_hal_gpio.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c + + + + + + + + + + + + + + diff --git a/bsp/stm32/stm32f407-robomaster-c/rtconfig.h b/bsp/stm32/stm32f407-robomaster-c/rtconfig.h new file mode 100644 index 0000000000..78104e6805 --- /dev/null +++ b/bsp/stm32/stm32f407-robomaster-c/rtconfig.h @@ -0,0 +1,187 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 + +/* kservice optimization */ + +#define RT_DEBUG +#define RT_DEBUG_COLOR + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x40004 +#define ARCH_ARM +#define RT_USING_CPU_FFS +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M4 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_USING_MSH_ONLY +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_LIBC_USING_TIME +#define RT_LIBC_FIXED_TIMEZONE 8 + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + + +/* AI packages */ + + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + +#define SOC_FAMILY_STM32 +#define SOC_SERIES_STM32F4 + +/* Hardware Drivers Config */ + +#define SOC_STM32F407IG + +/* Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART1 + +/* Board extended module Drivers */ + + +#endif diff --git a/bsp/stm32/stm32f407-robomaster-c/rtconfig.py b/bsp/stm32/stm32f407-robomaster-c/rtconfig.py new file mode 100644 index 0000000000..b0cd716905 --- /dev/null +++ b/bsp/stm32/stm32f407-robomaster-c/rtconfig.py @@ -0,0 +1,149 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv4_sp' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu VFPv4_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/stm32/stm32f407-robomaster-c/template.ewd b/bsp/stm32/stm32f407-robomaster-c/template.ewd new file mode 100644 index 0000000000..0328777969 --- /dev/null +++ b/bsp/stm32/stm32f407-robomaster-c/template.ewd @@ -0,0 +1,2966 @@ + + + 3 + + rt-thread + + ARM + + 1 + + C-SPY + 2 + + 30 + 1 + 1 + + + + + + + + + + + + + + + + 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a/bsp/stm32/stm32f407-robomaster-c/template.eww b/bsp/stm32/stm32f407-robomaster-c/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/stm32/stm32f407-robomaster-c/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/stm32/stm32f407-robomaster-c/template.uvopt b/bsp/stm32/stm32f407-robomaster-c/template.uvopt new file mode 100644 index 0000000000..b53d69d5df --- /dev/null +++ b/bsp/stm32/stm32f407-robomaster-c/template.uvopt @@ -0,0 +1,162 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 25000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 6 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U30000299 -O207 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 + + + 0 + UL2CM3 + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + diff --git a/bsp/stm32/stm32f407-robomaster-c/template.uvoptx b/bsp/stm32/stm32f407-robomaster-c/template.uvoptx new file mode 100644 index 0000000000..ab07607d4a --- /dev/null +++ b/bsp/stm32/stm32f407-robomaster-c/template.uvoptx @@ -0,0 +1,197 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + ST-LINKIII-KEIL_SWO + -U0674FF504955857567053730 -O206 -SF10000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP (ARM Core") -D00(2BA01477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024.FLM -FS08000000 -FL0100000 -FP0($$Device:STM32F407IGHx$CMSIS\Flash\STM32F4xx_1024.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0STM32F4xx_1024 -FL0100000 -FS08000000 -FP0($$Device:STM32F407IGHx$CMSIS\Flash\STM32F4xx_1024.FLM) + + + 0 + JL2CM3 + -U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024.FLM -FS08000000 -FL0100000 -FP0($$Device:STM32F407IGHx$CMSIS\Flash\STM32F4xx_1024.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 10000000 + + + + + + Source Group 1 + 0 + 0 + 0 + 0 + + + diff --git a/bsp/stm32/stm32f407-robomaster-c/template.uvproj b/bsp/stm32/stm32f407-robomaster-c/template.uvproj new file mode 100644 index 0000000000..6ca2a92953 --- /dev/null +++ b/bsp/stm32/stm32f407-robomaster-c/template.uvproj @@ -0,0 +1,407 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + + + STM32F407ZG + STMicroelectronics + IRAM(0x20000000-0x2001FFFF) IRAM2(0x10000000-0x1000FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(25000000) CPUTYPE("Cortex-M4") FPU2 + + "Startup\ST\STM32F4xx\startup_stm32f40_41xxx.s" ("STM32F40/41xxx Startup Code") + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000) + 6105 + stm32f4xx.h + + + + + + + -DSTM32F40_41xxx + + + SFD\ST\STM32F4xx\STM32F40x.sfr + 0 + 0 + + + + ST\STM32F4xx\ + ST\STM32F4xx\ + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU -REMAP + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 0 + + 0 + 6 + + + + + + + + + + + + + + Segger\JL2CM3.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 1 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + + diff --git a/bsp/stm32/stm32f407-robomaster-c/template.uvprojx b/bsp/stm32/stm32f407-robomaster-c/template.uvprojx new file mode 100644 index 0000000000..90f76b3093 --- /dev/null +++ b/bsp/stm32/stm32f407-robomaster-c/template.uvprojx @@ -0,0 +1,395 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + STM32F407IGHx + STMicroelectronics + Keil.STM32F4xx_DFP.2.15.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IRAM2(0x10000000,0x00010000) IROM(0x08000000,0x00100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407IGHx$CMSIS\Flash\STM32F4xx_1024.FLM)) + 0 + $$Device:STM32F407IGHx$Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h + + + + + + + + + + $$Device:STM32F407IGHx$CMSIS\SVD\STM32F40x.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Source Group 1 + + + + + + + + + + + + diff --git a/bsp/stm32/stm32f407-st-discovery/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f407-st-discovery/board/CubeMX_Config/CubeMX_Config.ioc index 195ad7beb1..c208e8f6bd 100644 --- a/bsp/stm32/stm32f407-st-discovery/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32f407-st-discovery/board/CubeMX_Config/CubeMX_Config.ioc @@ -25,18 +25,19 @@ Mcu.PinsNb=11 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32F407VGTx -MxCube.Version=5.0.0 -MxDb.Version=DB.5.0.0 -NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:true -NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:true -NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:true -NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:true -NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:true -NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true +MxCube.Version=6.2.1 +MxDb.Version=DB.6.0.21 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:true\:false +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:true\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:true\:false +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false NVIC.PriorityGroup=NVIC_PRIORITYGROUP_0 -NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true -NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true -NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:true +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false +NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false PA13.GPIOParameters=GPIO_Label PA13.GPIO_Label=SWDIO PA13.Locked=true @@ -75,18 +76,14 @@ PB3.GPIOParameters=GPIO_Label PB3.GPIO_Label=SWO PB3.Locked=true PB3.Signal=SYS_JTDO-SWO +PB6.GPIOParameters=GPIO_PuPd +PB6.GPIO_PuPd=GPIO_PULLUP PB6.Mode=Asynchronous PB6.Signal=USART1_TX +PB7.GPIOParameters=GPIO_PuPd +PB7.GPIO_PuPd=GPIO_PULLUP PB7.Mode=Asynchronous PB7.Signal=USART1_RX -PCC.Checker=false -PCC.Line=STM32F407/417 -PCC.MCU=STM32F407V(E-G)Tx -PCC.PartNumber=STM32F407VGTx -PCC.Seq0=0 -PCC.Series=STM32F4 -PCC.Temperature=25 -PCC.Vdd=3.3 PH0-OSC_IN.GPIOParameters=GPIO_Label PH0-OSC_IN.GPIO_Label=PH0-OSC_IN PH0-OSC_IN.Locked=true diff --git a/bsp/stm32/stm32f407-st-discovery/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c b/bsp/stm32/stm32f407-st-discovery/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c index 2bac295eeb..e1da0e121a 100644 --- a/bsp/stm32/stm32f407-st-discovery/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c +++ b/bsp/stm32/stm32f407-st-discovery/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c @@ -2,46 +2,46 @@ /** ****************************************************************************** * File Name : stm32f4xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** * This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether + * USER CODE END. Other portions of this file, whether * inserted by the user or by software development tools * are owned by their respective copyright owners. * - * Copyright (c) 2018 STMicroelectronics International N.V. + * Copyright (c) 2018 STMicroelectronics International N.V. * All rights reserved. * - * Redistribution and use in source and binary forms, with or without + * Redistribution and use in source and binary forms, with or without * modification, are permitted, provided that the following conditions are met: * - * 1. Redistribution of source code must retain the above copyright notice, + * 1. Redistribution of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of other - * contributors to this software may be used to endorse or promote products + * 3. Neither the name of STMicroelectronics nor the names of other + * contributors to this software may be used to endorse or promote products * derived from this software without specific written permission. - * 4. This software, including modifications and/or derivative works of this + * 4. This software, including modifications and/or derivative works of this * software, must execute solely and exclusively on microcontroller or * microprocessor devices manufactured by or for STMicroelectronics. - * 5. Redistribution and use of this software other than as permitted under - * this license is void and will automatically terminate your rights under - * this license. + * 5. Redistribution and use of this software other than as permitted under + * this license is void and will automatically terminate your rights under + * this license. * - * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY - * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT + * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * @@ -62,7 +62,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -117,7 +117,6 @@ void HAL_MspInit(void) */ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) { - GPIO_InitTypeDef GPIO_InitStruct = {0}; if(hspi->Instance==SPI1) { @@ -126,12 +125,12 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**SPI1 GPIO Configuration + /**SPI1 GPIO Configuration PA5 ------> SPI1_SCK PA6 ------> SPI1_MISO - PA7 ------> SPI1_MOSI + PA7 ------> SPI1_MOSI */ GPIO_InitStruct.Pin = SPI1_SCK_Pin|SPI1_MISO_Pin|SPI1_MOSI_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -153,10 +152,8 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) * @param hspi: SPI handle pointer * @retval None */ - void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) { - if(hspi->Instance==SPI1) { /* USER CODE BEGIN SPI1_MspDeInit 0 */ @@ -164,11 +161,11 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI1_CLK_DISABLE(); - - /**SPI1 GPIO Configuration + + /**SPI1 GPIO Configuration PA5 ------> SPI1_SCK PA6 ------> SPI1_MISO - PA7 ------> SPI1_MOSI + PA7 ------> SPI1_MOSI */ HAL_GPIO_DeInit(GPIOA, SPI1_SCK_Pin|SPI1_MISO_Pin|SPI1_MOSI_Pin); @@ -187,7 +184,6 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { - GPIO_InitTypeDef GPIO_InitStruct = {0}; if(huart->Instance==USART1) { @@ -196,11 +192,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - + __HAL_RCC_GPIOB_CLK_ENABLE(); - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PB6 ------> USART1_TX - PB7 ------> USART1_RX + PB7 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -222,10 +218,8 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) * @param huart: UART handle pointer * @retval None */ - void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) { - if(huart->Instance==USART1) { /* USER CODE BEGIN USART1_MspDeInit 0 */ @@ -233,10 +227,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration + + /**USART1 GPIO Configuration PB6 ------> USART1_TX - PB7 ------> USART1_RX + PB7 ------> USART1_RX */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6|GPIO_PIN_7); diff --git a/bsp/stm32/stm32f410-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f410-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc index 2ff19285ab..daf5f74fde 100644 --- a/bsp/stm32/stm32f410-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32f410-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc @@ -48,14 +48,12 @@ PA14.GPIO_Label=TCK PA14.Locked=true PA14.Mode=Serial_Wire PA14.Signal=SYS_JTCK-SWCLK -PA2.GPIOParameters=GPIO_Label -PA2.GPIO_Label=USART_TX -PA2.Locked=true +PA2.GPIOParameters=GPIO_PuPd +PA2.GPIO_PuPd=GPIO_PULLUP PA2.Mode=Asynchronous PA2.Signal=USART2_TX -PA3.GPIOParameters=GPIO_Label -PA3.GPIO_Label=USART_RX -PA3.Locked=true +PA3.GPIOParameters=GPIO_PuPd +PA3.GPIO_PuPd=GPIO_PULLUP PA3.Mode=Asynchronous PA3.Signal=USART2_RX PA5.GPIOParameters=GPIO_Label diff --git a/bsp/stm32/stm32f410-st-nucleo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c b/bsp/stm32/stm32f410-st-nucleo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c index 55374ff0d2..1246457260 100644 --- a/bsp/stm32/stm32f410-st-nucleo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c +++ b/bsp/stm32/stm32f410-st-nucleo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c @@ -2,7 +2,7 @@ /** ****************************************************************************** * File Name : stm32f4xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** * @attention @@ -32,7 +32,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -95,15 +95,15 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART2 GPIO Configuration + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ GPIO_InitStruct.Pin = USART_TX_Pin|USART_RX_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF7_USART2; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); @@ -130,10 +130,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART2_CLK_DISABLE(); - - /**USART2 GPIO Configuration + + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ HAL_GPIO_DeInit(GPIOA, USART_TX_Pin|USART_RX_Pin); diff --git a/bsp/stm32/stm32f411-atk-nano/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f411-atk-nano/board/CubeMX_Config/CubeMX_Config.ioc index 1791e31d5e..397b95b06c 100644 --- a/bsp/stm32/stm32f411-atk-nano/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32f411-atk-nano/board/CubeMX_Config/CubeMX_Config.ioc @@ -57,18 +57,26 @@ NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +PA9.GPIOParameters=GPIO_PuPd +PA9.GPIO_PuPd=GPIO_PULLUP +PA9.Mode=Asynchronous +PA9.Signal=USART1_TX +PA10.GPIOParameters=GPIO_PuPd +PA10.GPIO_PuPd=GPIO_PULLUP PA10.Mode=Asynchronous PA10.Signal=USART1_RX PA13.Mode=Serial_Wire PA13.Signal=SYS_JTMS-SWDIO PA14.Mode=Serial_Wire PA14.Signal=SYS_JTCK-SWCLK +PA2.GPIOParameters=GPIO_PuPd +PA2.GPIO_PuPd=GPIO_PULLUP PA2.Mode=Asynchronous PA2.Signal=USART2_TX +PA3.GPIOParameters=GPIO_PuPd +PA3.GPIO_PuPd=GPIO_PULLUP PA3.Mode=Asynchronous PA3.Signal=USART2_RX -PA9.Mode=Asynchronous -PA9.Signal=USART1_TX PB1.Locked=true PB1.Signal=ADCx_IN9 PB13.Locked=true diff --git a/bsp/stm32/stm32f411-atk-nano/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c b/bsp/stm32/stm32f411-atk-nano/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c index ac3d0bf3f5..5598c57bce 100644 --- a/bsp/stm32/stm32f411-atk-nano/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c +++ b/bsp/stm32/stm32f411-atk-nano/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c @@ -2,12 +2,12 @@ /** ****************************************************************************** * File Name : stm32f4xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** ** This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether + * USER CODE END. Other portions of this file, whether * inserted by the user or by software development tools * are owned by their respective copyright owners. * @@ -52,7 +52,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -114,10 +114,10 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) /* USER CODE END ADC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_ADC1_CLK_ENABLE(); - + __HAL_RCC_GPIOB_CLK_ENABLE(); - /**ADC1 GPIO Configuration - PB1 ------> ADC1_IN9 + /**ADC1 GPIO Configuration + PB1 ------> ADC1_IN9 */ GPIO_InitStruct.Pin = GPIO_PIN_1; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; @@ -148,9 +148,9 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) /* USER CODE END ADC1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_ADC1_CLK_DISABLE(); - - /**ADC1 GPIO Configuration - PB1 ------> ADC1_IN9 + + /**ADC1 GPIO Configuration + PB1 ------> ADC1_IN9 */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_1); @@ -176,11 +176,11 @@ void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) /* USER CODE BEGIN I2C1_MspInit 0 */ /* USER CODE END I2C1_MspInit 0 */ - + __HAL_RCC_GPIOB_CLK_ENABLE(); - /**I2C1 GPIO Configuration + /**I2C1 GPIO Configuration PB6 ------> I2C1_SCL - PB7 ------> I2C1_SDA + PB7 ------> I2C1_SDA */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; @@ -215,10 +215,10 @@ void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c) /* USER CODE END I2C1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_I2C1_CLK_DISABLE(); - - /**I2C1 GPIO Configuration + + /**I2C1 GPIO Configuration PB6 ------> I2C1_SCL - PB7 ------> I2C1_SDA + PB7 ------> I2C1_SDA */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6|GPIO_PIN_7); @@ -293,12 +293,12 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI2_CLK_ENABLE(); - + __HAL_RCC_GPIOB_CLK_ENABLE(); - /**SPI2 GPIO Configuration + /**SPI2 GPIO Configuration PB13 ------> SPI2_SCK PB14 ------> SPI2_MISO - PB15 ------> SPI2_MOSI + PB15 ------> SPI2_MOSI */ GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -331,11 +331,11 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI2_CLK_DISABLE(); - - /**SPI2 GPIO Configuration + + /**SPI2 GPIO Configuration PB13 ------> SPI2_SCK PB14 ------> SPI2_MISO - PB15 ------> SPI2_MOSI + PB15 ------> SPI2_MOSI */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15); @@ -363,11 +363,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -387,11 +387,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART2 GPIO Configuration + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -424,10 +424,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration + + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); @@ -442,10 +442,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART2_CLK_DISABLE(); - - /**USART2 GPIO Configuration + + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3); diff --git a/bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc index 68d45640ce..d770287e0b 100644 --- a/bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc @@ -69,8 +69,12 @@ PA14.GPIO_Label=TCK PA14.Locked=true PA14.Mode=Serial_Wire PA14.Signal=SYS_JTCK-SWCLK +PA2.GPIOParameters=GPIO_PuPd +PA2.GPIO_PuPd=GPIO_PULLUP PA2.Mode=Asynchronous PA2.Signal=USART2_TX +PA3.GPIOParameters=GPIO_PuPd +PA3.GPIO_PuPd=GPIO_PULLUP PA3.Mode=Asynchronous PA3.Signal=USART2_RX PA5.Mode=Full_Duplex_Master diff --git a/bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c b/bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c index b2c91f0c47..ff38319ce3 100644 --- a/bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c +++ b/bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c @@ -2,12 +2,12 @@ /** ****************************************************************************** * File Name : stm32f4xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** ** This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether + * USER CODE END. Other portions of this file, whether * inserted by the user or by software development tools * are owned by their respective copyright owners. * @@ -52,7 +52,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -78,7 +78,7 @@ /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ - + void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); /** * Initializes the Global MSP. @@ -165,13 +165,13 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); - /**SPI1 GPIO Configuration + /**SPI1 GPIO Configuration PA5 ------> SPI1_SCK PB4 ------> SPI1_MISO - PB5 ------> SPI1_MOSI + PB5 ------> SPI1_MOSI */ GPIO_InitStruct.Pin = GPIO_PIN_5; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -211,11 +211,11 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI1_CLK_DISABLE(); - - /**SPI1 GPIO Configuration + + /**SPI1 GPIO Configuration PA5 ------> SPI1_SCK PB4 ------> SPI1_MISO - PB5 ------> SPI1_MOSI + PB5 ------> SPI1_MOSI */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5); @@ -260,14 +260,14 @@ void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) /* USER CODE BEGIN TIM3_MspPostInit 0 */ /* USER CODE END TIM3_MspPostInit 0 */ - + __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); - /**TIM3 GPIO Configuration + /**TIM3 GPIO Configuration PA6 ------> TIM3_CH1 PA7 ------> TIM3_CH2 PB0 ------> TIM3_CH3 - PB1 ------> TIM3_CH4 + PB1 ------> TIM3_CH4 */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -330,11 +330,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART2 GPIO Configuration + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -354,11 +354,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART6_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART6_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART6 GPIO Configuration + /**USART6 GPIO Configuration PA11 ------> USART6_TX - PA12 ------> USART6_RX + PA12 ------> USART6_RX */ GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -391,10 +391,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART2_CLK_DISABLE(); - - /**USART2 GPIO Configuration + + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3); @@ -409,10 +409,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART6_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART6_CLK_DISABLE(); - - /**USART6 GPIO Configuration + + /**USART6 GPIO Configuration PA11 ------> USART6_TX - PA12 ------> USART6_RX + PA12 ------> USART6_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11|GPIO_PIN_12); diff --git a/bsp/stm32/stm32f411-weact-MiniF4/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f411-weact-MiniF4/board/CubeMX_Config/CubeMX_Config.ioc index 1468ade621..4bf9eb69a8 100644 --- a/bsp/stm32/stm32f411-weact-MiniF4/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32f411-weact-MiniF4/board/CubeMX_Config/CubeMX_Config.ioc @@ -49,6 +49,12 @@ NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +PA9.GPIOParameters=GPIO_PuPd +PA9.GPIO_PuPd=GPIO_PULLUP +PA9.Mode=Asynchronous +PA9.Signal=USART1_TX +PA10.GPIOParameters=GPIO_PuPd +PA10.GPIO_PuPd=GPIO_PULLUP PA10.Mode=Asynchronous PA10.Signal=USART1_RX PA11.Mode=Device_Only @@ -65,8 +71,6 @@ PA6.Mode=Full_Duplex_Master PA6.Signal=SPI1_MISO PA7.Mode=Full_Duplex_Master PA7.Signal=SPI1_MOSI -PA9.Mode=Asynchronous -PA9.Signal=USART1_TX PC13-ANTI_TAMP.Locked=true PC13-ANTI_TAMP.Signal=GPIO_Output PC14-OSC32_IN.Mode=LSE-External-Oscillator diff --git a/bsp/stm32/stm32f411-weact-MiniF4/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c b/bsp/stm32/stm32f411-weact-MiniF4/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c index 97a4cad91d..ff0ff3b0b6 100644 --- a/bsp/stm32/stm32f411-weact-MiniF4/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c +++ b/bsp/stm32/stm32f411-weact-MiniF4/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c @@ -2,7 +2,7 @@ /** ****************************************************************************** * File Name : stm32f4xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** * @attention @@ -32,7 +32,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -137,12 +137,12 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**SPI1 GPIO Configuration + /**SPI1 GPIO Configuration PA5 ------> SPI1_SCK PA6 ------> SPI1_MISO - PA7 ------> SPI1_MOSI + PA7 ------> SPI1_MOSI */ GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -173,11 +173,11 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI1_CLK_DISABLE(); - - /**SPI1 GPIO Configuration + + /**SPI1 GPIO Configuration PA5 ------> SPI1_SCK PA6 ------> SPI1_MISO - PA7 ------> SPI1_MOSI + PA7 ------> SPI1_MOSI */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7); @@ -270,15 +270,15 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF7_USART1; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); @@ -305,10 +305,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration + + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); @@ -333,11 +333,11 @@ void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd) /* USER CODE BEGIN USB_OTG_FS_MspInit 0 */ /* USER CODE END USB_OTG_FS_MspInit 0 */ - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USB_OTG_FS GPIO Configuration + /**USB_OTG_FS GPIO Configuration PA11 ------> USB_OTG_FS_DM - PA12 ------> USB_OTG_FS_DP + PA12 ------> USB_OTG_FS_DP */ GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -370,10 +370,10 @@ void HAL_PCD_MspDeInit(PCD_HandleTypeDef* hpcd) /* USER CODE END USB_OTG_FS_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USB_OTG_FS_CLK_DISABLE(); - - /**USB_OTG_FS GPIO Configuration + + /**USB_OTG_FS GPIO Configuration PA11 ------> USB_OTG_FS_DM - PA12 ------> USB_OTG_FS_DP + PA12 ------> USB_OTG_FS_DP */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11|GPIO_PIN_12); diff --git a/bsp/stm32/stm32f412-st-nucleo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c b/bsp/stm32/stm32f412-st-nucleo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c index 2ef6d3f970..1cb7cb865a 100644 --- a/bsp/stm32/stm32f412-st-nucleo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c +++ b/bsp/stm32/stm32f412-st-nucleo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c @@ -2,12 +2,12 @@ /** ****************************************************************************** * File Name : stm32f4xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** ** This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether + * USER CODE END. Other portions of this file, whether * inserted by the user or by software development tools * are owned by their respective copyright owners. * @@ -52,7 +52,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -114,11 +114,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART3_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART3_CLK_ENABLE(); - + __HAL_RCC_GPIOD_CLK_ENABLE(); - /**USART3 GPIO Configuration + /**USART3 GPIO Configuration PD8 ------> USART3_TX - PD9 ------> USART3_RX + PD9 ------> USART3_RX */ GPIO_InitStruct.Pin = STLK_RX_Pin|STLK_TX_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -151,10 +151,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART3_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART3_CLK_DISABLE(); - - /**USART3 GPIO Configuration + + /**USART3 GPIO Configuration PD8 ------> USART3_TX - PD9 ------> USART3_RX + PD9 ------> USART3_RX */ HAL_GPIO_DeInit(GPIOD, STLK_RX_Pin|STLK_TX_Pin); @@ -180,13 +180,13 @@ void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd) /* USER CODE BEGIN USB_OTG_FS_MspInit 0 */ /* USER CODE END USB_OTG_FS_MspInit 0 */ - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USB_OTG_FS GPIO Configuration + /**USB_OTG_FS GPIO Configuration PA8 ------> USB_OTG_FS_SOF PA10 ------> USB_OTG_FS_ID PA11 ------> USB_OTG_FS_DM - PA12 ------> USB_OTG_FS_DP + PA12 ------> USB_OTG_FS_DP */ GPIO_InitStruct.Pin = USB_SOF_Pin|USB_ID_Pin|USB_DM_Pin|USB_DP_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -221,12 +221,12 @@ void HAL_PCD_MspDeInit(PCD_HandleTypeDef* hpcd) /* USER CODE END USB_OTG_FS_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USB_OTG_FS_CLK_DISABLE(); - - /**USB_OTG_FS GPIO Configuration + + /**USB_OTG_FS GPIO Configuration PA8 ------> USB_OTG_FS_SOF PA10 ------> USB_OTG_FS_ID PA11 ------> USB_OTG_FS_DM - PA12 ------> USB_OTG_FS_DP + PA12 ------> USB_OTG_FS_DP */ HAL_GPIO_DeInit(GPIOA, USB_SOF_Pin|USB_ID_Pin|USB_DM_Pin|USB_DP_Pin); diff --git a/bsp/stm32/stm32f412-st-nucleo/rtconfig.py b/bsp/stm32/stm32f412-st-nucleo/rtconfig.py index 573c1f7492..9193d4a1d5 100644 --- a/bsp/stm32/stm32f412-st-nucleo/rtconfig.py +++ b/bsp/stm32/stm32f412-st-nucleo/rtconfig.py @@ -94,6 +94,40 @@ elif PLATFORM == 'armcc': POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' +elif PLATFORM == 'armclang': + # toolchains + CC = 'armclang' + CXX = 'armclang' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-m4 ' + CFLAGS += ' -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 ' + CFLAGS += ' -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar ' + CFLAGS += ' -gdwarf-3 -ffunction-sections ' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers ' + LFLAGS += ' --list rt-thread.map ' + LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" ' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib' + + EXEC_PATH += '/ARM/ARMCLANG/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O1' # armclang recommend + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + elif PLATFORM == 'iar': # toolchains CC = 'iccarm' diff --git a/bsp/stm32/stm32f413-st-nucleo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c b/bsp/stm32/stm32f413-st-nucleo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c index b70b0c1c20..fbc3920044 100644 --- a/bsp/stm32/stm32f413-st-nucleo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c +++ b/bsp/stm32/stm32f413-st-nucleo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c @@ -2,12 +2,12 @@ /** ****************************************************************************** * File Name : stm32f4xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** ** This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether + * USER CODE END. Other portions of this file, whether * inserted by the user or by software development tools * are owned by their respective copyright owners. * @@ -52,7 +52,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -78,7 +78,7 @@ /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ - + void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); /** * Initializes the Global MSP. @@ -115,10 +115,10 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) /* USER CODE END ADC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_ADC1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**ADC1 GPIO Configuration - PA5 ------> ADC1_IN5 + /**ADC1 GPIO Configuration + PA5 ------> ADC1_IN5 */ GPIO_InitStruct.Pin = GPIO_PIN_5; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; @@ -147,9 +147,9 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) /* USER CODE END ADC1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_ADC1_CLK_DISABLE(); - - /**ADC1 GPIO Configuration - PA5 ------> ADC1_IN5 + + /**ADC1 GPIO Configuration + PA5 ------> ADC1_IN5 */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5); @@ -174,11 +174,11 @@ void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) /* USER CODE BEGIN I2C1_MspInit 0 */ /* USER CODE END I2C1_MspInit 0 */ - + __HAL_RCC_GPIOB_CLK_ENABLE(); - /**I2C1 GPIO Configuration + /**I2C1 GPIO Configuration PB6 ------> I2C1_SCL - PB9 ------> I2C1_SDA + PB9 ------> I2C1_SDA */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_9; GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; @@ -211,10 +211,10 @@ void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c) /* USER CODE END I2C1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_I2C1_CLK_DISABLE(); - - /**I2C1 GPIO Configuration + + /**I2C1 GPIO Configuration PB6 ------> I2C1_SCL - PB9 ------> I2C1_SDA + PB9 ------> I2C1_SDA */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6|GPIO_PIN_9); @@ -285,13 +285,13 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI2_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); - /**SPI2 GPIO Configuration + /**SPI2 GPIO Configuration PC2 ------> SPI2_MISO PC3 ------> SPI2_MOSI - PB10 ------> SPI2_SCK + PB10 ------> SPI2_SCK */ GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -329,11 +329,11 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI2_CLK_DISABLE(); - - /**SPI2 GPIO Configuration + + /**SPI2 GPIO Configuration PC2 ------> SPI2_MISO PC3 ------> SPI2_MOSI - PB10 ------> SPI2_SCK + PB10 ------> SPI2_SCK */ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_2|GPIO_PIN_3); @@ -409,10 +409,10 @@ void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) /* USER CODE BEGIN TIM2_MspPostInit 0 */ /* USER CODE END TIM2_MspPostInit 0 */ - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**TIM2 GPIO Configuration - PA3 ------> TIM2_CH4 + /**TIM2 GPIO Configuration + PA3 ------> TIM2_CH4 */ GPIO_InitStruct.Pin = GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -498,12 +498,12 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); - /**USART2 GPIO Configuration + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PD6 ------> USART2_RX + PD6 ------> USART2_RX */ GPIO_InitStruct.Pin = GPIO_PIN_2; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -530,11 +530,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART3_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART3_CLK_ENABLE(); - + __HAL_RCC_GPIOD_CLK_ENABLE(); - /**USART3 GPIO Configuration + /**USART3 GPIO Configuration PD8 ------> USART3_TX - PD9 ------> USART3_RX + PD9 ------> USART3_RX */ GPIO_InitStruct.Pin = STLK_RX_Pin|STLK_TX_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -565,10 +565,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART2_CLK_DISABLE(); - - /**USART2 GPIO Configuration + + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PD6 ------> USART2_RX + PD6 ------> USART2_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2); @@ -585,10 +585,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART3_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART3_CLK_DISABLE(); - - /**USART3 GPIO Configuration + + /**USART3 GPIO Configuration PD8 ------> USART3_TX - PD9 ------> USART3_RX + PD9 ------> USART3_RX */ HAL_GPIO_DeInit(GPIOD, STLK_RX_Pin|STLK_TX_Pin); @@ -613,14 +613,14 @@ void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd) /* USER CODE BEGIN USB_OTG_FS_MspInit 0 */ /* USER CODE END USB_OTG_FS_MspInit 0 */ - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USB_OTG_FS GPIO Configuration + /**USB_OTG_FS GPIO Configuration PA8 ------> USB_OTG_FS_SOF PA9 ------> USB_OTG_FS_VBUS PA10 ------> USB_OTG_FS_ID PA11 ------> USB_OTG_FS_DM - PA12 ------> USB_OTG_FS_DP + PA12 ------> USB_OTG_FS_DP */ GPIO_InitStruct.Pin = USB_SOF_Pin|USB_ID_Pin|USB_DM_Pin|USB_DP_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -658,15 +658,15 @@ void HAL_PCD_MspDeInit(PCD_HandleTypeDef* hpcd) /* USER CODE END USB_OTG_FS_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USB_OTG_FS_CLK_DISABLE(); - - /**USB_OTG_FS GPIO Configuration + + /**USB_OTG_FS GPIO Configuration PA8 ------> USB_OTG_FS_SOF PA9 ------> USB_OTG_FS_VBUS PA10 ------> USB_OTG_FS_ID PA11 ------> USB_OTG_FS_DM - PA12 ------> USB_OTG_FS_DP + PA12 ------> USB_OTG_FS_DP */ - HAL_GPIO_DeInit(GPIOA, USB_SOF_Pin|USB_VBUS_Pin|USB_ID_Pin|USB_DM_Pin + HAL_GPIO_DeInit(GPIOA, USB_SOF_Pin|USB_VBUS_Pin|USB_ID_Pin|USB_DM_Pin |USB_DP_Pin); /* USER CODE BEGIN USB_OTG_FS_MspDeInit 1 */ diff --git a/bsp/stm32/stm32f427-robomaster-a/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c b/bsp/stm32/stm32f427-robomaster-a/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c index 19b391828c..efa99aed9a 100644 --- a/bsp/stm32/stm32f427-robomaster-a/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c +++ b/bsp/stm32/stm32f427-robomaster-a/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c @@ -2,12 +2,12 @@ /** ****************************************************************************** * File Name : stm32f4xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** ** This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether + * USER CODE END. Other portions of this file, whether * inserted by the user or by software development tools * are owned by their respective copyright owners. * @@ -52,7 +52,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -78,7 +78,7 @@ /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ - + void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); /** * Initializes the Global MSP. @@ -120,11 +120,11 @@ void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan) if(HAL_RCC_CAN1_CLK_ENABLED==1){ __HAL_RCC_CAN1_CLK_ENABLE(); } - + __HAL_RCC_GPIOD_CLK_ENABLE(); - /**CAN1 GPIO Configuration + /**CAN1 GPIO Configuration PD0 ------> CAN1_RX - PD1 ------> CAN1_TX + PD1 ------> CAN1_TX */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -148,11 +148,11 @@ void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan) if(HAL_RCC_CAN1_CLK_ENABLED==1){ __HAL_RCC_CAN1_CLK_ENABLE(); } - + __HAL_RCC_GPIOB_CLK_ENABLE(); - /**CAN2 GPIO Configuration + /**CAN2 GPIO Configuration PB12 ------> CAN2_RX - PB13 ------> CAN2_TX + PB13 ------> CAN2_TX */ GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_13; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -186,10 +186,10 @@ void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) if(HAL_RCC_CAN1_CLK_ENABLED==0){ __HAL_RCC_CAN1_CLK_DISABLE(); } - - /**CAN1 GPIO Configuration + + /**CAN1 GPIO Configuration PD0 ------> CAN1_RX - PD1 ------> CAN1_TX + PD1 ------> CAN1_TX */ HAL_GPIO_DeInit(GPIOD, GPIO_PIN_0|GPIO_PIN_1); @@ -208,10 +208,10 @@ void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) if(HAL_RCC_CAN1_CLK_ENABLED==0){ __HAL_RCC_CAN1_CLK_DISABLE(); } - - /**CAN2 GPIO Configuration + + /**CAN2 GPIO Configuration PB12 ------> CAN2_RX - PB13 ------> CAN2_TX + PB13 ------> CAN2_TX */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_12|GPIO_PIN_13); @@ -238,18 +238,18 @@ void HAL_SD_MspInit(SD_HandleTypeDef* hsd) /* USER CODE END SDIO_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SDIO_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); - /**SDIO GPIO Configuration + /**SDIO GPIO Configuration PC12 ------> SDIO_CK PC11 ------> SDIO_D3 PC10 ------> SDIO_D2 PD2 ------> SDIO_CMD PC9 ------> SDIO_D1 - PC8 ------> SDIO_D0 + PC8 ------> SDIO_D0 */ - GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_9 + GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_9 |GPIO_PIN_8; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -286,16 +286,16 @@ void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) /* USER CODE END SDIO_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SDIO_CLK_DISABLE(); - - /**SDIO GPIO Configuration + + /**SDIO GPIO Configuration PC12 ------> SDIO_CK PC11 ------> SDIO_D3 PC10 ------> SDIO_D2 PD2 ------> SDIO_CMD PC9 ------> SDIO_D1 - PC8 ------> SDIO_D0 + PC8 ------> SDIO_D0 */ - HAL_GPIO_DeInit(GPIOC, GPIO_PIN_12|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_9 + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_12|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_9 |GPIO_PIN_8); HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); @@ -323,12 +323,12 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI5_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI5_CLK_ENABLE(); - + __HAL_RCC_GPIOF_CLK_ENABLE(); - /**SPI5 GPIO Configuration + /**SPI5 GPIO Configuration PF7 ------> SPI5_SCK PF9 ------> SPI5_MOSI - PF8 ------> SPI5_MISO + PF8 ------> SPI5_MISO */ GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_9|GPIO_PIN_8; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -359,11 +359,11 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI5_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI5_CLK_DISABLE(); - - /**SPI5 GPIO Configuration + + /**SPI5 GPIO Configuration PF7 ------> SPI5_SCK PF9 ------> SPI5_MOSI - PF8 ------> SPI5_MISO + PF8 ------> SPI5_MISO */ HAL_GPIO_DeInit(GPIOF, GPIO_PIN_7|GPIO_PIN_9|GPIO_PIN_8); @@ -427,11 +427,11 @@ void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) /* USER CODE END TIM4_MspPostInit 0 */ __HAL_RCC_GPIOD_CLK_ENABLE(); - /**TIM4 GPIO Configuration + /**TIM4 GPIO Configuration PD15 ------> TIM4_CH4 PD14 ------> TIM4_CH3 PD13 ------> TIM4_CH2 - PD12 ------> TIM4_CH1 + PD12 ------> TIM4_CH1 */ GPIO_InitStruct.Pin = GPIO_PIN_15|GPIO_PIN_14|GPIO_PIN_13|GPIO_PIN_12; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -449,14 +449,14 @@ void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) /* USER CODE BEGIN TIM5_MspPostInit 0 */ /* USER CODE END TIM5_MspPostInit 0 */ - + __HAL_RCC_GPIOI_CLK_ENABLE(); __HAL_RCC_GPIOH_CLK_ENABLE(); - /**TIM5 GPIO Configuration + /**TIM5 GPIO Configuration PI0 ------> TIM5_CH4 PH12 ------> TIM5_CH3 PH11 ------> TIM5_CH2 - PH10 ------> TIM5_CH1 + PH10 ------> TIM5_CH1 */ GPIO_InitStruct.Pin = GPIO_PIN_0; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -481,10 +481,10 @@ void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) /* USER CODE BEGIN TIM12_MspPostInit 0 */ /* USER CODE END TIM12_MspPostInit 0 */ - + __HAL_RCC_GPIOH_CLK_ENABLE(); - /**TIM12 GPIO Configuration - PH6 ------> TIM12_CH1 + /**TIM12 GPIO Configuration + PH6 ------> TIM12_CH1 */ GPIO_InitStruct.Pin = GPIO_PIN_6; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -559,11 +559,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END UART7_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_UART7_CLK_ENABLE(); - + __HAL_RCC_GPIOE_CLK_ENABLE(); - /**UART7 GPIO Configuration + /**UART7 GPIO Configuration PE8 ------> UART7_TX - PE7 ------> UART7_RX + PE7 ------> UART7_RX */ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -583,11 +583,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END UART8_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_UART8_CLK_ENABLE(); - + __HAL_RCC_GPIOE_CLK_ENABLE(); - /**UART8 GPIO Configuration + /**UART8 GPIO Configuration PE1 ------> UART8_TX - PE0 ------> UART8_RX + PE0 ------> UART8_RX */ GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_0; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -607,11 +607,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - + __HAL_RCC_GPIOB_CLK_ENABLE(); - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PB7 ------> USART1_RX - PB6 ------> USART1_TX + PB6 ------> USART1_TX */ GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_6; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -631,11 +631,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART3_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART3_CLK_ENABLE(); - + __HAL_RCC_GPIOD_CLK_ENABLE(); - /**USART3 GPIO Configuration + /**USART3 GPIO Configuration PD9 ------> USART3_RX - PD8 ------> USART3_TX + PD8 ------> USART3_TX */ GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_8; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -655,11 +655,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART6_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART6_CLK_ENABLE(); - + __HAL_RCC_GPIOG_CLK_ENABLE(); - /**USART6 GPIO Configuration + /**USART6 GPIO Configuration PG14 ------> USART6_TX - PG9 ------> USART6_RX + PG9 ------> USART6_RX */ GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_9; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -693,10 +693,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END UART7_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_UART7_CLK_DISABLE(); - - /**UART7 GPIO Configuration + + /**UART7 GPIO Configuration PE8 ------> UART7_TX - PE7 ------> UART7_RX + PE7 ------> UART7_RX */ HAL_GPIO_DeInit(GPIOE, GPIO_PIN_8|GPIO_PIN_7); @@ -711,10 +711,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END UART8_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_UART8_CLK_DISABLE(); - - /**UART8 GPIO Configuration + + /**UART8 GPIO Configuration PE1 ------> UART8_TX - PE0 ------> UART8_RX + PE0 ------> UART8_RX */ HAL_GPIO_DeInit(GPIOE, GPIO_PIN_1|GPIO_PIN_0); @@ -729,10 +729,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration + + /**USART1 GPIO Configuration PB7 ------> USART1_RX - PB6 ------> USART1_TX + PB6 ------> USART1_TX */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_7|GPIO_PIN_6); @@ -747,10 +747,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART3_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART3_CLK_DISABLE(); - - /**USART3 GPIO Configuration + + /**USART3 GPIO Configuration PD9 ------> USART3_RX - PD8 ------> USART3_TX + PD8 ------> USART3_TX */ HAL_GPIO_DeInit(GPIOD, GPIO_PIN_9|GPIO_PIN_8); @@ -765,10 +765,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART6_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART6_CLK_DISABLE(); - - /**USART6 GPIO Configuration + + /**USART6 GPIO Configuration PG14 ------> USART6_TX - PG9 ------> USART6_RX + PG9 ------> USART6_RX */ HAL_GPIO_DeInit(GPIOG, GPIO_PIN_14|GPIO_PIN_9); diff --git a/bsp/stm32/stm32f429-armfly-v6/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f429-armfly-v6/board/CubeMX_Config/CubeMX_Config.ioc index 713e78f639..298807cd0b 100644 --- a/bsp/stm32/stm32f429-armfly-v6/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32f429-armfly-v6/board/CubeMX_Config/CubeMX_Config.ioc @@ -175,6 +175,12 @@ NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false PA0/WKUP.Signal=S_TIM2_CH1_ETR PA1.Mode=RMII PA1.Signal=ETH_REF_CLK +PA9.GPIOParameters=GPIO_PuPd +PA9.GPIO_PuPd=GPIO_PULLUP +PA9.Mode=Asynchronous +PA9.Signal=USART1_TX +PA10.GPIOParameters=GPIO_PuPd +PA10.GPIO_PuPd=GPIO_PULLUP PA10.Mode=Asynchronous PA10.Signal=USART1_RX PA13.Mode=Serial_Wire @@ -185,8 +191,6 @@ PA2.Mode=RMII PA2.Signal=ETH_MDIO PA7.Mode=RMII PA7.Signal=ETH_CRS_DV -PA9.Mode=Asynchronous -PA9.Signal=USART1_TX PB13.Mode=RMII PB13.Signal=ETH_TXD1 PB3.Locked=true diff --git a/bsp/stm32/stm32f429-armfly-v6/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c b/bsp/stm32/stm32f429-armfly-v6/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c index 5e0a3aac30..5d46a084d8 100644 --- a/bsp/stm32/stm32f429-armfly-v6/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c +++ b/bsp/stm32/stm32f429-armfly-v6/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c @@ -2,12 +2,12 @@ /** ****************************************************************************** * File Name : stm32f4xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** ** This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether + * USER CODE END. Other portions of this file, whether * inserted by the user or by software development tools * are owned by their respective copyright owners. * @@ -52,7 +52,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -78,7 +78,7 @@ /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ - + void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); /** * Initializes the Global MSP. @@ -116,11 +116,11 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) /* USER CODE END ADC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_ADC1_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); - /**ADC1 GPIO Configuration + /**ADC1 GPIO Configuration PC0 ------> ADC1_IN10 - PC3 ------> ADC1_IN13 + PC3 ------> ADC1_IN13 */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; @@ -151,10 +151,10 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) /* USER CODE END ADC1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_ADC1_CLK_DISABLE(); - - /**ADC1 GPIO Configuration + + /**ADC1 GPIO Configuration PC0 ------> ADC1_IN10 - PC3 ------> ADC1_IN13 + PC3 ------> ADC1_IN13 */ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_0|GPIO_PIN_3); @@ -229,12 +229,12 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) /* USER CODE END ETH_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_ETH_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOG_CLK_ENABLE(); - /**ETH GPIO Configuration + /**ETH GPIO Configuration PC1 ------> ETH_MDC PA1 ------> ETH_REF_CLK PA2 ------> ETH_MDIO @@ -243,7 +243,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) PC5 ------> ETH_RXD1 PB13 ------> ETH_TXD1 PG11 ------> ETH_TX_EN - PG13 ------> ETH_TXD0 + PG13 ------> ETH_TXD0 */ GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -297,8 +297,8 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) /* USER CODE END ETH_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_ETH_CLK_DISABLE(); - - /**ETH GPIO Configuration + + /**ETH GPIO Configuration PC1 ------> ETH_MDC PA1 ------> ETH_REF_CLK PA2 ------> ETH_MDIO @@ -307,7 +307,7 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) PC5 ------> ETH_RXD1 PB13 ------> ETH_TXD1 PG11 ------> ETH_TX_EN - PG13 ------> ETH_TXD0 + PG13 ------> ETH_TXD0 */ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5); @@ -341,11 +341,11 @@ void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) /* USER CODE END LTDC_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_LTDC_CLK_ENABLE(); - + __HAL_RCC_GPIOI_CLK_ENABLE(); __HAL_RCC_GPIOJ_CLK_ENABLE(); __HAL_RCC_GPIOK_CLK_ENABLE(); - /**LTDC GPIO Configuration + /**LTDC GPIO Configuration PI12 ------> LTDC_HSYNC PI13 ------> LTDC_VSYNC PI14 ------> LTDC_CLK @@ -373,7 +373,7 @@ void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) PK4 ------> LTDC_B5 PK5 ------> LTDC_B6 PK6 ------> LTDC_B7 - PK7 ------> LTDC_DE + PK7 ------> LTDC_DE */ GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -382,9 +382,9 @@ void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; HAL_GPIO_Init(GPIOI, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 - |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7 - |GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7 + |GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 |GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -392,7 +392,7 @@ void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; HAL_GPIO_Init(GPIOJ, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -424,8 +424,8 @@ void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc) /* USER CODE END LTDC_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_LTDC_CLK_DISABLE(); - - /**LTDC GPIO Configuration + + /**LTDC GPIO Configuration PI12 ------> LTDC_HSYNC PI13 ------> LTDC_VSYNC PI14 ------> LTDC_CLK @@ -453,16 +453,16 @@ void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc) PK4 ------> LTDC_B5 PK5 ------> LTDC_B6 PK6 ------> LTDC_B7 - PK7 ------> LTDC_DE + PK7 ------> LTDC_DE */ HAL_GPIO_DeInit(GPIOI, GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15); - HAL_GPIO_DeInit(GPIOJ, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 - |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7 - |GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + HAL_GPIO_DeInit(GPIOJ, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7 + |GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 |GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15); - HAL_GPIO_DeInit(GPIOK, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + HAL_GPIO_DeInit(GPIOK, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7); /* USER CODE BEGIN LTDC_MspDeInit 1 */ @@ -536,18 +536,18 @@ void HAL_SD_MspInit(SD_HandleTypeDef* hsd) /* USER CODE END SDIO_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SDIO_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); - /**SDIO GPIO Configuration + /**SDIO GPIO Configuration PC8 ------> SDIO_D0 PC9 ------> SDIO_D1 PC10 ------> SDIO_D2 PC11 ------> SDIO_D3 PC12 ------> SDIO_CK - PD2 ------> SDIO_CMD + PD2 ------> SDIO_CMD */ - GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 |GPIO_PIN_12; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -586,16 +586,16 @@ void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) /* USER CODE END SDIO_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SDIO_CLK_DISABLE(); - - /**SDIO GPIO Configuration + + /**SDIO GPIO Configuration PC8 ------> SDIO_D0 PC9 ------> SDIO_D1 PC10 ------> SDIO_D2 PC11 ------> SDIO_D3 PC12 ------> SDIO_CK - PD2 ------> SDIO_CMD + PD2 ------> SDIO_CMD */ - HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 |GPIO_PIN_12); HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); @@ -624,12 +624,12 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI3_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI3_CLK_ENABLE(); - + __HAL_RCC_GPIOB_CLK_ENABLE(); - /**SPI3 GPIO Configuration + /**SPI3 GPIO Configuration PB3 ------> SPI3_SCK PB4 ------> SPI3_MISO - PB5 ------> SPI3_MOSI + PB5 ------> SPI3_MOSI */ GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -662,11 +662,11 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI3_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI3_CLK_DISABLE(); - - /**SPI3 GPIO Configuration + + /**SPI3 GPIO Configuration PB3 ------> SPI3_SCK PB4 ------> SPI3_MISO - PB5 ------> SPI3_MOSI + PB5 ------> SPI3_MOSI */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5); @@ -742,10 +742,10 @@ void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) /* USER CODE BEGIN TIM2_MspPostInit 0 */ /* USER CODE END TIM2_MspPostInit 0 */ - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**TIM2 GPIO Configuration - PA0/WKUP ------> TIM2_CH1 + /**TIM2 GPIO Configuration + PA0/WKUP ------> TIM2_CH1 */ GPIO_InitStruct.Pin = GPIO_PIN_0; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -834,11 +834,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -874,10 +874,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration + + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); @@ -903,8 +903,8 @@ static void HAL_FMC_MspInit(void){ FMC_Initialized = 1; /* Peripheral clock enable */ __HAL_RCC_FMC_CLK_ENABLE(); - - /** FMC GPIO Configuration + + /** FMC GPIO Configuration PI9 ------> FMC_D30 PI10 ------> FMC_D31 PF0 ------> FMC_A0 @@ -965,8 +965,8 @@ static void HAL_FMC_MspInit(void){ PI6 ------> FMC_D28 PI7 ------> FMC_D29 */ - GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_0|GPIO_PIN_1 - |GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5 + GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_0|GPIO_PIN_1 + |GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5 |GPIO_PIN_6|GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -974,8 +974,8 @@ static void HAL_FMC_MspInit(void){ GPIO_InitStruct.Alternate = GPIO_AF12_FMC; HAL_GPIO_Init(GPIOI, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 - |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_11|GPIO_PIN_12 + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_11|GPIO_PIN_12 |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -983,8 +983,8 @@ static void HAL_FMC_MspInit(void){ GPIO_InitStruct.Alternate = GPIO_AF12_FMC; HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_5|GPIO_PIN_8 - |GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12 + GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_5|GPIO_PIN_8 + |GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12 |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -992,7 +992,7 @@ static void HAL_FMC_MspInit(void){ GPIO_InitStruct.Alternate = GPIO_AF12_FMC; HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5 + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5 |GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -1000,8 +1000,8 @@ static void HAL_FMC_MspInit(void){ GPIO_InitStruct.Alternate = GPIO_AF12_FMC; HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 - |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 + GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 + |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -1009,8 +1009,8 @@ static void HAL_FMC_MspInit(void){ GPIO_InitStruct.Alternate = GPIO_AF12_FMC; HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14 - |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4 + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14 + |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4 |GPIO_PIN_5; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -1055,8 +1055,8 @@ static void HAL_FMC_MspDeInit(void){ FMC_DeInitialized = 1; /* Peripheral clock enable */ __HAL_RCC_FMC_CLK_DISABLE(); - - /** FMC GPIO Configuration + + /** FMC GPIO Configuration PI9 ------> FMC_D30 PI10 ------> FMC_D31 PF0 ------> FMC_A0 @@ -1117,27 +1117,27 @@ static void HAL_FMC_MspDeInit(void){ PI6 ------> FMC_D28 PI7 ------> FMC_D29 */ - HAL_GPIO_DeInit(GPIOI, GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_0|GPIO_PIN_1 - |GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5 + HAL_GPIO_DeInit(GPIOI, GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_0|GPIO_PIN_1 + |GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5 |GPIO_PIN_6|GPIO_PIN_7); - HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 - |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_11|GPIO_PIN_12 + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_11|GPIO_PIN_12 |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15); - HAL_GPIO_DeInit(GPIOH, GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_5|GPIO_PIN_8 - |GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12 + HAL_GPIO_DeInit(GPIOH, GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_5|GPIO_PIN_8 + |GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12 |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15); - HAL_GPIO_DeInit(GPIOG, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5 + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5 |GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_15); - HAL_GPIO_DeInit(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 - |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 + HAL_GPIO_DeInit(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 + |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1); - HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14 - |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4 + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14 + |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4 |GPIO_PIN_5); /* USER CODE BEGIN FMC_MspDeInit 1 */ diff --git a/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c b/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c index ad60e8e19a..0d0405b7a1 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c +++ b/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c @@ -2,12 +2,12 @@ /** ****************************************************************************** * File Name : stm32f4xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** ** This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether + * USER CODE END. Other portions of this file, whether * inserted by the user or by software development tools * are owned by their respective copyright owners. * @@ -52,7 +52,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -78,7 +78,7 @@ /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ - + void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); /** * Initializes the Global MSP. @@ -115,10 +115,10 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) /* USER CODE END ADC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_ADC1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**ADC1 GPIO Configuration - PA5 ------> ADC1_IN5 + /**ADC1 GPIO Configuration + PA5 ------> ADC1_IN5 */ GPIO_InitStruct.Pin = GPIO_PIN_5; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; @@ -147,9 +147,9 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) /* USER CODE END ADC1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_ADC1_CLK_DISABLE(); - - /**ADC1 GPIO Configuration - PA5 ------> ADC1_IN5 + + /**ADC1 GPIO Configuration + PA5 ------> ADC1_IN5 */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5); @@ -176,11 +176,11 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) /* USER CODE END ETH_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_ETH_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOG_CLK_ENABLE(); - /**ETH GPIO Configuration + /**ETH GPIO Configuration PC1 ------> ETH_MDC PA1 ------> ETH_REF_CLK PA2 ------> ETH_MDIO @@ -189,7 +189,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) PC5 ------> ETH_RXD1 PG11 ------> ETH_TX_EN PG13 ------> ETH_TXD0 - PG14 ------> ETH_TXD1 + PG14 ------> ETH_TXD1 */ GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -234,8 +234,8 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) /* USER CODE END ETH_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_ETH_CLK_DISABLE(); - - /**ETH GPIO Configuration + + /**ETH GPIO Configuration PC1 ------> ETH_MDC PA1 ------> ETH_REF_CLK PA2 ------> ETH_MDIO @@ -244,7 +244,7 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) PC5 ------> ETH_RXD1 PG11 ------> ETH_TX_EN PG13 ------> ETH_TXD0 - PG14 ------> ETH_TXD1 + PG14 ------> ETH_TXD1 */ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5); @@ -319,18 +319,18 @@ void HAL_SD_MspInit(SD_HandleTypeDef* hsd) /* USER CODE END SDIO_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SDIO_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); - /**SDIO GPIO Configuration + /**SDIO GPIO Configuration PC8 ------> SDIO_D0 PC9 ------> SDIO_D1 PC10 ------> SDIO_D2 PC11 ------> SDIO_D3 PC12 ------> SDIO_CK - PD2 ------> SDIO_CMD + PD2 ------> SDIO_CMD */ - GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 |GPIO_PIN_12; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -367,16 +367,16 @@ void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) /* USER CODE END SDIO_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SDIO_CLK_DISABLE(); - - /**SDIO GPIO Configuration + + /**SDIO GPIO Configuration PC8 ------> SDIO_D0 PC9 ------> SDIO_D1 PC10 ------> SDIO_D2 PC11 ------> SDIO_D3 PC12 ------> SDIO_CK - PD2 ------> SDIO_CMD + PD2 ------> SDIO_CMD */ - HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 |GPIO_PIN_12); HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); @@ -404,13 +404,13 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); - /**SPI1 GPIO Configuration + /**SPI1 GPIO Configuration PA6 ------> SPI1_MISO PB3 ------> SPI1_SCK - PB5 ------> SPI1_MOSI + PB5 ------> SPI1_MOSI */ GPIO_InitStruct.Pin = GPIO_PIN_6; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -437,12 +437,12 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI2_CLK_ENABLE(); - + __HAL_RCC_GPIOB_CLK_ENABLE(); - /**SPI2 GPIO Configuration + /**SPI2 GPIO Configuration PB13 ------> SPI2_SCK PB14 ------> SPI2_MISO - PB15 ------> SPI2_MOSI + PB15 ------> SPI2_MOSI */ GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -462,12 +462,12 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI5_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI5_CLK_ENABLE(); - + __HAL_RCC_GPIOF_CLK_ENABLE(); - /**SPI5 GPIO Configuration + /**SPI5 GPIO Configuration PF7 ------> SPI5_SCK PF8 ------> SPI5_MISO - PF9 ------> SPI5_MOSI + PF9 ------> SPI5_MOSI */ GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -498,11 +498,11 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI1_CLK_DISABLE(); - - /**SPI1 GPIO Configuration + + /**SPI1 GPIO Configuration PA6 ------> SPI1_MISO PB3 ------> SPI1_SCK - PB5 ------> SPI1_MOSI + PB5 ------> SPI1_MOSI */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_6); @@ -519,11 +519,11 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI2_CLK_DISABLE(); - - /**SPI2 GPIO Configuration + + /**SPI2 GPIO Configuration PB13 ------> SPI2_SCK PB14 ------> SPI2_MISO - PB15 ------> SPI2_MOSI + PB15 ------> SPI2_MOSI */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15); @@ -538,11 +538,11 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI5_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI5_CLK_DISABLE(); - - /**SPI5 GPIO Configuration + + /**SPI5 GPIO Configuration PF7 ------> SPI5_SCK PF8 ------> SPI5_MISO - PF9 ------> SPI5_MOSI + PF9 ------> SPI5_MOSI */ HAL_GPIO_DeInit(GPIOF, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9); @@ -616,10 +616,10 @@ void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) /* USER CODE BEGIN TIM2_MspPostInit 0 */ /* USER CODE END TIM2_MspPostInit 0 */ - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**TIM2 GPIO Configuration - PA3 ------> TIM2_CH4 + /**TIM2 GPIO Configuration + PA3 ------> TIM2_CH4 */ GPIO_InitStruct.Pin = GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -701,16 +701,16 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) if(huart->Instance==USART1) { /* USER CODE BEGIN USART1_MspInit 0 */ - + /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -733,11 +733,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); - + __HAL_RCC_GPIOD_CLK_ENABLE(); - /**USART2 GPIO Configuration + /**USART2 GPIO Configuration PD5 ------> USART2_TX - PD6 ------> USART2_RX + PD6 ------> USART2_RX */ GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -757,11 +757,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART3_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART3_CLK_ENABLE(); - + __HAL_RCC_GPIOB_CLK_ENABLE(); - /**USART3 GPIO Configuration + /**USART3 GPIO Configuration PB10 ------> USART3_TX - PB11 ------> USART3_RX + PB11 ------> USART3_RX */ GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -792,10 +792,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration + + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); @@ -812,10 +812,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART2_CLK_DISABLE(); - - /**USART2 GPIO Configuration + + /**USART2 GPIO Configuration PD5 ------> USART2_TX - PD6 ------> USART2_RX + PD6 ------> USART2_RX */ HAL_GPIO_DeInit(GPIOD, GPIO_PIN_5|GPIO_PIN_6); @@ -830,10 +830,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART3_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART3_CLK_DISABLE(); - - /**USART3 GPIO Configuration + + /**USART3 GPIO Configuration PB10 ------> USART3_TX - PB11 ------> USART3_RX + PB11 ------> USART3_RX */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_10|GPIO_PIN_11); @@ -858,11 +858,11 @@ void HAL_HCD_MspInit(HCD_HandleTypeDef* hhcd) /* USER CODE BEGIN USB_OTG_FS_MspInit 0 */ /* USER CODE END USB_OTG_FS_MspInit 0 */ - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USB_OTG_FS GPIO Configuration + /**USB_OTG_FS GPIO Configuration PA11 ------> USB_OTG_FS_DM - PA12 ------> USB_OTG_FS_DP + PA12 ------> USB_OTG_FS_DP */ GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -898,10 +898,10 @@ void HAL_HCD_MspDeInit(HCD_HandleTypeDef* hhcd) /* USER CODE END USB_OTG_FS_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USB_OTG_FS_CLK_DISABLE(); - - /**USB_OTG_FS GPIO Configuration + + /**USB_OTG_FS GPIO Configuration PA11 ------> USB_OTG_FS_DM - PA12 ------> USB_OTG_FS_DP + PA12 ------> USB_OTG_FS_DP */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11|GPIO_PIN_12); @@ -927,8 +927,8 @@ static void HAL_FMC_MspInit(void){ FMC_Initialized = 1; /* Peripheral clock enable */ __HAL_RCC_FMC_CLK_ENABLE(); - - /** FMC GPIO Configuration + + /** FMC GPIO Configuration PF0 ------> FMC_A0 PF1 ------> FMC_A1 PF2 ------> FMC_A2 @@ -969,8 +969,8 @@ static void HAL_FMC_MspInit(void){ PE0 ------> FMC_NBL0 PE1 ------> FMC_NBL1 */ - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 - |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_11|GPIO_PIN_12 + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_11|GPIO_PIN_12 |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -985,7 +985,7 @@ static void HAL_FMC_MspInit(void){ GPIO_InitStruct.Alternate = GPIO_AF12_FMC; HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_4 + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_4 |GPIO_PIN_5|GPIO_PIN_8|GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -993,8 +993,8 @@ static void HAL_FMC_MspInit(void){ GPIO_InitStruct.Alternate = GPIO_AF12_FMC; HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 - |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 + GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 + |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -1002,7 +1002,7 @@ static void HAL_FMC_MspInit(void){ GPIO_InitStruct.Alternate = GPIO_AF12_FMC; HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14 + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14 |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -1037,8 +1037,8 @@ static void HAL_FMC_MspDeInit(void){ FMC_DeInitialized = 1; /* Peripheral clock enable */ __HAL_RCC_FMC_CLK_DISABLE(); - - /** FMC GPIO Configuration + + /** FMC GPIO Configuration PF0 ------> FMC_A0 PF1 ------> FMC_A1 PF2 ------> FMC_A2 @@ -1079,20 +1079,20 @@ static void HAL_FMC_MspDeInit(void){ PE0 ------> FMC_NBL0 PE1 ------> FMC_NBL1 */ - HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 - |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_11|GPIO_PIN_12 + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_11|GPIO_PIN_12 |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15); HAL_GPIO_DeInit(GPIOC, GPIO_PIN_0|GPIO_PIN_2|GPIO_PIN_3); - HAL_GPIO_DeInit(GPIOG, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_4 + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_4 |GPIO_PIN_5|GPIO_PIN_8|GPIO_PIN_15); - HAL_GPIO_DeInit(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 - |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 + HAL_GPIO_DeInit(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 + |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1); - HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14 + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14 |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1); /* USER CODE BEGIN FMC_MspDeInit 1 */ @@ -1125,12 +1125,12 @@ void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai) __HAL_RCC_SAI1_CLK_ENABLE(); } SAI1_client ++; - - /**SAI1_A_Block_A GPIO Configuration + + /**SAI1_A_Block_A GPIO Configuration PE2 ------> SAI1_MCLK_A PE4 ------> SAI1_FS_A PE5 ------> SAI1_SCK_A - PE6 ------> SAI1_SD_A + PE6 ------> SAI1_SD_A */ GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -1148,9 +1148,9 @@ void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai) __HAL_RCC_SAI1_CLK_ENABLE(); } SAI1_client ++; - - /**SAI1_B_Block_B GPIO Configuration - PE3 ------> SAI1_SD_B + + /**SAI1_B_Block_B GPIO Configuration + PE3 ------> SAI1_SD_B */ GPIO_InitStruct.Pin = GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -1171,15 +1171,15 @@ void HAL_SAI_MspDeInit(SAI_HandleTypeDef* hsai) SAI1_client --; if (SAI1_client == 0) { - /* Peripheral clock disable */ + /* Peripheral clock disable */ __HAL_RCC_SAI1_CLK_DISABLE(); } - - /**SAI1_A_Block_A GPIO Configuration + + /**SAI1_A_Block_A GPIO Configuration PE2 ------> SAI1_MCLK_A PE4 ------> SAI1_FS_A PE5 ------> SAI1_SCK_A - PE6 ------> SAI1_SD_A + PE6 ------> SAI1_SD_A */ HAL_GPIO_DeInit(GPIOE, GPIO_PIN_2|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6); @@ -1192,9 +1192,9 @@ void HAL_SAI_MspDeInit(SAI_HandleTypeDef* hsai) /* Peripheral clock disable */ __HAL_RCC_SAI1_CLK_DISABLE(); } - - /**SAI1_B_Block_B GPIO Configuration - PE3 ------> SAI1_SD_B + + /**SAI1_B_Block_B GPIO Configuration + PE3 ------> SAI1_SD_B */ HAL_GPIO_DeInit(GPIOE, GPIO_PIN_3); diff --git a/bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/CubeMX_Config.ioc index b23d058006..40485e9361 100644 --- a/bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/CubeMX_Config.ioc @@ -153,6 +153,12 @@ NVIC.USART1_IRQn=true\:0\:0\:false\:false\:true\:true NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false PA1.Mode=RMII PA1.Signal=ETH_REF_CLK +PA9.GPIOParameters=GPIO_PuPd +PA9.GPIO_PuPd=GPIO_PULLUP +PA9.Mode=Asynchronous +PA9.Signal=USART1_TX +PA10.GPIOParameters=GPIO_PuPd +PA10.GPIO_PuPd=GPIO_PULLUP PA10.Mode=Asynchronous PA10.Signal=USART1_RX PA11.Mode=RGB888 @@ -170,8 +176,6 @@ PA3.Mode=RGB888 PA3.Signal=LTDC_B5 PA7.Mode=RMII PA7.Signal=ETH_CRS_DV -PA9.Mode=Asynchronous -PA9.Signal=USART1_TX PB0.Locked=true PB0.Mode=RGB888 PB0.Signal=LTDC_R3 diff --git a/bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c b/bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c index 380fd93b83..059f740127 100644 --- a/bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c +++ b/bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c @@ -2,12 +2,12 @@ /** ****************************************************************************** * File Name : stm32f4xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** ** This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether + * USER CODE END. Other portions of this file, whether * inserted by the user or by software development tools * are owned by their respective copyright owners. * @@ -52,7 +52,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -78,7 +78,7 @@ /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ - + void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); /** * Initializes the Global MSP. @@ -116,10 +116,10 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) /* USER CODE END ADC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_ADC1_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); - /**ADC1 GPIO Configuration - PC3 ------> ADC1_IN13 + /**ADC1 GPIO Configuration + PC3 ------> ADC1_IN13 */ GPIO_InitStruct.Pin = GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; @@ -150,9 +150,9 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) /* USER CODE END ADC1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_ADC1_CLK_DISABLE(); - - /**ADC1 GPIO Configuration - PC3 ------> ADC1_IN13 + + /**ADC1 GPIO Configuration + PC3 ------> ADC1_IN13 */ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_3); @@ -227,12 +227,12 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) /* USER CODE END ETH_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_ETH_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOG_CLK_ENABLE(); - /**ETH GPIO Configuration + /**ETH GPIO Configuration PC1 ------> ETH_MDC PA1 ------> ETH_REF_CLK PA2 ------> ETH_MDIO @@ -241,7 +241,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) PC5 ------> ETH_RXD1 PB11 ------> ETH_TX_EN PG13 ------> ETH_TXD0 - PG14 ------> ETH_TXD1 + PG14 ------> ETH_TXD1 */ GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -295,8 +295,8 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) /* USER CODE END ETH_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_ETH_CLK_DISABLE(); - - /**ETH GPIO Configuration + + /**ETH GPIO Configuration PC1 ------> ETH_MDC PA1 ------> ETH_REF_CLK PA2 ------> ETH_MDIO @@ -305,7 +305,7 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) PC5 ------> ETH_RXD1 PB11 ------> ETH_TX_EN PG13 ------> ETH_TXD0 - PG14 ------> ETH_TXD1 + PG14 ------> ETH_TXD1 */ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5); @@ -339,7 +339,7 @@ void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) /* USER CODE END LTDC_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_LTDC_CLK_ENABLE(); - + __HAL_RCC_GPIOE_CLK_ENABLE(); __HAL_RCC_GPIOI_CLK_ENABLE(); __HAL_RCC_GPIOF_CLK_ENABLE(); @@ -349,7 +349,7 @@ void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) __HAL_RCC_GPIOG_CLK_ENABLE(); __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); - /**LTDC GPIO Configuration + /**LTDC GPIO Configuration PE4 ------> LTDC_B0 PE5 ------> LTDC_G0 PE6 ------> LTDC_G1 @@ -377,7 +377,7 @@ void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) PG12 ------> LTDC_B1 PB8 ------> LTDC_B6 PB9 ------> LTDC_B7 - PI4 ------> LTDC_B4 + PI4 ------> LTDC_B4 */ GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -386,7 +386,7 @@ void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_0|GPIO_PIN_2 + GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_0|GPIO_PIN_2 |GPIO_PIN_4; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -401,7 +401,7 @@ void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_8|GPIO_PIN_13 + GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_8|GPIO_PIN_13 |GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -482,8 +482,8 @@ void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc) /* USER CODE END LTDC_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_LTDC_CLK_DISABLE(); - - /**LTDC GPIO Configuration + + /**LTDC GPIO Configuration PE4 ------> LTDC_B0 PE5 ------> LTDC_G0 PE6 ------> LTDC_G1 @@ -511,23 +511,23 @@ void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc) PG12 ------> LTDC_B1 PB8 ------> LTDC_B6 PB9 ------> LTDC_B7 - PI4 ------> LTDC_B4 + PI4 ------> LTDC_B4 */ HAL_GPIO_DeInit(GPIOE, GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6); - HAL_GPIO_DeInit(GPIOI, GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_0|GPIO_PIN_2 + HAL_GPIO_DeInit(GPIOI, GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_0|GPIO_PIN_2 |GPIO_PIN_4); HAL_GPIO_DeInit(GPIOF, GPIO_PIN_10); - HAL_GPIO_DeInit(GPIOH, GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_8|GPIO_PIN_13 + HAL_GPIO_DeInit(GPIOH, GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_8|GPIO_PIN_13 |GPIO_PIN_15); HAL_GPIO_DeInit(GPIOA, GPIO_PIN_3|GPIO_PIN_11|GPIO_PIN_12); HAL_GPIO_DeInit(GPIOB, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_8|GPIO_PIN_9); - HAL_GPIO_DeInit(GPIOG, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_10|GPIO_PIN_11 + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_10|GPIO_PIN_11 |GPIO_PIN_12); HAL_GPIO_DeInit(GPIOC, GPIO_PIN_7); @@ -605,18 +605,18 @@ void HAL_SD_MspInit(SD_HandleTypeDef* hsd) /* USER CODE END SDIO_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SDIO_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); - /**SDIO GPIO Configuration + /**SDIO GPIO Configuration PC8 ------> SDIO_D0 PC9 ------> SDIO_D1 PC10 ------> SDIO_D2 PC11 ------> SDIO_D3 PC12 ------> SDIO_CK - PD2 ------> SDIO_CMD + PD2 ------> SDIO_CMD */ - GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 |GPIO_PIN_12; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -655,16 +655,16 @@ void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) /* USER CODE END SDIO_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SDIO_CLK_DISABLE(); - - /**SDIO GPIO Configuration + + /**SDIO GPIO Configuration PC8 ------> SDIO_D0 PC9 ------> SDIO_D1 PC10 ------> SDIO_D2 PC11 ------> SDIO_D3 PC12 ------> SDIO_CK - PD2 ------> SDIO_CMD + PD2 ------> SDIO_CMD */ - HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 |GPIO_PIN_12); HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); @@ -693,12 +693,12 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI5_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI5_CLK_ENABLE(); - + __HAL_RCC_GPIOF_CLK_ENABLE(); - /**SPI5 GPIO Configuration + /**SPI5 GPIO Configuration PF7 ------> SPI5_SCK PF8 ------> SPI5_MISO - PF9 ------> SPI5_MOSI + PF9 ------> SPI5_MOSI */ GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -731,11 +731,11 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI5_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI5_CLK_DISABLE(); - - /**SPI5 GPIO Configuration + + /**SPI5 GPIO Configuration PF7 ------> SPI5_SCK PF8 ------> SPI5_MISO - PF9 ------> SPI5_MOSI + PF9 ------> SPI5_MOSI */ HAL_GPIO_DeInit(GPIOF, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9); @@ -811,12 +811,12 @@ void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) /* USER CODE BEGIN TIM5_MspPostInit 0 */ /* USER CODE END TIM5_MspPostInit 0 */ - + __HAL_RCC_GPIOH_CLK_ENABLE(); - /**TIM5 GPIO Configuration + /**TIM5 GPIO Configuration PH10 ------> TIM5_CH1 PH11 ------> TIM5_CH2 - PH12 ------> TIM5_CH3 + PH12 ------> TIM5_CH3 */ GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -905,11 +905,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -945,10 +945,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration + + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); @@ -974,8 +974,8 @@ static void HAL_FMC_MspInit(void){ FMC_Initialized = 1; /* Peripheral clock enable */ __HAL_RCC_FMC_CLK_ENABLE(); - - /** FMC GPIO Configuration + + /** FMC GPIO Configuration PF0 ------> FMC_A0 PF1 ------> FMC_A1 PF2 ------> FMC_A2 @@ -1015,8 +1015,8 @@ static void HAL_FMC_MspInit(void){ PE0 ------> FMC_NBL0 PE1 ------> FMC_NBL1 */ - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 - |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_11|GPIO_PIN_12 + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_11|GPIO_PIN_12 |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -1031,7 +1031,7 @@ static void HAL_FMC_MspInit(void){ GPIO_InitStruct.Alternate = GPIO_AF12_FMC; HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5 + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5 |GPIO_PIN_8|GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -1039,8 +1039,8 @@ static void HAL_FMC_MspInit(void){ GPIO_InitStruct.Alternate = GPIO_AF12_FMC; HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 - |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 + GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 + |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -1055,7 +1055,7 @@ static void HAL_FMC_MspInit(void){ GPIO_InitStruct.Alternate = GPIO_AF12_FMC; HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14 + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14 |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -1090,8 +1090,8 @@ static void HAL_FMC_MspDeInit(void){ FMC_DeInitialized = 1; /* Peripheral clock enable */ __HAL_RCC_FMC_CLK_DISABLE(); - - /** FMC GPIO Configuration + + /** FMC GPIO Configuration PF0 ------> FMC_A0 PF1 ------> FMC_A1 PF2 ------> FMC_A2 @@ -1131,22 +1131,22 @@ static void HAL_FMC_MspDeInit(void){ PE0 ------> FMC_NBL0 PE1 ------> FMC_NBL1 */ - HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 - |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_11|GPIO_PIN_12 + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_11|GPIO_PIN_12 |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15); HAL_GPIO_DeInit(GPIOC, GPIO_PIN_0); - HAL_GPIO_DeInit(GPIOG, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5 + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5 |GPIO_PIN_8|GPIO_PIN_15); - HAL_GPIO_DeInit(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 - |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 + HAL_GPIO_DeInit(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 + |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1); HAL_GPIO_DeInit(GPIOH, GPIO_PIN_6|GPIO_PIN_7); - HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14 + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14 |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1); /* USER CODE BEGIN FMC_MspDeInit 1 */ diff --git a/bsp/stm32/stm32f429-st-disco/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f429-st-disco/board/CubeMX_Config/CubeMX_Config.ioc index 235ba2c905..058533f6dd 100644 --- a/bsp/stm32/stm32f429-st-disco/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32f429-st-disco/board/CubeMX_Config/CubeMX_Config.ioc @@ -194,15 +194,15 @@ PA1.GPIO_ModeDefaultEXTI=GPIO_MODE_EVT_RISING PA1.GPIO_PuPd=GPIO_NOPULL PA1.Locked=true PA1.Signal=GPXTI1 -PA10.GPIOParameters=GPIO_Label +PA10.GPIOParameters=GPIO_Label,GPIO_PuPd PA10.GPIO_Label=STLINK_TX [STM32F103CBT6_PA2] -PA10.Locked=true +PA10.GPIO_PuPd=GPIO_PULLUP PA10.Mode=Asynchronous PA10.Signal=USART1_RX PA11.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode PA11.GPIO_Label=R4 PA11.GPIO_Mode=GPIO_MODE_AF_PP -PA11.GPIO_PuPd=GPIO_NOPULL +PA11.GPIO_PuPd=GPIO_PULLUP PA11.GPIO_Speed=GPIO_SPEED_FREQ_LOW PA11.Locked=true PA11.Mode=RGB565 @@ -210,7 +210,7 @@ PA11.Signal=LTDC_R4 PA12.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode PA12.GPIO_Label=R5 PA12.GPIO_Mode=GPIO_MODE_AF_PP -PA12.GPIO_PuPd=GPIO_NOPULL +PA12.GPIO_PuPd=GPIO_PULLUP PA12.GPIO_Speed=GPIO_SPEED_FREQ_LOW PA12.Locked=true PA12.Mode=RGB565 @@ -276,9 +276,9 @@ PA8.GPIO_Speed=GPIO_SPEED_FREQ_LOW PA8.Locked=true PA8.Mode=I2C PA8.Signal=I2C3_SCL -PA9.GPIOParameters=GPIO_Label +PA9.GPIOParameters=GPIO_Label,GPIO_PULLUP PA9.GPIO_Label=STLINK_RX [STM32F103CBT6_PA3] -PA9.Locked=true +PA9.GPIO_PuPd=GPIO_PULLUP PA9.Mode=Asynchronous PA9.Signal=USART1_TX PB0.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode diff --git a/bsp/stm32/stm32f429-st-disco/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c b/bsp/stm32/stm32f429-st-disco/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c index e4cc442eb3..ca708938e4 100644 --- a/bsp/stm32/stm32f429-st-disco/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c +++ b/bsp/stm32/stm32f429-st-disco/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c @@ -2,7 +2,7 @@ /** ****************************************************************************** * File Name : stm32f4xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** * @attention @@ -32,7 +32,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -187,12 +187,12 @@ void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) /* USER CODE BEGIN I2C3_MspInit 0 */ /* USER CODE END I2C3_MspInit 0 */ - + __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE(); - /**I2C3 GPIO Configuration + /**I2C3 GPIO Configuration PC9 ------> I2C3_SDA - PA8 ------> I2C3_SCL + PA8 ------> I2C3_SCL */ GPIO_InitStruct.Pin = I2C3_SDA_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; @@ -232,10 +232,10 @@ void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c) /* USER CODE END I2C3_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_I2C3_CLK_DISABLE(); - - /**I2C3 GPIO Configuration + + /**I2C3 GPIO Configuration PC9 ------> I2C3_SDA - PA8 ------> I2C3_SCL + PA8 ------> I2C3_SCL */ HAL_GPIO_DeInit(I2C3_SDA_GPIO_Port, I2C3_SDA_Pin); @@ -264,14 +264,14 @@ void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) /* USER CODE END LTDC_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_LTDC_CLK_ENABLE(); - + __HAL_RCC_GPIOF_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOG_CLK_ENABLE(); __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); - /**LTDC GPIO Configuration + /**LTDC GPIO Configuration PF10 ------> LTDC_DE PA3 ------> LTDC_B5 PA4 ------> LTDC_VSYNC @@ -293,7 +293,7 @@ void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) PG11 ------> LTDC_B3 PG12 ------> LTDC_B4 PB8 ------> LTDC_B6 - PB9 ------> LTDC_B7 + PB9 ------> LTDC_B7 */ GPIO_InitStruct.Pin = ENABLE_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -302,7 +302,7 @@ void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; HAL_GPIO_Init(ENABLE_GPIO_Port, &GPIO_InitStruct); - GPIO_InitStruct.Pin = B5_Pin|VSYNC_Pin|G2_Pin|R4_Pin + GPIO_InitStruct.Pin = B5_Pin|VSYNC_Pin|G2_Pin|R4_Pin |R5_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -377,8 +377,8 @@ void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc) /* USER CODE END LTDC_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_LTDC_CLK_DISABLE(); - - /**LTDC GPIO Configuration + + /**LTDC GPIO Configuration PF10 ------> LTDC_DE PA3 ------> LTDC_B5 PA4 ------> LTDC_VSYNC @@ -400,17 +400,17 @@ void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc) PG11 ------> LTDC_B3 PG12 ------> LTDC_B4 PB8 ------> LTDC_B6 - PB9 ------> LTDC_B7 + PB9 ------> LTDC_B7 */ HAL_GPIO_DeInit(ENABLE_GPIO_Port, ENABLE_Pin); - HAL_GPIO_DeInit(GPIOA, B5_Pin|VSYNC_Pin|G2_Pin|R4_Pin + HAL_GPIO_DeInit(GPIOA, B5_Pin|VSYNC_Pin|G2_Pin|R4_Pin |R5_Pin); - HAL_GPIO_DeInit(GPIOB, R3_Pin|R6_Pin|G4_Pin|G5_Pin + HAL_GPIO_DeInit(GPIOB, R3_Pin|R6_Pin|G4_Pin|G5_Pin |B6_Pin|B7_Pin); - HAL_GPIO_DeInit(GPIOG, R7_Pin|DOTCLK_Pin|G3_Pin|B3_Pin + HAL_GPIO_DeInit(GPIOG, R7_Pin|DOTCLK_Pin|G3_Pin|B3_Pin |B4_Pin); HAL_GPIO_DeInit(GPIOC, HSYNC_Pin|G6_Pin|R2_Pin); @@ -442,12 +442,12 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI5_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI5_CLK_ENABLE(); - + __HAL_RCC_GPIOF_CLK_ENABLE(); - /**SPI5 GPIO Configuration + /**SPI5 GPIO Configuration PF7 ------> SPI5_SCK PF8 ------> SPI5_MISO - PF9 ------> SPI5_MOSI + PF9 ------> SPI5_MOSI */ GPIO_InitStruct.Pin = SPI5_SCK_Pin|SPI5_MISO_Pin|SPI5_MOSI_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -478,11 +478,11 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI5_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI5_CLK_DISABLE(); - - /**SPI5 GPIO Configuration + + /**SPI5 GPIO Configuration PF7 ------> SPI5_SCK PF8 ------> SPI5_MISO - PF9 ------> SPI5_MOSI + PF9 ------> SPI5_MOSI */ HAL_GPIO_DeInit(GPIOF, SPI5_SCK_Pin|SPI5_MISO_Pin|SPI5_MOSI_Pin); @@ -553,11 +553,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = STLINK_RX_Pin|STLINK_TX_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -588,10 +588,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration + + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ HAL_GPIO_DeInit(GPIOA, STLINK_RX_Pin|STLINK_TX_Pin); @@ -615,8 +615,8 @@ static void HAL_FMC_MspInit(void){ FMC_Initialized = 1; /* Peripheral clock enable */ __HAL_RCC_FMC_CLK_ENABLE(); - - /** FMC GPIO Configuration + + /** FMC GPIO Configuration PF0 ------> FMC_A0 PF1 ------> FMC_A1 PF2 ------> FMC_A2 @@ -656,8 +656,8 @@ static void HAL_FMC_MspInit(void){ PE0 ------> FMC_NBL0 PE1 ------> FMC_NBL1 */ - GPIO_InitStruct.Pin = A0_Pin|A1_Pin|A2_Pin|A3_Pin - |A4_Pin|A5_Pin|SDNRAS_Pin|A6_Pin + GPIO_InitStruct.Pin = A0_Pin|A1_Pin|A2_Pin|A3_Pin + |A4_Pin|A5_Pin|SDNRAS_Pin|A6_Pin |A7_Pin|A8_Pin|A9_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -672,7 +672,7 @@ static void HAL_FMC_MspInit(void){ GPIO_InitStruct.Alternate = GPIO_AF12_FMC; HAL_GPIO_Init(SDNWE_GPIO_Port, &GPIO_InitStruct); - GPIO_InitStruct.Pin = A10_Pin|A11_Pin|BA0_Pin|BA1_Pin + GPIO_InitStruct.Pin = A10_Pin|A11_Pin|BA0_Pin|BA1_Pin |SDCLK_Pin|SDNCAS_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -680,8 +680,8 @@ static void HAL_FMC_MspInit(void){ GPIO_InitStruct.Alternate = GPIO_AF12_FMC; HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); - GPIO_InitStruct.Pin = D4_Pin|D5_Pin|D6_Pin|D7_Pin - |D8_Pin|D9_Pin|D10_Pin|D11_Pin + GPIO_InitStruct.Pin = D4_Pin|D5_Pin|D6_Pin|D7_Pin + |D8_Pin|D9_Pin|D10_Pin|D11_Pin |D12_Pin|NBL0_Pin|NBL1_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -689,7 +689,7 @@ static void HAL_FMC_MspInit(void){ GPIO_InitStruct.Alternate = GPIO_AF12_FMC; HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); - GPIO_InitStruct.Pin = D13_Pin|D14_Pin|D15_Pin|D0_Pin + GPIO_InitStruct.Pin = D13_Pin|D14_Pin|D15_Pin|D0_Pin |D1_Pin|D2_Pin|D3_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -731,8 +731,8 @@ static void HAL_FMC_MspDeInit(void){ FMC_DeInitialized = 1; /* Peripheral clock enable */ __HAL_RCC_FMC_CLK_DISABLE(); - - /** FMC GPIO Configuration + + /** FMC GPIO Configuration PF0 ------> FMC_A0 PF1 ------> FMC_A1 PF2 ------> FMC_A2 @@ -772,20 +772,20 @@ static void HAL_FMC_MspDeInit(void){ PE0 ------> FMC_NBL0 PE1 ------> FMC_NBL1 */ - HAL_GPIO_DeInit(GPIOF, A0_Pin|A1_Pin|A2_Pin|A3_Pin - |A4_Pin|A5_Pin|SDNRAS_Pin|A6_Pin + HAL_GPIO_DeInit(GPIOF, A0_Pin|A1_Pin|A2_Pin|A3_Pin + |A4_Pin|A5_Pin|SDNRAS_Pin|A6_Pin |A7_Pin|A8_Pin|A9_Pin); HAL_GPIO_DeInit(SDNWE_GPIO_Port, SDNWE_Pin); - HAL_GPIO_DeInit(GPIOG, A10_Pin|A11_Pin|BA0_Pin|BA1_Pin + HAL_GPIO_DeInit(GPIOG, A10_Pin|A11_Pin|BA0_Pin|BA1_Pin |SDCLK_Pin|SDNCAS_Pin); - HAL_GPIO_DeInit(GPIOE, D4_Pin|D5_Pin|D6_Pin|D7_Pin - |D8_Pin|D9_Pin|D10_Pin|D11_Pin + HAL_GPIO_DeInit(GPIOE, D4_Pin|D5_Pin|D6_Pin|D7_Pin + |D8_Pin|D9_Pin|D10_Pin|D11_Pin |D12_Pin|NBL0_Pin|NBL1_Pin); - HAL_GPIO_DeInit(GPIOD, D13_Pin|D14_Pin|D15_Pin|D0_Pin + HAL_GPIO_DeInit(GPIOD, D13_Pin|D14_Pin|D15_Pin|D0_Pin |D1_Pin|D2_Pin|D3_Pin); HAL_GPIO_DeInit(GPIOB, SDCKE1_Pin|SDNE1_Pin); diff --git a/bsp/stm32/stm32f446-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f446-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc index ea2f9755c5..6293374ccd 100644 --- a/bsp/stm32/stm32f446-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32f446-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc @@ -34,14 +34,14 @@ NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false -PA10.Mode=Asynchronous -PA10.Signal=USART1_RX -PA13.Mode=Serial_Wire -PA13.Signal=SYS_JTMS-SWDIO -PA14.Mode=Serial_Wire -PA14.Signal=SYS_JTCK-SWCLK +PA9.GPIOParameters=GPIO_PuPd +PA9.GPIO_PuPd=GPIO_PULLUP PA9.Mode=Asynchronous PA9.Signal=USART1_TX +PA10.GPIOParameters=GPIO_PuPd +PA10.GPIO_PuPd=GPIO_PULLUP +PA10.Mode=Asynchronous +PA10.Signal=USART1_RX PC14-OSC32_IN.Mode=LSE-External-Oscillator PC14-OSC32_IN.Signal=RCC_OSC32_IN PC15-OSC32_OUT.Mode=LSE-External-Oscillator diff --git a/bsp/stm32/stm32f446-st-nucleo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c b/bsp/stm32/stm32f446-st-nucleo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c index a299f50c87..23b216769b 100644 --- a/bsp/stm32/stm32f446-st-nucleo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c +++ b/bsp/stm32/stm32f446-st-nucleo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c @@ -2,12 +2,12 @@ /** ****************************************************************************** * File Name : stm32f4xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** ** This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether + * USER CODE END. Other portions of this file, whether * inserted by the user or by software development tools * are owned by their respective copyright owners. * @@ -52,7 +52,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -114,11 +114,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -151,10 +151,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration + + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); diff --git a/bsp/stm32/stm32f469-st-disco/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f469-st-disco/board/CubeMX_Config/CubeMX_Config.ioc index ba698b848e..3e1042d18c 100644 --- a/bsp/stm32/stm32f469-st-disco/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32f469-st-disco/board/CubeMX_Config/CubeMX_Config.ioc @@ -182,10 +182,12 @@ PA15.GPIOParameters=GPIO_Speed PA15.GPIO_Speed=GPIO_SPEED_FREQ_HIGH PA15.Mode=Half_Duplex_Master PA15.Signal=I2S3_WS -PB10.Locked=true +PB10.GPIOParameters=GPIO_PuPd +PB10.GPIO_PuPd=GPIO_PULLUP PB10.Mode=Asynchronous PB10.Signal=USART3_TX -PB11.Locked=true +PB11.GPIOParameters=GPIO_PuPd +PB11.GPIO_PuPd=GPIO_PULLUP PB11.Mode=Asynchronous PB11.Signal=USART3_RX PB3.GPIOParameters=GPIO_Speed diff --git a/bsp/stm32/stm32f469-st-disco/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c b/bsp/stm32/stm32f469-st-disco/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c index 08cb949966..4c00b2386a 100644 --- a/bsp/stm32/stm32f469-st-disco/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c +++ b/bsp/stm32/stm32f469-st-disco/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c @@ -2,7 +2,7 @@ /** ****************************************************************************** * File Name : stm32f4xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** * @attention @@ -32,7 +32,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -58,7 +58,7 @@ /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ - + void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); /** * Initializes the Global MSP. @@ -227,14 +227,14 @@ void HAL_I2S_MspInit(I2S_HandleTypeDef* hi2s) /* USER CODE END SPI3_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI3_CLK_ENABLE(); - + __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); - /**I2S3 GPIO Configuration + /**I2S3 GPIO Configuration PB3 ------> I2S3_CK PA15 ------> I2S3_WS - PD6 ------> I2S3_SD + PD6 ------> I2S3_SD */ GPIO_InitStruct.Pin = GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -282,11 +282,11 @@ void HAL_I2S_MspDeInit(I2S_HandleTypeDef* hi2s) /* USER CODE END SPI3_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI3_CLK_DISABLE(); - - /**I2S3 GPIO Configuration + + /**I2S3 GPIO Configuration PB3 ------> I2S3_CK PA15 ------> I2S3_WS - PD6 ------> I2S3_SD + PD6 ------> I2S3_SD */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_3); @@ -363,16 +363,16 @@ void HAL_QSPI_MspInit(QSPI_HandleTypeDef* hqspi) /* USER CODE END QUADSPI_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_QSPI_CLK_ENABLE(); - + __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOF_CLK_ENABLE(); - /**QUADSPI GPIO Configuration + /**QUADSPI GPIO Configuration PB6 ------> QUADSPI_BK1_NCS PF7 ------> QUADSPI_BK1_IO2 PF6 ------> QUADSPI_BK1_IO3 PF10 ------> QUADSPI_CLK PF9 ------> QUADSPI_BK1_IO1 - PF8 ------> QUADSPI_BK1_IO0 + PF8 ------> QUADSPI_BK1_IO0 */ GPIO_InitStruct.Pin = GPIO_PIN_6; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -417,18 +417,18 @@ void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef* hqspi) /* USER CODE END QUADSPI_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_QSPI_CLK_DISABLE(); - - /**QUADSPI GPIO Configuration + + /**QUADSPI GPIO Configuration PB6 ------> QUADSPI_BK1_NCS PF7 ------> QUADSPI_BK1_IO2 PF6 ------> QUADSPI_BK1_IO3 PF10 ------> QUADSPI_CLK PF9 ------> QUADSPI_BK1_IO1 - PF8 ------> QUADSPI_BK1_IO0 + PF8 ------> QUADSPI_BK1_IO0 */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6); - HAL_GPIO_DeInit(GPIOF, GPIO_PIN_7|GPIO_PIN_6|GPIO_PIN_10|GPIO_PIN_9 + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_7|GPIO_PIN_6|GPIO_PIN_10|GPIO_PIN_9 |GPIO_PIN_8); /* USER CODE BEGIN QUADSPI_MspDeInit 1 */ @@ -454,18 +454,18 @@ void HAL_SD_MspInit(SD_HandleTypeDef* hsd) /* USER CODE END SDIO_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SDIO_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); - /**SDIO GPIO Configuration + /**SDIO GPIO Configuration PC12 ------> SDIO_CK PC11 ------> SDIO_D3 PC10 ------> SDIO_D2 PD2 ------> SDIO_CMD PC9 ------> SDIO_D1 - PC8 ------> SDIO_D0 + PC8 ------> SDIO_D0 */ - GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_9 + GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_9 |GPIO_PIN_8; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -502,16 +502,16 @@ void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) /* USER CODE END SDIO_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SDIO_CLK_DISABLE(); - - /**SDIO GPIO Configuration + + /**SDIO GPIO Configuration PC12 ------> SDIO_CK PC11 ------> SDIO_D3 PC10 ------> SDIO_D2 PD2 ------> SDIO_CMD PC9 ------> SDIO_D1 - PC8 ------> SDIO_D0 + PC8 ------> SDIO_D0 */ - HAL_GPIO_DeInit(GPIOC, GPIO_PIN_12|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_9 + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_12|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_9 |GPIO_PIN_8); HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); @@ -539,10 +539,10 @@ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) /* USER CODE END TIM4_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM4_CLK_ENABLE(); - + __HAL_RCC_GPIOD_CLK_ENABLE(); - /**TIM4 GPIO Configuration - PD12 ------> TIM4_CH1 + /**TIM4 GPIO Configuration + PD12 ------> TIM4_CH1 */ GPIO_InitStruct.Pin = GPIO_PIN_12; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -566,10 +566,10 @@ void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) /* USER CODE BEGIN TIM4_MspPostInit 0 */ /* USER CODE END TIM4_MspPostInit 0 */ - + __HAL_RCC_GPIOD_CLK_ENABLE(); - /**TIM4 GPIO Configuration - PD13 ------> TIM4_CH2 + /**TIM4 GPIO Configuration + PD13 ------> TIM4_CH2 */ GPIO_InitStruct.Pin = GPIO_PIN_13; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -599,10 +599,10 @@ void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base) /* USER CODE END TIM4_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_TIM4_CLK_DISABLE(); - - /**TIM4 GPIO Configuration + + /**TIM4 GPIO Configuration PD12 ------> TIM4_CH1 - PD13 ------> TIM4_CH2 + PD13 ------> TIM4_CH2 */ HAL_GPIO_DeInit(GPIOD, GPIO_PIN_12|GPIO_PIN_13); @@ -629,11 +629,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART3_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART3_CLK_ENABLE(); - + __HAL_RCC_GPIOB_CLK_ENABLE(); - /**USART3 GPIO Configuration + /**USART3 GPIO Configuration PB10 ------> USART3_TX - PB11 ------> USART3_RX + PB11 ------> USART3_RX */ GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -664,10 +664,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART3_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART3_CLK_DISABLE(); - - /**USART3 GPIO Configuration + + /**USART3 GPIO Configuration PB10 ------> USART3_TX - PB11 ------> USART3_RX + PB11 ------> USART3_RX */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_10|GPIO_PIN_11); @@ -692,11 +692,11 @@ void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd) /* USER CODE BEGIN USB_OTG_FS_MspInit 0 */ /* USER CODE END USB_OTG_FS_MspInit 0 */ - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USB_OTG_FS GPIO Configuration + /**USB_OTG_FS GPIO Configuration PA12 ------> USB_OTG_FS_DP - PA11 ------> USB_OTG_FS_DM + PA11 ------> USB_OTG_FS_DM */ GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_11; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -732,10 +732,10 @@ void HAL_PCD_MspDeInit(PCD_HandleTypeDef* hpcd) /* USER CODE END USB_OTG_FS_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USB_OTG_FS_CLK_DISABLE(); - - /**USB_OTG_FS GPIO Configuration + + /**USB_OTG_FS GPIO Configuration PA12 ------> USB_OTG_FS_DP - PA11 ------> USB_OTG_FS_DM + PA11 ------> USB_OTG_FS_DM */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_12|GPIO_PIN_11); @@ -761,8 +761,8 @@ static void HAL_FMC_MspInit(void){ FMC_Initialized = 1; /* Peripheral clock enable */ __HAL_RCC_FMC_CLK_ENABLE(); - - /** FMC GPIO Configuration + + /** FMC GPIO Configuration PE1 ------> FMC_NBL1 PE0 ------> FMC_NBL0 PG15 ------> FMC_SDNCAS @@ -820,8 +820,8 @@ static void HAL_FMC_MspInit(void){ PE15 ------> FMC_D12 PE13 ------> FMC_D10 */ - GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_8|GPIO_PIN_9 - |GPIO_PIN_11|GPIO_PIN_14|GPIO_PIN_7|GPIO_PIN_10 + GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_8|GPIO_PIN_9 + |GPIO_PIN_11|GPIO_PIN_14|GPIO_PIN_7|GPIO_PIN_10 |GPIO_PIN_12|GPIO_PIN_15|GPIO_PIN_13; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -829,7 +829,7 @@ static void HAL_FMC_MspInit(void){ GPIO_InitStruct.Alternate = GPIO_AF12_FMC; HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_15|GPIO_PIN_8|GPIO_PIN_1|GPIO_PIN_0 + GPIO_InitStruct.Pin = GPIO_PIN_15|GPIO_PIN_8|GPIO_PIN_1|GPIO_PIN_0 |GPIO_PIN_5|GPIO_PIN_4; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -837,7 +837,7 @@ static void HAL_FMC_MspInit(void){ GPIO_InitStruct.Alternate = GPIO_AF12_FMC; HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_15|GPIO_PIN_10 + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_15|GPIO_PIN_10 |GPIO_PIN_14|GPIO_PIN_9|GPIO_PIN_8; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -845,8 +845,8 @@ static void HAL_FMC_MspInit(void){ GPIO_InitStruct.Alternate = GPIO_AF12_FMC; HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_3|GPIO_PIN_2|GPIO_PIN_5 - |GPIO_PIN_7|GPIO_PIN_10|GPIO_PIN_6|GPIO_PIN_1 + GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_3|GPIO_PIN_2|GPIO_PIN_5 + |GPIO_PIN_7|GPIO_PIN_10|GPIO_PIN_6|GPIO_PIN_1 |GPIO_PIN_9|GPIO_PIN_0; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -854,8 +854,8 @@ static void HAL_FMC_MspInit(void){ GPIO_InitStruct.Alternate = GPIO_AF12_FMC; HAL_GPIO_Init(GPIOI, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 - |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_15 + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_15 |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_11; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -863,8 +863,8 @@ static void HAL_FMC_MspInit(void){ GPIO_InitStruct.Alternate = GPIO_AF12_FMC; HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_15|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_3 - |GPIO_PIN_2|GPIO_PIN_12|GPIO_PIN_9|GPIO_PIN_11 + GPIO_InitStruct.Pin = GPIO_PIN_15|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_3 + |GPIO_PIN_2|GPIO_PIN_12|GPIO_PIN_9|GPIO_PIN_11 |GPIO_PIN_8|GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -906,8 +906,8 @@ static void HAL_FMC_MspDeInit(void){ FMC_DeInitialized = 1; /* Peripheral clock enable */ __HAL_RCC_FMC_CLK_DISABLE(); - - /** FMC GPIO Configuration + + /** FMC GPIO Configuration PE1 ------> FMC_NBL1 PE0 ------> FMC_NBL0 PG15 ------> FMC_SDNCAS @@ -965,26 +965,26 @@ static void HAL_FMC_MspDeInit(void){ PE15 ------> FMC_D12 PE13 ------> FMC_D10 */ - HAL_GPIO_DeInit(GPIOE, GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_8|GPIO_PIN_9 - |GPIO_PIN_11|GPIO_PIN_14|GPIO_PIN_7|GPIO_PIN_10 + HAL_GPIO_DeInit(GPIOE, GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_8|GPIO_PIN_9 + |GPIO_PIN_11|GPIO_PIN_14|GPIO_PIN_7|GPIO_PIN_10 |GPIO_PIN_12|GPIO_PIN_15|GPIO_PIN_13); - HAL_GPIO_DeInit(GPIOG, GPIO_PIN_15|GPIO_PIN_8|GPIO_PIN_1|GPIO_PIN_0 + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_15|GPIO_PIN_8|GPIO_PIN_1|GPIO_PIN_0 |GPIO_PIN_5|GPIO_PIN_4); - HAL_GPIO_DeInit(GPIOD, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_15|GPIO_PIN_10 + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_15|GPIO_PIN_10 |GPIO_PIN_14|GPIO_PIN_9|GPIO_PIN_8); - HAL_GPIO_DeInit(GPIOI, GPIO_PIN_4|GPIO_PIN_3|GPIO_PIN_2|GPIO_PIN_5 - |GPIO_PIN_7|GPIO_PIN_10|GPIO_PIN_6|GPIO_PIN_1 + HAL_GPIO_DeInit(GPIOI, GPIO_PIN_4|GPIO_PIN_3|GPIO_PIN_2|GPIO_PIN_5 + |GPIO_PIN_7|GPIO_PIN_10|GPIO_PIN_6|GPIO_PIN_1 |GPIO_PIN_9|GPIO_PIN_0); - HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 - |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_15 + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_15 |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_11); - HAL_GPIO_DeInit(GPIOH, GPIO_PIN_15|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_3 - |GPIO_PIN_2|GPIO_PIN_12|GPIO_PIN_9|GPIO_PIN_11 + HAL_GPIO_DeInit(GPIOH, GPIO_PIN_15|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_3 + |GPIO_PIN_2|GPIO_PIN_12|GPIO_PIN_9|GPIO_PIN_11 |GPIO_PIN_8|GPIO_PIN_10); HAL_GPIO_DeInit(GPIOC, GPIO_PIN_0); diff --git a/bsp/stm32/stm32f746-st-disco/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f746-st-disco/board/CubeMX_Config/CubeMX_Config.ioc index 3813651ece..148a2ca783 100644 --- a/bsp/stm32/stm32f746-st-disco/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32f746-st-disco/board/CubeMX_Config/CubeMX_Config.ioc @@ -142,15 +142,18 @@ PA2.Mode=RMII PA2.Signal=ETH_MDIO PA7.Mode=RMII PA7.Signal=ETH_CRS_DV -PA9.Locked=true +PA9.GPIOParameters=GPIO_PuPd +PA9.GPIO_PuPd=GPIO_PULLUP PA9.Mode=Asynchronous PA9.Signal=USART1_TX +PB7.GPIOParameters=GPIO_PuPd +PB7.GPIO_PuPd=GPIO_PULLUP +PB7.Mode=Asynchronous +PB7.Signal=USART1_RX PB2.Mode=Single Bank 1 PB2.Signal=QUADSPI_CLK PB6.Mode=Single Bank 1 PB6.Signal=QUADSPI_BK1_NCS -PB7.Mode=Asynchronous -PB7.Signal=USART1_RX PC1.Mode=RMII PC1.Signal=ETH_MDC PC10.Mode=SD_4_bits_Wide_bus diff --git a/bsp/stm32/stm32f746-st-disco/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c b/bsp/stm32/stm32f746-st-disco/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c index fd77b00626..8f4696a1d7 100644 --- a/bsp/stm32/stm32f746-st-disco/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c +++ b/bsp/stm32/stm32f746-st-disco/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c @@ -2,12 +2,12 @@ /** ****************************************************************************** * File Name : stm32f7xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** ** This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether + * USER CODE END. Other portions of this file, whether * inserted by the user or by software development tools * are owned by their respective copyright owners. * @@ -52,7 +52,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -113,11 +113,11 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) /* USER CODE END ETH_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_ETH_CLK_ENABLE(); - + __HAL_RCC_GPIOG_CLK_ENABLE(); __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE(); - /**ETH GPIO Configuration + /**ETH GPIO Configuration PG14 ------> ETH_TXD1 PG13 ------> ETH_TXD0 PG11 ------> ETH_TX_EN @@ -126,7 +126,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) PC4 ------> ETH_RXD0 PA2 ------> ETH_MDIO PC5 ------> ETH_RXD1 - PA7 ------> ETH_CRS_DV + PA7 ------> ETH_CRS_DV */ GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_13|GPIO_PIN_11; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -171,8 +171,8 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) /* USER CODE END ETH_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_ETH_CLK_DISABLE(); - - /**ETH GPIO Configuration + + /**ETH GPIO Configuration PG14 ------> ETH_TXD1 PG13 ------> ETH_TXD0 PG11 ------> ETH_TX_EN @@ -181,7 +181,7 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) PC4 ------> ETH_RXD0 PA2 ------> ETH_MDIO PC5 ------> ETH_RXD1 - PA7 ------> ETH_CRS_DV + PA7 ------> ETH_CRS_DV */ HAL_GPIO_DeInit(GPIOG, GPIO_PIN_14|GPIO_PIN_13|GPIO_PIN_11); @@ -212,13 +212,13 @@ void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) /* USER CODE END LTDC_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_LTDC_CLK_ENABLE(); - + __HAL_RCC_GPIOE_CLK_ENABLE(); __HAL_RCC_GPIOJ_CLK_ENABLE(); __HAL_RCC_GPIOK_CLK_ENABLE(); __HAL_RCC_GPIOG_CLK_ENABLE(); __HAL_RCC_GPIOI_CLK_ENABLE(); - /**LTDC GPIO Configuration + /**LTDC GPIO Configuration PE4 ------> LTDC_B0 PJ13 ------> LTDC_B1 PK7 ------> LTDC_DE @@ -246,7 +246,7 @@ void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) PJ3 ------> LTDC_R4 PJ2 ------> LTDC_R3 PJ0 ------> LTDC_R1 - PJ1 ------> LTDC_R2 + PJ1 ------> LTDC_R2 */ GPIO_InitStruct.Pin = GPIO_PIN_4; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -255,9 +255,9 @@ void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15|GPIO_PIN_11 - |GPIO_PIN_8|GPIO_PIN_10|GPIO_PIN_7|GPIO_PIN_9 - |GPIO_PIN_6|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_3 + GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15|GPIO_PIN_11 + |GPIO_PIN_8|GPIO_PIN_10|GPIO_PIN_7|GPIO_PIN_9 + |GPIO_PIN_6|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_3 |GPIO_PIN_2|GPIO_PIN_0|GPIO_PIN_1; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -265,7 +265,7 @@ void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; HAL_GPIO_Init(GPIOJ, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_6|GPIO_PIN_5|GPIO_PIN_4 + GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_6|GPIO_PIN_5|GPIO_PIN_4 |GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_0; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -309,8 +309,8 @@ void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc) /* USER CODE END LTDC_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_LTDC_CLK_DISABLE(); - - /**LTDC GPIO Configuration + + /**LTDC GPIO Configuration PE4 ------> LTDC_B0 PJ13 ------> LTDC_B1 PK7 ------> LTDC_DE @@ -338,16 +338,16 @@ void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc) PJ3 ------> LTDC_R4 PJ2 ------> LTDC_R3 PJ0 ------> LTDC_R1 - PJ1 ------> LTDC_R2 + PJ1 ------> LTDC_R2 */ HAL_GPIO_DeInit(GPIOE, GPIO_PIN_4); - HAL_GPIO_DeInit(GPIOJ, GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15|GPIO_PIN_11 - |GPIO_PIN_8|GPIO_PIN_10|GPIO_PIN_7|GPIO_PIN_9 - |GPIO_PIN_6|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_3 + HAL_GPIO_DeInit(GPIOJ, GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15|GPIO_PIN_11 + |GPIO_PIN_8|GPIO_PIN_10|GPIO_PIN_7|GPIO_PIN_9 + |GPIO_PIN_6|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_3 |GPIO_PIN_2|GPIO_PIN_0|GPIO_PIN_1); - HAL_GPIO_DeInit(GPIOK, GPIO_PIN_7|GPIO_PIN_6|GPIO_PIN_5|GPIO_PIN_4 + HAL_GPIO_DeInit(GPIOK, GPIO_PIN_7|GPIO_PIN_6|GPIO_PIN_5|GPIO_PIN_4 |GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_0); HAL_GPIO_DeInit(GPIOG, GPIO_PIN_12); @@ -377,17 +377,17 @@ void HAL_QSPI_MspInit(QSPI_HandleTypeDef* hqspi) /* USER CODE END QUADSPI_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_QSPI_CLK_ENABLE(); - + __HAL_RCC_GPIOE_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); - /**QUADSPI GPIO Configuration + /**QUADSPI GPIO Configuration PE2 ------> QUADSPI_BK1_IO2 PB6 ------> QUADSPI_BK1_NCS PB2 ------> QUADSPI_CLK PD12 ------> QUADSPI_BK1_IO1 PD13 ------> QUADSPI_BK1_IO3 - PD11 ------> QUADSPI_BK1_IO0 + PD11 ------> QUADSPI_BK1_IO0 */ GPIO_InitStruct.Pin = GPIO_PIN_2; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -439,14 +439,14 @@ void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef* hqspi) /* USER CODE END QUADSPI_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_QSPI_CLK_DISABLE(); - - /**QUADSPI GPIO Configuration + + /**QUADSPI GPIO Configuration PE2 ------> QUADSPI_BK1_IO2 PB6 ------> QUADSPI_BK1_NCS PB2 ------> QUADSPI_CLK PD12 ------> QUADSPI_BK1_IO1 PD13 ------> QUADSPI_BK1_IO3 - PD11 ------> QUADSPI_BK1_IO0 + PD11 ------> QUADSPI_BK1_IO0 */ HAL_GPIO_DeInit(GPIOE, GPIO_PIN_2); @@ -477,18 +477,18 @@ void HAL_SD_MspInit(SD_HandleTypeDef* hsd) /* USER CODE END SDMMC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SDMMC1_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); - /**SDMMC1 GPIO Configuration + /**SDMMC1 GPIO Configuration PC12 ------> SDMMC1_CK PC11 ------> SDMMC1_D3 PC10 ------> SDMMC1_D2 PD2 ------> SDMMC1_CMD PC9 ------> SDMMC1_D1 - PC8 ------> SDMMC1_D0 + PC8 ------> SDMMC1_D0 */ - GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_9 + GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_9 |GPIO_PIN_8; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -525,16 +525,16 @@ void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) /* USER CODE END SDMMC1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SDMMC1_CLK_DISABLE(); - - /**SDMMC1 GPIO Configuration + + /**SDMMC1 GPIO Configuration PC12 ------> SDMMC1_CK PC11 ------> SDMMC1_D3 PC10 ------> SDMMC1_D2 PD2 ------> SDMMC1_CMD PC9 ------> SDMMC1_D1 - PC8 ------> SDMMC1_D0 + PC8 ------> SDMMC1_D0 */ - HAL_GPIO_DeInit(GPIOC, GPIO_PIN_12|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_9 + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_12|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_9 |GPIO_PIN_8); HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); @@ -606,23 +606,23 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - + __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PB7 ------> USART1_RX - PA9 ------> USART1_TX + PA9 ------> USART1_TX */ GPIO_InitStruct.Pin = GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF7_USART1; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); GPIO_InitStruct.Pin = GPIO_PIN_9; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF7_USART1; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); @@ -649,10 +649,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration + + /**USART1 GPIO Configuration PB7 ------> USART1_RX - PA9 ------> USART1_TX + PA9 ------> USART1_TX */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_7); @@ -678,8 +678,8 @@ static void HAL_FMC_MspInit(void){ FMC_Initialized = 1; /* Peripheral clock enable */ __HAL_RCC_FMC_CLK_ENABLE(); - - /** FMC GPIO Configuration + + /** FMC GPIO Configuration PG15 ------> FMC_SDNCAS PD0 ------> FMC_D2 PD1 ------> FMC_D3 @@ -771,8 +771,8 @@ static void HAL_FMC_MspDeInit(void){ FMC_DeInitialized = 1; /* Peripheral clock enable */ __HAL_RCC_FMC_CLK_DISABLE(); - - /** FMC GPIO Configuration + + /** FMC GPIO Configuration PG15 ------> FMC_SDNCAS PD0 ------> FMC_D2 PD1 ------> FMC_D3 @@ -809,22 +809,22 @@ static void HAL_FMC_MspDeInit(void){ PE15 ------> FMC_D12 PE13 ------> FMC_D10 */ - HAL_GPIO_DeInit(GPIOG, GPIO_PIN_15|GPIO_PIN_8|GPIO_PIN_0|GPIO_PIN_5 + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_15|GPIO_PIN_8|GPIO_PIN_0|GPIO_PIN_5 |GPIO_PIN_4); - HAL_GPIO_DeInit(GPIOD, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_15|GPIO_PIN_10 + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_15|GPIO_PIN_10 |GPIO_PIN_14|GPIO_PIN_9|GPIO_PIN_8); - HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 - |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_15 + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_15 |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_11); HAL_GPIO_DeInit(GPIOH, GPIO_PIN_5|GPIO_PIN_3); HAL_GPIO_DeInit(GPIOC, GPIO_PIN_3); - HAL_GPIO_DeInit(GPIOE, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_11|GPIO_PIN_14 - |GPIO_PIN_7|GPIO_PIN_10|GPIO_PIN_12|GPIO_PIN_15 + HAL_GPIO_DeInit(GPIOE, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_11|GPIO_PIN_14 + |GPIO_PIN_7|GPIO_PIN_10|GPIO_PIN_12|GPIO_PIN_15 |GPIO_PIN_13); /* USER CODE BEGIN FMC_MspDeInit 1 */ diff --git a/bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/CubeMX_Config.ioc index 506854c422..e1b152b6e1 100644 --- a/bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/CubeMX_Config.ioc @@ -161,7 +161,12 @@ NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false PA1.Mode=RMII PA1.Signal=ETH_REF_CLK -PA10.Locked=true +PA9.GPIOParameters=GPIO_PuPd +PA9.GPIO_PuPd=GPIO_PULLUP +PA9.Mode=Asynchronous +PA9.Signal=USART1_TX +PA10.GPIOParameters=GPIO_PuPd +PA10.GPIO_PuPd=GPIO_PULLUP PA10.Mode=Asynchronous PA10.Signal=USART1_RX PA11.Mode=Host_Only @@ -182,9 +187,6 @@ PA7.Mode=RMII PA7.Signal=ETH_CRS_DV PA8.Mode=RGB565 PA8.Signal=LTDC_B3 -PA9.Locked=true -PA9.Mode=Asynchronous -PA9.Signal=USART1_TX PB0.Locked=true PB0.Signal=S_TIM3_CH3 PB1.Mode=RGB565 diff --git a/bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c b/bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c index 3fe29e92c9..988628d3d8 100644 --- a/bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c +++ b/bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c @@ -2,12 +2,12 @@ /** ****************************************************************************** * File Name : stm32f7xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** ** This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether + * USER CODE END. Other portions of this file, whether * inserted by the user or by software development tools * are owned by their respective copyright owners. * @@ -52,7 +52,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -78,7 +78,7 @@ /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ - + void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); /** * Initializes the Global MSP. @@ -115,10 +115,10 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) /* USER CODE END ADC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_ADC1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**ADC1 GPIO Configuration - PA5 ------> ADC1_IN5 + /**ADC1 GPIO Configuration + PA5 ------> ADC1_IN5 */ GPIO_InitStruct.Pin = GPIO_PIN_5; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; @@ -147,9 +147,9 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) /* USER CODE END ADC1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_ADC1_CLK_DISABLE(); - - /**ADC1 GPIO Configuration - PA5 ------> ADC1_IN5 + + /**ADC1 GPIO Configuration + PA5 ------> ADC1_IN5 */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5); @@ -176,12 +176,12 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) /* USER CODE END ETH_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_ETH_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOG_CLK_ENABLE(); - /**ETH GPIO Configuration + /**ETH GPIO Configuration PC1 ------> ETH_MDC PA1 ------> ETH_REF_CLK PA2 ------> ETH_MDIO @@ -190,7 +190,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) PC5 ------> ETH_RXD1 PB11 ------> ETH_TX_EN PG13 ------> ETH_TXD0 - PG14 ------> ETH_TXD1 + PG14 ------> ETH_TXD1 */ GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -242,8 +242,8 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) /* USER CODE END ETH_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_ETH_CLK_DISABLE(); - - /**ETH GPIO Configuration + + /**ETH GPIO Configuration PC1 ------> ETH_MDC PA1 ------> ETH_REF_CLK PA2 ------> ETH_MDIO @@ -252,7 +252,7 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) PC5 ------> ETH_RXD1 PB11 ------> ETH_TX_EN PG13 ------> ETH_TXD0 - PG14 ------> ETH_TXD1 + PG14 ------> ETH_TXD1 */ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5); @@ -285,14 +285,14 @@ void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) /* USER CODE END LTDC_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_LTDC_CLK_ENABLE(); - + __HAL_RCC_GPIOI_CLK_ENABLE(); __HAL_RCC_GPIOF_CLK_ENABLE(); __HAL_RCC_GPIOH_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOG_CLK_ENABLE(); - /**LTDC GPIO Configuration + /**LTDC GPIO Configuration PI9 ------> LTDC_VSYNC PI10 ------> LTDC_HSYNC PI11 ------> LTDC_G6 @@ -312,7 +312,7 @@ void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) PG12 ------> LTDC_B4 PB8 ------> LTDC_B6 PB9 ------> LTDC_B7 - PI5 ------> LTDC_B5 + PI5 ------> LTDC_B5 */ GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_2|GPIO_PIN_5; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -413,8 +413,8 @@ void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc) /* USER CODE END LTDC_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_LTDC_CLK_DISABLE(); - - /**LTDC GPIO Configuration + + /**LTDC GPIO Configuration PI9 ------> LTDC_VSYNC PI10 ------> LTDC_HSYNC PI11 ------> LTDC_G6 @@ -434,14 +434,14 @@ void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc) PG12 ------> LTDC_B4 PB8 ------> LTDC_B6 PB9 ------> LTDC_B7 - PI5 ------> LTDC_B5 + PI5 ------> LTDC_B5 */ - HAL_GPIO_DeInit(GPIOI, GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_2 + HAL_GPIO_DeInit(GPIOI, GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_2 |GPIO_PIN_5); HAL_GPIO_DeInit(GPIOF, GPIO_PIN_10); - HAL_GPIO_DeInit(GPIOH, GPIO_PIN_4|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + HAL_GPIO_DeInit(GPIOH, GPIO_PIN_4|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 |GPIO_PIN_14); HAL_GPIO_DeInit(GPIOA, GPIO_PIN_6|GPIO_PIN_8); @@ -473,16 +473,16 @@ void HAL_QSPI_MspInit(QSPI_HandleTypeDef* hqspi) /* USER CODE END QUADSPI_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_QSPI_CLK_ENABLE(); - + __HAL_RCC_GPIOF_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); - /**QUADSPI GPIO Configuration + /**QUADSPI GPIO Configuration PF6 ------> QUADSPI_BK1_IO3 PF7 ------> QUADSPI_BK1_IO2 PF8 ------> QUADSPI_BK1_IO0 PF9 ------> QUADSPI_BK1_IO1 PB2 ------> QUADSPI_CLK - PB6 ------> QUADSPI_BK1_NCS + PB6 ------> QUADSPI_BK1_NCS */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -534,14 +534,14 @@ void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef* hqspi) /* USER CODE END QUADSPI_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_QSPI_CLK_DISABLE(); - - /**QUADSPI GPIO Configuration + + /**QUADSPI GPIO Configuration PF6 ------> QUADSPI_BK1_IO3 PF7 ------> QUADSPI_BK1_IO2 PF8 ------> QUADSPI_BK1_IO0 PF9 ------> QUADSPI_BK1_IO1 PB2 ------> QUADSPI_CLK - PB6 ------> QUADSPI_BK1_NCS + PB6 ------> QUADSPI_BK1_NCS */ HAL_GPIO_DeInit(GPIOF, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9); @@ -614,18 +614,18 @@ void HAL_SD_MspInit(SD_HandleTypeDef* hsd) /* USER CODE END SDMMC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SDMMC1_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); - /**SDMMC1 GPIO Configuration + /**SDMMC1 GPIO Configuration PC8 ------> SDMMC1_D0 PC9 ------> SDMMC1_D1 PC10 ------> SDMMC1_D2 PC11 ------> SDMMC1_D3 PC12 ------> SDMMC1_CK - PD2 ------> SDMMC1_CMD + PD2 ------> SDMMC1_CMD */ - GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 |GPIO_PIN_12; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -662,16 +662,16 @@ void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) /* USER CODE END SDMMC1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SDMMC1_CLK_DISABLE(); - - /**SDMMC1 GPIO Configuration + + /**SDMMC1 GPIO Configuration PC8 ------> SDMMC1_D0 PC9 ------> SDMMC1_D1 PC10 ------> SDMMC1_D2 PC11 ------> SDMMC1_D3 PC12 ------> SDMMC1_CK - PD2 ------> SDMMC1_CMD + PD2 ------> SDMMC1_CMD */ - HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 |GPIO_PIN_12); HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); @@ -699,12 +699,12 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI2_CLK_ENABLE(); - + __HAL_RCC_GPIOB_CLK_ENABLE(); - /**SPI2 GPIO Configuration + /**SPI2 GPIO Configuration PB13 ------> SPI2_SCK PB14 ------> SPI2_MISO - PB15 ------> SPI2_MOSI + PB15 ------> SPI2_MOSI */ GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -735,11 +735,11 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI2_CLK_DISABLE(); - - /**SPI2 GPIO Configuration + + /**SPI2 GPIO Configuration PB13 ------> SPI2_SCK PB14 ------> SPI2_MISO - PB15 ------> SPI2_MOSI + PB15 ------> SPI2_MOSI */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15); @@ -836,8 +836,8 @@ void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) /* USER CODE END TIM2_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); - /**TIM2 GPIO Configuration - PA3 ------> TIM2_CH4 + /**TIM2 GPIO Configuration + PA3 ------> TIM2_CH4 */ GPIO_InitStruct.Pin = GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -855,10 +855,10 @@ void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) /* USER CODE BEGIN TIM3_MspPostInit 0 */ /* USER CODE END TIM3_MspPostInit 0 */ - + __HAL_RCC_GPIOB_CLK_ENABLE(); - /**TIM3 GPIO Configuration - PB0 ------> TIM3_CH3 + /**TIM3 GPIO Configuration + PB0 ------> TIM3_CH3 */ GPIO_InitStruct.Pin = GPIO_PIN_0; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -966,15 +966,15 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF7_USART1; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); @@ -990,15 +990,15 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); - + __HAL_RCC_GPIOD_CLK_ENABLE(); - /**USART2 GPIO Configuration + /**USART2 GPIO Configuration PD5 ------> USART2_TX - PD6 ------> USART2_RX + PD6 ------> USART2_RX */ GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF7_USART2; HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); @@ -1025,10 +1025,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration + + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); @@ -1043,10 +1043,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART2_CLK_DISABLE(); - - /**USART2 GPIO Configuration + + /**USART2 GPIO Configuration PD5 ------> USART2_TX - PD6 ------> USART2_RX + PD6 ------> USART2_RX */ HAL_GPIO_DeInit(GPIOD, GPIO_PIN_5|GPIO_PIN_6); @@ -1071,11 +1071,11 @@ void HAL_HCD_MspInit(HCD_HandleTypeDef* hhcd) /* USER CODE BEGIN USB_OTG_FS_MspInit 0 */ /* USER CODE END USB_OTG_FS_MspInit 0 */ - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USB_OTG_FS GPIO Configuration + /**USB_OTG_FS GPIO Configuration PA11 ------> USB_OTG_FS_DM - PA12 ------> USB_OTG_FS_DP + PA12 ------> USB_OTG_FS_DP */ GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -1111,10 +1111,10 @@ void HAL_HCD_MspDeInit(HCD_HandleTypeDef* hhcd) /* USER CODE END USB_OTG_FS_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USB_OTG_FS_CLK_DISABLE(); - - /**USB_OTG_FS GPIO Configuration + + /**USB_OTG_FS GPIO Configuration PA11 ------> USB_OTG_FS_DM - PA12 ------> USB_OTG_FS_DP + PA12 ------> USB_OTG_FS_DP */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11|GPIO_PIN_12); @@ -1140,8 +1140,8 @@ static void HAL_FMC_MspInit(void){ FMC_Initialized = 1; /* Peripheral clock enable */ __HAL_RCC_FMC_CLK_ENABLE(); - - /** FMC GPIO Configuration + + /** FMC GPIO Configuration PF0 ------> FMC_A0 PF1 ------> FMC_A1 PF2 ------> FMC_A2 @@ -1180,8 +1180,8 @@ static void HAL_FMC_MspInit(void){ PD1 ------> FMC_D3 PG15 ------> FMC_SDNCAS */ - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 - |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_11|GPIO_PIN_12 + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_11|GPIO_PIN_12 |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -1196,7 +1196,7 @@ static void HAL_FMC_MspInit(void){ GPIO_InitStruct.Alternate = GPIO_AF12_FMC; HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_4 + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_4 |GPIO_PIN_5|GPIO_PIN_8|GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -1204,8 +1204,8 @@ static void HAL_FMC_MspInit(void){ GPIO_InitStruct.Alternate = GPIO_AF12_FMC; HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 - |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 + GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 + |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 |GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -1213,7 +1213,7 @@ static void HAL_FMC_MspInit(void){ GPIO_InitStruct.Alternate = GPIO_AF12_FMC; HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14 + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14 |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -1248,8 +1248,8 @@ static void HAL_FMC_MspDeInit(void){ FMC_DeInitialized = 1; /* Peripheral clock enable */ __HAL_RCC_FMC_CLK_DISABLE(); - - /** FMC GPIO Configuration + + /** FMC GPIO Configuration PF0 ------> FMC_A0 PF1 ------> FMC_A1 PF2 ------> FMC_A2 @@ -1288,20 +1288,20 @@ static void HAL_FMC_MspDeInit(void){ PD1 ------> FMC_D3 PG15 ------> FMC_SDNCAS */ - HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 - |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_11|GPIO_PIN_12 + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_11|GPIO_PIN_12 |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15); HAL_GPIO_DeInit(GPIOC, GPIO_PIN_0|GPIO_PIN_2|GPIO_PIN_3); - HAL_GPIO_DeInit(GPIOG, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_4 + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_4 |GPIO_PIN_5|GPIO_PIN_8|GPIO_PIN_15); - HAL_GPIO_DeInit(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 - |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 + HAL_GPIO_DeInit(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 + |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 |GPIO_PIN_15); - HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14 + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14 |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1); /* USER CODE BEGIN FMC_MspDeInit 1 */ diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/CubeMX_Config.ioc index c9b386e6ca..bc1a38ca7c 100644 --- a/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/CubeMX_Config.ioc @@ -138,7 +138,12 @@ NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false PA1.Mode=RMII PA1.Signal=ETH_REF_CLK -PA10.Locked=true +PA9.GPIOParameters=GPIO_PuPd +PA9.GPIO_PuPd=GPIO_PULLUP +PA9.Mode=Asynchronous +PA9.Signal=USART1_TX +PA10.GPIOParameters=GPIO_PuPd +PA10.GPIO_PuPd=GPIO_PULLUP PA10.Mode=Asynchronous PA10.Signal=USART1_RX PA11.GPIOParameters=GPIO_Speed @@ -160,9 +165,6 @@ PA3.Signal=LTDC_B5 PA5.Signal=ADCx_IN5 PA7.Mode=RMII PA7.Signal=ETH_CRS_DV -PA9.Locked=true -PA9.Mode=Asynchronous -PA9.Signal=USART1_TX PB0.GPIOParameters=GPIO_Speed PB0.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH PB0.Mode=RGB888 diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c b/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c index a395939496..785137daf5 100644 --- a/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c +++ b/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c @@ -2,12 +2,12 @@ /** ****************************************************************************** * File Name : stm32f7xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** ** This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether + * USER CODE END. Other portions of this file, whether * inserted by the user or by software development tools * are owned by their respective copyright owners. * @@ -52,7 +52,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -113,10 +113,10 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) /* USER CODE END ADC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_ADC1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**ADC1 GPIO Configuration - PA5 ------> ADC1_IN5 + /**ADC1 GPIO Configuration + PA5 ------> ADC1_IN5 */ GPIO_InitStruct.Pin = GPIO_PIN_5; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; @@ -145,9 +145,9 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) /* USER CODE END ADC1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_ADC1_CLK_DISABLE(); - - /**ADC1 GPIO Configuration - PA5 ------> ADC1_IN5 + + /**ADC1 GPIO Configuration + PA5 ------> ADC1_IN5 */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5); @@ -218,11 +218,11 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) /* USER CODE END ETH_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_ETH_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); - /**ETH GPIO Configuration + /**ETH GPIO Configuration PC1 ------> ETH_MDC PA1 ------> ETH_REF_CLK PA2 ------> ETH_MDIO @@ -231,7 +231,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) PC5 ------> ETH_RXD1 PB11 ------> ETH_TX_EN PB12 ------> ETH_TXD0 - PB13 ------> ETH_TXD1 + PB13 ------> ETH_TXD1 */ GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -276,8 +276,8 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) /* USER CODE END ETH_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_ETH_CLK_DISABLE(); - - /**ETH GPIO Configuration + + /**ETH GPIO Configuration PC1 ------> ETH_MDC PA1 ------> ETH_REF_CLK PA2 ------> ETH_MDIO @@ -286,7 +286,7 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) PC5 ------> ETH_RXD1 PB11 ------> ETH_TX_EN PB12 ------> ETH_TXD0 - PB13 ------> ETH_TXD1 + PB13 ------> ETH_TXD1 */ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5); @@ -317,7 +317,7 @@ void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) /* USER CODE END LTDC_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_LTDC_CLK_ENABLE(); - + __HAL_RCC_GPIOE_CLK_ENABLE(); __HAL_RCC_GPIOI_CLK_ENABLE(); __HAL_RCC_GPIOF_CLK_ENABLE(); @@ -327,7 +327,7 @@ void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) __HAL_RCC_GPIOG_CLK_ENABLE(); __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); - /**LTDC GPIO Configuration + /**LTDC GPIO Configuration PE4 ------> LTDC_B0 PE5 ------> LTDC_G0 PE6 ------> LTDC_G1 @@ -355,7 +355,7 @@ void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) PG12 ------> LTDC_B1 PB8 ------> LTDC_B6 PB9 ------> LTDC_B7 - PI4 ------> LTDC_B4 + PI4 ------> LTDC_B4 */ GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -364,7 +364,7 @@ void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_0|GPIO_PIN_2 + GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_0|GPIO_PIN_2 |GPIO_PIN_4; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -379,7 +379,7 @@ void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_8|GPIO_PIN_13 + GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_8|GPIO_PIN_13 |GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -465,8 +465,8 @@ void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc) /* USER CODE END LTDC_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_LTDC_CLK_DISABLE(); - - /**LTDC GPIO Configuration + + /**LTDC GPIO Configuration PE4 ------> LTDC_B0 PE5 ------> LTDC_G0 PE6 ------> LTDC_G1 @@ -494,23 +494,23 @@ void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc) PG12 ------> LTDC_B1 PB8 ------> LTDC_B6 PB9 ------> LTDC_B7 - PI4 ------> LTDC_B4 + PI4 ------> LTDC_B4 */ HAL_GPIO_DeInit(GPIOE, GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6); - HAL_GPIO_DeInit(GPIOI, GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_0|GPIO_PIN_2 + HAL_GPIO_DeInit(GPIOI, GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_0|GPIO_PIN_2 |GPIO_PIN_4); HAL_GPIO_DeInit(GPIOF, GPIO_PIN_10); - HAL_GPIO_DeInit(GPIOH, GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_8|GPIO_PIN_13 + HAL_GPIO_DeInit(GPIOH, GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_8|GPIO_PIN_13 |GPIO_PIN_15); HAL_GPIO_DeInit(GPIOA, GPIO_PIN_3|GPIO_PIN_11|GPIO_PIN_12); HAL_GPIO_DeInit(GPIOB, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_8|GPIO_PIN_9); - HAL_GPIO_DeInit(GPIOG, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_10|GPIO_PIN_11 + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_10|GPIO_PIN_11 |GPIO_PIN_12); HAL_GPIO_DeInit(GPIOC, GPIO_PIN_7); @@ -540,16 +540,16 @@ void HAL_QSPI_MspInit(QSPI_HandleTypeDef* hqspi) /* USER CODE END QUADSPI_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_QSPI_CLK_ENABLE(); - + __HAL_RCC_GPIOF_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); - /**QUADSPI GPIO Configuration + /**QUADSPI GPIO Configuration PF6 ------> QUADSPI_BK1_IO3 PF7 ------> QUADSPI_BK1_IO2 PF8 ------> QUADSPI_BK1_IO0 PF9 ------> QUADSPI_BK1_IO1 PB2 ------> QUADSPI_CLK - PB6 ------> QUADSPI_BK1_NCS + PB6 ------> QUADSPI_BK1_NCS */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -601,14 +601,14 @@ void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef* hqspi) /* USER CODE END QUADSPI_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_QSPI_CLK_DISABLE(); - - /**QUADSPI GPIO Configuration + + /**QUADSPI GPIO Configuration PF6 ------> QUADSPI_BK1_IO3 PF7 ------> QUADSPI_BK1_IO2 PF8 ------> QUADSPI_BK1_IO0 PF9 ------> QUADSPI_BK1_IO1 PB2 ------> QUADSPI_CLK - PB6 ------> QUADSPI_BK1_NCS + PB6 ------> QUADSPI_BK1_NCS */ HAL_GPIO_DeInit(GPIOF, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9); @@ -637,18 +637,18 @@ void HAL_SD_MspInit(SD_HandleTypeDef* hsd) /* USER CODE END SDMMC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SDMMC1_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); - /**SDMMC1 GPIO Configuration + /**SDMMC1 GPIO Configuration PC8 ------> SDMMC1_D0 PC9 ------> SDMMC1_D1 PC10 ------> SDMMC1_D2 PC11 ------> SDMMC1_D3 PC12 ------> SDMMC1_CK - PD2 ------> SDMMC1_CMD + PD2 ------> SDMMC1_CMD */ - GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 |GPIO_PIN_12; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -685,16 +685,16 @@ void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) /* USER CODE END SDMMC1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SDMMC1_CLK_DISABLE(); - - /**SDMMC1 GPIO Configuration + + /**SDMMC1 GPIO Configuration PC8 ------> SDMMC1_D0 PC9 ------> SDMMC1_D1 PC10 ------> SDMMC1_D2 PC11 ------> SDMMC1_D3 PC12 ------> SDMMC1_CK - PD2 ------> SDMMC1_CMD + PD2 ------> SDMMC1_CMD */ - HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 |GPIO_PIN_12); HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); @@ -722,15 +722,15 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF7_USART1; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); @@ -757,10 +757,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration + + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); @@ -784,8 +784,8 @@ static void HAL_FMC_MspInit(void){ FMC_Initialized = 1; /* Peripheral clock enable */ __HAL_RCC_FMC_CLK_ENABLE(); - - /** FMC GPIO Configuration + + /** FMC GPIO Configuration PF0 ------> FMC_A0 PF1 ------> FMC_A1 PF2 ------> FMC_A2 @@ -825,8 +825,8 @@ static void HAL_FMC_MspInit(void){ PE0 ------> FMC_NBL0 PE1 ------> FMC_NBL1 */ - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 - |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_11|GPIO_PIN_12 + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_11|GPIO_PIN_12 |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -841,7 +841,7 @@ static void HAL_FMC_MspInit(void){ GPIO_InitStruct.Alternate = GPIO_AF12_FMC; HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5 + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5 |GPIO_PIN_8|GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -849,8 +849,8 @@ static void HAL_FMC_MspInit(void){ GPIO_InitStruct.Alternate = GPIO_AF12_FMC; HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 - |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 + GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 + |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -865,7 +865,7 @@ static void HAL_FMC_MspInit(void){ GPIO_InitStruct.Alternate = GPIO_AF12_FMC; HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14 + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14 |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -900,8 +900,8 @@ static void HAL_FMC_MspDeInit(void){ FMC_DeInitialized = 1; /* Peripheral clock enable */ __HAL_RCC_FMC_CLK_DISABLE(); - - /** FMC GPIO Configuration + + /** FMC GPIO Configuration PF0 ------> FMC_A0 PF1 ------> FMC_A1 PF2 ------> FMC_A2 @@ -941,22 +941,22 @@ static void HAL_FMC_MspDeInit(void){ PE0 ------> FMC_NBL0 PE1 ------> FMC_NBL1 */ - HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 - |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_11|GPIO_PIN_12 + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_11|GPIO_PIN_12 |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15); HAL_GPIO_DeInit(GPIOC, GPIO_PIN_0); - HAL_GPIO_DeInit(GPIOG, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5 + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5 |GPIO_PIN_8|GPIO_PIN_15); - HAL_GPIO_DeInit(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 - |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 + HAL_GPIO_DeInit(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 + |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1); HAL_GPIO_DeInit(GPIOH, GPIO_PIN_6|GPIO_PIN_7); - HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14 + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14 |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1); /* USER CODE BEGIN FMC_MspDeInit 1 */ diff --git a/bsp/stm32/stm32f767-st-nucleo/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c b/bsp/stm32/stm32f767-st-nucleo/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c index 770d50f63e..7306fcf76f 100644 --- a/bsp/stm32/stm32f767-st-nucleo/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c +++ b/bsp/stm32/stm32f767-st-nucleo/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c @@ -2,12 +2,12 @@ /** ****************************************************************************** * File Name : stm32f7xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** ** This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether + * USER CODE END. Other portions of this file, whether * inserted by the user or by software development tools * are owned by their respective copyright owners. * @@ -52,7 +52,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -114,12 +114,12 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) /* USER CODE END ETH_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_ETH_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOG_CLK_ENABLE(); - /**ETH GPIO Configuration + /**ETH GPIO Configuration PC1 ------> ETH_MDC PA1 ------> ETH_REF_CLK PA2 ------> ETH_MDIO @@ -128,7 +128,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) PC5 ------> ETH_RXD1 PB13 ------> ETH_TXD1 PG11 ------> ETH_TX_EN - PG13 ------> ETH_TXD0 + PG13 ------> ETH_TXD0 */ GPIO_InitStruct.Pin = RMII_MDC_Pin|RMII_RXD0_Pin|RMII_RXD1_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -182,8 +182,8 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) /* USER CODE END ETH_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_ETH_CLK_DISABLE(); - - /**ETH GPIO Configuration + + /**ETH GPIO Configuration PC1 ------> ETH_MDC PA1 ------> ETH_REF_CLK PA2 ------> ETH_MDIO @@ -192,7 +192,7 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) PC5 ------> ETH_RXD1 PB13 ------> ETH_TXD1 PG11 ------> ETH_TX_EN - PG13 ------> ETH_TXD0 + PG13 ------> ETH_TXD0 */ HAL_GPIO_DeInit(GPIOC, RMII_MDC_Pin|RMII_RXD0_Pin|RMII_RXD1_Pin); @@ -226,15 +226,15 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART3_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART3_CLK_ENABLE(); - + __HAL_RCC_GPIOD_CLK_ENABLE(); - /**USART3 GPIO Configuration + /**USART3 GPIO Configuration PD8 ------> USART3_TX - PD9 ------> USART3_RX + PD9 ------> USART3_RX */ GPIO_InitStruct.Pin = STLK_RX_Pin|STLK_TX_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF7_USART3; HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); @@ -263,10 +263,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART3_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART3_CLK_DISABLE(); - - /**USART3 GPIO Configuration + + /**USART3 GPIO Configuration PD8 ------> USART3_TX - PD9 ------> USART3_RX + PD9 ------> USART3_RX */ HAL_GPIO_DeInit(GPIOD, STLK_RX_Pin|STLK_TX_Pin); @@ -292,14 +292,14 @@ void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd) /* USER CODE BEGIN USB_OTG_FS_MspInit 0 */ /* USER CODE END USB_OTG_FS_MspInit 0 */ - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USB_OTG_FS GPIO Configuration + /**USB_OTG_FS GPIO Configuration PA8 ------> USB_OTG_FS_SOF PA9 ------> USB_OTG_FS_VBUS PA10 ------> USB_OTG_FS_ID PA11 ------> USB_OTG_FS_DM - PA12 ------> USB_OTG_FS_DP + PA12 ------> USB_OTG_FS_DP */ GPIO_InitStruct.Pin = USB_SOF_Pin|USB_ID_Pin|USB_DM_Pin|USB_DP_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -339,15 +339,15 @@ void HAL_PCD_MspDeInit(PCD_HandleTypeDef* hpcd) /* USER CODE END USB_OTG_FS_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USB_OTG_FS_CLK_DISABLE(); - - /**USB_OTG_FS GPIO Configuration + + /**USB_OTG_FS GPIO Configuration PA8 ------> USB_OTG_FS_SOF PA9 ------> USB_OTG_FS_VBUS PA10 ------> USB_OTG_FS_ID PA11 ------> USB_OTG_FS_DM - PA12 ------> USB_OTG_FS_DP + PA12 ------> USB_OTG_FS_DP */ - HAL_GPIO_DeInit(GPIOA, USB_SOF_Pin|USB_VBUS_Pin|USB_ID_Pin|USB_DM_Pin + HAL_GPIO_DeInit(GPIOA, USB_SOF_Pin|USB_VBUS_Pin|USB_ID_Pin|USB_DM_Pin |USB_DP_Pin); /* USER CODE BEGIN USB_OTG_FS_MspDeInit 1 */ diff --git a/bsp/stm32/stm32f769-st-disco/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f769-st-disco/board/CubeMX_Config/CubeMX_Config.ioc index 73e883d6c0..f4bc362e25 100644 --- a/bsp/stm32/stm32f769-st-disco/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32f769-st-disco/board/CubeMX_Config/CubeMX_Config.ioc @@ -60,7 +60,12 @@ NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false PA1.Mode=MII PA1.Signal=ETH_RX_CLK -PA10.Locked=true +PA9.GPIOParameters=GPIO_PuPd +PA9.GPIO_PuPd=GPIO_PULLUP +PA9.Mode=Asynchronous +PA9.Signal=USART1_TX +PA10.GPIOParameters=GPIO_PuPd +PA10.GPIO_PuPd=GPIO_PULLUP PA10.Mode=Asynchronous PA10.Signal=USART1_RX PA13.Mode=Serial_Wire @@ -71,9 +76,6 @@ PA2.Mode=MII PA2.Signal=ETH_MDIO PA7.Mode=MII PA7.Signal=ETH_RX_DV -PA9.Locked=true -PA9.Mode=Asynchronous -PA9.Signal=USART1_TX PC1.Mode=MII PC1.Signal=ETH_MDC PC12.Locked=true diff --git a/bsp/stm32/stm32f769-st-disco/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c b/bsp/stm32/stm32f769-st-disco/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c index 99a22fec0f..4f8f77a12b 100644 --- a/bsp/stm32/stm32f769-st-disco/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c +++ b/bsp/stm32/stm32f769-st-disco/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c @@ -2,7 +2,7 @@ /** ****************************************************************************** * File Name : stm32f7xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** * @attention @@ -32,7 +32,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -93,13 +93,13 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) /* USER CODE END ETH_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_ETH_CLK_ENABLE(); - + __HAL_RCC_GPIOE_CLK_ENABLE(); __HAL_RCC_GPIOG_CLK_ENABLE(); __HAL_RCC_GPIOH_CLK_ENABLE(); __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE(); - /**ETH GPIO Configuration + /**ETH GPIO Configuration PE2 ------> ETH_TXD3 PG14 ------> ETH_TXD1 PG13 ------> ETH_TXD0 @@ -115,7 +115,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) PA2 ------> ETH_MDIO PC5 ------> ETH_RXD1 PH6 ------> ETH_RXD2 - PA7 ------> ETH_RX_DV + PA7 ------> ETH_RX_DV */ GPIO_InitStruct.Pin = GPIO_PIN_2; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -138,7 +138,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) GPIO_InitStruct.Alternate = GPIO_AF11_ETH; HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_4 + GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_4 |GPIO_PIN_5; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -175,8 +175,8 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) /* USER CODE END ETH_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_ETH_CLK_DISABLE(); - - /**ETH GPIO Configuration + + /**ETH GPIO Configuration PE2 ------> ETH_TXD3 PG14 ------> ETH_TXD1 PG13 ------> ETH_TXD0 @@ -192,7 +192,7 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) PA2 ------> ETH_MDIO PC5 ------> ETH_RXD1 PH6 ------> ETH_RXD2 - PA7 ------> ETH_RX_DV + PA7 ------> ETH_RX_DV */ HAL_GPIO_DeInit(GPIOE, GPIO_PIN_2); @@ -200,7 +200,7 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) HAL_GPIO_DeInit(GPIOH, GPIO_PIN_3|GPIO_PIN_2|GPIO_PIN_7|GPIO_PIN_6); - HAL_GPIO_DeInit(GPIOC, GPIO_PIN_3|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_4 + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_3|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_4 |GPIO_PIN_5); HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7); @@ -228,23 +228,23 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END UART5_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_UART5_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); - /**UART5 GPIO Configuration + /**UART5 GPIO Configuration PC12 ------> UART5_TX - PD2 ------> UART5_RX + PD2 ------> UART5_RX */ GPIO_InitStruct.Pin = GPIO_PIN_12; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF8_UART5; HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); GPIO_InitStruct.Pin = GPIO_PIN_2; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF8_UART5; HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); @@ -260,15 +260,15 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PA10 ------> USART1_RX - PA9 ------> USART1_TX + PA9 ------> USART1_TX */ GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_9; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF7_USART1; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); @@ -295,10 +295,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END UART5_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_UART5_CLK_DISABLE(); - - /**UART5 GPIO Configuration + + /**UART5 GPIO Configuration PC12 ------> UART5_TX - PD2 ------> UART5_RX + PD2 ------> UART5_RX */ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_12); @@ -315,10 +315,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration + + /**USART1 GPIO Configuration PA10 ------> USART1_RX - PA9 ------> USART1_TX + PA9 ------> USART1_TX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_10|GPIO_PIN_9); diff --git a/bsp/stm32/stm32g070-st-nucleo/board/CubeMX_Config/Src/stm32g0xx_hal_msp.c b/bsp/stm32/stm32g070-st-nucleo/board/CubeMX_Config/Src/stm32g0xx_hal_msp.c index 7c05429633..3c74feb4d2 100644 --- a/bsp/stm32/stm32g070-st-nucleo/board/CubeMX_Config/Src/stm32g0xx_hal_msp.c +++ b/bsp/stm32/stm32g070-st-nucleo/board/CubeMX_Config/Src/stm32g0xx_hal_msp.c @@ -2,7 +2,7 @@ /** ****************************************************************************** * File Name : stm32g0xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** * @attention @@ -32,7 +32,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -58,7 +58,7 @@ /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ - + void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); /** * Initializes the Global MSP. @@ -95,10 +95,10 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) /* USER CODE END ADC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_ADC_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**ADC1 GPIO Configuration - PA0 ------> ADC1_IN0 + /**ADC1 GPIO Configuration + PA0 ------> ADC1_IN0 */ GPIO_InitStruct.Pin = GPIO_PIN_0; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; @@ -127,9 +127,9 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) /* USER CODE END ADC1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_ADC_CLK_DISABLE(); - - /**ADC1 GPIO Configuration - PA0 ------> ADC1_IN0 + + /**ADC1 GPIO Configuration + PA0 ------> ADC1_IN0 */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_0); @@ -202,12 +202,12 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**SPI1 GPIO Configuration + /**SPI1 GPIO Configuration PA1 ------> SPI1_SCK PA11 [PA9] ------> SPI1_MISO - PA12 [PA10] ------> SPI1_MOSI + PA12 [PA10] ------> SPI1_MOSI */ GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_11|GPIO_PIN_12; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -227,13 +227,13 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI2_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); - /**SPI2 GPIO Configuration + /**SPI2 GPIO Configuration PC2 ------> SPI2_MISO PC3 ------> SPI2_MOSI - PB10 ------> SPI2_SCK + PB10 ------> SPI2_SCK */ GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -271,11 +271,11 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI1_CLK_DISABLE(); - - /**SPI1 GPIO Configuration + + /**SPI1 GPIO Configuration PA1 ------> SPI1_SCK PA11 [PA9] ------> SPI1_MISO - PA12 [PA10] ------> SPI1_MOSI + PA12 [PA10] ------> SPI1_MOSI */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1|GPIO_PIN_11|GPIO_PIN_12); @@ -290,11 +290,11 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI2_CLK_DISABLE(); - - /**SPI2 GPIO Configuration + + /**SPI2 GPIO Configuration PC2 ------> SPI2_MISO PC3 ------> SPI2_MOSI - PB10 ------> SPI2_SCK + PB10 ------> SPI2_SCK */ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_2|GPIO_PIN_3); @@ -348,14 +348,14 @@ void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) /* USER CODE BEGIN TIM3_MspPostInit 0 */ /* USER CODE END TIM3_MspPostInit 0 */ - + __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); - /**TIM3 GPIO Configuration + /**TIM3 GPIO Configuration PA6 ------> TIM3_CH1 PA7 ------> TIM3_CH2 PB0 ------> TIM3_CH3 - PB1 ------> TIM3_CH4 + PB1 ------> TIM3_CH4 */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -426,15 +426,15 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PC4 ------> USART1_TX - PC5 ------> USART1_RX + PC5 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Alternate = GPIO_AF1_USART1; HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); @@ -450,11 +450,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART2 GPIO Configuration + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -474,23 +474,23 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART3_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART3_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); - /**USART3 GPIO Configuration + /**USART3 GPIO Configuration PC11 ------> USART3_RX - PB2 ------> USART3_TX + PB2 ------> USART3_TX */ GPIO_InitStruct.Pin = GPIO_PIN_11; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Alternate = GPIO_AF0_USART3; HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); GPIO_InitStruct.Pin = GPIO_PIN_2; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Alternate = GPIO_AF4_USART3; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); @@ -517,10 +517,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration + + /**USART1 GPIO Configuration PC4 ------> USART1_TX - PC5 ------> USART1_RX + PC5 ------> USART1_RX */ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_4|GPIO_PIN_5); @@ -535,10 +535,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART2_CLK_DISABLE(); - - /**USART2 GPIO Configuration + + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3); @@ -553,10 +553,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART3_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART3_CLK_DISABLE(); - - /**USART3 GPIO Configuration + + /**USART3 GPIO Configuration PC11 ------> USART3_RX - PB2 ------> USART3_TX + PB2 ------> USART3_TX */ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_11); diff --git a/bsp/stm32/stm32g071-st-nucleo/board/CubeMX_Config/Src/stm32g0xx_hal_msp.c b/bsp/stm32/stm32g071-st-nucleo/board/CubeMX_Config/Src/stm32g0xx_hal_msp.c index 3cfed698d3..5dc12fb616 100644 --- a/bsp/stm32/stm32g071-st-nucleo/board/CubeMX_Config/Src/stm32g0xx_hal_msp.c +++ b/bsp/stm32/stm32g071-st-nucleo/board/CubeMX_Config/Src/stm32g0xx_hal_msp.c @@ -2,12 +2,12 @@ /** ****************************************************************************** * File Name : stm32g0xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** ** This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether + * USER CODE END. Other portions of this file, whether * inserted by the user or by software development tools * are owned by their respective copyright owners. * @@ -52,7 +52,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -78,7 +78,7 @@ /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ - + void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); /** * Initializes the Global MSP. @@ -116,11 +116,11 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) /* USER CODE END ADC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_ADC_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**ADC1 GPIO Configuration + /**ADC1 GPIO Configuration PA0 ------> ADC1_IN0 - PA1 ------> ADC1_IN1 + PA1 ------> ADC1_IN1 */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; @@ -151,10 +151,10 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) /* USER CODE END ADC1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_ADC_CLK_DISABLE(); - - /**ADC1 GPIO Configuration + + /**ADC1 GPIO Configuration PA0 ------> ADC1_IN0 - PA1 ------> ADC1_IN1 + PA1 ------> ADC1_IN1 */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_0|GPIO_PIN_1); @@ -182,11 +182,11 @@ void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac) /* USER CODE END DAC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_DAC1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**DAC1 GPIO Configuration + /**DAC1 GPIO Configuration PA4 ------> DAC1_OUT1 - PA5 ------> DAC1_OUT2 + PA5 ------> DAC1_OUT2 */ GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; @@ -217,10 +217,10 @@ void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac) /* USER CODE END DAC1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_DAC1_CLK_DISABLE(); - - /**DAC1 GPIO Configuration + + /**DAC1 GPIO Configuration PA4 ------> DAC1_OUT1 - PA5 ------> DAC1_OUT2 + PA5 ------> DAC1_OUT2 */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_4|GPIO_PIN_5); @@ -248,15 +248,15 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END LPUART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_LPUART1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**LPUART1 GPIO Configuration + /**LPUART1 GPIO Configuration PA2 ------> LPUART1_TX - PA3 ------> LPUART1_RX + PA3 ------> LPUART1_RX */ GPIO_InitStruct.Pin = LPUART1_TX_Pin|LPUART1_RX_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Alternate = GPIO_AF6_LPUART1; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); @@ -275,11 +275,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PC4 ------> USART1_TX - PC5 ------> USART1_RX + PC5 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -299,12 +299,12 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); - /**USART2 GPIO Configuration + /**USART2 GPIO Configuration PA15 ------> USART2_RX - PD5 ------> USART2_TX + PD5 ------> USART2_TX */ GPIO_InitStruct.Pin = GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -331,12 +331,12 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART3_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART3_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); - /**USART3 GPIO Configuration + /**USART3 GPIO Configuration PC11 ------> USART3_RX - PB2 ------> USART3_TX + PB2 ------> USART3_TX */ GPIO_InitStruct.Pin = GPIO_PIN_11; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -379,10 +379,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END LPUART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_LPUART1_CLK_DISABLE(); - - /**LPUART1 GPIO Configuration + + /**LPUART1 GPIO Configuration PA2 ------> LPUART1_TX - PA3 ------> LPUART1_RX + PA3 ------> LPUART1_RX */ HAL_GPIO_DeInit(GPIOA, LPUART1_TX_Pin|LPUART1_RX_Pin); @@ -406,10 +406,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration + + /**USART1 GPIO Configuration PC4 ------> USART1_TX - PC5 ------> USART1_RX + PC5 ------> USART1_RX */ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_4|GPIO_PIN_5); @@ -424,10 +424,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART2_CLK_DISABLE(); - - /**USART2 GPIO Configuration + + /**USART2 GPIO Configuration PA15 ------> USART2_RX - PD5 ------> USART2_TX + PD5 ------> USART2_TX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_15); @@ -444,10 +444,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART3_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART3_CLK_DISABLE(); - - /**USART3 GPIO Configuration + + /**USART3 GPIO Configuration PC11 ------> USART3_RX - PB2 ------> USART3_TX + PB2 ------> USART3_TX */ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_11); @@ -486,13 +486,13 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); - /**SPI1 GPIO Configuration + /**SPI1 GPIO Configuration PA6 ------> SPI1_MISO PA7 ------> SPI1_MOSI - PD8 ------> SPI1_SCK + PD8 ------> SPI1_SCK */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -519,13 +519,13 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI2_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); - /**SPI2 GPIO Configuration + /**SPI2 GPIO Configuration PC2 ------> SPI2_MISO PC3 ------> SPI2_MOSI - PB13 ------> SPI2_SCK + PB13 ------> SPI2_SCK */ GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -565,11 +565,11 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI1_CLK_DISABLE(); - - /**SPI1 GPIO Configuration + + /**SPI1 GPIO Configuration PA6 ------> SPI1_MISO PA7 ------> SPI1_MOSI - PD8 ------> SPI1_SCK + PD8 ------> SPI1_SCK */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_6|GPIO_PIN_7); @@ -586,11 +586,11 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI2_CLK_DISABLE(); - - /**SPI2 GPIO Configuration + + /**SPI2 GPIO Configuration PC2 ------> SPI2_MISO PC3 ------> SPI2_MOSI - PB13 ------> SPI2_SCK + PB13 ------> SPI2_SCK */ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_2|GPIO_PIN_3); @@ -646,14 +646,14 @@ void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) /* USER CODE BEGIN TIM3_MspPostInit 0 */ /* USER CODE END TIM3_MspPostInit 0 */ - + __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOC_CLK_ENABLE(); - /**TIM3 GPIO Configuration + /**TIM3 GPIO Configuration PB0 ------> TIM3_CH3 PB1 ------> TIM3_CH4 PC6 ------> TIM3_CH1 - PC7 ------> TIM3_CH2 + PC7 ------> TIM3_CH2 */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; diff --git a/bsp/stm32/stm32g431-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32g431-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc index 420cba6a01..854757a8f5 100644 --- a/bsp/stm32/stm32g431-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32g431-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc @@ -57,18 +57,24 @@ PA14.GPIO_Label=T_SWCLK PA14.Locked=true PA14.Mode=Serial_Wire PA14.Signal=SYS_JTCK-SWCLK -PA2.Locked=true +PA2.GPIOParameters=GPIO_PuPd +PA2.GPIO_PuPd=GPIO_PULLUP PA2.Mode=Asynchronous -PA2.Signal=LPUART1_TX -PA3.Locked=true +PA2.Signal=USART2_TX +PA3.GPIOParameters=GPIO_PuPd +PA3.GPIO_PuPd=GPIO_PULLUP PA3.Mode=Asynchronous -PA3.Signal=LPUART1_RX +PA3.Signal=USART2_RX PA5.GPIOParameters=GPIO_Label PA5.GPIO_Label=LD2 [green] PA5.Locked=true PA5.Signal=GPIO_Output +PB10.GPIOParameters=GPIO_PuPd +PB10.GPIO_PuPd=GPIO_PULLUP PB10.Mode=Asynchronous PB10.Signal=USART3_TX +PB11.GPIOParameters=GPIO_PuPd +PB11.GPIO_PuPd=GPIO_PULLUP PB11.Mode=Asynchronous PB11.Signal=USART3_RX PB3.GPIOParameters=GPIO_Label diff --git a/bsp/stm32/stm32g431-st-nucleo/board/CubeMX_Config/Src/stm32g4xx_hal_msp.c b/bsp/stm32/stm32g431-st-nucleo/board/CubeMX_Config/Src/stm32g4xx_hal_msp.c index 759ac0f62c..51088806a3 100644 --- a/bsp/stm32/stm32g431-st-nucleo/board/CubeMX_Config/Src/stm32g4xx_hal_msp.c +++ b/bsp/stm32/stm32g431-st-nucleo/board/CubeMX_Config/Src/stm32g4xx_hal_msp.c @@ -2,7 +2,7 @@ /** ****************************************************************************** * File Name : stm32g4xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** * @attention @@ -32,7 +32,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -72,7 +72,7 @@ void HAL_MspInit(void) /* System interrupt init*/ - /** Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral + /** Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral */ LL_PWR_DisableDeadBatteryPD(); @@ -97,15 +97,15 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END LPUART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_LPUART1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**LPUART1 GPIO Configuration + /**LPUART1 GPIO Configuration PA2 ------> LPUART1_TX - PA3 ------> LPUART1_RX + PA3 ------> LPUART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Alternate = GPIO_AF12_LPUART1; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); @@ -121,15 +121,15 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END UART4_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_UART4_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); - /**UART4 GPIO Configuration + /**UART4 GPIO Configuration PC10 ------> UART4_TX - PC11 ------> UART4_RX + PC11 ------> UART4_RX */ GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Alternate = GPIO_AF5_UART4; HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); @@ -145,15 +145,15 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PC4 ------> USART1_TX - PC5 ------> USART1_RX + PC5 ------> USART1_RX */ GPIO_InitStruct.Pin = USART1_TX_Pin|USART1_RX_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Alternate = GPIO_AF7_USART1; HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); @@ -169,15 +169,15 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART3_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART3_CLK_ENABLE(); - + __HAL_RCC_GPIOB_CLK_ENABLE(); - /**USART3 GPIO Configuration + /**USART3 GPIO Configuration PB10 ------> USART3_TX - PB11 ------> USART3_RX + PB11 ------> USART3_RX */ GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Alternate = GPIO_AF7_USART3; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); @@ -204,10 +204,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END LPUART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_LPUART1_CLK_DISABLE(); - - /**LPUART1 GPIO Configuration + + /**LPUART1 GPIO Configuration PA2 ------> LPUART1_TX - PA3 ------> LPUART1_RX + PA3 ------> LPUART1_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3); @@ -222,10 +222,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END UART4_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_UART4_CLK_DISABLE(); - - /**UART4 GPIO Configuration + + /**UART4 GPIO Configuration PC10 ------> UART4_TX - PC11 ------> UART4_RX + PC11 ------> UART4_RX */ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_10|GPIO_PIN_11); @@ -240,10 +240,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration + + /**USART1 GPIO Configuration PC4 ------> USART1_TX - PC5 ------> USART1_RX + PC5 ------> USART1_RX */ HAL_GPIO_DeInit(GPIOC, USART1_TX_Pin|USART1_RX_Pin); @@ -258,10 +258,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART3_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART3_CLK_DISABLE(); - - /**USART3 GPIO Configuration + + /**USART3 GPIO Configuration PB10 ------> USART3_TX - PB11 ------> USART3_RX + PB11 ------> USART3_RX */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_10|GPIO_PIN_11); diff --git a/bsp/stm32/stm32h743-atk-apollo/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32h743-atk-apollo/board/CubeMX_Config/CubeMX_Config.ioc index fd2d5efe67..7ef3f3f109 100644 --- a/bsp/stm32/stm32h743-atk-apollo/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32h743-atk-apollo/board/CubeMX_Config/CubeMX_Config.ioc @@ -161,23 +161,29 @@ NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true NVIC.USART1_IRQn=true\:0\:0\:false\:false\:true\:true\:true NVIC.USART2_IRQn=true\:0\:0\:false\:false\:true\:true\:true NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false -PA10.Locked=true +PA9.GPIOParameters=GPIO_PuPd +PA9.GPIO_PuPd=GPIO_PULLUP +PA9.Mode=Asynchronous +PA9.Signal=USART1_TX +PA10.GPIOParameters=GPIO_PuPd +PA10.GPIO_PuPd=GPIO_PULLUP PA10.Mode=Asynchronous PA10.Signal=USART1_RX PA13\ (JTMS/SWDIO).Mode=Serial_Wire PA13\ (JTMS/SWDIO).Signal=DEBUG_JTMS-SWDIO PA14\ (JTCK/SWCLK).Mode=Serial_Wire PA14\ (JTCK/SWCLK).Signal=DEBUG_JTCK-SWCLK +PA2.GPIOParameters=GPIO_PuPd +PA2.GPIO_PuPd=GPIO_PULLUP PA2.Mode=Asynchronous PA2.Signal=USART2_TX +PA3.GPIOParameters=GPIO_PuPd +PA3.GPIO_PuPd=GPIO_PULLUP PA3.Mode=Asynchronous PA3.Signal=USART2_RX PA4.Signal=COMP_DAC11_group PA5.Locked=true PA5.Signal=ADCx_INP19 -PA9.Locked=true -PA9.Mode=Asynchronous -PA9.Signal=USART1_TX PB13.GPIOParameters=GPIO_Speed PB13.GPIO_Speed=GPIO_SPEED_FREQ_HIGH PB13.Locked=true diff --git a/bsp/stm32/stm32h743-atk-apollo/board/CubeMX_Config/Src/stm32h7xx_hal_msp.c b/bsp/stm32/stm32h743-atk-apollo/board/CubeMX_Config/Src/stm32h7xx_hal_msp.c index 42d6806ff0..fef02fcddd 100644 --- a/bsp/stm32/stm32h743-atk-apollo/board/CubeMX_Config/Src/stm32h7xx_hal_msp.c +++ b/bsp/stm32/stm32h743-atk-apollo/board/CubeMX_Config/Src/stm32h7xx_hal_msp.c @@ -2,12 +2,12 @@ /** ****************************************************************************** * File Name : stm32h7xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** ** This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether + * USER CODE END. Other portions of this file, whether * inserted by the user or by software development tools * are owned by their respective copyright owners. * @@ -52,7 +52,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -278,12 +278,12 @@ void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) /* USER CODE END LTDC_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_LTDC_CLK_ENABLE(); - + __HAL_RCC_GPIOI_CLK_ENABLE(); __HAL_RCC_GPIOF_CLK_ENABLE(); __HAL_RCC_GPIOH_CLK_ENABLE(); __HAL_RCC_GPIOG_CLK_ENABLE(); - /**LTDC GPIO Configuration + /**LTDC GPIO Configuration PI9 ------> LTDC_VSYNC PI10 ------> LTDC_HSYNC PF10 ------> LTDC_DE @@ -303,10 +303,10 @@ void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) PI4 ------> LTDC_B4 PI5 ------> LTDC_B5 PI6 ------> LTDC_B6 - PI7 ------> LTDC_B7 + PI7 ------> LTDC_B7 */ - GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_0|GPIO_PIN_1 - |GPIO_PIN_2|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6 + GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_0|GPIO_PIN_1 + |GPIO_PIN_2|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6 |GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -321,7 +321,7 @@ void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12 + GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12 |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -358,8 +358,8 @@ void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc) /* USER CODE END LTDC_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_LTDC_CLK_DISABLE(); - - /**LTDC GPIO Configuration + + /**LTDC GPIO Configuration PI9 ------> LTDC_VSYNC PI10 ------> LTDC_HSYNC PF10 ------> LTDC_DE @@ -379,15 +379,15 @@ void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc) PI4 ------> LTDC_B4 PI5 ------> LTDC_B5 PI6 ------> LTDC_B6 - PI7 ------> LTDC_B7 + PI7 ------> LTDC_B7 */ - HAL_GPIO_DeInit(GPIOI, GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_0|GPIO_PIN_1 - |GPIO_PIN_2|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6 + HAL_GPIO_DeInit(GPIOI, GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_0|GPIO_PIN_1 + |GPIO_PIN_2|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6 |GPIO_PIN_7); HAL_GPIO_DeInit(GPIOF, GPIO_PIN_10); - HAL_GPIO_DeInit(GPIOH, GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12 + HAL_GPIO_DeInit(GPIOH, GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12 |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15); HAL_GPIO_DeInit(GPIOG, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_11); @@ -415,16 +415,16 @@ void HAL_QSPI_MspInit(QSPI_HandleTypeDef* hqspi) /* USER CODE END QUADSPI_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_QSPI_CLK_ENABLE(); - + __HAL_RCC_GPIOF_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); - /**QUADSPI GPIO Configuration + /**QUADSPI GPIO Configuration PF6 ------> QUADSPI_BK1_IO3 PF7 ------> QUADSPI_BK1_IO2 PF8 ------> QUADSPI_BK1_IO0 PF9 ------> QUADSPI_BK1_IO1 PB2 ------> QUADSPI_CLK - PB6 ------> QUADSPI_BK1_NCS + PB6 ------> QUADSPI_BK1_NCS */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -476,14 +476,14 @@ void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef* hqspi) /* USER CODE END QUADSPI_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_QSPI_CLK_DISABLE(); - - /**QUADSPI GPIO Configuration + + /**QUADSPI GPIO Configuration PF6 ------> QUADSPI_BK1_IO3 PF7 ------> QUADSPI_BK1_IO2 PF8 ------> QUADSPI_BK1_IO0 PF9 ------> QUADSPI_BK1_IO1 PB2 ------> QUADSPI_CLK - PB6 ------> QUADSPI_BK1_NCS + PB6 ------> QUADSPI_BK1_NCS */ HAL_GPIO_DeInit(GPIOF, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9); @@ -512,10 +512,10 @@ void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) /* USER CODE END RTC_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_RTC_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); - /**RTC GPIO Configuration - PC13 ------> RTC_OUT_CALIB + /**RTC GPIO Configuration + PC13 ------> RTC_OUT_CALIB */ HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); @@ -541,9 +541,9 @@ void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) /* USER CODE END RTC_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_RTC_DISABLE(); - - /**RTC GPIO Configuration - PC13 ------> RTC_OUT_CALIB + + /**RTC GPIO Configuration + PC13 ------> RTC_OUT_CALIB */ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_13); @@ -570,18 +570,18 @@ void HAL_SD_MspInit(SD_HandleTypeDef* hsd) /* USER CODE END SDMMC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SDMMC1_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); - /**SDMMC1 GPIO Configuration + /**SDMMC1 GPIO Configuration PC8 ------> SDMMC1_D0 PC9 ------> SDMMC1_D1 PC10 ------> SDMMC1_D2 PC11 ------> SDMMC1_D3 PC12 ------> SDMMC1_CK - PD2 ------> SDMMC1_CMD + PD2 ------> SDMMC1_CMD */ - GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 |GPIO_PIN_12; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -621,16 +621,16 @@ void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) /* USER CODE END SDMMC1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SDMMC1_CLK_DISABLE(); - - /**SDMMC1 GPIO Configuration + + /**SDMMC1 GPIO Configuration PC8 ------> SDMMC1_D0 PC9 ------> SDMMC1_D1 PC10 ------> SDMMC1_D2 PC11 ------> SDMMC1_D3 PC12 ------> SDMMC1_CK - PD2 ------> SDMMC1_CMD + PD2 ------> SDMMC1_CMD */ - HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 |GPIO_PIN_12); HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); @@ -660,12 +660,12 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI2_CLK_ENABLE(); - + __HAL_RCC_GPIOB_CLK_ENABLE(); - /**SPI2 GPIO Configuration + /**SPI2 GPIO Configuration PB13 ------> SPI2_SCK PB14 ------> SPI2_MISO - PB15 ------> SPI2_MOSI + PB15 ------> SPI2_MOSI */ GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -696,11 +696,11 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI2_CLK_DISABLE(); - - /**SPI2 GPIO Configuration + + /**SPI2 GPIO Configuration PB13 ------> SPI2_SCK PB14 ------> SPI2_MISO - PB15 ------> SPI2_MOSI + PB15 ------> SPI2_MOSI */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15); @@ -727,15 +727,15 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Alternate = GPIO_AF7_USART1; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); @@ -754,15 +754,15 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART2 GPIO Configuration + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Alternate = GPIO_AF7_USART2; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); @@ -792,10 +792,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration + + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); @@ -812,10 +812,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART2_CLK_DISABLE(); - - /**USART2 GPIO Configuration + + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3); @@ -842,8 +842,8 @@ static void HAL_FMC_MspInit(void){ /* Peripheral clock enable */ __HAL_RCC_FMC_CLK_ENABLE(); - - /** FMC GPIO Configuration + + /** FMC GPIO Configuration PF0 ------> FMC_A0 PF1 ------> FMC_A1 PF2 ------> FMC_A2 @@ -884,8 +884,8 @@ static void HAL_FMC_MspInit(void){ PE0 ------> FMC_NBL0 PE1 ------> FMC_NBL1 */ - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 - |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_11|GPIO_PIN_12 + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_11|GPIO_PIN_12 |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -900,7 +900,7 @@ static void HAL_FMC_MspInit(void){ GPIO_InitStruct.Alternate = GPIO_AF12_FMC; HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_4 + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_4 |GPIO_PIN_5|GPIO_PIN_8|GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -908,8 +908,8 @@ static void HAL_FMC_MspInit(void){ GPIO_InitStruct.Alternate = GPIO_AF12_FMC; HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 - |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 + GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 + |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -917,7 +917,7 @@ static void HAL_FMC_MspInit(void){ GPIO_InitStruct.Alternate = GPIO_AF12_FMC; HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14 + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14 |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -952,8 +952,8 @@ static void HAL_FMC_MspDeInit(void){ FMC_DeInitialized = 1; /* Peripheral clock enable */ __HAL_RCC_FMC_CLK_DISABLE(); - - /** FMC GPIO Configuration + + /** FMC GPIO Configuration PF0 ------> FMC_A0 PF1 ------> FMC_A1 PF2 ------> FMC_A2 @@ -994,20 +994,20 @@ static void HAL_FMC_MspDeInit(void){ PE0 ------> FMC_NBL0 PE1 ------> FMC_NBL1 */ - HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 - |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_11|GPIO_PIN_12 + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_11|GPIO_PIN_12 |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15); HAL_GPIO_DeInit(GPIOC, GPIO_PIN_0|GPIO_PIN_2|GPIO_PIN_3); - HAL_GPIO_DeInit(GPIOG, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_4 + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_4 |GPIO_PIN_5|GPIO_PIN_8|GPIO_PIN_15); - HAL_GPIO_DeInit(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 - |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 + HAL_GPIO_DeInit(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 + |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1); - HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14 + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14 |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1); /* USER CODE BEGIN FMC_MspDeInit 1 */ diff --git a/bsp/stm32/stm32h743-st-nucleo/board/CubeMX_Config/Src/stm32h7xx_hal_msp.c b/bsp/stm32/stm32h743-st-nucleo/board/CubeMX_Config/Src/stm32h7xx_hal_msp.c index 60881f1c22..099374e220 100644 --- a/bsp/stm32/stm32h743-st-nucleo/board/CubeMX_Config/Src/stm32h7xx_hal_msp.c +++ b/bsp/stm32/stm32h743-st-nucleo/board/CubeMX_Config/Src/stm32h7xx_hal_msp.c @@ -2,7 +2,7 @@ /** ****************************************************************************** * File Name : stm32h7xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** * @attention @@ -32,7 +32,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -92,15 +92,15 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART3_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART3_CLK_ENABLE(); - + __HAL_RCC_GPIOD_CLK_ENABLE(); - /**USART3 GPIO Configuration + /**USART3 GPIO Configuration PD8 ------> USART3_TX - PD9 ------> USART3_RX + PD9 ------> USART3_RX */ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Alternate = GPIO_AF7_USART3; HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); @@ -127,10 +127,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART3_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART3_CLK_DISABLE(); - - /**USART3 GPIO Configuration + + /**USART3 GPIO Configuration PD8 ------> USART3_TX - PD9 ------> USART3_RX + PD9 ------> USART3_RX */ HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8|GPIO_PIN_9); diff --git a/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM4/Src/stm32h7xx_hal_msp.c b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM4/Src/stm32h7xx_hal_msp.c index 858912e780..c291e0ff67 100644 --- a/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM4/Src/stm32h7xx_hal_msp.c +++ b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM4/Src/stm32h7xx_hal_msp.c @@ -2,7 +2,7 @@ /** ****************************************************************************** * File Name : stm32h7xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** * @attention @@ -32,7 +32,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ diff --git a/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM7/Src/stm32h7xx_hal_msp.c b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM7/Src/stm32h7xx_hal_msp.c index b2f1998e9b..02fb8a88f2 100644 --- a/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM7/Src/stm32h7xx_hal_msp.c +++ b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM7/Src/stm32h7xx_hal_msp.c @@ -2,7 +2,7 @@ /** ****************************************************************************** * File Name : stm32h7xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** * @attention @@ -32,7 +32,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -92,15 +92,15 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PA10 ------> USART1_RX - PA9 ------> USART1_TX + PA9 ------> USART1_TX */ GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_9; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Alternate = GPIO_AF7_USART1; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); @@ -127,10 +127,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration + + /**USART1 GPIO Configuration PA10 ------> USART1_RX - PA9 ------> USART1_TX + PA9 ------> USART1_TX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_10|GPIO_PIN_9); diff --git a/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CubeMX_Config.ioc index 7e5db8c6e6..83eefbe36d 100644 --- a/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CubeMX_Config.ioc @@ -52,13 +52,15 @@ NVIC2.PriorityGroup=NVIC_PRIORITYGROUP_4 NVIC2.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC2.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true NVIC2.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false -PA10.GPIOParameters=PinAttribute +PA10.GPIOParameters=PinAttribute,GPIO_PuPd PA10.Locked=true +PA10.GPIO_PuPd=GPIO_PULLUP PA10.Mode=Asynchronous PA10.PinAttribute=CortexM7 PA10.Signal=USART1_RX -PA9.GPIOParameters=PinAttribute +PA9.GPIOParameters=PinAttribute,GPIO_PuPd PA9.Locked=true +PA9.GPIO_PuPd=GPIO_PULLUP PA9.Mode=Asynchronous PA9.PinAttribute=CortexM7 PA9.Signal=USART1_TX diff --git a/bsp/stm32/stm32h750-armfly-h7-tool/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32h750-armfly-h7-tool/board/CubeMX_Config/CubeMX_Config.ioc index d7da87788c..fd677d2731 100644 --- a/bsp/stm32/stm32h750-armfly-h7-tool/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32h750-armfly-h7-tool/board/CubeMX_Config/CubeMX_Config.ioc @@ -103,7 +103,12 @@ NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false PA1.Mode=RMII PA1.Signal=ETH_REF_CLK -PA10.Locked=true +PA9.GPIOParameters=GPIO_PuPd +PA9.GPIO_PuPd=GPIO_PULLUP +PA9.Mode=Asynchronous +PA9.Signal=USART1_TX +PA10.GPIOParameters=GPIO_PuPd +PA10.GPIO_PuPd=GPIO_PULLUP PA10.Mode=Asynchronous PA10.Signal=USART1_RX PA2.Mode=RMII @@ -115,9 +120,6 @@ PA5.Mode=Device_HS PA5.Signal=USB_OTG_HS_ULPI_CK PA7.Mode=RMII PA7.Signal=ETH_CRS_DV -PA9.Locked=true -PA9.Mode=Asynchronous -PA9.Signal=USART1_TX PB0.Mode=Device_HS PB0.Signal=USB_OTG_HS_ULPI_D1 PB1.Mode=Device_HS diff --git a/bsp/stm32/stm32h750-armfly-h7-tool/board/CubeMX_Config/Src/stm32h7xx_hal_msp.c b/bsp/stm32/stm32h750-armfly-h7-tool/board/CubeMX_Config/Src/stm32h7xx_hal_msp.c index 690d875704..726068cad2 100644 --- a/bsp/stm32/stm32h750-armfly-h7-tool/board/CubeMX_Config/Src/stm32h7xx_hal_msp.c +++ b/bsp/stm32/stm32h750-armfly-h7-tool/board/CubeMX_Config/Src/stm32h7xx_hal_msp.c @@ -2,7 +2,7 @@ /** ****************************************************************************** * File Name : stm32h7xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** * @attention @@ -32,7 +32,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -58,7 +58,7 @@ /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ - + void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); /** * Initializes the Global MSP. @@ -94,11 +94,11 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) /* USER CODE END ADC3_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_ADC3_CLK_ENABLE(); - + __HAL_RCC_GPIOF_CLK_ENABLE(); - /**ADC3 GPIO Configuration + /**ADC3 GPIO Configuration PF3 ------> ADC3_INP5 - PF8 ------> ADC3_INP7 + PF8 ------> ADC3_INP7 */ GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_8; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; @@ -127,10 +127,10 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) /* USER CODE END ADC3_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_ADC3_CLK_DISABLE(); - - /**ADC3 GPIO Configuration + + /**ADC3 GPIO Configuration PF3 ------> ADC3_INP5 - PF8 ------> ADC3_INP7 + PF8 ------> ADC3_INP7 */ HAL_GPIO_DeInit(GPIOF, GPIO_PIN_3|GPIO_PIN_8); @@ -201,10 +201,10 @@ void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac) /* USER CODE END DAC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_DAC12_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**DAC1 GPIO Configuration - PA4 ------> DAC1_OUT1 + /**DAC1 GPIO Configuration + PA4 ------> DAC1_OUT1 */ GPIO_InitStruct.Pin = GPIO_PIN_4; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; @@ -233,9 +233,9 @@ void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac) /* USER CODE END DAC1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_DAC12_CLK_DISABLE(); - - /**DAC1 GPIO Configuration - PA4 ------> DAC1_OUT1 + + /**DAC1 GPIO Configuration + PA4 ------> DAC1_OUT1 */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_4); @@ -264,11 +264,11 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) __HAL_RCC_ETH1MAC_CLK_ENABLE(); __HAL_RCC_ETH1TX_CLK_ENABLE(); __HAL_RCC_ETH1RX_CLK_ENABLE(); - + __HAL_RCC_GPIOG_CLK_ENABLE(); __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE(); - /**ETH GPIO Configuration + /**ETH GPIO Configuration PG14 ------> ETH_TXD1 PG13 ------> ETH_TXD0 PG11 ------> ETH_TX_EN @@ -277,7 +277,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) PC4 ------> ETH_RXD0 PA2 ------> ETH_MDIO PC5 ------> ETH_RXD1 - PA7 ------> ETH_CRS_DV + PA7 ------> ETH_CRS_DV */ GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_13|GPIO_PIN_11; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -324,8 +324,8 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) __HAL_RCC_ETH1MAC_CLK_DISABLE(); __HAL_RCC_ETH1TX_CLK_DISABLE(); __HAL_RCC_ETH1RX_CLK_DISABLE(); - - /**ETH GPIO Configuration + + /**ETH GPIO Configuration PG14 ------> ETH_TXD1 PG13 ------> ETH_TXD0 PG11 ------> ETH_TX_EN @@ -334,7 +334,7 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) PC4 ------> ETH_RXD0 PA2 ------> ETH_MDIO PC5 ------> ETH_RXD1 - PA7 ------> ETH_CRS_DV + PA7 ------> ETH_CRS_DV */ HAL_GPIO_DeInit(GPIOG, GPIO_PIN_14|GPIO_PIN_13|GPIO_PIN_11); @@ -365,18 +365,18 @@ void HAL_QSPI_MspInit(QSPI_HandleTypeDef* hqspi) /* USER CODE END QUADSPI_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_QSPI_CLK_ENABLE(); - + __HAL_RCC_GPIOG_CLK_ENABLE(); __HAL_RCC_GPIOF_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); - /**QUADSPI GPIO Configuration + /**QUADSPI GPIO Configuration PG6 ------> QUADSPI_BK1_NCS PF7 ------> QUADSPI_BK1_IO2 PB2 ------> QUADSPI_CLK PD13 ------> QUADSPI_BK1_IO3 PD12 ------> QUADSPI_BK1_IO1 - PD11 ------> QUADSPI_BK1_IO0 + PD11 ------> QUADSPI_BK1_IO0 */ GPIO_InitStruct.Pin = GPIO_PIN_6; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -428,14 +428,14 @@ void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef* hqspi) /* USER CODE END QUADSPI_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_QSPI_CLK_DISABLE(); - - /**QUADSPI GPIO Configuration + + /**QUADSPI GPIO Configuration PG6 ------> QUADSPI_BK1_NCS PF7 ------> QUADSPI_BK1_IO2 PB2 ------> QUADSPI_CLK PD13 ------> QUADSPI_BK1_IO3 PD12 ------> QUADSPI_BK1_IO1 - PD11 ------> QUADSPI_BK1_IO0 + PD11 ------> QUADSPI_BK1_IO0 */ HAL_GPIO_DeInit(GPIOG, GPIO_PIN_6); @@ -512,11 +512,11 @@ void HAL_MMC_MspInit(MMC_HandleTypeDef* hmmc) /* USER CODE END SDMMC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SDMMC1_CLK_ENABLE(); - + __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); - /**SDMMC1 GPIO Configuration + /**SDMMC1 GPIO Configuration PB8 ------> SDMMC1_D4 PC12 ------> SDMMC1_CK PB9 ------> SDMMC1_D5 @@ -526,7 +526,7 @@ void HAL_MMC_MspInit(MMC_HandleTypeDef* hmmc) PC9 ------> SDMMC1_D1 PC8 ------> SDMMC1_D0 PC7 ------> SDMMC1_D7 - PC6 ------> SDMMC1_D6 + PC6 ------> SDMMC1_D6 */ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -535,7 +535,7 @@ void HAL_MMC_MspInit(MMC_HandleTypeDef* hmmc) GPIO_InitStruct.Alternate = GPIO_AF12_SDIO1; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_9 + GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_9 |GPIO_PIN_8|GPIO_PIN_7|GPIO_PIN_6; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -572,8 +572,8 @@ void HAL_MMC_MspDeInit(MMC_HandleTypeDef* hmmc) /* USER CODE END SDMMC1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SDMMC1_CLK_DISABLE(); - - /**SDMMC1 GPIO Configuration + + /**SDMMC1 GPIO Configuration PB8 ------> SDMMC1_D4 PC12 ------> SDMMC1_CK PB9 ------> SDMMC1_D5 @@ -583,11 +583,11 @@ void HAL_MMC_MspDeInit(MMC_HandleTypeDef* hmmc) PC9 ------> SDMMC1_D1 PC8 ------> SDMMC1_D0 PC7 ------> SDMMC1_D7 - PC6 ------> SDMMC1_D6 + PC6 ------> SDMMC1_D6 */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_8|GPIO_PIN_9); - HAL_GPIO_DeInit(GPIOC, GPIO_PIN_12|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_9 + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_12|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_9 |GPIO_PIN_8|GPIO_PIN_7|GPIO_PIN_6); HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); @@ -615,10 +615,10 @@ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) /* USER CODE END TIM12_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM12_CLK_ENABLE(); - + __HAL_RCC_GPIOB_CLK_ENABLE(); - /**TIM12 GPIO Configuration - PB14 ------> TIM12_CH1 + /**TIM12 GPIO Configuration + PB14 ------> TIM12_CH1 */ GPIO_InitStruct.Pin = GPIO_PIN_14; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -642,10 +642,10 @@ void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) /* USER CODE BEGIN TIM12_MspPostInit 0 */ /* USER CODE END TIM12_MspPostInit 0 */ - + __HAL_RCC_GPIOH_CLK_ENABLE(); - /**TIM12 GPIO Configuration - PH9 ------> TIM12_CH2 + /**TIM12 GPIO Configuration + PH9 ------> TIM12_CH2 */ GPIO_InitStruct.Pin = GPIO_PIN_9; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -675,10 +675,10 @@ void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base) /* USER CODE END TIM12_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_TIM12_CLK_DISABLE(); - - /**TIM12 GPIO Configuration + + /**TIM12 GPIO Configuration PH9 ------> TIM12_CH2 - PB14 ------> TIM12_CH1 + PB14 ------> TIM12_CH1 */ HAL_GPIO_DeInit(GPIOH, GPIO_PIN_9); @@ -707,15 +707,15 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END UART4_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_UART4_CLK_ENABLE(); - + __HAL_RCC_GPIOH_CLK_ENABLE(); - /**UART4 GPIO Configuration + /**UART4 GPIO Configuration PH13 ------> UART4_TX - PH14 ------> UART4_RX + PH14 ------> UART4_RX */ GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Alternate = GPIO_AF8_UART4; HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); @@ -731,15 +731,15 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PA10 ------> USART1_RX - PA9 ------> USART1_TX + PA9 ------> USART1_TX */ GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_9; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Alternate = GPIO_AF7_USART1; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); @@ -766,10 +766,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END UART4_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_UART4_CLK_DISABLE(); - - /**UART4 GPIO Configuration + + /**UART4 GPIO Configuration PH13 ------> UART4_TX - PH14 ------> UART4_RX + PH14 ------> UART4_RX */ HAL_GPIO_DeInit(GPIOH, GPIO_PIN_13|GPIO_PIN_14); @@ -784,10 +784,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration + + /**USART1 GPIO Configuration PA10 ------> USART1_RX - PA9 ------> USART1_TX + PA9 ------> USART1_TX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_10|GPIO_PIN_9); @@ -812,13 +812,13 @@ void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd) /* USER CODE BEGIN USB_OTG_HS_MspInit 0 */ /* USER CODE END USB_OTG_HS_MspInit 0 */ - + __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOI_CLK_ENABLE(); __HAL_RCC_GPIOH_CLK_ENABLE(); __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USB_OTG_HS GPIO Configuration + /**USB_OTG_HS GPIO Configuration PB5 ------> USB_OTG_HS_ULPI_D7 PI11 ------> USB_OTG_HS_ULPI_DIR PH4 ------> USB_OTG_HS_ULPI_NXT @@ -830,9 +830,9 @@ void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd) PB1 ------> USB_OTG_HS_ULPI_D2 PB0 ------> USB_OTG_HS_ULPI_D1 PB10 ------> USB_OTG_HS_ULPI_D3 - PB11 ------> USB_OTG_HS_ULPI_D4 + PB11 ------> USB_OTG_HS_ULPI_D4 */ - GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_1 + GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_1 |GPIO_PIN_0|GPIO_PIN_10|GPIO_PIN_11; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -894,8 +894,8 @@ void HAL_PCD_MspDeInit(PCD_HandleTypeDef* hpcd) /* Peripheral clock disable */ __HAL_RCC_USB_OTG_HS_CLK_DISABLE(); __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE(); - - /**USB_OTG_HS GPIO Configuration + + /**USB_OTG_HS GPIO Configuration PB5 ------> USB_OTG_HS_ULPI_D7 PI11 ------> USB_OTG_HS_ULPI_DIR PH4 ------> USB_OTG_HS_ULPI_NXT @@ -907,9 +907,9 @@ void HAL_PCD_MspDeInit(PCD_HandleTypeDef* hpcd) PB1 ------> USB_OTG_HS_ULPI_D2 PB0 ------> USB_OTG_HS_ULPI_D1 PB10 ------> USB_OTG_HS_ULPI_D3 - PB11 ------> USB_OTG_HS_ULPI_D4 + PB11 ------> USB_OTG_HS_ULPI_D4 */ - HAL_GPIO_DeInit(GPIOB, GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_1 + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_1 |GPIO_PIN_0|GPIO_PIN_10|GPIO_PIN_11); HAL_GPIO_DeInit(GPIOI, GPIO_PIN_11); diff --git a/bsp/stm32/stm32h750-artpi-h750/.config b/bsp/stm32/stm32h750-artpi-h750/.config index c31157512a..3125ac5607 100644 --- a/bsp/stm32/stm32h750-artpi-h750/.config +++ b/bsp/stm32/stm32h750-artpi-h750/.config @@ -21,6 +21,12 @@ CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 CONFIG_IDLE_THREAD_STACK_SIZE=256 # CONFIG_RT_USING_TIMER_SOFT is not set + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set CONFIG_RT_DEBUG=y # CONFIG_RT_DEBUG_COLOR is not set # CONFIG_RT_DEBUG_INIT_CONFIG is not set @@ -52,6 +58,7 @@ CONFIG_RT_USING_MEMPOOL=y # CONFIG_RT_USING_NOHEAP is not set CONFIG_RT_USING_SMALL_MEM=y # CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_USERHEAP is not set # CONFIG_RT_USING_MEMTRACE is not set CONFIG_RT_USING_HEAP=y @@ -64,7 +71,7 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart4" -CONFIG_RT_VER_NUM=0x40003 +CONFIG_RT_VER_NUM=0x40004 CONFIG_ARCH_ARM=y CONFIG_RT_USING_CPU_FFS=y CONFIG_ARCH_ARM_CORTEX_M=y @@ -115,6 +122,8 @@ CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 # CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set # CONFIG_RT_SERIAL_USING_DMA is not set CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_CAN is not set @@ -153,6 +162,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_LIBC is not set # CONFIG_RT_USING_PTHREADS is not set CONFIG_RT_LIBC_USING_TIME=y +CONFIG_RT_LIBC_FIXED_TIMEZONE=8 # # Network @@ -189,8 +199,14 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_RT_LINK is not set # CONFIG_RT_USING_LWP is not set +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + # # RT-Thread online packages # @@ -258,8 +274,6 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_LIBRWS is not set # CONFIG_PKG_USING_TCPSERVER is not set # CONFIG_PKG_USING_PROTOBUF_C is not set -# CONFIG_PKG_USING_ONNX_PARSER is not set -# CONFIG_PKG_USING_ONNX_BACKEND is not set # CONFIG_PKG_USING_DLT645 is not set # CONFIG_PKG_USING_QXWZ is not set # CONFIG_PKG_USING_SMTP_CLIENT is not set @@ -271,6 +285,12 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_NMEALIB is not set # CONFIG_PKG_USING_AGILE_JSMN is not set # CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_BSAL is not set # # security packages @@ -296,6 +316,9 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_STEMWIN is not set # CONFIG_PKG_USING_WAVPLAYER is not set # CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set # # tools packages @@ -307,9 +330,12 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_RDB is not set # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set # CONFIG_PKG_USING_ADBD is not set # CONFIG_PKG_USING_COREMARK is not set # CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set # CONFIG_PKG_USING_NR_MICRO_SHELL is not set # CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set # CONFIG_PKG_USING_LUNAR_CALENDAR is not set @@ -317,6 +343,18 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_GPS_RMC is not set # CONFIG_PKG_USING_URLENCODE is not set # CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set # # system packages @@ -335,6 +373,8 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_CMSIS is not set # CONFIG_PKG_USING_DFS_YAFFS is not set # CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set # CONFIG_PKG_USING_THREAD_POOL is not set # CONFIG_PKG_USING_ROBOTS is not set # CONFIG_PKG_USING_EV is not set @@ -344,7 +384,25 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_RAMDISK is not set # CONFIG_PKG_USING_MININI is not set # CONFIG_PKG_USING_QBOOT is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# # CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set # # peripheral libraries and drivers @@ -353,6 +411,7 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set # CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_U8G2 is not set @@ -397,6 +456,28 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_AGILE_CONSOLE is not set # CONFIG_PKG_USING_LD3320 is not set # CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set # # miscellaneous packages @@ -406,6 +487,7 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_FASTLZ is not set # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set # CONFIG_PKG_USING_MULTIBUTTON is not set # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set @@ -426,16 +508,72 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set # CONFIG_PKG_USING_HELLO is not set # CONFIG_PKG_USING_VI is not set -# CONFIG_PKG_USING_NNOM is not set -# CONFIG_PKG_USING_LIBANN is not set -# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_KI is not set # CONFIG_PKG_USING_ARMv7M_DWT is not set # CONFIG_PKG_USING_VT100 is not set -# CONFIG_PKG_USING_ULAPACK is not set # CONFIG_PKG_USING_UKAL is not set # CONFIG_PKG_USING_CRCLIB is not set + +# +# games: games run on RT-Thread console +# # CONFIG_PKG_USING_THREES is not set # CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set + +# +# Privated Packages of RealThread +# +# CONFIG_PKG_USING_CODEC is not set +# CONFIG_PKG_USING_PLAYER is not set +# CONFIG_PKG_USING_MPLAYER is not set +# CONFIG_PKG_USING_PERSIMMON_SRC is not set +# CONFIG_PKG_USING_JS_PERSIMMON is not set +# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set + +# +# Network Utilities +# +# CONFIG_PKG_USING_WICED is not set +# CONFIG_PKG_USING_CLOUDSDK is not set +# CONFIG_PKG_USING_POWER_MANAGER is not set +# CONFIG_PKG_USING_RT_OTA is not set +# CONFIG_PKG_USING_RTINSIGHT is not set +# CONFIG_PKG_USING_SMARTCONFIG is not set +# CONFIG_PKG_USING_RTX is not set +# CONFIG_RT_USING_TESTCASE is not set +# CONFIG_PKG_USING_NGHTTP2 is not set +# CONFIG_PKG_USING_AVS is not set +# CONFIG_PKG_USING_ALI_LINKKIT is not set +# CONFIG_PKG_USING_STS is not set +# CONFIG_PKG_USING_DLMS is not set +# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set +# CONFIG_PKG_USING_ZBAR is not set +# CONFIG_PKG_USING_MCF is not set +# CONFIG_PKG_USING_URPC is not set +# CONFIG_PKG_USING_DCM is not set +# CONFIG_PKG_USING_EMQ is not set +# CONFIG_PKG_USING_CFGM is not set +# CONFIG_PKG_USING_RT_CMSIS_DAP is not set +# CONFIG_PKG_USING_SMODULE is not set +# CONFIG_PKG_USING_SNFD is not set +# CONFIG_PKG_USING_UDBD is not set +# CONFIG_PKG_USING_BENCHMARK is not set +# CONFIG_PKG_USING_UBJSON is not set +# CONFIG_PKG_USING_DATATYPE is not set +# CONFIG_PKG_USING_FASTFS is not set +# CONFIG_PKG_USING_RIL is not set +# CONFIG_PKG_USING_WATCH_DCM_SVC is not set +# CONFIG_PKG_USING_WATCH_APP_FWK is not set +# CONFIG_PKG_USING_GUI_TEST is not set +# CONFIG_PKG_USING_PMEM is not set +# CONFIG_PKG_USING_LWRDP is not set +# CONFIG_PKG_USING_MASAN is not set CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32H7=y diff --git a/bsp/stm32/stm32h750-artpi-h750/board/CubeMX_Config/Core/Inc/main.h b/bsp/stm32/stm32h750-artpi-h750/board/CubeMX_Config/Core/Inc/main.h index 4677beb2d9..b6b51e650c 100644 --- a/bsp/stm32/stm32h750-artpi-h750/board/CubeMX_Config/Core/Inc/main.h +++ b/bsp/stm32/stm32h750-artpi-h750/board/CubeMX_Config/Core/Inc/main.h @@ -51,7 +51,7 @@ extern "C" { /* USER CODE END EM */ /* Exported functions prototypes ---------------------------------------------*/ -void Error_Handler(void); + /* USER CODE BEGIN EFP */ diff --git a/bsp/stm32/stm32h750-artpi-h750/board/CubeMX_Config/Core/Src/stm32h7xx_hal_msp.c b/bsp/stm32/stm32h750-artpi-h750/board/CubeMX_Config/Core/Src/stm32h7xx_hal_msp.c index 77a19bb14b..cf63245b6f 100644 --- a/bsp/stm32/stm32h750-artpi-h750/board/CubeMX_Config/Core/Src/stm32h7xx_hal_msp.c +++ b/bsp/stm32/stm32h750-artpi-h750/board/CubeMX_Config/Core/Src/stm32h7xx_hal_msp.c @@ -101,14 +101,14 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) */ GPIO_InitStruct.Pin = GPIO_PIN_9; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Alternate = GPIO_AF8_UART4; HAL_GPIO_Init(GPIOI, &GPIO_InitStruct); GPIO_InitStruct.Pin = GPIO_PIN_0; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Alternate = GPIO_AF8_UART4; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); @@ -153,7 +153,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USART3 interrupt Init */ HAL_NVIC_SetPriority(USART3_IRQn, 0, 0); HAL_NVIC_EnableIRQ(USART3_IRQn); - + NVIC_EnableIRQ(USART3_IRQn); /* USER CODE BEGIN USART3_MspInit 1 */ diff --git a/bsp/stm32/stm32h750-artpi-h750/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32h750-artpi-h750/board/CubeMX_Config/CubeMX_Config.ioc index a71fd18402..0c04bf4b43 100644 --- a/bsp/stm32/stm32h750-artpi-h750/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32h750-artpi-h750/board/CubeMX_Config/CubeMX_Config.ioc @@ -27,8 +27,8 @@ Mcu.PinsNb=11 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32H750XBHx -MxCube.Version=6.0.1 -MxDb.Version=DB.6.0.0 +MxCube.Version=6.2.1 +MxDb.Version=DB.6.0.21 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.ForceEnableDMAVector=true @@ -42,13 +42,17 @@ NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true NVIC.UART4_IRQn=true\:0\:0\:false\:false\:true\:true\:true NVIC.USART3_IRQn=true\:0\:0\:false\:false\:true\:true\:true NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +PA0.GPIOParameters=GPIO_PuPd +PA0.GPIO_PuPd=GPIO_PULLUP PA0.Locked=true PA0.Mode=Asynchronous PA0.Signal=UART4_TX -PB10.Locked=true +PB10.GPIOParameters=GPIO_PuPd +PB10.GPIO_PuPd=GPIO_PULLUP PB10.Mode=Asynchronous PB10.Signal=USART3_TX -PB11.Locked=true +PB11.GPIOParameters=GPIO_PuPd +PB11.GPIO_PuPd=GPIO_PULLUP PB11.Mode=Asynchronous PB11.Signal=USART3_RX PD11.Mode=CTS_RTS @@ -63,6 +67,8 @@ PI11.Locked=true PI11.Signal=GPIO_Output PI8.Locked=true PI8.Signal=GPIO_Output +PI9.GPIOParameters=GPIO_PuPd +PI9.GPIO_PuPd=GPIO_PULLUP PI9.Locked=true PI9.Mode=Asynchronous PI9.Signal=UART4_RX @@ -77,7 +83,7 @@ ProjectManager.CustomerFirmwarePackage= ProjectManager.DefaultFWLocation=true ProjectManager.DeletePrevious=true ProjectManager.DeviceId=STM32H750XBHx -ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.8.0 +ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.9.0 ProjectManager.FreePins=false ProjectManager.HalAssertFull=false ProjectManager.HeapSize=0x200 diff --git a/bsp/stm32/stm32h750-artpi-h750/rtconfig.h b/bsp/stm32/stm32h750-artpi-h750/rtconfig.h index 8d75171203..f6bda0feda 100644 --- a/bsp/stm32/stm32h750-artpi-h750/rtconfig.h +++ b/bsp/stm32/stm32h750-artpi-h750/rtconfig.h @@ -16,6 +16,9 @@ #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 #define IDLE_THREAD_STACK_SIZE 256 + +/* kservice optimization */ + #define RT_DEBUG /* Inter-Thread communication */ @@ -38,7 +41,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart4" -#define RT_VER_NUM 0x40003 +#define RT_VER_NUM 0x40004 #define ARCH_ARM #define RT_USING_CPU_FFS #define ARCH_ARM_CORTEX_M @@ -78,6 +81,7 @@ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 #define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_PIN @@ -87,6 +91,7 @@ /* POSIX layer and C standard library */ #define RT_LIBC_USING_TIME +#define RT_LIBC_FIXED_TIMEZONE 8 /* Network */ @@ -108,6 +113,9 @@ /* Utilities */ +/* RT-Thread Utestcases */ + + /* RT-Thread online packages */ /* IoT - internet of things */ @@ -139,14 +147,29 @@ /* system packages */ +/* Micrium: Micrium software products porting for RT-Thread */ + + /* peripheral libraries and drivers */ +/* AI packages */ + + /* miscellaneous packages */ /* samples: kernel and components samples */ + +/* games: games run on RT-Thread console */ + + +/* Privated Packages of RealThread */ + + +/* Network Utilities */ + #define SOC_FAMILY_STM32 #define SOC_SERIES_STM32H7 diff --git a/bsp/stm32/stm32h750-artpi-h750/rtconfig.py b/bsp/stm32/stm32h750-artpi-h750/rtconfig.py index 2c9cbdd792..13a0ebbdb9 100644 --- a/bsp/stm32/stm32h750-artpi-h750/rtconfig.py +++ b/bsp/stm32/stm32h750-artpi-h750/rtconfig.py @@ -94,6 +94,40 @@ elif PLATFORM == 'armcc': POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' +elif PLATFORM == 'armclang': + # toolchains + CC = 'armclang' + CXX = 'armclang' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M7.fp.sp ' + CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-M7 ' + CFLAGS += ' -mcpu=cortex-M7 -mfpu=fpv4-sp-d16 ' + CFLAGS += ' -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar ' + CFLAGS += ' -gdwarf-3 -ffunction-sections ' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers ' + LFLAGS += ' --list rt-thread.map ' + LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" ' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib' + + EXEC_PATH += '/ARM/ARMCLANG/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O1' # armclang recommend + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + elif PLATFORM == 'iar': # toolchains CC = 'iccarm' diff --git a/bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc index fd1de238ea..1305e437aa 100644 --- a/bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc @@ -27,8 +27,12 @@ NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.SVC_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true +PA2.GPIOParameters=GPIO_PuPd +PA2.GPIO_PuPd=GPIO_PULLUP PA2.Mode=Asynchronous PA2.Signal=USART2_TX +PA3.GPIOParameters=GPIO_PuPd +PA3.GPIO_PuPd=GPIO_PULLUP PA3.Mode=Asynchronous PA3.Signal=USART2_RX PC14-OSC32_IN.Mode=LSE-External-Oscillator diff --git a/bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/Src/stm32l0xx_hal_msp.c b/bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/Src/stm32l0xx_hal_msp.c index 3570c90a39..8d69a8a2f7 100644 --- a/bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/Src/stm32l0xx_hal_msp.c +++ b/bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/Src/stm32l0xx_hal_msp.c @@ -2,7 +2,7 @@ /** ****************************************************************************** * File Name : stm32l0xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** * @attention @@ -32,7 +32,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -93,15 +93,15 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART2 GPIO Configuration + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF4_USART2; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); @@ -128,10 +128,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART2_CLK_DISABLE(); - - /**USART2 GPIO Configuration + + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3); diff --git a/bsp/stm32/stm32l053-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32l053-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc index 73cbefbcd2..e31f64da5b 100644 --- a/bsp/stm32/stm32l053-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32l053-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc @@ -24,14 +24,15 @@ Mcu.PinsNb=11 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32L053R8Tx -MxCube.Version=4.27.0 -MxDb.Version=DB.4.0.270 -NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false -NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false -NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false -NVIC.SVC_IRQn=true\:0\:0\:false\:false\:true\:false -NVIC.SysTick_IRQn=true\:0\:0\:true\:false\:true\:true -NVIC.USART2_IRQn=true\:0\:0\:false\:false\:true\:true +MxCube.Version=6.2.1 +MxDb.Version=DB.6.0.21 +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.SVC_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.SysTick_IRQn=true\:0\:0\:true\:false\:true\:true\:true +NVIC.USART2_IRQn=true\:0\:0\:false\:false\:true\:true\:true PA13.GPIOParameters=GPIO_Label PA13.GPIO_Label=TMS PA13.Locked=true @@ -42,13 +43,15 @@ PA14.GPIO_Label=TCK PA14.Locked=true PA14.Mode=Serial_Wire PA14.Signal=SYS_SWCLK -PA2.GPIOParameters=GPIO_Label +PA2.GPIOParameters=GPIO_PuPd,GPIO_Label PA2.GPIO_Label=USART_TX +PA2.GPIO_PuPd=GPIO_PULLUP PA2.Locked=true PA2.Mode=Asynchronous PA2.Signal=USART2_TX -PA3.GPIOParameters=GPIO_Label +PA3.GPIOParameters=GPIO_PuPd,GPIO_Label PA3.GPIO_Label=USART_RX +PA3.GPIO_PuPd=GPIO_PULLUP PA3.Locked=true PA3.Mode=Asynchronous PA3.Signal=USART2_RX @@ -67,14 +70,6 @@ PC14-OSC32_IN.Signal=RCC_OSC32_IN PC15-OSC32_OUT.Locked=true PC15-OSC32_OUT.Mode=LSE-External-Oscillator PC15-OSC32_OUT.Signal=RCC_OSC32_OUT -PCC.Checker=true -PCC.Line=STM32L0x3 -PCC.MCU=STM32L053R(6-8)Tx -PCC.PartNumber=STM32L053R8Tx -PCC.Seq0=0 -PCC.Series=STM32L0 -PCC.Temperature=25 -PCC.Vdd=null PH0-OSC_IN.Locked=true PH0-OSC_IN.Mode=HSE-External-Oscillator PH0-OSC_IN.Signal=RCC_OSC_IN @@ -91,7 +86,7 @@ ProjectManager.CustomerFirmwarePackage= ProjectManager.DefaultFWLocation=true ProjectManager.DeletePrevious=true ProjectManager.DeviceId=STM32L053R8Tx -ProjectManager.FirmwarePackage=STM32Cube FW_L0 V1.10.0 +ProjectManager.FirmwarePackage=STM32Cube FW_L0 V1.12.0 ProjectManager.FreePins=false ProjectManager.HalAssertFull=false ProjectManager.HeapSize=0x200 @@ -104,6 +99,7 @@ ProjectManager.PreviousToolchain= ProjectManager.ProjectBuild=false ProjectManager.ProjectFileName=CubeMX_Config.ioc ProjectManager.ProjectName=CubeMX_Config +ProjectManager.RegisterCallBack= ProjectManager.StackSize=0x400 ProjectManager.TargetToolchain=MDK-ARM V5 ProjectManager.ToolChainLocation= diff --git a/bsp/stm32/stm32l053-st-nucleo/board/CubeMX_Config/Src/stm32l0xx_hal_msp.c b/bsp/stm32/stm32l053-st-nucleo/board/CubeMX_Config/Src/stm32l0xx_hal_msp.c index 8eb266519d..ac7c1552f4 100644 --- a/bsp/stm32/stm32l053-st-nucleo/board/CubeMX_Config/Src/stm32l0xx_hal_msp.c +++ b/bsp/stm32/stm32l053-st-nucleo/board/CubeMX_Config/Src/stm32l0xx_hal_msp.c @@ -1,12 +1,12 @@ /** ****************************************************************************** * File Name : stm32l0xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** ** This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether + * USER CODE END. Other portions of this file, whether * inserted by the user or by software development tools * are owned by their respective copyright owners. * @@ -78,14 +78,14 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); - - /**USART2 GPIO Configuration + + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ GPIO_InitStruct.Pin = USART_TX_Pin|USART_RX_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF4_USART2; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); @@ -110,10 +110,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART2_CLK_DISABLE(); - - /**USART2 GPIO Configuration + + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ HAL_GPIO_DeInit(GPIOA, USART_TX_Pin|USART_RX_Pin); diff --git a/bsp/stm32/stm32l412-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32l412-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc index 4727ba50c3..355a13cc67 100644 --- a/bsp/stm32/stm32l412-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32l412-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc @@ -54,14 +54,14 @@ PA14\ (JTCK/SWCLK).Mode=Serial_Wire PA14\ (JTCK/SWCLK).Signal=SYS_JTCK-SWCLK PA2.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label PA2.GPIO_Label=USART_TX -PA2.GPIO_PuPd=GPIO_NOPULL +PA2.GPIO_PuPd=GPIO_PULLUP PA2.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH PA2.Locked=true PA2.Mode=Asynchronous PA2.Signal=USART2_TX PA3.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label PA3.GPIO_Label=USART_RX -PA3.GPIO_PuPd=GPIO_NOPULL +PA3.GPIO_PuPd=GPIO_PULLUP PA3.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH PA3.Locked=true PA3.Mode=Asynchronous diff --git a/bsp/stm32/stm32l412-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c b/bsp/stm32/stm32l412-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c index 4e7628b29c..2361ae6c6a 100644 --- a/bsp/stm32/stm32l412-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c +++ b/bsp/stm32/stm32l412-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c @@ -2,7 +2,7 @@ /** ****************************************************************************** * File Name : stm32l4xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** * @attention @@ -32,7 +32,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -93,15 +93,15 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART2 GPIO Configuration + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ GPIO_InitStruct.Pin = USART_TX_Pin|USART_RX_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF7_USART2; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); @@ -128,10 +128,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART2_CLK_DISABLE(); - - /**USART2 GPIO Configuration + + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ HAL_GPIO_DeInit(GPIOA, USART_TX_Pin|USART_RX_Pin); diff --git a/bsp/stm32/stm32l431-BearPi/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32l431-BearPi/board/CubeMX_Config/CubeMX_Config.ioc index ce0175ce52..7600b27cb1 100644 --- a/bsp/stm32/stm32l431-BearPi/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32l431-BearPi/board/CubeMX_Config/CubeMX_Config.ioc @@ -37,12 +37,14 @@ NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false -PA10.Locked=true -PA10.Mode=Asynchronous -PA10.Signal=USART1_RX -PA9.Locked=true +PA9.GPIOParameters=GPIO_PuPd +PA9.GPIO_PuPd=GPIO_PULLUP PA9.Mode=Asynchronous PA9.Signal=USART1_TX +PA10.GPIOParameters=GPIO_PuPd +PA10.GPIO_PuPd=GPIO_PULLUP +PA10.Mode=Asynchronous +PA10.Signal=USART1_RX PB13.Locked=true PB13.Mode=Simplex_Bidirectional_Master PB13.Signal=SPI2_SCK diff --git a/bsp/stm32/stm32l431-BearPi/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c b/bsp/stm32/stm32l431-BearPi/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c index 943aadf254..44adfa4b3b 100644 --- a/bsp/stm32/stm32l431-BearPi/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c +++ b/bsp/stm32/stm32l431-BearPi/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c @@ -2,7 +2,7 @@ /** ****************************************************************************** * File Name : stm32l4xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** * @attention @@ -32,7 +32,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -93,12 +93,12 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI2_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); - /**SPI2 GPIO Configuration + /**SPI2 GPIO Configuration PC3 ------> SPI2_MOSI - PB13 ------> SPI2_SCK + PB13 ------> SPI2_SCK */ GPIO_InitStruct.Pin = GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -136,10 +136,10 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI2_CLK_DISABLE(); - - /**SPI2 GPIO Configuration + + /**SPI2 GPIO Configuration PC3 ------> SPI2_MOSI - PB13 ------> SPI2_SCK + PB13 ------> SPI2_SCK */ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_3); @@ -168,15 +168,15 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF7_USART1; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); @@ -203,10 +203,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration + + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); diff --git a/bsp/stm32/stm32l432-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32l432-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc index 7304c402cd..844c31b868 100644 --- a/bsp/stm32/stm32l432-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32l432-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc @@ -54,14 +54,16 @@ PA14\ (JTCK-SWCLK).GPIO_Label=SWCLK PA14\ (JTCK-SWCLK).Locked=true PA14\ (JTCK-SWCLK).Mode=Serial_Wire PA14\ (JTCK-SWCLK).Signal=SYS_JTCK-SWCLK -PA15\ (JTDI).GPIOParameters=GPIO_Speed,GPIO_Label +PA15\ (JTDI).GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label PA15\ (JTDI).GPIO_Label=VCP_RX +PA15\ (JTDI).GPIO_PuPd=GPIO_PULLUP PA15\ (JTDI).GPIO_Speed=GPIO_SPEED_FREQ_MEDIUM PA15\ (JTDI).Locked=true PA15\ (JTDI).Mode=Asynchronous PA15\ (JTDI).Signal=USART2_RX -PA2.GPIOParameters=GPIO_Speed,GPIO_Label +PA2.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label PA2.GPIO_Label=VCP_TX +PA2.GPIO_PuPd=GPIO_PULLUP PA2.GPIO_Speed=GPIO_SPEED_FREQ_MEDIUM PA2.Locked=true PA2.Mode=Asynchronous @@ -76,14 +78,6 @@ PC14-OSC32_IN\ (PC14).Signal=RCC_OSC32_IN PC15-OSC32_OUT\ (PC15).Locked=true PC15-OSC32_OUT\ (PC15).Mode=LSE-External-Oscillator PC15-OSC32_OUT\ (PC15).Signal=RCC_OSC32_OUT -PCC.Checker=true -PCC.Line=STM32L4x2 -PCC.MCU=STM32L432K(B-C)Ux -PCC.PartNumber=STM32L432KCUx -PCC.Seq0=0 -PCC.Series=STM32L4 -PCC.Temperature=25 -PCC.Vdd=null PinOutPanel.RotationAngle=0 ProjectManager.AskForMigrate=true ProjectManager.BackupPrevious=false diff --git a/bsp/stm32/stm32l432-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c b/bsp/stm32/stm32l432-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c index 78ee2bd1f2..e778c888fa 100644 --- a/bsp/stm32/stm32l432-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c +++ b/bsp/stm32/stm32l432-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c @@ -1,38 +1,19 @@ +/* USER CODE BEGIN Header */ /** ****************************************************************************** - * File Name : stm32l4xx_hal_msp.c - * Description : This file provides code for the MSP Initialization - * and de-Initialization codes. + * @file stm32l4xx_hal_msp.c + * @brief This file provides code for the MSP Initialization + * and de-Initialization codes. ****************************************************************************** - ** This notice applies to any and all portions of this file - * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether - * inserted by the user or by software development tools - * are owned by their respective copyright owners. + * @attention * - * COPYRIGHT(c) 2019 STMicroelectronics + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -122,21 +103,21 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); - - /**USART2 GPIO Configuration + + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA15 (JTDI) ------> USART2_RX + PA15 (JTDI) ------> USART2_RX */ GPIO_InitStruct.Pin = VCP_TX_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM; GPIO_InitStruct.Alternate = GPIO_AF7_USART2; HAL_GPIO_Init(VCP_TX_GPIO_Port, &GPIO_InitStruct); GPIO_InitStruct.Pin = VCP_RX_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM; GPIO_InitStruct.Alternate = GPIO_AF3_USART2; HAL_GPIO_Init(VCP_RX_GPIO_Port, &GPIO_InitStruct); @@ -158,10 +139,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART2_CLK_DISABLE(); - - /**USART2 GPIO Configuration + + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA15 (JTDI) ------> USART2_RX + PA15 (JTDI) ------> USART2_RX */ HAL_GPIO_DeInit(GPIOA, VCP_TX_Pin|VCP_RX_Pin); diff --git a/bsp/stm32/stm32l433-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32l433-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc index 6dce14b8ae..c6ebbe94cb 100644 --- a/bsp/stm32/stm32l433-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32l433-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc @@ -57,7 +57,12 @@ NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false PA1.Mode=Full_Duplex_Master PA1.Signal=SPI1_SCK -PA10.Locked=true +PA9.GPIOParameters=GPIO_PuPd +PA9.GPIO_PuPd=GPIO_PULLUP +PA9.Mode=Asynchronous +PA9.Signal=USART1_TX +PA10.GPIOParameters=GPIO_PuPd +PA10.GPIO_PuPd=GPIO_PULLUP PA10.Mode=Asynchronous PA10.Signal=USART1_RX PA11.Mode=Full_Duplex_Master @@ -75,9 +80,12 @@ PA14\ (JTCK-SWCLK).Locked=true PA14\ (JTCK-SWCLK).Mode=Serial_Wire PA14\ (JTCK-SWCLK).Signal=SYS_JTCK-SWCLK PA2.Locked=true +PA2.GPIOParameters=GPIO_PuPd +PA2.GPIO_PuPd=GPIO_PULLUP PA2.Mode=Asynchronous PA2.Signal=USART2_TX -PA3.Locked=true +PA3.GPIOParameters=GPIO_PuPd +PA3.GPIO_PuPd=GPIO_PULLUP PA3.Mode=Asynchronous PA3.Signal=USART2_RX PA4.GPIOParameters=GPIO_Label @@ -100,9 +108,6 @@ PA7.GPIOParameters=GPIO_Label PA7.GPIO_Label=SMPS_SW [TS3A44159PWR_IN1_2] PA7.Locked=true PA7.Signal=GPIO_Output -PA9.Locked=true -PA9.Mode=Asynchronous -PA9.Signal=USART1_TX PB13.GPIOParameters=GPIO_Label PB13.GPIO_Label=LD4 [green Led] PB13.Locked=true diff --git a/bsp/stm32/stm32l433-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c b/bsp/stm32/stm32l433-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c index 1ce37c7e25..140de137cc 100644 --- a/bsp/stm32/stm32l433-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c +++ b/bsp/stm32/stm32l433-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c @@ -2,7 +2,7 @@ /** ****************************************************************************** * File Name : stm32l4xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** * @attention @@ -32,7 +32,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -181,12 +181,12 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**SPI1 GPIO Configuration + /**SPI1 GPIO Configuration PA1 ------> SPI1_SCK PA11 ------> SPI1_MISO - PA12 ------> SPI1_MOSI + PA12 ------> SPI1_MOSI */ GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_11|GPIO_PIN_12; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -217,11 +217,11 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI1_CLK_DISABLE(); - - /**SPI1 GPIO Configuration + + /**SPI1 GPIO Configuration PA1 ------> SPI1_SCK PA11 ------> SPI1_MISO - PA12 ------> SPI1_MOSI + PA12 ------> SPI1_MOSI */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1|GPIO_PIN_11|GPIO_PIN_12); @@ -292,15 +292,15 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF7_USART1; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); @@ -316,15 +316,15 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART2 GPIO Configuration + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF7_USART2; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); @@ -351,10 +351,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration + + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); @@ -369,10 +369,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART2_CLK_DISABLE(); - - /**USART2 GPIO Configuration + + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3); diff --git a/bsp/stm32/stm32l452-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32l452-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc index 0d6a6e0fcf..5ecfc94d87 100644 --- a/bsp/stm32/stm32l452-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32l452-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc @@ -46,6 +46,12 @@ NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false PA1.Mode=Full_Duplex_Master PA1.Signal=SPI1_SCK +PA9.GPIOParameters=GPIO_PuPd +PA9.GPIO_PuPd=GPIO_PULLUP +PA9.Mode=Asynchronous +PA9.Signal=USART1_TX +PA10.GPIOParameters=GPIO_PuPd +PA10.GPIO_PuPd=GPIO_PULLUP PA10.Mode=Asynchronous PA10.Signal=USART1_RX PA13\ (JTMS/SWDIO).GPIOParameters=GPIO_Label @@ -61,7 +67,7 @@ PA14\ (JTCK/SWCLK).Signal=SYS_JTCK-SWCLK PA2.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode PA2.GPIO_Label=USART_TX PA2.GPIO_Mode=GPIO_MODE_AF_PP -PA2.GPIO_PuPd=GPIO_NOPULL +PA2.GPIO_PuPd=GPIO_PULLUP PA2.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH PA2.Locked=true PA2.Mode=Asynchronous @@ -69,7 +75,7 @@ PA2.Signal=USART2_TX PA3.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode PA3.GPIO_Label=USART_RX PA3.GPIO_Mode=GPIO_MODE_AF_PP -PA3.GPIO_PuPd=GPIO_NOPULL +PA3.GPIO_PuPd=GPIO_PULLUP PA3.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH PA3.Locked=true PA3.Mode=Asynchronous @@ -85,8 +91,6 @@ PA6.Mode=Full_Duplex_Master PA6.Signal=SPI1_MISO PA7.Mode=Full_Duplex_Master PA7.Signal=SPI1_MOSI -PA9.Mode=Asynchronous -PA9.Signal=USART1_TX PB3\ (JTDO/TRACESWO).GPIOParameters=GPIO_Label PB3\ (JTDO/TRACESWO).GPIO_Label=SWO PB3\ (JTDO/TRACESWO).Locked=true diff --git a/bsp/stm32/stm32l452-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c b/bsp/stm32/stm32l452-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c index 1d5d64d3b5..101aa6b6b1 100644 --- a/bsp/stm32/stm32l452-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c +++ b/bsp/stm32/stm32l452-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c @@ -2,7 +2,7 @@ /** ****************************************************************************** * File Name : stm32l4xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** * @attention @@ -32,7 +32,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -93,12 +93,12 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**SPI1 GPIO Configuration + /**SPI1 GPIO Configuration PA1 ------> SPI1_SCK PA6 ------> SPI1_MISO - PA7 ------> SPI1_MOSI + PA7 ------> SPI1_MOSI */ GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_6|GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -129,11 +129,11 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI1_CLK_DISABLE(); - - /**SPI1 GPIO Configuration + + /**SPI1 GPIO Configuration PA1 ------> SPI1_SCK PA6 ------> SPI1_MISO - PA7 ------> SPI1_MOSI + PA7 ------> SPI1_MOSI */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1|GPIO_PIN_6|GPIO_PIN_7); @@ -160,15 +160,15 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF7_USART1; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); @@ -184,15 +184,15 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART2 GPIO Configuration + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ GPIO_InitStruct.Pin = USART_TX_Pin|USART_RX_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF7_USART2; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); @@ -219,10 +219,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration + + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); @@ -237,10 +237,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART2_CLK_DISABLE(); - - /**USART2 GPIO Configuration + + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ HAL_GPIO_DeInit(GPIOA, USART_TX_Pin|USART_RX_Pin); diff --git a/bsp/stm32/stm32l475-atk-pandora/.config b/bsp/stm32/stm32l475-atk-pandora/.config index 18377e1e4e..e7dac17128 100644 --- a/bsp/stm32/stm32l475-atk-pandora/.config +++ b/bsp/stm32/stm32l475-atk-pandora/.config @@ -21,6 +21,12 @@ CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 CONFIG_IDLE_THREAD_STACK_SIZE=256 # CONFIG_RT_USING_TIMER_SOFT is not set + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set CONFIG_RT_DEBUG=y CONFIG_RT_DEBUG_COLOR=y # CONFIG_RT_DEBUG_INIT_CONFIG is not set @@ -52,6 +58,7 @@ CONFIG_RT_USING_MEMPOOL=y # CONFIG_RT_USING_NOHEAP is not set CONFIG_RT_USING_SMALL_MEM=y # CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_USERHEAP is not set # CONFIG_RT_USING_MEMTRACE is not set CONFIG_RT_USING_HEAP=y @@ -64,7 +71,7 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=256 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" -CONFIG_RT_VER_NUM=0x40002 +CONFIG_RT_VER_NUM=0x40004 CONFIG_ARCH_ARM=y CONFIG_RT_USING_CPU_FFS=y CONFIG_ARCH_ARM_CORTEX_M=y @@ -115,14 +122,17 @@ CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 # CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_USING_SERIAL_V1 is not set +CONFIG_RT_USING_SERIAL_V2=y CONFIG_RT_SERIAL_USING_DMA=y -CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set # CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set @@ -135,7 +145,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_SENSOR is not set # CONFIG_RT_USING_TOUCH is not set # CONFIG_RT_USING_HWCRYPTO is not set -# CONFIG_RT_USING_ENCODER is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set # CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_WIFI is not set @@ -150,7 +160,7 @@ CONFIG_RT_USING_PIN=y # # CONFIG_RT_USING_LIBC is not set # CONFIG_RT_USING_PTHREADS is not set -CONFIG_RT_LIBC_USING_TIME=y +# CONFIG_RT_LIBC_USING_TIME is not set # # Network @@ -187,8 +197,14 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_RT_LINK is not set # CONFIG_RT_USING_LWP is not set +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + # # RT-Thread online packages # @@ -196,10 +212,15 @@ CONFIG_RT_LIBC_USING_TIME=y # # IoT - internet of things # +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set # CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set @@ -226,6 +247,8 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set # CONFIG_PKG_USING_AT_DEVICE is not set # CONFIG_PKG_USING_ATSRV_SOCKET is not set # CONFIG_PKG_USING_WIZNET is not set @@ -237,7 +260,10 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set # CONFIG_PKG_USING_NIMBLE is not set # CONFIG_PKG_USING_OTA_DOWNLOADER is not set # CONFIG_PKG_USING_IPMSG is not set @@ -246,8 +272,23 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_LIBRWS is not set # CONFIG_PKG_USING_TCPSERVER is not set # CONFIG_PKG_USING_PROTOBUF_C is not set -# CONFIG_PKG_USING_ONNX_PARSER is not set -# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_BSAL is not set # # security packages @@ -255,6 +296,8 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_MBEDTLS is not set # CONFIG_PKG_USING_libsodium is not set # CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set # # language packages @@ -270,6 +313,10 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_MUPDF is not set # CONFIG_PKG_USING_STEMWIN is not set # CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set # # tools packages @@ -281,7 +328,31 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_RDB is not set # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set # CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set # # system packages @@ -293,14 +364,43 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set # CONFIG_PKG_USING_CMSIS is not set # CONFIG_PKG_USING_DFS_YAFFS is not set # CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set # CONFIG_PKG_USING_THREAD_POOL is not set # CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set # # peripheral libraries and drivers @@ -308,6 +408,8 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_SENSORS_DRIVERS is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_U8G2 is not set @@ -316,10 +418,16 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_SX12XX is not set # CONFIG_PKG_USING_SIGNAL_LED is not set # CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set # CONFIG_PKG_USING_WM_LIBRARIES is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set # CONFIG_PKG_USING_INFRARED is not set # CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set # CONFIG_PKG_USING_AT24CXX is not set # CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set # CONFIG_PKG_USING_AD7746 is not set @@ -327,7 +435,47 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_I2C_TOOLS is not set # CONFIG_PKG_USING_NRF24L01 is not set # CONFIG_PKG_USING_TOUCH_DRIVERS is not set -# CONFIG_PKG_USING_LCD_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set # # miscellaneous packages @@ -337,6 +485,7 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_FASTLZ is not set # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set # CONFIG_PKG_USING_MULTIBUTTON is not set # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set @@ -345,6 +494,8 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_TINYFRAME is not set # CONFIG_PKG_USING_KENDRYTE_DEMO is not set # CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set # # samples: kernel and components samples @@ -355,9 +506,72 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set # CONFIG_PKG_USING_HELLO is not set # CONFIG_PKG_USING_VI is not set -# CONFIG_PKG_USING_NNOM is not set -# CONFIG_PKG_USING_LIBANN is not set -# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set + +# +# games: games run on RT-Thread console +# +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set + +# +# Privated Packages of RealThread +# +# CONFIG_PKG_USING_CODEC is not set +# CONFIG_PKG_USING_PLAYER is not set +# CONFIG_PKG_USING_MPLAYER is not set +# CONFIG_PKG_USING_PERSIMMON_SRC is not set +# CONFIG_PKG_USING_JS_PERSIMMON is not set +# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set + +# +# Network Utilities +# +# CONFIG_PKG_USING_WICED is not set +# CONFIG_PKG_USING_CLOUDSDK is not set +# CONFIG_PKG_USING_POWER_MANAGER is not set +# CONFIG_PKG_USING_RT_OTA is not set +# CONFIG_PKG_USING_RTINSIGHT is not set +# CONFIG_PKG_USING_SMARTCONFIG is not set +# CONFIG_PKG_USING_RTX is not set +# CONFIG_RT_USING_TESTCASE is not set +# CONFIG_PKG_USING_NGHTTP2 is not set +# CONFIG_PKG_USING_AVS is not set +# CONFIG_PKG_USING_ALI_LINKKIT is not set +# CONFIG_PKG_USING_STS is not set +# CONFIG_PKG_USING_DLMS is not set +# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set +# CONFIG_PKG_USING_ZBAR is not set +# CONFIG_PKG_USING_MCF is not set +# CONFIG_PKG_USING_URPC is not set +# CONFIG_PKG_USING_DCM is not set +# CONFIG_PKG_USING_EMQ is not set +# CONFIG_PKG_USING_CFGM is not set +# CONFIG_PKG_USING_RT_CMSIS_DAP is not set +# CONFIG_PKG_USING_SMODULE is not set +# CONFIG_PKG_USING_SNFD is not set +# CONFIG_PKG_USING_UDBD is not set +# CONFIG_PKG_USING_BENCHMARK is not set +# CONFIG_PKG_USING_UBJSON is not set +# CONFIG_PKG_USING_DATATYPE is not set +# CONFIG_PKG_USING_FASTFS is not set +# CONFIG_PKG_USING_RIL is not set +# CONFIG_PKG_USING_WATCH_DCM_SVC is not set +# CONFIG_PKG_USING_WATCH_APP_FWK is not set +# CONFIG_PKG_USING_GUI_TEST is not set +# CONFIG_PKG_USING_PMEM is not set +# CONFIG_PKG_USING_LWRDP is not set +# CONFIG_PKG_USING_MASAN is not set CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32L4=y @@ -370,12 +584,15 @@ CONFIG_SOC_STM32L475VE=y # Onboard Peripheral Drivers # CONFIG_BSP_USING_STLINK_TO_USART=y +# CONFIG_BSP_USING_KEY is not set # CONFIG_BSP_USING_QSPI_FLASH is not set # CONFIG_BSP_USING_SPI_LCD is not set # CONFIG_BSP_USING_SDCARD is not set # CONFIG_BSP_USING_ICM20608 is not set # CONFIG_BSP_USING_AHT10 is not set # CONFIG_BSP_USING_AUDIO is not set +# CONFIG_BSP_USING_USB_AUDIO is not set +# CONFIG_BSP_USING_WIFI is not set # # On-chip Peripheral Drivers @@ -384,7 +601,14 @@ CONFIG_BSP_USING_GPIO=y CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART1=y # CONFIG_BSP_UART1_RX_USING_DMA is not set -# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_UART1_TX_USING_DMA is not set +CONFIG_BSP_UART1_RX_BUFSIZE=256 +CONFIG_BSP_UART1_TX_BUFSIZE=0 +CONFIG_BSP_USING_UART2=y +CONFIG_BSP_UART2_RX_USING_DMA=y +CONFIG_BSP_UART2_TX_USING_DMA=y +CONFIG_BSP_UART2_RX_BUFSIZE=256 +CONFIG_BSP_UART2_TX_BUFSIZE=256 # CONFIG_BSP_USING_ON_CHIP_FLASH is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_QSPI is not set @@ -393,9 +617,11 @@ CONFIG_BSP_USING_UART1=y # CONFIG_BSP_USING_TIM is not set # CONFIG_BSP_USING_PWM is not set # CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_DAC is not set # CONFIG_BSP_USING_ONCHIP_RTC is not set # CONFIG_BSP_USING_WDT is not set -# CONFIG_BSP_USING_USBD_FS is not set +# CONFIG_BSP_USING_USBD is not set +# CONFIG_BSP_USING_STM32_SDIO is not set # CONFIG_BSP_USING_CRC is not set # CONFIG_BSP_USING_RNG is not set # CONFIG_BSP_USING_UDID is not set diff --git a/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/STM32L475VE.ioc b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/STM32L475VE.ioc index 3a59471b8a..e7711fa510 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/STM32L475VE.ioc +++ b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/STM32L475VE.ioc @@ -95,8 +95,8 @@ Mcu.PinsNb=56 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32L475VETx -MxCube.Version=6.0.1 -MxDb.Version=DB.6.0.0 +MxCube.Version=6.2.1 +MxDb.Version=DB.6.0.21 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.ForceEnableDMAVector=true @@ -109,6 +109,8 @@ NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +PA10.GPIOParameters=GPIO_PuPd +PA10.GPIO_PuPd=GPIO_PULLUP PA10.Mode=Asynchronous PA10.Signal=USART1_RX PA11.Mode=Device_Only @@ -119,8 +121,12 @@ PA13\ (JTMS-SWDIO).Mode=Serial_Wire PA13\ (JTMS-SWDIO).Signal=SYS_JTMS-SWDIO PA14\ (JTCK-SWCLK).Mode=Serial_Wire PA14\ (JTCK-SWCLK).Signal=SYS_JTCK-SWCLK +PA2.GPIOParameters=GPIO_PuPd +PA2.GPIO_PuPd=GPIO_PULLUP PA2.Mode=Asynchronous PA2.Signal=USART2_TX +PA3.GPIOParameters=GPIO_PuPd +PA3.GPIO_PuPd=GPIO_PULLUP PA3.Mode=Asynchronous PA3.Signal=USART2_RX PA4.Signal=COMP_DAC11_group @@ -130,6 +136,8 @@ PA6.Mode=Full_Duplex_Master PA6.Signal=SPI1_MISO PA7.Mode=Full_Duplex_Master PA7.Signal=SPI1_MOSI +PA9.GPIOParameters=GPIO_PuPd +PA9.GPIO_PuPd=GPIO_PULLUP PA9.Mode=Asynchronous PA9.Signal=USART1_TX PB10.Signal=S_TIM2_CH3 @@ -211,7 +219,7 @@ ProjectManager.CustomerFirmwarePackage= ProjectManager.DefaultFWLocation=true ProjectManager.DeletePrevious=true ProjectManager.DeviceId=STM32L475VETx -ProjectManager.FirmwarePackage=STM32Cube FW_L4 V1.16.0 +ProjectManager.FirmwarePackage=STM32Cube FW_L4 V1.17.0 ProjectManager.FreePins=false ProjectManager.HalAssertFull=false ProjectManager.HeapSize=0x200 diff --git a/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c index a3f28f6117..77fb0eecc6 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c +++ b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c @@ -2,12 +2,12 @@ /** ****************************************************************************** * File Name : stm32l4xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** ** This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether + * USER CODE END. Other portions of this file, whether * inserted by the user or by software development tools * are owned by their respective copyright owners. * @@ -52,7 +52,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -869,7 +869,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) */ GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF7_USART1; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); @@ -893,7 +893,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) */ GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF7_USART2; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); diff --git a/bsp/stm32/stm32l475-atk-pandora/board/Kconfig b/bsp/stm32/stm32l475-atk-pandora/board/Kconfig index bc71249fa0..e8a0713647 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/Kconfig +++ b/bsp/stm32/stm32l475-atk-pandora/board/Kconfig @@ -152,23 +152,59 @@ menu "On-chip Peripheral Drivers" default y select RT_USING_SERIAL if BSP_USING_UART - config BSP_USING_UART1 - bool "Enable UART1" + menuconfig BSP_USING_UART1 + bool "Enable UART1 (Debugger)" default y + if BSP_USING_UART1 + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n - config BSP_UART1_RX_USING_DMA - bool "Enable UART1 RX DMA" - depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA - default n + config BSP_UART1_TX_USING_DMA + bool "Enable UART1 TX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n - config BSP_USING_UART2 + config BSP_UART1_RX_BUFSIZE + int "Set UART1 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART1_TX_BUFSIZE + int "Set UART1 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + + menuconfig BSP_USING_UART2 bool "Enable UART2" default n + if BSP_USING_UART2 + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n - config BSP_UART2_RX_USING_DMA - bool "Enable UART2 RX DMA" - depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA - default n + config BSP_UART2_TX_USING_DMA + bool "Enable UART2 TX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + config BSP_UART2_RX_BUFSIZE + int "Set UART2 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART2_TX_BUFSIZE + int "Set UART2 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 256 + endif endif config BSP_USING_ON_CHIP_FLASH diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd.c index f80ca3a4b2..6ec90f880c 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd.c +++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd.c @@ -446,18 +446,33 @@ void lcd_draw_line(rt_uint16_t x1, rt_uint16_t y1, rt_uint16_t x2, rt_uint16_t y if (y1 == y2) { /* fast draw transverse line */ - lcd_address_set(x1, y1, x2, y2); + rt_uint32_t x_offset = 0; + if (x1 < x2) + { + x_offset = x2 - x1; + lcd_address_set(x1, y1, x2, y2); + } + else if (x1 > x2) + { + x_offset = x1 - x2; + lcd_address_set(x2, y2, x1, y1); + } + else + { + lcd_draw_point(x1, y1); + return; + } rt_uint8_t line_buf[480] = {0}; - for (i = 0; i < x2 - x1; i++) + for (i = 0; i < x_offset; i++) { line_buf[2 * i] = FORE_COLOR >> 8; line_buf[2 * i + 1] = FORE_COLOR; } rt_pin_write(LCD_DC_PIN, PIN_HIGH); - rt_spi_send(spi_dev_lcd, line_buf, (x2 - x1) * 2); + rt_spi_send(spi_dev_lcd, line_buf, x_offset * 2); return ; } diff --git a/bsp/stm32/stm32l475-atk-pandora/project.uvprojx b/bsp/stm32/stm32l475-atk-pandora/project.uvprojx index 1a187748bd..cdeaf7aa9f 100644 --- a/bsp/stm32/stm32l475-atk-pandora/project.uvprojx +++ b/bsp/stm32/stm32l475-atk-pandora/project.uvprojx @@ -1,7 +1,10 @@ + 2.1 +
### uVision Project, (C) Keil Software
+ rt-thread @@ -13,31 +16,31 @@ STM32L475VETx STMicroelectronics - Keil.STM32L4xx_DFP.2.0.0 + Keil.STM32L4xx_DFP.2.2.0 http://www.keil.com/pack IRAM(0x20000000,0x00018000) IRAM2(0x10000000,0x00008000) IROM(0x08000000,0x00080000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE - - + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_512 -FS08000000 -FL080000 -FP0($$Device:STM32L475VETx$CMSIS\Flash\STM32L4xx_512.FLM)) 0 $$Device:STM32L475VETx$Drivers\CMSIS\Device\ST\STM32L4xx\Include\stm32l4xx.h - - - - - - - - - + + + + + + + + + $$Device:STM32L475VETx$CMSIS\SVD\STM32L4x5.svd 0 0 - - - - - + + + + + 0 0 @@ -59,8 +62,8 @@ 0 0 - - + + 0 0 0 @@ -69,8 +72,8 @@ 0 0 - - + + 0 0 0 @@ -80,14 +83,14 @@ 1 0 fromelf --bin !L --output rtthread.bin - + 0 0 0 0 0 - + 0 @@ -101,8 +104,8 @@ 0 0 3 - - + + 1 @@ -136,10 +139,10 @@ 1 BIN\UL2CM3.DLL "" () - - - - + + + + 0 @@ -172,7 +175,7 @@ 0 0 "Cortex-M4" - + 0 0 0 @@ -181,6 +184,7 @@ 0 0 2 + 0 1 0 8 @@ -304,7 +308,7 @@ 0x8000 - + 1 @@ -331,10 +335,10 @@ 0 0 - - USE_HAL_DRIVER, __RTTHREAD__, STM32L475xx - - .;applications;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;board\CubeMX_Config\Inc;board\ports;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\components\finsh;.;..\..\..\include;..\..\..\components\libc\compilers\common;..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Inc;..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Include;..\libraries\STM32L4xx_HAL\CMSIS\Include + + USE_HAL_DRIVER, __RTTHREAD__, STM32L475xx, __CLK_TCK=RT_TICK_PER_SECOND + + .;applications;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;board\CubeMX_Config\Inc;board\ports;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\components\finsh;.;..\..\..\include;..\..\..\components\libc\compilers\common;..\..\..\components\libc\compilers\common\none-gcc;..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Inc;..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Include;..\libraries\STM32L4xx_HAL\CMSIS\Include;..\..\..\examples\utest\testcases\kernel @@ -349,10 +353,10 @@ 0 0 - - - - + + + + @@ -364,13 +368,13 @@ 0 0x08000000 0x20000000 - + .\board\linker_scripts\link.sct - - - - - + + + + + @@ -387,35 +391,27 @@ CPU - - - backtrace.c - 1 - ..\..\..\libcpu\arm\common\backtrace.c - - div0.c 1 ..\..\..\libcpu\arm\common\div0.c - - showmem.c 1 ..\..\..\libcpu\arm\common\showmem.c - - + + backtrace.c + 1 + ..\..\..\libcpu\arm\common\backtrace.c + cpuport.c 1 ..\..\..\libcpu\arm\cortex-m4\cpuport.c - - context_rvds.S 2 @@ -431,102 +427,76 @@ 1 ..\..\..\components\drivers\misc\pin.c - - - serial.c + serial_v2.c 1 - ..\..\..\components\drivers\serial\serial.c + ..\..\..\components\drivers\serial\serial_v2.c - - - - completion.c - 1 - ..\..\..\components\drivers\src\completion.c - - - dataqueue.c 1 ..\..\..\components\drivers\src\dataqueue.c - - - pipe.c + workqueue.c 1 - ..\..\..\components\drivers\src\pipe.c + ..\..\..\components\drivers\src\workqueue.c - - - - ringblk_buf.c - 1 - ..\..\..\components\drivers\src\ringblk_buf.c - - - ringbuffer.c 1 ..\..\..\components\drivers\src\ringbuffer.c - - + + ringblk_buf.c + 1 + ..\..\..\components\drivers\src\ringblk_buf.c + + + pipe.c + 1 + ..\..\..\components\drivers\src\pipe.c + + + completion.c + 1 + ..\..\..\components\drivers\src\completion.c + waitqueue.c 1 ..\..\..\components\drivers\src\waitqueue.c - - - workqueue.c - 1 - ..\..\..\components\drivers\src\workqueue.c - - Drivers - - - board.c - 1 - board\board.c - - stm32l4xx_hal_msp.c 1 board\CubeMX_Config\Src\stm32l4xx_hal_msp.c - - + + board.c + 1 + board\board.c + startup_stm32l475xx.s 2 ..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Source\Templates\arm\startup_stm32l475xx.s - - drv_gpio.c 1 ..\libraries\HAL_Drivers\drv_gpio.c - - - drv_usart.c + drv_usart_v2.c 1 - ..\libraries\HAL_Drivers\drv_usart.c + ..\libraries\HAL_Drivers\drv_usart_v2.c - - drv_common.c 1 @@ -542,15 +512,11 @@ 1 ..\..\..\components\finsh\shell.c - - cmd.c 1 ..\..\..\components\finsh\cmd.c - - msh.c 1 @@ -562,110 +528,69 @@ Kernel - clock.c + scheduler.c 1 - ..\..\..\src\clock.c + ..\..\..\src\scheduler.c - - - - components.c - 1 - ..\..\..\src\components.c - - - - - device.c - 1 - ..\..\..\src\device.c - - - idle.c 1 ..\..\..\src\idle.c - - - - ipc.c - 1 - ..\..\..\src\ipc.c - - - - - irq.c - 1 - ..\..\..\src\irq.c - - - - - kservice.c - 1 - ..\..\..\src\kservice.c - - - - - mem.c - 1 - ..\..\..\src\mem.c - - - - - mempool.c - 1 - ..\..\..\src\mempool.c - - - object.c 1 ..\..\..\src\object.c - - - scheduler.c + components.c 1 - ..\..\..\src\scheduler.c + ..\..\..\src\components.c - - - - signal.c - 1 - ..\..\..\src\signal.c - - - thread.c 1 ..\..\..\src\thread.c - - + + mempool.c + 1 + ..\..\..\src\mempool.c + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + clock.c + 1 + ..\..\..\src\clock.c + timer.c 1 ..\..\..\src\timer.c - - - - libc - - time.c + mem.c 1 - ..\..\..\components\libc\compilers\common\time.c + ..\..\..\src\mem.c + + + device.c + 1 + ..\..\..\src\device.c + + + irq.c + 1 + ..\..\..\src\irq.c @@ -673,158 +598,120 @@ Libraries - system_stm32l4xx.c + stm32l4xx_hal_cryp.c 1 - ..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Source\Templates\system_stm32l4xx.c + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cryp.c - - - stm32l4xx_hal.c + stm32l4xx_hal_uart.c 1 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal.c + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart.c - - - stm32l4xx_hal_comp.c + stm32l4xx_hal_usart.c 1 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_comp.c + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_usart.c - - stm32l4xx_hal_cortex.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cortex.c - - + + stm32l4xx_hal_gpio.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c + + + stm32l4xx_hal_dma.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c + + + stm32l4xx_hal_pwr.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c + + + stm32l4xx_hal_rcc_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c + + + stm32l4xx_hal_rcc.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc.c + + + stm32l4xx_hal_dma_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma_ex.c + + + stm32l4xx_hal_exti.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_exti.c + stm32l4xx_hal_crc.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc.c - - + + stm32l4xx_hal.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal.c + + + stm32l4xx_hal_usart_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_usart_ex.c + + + stm32l4xx_hal_uart_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart_ex.c + stm32l4xx_hal_crc_ex.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc_ex.c - - - stm32l4xx_hal_cryp.c + stm32l4xx_hal_comp.c 1 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cryp.c + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_comp.c + + + stm32l4xx_hal_pwr_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c + + + stm32l4xx_hal_rng.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rng.c + + + system_stm32l4xx.c + 1 + ..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Source\Templates\system_stm32l4xx.c - - stm32l4xx_hal_cryp_ex.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cryp_ex.c - - - stm32l4xx_hal_dma.c - 1 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c - - - - - stm32l4xx_hal_dma_ex.c - 1 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma_ex.c - - - - - stm32l4xx_hal_exti.c - 1 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_exti.c - - - - - stm32l4xx_hal_pwr.c - 1 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c - - - - - stm32l4xx_hal_pwr_ex.c - 1 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c - - - - - stm32l4xx_hal_rcc.c - 1 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc.c - - - - - stm32l4xx_hal_rcc_ex.c - 1 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c - - - - - stm32l4xx_hal_rng.c - 1 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rng.c - - - - - stm32l4xx_hal_gpio.c - 1 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c - - - - - stm32l4xx_hal_uart.c - 1 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart.c - - - - - stm32l4xx_hal_uart_ex.c - 1 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart_ex.c - - - - - stm32l4xx_hal_usart.c - 1 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_usart.c - - - - - stm32l4xx_hal_usart_ex.c - 1 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_usart_ex.c - - + - - - + + + + diff --git a/bsp/stm32/stm32l475-atk-pandora/rtconfig.h b/bsp/stm32/stm32l475-atk-pandora/rtconfig.h index e18e51ae82..5f3f8a812b 100644 --- a/bsp/stm32/stm32l475-atk-pandora/rtconfig.h +++ b/bsp/stm32/stm32l475-atk-pandora/rtconfig.h @@ -16,6 +16,9 @@ #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 #define IDLE_THREAD_STACK_SIZE 256 + +/* kservice optimization */ + #define RT_DEBUG #define RT_DEBUG_COLOR @@ -39,7 +42,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 256 #define RT_CONSOLE_DEVICE_NAME "uart1" -#define RT_VER_NUM 0x40002 +#define RT_VER_NUM 0x40004 #define ARCH_ARM #define RT_USING_CPU_FFS #define ARCH_ARM_CORTEX_M @@ -79,8 +82,8 @@ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL +#define RT_USING_SERIAL_V2 #define RT_SERIAL_USING_DMA -#define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_PIN /* Using USB */ @@ -88,7 +91,6 @@ /* POSIX layer and C standard library */ -#define RT_LIBC_USING_TIME /* Network */ @@ -110,6 +112,9 @@ /* Utilities */ +/* RT-Thread Utestcases */ + + /* RT-Thread online packages */ /* IoT - internet of things */ @@ -141,14 +146,29 @@ /* system packages */ +/* Micrium: Micrium software products porting for RT-Thread */ + + /* peripheral libraries and drivers */ +/* AI packages */ + + /* miscellaneous packages */ /* samples: kernel and components samples */ + +/* games: games run on RT-Thread console */ + + +/* Privated Packages of RealThread */ + + +/* Network Utilities */ + #define SOC_FAMILY_STM32 #define SOC_SERIES_STM32L4 @@ -165,6 +185,13 @@ #define BSP_USING_GPIO #define BSP_USING_UART #define BSP_USING_UART1 +#define BSP_UART1_RX_BUFSIZE 256 +#define BSP_UART1_TX_BUFSIZE 0 +#define BSP_USING_UART2 +#define BSP_UART2_RX_USING_DMA +#define BSP_UART2_TX_USING_DMA +#define BSP_UART2_RX_BUFSIZE 256 +#define BSP_UART2_TX_BUFSIZE 256 /* Board extended module Drivers */ diff --git a/bsp/stm32/stm32l475-atk-pandora/rtconfig.py b/bsp/stm32/stm32l475-atk-pandora/rtconfig.py index 9314a28375..4250a3d152 100644 --- a/bsp/stm32/stm32l475-atk-pandora/rtconfig.py +++ b/bsp/stm32/stm32l475-atk-pandora/rtconfig.py @@ -91,7 +91,6 @@ elif PLATFORM == 'armcc': CXXFLAGS = CFLAGS - CFLAGS += ' -std=c99' POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' @@ -105,7 +104,7 @@ elif PLATFORM == 'armclang': TARGET_EXT = 'axf' DEVICE = ' --cpu Cortex-M4.fp ' - CFLAGS = ' -xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 ' + CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-m4 ' CFLAGS += ' -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 ' CFLAGS += ' -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar ' CFLAGS += ' -gdwarf-3 -ffunction-sections ' @@ -125,6 +124,7 @@ elif PLATFORM == 'armclang': CFLAGS += ' -O2' CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' diff --git a/bsp/stm32/stm32l475-st-discovery/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c b/bsp/stm32/stm32l475-st-discovery/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c index a7fa9c3e37..37ccf5eef2 100644 --- a/bsp/stm32/stm32l475-st-discovery/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c +++ b/bsp/stm32/stm32l475-st-discovery/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c @@ -2,12 +2,12 @@ /** ****************************************************************************** * File Name : stm32l4xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** ** This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether + * USER CODE END. Other portions of this file, whether * inserted by the user or by software development tools * are owned by their respective copyright owners. * @@ -52,7 +52,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -113,15 +113,15 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - + __HAL_RCC_GPIOB_CLK_ENABLE(); - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PB6 ------> USART1_TX - PB7 ------> USART1_RX + PB7 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF7_USART1; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); @@ -148,10 +148,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration + + /**USART1 GPIO Configuration PB6 ------> USART1_TX - PB7 ------> USART1_RX + PB7 ------> USART1_RX */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6|GPIO_PIN_7); diff --git a/bsp/stm32/stm32l476-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32l476-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc index 7d78ad4047..92fbb30a7d 100644 --- a/bsp/stm32/stm32l476-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32l476-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc @@ -222,7 +222,14 @@ Mcu.Pin11=PB10 Mcu.Pin12=PB14 RCC.PLLN=10 Mcu.Pin10=PA7 +PA2.GPIOParameters=GPIO_PuPd +PA2.GPIO_PuPd=GPIO_PULLUP PA2.Mode=Asynchronous +PA2.Signal=USART2_TX +PA3.GPIOParameters=GPIO_PuPd +PA3.GPIO_PuPd=GPIO_PULLUP +PA3.Mode=Asynchronous +PA3.Signal=USART2_RX VP_LPTIM1_VS_LPTIM_counterModeInternalClock.Signal=LPTIM1_VS_LPTIM_counterModeInternalClock RCC.PWRFreq_Value=80000000 RCC.I2C2Freq_Value=80000000 diff --git a/bsp/stm32/stm32l476-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c b/bsp/stm32/stm32l476-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c index dda464c29e..32c1642b53 100644 --- a/bsp/stm32/stm32l476-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c +++ b/bsp/stm32/stm32l476-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c @@ -2,12 +2,12 @@ /** ****************************************************************************** * File Name : stm32l4xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** ** This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether + * USER CODE END. Other portions of this file, whether * inserted by the user or by software development tools * are owned by their respective copyright owners. * @@ -52,7 +52,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -118,10 +118,10 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) if(HAL_RCC_ADC_CLK_ENABLED==1){ __HAL_RCC_ADC_CLK_ENABLE(); } - + __HAL_RCC_GPIOC_CLK_ENABLE(); - /**ADC1 GPIO Configuration - PC0 ------> ADC1_IN1 + /**ADC1 GPIO Configuration + PC0 ------> ADC1_IN1 */ GPIO_InitStruct.Pin = GPIO_PIN_0; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL; @@ -142,10 +142,10 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) if(HAL_RCC_ADC_CLK_ENABLED==1){ __HAL_RCC_ADC_CLK_ENABLE(); } - + __HAL_RCC_GPIOC_CLK_ENABLE(); - /**ADC2 GPIO Configuration - PC1 ------> ADC2_IN2 + /**ADC2 GPIO Configuration + PC1 ------> ADC2_IN2 */ GPIO_InitStruct.Pin = GPIO_PIN_1; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL; @@ -166,10 +166,10 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) if(HAL_RCC_ADC_CLK_ENABLED==1){ __HAL_RCC_ADC_CLK_ENABLE(); } - + __HAL_RCC_GPIOC_CLK_ENABLE(); - /**ADC3 GPIO Configuration - PC2 ------> ADC3_IN3 + /**ADC3 GPIO Configuration + PC2 ------> ADC3_IN3 */ GPIO_InitStruct.Pin = GPIO_PIN_2; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL; @@ -201,9 +201,9 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) if(HAL_RCC_ADC_CLK_ENABLED==0){ __HAL_RCC_ADC_CLK_DISABLE(); } - - /**ADC1 GPIO Configuration - PC0 ------> ADC1_IN1 + + /**ADC1 GPIO Configuration + PC0 ------> ADC1_IN1 */ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_0); @@ -221,9 +221,9 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) if(HAL_RCC_ADC_CLK_ENABLED==0){ __HAL_RCC_ADC_CLK_DISABLE(); } - - /**ADC2 GPIO Configuration - PC1 ------> ADC2_IN2 + + /**ADC2 GPIO Configuration + PC1 ------> ADC2_IN2 */ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1); @@ -241,9 +241,9 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) if(HAL_RCC_ADC_CLK_ENABLED==0){ __HAL_RCC_ADC_CLK_DISABLE(); } - - /**ADC3 GPIO Configuration - PC2 ------> ADC3_IN3 + + /**ADC3 GPIO Configuration + PC2 ------> ADC3_IN3 */ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_2); @@ -358,12 +358,12 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**SPI1 GPIO Configuration + /**SPI1 GPIO Configuration PA5 ------> SPI1_SCK PA6 ------> SPI1_MISO - PA7 ------> SPI1_MOSI + PA7 ------> SPI1_MOSI */ GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -383,13 +383,13 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI2_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); - /**SPI2 GPIO Configuration + /**SPI2 GPIO Configuration PC3 ------> SPI2_MOSI PB10 ------> SPI2_SCK - PB14 ------> SPI2_MISO + PB14 ------> SPI2_MISO */ GPIO_InitStruct.Pin = GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -416,12 +416,12 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI3_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI3_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); - /**SPI3 GPIO Configuration + /**SPI3 GPIO Configuration PC10 ------> SPI3_SCK PC11 ------> SPI3_MISO - PC12 ------> SPI3_MOSI + PC12 ------> SPI3_MOSI */ GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -452,11 +452,11 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI1_CLK_DISABLE(); - - /**SPI1 GPIO Configuration + + /**SPI1 GPIO Configuration PA5 ------> SPI1_SCK PA6 ------> SPI1_MISO - PA7 ------> SPI1_MOSI + PA7 ------> SPI1_MOSI */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7); @@ -471,11 +471,11 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI2_CLK_DISABLE(); - - /**SPI2 GPIO Configuration + + /**SPI2 GPIO Configuration PC3 ------> SPI2_MOSI PB10 ------> SPI2_SCK - PB14 ------> SPI2_MISO + PB14 ------> SPI2_MISO */ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_3); @@ -492,11 +492,11 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI3_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI3_CLK_DISABLE(); - - /**SPI3 GPIO Configuration + + /**SPI3 GPIO Configuration PC10 ------> SPI3_SCK PC11 ------> SPI3_MISO - PC12 ------> SPI3_MOSI + PC12 ------> SPI3_MOSI */ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12); @@ -611,15 +611,15 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART2 GPIO Configuration + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF7_USART2; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); @@ -646,10 +646,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART2_CLK_DISABLE(); - - /**USART2 GPIO Configuration + + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3); diff --git a/bsp/stm32/stm32l496-ali-developer/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32l496-ali-developer/board/CubeMX_Config/CubeMX_Config.ioc index 851bf513a1..f74b8b254b 100644 --- a/bsp/stm32/stm32l496-ali-developer/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32l496-ali-developer/board/CubeMX_Config/CubeMX_Config.ioc @@ -86,8 +86,12 @@ PA13\ (JTMS/SWDIO).Mode=Serial_Wire PA13\ (JTMS/SWDIO).Signal=SYS_JTMS-SWDIO PA14\ (JTCK/SWCLK).Mode=Serial_Wire PA14\ (JTCK/SWCLK).Signal=SYS_JTCK-SWCLK +PA2.GPIOParameters=GPIO_PuPd +PA2.GPIO_PuPd=GPIO_PULLUP PA2.Mode=Asynchronous PA2.Signal=USART2_TX +PA3.GPIOParameters=GPIO_PuPd +PA3.GPIO_PuPd=GPIO_PULLUP PA3.Mode=Asynchronous PA3.Signal=USART2_RX PA5.Locked=true @@ -101,11 +105,15 @@ PA9.Locked=true PA9.Mode=Full_Duplex_Master PA9.Signal=SPI2_SCK PB10.Locked=true +PB10.GPIOParameters=GPIO_PuPd +PB10.GPIO_PuPd=GPIO_PULLUP PB10.Mode=Asynchronous PB10.Signal=LPUART1_RX PB11.Locked=true PB11.Mode=Asynchronous PB11.Signal=LPUART1_TX +PB11.GPIOParameters=GPIO_PuPd +PB11.GPIO_PuPd=GPIO_PULLUP PC1.Mode=Full_Duplex_Master PC1.Signal=SPI2_MOSI PC10.Mode=SD_4_bits_Wide_bus diff --git a/bsp/stm32/stm32l496-ali-developer/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c b/bsp/stm32/stm32l496-ali-developer/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c index 1b769dd9c6..d3c1d9fa89 100644 --- a/bsp/stm32/stm32l496-ali-developer/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c +++ b/bsp/stm32/stm32l496-ali-developer/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c @@ -2,12 +2,12 @@ /** ****************************************************************************** * File Name : stm32l4xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** ** This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether + * USER CODE END. Other portions of this file, whether * inserted by the user or by software development tools * are owned by their respective copyright owners. * @@ -52,7 +52,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -78,7 +78,7 @@ /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ - + void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); /** * Initializes the Global MSP. @@ -116,11 +116,11 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) /* USER CODE END ADC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_ADC_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); - /**ADC1 GPIO Configuration + /**ADC1 GPIO Configuration PC2 ------> ADC1_IN3 - PC3 ------> ADC1_IN4 + PC3 ------> ADC1_IN4 */ GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL; @@ -151,10 +151,10 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) /* USER CODE END ADC1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_ADC_CLK_DISABLE(); - - /**ADC1 GPIO Configuration + + /**ADC1 GPIO Configuration PC2 ------> ADC1_IN3 - PC3 ------> ADC1_IN4 + PC3 ------> ADC1_IN4 */ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_2|GPIO_PIN_3); @@ -182,15 +182,15 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END LPUART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_LPUART1_CLK_ENABLE(); - + __HAL_RCC_GPIOB_CLK_ENABLE(); - /**LPUART1 GPIO Configuration + /**LPUART1 GPIO Configuration PB10 ------> LPUART1_RX - PB11 ------> LPUART1_TX + PB11 ------> LPUART1_TX */ GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF8_LPUART1; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); @@ -206,15 +206,15 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART2 GPIO Configuration + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF7_USART2; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); @@ -230,15 +230,15 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART3_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART3_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); - /**USART3 GPIO Configuration + /**USART3 GPIO Configuration PC4 ------> USART3_TX - PC5 ------> USART3_RX + PC5 ------> USART3_RX */ GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF7_USART3; HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); @@ -267,10 +267,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END LPUART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_LPUART1_CLK_DISABLE(); - - /**LPUART1 GPIO Configuration + + /**LPUART1 GPIO Configuration PB10 ------> LPUART1_RX - PB11 ------> LPUART1_TX + PB11 ------> LPUART1_TX */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_10|GPIO_PIN_11); @@ -285,10 +285,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART2_CLK_DISABLE(); - - /**USART2 GPIO Configuration + + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3); @@ -303,10 +303,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART3_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART3_CLK_DISABLE(); - - /**USART3 GPIO Configuration + + /**USART3 GPIO Configuration PC4 ------> USART3_TX - PC5 ------> USART3_RX + PC5 ------> USART3_RX */ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_4|GPIO_PIN_5); @@ -381,18 +381,18 @@ void HAL_SD_MspInit(SD_HandleTypeDef* hsd) /* USER CODE END SDMMC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SDMMC1_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); - /**SDMMC1 GPIO Configuration + /**SDMMC1 GPIO Configuration PC8 ------> SDMMC1_D0 PC9 ------> SDMMC1_D1 PC10 ------> SDMMC1_D2 PC11 ------> SDMMC1_D3 PC12 ------> SDMMC1_CK - PD2 ------> SDMMC1_CMD + PD2 ------> SDMMC1_CMD */ - GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 |GPIO_PIN_12; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -431,16 +431,16 @@ void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) /* USER CODE END SDMMC1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SDMMC1_CLK_DISABLE(); - - /**SDMMC1 GPIO Configuration + + /**SDMMC1 GPIO Configuration PC8 ------> SDMMC1_D0 PC9 ------> SDMMC1_D1 PC10 ------> SDMMC1_D2 PC11 ------> SDMMC1_D3 PC12 ------> SDMMC1_CK - PD2 ------> SDMMC1_CMD + PD2 ------> SDMMC1_CMD */ - HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 |GPIO_PIN_12); HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); @@ -469,12 +469,12 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**SPI1 GPIO Configuration + /**SPI1 GPIO Configuration PA5 ------> SPI1_SCK PA6 ------> SPI1_MISO - PA7 ------> SPI1_MOSI + PA7 ------> SPI1_MOSI */ GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -494,14 +494,14 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI2_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); - /**SPI2 GPIO Configuration + /**SPI2 GPIO Configuration PC1 ------> SPI2_MOSI PA9 ------> SPI2_SCK - PD3 ------> SPI2_MISO + PD3 ------> SPI2_MISO */ GPIO_InitStruct.Pin = GPIO_PIN_1; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -548,11 +548,11 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI1_CLK_DISABLE(); - - /**SPI1 GPIO Configuration + + /**SPI1 GPIO Configuration PA5 ------> SPI1_SCK PA6 ------> SPI1_MISO - PA7 ------> SPI1_MOSI + PA7 ------> SPI1_MOSI */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7); @@ -567,11 +567,11 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI2_CLK_DISABLE(); - - /**SPI2 GPIO Configuration + + /**SPI2 GPIO Configuration PC1 ------> SPI2_MOSI PA9 ------> SPI2_SCK - PD3 ------> SPI2_MISO + PD3 ------> SPI2_MISO */ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1); @@ -663,12 +663,12 @@ void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) /* USER CODE BEGIN TIM3_MspPostInit 0 */ /* USER CODE END TIM3_MspPostInit 0 */ - + __HAL_RCC_GPIOE_CLK_ENABLE(); - /**TIM3 GPIO Configuration + /**TIM3 GPIO Configuration PE4 ------> TIM3_CH2 PE5 ------> TIM3_CH3 - PE6 ------> TIM3_CH4 + PE6 ------> TIM3_CH4 */ GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; diff --git a/bsp/stm32/stm32l496-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c b/bsp/stm32/stm32l496-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c index e93c9f5f34..2b5755574f 100644 --- a/bsp/stm32/stm32l496-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c +++ b/bsp/stm32/stm32l496-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c @@ -2,7 +2,7 @@ /** ****************************************************************************** * File Name : stm32l4xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** * @attention @@ -32,7 +32,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -93,16 +93,16 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END LPUART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_LPUART1_CLK_ENABLE(); - + __HAL_RCC_GPIOG_CLK_ENABLE(); HAL_PWREx_EnableVddIO2(); - /**LPUART1 GPIO Configuration + /**LPUART1 GPIO Configuration PG7 ------> LPUART1_TX - PG8 ------> LPUART1_RX + PG8 ------> LPUART1_RX */ GPIO_InitStruct.Pin = STLK_RX_Pin|STLK_TX_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF8_LPUART1; HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); @@ -129,10 +129,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END LPUART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_LPUART1_CLK_DISABLE(); - - /**LPUART1 GPIO Configuration + + /**LPUART1 GPIO Configuration PG7 ------> LPUART1_TX - PG8 ------> LPUART1_RX + PG8 ------> LPUART1_RX */ HAL_GPIO_DeInit(GPIOG, STLK_RX_Pin|STLK_TX_Pin); @@ -157,14 +157,14 @@ void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd) /* USER CODE BEGIN USB_OTG_FS_MspInit 0 */ /* USER CODE END USB_OTG_FS_MspInit 0 */ - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USB_OTG_FS GPIO Configuration + /**USB_OTG_FS GPIO Configuration PA8 ------> USB_OTG_FS_SOF PA9 ------> USB_OTG_FS_VBUS PA10 ------> USB_OTG_FS_ID PA11 ------> USB_OTG_FS_DM - PA12 ------> USB_OTG_FS_DP + PA12 ------> USB_OTG_FS_DP */ GPIO_InitStruct.Pin = USB_SOF_Pin|USB_ID_Pin|USB_DM_Pin|USB_DP_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -214,15 +214,15 @@ void HAL_PCD_MspDeInit(PCD_HandleTypeDef* hpcd) /* USER CODE END USB_OTG_FS_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USB_OTG_FS_CLK_DISABLE(); - - /**USB_OTG_FS GPIO Configuration + + /**USB_OTG_FS GPIO Configuration PA8 ------> USB_OTG_FS_SOF PA9 ------> USB_OTG_FS_VBUS PA10 ------> USB_OTG_FS_ID PA11 ------> USB_OTG_FS_DM - PA12 ------> USB_OTG_FS_DP + PA12 ------> USB_OTG_FS_DP */ - HAL_GPIO_DeInit(GPIOA, USB_SOF_Pin|USB_VBUS_Pin|USB_ID_Pin|USB_DM_Pin + HAL_GPIO_DeInit(GPIOA, USB_SOF_Pin|USB_VBUS_Pin|USB_ID_Pin|USB_DM_Pin |USB_DP_Pin); /* Disable VDDUSB */ diff --git a/bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c b/bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c index 7446f38eb7..8bb1c70fd9 100644 --- a/bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c +++ b/bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c @@ -2,7 +2,7 @@ /** ****************************************************************************** * File Name : stm32l4xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** * @attention @@ -32,7 +32,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -93,12 +93,12 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END LPUART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_LPUART1_CLK_ENABLE(); - + __HAL_RCC_GPIOG_CLK_ENABLE(); HAL_PWREx_EnableVddIO2(); - /**LPUART1 GPIO Configuration + /**LPUART1 GPIO Configuration PG7 ------> LPUART1_TX - PG8 ------> LPUART1_RX + PG8 ------> LPUART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -118,15 +118,15 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART3_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART3_CLK_ENABLE(); - + __HAL_RCC_GPIOD_CLK_ENABLE(); - /**USART3 GPIO Configuration + /**USART3 GPIO Configuration PD8 ------> USART3_TX - PD9 ------> USART3_RX + PD9 ------> USART3_RX */ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF7_USART3; HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); @@ -153,10 +153,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END LPUART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_LPUART1_CLK_DISABLE(); - - /**LPUART1 GPIO Configuration + + /**LPUART1 GPIO Configuration PG7 ------> LPUART1_TX - PG8 ------> LPUART1_RX + PG8 ------> LPUART1_RX */ HAL_GPIO_DeInit(GPIOG, GPIO_PIN_7|GPIO_PIN_8); @@ -171,10 +171,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART3_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART3_CLK_DISABLE(); - - /**USART3 GPIO Configuration + + /**USART3 GPIO Configuration PD8 ------> USART3_TX - PD9 ------> USART3_RX + PD9 ------> USART3_RX */ HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8|GPIO_PIN_9); diff --git a/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/CubeMX_Config.ioc index 1ded20f423..b5a954c18e 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/CubeMX_Config.ioc @@ -101,10 +101,12 @@ NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false -PB10.Locked=true +PB10.GPIOParameters=GPIO_PuPd +PB10.GPIO_PuPd=GPIO_PULLUP PB10.Mode=Asynchronous PB10.Signal=USART3_TX -PB11.Locked=true +PB11.GPIOParameters=GPIO_PuPd +PB11.GPIO_PuPd=GPIO_PULLUP PB11.Mode=Asynchronous PB11.Signal=USART3_RX PC14-OSC32_IN\ (PC14).Mode=LSE-External-Oscillator diff --git a/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c b/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c index 0cdb9babc3..457a8f7516 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c +++ b/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c @@ -2,12 +2,12 @@ /** ****************************************************************************** * File Name : stm32l4xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** ** This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether + * USER CODE END. Other portions of this file, whether * inserted by the user or by software development tools * are owned by their respective copyright owners. * @@ -52,7 +52,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -302,15 +302,15 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART3_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART3_CLK_ENABLE(); - + __HAL_RCC_GPIOB_CLK_ENABLE(); - /**USART3 GPIO Configuration + /**USART3 GPIO Configuration PB11 ------> USART3_RX - PB10 ------> USART3_TX + PB10 ------> USART3_TX */ GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF7_USART3; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); @@ -339,10 +339,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART3_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART3_CLK_DISABLE(); - - /**USART3 GPIO Configuration + + /**USART3 GPIO Configuration PB11 ------> USART3_RX - PB10 ------> USART3_TX + PB10 ------> USART3_TX */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_11|GPIO_PIN_10); @@ -366,8 +366,8 @@ static void HAL_FMC_MspInit(void){ FMC_Initialized = 1; /* Peripheral clock enable */ __HAL_RCC_FMC_CLK_ENABLE(); - - /** FMC GPIO Configuration + + /** FMC GPIO Configuration PE0 ------> FMC_NBL0 PE1 ------> FMC_NBL1 PD0 ------> FMC_D2 @@ -412,9 +412,9 @@ static void HAL_FMC_MspInit(void){ PF12 ------> FMC_A6 PE11 ------> FMC_D8 */ - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_3 - |GPIO_PIN_5|GPIO_PIN_10|GPIO_PIN_9|GPIO_PIN_15 - |GPIO_PIN_8|GPIO_PIN_14|GPIO_PIN_7|GPIO_PIN_13 + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_3 + |GPIO_PIN_5|GPIO_PIN_10|GPIO_PIN_9|GPIO_PIN_15 + |GPIO_PIN_8|GPIO_PIN_14|GPIO_PIN_7|GPIO_PIN_13 |GPIO_PIN_12|GPIO_PIN_11; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -422,9 +422,9 @@ static void HAL_FMC_MspInit(void){ GPIO_InitStruct.Alternate = GPIO_AF12_FMC; HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_4|GPIO_PIN_1|GPIO_PIN_5 - |GPIO_PIN_7|GPIO_PIN_13|GPIO_PIN_15|GPIO_PIN_14 - |GPIO_PIN_12|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_9 + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_4|GPIO_PIN_1|GPIO_PIN_5 + |GPIO_PIN_7|GPIO_PIN_13|GPIO_PIN_15|GPIO_PIN_14 + |GPIO_PIN_12|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_9 |GPIO_PIN_8; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -432,8 +432,8 @@ static void HAL_FMC_MspInit(void){ GPIO_InitStruct.Alternate = GPIO_AF12_FMC; HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_3 - |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_15|GPIO_PIN_14 + GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_3 + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_15|GPIO_PIN_14 |GPIO_PIN_13|GPIO_PIN_12; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -441,7 +441,7 @@ static void HAL_FMC_MspInit(void){ GPIO_InitStruct.Alternate = GPIO_AF12_FMC; HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_3|GPIO_PIN_5|GPIO_PIN_1 + GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_3|GPIO_PIN_5|GPIO_PIN_1 |GPIO_PIN_2|GPIO_PIN_0; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -476,8 +476,8 @@ static void HAL_FMC_MspDeInit(void){ FMC_DeInitialized = 1; /* Peripheral clock enable */ __HAL_RCC_FMC_CLK_DISABLE(); - - /** FMC GPIO Configuration + + /** FMC GPIO Configuration PE0 ------> FMC_NBL0 PE1 ------> FMC_NBL1 PD0 ------> FMC_D2 @@ -522,21 +522,21 @@ static void HAL_FMC_MspDeInit(void){ PF12 ------> FMC_A6 PE11 ------> FMC_D8 */ - HAL_GPIO_DeInit(GPIOE, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_3 - |GPIO_PIN_5|GPIO_PIN_10|GPIO_PIN_9|GPIO_PIN_15 - |GPIO_PIN_8|GPIO_PIN_14|GPIO_PIN_7|GPIO_PIN_13 + HAL_GPIO_DeInit(GPIOE, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_3 + |GPIO_PIN_5|GPIO_PIN_10|GPIO_PIN_9|GPIO_PIN_15 + |GPIO_PIN_8|GPIO_PIN_14|GPIO_PIN_7|GPIO_PIN_13 |GPIO_PIN_12|GPIO_PIN_11); - HAL_GPIO_DeInit(GPIOD, GPIO_PIN_0|GPIO_PIN_4|GPIO_PIN_1|GPIO_PIN_5 - |GPIO_PIN_7|GPIO_PIN_13|GPIO_PIN_15|GPIO_PIN_14 - |GPIO_PIN_12|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_9 + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_0|GPIO_PIN_4|GPIO_PIN_1|GPIO_PIN_5 + |GPIO_PIN_7|GPIO_PIN_13|GPIO_PIN_15|GPIO_PIN_14 + |GPIO_PIN_12|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_9 |GPIO_PIN_8); - HAL_GPIO_DeInit(GPIOF, GPIO_PIN_2|GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_3 - |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_15|GPIO_PIN_14 + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_2|GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_3 + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_15|GPIO_PIN_14 |GPIO_PIN_13|GPIO_PIN_12); - HAL_GPIO_DeInit(GPIOG, GPIO_PIN_4|GPIO_PIN_3|GPIO_PIN_5|GPIO_PIN_1 + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_4|GPIO_PIN_3|GPIO_PIN_5|GPIO_PIN_1 |GPIO_PIN_2|GPIO_PIN_0); /* USER CODE BEGIN FMC_MspDeInit 1 */ diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/CubeMX_Config/CM4/Src/stm32mp1xx_hal_msp.c b/bsp/stm32/stm32mp157a-st-discovery/board/CubeMX_Config/CM4/Src/stm32mp1xx_hal_msp.c index 5ca08fbbd0..940be95f73 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/CubeMX_Config/CM4/Src/stm32mp1xx_hal_msp.c +++ b/bsp/stm32/stm32mp157a-st-discovery/board/CubeMX_Config/CM4/Src/stm32mp1xx_hal_msp.c @@ -2,7 +2,7 @@ /** ****************************************************************************** * File Name : stm32mp1xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** * @attention @@ -33,7 +33,7 @@ DMA_HandleTypeDef hdma_cryp_out = {0}; /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -59,7 +59,7 @@ DMA_HandleTypeDef hdma_cryp_out = {0}; /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ - + /** * Initializes the Global MSP. */ @@ -74,7 +74,7 @@ void HAL_MspInit(void) /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ - if (IS_ENGINEERING_BOOT_MODE()) + if (IS_ENGINEERING_BOOT_MODE()) { __HAL_RCC_SYSRAM_CLK_ENABLE(); } @@ -102,7 +102,7 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) /* USER CODE END ADC2_MspInit 0 */ if(IS_ENGINEERING_BOOT_MODE()) { - /** Initializes the peripherals clock + /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PER; @@ -115,10 +115,10 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) /* Peripheral clock enable */ __HAL_RCC_ADC12_CLK_ENABLE(); - + __HAL_RCC_GPIOF_CLK_ENABLE(); - /**ADC2 GPIO Configuration - PF14 ------> ADC2_INP6 + /**ADC2 GPIO Configuration + PF14 ------> ADC2_INP6 */ GPIO_InitStruct.Pin = GPIO_PIN_14; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; @@ -145,9 +145,9 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) /* USER CODE END ADC2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_ADC12_CLK_DISABLE(); - - /**ADC2 GPIO Configuration - PF14 ------> ADC2_INP6 + + /**ADC2 GPIO Configuration + PF14 ------> ADC2_INP6 */ HAL_GPIO_DeInit(GPIOF, GPIO_PIN_14); @@ -174,10 +174,10 @@ void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac) /* USER CODE END DAC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_DAC12_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**DAC1 GPIO Configuration - PA4 ------> DAC1_OUT1 + /**DAC1 GPIO Configuration + PA4 ------> DAC1_OUT1 */ GPIO_InitStruct.Pin = GPIO_PIN_4; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; @@ -205,9 +205,9 @@ void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac) /* USER CODE END DAC1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_DAC12_CLK_DISABLE(); - - /**DAC1 GPIO Configuration - PA4 ------> DAC1_OUT1 + + /**DAC1 GPIO Configuration + PA4 ------> DAC1_OUT1 */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_4); @@ -287,7 +287,7 @@ void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef* hlptim) /* USER CODE END LPTIM1_MspInit 0 */ if(IS_ENGINEERING_BOOT_MODE()) { - /** Initializes the peripherals clock + /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPTIM1; PeriphClkInit.Lptim1ClockSelection = RCC_LPTIM1CLKSOURCE_LSI; @@ -315,7 +315,7 @@ void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef* hlptim) if(IS_ENGINEERING_BOOT_MODE()) { - /** Initializes the peripherals clock + /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPTIM23; PeriphClkInit.Lptim23ClockSelection = RCC_LPTIM23CLKSOURCE_PCLK3; @@ -343,7 +343,7 @@ void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef* hlptim) if(IS_ENGINEERING_BOOT_MODE()) { - /** Initializes the peripherals clock + /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPTIM23; PeriphClkInit.Lptim23ClockSelection = RCC_LPTIM23CLKSOURCE_PCLK3; @@ -371,7 +371,7 @@ void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef* hlptim) if(IS_ENGINEERING_BOOT_MODE()) { - /** Initializes the peripherals clock + /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPTIM45; PeriphClkInit.Lptim45ClockSelection = RCC_LPTIM45CLKSOURCE_PCLK3; @@ -399,7 +399,7 @@ void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef* hlptim) if(IS_ENGINEERING_BOOT_MODE()) { - /** Initializes the peripherals clock + /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPTIM45; PeriphClkInit.Lptim45ClockSelection = RCC_LPTIM45CLKSOURCE_PCLK3; @@ -520,7 +520,7 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI5_MspInit 0 */ if(IS_ENGINEERING_BOOT_MODE()) { - /** Initializes the peripherals clock + /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SPI45; PeriphClkInit.Spi45ClockSelection = RCC_SPI45CLKSOURCE_PCLK2; @@ -533,12 +533,12 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* Peripheral clock enable */ __HAL_RCC_SPI5_CLK_ENABLE(); - + __HAL_RCC_GPIOF_CLK_ENABLE(); - /**SPI5 GPIO Configuration + /**SPI5 GPIO Configuration PF9 ------> SPI5_MOSI PF8 ------> SPI5_MISO - PF7 ------> SPI5_SCK + PF7 ------> SPI5_SCK */ GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_8|GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -569,10 +569,10 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI5_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI5_CLK_DISABLE(); - - /**SPI5 GPIO Configuration + + /**SPI5 GPIO Configuration PF9 ------> SPI5_MOSI - PF7 ------> SPI5_SCK + PF7 ------> SPI5_SCK */ HAL_GPIO_DeInit(GPIOF, GPIO_PIN_9|GPIO_PIN_7); @@ -646,10 +646,10 @@ void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) /* USER CODE BEGIN TIM4_MspPostInit 0 */ /* USER CODE END TIM4_MspPostInit 0 */ - + __HAL_RCC_GPIOD_CLK_ENABLE(); - /**TIM4 GPIO Configuration - PD13 ------> TIM4_CH2 + /**TIM4 GPIO Configuration + PD13 ------> TIM4_CH2 */ GPIO_InitStruct.Pin = GPIO_PIN_13; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -736,7 +736,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END UART4_MspInit 0 */ if(IS_ENGINEERING_BOOT_MODE()) { - /** Initializes the peripherals clock + /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_UART24; PeriphClkInit.Uart24ClockSelection = RCC_UART24CLKSOURCE_HSI; @@ -749,23 +749,23 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* Peripheral clock enable */ __HAL_RCC_UART4_CLK_ENABLE(); - + __HAL_RCC_GPIOG_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); - /**UART4 GPIO Configuration + /**UART4 GPIO Configuration PG11 ------> UART4_TX - PB2 ------> UART4_RX + PB2 ------> UART4_RX */ GPIO_InitStruct.Pin = STLINK_RX_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Alternate = GPIO_AF6_UART4; HAL_GPIO_Init(STLINK_RX_GPIO_Port, &GPIO_InitStruct); GPIO_InitStruct.Pin = STLINK_TX_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Alternate = GPIO_AF8_UART4; HAL_GPIO_Init(STLINK_TX_GPIO_Port, &GPIO_InitStruct); @@ -781,7 +781,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) if(IS_ENGINEERING_BOOT_MODE()) { - /** Initializes the peripherals clock + /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_UART35; PeriphClkInit.Uart35ClockSelection = RCC_UART35CLKSOURCE_PCLK1; @@ -794,22 +794,22 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* Peripheral clock enable */ __HAL_RCC_USART3_CLK_ENABLE(); - + __HAL_RCC_GPIOB_CLK_ENABLE(); - /**USART3 GPIO Configuration + /**USART3 GPIO Configuration PB10 ------> USART3_TX - PB12 ------> USART3_RX + PB12 ------> USART3_RX */ GPIO_InitStruct.Pin = GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Alternate = GPIO_AF7_USART3; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); GPIO_InitStruct.Pin = GPIO_PIN_12; GPIO_InitStruct.Mode = GPIO_MODE_AF; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Alternate = GPIO_AF8_USART3; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); @@ -835,10 +835,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END UART4_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_UART4_CLK_DISABLE(); - - /**UART4 GPIO Configuration + + /**UART4 GPIO Configuration PG11 ------> UART4_TX - PB2 ------> UART4_RX + PB2 ------> UART4_RX */ HAL_GPIO_DeInit(STLINK_RX_GPIO_Port, STLINK_RX_Pin); @@ -855,10 +855,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART3_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART3_CLK_DISABLE(); - - /**USART3 GPIO Configuration + + /**USART3 GPIO Configuration PB10 ------> USART3_TX - PB12 ------> USART3_RX + PB12 ------> USART3_RX */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_10|GPIO_PIN_12); @@ -904,12 +904,12 @@ void HAL_I2C_MspInit(I2C_HandleTypeDef *hI2c) { GPIO_InitTypeDef GPIO_InitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - + if(hI2c->Instance == I2C4) { if(IS_ENGINEERING_BOOT_MODE()) { - /*** Configure the I2C peripheral clock ***/ + /*** Configure the I2C peripheral clock ***/ PeriphClkInit.I2c46ClockSelection = RCC_I2C46CLKSOURCE_HSI; PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C46; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) @@ -931,11 +931,11 @@ void HAL_I2C_MspInit(I2C_HandleTypeDef *hI2c) /* Enable I2C clock */ __HAL_RCC_I2C4_CLK_ENABLE(); - /* Force the I2C peripheral clock reset */ + /* Force the I2C peripheral clock reset */ __HAL_RCC_I2C4_FORCE_RESET(); - /* Release the I2C peripheral clock reset */ + /* Release the I2C peripheral clock reset */ __HAL_RCC_I2C4_RELEASE_RESET(); - + HAL_NVIC_SetPriority(I2C4_ER_IRQn, 0, 1); HAL_NVIC_EnableIRQ(I2C4_ER_IRQn); HAL_NVIC_SetPriority(I2C4_EV_IRQn, 0, 2); @@ -953,13 +953,13 @@ void HAL_SD_MspInit(SD_HandleTypeDef* hsd) { GPIO_InitTypeDef GPIO_InitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - + if(hsd->Instance==SDMMC1) { /* USER CODE BEGIN SDMMC1_MspInit 0 */ if (IS_ENGINEERING_BOOT_MODE()) { - /** Initializes the peripherals clock + /** Initializes the peripherals clock */ PeriphClkInit.Sdmmc12ClockSelection = RCC_SDMMC12CLKSOURCE_PLL4; PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SDMMC12; @@ -971,18 +971,18 @@ void HAL_SD_MspInit(SD_HandleTypeDef* hsd) /* USER CODE END SDMMC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SDMMC1_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); - /**SDMMC1 GPIO Configuration + /**SDMMC1 GPIO Configuration PC8 ------> SDMMC1_D0 PC9 ------> SDMMC1_D1 PC10 ------> SDMMC1_D2 PC11 ------> SDMMC1_D3 PC12 ------> SDMMC1_CK - PD2 ------> SDMMC1_CMD + PD2 ------> SDMMC1_CMD */ - GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 |GPIO_PIN_12; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -995,7 +995,7 @@ void HAL_SD_MspInit(SD_HandleTypeDef* hsd) __HAL_RCC_SDMMC1_FORCE_RESET(); __HAL_RCC_SDMMC1_RELEASE_RESET(); - + /* SDMMC1 interrupt Init */ HAL_NVIC_SetPriority(SDMMC1_IRQn, 2, 0); HAL_NVIC_EnableIRQ(SDMMC1_IRQn); @@ -1008,7 +1008,7 @@ void HAL_SD_MspInit(SD_HandleTypeDef* hsd) /* USER CODE BEGIN SDMMC2_MspInit 0 */ if (IS_ENGINEERING_BOOT_MODE()) { - /** Initializes the peripherals clock + /** Initializes the peripherals clock */ PeriphClkInit.Sdmmc12ClockSelection = RCC_SDMMC12CLKSOURCE_PLL4; PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SDMMC12; @@ -1020,17 +1020,17 @@ void HAL_SD_MspInit(SD_HandleTypeDef* hsd) /* USER CODE END SDMMC2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SDMMC2_CLK_ENABLE(); - + __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOE_CLK_ENABLE(); __HAL_RCC_GPIOG_CLK_ENABLE(); - /**SDMMC2 GPIO Configuration + /**SDMMC2 GPIO Configuration PB14 ------> SDMMC2_D0 PB15 ------> SDMMC2_D1 PB3 ------> SDMMC2_D2 PB4 ------> SDMMC2_D3 PE3 ------> SDMMC2_CK - PG6 ------> SDMMC2_CMD + PG6 ------> SDMMC2_CMD */ GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_14|GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -1055,7 +1055,7 @@ void HAL_SD_MspInit(SD_HandleTypeDef* hsd) __HAL_RCC_SDMMC2_FORCE_RESET(); __HAL_RCC_SDMMC2_RELEASE_RESET(); - + /* SDMMC2 interrupt Init */ HAL_NVIC_SetPriority(SDMMC2_IRQn, 2, 0); HAL_NVIC_EnableIRQ(SDMMC2_IRQn); @@ -1080,16 +1080,16 @@ void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) /* USER CODE END SDMMC1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SDMMC1_CLK_DISABLE(); - - /**SDMMC1 GPIO Configuration + + /**SDMMC1 GPIO Configuration PC8 ------> SDMMC1_D0 PC9 ------> SDMMC1_D1 PC10 ------> SDMMC1_D2 PC11 ------> SDMMC1_D3 PC12 ------> SDMMC1_CK - PD2 ------> SDMMC1_CMD + PD2 ------> SDMMC1_CMD */ - HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 |GPIO_PIN_12); HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); @@ -1111,7 +1111,7 @@ void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hI2c) { GPIO_InitTypeDef GPIO_InitStruct = {0}; - + if(hI2c->Instance == I2C4) { /* Configure I2C Tx, Rx as alternate function */ @@ -1187,7 +1187,7 @@ void HAL_RNG_MspInit(RNG_HandleTypeDef* hrng) /* USER CODE END RNG2_MspInit 0 */ if(IS_ENGINEERING_BOOT_MODE()) { - /** Initializes the peripherals clock + /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RNG2; PeriphClkInit.Rng2ClockSelection = RCC_RNG2CLKSOURCE_CSI; @@ -1243,7 +1243,7 @@ void HAL_HASH_MspInit(HASH_HandleTypeDef* hhash) __HAL_RCC_HASH2_CLK_ENABLE(); /* USER CODE BEGIN HASH2_MspInit 1 */ __HAL_RCC_DMAMUX_CLK_ENABLE(); - + /* Peripheral DMA init*/ hdma_hash_in.Instance = DMA2_Stream7; hdma_hash_in.Init.Request = DMA_REQUEST_HASH2_IN; @@ -1386,7 +1386,7 @@ void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) /* USER CODE BEGIN SDMMC1_MspInit 0 */ if (IS_ENGINEERING_BOOT_MODE()) { - /** Initializes the peripherals clock + /** Initializes the peripherals clock */ PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC; diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/CM4/Src/stm32mp1xx_hal_msp.c b/bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/CM4/Src/stm32mp1xx_hal_msp.c index 20f6aa2d63..6e8d4b0ca2 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/CM4/Src/stm32mp1xx_hal_msp.c +++ b/bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/CM4/Src/stm32mp1xx_hal_msp.c @@ -2,7 +2,7 @@ /** ****************************************************************************** * File Name : stm32mp1xx_hal_msp.c - * Description : This file provides code for the MSP Initialization + * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** * @attention @@ -39,7 +39,7 @@ DMA_HandleTypeDef hdma_dfsdm1_flt1 = {0}; /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -65,7 +65,7 @@ DMA_HandleTypeDef hdma_dfsdm1_flt1 = {0}; /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ - + void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); /** * Initializes the Global MSP. @@ -85,7 +85,7 @@ void HAL_MspInit(void) { __HAL_RCC_SYSRAM_CLK_ENABLE(); } - + HAL_NVIC_SetPriority(RCC_WAKEUP_IRQn, 0, 0); HAL_NVIC_EnableIRQ(RCC_WAKEUP_IRQn); __HAL_RCC_ENABLE_IT(RCC_IT_WKUP); @@ -109,7 +109,7 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) /* USER CODE END ADC2_MspInit 0 */ if(IS_ENGINEERING_BOOT_MODE()) { - /** Initializes the peripherals clock + /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PER; @@ -122,10 +122,10 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) /* Peripheral clock enable */ __HAL_RCC_ADC12_CLK_ENABLE(); - + __HAL_RCC_GPIOF_CLK_ENABLE(); - /**ADC2 GPIO Configuration - PF14 ------> ADC2_INP6 + /**ADC2 GPIO Configuration + PF14 ------> ADC2_INP6 */ GPIO_InitStruct.Pin = GPIO_PIN_14; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; @@ -152,9 +152,9 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) /* USER CODE END ADC2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_ADC12_CLK_DISABLE(); - - /**ADC2 GPIO Configuration - PF14 ------> ADC2_INP6 + + /**ADC2 GPIO Configuration + PF14 ------> ADC2_INP6 */ HAL_GPIO_DeInit(GPIOF, GPIO_PIN_14); @@ -181,10 +181,10 @@ void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac) /* USER CODE END DAC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_DAC12_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**DAC1 GPIO Configuration - PA4 ------> DAC1_OUT1 + /**DAC1 GPIO Configuration + PA4 ------> DAC1_OUT1 */ GPIO_InitStruct.Pin = GPIO_PIN_4; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; @@ -212,9 +212,9 @@ void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac) /* USER CODE END DAC1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_DAC12_CLK_DISABLE(); - - /**DAC1 GPIO Configuration - PA4 ------> DAC1_OUT1 + + /**DAC1 GPIO Configuration + PA4 ------> DAC1_OUT1 */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_4); @@ -294,7 +294,7 @@ void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef* hlptim) /* USER CODE END LPTIM1_MspInit 0 */ if(IS_ENGINEERING_BOOT_MODE()) { - /** Initializes the peripherals clock + /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPTIM1; PeriphClkInit.Lptim1ClockSelection = RCC_LPTIM1CLKSOURCE_LSE; @@ -322,7 +322,7 @@ void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef* hlptim) if(IS_ENGINEERING_BOOT_MODE()) { - /** Initializes the peripherals clock + /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPTIM23; PeriphClkInit.Lptim23ClockSelection = RCC_LPTIM23CLKSOURCE_PCLK3; @@ -350,7 +350,7 @@ void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef* hlptim) if(IS_ENGINEERING_BOOT_MODE()) { - /** Initializes the peripherals clock + /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPTIM23; PeriphClkInit.Lptim23ClockSelection = RCC_LPTIM23CLKSOURCE_PCLK3; @@ -378,7 +378,7 @@ void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef* hlptim) if(IS_ENGINEERING_BOOT_MODE()) { - /** Initializes the peripherals clock + /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPTIM45; PeriphClkInit.Lptim45ClockSelection = RCC_LPTIM45CLKSOURCE_PCLK3; @@ -406,7 +406,7 @@ void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef* hlptim) if(IS_ENGINEERING_BOOT_MODE()) { - /** Initializes the peripherals clock + /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPTIM45; PeriphClkInit.Lptim45ClockSelection = RCC_LPTIM45CLKSOURCE_PCLK3; @@ -527,7 +527,7 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI1_MspInit 0 */ if(IS_ENGINEERING_BOOT_MODE()) { - /** Initializes the peripherals clock + /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SPI1; PeriphClkInit.Spi1ClockSelection = RCC_SPI1CLKSOURCE_PLL4; @@ -540,9 +540,9 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* Peripheral clock enable */ __HAL_RCC_SPI1_CLK_ENABLE(); - + __HAL_RCC_GPIOZ_CLK_ENABLE(); - /**SPI1 GPIO Configuration + /**SPI1 GPIO Configuration PZ2 ------> SPI1_MOSI PZ1 ------> SPI1_MISO PZ0 ------> SPI1_SCK @@ -576,10 +576,10 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI5_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI5_CLK_DISABLE(); - - /**SPI5 GPIO Configuration + + /**SPI5 GPIO Configuration PF9 ------> SPI5_MOSI - PF7 ------> SPI5_SCK + PF7 ------> SPI5_SCK */ HAL_GPIO_DeInit(GPIOF, GPIO_PIN_9|GPIO_PIN_7); @@ -653,10 +653,10 @@ void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) /* USER CODE BEGIN TIM4_MspPostInit 0 */ /* USER CODE END TIM4_MspPostInit 0 */ - + __HAL_RCC_GPIOD_CLK_ENABLE(); - /**TIM4 GPIO Configuration - PD13 ------> TIM4_CH2 + /**TIM4 GPIO Configuration + PD13 ------> TIM4_CH2 */ GPIO_InitStruct.Pin = GPIO_PIN_13; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -743,7 +743,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END UART4_MspInit 0 */ if(IS_ENGINEERING_BOOT_MODE()) { - /** Initializes the peripherals clock + /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_UART24; PeriphClkInit.Uart24ClockSelection = RCC_UART24CLKSOURCE_HSI; @@ -756,23 +756,23 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* Peripheral clock enable */ __HAL_RCC_UART4_CLK_ENABLE(); - + __HAL_RCC_GPIOG_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); - /**UART4 GPIO Configuration + /**UART4 GPIO Configuration PG11 ------> UART4_TX - PB2 ------> UART4_RX + PB2 ------> UART4_RX */ GPIO_InitStruct.Pin = STLINK_RX_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Alternate = GPIO_AF6_UART4; HAL_GPIO_Init(STLINK_RX_GPIO_Port, &GPIO_InitStruct); GPIO_InitStruct.Pin = STLINK_TX_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Alternate = GPIO_AF8_UART4; HAL_GPIO_Init(STLINK_TX_GPIO_Port, &GPIO_InitStruct); @@ -788,7 +788,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) if(IS_ENGINEERING_BOOT_MODE()) { - /** Initializes the peripherals clock + /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_UART35; PeriphClkInit.Uart35ClockSelection = RCC_UART35CLKSOURCE_PCLK1; @@ -801,22 +801,22 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* Peripheral clock enable */ __HAL_RCC_USART3_CLK_ENABLE(); - + __HAL_RCC_GPIOB_CLK_ENABLE(); - /**USART3 GPIO Configuration + /**USART3 GPIO Configuration PB10 ------> USART3_TX - PB12 ------> USART3_RX + PB12 ------> USART3_RX */ GPIO_InitStruct.Pin = GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Alternate = GPIO_AF7_USART3; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); GPIO_InitStruct.Pin = GPIO_PIN_12; GPIO_InitStruct.Mode = GPIO_MODE_AF; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Alternate = GPIO_AF8_USART3; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); @@ -842,10 +842,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END UART4_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_UART4_CLK_DISABLE(); - - /**UART4 GPIO Configuration + + /**UART4 GPIO Configuration PG11 ------> UART4_TX - PB2 ------> UART4_RX + PB2 ------> UART4_RX */ HAL_GPIO_DeInit(STLINK_RX_GPIO_Port, STLINK_RX_Pin); @@ -862,10 +862,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART3_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART3_CLK_DISABLE(); - - /**USART3 GPIO Configuration + + /**USART3 GPIO Configuration PB10 ------> USART3_TX - PB12 ------> USART3_RX + PB12 ------> USART3_RX */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_10|GPIO_PIN_12); @@ -911,12 +911,12 @@ void HAL_I2C_MspInit(I2C_HandleTypeDef *hI2c) { GPIO_InitTypeDef GPIO_InitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - + if(hI2c->Instance == I2C4) { if(IS_ENGINEERING_BOOT_MODE()) { - /*** Configure the I2C peripheral clock ***/ + /*** Configure the I2C peripheral clock ***/ PeriphClkInit.I2c46ClockSelection = RCC_I2C46CLKSOURCE_HSI; PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C46; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) @@ -938,11 +938,11 @@ void HAL_I2C_MspInit(I2C_HandleTypeDef *hI2c) /* Enable I2C clock */ __HAL_RCC_I2C4_CLK_ENABLE(); - /* Force the I2C peripheral clock reset */ + /* Force the I2C peripheral clock reset */ __HAL_RCC_I2C4_FORCE_RESET(); - /* Release the I2C peripheral clock reset */ + /* Release the I2C peripheral clock reset */ __HAL_RCC_I2C4_RELEASE_RESET(); - + HAL_NVIC_SetPriority(I2C4_ER_IRQn, 0, 1); HAL_NVIC_EnableIRQ(I2C4_ER_IRQn); HAL_NVIC_SetPriority(I2C4_EV_IRQn, 0, 2); @@ -958,7 +958,7 @@ void HAL_I2C_MspInit(I2C_HandleTypeDef *hI2c) void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hI2c) { GPIO_InitTypeDef GPIO_InitStruct = {0}; - + if(hI2c->Instance == I2C4) { /* Configure I2C Tx, Rx as alternate function */ @@ -990,7 +990,7 @@ void HAL_SD_MspInit(SD_HandleTypeDef* hsd) /* USER CODE BEGIN SDMMC1_MspInit 0 */ if (IS_ENGINEERING_BOOT_MODE()) { - /** Initializes the peripherals clock + /** Initializes the peripherals clock */ PeriphClkInit.Sdmmc12ClockSelection = RCC_SDMMC12CLKSOURCE_PLL4; PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SDMMC12; @@ -1018,7 +1018,7 @@ void HAL_SD_MspInit(SD_HandleTypeDef* hsd) PC12 ------> SDMMC1_CK PD2 ------> SDMMC1_CMD PE4 ------> SDMMC1_CKIN - PF2 ------> SDMMC1_D0DIR + PF2 ------> SDMMC1_D0DIR */ GPIO_InitStruct.Pin = GPIO_PIN_9; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -1033,11 +1033,11 @@ void HAL_SD_MspInit(SD_HandleTypeDef* hsd) GPIO_InitStruct.Pin = GPIO_PIN_7; GPIO_InitStruct.Alternate = GPIO_AF8_SDIO1; HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - + GPIO_InitStruct.Pin = GPIO_PIN_4; HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 |GPIO_PIN_12; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Alternate = GPIO_AF12_SDIO1; @@ -1056,13 +1056,13 @@ void HAL_SD_MspInit(SD_HandleTypeDef* hsd) /* USER CODE END SDMMC1_MspInit 1 */ } - + if(hsd->Instance==SDMMC2) { /* USER CODE BEGIN SDMMC2_MspInit 0 */ if (IS_ENGINEERING_BOOT_MODE()) { - /** Initializes the peripherals clock + /** Initializes the peripherals clock */ PeriphClkInit.Sdmmc12ClockSelection = RCC_SDMMC12CLKSOURCE_PLL4; PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SDMMC12; @@ -1088,7 +1088,7 @@ void HAL_SD_MspInit(SD_HandleTypeDef* hsd) PA8 ------> SDMMC2_D4 PA9 ------> SDMMC2_D5 PE5 ------> SDMMC2_D6 - PD3 ------> SDMMC2_D7 + PD3 ------> SDMMC2_D7 PE3 ------> SDMMC2_CK PG6 ------> SDMMC2_CMD */ @@ -1104,10 +1104,10 @@ void HAL_SD_MspInit(SD_HandleTypeDef* hsd) GPIO_InitStruct.Pin = GPIO_PIN_3; HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); - + GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_5; HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); - + GPIO_InitStruct.Pin = GPIO_PIN_9; GPIO_InitStruct.Alternate = GPIO_AF10_SDIO2; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); @@ -1143,8 +1143,8 @@ void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) /* USER CODE END SDMMC1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SDMMC1_CLK_DISABLE(); - - /**SDMMC1 GPIO Configuration + + /**SDMMC1 GPIO Configuration PB9 ------> SDMMC1_CDIR PC7 ------> SDMMC1_D123DIR PC8 ------> SDMMC1_D0 @@ -1154,17 +1154,17 @@ void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) PC12 ------> SDMMC1_CK PD2 ------> SDMMC1_CMD PE4 ------> SDMMC1_CKIN - PF2 ------> SDMMC1_D0DIR + PF2 ------> SDMMC1_D0DIR */ - HAL_GPIO_DeInit(GPIOC, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 |GPIO_PIN_12); HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); HAL_GPIO_DeInit(GPIOB, GPIO_PIN_9); - + HAL_GPIO_DeInit(GPIOE, GPIO_PIN_4); - + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_2); /* SDMMC1 interrupt DeInit */ HAL_NVIC_DisableIRQ(SDMMC1_IRQn); @@ -1172,7 +1172,7 @@ void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) /* USER CODE END SDMMC1_MspDeInit 1 */ } - + if(hsd->Instance==SDMMC2) { /* USER CODE BEGIN SDMMC2_MspDeInit 0 */ @@ -1180,8 +1180,8 @@ void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) /* USER CODE END SDMMC2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SDMMC2_CLK_DISABLE(); - - /**SDMMC2 GPIO Configuration + + /**SDMMC2 GPIO Configuration PB14 ------> SDMMC2_D0 PB15 ------> SDMMC2_D1 PB3 ------> SDMMC2_D2 @@ -1189,7 +1189,7 @@ void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) PA8 ------> SDMMC2_D4 PA9 ------> SDMMC2_D5 PE5 ------> SDMMC2_D6 - PD3 ------> SDMMC2_D7 + PD3 ------> SDMMC2_D7 PE3 ------> SDMMC2_CK PG6 ------> SDMMC2_CMD */ @@ -1198,9 +1198,9 @@ void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) HAL_GPIO_DeInit(GPIOA, GPIO_PIN_8|GPIO_PIN_9); HAL_GPIO_DeInit(GPIOD, GPIO_PIN_3); - + HAL_GPIO_DeInit(GPIOE, GPIO_PIN_3|GPIO_PIN_5); - + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_6); /* SDMMC2 interrupt DeInit */ HAL_NVIC_DisableIRQ(SDMMC2_IRQn); @@ -1221,7 +1221,7 @@ void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai) /* Peripheral clock enable */ if(IS_ENGINEERING_BOOT_MODE()) { - /** Initializes the peripherals clock + /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SAI2; PeriphClkInit.Sai2ClockSelection = RCC_SAI2CLKSOURCE_PLL3_Q; @@ -1236,7 +1236,7 @@ void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai) __HAL_RCC_GPIOF_CLK_ENABLE(); __HAL_RCC_SAI2_CLK_ENABLE(); - /**SAI2_A_Block_A GPIO Configuration + /**SAI2_A_Block_A GPIO Configuration PE0 ------> SAI2_MCLK_A PI7 ------> SAI2_FS_A PI5 ------> SAI2_SCK_A @@ -1269,7 +1269,7 @@ void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai) hdma_sai2_a.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; hdma_sai2_a.Init.MemBurst = DMA_MBURST_SINGLE; hdma_sai2_a.Init.PeriphBurst = DMA_PBURST_SINGLE; - + HAL_DMA_DeInit(&hdma_sai2_a); if (HAL_DMA_Init(&hdma_sai2_a) != HAL_OK) { @@ -1277,17 +1277,17 @@ void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai) } __HAL_LINKDMA(hsai,hdmatx,hdma_sai2_a); __HAL_DMA_ENABLE(&hdma_sai2_a); - + HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 0x02, 0); HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn); } - + if (hsai->Instance==SAI2_Block_B) { /* Peripheral clock enable */ if (IS_ENGINEERING_BOOT_MODE()) { - /** Initializes the peripherals clock + /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SAI2; PeriphClkInit.Sai2ClockSelection = RCC_SAI2CLKSOURCE_PLL3_Q; @@ -1299,8 +1299,8 @@ void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai) } __HAL_RCC_GPIOF_CLK_ENABLE(); __HAL_RCC_SAI2_CLK_ENABLE(); - - /**SAI2_B_Block_B GPIO Configuration + + /**SAI2_B_Block_B GPIO Configuration PE12 ------> SAI2_MCLK_B PE13 ------> SAI2_FS_B PE14 ------> SAI2_SCK_B @@ -1313,13 +1313,13 @@ void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai) GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF10_SAI2; HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); - + GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14; HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); - + __HAL_RCC_DMAMUX_CLK_ENABLE(); __HAL_RCC_DMA1_CLK_ENABLE(); - + /* Peripheral DMA init*/ hdma_sai2_b.Instance = DMA1_Stream1; hdma_sai2_b.Init.Request = DMA_REQUEST_SAI2_B; @@ -1334,7 +1334,7 @@ void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai) hdma_sai2_b.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; hdma_sai2_b.Init.MemBurst = DMA_MBURST_SINGLE; hdma_sai2_b.Init.PeriphBurst = DMA_PBURST_SINGLE; - + HAL_DMA_DeInit(&hdma_sai2_b); if (HAL_DMA_Init(&hdma_sai2_b) != HAL_OK) { @@ -1343,7 +1343,7 @@ void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai) __HAL_LINKDMA(hsai,hdmarx,hdma_sai2_b); __HAL_DMA_ENABLE(&hdma_sai2_b); HAL_NVIC_SetPriority(DMA1_Stream1_IRQn, 0x02, 0); - HAL_NVIC_EnableIRQ(DMA1_Stream1_IRQn); + HAL_NVIC_EnableIRQ(DMA1_Stream1_IRQn); } /* SAI4 */ if(hsai->Instance==SAI4_Block_A) @@ -1351,7 +1351,7 @@ void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai) /* Peripheral clock enable */ if(IS_ENGINEERING_BOOT_MODE()) { - /** Initializes the peripherals clock + /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SAI4; PeriphClkInit.Sai4ClockSelection = RCC_SAI4CLKSOURCE_PLL3_Q; @@ -1363,9 +1363,9 @@ void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai) } __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_SAI4_CLK_ENABLE(); - - /**SAI4_A_Block_A GPIO Configuration - PB5 ------> SAI4_SD_A + + /**SAI4_A_Block_A GPIO Configuration + PB5 ------> SAI4_SD_A */ GPIO_InitStruct.Pin = GPIO_PIN_5; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -1377,7 +1377,7 @@ void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai) /* Peripheral DMA init*/ __HAL_RCC_DMAMUX_CLK_ENABLE(); __HAL_RCC_DMA1_CLK_ENABLE(); - + hdma_sai4_a.Instance = DMA1_Stream2; hdma_sai4_a.Init.Request = DMA_REQUEST_SAI4_A; hdma_sai4_a.Init.Direction = DMA_MEMORY_TO_PERIPH; @@ -1391,7 +1391,7 @@ void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai) hdma_sai4_a.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; hdma_sai4_a.Init.MemBurst = DMA_MBURST_SINGLE; hdma_sai4_a.Init.PeriphBurst = DMA_PBURST_SINGLE; - + HAL_DMA_DeInit(&hdma_sai4_a); if (HAL_DMA_Init(&hdma_sai4_a) != HAL_OK) { @@ -1400,7 +1400,7 @@ void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai) __HAL_LINKDMA(hsai,hdmatx,hdma_sai4_a); __HAL_DMA_ENABLE(&hdma_sai4_a); HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 0x02, 0); - HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn); + HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn); } } @@ -1420,27 +1420,27 @@ void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi) /* USER CODE END DCMI_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_DCMI_CLK_ENABLE(); - + __HAL_RCC_GPIOH_CLK_ENABLE(); __HAL_RCC_GPIOE_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOI_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE(); - + /**DCMI GPIO Configuration - PH9 ------> DCMI_D0 + PH9 ------> DCMI_D0 PH10 ------> DCMI_D1 PH11 ------> DCMI_D2 PH12 ------> DCMI_D3 PH14 ------> DCMI_D4 - PI4 ------> DCMI_D5 - PB8 ------> DCMI_D6 - PE6 ------> DCMI_D7 + PI4 ------> DCMI_D5 + PB8 ------> DCMI_D6 + PE6 ------> DCMI_D7 PH8 ------> DCMI_HSYNC PB7 ------> DCMI_VSYNC PA6 ------> DCMI_PIXCLK */ - GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_14|GPIO_PIN_8 + GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_14|GPIO_PIN_8 |GPIO_PIN_9|GPIO_PIN_12; GPIO_InitStruct.Mode = GPIO_MODE_AF; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -1470,10 +1470,10 @@ void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi) GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Alternate = GPIO_AF13_DCMI; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - HAL_NVIC_SetPriority(DCMI_IRQn, 0x03, 0x00); - HAL_NVIC_EnableIRQ(DCMI_IRQn); - + + HAL_NVIC_SetPriority(DCMI_IRQn, 0x03, 0x00); + HAL_NVIC_EnableIRQ(DCMI_IRQn); + /* USER CODE BEGIN DCMI_MspInit 1 */ /* USER CODE END DCMI_MspInit 1 */ } @@ -1495,8 +1495,8 @@ void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi) /* USER CODE END DCMI_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_DCMI_CLK_DISABLE(); - - /**DCMI GPIO Configuration + + /**DCMI GPIO Configuration PH10 ------> DCMI_D1 PH11 ------> DCMI_D2 PH14 ------> DCMI_D4 @@ -1507,9 +1507,9 @@ void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi) PB7 ------> DCMI_VSYNC PI4 ------> DCMI_D5 PA6 ------> DCMI_PIXCLK - PB8 ------> DCMI_D6 + PB8 ------> DCMI_D6 */ - HAL_GPIO_DeInit(GPIOH, GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_14|GPIO_PIN_8 + HAL_GPIO_DeInit(GPIOH, GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_14|GPIO_PIN_8 |GPIO_PIN_9|GPIO_PIN_12); HAL_GPIO_DeInit(GPIOE, GPIO_PIN_6); @@ -1544,7 +1544,7 @@ void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef* hfdcan) /* USER CODE END FDCAN1_MspInit 0 */ if(IS_ENGINEERING_BOOT_MODE()) { - /** Initializes the peripherals clock + /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_FDCAN; PeriphClkInit.FdcanClockSelection = RCC_FDCANCLKSOURCE_HSE; @@ -1557,12 +1557,12 @@ void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef* hfdcan) /* Peripheral clock enable */ __HAL_RCC_FDCAN_CLK_ENABLE(); - + __HAL_RCC_GPIOH_CLK_ENABLE(); __HAL_RCC_GPIOI_CLK_ENABLE(); - /**FDCAN1 GPIO Configuration + /**FDCAN1 GPIO Configuration PH13 ------> FDCAN1_TX - PI9 ------> FDCAN1_RX + PI9 ------> FDCAN1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_13; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -1605,10 +1605,10 @@ void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef* hfdcan) /* USER CODE END FDCAN1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_FDCAN_CLK_DISABLE(); - - /**FDCAN1 GPIO Configuration + + /**FDCAN1 GPIO Configuration PH13 ------> FDCAN1_TX - PI9 ------> FDCAN1_RX + PI9 ------> FDCAN1_RX */ HAL_GPIO_DeInit(GPIOH, GPIO_PIN_13); @@ -1655,7 +1655,7 @@ void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef* hspdifrx) __HAL_RCC_DMAMUX_CLK_ENABLE(); __HAL_RCC_DMA1_CLK_ENABLE(); - + hdma_spdifrx_rx.Instance = DMA1_Stream7; hdma_spdifrx_rx.Init.Request = DMA_REQUEST_SPDIF_RX_DT; hdma_spdifrx_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; @@ -1668,8 +1668,8 @@ void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef* hspdifrx) hdma_spdifrx_rx.Init.FIFOMode = DMA_FIFOMODE_ENABLE; hdma_spdifrx_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; hdma_spdifrx_rx.Init.MemBurst = DMA_MBURST_SINGLE; - hdma_spdifrx_rx.Init.PeriphBurst = DMA_MBURST_SINGLE; - + hdma_spdifrx_rx.Init.PeriphBurst = DMA_MBURST_SINGLE; + HAL_DMA_DeInit(&hdma_spdifrx_rx); if (HAL_DMA_Init(&hdma_spdifrx_rx) != HAL_OK) { @@ -1677,7 +1677,7 @@ void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef* hspdifrx) } __HAL_LINKDMA(hspdifrx, hdmaDrRx, hdma_spdifrx_rx); - + HAL_NVIC_SetPriority(DMA1_Stream7_IRQn, 0x02, 0); HAL_NVIC_EnableIRQ(DMA1_Stream7_IRQn); } @@ -1713,10 +1713,10 @@ void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef* hdfsdm_channel) __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOF_CLK_ENABLE(); - /**DFSDM1 GPIO Configuration + /**DFSDM1 GPIO Configuration PC3 ------> DFSDM1_DATIN1 PB13 ------> DFSDM1_CKOUT - PF13 ------> DFSDM1_DATIN3 + PF13 ------> DFSDM1_DATIN3 */ GPIO_InitStruct.Pin = GPIO_PIN_13; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -1724,7 +1724,7 @@ void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef* hdfsdm_channel) GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; GPIO_InitStruct.Alternate = GPIO_AF3_DFSDM1; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - + GPIO_InitStruct.Pin = GPIO_PIN_3; GPIO_InitStruct.Alternate = GPIO_AF3_DFSDM1; HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); @@ -1737,10 +1737,10 @@ void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef* hdfsdm_channel) void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) { RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - + if(IS_ENGINEERING_BOOT_MODE()) { - /** Initializes the peripherals clock + /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_DFSDM1; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) @@ -1748,12 +1748,12 @@ void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) Error_Handler(); } } - + __HAL_RCC_DFSDM1_CLK_ENABLE(); /* DMA controller clock enable */ __HAL_RCC_DMAMUX_CLK_ENABLE(); __HAL_RCC_DMA2_CLK_ENABLE(); - + if(hdfsdm_filter->Instance == DFSDM1_Filter0) { hdma_dfsdm1_flt0.Instance = DMA2_Stream2; @@ -1777,7 +1777,7 @@ void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) /* Several peripheral DMA handle pointers point to the same DMA handle. Be aware that there is only one channel to perform all the requested DMAs. */ __HAL_LINKDMA(hdfsdm_filter,hdmaReg,hdma_dfsdm1_flt0); - + HAL_NVIC_SetPriority(DMA2_Stream2_IRQn, 2, 0); HAL_NVIC_EnableIRQ(DMA2_Stream2_IRQn); } @@ -1797,14 +1797,14 @@ void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) hdma_dfsdm1_flt1.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; hdma_dfsdm1_flt1.Init.MemBurst = DMA_MBURST_SINGLE; hdma_dfsdm1_flt1.Init.PeriphBurst = DMA_PBURST_SINGLE; - + if (HAL_DMA_Init(&hdma_dfsdm1_flt1) != HAL_OK) { Error_Handler(); } - + __HAL_LINKDMA(hdfsdm_filter,hdmaReg,hdma_dfsdm1_flt1); - + HAL_NVIC_SetPriority(DMA2_Stream1_IRQn, 2, 0); HAL_NVIC_EnableIRQ(DMA2_Stream1_IRQn); } @@ -1837,7 +1837,7 @@ void HAL_HASH_MspInit(HASH_HandleTypeDef* hhash) __HAL_RCC_HASH2_CLK_ENABLE(); /* USER CODE BEGIN HASH2_MspInit 1 */ __HAL_RCC_DMAMUX_CLK_ENABLE(); - + /* Peripheral DMA init*/ hdma_hash_in.Instance = DMA2_Stream7; hdma_hash_in.Init.Request = DMA_REQUEST_HASH2_IN; @@ -1946,7 +1946,7 @@ void HAL_RNG_MspInit(RNG_HandleTypeDef* hrng) /* USER CODE END RNG2_MspInit 0 */ if(IS_ENGINEERING_BOOT_MODE()) { - /** Initializes the peripherals clock + /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RNG2; PeriphClkInit.Rng2ClockSelection = RCC_RNG2CLKSOURCE_LSE; diff --git a/bsp/stm32/stm32wb55-st-nucleo/board/CubeMX_Config/Src/stm32wbxx_hal_msp.c b/bsp/stm32/stm32wb55-st-nucleo/board/CubeMX_Config/Src/stm32wbxx_hal_msp.c index 208e05644a..3e44fb9be1 100644 --- a/bsp/stm32/stm32wb55-st-nucleo/board/CubeMX_Config/Src/stm32wbxx_hal_msp.c +++ b/bsp/stm32/stm32wb55-st-nucleo/board/CubeMX_Config/Src/stm32wbxx_hal_msp.c @@ -226,7 +226,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) */ GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Alternate = GPIO_AF8_LPUART1; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); @@ -250,7 +250,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Alternate = GPIO_AF7_USART1; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); diff --git a/bsp/stm32/stm32wl55-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32wl55-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc index 4810da4b1f..510a488e01 100644 --- a/bsp/stm32/stm32wl55-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32wl55-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc @@ -45,12 +45,14 @@ PA1.GPIOParameters=GPIO_Label PA1.GPIO_Label=BUT2 PA1.Locked=true PA1.Signal=GPIO_Input -PA2.Locked=true +PA2.GPIOParameters=GPIO_PuPd +PA2.GPIO_PuPd=GPIO_PULLUP PA2.Mode=Asynchronous -PA2.Signal=LPUART1_TX -PA3.Locked=true +PA2.Signal=USART2_TX +PA3.GPIOParameters=GPIO_PuPd +PA3.GPIO_PuPd=GPIO_PULLUP PA3.Mode=Asynchronous -PA3.Signal=LPUART1_RX +PA3.Signal=USART2_RX PB11.GPIOParameters=GPIO_Label PB11.GPIO_Label=LED3 PB11.Locked=true diff --git a/bsp/stm32/stm32wl55-st-nucleo/board/CubeMX_Config/Src/stm32wlxx_hal_msp.c b/bsp/stm32/stm32wl55-st-nucleo/board/CubeMX_Config/Src/stm32wlxx_hal_msp.c index 72350eda0d..798e9a7ee0 100644 --- a/bsp/stm32/stm32wl55-st-nucleo/board/CubeMX_Config/Src/stm32wlxx_hal_msp.c +++ b/bsp/stm32/stm32wl55-st-nucleo/board/CubeMX_Config/Src/stm32wlxx_hal_msp.c @@ -102,7 +102,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) */ GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_2; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Alternate = GPIO_AF8_LPUART1; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); diff --git a/bsp/tm4c129x/drivers/drv_eth.c b/bsp/tm4c129x/drivers/drv_eth.c index 12d9f88f3e..11b96a10a5 100644 --- a/bsp/tm4c129x/drivers/drv_eth.c +++ b/bsp/tm4c129x/drivers/drv_eth.c @@ -89,10 +89,12 @@ #define PHY_PHYS_ADDR 0 #endif +#if 1 #ifndef EMAC_PHY_CONFIG #define EMAC_PHY_CONFIG (EMAC_PHY_TYPE_INTERNAL | EMAC_PHY_INT_MDIX_EN | \ EMAC_PHY_AN_100B_T_FULL_DUPLEX) #endif +#endif /** * If necessary, set the defaui32t number of transmit and receive DMA descriptors @@ -142,6 +144,11 @@ extern void lwIPHostGetTime(u32_t *time_s, u32_t *time_ns); #include "lwipopts.h" #include "drv_eth.h" +/* Define those to better describe your network interface. */ +#define IFNAME0 't' +#define IFNAME1 'i' + + /** * A structure used to keep track of driver state and error counts. */ @@ -233,6 +240,13 @@ static tStellarisIF g_StellarisIFData = { volatile uint32_t g_ui32NormalInts; volatile uint32_t g_ui32AbnormalInts; +/** + * Status flag for EEE link established + */ +#if EEE_SUPPORT +volatile bool g_bEEELinkActive; +#endif + /** * A macro which determines whether a pointer is within the SRAM address * space and, hence, points to a buffer that the Ethernet MAC can directly @@ -335,9 +349,35 @@ tivaif_hwinit(struct netif *psNetif) { uint16_t ui16Val; + /* clear the EEE Link Active flag */ +#if EEE_SUPPORT + g_bEEELinkActive = false; +#endif + + /* Set MAC hardware address length */ + psNetif->hwaddr_len = ETHARP_HWADDR_LEN; + + /* Set MAC hardware address */ + EMACAddrGet(EMAC0_BASE, 0, &(psNetif->hwaddr[0])); + + /* Maximum transfer unit */ + psNetif->mtu = 1500; + + /* Device capabilities */ + psNetif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP; + /* Initialize the DMA descriptors. */ InitDMADescriptors(); +#if defined(EMAC_PHY_IS_EXT_MII) || defined(EMAC_PHY_IS_EXT_RMII) + /* If PHY is external then reset the PHY before configuring it */ + EMACPHYWrite(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_BMCR, + EPHY_BMCR_MIIRESET); + + while((EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_BMCR) & + EPHY_BMCR_MIIRESET) == EPHY_BMCR_MIIRESET); +#endif + /* Clear any stray PHY interrupts that may be set. */ ui16Val = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_MISR1); ui16Val = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_MISR2); @@ -398,8 +438,13 @@ tivaif_hwinit(struct netif *psNetif) IntMasterEnable(); /* Tell the PHY to start an auto-negotiation cycle. */ +#if defined(EMAC_PHY_IS_EXT_MII) || defined(EMAC_PHY_IS_EXT_RMII) + EMACPHYWrite(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_BMCR, (EPHY_BMCR_SPEED | + EPHY_BMCR_DUPLEXM | EPHY_BMCR_ANEN | EPHY_BMCR_RESTARTAN)); +#else EMACPHYWrite(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_BMCR, (EPHY_BMCR_ANEN | EPHY_BMCR_RESTARTAN)); +#endif } #ifdef DEBUG @@ -484,16 +529,16 @@ tivaif_check_pbuf(struct pbuf *p) tivaif_trace_pbuf("Copied:", pBuf); #endif DRIVER_STATS_INC(TXCopyCount); - - /* Reduce the reference count on the original pbuf since - * we're not going to hold on to it after returning from - * tivaif_transmit. Note that we already bumped - * the reference count at the top of tivaif_transmit. - */ - pbuf_free(p); } } + /* Reduce the reference count on the original pbuf since we're not + * going to hold on to it after returning from tivaif_transmit. + * Note that we already bumped the reference count at the top of + * tivaif_transmit. + */ + pbuf_free(p); + /* Send back the new pbuf pointer or NULL if an error occurred. */ return(pBuf); } @@ -573,7 +618,7 @@ tivaif_transmit(net_device_t dev, struct pbuf *p) { /** * The current write descriptor has a pbuf attached to it so this - * implies that the ring is fui32l. Reject this transmit request with a + * implies that the ring is full. Reject this transmit request with a * memory error since we can't satisfy it just now. */ pbuf_free(p); @@ -630,13 +675,8 @@ tivaif_transmit(net_device_t dev, struct pbuf *p) pDesc->Desc.ui32CtrlStatus = 0; } -#ifdef RT_LWIP_USING_HW_CHECKSUM pDesc->Desc.ui32CtrlStatus |= (DES0_TX_CTRL_IP_ALL_CKHSUMS | DES0_TX_CTRL_CHAINED); -#else - pDesc->Desc.ui32CtrlStatus |= (DES0_TX_CTRL_NO_CHKSUM | - DES0_TX_CTRL_CHAINED); -#endif /* Decrement our descriptor counter, move on to the next buffer in the * pbuf chain. */ @@ -761,7 +801,7 @@ tivaif_receive(net_device_t dev) { tDescriptorList *pDescList; tStellarisIF *pIF; - struct pbuf *pBuf; + static struct pbuf *pBuf = NULL; uint32_t ui32DescEnd; /* Get a pointer to our state data */ @@ -773,10 +813,10 @@ tivaif_receive(net_device_t dev) /* Start with a NULL pbuf so that we don't try to link chain the first * time round. */ - pBuf = NULL; + //pBuf = NULL; /* Determine where we start and end our walk of the descriptor list */ - ui32DescEnd = pDescList->ui32Read ? (pDescList->ui32Read - 1) : (pDescList->ui32NumDescs - 1); + ui32DescEnd = pDescList->ui32Read ? (pDescList->ui32Read - 1) : (pDescList->ui32NumDescs - 1); /* Step through the descriptors that are marked for CPU attention. */ while(pDescList->ui32Read != ui32DescEnd) @@ -816,7 +856,7 @@ tivaif_receive(net_device_t dev) if(pBuf) { /* Link this pbuf to the last one we looked at since this buffer - * is a continuation of an existing frame (split across mui32tiple + * is a continuation of an existing frame (split across multiple * pbufs). Note that we use pbuf_cat() here rather than * pbuf_chain() since we don't want to increase the reference * count of either pbuf - we only want to link them together. @@ -843,6 +883,7 @@ tivaif_receive(net_device_t dev) pbuf_free(pBuf); LINK_STATS_INC(link.drop); DRIVER_STATS_INC(RXPacketErrCount); + pBuf = NULL; } else { @@ -860,13 +901,11 @@ tivaif_receive(net_device_t dev) #if NO_SYS if(ethernet_input(pBuf, psNetif) != RT_EOK) - { #else - //if(tcpip_input(pBuf, psNetif) != RT_EOK) - if((rt_mb_send(dev->rx_pbuf_mb, (rt_uint32_t)pBuf) != RT_EOK) || - (eth_device_ready(&(dev->parent)) != RT_EOK)) - { + //if(tcpip_input(pBuf, psNetif) != ERR_OK) + if(rt_mb_send(dev->rx_pbuf_mb, (rt_uint32_t)pBuf) != RT_EOK) #endif + { /* drop the packet */ LWIP_DEBUGF(NETIF_DEBUG, ("tivaif_input: input error\n")); pbuf_free(pBuf); @@ -943,6 +982,9 @@ void tivaif_process_phy_interrupt(net_device_t dev) { uint16_t ui16Val, ui16Status; +#if EEE_SUPPORT + uint16_t ui16EEEStatus; +#endif uint32_t ui32Config, ui32Mode, ui32RxMaxFrameSize; /* Read the PHY interrupt status. This clears all interrupt sources. @@ -951,13 +993,16 @@ tivaif_process_phy_interrupt(net_device_t dev) */ ui16Val = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_MISR1); - /* - * Dummy read PHY REG EPHY_BMSR, it will force update the EPHY_STS register - */ - EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_BMSR); /* Read the current PHY status. */ ui16Status = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_STS); + /* If EEE mode support is requested then read the value of the Link + * partners status + */ +#if EEE_SUPPORT + ui16EEEStatus = EMACPHYMMDRead(EMAC0_BASE, PHY_PHYS_ADDR, 0x703D); +#endif + /* Has the link status changed? */ if(ui16Val & EPHY_MISR1_LINKSTAT) { @@ -972,6 +1017,19 @@ tivaif_process_phy_interrupt(net_device_t dev) eth_device_linkchange(&(dev->parent), RT_TRUE); #endif + /* if the link has been advertised as EEE capable then configure + * the MAC register for LPI timers and manually set the PHY link + * status bit + */ +#if EEE_SUPPORT + if(ui16EEEStatus & 0x2) + { + EMACLPIConfig(EMAC0_BASE, true, 1000, 36); + EMACLPILinkSet(EMAC0_BASE); + g_bEEELinkActive = true; + } +#endif + /* In this case we drop through since we may need to reconfigure * the MAC depending upon the speed and half/fui32l-duplex settings. */ @@ -985,6 +1043,16 @@ tivaif_process_phy_interrupt(net_device_t dev) //tcpip_callback((tcpip_callback_fn)netif_set_link_down, psNetif); eth_device_linkchange(&(dev->parent), RT_FALSE); #endif + + /* if the link has been advertised as EEE capable then clear the + * MAC register LPI timers and manually clear the PHY link status + * bit + */ +#if EEE_SUPPORT + g_bEEELinkActive = false; + EMACLPILinkClear(EMAC0_BASE); + EMACLPIConfig(EMAC0_BASE, false, 1000, 0); +#endif } } @@ -1061,11 +1129,17 @@ tivaif_interrupt(net_device_t dev, uint32_t ui32Status) */ if(ui32Status & EMAC_INT_TRANSMIT) { +#if EEE_SUPPORT + if(g_bEEELinkActive) + { + EMACLPIEnter(EMAC0_BASE); + } +#endif tivaif_process_transmit(dev->dma_if); } /** - * Process the receive DMA list and pass all successfui32ly received packets + * Process the receive DMA list and pass all successfully received packets * up the stack. We also call this function in cases where the receiver has * stalled due to missing buffers since the receive function will attempt to * allocate new pbufs for descriptor entries which have none. diff --git a/bsp/tm4c129x/libraries/driverlib/adc.c b/bsp/tm4c129x/libraries/driverlib/adc.c index 81e7dc05fc..12e8553919 100644 --- a/bsp/tm4c129x/libraries/driverlib/adc.c +++ b/bsp/tm4c129x/libraries/driverlib/adc.c @@ -2,25 +2,25 @@ // // adc.c - Driver for the ADC. // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -554,7 +554,7 @@ ADCSequenceConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum, // Set the shift for the module and generator // ui32Gen = (ui32Gen - ADC_TRIGGER_PWM0) * 8; - + HWREG(ui32Base + ADC_O_TSSEL) = ((HWREG(ui32Base + ADC_O_TSSEL) & ~(0x30 << ui32Gen)) | ((ui32Trigger & 0x30) << ui32Gen)); @@ -568,10 +568,15 @@ ADCSequenceConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum, //! \param ui32Base is the base address of the ADC module. //! \param ui32SequenceNum is the sample sequence number. //! \param ui32Step is the step to be configured. -//! \param ui32Config is the configuration of this step; must be a logical OR +//! \param ui32Config is the configuration of this step; is a logical OR //! of \b ADC_CTL_TS, \b ADC_CTL_IE, \b ADC_CTL_END, \b ADC_CTL_D, one of the //! input channel selects (\b ADC_CTL_CH0 through \b ADC_CTL_CH23), and one of //! the digital comparator selects (\b ADC_CTL_CMP0 through \b ADC_CTL_CMP7). +//! On some parts the sample and hold time can be increased by including a +//! logical OR of one of \b ADC_CTL_SHOLD_4, \b ADC_CTL_SHOLD_8, +//! \b ADC_CTL_SHOLD_16, \b ADC_CTL_SHOLD_32, \b ADC_CTL_SHOLD_64, +//! \b ADC_CTL_SHOLD_128 or \b ADC_CTL_SHOLD_256. The default sample time is 4 +//! ADC clocks. //! //! This function configures the ADC for one step of a sample sequence. The //! ADC can be configured for single-ended or differential operation (the @@ -1010,9 +1015,9 @@ ADCSoftwareOversampleStepConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum, ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); ASSERT(ui32SequenceNum < 3); ASSERT(((ui32SequenceNum == 0) && - (ui32Step < + (ui32Step < (8 >> g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum]))) || - (ui32Step < + (ui32Step < (4 >> g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum]))); // @@ -1029,7 +1034,7 @@ ADCSoftwareOversampleStepConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum, // Loop through the hardware steps that make up this step of the software // oversampled sequence. // - for(ui32SequenceNum = + for(ui32SequenceNum = (1 << g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum]); ui32SequenceNum; ui32SequenceNum--) { @@ -1114,9 +1119,9 @@ ADCSoftwareOversampleDataGet(uint32_t ui32Base, uint32_t ui32SequenceNum, ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); ASSERT(ui32SequenceNum < 3); ASSERT(((ui32SequenceNum == 0) && - (ui32Count < + (ui32Count < (8 >> g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum]))) || - (ui32Count < + (ui32Count < (4 >> g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum]))); // @@ -1145,7 +1150,7 @@ ADCSoftwareOversampleDataGet(uint32_t ui32Base, uint32_t ui32SequenceNum, // // Write the averaged sample to the output buffer. // - *pui32Buffer++ = + *pui32Buffer++ = ui32Accum >> g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum]; } } @@ -1678,7 +1683,7 @@ ADCIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags) //! //! The ADC reference is set as specified by \e ui32Ref. It must be one of //! \b ADC_REF_INT, or \b ADC_REF_EXT_3V for internal or external reference -//! If \b ADC_REF_INT is chosen, then an internal 3V reference is used and +//! If \b ADC_REF_INT is chosen, then an internal 3V reference is used and //! no external reference is needed. If \b ADC_REF_EXT_3V is chosen, then //! a 3V reference must be supplied to the AVREF pin. //! @@ -1977,7 +1982,7 @@ ADCClockConfigSet(uint32_t ui32Base, uint32_t ui32Config, // // Check the argument. // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); + ASSERT(ui32Base == ADC0_BASE); ASSERT((ui32ClockDiv - 1) <= (ADC_CC_CLKDIV_M >> ADC_CC_CLKDIV_S)); // @@ -2036,12 +2041,12 @@ ADCClockConfigGet(uint32_t ui32Base, uint32_t *pui32ClockDiv) // // Check the argument. // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); + ASSERT(ui32Base == ADC0_BASE); // // Read the current configuration. // - ui32Config = HWREG(ui32Base + ADC_O_CC); + ui32Config = HWREG(ADC0_BASE + ADC_O_CC); // // If the clock divider was requested provide the current value. @@ -2060,7 +2065,7 @@ ADCClockConfigGet(uint32_t ui32Base, uint32_t *pui32ClockDiv) // // Add in the sample interval to the configuration. // - ui32Config |= (HWREG(ui32Base + ADC_O_PC) & ADC_PC_SR_M) << 4; + ui32Config |= (HWREG(ADC0_BASE + ADC_O_PC) & ADC_PC_SR_M) << 4; return(ui32Config); } diff --git a/bsp/tm4c129x/libraries/driverlib/adc.h b/bsp/tm4c129x/libraries/driverlib/adc.h index 993b6a3fb5..d2d6bcd38b 100644 --- a/bsp/tm4c129x/libraries/driverlib/adc.h +++ b/bsp/tm4c129x/libraries/driverlib/adc.h @@ -2,25 +2,25 @@ // // adc.h - ADC headers for using the ADC driver functions. // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/aes.c b/bsp/tm4c129x/libraries/driverlib/aes.c index 06cf55bb0b..d15a0900e5 100644 --- a/bsp/tm4c129x/libraries/driverlib/aes.c +++ b/bsp/tm4c129x/libraries/driverlib/aes.c @@ -2,25 +2,25 @@ // // aes.c - Driver for the AES module. // -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2012-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/aes.h b/bsp/tm4c129x/libraries/driverlib/aes.h index 6cf44780dd..6b505f68b3 100644 --- a/bsp/tm4c129x/libraries/driverlib/aes.h +++ b/bsp/tm4c129x/libraries/driverlib/aes.h @@ -2,25 +2,25 @@ // // aes.h - Defines and Macros for the AES module. // -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2012-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/can.c b/bsp/tm4c129x/libraries/driverlib/can.c index d53584585c..81b05446a4 100644 --- a/bsp/tm4c129x/libraries/driverlib/can.c +++ b/bsp/tm4c129x/libraries/driverlib/can.c @@ -2,25 +2,25 @@ // // can.c - Driver for the CAN module. // -// Copyright (c) 2006-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2006-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -831,7 +831,7 @@ CANIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) IntRegister(ui8IntNumber, pfnHandler); // - // Enable the Ethernet interrupt. + // Enable the CAN interrupt. // IntEnable(ui8IntNumber); } @@ -1077,6 +1077,13 @@ CANIntStatus(uint32_t ui32Base, tCANIntStsReg eIntStsReg) //! being immediately reentered (because the interrupt controller still sees //! the interrupt source asserted). //! +//! \note The functions CANIntClear(), CANMessageSet(), and CANMessageClear() +//! are not re-entrant. If any of these functions are used in the main +//! application code and if any of them are also used within an interrupt +//! routine, then the corresponding interrupt for that interrupt routine should +//! be disabled prior to the call for any of these functions. The interrupt +//! can be re-enabled immediately after the function call has returned. +//! //! \return None. // //***************************************************************************** @@ -1470,6 +1477,13 @@ CANErrCntrGet(uint32_t ui32Base, uint32_t *pui32RxCount, //! If you specify a message object buffer that already contains a message //! definition, it is overwritten. //! +//! \note The functions CANIntClear(), CANMessageSet(), and CANMessageClear() +//! are not re-entrant. If any of these functions are used in the main +//! application code and if any of them are also used within an interrupt +//! routine, then the corresponding interrupt for that interrupt routine should +//! be disabled prior to the call for any of these functions. The interrupt +//! can be re-enabled immediately after the function call has returned. +//! //! \return None. // //***************************************************************************** @@ -1831,6 +1845,12 @@ CANMessageSet(uint32_t ui32Base, uint32_t ui32ObjID, //! - \b MSG_OBJ_DATA_LOST indicates that at least one message was received on //! this message object and not read by the host before being overwritten. //! +//! \note This function is not re-entrant. If it is used in both main +//! application code and in an interrupt routine, then the corresponding +//! interrupt should be disabled prior to the call for CANMessageGet(). +//! The interrupt can be re-enabled immediately after the function call has +//! returned. +//! //! \return None. // //***************************************************************************** @@ -2076,6 +2096,13 @@ CANMessageGet(uint32_t ui32Base, uint32_t ui32ObjID, //! object has been ``cleared,'' it no longer automatically sends or receives //! messages, nor does it generate interrupts. //! +//! \note The functions CANIntClear(), CANMessageSet(), and CANMessageClear() +//! are not re-entrant. If any of these functions are used in the main +//! application code and if any of them are also used within an interrupt +//! routine, then the corresponding interrupt for that interrupt routine should +//! be disabled prior to the call for any of these functions. The interrupt +//! can be re-enabled immediately after the function call has returned. +//! //! \return None. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/can.h b/bsp/tm4c129x/libraries/driverlib/can.h index 199721906b..c4a8b10ca2 100644 --- a/bsp/tm4c129x/libraries/driverlib/can.h +++ b/bsp/tm4c129x/libraries/driverlib/can.h @@ -2,25 +2,25 @@ // // can.h - Defines and Macros for the CAN controller. // -// Copyright (c) 2006-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2006-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/comp.c b/bsp/tm4c129x/libraries/driverlib/comp.c index 6f03b7c01a..3b4ab2042b 100644 --- a/bsp/tm4c129x/libraries/driverlib/comp.c +++ b/bsp/tm4c129x/libraries/driverlib/comp.c @@ -2,25 +2,25 @@ // // comp.c - Driver for the analog comparator. // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/comp.h b/bsp/tm4c129x/libraries/driverlib/comp.h index 2f95df09c9..5f33b332a8 100644 --- a/bsp/tm4c129x/libraries/driverlib/comp.h +++ b/bsp/tm4c129x/libraries/driverlib/comp.h @@ -2,25 +2,25 @@ // // comp.h - Prototypes for the analog comparator driver. // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/cpu.c b/bsp/tm4c129x/libraries/driverlib/cpu.c index 0cddffc340..fb1c9a667b 100644 --- a/bsp/tm4c129x/libraries/driverlib/cpu.c +++ b/bsp/tm4c129x/libraries/driverlib/cpu.c @@ -3,25 +3,25 @@ // cpu.c - Instruction wrappers for special CPU instructions needed by the // drivers. // -// Copyright (c) 2006-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2006-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -33,8 +33,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/cpu.h b/bsp/tm4c129x/libraries/driverlib/cpu.h index 11a07e88d0..4f8976e9cf 100644 --- a/bsp/tm4c129x/libraries/driverlib/cpu.h +++ b/bsp/tm4c129x/libraries/driverlib/cpu.h @@ -2,25 +2,25 @@ // // cpu.h - Prototypes for the CPU instruction wrapper functions. // -// Copyright (c) 2006-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2006-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/crc.c b/bsp/tm4c129x/libraries/driverlib/crc.c index 55bd4d6048..a4364a9b13 100644 --- a/bsp/tm4c129x/libraries/driverlib/crc.c +++ b/bsp/tm4c129x/libraries/driverlib/crc.c @@ -2,25 +2,25 @@ // // crc.c - Driver for the CRC module. // -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2012-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/crc.h b/bsp/tm4c129x/libraries/driverlib/crc.h index 7d33e84cb6..eff20a2f4f 100644 --- a/bsp/tm4c129x/libraries/driverlib/crc.h +++ b/bsp/tm4c129x/libraries/driverlib/crc.h @@ -2,25 +2,25 @@ // // crc.h - Defines and Macros for CRC module. // -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2012-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/debug.h b/bsp/tm4c129x/libraries/driverlib/debug.h index fd2e3afba1..3181b236d9 100644 --- a/bsp/tm4c129x/libraries/driverlib/debug.h +++ b/bsp/tm4c129x/libraries/driverlib/debug.h @@ -2,25 +2,25 @@ // // debug.h - Macros for assisting debug of the driver library. // -// Copyright (c) 2006-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2006-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/des.c b/bsp/tm4c129x/libraries/driverlib/des.c index 1b6e86a2a8..0b92887b5d 100644 --- a/bsp/tm4c129x/libraries/driverlib/des.c +++ b/bsp/tm4c129x/libraries/driverlib/des.c @@ -2,25 +2,25 @@ // // des.c - Driver for the DES data transformation. // -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2012-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/des.h b/bsp/tm4c129x/libraries/driverlib/des.h index 9f6c8d1853..54cfb50776 100644 --- a/bsp/tm4c129x/libraries/driverlib/des.h +++ b/bsp/tm4c129x/libraries/driverlib/des.h @@ -2,25 +2,25 @@ // // des.h - Defines and Macros for the DES module. // -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2012-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/eeprom.c b/bsp/tm4c129x/libraries/driverlib/eeprom.c index 6daae87be0..11b0635326 100644 --- a/bsp/tm4c129x/libraries/driverlib/eeprom.c +++ b/bsp/tm4c129x/libraries/driverlib/eeprom.c @@ -2,25 +2,25 @@ // // eeprom.c - Driver for programming the on-chip EEPROM. // -// Copyright (c) 2010-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2010-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/eeprom.h b/bsp/tm4c129x/libraries/driverlib/eeprom.h index 0336010e06..0df91a05e6 100644 --- a/bsp/tm4c129x/libraries/driverlib/eeprom.h +++ b/bsp/tm4c129x/libraries/driverlib/eeprom.h @@ -2,25 +2,25 @@ // // eeprom.h - Prototypes for the EEPROM driver. // -// Copyright (c) 2010-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2010-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/emac.c b/bsp/tm4c129x/libraries/driverlib/emac.c index 8c238d299e..4887f55e27 100644 --- a/bsp/tm4c129x/libraries/driverlib/emac.c +++ b/bsp/tm4c129x/libraries/driverlib/emac.c @@ -3,25 +3,25 @@ // emac.c - Driver for the Integrated Ethernet Controller on Snowflake-class // Tiva devices. // -// Copyright (c) 2013-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2013-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -33,8 +33,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -297,12 +297,12 @@ g_pi16MIIClockDiv[] = //! (where each descriptor includes a field that points to the next descriptor //! in the list). In ring mode, the hardware uses the \e ui32DescSkipSize to //! skip past any application-defined fields after the end of the hardware- -//! defined descriptor fields. The parameter value indicates the number of -//! 32-bit words to skip after the last field of the hardware-defined -//! descriptor to get to the first field of the next descriptor. When using -//! arrays of either the \b tEMACDMADescriptor or \b tEMACAltDMADescriptor +//! defined descriptor fields. The parameter value indicates the number of +//! 32-bit words to skip after the last field of the hardware-defined +//! descriptor to get to the first field of the next descriptor. When using +//! arrays of either the \b tEMACDMADescriptor or \b tEMACAltDMADescriptor //! types defined for this driver, \e ui32DescSkipSize must be set to 1 to skip -//! the \e pvNext pointer added to the end of each of these structures. +//! the \e pvNext pointer added to the end of each of these structures. //! Applications may modify these structure definitions to include their own //! application-specific data and modify \e ui32DescSkipSize appropriately if //! desired. @@ -419,8 +419,8 @@ EMACInit(uint32_t ui32Base, uint32_t ui32SysClk, uint32_t ui32BusConfig, //! //! \param ui32Base is the base address of the Ethernet controller. //! -//! This function performs a reset of the Ethernet MAC by resetting all logic -//! and returning all registers to their default values. The function returns +//! This function performs a reset of the Ethernet MAC by resetting all logic +//! and returning all registers to their default values. The function returns //! only after the hardware indicates that the reset has completed. //! //! \note To ensure that the reset completes, the selected PHY clock must be @@ -495,7 +495,7 @@ EMACReset(uint32_t ui32Base) //! RMII interface. //! //! If \b EMAC_PHY_TYPE_INTERNAL is selected, the following flags may be ORed -//! into \e ui32Config to control various PHY features and modes. These flags +//! into \e ui32Config to control various PHY features and modes. These flags //! are ignored if an external PHY is selected. //! //! - \b EMAC_PHY_INT_NIB_TXERR_DET_DIS disables odd nibble transmit error @@ -682,7 +682,7 @@ EMACPHYConfigSet(uint32_t ui32Base, uint32_t ui32Config) //! The back-off limit determines the range of the random time that the MAC //! delays after a collision and before attempting to retransmit a frame. One //! of the following values must be used to select this limit. In each case, -//! the retransmission delay in terms of 512 bit time slots, is the lower of +//! the retransmission delay in terms of 512 bit time slots, is the lower of //! (2 ** N) and a random number between 0 and the selected backoff-limit. //! //! - \b EMAC_CONFIG_BO_LIMIT_1024 @@ -727,10 +727,10 @@ EMACPHYConfigSet(uint32_t ui32Base, uint32_t ui32Config) //! up to 9018 (or 9022 if using VLAN tagging) to be handled without reporting //! giant frame errors. //! - \b EMAC_CONFIG_100MBPS forces the MAC to communicate with the PHY using -//! 100Mbps signaling. If this option is not specified, the MAC uses 10Mbps -//! signaling. This speed setting is important when using an external RMII -//! PHY where the selected rate must match the PHY's setting which may have -//! been made as a result of auto-negotiation. When using the internal PHY +//! 100Mbps signaling. If this option is not specified, the MAC uses 10Mbps +//! signaling. This speed setting is important when using an external RMII +//! PHY where the selected rate must match the PHY's setting which may have +//! been made as a result of auto-negotiation. When using the internal PHY //! or an external MII PHY, the signaling rate is controlled by the PHY- //! provided transmit and receive clocks. //! - \b EMAC_CONFIG_CS_DISABLE disables Carrier Sense during transmission @@ -743,15 +743,15 @@ EMACPHYConfigSet(uint32_t ui32Base, uint32_t ui32Config) //! of the checksum calculations are reported via status fields in the DMA //! receive descriptors. //! - \b EMAC_CONFIG_RETRY_DISABLE disables retransmission in cases where -//! half-duplex mode is in use and a collision occurs. This condition causes -//! the current frame to be ignored and a frame abort to be reported in the +//! half-duplex mode is in use and a collision occurs. This condition causes +//! the current frame to be ignored and a frame abort to be reported in the //! transmit frame status. //! - \b EMAC_CONFIG_AUTO_CRC_STRIPPING strips the last 4 bytes (frame check //! sequence) from all Ether type frames before forwarding the frames to the //! application. //! - \b EMAC_CONFIG_DEFERRAL_CHK_ENABLE enables transmit deferral checking -//! in half-duplex mode. When enabled, the transmitter reports an error if it -//! is unable to transmit a frame for more than 24288 bit times (or 155680 +//! in half-duplex mode. When enabled, the transmitter reports an error if it +//! is unable to transmit a frame for more than 24288 bit times (or 155680 //! bit times in Jumbo frame mode) due to an active carrier sense signal on //! the MII. //! @@ -971,14 +971,14 @@ EMACConfigSet(uint32_t ui32Base, uint32_t ui32Config, uint32_t ui32ModeFlags, //! fields in the DMA receive descriptors. //! - \b EMAC_CONFIG_RETRY_DISABLE indicates that retransmission is disabled //! in cases where half-duplex mode is in use and a collision occurs. This -//! condition causes the current frame to be ignored and a frame abort to be +//! condition causes the current frame to be ignored and a frame abort to be //! reported in the transmit frame status. //! - \b EMAC_CONFIG_AUTO_CRC_STRIPPING indicates that the last 4 bytes //! (frame check sequence) from all Ether type frames are being stripped before //! frames are forwarded to the application. //! - \b EMAC_CONFIG_DEFERRAL_CHK_ENABLE indicates that transmit deferral //! checking is disabled in half-duplex mode. When enabled, the transmitter -//! reports an error if it is unable to transmit a frame for more than 24288 +//! reports an error if it is unable to transmit a frame for more than 24288 //! bit times (or 155680 bit times in Jumbo frame mode) due to an active //! carrier sense signal on the MII. //! - \b EMAC_CONFIG_TX_ENABLED indicates that the MAC transmitter is @@ -1225,7 +1225,7 @@ EMACAddrSet(uint32_t ui32Base, uint32_t ui32Index, const uint8_t *pui8MACAddr) //! //! AC-DE-48-00-00-80 //! -//! the data is returned with 0xAC in the first byte of the array, 0xDE in +//! the data is returned with 0xAC in the first byte of the array, 0xDE in //! the second, 0x48 in the third and so on. //! //! \return None. @@ -1287,7 +1287,7 @@ EMACNumAddrGet(uint32_t ui32Base) //! addresses. //! //! \param ui32Base is the base address of the controller. -//! \param ui32Index is the index of the MAC address slot for which the filter +//! \param ui32Index is the index of the MAC address slot for which the filter //! is to be set. //! \param ui32Config sets the filter parameters for the given MAC address. //! @@ -1295,9 +1295,9 @@ EMACNumAddrGet(uint32_t ui32Base) //! address slots that the controller supports. This configuration is used //! when perfect filtering (rather than hash table filtering) is selected. //! -//! Valid values for \e ui32Index are from 1 to (number of MAC address -//! slots - 1). The number of supported MAC address slots may be found by -//! calling EMACNumAddrGet(). MAC index 0 is the local MAC address and does +//! Valid values for \e ui32Index are from 1 to (number of MAC address +//! slots - 1). The number of supported MAC address slots may be found by +//! calling EMACNumAddrGet(). MAC index 0 is the local MAC address and does //! not have filtering parameters associated with it. //! //! The \e ui32Config parameter determines how the given MAC address is used @@ -1362,16 +1362,16 @@ EMACAddrFilterSet(uint32_t ui32Base, uint32_t ui32Index, uint32_t ui32Config) //! addresses. //! //! \param ui32Base is the base address of the controller. -//! \param ui32Index is the index of the MAC address slot for which the filter +//! \param ui32Index is the index of the MAC address slot for which the filter //! is to be queried. //! //! This function returns filtering parameters associated with one of the MAC //! address slots that the controller supports. This configuration is used //! when perfect filtering (rather than hash table filtering) is selected. //! -//! Valid values for \e ui32Index are from 1 to (number of MAC address -//! slots - 1). The number of supported MAC address slots may be found by -//! calling EMACNumAddrGet(). MAC index 0 is the local MAC address and does +//! Valid values for \e ui32Index are from 1 to (number of MAC address +//! slots - 1). The number of supported MAC address slots may be found by +//! calling EMACNumAddrGet(). MAC index 0 is the local MAC address and does //! not have filtering parameters associated with it. //! //! \return Returns the filter configuration as the logical OR of the @@ -1450,7 +1450,7 @@ EMACAddrFilterGet(uint32_t ui32Base, uint32_t ui32Index) //! when the source address field in the frame does not match the values //! programmed into the enabled SA registers. //! - \b EMAC_FRMFILTER_INV_SADDR enables inverse source address filtering. -//! When this option is specified, frames for which the SA does not match the +//! When this option is specified, frames for which the SA does not match the //! SA registers are marked as passing the source address filter. //! - \b EMAC_FRMFILTER_BROADCAST configures the MAC to discard all incoming //! broadcast frames. @@ -1530,7 +1530,7 @@ EMACFrameFilterSet(uint32_t ui32Base, uint32_t ui32FilterOpts) //! received frames when the source address field in the frame does not match //! the values programmed into the enabled SA registers. //! - \b EMAC_FRMFILTER_INV_SADDR enables inverse source address filtering. -//! When this option is specified, frames for which the SA does not match the +//! When this option is specified, frames for which the SA does not match the //! SA registers are marked as passing the source address filter. //! - \b EMAC_FRMFILTER_BROADCAST indicates that the MAC is configured to //! discard all incoming broadcast frames. @@ -1621,9 +1621,9 @@ EMACHashFilterSet(uint32_t ui32Base, uint32_t ui32HashHi, uint32_t ui32HashLo) //! Returns the current MAC address hash filter table. //! //! \param ui32Base is the base address of the controller. -//! \param pui32HashHi points to storage to be written with the upper 32 bits +//! \param pui32HashHi points to storage to be written with the upper 32 bits //! of the current 64-bit hash filter table. -//! \param pui32HashLo points to storage to be written with the lower 32 bits +//! \param pui32HashLo points to storage to be written with the lower 32 bits //! of the current 64-bit hash filter table. //! //! This function may be used to retrieve the current 64-bit hash filter table @@ -1766,8 +1766,8 @@ EMACRxWatchdogTimerSet(uint32_t ui32Base, uint8_t ui8Timeout) //! - \b EMAC_STATUS_RWC_ACTIVE //! - \b EMAC_STATUS_RPE_ACTIVE //! -//! The transmit frame controller status can be extracted from the returned -//! value by ANDing with \b EMAC_STATUS_TFC_STATE_MASK and is one of the +//! The transmit frame controller status can be extracted from the returned +//! value by ANDing with \b EMAC_STATUS_TFC_STATE_MASK and is one of the //! following: //! //! - \b EMAC_STATUS_TFC_STATE_IDLE @@ -1775,8 +1775,8 @@ EMACRxWatchdogTimerSet(uint32_t ui32Base, uint8_t ui8Timeout) //! - \b EMAC_STATUS_TFC_STATE_PAUSING //! - \b EMAC_STATUS_TFC_STATE_WRITING //! -//! The transmit FIFO read controller status can be extracted from the returned -//! value by ANDing with \b EMAC_STATUS_TRC_STATE_MASK and is one of the +//! The transmit FIFO read controller status can be extracted from the returned +//! value by ANDing with \b EMAC_STATUS_TRC_STATE_MASK and is one of the //! following: //! //! - \b EMAC_STATUS_TRC_STATE_IDLE @@ -1785,7 +1785,7 @@ EMACRxWatchdogTimerSet(uint32_t ui32Base, uint8_t ui8Timeout) //! - \b EMAC_STATUS_TRC_STATE_STATUS //! //! The current receive FIFO levels can be extracted from the returned value -//! by ANDing with \b EMAC_STATUS_RX_FIFO_LEVEL_MASK and is one of the +//! by ANDing with \b EMAC_STATUS_RX_FIFO_LEVEL_MASK and is one of the //! following: //! //! - \b EMAC_STATUS_RX_FIFO_EMPTY indicating that the FIFO is empty. @@ -1796,7 +1796,7 @@ EMACRxWatchdogTimerSet(uint32_t ui32Base, uint8_t ui8Timeout) //! - \b EMAC_STATUS_RX_FIFO_FULL indicating that the FIFO is full. //! //! The current receive FIFO state can be extracted from the returned value -//! by ANDing with \b EMAC_STATUS_RX_FIFO_STATE_MASK and is one of the +//! by ANDing with \b EMAC_STATUS_RX_FIFO_STATE_MASK and is one of the //! following: //! //! - \b EMAC_STATUS_RX_FIFO_IDLE @@ -2049,7 +2049,7 @@ EMACTxDMADescriptorListSet(uint32_t ui32Base, tEMACDMADescriptor *pDescriptor) //! \param ui32Base is the base address of the controller. //! //! This function returns a pointer to the head of the Ethernet MAC's transmit -//! DMA descriptor list. This value corresponds to the pointer originally set +//! DMA descriptor list. This value corresponds to the pointer originally set //! using a call to EMACTxDMADescriptorListSet(). //! //! \return Returns a pointer to the start of the DMA transmit descriptor list. @@ -2438,8 +2438,8 @@ EMACIntUnregister(uint32_t ui32Base) //! - \b EMAC_INT_RX_OVERFLOW indicates that an overflow was experienced //! during reception. //! - \b EMAC_INT_TX_JABBER indicates that the transmit jabber timer expired. -//! This condition occurs when the frame size exceeds 2048 bytes (or 10240 -//! bytes in Jumbo Frame mode) and causes the transmit process to abort and +//! This condition occurs when the frame size exceeds 2048 bytes (or 10240 +//! bytes in Jumbo Frame mode) and causes the transmit process to abort and //! enter the Stopped state. //! - \b EMAC_INT_TX_NO_BUFFER indicates that the host owns the next buffer //! in the DMA's transmit descriptor list and that the DMA cannot, therefore, @@ -2540,8 +2540,8 @@ EMACIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) //! - \b EMAC_INT_RX_OVERFLOW indicates that an overflow was experienced //! during reception. //! - \b EMAC_INT_TX_JABBER indicates that the transmit jabber timer expired. -//! This condition occurs when the frame size exceeds 2048 bytes (or 10240 -//! bytes in Jumbo Frame mode) and causes the transmit process to abort and +//! This condition occurs when the frame size exceeds 2048 bytes (or 10240 +//! bytes in Jumbo Frame mode) and causes the transmit process to abort and //! enter the Stopped state. //! - \b EMAC_INT_TX_NO_BUFFER indicates that the host owns the next buffer //! in the DMA's transmit descriptor list and that the DMA cannot, therefore, @@ -2660,8 +2660,8 @@ EMACIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) //! - \b EMAC_INT_RX_OVERFLOW indicates that an overflow was experienced //! during reception. //! - \b EMAC_INT_TX_JABBER indicates that the transmit jabber timer expired. -//! This condition occurs when the frame size exceeds 2048 bytes (or 10240 -//! bytes in Jumbo Frame mode) and causes the transmit process to abort and +//! This condition occurs when the frame size exceeds 2048 bytes (or 10240 +//! bytes in Jumbo Frame mode) and causes the transmit process to abort and //! enter the Stopped state. //! - \b EMAC_INT_TX_NO_BUFFER indicates that the host owns the next buffer //! in the DMA's transmit descriptor list and that the DMA cannot, therefore, @@ -2767,8 +2767,8 @@ EMACIntStatus(uint32_t ui32Base, bool bMasked) //! - \b EMAC_INT_RX_OVERFLOW indicates that an overflow was experienced //! during reception. //! - \b EMAC_INT_TX_JABBER indicates that the transmit jabber timer expired. -//! This condition occurs when the frame size exceeds 2048 bytes (or 10240 -//! bytes in Jumbo Frame mode) and causes the transmit process to abort and +//! This condition occurs when the frame size exceeds 2048 bytes (or 10240 +//! bytes in Jumbo Frame mode) and causes the transmit process to abort and //! enter the Stopped state. //! - \b EMAC_INT_TX_NO_BUFFER indicates that the host owns the next buffer //! in the DMA's transmit descriptor list and that the DMA cannot, therefore, @@ -3160,7 +3160,7 @@ EMACPHYPowerOn(uint32_t ui32Base, uint8_t ui8PhyAddr) //! simple 31-bit counter, rolling over to 0 after reaching 0x7FFFFFFF. In //! this case, each lsb of the subsecond counter represents 0.465 ns (assuming //! the definition of 1 second resolution for the seconds counter). When -//! binary rollover mode is selected, the subsecond counter acts as a +//! binary rollover mode is selected, the subsecond counter acts as a //! nanosecond counter and rolls over to 0 after reaching 999,999,999 making //! each lsb represent 1 nanosecond. //! @@ -3250,7 +3250,7 @@ EMACTimestampConfigSet(uint32_t ui32Base, uint32_t ui32Config, //! are filtered using any of the configured MAC addresses. Messages with a //! destination address programmed into the MAC address filter are passed, //! others are discarded. If this flag is absent, the MAC address is ignored. -//! - \b EMAC_TS_UPDATE_FINE implements the fine update method that causes the +//! - \b EMAC_TS_UPDATE_FINE implements the fine update method that causes the //! IEEE 1588 clock to advance by the the value returned in the //! \e *pui32SubSecondInc parameter each time a carry is generated from the //! addend accumulator register. If this flag is absent, the coarse update @@ -3689,7 +3689,7 @@ EMACTimestampTargetIntDisable(uint32_t ui32Base) ASSERT(ui32Base == EMAC0_BASE); // - // Clear the bit to disable the timestamp target interrupt. This bit + // Clear the bit to disable the timestamp target interrupt. This bit // clears automatically when the interrupt fires, so it only must be // disabled if you want to cancel a previously-set interrupt. // @@ -4022,7 +4022,7 @@ EMACTimestampPPSPeriodSet(uint32_t ui32Base, uint32_t ui32Period, //! (Type = 0x88A8) frames as valid VLAN-tagged frames. If absent, only //! frames with type 0x8100 are considered valid VLAN frames. //! - \b EMAC_VLAN_RX_INVERSE_MATCH causes the receiver to pass all VLAN -//! frames for which the tags do not match the supplied \e ui16Tag value. If +//! frames for which the tags do not match the supplied \e ui16Tag value. If //! this flag is absent, only tagged frames matching \e ui16Tag are passed. //! - \b EMAC_VLAN_RX_12BIT_TAG causes the receiver to compare only the //! bottom 12 bits of \e ui16Tag when performing either perfect or hash @@ -4082,7 +4082,7 @@ EMACVLANRxConfigSet(uint32_t ui32Base, uint16_t ui16Tag, uint32_t ui32Config) //! S-VLAN (Type = 0x88A8) frames as valid VLAN-tagged frames. If absent, only //! frames with type 0x8100 are considered valid VLAN frames. //! - \b EMAC_VLAN_RX_INVERSE_MATCH indicates that the receiver passes all -//! VLAN frames for which the tags do not match the \e *pui16Tag value. If +//! VLAN frames for which the tags do not match the \e *pui16Tag value. If //! this flag is absent, only tagged frames matching \e *pui16Tag are passed. //! - \b EMAC_VLAN_RX_12BIT_TAG indicates that the receiver is comparing only //! the bottom 12 bits of \e *pui16Tag when performing either perfect or hash @@ -4254,7 +4254,7 @@ EMACVLANTxConfigGet(uint32_t ui32Base, uint16_t *pui16Tag) //! Returns the bit number to set in the VLAN hash filter corresponding to a //! given tag. //! -//! \param ui16Tag is the VLAN tag for which the hash filter bit number is to +//! \param ui16Tag is the VLAN tag for which the hash filter bit number is to //! be determined. //! //! This function may be used to determine which bit in the VLAN hash filter @@ -4379,8 +4379,8 @@ EMACVLANHashFilterGet(uint32_t ui32Base) //! calculated on up to 31 payload bytes in the frame. The actual bytes used //! in the CRC calculation are defined by means of a bit mask where a ``1'' //! indicates that a byte in the frame should contribute to the CRC -//! calculation and a ``0'' indicates that the byte should be skipped, as well -//! as an offset from the start of the frame to the payload byte that represents +//! calculation and a ``0'' indicates that the byte should be skipped, as well +//! as an offset from the start of the frame to the payload byte that represents //! the first byte in the 31-byte CRC-checked sequence. //! //! The \e pFilter parameter points to a structure containing the information @@ -4400,7 +4400,7 @@ EMACVLANHashFilterGet(uint32_t ui32Base) //! - \b pui8Offset defines the zero-based index of the byte within the frame //! at which CRC checking defined by \b pui32ByteMask begins. //! Alternatively, this value can be thought of as the number of bytes in the -//! frame that the MAC skips before accumulating the CRC based on the pattern +//! frame that the MAC skips before accumulating the CRC based on the pattern //! in \b pui32ByteMask. //! - \b pui16CRC provides the value of the calculated CRC for a valid remote //! wake-up frame. If the incoming frame is processed according to the filter @@ -4466,7 +4466,7 @@ EMACRemoteWakeUpFrameFilterSet(uint32_t ui32Base, //! actual bytes used in the CRC calculation are defined by means of a bit mask //! where a ``1'' indicates that a byte in the frame should contribute to the //! CRC calculation and a ``0'' indicates that the byte should be skipped, and -//! an offset from the start of the frame to the payload byte that represents +//! an offset from the start of the frame to the payload byte that represents //! the first byte in the 31-byte CRC-checked sequence. //! //! The \e pFilter parameter points to storage that is written with a @@ -4756,7 +4756,7 @@ EMACWoLEnter(uint32_t ui32Base) //! This function is used to configure the LPI timer and control registers when //! the link is established as EEE mode or when the link is lost. When the link //! is established as EEE, then \e ui16LPILSTimer is programmed as the link -//! status timer value and \e ui16LPITWTimer is programmed as the transmit wait +//! status timer value and \e ui16LPITWTimer is programmed as the transmit wait //! timer value. The parameter \e bLPIConfig is used to decide if the transmit //! path must be automated or should be under user control. //! @@ -4773,7 +4773,7 @@ EMACLPIConfig(uint32_t ui32Base, bool bLPIConfig, uint16_t ui16LPILSTimer, // Parameter sanity check. // ASSERT(ui32Base == EMAC0_BASE); - + ui32TimerValue = ((ui16LPILSTimer << EMAC_LPITIMERCTL_LST_S) & EMAC_LPITIMERCTL_LST_M); ui32TimerValue |= ui16LPITWTimer & EMAC_LPITIMERCTL_TWT_M; @@ -4932,7 +4932,7 @@ EMACPHYMMDWrite(uint32_t ui32Base, uint8_t ui8PhyAddr, uint16_t ui16RegAddr, // // Write the extended register value. // - EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_REGCTL, + EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_REGCTL, (0x4000 | DEV_ADDR(ui16RegAddr))); EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_REGCTL, ui16Data); } @@ -4970,7 +4970,7 @@ EMACPHYMMDRead(uint32_t ui32Base, uint8_t ui8PhyAddr, uint16_t ui16RegAddr) // // Read the extended register value. // - EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_REGCTL, + EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_REGCTL, (0x4000 | DEV_ADDR(ui16RegAddr))); return(EMACPHYRead(ui32Base, ui8PhyAddr, EPHY_ADDAR)); } diff --git a/bsp/tm4c129x/libraries/driverlib/emac.h b/bsp/tm4c129x/libraries/driverlib/emac.h index f82919c8c0..4fd0811865 100644 --- a/bsp/tm4c129x/libraries/driverlib/emac.h +++ b/bsp/tm4c129x/libraries/driverlib/emac.h @@ -3,25 +3,25 @@ // emac.h - Defines and Macros for the Ethernet module on Snowflake-class // devices. // -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2012-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -33,8 +33,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/epi.c b/bsp/tm4c129x/libraries/driverlib/epi.c index c85a02621e..43f146272c 100644 --- a/bsp/tm4c129x/libraries/driverlib/epi.c +++ b/bsp/tm4c129x/libraries/driverlib/epi.c @@ -2,25 +2,25 @@ // // epi.c - Driver for the EPI module. // -// Copyright (c) 2008-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2008-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/epi.h b/bsp/tm4c129x/libraries/driverlib/epi.h index fc26a81469..9a0a8b4d0c 100644 --- a/bsp/tm4c129x/libraries/driverlib/epi.h +++ b/bsp/tm4c129x/libraries/driverlib/epi.h @@ -2,25 +2,25 @@ // // epi.h - Prototypes and macros for the EPI module. // -// Copyright (c) 2008-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2008-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -338,7 +338,7 @@ EPIWorkaroundWordWrite(uint32_t *pui32Addr, uint32_t ui32Value) __asm { // - // Add a NOP to ensure we dont have a flash read immediately before + // Add a NOP to ensure we don抰 have a flash read immediately before // the EPI read. // NOP @@ -364,7 +364,7 @@ EPIWorkaroundWordRead(uint32_t *pui32Addr) __asm { // - // Add a NOP to ensure we dont have a flash read immediately before + // Add a NOP to ensure we don抰 have a flash read immediately before // the EPI read. // NOP @@ -392,7 +392,7 @@ EPIWorkaroundHWordWrite(uint16_t *pui16Addr, uint16_t ui16Value) __asm { // - // Add a NOP to ensure we dont have a flash read immediately before + // Add a NOP to ensure we don抰 have a flash read immediately before // the EPI read. // NOP @@ -419,7 +419,7 @@ EPIWorkaroundHWordRead(uint16_t *pui16Addr) __asm { // - // Add a NOP to ensure we dont have a flash read immediately before + // Add a NOP to ensure we don抰 have a flash read immediately before // the EPI read. // NOP @@ -447,7 +447,7 @@ EPIWorkaroundByteWrite(uint8_t *pui8Addr, uint8_t ui8Value) __asm { // - // Add a NOP to ensure we dont have a flash read immediately before + // Add a NOP to ensure we don抰 have a flash read immediately before // the EPI read. // NOP @@ -474,7 +474,7 @@ EPIWorkaroundByteRead(uint8_t *pui8Addr) __asm { // - // Add a NOP to ensure we dont have a flash read immediately before + // Add a NOP to ensure we don抰 have a flash read immediately before // the EPI read. // NOP @@ -525,7 +525,7 @@ EPIWorkaroundWordWrite(uint32_t *pui32Addr, uint32_t ui32Value) __asm volatile ( // - // Add a NOP to ensure we dont have a flash read immediately before + // Add a NOP to ensure we don抰 have a flash read immediately before // the EPI read. // " NOP\n" @@ -553,7 +553,7 @@ EPIWorkaroundWordRead(uint32_t *pui32Addr) __asm volatile( // - // Add a NOP to ensure we dont have a flash read immediately before + // Add a NOP to ensure we don抰 have a flash read immediately before // the EPI read. // " NOP\n" @@ -580,7 +580,7 @@ EPIWorkaroundHWordWrite(uint16_t *pui16Addr, uint16_t ui16Value) __asm volatile ( // - // Add a NOP to ensure we dont have a flash read immediately before + // Add a NOP to ensure we don抰 have a flash read immediately before // the EPI read. // " NOP\n" @@ -610,7 +610,7 @@ EPIWorkaroundHWordRead(uint16_t *pui16Addr) __asm volatile( // - // Add a NOP to ensure we dont have a flash read immediately before + // Add a NOP to ensure we don抰 have a flash read immediately before // the EPI read. // " NOP\n" @@ -636,7 +636,7 @@ EPIWorkaroundByteWrite(uint8_t *pui8Addr, uint8_t ui8Value) __asm volatile ( // - // Add a NOP to ensure we dont have a flash read immediately before + // Add a NOP to ensure we don抰 have a flash read immediately before // the EPI read. // " NOP\n" @@ -665,7 +665,7 @@ EPIWorkaroundByteRead(uint8_t *pui8Addr) __asm volatile( // - // Add a NOP to ensure we dont have a flash read immediately before + // Add a NOP to ensure we don抰 have a flash read immediately before // the EPI read. // " NOP\n" diff --git a/bsp/tm4c129x/libraries/driverlib/flash.c b/bsp/tm4c129x/libraries/driverlib/flash.c index 158176a766..b12887e541 100644 --- a/bsp/tm4c129x/libraries/driverlib/flash.c +++ b/bsp/tm4c129x/libraries/driverlib/flash.c @@ -2,25 +2,25 @@ // // flash.c - Driver for programming the on-chip flash. // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/flash.h b/bsp/tm4c129x/libraries/driverlib/flash.h index 0d20ab1c48..c36cfc18c4 100644 --- a/bsp/tm4c129x/libraries/driverlib/flash.h +++ b/bsp/tm4c129x/libraries/driverlib/flash.h @@ -2,25 +2,25 @@ // // flash.h - Prototypes for the flash driver. // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/fpu.c b/bsp/tm4c129x/libraries/driverlib/fpu.c index 8e0d793da6..027323a014 100644 --- a/bsp/tm4c129x/libraries/driverlib/fpu.c +++ b/bsp/tm4c129x/libraries/driverlib/fpu.c @@ -3,25 +3,25 @@ // fpu.c - Routines for manipulating the floating-point unit in the Cortex-M // processor. // -// Copyright (c) 2011-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2011-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -33,8 +33,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/fpu.h b/bsp/tm4c129x/libraries/driverlib/fpu.h index c96d69a734..3e5ec4c60f 100644 --- a/bsp/tm4c129x/libraries/driverlib/fpu.h +++ b/bsp/tm4c129x/libraries/driverlib/fpu.h @@ -2,25 +2,25 @@ // // fpu.h - Prototypes for the floatint point manipulation routines. // -// Copyright (c) 2011-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2011-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/gpio.c b/bsp/tm4c129x/libraries/driverlib/gpio.c index 5e55dd7f1c..9e186e31bd 100644 --- a/bsp/tm4c129x/libraries/driverlib/gpio.c +++ b/bsp/tm4c129x/libraries/driverlib/gpio.c @@ -2,25 +2,25 @@ // // gpio.c - API for GPIO ports // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -479,8 +479,9 @@ GPIOIntTypeGet(uint32_t ui32Port, uint8_t ui8Pin) ui32IS = HWREG(ui32Port + GPIO_O_IS); ui32IEV = HWREG(ui32Port + GPIO_O_IEV); ui32SI = HWREG(ui32Port + GPIO_O_SI); + return(((ui32IBE & ui8Pin) ? 1 : 0) | ((ui32IS & ui8Pin) ? 2 : 0) | - ((ui32IEV & ui8Pin) ? 4 : 0) | (ui32SI & 0x01) ? 0x10000 : 0); + ((ui32IEV & ui8Pin) ? 4 : 0) | ((ui32SI & 0x01) ? 0x10000 : 0)); } //***************************************************************************** @@ -573,21 +574,22 @@ GPIOPadConfigSet(uint32_t ui32Port, uint8_t ui8Pins, (ui32PinType == GPIO_PIN_TYPE_WAKE_HIGH) || (ui32PinType == GPIO_PIN_TYPE_ANALOG)); - - // - // Set the GPIO peripheral configuration register first as required. This - // register only appears in TM4E111 and later device classes, but is a - // harmless write on older devices. Walk pins 0-7 and clear or set the - // provided PC[EDMn] encoding. - // - for(ui8Bit = 0; ui8Bit < 8; ui8Bit++) + if (!(CLASS_IS_TM4C123)) { - if(ui8Pins & (1 << ui8Bit)) + // + // Set the GPIO peripheral configuration register first as required. + // This register only appears in TM4C129x devices, but is a harmless + // write on older devices. + // + for(ui8Bit = 0; ui8Bit < 8; ui8Bit++) { - HWREG(ui32Port + GPIO_O_PC) = (HWREG(ui32Port + GPIO_O_PC) & - ~(0x3 << (2 * ui8Bit))); - HWREG(ui32Port + GPIO_O_PC) |= (((ui32Strength >> 5) & 0x3) << - (2 * ui8Bit)); + if(ui8Pins & (1 << ui8Bit)) + { + HWREG(ui32Port + GPIO_O_PC) = (HWREG(ui32Port + GPIO_O_PC) & + ~(0x3 << (2 * ui8Bit))); + HWREG(ui32Port + GPIO_O_PC) |= (((ui32Strength >> 5) & 0x3) << + (2 * ui8Bit)); + } } } @@ -615,56 +617,62 @@ GPIOPadConfigSet(uint32_t ui32Port, uint8_t ui8Pins, (HWREG(ui32Port + GPIO_O_SLR) & ~(ui8Pins))); - // - // Set the 12-mA drive select register. This register only appears in - // TM4E111 and later device classes, but is a harmless write on older - // devices. - // - HWREG(ui32Port + GPIO_O_DR12R) = ((ui32Strength & 0x10) ? - (HWREG(ui32Port + GPIO_O_DR12R) | - ui8Pins) : - (HWREG(ui32Port + GPIO_O_DR12R) & - ~(ui8Pins))); + if (!(CLASS_IS_TM4C123)) + { + // + // Set the 12-mA drive select register. This register only appears in + // TM4C129x and later device classes, but is a harmless write on older + // devices. + // + HWREG(ui32Port + GPIO_O_DR12R) = ((ui32Strength & 0x10) ? + (HWREG(ui32Port + GPIO_O_DR12R) | + ui8Pins) : + (HWREG(ui32Port + GPIO_O_DR12R) & + ~(ui8Pins))); + } // // Set the pin type. // HWREG(ui32Port + GPIO_O_ODR) = ((ui32PinType & 1) ? - (HWREG(ui32Port + GPIO_O_ODR) | ui8Pins) : - (HWREG(ui32Port + GPIO_O_ODR) & ~(ui8Pins))); + (HWREG(ui32Port + GPIO_O_ODR) | ui8Pins) : + (HWREG(ui32Port + GPIO_O_ODR) & ~(ui8Pins))); HWREG(ui32Port + GPIO_O_PUR) = ((ui32PinType & 2) ? - (HWREG(ui32Port + GPIO_O_PUR) | ui8Pins) : - (HWREG(ui32Port + GPIO_O_PUR) & ~(ui8Pins))); + (HWREG(ui32Port + GPIO_O_PUR) | ui8Pins) : + (HWREG(ui32Port + GPIO_O_PUR) & ~(ui8Pins))); HWREG(ui32Port + GPIO_O_PDR) = ((ui32PinType & 4) ? - (HWREG(ui32Port + GPIO_O_PDR) | ui8Pins) : - (HWREG(ui32Port + GPIO_O_PDR) & ~(ui8Pins))); + (HWREG(ui32Port + GPIO_O_PDR) | ui8Pins) : + (HWREG(ui32Port + GPIO_O_PDR) & ~(ui8Pins))); HWREG(ui32Port + GPIO_O_DEN) = ((ui32PinType & 8) ? - (HWREG(ui32Port + GPIO_O_DEN) | ui8Pins) : - (HWREG(ui32Port + GPIO_O_DEN) & ~(ui8Pins))); + (HWREG(ui32Port + GPIO_O_DEN) | ui8Pins) : + (HWREG(ui32Port + GPIO_O_DEN) & ~(ui8Pins))); - // - // Set the wake pin enable register and the wake level register. These - // registers only appear in TM4E111 and later device classes, but are - // harmless writes on older devices. - // - HWREG(ui32Port + GPIO_O_WAKELVL) = ((ui32PinType & 0x200) ? - (HWREG(ui32Port + GPIO_O_WAKELVL) | - ui8Pins) : - (HWREG(ui32Port + GPIO_O_WAKELVL) & - ~(ui8Pins))); - HWREG(ui32Port + GPIO_O_WAKEPEN) = ((ui32PinType & 0x300) ? - (HWREG(ui32Port + GPIO_O_WAKEPEN) | - ui8Pins) : - (HWREG(ui32Port + GPIO_O_WAKEPEN) & - ~(ui8Pins))); + if (!(CLASS_IS_TM4C123)) + { + // + // Set the wake pin enable register and the wake level register. These + // registers only appear in TM4C129x and later device classes, but are + // harmless writes on older devices. + // + HWREG(ui32Port + GPIO_O_WAKELVL) = ((ui32PinType & 0x200) ? + (HWREG(ui32Port + GPIO_O_WAKELVL) | + ui8Pins) : + (HWREG(ui32Port + GPIO_O_WAKELVL) & + ~(ui8Pins))); + HWREG(ui32Port + GPIO_O_WAKEPEN) = ((ui32PinType & 0x300) ? + (HWREG(ui32Port + GPIO_O_WAKEPEN) | + ui8Pins) : + (HWREG(ui32Port + GPIO_O_WAKEPEN) & + ~(ui8Pins))); + } // // Set the analog mode select register. // HWREG(ui32Port + GPIO_O_AMSEL) = - ((ui32PinType == GPIO_PIN_TYPE_ANALOG) ? - (HWREG(ui32Port + GPIO_O_AMSEL) | ui8Pins) : - (HWREG(ui32Port + GPIO_O_AMSEL) & ~(ui8Pins))); + ((ui32PinType == GPIO_PIN_TYPE_ANALOG) ? + (HWREG(ui32Port + GPIO_O_AMSEL) | ui8Pins) : + (HWREG(ui32Port + GPIO_O_AMSEL) & ~(ui8Pins))); } //***************************************************************************** @@ -710,9 +718,12 @@ GPIOPadConfigGet(uint32_t ui32Port, uint8_t ui8Pin, ui32Strength |= ((HWREG(ui32Port + GPIO_O_DR4R) & ui8Pin) ? 2 : 0); ui32Strength |= ((HWREG(ui32Port + GPIO_O_DR8R) & ui8Pin) ? 4 : 0); ui32Strength |= ((HWREG(ui32Port + GPIO_O_SLR) & ui8Pin) ? 8 : 0); - ui32Strength |= ((HWREG(ui32Port + GPIO_O_DR12R) & ui8Pin) ? 0x10 : 0); - ui32Strength |= (((HWREG(ui32Port + GPIO_O_PC) >> - (2 * ui8Pin)) & 0x3) << 5); + if (!(CLASS_IS_TM4C123)) + { + ui32Strength |= ((HWREG(ui32Port + GPIO_O_DR12R) & ui8Pin) ? 0x10 : 0); + ui32Strength |= (((HWREG(ui32Port + GPIO_O_PC) >> + (2 * ui8Pin)) & 0x3) << 5); + } *pui32Strength = ui32Strength; // @@ -722,10 +733,13 @@ GPIOPadConfigGet(uint32_t ui32Port, uint8_t ui8Pin, ui32PinType |= ((HWREG(ui32Port + GPIO_O_PUR) & ui8Pin) ? 2 : 0); ui32PinType |= ((HWREG(ui32Port + GPIO_O_PDR) & ui8Pin) ? 4 : 0); ui32PinType |= ((HWREG(ui32Port + GPIO_O_DEN) & ui8Pin) ? 8 : 0); - if(HWREG(ui32Port + GPIO_O_WAKEPEN) & ui8Pin) + if (!(CLASS_IS_TM4C123)) { - ui32PinType |= ((HWREG(ui32Port + GPIO_O_WAKELVL) & ui8Pin) ? - 0x200 : 0x100); + if(HWREG(ui32Port + GPIO_O_WAKEPEN) & ui8Pin) + { + ui32PinType |= ((HWREG(ui32Port + GPIO_O_WAKELVL) & ui8Pin) ? + 0x200 : 0x100); + } } *pui32PinType = ui32PinType; } @@ -2614,6 +2628,41 @@ GPIOADCTriggerDisable(uint32_t ui32Port, uint8_t ui8Pins) HWREG(ui32Port + GPIO_O_ADCCTL) &= (~ui8Pins); } +//***************************************************************************** +// +//! Unlocks a GPIO pin which had been previously locked. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui8Pins is the bit-packed representation of the pin(s). +//! +//! This function is used to unlock pins which were locked for specific +//! functionality such as JTAG operation. To be able to use pins which have +//! been locked, the following procedure is required to unlock the pin and +//! commit the change. This function will have no effect on pins which are +//! not protected by the GPIOCR register. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOUnlockPin(uint32_t ui32Port, uint8_t ui8Pins) +{ + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + // + // Unlock the port by using the device LOCK key + // + HWREG(ui32Port + GPIO_O_LOCK) = GPIO_LOCK_KEY; + + // + // Commit the pin to keep it in GPIO mode + // + HWREG(ui32Port + GPIO_O_CR) |= ui8Pins; +} + //***************************************************************************** // // Close the Doxygen group. diff --git a/bsp/tm4c129x/libraries/driverlib/gpio.h b/bsp/tm4c129x/libraries/driverlib/gpio.h index 47b0dd71b4..fc7e54278f 100644 --- a/bsp/tm4c129x/libraries/driverlib/gpio.h +++ b/bsp/tm4c129x/libraries/driverlib/gpio.h @@ -2,25 +2,25 @@ // // gpio.h - Defines and Macros for GPIO API. // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -191,6 +191,7 @@ extern void GPIODMATriggerEnable(uint32_t ui32Port, uint8_t ui8Pins); extern void GPIODMATriggerDisable(uint32_t ui32Port, uint8_t ui8Pins); extern void GPIOADCTriggerEnable(uint32_t ui32Port, uint8_t ui8Pins); extern void GPIOADCTriggerDisable(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOUnlockPin(uint32_t ui32Port, uint8_t ui8Pins); //***************************************************************************** // diff --git a/bsp/tm4c129x/libraries/driverlib/hibernate.c b/bsp/tm4c129x/libraries/driverlib/hibernate.c index a371578387..8cb6ba5eca 100644 --- a/bsp/tm4c129x/libraries/driverlib/hibernate.c +++ b/bsp/tm4c129x/libraries/driverlib/hibernate.c @@ -2,25 +2,25 @@ // // hibernate.c - Driver for the Hibernation module // -// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2007-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -128,7 +128,7 @@ _HibernateWriteComplete(void) //! the system clock is the value returned by SysCtlClockGet() for TM4C123x //! devices or the value returned by SysCtlClockFreqSet() for TM4C129x devices, //! or it can be explicitly hard coded if it is constant and known (to save the -//! code/execution overhead of a call to SysCtlClockGet() or fetch of the +//! code/execution overhead of a call to SysCtlClockGet() or fetch of the //! variable call holding the return value of SysCtlClockFreqSet()). //! //! \return None. @@ -272,8 +272,7 @@ HibernateClockConfig(uint32_t ui32Config) // if(HIBERNATE_CLOCK_OUTPUT) { - HWREG(HIB_CC) = ui32Config & (HIBERNATE_OUT_SYSCLK | - HIBERNATE_OUT_ALT1CLK); + HWREG(HIB_CC) = ui32Config & (HIBERNATE_OUT_SYSCLK); } } @@ -1615,6 +1614,12 @@ _HibernateCalendarSet(uint32_t ui32Reg, struct tm *psTime) //! the hibernate counter is configured in calendar mode using the //! HibernateCounterMode() function with one of the calendar modes. //! +//! The hibernate module contains a 7-bit register field to store the year with +//! valid values ranges from 0 to 99. In order to maximize the calendar +//! year up to 2099, the HibernateCalendarSet() will accept calendar year +//! after the year 2000 only. Calendar years before 2000 (i.e. 1987) will +//! produce unexpected results. +//! //! \note The hibernate calendar mode is not available on all Tiva //! devices. Please consult the data sheet to determine if the device you are //! using supports this feature in the Hibernation module. diff --git a/bsp/tm4c129x/libraries/driverlib/hibernate.h b/bsp/tm4c129x/libraries/driverlib/hibernate.h index 80633b950c..b8082d86c1 100644 --- a/bsp/tm4c129x/libraries/driverlib/hibernate.h +++ b/bsp/tm4c129x/libraries/driverlib/hibernate.h @@ -2,25 +2,25 @@ // // hibernate.h - API definition for the Hibernation module. // -// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2007-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -104,7 +104,6 @@ extern "C" #define HIBERNATE_OSC_DISABLE 0x00010000 #define HIBERNATE_OUT_WRSTALL 0x20000000 #define HIBERNATE_OUT_SYSCLK 0x00000001 -#define HIBERNATE_OUT_ALT1CLK 0x00000002 //***************************************************************************** // diff --git a/bsp/tm4c129x/libraries/driverlib/i2c.c b/bsp/tm4c129x/libraries/driverlib/i2c.c index 37aa1d764b..f8da84cce4 100644 --- a/bsp/tm4c129x/libraries/driverlib/i2c.c +++ b/bsp/tm4c129x/libraries/driverlib/i2c.c @@ -2,25 +2,25 @@ // // i2c.c - Driver for Inter-IC (I2C) bus block. // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -194,7 +194,7 @@ _I2CIntNumberGet(uint32_t ui32Base) //! the system clock is the value returned by SysCtlClockGet() for TM4C123x //! devices or the value returned by SysCtlClockFreqSet() for TM4C129x devices, //! or it can be explicitly hard coded if it is constant and known (to save the -//! code/execution overhead of a call to SysCtlClockGet() or fetch of the +//! code/execution overhead of a call to SysCtlClockGet() or fetch of the //! variable call holding the return value of SysCtlClockFreqSet()). //! //! \return None. @@ -1782,7 +1782,7 @@ I2CRxFIFOFlush(uint32_t ui32Base) //! //! This function retrieves the status for both the transmit (TX) and receive //! (RX) FIFOs. The trigger level for the transmit FIFO is set using -//! I2CTxFIFOConfigSet() and for the receive FIFO using I2CTxFIFOConfigSet(). +//! I2CTxFIFOConfigSet() and for the receive FIFO using I2CRxFIFOConfigSet(). //! //! \note Not all Tiva devices have an I2C FIFO. Please consult the //! device data sheet to determine if this feature is supported. diff --git a/bsp/tm4c129x/libraries/driverlib/i2c.h b/bsp/tm4c129x/libraries/driverlib/i2c.h index ab7b44e4fe..709930af08 100644 --- a/bsp/tm4c129x/libraries/driverlib/i2c.h +++ b/bsp/tm4c129x/libraries/driverlib/i2c.h @@ -2,25 +2,25 @@ // // i2c.h - Prototypes for the I2C Driver. // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/interrupt.c b/bsp/tm4c129x/libraries/driverlib/interrupt.c index ebf5f95bd3..12d9686ebe 100644 --- a/bsp/tm4c129x/libraries/driverlib/interrupt.c +++ b/bsp/tm4c129x/libraries/driverlib/interrupt.c @@ -2,25 +2,25 @@ // // interrupt.c - Driver for the NVIC Interrupt Controller. // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/interrupt.h b/bsp/tm4c129x/libraries/driverlib/interrupt.h index effb30c88a..79d457ead2 100644 --- a/bsp/tm4c129x/libraries/driverlib/interrupt.h +++ b/bsp/tm4c129x/libraries/driverlib/interrupt.h @@ -2,25 +2,25 @@ // // interrupt.h - Prototypes for the NVIC Interrupt Controller Driver. // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/lcd.c b/bsp/tm4c129x/libraries/driverlib/lcd.c index 195d0ef0ba..e14340463a 100644 --- a/bsp/tm4c129x/libraries/driverlib/lcd.c +++ b/bsp/tm4c129x/libraries/driverlib/lcd.c @@ -2,25 +2,25 @@ // // lcd.c - Defines and Macros for the LCD Controller module. // -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2012-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/lcd.h b/bsp/tm4c129x/libraries/driverlib/lcd.h index 766cf94361..1df72f19cf 100644 --- a/bsp/tm4c129x/libraries/driverlib/lcd.h +++ b/bsp/tm4c129x/libraries/driverlib/lcd.h @@ -2,25 +2,25 @@ // // lcd.h - Defines and Macros for the LCD Controller module. // -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2012-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/mpu.c b/bsp/tm4c129x/libraries/driverlib/mpu.c index 4d01f1b403..42c093e964 100644 --- a/bsp/tm4c129x/libraries/driverlib/mpu.c +++ b/bsp/tm4c129x/libraries/driverlib/mpu.c @@ -2,25 +2,25 @@ // // mpu.c - Driver for the Cortex-M3 memory protection unit (MPU). // -// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2007-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/mpu.h b/bsp/tm4c129x/libraries/driverlib/mpu.h index 9c8377f8ce..5fa8ad3645 100644 --- a/bsp/tm4c129x/libraries/driverlib/mpu.h +++ b/bsp/tm4c129x/libraries/driverlib/mpu.h @@ -2,25 +2,25 @@ // // mpu.h - Defines and Macros for the memory protection unit. // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/onewire.c b/bsp/tm4c129x/libraries/driverlib/onewire.c index 24d671f125..09f8ef1e66 100644 --- a/bsp/tm4c129x/libraries/driverlib/onewire.c +++ b/bsp/tm4c129x/libraries/driverlib/onewire.c @@ -2,25 +2,25 @@ // // onewire.c - Driver for OneWire master module. // -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2012-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/onewire.h b/bsp/tm4c129x/libraries/driverlib/onewire.h index 731f3f99bb..f2ba6e70e6 100644 --- a/bsp/tm4c129x/libraries/driverlib/onewire.h +++ b/bsp/tm4c129x/libraries/driverlib/onewire.h @@ -2,25 +2,25 @@ // // onewire.h - Prototypes for the OneWire Driver. // -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2012-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/pin_map.h b/bsp/tm4c129x/libraries/driverlib/pin_map.h index 9d68609861..8f8f9dee1b 100644 --- a/bsp/tm4c129x/libraries/driverlib/pin_map.h +++ b/bsp/tm4c129x/libraries/driverlib/pin_map.h @@ -2,25 +2,25 @@ // // pin_map.h - Mapping of peripherals to pins for all parts. // -// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2007-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/pwm.c b/bsp/tm4c129x/libraries/driverlib/pwm.c index 54fbe52e5c..fdbec4e959 100644 --- a/bsp/tm4c129x/libraries/driverlib/pwm.c +++ b/bsp/tm4c129x/libraries/driverlib/pwm.c @@ -2,25 +2,25 @@ // // pwm.c - API for the PWM modules // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -1624,11 +1624,11 @@ PWMIntStatus(uint32_t ui32Base, bool bMasked) //! \e ui32FaultInts must be the logical OR of any of \b PWM_INT_FAULT0, //! \b PWM_INT_FAULT1, \b PWM_INT_FAULT2, or \b PWM_INT_FAULT3. //! -//! The fault interrupts are derived by performing a logical OR of each of the +//! The fault interrupts are derived by performing a logical OR of each of the //! configured fault trigger signals for a given generator. Therefore, these -//! interrupts are not directly related to the four possible FAULTn inputs to -//! the device but indicate that a fault has been signaled to one of the four -//! possible PWM generators. +//! interrupts are not directly related to the four possible FAULTn inputs to +//! the device but indicate that a fault has been signaled to one of the four +//! possible PWM generators. //! //! \note Because there is a write buffer in the Cortex-M processor, it may //! take several clock cycles before the interrupt source is actually cleared. @@ -1993,7 +1993,8 @@ PWMClockSet(uint32_t ui32Base, uint32_t ui32Config) // Check the arguments. // ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT((ui32Config == PWM_SYSCLK_DIV_2) || + ASSERT((ui32Config == PWM_SYSCLK_DIV_1) || + (ui32Config == PWM_SYSCLK_DIV_2) || (ui32Config == PWM_SYSCLK_DIV_4) || (ui32Config == PWM_SYSCLK_DIV_8) || (ui32Config == PWM_SYSCLK_DIV_16) || diff --git a/bsp/tm4c129x/libraries/driverlib/pwm.h b/bsp/tm4c129x/libraries/driverlib/pwm.h index c18d98acb2..e11cd4be3c 100644 --- a/bsp/tm4c129x/libraries/driverlib/pwm.h +++ b/bsp/tm4c129x/libraries/driverlib/pwm.h @@ -2,25 +2,25 @@ // // pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/qei.c b/bsp/tm4c129x/libraries/driverlib/qei.c index b4def78493..a1b0f03e61 100644 --- a/bsp/tm4c129x/libraries/driverlib/qei.c +++ b/bsp/tm4c129x/libraries/driverlib/qei.c @@ -2,25 +2,25 @@ // // qei.c - Driver for the Quadrature Encoder with Index. // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/qei.h b/bsp/tm4c129x/libraries/driverlib/qei.h index 031897ae31..4b8794d8dd 100644 --- a/bsp/tm4c129x/libraries/driverlib/qei.h +++ b/bsp/tm4c129x/libraries/driverlib/qei.h @@ -2,25 +2,25 @@ // // qei.h - Prototypes for the Quadrature Encoder Driver. // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/readme.txt b/bsp/tm4c129x/libraries/driverlib/readme.txt index 1f90c23656..482941f98b 100644 --- a/bsp/tm4c129x/libraries/driverlib/readme.txt +++ b/bsp/tm4c129x/libraries/driverlib/readme.txt @@ -2,7 +2,7 @@ This project will build the TivaWare Peripheral Driver Library. ------------------------------------------------------------------------------- -Copyright (c) 2006-2017 Texas Instruments Incorporated. All rights reserved. +Copyright (c) 2006-2020 Texas Instruments Incorporated. All rights reserved. Software License Agreement Redistribution and use in source and binary forms, with or without @@ -14,7 +14,7 @@ Software License Agreement Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the + documentation and/or other materials provided with the distribution. Neither the name of Texas Instruments Incorporated nor the names of @@ -33,4 +33,4 @@ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. diff --git a/bsp/tm4c129x/libraries/driverlib/rom.h b/bsp/tm4c129x/libraries/driverlib/rom.h index 2ffdab87e5..1997e841fa 100644 --- a/bsp/tm4c129x/libraries/driverlib/rom.h +++ b/bsp/tm4c129x/libraries/driverlib/rom.h @@ -2,25 +2,25 @@ // // rom.h - Macros to facilitate calling functions in the ROM. // -// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2007-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/rom_map.h b/bsp/tm4c129x/libraries/driverlib/rom_map.h index e45ede445f..2a2ea9d3fd 100644 --- a/bsp/tm4c129x/libraries/driverlib/rom_map.h +++ b/bsp/tm4c129x/libraries/driverlib/rom_map.h @@ -3,25 +3,25 @@ // rom_map.h - Macros to facilitate calling functions in the ROM when they are // available and in flash otherwise. // -// Copyright (c) 2008-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2008-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -33,8 +33,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -1703,6 +1703,20 @@ #define MAP_FlashUserSet \ FlashUserSet #endif +#ifdef ROM_FlashAllUserRegisterGet +#define MAP_FlashAllUserRegisterGet \ + ROM_FlashAllUserRegisterGet +#else +#define MAP_FlashAllUserRegisterGet \ + FlashAllUserRegisterGet +#endif +#ifdef ROM_FlashAllUserRegisterSet +#define MAP_FlashAllUserRegisterSet \ + ROM_FlashAllUserRegisterSet +#else +#define MAP_FlashAllUserRegisterSet \ + FlashAllUserRegisterSet +#endif #ifdef ROM_FlashUserSave #define MAP_FlashUserSave \ ROM_FlashUserSave @@ -1710,6 +1724,13 @@ #define MAP_FlashUserSave \ FlashUserSave #endif +#ifdef ROM_FlashAllUserRegisterSave +#define MAP_FlashAllUserRegisterSave \ + ROM_FlashAllUserRegisterSave +#else +#define MAP_FlashAllUserRegisterSave \ + FlashAllUserRegisterSave +#endif #ifdef ROM_FlashIntEnable #define MAP_FlashIntEnable \ ROM_FlashIntEnable @@ -1883,6 +1904,41 @@ #define MAP_GPIOPinTypeComparator \ GPIOPinTypeComparator #endif +#ifdef ROM_GPIOPinTypeComparatorOutput +#define MAP_GPIOPinTypeComparatorOutput \ + ROM_GPIOPinTypeComparatorOutput +#else +#define MAP_GPIOPinTypeComparatorOutput \ + GPIOPinTypeComparatorOutput +#endif +#ifdef ROM_GPIOPinTypeDIVSCLK +#define MAP_GPIOPinTypeDIVSCLK \ + ROM_GPIOPinTypeDIVSCLK +#else +#define MAP_GPIOPinTypeDIVSCLK \ + GPIOPinTypeDIVSCLK +#endif +#ifdef ROM_GPIOPinTypeEPI +#define MAP_GPIOPinTypeEPI \ + ROM_GPIOPinTypeEPI +#else +#define MAP_GPIOPinTypeEPI \ + GPIOPinTypeEPI +#endif +#ifdef ROM_GPIOPinTypeEthernetLED +#define MAP_GPIOPinTypeEthernetLED \ + ROM_GPIOPinTypeEthernetLED +#else +#define MAP_GPIOPinTypeEthernetLED \ + GPIOPinTypeEthernetLED +#endif +#ifdef ROM_GPIOPinTypeEthernetMII +#define MAP_GPIOPinTypeEthernetMII \ + ROM_GPIOPinTypeEthernetMII +#else +#define MAP_GPIOPinTypeEthernetMII \ + GPIOPinTypeEthernetMII +#endif #ifdef ROM_GPIOPinTypeGPIOInput #define MAP_GPIOPinTypeGPIOInput \ ROM_GPIOPinTypeGPIOInput @@ -1897,6 +1953,13 @@ #define MAP_GPIOPinTypeGPIOOutput \ GPIOPinTypeGPIOOutput #endif +#ifdef ROM_GPIOPinTypeHibernateRTCCLK +#define MAP_GPIOPinTypeHibernateRTCCLK \ + ROM_GPIOPinTypeHibernateRTCCLK +#else +#define MAP_GPIOPinTypeHibernateRTCCLK \ + GPIOPinTypeHibernateRTCCLK +#endif #ifdef ROM_GPIOPinTypeI2C #define MAP_GPIOPinTypeI2C \ ROM_GPIOPinTypeI2C @@ -1932,6 +1995,13 @@ #define MAP_GPIOPinTypeTimer \ GPIOPinTypeTimer #endif +#ifdef ROM_GPIOPinTypeTrace +#define MAP_GPIOPinTypeTrace \ + ROM_GPIOPinTypeTrace +#else +#define MAP_GPIOPinTypeTrace \ + GPIOPinTypeTrace +#endif #ifdef ROM_GPIOPinTypeUART #define MAP_GPIOPinTypeUART \ ROM_GPIOPinTypeUART @@ -2058,6 +2128,34 @@ #define MAP_GPIOIntStatus \ GPIOIntStatus #endif +#ifdef ROM_GPIOIntRegister +#define MAP_GPIOIntRegiste \ + ROM_GPIOIntRegister +#else +#define MAP_GPIOIntRegister \ + GPIOIntRegister +#endif +#ifdef ROM_GPIOIntUnregister +#define MAP_GPIOIntUnregister \ + ROM_GPIOIntUnregister +#else +#define MAP_GPIOIntUnregister \ + GPIOIntUnregister +#endif +#ifdef ROM_GPIOIntRegisterPin +#define MAP_GPIOIntRegisterPin \ + ROM_GPIOIntRegisterPin +#else +#define MAP_GPIOIntRegisterPin \ + GPIOIntRegisterPin +#endif +#ifdef ROM_GPIOIntUnregisterPin +#define MAP_GPIOIntUnregisterPin \ + ROM_GPIOIntUnregisterPin +#else +#define MAP_GPIOIntUnregisterPin \ + GPIOIntUnregisterPin +#endif #ifdef ROM_GPIOPinWakeStatus #define MAP_GPIOPinWakeStatus \ ROM_GPIOPinWakeStatus @@ -2065,6 +2163,13 @@ #define MAP_GPIOPinWakeStatus \ GPIOPinWakeStatus #endif +#ifdef ROM_GPIOUnlockPin +#define MAP_GPIOUnlockPin \ + ROM_GPIOUnlockPin +#else +#define MAP_GPIOUnlockPin \ + GPIOUnlockPin +#endif //***************************************************************************** // @@ -2756,6 +2861,13 @@ #define MAP_I2CMasterGlitchFilterConfigSet \ I2CMasterGlitchFilterConfigSet #endif +#ifdef ROM_I2CLoopbackEnable +#define MAP_I2CLoopbackEnable \ + ROM_I2CLoopbackEnable +#else +#define MAP_I2CLoopbackEnable \ + I2CLoopbackEnable +#endif //***************************************************************************** // @@ -3492,6 +3604,27 @@ #define MAP_QEIErrorGet \ QEIErrorGet #endif +#ifdef ROM_QEIFilterEnable +#define MAP_QEIFilterEnable \ + ROM_QEIFilterEnable +#else +#define MAP_QEIFilterEnable \ + QEIFilterEnable +#endif +#ifdef ROM_QEIFilterDisable +#define MAP_QEIFilterDisable \ + ROM_QEIFilterDisable +#else +#define MAP_QEIFilterDisable \ + QEIFilterDisable +#endif +#ifdef ROM_QEIFilterConfigure +#define MAP_QEIFilterConfigure \ + ROM_QEIFilterConfigure +#else +#define MAP_QEIFilterConfigure \ + QEIFilterConfigure +#endif #ifdef ROM_QEIVelocityEnable #define MAP_QEIVelocityEnable \ ROM_QEIVelocityEnable @@ -4405,6 +4538,20 @@ #define MAP_SSIAdvFrameHoldDisable \ SSIAdvFrameHoldDisable #endif +#ifdef ROM_SSILoopbackEnable +#define MAP_SSILoopbackEnable \ + ROM_SSILoopbackEnable +#else +#define MAP_SSILoopbackEnable \ + SSILoopbackEnable +#endif +#ifdef ROM_SSILoopbackDisable +#define MAP_SSILoopbackDisable \ + ROM_SSILoopbackDisable +#else +#define MAP_SSILoopbackDisable \ + SSILoopbackDisable +#endif //***************************************************************************** // @@ -4726,6 +4873,13 @@ #define MAP_SysCtlAltClkConfig \ SysCtlAltClkConfig #endif +#ifdef ROM_SysCtlVCOGet +#define MAP_SysCtlVCOGet \ + ROM_SysCtlVCOGet +#else +#define MAP_SysCtlVCOGet \ + SysCtlVCOGet +#endif //***************************************************************************** // @@ -5066,6 +5220,13 @@ #define MAP_TimerSynchronize \ TimerSynchronize #endif +#ifdef ROM_TimerUpdateMode +#define MAP_TimerUpdateMode \ + ROM_TimerUpdateMode +#else +#define MAP_TimerUpdateMode \ + TimerUpdateMode +#endif //***************************************************************************** // @@ -5380,6 +5541,13 @@ #define MAP_UARTFlowControlSet \ UARTFlowControlSet #endif +#ifdef ROM_UARTLoopbackEnable +#define MAP_UARTLoopbackEnable \ + ROM_UARTLoopbackEnable +#else +#define MAP_UARTLoopbackEnable \ + UARTLoopbackEnable +#endif //***************************************************************************** // diff --git a/bsp/tm4c129x/libraries/driverlib/rtos_bindings.h b/bsp/tm4c129x/libraries/driverlib/rtos_bindings.h index 90762502c0..71c0cfaceb 100644 --- a/bsp/tm4c129x/libraries/driverlib/rtos_bindings.h +++ b/bsp/tm4c129x/libraries/driverlib/rtos_bindings.h @@ -3,25 +3,25 @@ // rtos_bindings.h - Macros intended to aid porting of TivaWare modules // for use with an RTOS. // -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2012-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -33,8 +33,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/shamd5.c b/bsp/tm4c129x/libraries/driverlib/shamd5.c index d748ac4bb5..e399699001 100644 --- a/bsp/tm4c129x/libraries/driverlib/shamd5.c +++ b/bsp/tm4c129x/libraries/driverlib/shamd5.c @@ -2,25 +2,25 @@ // // shamd5.c - Driver for the SHA/MD5 module. // -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2012-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/shamd5.h b/bsp/tm4c129x/libraries/driverlib/shamd5.h index 3b0e793b4f..b2b3cd0dbc 100644 --- a/bsp/tm4c129x/libraries/driverlib/shamd5.h +++ b/bsp/tm4c129x/libraries/driverlib/shamd5.h @@ -2,25 +2,25 @@ // // shamd5.h - Defines and Macros for the SHA/MD5. // -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2012-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/ssi.c b/bsp/tm4c129x/libraries/driverlib/ssi.c index cf7a2d3bc2..db200db903 100644 --- a/bsp/tm4c129x/libraries/driverlib/ssi.c +++ b/bsp/tm4c129x/libraries/driverlib/ssi.c @@ -2,25 +2,25 @@ // // ssi.c - Driver for Synchronous Serial Interface. // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -176,9 +176,9 @@ _SSIIntNumberGet(uint32_t ui32Base) //! The \e ui32Protocol parameter defines the data frame format. The //! \e ui32Protocol parameter can be one of the following values: //! \b SSI_FRF_MOTO_MODE_0, \b SSI_FRF_MOTO_MODE_1, \b SSI_FRF_MOTO_MODE_2, -//! \b SSI_FRF_MOTO_MODE_3, \b SSI_FRF_TI, or \b SSI_FRF_NMW. Note that +//! \b SSI_FRF_MOTO_MODE_3, \b SSI_FRF_TI, or \b SSI_FRF_NMW. Note that //! the \b SSI_FRF_NMW option is only available on some devices. Refer to the -//! device data sheet to determine if the Microwire format is supported on +//! device data sheet to determine if the Microwire format is supported on //! a particular device. The Motorola frame formats encode the following //! polarity and phase configurations: //! @@ -213,7 +213,7 @@ _SSIIntNumberGet(uint32_t ui32Base) //! the system clock is the value returned by SysCtlClockGet() for TM4C123x //! devices or the value returned by SysCtlClockFreqSet() for TM4C129x devices, //! or it can be explicitly hard coded if it is constant and known (to save the -//! code/execution overhead of a call to SysCtlClockGet() or fetch of the +//! code/execution overhead of a call to SysCtlClockGet() or fetch of the //! variable call holding the return value of SysCtlClockFreqSet()). //! //! \return None. @@ -692,10 +692,10 @@ SSIDataGet(uint32_t ui32Base, uint32_t *pui32Data) //! \param pui32Data is a pointer to a storage location for data that was //! received over the SSI interface. //! -//! This function gets received data from the receive FIFO of the specified SSI -//! module and places that data into the location specified by the \e ui32Data -//! parameter. If there is no data in the FIFO, then this function returns a -//! zero. +//! This function gets one received data element from the receive FIFO of the +//! specified SSI module and places that data into the location specified by +//! the \e ui32Data parameter. If there is no data in the FIFO, then this +//! function returns a zero. //! //! \note Only the lower N bits of the value written to \e pui32Data contain //! valid data, where N is the data width as configured by @@ -703,7 +703,7 @@ SSIDataGet(uint32_t ui32Base, uint32_t *pui32Data) //! 8-bit data width, only the lower 8 bits of the value written to //! \e pui32Data contain valid data. //! -//! \return Returns the number of elements read from the SSI receive FIFO. +//! \return Returns 1 if there is data element read or 0 if no data in FIFO // //***************************************************************************** int32_t @@ -1013,7 +1013,7 @@ SSIAdvDataPutFrameEnd(uint32_t ui32Base, uint32_t ui32Data) // Check the arguments. // ASSERT(_SSIBaseValid(ui32Base)); - ASSERT((ui32Data & 0xff) == 0); + ASSERT((ui32Data & 0xffffff00) == 0); // // Wait until there is space. @@ -1058,7 +1058,7 @@ SSIAdvDataPutFrameEndNonBlocking(uint32_t ui32Base, uint32_t ui32Data) // Check the arguments. // ASSERT(_SSIBaseValid(ui32Base)); - ASSERT((ui32Data & 0xff) == 0); + ASSERT((ui32Data & 0xffffff00) == 0); // // Check for space to write. @@ -1111,7 +1111,7 @@ SSIAdvFrameHoldEnable(uint32_t ui32Base) //***************************************************************************** // -//! Configures the SSI advanced mode to de-assert the SSIFss signal after every +//! Configures the SSI advanced mode to de-assert the SSIFss signal after every //! byte transfer. //! //! \param ui32Base is the base address of the SSI module. @@ -1142,6 +1142,61 @@ SSIAdvFrameHoldDisable(uint32_t ui32Base) HWREG(ui32Base + SSI_O_CR1) &= ~(SSI_CR1_FSSHLDFRM); } +//***************************************************************************** +// +//! Enables the use of SSI Loopback mode. +//! +//! \param ui32Base is the base address of the SSI module. +//! +//! This function configures the SSI module to enter loopback mode. When in +//! loopback mode, the output of the transmit serial shift register is +//! connected internally to the input of the receive serial shift register. +//! This mode is useful for diagnostic/debug testing of the SSI module. +//! +//! \return None. +// +//***************************************************************************** +void +SSILoopbackEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_SSIBaseValid(ui32Base)); + + // + // Enable Loopback mode + // + HWREG(ui32Base + SSI_O_CR1) |= 1u; +} + +//***************************************************************************** +// +//! Disables the use of SSI Loopback mode. +//! +//! \param ui32Base is the base address of the SSI module. +//! +//! This function restores the SSI module to be in normal serial port operation +//! where the the input of the receive serial shift register is no longer +//! connected internally to the output of the transmit serial shift register. +//! +//! \return None. +// +//***************************************************************************** +void +SSILoopbackDisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_SSIBaseValid(ui32Base)); + + // + // Disable Loopback mode + // + HWREG(ui32Base + SSI_O_CR1) &= ~(1u); +} + //***************************************************************************** // // Close the Doxygen group. diff --git a/bsp/tm4c129x/libraries/driverlib/ssi.h b/bsp/tm4c129x/libraries/driverlib/ssi.h index 37d928dd1b..64c18b0a17 100644 --- a/bsp/tm4c129x/libraries/driverlib/ssi.h +++ b/bsp/tm4c129x/libraries/driverlib/ssi.h @@ -2,25 +2,25 @@ // // ssi.h - Prototypes for the Synchronous Serial Interface Driver. // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -144,6 +144,8 @@ extern int32_t SSIAdvDataPutFrameEndNonBlocking(uint32_t ui32Base, uint32_t ui32Data); extern void SSIAdvFrameHoldEnable(uint32_t ui32Base); extern void SSIAdvFrameHoldDisable(uint32_t ui32Base); +extern void SSILoopbackEnable(uint32_t ui32Base); +extern void SSILoopbackDisable(uint32_t ui32Base); //***************************************************************************** // diff --git a/bsp/tm4c129x/libraries/driverlib/sw_crc.c b/bsp/tm4c129x/libraries/driverlib/sw_crc.c index 0706c34d50..fc48a53740 100644 --- a/bsp/tm4c129x/libraries/driverlib/sw_crc.c +++ b/bsp/tm4c129x/libraries/driverlib/sw_crc.c @@ -2,25 +2,25 @@ // // sw_crc.c - Software CRC functions. // -// Copyright (c) 2010-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2010-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/sw_crc.h b/bsp/tm4c129x/libraries/driverlib/sw_crc.h index 0e60775ffc..c3d319d7c5 100644 --- a/bsp/tm4c129x/libraries/driverlib/sw_crc.h +++ b/bsp/tm4c129x/libraries/driverlib/sw_crc.h @@ -2,25 +2,25 @@ // // sw_crc.h - Prototypes for the software CRC functions. // -// Copyright (c) 2010-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2010-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/sysctl.c b/bsp/tm4c129x/libraries/driverlib/sysctl.c index 161b5fa6d7..2cf594a167 100644 --- a/bsp/tm4c129x/libraries/driverlib/sysctl.c +++ b/bsp/tm4c129x/libraries/driverlib/sysctl.c @@ -2,25 +2,25 @@ // // sysctl.c - Driver for the system controller. // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -2216,7 +2216,7 @@ SysCtlClockFreqSet(uint32_t ui32Config, uint32_t ui32SysClock) } HWREG(SYSCTL_MOSCCTL) = ui32MOSCCTL; - + // // Timeout using the legacy delay value. // @@ -2241,7 +2241,7 @@ SysCtlClockFreqSet(uint32_t ui32Config, uint32_t ui32SysClock) return(0); } - + } else { @@ -2495,8 +2495,8 @@ SysCtlClockFreqSet(uint32_t ui32Config, uint32_t ui32SysClock) //! many of which are grouped into sets where only one can be chosen. //! //! The system clock divider is chosen with one of the following values: -//! \b SYSCTL_SYSDIV_1, \b SYSCTL_SYSDIV_2, \b SYSCTL_SYSDIV_3, ... -//! \b SYSCTL_SYSDIV_64. +//! \b SYSCTL_SYSDIV_1, \b SYSCTL_SYSDIV_2, \b SYSCTL_SYSDIV_2_5, +//! \b SYSCTL_SYSDIV_3, ... \b SYSCTL_SYSDIV_63_5, \b SYSCTL_SYSDIV_64. //! //! The use of the PLL is chosen with either \b SYSCTL_USE_PLL or //! \b SYSCTL_USE_OSC. @@ -3522,8 +3522,9 @@ SysCtlVoltageEventClear(uint32_t ui32Status) // //! Gets the effective VCO frequency. //! -//! \param ui32Crystal holds the crystal value used for the PLL. -//! \param pui32VCOFrequency is a pointer to the storage location which holds +//! \param ui32Crystal holds the crystal value definition from \b sysctl.h +//! such as \b SYSCTL_XTAL_25MHZ. +//! \param pui32VCOFrequency is a pointer to the storage location which holds //! value of the VCO computed. //! //! This function calculates the VCO of the PLL before the system divider is @@ -3566,9 +3567,9 @@ SysCtlVCOGet(uint32_t ui32Crystal, uint32_t *pui32VCOFrequency) // Return error if PLL is not used. // *pui32VCOFrequency = 0; - return(false); + return(false); } - + // // Get the index of the crystal from the ui32Config parameter. // @@ -3586,13 +3587,13 @@ SysCtlVCOGet(uint32_t ui32Crystal, uint32_t *pui32VCOFrequency) ui32PLLFreq0 = HWREG(SYSCTL_PLLFREQ0); ui32PLLFreq1 = HWREG(SYSCTL_PLLFREQ1); - ui32MInt = (ui32PLLFreq0 & SYSCTL_PLLFREQ0_MINT_M) >> + ui32MInt = (ui32PLLFreq0 & SYSCTL_PLLFREQ0_MINT_M) >> SYSCTL_PLLFREQ0_MINT_S; - ui32MFrac = (ui32PLLFreq0 & SYSCTL_PLLFREQ0_MFRAC_M) >> + ui32MFrac = (ui32PLLFreq0 & SYSCTL_PLLFREQ0_MFRAC_M) >> SYSCTL_PLLFREQ0_MFRAC_S; - ui32NDiv = (ui32PLLFreq1 & SYSCTL_PLLFREQ1_N_M) >> + ui32NDiv = (ui32PLLFreq1 & SYSCTL_PLLFREQ1_N_M) >> SYSCTL_PLLFREQ1_N_S; - ui32QDiv = (ui32PLLFreq1 & SYSCTL_PLLFREQ1_Q_M) >> + ui32QDiv = (ui32PLLFreq1 & SYSCTL_PLLFREQ1_Q_M) >> SYSCTL_PLLFREQ1_Q_S; // @@ -3600,7 +3601,7 @@ SysCtlVCOGet(uint32_t ui32Crystal, uint32_t *pui32VCOFrequency) // ui32TempVCO = (ui32Osc * ui32MInt) + ((ui32Osc * ui32MFrac) / 1024); ui32TempVCO /= ((ui32NDiv + 1) * (ui32QDiv + 1)); - + *pui32VCOFrequency = ui32TempVCO; return(true); } diff --git a/bsp/tm4c129x/libraries/driverlib/sysctl.h b/bsp/tm4c129x/libraries/driverlib/sysctl.h index 0bce4852d7..1f68c46e98 100644 --- a/bsp/tm4c129x/libraries/driverlib/sysctl.h +++ b/bsp/tm4c129x/libraries/driverlib/sysctl.h @@ -2,25 +2,25 @@ // // sysctl.h - Prototypes for the system control driver. // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -344,8 +344,23 @@ extern "C" #define SYSCTL_SYSDIV_61_5 0xDE800000 // Processor clock is pll / 61.5 #define SYSCTL_SYSDIV_62_5 0xDF000000 // Processor clock is pll / 62.5 #define SYSCTL_SYSDIV_63_5 0xDF800000 // Processor clock is pll / 63.5 -#define SYSCTL_CFG_VCO_480 0xF1000000 // VCO is 480 MHz -#define SYSCTL_CFG_VCO_320 0xF0000000 // VCO is 320 MHz +// +// TivaWare 2.2.0.xxx Update +// Due to TM4C129x Errata Item SYSCTL#22, the SYSCTL_CFG_VCO_xxx configurations +// have misleading *names* as currently defined as the VCO does not run at the +// stated frequencies. To amend this, new *name* defintions are being used, +// however the register configuration remains the same. +// The old definitions will remain for compatibility with code ported from +// older versions of TivaWare. +// +#define SYSCTL_CFG_VCO_480 0xF1000000 // VCO is 480 MHz - Legacy + // Does not work @ 480, use + // SYSCTL_CFG_VCO_240 instead +#define SYSCTL_CFG_VCO_320 0xF0000000 // VCO is 320 MHz - Legacy + // Does not work @ 320, use + // SYSCTL_CFG_VCO_160 instead +#define SYSCTL_CFG_VCO_240 0xF1000000 // VCO is 240 MHz +#define SYSCTL_CFG_VCO_160 0xF0000000 // VCO is 160 MHz #define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock #define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock #define SYSCTL_XTAL_1MHZ 0x00000000 // External crystal is 1MHz diff --git a/bsp/tm4c129x/libraries/driverlib/sysexc.c b/bsp/tm4c129x/libraries/driverlib/sysexc.c index d269b74bcd..ebf4e2e3f1 100644 --- a/bsp/tm4c129x/libraries/driverlib/sysexc.c +++ b/bsp/tm4c129x/libraries/driverlib/sysexc.c @@ -2,25 +2,25 @@ // // sysexc.c - Routines for the System Exception Module. // -// Copyright (c) 2011-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2011-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/sysexc.h b/bsp/tm4c129x/libraries/driverlib/sysexc.h index aece4409d1..0dad3df2f7 100644 --- a/bsp/tm4c129x/libraries/driverlib/sysexc.h +++ b/bsp/tm4c129x/libraries/driverlib/sysexc.h @@ -2,25 +2,25 @@ // // sysexc.h - Prototypes for the System Exception Module routines. // -// Copyright (c) 2011-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2011-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/systick.c b/bsp/tm4c129x/libraries/driverlib/systick.c index 662da1729e..174e5b889e 100644 --- a/bsp/tm4c129x/libraries/driverlib/systick.c +++ b/bsp/tm4c129x/libraries/driverlib/systick.c @@ -2,25 +2,25 @@ // // systick.c - Driver for the SysTick timer in NVIC. // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/systick.h b/bsp/tm4c129x/libraries/driverlib/systick.h index 35909ee3fb..4f36568ad7 100644 --- a/bsp/tm4c129x/libraries/driverlib/systick.h +++ b/bsp/tm4c129x/libraries/driverlib/systick.h @@ -2,25 +2,25 @@ // // systick.h - Prototypes for the SysTick driver. // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/tiva_timer.c b/bsp/tm4c129x/libraries/driverlib/tiva_timer.c index d348849570..f167400254 100644 --- a/bsp/tm4c129x/libraries/driverlib/tiva_timer.c +++ b/bsp/tm4c129x/libraries/driverlib/tiva_timer.c @@ -2,25 +2,25 @@ // // timer.c - Driver for the timer module. // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -297,6 +297,7 @@ TimerDisable(uint32_t ui32Base, uint32_t ui32Timer) //! - \b TIMER_CFG_A_CAP_TIME - Half-width edge time capture //! - \b TIMER_CFG_A_CAP_TIME_UP - Half-width edge time capture that counts up //! instead of down (not available on all parts) +//! - \b TIMER_CFG_A_ONE_SHOT_PWM - Half-width one shot PWM output //! - \b TIMER_CFG_A_PWM - Half-width PWM output //! //! Some Tiva devices also allow configuring an action when the timers @@ -351,11 +352,11 @@ TimerConfigure(uint32_t ui32Base, uint32_t ui32Config) // Check the arguments. // ASSERT(_TimerBaseValid(ui32Base)); - ASSERT((ui32Config == TIMER_CFG_ONE_SHOT) || - (ui32Config == TIMER_CFG_ONE_SHOT_UP) || - (ui32Config == TIMER_CFG_PERIODIC) || - (ui32Config == TIMER_CFG_PERIODIC_UP) || - (ui32Config == TIMER_CFG_RTC) || + ASSERT(((ui32Config & 0xfff0ffff) == TIMER_CFG_ONE_SHOT) || + ((ui32Config & 0xfff0ffff) == TIMER_CFG_ONE_SHOT_UP) || + ((ui32Config & 0xfff0ffff) == TIMER_CFG_PERIODIC) || + ((ui32Config & 0xfff0ffff) == TIMER_CFG_PERIODIC_UP) || + ((ui32Config & 0xfff0ffff) == TIMER_CFG_RTC) || ((ui32Config & 0xff000000) == TIMER_CFG_SPLIT_PAIR)); ASSERT(((ui32Config & 0xff000000) != TIMER_CFG_SPLIT_PAIR) || ((((ui32Config & 0x000000ff) == TIMER_CFG_A_ONE_SHOT) || @@ -366,6 +367,7 @@ TimerConfigure(uint32_t ui32Base, uint32_t ui32Config) ((ui32Config & 0x000000ff) == TIMER_CFG_A_CAP_COUNT_UP) || ((ui32Config & 0x000000ff) == TIMER_CFG_A_CAP_TIME) || ((ui32Config & 0x000000ff) == TIMER_CFG_A_CAP_TIME_UP) || + ((ui32Config & 0x000000ff) == TIMER_CFG_A_ONE_SHOT_PWM) || ((ui32Config & 0x000000ff) == TIMER_CFG_A_PWM)) && (((ui32Config & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT) || ((ui32Config & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT_UP) || @@ -375,6 +377,7 @@ TimerConfigure(uint32_t ui32Base, uint32_t ui32Config) ((ui32Config & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT_UP) || ((ui32Config & 0x0000ff00) == TIMER_CFG_B_CAP_TIME) || ((ui32Config & 0x0000ff00) == TIMER_CFG_B_CAP_TIME_UP) || + ((ui32Config & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT_PWM) || ((ui32Config & 0x0000ff00) == TIMER_CFG_B_PWM)))); // @@ -1454,10 +1457,12 @@ TimerIntUnregister(uint32_t ui32Base, uint32_t ui32Timer) //! - \b TIMER_TIMA_DMA - Timer A uDMA complete //! - \b TIMER_CAPB_EVENT - Capture B event interrupt //! - \b TIMER_CAPB_MATCH - Capture B match interrupt +//! - \b TIMER_TIMB_MATCH - Timer B match interrupt //! - \b TIMER_TIMB_TIMEOUT - Timer B timeout interrupt //! - \b TIMER_RTC_MATCH - RTC interrupt mask //! - \b TIMER_CAPA_EVENT - Capture A event interrupt //! - \b TIMER_CAPA_MATCH - Capture A match interrupt +//! - \b TIMER_TIMA_MATCH - Timer A match interrupt //! - \b TIMER_TIMA_TIMEOUT - Timer A timeout interrupt //! //! \return None. diff --git a/bsp/tm4c129x/libraries/driverlib/tiva_timer.h b/bsp/tm4c129x/libraries/driverlib/tiva_timer.h index 7eb619a7e0..e23b14d752 100644 --- a/bsp/tm4c129x/libraries/driverlib/tiva_timer.h +++ b/bsp/tm4c129x/libraries/driverlib/tiva_timer.h @@ -2,25 +2,25 @@ // // timer.h - Prototypes for the timer module // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -72,6 +72,7 @@ extern "C" #define TIMER_CFG_A_CAP_COUNT_UP 0x00000013 // Timer A event up-counter #define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer #define TIMER_CFG_A_CAP_TIME_UP 0x00000017 // Timer A event up-count timer +#define TIMER_CFG_A_ONE_SHOT_PWM 0x00000009 // Timer A one-shot PWM output #define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output #define TIMER_CFG_B_ONE_SHOT 0x00002100 // Timer B one-shot timer #define TIMER_CFG_B_ONE_SHOT_UP 0x00003100 // Timer B one-shot up-count timer @@ -81,6 +82,7 @@ extern "C" #define TIMER_CFG_B_CAP_COUNT_UP 0x00001300 // Timer B event up-counter #define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer #define TIMER_CFG_B_CAP_TIME_UP 0x00001700 // Timer B event up-count timer +#define TIMER_CFG_B_ONE_SHOT_PWM 0x00000900 // Timer B one-shot PWM output #define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output #define TIMER_CFG_A_ACT_TOINTD 0x00010000 // Timer A compare action disable // time-out interrupt. diff --git a/bsp/tm4c129x/libraries/driverlib/uart.c b/bsp/tm4c129x/libraries/driverlib/uart.c index 847f464cea..6690a8eb8a 100644 --- a/bsp/tm4c129x/libraries/driverlib/uart.c +++ b/bsp/tm4c129x/libraries/driverlib/uart.c @@ -2,25 +2,25 @@ // // uart.c - Driver for the UART. // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -355,7 +355,7 @@ UARTFIFOLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel, //! the system clock is the value returned by SysCtlClockGet() for TM4C123x //! devices or the value returned by SysCtlClockFreqSet() for TM4C129x devices, //! or it can be explicitly hard coded if it is constant and known (to save the -//! code/execution overhead of a call to SysCtlClockGet() or fetch of the +//! code/execution overhead of a call to SysCtlClockGet() or fetch of the //! variable call holding the return value of SysCtlClockFreqSet()). //! //! The function disables the UART by calling UARTDisable() before changing the @@ -459,7 +459,7 @@ UARTConfigSetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, //! the system clock is the value returned by SysCtlClockGet() for TM4C123x //! devices or the value returned by SysCtlClockFreqSet() for TM4C129x devices, //! or it can be explicitly hard coded if it is constant and known (to save the -//! code/execution overhead of a call to SysCtlClockGet() or fetch of the +//! code/execution overhead of a call to SysCtlClockGet() or fetch of the //! variable call holding the return value of SysCtlClockFreqSet()). //! //! For Tiva parts that have the ability to specify the UART baud clock @@ -811,7 +811,17 @@ UARTModemControlSet(uint32_t ui32Base, uint32_t ui32Control) // // Check the arguments. // +#if defined(TARGET_IS_TM4C123_RA1) || defined(TARGET_IS_TM4C123_RA2) || \ + defined(TARGET_IS_TM4C123_RA3) || defined(TARGET_IS_TM4C123_RB0) || \ + defined(TARGET_IS_TM4C123_RB1) ASSERT(ui32Base == UART1_BASE); +#else + ASSERT((ui32Base == UART0_BASE) || + (ui32Base == UART1_BASE) || + (ui32Base == UART2_BASE) || + (ui32Base == UART3_BASE) || + (ui32Base == UART4_BASE)); +#endif ASSERT((ui32Control & ~(UART_OUTPUT_RTS | UART_OUTPUT_DTR)) == 0); // @@ -853,7 +863,17 @@ UARTModemControlClear(uint32_t ui32Base, uint32_t ui32Control) // // Check the arguments. // +#if defined(TARGET_IS_TM4C123_RA1) || defined(TARGET_IS_TM4C123_RA2) || \ + defined(TARGET_IS_TM4C123_RA3) || defined(TARGET_IS_TM4C123_RB0) || \ + defined(TARGET_IS_TM4C123_RB1) ASSERT(ui32Base == UART1_BASE); +#else + ASSERT((ui32Base == UART0_BASE) || + (ui32Base == UART1_BASE) || + (ui32Base == UART2_BASE) || + (ui32Base == UART3_BASE) || + (ui32Base == UART4_BASE)); +#endif ASSERT((ui32Control & ~(UART_OUTPUT_RTS | UART_OUTPUT_DTR)) == 0); // @@ -889,7 +909,17 @@ UARTModemControlGet(uint32_t ui32Base) // // Check the arguments. // +#if defined(TARGET_IS_TM4C123_RA1) || defined(TARGET_IS_TM4C123_RA2) || \ + defined(TARGET_IS_TM4C123_RA3) || defined(TARGET_IS_TM4C123_RB0) || \ + defined(TARGET_IS_TM4C123_RB1) ASSERT(ui32Base == UART1_BASE); +#else + ASSERT((ui32Base == UART0_BASE) || + (ui32Base == UART1_BASE) || + (ui32Base == UART2_BASE) || + (ui32Base == UART3_BASE) || + (ui32Base == UART4_BASE)); +#endif return(HWREG(ui32Base + UART_O_CTL) & (UART_OUTPUT_RTS | UART_OUTPUT_DTR)); } @@ -919,7 +949,17 @@ UARTModemStatusGet(uint32_t ui32Base) // // Check the arguments. // +#if defined(TARGET_IS_TM4C123_RA1) || defined(TARGET_IS_TM4C123_RA2) || \ + defined(TARGET_IS_TM4C123_RA3) || defined(TARGET_IS_TM4C123_RB0) || \ + defined(TARGET_IS_TM4C123_RB1) ASSERT(ui32Base == UART1_BASE); +#else + ASSERT((ui32Base == UART0_BASE) || + (ui32Base == UART1_BASE) || + (ui32Base == UART2_BASE) || + (ui32Base == UART3_BASE) || + (ui32Base == UART4_BASE)); +#endif return(HWREG(ui32Base + UART_O_FR) & (UART_INPUT_RI | UART_INPUT_DCD | UART_INPUT_CTS | UART_INPUT_DSR)); @@ -1967,7 +2007,7 @@ UART9BitAddrSend(uint32_t ui32Base, uint8_t ui8Addr) //! diagnostics and debug. In this mode, the transmit and receive terminals of //! the same UART port are internally connected. Hence, the data transmitted //! on the UnTx output is received on the UxRx input, without having to go -//! through I/O's. UARTCharPut(), UARTCharGet() functions can be used along +//! through I/O's. UARTCharPut(), UARTCharGet() functions can be used along //! with this function. //! //! \return None. diff --git a/bsp/tm4c129x/libraries/driverlib/uart.h b/bsp/tm4c129x/libraries/driverlib/uart.h index 3a9397550d..9fc3074fe9 100644 --- a/bsp/tm4c129x/libraries/driverlib/uart.h +++ b/bsp/tm4c129x/libraries/driverlib/uart.h @@ -2,25 +2,25 @@ // // uart.h - Defines and Macros for the UART. // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/udma.c b/bsp/tm4c129x/libraries/driverlib/udma.c index bb2941af92..385553734a 100644 --- a/bsp/tm4c129x/libraries/driverlib/udma.c +++ b/bsp/tm4c129x/libraries/driverlib/udma.c @@ -2,25 +2,25 @@ // // udma.c - Driver for the micro-DMA controller. // -// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2007-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/udma.h b/bsp/tm4c129x/libraries/driverlib/udma.h index a8d3684489..663181fb19 100644 --- a/bsp/tm4c129x/libraries/driverlib/udma.h +++ b/bsp/tm4c129x/libraries/driverlib/udma.h @@ -2,25 +2,25 @@ // // udma.h - Prototypes and macros for the uDMA controller. // -// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2007-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/usb.c b/bsp/tm4c129x/libraries/driverlib/usb.c index 839a5575ed..65e2a5e839 100644 --- a/bsp/tm4c129x/libraries/driverlib/usb.c +++ b/bsp/tm4c129x/libraries/driverlib/usb.c @@ -2,25 +2,25 @@ // // usb.c - Driver for the USB Interface. // -// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2007-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/usb.h b/bsp/tm4c129x/libraries/driverlib/usb.h index 1fed815842..39b7c335e8 100644 --- a/bsp/tm4c129x/libraries/driverlib/usb.h +++ b/bsp/tm4c129x/libraries/driverlib/usb.h @@ -2,25 +2,25 @@ // // usb.h - Prototypes for the USB Interface Driver. // -// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2007-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/watchdog.c b/bsp/tm4c129x/libraries/driverlib/watchdog.c index e1761ff747..9d09f463f1 100644 --- a/bsp/tm4c129x/libraries/driverlib/watchdog.c +++ b/bsp/tm4c129x/libraries/driverlib/watchdog.c @@ -2,25 +2,25 @@ // // watchdog.c - Driver for the Watchdog Timer Module. // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -492,7 +492,7 @@ WatchdogIntStatus(uint32_t ui32Base, bool bMasked) //! actually cleared. Failure to do so may result in the interrupt handler //! being immediately reentered (because the interrupt controller still sees //! the interrupt source asserted). This function has no effect if the watchdog -//! timer has been locked. +//! timer has been locked. //! //! \return None. // diff --git a/bsp/tm4c129x/libraries/driverlib/watchdog.h b/bsp/tm4c129x/libraries/driverlib/watchdog.h index a14a4fb04c..a92ad93c1d 100644 --- a/bsp/tm4c129x/libraries/driverlib/watchdog.h +++ b/bsp/tm4c129x/libraries/driverlib/watchdog.h @@ -2,25 +2,25 @@ // // watchdog.h - Prototypes for the Watchdog Timer API // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/asmdefs.h b/bsp/tm4c129x/libraries/inc/asmdefs.h index b0e4cc217c..292815ac0f 100644 --- a/bsp/tm4c129x/libraries/inc/asmdefs.h +++ b/bsp/tm4c129x/libraries/inc/asmdefs.h @@ -2,25 +2,25 @@ // // asmdefs.h - Macros to allow assembly code be portable among toolchains. // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +// This is part of revision 2.2.0.295 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_adc.h b/bsp/tm4c129x/libraries/inc/hw_adc.h index 41f8a33e4d..35a5ef14f4 100644 --- a/bsp/tm4c129x/libraries/inc/hw_adc.h +++ b/bsp/tm4c129x/libraries/inc/hw_adc.h @@ -2,25 +2,25 @@ // // hw_adc.h - Macros used when accessing the ADC hardware. // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +// This is part of revision 2.2.0.295 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_aes.h b/bsp/tm4c129x/libraries/inc/hw_aes.h index 79d56113d6..4082d173f4 100644 --- a/bsp/tm4c129x/libraries/inc/hw_aes.h +++ b/bsp/tm4c129x/libraries/inc/hw_aes.h @@ -2,25 +2,25 @@ // // hw_aes.h - Macros used when accessing the AES hardware. // -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2012-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +// This is part of revision 2.2.0.295 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_can.h b/bsp/tm4c129x/libraries/inc/hw_can.h index 398a83d6cb..1e09d4f91f 100644 --- a/bsp/tm4c129x/libraries/inc/hw_can.h +++ b/bsp/tm4c129x/libraries/inc/hw_can.h @@ -2,25 +2,25 @@ // // hw_can.h - Defines and macros used when accessing the CAN controllers. // -// Copyright (c) 2006-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2006-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +// This is part of revision 2.2.0.295 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_ccm.h b/bsp/tm4c129x/libraries/inc/hw_ccm.h index 9664ceea75..4b415c7ae3 100644 --- a/bsp/tm4c129x/libraries/inc/hw_ccm.h +++ b/bsp/tm4c129x/libraries/inc/hw_ccm.h @@ -2,25 +2,25 @@ // // hw_ccm.h - Macros used when accessing the CCM hardware. // -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2012-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +// This is part of revision 2.2.0.295 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_comp.h b/bsp/tm4c129x/libraries/inc/hw_comp.h index 24616aa954..7212db5791 100644 --- a/bsp/tm4c129x/libraries/inc/hw_comp.h +++ b/bsp/tm4c129x/libraries/inc/hw_comp.h @@ -2,25 +2,25 @@ // // hw_comp.h - Macros used when accessing the comparator hardware. // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +// This is part of revision 2.2.0.295 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_des.h b/bsp/tm4c129x/libraries/inc/hw_des.h index 775c3a745c..79025df33a 100644 --- a/bsp/tm4c129x/libraries/inc/hw_des.h +++ b/bsp/tm4c129x/libraries/inc/hw_des.h @@ -2,25 +2,25 @@ // // hw_des.h - Macros used when accessing the DES hardware. // -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2012-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +// This is part of revision 2.2.0.295 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_eeprom.h b/bsp/tm4c129x/libraries/inc/hw_eeprom.h index 2118c958e6..1151b7cf64 100644 --- a/bsp/tm4c129x/libraries/inc/hw_eeprom.h +++ b/bsp/tm4c129x/libraries/inc/hw_eeprom.h @@ -2,25 +2,25 @@ // // hw_eeprom.h - Macros used when accessing the EEPROM controller. // -// Copyright (c) 2011-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2011-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +// This is part of revision 2.2.0.295 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_emac.h b/bsp/tm4c129x/libraries/inc/hw_emac.h index a836da9d21..2ce40c2cfe 100644 --- a/bsp/tm4c129x/libraries/inc/hw_emac.h +++ b/bsp/tm4c129x/libraries/inc/hw_emac.h @@ -2,25 +2,25 @@ // // hw_emac.h - Macros used when accessing the EMAC hardware. // -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2012-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +// This is part of revision 2.2.0.295 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_epi.h b/bsp/tm4c129x/libraries/inc/hw_epi.h index ea9f065562..fb9ff83f4e 100644 --- a/bsp/tm4c129x/libraries/inc/hw_epi.h +++ b/bsp/tm4c129x/libraries/inc/hw_epi.h @@ -2,25 +2,25 @@ // // hw_epi.h - Macros for use in accessing the EPI registers. // -// Copyright (c) 2008-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2008-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +// This is part of revision 2.2.0.295 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_fan.h b/bsp/tm4c129x/libraries/inc/hw_fan.h index 9c191cf0af..81d0cd4582 100644 --- a/bsp/tm4c129x/libraries/inc/hw_fan.h +++ b/bsp/tm4c129x/libraries/inc/hw_fan.h @@ -2,25 +2,25 @@ // // hw_fan.h - Macros used when accessing the fan control hardware. // -// Copyright (c) 2010-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2010-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +// This is part of revision 2.2.0.295 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_flash.h b/bsp/tm4c129x/libraries/inc/hw_flash.h index e38e85b59d..a6590f04cf 100644 --- a/bsp/tm4c129x/libraries/inc/hw_flash.h +++ b/bsp/tm4c129x/libraries/inc/hw_flash.h @@ -2,25 +2,25 @@ // // hw_flash.h - Macros used when accessing the flash controller. // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +// This is part of revision 2.2.0.295 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_gpio.h b/bsp/tm4c129x/libraries/inc/hw_gpio.h index 9e95aed435..679943573f 100644 --- a/bsp/tm4c129x/libraries/inc/hw_gpio.h +++ b/bsp/tm4c129x/libraries/inc/hw_gpio.h @@ -2,25 +2,25 @@ // // hw_gpio.h - Defines and Macros for GPIO hardware. // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +// This is part of revision 2.2.0.295 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_hibernate.h b/bsp/tm4c129x/libraries/inc/hw_hibernate.h index ce469a20e1..c6ac859371 100644 --- a/bsp/tm4c129x/libraries/inc/hw_hibernate.h +++ b/bsp/tm4c129x/libraries/inc/hw_hibernate.h @@ -2,25 +2,25 @@ // // hw_hibernate.h - Defines and Macros for the Hibernation module. // -// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2007-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +// This is part of revision 2.2.0.295 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_i2c.h b/bsp/tm4c129x/libraries/inc/hw_i2c.h index d9d00b5d57..3403a969dc 100644 --- a/bsp/tm4c129x/libraries/inc/hw_i2c.h +++ b/bsp/tm4c129x/libraries/inc/hw_i2c.h @@ -2,25 +2,25 @@ // // hw_i2c.h - Macros used when accessing the I2C master and slave hardware. // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +// This is part of revision 2.2.0.295 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_ints.h b/bsp/tm4c129x/libraries/inc/hw_ints.h index c75a84a6bb..7ecd162e7c 100644 --- a/bsp/tm4c129x/libraries/inc/hw_ints.h +++ b/bsp/tm4c129x/libraries/inc/hw_ints.h @@ -3,25 +3,25 @@ // hw_ints.h - Macros that define the interrupt assignment on Tiva C Series // MCUs. // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -33,8 +33,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +// This is part of revision 2.2.0.295 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_lcd.h b/bsp/tm4c129x/libraries/inc/hw_lcd.h index bf0be0ae2f..865bfe47f6 100644 --- a/bsp/tm4c129x/libraries/inc/hw_lcd.h +++ b/bsp/tm4c129x/libraries/inc/hw_lcd.h @@ -2,25 +2,25 @@ // // hw_lcd.h - Defines and macros used when accessing the LCD controller. // -// Copyright (c) 2011-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2011-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +// This is part of revision 2.2.0.295 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_memmap.h b/bsp/tm4c129x/libraries/inc/hw_memmap.h index 87033ab823..882aa9de95 100644 --- a/bsp/tm4c129x/libraries/inc/hw_memmap.h +++ b/bsp/tm4c129x/libraries/inc/hw_memmap.h @@ -2,25 +2,25 @@ // // hw_memmap.h - Macros defining the memory map of the device. // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +// This is part of revision 2.2.0.295 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_nvic.h b/bsp/tm4c129x/libraries/inc/hw_nvic.h index be8becf0fb..9d18a6929a 100644 --- a/bsp/tm4c129x/libraries/inc/hw_nvic.h +++ b/bsp/tm4c129x/libraries/inc/hw_nvic.h @@ -2,25 +2,25 @@ // // hw_nvic.h - Macros used when accessing the NVIC hardware. // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +// This is part of revision 2.2.0.295 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_onewire.h b/bsp/tm4c129x/libraries/inc/hw_onewire.h index bf810b7ce9..8b48cd5dc6 100644 --- a/bsp/tm4c129x/libraries/inc/hw_onewire.h +++ b/bsp/tm4c129x/libraries/inc/hw_onewire.h @@ -2,25 +2,25 @@ // // hw_onewire.h - Macros used when accessing the One wire hardware. // -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2012-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +// This is part of revision 2.2.0.295 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_pwm.h b/bsp/tm4c129x/libraries/inc/hw_pwm.h index 2167aad93a..1ec5cf7796 100644 --- a/bsp/tm4c129x/libraries/inc/hw_pwm.h +++ b/bsp/tm4c129x/libraries/inc/hw_pwm.h @@ -2,25 +2,25 @@ // // hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports. // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +// This is part of revision 2.2.0.295 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_qei.h b/bsp/tm4c129x/libraries/inc/hw_qei.h index a86f5259bd..cfb8f4d203 100644 --- a/bsp/tm4c129x/libraries/inc/hw_qei.h +++ b/bsp/tm4c129x/libraries/inc/hw_qei.h @@ -2,25 +2,25 @@ // // hw_qei.h - Macros used when accessing the QEI hardware. // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +// This is part of revision 2.2.0.295 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_shamd5.h b/bsp/tm4c129x/libraries/inc/hw_shamd5.h index d34c76092c..1fa68fa838 100644 --- a/bsp/tm4c129x/libraries/inc/hw_shamd5.h +++ b/bsp/tm4c129x/libraries/inc/hw_shamd5.h @@ -2,25 +2,25 @@ // // hw_shamd5.h - Macros used when accessing the SHA/MD5 hardware. // -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2012-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +// This is part of revision 2.2.0.295 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_ssi.h b/bsp/tm4c129x/libraries/inc/hw_ssi.h index 36a92cf1e4..43560acb16 100644 --- a/bsp/tm4c129x/libraries/inc/hw_ssi.h +++ b/bsp/tm4c129x/libraries/inc/hw_ssi.h @@ -2,25 +2,25 @@ // // hw_ssi.h - Macros used when accessing the SSI hardware. // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +// This is part of revision 2.2.0.295 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_sysctl.h b/bsp/tm4c129x/libraries/inc/hw_sysctl.h index cab5049da5..d591b05c57 100644 --- a/bsp/tm4c129x/libraries/inc/hw_sysctl.h +++ b/bsp/tm4c129x/libraries/inc/hw_sysctl.h @@ -2,25 +2,25 @@ // // hw_sysctl.h - Macros used when accessing the system control hardware. // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +// This is part of revision 2.2.0.295 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_sysexc.h b/bsp/tm4c129x/libraries/inc/hw_sysexc.h index 314d17a8a1..0be323e231 100644 --- a/bsp/tm4c129x/libraries/inc/hw_sysexc.h +++ b/bsp/tm4c129x/libraries/inc/hw_sysexc.h @@ -2,25 +2,25 @@ // // hw_sysexc.h - Macros used when accessing the system exception module. // -// Copyright (c) 2011-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2011-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +// This is part of revision 2.2.0.295 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_timer.h b/bsp/tm4c129x/libraries/inc/hw_timer.h index 47a857567a..08d855214c 100644 --- a/bsp/tm4c129x/libraries/inc/hw_timer.h +++ b/bsp/tm4c129x/libraries/inc/hw_timer.h @@ -2,25 +2,25 @@ // // hw_timer.h - Defines and macros used when accessing the timer. // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +// This is part of revision 2.2.0.295 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_types.h b/bsp/tm4c129x/libraries/inc/hw_types.h index ec493b5061..9b0a5bf7b9 100644 --- a/bsp/tm4c129x/libraries/inc/hw_types.h +++ b/bsp/tm4c129x/libraries/inc/hw_types.h @@ -2,25 +2,25 @@ // // hw_types.h - Common types and macros. // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +// This is part of revision 2.2.0.295 of the Tiva Firmware Development Package. // //***************************************************************************** @@ -110,7 +110,7 @@ #ifndef REVISION_IS_A1 #define REVISION_IS_A1 \ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ - (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0)) + (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_1)) #endif #ifndef REVISION_IS_A2 diff --git a/bsp/tm4c129x/libraries/inc/hw_uart.h b/bsp/tm4c129x/libraries/inc/hw_uart.h index 1c40b79f3d..8d98957073 100644 --- a/bsp/tm4c129x/libraries/inc/hw_uart.h +++ b/bsp/tm4c129x/libraries/inc/hw_uart.h @@ -2,25 +2,25 @@ // // hw_uart.h - Macros and defines used when accessing the UART hardware. // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +// This is part of revision 2.2.0.295 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_udma.h b/bsp/tm4c129x/libraries/inc/hw_udma.h index 1d52b00901..5cd8c33a3d 100644 --- a/bsp/tm4c129x/libraries/inc/hw_udma.h +++ b/bsp/tm4c129x/libraries/inc/hw_udma.h @@ -2,25 +2,25 @@ // // hw_udma.h - Macros for use in accessing the UDMA registers. // -// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2007-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +// This is part of revision 2.2.0.295 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_usb.h b/bsp/tm4c129x/libraries/inc/hw_usb.h index 7aa3b50a29..506af163f3 100644 --- a/bsp/tm4c129x/libraries/inc/hw_usb.h +++ b/bsp/tm4c129x/libraries/inc/hw_usb.h @@ -2,25 +2,25 @@ // // hw_usb.h - Macros for use in accessing the USB registers. // -// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2007-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +// This is part of revision 2.2.0.295 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_watchdog.h b/bsp/tm4c129x/libraries/inc/hw_watchdog.h index 783b6f07f6..937d5146a4 100644 --- a/bsp/tm4c129x/libraries/inc/hw_watchdog.h +++ b/bsp/tm4c129x/libraries/inc/hw_watchdog.h @@ -2,25 +2,25 @@ // // hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware. // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +// This is part of revision 2.2.0.295 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/tm4c1294ncpdt.h b/bsp/tm4c129x/libraries/inc/tm4c1294ncpdt.h index 458eaac395..ef80879350 100644 --- a/bsp/tm4c129x/libraries/inc/tm4c1294ncpdt.h +++ b/bsp/tm4c129x/libraries/inc/tm4c1294ncpdt.h @@ -2,25 +2,25 @@ // // tm4c1294ncpdt.h - TM4C1294NCPDT Register Definitions // -// Copyright (c) 2013-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2013-2020 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: -// +// // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// documentation and/or other materials provided with the // distribution. -// +// // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -32,8 +32,8 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +// This is part of revision 2.2.0.295 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/startup/startup_ewarm.c b/bsp/tm4c129x/libraries/startup/startup_ewarm.c index a5dbd78756..9542e980b6 100644 --- a/bsp/tm4c129x/libraries/startup/startup_ewarm.c +++ b/bsp/tm4c129x/libraries/startup/startup_ewarm.c @@ -5,20 +5,20 @@ // // Copyright (c) 2013-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Texas Instruments (TI) is supplying this software for use solely and // exclusively on TI's microcontroller products. The software is owned by // TI and/or its suppliers, and is protected under applicable copyright // laws. You may not combine this software with "viral" open-source // software in order to form a larger program. -// +// // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. -// +// // This is part of revision 2.1.4.178 of the DK-TM4C129X Firmware Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/startup/startup_gcc.c b/bsp/tm4c129x/libraries/startup/startup_gcc.c index 3f9d93a46b..30a95d3f34 100644 --- a/bsp/tm4c129x/libraries/startup/startup_gcc.c +++ b/bsp/tm4c129x/libraries/startup/startup_gcc.c @@ -4,20 +4,20 @@ // // Copyright (c) 2013-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Texas Instruments (TI) is supplying this software for use solely and // exclusively on TI's microcontroller products. The software is owned by // TI and/or its suppliers, and is protected under applicable copyright // laws. You may not combine this software with "viral" open-source // software in order to form a larger program. -// +// // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. -// +// // This is part of revision 2.1.4.178 of the DK-TM4C129X Firmware Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/startup/startup_rvmdk.S b/bsp/tm4c129x/libraries/startup/startup_rvmdk.S index 3554d00143..4754d15316 100644 --- a/bsp/tm4c129x/libraries/startup/startup_rvmdk.S +++ b/bsp/tm4c129x/libraries/startup/startup_rvmdk.S @@ -5,20 +5,20 @@ ; ; Copyright (c) 2013-2017 Texas Instruments Incorporated. All rights reserved. ; Software License Agreement -; +; ; Texas Instruments (TI) is supplying this software for use solely and ; exclusively on TI's microcontroller products. The software is owned by ; TI and/or its suppliers, and is protected under applicable copyright ; laws. You may not combine this software with "viral" open-source ; software in order to form a larger program. -; +; ; THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. ; NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT ; NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ; A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY ; CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL ; DAMAGES, FOR ANY REASON WHATSOEVER. -; +; ; This is part of revision 2.1.4.178 of the DK-TM4C129X Firmware Package. ; ;****************************************************************************** diff --git a/bsp/w60x/drivers/pin_config.h b/bsp/w60x/drivers/pin_config.h index c704fafb22..130c81ea1c 100644 --- a/bsp/w60x/drivers/pin_config.h +++ b/bsp/w60x/drivers/pin_config.h @@ -14,8 +14,13 @@ #define WM_UART2_RX_PIN 1 // PB19 : UART2_RX (W601) #define WM_UART2_TX_PIN 2 // PB20 : UART2_TX (W601) +#if defined(SOC_W600_A8xx) #define WM_UART1_RX_PIN 31 // PB11 : UART1_RX (W600) #define WM_UART1_TX_PIN 32 // PB12 : UART1_TX (W600) +#elif defined(SOC_W601_A8xx) +#define WM_UART1_RX_PIN 66 // PB11 : UART1_RX (W601) +#define WM_UART1_TX_PIN 67 // PB12 : UART1_TX (W601) +#endif // spi #define WM_SPI_CK_PIN 53 // PB27 : SPI_SCK diff --git a/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sleep.h b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sleep.h index 7e8c778295..ca6e56a7ec 100644 --- a/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sleep.h +++ b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sleep.h @@ -1,3 +1,12 @@ +/* + * Copyright (c) 2020-2021, WangHuachen + * + * SPDX-License-Identifier: MIT + * + * Change Logs: + * Date Author Notes + * 2020-11-30 WangHuachen the first version + */ #ifndef XLI_SLEEP_H #define XLI_SLEEP_H diff --git a/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_assert.h b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_assert.h index de095f1f4c..7abe853e29 100644 --- a/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_assert.h +++ b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_assert.h @@ -1,3 +1,12 @@ +/* + * Copyright (c) 2020-2021, WangHuachen + * + * SPDX-License-Identifier: MIT + * + * Change Logs: + * Date Author Notes + * 2020-11-30 WangHuachen the first version + */ #ifndef XIL_ASSERT_H /* prevent circular inclusions */ #define XIL_ASSERT_H /* by using protection macros */ diff --git a/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_cache.h b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_cache.h index 1731e84850..575157e6d2 100644 --- a/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_cache.h +++ b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_cache.h @@ -1,6 +1,17 @@ +/* + * Copyright (c) 2020-2021, WangHuachen + * + * SPDX-License-Identifier: MIT + * + * Change Logs: + * Date Author Notes + * 2020-11-30 WangHuachen the first version + */ #ifndef XIL_CACHE_H #define XIL_CACHE_H +#include + #ifdef __cplusplus extern "C" { #endif diff --git a/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_printf.h b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_printf.h index b6983a5d7e..29de8c2441 100644 --- a/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_printf.h +++ b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_printf.h @@ -1,5 +1,14 @@ - #ifndef XIL_PRINTF_H - #define XIL_PRINTF_H +/* + * Copyright (c) 2020-2021, WangHuachen + * + * SPDX-License-Identifier: MIT + * + * Change Logs: + * Date Author Notes + * 2020-11-30 WangHuachen the first version + */ +#ifndef XIL_PRINTF_H +#define XIL_PRINTF_H #include diff --git a/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_types.h b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_types.h index a6988a20a5..cebdbcd56e 100644 --- a/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_types.h +++ b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_types.h @@ -1,3 +1,13 @@ +/* + * Copyright (C) 2010-2020 Xilinx, Inc. + * Copyright (c) 2020-2021, WangHuachen + * All rights reserved. + * SPDX-License-Identifier: MIT + * + * Change Logs: + * Date Author Notes + * 2020-11-30 WangHuachen the first version + */ #ifndef XIL_TYPES_H /* prevent circular inclusions */ #define XIL_TYPES_H /* by using protection macros */ @@ -70,6 +80,30 @@ typedef void (*XInterruptHandler) (void *InstancePtr); */ typedef void (*XExceptionHandler) (void *InstancePtr); +/** + * @brief Returns 32-63 bits of a number. + * @param n : Number being accessed. + * @return Bits 32-63 of number. + * + * @note A basic shift-right of a 64- or 32-bit quantity. + * Use this to suppress the "right shift count >= width of type" + * warning when that quantity is 32-bits. + */ +#if defined (__aarch64__) || defined (__arch64__) +#define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16)) +#else +#define UPPER_32_BITS(n) 0U +#endif +/** + * @brief Returns 0-31 bits of a number + * @param n : Number being accessed. + * @return Bits 0-31 of number + */ +#define LOWER_32_BITS(n) ((u32)(n)) + + + + /************************** Constant Definitions *****************************/ #ifndef TRUE diff --git a/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xplatform_info.h b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xplatform_info.h index 4213736270..0024b53f6c 100644 --- a/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xplatform_info.h +++ b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xplatform_info.h @@ -1,3 +1,13 @@ +/* + * Copyright (C) 2014-2020 Xilinx, Inc. + * Copyright (c) 2020-2021, WangHuachen + * All rights reserved. + * SPDX-License-Identifier: MIT + * + * Change Logs: + * Date Author Notes + * 2020-11-30 WangHuachen the first version + */ #ifndef XPLATFORM_INFO_H /* prevent circular inclusions */ #define XPLATFORM_INFO_H /* by using protection macros */ diff --git a/bsp/zynqmp-r5-axu4ev/drivers/drv_eth.c b/bsp/zynqmp-r5-axu4ev/drivers/drv_eth.c index e3e1884cf2..05c29305fc 100644 --- a/bsp/zynqmp-r5-axu4ev/drivers/drv_eth.c +++ b/bsp/zynqmp-r5-axu4ev/drivers/drv_eth.c @@ -7,8 +7,6 @@ * Date Author Notes * 2021-5-10 WangHuachen the first version */ - - #include "board.h" #include #include "lwipopts.h" diff --git a/bsp/zynqmp-r5-axu4ev/drivers/zynqmp-r5.h b/bsp/zynqmp-r5-axu4ev/drivers/zynqmp-r5.h index 3192942b57..fc8cfb0f97 100644 --- a/bsp/zynqmp-r5-axu4ev/drivers/zynqmp-r5.h +++ b/bsp/zynqmp-r5-axu4ev/drivers/zynqmp-r5.h @@ -1,3 +1,12 @@ +/* + * Copyright (c) 2020-2021, WangHuachen + * + * SPDX-License-Identifier: MIT + * + * Change Logs: + * Date Author Notes + * 2020-11-30 WangHuachen the first version + */ #ifndef __ZYNQMP_R5_H__ #define __ZYNQMP_R5_H__ diff --git a/components/dfs/include/dfs_fs.h b/components/dfs/include/dfs_fs.h index 828f15a0f5..3d194515df 100644 --- a/components/dfs/include/dfs_fs.h +++ b/components/dfs/include/dfs_fs.h @@ -15,7 +15,7 @@ #ifdef RT_USING_LIBC #include #endif - +#include #ifdef __cplusplus extern "C" { #endif diff --git a/components/dfs/src/dfs_file.c b/components/dfs/src/dfs_file.c index 802311b54e..fa0f6000b4 100644 --- a/components/dfs/src/dfs_file.c +++ b/components/dfs/src/dfs_file.c @@ -157,7 +157,7 @@ int dfs_file_ioctl(struct dfs_fd *fd, int cmd, void *args) return -EINVAL; /* regular file system fd */ - if (fd->type == FT_REGULAR || fd->type == FT_DEVICE) + if (fd->type == FT_REGULAR) { switch (cmd) { diff --git a/components/drivers/Kconfig b/components/drivers/Kconfig index c7fec6cba9..d3fd14b52d 100755 --- a/components/drivers/Kconfig +++ b/components/drivers/Kconfig @@ -24,22 +24,30 @@ if RT_USING_DEVICE_IPC endif endif -config RT_USING_SERIAL - bool "Using serial device drivers" +menuconfig RT_USING_SERIAL + bool "USING Serial device drivers" select RT_USING_DEVICE_IPC select RT_USING_DEVICE default y -if RT_USING_SERIAL - config RT_SERIAL_USING_DMA - bool "Enable serial DMA mode" - default y + if RT_USING_SERIAL + choice + prompt "Choice Serial version" + default RT_USING_SERIAL_V1 + config RT_USING_SERIAL_V1 + bool "RT_USING_SERIAL_V1" + config RT_USING_SERIAL_V2 + bool "RT_USING_SERIAL_V2" + endchoice + config RT_SERIAL_USING_DMA + bool "Enable serial DMA mode" + default y - config RT_SERIAL_RB_BUFSZ - int "Set RX buffer size" - default 64 - -endif + config RT_SERIAL_RB_BUFSZ + int "Set RX buffer size" + depends on !RT_USING_SERIAL_V2 + default 64 + endif config RT_USING_CAN bool "Using CAN device drivers" diff --git a/components/drivers/cputime/cputime.c b/components/drivers/cputime/cputime.c index 4a9eee3a71..750733f366 100644 --- a/components/drivers/cputime/cputime.c +++ b/components/drivers/cputime/cputime.c @@ -10,6 +10,7 @@ #include #include +#include static const struct rt_clock_cputime_ops *_cputime_ops = RT_NULL; @@ -24,7 +25,7 @@ float clock_cpu_getres(void) if (_cputime_ops) return _cputime_ops->cputime_getres(); - rt_set_errno(-ENOSYS); + rt_set_errno(ENOSYS); return 0; } @@ -38,7 +39,7 @@ uint32_t clock_cpu_gettime(void) if (_cputime_ops) return _cputime_ops->cputime_gettime(); - rt_set_errno(-ENOSYS); + rt_set_errno(ENOSYS); return 0; } diff --git a/components/drivers/include/drivers/rtc.h b/components/drivers/include/drivers/rtc.h index a9e1c17a9d..9eddf801b7 100644 --- a/components/drivers/include/drivers/rtc.h +++ b/components/drivers/include/drivers/rtc.h @@ -12,6 +12,7 @@ #define __RTC_H__ #include +#include rt_err_t set_date(rt_uint32_t year, rt_uint32_t month, rt_uint32_t day); rt_err_t set_time(rt_uint32_t hour, rt_uint32_t minute, rt_uint32_t second); diff --git a/components/drivers/include/drivers/rtc_core.h b/components/drivers/include/drivers/rtc_core.h new file mode 100644 index 0000000000..f0c7b64e94 --- /dev/null +++ b/components/drivers/include/drivers/rtc_core.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-06-11 iysheng first version. + */ + +#ifndef __RTC_CORE_H__ +#define __RTC_CORE_H__ + +#include + +#define RT_DEVICE_CTRL_RTC_GET_TIME 0x10 /**< get second time */ +#define RT_DEVICE_CTRL_RTC_SET_TIME 0x11 /**< set second time */ +#define RT_DEVICE_CTRL_RTC_GET_TIME_US 0x12 /**< get microsecond time */ +#define RT_DEVICE_CTRL_RTC_SET_TIME_US 0x13 /**< set microsecond time */ +#define RT_DEVICE_CTRL_RTC_GET_ALARM 0x14 /**< get alarm */ +#define RT_DEVICE_CTRL_RTC_SET_ALARM 0x15 /**< set alarm */ + +struct rt_rtc_ops +{ + rt_err_t (*init)(void); + rt_err_t (*get_secs)(void *arg); + rt_err_t (*set_secs)(void *arg); + rt_err_t (*get_alarm)(void *arg); + rt_err_t (*set_alarm)(void *arg); + rt_err_t (*get_usecs)(void *arg); + rt_err_t (*set_usecs)(void *arg); +}; + +typedef struct rt_rtc_device +{ + struct rt_device parent; + const struct rt_rtc_ops *ops; +} rt_rtc_dev_t; + +rt_err_t rt_rtc_dev_register(rt_rtc_dev_t *rtc, + const char *name, + rt_uint32_t flag, + void *data); + +#endif /* __RTC_CORE_H__ */ diff --git a/components/drivers/include/drivers/serial_v2.h b/components/drivers/include/drivers/serial_v2.h new file mode 100644 index 0000000000..3ba46bdcdd --- /dev/null +++ b/components/drivers/include/drivers/serial_v2.h @@ -0,0 +1,185 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-06-01 KyleChan first version + */ + +#ifndef __SERIAL_V2_H__ +#define __SERIAL_V2_H__ + +#include + +#define BAUD_RATE_2400 2400 +#define BAUD_RATE_4800 4800 +#define BAUD_RATE_9600 9600 +#define BAUD_RATE_19200 19200 +#define BAUD_RATE_38400 38400 +#define BAUD_RATE_57600 57600 +#define BAUD_RATE_115200 115200 +#define BAUD_RATE_230400 230400 +#define BAUD_RATE_460800 460800 +#define BAUD_RATE_921600 921600 +#define BAUD_RATE_2000000 2000000 +#define BAUD_RATE_3000000 3000000 + +#define DATA_BITS_5 5 +#define DATA_BITS_6 6 +#define DATA_BITS_7 7 +#define DATA_BITS_8 8 +#define DATA_BITS_9 9 + +#define STOP_BITS_1 0 +#define STOP_BITS_2 1 +#define STOP_BITS_3 2 +#define STOP_BITS_4 3 + +#ifdef _WIN32 +#include +#else +#define PARITY_NONE 0 +#define PARITY_ODD 1 +#define PARITY_EVEN 2 +#endif + +#define BIT_ORDER_LSB 0 +#define BIT_ORDER_MSB 1 + +#define NRZ_NORMAL 0 /* Non Return to Zero : normal mode */ +#define NRZ_INVERTED 1 /* Non Return to Zero : inverted mode */ + +#define RT_DEVICE_FLAG_RX_BLOCKING 0x1000 +#define RT_DEVICE_FLAG_RX_NON_BLOCKING 0x2000 + +#define RT_DEVICE_FLAG_TX_BLOCKING 0x4000 +#define RT_DEVICE_FLAG_TX_NON_BLOCKING 0x8000 + +#define RT_SERIAL_RX_BLOCKING RT_DEVICE_FLAG_RX_BLOCKING +#define RT_SERIAL_RX_NON_BLOCKING RT_DEVICE_FLAG_RX_NON_BLOCKING +#define RT_SERIAL_TX_BLOCKING RT_DEVICE_FLAG_TX_BLOCKING +#define RT_SERIAL_TX_NON_BLOCKING RT_DEVICE_FLAG_TX_NON_BLOCKING + +#define RT_DEVICE_CHECK_OPTMODE 0x20 + +#define RT_SERIAL_EVENT_RX_IND 0x01 /* Rx indication */ +#define RT_SERIAL_EVENT_TX_DONE 0x02 /* Tx complete */ +#define RT_SERIAL_EVENT_RX_DMADONE 0x03 /* Rx DMA transfer done */ +#define RT_SERIAL_EVENT_TX_DMADONE 0x04 /* Tx DMA transfer done */ +#define RT_SERIAL_EVENT_RX_TIMEOUT 0x05 /* Rx timeout */ + +#define RT_SERIAL_ERR_OVERRUN 0x01 +#define RT_SERIAL_ERR_FRAMING 0x02 +#define RT_SERIAL_ERR_PARITY 0x03 + +#define RT_SERIAL_TX_DATAQUEUE_SIZE 2048 +#define RT_SERIAL_TX_DATAQUEUE_LWM 30 + +#define RT_SERIAL_RX_MINBUFSZ 64 +#define RT_SERIAL_TX_MINBUFSZ 64 + +#define RT_SERIAL_TX_BLOCKING_BUFFER 1 +#define RT_SERIAL_TX_BLOCKING_NO_BUFFER 0 + +/* Default config for serial_configure structure */ +#define RT_SERIAL_CONFIG_DEFAULT \ +{ \ + BAUD_RATE_115200, /* 115200 bits/s */ \ + DATA_BITS_8, /* 8 databits */ \ + STOP_BITS_1, /* 1 stopbit */ \ + PARITY_NONE, /* No parity */ \ + BIT_ORDER_LSB, /* LSB first sent */ \ + NRZ_NORMAL, /* Normal mode */ \ + RT_SERIAL_RX_MINBUFSZ, /* rxBuf size */ \ + RT_SERIAL_TX_MINBUFSZ, /* txBuf size */ \ + 0 \ +} + +struct serial_configure +{ + rt_uint32_t baud_rate; + + rt_uint32_t data_bits :4; + rt_uint32_t stop_bits :2; + rt_uint32_t parity :2; + rt_uint32_t bit_order :1; + rt_uint32_t invert :1; + rt_uint32_t rx_bufsz :16; + rt_uint32_t tx_bufsz :16; + rt_uint32_t reserved :6; +}; + +/* + * Serial Receive FIFO mode + */ +struct rt_serial_rx_fifo +{ + struct rt_ringbuffer rb; + + struct rt_completion rx_cpt; + + rt_uint16_t rx_cpt_index; + + /* software fifo */ + rt_uint8_t buffer[]; +}; + +/* + * Serial Transmit FIFO mode + */ +struct rt_serial_tx_fifo +{ + struct rt_ringbuffer rb; + + rt_size_t put_size; + + rt_bool_t activated; + + struct rt_completion tx_cpt; + + /* software fifo */ + rt_uint8_t buffer[]; +}; + +struct rt_serial_device +{ + struct rt_device parent; + + const struct rt_uart_ops *ops; + struct serial_configure config; + + void *serial_rx; + void *serial_tx; +}; + +/** + * uart operators + */ +struct rt_uart_ops +{ + rt_err_t (*configure)(struct rt_serial_device *serial, + struct serial_configure *cfg); + + rt_err_t (*control)(struct rt_serial_device *serial, + int cmd, + void *arg); + + int (*putc)(struct rt_serial_device *serial, char c); + int (*getc)(struct rt_serial_device *serial); + + rt_size_t (*transmit)(struct rt_serial_device *serial, + rt_uint8_t *buf, + rt_size_t size, + rt_uint32_t tx_flag); +}; + +void rt_hw_serial_isr(struct rt_serial_device *serial, int event); + +rt_err_t rt_hw_serial_register(struct rt_serial_device *serial, + const char *name, + rt_uint32_t flag, + void *data); + +#endif diff --git a/components/drivers/include/ipc/workqueue.h b/components/drivers/include/ipc/workqueue.h index ccbc42b226..a156145641 100644 --- a/components/drivers/include/ipc/workqueue.h +++ b/components/drivers/include/ipc/workqueue.h @@ -64,11 +64,12 @@ rt_err_t rt_workqueue_submit_work(struct rt_workqueue *queue, struct rt_work *wo rt_err_t rt_workqueue_cancel_work(struct rt_workqueue *queue, struct rt_work *work); rt_err_t rt_workqueue_cancel_work_sync(struct rt_workqueue *queue, struct rt_work *work); rt_err_t rt_workqueue_cancel_all_work(struct rt_workqueue *queue); +rt_err_t rt_workqueue_critical_work(struct rt_workqueue *queue, struct rt_work *work); #ifdef RT_USING_SYSTEM_WORKQUEUE rt_err_t rt_work_submit(struct rt_work *work, rt_tick_t time); rt_err_t rt_work_cancel(struct rt_work *work); -#endif +#endif /* RT_USING_SYSTEM_WORKQUEUE */ rt_inline void rt_work_init(struct rt_work *work, void (*work_func)(struct rt_work *work, void *work_data), void *work_data) @@ -84,7 +85,6 @@ rt_inline void rt_work_init(struct rt_work *work, void (*work_func)(struct rt_wo void rt_delayed_work_init(struct rt_delayed_work *work, void (*work_func)(struct rt_work *work, void *work_data), void *work_data); -int rt_work_sys_workqueue_init(void); -#endif +#endif /* RT_USING_HEAP */ #endif diff --git a/components/drivers/include/rtdevice.h b/components/drivers/include/rtdevice.h index fbd3c9e7b2..07a2be361e 100644 --- a/components/drivers/include/rtdevice.h +++ b/components/drivers/include/rtdevice.h @@ -57,7 +57,11 @@ extern "C" { #endif /* RT_USING_USB_HOST */ #ifdef RT_USING_SERIAL +#ifdef RT_USING_SERIAL_V2 +#include "drivers/serial_v2.h" +#else #include "drivers/serial.h" +#endif #endif /* RT_USING_SERIAL */ #ifdef RT_USING_I2C diff --git a/components/drivers/pm/pm.c b/components/drivers/pm/pm.c index 80ed101498..cf488a9ce1 100644 --- a/components/drivers/pm/pm.c +++ b/components/drivers/pm/pm.c @@ -836,12 +836,10 @@ rt_uint32_t rt_pm_module_get_status(void) rt_uint32_t req_status = 0x00; pm = &_pm; - for (index = 0; index < 32; index ++) + for (index = 0; index < PM_MODULE_MAX_ID; index ++) { if (pm->module_status[index].req_status == 0x01) req_status |= 1<= PM_MODULE_MAX_ID) - break; } return req_status; diff --git a/components/drivers/rtc/SConscript b/components/drivers/rtc/SConscript index 6ec8bcb3c5..c3252fe7f9 100644 --- a/components/drivers/rtc/SConscript +++ b/components/drivers/rtc/SConscript @@ -7,7 +7,7 @@ CPPPATH = [cwd + '/../include'] group = [] if GetDepend(['RT_USING_RTC']): - src = src + ['rtc.c'] + src = src + ['rtc.c', 'rtc_core.c'] if GetDepend(['RT_USING_ALARM']): src = src + ['alarm.c'] if GetDepend(['RT_USING_SOFT_RTC']): diff --git a/components/drivers/rtc/rtc.c b/components/drivers/rtc/rtc.c index b5005429a0..3a843e2e0c 100644 --- a/components/drivers/rtc/rtc.c +++ b/components/drivers/rtc/rtc.c @@ -16,6 +16,7 @@ #include #include #include +#include #ifdef RT_USING_RTC diff --git a/components/drivers/rtc/rtc_core.c b/components/drivers/rtc/rtc_core.c new file mode 100644 index 0000000000..80bb61c8aa --- /dev/null +++ b/components/drivers/rtc/rtc_core.c @@ -0,0 +1,123 @@ +/* + * COPYRIGHT (C) 2011-2021, Real-Thread Information Technology Ltd + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-06-11 iysheng first version. + */ + +#include + +#define TRY_DO_RTC_FUNC(rt_rtc_dev, func_name, args) \ + rt_rtc_dev->ops->func_name ? rt_rtc_dev->ops->func_name(args) : -RT_EINVAL; + +/* + * This function initializes rtc_core + */ +static rt_err_t rt_rtc_core_init(struct rt_device *dev) +{ + rt_rtc_dev_t *rtc_core; + + RT_ASSERT(dev != RT_NULL); + rtc_core = (rt_rtc_dev_t *)dev; + if (rtc_core->ops->init) + { + return (rtc_core->ops->init()); + } + + return (-RT_ENOSYS); +} + +static rt_err_t rt_rtc_core_open(struct rt_device *dev, rt_uint16_t oflag) +{ + return (RT_EOK); +} + +static rt_err_t rt_rtc_core_close(struct rt_device *dev) +{ + /* Add close member function in rt_rtc_ops when need, + * then call that function here. + * */ + return (RT_EOK); +} + +static rt_err_t rt_rtc_core_control(struct rt_device *dev, + int cmd, + void *args) +{ + rt_rtc_dev_t *rtc_core; + rt_err_t ret = -RT_EINVAL; + + RT_ASSERT(dev != RT_NULL); + rtc_core = (rt_rtc_dev_t *)dev; + + switch (cmd) + { + case RT_DEVICE_CTRL_RTC_GET_TIME: + ret = TRY_DO_RTC_FUNC(rtc_core, get_secs, args); + break; + case RT_DEVICE_CTRL_RTC_SET_TIME: + ret = TRY_DO_RTC_FUNC(rtc_core, set_secs, args); + break; + case RT_DEVICE_CTRL_RTC_GET_TIME_US: + ret = TRY_DO_RTC_FUNC(rtc_core, get_usecs, args); + break; + case RT_DEVICE_CTRL_RTC_SET_TIME_US: + ret = TRY_DO_RTC_FUNC(rtc_core, set_usecs, args); + break; + case RT_DEVICE_CTRL_RTC_GET_ALARM: + ret = TRY_DO_RTC_FUNC(rtc_core, get_alarm, args); + break; + case RT_DEVICE_CTRL_RTC_SET_ALARM: + ret = TRY_DO_RTC_FUNC(rtc_core, set_alarm, args); + break; + default: + break; + } + + return ret; +} +#ifdef RT_USING_DEVICE_OPS +const static struct rt_device_ops rtc_core_ops = +{ + rt_rtc_core_init, + rt_rtc_core_open, + rt_rtc_core_close, + RT_NULL, + RT_NULL, + rt_rtc_core_control, +}; +#endif + +rt_err_t rt_rtc_dev_register(rt_rtc_dev_t *rtc, + const char *name, + rt_uint32_t flag, + void *data) +{ + struct rt_device *device; + RT_ASSERT(rtc != RT_NULL); + + device = &(rtc->parent); + + device->type = RT_Device_Class_RTC; + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + +#ifdef RT_USING_DEVICE_OPS + device->ops = &rtc_core_ops; +#else + device->init = rt_rtc_core_init; + device->open = rt_rtc_core_open; + device->close = rt_rtc_core_close; + device->read = RT_NULL; + device->write = RT_NULL; + device->control = rt_rtc_core_control; +#endif + device->user_data = data; + + /* register a character device */ + return rt_device_register(device, name, flag); +} + diff --git a/components/drivers/sdio/mmc.c b/components/drivers/sdio/mmc.c index d8f3a9e0a5..bebfa39ea2 100644 --- a/components/drivers/sdio/mmc.c +++ b/components/drivers/sdio/mmc.c @@ -122,7 +122,7 @@ static int mmc_get_ext_csd(struct rt_mmcsd_card *card, rt_uint8_t **new_ext_csd) *new_ext_csd = RT_NULL; - if (GET_BITS(card->resp_cid, 122, 4) < 4) + if (GET_BITS(card->resp_csd, 122, 4) < 4) return 0; /* @@ -303,7 +303,7 @@ static int mmc_select_bus_width(struct rt_mmcsd_card *card, rt_uint8_t *ext_csd) unsigned idx, trys, bus_width = 0; int err = 0; - if (GET_BITS(card->resp_cid, 122, 4) < 4) + if (GET_BITS(card->resp_csd, 122, 4) < 4) return 0; /* diff --git a/components/drivers/serial/SConscript b/components/drivers/serial/SConscript index a6eb115919..81d791803a 100644 --- a/components/drivers/serial/SConscript +++ b/components/drivers/serial/SConscript @@ -1,8 +1,14 @@ from building import * -cwd = GetCurrentDir() -src = Glob('*.c') +cwd = GetCurrentDir() CPPPATH = [cwd + '/../include'] -group = DefineGroup('DeviceDrivers', src, depend = ['RT_USING_SERIAL'], CPPPATH = CPPPATH) +group = [] +if GetDepend(['RT_USING_SERIAL']): + if GetDepend(['RT_USING_SERIAL_V2']): + src = Glob('serial_v2.c') + group = DefineGroup('DeviceDrivers', src, depend = ['RT_USING_SERIAL_V2'], CPPPATH = CPPPATH) + else: + src = Glob('serial.c') + group = DefineGroup('DeviceDrivers', src, depend = ['RT_USING_SERIAL'], CPPPATH = CPPPATH) Return('group') diff --git a/components/drivers/serial/serial.c b/components/drivers/serial/serial.c index 2736ceed66..76298ea153 100644 --- a/components/drivers/serial/serial.c +++ b/components/drivers/serial/serial.c @@ -38,6 +38,7 @@ #ifdef RT_USING_POSIX #include #include +#include #ifdef RT_USING_POSIX_TERMIOS #include @@ -954,9 +955,7 @@ static void _tc_flush(struct rt_serial_device *serial, int queue) { RT_ASSERT(RT_NULL != rx_fifo); level = rt_hw_interrupt_disable(); - rt_memset(rx_fifo->buffer, 0, serial->config.bufsz); - rx_fifo->put_index = 0; - rx_fifo->get_index = 0; + rx_fifo->get_index = rx_fifo->put_index; rx_fifo->is_full = RT_FALSE; rt_hw_interrupt_enable(level); } diff --git a/components/drivers/serial/serial_v2.c b/components/drivers/serial/serial_v2.c new file mode 100644 index 0000000000..6e65457a5d --- /dev/null +++ b/components/drivers/serial/serial_v2.c @@ -0,0 +1,1268 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-06-01 KyleChan first version + */ + +#include +#include +#include + +#define DBG_TAG "UART" +#define DBG_LVL DBG_INFO +#include + +#ifdef RT_USING_POSIX +#include +#include +#include + +#ifdef getc +#undef getc +#endif + +#ifdef putc +#undef putc +#endif + +static rt_err_t serial_fops_rx_ind(rt_device_t dev, rt_size_t size) +{ + rt_wqueue_wakeup(&(dev->wait_queue), (void*)POLLIN); + + return RT_EOK; +} + +/* fops for serial */ +static int serial_fops_open(struct dfs_fd *fd) +{ + rt_err_t ret = 0; + rt_uint16_t flags = 0; + rt_device_t device; + + device = (rt_device_t)fd->data; + RT_ASSERT(device != RT_NULL); + + switch (fd->flags & O_ACCMODE) + { + case O_RDONLY: + LOG_D("fops open: O_RDONLY!"); + flags = RT_DEVICE_FLAG_RDONLY; + break; + case O_WRONLY: + LOG_D("fops open: O_WRONLY!"); + flags = RT_DEVICE_FLAG_WRONLY; + break; + case O_RDWR: + LOG_D("fops open: O_RDWR!"); + flags = RT_DEVICE_FLAG_RDWR; + break; + default: + LOG_E("fops open: unknown mode - %d!", fd->flags & O_ACCMODE); + break; + } + + if ((fd->flags & O_ACCMODE) != O_WRONLY) + rt_device_set_rx_indicate(device, serial_fops_rx_ind); + ret = rt_device_open(device, flags); + if (ret == RT_EOK) return 0; + + return ret; +} + +static int serial_fops_close(struct dfs_fd *fd) +{ + rt_device_t device; + + device = (rt_device_t)fd->data; + + rt_device_set_rx_indicate(device, RT_NULL); + rt_device_close(device); + + return 0; +} + +static int serial_fops_ioctl(struct dfs_fd *fd, int cmd, void *args) +{ + rt_device_t device; + + device = (rt_device_t)fd->data; + switch (cmd) + { + case FIONREAD: + break; + case FIONWRITE: + break; + } + + return rt_device_control(device, cmd, args); +} + +static int serial_fops_read(struct dfs_fd *fd, void *buf, size_t count) +{ + int size = 0; + rt_device_t device; + + device = (rt_device_t)fd->data; + + do + { + size = rt_device_read(device, -1, buf, count); + if (size <= 0) + { + if (fd->flags & O_NONBLOCK) + { + size = -EAGAIN; + break; + } + + rt_wqueue_wait(&(device->wait_queue), 0, RT_WAITING_FOREVER); + } + }while (size <= 0); + + return size; +} + +static int serial_fops_write(struct dfs_fd *fd, const void *buf, size_t count) +{ + rt_device_t device; + + device = (rt_device_t)fd->data; + return rt_device_write(device, -1, buf, count); +} + +static int serial_fops_poll(struct dfs_fd *fd, struct rt_pollreq *req) +{ + int mask = 0; + int flags = 0; + rt_device_t device; + struct rt_serial_device *serial; + + device = (rt_device_t)fd->data; + RT_ASSERT(device != RT_NULL); + + serial = (struct rt_serial_device *)device; + + /* only support POLLIN */ + flags = fd->flags & O_ACCMODE; + if (flags == O_RDONLY || flags == O_RDWR) + { + rt_base_t level; + struct rt_serial_rx_fifo* rx_fifo; + + rt_poll_add(&(device->wait_queue), req); + + rx_fifo = (struct rt_serial_rx_fifo*) serial->serial_rx; + + level = rt_hw_interrupt_disable(); + + if (rt_ringbuffer_data_len(&rx_fifo->rb)) + mask |= POLLIN; + rt_hw_interrupt_enable(level); + } + // mask|=POLLOUT; + return mask; +} + +const static struct dfs_file_ops _serial_fops = +{ + serial_fops_open, + serial_fops_close, + serial_fops_ioctl, + serial_fops_read, + serial_fops_write, + RT_NULL, /* flush */ + RT_NULL, /* lseek */ + RT_NULL, /* getdents */ + serial_fops_poll, +}; +#endif + +static rt_size_t rt_serial_get_linear_buffer(struct rt_ringbuffer *rb, + rt_uint8_t **ptr) +{ + rt_size_t size; + + RT_ASSERT(rb != RT_NULL); + + *ptr = RT_NULL; + + /* whether has enough data */ + size = rt_ringbuffer_data_len(rb); + + /* no data */ + if (size == 0) + return 0; + + *ptr = &rb->buffer_ptr[rb->read_index]; + + if(rb->buffer_size - rb->read_index > size) + { + return size; + } + + return rb->buffer_size - rb->read_index; +} + +static rt_size_t rt_serial_update_read_index(struct rt_ringbuffer *rb, + rt_uint16_t read_index) +{ + rt_size_t size; + + RT_ASSERT(rb != RT_NULL); + + /* whether has enough data */ + size = rt_ringbuffer_data_len(rb); + + /* no data */ + if (size == 0) + return 0; + + /* less data */ + if(size < read_index) + read_index = size; + + if(rb->buffer_size - rb->read_index > read_index) + { + rb->read_index += read_index; + return read_index; + } + + read_index = rb->buffer_size - rb->read_index; + + /* we are going into the other side of the mirror */ + rb->read_mirror = ~rb->read_mirror; + rb->read_index = 0; + + return read_index; +} + +static rt_size_t rt_serial_update_write_index(struct rt_ringbuffer *rb, + rt_uint16_t write_index) +{ + rt_uint16_t size; + RT_ASSERT(rb != RT_NULL); + + /* whether has enough space */ + size = rt_ringbuffer_space_len(rb); + + /* no space */ + if (size == 0) + return 0; + + /* drop some data */ + if (size < write_index) + write_index = size; + + if (rb->buffer_size - rb->write_index > write_index) + { + /* this should not cause overflow because there is enough space for + * length of data in current mirror */ + rb->write_index += write_index; + return write_index; + } + + /* we are going into the other side of the mirror */ + rb->write_mirror = ~rb->write_mirror; + rb->write_index = write_index - (rb->buffer_size - rb->write_index); + + return write_index; +} + + +/** + * @brief Serial polling receive data routine, This function will receive data + * in a continuous loop by one by one byte. + * @param dev The pointer of device driver structure + * @param pos Empty parameter. + * @param buffer Receive data buffer. + * @param size Receive data buffer length. + * @return Return the final length of data received. + */ +rt_size_t _serial_poll_rx(struct rt_device *dev, + rt_off_t pos, + void *buffer, + rt_size_t size) +{ + struct rt_serial_device *serial; + rt_size_t getc_size; + int getc_element; /* Gets one byte of data received */ + rt_uint8_t *getc_buffer; /* Pointer to the receive data buffer */ + + RT_ASSERT(dev != RT_NULL); + + serial = (struct rt_serial_device *)dev; + RT_ASSERT(serial != RT_NULL); + getc_buffer = (rt_uint8_t *)buffer; + getc_size = size; + + while(size) + { + getc_element = serial->ops->getc(serial); + if (getc_element == -1) break; + + *getc_buffer = getc_element; + + ++ getc_buffer; + -- size; + + if (serial->parent.open_flag & RT_DEVICE_FLAG_STREAM) + { + /* If open_flag satisfies RT_DEVICE_FLAG_STREAM + * and the received character is '\n', exit the loop directly */ + if (getc_element == '\n') break; + } + } + + return getc_size - size; +} + +/** + * @brief Serial polling transmit data routines, This function will transmit + * data in a continuous loop by one by one byte. + * @param dev The pointer of device driver structure + * @param pos Empty parameter. + * @param buffer Transmit data buffer. + * @param size Transmit data buffer length. + * @return Return the final length of data received. + */ +rt_size_t _serial_poll_tx(struct rt_device *dev, + rt_off_t pos, + const void *buffer, + rt_size_t size) +{ + struct rt_serial_device *serial; + rt_size_t putc_size; + rt_uint8_t *putc_buffer; /* Pointer to the transmit data buffer */ + RT_ASSERT(dev != RT_NULL); + + serial = (struct rt_serial_device *)dev; + RT_ASSERT(serial != RT_NULL); + + putc_buffer = (rt_uint8_t *)buffer; + putc_size = size; + + while (size) + { + if (serial->parent.open_flag & RT_DEVICE_FLAG_STREAM) + { + /* If open_flag satisfies RT_DEVICE_FLAG_STREAM and the received character is '\n', + * inserts '\r' character before '\n' character for the effect of carriage return newline */ + if (*putc_buffer == '\n') + serial->ops->putc(serial, '\r'); + } + serial->ops->putc(serial, *putc_buffer); + + ++ putc_buffer; + -- size; + } + + return putc_size - size; +} + +/** + * @brief Serial receive data routines, This function will receive + * data by using fifo + * @param dev The pointer of device driver structure + * @param pos Empty parameter. + * @param buffer Receive data buffer. + * @param size Receive data buffer length. + * @return Return the final length of data received. + */ +static rt_size_t _serial_fifo_rx(struct rt_device *dev, + rt_off_t pos, + void *buffer, + rt_size_t size) +{ + struct rt_serial_device *serial; + struct rt_serial_rx_fifo *rx_fifo; + rt_base_t level; + rt_size_t recv_len; /* The length of data from the ringbuffer */ + + RT_ASSERT(dev != RT_NULL); + if (size == 0) return 0; + + serial = (struct rt_serial_device *)dev; + + RT_ASSERT((serial != RT_NULL) && (buffer != RT_NULL)); + + rx_fifo = (struct rt_serial_rx_fifo *) serial->serial_rx; + + if (dev->open_flag & RT_SERIAL_RX_BLOCKING) + { + if (size > serial->config.rx_bufsz) + { + LOG_W("(%s) serial device received data:[%d] larger than " + "rx_bufsz:[%d], please increase the BSP_UARTx_RX_BUFSIZE option", + dev->parent.name, size, serial->config.rx_bufsz); + + return 0; + } + /* Get the length of the data from the ringbuffer */ + recv_len = rt_ringbuffer_data_len(&(rx_fifo->rb)); + + if (recv_len < size) + { + /* When recv_len is less than size, rx_cpt_index is updated to the size + * and rt_current_thread is suspend until rx_cpt_index is equal to 0 */ + rx_fifo->rx_cpt_index = size; + rt_completion_wait(&(rx_fifo->rx_cpt), RT_WAITING_FOREVER); + } + } + + /* This part of the code is open_flag as RT_SERIAL_RX_NON_BLOCKING */ + + level = rt_hw_interrupt_disable(); + /* When open_flag is RT_SERIAL_RX_NON_BLOCKING, + * the data is retrieved directly from the ringbuffer and returned */ + recv_len = rt_ringbuffer_get(&(rx_fifo->rb), buffer, size); + + rt_hw_interrupt_enable(level); + + return recv_len; +} + +/** + * @brief Serial transmit data routines, This function will transmit + * data by using blocking_nbuf. + * @param dev The pointer of device driver structure + * @param pos Empty parameter. + * @param buffer Transmit data buffer. + * @param size Transmit data buffer length. + * @return Return the final length of data transmit. + */ +static rt_size_t _serial_fifo_tx_blocking_nbuf(struct rt_device *dev, + rt_off_t pos, + const void *buffer, + rt_size_t size) +{ + struct rt_serial_device *serial; + struct rt_serial_tx_fifo *tx_fifo = RT_NULL; + + RT_ASSERT(dev != RT_NULL); + if (size == 0) return 0; + + serial = (struct rt_serial_device *)dev; + RT_ASSERT((serial != RT_NULL) && (buffer != RT_NULL)); + tx_fifo = (struct rt_serial_tx_fifo *) serial->serial_tx; + RT_ASSERT(tx_fifo != RT_NULL); + + /* When serial transmit in tx_blocking mode, + * if the activated mode is RT_TRUE, it will return directly */ + if (tx_fifo->activated == RT_TRUE) return 0; + + tx_fifo->activated = RT_TRUE; + /* Call the transmit interface for transmission */ + serial->ops->transmit(serial, + (rt_uint8_t *)buffer, + size, + RT_SERIAL_TX_BLOCKING); + /* Waiting for the transmission to complete */ + rt_completion_wait(&(tx_fifo->tx_cpt), RT_WAITING_FOREVER); + + return size; +} + +/** + * @brief Serial transmit data routines, This function will transmit + * data by using blocking_buf. + * @param dev The pointer of device driver structure + * @param pos Empty parameter. + * @param buffer Transmit data buffer. + * @param size Transmit data buffer length. + * @return Return the final length of data transmit. + */ +static rt_size_t _serial_fifo_tx_blocking_buf(struct rt_device *dev, + rt_off_t pos, + const void *buffer, + rt_size_t size) +{ + struct rt_serial_device *serial; + struct rt_serial_tx_fifo *tx_fifo = RT_NULL; + + RT_ASSERT(dev != RT_NULL); + if (size == 0) return 0; + + serial = (struct rt_serial_device *)dev; + RT_ASSERT((serial != RT_NULL) && (buffer != RT_NULL)); + tx_fifo = (struct rt_serial_tx_fifo *) serial->serial_tx; + RT_ASSERT(tx_fifo != RT_NULL); + /* When serial transmit in tx_blocking mode, + * if the activated mode is RT_TRUE, it will return directly */ + if (tx_fifo->activated == RT_TRUE) return 0; + + tx_fifo->activated = RT_TRUE; + rt_size_t length = size; + rt_size_t offset = 0; + + while (size) + { + /* Copy one piece of data into the ringbuffer at a time + * until the length of the data is equal to size */ + tx_fifo->put_size = rt_ringbuffer_put(&(tx_fifo->rb), + (rt_uint8_t *)buffer + offset, + size); + + offset += tx_fifo->put_size; + size -= tx_fifo->put_size; + /* Call the transmit interface for transmission */ + serial->ops->transmit(serial, + (rt_uint8_t *)buffer + offset, + tx_fifo->put_size, + RT_SERIAL_TX_BLOCKING); + /* Waiting for the transmission to complete */ + rt_completion_wait(&(tx_fifo->tx_cpt), RT_WAITING_FOREVER); + } + + return length; +} + +/** + * @brief Serial transmit data routines, This function will transmit + * data by using nonblocking. + * @param dev The pointer of device driver structure + * @param pos Empty parameter. + * @param buffer Transmit data buffer. + * @param size Transmit data buffer length. + * @return Return the final length of data transmit. + */ +static rt_size_t _serial_fifo_tx_nonblocking(struct rt_device *dev, + rt_off_t pos, + const void *buffer, + rt_size_t size) +{ + struct rt_serial_device *serial; + struct rt_serial_tx_fifo *tx_fifo; + rt_base_t level; + rt_size_t length; + + RT_ASSERT(dev != RT_NULL); + if (size == 0) return 0; + + serial = (struct rt_serial_device *)dev; + RT_ASSERT((serial != RT_NULL) && (buffer != RT_NULL)); + tx_fifo = (struct rt_serial_tx_fifo *) serial->serial_tx; + + level = rt_hw_interrupt_disable(); + + if (tx_fifo->activated == RT_FALSE) + { + /* When serial transmit in tx_non_blocking mode, if the activated mode is RT_FALSE, + * start copying data into the ringbuffer */ + tx_fifo->activated = RT_TRUE; + /* Copying data into the ringbuffer */ + length = rt_ringbuffer_put(&(tx_fifo->rb), buffer, size); + + rt_hw_interrupt_enable(level); + + rt_uint8_t *put_ptr = RT_NULL; + /* Get the linear length buffer from rinbuffer */ + tx_fifo->put_size = rt_serial_get_linear_buffer(&(tx_fifo->rb), &put_ptr); + /* Call the transmit interface for transmission */ + serial->ops->transmit(serial, + put_ptr, + tx_fifo->put_size, + RT_SERIAL_TX_NON_BLOCKING); + /* In tx_nonblocking mode, there is no need to call rt_completion_wait() APIs to wait + * for the rt_current_thread to resume */ + return length; + } + + /* If the activated mode is RT_FALSE, it means that serial device is transmitting, + * where only the data in the ringbuffer and there is no need to call the transmit() API. + * Note that this part of the code requires disable interrupts + * to prevent multi thread reentrant */ + + /* Copying data into the ringbuffer */ + length = rt_ringbuffer_put(&(tx_fifo->rb), buffer, size); + + rt_hw_interrupt_enable(level); + + return length; +} + + +/** + * @brief Enable serial transmit mode. + * @param dev The pointer of device driver structure + * @param rx_oflag The flag of that the serial port opens. + * @return Return the status of the operation. + */ +static rt_err_t rt_serial_tx_enable(struct rt_device *dev, + rt_uint16_t tx_oflag) +{ + struct rt_serial_device *serial; + struct rt_serial_tx_fifo *tx_fifo = RT_NULL; + + RT_ASSERT(dev != RT_NULL); + serial = (struct rt_serial_device *)dev; + + if (serial->config.tx_bufsz == 0) + { + /* Cannot use RT_SERIAL_TX_NON_BLOCKING when tx_bufsz is 0 */ + if (tx_oflag == RT_SERIAL_TX_NON_BLOCKING) + { + LOG_E("(%s) serial device with misconfigure: tx_bufsz = 0", + dev->parent.name); + return -RT_EINVAL; + } + +#ifndef RT_USING_DEVICE_OPS + dev->write = _serial_poll_tx; +#endif + + dev->open_flag |= RT_SERIAL_TX_BLOCKING; + return RT_EOK; + } + /* Limits the minimum value of tx_bufsz */ + if (serial->config.tx_bufsz < RT_SERIAL_TX_MINBUFSZ) + serial->config.tx_bufsz = RT_SERIAL_TX_MINBUFSZ; + + if (tx_oflag == RT_SERIAL_TX_BLOCKING) + { + /* When using RT_SERIAL_TX_BLOCKING, it is necessary to determine + * whether serial device needs to use buffer */ + rt_err_t optmode; /* The operating mode used by serial device */ + /* Call the Control() API to get the operating mode */ + optmode = serial->ops->control(serial, + RT_DEVICE_CHECK_OPTMODE, + (void *)RT_DEVICE_FLAG_TX_BLOCKING); + if (optmode == RT_SERIAL_TX_BLOCKING_BUFFER) + { + /* If use RT_SERIAL_TX_BLOCKING_BUFFER, the ringbuffer is initialized */ + tx_fifo = (struct rt_serial_tx_fifo *) rt_malloc + (sizeof(struct rt_serial_tx_fifo) + serial->config.tx_bufsz); + RT_ASSERT(tx_fifo != RT_NULL); + + rt_ringbuffer_init(&(tx_fifo->rb), + tx_fifo->buffer, + serial->config.tx_bufsz); + serial->serial_tx = tx_fifo; + +#ifndef RT_USING_DEVICE_OPS + dev->write = _serial_fifo_tx_blocking_buf; +#endif + } + else + { + /* If not use RT_SERIAL_TX_BLOCKING_BUFFER, + * the control() API is called to configure the serial device */ + tx_fifo = (struct rt_serial_tx_fifo*) rt_malloc + (sizeof(struct rt_serial_tx_fifo)); + RT_ASSERT(tx_fifo != RT_NULL); + + serial->serial_tx = tx_fifo; + +#ifndef RT_USING_DEVICE_OPS + dev->write = _serial_fifo_tx_blocking_nbuf; +#endif + + /* Call the control() API to configure the serial device by RT_SERIAL_TX_BLOCKING*/ + serial->ops->control(serial, + RT_DEVICE_CTRL_CONFIG, + (void *)RT_SERIAL_TX_BLOCKING); + } + + tx_fifo->activated = RT_FALSE; + tx_fifo->put_size = 0; + rt_completion_init(&(tx_fifo->tx_cpt)); + dev->open_flag |= RT_SERIAL_TX_BLOCKING; + + return RT_EOK; + } + /* When using RT_SERIAL_TX_NON_BLOCKING, ringbuffer needs to be initialized, + * and initialize the tx_fifo->activated value is RT_FALSE. + */ + tx_fifo = (struct rt_serial_tx_fifo *) rt_malloc + (sizeof(struct rt_serial_tx_fifo) + serial->config.tx_bufsz); + RT_ASSERT(tx_fifo != RT_NULL); + + tx_fifo->activated = RT_FALSE; + tx_fifo->put_size = 0; + rt_ringbuffer_init(&(tx_fifo->rb), + tx_fifo->buffer, + serial->config.tx_bufsz); + serial->serial_tx = tx_fifo; + +#ifndef RT_USING_DEVICE_OPS + dev->write = _serial_fifo_tx_nonblocking; +#endif + + dev->open_flag |= RT_SERIAL_TX_NON_BLOCKING; + /* Call the control() API to configure the serial device by RT_SERIAL_TX_NON_BLOCKING*/ + serial->ops->control(serial, + RT_DEVICE_CTRL_CONFIG, + (void *)RT_SERIAL_TX_NON_BLOCKING); + + return RT_EOK; +} + + +/** + * @brief Enable serial receive mode. + * @param dev The pointer of device driver structure + * @param rx_oflag The flag of that the serial port opens. + * @return Return the status of the operation. + */ +static rt_err_t rt_serial_rx_enable(struct rt_device *dev, + rt_uint16_t rx_oflag) +{ + struct rt_serial_device *serial; + struct rt_serial_rx_fifo *rx_fifo = RT_NULL; + + RT_ASSERT(dev != RT_NULL); + serial = (struct rt_serial_device *)dev; + + if (serial->config.rx_bufsz == 0) + { + /* Cannot use RT_SERIAL_RX_NON_BLOCKING when rx_bufsz is 0 */ + if (rx_oflag == RT_SERIAL_RX_NON_BLOCKING) + { + LOG_E("(%s) serial device with misconfigure: rx_bufsz = 0", + dev->parent.name); + return -RT_EINVAL; + } + +#ifndef RT_USING_DEVICE_OPS + dev->read = _serial_poll_rx; +#endif + + dev->open_flag |= RT_SERIAL_RX_BLOCKING; + return RT_EOK; + } + /* Limits the minimum value of rx_bufsz */ + if (serial->config.rx_bufsz < RT_SERIAL_RX_MINBUFSZ) + serial->config.rx_bufsz = RT_SERIAL_RX_MINBUFSZ; + + rx_fifo = (struct rt_serial_rx_fifo *) rt_malloc + (sizeof(struct rt_serial_rx_fifo) + serial->config.rx_bufsz); + + RT_ASSERT(rx_fifo != RT_NULL); + rt_ringbuffer_init(&(rx_fifo->rb), rx_fifo->buffer, serial->config.rx_bufsz); + + serial->serial_rx = rx_fifo; + +#ifndef RT_USING_DEVICE_OPS + dev->read = _serial_fifo_rx; +#endif + + if (rx_oflag == RT_SERIAL_RX_NON_BLOCKING) + { + dev->open_flag |= RT_SERIAL_RX_NON_BLOCKING; + /* Call the control() API to configure the serial device by RT_SERIAL_RX_NON_BLOCKING*/ + serial->ops->control(serial, + RT_DEVICE_CTRL_CONFIG, + (void *) RT_SERIAL_RX_NON_BLOCKING); + + return RT_EOK; + } + /* When using RT_SERIAL_RX_BLOCKING, rt_completion_init() and rx_cpt_index are initialized */ + rx_fifo->rx_cpt_index = 0; + rt_completion_init(&(rx_fifo->rx_cpt)); + dev->open_flag |= RT_SERIAL_RX_BLOCKING; + /* Call the control() API to configure the serial device by RT_SERIAL_RX_BLOCKING*/ + serial->ops->control(serial, + RT_DEVICE_CTRL_CONFIG, + (void *) RT_SERIAL_RX_BLOCKING); + + return RT_EOK; +} + +/** + * @brief Disable serial receive mode. + * @param dev The pointer of device driver structure + * @param rx_oflag The flag of that the serial port opens. + * @return Return the status of the operation. + */ +static rt_err_t rt_serial_rx_disable(struct rt_device *dev, + rt_uint16_t rx_oflag) +{ + struct rt_serial_device *serial; + struct rt_serial_rx_fifo *rx_fifo; + + RT_ASSERT(dev != RT_NULL); + serial = (struct rt_serial_device *)dev; + +#ifndef RT_USING_DEVICE_OPS + dev->read = RT_NULL; +#endif + + if (serial->serial_rx == RT_NULL) return RT_EOK; + + do + { + if (rx_oflag == RT_SERIAL_RX_NON_BLOCKING) + { + dev->open_flag &= ~ RT_SERIAL_RX_NON_BLOCKING; + serial->ops->control(serial, + RT_DEVICE_CTRL_CLR_INT, + (void *)RT_SERIAL_RX_NON_BLOCKING); + break; + } + + dev->open_flag &= ~ RT_SERIAL_RX_BLOCKING; + serial->ops->control(serial, + RT_DEVICE_CTRL_CLR_INT, + (void *)RT_SERIAL_RX_BLOCKING); + } while (0); + + rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; + RT_ASSERT(rx_fifo != RT_NULL); + rt_free(rx_fifo); + serial->serial_rx = RT_NULL; + + return RT_EOK; +} + +/** + * @brief Disable serial tranmit mode. + * @param dev The pointer of device driver structure + * @param rx_oflag The flag of that the serial port opens. + * @return Return the status of the operation. + */ +static rt_err_t rt_serial_tx_disable(struct rt_device *dev, + rt_uint16_t tx_oflag) +{ + struct rt_serial_device *serial; + struct rt_serial_tx_fifo *tx_fifo; + + RT_ASSERT(dev != RT_NULL); + serial = (struct rt_serial_device *)dev; + +#ifndef RT_USING_DEVICE_OPS + dev->write = RT_NULL; +#endif + + if (serial->serial_tx == RT_NULL) return RT_EOK; + + tx_fifo = (struct rt_serial_tx_fifo *)serial->serial_tx; + RT_ASSERT(tx_fifo != RT_NULL); + + do + { + if (tx_oflag == RT_SERIAL_TX_NON_BLOCKING) + { + dev->open_flag &= ~ RT_SERIAL_TX_NON_BLOCKING; + + serial->ops->control(serial, + RT_DEVICE_CTRL_CLR_INT, + (void *)RT_SERIAL_TX_NON_BLOCKING); + break; + } + + rt_completion_done(&(tx_fifo->tx_cpt)); + dev->open_flag &= ~ RT_SERIAL_TX_BLOCKING; + serial->ops->control(serial, + RT_DEVICE_CTRL_CLR_INT, + (void *)RT_SERIAL_TX_BLOCKING); + } while (0); + + rt_free(tx_fifo); + serial->serial_tx = RT_NULL; + + return RT_EOK; +} + +/** + * @brief Initialize the serial device. + * @param dev The pointer of device driver structure + * @return Return the status of the operation. + */ +static rt_err_t rt_serial_init(struct rt_device *dev) +{ + rt_err_t result = RT_EOK; + struct rt_serial_device *serial; + + RT_ASSERT(dev != RT_NULL); + serial = (struct rt_serial_device *)dev; + + /* initialize rx/tx */ + serial->serial_rx = RT_NULL; + serial->serial_tx = RT_NULL; + + /* apply configuration */ + if (serial->ops->configure) + result = serial->ops->configure(serial, &serial->config); + + return result; +} + +/** + * @brief Open the serial device. + * @param dev The pointer of device driver structure + * @param oflag The flag of that the serial port opens. + * @return Return the status of the operation. + */ +static rt_err_t rt_serial_open(struct rt_device *dev, rt_uint16_t oflag) +{ + struct rt_serial_device *serial; + + RT_ASSERT(dev != RT_NULL); + serial = (struct rt_serial_device *)dev; + + /* Check that the device has been turned on */ + if ((dev->open_flag) & (15 << 12)) + { + LOG_D("(%s) serial device has already been opened, it will run in its original configuration", dev->parent.name); + return RT_EOK; + } + + LOG_D("open serial device: 0x%08x with open flag: 0x%04x", + dev, oflag); + + /* By default, the receive mode of a serial devide is RT_SERIAL_RX_NON_BLOCKING */ + if ((oflag & RT_SERIAL_RX_BLOCKING) == RT_SERIAL_RX_BLOCKING) + dev->open_flag |= RT_SERIAL_RX_BLOCKING; + else + dev->open_flag |= RT_SERIAL_RX_NON_BLOCKING; + + /* By default, the transmit mode of a serial devide is RT_SERIAL_TX_BLOCKING */ + if ((oflag & RT_SERIAL_TX_NON_BLOCKING) == RT_SERIAL_TX_NON_BLOCKING) + dev->open_flag |= RT_SERIAL_TX_NON_BLOCKING; + else + dev->open_flag |= RT_SERIAL_TX_BLOCKING; + + /* set steam flag */ + if ((oflag & RT_DEVICE_FLAG_STREAM) || + (dev->open_flag & RT_DEVICE_FLAG_STREAM)) + dev->open_flag |= RT_DEVICE_FLAG_STREAM; + + /* initialize the Rx structure according to open flag */ + if (serial->serial_rx == RT_NULL) + rt_serial_rx_enable(dev, dev->open_flag & + (RT_SERIAL_RX_BLOCKING | RT_SERIAL_RX_NON_BLOCKING)); + + /* initialize the Tx structure according to open flag */ + if (serial->serial_tx == RT_NULL) + rt_serial_tx_enable(dev, dev->open_flag & + (RT_SERIAL_TX_BLOCKING | RT_SERIAL_TX_NON_BLOCKING)); + + return RT_EOK; +} + + +/** + * @brief Close the serial device. + * @param dev The pointer of device driver structure + * @return Return the status of the operation. + */ +static rt_err_t rt_serial_close(struct rt_device *dev) +{ + struct rt_serial_device *serial; + + RT_ASSERT(dev != RT_NULL); + serial = (struct rt_serial_device *)dev; + + /* this device has more reference count */ + if (dev->ref_count > 1) return -RT_ERROR; + /* Disable serial receive mode. */ + rt_serial_rx_disable(dev, dev->open_flag & + (RT_SERIAL_RX_BLOCKING | RT_SERIAL_RX_NON_BLOCKING)); + /* Disable serial tranmit mode. */ + rt_serial_tx_disable(dev, dev->open_flag & + (RT_SERIAL_TX_BLOCKING | RT_SERIAL_TX_NON_BLOCKING)); + + /* Clear the callback function */ + serial->parent.rx_indicate = RT_NULL; + serial->parent.tx_complete = RT_NULL; + + /* Call the control() API to close the serial device */ + serial->ops->control(serial, RT_DEVICE_CTRL_CLOSE, RT_NULL); + dev->flag &= ~RT_DEVICE_FLAG_ACTIVATED; + + return RT_EOK; +} + +/** + * @brief Control the serial device. + * @param dev The pointer of device driver structure + * @param cmd The command value that controls the serial device + * @param args The parameter value that controls the serial device + * @return Return the status of the operation. + */ +static rt_err_t rt_serial_control(struct rt_device *dev, + int cmd, + void *args) +{ + rt_err_t ret = RT_EOK; + struct rt_serial_device *serial; + + RT_ASSERT(dev != RT_NULL); + serial = (struct rt_serial_device *)dev; + + switch (cmd) + { + case RT_DEVICE_CTRL_SUSPEND: + /* suspend device */ + dev->flag |= RT_DEVICE_FLAG_SUSPENDED; + break; + + case RT_DEVICE_CTRL_RESUME: + /* resume device */ + dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; + break; + + case RT_DEVICE_CTRL_CONFIG: + if (args != RT_NULL) + { + struct serial_configure *pconfig = (struct serial_configure *) args; + if (serial->parent.ref_count) + { + /*can not change buffer size*/ + return -RT_EBUSY; + } + /* set serial configure */ + serial->config = *pconfig; + serial->ops->configure(serial, + (struct serial_configure *) args); + } + + break; + + default : + /* control device */ + ret = serial->ops->control(serial, cmd, args); + break; + } + + return ret; +} + +#ifdef RT_USING_DEVICE_OPS +static rt_size_t rt_serial_read(struct rt_device *dev, + rt_off_t pos, + void *buffer, + rt_size_t size) +{ + struct rt_serial_device *serial; + + RT_ASSERT(dev != RT_NULL); + if (size == 0) return 0; + + serial = (struct rt_serial_device *)dev; + + if (serial->config.rx_bufsz) + { + return _serial_fifo_rx(dev, pos, buffer, size); + } + + return _serial_poll_rx(dev, pos, buffer, size); +} + + +static rt_size_t rt_serial_write(struct rt_device *dev, + rt_off_t pos, + const void *buffer, + rt_size_t size) +{ + struct rt_serial_device *serial; + struct rt_serial_tx_fifo *tx_fifo; + + RT_ASSERT(dev != RT_NULL); + if (size == 0) return 0; + + serial = (struct rt_serial_device *)dev; + RT_ASSERT((serial != RT_NULL) && (buffer != RT_NULL)); + tx_fifo = (struct rt_serial_tx_fifo *) serial->serial_tx; + + if (serial->config.tx_bufsz == 0) + { + return _serial_poll_tx(dev, pos, buffer, size); + } + + if (dev->open_flag | RT_SERIAL_TX_BLOCKING) + { + if ((tx_fifo->rb.buffer_ptr) == RT_NULL) + { + return _serial_fifo_tx_blocking_nbuf(dev, pos, buffer, size); + } + + return _serial_fifo_tx_blocking_buf(dev, pos, buffer, size); + } + + return _serial_fifo_tx_nonblocking(dev, pos, buffer, size); +} + +const static struct rt_device_ops serial_ops = +{ + rt_serial_init, + rt_serial_open, + rt_serial_close, + rt_serial_read, + rt_serial_write, + rt_serial_control +}; +#endif + +/** + * @brief Register the serial device. + * @param serial RT-thread serial device. + * @param name The device driver's name + * @param flag The capabilities flag of device. + * @param data The device driver's data. + * @return Return the status of the operation. + */ +rt_err_t rt_hw_serial_register(struct rt_serial_device *serial, + const char *name, + rt_uint32_t flag, + void *data) +{ + rt_err_t ret; + struct rt_device *device; + RT_ASSERT(serial != RT_NULL); + + device = &(serial->parent); + + device->type = RT_Device_Class_Char; + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + +#ifdef RT_USING_DEVICE_OPS + device->ops = &serial_ops; +#else + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = RT_NULL; + device->write = RT_NULL; + device->control = rt_serial_control; +#endif + device->user_data = data; + + /* register a character device */ + ret = rt_device_register(device, name, flag); + +#if defined(RT_USING_POSIX) + /* set fops */ + device->fops = &_serial_fops; +#endif + return ret; +} + +/** + * @brief ISR for serial interrupt + * @param serial RT-thread serial device. + * @param event ISR event type. + */ +void rt_hw_serial_isr(struct rt_serial_device *serial, int event) +{ + RT_ASSERT(serial != RT_NULL); + + switch (event & 0xff) + { + /* Interrupt receive event */ + case RT_SERIAL_EVENT_RX_IND: + case RT_SERIAL_EVENT_RX_DMADONE: + { + struct rt_serial_rx_fifo *rx_fifo; + rt_size_t rx_length = 0; + rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; + RT_ASSERT(rx_fifo != RT_NULL); + + /* If the event is RT_SERIAL_EVENT_RX_IND, rx_length is equal to 0 */ + rx_length = (event & (~0xff)) >> 8; + + if (rx_length) + rt_serial_update_write_index(&(rx_fifo->rb), rx_length); + + /* Get the length of the data from the ringbuffer */ + rx_length = rt_ringbuffer_data_len(&rx_fifo->rb); + if (rx_length == 0) break; + + if (serial->parent.open_flag & RT_SERIAL_RX_BLOCKING) + { + if (rx_fifo->rx_cpt_index && rx_length >= rx_fifo->rx_cpt_index ) + { + rx_fifo->rx_cpt_index = 0; + rt_completion_done(&(rx_fifo->rx_cpt)); + } + } + /* Trigger the receiving completion callback */ + if (serial->parent.rx_indicate != RT_NULL) + serial->parent.rx_indicate(&(serial->parent), rx_length); + break; + } + + /* Interrupt transmit event */ + case RT_SERIAL_EVENT_TX_DONE: + { + struct rt_serial_tx_fifo *tx_fifo; + rt_size_t tx_length = 0; + tx_fifo = (struct rt_serial_tx_fifo *)serial->serial_tx; + RT_ASSERT(tx_fifo != RT_NULL); + + /* Get the length of the data from the ringbuffer */ + tx_length = rt_ringbuffer_data_len(&tx_fifo->rb); + /* If there is no data in tx_ringbuffer, + * then the transmit completion callback is triggered*/ + if (tx_length == 0) + { + tx_fifo->activated = RT_FALSE; + /* Trigger the transmit completion callback */ + if (serial->parent.tx_complete != RT_NULL) + serial->parent.tx_complete(&serial->parent, RT_NULL); + + if (serial->parent.open_flag & RT_SERIAL_TX_BLOCKING) + rt_completion_done(&(tx_fifo->tx_cpt)); + + break; + } + + /* Call the transmit interface for transmission again */ + /* Note that in interrupt mode, tx_fifo->buffer and tx_length + * are inactive parameters */ + serial->ops->transmit(serial, + tx_fifo->buffer, + tx_length, + serial->parent.open_flag & ( \ + RT_SERIAL_TX_BLOCKING | \ + RT_SERIAL_TX_NON_BLOCKING)); + break; + } + + case RT_SERIAL_EVENT_TX_DMADONE: + { + struct rt_serial_tx_fifo *tx_fifo; + tx_fifo = (struct rt_serial_tx_fifo *)serial->serial_tx; + RT_ASSERT(tx_fifo != RT_NULL); + + tx_fifo->activated = RT_FALSE; + + /* Trigger the transmit completion callback */ + if (serial->parent.tx_complete != RT_NULL) + serial->parent.tx_complete(&serial->parent, RT_NULL); + + if (serial->parent.open_flag & RT_SERIAL_TX_BLOCKING) + { + rt_completion_done(&(tx_fifo->tx_cpt)); + break; + } + + rt_serial_update_read_index(&tx_fifo->rb, tx_fifo->put_size); + /* Get the length of the data from the ringbuffer. + * If there is some data in tx_ringbuffer, + * then call the transmit interface for transmission again */ + if (rt_ringbuffer_data_len(&tx_fifo->rb)) + { + tx_fifo->activated = RT_TRUE; + + rt_uint8_t *put_ptr = RT_NULL; + /* Get the linear length buffer from rinbuffer */ + tx_fifo->put_size = rt_serial_get_linear_buffer(&(tx_fifo->rb), &put_ptr); + /* Call the transmit interface for transmission again */ + serial->ops->transmit(serial, + put_ptr, + tx_fifo->put_size, + RT_SERIAL_TX_NON_BLOCKING); + } + + break; + } + + default: + break; + } +} diff --git a/components/drivers/src/pipe.c b/components/drivers/src/pipe.c index 236c1ffec7..7fa5eb067d 100644 --- a/components/drivers/src/pipe.c +++ b/components/drivers/src/pipe.c @@ -11,11 +11,13 @@ #include #include #include +#include -#if defined(RT_USING_POSIX) +#ifdef RT_USING_POSIX #include #include #include +#include static int pipe_fops_open(struct dfs_fd *fd) { @@ -374,7 +376,7 @@ rt_size_t rt_pipe_read(rt_device_t device, rt_off_t pos, void *buffer, rt_size_t if (device == RT_NULL) { - rt_set_errno(-EINVAL); + rt_set_errno(EINVAL); return 0; } if (count == 0) return 0; @@ -402,7 +404,7 @@ rt_size_t rt_pipe_write(rt_device_t device, rt_off_t pos, const void *buffer, rt if (device == RT_NULL) { - rt_set_errno(-EINVAL); + rt_set_errno(EINVAL); return 0; } if (count == 0) return 0; @@ -516,12 +518,12 @@ int rt_pipe_delete(const char *name) } else { - result = -ENODEV; + result = -RT_EINVAL; } } else { - result = -ENODEV; + result = -RT_EINVAL; } return result; diff --git a/components/drivers/src/workqueue.c b/components/drivers/src/workqueue.c index f195dad927..065c505015 100644 --- a/components/drivers/src/workqueue.c +++ b/components/drivers/src/workqueue.c @@ -358,7 +358,7 @@ rt_err_t rt_work_cancel(struct rt_work *work) return rt_workqueue_cancel_work(sys_workq, work); } -int rt_work_sys_workqueue_init(void) +static int rt_work_sys_workqueue_init(void) { if (sys_workq != RT_NULL) return RT_EOK; @@ -370,5 +370,5 @@ int rt_work_sys_workqueue_init(void) return RT_EOK; } INIT_PREV_EXPORT(rt_work_sys_workqueue_init); -#endif -#endif +#endif /* RT_USING_SYSTEM_WORKQUEUE */ +#endif /* RT_USING_HEAP */ diff --git a/components/finsh/cmd.c b/components/finsh/cmd.c index 4c76ab7395..9bbcc440cf 100644 --- a/components/finsh/cmd.c +++ b/components/finsh/cmd.c @@ -175,8 +175,8 @@ long list_thread(void) maxlen = RT_NAME_MAX; #ifdef RT_USING_SMP - rt_kprintf("%-*.s cpu pri status sp stack size max used left tick error\n", maxlen, item_title); object_split(maxlen); - rt_kprintf( " --- --- ------- ---------- ---------- ------ ---------- ---\n"); + rt_kprintf("%-*.s cpu bind pri status sp stack size max used left tick error\n", maxlen, item_title); object_split(maxlen); + rt_kprintf( " --- ---- --- ------- ---------- ---------- ------ ---------- ---\n"); #else rt_kprintf("%-*.s pri status sp stack size max used left tick error\n", maxlen, item_title); object_split(maxlen); rt_kprintf( " --- ------- ---------- ---------- ------ ---------- ---\n"); @@ -211,9 +211,9 @@ long list_thread(void) #ifdef RT_USING_SMP if (thread->oncpu != RT_CPU_DETACHED) - rt_kprintf("%-*.*s %3d %3d ", maxlen, RT_NAME_MAX, thread->name, thread->oncpu, thread->current_priority); + rt_kprintf("%-*.*s %3d %3d %4d ", maxlen, RT_NAME_MAX, thread->name, thread->oncpu, thread->bind_cpu, thread->current_priority); else - rt_kprintf("%-*.*s N/A %3d ", maxlen, RT_NAME_MAX, thread->name, thread->current_priority); + rt_kprintf("%-*.*s N/A %3d %4d ", maxlen, RT_NAME_MAX, thread->name, thread->bind_cpu, thread->current_priority); #else rt_kprintf("%-*.*s %3d ", maxlen, RT_NAME_MAX, thread->name, thread->current_priority); diff --git a/components/finsh/msh_file.c b/components/finsh/msh_file.c index 459d77af4e..3f21cc6f34 100644 --- a/components/finsh/msh_file.c +++ b/components/finsh/msh_file.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2015-09-25 Bernard the first verion for FinSH + * 2021-06-09 Meco Man implement tail command */ #include @@ -146,7 +147,7 @@ int msh_exec_script(const char *cmd_line, int size) extern char working_directory[]; #endif -int cmd_ls(int argc, char **argv) +static int cmd_ls(int argc, char **argv) { extern void ls(const char *pathname); @@ -165,9 +166,9 @@ int cmd_ls(int argc, char **argv) return 0; } -FINSH_FUNCTION_EXPORT_ALIAS(cmd_ls, __cmd_ls, List information about the FILEs.); +MSH_CMD_EXPORT_ALIAS(cmd_ls, ls, List information about the FILEs.); -int cmd_cp(int argc, char **argv) +static int cmd_cp(int argc, char **argv) { void copy(const char *src, const char *dst); @@ -183,9 +184,9 @@ int cmd_cp(int argc, char **argv) return 0; } -FINSH_FUNCTION_EXPORT_ALIAS(cmd_cp, __cmd_cp, Copy SOURCE to DEST.); +MSH_CMD_EXPORT_ALIAS(cmd_cp, cp, Copy SOURCE to DEST.); -int cmd_mv(int argc, char **argv) +static int cmd_mv(int argc, char **argv) { if (argc != 3) { @@ -242,9 +243,9 @@ int cmd_mv(int argc, char **argv) return 0; } -FINSH_FUNCTION_EXPORT_ALIAS(cmd_mv, __cmd_mv, Rename SOURCE to DEST.); +MSH_CMD_EXPORT_ALIAS(cmd_mv, mv, Rename SOURCE to DEST.); -int cmd_cat(int argc, char **argv) +static int cmd_cat(int argc, char **argv) { int index; extern void cat(const char *filename); @@ -263,7 +264,7 @@ int cmd_cat(int argc, char **argv) return 0; } -FINSH_FUNCTION_EXPORT_ALIAS(cmd_cat, __cmd_cat, Concatenate FILE(s)); +MSH_CMD_EXPORT_ALIAS(cmd_cat, cat, Concatenate FILE(s)); static void directory_delete_for_msh(const char *pathname, char f, char v) { @@ -329,7 +330,7 @@ static void directory_delete_for_msh(const char *pathname, char f, char v) } } -int cmd_rm(int argc, char **argv) +static int cmd_rm(int argc, char **argv) { int index, n; char f = 0, r = 0, v = 0; @@ -399,10 +400,10 @@ int cmd_rm(int argc, char **argv) } return 0; } -FINSH_FUNCTION_EXPORT_ALIAS(cmd_rm, __cmd_rm, Remove(unlink) the FILE(s).); +MSH_CMD_EXPORT_ALIAS(cmd_rm, rm, Remove(unlink) the FILE(s).); #ifdef DFS_USING_WORKDIR -int cmd_cd(int argc, char **argv) +static int cmd_cd(int argc, char **argv) { if (argc == 1) { @@ -418,17 +419,17 @@ int cmd_cd(int argc, char **argv) return 0; } -FINSH_FUNCTION_EXPORT_ALIAS(cmd_cd, __cmd_cd, Change the shell working directory.); +MSH_CMD_EXPORT_ALIAS(cmd_cd, cd, Change the shell working directory.); -int cmd_pwd(int argc, char **argv) +static int cmd_pwd(int argc, char **argv) { rt_kprintf("%s\n", working_directory); return 0; } -FINSH_FUNCTION_EXPORT_ALIAS(cmd_pwd, __cmd_pwd, Print the name of the current working directory.); +MSH_CMD_EXPORT_ALIAS(cmd_pwd, pwd, Print the name of the current working directory.); #endif -int cmd_mkdir(int argc, char **argv) +static int cmd_mkdir(int argc, char **argv) { if (argc == 1) { @@ -442,9 +443,9 @@ int cmd_mkdir(int argc, char **argv) return 0; } -FINSH_FUNCTION_EXPORT_ALIAS(cmd_mkdir, __cmd_mkdir, Create the DIRECTORY.); +MSH_CMD_EXPORT_ALIAS(cmd_mkdir, mkdir, Create the DIRECTORY.); -int cmd_mkfs(int argc, char **argv) +static int cmd_mkfs(int argc, char **argv) { int result = 0; char *type = "elm"; /* use the default file system type as 'fatfs' */ @@ -474,10 +475,10 @@ int cmd_mkfs(int argc, char **argv) return 0; } -FINSH_FUNCTION_EXPORT_ALIAS(cmd_mkfs, __cmd_mkfs, format disk with file system); +MSH_CMD_EXPORT_ALIAS(cmd_mkfs, mkfs, format disk with file system); extern struct dfs_filesystem filesystem_table[]; -int cmd_mount(int argc, char *argv[]) +static int cmd_mount(int argc, char **argv) { if (argc == 1) { @@ -522,10 +523,10 @@ int cmd_mount(int argc, char *argv[]) return -1; } } -FINSH_FUNCTION_EXPORT_ALIAS(cmd_mount, __cmd_mount, mount ); +MSH_CMD_EXPORT_ALIAS(cmd_mount, mount, mount ); /* unmount the filesystem from the specified mountpoint */ -int cmd_umount(int argc, char *argv[]) +static int cmd_umount(int argc, char **argv) { char *path = argv[1]; @@ -547,10 +548,10 @@ int cmd_umount(int argc, char *argv[]) return 0; } } -FINSH_FUNCTION_EXPORT_ALIAS(cmd_umount, __cmd_umount, Unmount device from file system); +MSH_CMD_EXPORT_ALIAS(cmd_umount, umount, Unmount device from file system); extern int df(const char *path); -int cmd_df(int argc, char **argv) +static int cmd_df(int argc, char **argv) { if (argc != 2) { @@ -570,9 +571,9 @@ int cmd_df(int argc, char **argv) return 0; } -FINSH_FUNCTION_EXPORT_ALIAS(cmd_df, __cmd_df, disk free); +MSH_CMD_EXPORT_ALIAS(cmd_df, df, disk free); -int cmd_echo(int argc, char **argv) +static int cmd_echo(int argc, char **argv) { if (argc == 2) { @@ -600,7 +601,106 @@ int cmd_echo(int argc, char **argv) return 0; } -FINSH_FUNCTION_EXPORT_ALIAS(cmd_echo, __cmd_echo, echo string to file); +MSH_CMD_EXPORT_ALIAS(cmd_echo, echo, echo string to file); + +static int cmd_tail(int argc, char **argv) +{ + int fd; + char c = RT_NULL; + char *file_name = RT_NULL; + rt_uint32_t total_lines = 0; + rt_uint32_t target_line = 0; + rt_uint32_t current_line = 0; + rt_uint32_t required_lines = 0; + rt_uint32_t after_xxx_line = 0; + + if(argc < 2) + { + rt_kprintf("Usage: tail [-n numbers] \n"); + return -1; + } + else if(argc == 2) + { + required_lines = 10; /* default: 10 lines from tail */ + file_name = argv[1]; + } + else if(rt_strcmp(argv[1], "-n") == 0) + { + if(argv[2][0] != '+') + { + required_lines = atoi(argv[2]); + } + else + { + after_xxx_line = atoi(&argv[2][1]); /* eg: +100, to get the 100 */ + } + file_name = argv[3]; + } + else + { + rt_kprintf("Usage: tail [-n numbers] \n"); + return -1; + } + + fd = open(file_name, O_RDONLY); + if (fd < 0) + { + rt_kprintf("File doesn't exist\n"); + return -1; + } + + while ((read(fd, &c, sizeof(char))) > 0) + { + if (c == '\n') + { + total_lines++; + } + } + + rt_kprintf("\nTotal Number of lines:%d\n", total_lines); + + if(after_xxx_line != 0) + { + if(total_lines > after_xxx_line) + { + required_lines = total_lines - after_xxx_line; + } + else + { + rt_kprintf("\nError:Required lines are more than total number of lines\n"); + close(fd); + return -1; + } + } + + if (required_lines > total_lines) + { + rt_kprintf("\nError:Required lines are more than total number of lines\n"); + close(fd); + return -1; + } + rt_kprintf("Required Number of lines:%d\n", required_lines); + + target_line = total_lines - required_lines; + lseek(fd, 0, SEEK_SET); /* back to head */ + + while ((read(fd, &c, sizeof(char))) > 0) + { + if (c == '\n') + { + current_line++; + } + if (current_line > target_line) + { + rt_kprintf("%c", c); + } + } + rt_kprintf("\n"); + + close(fd); + return 0; +} +MSH_CMD_EXPORT_ALIAS(cmd_tail, tail, print the last N-lines data of the given file); #endif /* defined(FINSH_USING_MSH) && defined(RT_USING_DFS) */ diff --git a/components/finsh/shell.c b/components/finsh/shell.c index 6f1133bf3b..c89139c0ed 100644 --- a/components/finsh/shell.c +++ b/components/finsh/shell.c @@ -97,7 +97,7 @@ int finsh_set_prompt(const char * prompt) } #endif /* RT_USING_HEAP */ -#if defined(RT_USING_DFS) +#ifdef RT_USING_DFS #include #endif /* RT_USING_DFS */ @@ -817,7 +817,7 @@ int finsh_system_init(void) rt_thread_t tid; #ifdef FINSH_USING_SYMTAB -#if defined(__CC_ARM) || defined(__CLANG_ARM) /* ARM C Compiler */ +#ifdef __ARMCC_VERSION /* ARM C Compiler */ extern const int FSymTab$$Base; extern const int FSymTab$$Limit; extern const int VSymTab$$Base; diff --git a/components/libc/Kconfig b/components/libc/Kconfig index a89b252caa..37a98ba836 100644 --- a/components/libc/Kconfig +++ b/components/libc/Kconfig @@ -59,9 +59,9 @@ if RT_USING_LIBC != y default y endif -config RT_LIBC_FIXED_TIMEZONE +config RT_LIBC_DEFAULT_TIMEZONE depends on (RT_LIBC_USING_TIME || RT_USING_LIBC) - int "Manually set a fixed time zone (UTC+)" + int "Set the default time zone (UTC+)" range -12 12 default 8 diff --git a/components/libc/compilers/common/SConscript b/components/libc/compilers/common/SConscript index 039e53a0b3..b1982aa329 100644 --- a/components/libc/compilers/common/SConscript +++ b/components/libc/compilers/common/SConscript @@ -9,20 +9,17 @@ CPPPATH = [cwd] if GetDepend('RT_USING_LIBC'): src += Glob('*.c') -else: - if GetDepend('RT_LIBC_USING_TIME'): - src += ['time.c'] - -if GetDepend('RT_USING_POSIX') == False: - SrcRemove(src, ['unistd.c']) + if GetDepend('RT_USING_POSIX') == False: + SrcRemove(src, ['unistd.c', 'delay.c']) +elif GetDepend('RT_LIBC_USING_TIME'): + src += ['time.c'] if rtconfig.CROSS_TOOL == 'keil': CPPDEFINES = ['__CLK_TCK=RT_TICK_PER_SECOND'] else: CPPDEFINES = [] -if GetDepend('RT_USING_LIBC') or GetDepend('RT_LIBC_USING_TIME'): - group = DefineGroup('libc', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) +group = DefineGroup('libc', src, depend = [], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) list = os.listdir(cwd) for d in list: diff --git a/components/libc/compilers/common/delay.c b/components/libc/compilers/common/delay.c new file mode 100644 index 0000000000..4666258d3b --- /dev/null +++ b/components/libc/compilers/common/delay.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-05-07 Meco Man first Version + */ +#include +#include + +void msleep(unsigned int msecs) +{ + rt_thread_mdelay(msecs); +} +RTM_EXPORT(msleep); + +void ssleep(unsigned int seconds) +{ + msleep(seconds * 1000); +} +RTM_EXPORT(ssleep); + +void mdelay(unsigned long msecs) +{ + rt_hw_us_delay(msecs * 1000); +} +RTM_EXPORT(mdelay); + +void udelay(unsigned long usecs) +{ + rt_hw_us_delay(usecs); +} +RTM_EXPORT(udelay); + +void ndelay(unsigned long nsecs) +{ + rt_hw_us_delay(1); +} +RTM_EXPORT(ndelay); diff --git a/components/libc/compilers/common/delay.h b/components/libc/compilers/common/delay.h new file mode 100644 index 0000000000..f32708af55 --- /dev/null +++ b/components/libc/compilers/common/delay.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-05-07 Meco Man first Version + */ +#ifndef __DELAY_H__ +#define __DELAY_H__ + +void msleep(unsigned int msecs); +void ssleep(unsigned int seconds); +void mdelay(unsigned long msecs); +void udelay(unsigned long usecs); +void ndelay(unsigned long nsecs); + +#endif diff --git a/components/libc/compilers/common/none-gcc/SConscript b/components/libc/compilers/common/none-gcc/SConscript index c5838f8949..c766c8f82d 100644 --- a/components/libc/compilers/common/none-gcc/SConscript +++ b/components/libc/compilers/common/none-gcc/SConscript @@ -6,8 +6,10 @@ src = [] cwd = GetCurrentDir() CPPPATH = [cwd] group = [] -src += Glob('*.c') + +if GetDepend('RT_USING_LIBC'): + src += Glob('*.c') if rtconfig.PLATFORM != 'gcc' or rtconfig.ARCH == 'sim': - group = DefineGroup('libc', src, depend = ['RT_USING_LIBC'], CPPPATH = CPPPATH) + group = DefineGroup('libc', src, depend = [], CPPPATH = CPPPATH) Return('group') diff --git a/include/libc/libc_errno.h b/components/libc/compilers/common/none-gcc/sys/errno.h similarity index 94% rename from include/libc/libc_errno.h rename to components/libc/compilers/common/none-gcc/sys/errno.h index 30d6092e33..ad3614024d 100644 --- a/include/libc/libc_errno.h +++ b/components/libc/compilers/common/none-gcc/sys/errno.h @@ -5,20 +5,12 @@ * * Change Logs: * Date Author Notes - * 2016-11-12 Bernard The first version + * 2021-05-22 Meco Man The first version. */ +#ifndef _SYS_ERRNO_H +#define _SYS_ERRNO_H -#ifndef LIBC_ERRNO_H__ -#define LIBC_ERRNO_H__ - -#include - -#if defined(RT_USING_NEWLIB) || defined(_WIN32) || (defined( __GNUC__ ) && !defined(__ARMCC_VERSION)) -/* use errno.h file in toolchains */ -#include -#endif - -#if defined(__CC_ARM) +#if defined(__ARMCC_VERSION) /* defined in armcc/errno.h @@ -29,6 +21,7 @@ defined in armcc/errno.h #define EINVAL 5 #define ENOMEM 6 */ + #define ERROR_BASE_NO 7 #elif defined(__IAR_SYSTEMS_ICC__) @@ -41,12 +34,11 @@ defined in armcc/errno.h #define ERROR_BASE_NO 36 #else - #define ERROR_BASE_NO 0 #endif -#if !defined(RT_USING_NEWLIB) && !defined(_WIN32) && !(defined( __GNUC__ ) && !defined(__ARMCC_VERSION)) - +#if defined(__ARMCC_VERSION) || defined(__IAR_SYSTEMS_ICC__) +#include #define EPERM (ERROR_BASE_NO + 1) #define ENOENT (ERROR_BASE_NO + 2) #define ESRCH (ERROR_BASE_NO + 3) @@ -200,7 +192,6 @@ defined in armcc/errno.h #define ENOTRECOVERABLE (ERROR_BASE_NO + 131) #define ERFKILL (ERROR_BASE_NO + 132) #define EHWPOISON (ERROR_BASE_NO + 133) - #endif #endif diff --git a/components/libc/compilers/common/sys/ioctl.h b/components/libc/compilers/common/sys/ioctl.h index 648d90230d..51f51f2ea4 100644 --- a/components/libc/compilers/common/sys/ioctl.h +++ b/components/libc/compilers/common/sys/ioctl.h @@ -15,4 +15,224 @@ #include #endif +struct winsize { + unsigned short ws_row; + unsigned short ws_col; + unsigned short ws_xpixel; + unsigned short ws_ypixel; +}; + +#define _IOC(a,b,c,d) ( ((a)<<30) | ((b)<<8) | (c) | ((d)<<16) ) +#define _IOC_NONE 0U +#define _IOC_WRITE 1U +#define _IOC_READ 2U + +#if !defined (_WIN32) && !defined (__TASKING__) +#define _IO(a,b) _IOC(_IOC_NONE,(a),(b),0) +#define _IOW(a,b,c) _IOC(_IOC_WRITE,(a),(b),sizeof(c)) +#define _IOR(a,b,c) _IOC(_IOC_READ,(a),(b),sizeof(c)) +#define _IOWR(a,b,c) _IOC(_IOC_READ|_IOC_WRITE,(a),(b),sizeof(c)) + +#define FIONREAD _IOR('f', 127, int) /* get # bytes to read */ +#define FIONBIO _IOW('f', 126, int) /* set/clear non-blocking i/o */ +#define FIONWRITE _IOR('f', 121, int) /* get # bytes outstanding in send queue */ +#endif + +#define TCGETS 0x5401 +#define TCSETS 0x5402 +#define TCSETSW 0x5403 +#define TCSETSF 0x5404 +#define TCGETA 0x5405 +#define TCSETA 0x5406 +#define TCSETAW 0x5407 +#define TCSETAF 0x5408 +#define TCSBRK 0x5409 +#define TCXONC 0x540A +#define TCFLSH 0x540B +#define TIOCEXCL 0x540C +#define TIOCNXCL 0x540D +#define TIOCSCTTY 0x540E +#define TIOCGPGRP 0x540F +#define TIOCSPGRP 0x5410 +#define TIOCOUTQ 0x5411 +#define TIOCSTI 0x5412 +#define TIOCGWINSZ 0x5413 +#define TIOCSWINSZ 0x5414 +#define TIOCMGET 0x5415 +#define TIOCMBIS 0x5416 +#define TIOCMBIC 0x5417 +#define TIOCMSET 0x5418 +#define TIOCGSOFTCAR 0x5419 +#define TIOCSSOFTCAR 0x541A +#ifndef FIONREAD +#define FIONREAD 0x541B +#endif +#define TIOCINQ FIONREAD +#define TIOCLINUX 0x541C +#define TIOCCONS 0x541D +#define TIOCGSERIAL 0x541E +#define TIOCSSERIAL 0x541F +#define TIOCPKT 0x5420 +#ifndef FIONBIO +#define FIONBIO 0x5421 +#endif +#define TIOCNOTTY 0x5422 +#define TIOCSETD 0x5423 +#define TIOCGETD 0x5424 +#define TCSBRKP 0x5425 +#define TIOCSBRK 0x5427 +#define TIOCCBRK 0x5428 +#define TIOCGSID 0x5429 +#define TIOCGRS485 0x542E +#define TIOCSRS485 0x542F +#define TIOCGPTN 0x80045430 +#define TIOCSPTLCK 0x40045431 +#define TIOCGDEV 0x80045432 +#define TCGETX 0x5432 +#define TCSETX 0x5433 +#define TCSETXF 0x5434 +#define TCSETXW 0x5435 +#define TIOCSIG 0x40045436 +#define TIOCVHANGUP 0x5437 +#define TIOCGPKT 0x80045438 +#define TIOCGPTLCK 0x80045439 +#define TIOCGEXCL 0x80045440 + +#define FIONCLEX 0x5450 +#define FIOCLEX 0x5451 + +#ifndef _WIN32 +#define FIOASYNC 0x5452 +#endif + +#define TIOCSERCONFIG 0x5453 +#define TIOCSERGWILD 0x5454 +#define TIOCSERSWILD 0x5455 +#define TIOCGLCKTRMIOS 0x5456 +#define TIOCSLCKTRMIOS 0x5457 +#define TIOCSERGSTRUCT 0x5458 +#define TIOCSERGETLSR 0x5459 +#define TIOCSERGETMULTI 0x545A +#define TIOCSERSETMULTI 0x545B + +#define TIOCMIWAIT 0x545C +#define TIOCGICOUNT 0x545D +#define FIOQSIZE 0x5460 + +#define TIOCPKT_DATA 0 +#define TIOCPKT_FLUSHREAD 1 +#define TIOCPKT_FLUSHWRITE 2 +#define TIOCPKT_STOP 4 +#define TIOCPKT_START 8 +#define TIOCPKT_NOSTOP 16 +#define TIOCPKT_DOSTOP 32 +#define TIOCPKT_IOCTL 64 + +#define TIOCSER_TEMT 0x01 + +#define TIOCM_LE 0x001 +#define TIOCM_DTR 0x002 +#define TIOCM_RTS 0x004 +#define TIOCM_ST 0x008 +#define TIOCM_SR 0x010 +#define TIOCM_CTS 0x020 +#define TIOCM_CAR 0x040 +#define TIOCM_RNG 0x080 +#define TIOCM_DSR 0x100 +#define TIOCM_CD TIOCM_CAR +#define TIOCM_RI TIOCM_RNG +#define TIOCM_OUT1 0x2000 +#define TIOCM_OUT2 0x4000 +#define TIOCM_LOOP 0x8000 + +#define N_TTY 0 +#define N_SLIP 1 +#define N_MOUSE 2 +#define N_PPP 3 +#define N_STRIP 4 +#define N_AX25 5 +#define N_X25 6 +#define N_6PACK 7 +#define N_MASC 8 +#define N_R3964 9 +#define N_PROFIBUS_FDL 10 +#define N_IRDA 11 +#define N_SMSBLOCK 12 +#define N_HDLC 13 +#define N_SYNC_PPP 14 +#define N_HCI 15 + +#define FIOSETOWN 0x8901 +#define SIOCSPGRP 0x8902 +#define FIOGETOWN 0x8903 +#define SIOCGPGRP 0x8904 +#ifndef SIOCATMARK +#define SIOCATMARK 0x8905 +#endif +#define SIOCGSTAMP 0x8906 +#define SIOCGSTAMPNS 0x8907 + +#define SIOCADDRT 0x890B +#define SIOCDELRT 0x890C +#define SIOCRTMSG 0x890D + +#define SIOCGIFNAME 0x8910 +#define SIOCSIFLINK 0x8911 +#define SIOCGIFCONF 0x8912 +#define SIOCGIFFLAGS 0x8913 +#define SIOCSIFFLAGS 0x8914 +#define SIOCGIFADDR 0x8915 +#define SIOCSIFADDR 0x8916 +#define SIOCGIFDSTADDR 0x8917 +#define SIOCSIFDSTADDR 0x8918 +#define SIOCGIFBRDADDR 0x8919 +#define SIOCSIFBRDADDR 0x891a +#define SIOCGIFNETMASK 0x891b +#define SIOCSIFNETMASK 0x891c +#define SIOCGIFMETRIC 0x891d +#define SIOCSIFMETRIC 0x891e +#define SIOCGIFMEM 0x891f +#define SIOCSIFMEM 0x8920 +#define SIOCGIFMTU 0x8921 +#define SIOCSIFMTU 0x8922 +#define SIOCSIFNAME 0x8923 +#define SIOCSIFHWADDR 0x8924 +#define SIOCGIFENCAP 0x8925 +#define SIOCSIFENCAP 0x8926 +#define SIOCGIFHWADDR 0x8927 +#define SIOCGIFSLAVE 0x8929 +#define SIOCSIFSLAVE 0x8930 +#define SIOCADDMULTI 0x8931 +#define SIOCDELMULTI 0x8932 +#define SIOCGIFINDEX 0x8933 +#define SIOGIFINDEX SIOCGIFINDEX +#define SIOCSIFPFLAGS 0x8934 +#define SIOCGIFPFLAGS 0x8935 +#define SIOCDIFADDR 0x8936 +#define SIOCSIFHWBROADCAST 0x8937 +#define SIOCGIFCOUNT 0x8938 + +#define SIOCGIFBR 0x8940 +#define SIOCSIFBR 0x8941 + +#define SIOCGIFTXQLEN 0x8942 +#define SIOCSIFTXQLEN 0x8943 + +#define SIOCDARP 0x8953 +#define SIOCGARP 0x8954 +#define SIOCSARP 0x8955 + +#define SIOCDRARP 0x8960 +#define SIOCGRARP 0x8961 +#define SIOCSRARP 0x8962 + +#define SIOCGIFMAP 0x8970 +#define SIOCSIFMAP 0x8971 + +#define SIOCADDDLCI 0x8980 +#define SIOCDELDLCI 0x8981 + +#define SIOCDEVPRIVATE 0x89F0 +#define SIOCPROTOPRIVATE 0x89E0 + #endif diff --git a/components/libc/compilers/common/sys/time.h b/components/libc/compilers/common/sys/time.h index bb1a9c96fd..4ca665c536 100644 --- a/components/libc/compilers/common/sys/time.h +++ b/components/libc/compilers/common/sys/time.h @@ -12,6 +12,7 @@ #define _SYS_TIME_H_ #include +#include #include #ifdef __cplusplus @@ -98,6 +99,12 @@ int clock_settime (clockid_t clockid, const struct timespec *tp); int clock_time_to_tick(const struct timespec *time); #endif /* RT_USING_POSIX */ + +/* timezone APIs (Not standard LIBC APIs) */ +void rt_tz_set(rt_int8_t tz); +rt_int8_t rt_tz_get(void); +rt_int8_t rt_tz_is_dst(void); + #ifdef __cplusplus } #endif diff --git a/components/libc/compilers/common/time.c b/components/libc/compilers/common/time.c index 9996212444..8f4856a330 100644 --- a/components/libc/compilers/common/time.c +++ b/components/libc/compilers/common/time.c @@ -18,9 +18,11 @@ * 2021-02-12 Meco Man move all of the functions located in to this file * 2021-03-15 Meco Man fixed a bug of leaking memory in asctime() * 2021-05-01 Meco Man support fixed timezone + * 2021-07-21 Meco Man implement that change/set timezone APIs */ #include "sys/time.h" +#include #include #ifdef RT_USING_DEVICE @@ -31,10 +33,6 @@ #define DBG_LVL DBG_INFO #include -#ifndef RT_LIBC_FIXED_TIMEZONE -#define RT_LIBC_FIXED_TIMEZONE 8 /* UTC+8 */ -#endif - /* seconds per day */ #define SPD 24*60*60 @@ -201,7 +199,7 @@ struct tm *gmtime_r(const time_t *timep, struct tm *r) r->tm_mon = i; r->tm_mday += work - __spm[i]; - r->tm_isdst = 0; + r->tm_isdst = rt_tz_is_dst(); return r; } RTM_EXPORT(gmtime_r); @@ -217,7 +215,7 @@ struct tm* localtime_r(const time_t* t, struct tm* r) { time_t local_tz; - local_tz = *t + RT_LIBC_FIXED_TIMEZONE * 3600; + local_tz = *t + rt_tz_get() * 3600; return gmtime_r(&local_tz, r); } RTM_EXPORT(localtime_r); @@ -234,7 +232,7 @@ time_t mktime(struct tm * const t) time_t timestamp; timestamp = timegm(t); - timestamp = timestamp - 3600 * RT_LIBC_FIXED_TIMEZONE; + timestamp = timestamp - 3600 * rt_tz_get(); return timestamp; } RTM_EXPORT(mktime); @@ -425,7 +423,7 @@ int gettimeofday(struct timeval *tv, struct timezone *tz) if(tz != RT_NULL) { tz->tz_dsttime = DST_NONE; - tz->tz_minuteswest = -(RT_LIBC_FIXED_TIMEZONE * 60); + tz->tz_minuteswest = -(rt_tz_get() * 60); } if (tv != RT_NULL && get_timeval(tv) == RT_EOK) @@ -475,12 +473,17 @@ static int clock_time_system_init() rt_device_t device; time = 0; + +#ifdef RT_USING_RTC device = rt_device_find("rtc"); if (device != RT_NULL) { /* get realtime seconds */ rt_device_control(device, RT_DEVICE_CTRL_RTC_GET_TIME, &time); } +#else + LOG_W("Cannot find a RTC device to provide time!"); +#endif /* get tick */ tick = rt_tick_get(); @@ -593,6 +596,7 @@ int clock_settime(clockid_t clockid, const struct timespec *tp) _timevalue.tv_usec = MICROSECOND_PER_SECOND - (tick % RT_TICK_PER_SECOND) * MICROSECOND_PER_TICK; _timevalue.tv_sec = second - tick/RT_TICK_PER_SECOND - 1; +#ifdef RT_USING_RTC /* update for RTC device */ device = rt_device_find("rtc"); if (device != RT_NULL) @@ -601,6 +605,9 @@ int clock_settime(clockid_t clockid, const struct timespec *tp) rt_device_control(device, RT_DEVICE_CTRL_RTC_SET_TIME, &second); } else +#else + LOG_W("Cannot find a RTC device to save time!"); +#endif return -1; return 0; @@ -641,3 +648,31 @@ int clock_time_to_tick(const struct timespec *time) RTM_EXPORT(clock_time_to_tick); #endif /* RT_USING_POSIX */ + + +/* timezone APIs (Not standard LIBC APIs) */ +#ifndef RT_LIBC_DEFAULT_TIMEZONE +#define RT_LIBC_DEFAULT_TIMEZONE 8 +#endif + +#include + +volatile static rt_int8_t rt_current_timezone = RT_LIBC_DEFAULT_TIMEZONE; + +void rt_tz_set(rt_int8_t tz) +{ + register rt_base_t level; + level = rt_hw_interrupt_disable(); + rt_current_timezone = tz; + rt_hw_interrupt_enable(level); +} + +rt_int8_t rt_tz_get(void) +{ + return rt_current_timezone; +} + +rt_int8_t rt_tz_is_dst(void) +{ + return 0; +} diff --git a/components/libc/compilers/common/unistd.c b/components/libc/compilers/common/unistd.c index 6c81fc7662..9a457c4200 100644 --- a/components/libc/compilers/common/unistd.c +++ b/components/libc/compilers/common/unistd.c @@ -37,26 +37,41 @@ RTM_EXPORT(isatty); char *ttyname(int fd) { - return "/dev/tty"; /*TODO: need to add more specific*/ + return "/dev/tty"; /* TODO: need to add more specific */ } RTM_EXPORT(ttyname); unsigned int sleep(unsigned int seconds) { - rt_tick_t delta_tick; + if (rt_thread_self() != RT_NULL) + { + rt_thread_delay(seconds * RT_TICK_PER_SECOND); + } + else /* scheduler has not run yet */ + { + while(seconds > 0) + { + rt_hw_us_delay(1000000u); + seconds --; + } + } - delta_tick = rt_tick_get(); - rt_thread_delay(seconds * RT_TICK_PER_SECOND); - delta_tick = rt_tick_get() - delta_tick; - - return seconds - delta_tick/RT_TICK_PER_SECOND; + return 0; } RTM_EXPORT(sleep); int usleep(useconds_t usec) { - rt_thread_mdelay(usec / 1000u); + if (rt_thread_self() != RT_NULL) + { + rt_thread_mdelay(usec / 1000u); + } + else /* scheduler has not run yet */ + { + rt_hw_us_delay(usec / 1000u); + } rt_hw_us_delay(usec % 1000u); + return 0; } RTM_EXPORT(usleep); diff --git a/components/libc/compilers/newlib/minilib.c b/components/libc/compilers/newlib/minilib.c index f6df38f67b..612554ca66 100644 --- a/components/libc/compilers/newlib/minilib.c +++ b/components/libc/compilers/newlib/minilib.c @@ -12,8 +12,9 @@ #include #ifdef RT_USING_HEAP /* Memory routine */ -void * -_malloc_r (struct _reent *ptr, size_t size) +#include + +void * _malloc_r (struct _reent *ptr, size_t size) { void* result; @@ -26,8 +27,7 @@ _malloc_r (struct _reent *ptr, size_t size) return result; } -void * -_realloc_r (struct _reent *ptr, void *old, size_t newlen) +void * _realloc_r (struct _reent *ptr, void *old, size_t newlen) { void* result; @@ -53,15 +53,13 @@ void *_calloc_r (struct _reent *ptr, size_t size, size_t len) return result; } -void -_free_r (struct _reent *ptr, void *addr) +void _free_r (struct _reent *ptr, void *addr) { rt_free (addr); } #else -void * -_sbrk_r(struct _reent *ptr, ptrdiff_t incr) +void * _sbrk_r(struct _reent *ptr, ptrdiff_t incr) { return RT_NULL; } diff --git a/components/libc/compilers/newlib/syscalls.c b/components/libc/compilers/newlib/syscalls.c index 7c5d51eca6..e01dc59eb6 100644 --- a/components/libc/compilers/newlib/syscalls.c +++ b/components/libc/compilers/newlib/syscalls.c @@ -29,21 +29,18 @@ /* Reentrant versions of system calls. */ #ifndef _REENT_ONLY -int * -__errno () +int *__errno () { return _rt_errno(); } #endif -int -_getpid_r(struct _reent *ptr) +int _getpid_r(struct _reent *ptr) { return 0; } -int -_close_r(struct _reent *ptr, int fd) +int _close_r(struct _reent *ptr, int fd) { #ifndef RT_USING_DFS /* return "not supported" */ @@ -54,40 +51,35 @@ _close_r(struct _reent *ptr, int fd) #endif } -int -_execve_r(struct _reent *ptr, const char * name, char *const *argv, char *const *env) +int _execve_r(struct _reent *ptr, const char * name, char *const *argv, char *const *env) { /* return "not supported" */ ptr->_errno = ENOTSUP; return -1; } -int -_fcntl_r(struct _reent *ptr, int fd, int cmd, int arg) +int _fcntl_r(struct _reent *ptr, int fd, int cmd, int arg) { /* return "not supported" */ ptr->_errno = ENOTSUP; return -1; } -int -_fork_r(struct _reent *ptr) +int _fork_r(struct _reent *ptr) { /* return "not supported" */ ptr->_errno = ENOTSUP; return -1; } -int -_fstat_r(struct _reent *ptr, int fd, struct stat *pstat) +int _fstat_r(struct _reent *ptr, int fd, struct stat *pstat) { /* return "not supported" */ ptr->_errno = ENOTSUP; return -1; } -int -_isatty_r(struct _reent *ptr, int fd) +int _isatty_r(struct _reent *ptr, int fd) { if (fd >=0 && fd < 3) { @@ -99,24 +91,21 @@ _isatty_r(struct _reent *ptr, int fd) } } -int -_kill_r(struct _reent *ptr, int pid, int sig) +int _kill_r(struct _reent *ptr, int pid, int sig) { /* return "not supported" */ ptr->_errno = ENOTSUP; return -1; } -int -_link_r(struct _reent *ptr, const char *old, const char *new) +int _link_r(struct _reent *ptr, const char *old, const char *new) { /* return "not supported" */ ptr->_errno = ENOTSUP; return -1; } -_off_t -_lseek_r(struct _reent *ptr, int fd, _off_t pos, int whence) +_off_t _lseek_r(struct _reent *ptr, int fd, _off_t pos, int whence) { #ifndef RT_USING_DFS /* return "not supported" */ @@ -130,8 +119,7 @@ _lseek_r(struct _reent *ptr, int fd, _off_t pos, int whence) #endif } -int -_mkdir_r(struct _reent *ptr, const char *name, int mode) +int _mkdir_r(struct _reent *ptr, const char *name, int mode) { #ifndef RT_USING_DFS /* return "not supported" */ @@ -145,8 +133,7 @@ _mkdir_r(struct _reent *ptr, const char *name, int mode) #endif } -int -_open_r(struct _reent *ptr, const char *file, int flags, int mode) +int _open_r(struct _reent *ptr, const char *file, int flags, int mode) { #ifndef RT_USING_DFS /* return "not supported" */ @@ -160,8 +147,7 @@ _open_r(struct _reent *ptr, const char *file, int flags, int mode) #endif } -_ssize_t -_read_r(struct _reent *ptr, int fd, void *buf, size_t nbytes) +_ssize_t _read_r(struct _reent *ptr, int fd, void *buf, size_t nbytes) { #ifndef RT_USING_DFS /* return "not supported" */ @@ -175,8 +161,7 @@ _read_r(struct _reent *ptr, int fd, void *buf, size_t nbytes) #endif } -int -_rename_r(struct _reent *ptr, const char *old, const char *new) +int _rename_r(struct _reent *ptr, const char *old, const char *new) { #ifndef RT_USING_DFS /* return "not supported" */ @@ -190,8 +175,7 @@ _rename_r(struct _reent *ptr, const char *old, const char *new) #endif } -int -_stat_r(struct _reent *ptr, const char *file, struct stat *pstat) +int _stat_r(struct _reent *ptr, const char *file, struct stat *pstat) { #ifndef RT_USING_DFS /* return "not supported" */ @@ -205,8 +189,7 @@ _stat_r(struct _reent *ptr, const char *file, struct stat *pstat) #endif } -int -_unlink_r(struct _reent *ptr, const char *file) +int _unlink_r(struct _reent *ptr, const char *file) { #ifndef RT_USING_DFS /* return "not supported" */ @@ -217,16 +200,14 @@ _unlink_r(struct _reent *ptr, const char *file) #endif } -int -_wait_r(struct _reent *ptr, int *status) +int _wait_r(struct _reent *ptr, int *status) { /* return "not supported" */ ptr->_errno = ENOTSUP; return -1; } -_ssize_t -_write_r(struct _reent *ptr, int fd, const void *buf, size_t nbytes) +_ssize_t _write_r(struct _reent *ptr, int fd, const void *buf, size_t nbytes) { #ifndef RT_USING_DFS #ifdef RT_USING_DEVICE @@ -253,8 +234,7 @@ _write_r(struct _reent *ptr, int fd, const void *buf, size_t nbytes) } #ifdef RT_USING_HEAP /* Memory routine */ -void * -_malloc_r (struct _reent *ptr, size_t size) +void *_malloc_r (struct _reent *ptr, size_t size) { void* result; @@ -267,8 +247,7 @@ _malloc_r (struct _reent *ptr, size_t size) return result; } -void * -_realloc_r (struct _reent *ptr, void *old, size_t newlen) +void *_realloc_r (struct _reent *ptr, void *old, size_t newlen) { void* result; @@ -294,8 +273,7 @@ void *_calloc_r (struct _reent *ptr, size_t size, size_t len) return result; } -void -_free_r (struct _reent *ptr, void *addr) +void _free_r (struct _reent *ptr, void *addr) { rt_free (addr); } @@ -309,16 +287,14 @@ _sbrk_r(struct _reent *ptr, ptrdiff_t incr) #endif /*RT_USING_HEAP*/ /* for exit() and abort() */ -__attribute__ ((noreturn)) void -_exit (int status) +__attribute__ ((noreturn)) void _exit (int status) { extern void __rt_libc_exit(int status); __rt_libc_exit(status); while(1); } -void -_system(const char *s) +void _system(const char *s) { extern int __rt_libc_system(const char *string); __rt_libc_system(s); diff --git a/components/libc/getline/posix_getline.c b/components/libc/getline/posix_getline.c index 794ac3a07d..da80242ecc 100644 --- a/components/libc/getline/posix_getline.c +++ b/components/libc/getline/posix_getline.c @@ -11,8 +11,8 @@ #include "posix_getline.h" #include -#include -#include +#include +#include ssize_t getdelim(char **lineptr, size_t *n, int delim, FILE *stream) { char *cur_pos, *new_lineptr; @@ -43,7 +43,7 @@ ssize_t getdelim(char **lineptr, size_t *n, int delim, FILE *stream) { break; if ((*lineptr + *n - cur_pos) < 2) { - if (SSIZE_MAX / 2 < *n) { + if (LONG_MAX / 2 < *n) { #ifdef EOVERFLOW errno = EOVERFLOW; #else diff --git a/components/libc/pthreads/posix_types.h b/components/libc/pthreads/posix_types.h index 942657ef39..5838e8b370 100644 --- a/components/libc/pthreads/posix_types.h +++ b/components/libc/pthreads/posix_types.h @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #endif diff --git a/components/libc/pthreads/semaphore.c b/components/libc/pthreads/semaphore.c index 398cdf1f49..199b33bfe8 100644 --- a/components/libc/pthreads/semaphore.c +++ b/components/libc/pthreads/semaphore.c @@ -186,7 +186,7 @@ int sem_init(sem_t *sem, int pshared, unsigned int value) rt_snprintf(name, sizeof(name), "psem%02d", psem_number++); sem->sem = rt_sem_create(name, value, RT_IPC_FLAG_FIFO); - if (sem == RT_NULL) + if (sem->sem == RT_NULL) { rt_set_errno(ENOMEM); diff --git a/components/libc/signal/posix_signal.c b/components/libc/signal/posix_signal.c index b06fe12685..1cb561d428 100644 --- a/components/libc/signal/posix_signal.c +++ b/components/libc/signal/posix_signal.c @@ -10,7 +10,8 @@ #include #include -#include +#include +#include #include "posix_signal.h" #define sig_valid(sig_no) (sig_no >= 0 && sig_no < RT_SIG_MAX) diff --git a/components/libc/termios/posix_termios.c b/components/libc/termios/posix_termios.c index 01ba010c86..9f33c857e6 100644 --- a/components/libc/termios/posix_termios.c +++ b/components/libc/termios/posix_termios.c @@ -9,9 +9,8 @@ */ #include #include -#include #include - +#include #include int tcgetattr(int fd, struct termios *tio) @@ -128,4 +127,3 @@ int cfsetspeed(struct termios *tio, speed_t speed) return cfsetospeed(tio, speed); } #endif - diff --git a/components/libc/termios/posix_termios.h b/components/libc/termios/posix_termios.h index 5bd1999b0a..6dc5531955 100644 --- a/components/libc/termios/posix_termios.h +++ b/components/libc/termios/posix_termios.h @@ -10,8 +10,8 @@ #ifndef TERMIOS_H__ #define TERMIOS_H__ -#include #include +#include #ifdef __cplusplus extern "C" { diff --git a/components/net/Kconfig b/components/net/Kconfig index ad1db0c0fc..0fede3eb90 100644 --- a/components/net/Kconfig +++ b/components/net/Kconfig @@ -114,7 +114,7 @@ config RT_USING_LWIP if RT_USING_LWIP choice prompt "lwIP version" - default RT_USING_LWIP212 + default RT_USING_LWIP203 help Select the lwIP version @@ -124,12 +124,15 @@ config RT_USING_LWIP config RT_USING_LWIP202 bool "lwIP v2.0.2" - config RT_USING_LWIP212 + config RT_USING_LWIP203 + bool "lwIP v2.0.3" + + config RT_USING_LWIP212 bool "lwIP v2.1.2" endchoice - if (RT_USING_LWIP202 || RT_USING_LWIP212) + if (RT_USING_LWIP202 || RT_USING_LWIP212 || RT_USING_LWIP203) config RT_USING_LWIP_IPV6 bool "IPV6 protocol" default n diff --git a/components/net/SConscript b/components/net/SConscript index 2012e6fbfe..031e92284c 100644 --- a/components/net/SConscript +++ b/components/net/SConscript @@ -7,10 +7,6 @@ objs = [] cwd = GetCurrentDir() list = os.listdir(cwd) -# the default version of LWIP is 2.0.2 -if not GetDepend('RT_USING_LWIP141') and not GetDepend('RT_USING_LWIP202') and not GetDepend('RT_USING_LWIP212'): - AddDepend('RT_USING_LWIP202') - for d in list: path = os.path.join(cwd, d) if os.path.isfile(os.path.join(path, 'SConscript')): diff --git a/components/net/at/at_socket/at_socket.c b/components/net/at/at_socket/at_socket.c index 6d4c040856..8215dd4417 100644 --- a/components/net/at/at_socket/at_socket.c +++ b/components/net/at/at_socket/at_socket.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include @@ -78,7 +79,7 @@ struct at_socket *at_get_socket(int socket) } /* get a block to the AT socket receive list*/ -static size_t at_recvpkt_put(rt_slist_t *rlist, const char *ptr, size_t length) +static rt_err_t at_recvpkt_put(rt_slist_t *rlist, const char *ptr, size_t length) { at_recv_pkt_t pkt = RT_NULL; @@ -86,7 +87,7 @@ static size_t at_recvpkt_put(rt_slist_t *rlist, const char *ptr, size_t length) if (pkt == RT_NULL) { LOG_E("No memory for receive packet table!"); - return 0; + return -RT_ENOMEM; } pkt->bfsz_totle = length; @@ -95,7 +96,7 @@ static size_t at_recvpkt_put(rt_slist_t *rlist, const char *ptr, size_t length) rt_slist_append(rlist, &pkt->list); - return length; + return RT_EOK; } /* delete and free all receive buffer list */ @@ -651,14 +652,20 @@ static void at_recv_notice_cb(struct at_socket *sock, at_socket_evt_t event, con RT_ASSERT(event == AT_SOCKET_EVT_RECV); /* check the socket object status */ - if (sock->magic != AT_SOCKET_MAGIC) + if (sock->magic != AT_SOCKET_MAGIC || sock->state == AT_SOCKET_CLOSED) { + rt_free((void *)buff); return; } /* put receive buffer to receiver packet list */ rt_mutex_take(sock->recv_lock, RT_WAITING_FOREVER); - at_recvpkt_put(&(sock->recvpkt_list), buff, bfsz); + if (at_recvpkt_put(&(sock->recvpkt_list), buff, bfsz) != RT_EOK) + { + rt_free((void *)buff); + rt_mutex_release(sock->recv_lock); + return; + } rt_mutex_release(sock->recv_lock); rt_sem_release(sock->recv_notice); @@ -815,7 +822,7 @@ int at_recvfrom(int socket, void *mem, size_t len, int flags, struct sockaddr *f /* wait the receive semaphore */ if (rt_sem_take(sock->recv_notice, timeout) < 0) { - LOG_E("AT socket (%d) receive timeout (%d)!", socket, timeout); + LOG_D("AT socket (%d) receive timeout (%d)!", socket, timeout); errno = EAGAIN; result = -1; goto __exit; diff --git a/components/net/at/include/at.h b/components/net/at/include/at.h index c6d0e3a5ce..0e93720ff0 100644 --- a/components/net/at/include/at.h +++ b/components/net/at/include/at.h @@ -113,10 +113,10 @@ typedef struct at_server *at_server_t; #ifdef AT_USING_CLIENT enum at_resp_status { - AT_RESP_OK = 0, /* AT response end is OK */ - AT_RESP_ERROR = -1, /* AT response end is ERROR */ - AT_RESP_TIMEOUT = -2, /* AT response is timeout */ - AT_RESP_BUFF_FULL= -3, /* AT response buffer is full */ + AT_RESP_OK = 0, /* AT response end is OK */ + AT_RESP_ERROR = -1, /* AT response end is ERROR */ + AT_RESP_TIMEOUT = -2, /* AT response is timeout */ + AT_RESP_BUFF_FULL= -3, /* AT response buffer is full */ }; typedef enum at_resp_status at_resp_status_t; diff --git a/components/net/at/src/at_client.c b/components/net/at/src/at_client.c index f40d7698a7..948020f4cf 100644 --- a/components/net/at/src/at_client.c +++ b/components/net/at/src/at_client.c @@ -29,6 +29,10 @@ static struct at_client at_client_table[AT_CLIENT_NUM_MAX] = { 0 }; +extern rt_size_t at_utils_send(rt_device_t dev, + rt_off_t pos, + const void *buffer, + rt_size_t size); extern rt_size_t at_vprintfln(rt_device_t device, const char *format, va_list args); extern void at_print_raw_cmd(const char *type, const char *cmd, rt_size_t size); extern const char *at_get_last_cmd(rt_size_t *cmd_size); @@ -393,7 +397,7 @@ int at_client_obj_wait_connect(at_client_t client, rt_uint32_t timeout) /* Check whether it is already connected */ resp->buf_len = 0; resp->line_counts = 0; - rt_device_write(client->device, 0, "AT\r\n", 4); + at_utils_send(client->device, 0, "AT\r\n", 4); if (rt_sem_take(client->resp_notice, resp->timeout) != RT_EOK) continue; @@ -434,7 +438,13 @@ rt_size_t at_client_obj_send(at_client_t client, const char *buf, rt_size_t size at_print_raw_cmd("sendline", buf, size); #endif - return rt_device_write(client->device, 0, buf, size); + rt_mutex_take(client->lock, RT_WAITING_FOREVER); + + rt_size_t len = at_utils_send(client->device, 0, buf, size); + + rt_mutex_release(client->lock); + + return len; } static rt_err_t at_client_getchar(at_client_t client, char *ch, rt_int32_t timeout) @@ -725,6 +735,8 @@ static void client_parser(at_client_t client) { at_response_t resp = client->resp; + char end_ch = client->recv_line_buf[client->recv_line_len - 1]; + /* current receive is response */ client->recv_line_buf[client->recv_line_len - 1] = '\0'; if (resp->buf_len + client->recv_line_len < resp->buf_size) @@ -742,7 +754,12 @@ static void client_parser(at_client_t client) LOG_E("Read response buffer failed. The Response buffer size is out of buffer size(%d)!", resp->buf_size); } /* check response result */ - if (rt_memcmp(client->recv_line_buf, AT_RESP_END_OK, rt_strlen(AT_RESP_END_OK)) == 0 + if ((client->end_sign != 0) && (end_ch == client->end_sign) && (resp->line_num == 0)) + { + /* get the end sign, return response state END_OK.*/ + client->resp_status = AT_RESP_OK; + } + else if (rt_memcmp(client->recv_line_buf, AT_RESP_END_OK, rt_strlen(AT_RESP_END_OK)) == 0 && resp->line_num == 0) { /* get the end data by response result, return response state END_OK. */ diff --git a/components/net/at/src/at_server.c b/components/net/at/src/at_server.c index bfbbbae2d3..1db26a260b 100644 --- a/components/net/at/src/at_server.c +++ b/components/net/at/src/at_server.c @@ -38,6 +38,10 @@ static at_server_t at_server_local = RT_NULL; static at_cmd_t cmd_table = RT_NULL; static rt_size_t cmd_num; +extern rt_size_t at_utils_send(rt_device_t dev, + rt_off_t pos, + const void *buffer, + rt_size_t size); extern void at_vprintf(rt_device_t device, const char *format, va_list args); extern void at_vprintfln(rt_device_t device, const char *format, va_list args); @@ -187,7 +191,7 @@ rt_size_t at_server_send(at_server_t server, const char *buf, rt_size_t size) return 0; } - return rt_device_write(server->device, 0, buf, size); + return at_utils_send(server->device, 0, buf, size); } /** @@ -412,7 +416,7 @@ static rt_err_t at_cmd_get_name(const char *cmd_buffer, char *cmd_name) return -RT_ERROR; } -static rt_err_t at_server_gerchar(at_server_t server, char *ch, rt_int32_t timeout) +static rt_err_t at_server_getchar(at_server_t server, char *ch, rt_int32_t timeout) { rt_err_t result = RT_EOK; @@ -595,7 +599,7 @@ int at_server_init(void) goto __exit; } - at_server_local->get_char = at_server_gerchar; + at_server_local->get_char = at_server_getchar; memcpy(at_server_local->end_mark, AT_CMD_END_MARK, sizeof(AT_CMD_END_MARK)); at_server_local->parser_entry = server_parser; diff --git a/components/net/at/src/at_utils.c b/components/net/at/src/at_utils.c index 8d8887fe5e..028f262566 100644 --- a/components/net/at/src/at_utils.c +++ b/components/net/at/src/at_utils.c @@ -65,24 +65,41 @@ const char *at_get_last_cmd(rt_size_t *cmd_size) return send_buf; } +RT_WEAK rt_size_t at_utils_send(rt_device_t dev, + rt_off_t pos, + const void *buffer, + rt_size_t size) +{ + return rt_device_write(dev, pos, buffer, size); +} + rt_size_t at_vprintf(rt_device_t device, const char *format, va_list args) { last_cmd_len = vsnprintf(send_buf, sizeof(send_buf), format, args); + if(last_cmd_len > sizeof(send_buf)) + last_cmd_len = sizeof(send_buf); #ifdef AT_PRINT_RAW_CMD at_print_raw_cmd("sendline", send_buf, last_cmd_len); #endif - return rt_device_write(device, 0, send_buf, last_cmd_len); + return at_utils_send(device, 0, send_buf, last_cmd_len); } rt_size_t at_vprintfln(rt_device_t device, const char *format, va_list args) { rt_size_t len; - len = at_vprintf(device, format, args); + last_cmd_len = vsnprintf(send_buf, sizeof(send_buf) - 2, format, args); + if(last_cmd_len > sizeof(send_buf) - 2) + last_cmd_len = sizeof(send_buf) - 2; + rt_memcpy(send_buf + last_cmd_len, "\r\n", 2); - rt_device_write(device, 0, "\r\n", 2); + len = last_cmd_len + 2; - return len + 2; +#ifdef AT_PRINT_RAW_CMD + at_print_raw_cmd("sendline", send_buf, len); +#endif + + return at_utils_send(device, 0, send_buf, len); } diff --git a/components/net/lwip-1.4.1/src/arch/include/arch/cc.h b/components/net/lwip-1.4.1/src/arch/include/arch/cc.h index 8dd59e8dee..82387b432d 100644 --- a/components/net/lwip-1.4.1/src/arch/include/arch/cc.h +++ b/components/net/lwip-1.4.1/src/arch/include/arch/cc.h @@ -37,8 +37,9 @@ #include #include - +#include #include + typedef uint8_t u8_t; typedef int8_t s8_t; typedef uint16_t u16_t; @@ -54,24 +55,18 @@ typedef uintptr_t mem_ptr_t; #define S32_F "ld" #define X32_F "lx" -#ifdef RT_USING_LIBC -#if !defined(__CC_ARM) && !defined(__IAR_SYSTEMS_ICC__) - +#include /* some errno not defined in newlib */ +#ifndef ENSRNOTFOUND #define ENSRNOTFOUND 163 /* Domain name not found */ /* WARNING: ESHUTDOWN also not defined in newlib. We chose 180 here because the number "108" which is used in arch.h has been assigned to another error code. */ -#define ESHUTDOWN 180 -#endif /* __CC_ARM/__IAR_SYSTEMS_ICC__ */ #endif -#if defined(RT_USING_LIBC) || defined(RT_LIBC_USING_TIME) || (defined( __GNUC__ ) && !defined(__ARMCC_VERSION)) +/* LWIP_TIMEVAL_PRIVATE: provided by */ #include #define LWIP_TIMEVAL_PRIVATE 0 -#else -#define LWIP_TIMEVAL_PRIVATE 1 -#endif #if defined(__CC_ARM) /* ARMCC compiler */ #define PACK_STRUCT_FIELD(x) x @@ -105,11 +100,8 @@ void sys_arch_assert(const char* file, int line); #define LWIP_PLATFORM_DIAG(x) do {rt_kprintf x;} while(0) #define LWIP_PLATFORM_ASSERT(x) do {rt_kprintf(x); sys_arch_assert(__FILE__, __LINE__);}while(0) -#include "string.h" - -#define SYS_ARCH_DECL_PROTECT(level) -#define SYS_ARCH_PROTECT(level) rt_enter_critical() -#define SYS_ARCH_UNPROTECT(level) rt_exit_critical() +#define SYS_ARCH_DECL_PROTECT(level) register rt_base_t level +#define SYS_ARCH_PROTECT(level) do {level = rt_hw_interrupt_disable();} while(0) +#define SYS_ARCH_UNPROTECT(level) do {rt_hw_interrupt_enable(level);} while(0) #endif /* __ARCH_CC_H__ */ - diff --git a/components/net/lwip-1.4.1/src/lwipopts.h b/components/net/lwip-1.4.1/src/lwipopts.h index a23a167970..0b7e092d6c 100644 --- a/components/net/lwip-1.4.1/src/lwipopts.h +++ b/components/net/lwip-1.4.1/src/lwipopts.h @@ -3,7 +3,7 @@ #include -#define ERRNO 1 +#define ERRNO #define NO_SYS 0 #define LWIP_SOCKET 1 diff --git a/components/net/lwip-2.0.2/src/api/sockets.c b/components/net/lwip-2.0.2/src/api/sockets.c index dc2477b611..87e0f86dff 100644 --- a/components/net/lwip-2.0.2/src/api/sockets.c +++ b/components/net/lwip-2.0.2/src/api/sockets.c @@ -531,7 +531,8 @@ lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen) return -1; } LWIP_ASSERT("invalid socket index", (newsock >= LWIP_SOCKET_OFFSET) && (newsock < NUM_SOCKETS + LWIP_SOCKET_OFFSET)); - // LWIP_ASSERT("newconn->callback == event_callback", newconn->callback == event_callback); + /* RT-Thread has changed callback when using BSD socket API, so remove this assert. */ + /* LWIP_ASSERT("newconn->callback == event_callback", newconn->callback == event_callback); */ nsock = &sockets[newsock - LWIP_SOCKET_OFFSET]; /* See event_callback: If data comes in right away after an accept, even diff --git a/components/net/lwip-2.0.2/src/arch/include/arch/cc.h b/components/net/lwip-2.0.2/src/arch/include/arch/cc.h index e3014f552c..28f86d257e 100644 --- a/components/net/lwip-2.0.2/src/arch/include/arch/cc.h +++ b/components/net/lwip-2.0.2/src/arch/include/arch/cc.h @@ -37,6 +37,7 @@ #include #include +#include #define U16_F "hu" #define S16_F "hd" @@ -45,12 +46,18 @@ #define S32_F "ld" #define X32_F "lx" -#if defined(RT_USING_LIBC) || defined(RT_LIBC_USING_TIME) || (defined( __GNUC__ ) && !defined(__ARMCC_VERSION)) +#include +/* some errno not defined in newlib */ +#ifndef ENSRNOTFOUND +#define ENSRNOTFOUND 163 /* Domain name not found */ +/* WARNING: ESHUTDOWN also not defined in newlib. We chose + 180 here because the number "108" which is used + in arch.h has been assigned to another error code. */ +#endif + +/* LWIP_TIMEVAL_PRIVATE: provided by */ #include #define LWIP_TIMEVAL_PRIVATE 0 -#else -#define LWIP_TIMEVAL_PRIVATE 1 -#endif #if defined(__CC_ARM) /* ARMCC compiler */ #define PACK_STRUCT_FIELD(x) x @@ -84,11 +91,8 @@ void sys_arch_assert(const char* file, int line); #define LWIP_PLATFORM_DIAG(x) do {rt_kprintf x;} while(0) #define LWIP_PLATFORM_ASSERT(x) do {rt_kprintf(x); sys_arch_assert(__FILE__, __LINE__);}while(0) -#include "string.h" - -#define SYS_ARCH_DECL_PROTECT(level) -#define SYS_ARCH_PROTECT(level) rt_enter_critical() -#define SYS_ARCH_UNPROTECT(level) rt_exit_critical() +#define SYS_ARCH_DECL_PROTECT(level) register rt_base_t level +#define SYS_ARCH_PROTECT(level) do {level = rt_hw_interrupt_disable();} while(0) +#define SYS_ARCH_UNPROTECT(level) do {rt_hw_interrupt_enable(level);} while(0) #endif /* __ARCH_CC_H__ */ - diff --git a/components/net/lwip-2.0.2/src/lwipopts.h b/components/net/lwip-2.0.2/src/lwipopts.h index 09bd223aa4..d559684c02 100644 --- a/components/net/lwip-2.0.2/src/lwipopts.h +++ b/components/net/lwip-2.0.2/src/lwipopts.h @@ -3,7 +3,7 @@ #include -#define ERRNO 1 +#define LWIP_ERRNO_STDINCLUDE #define LWIP_IPV4 1 diff --git a/components/net/lwip-2.0.3/CHANGELOG b/components/net/lwip-2.0.3/CHANGELOG new file mode 100644 index 0000000000..306217fe5a --- /dev/null +++ b/components/net/lwip-2.0.3/CHANGELOG @@ -0,0 +1,4295 @@ +HISTORY + +(git master) + + * [Enter new changes just after this line - do not remove this line] + +(STABLE-2.0.3) + + ++ Bugfixes: + + 2017-09-11: Simon Goldschmidt + * tcp_in.c: fix bug #51937 (leaking tcp_pcbs on passive close with unacked data) + + 2017-08-02: Abroz Bizjak/Simon Goldschmidt + * multiple fixes in IPv4 reassembly (leading to corrupted datagrams received) + + 2017-03-30: Simon Goldschmidt + * dhcp.c: return ERR_VAL instead of asserting on offset-out-of-pbuf + + 2017-03-23: Dirk Ziegelmeier + * dhcp.h: fix bug #50618 (dhcp_remove_struct() macro does not work) + +(STABLE-2.0.2) + + ++ New features: + + 2017-02-10: Dirk Ziegelmeier + * Implement task #14367: Hooks need a better place to be defined: + We now have a #define for a header file name that is #included in every .c + file that provides hooks. + + 2017-02-10: Simon Goldschmidt + * tcp_close does not fail on memory error (instead, FIN is sent from tcp_tmr) + + ++ Bugfixes: + + 2017-03-08 + * tcp: do not keep sending SYNs when getting ACKs + + 2017-03-08: Joel Cunningham + * tcp: Initialize ssthresh to TCP_SND_BUF (bug #50476) + + 2017-03-01: Simon Goldschmidt + * httpd: LWIP_HTTPD_POST_MANUAL_WND: fixed double-free when httpd_post_data_recved + is called nested from httpd_post_receive_data() (bug #50424) + + 2017-02-28: David van Moolenbroek/Simon Goldschmidt + * tcp: fixed bug #50418: LWIP_EVENT_API: fix invalid calbacks for SYN_RCVD pcb + + 2017-02-17: Simon Goldschmidt + * dns: Improved DNS_LOCAL_HOSTLIST interface (bug #50325) + + 2017-02-16: Simon Goldschmidt + * LWIP_NETCONN_FULLDUPLEX: fixed shutdown during write (bug #50274) + + 2017-02-13: Simon Goldschmidt/Dirk Ziegelmeier + * For tiny targtes, LWIP_RAND is optional (fix compile time checks) + + 2017-02-10: Simon Goldschmidt + * tcp: Fixed bug #47485 (tcp_close() should not fail on memory error) by retrying + to send FIN from tcp_fasttmr + + 2017-02-09: Simon Goldschmidt + * sockets: Fixed bug #44032 (LWIP_NETCONN_FULLDUPLEX: select might work on + invalid/reused socket) by not allowing to reallocate a socket that has + "select_waiting != 0" + + 2017-02-09: Simon Goldschmidt + * httpd: Fixed bug #50059 (httpd LWIP_HTTPD_SUPPORT_11_KEEPALIVE vs. + LWIP_HTTPD_KILL_OLD_ON_CONNECTIONS_EXCEEDED) + + 2017-02-08: Dirk Ziegelmeier + * Rename "IPv6 mapped IPv4 addresses" to their correct name from RFC4191: + "IPv4-mapped IPv6 address" + + 2017-02-08: Luc Revardel + * mld6.c: Fix bug #50220 (mld6_leavegroup does not send ICMP6_TYPE_MLD, even + if last reporter) + + 2017-02-08: David van Moolenbroek + * ip6.c: Patch #9250: fix source substitution in ip6_output_if() + + 2017-02-08: Simon Goldschmidt + * tcp_out.c: Fixed bug #50090 (last_unsent->oversize_left can become wrong value + in tcp_write error path) + + 2017-02-02: Dirk Ziegelmeier + * Fix bug #50206: UDP Netconn bind to IP6_ADDR_ANY fails + + 2017-01-18: Dirk Ziegelmeier + * Fix zero-copy RX, see bug bug #50064. PBUF_REFs were not supported as ARP requests. + + 2017-01-15: Axel Lin, Dirk Ziegelmeier + * minor bug fixes in mqtt + + 2017-01-11: Knut Andre Tidemann + * sockets/netconn: fix broken default ICMPv6 handling of checksums + +(STABLE-2.0.1) + + ++ New features: + + 2016-12-31: Simon Goldschmidt + * tcp.h/.c: added function tcp_listen_with_backlog_and_err() to get the error + reason when listening fails (bug #49861) + + 2016-12-20: Erik Andersen + * Add MQTT client + + 2016-12-14: Jan Breuer: + * opt.h, ndc.h/.c: add support for RDNSS option (as per RFC 6106) + + 2016-12-14: David van Moolenbroek + * opt.h, nd6.c: Added LWIP_HOOK_ND6_GET_GW() + + 2016-12-09: Dirk Ziegelmeier + * ip6_frag.c: Implemented support for LWIP_NETIF_TX_SINGLE_PBUF + + 2016-12-09: Simon Goldschmidt + * dns.c: added one-shot multicast DNS queries + + 2016-11-24: Ambroz Bizjak, David van Moolenbroek + * tcp_out.c: Optimize passing contiguous nocopy buffers to tcp_write (bug #46290) + + 2016-11-16: Dirk Ziegelmeier + * sockets.c: added support for IPv6 mapped IPv4 addresses + + ++ Bugfixes: + + 2016-12-16: Thomas Mueller + * api_lib.c: fixed race condition in return value of netconn_gethostbyname() + (and thus also lwip_gethostbyname/_r() and lwip_getaddrinfo()) + + 2016-12-15: David van Moolenbroek + * opt.h, tcp: added LWIP_HOOK_TCP_ISN() to implement less predictable initial + sequence numbers (see contrib/addons/tcp_isn for an example implementation) + + 2016-12-05: Dirk Ziegelmeier + * fixed compiling with IPv4 disabled (IPv6 only case) + + 2016-11-28: Simon Goldschmidt + * api_lib.c: fixed bug #49725 (send-timeout: netconn_write() can return + ERR_OK without all bytes being written) + + 2016-11-28: Ambroz Bizjak + * tcpi_in.c: fixed bug #49717 (window size in received SYN and SYN-ACK + assumed scaled) + + 2016-11-25: Simon Goldschmidt + * dhcp.c: fixed bug #49676 (Possible endless loop when parsing dhcp options) + + 2016-11-23: Dirk Ziegelmeier + * udp.c: fixed bug #49662: multicast traffic is now only received on a UDP PCB + (and therefore on a UDP socket/netconn) when the PCB is bound to IP_ADDR_ANY + + 2016-11-16: Dirk Ziegelmeier + * *: Fixed dual-stack behaviour, IPv6 mapped IPv4 support in socket API + + 2016-11-14: Joel Cunningham + * tcp_out.c: fixed bug #49533 (start persist timer when unsent seg can't fit + in window) + + 2016-11-16: Roberto Barbieri Carrera + * autoip.c: fixed bug #49610 (sometimes AutoIP fails to reuse the same address) + + 2016-11-11: Dirk Ziegelmeier + * sockets.c: fixed bug #49578 (dropping multicast membership does not work + with LWIP_SOCKET_OFFSET) + +(STABLE-2.0.0) + + ++ New features: + + 2016-07-27: Simon Goldschmidt + * opt.h, timeouts.h/.c: added LWIP_TIMERS_CUSTOM to override the default + implementation of timeouts + + 2016-07-xx: Dirk Ziegelmeier + * Large overhaul of doxygen documentation + + 2016-04-05: Simon Goldschmidt + * timers.h/.c: prepare for overriding current timeout implementation: all + stack-internal caclic timers are avaliable in the lwip_cyclic_timers array + + 2016-03-23: Simon Goldschmidt + * tcp: call accept-callback with ERR_MEM when allocating a pcb fails on + passive open to inform the application about this error + ATTENTION: applications have to handle NULL pcb in accept callback! + + 2016-02-22: Ivan Delamer + * Initial 6LoWPAN support + + 2016-02-XX to 2016-03-XX: Dirk Ziegelmeier + * Cleanup TCPIP thread sync methods in a way that it is possibe to use them + in arbitrary code that needs things to be done in TCPIP thread. Used to + decouple netconn, netif, ppp and 6LoWPAN from LWIP core. + + 2016-02-XX: Dirk Ziegelmeier + * Implement dual-stack support in RAW, UDP and TCP. Add new IP address + type IPADDR_ANY_TYPE for this. Netconn/Socket API: Dual-stack is + automatically supported when an IPv6 netconn/socket is created. + + 2015-12-26: Martin Hentschel and Dirk Ziegelmeier + * Rewrite SNMP agent. SNMPv2c + MIB compiler. + + 2015-11-12: Dirk Ziegelmeier + * Decouple SNMP stack from lwIP core and move stack to apps/ directory. + Breaking change: Users have to call snmp_init() now! + + 2015-11-12: Dirk Ziegelmeier + * Implement possibility to declare private memory pools. This is useful to + decouple some apps from the core (SNMP stack) or make contrib app usage + simpler (httpserver_raw) + + 2015-10-09: Simon Goldschmidt + * started to move "private" header files containing implementation details to + "lwip/priv/" include directory to seperate the API from the implementation. + + 2015-10-07: Simon Goldschmidt + * added sntp client as first "supported" application layer protocol implementation + added 'apps' folder + + 2015-09-30: Dirk Ziegelmeier + * snmp_structs.h, mib_structs.c, mib2.c: snmp: fixed ugly inheritance + implementation by aggregating the "base class" (struct mib_node) in all + derived node classes to get more type-safe code + + 2015-09-23: Simon Goldschmidt + * netif.h/.c, nd6.c: task #13729: Convert netif addresses (IPv4 & IPv6) to + ip_addr_t (so they can be used without conversion/temporary storage) + + 2015-09-08: Dirk Ziegelmeier + * snmp: Separate mib2 counter/table callbacks from snmp agent. This both cleans + up the code and should allow integration of a 3rd party agent/mib2. Simple + counters are kept in MIB2_STATS, tree/table change function prototypes moved to + snmp_mib2.h. + + 2015-09-03: Simon Goldschmidt + * opt.h, dns.h/.c: DNS/IPv6: added support for AAAA records + + 2015-09-01: Simon Goldschmidt + * task #12178: hardware checksum capabilities can be configured per netif + (use NETIF_SET_CHECKSUM_CTRL() in your netif's init function) + + 2015-08-30: Simon Goldschmidt + * PBUF_REF with "custom" pbufs is now supported for RX pbufs (see pcapif in + contrib for an example, LWIP_SUPPORT_CUSTOM_PBUF is required) + + 2015-08-30: Simon Goldschmidt + * support IPv4 source based routing: define LWIP_HOOK_IP4_ROUTE_SRC to point + to a routing function + + 2015-08-05: Simon Goldschmidt + * many files: allow multicast socket options IP_MULTICAST_TTL, IP_MULTICAST_IF + and IP_MULTICAST_LOOP to be used without IGMP + + 2015-04-24: Simon Goldschmidt + * dhcp.h/c, autoip.h/.c: added functions dhcp/autoip_supplied_address() to + check for the source of address assignment (replacement for NETIF_FLAG_DHCP) + + 2015-04-10: Simon Goldschmidt + * many files: task #13480: added LWIP_IPV4 define - IPv4 can be disabled, + leaving an IPv6-only stack + + 2015-04-09: Simon Goldschmidt + * nearly all files: task #12722 (improve IPv4/v6 address handling): renamed + ip_addr_t to ip4_addr_t, renamed ipX_addr_t to ip_addr_t and added IP + version; ip_addr_t is used for all generic IP addresses for the API, + ip(4/6)_addr_t are only used internally or when initializing netifs or when + calling version-related functions + + 2015-03-24: Simon Goldschmidt + * opt.h, ip4_addr.h, ip4.c, ip6.c: loopif is not required for loopback traffic + any more but passed through any netif (ENABLE_LOOPBACK has to be enabled) + + 2015-03-23: Simon Goldschmidt + * opt.h, etharp.c: with ETHARP_TABLE_MATCH_NETIF== 1, duplicate (Auto)-IP + addresses on multiple netifs should now be working correctly (if correctly + addressed by routing, that is) + + 2015-03-23: Simon Goldschmidt + * etharp.c: Stable etharp entries that are about to expire are now refreshed + using unicast to prevent unnecessary broadcast. Only if no answer is received + after 15 seconds, broadcast is used. + + 2015-03-06: Philip Gladstone + * netif.h/.c: patch #8359 (Provide utility function to add an IPv6 address to + an interface) + + 2015-03-05: Simon Goldschmidt + * netif.c, ip4.c, dhcp.c, autoip.c: fixed bug #37068 (netif up/down handling + is unclear): correclty separated administrative status of a netif (up/down) + from 'valid address' status + ATTENTION: netif_set_up() now always has to be called, even when dhcp/autoip + is used! + + 2015-02-26: patch by TabascoEye + * netif.c, udp.h/.c: fixed bug #40753 (re-bind UDP pcbs on change of IP address) + + 2015-02-22: chrysn, Simon Goldschmidt + * *.*: Changed nearly all functions taking 'ip(X)_addr_t' pointer to take + const pointers (changed user callbacks: raw_recv_fn, udp_recv_fn; changed + port callbacks: netif_output_fn, netif_igmp_mac_filter_fn) + + 2015-02-19: Ivan Delamer + * netif.h, dhcp.c: Removed unused netif flag for DHCP. The preferred way to evaluate + if DHCP is active is through netif->dhcp field. + + 2015-02-19: Ivan Delamer + * netif.h, slipif.c, ppp.c: Removed unused netif flag for point to point connections + + 2015-02-18: Simon Goldschmidt + * api_lib.c: fixed bug #37958 "netconn API doesn't handle correctly + connections half-closed by peer" + + 2015-02-18: Simon Goldschmidt + * tcp.c: tcp_alloc() prefers killing CLOSING/LAST_ACK over active connections + (see bug #39565) + + 2015-02-16: Claudius Zingerli, Sergio Caprile + * opt.h, dhcp.h/.c: patch #8361 "Add support for NTP option in DHCP" + + 2015-02-14: Simon Goldschmidt + * opt.h, snmp*: added support for write-access community and dedicated + community for sending traps + + 2015-02-13: Simon Goldschmidt + * opt.h, memp.c: added hook LWIP_HOOK_MEMP_AVAILABLE() to get informed when + a memp pool was empty and an item is now available + + 2015-02-13: Simon Goldschmidt + * opt.h, pbuf.h/.c, etharp.c: Added the option PBUF_LINK_ENCAPSULATION_HLEN to + allocate additional header space for TX on netifs requiring additional headers + + 2015-02-12: chrysn + * timers.h/.c: introduce sys_timeouts_sleeptime (returns the time left before + the next timeout is due, for NO_SYS==1) + + 2015-02-11: Nick van Ijzendoorn + * opt.h, sockets.h/c: patch #7702 "Include ability to increase the socket number + with defined offset" + + 2015-02-11: Frederick Baksik + * opt.h, def.h, others: patch #8423 "arch/perf.h" should be made an optional item + + 2015-02-11: Simon Goldschmidt + * api_msg.c, opt.h: started to implement fullduplex sockets/netconns + (note that this is highly unstable yet!) + + 2015-01-17: Simon Goldschmidt + * api: allow enabling socket API without (public) netconn API - netconn API is + still used by sockets, but keeping it private (static) should allow better + compiler optimizations + + 2015-01-16: Simon Goldschmidt + * tcp_in.c: fixed bug #20506 "Initial congestion window is very small" again + by implementing the calculation formula from RFC3390 + + 2014-12-10: Simon Goldschmidt + * api: added option LWIP_NETCONN_SEM_PER_THREAD to use a semaphore per thread + instead of using one per netconn and per select call + + 2014-12-08: Simon Goldschmidt + * ip6.h: fixed bug #43778: IPv6 header version not set on 16-bit platform + (macro IP6H_VTCFL_SET()) + + 2014-12-08: Simon Goldschmidt + * icmp.c, ip4.c, pbuf.c, udp.c, pbuf.h: task #11472 Support PBUF_REF for RX + (IPv6 and IPv4/v6 reassembly might not work yet) + + 2014-11-06: Simon Goldschmidt + * sockets.c/.h, init.c: lwip_socket_init() is not needed any more + -> compatibility define + + 2014-09-16: Simon Goldschmidt + * dns.c, opt.h: reduced ram usage by parsing DNS responses in place + + 2014-09-16: Simon Goldschmidt + * pbuf.h/.c: added pbuf_take_at() and pbuf_put_at() + + 2014-09-15: Simon Goldschmidt + * dns.c: added source port randomization to make the DNS client more robust + (see bug #43144) + + 2013-09-02: Simon Goldschmidt + * arch.h and many other files: added optional macros PACK_STRUCT_FLD_8() and + PACK_STRUCT_FLD_S() to prevent gcc 4 from warning about struct members that + do not need packing + + 2013-08-19: Simon Goldschmidt + * netif.h: bug #42998: made NETIF_MAX_HWADDR_LEN overridable for some special + networks + + 2013-03-17: Simon Goldschmidt (patch by Ghobad Emadi) + * opt.h, etharp.c: Added LWIP_HOOK_ETHARP_GET_GW to implement IPv4 routing with + multiple gateways + + 2013-04-20: Fatih Asici + * opt.h, etharp.h/.c: patch #7993: Added support for transmitting packets + with VLAN headers via hook function LWIP_HOOK_VLAN_SET and to check them + via hook function LWIP_HOOK_VLAN_CHECK + + 2014-02-20: Simon Goldschmidt (based on patch by Artem Pisarenko) + * patch #7885: modification of api modules to support FreeRTOS-MPU + (don't pass stack-pointers to other threads) + + 2014-02-05: Simon Goldschmidt (patch by "xtian" and "alex_ab") + * patch #6537/#7858: TCP window scaling support + + 2014-01-17: Jiri Engelthaler + * icmp, icmp6, opt.h: patch #8027: Completed HW checksuming for IPv4 and + IPv6 ICMP's + + 2012-08-22: Sylvain Rochet + * New PPP stack for lwIP, developed in ppp-new branch. + Based from pppd 2.4.5, released 2009-11-17, with huge changes to match + code size and memory requirements for embedded devices, including: + - Gluing together the previous low-level PPP code in lwIP to pppd 2.4.5, which + is more or less what pppd sys-* files are, so that we get something working + using the unix port. + - Merged some patchs from lwIP Git repository which add interesting features + or fix bugs. + - Merged some patchs from Debian pppd package which add interesting features + or fix bugs. + - Ported PPP timeout handling to the lwIP timers system + - Disabled all the PPP code using filesystem access, replaced in necessary cases + to configuration variables. + - Disabled all the PPP code forking processes. + - Removed IPX support, lwIP does not support IPX. + - Ported and improved random module from the previous PPP port. + - Removed samba TDB (file-driven database) usage, because it needs a filesystem. + - MS-CHAP required a DES implementation, we added the latest PolarSSL DES + implementation which is under a BSD-ish license. + - Also switched to PolarSSL MD4,MD5,SHA1 implementations, which are meant to be + used in embedded devices with reduced memory footprint. + - Removed PPP configuration file parsing support. + - Added macro definition EAP_SUPPORT to make EAP support optional. + - Added macro definition CHAP_SUPPORT to make CHAP support optional. + - Added macro definition MSCHAP_SUPPORT to make MSCHAP support optional. + - Added macro definition PAP_SUPPORT to make PAP support optional. + - Cleared all Linux syscall calls. + - Disabled demand support using a macro, so that it can be ported later. + - Disabled ECP support using a macro, so that it can be ported later. + - Disabled CCP support using a macro, so that it can be ported later. + - Disabled CBCP support using a macro, so that it can be ported later. + - Disabled LQR support using a macro, so that it can be ported later. + - Print packet debug feature optional, through PRINTPKT_SUPPORT + - Removed POSIX signal usage. + - Fully ported PPPoS code from the previous port. + - Fully ported PPPoE code from the previous port. + - Fully ported VJ compression protocol code from the previous port. + - Removed all malloc()/free() use from PPP, replaced by stack usage or PBUF. + - Disabled PPP server support using a macro, so that it can be ported later. + - Switched all PPP debug to lwIP debug system. + - Created PPP Control Block (PPP PCB), removed PPP unit integer everywhere, + removed all global variables everywhere, did everything necessary for + the PPP stack to support more than one PPP session (pppd only support + one session per process). + - Removed the statically allocated output buffer, now using PBUF. + - Improved structure size of all PPP modules, deep analyze of code to reduce + variables size to the bare minimum. Switched all boolean type (char type in + most architecture) to compiler generated bitfields. + - Added PPP IPv6 support, glued lwIP IPv6 support to PPP. + - Now using a persistent netif interface which can then be used in lwIP + functions requiring a netif. + - Now initializing PPP in lwip_init() function. + - Reworked completely the PPP state machine, so that we don't end up in + anymore in inconsistent state, especially with PPPoE. + - Improved the way we handle PPP reconnection after disconnect, cleaning + everything required so that we start the PPP connection again from a + clean state. + - Added PPP holdoff support, allow the lwIP user to wait a little bit before + reconnecting, prevents connection flood, especially when using PPPoL2TP. + - Added PPPoL2TP LAC support (a.k.a. UDP tunnels), adding a VPN client + feature to lwIP, L2TP being a widely used tunnel protocol. + - Switched all used PPP types to lwIP types (u8t, u16t, u32t, ...) + - Added PPP API "sequential" thread-safe API, based from NETIFAPI. + + 2011-07-21: Simon Goldschmidt + * sockets.c, opt.h: (bug #30185): added LWIP_FIONREAD_LINUXMODE that makes + ioctl/FIONREAD return the size of the next pending datagram. + + 2011-05-25: Simon Goldschmidt + * again nearly the whole stack, renamed ip.c to ip4.c, ip_addr.c to ip4_addr.c, + combined ipv4/ipv6 inet_chksum.c, added ip.h, ip_addr.h: Combined IPv4 + and IPv6 code where possible, added defines to access IPv4/IPv6 in non-IP + code so that the code is more readable. + + 2011-05-17: Patch by Ivan Delamer (only checked in by Simon Goldschmidt) + * nearly the whole stack: Finally, we got decent IPv6 support, big thanks to + Ivan! (this is work in progress: we're just post release anyway :-) + + + ++ Bugfixes: + + 2016-08-23: Simon Goldschmidt + * etharp: removed ETHARP_TRUST_IP_MAC since it is insecure and we don't need + it any more after implementing unicast ARP renewal towards arp entry timeout + + 2016-07-20: Simon Goldschmidt + * memp.h/.c: fixed bug #48442 (memp stats don't work for MEMP_MEM_MALLOC) + + 2016-07-21: Simon Goldschmidt (patch by Ambroz Bizjak) + * tcp_in.c, tcp_out.c: fixed bug #48543 (TCP sent callback may prematurely + report sent data when only part of a segment is acked) and don't include + SYN/FIN in snd_buf counter + + 2016-07-19: Simon Goldschmidt + * etharp.c: fixed bug #48477 (ARP input packet might update static entry) + + 2016-07-11: Simon Goldschmidt + * tcp_in.c: fixed bug #48476 (TCP sent callback called wrongly due to picking + up old pcb->acked + + 2016-06-30: Simon Goldschmidt (original patch by Fabian Koch) + * tcp_in.c: fixed bug #48170 (Vulnerable to TCP RST spoofing) + + 2016-05-20: Dirk Ziegelmeier + * sntp.h/.c: Fix return value of sntp_getserver() call to return a pointer + + 2016-04-05: Simon Goldschmidt (patch by Philip Gladstone) + * udp.c: patch #8358: allow more combinations of listening PCB for IPv6 + + 2016-04-05: Simon Goldschmidt + * netconn/socket API: fixed bug# 43739 (Accept not reporting errors about + aborted connections): netconn_accept() returns ERR_ABRT (sockets: ECONNABORTED) + for aborted connections, ERR_CLSD (sockets: EINVAL) if the listening netconn + is closed, which better seems to follow the standard. + + 2016-03-23: Florent Matignon + * dhcp.c: fixed bug #38203: DHCP options are not recorded in all DHCP ack messages + + 2016-03-22: Simon Goldschmidt + * tcp: changed accept handling to be done internally: the application does not + have to call tcp_accepted() any more. Instead, when delaying accept (e.g. sockets + do), call tcp_backlog_delayed()/tcp_backlog_accepted() (fixes bug #46696) + + 2016-03-22: Simon Goldschmidt + * dns.c: ignore dns response parsing errors, only abort resolving for correct + responses or error responses from correct server (bug #47459) + + 2016-03-17: Simon Goldschmidt + * api_msg.c: fixed bug #47448 (netconn/socket leak if RST is received during close) + + 2016-03-17: Joel Cunningham + * api_msg.c: don't fail closing a socket/netconn when failing to allocate the + FIN segment; blocking the calling thread for a while is better than risking + leaking a netconn/socket (see bug #46701) + + 2016-03-16: Joel Cunningham + * tcp_out.c: reset rto timer on fast retransmission + + 2016-03-16: Deomid Ryabkov + * tcp_out.c: fixed bug #46384 Segment size calculation bug with MSS != TCP_MSS + + 2016-03-05: Simon Goldschmidt + * err.h/.c, sockets.c: ERR_IF is not necessarily a fatal error + + 2015-11-19: fix by Kerem Hadimli + * sockets.c: fixed bug #46471: lwip_accept() leaks socket descriptors if new + netconn was already closed because of peer behavior + + 2015-11-12: fix by Valery Ushakov + * tcp_in.c: fixed bug #46365 tcp_accept_null() should call tcp_abort() + + 2015-10-02: Dirk Ziegelmeier/Simon Goldschmidt + * snmp: cleaned up snmp structs API (fixed race conditions from bug #46089, + reduce ram/rom usage of tables): incompatible change for private MIBs + + 2015-09-30: Simon Goldschmidt + * ip4_addr.c: fixed bug #46072: ip4addr_aton() does not check the number range + of all address parts + + 2015-08-28: Simon Goldschmidt + * tcp.c, tcp_in.c: fixed bug #44023: TCP ssthresh value is unclear: ssthresh + is set to the full send window for active open, too, and is updated once + after SYN to ensure the correct send window is used + + 2015-08-28: Simon Goldschmidt + * tcp: fixed bug #45559: Window scaling casts u32_t to u16_t without checks + + 2015-08-26: Simon Goldschmidt + * ip6_frag.h/.c: fixed bug bug #41009: IPv6 reassembly broken on 64-bit platforms: + define IPV6_FRAG_COPYHEADER==1 on these platforms to copy the IPv6 header + instead of referencing it, which gives more room for struct ip6_reass_helper + + 2015-08-25: Simon Goldschmidt + * sockets.c: fixed bug #45827: recvfrom: TCP window is updated with MSG_PEEK + + 2015-08-20: Manoj Kumar + * snmp_msg.h, msg_in.c: fixed bug #43790: Sending octet string of Length >255 + from SNMP agent + + 2015-08-19: Jens Nielsen + * icmp.c, ip4.c, tcp_in.c, udp.c, raw.c: fixed bug #45120: Broadcast & multiple + interfaces handling + + 2015-08-19: Simon Goldschmidt (patch by "Sandra") + * dns.c: fixed bug #45004: dns response without answer might be discarded + + 2015-08-18: Chrysn + * timers.c: patch #8704 fix sys_timeouts_sleeptime function + + 2015-07-01: Erik Ekman + * puf.c: fixed bug #45454 (pbuf_take_at() skips write and returns OK if offset + is at start of pbuf in chain) + + 2015-05-19: Simon Goldschmidt + * dhcp.h/.c: fixed bugs #45140 and #45141 (dhcp was not stopped correctly after + fixing bug #38204) + + 2015-03-21: Simon Goldschmidt (patch by Homyak) + * tcp_in.c: fixed bug #44766 (LWIP_WND_SCALE: tcphdr->wnd was not scaled in + two places) + + 2015-03-21: Simon Goldschmidt + * tcp_impl.h, tcp.c, tcp_in.c: fixed bug #41318 (Bad memory ref in tcp_input() + after tcp_close()) + + 2015-03-21: Simon Goldschmidt + * tcp_in.c: fixed bug #38468 (tcp_sent() not called on half-open connection for + data ACKed with the same ack as FIN) + + 2015-03-21: Simon Goldschmidt (patch by Christoffer Lind) + * dhcp.h/.c: fixed bug #38204 (DHCP lease time not handled correctly) + + 2015-03-20: Simon Goldschmidt + * dhcp.c: fixed bug #38714 (Missing option and client address in DHCPRELEASE message) + + 2015-03-19: Simon Goldschmidt + * api.h, tcpip.h, api_lib.c, api_msg.c: fixed race conditions in assigning + netconn->last_err (fixed bugs #38121 and #37676) + + 2015-03-09: Simon Goldschmidt + * ip4.c: fixed the IPv4 part of bug #43904 (ip_route() must detect linkup status) + + 2015-03-04: Simon Goldschmidt + * nd6.c: fixed bug #43784 (a host should send at least one Router Solicitation) + + 2015-03-04: Valery Ushakov + * ip6.c: fixed bug #41094 (Byte-order bug in IPv6 fragmentation header test) + + 2015-03-04: Zach Smith + * nd6.c: fixed bug #38153 (nd6_input() byte order issues) + + 2015-02-26: Simon Goldschmidt + * netif.c, tcp.h/.c: fixed bug #44378 (TCP connections are not aborted on netif + remove) + + 2015-02-25: Simon Goldschmidt + * ip4.c, etharp.c: fixed bug #40177 (System hangs when dealing with corrupted + packets), implemented task #12357 (Ensure that malicious packets don't + assert-fail): improved some pbuf_header calls to not assert-fail. + + 2015-02-25: patch by Joel Cunningham + * udp.h/.c, sockets.c: fixed bug #43028 (IP_MULTICAST_TTL affects unicast + datagrams) + + 2015-02-25: patch by Greg Renda + * ip4_frag.c: fixed bug #38210 (ip reassembly while remove oldest datagram) + + 2015-02-25: Simon Goldschmidt + * sockets.c: fixed bug #38165 (socket with mulicast): ensure igmp membership + are dropped when socket (not netconn!) is closed. + + 2015-02-25: Simon Goldschmidt + * ip4.h/.c, udp.c: fixed bug #38061 (wrong multicast routing in IPv4) by + adding an optional default netif for multicast routing + + 2015-02-25: Simon Goldschmidt + * netconn API: fixed that netconn_connect still used message passing for + LWIP_TCPIP_CORE_LOCKING==1 + + 2015-02-22: patch by Jens Nielsen + * icmp.c: fixed bug #38803 (Source address in broadcast ping reply) + + 2015-02-22: Simon Goldschmidt + * udp.h, sockets.c: added proper accessor functions for pcb->multicast_ip + (previously used by get/setsockopt only) + + 2015-02-18: Simon Goldschmidt + * sockets.c: Fixed select not reporting received FIN as 'readable' in certain + rare cases (bug #43779: select(), close(), and TCP retransmission error) + + 2015-02-17: Simon Goldschmidt + * err.h, sockets.c, api_msg.c: fixed bug #38853 "connect() use a wrong errno": + return ERR_ALREADY/EALRADY during connect, ERR_ISCONN/EISCONN when already + connected + + 2015-02-17: Simon Goldschmidt + * tcp_impl.h, tcp_out.c, tcp.c, api_msg.c: fixed bug #37614 "Errors from + ipX_output are not processed". Now tcp_output(_segment) checks for the return + value of ipX_output and does not try to send more on error. A netif driver + can call tcp_txnow() (from tcpip_thread!) to try to send again if TX buffers + are available again. + + 2015-02-14: patches by Freddie Chopin + * snmp*: made community writable, fixed some const pointers + + 2015-02-13: Simon Goldschmidt + * msg_in.c: fixed bug #22070 "MIB_OBJECT_WRITE_ONLY not implemented in SNMP" + + 2015-02-12: Simon Goldschmidt + * ip.h, ip4.c, ip6.c: fixed bug #36403 "ip4_input() and ip6_input() always pass + inp to higher layers": now the accepting netif is passed up, but the input + netif is available through ip_current_input_netif() if required. + + 2015-02-11: patch by hichard + * tcpip.c: fixed bug #43094 "The function tcpip_input() forget to handle IPv6" + + 2015-02-10: Simon Goldschmidt + * netconn API: fixed that netconn_close/netconn_delete still used message passing + for LWIP_TCPIP_CORE_LOCKING==1 + + 2015-02-10: Simon Goldschmidt + * netconn/socket api: fixed bug #44225 "closing TCP socket should time out + eventually", implemented task #6930 "Implement SO_LINGER": closing TCP sockets + times out after 20 seconds or after the configured SND_TIMEOUT or depending + on the linger settings. + + 2015-01-27: Simon Goldschmidt + * api_msg.c: fixed that SHUT_RD followed by SHUT_WR was different to SHUT_RDWR, + fixed return value of lwip_netconn_do_close on unconnected netconns + + 2015-01-17: Simon Goldschmidt + * sockets.c: fixed bug #43361 select() crashes with stale FDs + + 2015-01-17: Simon Goldschmidt + * sockets.c/.h, memp_std.h: fixed bug #40788 "lwip_setsockopt_internal() crashes" + by rewriting set/getsockopt functions to combine checks with the actual code + and add more NULL checks; this also fixes that CORE_LOCKING used message + passing for set/getsockopt. + + 2014-12-19: Simon Goldschmidt + * opt.h, dhcp.h/.c: prevent dhcp from starting when netif link is down (only + when LWIP_DHCP_CHECK_LINK_UP==1, which is disabled by default for + compatibility reasons) + + 2014-12-17: Simon Goldschmidt + * tcp_out.c: fixed bug #43840 Checksum error for TCP_CHECKSUM_ON_COPY==1 for + no-copy data with odd length + + 2014-12-10: Simon Goldschmidt + * sockets.c, tcp.c, others: fixed bug #43797 set/getsockopt: SO_SNDTIMEO/SO_RCVTIMEO + take int as option but should take timeval (LWIP_SO_SNDRCVTIMEO_STANDARD==0 can + be used to revert to the old 'winsock' style behaviour) + Fixed implementation of SO_ACCEPTCONN to just look at the pcb state + + 2014-12-09: Simon Goldschmidt + * ip4.c: fixed bug #43596 IGMP queries from 0.0.0.0 are discarded + + 2014-10-21: Simon Goldschmidt (patch by Joel Cunningham and Albert Huitsing) + * sockts.c: fixed bugs #41495 Possible threading issue in select() and #43278 + event_callback() handle context switch when calling sys_sem_signal() + + 2014-10-21: Simon Goldschmidt + * api_msg.c: fixed bug #38219 Assert on TCP netconn_write with sndtimeout set + + 2014-09-16: Kevin Cernekee + * dns.c: patch #8480 Fix handling of dns_seqno wraparound + + 2014-09-16: Simon Goldschmidt + * tcp_out.c: fixed bug #43192 tcp_enqueue_flags() should not check TCP_SND_QUEUELEN + when sending FIN + + 2014-09-03: Simon Goldschmidt + * msg_in.c: fixed bug #39355 SNMP Memory Leak in case of error + + 2014-09-02: Simon Goldschmidt + * err.h/.c, sockets.c, api_msg.c: fixed bug #43110 call getpeername() before + listen() will cause a error + + 2014-09-02: Simon Goldschmidt + * sockets.c: fixed bug #42117 lwip_fcntl does not set errno + + 2014-09-02: Simon Goldschmidt + * tcp.c: fixed bug #42299 tcp_abort() leaves freed pcb on tcp_bound_pcbs list + + 2014-08-20: Simon Goldschmidt + * dns.c: fixed bug #42987 lwIP is vulnerable to DNS cache poisoning due to + non-randomized TXIDs + + 2014-06-03: Simon Goldschmidt + * tcp_impl.h, tcp_in.c: fixed bug #37969 SYN packet dropped as short packet in + tcp_input function + + 2014-05-20: Simon Goldschmidt + * tcp_out.c: fixed bug #37184 tcp_write problem for pcbs in the SYN_SENT state + + 2014-05-19: Simon Goldschmidt + * *.h: Fixed bug #35874 reserved identifier violation (removed leading underscores + from header include guards) + + 2014-04-08: Simon Goldschmidt + * tcp.c: Fixed bug #36167 tcp server crash when client closes (maximum window) + + 2014-04-06: Simon Goldschmidt + * tcp_in.c: Fixed bug #36210 lwIP does not elicit an empty ACK when received + unacceptable ACK + + 2014-04-06: Simon Goldschmidt + * dhcp.c, ip4.c/.h, ip6.c/.h, udp.c/.h, ip.h: Fixed bug #41787 DHCP Discovery + is invalid when an IP is set to thet netif. + + 2014-03-14: Simon Goldschmidt + * tcp_out.c: Fixed bug #36153 TCP Cheksum error if LWIP_CHECKSUM_ON_COPY=1 + + 2014-03-11: Simon Goldschmidt (patch by Mason) + * opt.h, sockets.c: fixed bug #35928 BSD sockets functions must set errno for + POSIX-compliance + + 2014-02-27: Simon Goldschmidt + * dhcp.c: fixed bug #40303 DHCP xid renewed when sending a DHCPREQUEST + + 2014-02-27: Simon Goldschmidt + * raw.c: fixed bug #41680 raw socket can not receive IPv6 packet when + IP_SOF_BROADCAST_RECV==1 + + 2014-02-27: Simon Goldschmidt + * api_msg.c, sockets.c: fixed bug #38404 getpeeraddr returns success on + unconnected/listening TCP sockets + + 2014-02-27: Simon Goldschmidt + * sockets.c: fixed bug #41729 Some socket functions return Exyz instead of -1 + + 2014-02-25: Simon Goldschmidt + * ip4.c: fixed bug #39514 ip_route() may return an IPv6-only interface + + 2014-02-25: Simon Goldschmidt, patch by Fatih Asici + * pbuf.c: fixed bug #39356 Wrong increment in pbuf_memfind() + + 2014-02-25: Simon Goldschmidt + * netif.c/.h, udp.c: fixed bug #39225 udp.c uses netif_matches_ip6_addr() incorrectly; + renamed function netif_matches_ip6_addr() to netif_get_ip6_addr_match() + + 2014-02-25: Simon Goldschmidt + * igmp.c: fixed bug #39145 IGMP membership report for 224.0.0.1 + + 2014-02-22: Simon Goldschmidt (patch by Amir Shalem) + * etharp.c, opt.h: fixed bug #34681 Limit ARP queue length by ARP_QUEUE_LEN (=3) + + 2014-02-22: Simon Goldschmidt (patch by Amir Shalem) + * etharp.h/.c: fixed bug #34682 Limit ARP request flood for unresolved entry + + 2014-02-20: Simon Goldschmidt + * tcp_out.c: fixed bug #39683 Assertion "seg->tcphdr not aligned" failed with + MEM_ALIGNMENT = 8 + + 2014-02-20: Simon Goldschmidt + * sockets.c: fixed bug #39882 No function shall set errno to 0 + + 2014-02-20: Simon Goldschmidt + * mib_structs.c: fixed bug #40050 SNMP problem with MIB arrays > 255 + + 2014-02-20: Simon Goldschmidt + * api.h, sockets.c: fixed bug #41499 netconn::recv_avail can overflow + + 2014-01-08: Stathis Voukelatos + * memp_std.h: patch #7928 Fixed size calculation in MALLOC memory pool + creation macro + + 2014-01-18: Brian Fahs + * tcp_out.c: patch #8237: tcp_rexmit_rto fails to update pcb->unsent_oversize + when necessary + + 2014-01-17: Grant Erickson, Jay Logue, Simon Goldschmidt + * ipv6.c, netif.c: patch #7913 Enable Support for IPv6 Loopback + + 2014-01-16: Stathis Voukelatos + * netif.c: patch #7902 Fixed netif_poll() operation when LWIP_LOOPBACK_MAX_PBUFS > 0 + + 2014-01-14: "Freddie Chopin" + * snmp.h, mib2.c: fixed constness and spelling of sysdescr + + 2014-01-14: Simon Goldschmidt (patch by Thomas Faber) + * tcpip.c: patch #8241: Fix implicit declaration of ip_input with + LWIP_TCPIP_CORE_LOCKING_INPUT disabled + + 2014-01-14: chrysn + * timers.c: patch #8244 make timeouts usable reliably from outside of the + timeout routine + + 2014-01-10: Simon Goldschmidt + * ip_frag.c, ip6_frag.c: fixed bug #41041 Potential use-after-free in IPv6 reassembly + + 2014-01-10: Simon Goldschmidt + * memp.c: fixed bug #41188 Alignment error in memp_init() when MEMP_SEPARATE_POOLS==1 + + 2014-01-10: Simon Goldschmidt + * tcp.c: fixed bug #39898 tcp_fasttmr() possible lock due to infinte queue process loop + + 2013-06-29: Simon Goldschmidt + * inet.h, sockets.h: partially fixed bug #37585: IPv6 compatibility (in socket structs) + + 2013-06-29: Simon Goldschmidt + * inet6.h: bug #37585/task #12600: fixed struct in6_addr.s6_addr to conform to spec + + 2013-04-24: patch by Liam + * api_msg.c: patch #8008 Fix a potential null pointer dereference in assert + + 2013-04-24: Simon Goldschmidt + * igmp.c: fixed possible division by zero + + 2013-04-24: Simon Goldschmidt + * ip6.h, some ipv6 C files: fixed bug #38526 Coverity: Recursive Header Inclusion in ip6.h + + 2013-04-24: Simon Goldschmidt (patch by Emil Ljungdahl): + * netif.c: fixed bug #38586 netif_loop_output() "deadlocks" + + 2013-01-15: Simon Goldschmidt + * ip4.c: fixed bug #37665 ip_canforward operates on address in wrong byte order + + 2013-01-15: Simon Goldschmidt + * pbuf.h: fixed bug #38097 pbuf_free_ooseq() warning + + 2013-01-14: Simon Goldschmidt + * dns.c: fixed bug #37705 Possible memory corruption in DNS query + + 2013-01-11: Simon Goldschmidt + * raw.c: fixed bug #38066 Raw pcbs can alter packet without eating it + + 2012-08-22: Simon Goldschmidt + * memp.c: fixed bug #37166: memp_sanity check loops itself + + 2012-08-13: Simon Goldschmidt + * dhcp.c: fixed bug #36645: Calling dhcp_release before dhcp_start + dereferences NULL + + 2012-08-13: Simon Goldschmidt + * msg_out.c: fixed bug #36840 snmp_send_trap() NULL de-reference if traps + configured but no interfaces available + + 2012-08-13: Simon Goldschmidt + * dns.c: fixed bug #36899 DNS TTL 0 is cached for a long time + + 2012-05-11: Simon Goldschmidt (patch by Marty) + * memp.c: fixed bug #36412: memp.c does not compile when + MEMP_OVERFLOW_CHECK > zero and MEMP_SEPARATE_POOLS == 1 + + 2012-05-03: Simon Goldschmidt (patch by Sylvain Rochet) + * ppp.c: fixed bug #36283 (PPP struct used on header size computation and + not packed) + + 2012-05-03: Simon Goldschmidt (patch by David Empson) + * ppp.c: fixed bug #36388 (PPP: checksum-only in last pbuf leads to pbuf with + zero length) + + 2012-03-25: Simon Goldschmidt + * api_msg.c: Fixed bug #35817: do_connect() invalidly signals op_completed + for UDP/RAW with LWIP_TCPIP_CORE_LOCKING==1 + + 2012-03-25: Simon Goldschmidt + * api_msg.h, api_lib.c, api_msg.c, netifapi.c: fixed bug #35931: Name space + pollution in api_msg.c and netifapi.c + + 2011-08-24: Simon Goldschmidt + * inet6.h: fixed bug #34124 struct in6_addr does not conform to the standard + + + +(STABLE-1.4.1) + + ++ New features: + + 2012-03-25: Simon Goldschmidt (idea by Mason) + * posix/*: added posix-compatibility include files posix/netdb.h and posix/sys/socket.h + which are a simple wrapper to the correct lwIP include files. + + 2012-01-16: Simon Goldschmidt + * opt.h, icmp.c: Added option CHECKSUM_GEN_ICMP + + 2011-12-17: Simon Goldschmidt + * ip.h: implemented API functions to access so_options of IP pcbs (UDP, TCP, RAW) + (fixes bug #35061) + + 2011-09-27: Simon Goldschmidt + * opt.h, tcp.c, tcp_in.c: Implemented limiting data on ooseq queue (task #9989) + (define TCP_OOSEQ_MAX_BYTES / TCP_OOSEQ_MAX_PBUFS in lwipopts.h) + + 2011-09-21: Simon Goldschmidt + * opt.h, api.h, api_lib.c, api_msg.h/.c, sockets.c: Implemented timeout on + send (TCP only, bug #33820) + + 2011-09-21: Simon Goldschmidt + * init.c: Converted runtime-sanity-checks into compile-time checks that can + be disabled (since runtime checks can often not be seen on embedded targets) + + 2011-09-11: Simon Goldschmidt + * ppp.h, ppp_impl.h: splitted ppp.h to an internal and external header file + to get a clear separation of which functions an application or port may use + (task #11281) + + 2011-09-11: Simon Goldschmidt + * opt.h, tcp_impl.h, tcp.c, udp.h/.c: Added a config option to randomize + initial local TCP/UDP ports (so that different port ranges are used after + a reboot; bug #33818; this one added tcp_init/udp_init functions again) + + 2011-09-03: Simon Goldschmidt + * dhcp.c: DHCP uses LWIP_RAND() for xid's (bug #30302) + + 2011-08-24: Simon Goldschmidt + * opt.h, netif.h/.c: added netif remove callback (bug #32397) + + 2011-07-26: Simon Goldschmidt + * etharp.c: ETHARP_SUPPORT_VLAN: add support for an external VLAN filter + function instead of only checking for one VLAN (define ETHARP_VLAN_CHECK_FN) + + 2011-07-21: Simon Goldschmidt (patch by hanhui) + * ip4.c, etharp.c, pbuf.h: bug #33634 ip_forward() have a faulty behaviour: + Added pbuf flags to mark incoming packets as link-layer broadcast/multicast. + Also added code to allow ip_forward() to forward non-broadcast packets to + the input netif (set IP_FORWARD_ALLOW_TX_ON_RX_NETIF==1). + + 2011-06-26: Simon Goldschmidt (patch by Cameron Gutman) + * tcp.c, tcp_out.c: bug #33604: added some more asserts to check that + pcb->state != LISTEN + + 2011-05-14: Simon Goldschmidt (patch by Stéphane Lesage) + * tcpip.c/.h: patch #7449 allow tcpip callback from interrupt with static + memory message + + + ++ Bugfixes: + + 2012-09-26: Simon Goldschmidt + * api_msg.c: fixed bug #37405 'err_tcp()' uses already freed 'netconn' object + + 2012-09-26: patch by Henrik Persson + * dhcp.c: patch #7843 Fix corner case with dhcp timeouts + + 2012-09-26: patch by Henrik Persson + * dhcp.c: patch #7840 Segfault in dhcp_parse_reply if no end marker in dhcp packet + + 2012-08-22: Simon Goldschmidt + * memp.c: fixed bug #37166: memp_sanity check loops itself + + 2012-05-08: Simon Goldschmidt + * tcp_out.c: fixed bug: #36380 unsent_oversize mismatch in 1.4.1RC1 (this was + a debug-check issue only) + + 2012-03-27: Simon Goldschmidt + * vj.c: fixed bug #35756 header length calculation problem in ppp/vj.c + + 2012-03-27: Simon Goldschmidt (patch by Mason) + * tcp_out.c: fixed bug #35945: SYN packet should provide the recv MSS not the + send MSS + + 2012-03-22: Simon Goldschmidt + * ip4.c: fixed bug #35927: missing refragmentaion in ip_forward + + 2012-03-20: Simon Goldschmidt (patch by Mason) + * netdb.c: fixed bug #35907: lwip_gethostbyname_r returns an invalid h_addr_list + + 2012-03-12: Simon Goldschmidt (patch by Bostjan Meglic) + * ppp.c: fixed bug #35809: PPP GetMask(): Compiler warning on big endian, + possible bug on little endian system + + 2012-02-23: Simon Goldschmidt + * etharp.c: fixed bug #35595: Impossible to send broadcast without a gateway + (introduced when fixing bug# 33551) + + 2012-02-16: Simon Goldschmidt + * ppp.c: fixed pbuf leak when PPP session is aborted through pppSigHUP() + (bug #35541: PPP Memory Leak) + + 2012-02-16: Simon Goldschmidt + * etharp.c: fixed bug #35531: Impossible to send multicast without a gateway + (introduced when fixing bug# 33551) + + 2012-02-16: Simon Goldschmidt (patch by Stéphane Lesage) + * msg_in.c, msg_out.c: fixed bug #35536 SNMP: error too big response is malformed + + 2012-02-15: Simon Goldschmidt + * init.c: fixed bug #35537: MEMP_NUM_* sanity checks should be disabled with + MEMP_MEM_MALLOC==1 + + 2012-02-12: Simon Goldschmidt + * tcp.h, tcp_in.c, tcp_out.c: partly fixed bug #25882: TCP hangs on + MSS > pcb->snd_wnd (by not creating segments bigger than half the window) + + 2012-02-11: Simon Goldschmidt + * tcp.c: fixed bug #35435: No pcb state check before adding it to time-wait + queue while closing + + 2012-01-22: Simon Goldschmidt + * tcp.c, tcp_in.c: fixed bug #35305: pcb may be freed too early on shutdown(WR) + + 2012-01-21: Simon Goldschmidt + * tcp.c: fixed bug #34636: FIN_WAIT_2 - Incorrect shutdown of TCP pcb + + 2012-01-20: Simon Goldschmidt + * dhcp.c: fixed bug #35151: DHCP asserts on incoming option lengths + + 2012-01-20: Simon Goldschmidt + * pbuf.c: fixed bug #35291: NULL pointer in pbuf_copy + + 2011-11-25: Simon Goldschmidt + * tcp.h/.c, tcp_impl.h, tcp_in.c: fixed bug #31177: tcp timers can corrupt + tcp_active_pcbs in some cases + + 2011-11-23: Simon Goldschmidt + * sys.c: fixed bug #34884: sys_msleep() body needs to be surrounded with + '#ifndef sys_msleep' + + 2011-11-22: Simon Goldschmidt + * netif.c, etharp.h/.c: fixed bug #34684: Clear the arp table cache when + netif is brought down + + 2011-10-28: Simon Goldschmidt + * tcp_in.c: fixed bug #34638: Dead code in tcp_receive - pcb->dupacks + + 2011-10-23: Simon Goldschmidt + * mem.c: fixed bug #34429: possible memory corruption with + LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT set to 1 + + 2011-10-18: Simon Goldschmidt + * arch.h, netdb.c: fixed bug #34592: lwip_gethostbyname_r uses nonstandard + error value + + 2011-10-18: Simon Goldschmidt + * opt.h: fixed default values of TCP_SNDLOWAT and TCP_SNDQUEUELOWAT for small + windows (bug #34176 select after non-blocking send times out) + + 2011-10-18: Simon Goldschmidt + * tcp_impl.h, tcp_out.c: fixed bug #34587: TCP_BUILD_MSS_OPTION doesn't + consider netif->mtu, causes slow network + + 2011-10-18: Simon Goldschmidt + * sockets.c: fixed bug #34581 missing parentheses in udplite sockets code + + 2011-10-18: Simon Goldschmidt + * sockets.h: fixed bug #34580 fcntl() is missing in LWIP_COMPAT_SOCKETS + + 2011-10-17: Simon Goldschmidt + * api_msg.c: fixed bug #34569: shutdown(SHUT_WR) crashes netconn/socket api + + 2011-10-13: Simon Goldschmidt + * tcp_in.c, tcp_out.c: fixed bug #34517 (persist timer is started although no + zero window is received) by starting the persist timer when a zero window is + received, not when we have more data queued for sending than fits into the + window + + 2011-10-13: Simon Goldschmidt + * def.h, timers.c: fixed bug #34541: LWIP_U32_DIFF is unnecessarily complex + + 2011-10-13: Simon Goldschmidt + * sockets.c, api_lib.c: fixed bug #34540: compiler error when CORE_LOCKING is + used and not all protocols are enabled + + 2011-10-12: Simon Goldschmidt + * pbuf.c: fixed bug #34534: Error in sending fragmented IP if MEM_ALIGNMENT > 4 + + 2011-10-09: Simon Goldschmidt + * tcp_out.c: fixed bug #34426: tcp_zero_window_probe() transmits incorrect + byte value when pcb->unacked != NULL + + 2011-10-09: Simon Goldschmidt + * ip4.c: fixed bug #34447 LWIP_IP_ACCEPT_UDP_PORT(dst_port) wrong + + 2011-09-27: Simon Goldschmidt + * tcp_in.c, tcp_out.c: Reset pcb->unsent_oversize in 2 more places... + + 2011-09-27: Simon Goldschmidt + * tcp_in.c: fixed bug #28288: Data after FIN in oos queue + + 2011-09-27: Simon Goldschmidt + * dhcp.c: fixed bug #34406 dhcp_option_hostname() can overflow the pbuf + + 2011-09-24: Simon Goldschmidt + * mem.h: fixed bug #34377 MEM_SIZE_F is not defined if MEM_LIBC_MALLOC==1 + + 2011-09-23: Simon Goldschmidt + * pbuf.h, tcp.c, tcp_in.c: fixed bug #33871: rejecting TCP_EVENT_RECV() for + the last packet including FIN can lose data + + 2011-09-22: Simon Goldschmidt + * tcp_impl.h: fixed bug #34355: nagle does not take snd_buf/snd_queuelen into + account + + 2011-09-21: Simon Goldschmidt + * opt.h: fixed default value of TCP_SND_BUF to not violate the sanity checks + in init.c + + 2011-09-20: Simon Goldschmidt + * timers.c: fixed bug #34337 (possible NULL pointer in sys_check_timeouts) + + 2011-09-11: Simon Goldschmidt + * tcp_out.c: use pcb->mss instead of TCP_MSS for preallocate mss-sized pbufs + (bug #34019) + + 2011-09-09: Simon Goldschmidt + * udp.c: fixed bug #34072: UDP broadcast is received from wrong UDP pcb if + udp port matches + + 2011-09-03: Simon Goldschmidt + * tcp_in.c: fixed bug #33952 PUSH flag in incoming packet is lost when packet + is aggregated and sent to application + + 2011-09-01: Simon Goldschmidt + * opt.h: fixed bug #31809 LWIP_EVENT_API in opts.h is inconsistent compared + to other options + + 2011-09-01: Simon Goldschmidt + * tcp_in.c: fixed bug #34111 RST for ACK to listening pcb has wrong seqno + + 2011-08-24: Simon Goldschmidt + * api_msg.c, sockets.c: fixed bug #33956 Wrong error returned when calling + accept() on UDP connections + + 2011-08-24: Simon Goldschmidt + * sockets.h: fixed bug #34057 socklen_t should be a typedef + + 2011-08-24: Simon Goldschmidt + * pbuf.c: fixed bug #34112 Odd check in pbuf_alloced_custom (typo) + + 2011-08-24: Simon Goldschmidt + * dhcp.c: fixed bug #34122 dhcp: hostname can overflow + + 2011-08-24: Simon Goldschmidt + * netif.c: fixed bug #34121 netif_add/netif_set_ipaddr fail on NULL ipaddr + + 2011-08-22: Simon Goldschmidt + * tcp_out.c: fixed bug #33962 TF_FIN not always set after FIN is sent. (This + merely prevents nagle from not transmitting fast after closing.) + + 2011-07-22: Simon Goldschmidt + * api_lib.c, api_msg.c, sockets.c, api.h: fixed bug #31084 (socket API returns + always EMSGSIZE on non-blocking sockets if data size > send buffers) -> now + lwip_send() sends as much as possible for non-blocking sockets + + 2011-07-22: Simon Goldschmidt + * pbuf.c/.h, timers.c: freeing ooseq pbufs when the pbuf pool is empty implemented + for NO_SYS==1: when not using sys_check_timeouts(), call PBUF_CHECK_FREE_OOSEQ() + at regular intervals from main level. + + 2011-07-21: Simon Goldschmidt + * etharp.c: fixed bug #33551 (ARP entries may time out although in use) by + sending an ARP request when an ARP entry is used in the last minute before + it would time out. + + 2011-07-04: Simon Goldschmidt + * sys_arch.txt: Fixed documentation after changing sys arch prototypes for 1.4.0. + + 2011-06-26: Simon Goldschmidt + * tcp.c: fixed bug #31723 (tcp_kill_prio() kills pcbs with the same prio) by + updating its documentation only. + + 2011-06-26: Simon Goldschmidt + * mem.c: fixed bug #33545: With MEM_USE_POOLS==1, mem_malloc can return an + unaligned pointer. + + 2011-06-26: Simon Goldschmidt + * mem.c: fixed bug #33544 "warning in mem.c in lwip 1.4.0 with NO_SYS=1" + + 2011-05-25: Simon Goldschmidt + * tcp.c: fixed bug #33398 (pointless conversion when checking TCP port range) + + + +(STABLE-1.4.0) + + ++ New features: + + 2011-03-27: Simon Goldschmidt + * tcp_impl.h, tcp_in.c, tcp_out.c: Removed 'dataptr' from 'struct tcp_seg' and + calculate it in tcp_zero_window_probe (the only place where it was used). + + 2010-11-21: Simon Goldschmidt + * dhcp.c/.h: Added a function to deallocate the struct dhcp from a netif + (fixes bug #31525). + + 2010-07-12: Simon Goldschmidt (patch by Stephane Lesage) + * ip.c, udp.c/.h, pbuf.h, sockets.c: task #10495: Added support for + IP_MULTICAST_LOOP at socket- and raw-API level. + + 2010-06-16: Simon Goldschmidt + * ip.c: Added an optional define (LWIP_IP_ACCEPT_UDP_PORT) that can allow + link-layer-addressed UDP traffic to be received while a netif is down (just + like DHCP during configuration) + + 2010-05-22: Simon Goldschmidt + * many many files: bug #27352: removed packing from ip_addr_t, the packed + version is now only used in protocol headers. Added global storage for + current src/dest IP address while in input functions. + + 2010-05-16: Simon Goldschmidt + * def.h: task #10391: Add preprocessor-macros for compile-time htonl + calculation (and use them throughout the stack where applicable) + + 2010-05-16: Simon Goldschmidt + * opt.h, memp_std.h, memp.c, ppp_oe.h/.c: PPPoE now uses its own MEMP pool + instead of the heap (moved struct pppoe_softc from ppp_oe.c to ppp_oe.h) + + 2010-05-16: Simon Goldschmidt + * opt.h, memp_std.h, dns.h/.c: DNS_LOCAL_HOSTLIST_IS_DYNAMIC uses its own + MEMP pool instead of the heap + + 2010-05-13: Simon Goldschmidt + * tcp.c, udp.c: task #6995: Implement SO_REUSEADDR (correctly), added + new option SO_REUSE_RXTOALL to pass received UDP broadcast/multicast + packets to more than one pcb. + + 2010-05-02: Simon Goldschmidt + * netbuf.h/.c, sockets.c, api_msg.c: use checksum-on-copy for sending + UDP data for LWIP_NETIF_TX_SINGLE_PBUF==1 + + 2010-04-30: Simon Goldschmidt + * udp.h/.c, pbuf.h/.c: task #6849: added udp_send(_to/_if) functions that + take a precalculated checksum, added pbuf_fill_chksum() to copy data + into a pbuf and at the same time calculating the checksum for that data + + 2010-04-29: Simon Goldschmidt + * ip_addr.h, etharp.h/.c, autoip.c: Create overridable macros for copying + 2-byte-aligned IP addresses and MAC addresses + + 2010-04-28: Patch by Bill Auerbach + * ip.c: Inline generating IP checksum to save a function call + + 2010-04-14: Simon Goldschmidt + * tcpip.h/.c, timers.c: Added an overridable define to get informed when the + tcpip_thread processes messages or timeouts to implement a watchdog. + + 2010-03-28: Simon Goldschmidt + * ip_frag.c: create a new (contiguous) PBUF_RAM for every outgoing + fragment if LWIP_NETIF_TX_SINGLE_PBUF==1 + + 2010-03-27: Simon Goldschmidt + * etharp.c: Speedup TX by moving code from find_entry to etharp_output/ + etharp_query to prevent unnecessary function calls (inspired by + patch #7135). + + 2010-03-20: Simon Goldschmidt + * opt.h, tcpip.c/.h: Added an option to disable tcpip_(un)timeout code + since the linker cannot do this automatically to save space. + + 2010-03-20: Simon Goldschmidt + * opt.h, etharp.c/.h: Added support for static ARP table entries + + 2010-03-14: Simon Goldschmidt + * tcp_impl.h, tcp_out.c, inet_chksum.h/.c: task #6849: Calculate checksum + when creating TCP segments, not when (re-)transmitting them. + + 2010-03-07: Simon Goldschmidt + * sockets.c: bug #28775 (select/event_callback: only check select_cb_list + on change) plus use SYS_LIGHTWEIGHT_PROT to protect the select code. + This should speed up receiving data on sockets as the select code in + event_callback is only executed when select is waiting. + + 2010-03-06: Simon Goldschmidt + * tcp_out.c: task #7013 (Create option to have all packets delivered to + netif->output in one piece): Always copy to try to create single pbufs + in tcp_write. + + 2010-03-06: Simon Goldschmidt + * api.h, api_lib.c, sockets.c: task #10167 (sockets: speed up TCP recv + by not allocating a netbuf): added function netconn_recv_tcp_pbuf() + for tcp netconns to receive pbufs, not netbufs; use that function + for tcp sockets. + + 2010-03-05: Jakob Ole Stoklundsen / Simon Goldschmidt + * opt.h, tcp.h, tcp_impl.h, tcp.c, tcp_in.c, tcp_out.c: task #7040: + Work on tcp_enqueue: Don't waste memory when chaining segments, + added option TCP_OVERSIZE to prevent creating many small pbufs when + calling tcp_write with many small blocks of data. Instead, pbufs are + allocated larger than needed and the space is used for later calls to + tcp_write. + + 2010-02-21: Simon Goldschmidt + * stats.c/.h: Added const char* name to mem- and memp-stats for easier + debugging. + + 2010-02-21: Simon Goldschmidt + * tcp.h (and usages), added tcp_impl.h: Splitted API and internal + implementation of tcp to make API usage cleare to application programmers + + 2010-02-14: Simon Goldschmidt/Stephane Lesage + * ip_addr.h: Improved some defines working on ip addresses, added faster + macro to copy addresses that cannot be NULL + + 2010-02-13: Simon Goldschmidt + * api.h, api_lib.c, api_msg.c, sockets.c: task #7865 (implement non- + blocking send operation) + + 2010-02-12: Simon Goldschmidt + * sockets.c/.h: Added a minimal version of posix fctl() to have a + standardised way to set O_NONBLOCK for nonblocking sockets. + + 2010-02-12: Simon Goldschmidt + * dhcp.c/.h, autoip.c/.h: task #10139 (Prefer statically allocated + memory): added autoip_set_struct() and dhcp_set_struct() to let autoip + and dhcp work with user-allocated structs instead of callin mem_malloc + + 2010-02-12: Simon Goldschmidt/Jeff Barber + * tcp.c/h: patch #6865 (SO_REUSEADDR for TCP): if pcb.so_options has + SOF_REUSEADDR set, allow binding to endpoint in TIME_WAIT + + 2010-02-12: Simon Goldschmidt + * sys layer: task #10139 (Prefer statically allocated memory): converted + mbox and semaphore functions to take pointers to sys_mbox_t/sys_sem_t; + converted sys_mbox_new/sys_sem_new to take pointers and return err_t; + task #7212: Add Mutex concept in sys_arch (define LWIP_COMPAT_MUTEX + to let sys.h use binary semaphores instead of mutexes - as before) + + 2010-02-09: Simon Goldschmidt (Simon Kallweit) + * timers.c/.h: Added function sys_restart_timeouts() from patch #7085 + (Restart system timeout handling) + + 2010-02-09: Simon Goldschmidt + * netif.c/.h, removed loopif.c/.h: task #10153 (Integrate loopif into + netif.c) - loopif does not have to be created by the port any more, + just define LWIP_HAVE_LOOPIF to 1. + + 2010-02-08: Simon Goldschmidt + * inet.h, ip_addr.c/.h: Added reentrant versions of inet_ntoa/ipaddr_ntoa + inet_ntoa_r/ipaddr_ntoa_r + + 2010-02-08: Simon Goldschmidt + * netif.h: Added netif_s/get_igmp_mac_filter() macros + + 2010-02-05: Simon Goldschmidt + * netif.h: Added function-like macros to get/set the hostname on a netif + + 2010-02-04: Simon Goldschmidt + * nearly every file: Replaced struct ip_addr by typedef ip_addr_t to + make changing the actual implementation behind the typedef easier. + + 2010-02-01: Simon Goldschmidt + * opt.h, memp_std.h, dns.h, netdb.c, memp.c: Let netdb use a memp pool + for allocating memory when getaddrinfo() is called. + + 2010-01-31: Simon Goldschmidt + * dhcp.h, dhcp.c: Reworked the code that parses DHCP options: parse + them once instead of parsing for every option. This also removes + the need for mem_malloc from dhcp_recv and makes it possible to + correctly retrieve the BOOTP file. + + 2010-01-30: simon Goldschmidt + * sockets.c: Use SYS_LIGHTWEIGHT_PROT instead of a semaphore to protect + the sockets array. + + 2010-01-29: Simon Goldschmidt (patch by Laura Garrett) + * api.h, api_msg.c, sockets.c: Added except set support in select + (patch #6860) + + 2010-01-29: Simon Goldschmidt (patch by Laura Garrett) + * api.h, sockets.h, err.h, api_lib.c, api_msg.c, sockets.c, err.c: + Add non-blocking support for connect (partly from patch #6860), + plus many cleanups in socket & netconn API. + + 2010-01-27: Simon Goldschmidt + * opt.h, tcp.h, init.c, api_msg.c: Added TCP_SNDQUEUELOWAT corresponding + to TCP_SNDLOWAT and added tcp_sndqueuelen() - this fixes bug #28605 + + 2010-01-26: Simon Goldschmidt + * snmp: Use memp pools for snmp instead of the heap; added 4 new pools. + + 2010-01-14: Simon Goldschmidt + * ppp.c/.h: Fixed bug #27856: PPP: Set netif link- and status-callback + by adding ppp_set_netif_statuscallback()/ppp_set_netif_linkcallback() + + 2010-01-13: Simon Goldschmidt + * mem.c: The heap now may be moved to user-defined memory by defining + LWIP_RAM_HEAP_POINTER as a void pointer to that memory's address + (patch #6966 and bug #26133) + + 2010-01-10: Simon Goldschmidt (Bill Auerbach) + * opt.h, memp.c: patch #6822 (Add option to place memory pools in + separate arrays) + + 2010-01-10: Simon Goldschmidt + * init.c, igmp.c: patch #6463 (IGMP - Adding Random Delay): added define + LWIP_RAND() for lwip-wide randomization (to be defined in cc.h) + + 2009-12-31: Simon Goldschmidt + * tcpip.c, init.c, memp.c, sys.c, memp_std.h, sys.h, tcpip.h + added timers.c/.h: Separated timer implementation from semaphore/mbox + implementation, moved timer implementation to timers.c/.h, timers are + now only called from tcpip_thread or by explicitly checking them. + (TASK#7235) + + 2009-12-27: Simon Goldschmidt + * opt.h, etharp.h/.c, init.c, tcpip.c: Added an additional option + LWIP_ETHERNET to support ethernet without ARP (necessary for pure PPPoE) + + + ++ Bugfixes: + + 2011-04-20: Simon Goldschmidt + * sys_arch.txt: sys_arch_timeouts() is not needed any more. + + 2011-04-13: Simon Goldschmidt + * tcp.c, udp.c: Fixed bug #33048 (Bad range for IP source port numbers) by + using ports in the IANA private/dynamic range (49152 through 65535). + + 2011-03-29: Simon Goldschmidt, patch by Emil Lhungdahl: + * etharp.h/.c: Fixed broken VLAN support. + + 2011-03-27: Simon Goldschmidt + * tcp.c: Fixed bug #32926 (TCP_RMV(&tcp_bound_pcbs) is called on unbound tcp + pcbs) by checking if the pcb was bound (local_port != 0). + + 2011-03-27: Simon Goldschmidt + * ppp.c: Fixed bug #32280 (ppp: a pbuf is freed twice) + + 2011-03-27: Simon Goldschmidt + * sockets.c: Fixed bug #32906: lwip_connect+lwip_send did not work for udp and + raw pcbs with LWIP_TCPIP_CORE_LOCKING==1. + + 2011-03-27: Simon Goldschmidt + * tcp_out.c: Fixed bug #32820 (Outgoing TCP connections created before route + is present never times out) by starting retransmission timer before checking + route. + + 2011-03-22: Simon Goldschmidt + * ppp.c: Fixed bug #32648 (PPP code crashes when terminating a link) by only + calling sio_read_abort() if the file descriptor is valid. + + 2011-03-14: Simon Goldschmidt + * err.h/.c, sockets.c, api_msg.c: fixed bug #31748 (Calling non-blocking connect + more than once can render a socket useless) since it mainly involves changing + "FATAL" classification of error codes: ERR_USE and ERR_ISCONN just aren't fatal. + + 2011-03-13: Simon Goldschmidt + * sockets.c: fixed bug #32769 (ESHUTDOWN is linux-specific) by fixing + err_to_errno_table (ERR_CLSD: ENOTCONN instead of ESHUTDOWN), ERR_ISCONN: + use EALRADY instead of -1 + + 2011-03-13: Simon Goldschmidt + * api_lib.c: netconn_accept: return ERR_ABRT instead of ERR_CLSD if the + connection has been aborted by err_tcp (since this is not a normal closing + procedure). + + 2011-03-13: Simon Goldschmidt + * tcp.c: tcp_bind: return ERR_VAL instead of ERR_ISCONN when trying to bind + with pcb->state != CLOSED + + 2011-02-17: Simon Goldschmidt + * rawapi.txt: Fixed bug #32561 tcp_poll argument definition out-of-order in + documentation + + 2011-02-17: Simon Goldschmidt + * many files: Added missing U/UL modifiers to fix 16-bit-arch portability. + + 2011-01-24: Simon Goldschmidt + * sockets.c: Fixed bug #31741: lwip_select seems to have threading problems + + 2010-12-02: Simon Goldschmidt + * err.h: Fixed ERR_IS_FATAL so that ERR_WOULDBLOCK is not fatal. + + 2010-11-23: Simon Goldschmidt + * api.h, api_lib.c, api_msg.c, sockets.c: netconn.recv_avail is only used for + LWIP_SO_RCVBUF and ioctl/FIONREAD. + + 2010-11-23: Simon Goldschmidt + * etharp.c: Fixed bug #31720: ARP-queueing: RFC 1122 recommends to queue at + least 1 packet -> ARP_QUEUEING==0 now queues the most recent packet. + + 2010-11-23: Simon Goldschmidt + * tcp_in.c: Fixed bug #30577: tcp_input: don't discard ACK-only packets after + refusing 'refused_data' again. + + 2010-11-22: Simon Goldschmidt + * sockets.c: Fixed bug #31590: getsockopt(... SO_ERROR ...) gives EINPROGRESS + after a successful nonblocking connection. + + 2010-11-22: Simon Goldschmidt + * etharp.c: Fixed bug #31722: IP packets sent with an AutoIP source addr + must be sent link-local + + 2010-11-22: Simon Goldschmidt + * timers.c: patch #7329: tcp_timer_needed prototype was ifdef'ed out for + LWIP_TIMERS==0 + + 2010-11-20: Simon Goldschmidt + * sockets.c: Fixed bug #31170: lwip_setsockopt() does not set socket number + + 2010-11-20: Simon Goldschmidt + * sockets.h: Fixed bug #31304: Changed SHUT_RD, SHUT_WR and SHUT_RDWR to + resemble other stacks. + + 2010-11-20: Simon Goldschmidt + * dns.c: Fixed bug #31535: TCP_SND_QUEUELEN must be at least 2 or else + no-copy TCP writes will never succeed. + + 2010-11-20: Simon Goldschmidt + * dns.c: Fixed bug #31701: Error return value from dns_gethostbyname() does + not match documentation: return ERR_ARG instead of ERR_VAL if not + initialized or wrong argument. + + 2010-10-20: Simon Goldschmidt + * sockets.h: Fixed bug #31385: sizeof(struct sockaddr) is 30 but should be 16 + + 2010-10-05: Simon Goldschmidt + * dhcp.c: Once again fixed #30038: DHCP/AutoIP cooperation failed when + replugging the network cable after an AutoIP address was assigned. + + 2010-08-10: Simon Goldschmidt + * tcp.c: Fixed bug #30728: tcp_new_port() did not check listen pcbs + + 2010-08-03: Simon Goldschmidt + * udp.c, raw.c: Don't chain empty pbufs when sending them (fixes bug #30625) + + 2010-08-01: Simon Goldschmidt (patch by Greg Renda) + * ppp.c: Applied patch #7264 (PPP protocols are rejected incorrectly on big + endian architectures) + + 2010-07-28: Simon Goldschmidt + * api_lib.c, api_msg.c, sockets.c, mib2.c: Fixed compilation with TCP or UDP + disabled. + + 2010-07-27: Simon Goldschmidt + * tcp.c: Fixed bug #30565 (tcp_connect() check bound list): that check did no + harm but never did anything + + 2010-07-21: Simon Goldschmidt + * ip.c: Fixed invalid fix for bug #30402 (CHECKSUM_GEN_IP_INLINE does not + add IP options) + + 2010-07-16: Kieran Mansley + * msg_in.c: Fixed SNMP ASN constant defines to not use ! operator + + 2010-07-10: Simon Goldschmidt + * ip.c: Fixed bug #30402: CHECKSUM_GEN_IP_INLINE does not add IP options + + 2010-06-30: Simon Goldschmidt + * api_msg.c: fixed bug #30300 (shutdown parameter was not initialized in + netconn_delete) + + 2010-06-28: Kieran Mansley + * timers.c remove unportable printing of C function pointers + + 2010-06-24: Simon Goldschmidt + * init.c, timers.c/.h, opt.h, memp_std.h: From patch #7221: added flag + NO_SYS_NO_TIMERS to drop timer support for NO_SYS==1 for easier upgrading + + 2010-06-24: Simon Goldschmidt + * api(_lib).c/.h, api_msg.c/.h, sockets.c/.h: Fixed bug #10088: Correctly + implemented shutdown at socket level. + + 2010-06-21: Simon Goldschmidt + * pbuf.c/.h, ip_frag.c/.h, opt.h, memp_std.h: Fixed bug #29361 (ip_frag has + problems with zero-copy DMA MACs) by adding custom pbufs and implementing + custom pbufs that reference other (original) pbufs. Additionally set + IP_FRAG_USES_STATIC_BUF=0 as default to be on the safe side. + + 2010-06-15: Simon Goldschmidt + * dhcp.c: Fixed bug #29970: DHCP endian issue parsing option responses + + 2010-06-14: Simon Goldschmidt + * autoip.c: Fixed bug #30039: AutoIP does not reuse previous addresses + + 2010-06-12: Simon Goldschmidt + * dhcp.c: Fixed bug #30038: dhcp_network_changed doesn't reset AUTOIP coop + state + + 2010-05-17: Simon Goldschmidt + * netdb.c: Correctly NULL-terminate h_addr_list + + 2010-05-16: Simon Goldschmidt + * def.h/.c: changed the semantics of LWIP_PREFIX_BYTEORDER_FUNCS to prevent + "symbol already defined" i.e. when linking to winsock + + 2010-05-05: Simon Goldschmidt + * def.h, timers.c: Fixed bug #29769 (sys_check_timeouts: sys_now() may + overflow) + + 2010-04-21: Simon Goldschmidt + * api_msg.c: Fixed bug #29617 (sometime cause stall on delete listening + connection) + + 2010-03-28: Luca Ceresoli + * ip_addr.c/.h: patch #7143: Add a few missing const qualifiers + + 2010-03-27: Luca Ceresoli + * mib2.c: patch #7130: remove meaningless const qualifiers + + 2010-03-26: Simon Goldschmidt + * tcp_out.c: Make LWIP_NETIF_TX_SINGLE_PBUF work for TCP, too + + 2010-03-26: Simon Goldschmidt + * various files: Fixed compiling with different options disabled (TCP/UDP), + triggered by bug #29345; don't allocate acceptmbox if LWIP_TCP is disabled + + 2010-03-25: Simon Goldschmidt + * sockets.c: Fixed bug #29332: lwip_select() processes readset incorrectly + + 2010-03-25: Simon Goldschmidt + * tcp_in.c, test_tcp_oos.c: Fixed bug #29080: Correctly handle remote side + overrunning our rcv_wnd in ooseq case. + + 2010-03-22: Simon Goldschmidt + * tcp.c: tcp_listen() did not copy the pcb's prio. + + 2010-03-19: Simon Goldschmidt + * snmp_msg.c: Fixed bug #29256: SNMP Trap address was not correctly set + + 2010-03-14: Simon Goldschmidt + * opt.h, etharp.h: Fixed bug #29148 (Incorrect PBUF_POOL_BUFSIZE for ports + where ETH_PAD_SIZE > 0) by moving definition of ETH_PAD_SIZE to opt.h + and basing PBUF_LINK_HLEN on it. + + 2010-03-08: Simon Goldschmidt + * netif.c, ipv4/ip.c: task #10241 (AutoIP: don't break existing connections + when assiging routable address): when checking incoming packets and + aborting existing connection on address change, filter out link-local + addresses. + + 2010-03-06: Simon Goldschmidt + * sockets.c: Fixed LWIP_NETIF_TX_SINGLE_PBUF for LWIP_TCPIP_CORE_LOCKING + + 2010-03-06: Simon Goldschmidt + * ipv4/ip.c: Don't try to forward link-local addresses + + 2010-03-06: Simon Goldschmidt + * etharp.c: Fixed bug #29087: etharp: don't send packets for LinkLocal- + addresses to gw + + 2010-03-05: Simon Goldschmidt + * dhcp.c: Fixed bug #29072: Correctly set ciaddr based on message-type + and state. + + 2010-03-05: Simon Goldschmidt + * api_msg.c: Correctly set TCP_WRITE_FLAG_MORE when netconn_write is split + into multiple calls to tcp_write. + + 2010-02-21: Simon Goldschmidt + * opt.h, mem.h, dns.c: task #10140: Remove DNS_USES_STATIC_BUF (keep + the implementation of DNS_USES_STATIC_BUF==1) + + 2010-02-20: Simon Goldschmidt + * tcp.h, tcp.c, tcp_in.c, tcp_out.c: Task #10088: Correctly implement + close() vs. shutdown(). Now the application does not get any more + recv callbacks after calling tcp_close(). Added tcp_shutdown(). + + 2010-02-19: Simon Goldschmidt + * mem.c/.h, pbuf.c: Renamed mem_realloc() to mem_trim() to prevent + confusion with realloc() + + 2010-02-15: Simon Goldschmidt/Stephane Lesage + * netif.c/.h: Link status does not depend on LWIP_NETIF_LINK_CALLBACK + (fixes bug #28899) + + 2010-02-14: Simon Goldschmidt + * netif.c: Fixed bug #28877 (Duplicate ARP gratuitous packet with + LWIP_NETIF_LINK_CALLBACK set on) by only sending if both link- and + admin-status of a netif are up + + 2010-02-14: Simon Goldschmidt + * opt.h: Disable ETHARP_TRUST_IP_MAC by default since it slows down packet + reception and is not really necessary + + 2010-02-14: Simon Goldschmidt + * etharp.c/.h: Fixed ARP input processing: only add a new entry if a + request was directed as us (RFC 826, Packet Reception), otherwise + only update existing entries; internalized some functions + + 2010-02-14: Simon Goldschmidt + * netif.h, etharp.c, tcpip.c: Fixed bug #28183 (ARP and TCP/IP cannot be + disabled on netif used for PPPoE) by adding a new netif flag + (NETIF_FLAG_ETHERNET) that tells the stack the device is an ethernet + device but prevents usage of ARP (so that ethernet_input can be used + for PPPoE). + + 2010-02-12: Simon Goldschmidt + * netif.c: netif_set_link_up/down: only do something if the link state + actually changes + + 2010-02-12: Simon Goldschmidt/Stephane Lesage + * api_msg.c: Fixed bug #28865 (Cannot close socket/netconn in non-blocking + connect) + + 2010-02-12: Simon Goldschmidt + * mem.h: Fixed bug #28866 (mem_realloc function defined in mem.h) + + 2010-02-09: Simon Goldschmidt + * api_lib.c, api_msg.c, sockets.c, api.h, api_msg.h: Fixed bug #22110 + (recv() makes receive window update for data that wasn't received by + application) + + 2010-02-09: Simon Goldschmidt/Stephane Lesage + * sockets.c: Fixed bug #28853 (lwip_recvfrom() returns 0 on receive time-out + or any netconn_recv() error) + + 2010-02-09: Simon Goldschmidt + * ppp.c: task #10154 (PPP: Update snmp in/out counters for tx/rx packets) + + 2010-02-09: Simon Goldschmidt + * netif.c: For loopback packets, adjust the stats- and snmp-counters + for the loopback netif. + + 2010-02-08: Simon Goldschmidt + * igmp.c/.h, ip.h: Moved most defines from igmp.h to igmp.c for clarity + since they are not used anywhere else. + + 2010-02-08: Simon Goldschmidt (Stéphane Lesage) + * igmp.c, igmp.h, stats.c, stats.h: Improved IGMP stats + (patch from bug #28798) + + 2010-02-08: Simon Goldschmidt (Stéphane Lesage) + * igmp.c: Fixed bug #28798 (Error in "Max Response Time" processing) and + another bug when LWIP_RAND() returns zero. + + 2010-02-04: Simon Goldschmidt + * nearly every file: Use macros defined in ip_addr.h (some of them new) + to work with IP addresses (preparation for bug #27352 - Change ip_addr + from struct to typedef (u32_t) - and better code). + + 2010-01-31: Simon Goldschmidt + * netif.c: Don't call the link-callback from netif_set_up/down() since + this invalidly retriggers DHCP. + + 2010-01-29: Simon Goldschmidt + * ip_addr.h, inet.h, def.h, inet.c, def.c, more: Cleanly separate the + portability file inet.h and its contents from the stack: moved htonX- + functions to def.h (and the new def.c - they are not ipv4 dependent), + let inet.h depend on ip_addr.h and not the other way round. + This fixes bug #28732. + + 2010-01-28: Kieran Mansley + * tcp.c: Ensure ssthresh >= 2*MSS + + 2010-01-27: Simon Goldschmidt + * tcp.h, tcp.c, tcp_in.c: Fixed bug #27871: Calling tcp_abort() in recv + callback can lead to accessing unallocated memory. As a consequence, + ERR_ABRT means the application has called tcp_abort()! + + 2010-01-25: Simon Goldschmidt + * snmp_structs.h, msg_in.c: Partly fixed bug #22070 (MIB_OBJECT_WRITE_ONLY + not implemented in SNMP): write-only or not-accessible are still + returned by getnext (though not by get) + + 2010-01-24: Simon Goldschmidt + * snmp: Renamed the private mib node from 'private' to 'mib_private' to + not use reserved C/C++ keywords + + 2010-01-23: Simon Goldschmidt + * sockets.c: Fixed bug #28716: select() returns 0 after waiting for less + than 1 ms + + 2010-01-21: Simon Goldschmidt + * tcp.c, api_msg.c: Fixed bug #28651 (tcp_connect: no callbacks called + if tcp_enqueue fails) both in raw- and netconn-API + + 2010-01-19: Simon Goldschmidt + * api_msg.c: Fixed bug #27316: netconn: Possible deadlock in err_tcp + + 2010-01-18: Iordan Neshev/Simon Goldschmidt + * src/netif/ppp: reorganised PPP sourcecode to 2.3.11 including some + bugfix backports from 2.4.x. + + 2010-01-18: Simon Goldschmidt + * mem.c: Fixed bug #28679: mem_realloc calculates mem_stats wrong + + 2010-01-17: Simon Goldschmidt + * api_lib.c, api_msg.c, (api_msg.h, api.h, sockets.c, tcpip.c): + task #10102: "netconn: clean up conn->err threading issues" by adding + error return value to struct api_msg_msg + + 2010-01-17: Simon Goldschmidt + * api.h, api_lib.c, sockets.c: Changed netconn_recv() and netconn_accept() + to return err_t (bugs #27709 and #28087) + + 2010-01-14: Simon Goldschmidt + * ...: Use typedef for function prototypes throughout the stack. + + 2010-01-13: Simon Goldschmidt + * api_msg.h/.c, api_lib.c: Fixed bug #26672 (close connection when receive + window = 0) by correctly draining recvmbox/acceptmbox + + 2010-01-11: Simon Goldschmidt + * pap.c: Fixed bug #13315 (PPP PAP authentication can result in + erroneous callbacks) by copying the code from recent pppd + + 2010-01-10: Simon Goldschmidt + * raw.c: Fixed bug #28506 (raw_bind should filter received packets) + + 2010-01-10: Simon Goldschmidt + * tcp.h/.c: bug #28127 (remove call to tcp_output() from tcp_ack(_now)()) + + 2010-01-08: Simon Goldschmidt + * sockets.c: Fixed bug #28519 (lwip_recvfrom bug with len > 65535) + + 2010-01-08: Simon Goldschmidt + * dns.c: Copy hostname for DNS_LOCAL_HOSTLIST_IS_DYNAMIC==1 since string + passed to dns_local_addhost() might be volatile + + 2010-01-07: Simon Goldschmidt + * timers.c, tcp.h: Call tcp_timer_needed() with NO_SYS==1, too + + 2010-01-06: Simon Goldschmidt + * netdb.h: Fixed bug #28496: missing include guards in netdb.h + + 2009-12-31: Simon Goldschmidt + * many ppp files: Reorganised PPP source code from ucip structure to pppd + structure to easily compare our code against the pppd code (around v2.3.1) + + 2009-12-27: Simon Goldschmidt + * tcp_in.c: Another fix for bug #28241 (ooseq processing) and adapted + unit test + + +(STABLE-1.3.2) + + ++ New features: + + 2009-10-27 Simon Goldschmidt/Stephan Lesage + * netifapi.c/.h: Added netifapi_netif_set_addr() + + 2009-10-07 Simon Goldschmidt/Fabian Koch + * api_msg.c, netbuf.c/.h, opt.h: patch #6888: Patch for UDP Netbufs to + support dest-addr and dest-port (optional: LWIP_NETBUF_RECVINFO) + + 2009-08-26 Simon Goldschmidt/Simon Kallweit + * slipif.c/.h: bug #26397: SLIP polling support + + 2009-08-25 Simon Goldschmidt + * opt.h, etharp.h/.c: task #9033: Support IEEE 802.1q tagged frame (VLAN), + New configuration options ETHARP_SUPPORT_VLAN and ETHARP_VLAN_CHECK. + + 2009-08-25 Simon Goldschmidt + * ip_addr.h, netdb.c: patch #6900: added define ip_ntoa(struct ip_addr*) + + 2009-08-24 Jakob Stoklund Olesen + * autoip.c, dhcp.c, netif.c: patch #6725: Teach AutoIP and DHCP to respond + to netif_set_link_up(). + + 2009-08-23 Simon Goldschmidt + * tcp.h/.c: Added function tcp_debug_state_str() to convert a tcp state + to a human-readable string. + + ++ Bugfixes: + + 2009-12-24: Kieran Mansley + * tcp_in.c Apply patches from Oleg Tyshev to improve OOS processing + (BUG#28241) + + 2009-12-06: Simon Goldschmidt + * ppp.h/.c: Fixed bug #27079 (Yet another leak in PPP): outpacket_buf can + be statically allocated (like in ucip) + + 2009-12-04: Simon Goldschmidt (patch by Ioardan Neshev) + * pap.c: patch #6969: PPP: missing PAP authentication UNTIMEOUT + + 2009-12-03: Simon Goldschmidt + * tcp.h, tcp_in.c, tcp_out.c: Fixed bug #28106: dup ack for fast retransmit + could have non-zero length + + 2009-12-02: Simon Goldschmidt + * tcp_in.c: Fixed bug #27904: TCP sends too many ACKs: delay resetting + tcp_input_pcb until after calling the pcb's callbacks + + 2009-11-29: Simon Goldschmidt + * tcp_in.c: Fixed bug #28054: Two segments with FIN flag on the out-of- + sequence queue, also fixed PBUF_POOL leak in the out-of-sequence code + + 2009-11-29: Simon Goldschmidt + * pbuf.c: Fixed bug #28064: pbuf_alloc(PBUF_POOL) is not thread-safe by + queueing a call into tcpip_thread to free ooseq-bufs if the pool is empty + + 2009-11-26: Simon Goldschmidt + * tcp.h: Fixed bug #28098: Nagle can prevent fast retransmit from sending + segment + + 2009-11-26: Simon Goldschmidt + * tcp.h, sockets.c: Fixed bug #28099: API required to disable Nagle + algorithm at PCB level + + 2009-11-22: Simon Goldschmidt + * tcp_out.c: Fixed bug #27905: FIN isn't combined with data on unsent + + 2009-11-22: Simon Goldschmidt (suggested by Bill Auerbach) + * tcp.c: tcp_alloc: prevent increasing stats.err for MEMP_TCP_PCB when + reusing time-wait pcb + + 2009-11-20: Simon Goldschmidt (patch by Albert Bartel) + * sockets.c: Fixed bug #28062: Data received directly after accepting + does not wake up select + + 2009-11-11: Simon Goldschmidt + * netdb.h: Fixed bug #27994: incorrect define for freeaddrinfo(addrinfo) + + 2009-10-30: Simon Goldschmidt + * opt.h: Increased default value for TCP_MSS to 536, updated default + value for TCP_WND to 4*TCP_MSS to keep delayed ACK working. + + 2009-10-28: Kieran Mansley + * tcp_in.c, tcp_out.c, tcp.h: re-work the fast retransmission code + to follow algorithm from TCP/IP Illustrated + + 2009-10-27: Kieran Mansley + * tcp_in.c: fix BUG#27445: grow cwnd with every duplicate ACK + + 2009-10-25: Simon Goldschmidt + * tcp.h: bug-fix in the TCP_EVENT_RECV macro (has to call tcp_recved if + pcb->recv is NULL to keep rcv_wnd correct) + + 2009-10-25: Simon Goldschmidt + * tcp_in.c: Fixed bug #26251: RST process in TIME_WAIT TCP state + + 2009-10-23: Simon Goldschmidt (David Empson) + * tcp.c: Fixed bug #27783: Silly window avoidance for small window sizes + + 2009-10-21: Simon Goldschmidt + * tcp_in.c: Fixed bug #27215: TCP sent() callback gives leading and + trailing 1 byte len (SYN/FIN) + + 2009-10-21: Simon Goldschmidt + * tcp_out.c: Fixed bug #27315: zero window probe and FIN + + 2009-10-19: Simon Goldschmidt + * dhcp.c/.h: Minor code simplification (don't store received pbuf, change + conditional code to assert where applicable), check pbuf length before + testing for valid reply + + 2009-10-19: Simon Goldschmidt + * dhcp.c: Removed most calls to udp_connect since they aren't necessary + when using udp_sendto_if() - always stay connected to IP_ADDR_ANY. + + 2009-10-16: Simon Goldschmidt + * ip.c: Fixed bug #27390: Source IP check in ip_input() causes it to drop + valid DHCP packets -> allow 0.0.0.0 as source address when LWIP_DHCP is + enabled + + 2009-10-15: Simon Goldschmidt (Oleg Tyshev) + * tcp_in.c: Fixed bug #27329: dupacks by unidirectional data transmit + + 2009-10-15: Simon Goldschmidt + * api_lib.c: Fixed bug #27709: conn->err race condition on netconn_recv() + timeout + + 2009-10-15: Simon Goldschmidt + * autoip.c: Fixed bug #27704: autoip starts with wrong address + LWIP_AUTOIP_CREATE_SEED_ADDR() returned address in host byte order instead + of network byte order + + 2009-10-11 Simon Goldschmidt (Jörg Kesten) + * tcp_out.c: Fixed bug #27504: tcp_enqueue wrongly concatenates segments + which are not consecutive when retransmitting unacked segments + + 2009-10-09 Simon Goldschmidt + * opt.h: Fixed default values of some stats to only be enabled if used + Fixes bug #27338: sys_stats is defined when NO_SYS = 1 + + 2009-08-30 Simon Goldschmidt + * ip.c: Fixed bug bug #27345: "ip_frag() does not use the LWIP_NETIF_LOOPBACK + function" by checking for loopback before calling ip_frag + + 2009-08-25 Simon Goldschmidt + * dhcp.c: fixed invalid dependency to etharp_query if DHCP_DOES_ARP_CHECK==0 + + 2009-08-23 Simon Goldschmidt + * ppp.c: bug #27078: Possible memory leak in pppInit() + + 2009-08-23 Simon Goldschmidt + * netdb.c, dns.c: bug #26657: DNS, if host name is "localhost", result + is error. + + 2009-08-23 Simon Goldschmidt + * opt.h, init.c: bug #26649: TCP fails when TCP_MSS > TCP_SND_BUF + Fixed wrong parenthesis, added check in init.c + + 2009-08-23 Simon Goldschmidt + * ppp.c: bug #27266: wait-state debug message in pppMain occurs every ms + + 2009-08-23 Simon Goldschmidt + * many ppp files: bug #27267: Added include to string.h where needed + + 2009-08-23 Simon Goldschmidt + * tcp.h: patch #6843: tcp.h macro optimization patch (for little endian) + + +(STABLE-1.3.1) + + ++ New features: + + 2009-05-10 Simon Goldschmidt + * opt.h, sockets.c, pbuf.c, netbuf.h, pbuf.h: task #7013: Added option + LWIP_NETIF_TX_SINGLE_PBUF to try to create transmit packets from only + one pbuf to help MACs that don't support scatter-gather DMA. + + 2009-05-09 Simon Goldschmidt + * icmp.h, icmp.c: Shrinked ICMP code, added option to NOT check icoming + ECHO pbuf for size (just use it): LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN + + 2009-05-05 Simon Goldschmidt, Jakob Stoklund Olesen + * ip.h, ip.c: Added ip_current_netif() & ip_current_header() to receive + extended info about the currently received packet. + + 2009-04-27 Simon Goldschmidt + * sys.h: Made SYS_LIGHTWEIGHT_PROT and sys_now() work with NO_SYS=1 + + 2009-04-25 Simon Goldschmidt + * mem.c, opt.h: Added option MEM_USE_POOLS_TRY_BIGGER_POOL to try the next + bigger malloc pool if one is empty (only usable with MEM_USE_POOLS). + + 2009-04-21 Simon Goldschmidt + * dns.c, init.c, dns.h, opt.h: task #7507, patch #6786: DNS supports static + hosts table. New configuration options DNS_LOCAL_HOSTLIST and + DNS_LOCAL_HOSTLIST_IS_DYNAMIC. Also, DNS_LOOKUP_LOCAL_EXTERN() can be defined + as an external function for lookup. + + 2009-04-15 Simon Goldschmidt + * dhcp.c: patch #6763: Global DHCP XID can be redefined to something more unique + + 2009-03-31 Kieran Mansley + * tcp.c, tcp_out.c, tcp_in.c, sys.h, tcp.h, opts.h: add support for + TCP timestamp options, off by default. Rework tcp_enqueue() to + take option flags rather than specified option data + + 2009-02-18 Simon Goldschmidt + * cc.h: Added printf formatter for size_t: SZT_F + + 2009-02-16 Simon Goldschmidt (patch by Rishi Khan) + * icmp.c, opt.h: patch #6539: (configurable) response to broadcast- and multicast + pings + + 2009-02-12 Simon Goldschmidt + * init.h: Added LWIP_VERSION to get the current version of the stack + + 2009-02-11 Simon Goldschmidt (suggested by Gottfried Spitaler) + * opt.h, memp.h/.c: added MEMP_MEM_MALLOC to use mem_malloc/mem_free instead + of the pool allocator (can save code size with MEM_LIBC_MALLOC if libc-malloc + is otherwise used) + + 2009-01-28 Jonathan Larmour (suggested by Bill Bauerbach) + * ipv4/inet_chksum.c, ipv4/lwip/inet_chksum.h: inet_chksum_pseudo_partial() + is only used by UDPLITE at present, so conditionalise it. + + 2008-12-03 Simon Goldschmidt (base on patch from Luca Ceresoli) + * autoip.c: checked in (slightly modified) patch #6683: Customizable AUTOIP + "seed" address. This should reduce AUTOIP conflicts if + LWIP_AUTOIP_CREATE_SEED_ADDR is overridden. + + 2008-10-02 Jonathan Larmour and Rishi Khan + * sockets.c (lwip_accept): Return EWOULDBLOCK if would block on non-blocking + socket. + + 2008-06-30 Simon Goldschmidt + * mem.c, opt.h, stats.h: fixed bug #21433: Calling mem_free/pbuf_free from + interrupt context isn't safe: LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT allows + mem_free to run between mem_malloc iterations. Added illegal counter for + mem stats. + + 2008-06-27 Simon Goldschmidt + * stats.h/.c, some other files: patch #6483: stats module improvement: + Added defines to display each module's statistic individually, added stats + defines for MEM, MEMP and SYS modules, removed (unused) rexmit counter. + + 2008-06-17 Simon Goldschmidt + * err.h: patch #6459: Made err_t overridable to use a more efficient type + (define LWIP_ERR_T in cc.h) + + 2008-06-17 Simon Goldschmidt + * slipif.c: patch #6480: Added a configuration option for slipif for symmetry + to loopif + + 2008-06-17 Simon Goldschmidt (patch by Luca Ceresoli) + * netif.c, loopif.c, ip.c, netif.h, loopif.h, opt.h: Checked in slightly + modified version of patch # 6370: Moved loopif code to netif.c so that + loopback traffic is supported on all netifs (all local IPs). + Added option to limit loopback packets for each netifs. + + + ++ Bugfixes: + 2009-08-12 Kieran Mansley + * tcp_in.c, tcp.c: Fix bug #27209: handle trimming of segments when + out of window or out of order properly + + 2009-08-12 Kieran Mansley + * tcp_in.c: Fix bug #27199: use snd_wl2 instead of snd_wl1 + + 2009-07-28 Simon Goldschmidt + * mem.h: Fixed bug #27105: "realloc() cannot replace mem_realloc()"s + + 2009-07-27 Kieran Mansley + * api.h api_msg.h netdb.h sockets.h: add missing #include directives + + 2009-07-09 Kieran Mansley + * api_msg.c, sockets.c, api.h: BUG23240 use signed counters for + recv_avail and don't increment counters until message successfully + sent to mbox + + 2009-06-25 Kieran Mansley + * api_msg.c api.h: BUG26722: initialise netconn write variables + in netconn_alloc + + 2009-06-25 Kieran Mansley + * tcp.h: BUG26879: set ret value in TCP_EVENT macros when function is not set + + 2009-06-25 Kieran Mansley + * tcp.c, tcp_in.c, tcp_out.c, tcp.h: BUG26301 and BUG26267: correct + simultaneous close behaviour, and make snd_nxt have the same meaning + as in the RFCs. + + 2009-05-12 Simon Goldschmidt + * etharp.h, etharp.c, netif.c: fixed bug #26507: "Gratuitous ARP depends on + arp_table / uses etharp_query" by adding etharp_gratuitous() + + 2009-05-12 Simon Goldschmidt + * ip.h, ip.c, igmp.c: bug #26487: Added ip_output_if_opt that can add IP options + to the IP header (used by igmp_ip_output_if) + + 2009-05-06 Simon Goldschmidt + * inet_chksum.c: On little endian architectures, use LWIP_PLATFORM_HTONS (if + defined) for SWAP_BYTES_IN_WORD to speed up checksumming. + + 2009-05-05 Simon Goldschmidt + * sockets.c: bug #26405: Prematurely released semaphore causes lwip_select() + to crash + + 2009-05-04 Simon Goldschmidt + * init.c: snmp was not initialized in lwip_init() + + 2009-05-04 Frédéric Bernon + * dhcp.c, netbios.c: Changes if IP_SOF_BROADCAST is enabled. + + 2009-05-03 Simon Goldschmidt + * tcp.h: bug #26349: Nagle algorithm doesn't send although segment is full + (and unsent->next == NULL) + + 2009-05-02 Simon Goldschmidt + * tcpip.h, tcpip.c: fixed tcpip_untimeout (does not need the time, broken after + 1.3.0 in CVS only) - fixes compilation of ppp_oe.c + + 2009-05-02 Simon Goldschmidt + * msg_in.c: fixed bug #25636: SNMPSET value is ignored for integer fields + + 2009-05-01 Simon Goldschmidt + * pap.c: bug #21680: PPP upap_rauthnak() drops legal NAK packets + + 2009-05-01 Simon Goldschmidt + * ppp.c: bug #24228: Memory corruption with PPP and DHCP + + 2009-04-29 Frédéric Bernon + * raw.c, udp.c, init.c, opt.h, ip.h, sockets.h: bug #26309: Implement the + SO(F)_BROADCAST filter for all API layers. Avoid the unindented reception + of broadcast packets even when this option wasn't set. Port maintainers + which want to enable this filter have to set IP_SOF_BROADCAST=1 in opt.h. + If you want this option also filter broadcast on recv operations, you also + have to set IP_SOF_BROADCAST_RECV=1 in opt.h. + + 2009-04-28 Simon Goldschmidt, Jakob Stoklund Olesen + * dhcp.c: patch #6721, bugs #25575, #25576: Some small fixes to DHCP and + DHCP/AUTOIP cooperation + + 2009-04-25 Simon Goldschmidt, Oleg Tyshev + * tcp_out.c: bug #24212: Deadlocked tcp_retransmit due to exceeded pcb->cwnd + Fixed by sorting the unsent and unacked queues (segments are inserted at the + right place in tcp_output and tcp_rexmit). + + 2009-04-25 Simon Goldschmidt + * memp.c, mem.c, memp.h, mem_std.h: bug #26213 "Problem with memory allocation + when debugging": memp_sizes contained the wrong sizes (including sanity + regions); memp pools for MEM_USE_POOLS were too small + + 2009-04-24 Simon Goldschmidt, Frédéric Bernon + * inet.c: patch #6765: Fix a small problem with the last changes (incorrect + behavior, with with ip address string not ended by a '\0', a space or a + end of line) + + 2009-04-19 Simon Goldschmidt + * rawapi.txt: Fixed bug #26069: Corrected documentation: if tcp_connect fails, + pcb->err is called, not pcb->connected (with an error code). + + 2009-04-19 Simon Goldschmidt + * tcp_out.c: Fixed bug #26236: "TCP options (timestamp) don't work with + no-copy-tcpwrite": deallocate option data, only concat segments with same flags + + 2009-04-19 Simon Goldschmidt + * tcp_out.c: Fixed bug #25094: "Zero-length pbuf" (options are now allocated + in the header pbuf, not the data pbuf) + + 2009-04-18 Simon Goldschmidt + * api_msg.c: fixed bug #25695: Segmentation fault in do_writemore() + + 2009-04-15 Simon Goldschmidt + * sockets.c: tried to fix bug #23559: lwip_recvfrom problem with tcp + + 2009-04-15 Simon Goldschmidt + * dhcp.c: task #9192: mem_free of dhcp->options_in and dhcp->msg_in + + 2009-04-15 Simon Goldschmidt + * ip.c, ip6.c, tcp_out.c, ip.h: patch #6808: Add a utility function + ip_hinted_output() (for smaller code mainly) + + 2009-04-15 Simon Goldschmidt + * inet.c: patch #6765: Supporting new line characters in inet_aton() + + 2009-04-15 Simon Goldschmidt + * dhcp.c: patch #6764: DHCP rebind and renew did not send hostnam option; + Converted constant OPTION_MAX_MSG_SIZE to netif->mtu, check if netif->mtu + is big enough in dhcp_start + + 2009-04-15 Simon Goldschmidt + * netbuf.c: bug #26027: netbuf_chain resulted in pbuf memory leak + + 2009-04-15 Simon Goldschmidt + * sockets.c, ppp.c: bug #25763: corrected 4 occurrences of SMEMCPY to MEMCPY + + 2009-04-15 Simon Goldschmidt + * sockets.c: bug #26121: set_errno can be overridden + + 2009-04-09 Kieran Mansley (patch from Luca Ceresoli ) + * init.c, opt.h: Patch#6774 TCP_QUEUE_OOSEQ breaks compilation when + LWIP_TCP==0 + + 2009-04-09 Kieran Mansley (patch from Roy Lee ) + * tcp.h: Patch#6802 Add do-while-clauses to those function like + macros in tcp.h + + 2009-03-31 Kieran Mansley + * tcp.c, tcp_in.c, tcp_out.c, tcp.h, opt.h: Rework the way window + updates are calculated and sent (BUG20515) + + * tcp_in.c: cope with SYN packets received during established states, + and retransmission of initial SYN. + + * tcp_out.c: set push bit correctly when tcp segments are merged + + 2009-03-27 Kieran Mansley + * tcp_out.c set window correctly on probes (correcting change made + yesterday) + + 2009-03-26 Kieran Mansley + * tcp.c, tcp_in.c, tcp.h: add tcp_abandon() to cope with dropping + connections where no reset required (bug #25622) + + * tcp_out.c: set TCP_ACK flag on keepalive and zero window probes + (bug #20779) + + 2009-02-18 Simon Goldschmidt (Jonathan Larmour and Bill Auerbach) + * ip_frag.c: patch #6528: the buffer used for IP_FRAG_USES_STATIC_BUF could be + too small depending on MEM_ALIGNMENT + + 2009-02-16 Simon Goldschmidt + * sockets.h/.c, api_*.h/.c: fixed arguments of socket functions to match the standard; + converted size argument of netconn_write to 'size_t' + + 2009-02-16 Simon Goldschmidt + * tcp.h, tcp.c: fixed bug #24440: TCP connection close problem on 64-bit host + by moving accept callback function pointer to TCP_PCB_COMMON + + 2009-02-12 Simon Goldschmidt + * dhcp.c: fixed bug #25345 (DHCPDECLINE is sent with "Maximum message size" + option) + + 2009-02-11 Simon Goldschmidt + * dhcp.c: fixed bug #24480 (releasing old udp_pdb and pbuf in dhcp_start) + + 2009-02-11 Simon Goldschmidt + * opt.h, api_msg.c: added configurable default valud for netconn->recv_bufsize: + RECV_BUFSIZE_DEFAULT (fixes bug #23726: pbuf pool exhaustion on slow recv()) + + 2009-02-10 Simon Goldschmidt + * tcp.c: fixed bug #25467: Listen backlog is not reset on timeout in SYN_RCVD: + Accepts_pending is decrease on a corresponding listen pcb when a connection + in state SYN_RCVD is close. + + 2009-01-28 Jonathan Larmour + * pbuf.c: reclaim pbufs from TCP out-of-sequence segments if we run + out of pool pbufs. + + 2008-12-19 Simon Goldschmidt + * many files: patch #6699: fixed some warnings on platform where sizeof(int) == 2 + + 2008-12-10 Tamas Somogyi, Frédéric Bernon + * sockets.c: fixed bug #25051: lwip_recvfrom problem with udp: fromaddr and + port uses deleted netbuf. + + 2008-10-18 Simon Goldschmidt + * tcp_in.c: fixed bug ##24596: Vulnerability on faulty TCP options length + in tcp_parseopt + + 2008-10-15 Simon Goldschmidt + * ip_frag.c: fixed bug #24517: IP reassembly crashes on unaligned IP headers + by packing the struct ip_reass_helper. + + 2008-10-03 David Woodhouse, Jonathan Larmour + * etharp.c (etharp_arp_input): Fix type aliasing problem copying ip address. + + 2008-10-02 Jonathan Larmour + * dns.c: Hard-code structure sizes, to avoid issues on some compilers where + padding is included. + + 2008-09-30 Jonathan Larmour + * sockets.c (lwip_accept): check addr isn't NULL. If it's valid, do an + assertion check that addrlen isn't NULL. + + 2008-09-30 Jonathan Larmour + * tcp.c: Fix bug #24227, wrong error message in tcp_bind. + + 2008-08-26 Simon Goldschmidt + * inet.h, ip_addr.h: fixed bug #24132: Cross-dependency between ip_addr.h and + inet.h -> moved declaration of struct in_addr from ip_addr.h to inet.h + + 2008-08-14 Simon Goldschmidt + * api_msg.c: fixed bug #23847: do_close_internal references freed memory (when + tcp_close returns != ERR_OK) + + 2008-07-08 Frédéric Bernon + * stats.h: Fix some build bugs introduced with patch #6483 (missing some parameters + in macros, mainly if MEM_STATS=0 and MEMP_STATS=0). + + 2008-06-24 Jonathan Larmour + * tcp_in.c: Fix for bug #23693 as suggested by Art R. Ensure cseg is unused + if tcp_seg_copy fails. + + 2008-06-17 Simon Goldschmidt + * inet_chksum.c: Checked in some ideas of patch #6460 (loop optimizations) + and created defines for swapping bytes and folding u32 to u16. + + 2008-05-30 Kieran Mansley + * tcp_in.c Remove redundant "if" statement, and use real rcv_wnd + rather than rcv_ann_wnd when deciding if packets are in-window. + Contributed by + + 2008-05-30 Kieran Mansley + * mem.h: Fix BUG#23254. Change macro definition of mem_* to allow + passing as function pointers when MEM_LIBC_MALLOC is defined. + + 2008-05-09 Jonathan Larmour + * err.h, err.c, sockets.c: Fix bug #23119: Reorder timeout error code to + stop it being treated as a fatal error. + + 2008-04-15 Simon Goldschmidt + * dhcp.c: fixed bug #22804: dhcp_stop doesn't clear NETIF_FLAG_DHCP + (flag now cleared) + + 2008-03-27 Simon Goldschmidt + * mem.c, tcpip.c, tcpip.h, opt.h: fixed bug #21433 (Calling mem_free/pbuf_free + from interrupt context isn't safe): set LWIP_USE_HEAP_FROM_INTERRUPT to 1 + in lwipopts.h or use pbuf_free_callback(p)/mem_free_callback(m) to free pbufs + or heap memory from interrupt context + + 2008-03-26 Simon Goldschmidt + * tcp_in.c, tcp.c: fixed bug #22249: division by zero could occur if a remote + host sent a zero mss as TCP option. + + +(STABLE-1.3.0) + + ++ New features: + + 2008-03-10 Jonathan Larmour + * inet_chksum.c: Allow choice of one of the sample algorithms to be + made from lwipopts.h. Fix comment on how to override LWIP_CHKSUM. + + 2008-01-22 Frédéric Bernon + * tcp.c, tcp_in.c, tcp.h, opt.h: Rename LWIP_CALCULATE_EFF_SEND_MSS in + TCP_CALCULATE_EFF_SEND_MSS to have coherent TCP options names. + + 2008-01-14 Frédéric Bernon + * rawapi.txt, api_msg.c, tcp.c, tcp_in.c, tcp.h: changes for task #7675 "Enable + to refuse data on a TCP_EVENT_RECV call". Important, behavior changes for the + tcp_recv callback (see rawapi.txt). + + 2008-01-14 Frédéric Bernon, Marc Chaland + * ip.c: Integrate patch #6369" ip_input : checking before realloc". + + 2008-01-12 Frédéric Bernon + * tcpip.h, tcpip.c, api.h, api_lib.c, api_msg.c, sockets.c: replace the field + netconn::sem per netconn::op_completed like suggested for the task #7490 + "Add return value to sys_mbox_post". + + 2008-01-12 Frédéric Bernon + * api_msg.c, opt.h: replace DEFAULT_RECVMBOX_SIZE per DEFAULT_TCP_RECVMBOX_SIZE, + DEFAULT_UDP_RECVMBOX_SIZE and DEFAULT_RAW_RECVMBOX_SIZE (to optimize queues + sizes), like suggested for the task #7490 "Add return value to sys_mbox_post". + + 2008-01-10 Frédéric Bernon + * tcpip.h, tcpip.c: add tcpip_callback_with_block function for the task #7490 + "Add return value to sys_mbox_post". tcpip_callback is always defined as + "blocking" ("block" parameter = 1). + + 2008-01-10 Frédéric Bernon + * tcpip.h, tcpip.c, api.h, api_lib.c, api_msg.c, sockets.c: replace the field + netconn::mbox (sys_mbox_t) per netconn::sem (sys_sem_t) for the task #7490 + "Add return value to sys_mbox_post". + + 2008-01-05 Frédéric Bernon + * sys_arch.txt, api.h, api_lib.c, api_msg.h, api_msg.c, tcpip.c, sys.h, opt.h: + Introduce changes for task #7490 "Add return value to sys_mbox_post" with some + modifications in the sys_mbox api: sys_mbox_new take a "size" parameters which + indicate the number of pointers query by the mailbox. There is three defines + in opt.h to indicate sizes for tcpip::mbox, netconn::recvmbox, and for the + netconn::acceptmbox. Port maintainers, you can decide to just add this new + parameter in your implementation, but to ignore it to keep the previous behavior. + The new sys_mbox_trypost function return a value to know if the mailbox is + full or if the message is posted. Take a look to sys_arch.txt for more details. + This new function is used in tcpip_input (so, can be called in an interrupt + context since the function is not blocking), and in recv_udp and recv_raw. + + 2008-01-04 Frédéric Bernon, Simon Goldschmidt, Jonathan Larmour + * rawapi.txt, api.h, api_lib.c, api_msg.h, api_msg.c, sockets.c, tcp.h, tcp.c, + tcp_in.c, init.c, opt.h: rename backlog options with TCP_ prefix, limit the + "backlog" parameter in an u8_t, 0 is interpreted as "smallest queue", add + documentation in the rawapi.txt file. + + 2007-12-31 Kieran Mansley (based on patch from Per-Henrik Lundbolm) + * tcp.c, tcp_in.c, tcp_out.c, tcp.h: Add TCP persist timer + + 2007-12-31 Frédéric Bernon, Luca Ceresoli + * autoip.c, etharp.c: ip_addr.h: Integrate patch #6348: "Broadcast ARP packets + in autoip". The change in etharp_raw could be removed, since all calls to + etharp_raw use ethbroadcast for the "ethdst_addr" parameter. But it could be + wrong in the future. + + 2007-12-30 Frédéric Bernon, Tom Evans + * ip.c: Fix bug #21846 "LwIP doesn't appear to perform any IP Source Address + Filtering" reported by Tom Evans. + + 2007-12-21 Frédéric Bernon, Simon Goldschmidt, Jonathan Larmour + * tcp.h, opt.h, api.h, api_msg.h, tcp.c, tcp_in.c, api_lib.c, api_msg.c, + sockets.c, init.c: task #7252: Implement TCP listen backlog: Warning: raw API + applications have to call 'tcp_accepted(pcb)' in their accept callback to + keep accepting new connections. + + 2007-12-13 Frédéric Bernon + * api_msg.c, err.h, err.c, sockets.c, dns.c, dns.h: replace "enum dns_result" + by err_t type. Add a new err_t code "ERR_INPROGRESS". + + 2007-12-12 Frédéric Bernon + * dns.h, dns.c, opt.h: move DNS options to the "right" place. Most visibles + are the one which have ram usage. + + 2007-12-05 Frédéric Bernon + * netdb.c: add a LWIP_DNS_API_HOSTENT_STORAGE option to decide to use a static + set of variables (=0) or a local one (=1). In this last case, your port should + provide a function "struct hostent* sys_thread_hostent( struct hostent* h)" + which have to do a copy of "h" and return a pointer ont the "per-thread" copy. + + 2007-12-03 Simon Goldschmidt + * ip.c: ip_input: check if a packet is for inp first before checking all other + netifs on netif_list (speeds up packet receiving in most cases) + + 2007-11-30 Simon Goldschmidt + * udp.c, raw.c: task #7497: Sort lists (pcb, netif, ...) for faster access + UDP: move a (connected) pcb selected for input to the front of the list of + pcbs so that it is found faster next time. Same for RAW pcbs that have eaten + a packet. + + 2007-11-28 Simon Goldschmidt + * etharp.c, stats.c, stats.h, opt.h: Introduced ETHARP_STATS + + 2007-11-25 Simon Goldschmidt + * dhcp.c: dhcp_unfold_reply() uses pbuf_copy_partial instead of its own copy + algorithm. + + 2007-11-24 Simon Goldschmidt + * netdb.h, netdb.c, sockets.h/.c: Moved lwip_gethostbyname from sockets.c + to the new file netdb.c; included lwip_getaddrinfo. + + 2007-11-21 Simon Goldschmidt + * tcp.h, opt.h, tcp.c, tcp_in.c: implemented calculating the effective send-mss + based on the MTU of the netif used to send. Enabled by default. Disable by + setting LWIP_CALCULATE_EFF_SEND_MSS to 0. This fixes bug #21492. + + 2007-11-19 Frédéric Bernon + * api_msg.c, dns.h, dns.c: Implement DNS_DOES_NAME_CHECK option (check if name + received match the name query), implement DNS_USES_STATIC_BUF (the place where + copy dns payload to parse the response), return an error if there is no place + for a new query, and fix some minor problems. + + 2007-11-16 Simon Goldschmidt + * new files: ipv4/inet.c, ipv4/inet_chksum.c, ipv6/inet6.c + removed files: core/inet.c, core/inet6.c + Moved inet files into ipv4/ipv6 directory; splitted inet.c/inet.h into + inet and chksum part; changed includes in all lwIP files as appropriate + + 2007-11-16 Simon Goldschmidt + * api.h, api_msg.h, api_lib.c, api_msg.c, socket.h, socket.c: Added sequential + dns resolver function for netconn api (netconn_gethostbyname) and socket api + (gethostbyname/gethostbyname_r). + + 2007-11-15 Jim Pettinato, Frédéric Bernon + * opt.h, init.c, tcpip.c, dhcp.c, dns.h, dns.c: add DNS client for simple name + requests with RAW api interface. Initialization is done in lwip_init() with + build time options. DNS timer is added in tcpip_thread context. DHCP can set + DNS server ip addresses when options are received. You need to set LWIP_DNS=1 + in your lwipopts.h file (LWIP_DNS=0 in opt.h). DNS_DEBUG can be set to get + some traces with LWIP_DEBUGF. Sanity check have been added. There is a "todo" + list with points to improve. + + 2007-11-06 Simon Goldschmidt + * opt.h, mib2.c: Patch #6215: added ifAdminStatus write support (if explicitly + enabled by defining SNMP_SAFE_REQUESTS to 0); added code to check link status + for ifOperStatus if LWIP_NETIF_LINK_CALLBACK is defined. + + 2007-11-06 Simon Goldschmidt + * api.h, api_msg.h and dependent files: Task #7410: Removed the need to include + core header files in api.h (ip/tcp/udp/raw.h) to hide the internal + implementation from netconn api applications. + + 2007-11-03 Frédéric Bernon + * api.h, api_lib.c, api_msg.c, sockets.c, opt.h: add SO_RCVBUF option for UDP & + RAW netconn. You need to set LWIP_SO_RCVBUF=1 in your lwipopts.h (it's disabled + by default). Netconn API users can use the netconn_recv_bufsize macro to access + it. This is a first release which have to be improve for TCP. Note it used the + netconn::recv_avail which need to be more "thread-safe" (note there is already + the problem for FIONREAD with lwip_ioctl/ioctlsocket). + + 2007-11-01 Frédéric Bernon, Marc Chaland + * sockets.h, sockets.c, api.h, api_lib.c, api_msg.h, api_msg.c, tcp.h, tcp_out.c: + Integrate "patch #6250 : MSG_MORE flag for send". MSG_MORE is used at socket api + layer, NETCONN_MORE at netconn api layer, and TCP_WRITE_FLAG_MORE at raw api + layer. This option enable to delayed TCP PUSH flag on multiple "write" calls. + Note that previous "copy" parameter for "write" APIs is now called "apiflags". + + 2007-10-24 Frédéric Bernon + * api.h, api_lib.c, api_msg.c: Add macro API_EVENT in the same spirit than + TCP_EVENT_xxx macros to get a code more readable. It could also help to remove + some code (like we have talk in "patch #5919 : Create compile switch to remove + select code"), but it could be done later. + + 2007-10-08 Simon Goldschmidt + * many files: Changed initialization: many init functions are not needed any + more since we now rely on the compiler initializing global and static + variables to zero! + + 2007-10-06 Simon Goldschmidt + * ip_frag.c, memp.c, mib2.c, ip_frag.h, memp_std.h, opt.h: Changed IP_REASSEMBLY + to enqueue the received pbufs so that multiple packets can be reassembled + simultaneously and no static reassembly buffer is needed. + + 2007-10-05 Simon Goldschmidt + * tcpip.c, etharp.h, etharp.c: moved ethernet_input from tcpip.c to etharp.c so + all netifs (or ports) can use it. + + 2007-10-05 Frédéric Bernon + * netifapi.h, netifapi.c: add function netifapi_netif_set_default. Change the + common function to reduce a little bit the footprint (for all functions using + only the "netif" parameter). + + 2007-10-03 Frédéric Bernon + * netifapi.h, netifapi.c: add functions netifapi_netif_set_up, netifapi_netif_set_down, + netifapi_autoip_start and netifapi_autoip_stop. Use a common function to reduce + a little bit the footprint (for all functions using only the "netif" parameter). + + 2007-09-15 Frédéric Bernon + * udp.h, udp.c, sockets.c: Changes for "#20503 IGMP Improvement". Add IP_MULTICAST_IF + option in socket API, and a new field "multicast_ip" in "struct udp_pcb" (for + netconn and raw API users), only if LWIP_IGMP=1. Add getsockopt processing for + IP_MULTICAST_TTL and IP_MULTICAST_IF. + + 2007-09-10 Frédéric Bernon + * snmp.h, mib2.c: enable to remove SNMP timer (which consumne several cycles + even when it's not necessary). snmp_agent.txt tell to call snmp_inc_sysuptime() + each 10ms (but, it's intrusive if you use sys_timeout feature). Now, you can + decide to call snmp_add_sysuptime(100) each 1000ms (which is bigger "step", but + call to a lower frequency). Or, you can decide to not call snmp_inc_sysuptime() + or snmp_add_sysuptime(), and to define the SNMP_GET_SYSUPTIME(sysuptime) macro. + This one is undefined by default in mib2.c. SNMP_GET_SYSUPTIME is called inside + snmp_get_sysuptime(u32_t *value), and enable to change "sysuptime" value only + when it's queried (any direct call to "sysuptime" is changed by a call to + snmp_get_sysuptime). + + 2007-09-09 Frédéric Bernon, Bill Florac + * igmp.h, igmp.c, netif.h, netif.c, ip.c: To enable to have interfaces with IGMP, + and others without it, there is a new NETIF_FLAG_IGMP flag to set in netif->flags + if you want IGMP on an interface. igmp_stop() is now called inside netif_remove(). + igmp_report_groups() is now called inside netif_set_link_up() (need to have + LWIP_NETIF_LINK_CALLBACK=1) to resend reports once the link is up (avoid to wait + the next query message to receive the matching multicast streams). + + 2007-09-08 Frédéric Bernon + * sockets.c, ip.h, api.h, tcp.h: declare a "struct ip_pcb" which only contains + IP_PCB. Add in the netconn's "pcb" union a "struct ip_pcb *ip;" (no size change). + Use this new field to access to common pcb fields (ttl, tos, so_options, etc...). + Enable to access to these fields with LWIP_TCP=0. + + 2007-09-05 Frédéric Bernon + * udp.c, ipv4/icmp.c, ipv4/ip.c, ipv6/icmp.c, ipv6/ip6.c, ipv4/icmp.h, + ipv6/icmp.h, opt.h: Integrate "task #7272 : LWIP_ICMP option". The new option + LWIP_ICMP enable/disable ICMP module inside the IP stack (enable per default). + Be careful, disabling ICMP make your product non-compliant to RFC1122, but + help to reduce footprint, and to reduce "visibility" on the Internet. + + 2007-09-05 Frédéric Bernon, Bill Florac + * opt.h, sys.h, tcpip.c, slipif.c, ppp.c, sys_arch.txt: Change parameters list + for sys_thread_new (see "task #7252 : Create sys_thread_new_ex()"). Two new + parameters have to be provided: a task name, and a task stack size. For this + one, since it's platform dependant, you could define the best one for you in + your lwipopts.h. For port maintainers, you can just add these new parameters + in your sys_arch.c file, and but it's not mandatory, use them in your OS + specific functions. + + 2007-09-05 Frédéric Bernon + * inet.c, autoip.c, msg_in.c, msg_out.c, init.c: Move some build time checkings + inside init.c for task #7142 "Sanity check user-configurable values". + + 2007-09-04 Frédéric Bernon, Bill Florac + * igmp.h, igmp.c, memp_std.h, memp.c, init.c, opt.h: Replace mem_malloc call by + memp_malloc, and use a new MEMP_NUM_IGMP_GROUP option (see opt.h to define the + value). It will avoid potential fragmentation problems, use a counter to know + how many times a group is used on an netif, and free it when all applications + leave it. MEMP_NUM_IGMP_GROUP got 8 as default value (and init.c got a sanity + check if LWIP_IGMP!=0). + + 2007-09-03 Frédéric Bernon + * igmp.h, igmp.c, sockets.c, api_msg.c: Changes for "#20503 IGMP Improvement". + Initialize igmp_mac_filter to NULL in netif_add (this field should be set in + the netif's "init" function). Use the "imr_interface" field (for socket layer) + and/or the "interface" field (for netconn layer), for join/leave operations. + The igmp_join/leavegroup first parameter change from a netif to an ipaddr. + This field could be a netif's ipaddr, or "any" (same meaning than ip_addr_isany). + + 2007-08-30 Frédéric Bernon + * Add netbuf.h, netbuf.c, Change api.h, api_lib.c: #7249 "Split netbuf functions + from api/api_lib". Now netbuf API is independant of netconn, and can be used + with other API (application based on raw API, or future "socket2" API). Ports + maintainers just have to add src/api/netbuf.c in their makefile/projects. + + 2007-08-30 Frédéric Bernon, Jonathan Larmour + * init.c: Add first version of lwip_sanity_check for task #7142 "Sanity check + user-configurable values". + + 2007-08-29 Frédéric Bernon + * igmp.h, igmp.c, tcpip.c, init.c, netif.c: change igmp_init and add igmp_start. + igmp_start is call inside netif_add. Now, igmp initialization is in the same + spirit than the others modules. Modify some IGMP debug traces. + + 2007-08-29 Frédéric Bernon + * Add init.h, init.c, Change opt.h, tcpip.c: Task #7213 "Add a lwip_init function" + Add lwip_init function to regroup all modules initializations, and to provide + a place to add code for task #7142 "Sanity check user-configurable values". + Ports maintainers should remove direct initializations calls from their code, + and add init.c in their makefiles. Note that lwip_init() function is called + inside tcpip_init, but can also be used by raw api users since all calls are + disabled when matching options are disabled. Also note that their is new options + in opt.h, you should configure in your lwipopts.h (they are enabled per default). + + 2007-08-26 Marc Boucher + * api_msg.c: do_close_internal(): Reset the callbacks and arg (conn) to NULL + since they can under certain circumstances be called with an invalid conn + pointer after the connection has been closed (and conn has been freed). + + 2007-08-25 Frédéric Bernon (Artem Migaev's Patch) + * netif.h, netif.c: Integrate "patch #6163 : Function to check if link layer is up". + Add a netif_is_link_up() function if LWIP_NETIF_LINK_CALLBACK option is set. + + 2007-08-22 Frédéric Bernon + * netif.h, netif.c, opt.h: Rename LWIP_NETIF_CALLBACK in LWIP_NETIF_STATUS_CALLBACK + to be coherent with new LWIP_NETIF_LINK_CALLBACK option before next release. + + 2007-08-22 Frédéric Bernon + * tcpip.h, tcpip.c, ethernetif.c, opt.h: remove options ETHARP_TCPIP_INPUT & + ETHARP_TCPIP_ETHINPUT, now, only "ethinput" code is supported, even if the + name is tcpip_input (we keep the name of 1.2.0 function). + + 2007-08-17 Jared Grubb + * memp_std.h, memp.h, memp.c, mem.c, stats.c: (Task #7136) Centralize mempool + settings into new memp_std.h and optional user file lwippools.h. This adds + more dynamic mempools, and allows the user to create an arbitrary number of + mempools for mem_malloc. + + 2007-08-16 Marc Boucher + * api_msg.c: Initialize newconn->state to NETCONN_NONE in accept_function; + otherwise it was left to NETCONN_CLOSE and sent_tcp() could prematurely + close the connection. + + 2007-08-16 Marc Boucher + * sockets.c: lwip_accept(): check netconn_peer() error return. + + 2007-08-16 Marc Boucher + * mem.c, mem.h: Added mem_calloc(). + + 2007-08-16 Marc Boucher + * tcpip.c, tcpip.h memp.c, memp.h: Added distinct memp (MEMP_TCPIP_MSG_INPKT) + for input packets to prevent floods from consuming all of MEMP_TCPIP_MSG + and starving other message types. + Renamed MEMP_TCPIP_MSG to MEMP_TCPIP_MSG_API + + 2007-08-16 Marc Boucher + * pbuf.c, pbuf.h, etharp.c, tcp_in.c, sockets.c: Split pbuf flags in pbuf + type and flgs (later renamed to flags). + Use enum pbuf_flag as pbuf_type. Renumber PBUF_FLAG_*. + Improved lwip_recvfrom(). TCP push now propagated. + + 2007-08-16 Marc Boucher + * ethernetif.c, contrib/ports/various: ethbroadcast now a shared global + provided by etharp. + + 2007-08-16 Marc Boucher + * ppp_oe.c ppp_oe.h, auth.c chap.c fsm.c lcp.c ppp.c ppp.h, + etharp.c ethernetif.c, etharp.h, opt.h tcpip.h, tcpip.c: + Added PPPoE support and various PPP improvements. + + 2007-07-25 Simon Goldschmidt + * api_lib.c, ip_frag.c, pbuf.c, api.h, pbuf.h: Introduced pbuf_copy_partial, + making netbuf_copy_partial use this function. + + 2007-07-25 Simon Goldschmidt + * tcp_in.c: Fix bug #20506: Slow start / initial congestion window starts with + 2 * mss (instead of 1 * mss previously) to comply with some newer RFCs and + other stacks. + + 2007-07-13 Jared Grubb (integrated by Frédéric Bernon) + * opt.h, netif.h, netif.c, ethernetif.c: Add new configuration option to add + a link callback in the netif struct, and functions to handle it. Be carefull + for port maintainers to add the NETIF_FLAG_LINK_UP flag (like in ethernetif.c) + if you want to be sure to be compatible with future changes... + + 2007-06-30 Frédéric Bernon + * sockets.h, sockets.c: Implement MSG_PEEK flag for recv/recvfrom functions. + + 2007-06-21 Simon Goldschmidt + * etharp.h, etharp.c: Combined etharp_request with etharp_raw for both + LWIP_AUTOIP =0 and =1 to remove redundant code. + + 2007-06-21 Simon Goldschmidt + * mem.c, memp.c, mem.h, memp.h, opt.h: task #6863: Introduced the option + MEM_USE_POOLS to use 4 pools with different sized elements instead of a + heap. This both prevents memory fragmentation and gives a higher speed + at the cost of more memory consumption. Turned off by default. + + 2007-06-21 Simon Goldschmidt + * api_lib.c, api_msg.c, api.h, api_msg.h: Converted the length argument of + netconn_write (and therefore also api_msg_msg.msg.w.len) from u16_t into + int to be able to send a bigger buffer than 64K with one time (mainly + used from lwip_send). + + 2007-06-21 Simon Goldschmidt + * tcp.h, api_msg.c: Moved the nagle algorithm from netconn_write/do_write + into a define (tcp_output_nagle) in tcp.h to provide it to raw api users, too. + + 2007-06-21 Simon Goldschmidt + * api.h, api_lib.c, api_msg.c: Fixed bug #20021: Moved sendbuf-processing in + netconn_write from api_lib.c to api_msg.c to also prevent multiple context- + changes on low memory or empty send-buffer. + + 2007-06-18 Simon Goldschmidt + * etharp.c, etharp.h: Changed etharp to use a defined hardware address length + of 6 to avoid loading netif->hwaddr_len every time (since this file is only + used for ethernet and struct eth_addr already had a defined length of 6). + + 2007-06-17 Simon Goldschmidt + * sockets.c, sockets.h: Implemented socket options SO_NO_CHECK for UDP sockets + to disable UDP checksum generation on transmit. + + 2007-06-13 Frédéric Bernon, Simon Goldschmidt + * debug.h, api_msg.c: change LWIP_ERROR to use it to check errors like invalid + pointers or parameters, and let the possibility to redefined it in cc.h. Use + this macro to check "conn" parameter in api_msg.c functions. + + 2007-06-11 Simon Goldschmidt + * sockets.c, sockets.h: Added UDP lite support for sockets + + 2007-06-10 Simon Goldschmidt + * udp.h, opt.h, api_msg.c, ip.c, udp.c: Included switch LWIP_UDPLITE (enabled + by default) to switch off UDP-Lite support if not needed (reduces udp.c code + size) + + 2007-06-09 Dominik Spies (integrated by Frédéric Bernon) + * autoip.h, autoip.c, dhcp.h, dhcp.c, netif.h, netif.c, etharp.h, etharp.c, opt.h: + AutoIP implementation available for IPv4, with new options LWIP_AUTOIP and + LWIP_DHCP_AUTOIP_COOP if you want to cooperate with DHCP. Some tips to adapt + (see TODO mark in the source code). + + 2007-06-09 Simon Goldschmidt + * etharp.h, etharp.c, ethernetif.c: Modified order of parameters for + etharp_output() to match netif->output so etharp_output() can be used + directly as netif->output to save one function call. + + 2007-06-08 Simon Goldschmidt + * netif.h, ethernetif.c, slipif.c, loopif.c: Added define + NETIF_INIT_SNMP(netif, type, speed) to initialize per-netif snmp variables, + added initialization of those to ethernetif, slipif and loopif. + + 2007-05-18 Simon Goldschmidt + * opt.h, ip_frag.c, ip_frag.h, ip.c: Added option IP_FRAG_USES_STATIC_BUF + (defaulting to off for now) that can be set to 0 to send fragmented + packets by passing PBUF_REFs down the stack. + + 2007-05-23 Frédéric Bernon + * api_lib.c: Implement SO_RCVTIMEO for accept and recv on TCP + connections, such present in patch #5959. + + 2007-05-23 Frédéric Bernon + * api.h, api_lib.c, api_msg.c, sockets.c: group the different NETCONN_UDPxxx + code in only one part... + + 2007-05-18 Simon Goldschmidt + * opt.h, memp.h, memp.c: Added option MEMP_OVERFLOW_CHECK to check for memp + elements to overflow. This is achieved by adding some bytes before and after + each pool element (increasing their size, of course), filling them with a + prominent value and checking them on freeing the element. + Set it to 2 to also check every element in every pool each time memp_malloc() + or memp_free() is called (slower but more helpful). + + 2007-05-10 Simon Goldschmidt + * opt.h, memp.h, memp.c, pbuf.c (see task #6831): use a new memp pool for + PBUF_POOL pbufs instead of the old pool implementation in pbuf.c to reduce + code size. + + 2007-05-11 Frédéric Bernon + * sockets.c, api_lib.c, api_msg.h, api_msg.c, netifapi.h, netifapi.c, tcpip.c: + Include a function pointer instead of a table index in the message to reduce + footprint. Disable some part of lwip_send and lwip_sendto if some options are + not set (LWIP_TCP, LWIP_UDP, LWIP_RAW). + + 2007-05-10 Simon Goldschmidt + * *.h (except netif/ppp/*.h): Included patch #5448: include '#ifdef __cplusplus + \ extern "C" {' in all header files. Now you can write your application using + the lwIP stack in C++ and simply #include the core files. Note I have left + out the netif/ppp/*h header files for now, since I don't know which files are + included by applications and which are for internal use only. + + 2007-05-09 Simon Goldschmidt + * opt.h, *.c/*.h: Included patch #5920: Create define to override C-library + memcpy. 2 Defines are created: MEMCPY() for normal memcpy, SMEMCPY() for + situations where some compilers might inline the copy and save a function + call. Also replaced all calls to memcpy() with calls to (S)MEMCPY(). + + 2007-05-08 Simon Goldschmidt + * mem.h: If MEM_LIBC_MALLOC==1, allow the defines (e.g. mem_malloc() -> malloc()) + to be overriden in case the C-library malloc implementation is not protected + against concurrent access. + + 2007-05-04 Simon Goldschmidt (Atte Kojo) + * etharp.c: Introduced fast one-entry-cache to speed up ARP lookup when sending + multiple packets to the same host. + + 2007-05-04 Frédéric Bernon, Jonathan Larmour + * sockets.c, api.h, api_lib.c, api_msg.h, api_msg.c: Fix bug #19162 "lwip_sento: a possible + to corrupt remote addr/port connection state". Reduce problems "not enought memory" with + netbuf (if we receive lot of datagrams). Improve lwip_sendto (only one exchange between + sockets api and api_msg which run in tcpip_thread context). Add netconn_sento function. + Warning, if you directly access to "fromaddr" & "fromport" field from netbuf struct, + these fields are now renamed "addr" & "port". + + 2007-04-11 Jonathan Larmour + * sys.h, api_lib.c: Provide new sys_mbox_tryfetch function. Require ports to provide new + sys_arch_mbox_tryfetch function to get a message if one is there, otherwise return + with SYS_MBOX_EMPTY. sys_arch_mbox_tryfetch can be implemented as a function-like macro + by the port in sys_arch.h if desired. + + 2007-04-06 Frédéric Bernon, Simon Goldschmidt + * opt.h, tcpip.h, tcpip.c, netifapi.h, netifapi.c: New configuration option LWIP_NETIF_API + allow to use thread-safe functions to add/remove netif in list, and to start/stop dhcp + clients, using new functions from netifapi.h. Disable as default (no port change to do). + + 2007-04-05 Frédéric Bernon + * sockets.c: remplace ENOBUFS errors on alloc_socket by ENFILE to be more BSD compliant. + + 2007-04-04 Simon Goldschmidt + * arch.h, api_msg.c, dhcp.c, msg_in.c, sockets.c: Introduced #define LWIP_UNUSED_ARG(x) + use this for and architecture-independent form to tell the compiler you intentionally + are not using this variable. Can be overriden in cc.h. + + 2007-03-28 Frédéric Bernon + * opt.h, netif.h, dhcp.h, dhcp.c: New configuration option LWIP_NETIF_HOSTNAME allow to + define a hostname in netif struct (this is just a pointer, so, you can use a hardcoded + string, point on one of your's ethernetif field, or alloc a string you will free yourself). + It will be used by DHCP to register a client hostname, but can also be use when you call + snmp_set_sysname. + + 2007-03-28 Frédéric Bernon + * netif.h, netif.c: A new NETIF_FLAG_ETHARP flag is defined in netif.h, to allow to + initialize a network interface's flag with. It tell this interface is an ethernet + device, and we can use ARP with it to do a "gratuitous ARP" (RFC 3220 "IP Mobility + Support for IPv4" section 4.6) when interface is "up" with netif_set_up(). + + 2007-03-26 Frédéric Bernon, Jonathan Larmour + * opt.h, tcpip.c: New configuration option LWIP_ARP allow to disable ARP init at build + time if you only use PPP or SLIP. The default is enable. Note we don't have to call + etharp_init in your port's initilization sequence if you use tcpip.c, because this call + is done in tcpip_init function. + + 2007-03-22 Frédéric Bernon + * stats.h, stats.c, msg_in.c: Stats counters can be change to u32_t if necessary with the + new option LWIP_STATS_LARGE. If you need this option, define LWIP_STATS_LARGE to 1 in + your lwipopts.h. More, unused counters are not defined in the stats structs, and not + display by stats_display(). Note that some options (SYS_STATS and RAW_STATS) are defined + but never used. Fix msg_in.c with the correct #if test for a stat display. + + 2007-03-21 Kieran Mansley + * netif.c, netif.h: Apply patch#4197 with some changes (originator: rireland@hmgsl.com). + Provides callback on netif up/down state change. + + 2007-03-11 Frédéric Bernon, Mace Gael, Steve Reynolds + * sockets.h, sockets.c, api.h, api_lib.c, api_msg.h, api_msg.c, igmp.h, igmp.c, + ip.c, netif.h, tcpip.c, opt.h: + New configuration option LWIP_IGMP to enable IGMP processing. Based on only one + filter per all network interfaces. Declare a new function in netif to enable to + control the MAC filter (to reduce lwIP traffic processing). + + 2007-03-11 Frédéric Bernon + * tcp.h, tcp.c, sockets.c, tcp_out.c, tcp_in.c, opt.h: Keepalive values can + be configured at run time with LWIP_TCP_KEEPALIVE, but don't change this + unless you know what you're doing (default are RFC1122 compliant). Note + that TCP_KEEPIDLE and TCP_KEEPINTVL have to be set in seconds. + + 2007-03-08 Frédéric Bernon + * tcp.h: Keepalive values can be configured at compile time, but don't change + this unless you know what you're doing (default are RFC1122 compliant). + + 2007-03-08 Frédéric Bernon + * sockets.c, api.h, api_lib.c, tcpip.c, sys.h, sys.c, err.c, opt.h: + Implement LWIP_SO_RCVTIMEO configuration option to enable/disable SO_RCVTIMEO + on UDP sockets/netconn. + + 2007-03-08 Simon Goldschmidt + * snmp_msg.h, msg_in.c: SNMP UDP ports can be configured at compile time. + + 2007-03-06 Frédéric Bernon + * api.h, api_lib.c, sockets.h, sockets.c, tcpip.c, sys.h, sys.c, err.h: + Implement SO_RCVTIMEO on UDP sockets/netconn. + + 2007-02-28 Kieran Mansley (based on patch from Simon Goldschmidt) + * api_lib.c, tcpip.c, memp.c, memp.h: make API msg structs allocated + on the stack and remove the API msg type from memp + + 2007-02-26 Jonathan Larmour (based on patch from Simon Goldschmidt) + * sockets.h, sockets.c: Move socket initialization to new + lwip_socket_init() function. + NOTE: this changes the API with ports. Ports will have to be + updated to call lwip_socket_init() now. + + 2007-02-26 Jonathan Larmour (based on patch from Simon Goldschmidt) + * api_lib.c: Use memcpy in netbuf_copy_partial. + + + ++ Bug fixes: + + 2008-03-17 Frédéric Bernon, Ed Kerekes + * igmp.h, igmp.c: Fix bug #22613 "IGMP iphdr problem" (could have + some problems to fill the IP header on some targets, use now the + ip.h macros to do it). + + 2008-03-13 Frédéric Bernon + * sockets.c: Fix bug #22435 "lwip_recvfrom with TCP break;". Using + (lwip_)recvfrom with valid "from" and "fromlen" parameters, on a + TCP connection caused a crash. Note that using (lwip_)recvfrom + like this is a bit slow and that using (lwip)getpeername is the + good lwip way to do it (so, using recv is faster on tcp sockets). + + 2008-03-12 Frédéric Bernon, Jonathan Larmour + * api_msg.c, contrib/apps/ping.c: Fix bug #22530 "api_msg.c's + recv_raw() does not consume data", and the ping sample (with + LWIP_SOCKET=1, the code did the wrong supposition that lwip_recvfrom + returned the IP payload, without the IP header). + + 2008-03-04 Jonathan Larmour + * mem.c, stats.c, mem.h: apply patch #6414 to avoid compiler errors + and/or warnings on some systems where mem_size_t and size_t differ. + * pbuf.c, ppp.c: Fix warnings on some systems with mem_malloc. + + 2008-03-04 Kieran Mansley (contributions by others) + * Numerous small compiler error/warning fixes from contributions to + mailing list after 1.3.0 release candidate made. + + 2008-01-25 Cui hengbin (integrated by Frédéric Bernon) + * dns.c: Fix bug #22108 "DNS problem" caused by unaligned structures. + + 2008-01-15 Kieran Mansley + * tcp_out.c: BUG20511. Modify persist timer to start when we are + prevented from sending by a small send window, not just a zero + send window. + + 2008-01-09 Jonathan Larmour + * opt.h, ip.c: Rename IP_OPTIONS define to IP_OPTIONS_ALLOWED to avoid + conflict with Linux system headers. + + 2008-01-06 Jonathan Larmour + * dhcp.c: fix bug #19927: "DHCP NACK problem" by clearing any existing set IP + address entirely on receiving a DHCPNAK, and restarting discovery. + + 2007-12-21 Simon Goldschmidt + * sys.h, api_lib.c, api_msg.c, sockets.c: fix bug #21698: "netconn->recv_avail + is not protected" by using new macros for interlocked access to modify/test + netconn->recv_avail. + + 2007-12-20 Kieran Mansley (based on patch from Oleg Tyshev) + * tcp_in.c: fix bug# 21535 (nrtx not reset correctly in SYN_SENT state) + + 2007-12-20 Kieran Mansley (based on patch from Per-Henrik Lundbolm) + * tcp.c, tcp_in.c, tcp_out.c, tcp.h: fix bug #20199 (better handling + of silly window avoidance and prevent lwIP from shrinking the window) + + 2007-12-04 Simon Goldschmidt + * tcp.c, tcp_in.c: fix bug #21699 (segment leak in ooseq processing when last + data packet was lost): add assert that all segment lists are empty in + tcp_pcb_remove before setting pcb to CLOSED state; don't directly set CLOSED + state from LAST_ACK in tcp_process + + 2007-12-02 Simon Goldschmidt + * sockets.h: fix bug #21654: exclude definition of struct timeval from #ifndef FD_SET + If including for system-struct timeval, LWIP_TIMEVAL_PRIVATE now + has to be set to 0 in lwipopts.h + + 2007-12-02 Simon Goldschmidt + * api_msg.c, api_lib.c: fix bug #21656 (recvmbox problem in netconn API): always + allocate a recvmbox in netconn_new_with_proto_and_callback. For a tcp-listen + netconn, this recvmbox is later freed and a new mbox is allocated for acceptmbox. + This is a fix for thread-safety and allocates all items needed for a netconn + when the netconn is created. + + 2007-11-30 Simon Goldschmidt + * udp.c: first attempt to fix bug #21655 (DHCP doesn't work reliably with multiple + netifs): if LWIP_DHCP is enabled, UDP packets to DHCP_CLIENT_PORT are passed + to netif->dhcp->pcb only (if that exists) and not to any other pcb for the same + port (only solution to let UDP pcbs 'bind' to a netif instead of an IP address) + + 2007-11-27 Simon Goldschmidt + * ip.c: fixed bug #21643 (udp_send/raw_send don't fail if netif is down) by + letting ip_route only use netifs that are up. + + 2007-11-27 Simon Goldschmidt + * err.h, api_lib.c, api_msg.c, sockets.c: Changed error handling: ERR_MEM, ERR_BUF + and ERR_RTE are seen as non-fatal, all other errors are fatal. netconns and + sockets block most operations once they have seen a fatal error. + + 2007-11-27 Simon Goldschmidt + * udp.h, udp.c, dhcp.c: Implemented new function udp_sendto_if which takes the + netif to send as an argument (to be able to send on netifs that are down). + + 2007-11-26 Simon Goldschmidt + * tcp_in.c: Fixed bug #21582: pcb->acked accounting can be wrong when ACKs + arrive out-of-order + + 2007-11-21 Simon Goldschmidt + * tcp.h, tcp_out.c, api_msg.c: Fixed bug #20287: tcp_output_nagle sends too early + Fixed the nagle algorithm; nagle now also works for all raw API applications + and has to be explicitly disabled with 'tcp_pcb->flags |= TF_NODELAY' + + 2007-11-12 Frédéric Bernon + * sockets.c, api.h, api_lib.c, api_msg.h, api_msg.c: Fixed bug #20900. Now, most + of the netconn_peer and netconn_addr processing is done inside tcpip_thread + context in do_getaddr. + + 2007-11-10 Simon Goldschmidt + * etharp.c: Fixed bug: assert fired when MEMP_ARP_QUEUE was empty (which can + happen any time). Now the packet simply isn't enqueued when out of memory. + + 2007-11-01 Simon Goldschmidt + * tcp.c, tcp_in.c: Fixed bug #21494: The send mss (pcb->mss) is set to 536 (or + TCP_MSS if that is smaller) as long as no MSS option is received from the + remote host. + + 2007-11-01 Simon Goldschmidt + * tcp.h, tcp.c, tcp_in.c: Fixed bug #21491: The MSS option sent (with SYN) + is now based on TCP_MSS instead of pcb->mss (on passive open now effectively + sending our configured TCP_MSS instead of the one received). + + 2007-11-01 Simon Goldschmidt + * tcp_in.c: Fixed bug #21181: On active open, the initial congestion window was + calculated based on the configured TCP_MSS, not on the MSS option received + with SYN+ACK. + + 2007-10-09 Simon Goldschmidt + * udp.c, inet.c, inet.h: Fixed UDPLite: send: Checksum was always generated too + short and also was generated wrong if checksum coverage != tot_len; + receive: checksum was calculated wrong if checksum coverage != tot_len + + 2007-10-08 Simon Goldschmidt + * mem.c: lfree was not updated in mem_realloc! + + 2007-10-07 Frédéric Bernon + * sockets.c, api.h, api_lib.c: First step to fix "bug #20900 : Potential + crash error problem with netconn_peer & netconn_addr". VERY IMPORTANT: + this change cause an API breakage for netconn_addr, since a parameter + type change. Any compiler should cause an error without any changes in + yours netconn_peer calls (so, it can't be a "silent change"). It also + reduce a little bit the footprint for socket layer (lwip_getpeername & + lwip_getsockname use now a common lwip_getaddrname function since + netconn_peer & netconn_addr have the same parameters). + + 2007-09-20 Simon Goldschmidt + * tcp.c: Fixed bug #21080 (tcp_bind without check pcbs in TIME_WAIT state) + by checking tcp_tw_pcbs also + + 2007-09-19 Simon Goldschmidt + * icmp.c: Fixed bug #21107 (didn't reset IP TTL in ICMP echo replies) + + 2007-09-15 Mike Kleshov + * mem.c: Fixed bug #21077 (inaccuracy in calculation of lwip_stat.mem.used) + + 2007-09-06 Frédéric Bernon + * several-files: replace some #include "arch/cc.h" by "lwip/arch.h", or simply remove + it as long as "lwip/opt.h" is included before (this one include "lwip/debug.h" which + already include "lwip/arch.h"). Like that, default defines are provided by "lwip/arch.h" + if they are not defined in cc.h, in the same spirit than "lwip/opt.h" for lwipopts.h. + + 2007-08-30 Frédéric Bernon + * igmp.h, igmp.c: Some changes to remove some redundant code, add some traces, + and fix some coding style. + + 2007-08-28 Frédéric Bernon + * tcpip.c: Fix TCPIP_MSG_INPKT processing: now, tcpip_input can be used for any + kind of packets. These packets are considered like Ethernet packets (payload + pointing to ethhdr) if the netif got the NETIF_FLAG_ETHARP flag. Else, packets + are considered like IP packets (payload pointing to iphdr). + + 2007-08-27 Frédéric Bernon + * api.h, api_lib.c, api_msg.c: First fix for "bug #20900 : Potential crash error + problem with netconn_peer & netconn_addr". Introduce NETCONN_LISTEN netconn_state + and remove obsolete ones (NETCONN_RECV & NETCONN_ACCEPT). + + 2007-08-24 Kieran Mansley + * inet.c Modify (acc >> 16) test to ((acc >> 16) != 0) to help buggy + compiler (Paradigm C++) + + 2007-08-09 Frédéric Bernon, Bill Florac + * stats.h, stats.c, igmp.h, igmp.c, opt.h: Fix for bug #20503 : IGMP Improvement. + Introduce IGMP_STATS to centralize statistics management. + + 2007-08-09 Frédéric Bernon, Bill Florac + * udp.c: Fix for bug #20503 : IGMP Improvement. Enable to receive a multicast + packet on a udp pcb binded on an netif's IP address, and not on "any". + + 2007-08-09 Frédéric Bernon, Bill Florac + * igmp.h, igmp.c, ip.c: Fix minor changes from bug #20503 : IGMP Improvement. + This is mainly on using lookup/lookfor, and some coding styles... + + 2007-07-26 Frédéric Bernon (and "thedoctor") + * igmp.c: Fix bug #20595 to accept IGMPv3 "Query" messages. + + 2007-07-25 Simon Goldschmidt + * api_msg.c, tcp.c: Another fix for bug #20021: by not returning an error if + tcp_output fails in tcp_close, the code in do_close_internal gets simpler + (tcp_output is called again later from tcp timers). + + 2007-07-25 Simon Goldschmidt + * ip_frag.c: Fixed bug #20429: use the new pbuf_copy_partial instead of the old + copy_from_pbuf, which illegally modified the given pbuf. + + 2007-07-25 Simon Goldschmidt + * tcp_out.c: tcp_enqueue: pcb->snd_queuelen didn't work for chaine PBUF_RAMs: + changed snd_queuelen++ to snd_queuelen += pbuf_clen(p). + + 2007-07-24 Simon Goldschmidt + * api_msg.c, tcp.c: Fix bug #20480: Check the pcb passed to tcp_listen() for the + correct state (must be CLOSED). + + 2007-07-13 Thomas Taranowski (commited by Jared Grubb) + * memp.c: Fix bug #20478: memp_malloc returned NULL+MEMP_SIZE on failed + allocation. It now returns NULL. + + 2007-07-13 Frédéric Bernon + * api_msg.c: Fix bug #20318: api_msg "recv" callbacks don't call pbuf_free in + all error cases. + + 2007-07-13 Frédéric Bernon + * api_msg.c: Fix bug #20315: possible memory leak problem if tcp_listen failed, + because current code doesn't follow rawapi.txt documentation. + + 2007-07-13 Kieran Mansley + * src/core/tcp_in.c Apply patch#5741 from Oleg Tyshev to fix bug in + out of sequence processing of received packets + + 2007-07-03 Simon Goldschmidt + * nearly-all-files: Added assertions where PBUF_RAM pbufs are used and an + assumption is made that this pbuf is in one piece (i.e. not chained). These + assumptions clash with the possibility of converting to fully pool-based + pbuf implementations, where PBUF_RAM pbufs might be chained. + + 2007-07-03 Simon Goldschmidt + * api.h, api_lib.c, api_msg.c: Final fix for bug #20021 and some other problems + when closing tcp netconns: removed conn->sem, less context switches when + closing, both netconn_close and netconn_delete should safely close tcp + connections. + + 2007-07-02 Simon Goldschmidt + * ipv4/ip.h, ipv6/ip.h, opt.h, netif.h, etharp.h, ipv4/ip.c, netif.c, raw.c, + tcp_out.c, udp.c, etharp.c: Added option LWIP_NETIF_HWADDRHINT (default=off) + to cache ARP table indices with each pcb instead of single-entry cache for + the complete stack. + + 2007-07-02 Simon Goldschmidt + * tcp.h, tcp.c, tcp_in.c, tcp_out.c: Added some ASSERTS and casts to prevent + warnings when assigning to smaller types. + + 2007-06-28 Simon Goldschmidt + * tcp_out.c: Added check to prevent tcp_pcb->snd_queuelen from overflowing. + + 2007-06-28 Simon Goldschmidt + * tcp.h: Fixed bug #20287: Fixed nagle algorithm (sending was done too early if + a segment contained chained pbufs) + + 2007-06-28 Frédéric Bernon + * autoip.c: replace most of rand() calls by a macro LWIP_AUTOIP_RAND which compute + a "pseudo-random" value based on netif's MAC and some autoip fields. It's always + possible to define this macro in your own lwipopts.h to always use C library's + rand(). Note that autoip_create_rand_addr doesn't use this macro. + + 2007-06-28 Frédéric Bernon + * netifapi.h, netifapi.c, tcpip.h, tcpip.c: Update code to handle the option + LWIP_TCPIP_CORE_LOCKING, and do some changes to be coherent with last modifications + in api_lib/api_msg (use pointers and not type with table, etc...) + + 2007-06-26 Simon Goldschmidt + * udp.h: Fixed bug #20259: struct udp_hdr was lacking the packin defines. + + 2007-06-25 Simon Goldschmidt + * udp.c: Fixed bug #20253: icmp_dest_unreach was called with a wrong p->payload + for udp packets with no matching pcb. + + 2007-06-25 Simon Goldschmidt + * udp.c: Fixed bug #20220: UDP PCB search in udp_input(): a non-local match + could get udp input packets if the remote side matched. + + 2007-06-13 Simon Goldschmidt + * netif.c: Fixed bug #20180 (TCP pcbs listening on IP_ADDR_ANY could get + changed in netif_set_ipaddr if previous netif->ip_addr.addr was 0. + + 2007-06-13 Simon Goldschmidt + * api_msg.c: pcb_new sets conn->err if protocol is not implemented + -> netconn_new_..() does not allocate a new connection for unsupported + protocols. + + 2007-06-13 Frédéric Bernon, Simon Goldschmidt + * api_lib.c: change return expression in netconn_addr and netconn_peer, because + conn->err was reset to ERR_OK without any reasons (and error was lost)... + + 2007-06-13 Frédéric Bernon, Matthias Weisser + * opt.h, mem.h, mem.c, memp.c, pbuf.c, ip_frag.c, vj.c: Fix bug #20162. Rename + MEM_ALIGN in LWIP_MEM_ALIGN and MEM_ALIGN_SIZE in LWIP_MEM_ALIGN_SIZE to avoid + some macro names collision with some OS macros. + + 2007-06-11 Simon Goldschmidt + * udp.c: UDP Lite: corrected the use of chksum_len (based on RFC3828: if it's 0, + create checksum over the complete packet. On RX, if it's < 8 (and not 0), + discard the packet. Also removed the duplicate 'udphdr->chksum = 0' for both + UDP & UDP Lite. + + 2007-06-11 Srinivas Gollakota & Oleg Tyshev + * tcp_out.c: Fix for bug #20075 : "A problem with keep-alive timer and TCP flags" + where TCP flags wasn't initialized in tcp_keepalive. + + 2007-06-03 Simon Goldschmidt + * udp.c: udp_input(): Input pbuf was not freed if pcb had no recv function + registered, p->payload was modified without modifying p->len if sending + icmp_dest_unreach() (had no negative effect but was definitively wrong). + + 2007-06-03 Simon Goldschmidt + * icmp.c: Corrected bug #19937: For responding to an icmp echo request, icmp + re-used the input pbuf even if that didn't have enough space to include the + link headers. Now the space is tested and a new pbuf is allocated for the + echo response packet if the echo request pbuf isn't big enough. + + 2007-06-01 Simon Goldschmidt + * sockets.c: Checked in patch #5914: Moved sockopt processing into tcpip_thread. + + 2007-05-23 Frédéric Bernon + * api_lib.c, sockets.c: Fixed bug #5958 for netconn_listen (acceptmbox only + allocated by do_listen if success) and netconn_accept errors handling. In + most of api_lib functions, we replace some errors checkings like "if (conn==NULL)" + by ASSERT, except for netconn_delete. + + 2007-05-23 Frédéric Bernon + * api_lib.c: Fixed bug #5957 "Safe-thread problem inside netconn_recv" to return + an error code if it's impossible to fetch a pbuf on a TCP connection (and not + directly close the recvmbox). + + 2007-05-22 Simon Goldschmidt + * tcp.c: Fixed bug #1895 (tcp_bind not correct) by introducing a list of + bound but unconnected (and non-listening) tcp_pcbs. + + 2007-05-22 Frédéric Bernon + * sys.h, sys.c, api_lib.c, tcpip.c: remove sys_mbox_fetch_timeout() (was only + used for LWIP_SO_RCVTIMEO option) and use sys_arch_mbox_fetch() instead of + sys_mbox_fetch() in api files. Now, users SHOULD NOT use internal lwIP features + like "sys_timeout" in their application threads. + + 2007-05-22 Frédéric Bernon + * api.h, api_lib.c, api_msg.h, api_msg.c: change the struct api_msg_msg to see + which parameters are used by which do_xxx function, and to avoid "misusing" + parameters (patch #5938). + + 2007-05-22 Simon Goldschmidt + * api_lib.c, api_msg.c, raw.c, api.h, api_msg.h, raw.h: Included patch #5938: + changed raw_pcb.protocol from u16_t to u8_t since for IPv4 and IPv6, proto + is only 8 bits wide. This affects the api, as there, the protocol was + u16_t, too. + + 2007-05-18 Simon Goldschmidt + * memp.c: addition to patch #5913: smaller pointer was returned but + memp_memory was the same size -> did not save memory. + + 2007-05-16 Simon Goldschmidt + * loopif.c, slipif.c: Fix bug #19729: free pbuf if netif->input() returns + != ERR_OK. + + 2007-05-16 Simon Goldschmidt + * api_msg.c, udp.c: If a udp_pcb has a local_ip set, check if it is the same + as the one of the netif used for sending to prevent sending from old + addresses after a netif address gets changed (partly fixes bug #3168). + + 2007-05-16 Frédéric Bernon + * tcpip.c, igmp.h, igmp.c: Fixed bug "#19800 : IGMP: igmp_tick() will not work + with NO_SYS=1". Note that igmp_init is always in tcpip_thread (and not in + tcpip_init) because we have to be sure that network interfaces are already + added (mac filter is updated only in igmp_init for the moment). + + 2007-05-16 Simon Goldschmidt + * mem.c, memp.c: Removed semaphores from memp, changed sys_sem_wait calls + into sys_arch_sem_wait calls to prevent timers from running while waiting + for the heap. This fixes bug #19167. + + 2007-05-13 Simon Goldschmidt + * tcp.h, sockets.h, sockets.c: Fixed bug from patch #5865 by moving the defines + for socket options (lwip_set/-getsockopt) used with level IPPROTO_TCP from + tcp.h to sockets.h. + + 2007-05-07 Simon Goldschmidt + * mem.c: Another attempt to fix bug #17922. + + 2007-05-04 Simon Goldschmidt + * pbuf.c, pbuf.h, etharp.c: Further update to ARP queueing: Changed pbuf_copy() + implementation so that it can be reused (don't allocate the target + pbuf inside pbuf_copy()). + + 2007-05-04 Simon Goldschmidt + * memp.c: checked in patch #5913: in memp_malloc() we can return memp as mem + to save a little RAM (next pointer of memp is not used while not in pool). + + 2007-05-03 "maq" + * sockets.c: Fix ioctl FIONREAD when some data remains from last recv. + (patch #3574). + + 2007-04-23 Simon Goldschmidt + * loopif.c, loopif.h, opt.h, src/netif/FILES: fix bug #2595: "loopif results + in NULL reference for incoming TCP packets". Loopif has to be configured + (using LWIP_LOOPIF_MULTITHREADING) to directly call netif->input() + (multithreading environments, e.g. netif->input() = tcpip_input()) or + putting packets on a list that is fed to the stack by calling loopif_poll() + (single-thread / NO_SYS / polling environment where e.g. + netif->input() = ip_input). + + 2007-04-17 Jonathan Larmour + * pbuf.c: Use s32_t in pbuf_realloc(), as an s16_t can't reliably hold + the difference between two u16_t's. + * sockets.h: FD_SETSIZE needs to match number of sockets, which is + MEMP_NUM_NETCONN in sockets.c right now. + + 2007-04-12 Jonathan Larmour + * icmp.c: Reset IP header TTL in ICMP ECHO responses (bug #19580). + + 2007-04-12 Kieran Mansley + * tcp.c, tcp_in.c, tcp_out.c, tcp.h: Modify way the retransmission + timer is reset to fix bug#19434, with help from Oleg Tyshev. + + 2007-04-11 Simon Goldschmidt + * etharp.c, pbuf.c, pbuf.h: 3rd fix for bug #11400 (arp-queuing): More pbufs than + previously thought need to be copied (everything but PBUF_ROM!). Cleaned up + pbuf.c: removed functions no needed any more (by etharp). + + 2007-04-11 Kieran Mansley + * inet.c, ip_addr.h, sockets.h, sys.h, tcp.h: Apply patch #5745: Fix + "Constant is long" warnings with 16bit compilers. Contributed by + avatar@mmlab.cse.yzu.edu.tw + + 2007-04-05 Frédéric Bernon, Jonathan Larmour + * api_msg.c: Fix bug #16830: "err_tcp() posts to connection mailbox when no pend on + the mailbox is active". Now, the post is only done during a connect, and do_send, + do_write and do_join_leave_group don't do anything if a previous error was signaled. + + 2007-04-03 Frédéric Bernon + * ip.c: Don't set the IP_DF ("Don't fragment") flag in the IP header in IP output + packets. See patch #5834. + + 2007-03-30 Frédéric Bernon + * api_msg.c: add a "pcb_new" helper function to avoid redundant code, and to add + missing pcb allocations checking (in do_bind, and for each raw_new). Fix style. + + 2007-03-30 Frédéric Bernon + * most of files: prefix all debug.h define with "LWIP_" to avoid any conflict with + others environment defines (these were too "generic"). + + 2007-03-28 Frédéric Bernon + * api.h, api_lib.c, sockets.c: netbuf_ref doesn't check its internal pbuf_alloc call + result and can cause a crash. lwip_send now check netbuf_ref result. + + 2007-03-28 Simon Goldschmidt + * sockets.c Remove "#include " from sockets.c to avoid multiple + definition of macros (in errno.h and lwip/arch.h) if LWIP_PROVIDE_ERRNO is + defined. This is the way it should have been already (looking at + doc/sys_arch.txt) + + 2007-03-28 Kieran Mansley + * opt.h Change default PBUF_POOL_BUFSIZE (again) to accomodate default MSS + + IP and TCP headers *and* physical link headers + + 2007-03-26 Frédéric Bernon (based on patch from Dmitry Potapov) + * api_lib.c: patch for netconn_write(), fixes a possible race condition which cause + to send some garbage. It is not a definitive solution, but the patch does solve + the problem for most cases. + + 2007-03-22 Frédéric Bernon + * api_msg.h, api_msg.c: Remove obsolete API_MSG_ACCEPT and do_accept (never used). + + 2007-03-22 Frédéric Bernon + * api_lib.c: somes resources couldn't be freed if there was errors during + netconn_new_with_proto_and_callback. + + 2007-03-22 Frédéric Bernon + * ethernetif.c: update netif->input calls to check return value. In older ports, + it's a good idea to upgrade them, even if before, there could be another problem + (access to an uninitialized mailbox). + + 2007-03-21 Simon Goldschmidt + * sockets.c: fixed bug #5067 (essentialy a signed/unsigned warning fixed + by casting to unsigned). + + 2007-03-21 Frédéric Bernon + * api_lib.c, api_msg.c, tcpip.c: integrate sys_mbox_fetch(conn->mbox, NULL) calls from + api_lib.c to tcpip.c's tcpip_apimsg(). Now, use a local variable and not a + dynamic one from memp to send tcpip_msg to tcpip_thread in a synchrone call. + Free tcpip_msg from tcpip_apimsg is not done in tcpip_thread. This give a + faster and more reliable communication between api_lib and tcpip. + + 2007-03-21 Frédéric Bernon + * opt.h: Add LWIP_NETIF_CALLBACK (to avoid compiler warning) and set it to 0. + + 2007-03-21 Frédéric Bernon + * api_msg.c, igmp.c, igmp.h: Fix C++ style comments + + 2007-03-21 Kieran Mansley + * opt.h Change default PBUF_POOL_BUFSIZE to accomodate default MSS + + IP and TCP headers + + 2007-03-21 Kieran Mansley + * Fix all uses of pbuf_header to check the return value. In some + cases just assert if it fails as I'm not sure how to fix them, but + this is no worse than before when they would carry on regardless + of the failure. + + 2007-03-21 Kieran Mansley + * sockets.c, igmp.c, igmp.h, memp.h: Fix C++ style comments and + comment out missing header include in icmp.c + + 2007-03-20 Frédéric Bernon + * memp.h, stats.c: Fix stats_display function where memp_names table wasn't + synchronized with memp.h. + + 2007-03-20 Frédéric Bernon + * tcpip.c: Initialize tcpip's mbox, and verify if initialized in tcpip_input, + tcpip_ethinput, tcpip_callback, tcpip_apimsg, to fix a init problem with + network interfaces. Also fix a compiler warning. + + 2007-03-20 Kieran Mansley + * udp.c: Only try and use pbuf_header() to make space for headers if + not a ROM or REF pbuf. + + 2007-03-19 Frédéric Bernon + * api_msg.h, api_msg.c, tcpip.h, tcpip.c: Add return types to tcpip_apimsg() + and api_msg_post(). + + 2007-03-19 Frédéric Bernon + * Remove unimplemented "memp_realloc" function from memp.h. + + 2007-03-11 Simon Goldschmidt + * pbuf.c: checked in patch #5796: pbuf_alloc: len field claculation caused + memory corruption. + + 2007-03-11 Simon Goldschmidt (based on patch from Dmitry Potapov) + * api_lib.c, sockets.c, api.h, api_msg.h, sockets.h: Fixed bug #19251 + (missing `const' qualifier in socket functions), to get more compatible to + standard POSIX sockets. + + 2007-03-11 Frédéric Bernon (based on patch from Dmitry Potapov) + * sockets.c: Add asserts inside bind, connect and sendto to check input + parameters. Remove excessive set_errno() calls after get_socket(), because + errno is set inside of get_socket(). Move last sock_set_errno() inside + lwip_close. + + 2007-03-09 Simon Goldschmidt + * memp.c: Fixed bug #11400: New etharp queueing introduced bug: memp_memory + was allocated too small. + + 2007-03-06 Simon Goldschmidt + * tcpip.c: Initialize dhcp timers in tcpip_thread (if LWIP_DHCP) to protect + the stack from concurrent access. + + 2007-03-06 Frédéric Bernon, Dmitry Potapov + * tcpip.c, ip_frag.c, ethernetif.c: Fix some build problems, and a redundancy + call to "lwip_stats.link.recv++;" in low_level_input() & ethernetif_input(). + + 2007-03-06 Simon Goldschmidt + * ip_frag.c, ip_frag.h: Reduce code size: don't include code in those files + if IP_FRAG == 0 and IP_REASSEMBLY == 0 + + 2007-03-06 Frédéric Bernon, Simon Goldschmidt + * opt.h, ip_frag.h, tcpip.h, tcpip.c, ethernetif.c: add new configuration + option named ETHARP_TCPIP_ETHINPUT, which enable the new tcpip_ethinput. + Allow to do ARP processing for incoming packets inside tcpip_thread + (protecting ARP layer against concurrent access). You can also disable + old code using tcp_input with new define ETHARP_TCPIP_INPUT set to 0. + Older ports have to use tcpip_ethinput. + + 2007-03-06 Simon Goldschmidt (based on patch from Dmitry Potapov) + * err.h, err.c: fixed compiler warning "initialization dircards qualifiers + from pointer target type" + + 2007-03-05 Frédéric Bernon + * opt.h, sockets.h: add new configuration options (LWIP_POSIX_SOCKETS_IO_NAMES, + ETHARP_TRUST_IP_MAC, review SO_REUSE) + + 2007-03-04 Frédéric Bernon + * api_msg.c: Remove some compiler warnings : parameter "pcb" was never + referenced. + + 2007-03-04 Frédéric Bernon + * api_lib.c: Fix "[patch #5764] api_lib.c cleanup: after patch #5687" (from + Dmitry Potapov). + The api_msg struct stay on the stack (not moved to netconn struct). + + 2007-03-04 Simon Goldschmidt (based on patch from Dmitry Potapov) + * pbuf.c: Fix BUG#19168 - pbuf_free can cause deadlock (if + SYS_LIGHTWEIGHT_PROT=1 & freeing PBUF_RAM when mem_sem is not available) + Also fixed cast warning in pbuf_alloc() + + 2007-03-04 Simon Goldschmidt + * etharp.c, etharp.h, memp.c, memp.h, opt.h: Fix BUG#11400 - don't corrupt + existing pbuf chain when enqueuing multiple pbufs to a pending ARP request + + 2007-03-03 Frédéric Bernon + * udp.c: remove obsolete line "static struct udp_pcb *pcb_cache = NULL;" + It is static, and never used in udp.c except udp_init(). + + 2007-03-02 Simon Goldschmidt + * tcpip.c: Moved call to ip_init(), udp_init() and tcp_init() from + tcpip_thread() to tcpip_init(). This way, raw API connections can be + initialized before tcpip_thread is running (e.g. before OS is started) + + 2007-03-02 Frédéric Bernon + * rawapi.txt: Fix documentation mismatch with etharp.h about etharp_tmr's call + interval. + + 2007-02-28 Kieran Mansley + * pbuf.c: Fix BUG#17645 - ensure pbuf payload pointer is not moved + outside the region of the pbuf by pbuf_header() + + 2007-02-28 Kieran Mansley + * sockets.c: Fix BUG#19161 - ensure milliseconds timeout is non-zero + when supplied timeout is also non-zero + +(STABLE-1.2.0) + + 2006-12-05 Leon Woestenberg + * CHANGELOG: Mention STABLE-1.2.0 release. + + ++ New features: + + 2006-12-01 Christiaan Simons + * mem.h, opt.h: Added MEM_LIBC_MALLOC option. + Note this is a workaround. Currently I have no other options left. + + 2006-10-26 Christiaan Simons (accepted patch by Jonathan Larmour) + * ipv4/ip_frag.c: rename MAX_MTU to IP_FRAG_MAX_MTU and move define + to include/lwip/opt.h. + * ipv4/lwip/ip_frag.h: Remove unused IP_REASS_INTERVAL. + Move IP_REASS_MAXAGE and IP_REASS_BUFSIZE to include/lwip/opt.h. + * opt.h: Add above new options. + + 2006-08-18 Christiaan Simons + * tcp_{in,out}.c: added SNMP counters. + * ipv4/ip.c: added SNMP counters. + * ipv4/ip_frag.c: added SNMP counters. + + 2006-08-08 Christiaan Simons + * etharp.{c,h}: added etharp_find_addr() to read + (stable) ethernet/IP address pair from ARP table + + 2006-07-14 Christiaan Simons + * mib_structs.c: added + * include/lwip/snmp_structs.h: added + * netif.{c,h}, netif/ethernetif.c: added SNMP statistics to netif struct + + 2006-07-06 Christiaan Simons + * snmp/asn1_{enc,dec}.c added + * snmp/mib2.c added + * snmp/msg_{in,out}.c added + * include/lwip/snmp_asn1.h added + * include/lwip/snmp_msg.h added + * doc/snmp_agent.txt added + + 2006-03-29 Christiaan Simons + * inet.c, inet.h: Added platform byteswap support. + Added LWIP_PLATFORM_BYTESWAP define (defaults to 0) and + optional LWIP_PLATFORM_HTONS(), LWIP_PLATFORM_HTONL() macros. + + ++ Bug fixes: + + 2006-11-30 Christiaan Simons + * dhcp.c: Fixed false triggers of request_timeout. + + 2006-11-28 Christiaan Simons + * netif.c: In netif_add() fixed missing clear of ip_addr, netmask, gw and flags. + + 2006-10-11 Christiaan Simons + * api_lib.c etharp.c, ip.c, memp.c, stats.c, sys.{c,h} tcp.h: + Partially accepted patch #5449 for ANSI C compatibility / build fixes. + * ipv4/lwip/ip.h ipv6/lwip/ip.h: Corrected UDP-Lite protocol + identifier from 170 to 136 (bug #17574). + + 2006-10-10 Christiaan Simons + * api_msg.c: Fixed Nagle algorithm as reported by Bob Grice. + + 2006-08-17 Christiaan Simons + * udp.c: Fixed bug #17200, added check for broadcast + destinations for PCBs bound to a unicast address. + + 2006-08-07 Christiaan Simons + * api_msg.c: Flushing TCP output in do_close() (bug #15926). + + 2006-06-27 Christiaan Simons + * api_msg.c: Applied patch for cold case (bug #11135). + In accept_function() ensure newconn->callback is always initialized. + + 2006-06-15 Christiaan Simons + * mem.h: added MEM_SIZE_F alias to fix an ancient cold case (bug #1748), + facilitate printing of mem_size_t and u16_t statistics. + + 2006-06-14 Christiaan Simons + * api_msg.c: Applied patch #5146 to handle allocation failures + in accept() by Kevin Lawson. + + 2006-05-26 Christiaan Simons + * api_lib.c: Removed conn->sem creation and destruction + from netconn_write() and added sys_sem_new to netconn_new_*. + +(STABLE-1_1_1) + + 2006-03-03 Christiaan Simons + * ipv4/ip_frag.c: Added bound-checking assertions on ip_reassbitmap + access and added pbuf_alloc() return value checks. + + 2006-01-01 Leon Woestenberg + * tcp_{in,out}.c, tcp_out.c: Removed 'even sndbuf' fix in TCP, which is + now handled by the checksum routine properly. + + 2006-02-27 Leon Woestenberg + * pbuf.c: Fix alignment; pbuf_init() would not work unless + pbuf_pool_memory[] was properly aligned. (Patch by Curt McDowell.) + + 2005-12-20 Leon Woestenberg + * tcp.c: Remove PCBs which stay in LAST_ACK state too long. Patch + submitted by Mitrani Hiroshi. + + 2005-12-15 Christiaan Simons + * inet.c: Disabled the added summing routine to preserve code space. + + 2005-12-14 Leon Woestenberg + * tcp_in.c: Duplicate FIN ACK race condition fix by Kelvin Lawson. + Added Curt McDowell's optimized checksumming routine for future + inclusion. Need to create test case for unaliged, aligned, odd, + even length combination of cases on various endianess machines. + + 2005-12-09 Christiaan Simons + * inet.c: Rewrote standard checksum routine in proper portable C. + + 2005-11-25 Christiaan Simons + * udp.c tcp.c: Removed SO_REUSE hack. Should reside in socket code only. + * *.c: introduced cc.h LWIP_DEBUG formatters matching the u16_t, s16_t, + u32_t, s32_t typedefs. This solves most debug word-length assumes. + + 2005-07-17 Leon Woestenberg + * inet.c: Fixed unaligned 16-bit access in the standard checksum + routine by Peter Jolasson. + * slipif.c: Fixed implementation assumption of single-pbuf datagrams. + + 2005-02-04 Leon Woestenberg + * tcp_out.c: Fixed uninitialized 'queue' referenced in memerr branch. + * tcp_{out|in}.c: Applied patch fixing unaligned access. + + 2005-01-04 Leon Woestenberg + * pbuf.c: Fixed missing semicolon after LWIP_DEBUG statement. + + 2005-01-03 Leon Woestenberg + * udp.c: UDP pcb->recv() was called even when it was NULL. + +(STABLE-1_1_0) + + 2004-12-28 Leon Woestenberg + * etharp.*: Disabled multiple packets on the ARP queue. + This clashes with TCP queueing. + + 2004-11-28 Leon Woestenberg + * etharp.*: Fixed race condition from ARP request to ARP timeout. + Halved the ARP period, doubled the period counts. + ETHARP_MAX_PENDING now should be at least 2. This prevents + the counter from reaching 0 right away (which would allow + too little time for ARP responses to be received). + + 2004-11-25 Leon Woestenberg + * dhcp.c: Decline messages were not multicast but unicast. + * etharp.c: ETHARP_CREATE is renamed to ETHARP_TRY_HARD. + Do not try hard to insert arbitrary packet's source address, + etharp_ip_input() now calls etharp_update() without ETHARP_TRY_HARD. + etharp_query() now always DOES call ETHARP_TRY_HARD so that users + querying an address will see it appear in the cache (DHCP could + suffer from this when a server invalidly gave an in-use address.) + * ipv4/ip_addr.h: Renamed ip_addr_maskcmp() to _netcmp() as we are + comparing network addresses (identifiers), not the network masks + themselves. + * ipv4/ip_addr.c: ip_addr_isbroadcast() now checks that the given + IP address actually belongs to the network of the given interface. + + 2004-11-24 Kieran Mansley + * tcp.c: Increment pcb->snd_buf when ACK is received in SYN_SENT state. + +(STABLE-1_1_0-RC1) + + 2004-10-16 Kieran Mansley + * tcp.c: Add code to tcp_recved() to send an ACK (window update) immediately, + even if one is already pending, if the rcv_wnd is above a threshold + (currently TCP_WND/2). This avoids waiting for a timer to expire to send a + delayed ACK in order to open the window if the stack is only receiving data. + + 2004-09-12 Kieran Mansley + * tcp*.*: Retransmit time-out handling improvement by Sam Jansen. + + 2004-08-20 Tony Mountifield + * etharp.c: Make sure the first pbuf queued on an ARP entry + is properly ref counted. + + 2004-07-27 Tony Mountifield + * debug.h: Added (int) cast in LWIP_DEBUGF() to avoid compiler + warnings about comparison. + * pbuf.c: Stopped compiler complaining of empty if statement + when LWIP_DEBUGF() empty. Closed an unclosed comment. + * tcp.c: Stopped compiler complaining of empty if statement + when LWIP_DEBUGF() empty. + * ip.h Corrected IPH_TOS() macro: returns a byte, so doesn't need htons(). + * inet.c: Added a couple of casts to quiet the compiler. + No need to test isascii(c) before isdigit(c) or isxdigit(c). + + 2004-07-22 Tony Mountifield + * inet.c: Made data types consistent in inet_ntoa(). + Added casts for return values of checksum routines, to pacify compiler. + * ip_frag.c, tcp_out.c, sockets.c, pbuf.c + Small corrections to some debugging statements, to pacify compiler. + + 2004-07-21 Tony Mountifield + * etharp.c: Removed spurious semicolon and added missing end-of-comment. + * ethernetif.c Updated low_level_output() to match prototype for + netif->linkoutput and changed low_level_input() similarly for consistency. + * api_msg.c: Changed recv_raw() from int to u8_t, to match prototype + of raw_recv() in raw.h and so avoid compiler error. + * sockets.c: Added trivial (int) cast to keep compiler happier. + * ip.c, netif.c Changed debug statements to use the tidier ip4_addrN() macros. + +(STABLE-1_0_0) + + ++ Changes: + + 2004-07-05 Leon Woestenberg + * sockets.*: Restructured LWIP_PRIVATE_TIMEVAL. Make sure + your cc.h file defines this either 1 or 0. If non-defined, + defaults to 1. + * .c: Added and includes where used. + * etharp.c: Made some array indices unsigned. + + 2004-06-27 Leon Woestenberg + * netif.*: Added netif_set_up()/down(). + * dhcp.c: Changes to restart program flow. + + 2004-05-07 Leon Woestenberg + * etharp.c: In find_entry(), instead of a list traversal per candidate, do a + single-pass lookup for different candidates. Should exploit locality. + + 2004-04-29 Leon Woestenberg + * tcp*.c: Cleaned up source comment documentation for Doxygen processing. + * opt.h: ETHARP_ALWAYS_INSERT option removed to comply with ARP RFC. + * etharp.c: update_arp_entry() only adds new ARP entries when adviced to by + the caller. This deprecates the ETHARP_ALWAYS_INSERT overrule option. + + ++ Bug fixes: + + 2004-04-27 Leon Woestenberg + * etharp.c: Applied patch of bug #8708 by Toni Mountifield with a solution + suggested by Timmy Brolin. Fix for 32-bit processors that cannot access + non-aligned 32-bit words, such as soms 32-bit TCP/IP header fields. Fix + is to prefix the 14-bit Ethernet headers with two padding bytes. + + 2004-04-23 Leon Woestenberg + * ip_addr.c: Fix in the ip_addr_isbroadcast() check. + * etharp.c: Fixed the case where the packet that initiates the ARP request + is not queued, and gets lost. Fixed the case where the packets destination + address is already known; we now always queue the packet and perform an ARP + request. + +(STABLE-0_7_0) + + ++ Bug fixes: + + * Fixed TCP bug for SYN_SENT to ESTABLISHED state transition. + * Fixed TCP bug in dequeueing of FIN from out of order segment queue. + * Fixed two possible NULL references in rare cases. + +(STABLE-0_6_6) + + ++ Bug fixes: + + * Fixed DHCP which did not include the IP address in DECLINE messages. + + ++ Changes: + + * etharp.c has been hauled over a bit. + +(STABLE-0_6_5) + + ++ Bug fixes: + + * Fixed TCP bug induced by bad window resizing with unidirectional TCP traffic. + * Packets sent from ARP queue had invalid source hardware address. + + ++ Changes: + + * Pass-by ARP requests do now update the cache. + + ++ New features: + + * No longer dependent on ctype.h. + * New socket options. + * Raw IP pcb support. + +(STABLE-0_6_4) + + ++ Bug fixes: + + * Some debug formatters and casts fixed. + * Numereous fixes in PPP. + + ++ Changes: + + * DEBUGF now is LWIP_DEBUGF + * pbuf_dechain() has been re-enabled. + * Mentioned the changed use of CVS branches in README. + +(STABLE-0_6_3) + + ++ Bug fixes: + + * Fixed pool pbuf memory leak in pbuf_alloc(). + Occured if not enough PBUF_POOL pbufs for a packet pbuf chain. + Reported by Savin Zlobec. + + * PBUF_POOL chains had their tot_len field not set for non-first + pbufs. Fixed in pbuf_alloc(). + + ++ New features: + + * Added PPP stack contributed by Marc Boucher + + ++ Changes: + + * Now drops short packets for ICMP/UDP/TCP protocols. More robust. + + * ARP queueuing now queues the latest packet instead of the first. + This is the RFC recommended behaviour, but can be overridden in + lwipopts.h. + +(0.6.2) + + ++ Bugfixes: + + * TCP has been fixed to deal with the new use of the pbuf->ref + counter. + + * DHCP dhcp_inform() crash bug fixed. + + ++ Changes: + + * Removed pbuf_pool_free_cache and pbuf_pool_alloc_cache. Also removed + pbuf_refresh(). This has sped up pbuf pool operations considerably. + Implemented by David Haas. + +(0.6.1) + + ++ New features: + + * The packet buffer implementation has been enhanced to support + zero-copy and copy-on-demand for packet buffers which have their + payloads in application-managed memory. + Implemented by David Haas. + + Use PBUF_REF to make a pbuf refer to RAM. lwIP will use zero-copy + if an outgoing packet can be directly sent on the link, or perform + a copy-on-demand when necessary. + + The application can safely assume the packet is sent, and the RAM + is available to the application directly after calling udp_send() + or similar function. + + ++ Bugfixes: + + * ARP_QUEUEING should now correctly work for all cases, including + PBUF_REF. + Implemented by Leon Woestenberg. + + ++ Changes: + + * IP_ADDR_ANY is no longer a NULL pointer. Instead, it is a pointer + to a '0.0.0.0' IP address. + + * The packet buffer implementation is changed. The pbuf->ref counter + meaning has changed, and several pbuf functions have been + adapted accordingly. + + * netif drivers have to be changed to set the hardware address length field + that must be initialized correctly by the driver (hint: 6 for Ethernet MAC). + See the contrib/ports/c16x cs8900 driver as a driver example. + + * netif's have a dhcp field that must be initialized to NULL by the driver. + See the contrib/ports/c16x cs8900 driver as a driver example. + +(0.5.x) This file has been unmaintained up to 0.6.1. All changes are + logged in CVS but have not been explained here. + +(0.5.3) Changes since version 0.5.2 + + ++ Bugfixes: + + * memp_malloc(MEMP_API_MSG) could fail with multiple application + threads because it wasn't protected by semaphores. + + ++ Other changes: + + * struct ip_addr now packed. + + * The name of the time variable in arp.c has been changed to ctime + to avoid conflicts with the time() function. + +(0.5.2) Changes since version 0.5.1 + + ++ New features: + + * A new TCP function, tcp_tmr(), now handles both TCP timers. + + ++ Bugfixes: + + * A bug in tcp_parseopt() could cause the stack to hang because of a + malformed TCP option. + + * The address of new connections in the accept() function in the BSD + socket library was not handled correctly. + + * pbuf_dechain() did not update the ->tot_len field of the tail. + + * Aborted TCP connections were not handled correctly in all + situations. + + ++ Other changes: + + * All protocol header structs are now packed. + + * The ->len field in the tcp_seg structure now counts the actual + amount of data, and does not add one for SYN and FIN segments. + +(0.5.1) Changes since version 0.5.0 + + ++ New features: + + * Possible to run as a user process under Linux. + + * Preliminary support for cross platform packed structs. + + * ARP timer now implemented. + + ++ Bugfixes: + + * TCP output queue length was badly initialized when opening + connections. + + * TCP delayed ACKs were not sent correctly. + + * Explicit initialization of BSS segment variables. + + * read() in BSD socket library could drop data. + + * Problems with memory alignment. + + * Situations when all TCP buffers were used could lead to + starvation. + + * TCP MSS option wasn't parsed correctly. + + * Problems with UDP checksum calculation. + + * IP multicast address tests had endianess problems. + + * ARP requests had wrong destination hardware address. + + ++ Other changes: + + * struct eth_addr changed from u16_t[3] array to u8_t[6]. + + * A ->linkoutput() member was added to struct netif. + + * TCP and UDP ->dest_* struct members where changed to ->remote_*. + + * ntoh* macros are now null definitions for big endian CPUs. + +(0.5.0) Changes since version 0.4.2 + + ++ New features: + + * Redesigned operating system emulation layer to make porting easier. + + * Better control over TCP output buffers. + + * Documenation added. + + ++ Bugfixes: + + * Locking issues in buffer management. + + * Bugfixes in the sequential API. + + * IP forwarding could cause memory leakage. This has been fixed. + + ++ Other changes: + + * Directory structure somewhat changed; the core/ tree has been + collapsed. + +(0.4.2) Changes since version 0.4.1 + + ++ New features: + + * Experimental ARP implementation added. + + * Skeleton Ethernet driver added. + + * Experimental BSD socket API library added. + + ++ Bugfixes: + + * In very intense situations, memory leakage could occur. This has + been fixed. + + ++ Other changes: + + * Variables named "data" and "code" have been renamed in order to + avoid name conflicts in certain compilers. + + * Variable++ have in appliciable cases been translated to ++variable + since some compilers generate better code in the latter case. + +(0.4.1) Changes since version 0.4 + + ++ New features: + + * TCP: Connection attempts time out earlier than data + transmissions. Nagle algorithm implemented. Push flag set on the + last segment in a burst. + + * UDP: experimental support for UDP-Lite extensions. + + ++ Bugfixes: + + * TCP: out of order segments were in some cases handled incorrectly, + and this has now been fixed. Delayed acknowledgements was broken + in 0.4, has now been fixed. Binding to an address that is in use + now results in an error. Reset connections sometimes hung an + application; this has been fixed. + + * Checksum calculation sometimes failed for chained pbufs with odd + lengths. This has been fixed. + + * API: a lot of bug fixes in the API. The UDP API has been improved + and tested. Error reporting and handling has been + improved. Logical flaws and race conditions for incoming TCP + connections has been found and removed. + + * Memory manager: alignment issues. Reallocating memory sometimes + failed, this has been fixed. + + * Generic library: bcopy was flawed and has been fixed. + + ++ Other changes: + + * API: all datatypes has been changed from generic ones such as + ints, to specified ones such as u16_t. Functions that return + errors now have the correct type (err_t). + + * General: A lot of code cleaned up and debugging code removed. Many + portability issues have been fixed. + + * The license was changed; the advertising clause was removed. + + * C64 port added. + + * Thanks: Huge thanks go to Dagan Galarneau, Horst Garnetzke, Petri + Kosunen, Mikael Caleres, and Frits Wilmink for reporting and + fixing bugs! + +(0.4) Changes since version 0.3.1 + + * Memory management has been radically changed; instead of + allocating memory from a shared heap, memory for objects that are + rapidly allocated and deallocated is now kept in pools. Allocation + and deallocation from those memory pools is very fast. The shared + heap is still present but is used less frequently. + + * The memory, memory pool, and packet buffer subsystems now support + 4-, 2-, or 1-byte alignment. + + * "Out of memory" situations are handled in a more robust way. + + * Stack usage has been reduced. + + * Easier configuration of lwIP parameters such as memory usage, + TTLs, statistics gathering, etc. All configuration parameters are + now kept in a single header file "lwipopts.h". + + * The directory structure has been changed slightly so that all + architecture specific files are kept under the src/arch + hierarchy. + + * Error propagation has been improved, both in the protocol modules + and in the API. + + * The code for the RTXC architecture has been implemented, tested + and put to use. + + * Bugs have been found and corrected in the TCP, UDP, IP, API, and + the Internet checksum modules. + + * Bugs related to porting between a 32-bit and a 16-bit architecture + have been found and corrected. + + * The license has been changed slightly to conform more with the + original BSD license, including the advertisement clause. + +(0.3.1) Changes since version 0.3 + + * Fix of a fatal bug in the buffer management. Pbufs with allocated + RAM never returned the RAM when the pbuf was deallocated. + + * TCP congestion control, window updates and retransmissions did not + work correctly. This has now been fixed. + + * Bugfixes in the API. + +(0.3) Changes since version 0.2 + + * New and improved directory structure. All include files are now + kept in a dedicated include/ directory. + + * The API now has proper error handling. A new function, + netconn_err(), now returns an error code for the connection in + case of errors. + + * Improvements in the memory management subsystem. The system now + keeps a pointer to the lowest free memory block. A new function, + mem_malloc2() tries to allocate memory once, and if it fails tries + to free some memory and retry the allocation. + + * Much testing has been done with limited memory + configurations. lwIP now does a better job when overloaded. + + * Some bugfixes and improvements to the buffer (pbuf) subsystem. + + * Many bugfixes in the TCP code: + + - Fixed a bug in tcp_close(). + + - The TCP receive window was incorrectly closed when out of + sequence segments was received. This has been fixed. + + - Connections are now timed-out of the FIN-WAIT-2 state. + + - The initial congestion window could in some cases be too + large. This has been fixed. + + - The retransmission queue could in some cases be screwed up. This + has been fixed. + + - TCP RST flag now handled correctly. + + - Out of sequence data was in some cases never delivered to the + application. This has been fixed. + + - Retransmitted segments now contain the correct acknowledgment + number and advertised window. + + - TCP retransmission timeout backoffs are not correctly computed + (ala BSD). After a number of retransmissions, TCP now gives up + the connection. + + * TCP connections now are kept on three lists, one for active + connections, one for listening connections, and one for + connections that are in TIME-WAIT. This greatly speeds up the fast + timeout processing for sending delayed ACKs. + + * TCP now provides proper feedback to the application when a + connection has been successfully set up. + + * More comments have been added to the code. The code has also been + somewhat cleaned up. + +(0.2) Initial public release. diff --git a/components/net/lwip-2.0.3/COPYING b/components/net/lwip-2.0.3/COPYING new file mode 100644 index 0000000000..e23898b5e8 --- /dev/null +++ b/components/net/lwip-2.0.3/COPYING @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2001, 2002 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + + diff --git a/components/net/lwip-2.0.3/FILES b/components/net/lwip-2.0.3/FILES new file mode 100644 index 0000000000..e6e09989d9 --- /dev/null +++ b/components/net/lwip-2.0.3/FILES @@ -0,0 +1,5 @@ +src/ - The source code for the lwIP TCP/IP stack. +doc/ - The documentation for lwIP. +test/ - Some code to test whether the sources do what they should. + +See also the FILES file in each subdirectory. diff --git a/components/net/lwip-2.0.3/README b/components/net/lwip-2.0.3/README new file mode 100644 index 0000000000..0884d27bea --- /dev/null +++ b/components/net/lwip-2.0.3/README @@ -0,0 +1,100 @@ +INTRODUCTION + +lwIP is a small independent implementation of the TCP/IP protocol +suite that has been developed by Adam Dunkels at the Computer and +Networks Architectures (CNA) lab at the Swedish Institute of Computer +Science (SICS). + +The focus of the lwIP TCP/IP implementation is to reduce the RAM usage +while still having a full scale TCP. This making lwIP suitable for use +in embedded systems with tens of kilobytes of free RAM and room for +around 40 kilobytes of code ROM. + + +FEATURES + + * IP (Internet Protocol, IPv4 and IPv6) including packet forwarding over + multiple network interfaces + * ICMP (Internet Control Message Protocol) for network maintenance and debugging + * IGMP (Internet Group Management Protocol) for multicast traffic management + * MLD (Multicast listener discovery for IPv6). Aims to be compliant with + RFC 2710. No support for MLDv2 + * ND (Neighbor discovery and stateless address autoconfiguration for IPv6). + Aims to be compliant with RFC 4861 (Neighbor discovery) and RFC 4862 + (Address autoconfiguration) + * UDP (User Datagram Protocol) including experimental UDP-lite extensions + * TCP (Transmission Control Protocol) with congestion control, RTT estimation + and fast recovery/fast retransmit + * raw/native API for enhanced performance + * Optional Berkeley-like socket API + * DNS (Domain names resolver) + + +APPLICATIONS + + * HTTP server with SSI and CGI + * SNMPv2c agent with MIB compiler (Simple Network Management Protocol) + * SNTP (Simple network time protocol) + * NetBIOS name service responder + * MDNS (Multicast DNS) responder + * iPerf server implementation + + +LICENSE + +lwIP is freely available under a BSD license. + + +DEVELOPMENT + +lwIP has grown into an excellent TCP/IP stack for embedded devices, +and developers using the stack often submit bug fixes, improvements, +and additions to the stack to further increase its usefulness. + +Development of lwIP is hosted on Savannah, a central point for +software development, maintenance and distribution. Everyone can +help improve lwIP by use of Savannah's interface, Git and the +mailing list. A core team of developers will commit changes to the +Git source tree. + +The lwIP TCP/IP stack is maintained in the 'lwip' Git module and +contributions (such as platform ports) are in the 'contrib' Git module. + +See doc/savannah.txt for details on Git server access for users and +developers. + +The current Git trees are web-browsable: + http://git.savannah.gnu.org/cgit/lwip.git + http://git.savannah.gnu.org/cgit/lwip/lwip-contrib.git + +Submit patches and bugs via the lwIP project page: + http://savannah.nongnu.org/projects/lwip/ + +Continuous integration builds (GCC, clang): + https://travis-ci.org/yarrick/lwip-merged + + +DOCUMENTATION + +Self documentation of the source code is regularly extracted from the current +Git sources and is available from this web page: + http://www.nongnu.org/lwip/ + +There is now a constantly growing wiki about lwIP at + http://lwip.wikia.com/wiki/LwIP_Wiki + +Also, there are mailing lists you can subscribe at + http://savannah.nongnu.org/mail/?group=lwip +plus searchable archives: + http://lists.nongnu.org/archive/html/lwip-users/ + http://lists.nongnu.org/archive/html/lwip-devel/ + +lwIP was originally written by Adam Dunkels: + http://dunkels.com/adam/ + +Reading Adam's papers, the files in docs/, browsing the source code +documentation and browsing the mailing list archives is a good way to +become familiar with the design of lwIP. + +Adam Dunkels +Leon Woestenberg diff --git a/components/net/lwip-2.0.3/READTEST.md b/components/net/lwip-2.0.3/READTEST.md new file mode 100644 index 0000000000..a407a1db52 --- /dev/null +++ b/components/net/lwip-2.0.3/READTEST.md @@ -0,0 +1,29 @@ +Porting network interface device for RT-Thread in lwIP. + +The major jobs following RT-Thread Team. Only update the origin code of lwip 2.0.2 to lwip 2.0.3. +And keep the difference between on the change of RT-Thread Team. + +by xiangxistu 2021/06/21 17:00 PM +liuxianliang@rt-thread.com + +The major jobs following RT-Thread Team. The RT-Thread network interface device need to synchronize some network status and address information in lwIP, so it need to make some changes in the lwIP netwrok status and address operations function. +The specific changes are as follows: + + - netif.c: add RT-Thread netdev header file , status synchronize(UP, LINK_UP), address synchronize(IP, netmask, gateway); + + - dns.c: add RT-Thread header file, dns servers synchronize; + + - sockets.c: custom 'select' function implementation in RT-Thread by the wait queue mode. + +by ChenYong 2019/3/26 10:00 AM +chenyong@rt-thread.com + + +Porting lwip 2.0.2 running on RT-Thread. +The major jobs following RT-Thread Team. The RT-Thread team already port the lwip 2.0.0, so I only do some move code and test jobs. +I use the memory pools to test lwip 2.0.2, I use the iperf tool to test it about more than 20 hours, It is running normal. +I don't test it working on memory heap. +... +Good Luck. +by Hans.Huang 2017/3/27 10:52 AM +huangxi_hans@163.com diff --git a/components/net/lwip-2.0.3/SConscript b/components/net/lwip-2.0.3/SConscript new file mode 100644 index 0000000000..36d8e92dc6 --- /dev/null +++ b/components/net/lwip-2.0.3/SConscript @@ -0,0 +1,89 @@ +from building import * + +src = Split(""" +src/arch/sys_arch.c +src/api/api_lib.c +src/api/api_msg.c +src/api/err.c +src/api/netbuf.c +src/api/netdb.c +src/api/netifapi.c +src/api/sockets.c +src/api/tcpip.c +src/core/def.c +src/core/dns.c +src/core/inet_chksum.c +src/core/init.c +src/core/ip.c +src/core/memp.c +src/core/netif.c +src/core/pbuf.c +src/core/raw.c +src/core/stats.c +src/core/sys.c +src/core/tcp.c +src/core/tcp_in.c +src/core/tcp_out.c +src/core/timeouts.c +src/core/udp.c +src/netif/ethernet.c +src/netif/ethernetif.c +src/netif/lowpan6.c +""") + +ipv4_src = Split(""" +src/core/ipv4/autoip.c +src/core/ipv4/dhcp.c +src/core/ipv4/etharp.c +src/core/ipv4/icmp.c +src/core/ipv4/igmp.c +src/core/ipv4/ip4.c +src/core/ipv4/ip4_addr.c +src/core/ipv4/ip4_frag.c +""") + +ipv6_src = Split(""" +src/core/ipv6/dhcp6.c +src/core/ipv6/ethip6.c +src/core/ipv6/icmp6.c +src/core/ipv6/inet6.c +src/core/ipv6/ip6.c +src/core/ipv6/ip6_addr.c +src/core/ipv6/ip6_frag.c +src/core/ipv6/mld6.c +src/core/ipv6/nd6.c +""") + +snmp_src = Glob("src/apps/snmp/*.c") + +ppp_src = Glob("src/netif/ppp/*.c") + Glob("src/netif/ppp/polarssl/*c") + +src = src + ipv4_src + +# The set of source files associated with this SConscript file. +path = [GetCurrentDir() + '/src', + GetCurrentDir() + '/src/include', + GetCurrentDir() + '/src/include/ipv4', + GetCurrentDir() + '/src/arch/include', + GetCurrentDir() + '/src/include/netif'] + +if not GetDepend('RT_USING_SAL'): + path += [GetCurrentDir() + '/src/include/posix'] + +if GetDepend(['RT_LWIP_SNMP']): + src += snmp_src + path += [GetCurrentDir() + '/src/apps/snmp'] + +if GetDepend(['RT_LWIP_PPP']): + src += ppp_src + path += [GetCurrentDir() + '/src/netif/ppp'] + +if GetDepend(['RT_USING_LWIP_IPV6']): + src += ipv6_src + +if GetDepend(['RT_LWIP_USING_PING']): + src += Glob('src/apps/ping/ping.c') + +group = DefineGroup('lwIP', src, depend = ['RT_USING_LWIP', 'RT_USING_LWIP203'], CPPPATH = path) + +Return('group') diff --git a/components/net/lwip-2.0.3/UPGRADING b/components/net/lwip-2.0.3/UPGRADING new file mode 100644 index 0000000000..60a04385d3 --- /dev/null +++ b/components/net/lwip-2.0.3/UPGRADING @@ -0,0 +1,243 @@ +This file lists major changes between release versions that require +ports or applications to be changed. Use it to update a port or an +application written for an older version of lwIP to correctly work +with newer versions. + + +(git master) + + * [Enter new changes just after this line - do not remove this line] + +(2.0.2) + + ++ Application changes: + + * slipif: The way to pass serial port number has changed. netif->num is not + supported any more, netif->state is interpreted as an u8_t port number now + (it's not a POINTER to an u8_t any more!) + +(2.0.1) + + ++ Application changes: + + * UDP does NOT receive multicast traffic from ALL netifs on an UDP PCB bound to a specific + netif any more. Users need to bind to IP_ADDR_ANY to receive multicast traffic and compare + ip_current_netif() to the desired netif for every packet. + See bug #49662 for an explanation. + +(2.0.0) + + ++ Application changes: + + * Changed netif "up" flag handling to be an administrative flag (as opposed to the previous meaning of + "ip4-address-valid", a netif will now not be used for transmission if not up) -> even a DHCP netif + has to be set "up" before starting the DHCP client + * Added IPv6 support (dual-stack or IPv4/IPv6 only) + * Changed ip_addr_t to be a union in dual-stack mode (use ip4_addr_t where referring to IPv4 only). + * Major rewrite of SNMP (added MIB parser that creates code stubs for custom MIBs); + supports SNMPv2c (experimental v3 support) + * Moved some core applications from contrib repository to src/apps (and include/lwip/apps) + + +++ Raw API: + * Changed TCP listen backlog: removed tcp_accepted(), added the function pair tcp_backlog_delayed()/ + tcp_backlog_accepted() to explicitly delay backlog handling on a connection pcb + + +++ Socket API: + * Added an implementation for posix sendmsg() + * Added LWIP_FIONREAD_LINUXMODE that makes ioctl/FIONREAD return the size of the next pending datagram + + ++ Port changes + + +++ new files: + * MANY new and moved files! + * Added src/Filelists.mk for use in Makefile projects + * Continued moving stack-internal parts from abc.h to abc_priv.h in sub-folder "priv" + to let abc.h only contain the actual application programmer's API + + +++ sys layer: + * Made LWIP_TCPIP_CORE_LOCKING==1 the default as it usually performs better than + the traditional message passing (although with LWIP_COMPAT_MUTEX you are still + open to priority inversion, so this is not recommended any more) + * Added LWIP_NETCONN_SEM_PER_THREAD to use one "op_completed" semaphore per thread + instead of using one per netconn (these semaphores are used even with core locking + enabled as some longer lasting functions like big writes still need to delay) + * Added generalized abstraction for itoa(), strnicmp(), stricmp() and strnstr() + in def.h (to be overridden in cc.h) instead of config + options for netbiosns, httpd, dns, etc. ... + * New abstraction for hton* and ntoh* functions in def.h. + To override them, use the following in cc.h: + #define lwip_htons(x) + #define lwip_htonl(x) + + +++ new options: + * TODO + + +++ new pools: + * Added LWIP_MEMPOOL_* (declare/init/alloc/free) to declare private memp pools + that share memp.c code but do not have to be made global via lwippools.h + * Added pools for IPv6, MPU_COMPATIBLE, dns-api, netif-api, etc. + * added hook LWIP_HOOK_MEMP_AVAILABLE() to get informed when a memp pool was empty and an item + is now available + + * Signature of LWIP_HOOK_VLAN_SET macro was changed + + * LWIP_DECLARE_MEMORY_ALIGNED() may be used to declare aligned memory buffers (mem/memp) + or to move buffers to dedicated memory using compiler attributes + + * Standard C headers are used to define sized types and printf formatters + (disable by setting LWIP_NO_STDINT_H=1 or LWIP_NO_INTTYPES_H=1 if your compiler + does not support these) + + + ++ Major bugfixes/improvements + + * Added IPv6 support (dual-stack or IPv4/IPv6 only) + * Major rewrite of PPP (incl. keep-up with apache pppd) + see doc/ppp.txt for an upgrading how-to + * Major rewrite of SNMP (incl. MIB parser) + * Fixed timing issues that might have lead to losing a DHCP lease + * Made rx processing path more robust against crafted errors + * TCP window scaling support + * modification of api modules to support FreeRTOS-MPU (don't pass stack-pointers to other threads) + * made DNS client more robust + * support PBUF_REF for RX packets + * LWIP_NETCONN_FULLDUPLEX allows netconn/sockets to be used for reading/writing from separate + threads each (needs LWIP_NETCONN_SEM_PER_THREAD) + * Moved and reordered stats (mainly memp/mib2) + +(1.4.0) + + ++ Application changes: + + * Replaced struct ip_addr by typedef ip_addr_t (struct ip_addr is kept for + compatibility to old applications, but will be removed in the future). + + * Renamed mem_realloc() to mem_trim() to prevent confusion with realloc() + + +++ Raw API: + * Changed the semantics of tcp_close() (since it was rather a + shutdown before): Now the application does *NOT* get any calls to the recv + callback (aside from NULL/closed) after calling tcp_close() + + * When calling tcp_abort() from a raw API TCP callback function, + make sure you return ERR_ABRT to prevent accessing unallocated memory. + (ERR_ABRT now means the applicaiton has called tcp_abort!) + + +++ Netconn API: + * Changed netconn_receive() and netconn_accept() to return + err_t, not a pointer to new data/netconn. + + +++ Socket API: + * LWIP_SO_RCVTIMEO: when accept() or recv() time out, they + now set errno to EWOULDBLOCK/EAGAIN, not ETIMEDOUT. + + * Added a minimal version of posix fctl() to have a + standardised way to set O_NONBLOCK for nonblocking sockets. + + +++ all APIs: + * correctly implemented SO(F)_REUSEADDR + + ++ Port changes + + +++ new files: + + * Added 4 new files: def.c, timers.c, timers.h, tcp_impl.h: + + * Moved stack-internal parts of tcp.h to tcp_impl.h, tcp.h now only contains + the actual application programmer's API + + * Separated timer implementation from sys.h/.c, moved to timers.h/.c; + Added timer implementation for NO_SYS==1, set NO_SYS_NO_TIMERS==1 if you + still want to use your own timer implementation for NO_SYS==0 (as before). + + +++ sys layer: + + * Converted mbox- and semaphore-functions to take pointers to sys_mbox_t/ + sys_sem_t; + + * Converted sys_mbox_new/sys_sem_new to take pointers and return err_t; + + * Added Mutex concept in sys_arch (define LWIP_COMPAT_MUTEX to let sys.h use + binary semaphores instead of mutexes - as before) + + +++ new options: + + * Don't waste memory when chaining segments, added option TCP_OVERSIZE to + prevent creating many small pbufs when calling tcp_write with many small + blocks of data. Instead, pbufs are allocated larger than needed and the + space is used for later calls to tcp_write. + + * Added LWIP_NETIF_TX_SINGLE_PBUF to always copy to try to create single pbufs + in tcp_write/udp_send. + + * Added an additional option LWIP_ETHERNET to support ethernet without ARP + (necessary for pure PPPoE) + + * Add MEMP_SEPARATE_POOLS to place memory pools in separate arrays. This may + be used to place these pools into user-defined memory by using external + declaration. + + * Added TCP_SNDQUEUELOWAT corresponding to TCP_SNDLOWAT + + +++ new pools: + + * Netdb uses a memp pool for allocating memory when getaddrinfo() is called, + so MEMP_NUM_NETDB has to be set accordingly. + + * DNS_LOCAL_HOSTLIST_IS_DYNAMIC uses a memp pool instead of the heap, so + MEMP_NUM_LOCALHOSTLIST has to be set accordingly. + + * Snmp-agent uses a memp pools instead of the heap, so MEMP_NUM_SNMP_* have + to be set accordingly. + + * PPPoE uses a MEMP pool instead of the heap, so MEMP_NUM_PPPOE_INTERFACES + has to be set accordingly + + * Integrated loopif into netif.c - loopif does not have to be created by the + port any more, just define LWIP_HAVE_LOOPIF to 1. + + * Added define LWIP_RAND() for lwip-wide randomization (needs to be defined + in cc.h, e.g. used by igmp) + + * Added printf-formatter X8_F to printf u8_t as hex + + * The heap now may be moved to user-defined memory by defining + LWIP_RAM_HEAP_POINTER as a void pointer to that memory's address + + * added autoip_set_struct() and dhcp_set_struct() to let autoip and dhcp work + with user-allocated structs instead of calling mem_malloc + + * Added const char* name to mem- and memp-stats for easier debugging. + + * Calculate the TCP/UDP checksum while copying to only fetch data once: + Define LWIP_CHKSUM_COPY to a memcpy-like function that returns the checksum + + * Added SO_REUSE_RXTOALL to pass received UDP broadcast/multicast packets to + more than one pcb. + + * Changed the semantics of ARP_QUEUEING==0: ARP_QUEUEING now cannot be turned + off any more, if this is set to 0, only one packet (the most recent one) is + queued (like demanded by RFC 1122). + + + ++ Major bugfixes/improvements + + * Implemented tcp_shutdown() to only shut down one end of a connection + * Implemented shutdown() at socket- and netconn-level + * Added errorset support to select() + improved select speed overhead + * Merged pppd to v2.3.11 (including some backported bugfixes from 2.4.x) + * Added timer implementation for NO_SYS==1 (may be disabled with NO_SYS_NO_TIMERS==1 + * Use macros defined in ip_addr.h to work with IP addresses + * Implemented many nonblocking socket/netconn functions + * Fixed ARP input processing: only add a new entry if a request was directed as us + * mem_realloc() to mem_trim() to prevent confusion with realloc() + * Some improvements for AutoIP (don't route/forward link-local addresses, don't break + existing connections when assigning a routable address) + * Correctly handle remote side overrunning our rcv_wnd in ooseq case + * Removed packing from ip_addr_t, the packed version is now only used in protocol headers + * Corrected PBUF_POOL_BUFSIZE for ports where ETH_PAD_SIZE > 0 + * Added support for static ARP table entries + +(STABLE-1.3.2) + + * initial version of this file diff --git a/components/net/lwip-2.0.3/doc/FILES b/components/net/lwip-2.0.3/doc/FILES new file mode 100644 index 0000000000..e588575085 --- /dev/null +++ b/components/net/lwip-2.0.3/doc/FILES @@ -0,0 +1,9 @@ +doxygen/ - Configuration files and scripts to create the lwIP doxygen source + documentation (found at http://www.nongnu.org/lwip/) + +savannah.txt - How to obtain the current development source code. +contrib.txt - How to contribute to lwIP as a developer. +rawapi.txt - The documentation for the core API of lwIP. + Also provides an overview about the other APIs and multithreading. +sys_arch.txt - The documentation for a system abstraction layer of lwIP. +ppp.txt - Documentation of the PPP interface for lwIP. diff --git a/components/net/lwip-2.0.3/doc/NO_SYS_SampleCode.c b/components/net/lwip-2.0.3/doc/NO_SYS_SampleCode.c new file mode 100644 index 0000000000..f0af6600b7 --- /dev/null +++ b/components/net/lwip-2.0.3/doc/NO_SYS_SampleCode.c @@ -0,0 +1,122 @@ +void +eth_mac_irq() +{ + /* Service MAC IRQ here */ + + /* Allocate pbuf from pool (avoid using heap in interrupts) */ + struct pbuf* p = pbuf_alloc(PBUF_RAW, eth_data_count, PBUF_POOL); + + if(p != NULL) { + /* Copy ethernet frame into pbuf */ + pbuf_take(p, eth_data, eth_data_count); + + /* Put in a queue which is processed in main loop */ + if(!queue_try_put(&queue, p)) { + /* queue is full -> packet loss */ + pbuf_free(p); + } + } +} + +static err_t +netif_output(struct netif *netif, struct pbuf *p) +{ + LINK_STATS_INC(link.xmit); + + /* Update SNMP stats (only if you use SNMP) */ + MIB2_STATS_NETIF_ADD(netif, ifoutoctets, p->tot_len); + int unicast = ((p->payload[0] & 0x01) == 0); + if (unicast) { + MIB2_STATS_NETIF_INC(netif, ifoutucastpkts); + } else { + MIB2_STATS_NETIF_INC(netif, ifoutnucastpkts); + } + + lock_interrupts(); + pbuf_copy_partial(p, mac_send_buffer, p->tot_len, 0); + /* Start MAC transmit here */ + unlock_interrupts(); + + return ERR_OK; +} + +static void +netif_status_callback(struct netif *netif) +{ + printf("netif status changed %s\n", ip4addr_ntoa(netif_ip4_addr(netif))); +} + +static err_t +netif_init(struct netif *netif) +{ + netif->linkoutput = netif_output; + netif->output = etharp_output; + netif->output_ip6 = ethip6_output; + netif->mtu = ETHERNET_MTU; + netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET | NETIF_FLAG_IGMP | NETIF_FLAG_MLD6; + MIB2_INIT_NETIF(netif, snmp_ifType_ethernet_csmacd, 100000000); + + SMEMCPY(netif->hwaddr, your_mac_address_goes_here, sizeof(netif->hwaddr)); + netif->hwaddr_len = sizeof(netif->hwaddr); + + return ERR_OK; +} + +void +main(void) +{ + struct netif netif; + + lwip_init(); + + netif_add(&netif, IP4_ADDR_ANY, IP4_ADDR_ANY, IP4_ADDR_ANY, NULL, netif_init, netif_input); + netif.name[0] = 'e'; + netif.name[1] = '0'; + netif_create_ip6_linklocal_address(&netif, 1); + netif.ip6_autoconfig_enabled = 1; + netif_set_status_callback(&netif, netif_status_callback); + netif_set_default(&netif); + netif_set_up(&netif); + + /* Start DHCP and HTTPD */ + dhcp_start(&netif ); + httpd_init(); + + while(1) { + /* Check link state, e.g. via MDIO communication with PHY */ + if(link_state_changed()) { + if(link_is_up()) { + netif_set_link_up(&netif); + } else { + netif_set_link_down(&netif); + } + } + + /* Check for received frames, feed them to lwIP */ + lock_interrupts(); + struct pbuf* p = queue_try_get(&queue); + unlock_interrupts(); + + if(p != NULL) { + LINK_STATS_INC(link.recv); + + /* Update SNMP stats (only if you use SNMP) */ + MIB2_STATS_NETIF_ADD(netif, ifinoctets, p->tot_len); + int unicast = ((p->payload[0] & 0x01) == 0); + if (unicast) { + MIB2_STATS_NETIF_INC(netif, ifinucastpkts); + } else { + MIB2_STATS_NETIF_INC(netif, ifinnucastpkts); + } + + if(netif.input(p, &netif) != ERR_OK) { + pbuf_free(p); + } + } + + /* Cyclic lwIP timers check */ + sys_check_timeouts(); + + /* your application goes here */ + } +} diff --git a/components/net/lwip-2.0.3/doc/contrib.txt b/components/net/lwip-2.0.3/doc/contrib.txt new file mode 100644 index 0000000000..6f0d7bc516 --- /dev/null +++ b/components/net/lwip-2.0.3/doc/contrib.txt @@ -0,0 +1,58 @@ +1 Introduction + +This document describes some guidelines for people participating +in lwIP development. + +2 How to contribute to lwIP + +Here is a short list of suggestions to anybody working with lwIP and +trying to contribute bug reports, fixes, enhancements, platform ports etc. +First of all as you may already know lwIP is a volunteer project so feedback +to fixes or questions might often come late. Hopefully the bug and patch tracking +features of Savannah help us not lose users' input. + +2.1 Source code style: + +1. do not use tabs. +2. indentation is two spaces per level (i.e. per tab). +3. end debug messages with a trailing newline (\n). +4. one space between keyword and opening bracket. +5. no space between function and opening bracket. +6. one space and no newline before opening curly braces of a block. +7. closing curly brace on a single line. +8. spaces surrounding assignment and comparisons. +9. don't initialize static and/or global variables to zero, the compiler takes care of that. +10. use current source code style as further reference. + +2.2 Source code documentation style: + +1. JavaDoc compliant and Doxygen compatible. +2. Function documentation above functions in .c files, not .h files. + (This forces you to synchronize documentation and implementation.) +3. Use current documentation style as further reference. + +2.3 Bug reports and patches: + +1. Make sure you are reporting bugs or send patches against the latest + sources. (From the latest release and/or the current Git sources.) +2. If you think you found a bug make sure it's not already filed in the + bugtracker at Savannah. +3. If you have a fix put the patch on Savannah. If it is a patch that affects + both core and arch specific stuff please separate them so that the core can + be applied separately while leaving the other patch 'open'. The preferred way + is to NOT touch archs you can't test and let maintainers take care of them. + This is a good way to see if they are used at all - the same goes for unix + netifs except tapif. +4. Do not file a bug and post a fix to it to the patch area. Either a bug report + or a patch will be enough. + If you correct an existing bug then attach the patch to the bug rather than creating a new entry in the patch area. +5. Patches should be specific to a single change or to related changes. Do not mix bugfixes with spelling and other + trivial fixes unless the bugfix is trivial too. Do not reorganize code and rename identifiers in the same patch you + change behaviour if not necessary. A patch is easier to read and understand if it's to the point and short than + if it's not to the point and long :) so the chances for it to be applied are greater. + +2.4 Platform porters: + +1. If you have ported lwIP to a platform (an OS, a uC/processor or a combination of these) and + you think it could benefit others[1] you might want discuss this on the mailing list. You + can also ask for Git access to submit and maintain your port in the contrib Git module. diff --git a/components/net/lwip-2.0.3/doc/doxygen/generate.bat b/components/net/lwip-2.0.3/doc/doxygen/generate.bat new file mode 100644 index 0000000000..4eab18c7f4 --- /dev/null +++ b/components/net/lwip-2.0.3/doc/doxygen/generate.bat @@ -0,0 +1 @@ +doxygen lwip.Doxyfile diff --git a/components/net/lwip-2.0.3/doc/doxygen/generate.sh b/components/net/lwip-2.0.3/doc/doxygen/generate.sh new file mode 100644 index 0000000000..89344b0e81 --- /dev/null +++ b/components/net/lwip-2.0.3/doc/doxygen/generate.sh @@ -0,0 +1,3 @@ +#!/bin/sh + +doxygen lwip.Doxyfile diff --git a/components/net/lwip-2.0.3/doc/doxygen/lwip.Doxyfile b/components/net/lwip-2.0.3/doc/doxygen/lwip.Doxyfile new file mode 100644 index 0000000000..95fa363b41 --- /dev/null +++ b/components/net/lwip-2.0.3/doc/doxygen/lwip.Doxyfile @@ -0,0 +1,2505 @@ +# Doxyfile 1.8.11 + +# This file describes the settings to be used by the documentation system +# doxygen (www.doxygen.org) for a project. +# +# All text after a double hash (##) is considered a comment and is placed in +# front of the TAG it is preceding. +# +# All text after a single hash (#) is considered a comment and will be ignored. +# The format is: +# TAG = value [value, ...] +# For lists, items can also be appended using: +# TAG += value [value, ...] +# Values that contain spaces should be placed between quotes (\" \"). + +#--------------------------------------------------------------------------- +# Project related configuration options +#--------------------------------------------------------------------------- + +# This tag specifies the encoding used for all characters in the config file +# that follow. The default is UTF-8 which is also the encoding used for all text +# before the first occurrence of this tag. Doxygen uses libiconv (or the iconv +# built into libc) for the transcoding. See http://www.gnu.org/software/libiconv +# for the list of possible encodings. +# The default value is: UTF-8. + +DOXYFILE_ENCODING = UTF-8 + +# The PROJECT_NAME tag is a single word (or a sequence of words surrounded by +# double-quotes, unless you are using Doxywizard) that should identify the +# project for which the documentation is generated. This name is used in the +# title of most generated pages and in a few other places. +# The default value is: My Project. + +PROJECT_NAME = "lwIP" + +# The PROJECT_NUMBER tag can be used to enter a project or revision number. This +# could be handy for archiving the generated documentation or if some version +# control system is used. + +PROJECT_NUMBER = "2.0.3" + +# Using the PROJECT_BRIEF tag one can provide an optional one line description +# for a project that appears at the top of each page and should give viewer a +# quick idea about the purpose of the project. Keep the description short. + +PROJECT_BRIEF = "Lightweight IP stack" + +# With the PROJECT_LOGO tag one can specify a logo or an icon that is included +# in the documentation. The maximum height of the logo should not exceed 55 +# pixels and the maximum width should not exceed 200 pixels. Doxygen will copy +# the logo to the output directory. + +PROJECT_LOGO = + +# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) path +# into which the generated documentation will be written. If a relative path is +# entered, it will be relative to the location where doxygen was started. If +# left blank the current directory will be used. + +OUTPUT_DIRECTORY = output + +# If the CREATE_SUBDIRS tag is set to YES then doxygen will create 4096 sub- +# directories (in 2 levels) under the output directory of each output format and +# will distribute the generated files over these directories. Enabling this +# option can be useful when feeding doxygen a huge amount of source files, where +# putting all generated files in the same directory would otherwise causes +# performance problems for the file system. +# The default value is: NO. + +CREATE_SUBDIRS = NO + +# If the ALLOW_UNICODE_NAMES tag is set to YES, doxygen will allow non-ASCII +# characters to appear in the names of generated files. If set to NO, non-ASCII +# characters will be escaped, for example _xE3_x81_x84 will be used for Unicode +# U+3044. +# The default value is: NO. + +ALLOW_UNICODE_NAMES = NO + +# The OUTPUT_LANGUAGE tag is used to specify the language in which all +# documentation generated by doxygen is written. Doxygen will use this +# information to generate all constant output in the proper language. +# Possible values are: Afrikaans, Arabic, Armenian, Brazilian, Catalan, Chinese, +# Chinese-Traditional, Croatian, Czech, Danish, Dutch, English (United States), +# Esperanto, Farsi (Persian), Finnish, French, German, Greek, Hungarian, +# Indonesian, Italian, Japanese, Japanese-en (Japanese with English messages), +# Korean, Korean-en (Korean with English messages), Latvian, Lithuanian, +# Macedonian, Norwegian, Persian (Farsi), Polish, Portuguese, Romanian, Russian, +# Serbian, Serbian-Cyrillic, Slovak, Slovene, Spanish, Swedish, Turkish, +# Ukrainian and Vietnamese. +# The default value is: English. + +OUTPUT_LANGUAGE = English + +# If the BRIEF_MEMBER_DESC tag is set to YES, doxygen will include brief member +# descriptions after the members that are listed in the file and class +# documentation (similar to Javadoc). Set to NO to disable this. +# The default value is: YES. + +BRIEF_MEMBER_DESC = YES + +# If the REPEAT_BRIEF tag is set to YES, doxygen will prepend the brief +# description of a member or function before the detailed description +# +# Note: If both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the +# brief descriptions will be completely suppressed. +# The default value is: YES. + +REPEAT_BRIEF = YES + +# This tag implements a quasi-intelligent brief description abbreviator that is +# used to form the text in various listings. Each string in this list, if found +# as the leading text of the brief description, will be stripped from the text +# and the result, after processing the whole list, is used as the annotated +# text. Otherwise, the brief description is used as-is. If left blank, the +# following values are used ($name is automatically replaced with the name of +# the entity):The $name class, The $name widget, The $name file, is, provides, +# specifies, contains, represents, a, an and the. + +ABBREVIATE_BRIEF = "The $name class " \ + "The $name widget " \ + "The $name file " \ + is \ + provides \ + specifies \ + contains \ + represents \ + a \ + an \ + the + +# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then +# doxygen will generate a detailed section even if there is only a brief +# description. +# The default value is: NO. + +ALWAYS_DETAILED_SEC = NO + +# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all +# inherited members of a class in the documentation of that class as if those +# members were ordinary class members. Constructors, destructors and assignment +# operators of the base classes will not be shown. +# The default value is: NO. + +INLINE_INHERITED_MEMB = NO + +# If the FULL_PATH_NAMES tag is set to YES, doxygen will prepend the full path +# before files name in the file list and in the header files. If set to NO the +# shortest path that makes the file name unique will be used +# The default value is: YES. + +FULL_PATH_NAMES = YES + +# The STRIP_FROM_PATH tag can be used to strip a user-defined part of the path. +# Stripping is only done if one of the specified strings matches the left-hand +# part of the path. The tag can be used to show relative paths in the file list. +# If left blank the directory from which doxygen is run is used as the path to +# strip. +# +# Note that you can specify absolute paths here, but also relative paths, which +# will be relative from the directory where doxygen is started. +# This tag requires that the tag FULL_PATH_NAMES is set to YES. + +STRIP_FROM_PATH = ../../ + +# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of the +# path mentioned in the documentation of a class, which tells the reader which +# header file to include in order to use a class. If left blank only the name of +# the header file containing the class definition is used. Otherwise one should +# specify the list of include paths that are normally passed to the compiler +# using the -I flag. + +STRIP_FROM_INC_PATH = + +# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter (but +# less readable) file names. This can be useful is your file systems doesn't +# support long names like on DOS, Mac, or CD-ROM. +# The default value is: NO. + +SHORT_NAMES = NO + +# If the JAVADOC_AUTOBRIEF tag is set to YES then doxygen will interpret the +# first line (until the first dot) of a Javadoc-style comment as the brief +# description. If set to NO, the Javadoc-style will behave just like regular Qt- +# style comments (thus requiring an explicit @brief command for a brief +# description.) +# The default value is: NO. + +JAVADOC_AUTOBRIEF = NO + +# If the QT_AUTOBRIEF tag is set to YES then doxygen will interpret the first +# line (until the first dot) of a Qt-style comment as the brief description. If +# set to NO, the Qt-style will behave just like regular Qt-style comments (thus +# requiring an explicit \brief command for a brief description.) +# The default value is: NO. + +QT_AUTOBRIEF = NO + +# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make doxygen treat a +# multi-line C++ special comment block (i.e. a block of //! or /// comments) as +# a brief description. This used to be the default behavior. The new default is +# to treat a multi-line C++ comment block as a detailed description. Set this +# tag to YES if you prefer the old behavior instead. +# +# Note that setting this tag to YES also means that rational rose comments are +# not recognized any more. +# The default value is: NO. + +MULTILINE_CPP_IS_BRIEF = NO + +# If the INHERIT_DOCS tag is set to YES then an undocumented member inherits the +# documentation from any documented member that it re-implements. +# The default value is: YES. + +INHERIT_DOCS = YES + +# If the SEPARATE_MEMBER_PAGES tag is set to YES then doxygen will produce a new +# page for each member. If set to NO, the documentation of a member will be part +# of the file/class/namespace that contains it. +# The default value is: NO. + +SEPARATE_MEMBER_PAGES = NO + +# The TAB_SIZE tag can be used to set the number of spaces in a tab. Doxygen +# uses this value to replace tabs by spaces in code fragments. +# Minimum value: 1, maximum value: 16, default value: 4. + +TAB_SIZE = 8 + +# This tag can be used to specify a number of aliases that act as commands in +# the documentation. An alias has the form: +# name=value +# For example adding +# "sideeffect=@par Side Effects:\n" +# will allow you to put the command \sideeffect (or @sideeffect) in the +# documentation, which will result in a user-defined paragraph with heading +# "Side Effects:". You can put \n's in the value part of an alias to insert +# newlines. + +ALIASES = + +# This tag can be used to specify a number of word-keyword mappings (TCL only). +# A mapping has the form "name=value". For example adding "class=itcl::class" +# will allow you to use the command class in the itcl::class meaning. + +TCL_SUBST = + +# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C sources +# only. Doxygen will then generate output that is more tailored for C. For +# instance, some of the names that are used will be different. The list of all +# members will be omitted, etc. +# The default value is: NO. + +OPTIMIZE_OUTPUT_FOR_C = YES + +# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java or +# Python sources only. Doxygen will then generate output that is more tailored +# for that language. For instance, namespaces will be presented as packages, +# qualified scopes will look different, etc. +# The default value is: NO. + +OPTIMIZE_OUTPUT_JAVA = NO + +# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran +# sources. Doxygen will then generate output that is tailored for Fortran. +# The default value is: NO. + +OPTIMIZE_FOR_FORTRAN = NO + +# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL +# sources. Doxygen will then generate output that is tailored for VHDL. +# The default value is: NO. + +OPTIMIZE_OUTPUT_VHDL = NO + +# Doxygen selects the parser to use depending on the extension of the files it +# parses. With this tag you can assign which parser to use for a given +# extension. Doxygen has a built-in mapping, but you can override or extend it +# using this tag. The format is ext=language, where ext is a file extension, and +# language is one of the parsers supported by doxygen: IDL, Java, Javascript, +# C#, C, C++, D, PHP, Objective-C, Python, Fortran (fixed format Fortran: +# FortranFixed, free formatted Fortran: FortranFree, unknown formatted Fortran: +# Fortran. In the later case the parser tries to guess whether the code is fixed +# or free formatted code, this is the default for Fortran type files), VHDL. For +# instance to make doxygen treat .inc files as Fortran files (default is PHP), +# and .f files as C (default is Fortran), use: inc=Fortran f=C. +# +# Note: For files without extension you can use no_extension as a placeholder. +# +# Note that for custom extensions you also need to set FILE_PATTERNS otherwise +# the files are not read by doxygen. + +EXTENSION_MAPPING = + +# If the MARKDOWN_SUPPORT tag is enabled then doxygen pre-processes all comments +# according to the Markdown format, which allows for more readable +# documentation. See http://daringfireball.net/projects/markdown/ for details. +# The output of markdown processing is further processed by doxygen, so you can +# mix doxygen, HTML, and XML commands with Markdown formatting. Disable only in +# case of backward compatibilities issues. +# The default value is: YES. + +MARKDOWN_SUPPORT = YES + +# When enabled doxygen tries to link words that correspond to documented +# classes, or namespaces to their corresponding documentation. Such a link can +# be prevented in individual cases by putting a % sign in front of the word or +# globally by setting AUTOLINK_SUPPORT to NO. +# The default value is: YES. + +AUTOLINK_SUPPORT = YES + +# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want +# to include (a tag file for) the STL sources as input, then you should set this +# tag to YES in order to let doxygen match functions declarations and +# definitions whose arguments contain STL classes (e.g. func(std::string); +# versus func(std::string) {}). This also make the inheritance and collaboration +# diagrams that involve STL classes more complete and accurate. +# The default value is: NO. + +BUILTIN_STL_SUPPORT = NO + +# If you use Microsoft's C++/CLI language, you should set this option to YES to +# enable parsing support. +# The default value is: NO. + +CPP_CLI_SUPPORT = NO + +# Set the SIP_SUPPORT tag to YES if your project consists of sip (see: +# http://www.riverbankcomputing.co.uk/software/sip/intro) sources only. Doxygen +# will parse them like normal C++ but will assume all classes use public instead +# of private inheritance when no explicit protection keyword is present. +# The default value is: NO. + +SIP_SUPPORT = NO + +# For Microsoft's IDL there are propget and propput attributes to indicate +# getter and setter methods for a property. Setting this option to YES will make +# doxygen to replace the get and set methods by a property in the documentation. +# This will only work if the methods are indeed getting or setting a simple +# type. If this is not the case, or you want to show the methods anyway, you +# should set this option to NO. +# The default value is: YES. + +IDL_PROPERTY_SUPPORT = YES + +# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC +# tag is set to YES then doxygen will reuse the documentation of the first +# member in the group (if any) for the other members of the group. By default +# all members of a group must be documented explicitly. +# The default value is: NO. + +DISTRIBUTE_GROUP_DOC = NO + +# If one adds a struct or class to a group and this option is enabled, then also +# any nested class or struct is added to the same group. By default this option +# is disabled and one has to add nested compounds explicitly via \ingroup. +# The default value is: NO. + +GROUP_NESTED_COMPOUNDS = NO + +# Set the SUBGROUPING tag to YES to allow class member groups of the same type +# (for instance a group of public functions) to be put as a subgroup of that +# type (e.g. under the Public Functions section). Set it to NO to prevent +# subgrouping. Alternatively, this can be done per class using the +# \nosubgrouping command. +# The default value is: YES. + +SUBGROUPING = YES + +# When the INLINE_GROUPED_CLASSES tag is set to YES, classes, structs and unions +# are shown inside the group in which they are included (e.g. using \ingroup) +# instead of on a separate page (for HTML and Man pages) or section (for LaTeX +# and RTF). +# +# Note that this feature does not work in combination with +# SEPARATE_MEMBER_PAGES. +# The default value is: NO. + +INLINE_GROUPED_CLASSES = NO + +# When the INLINE_SIMPLE_STRUCTS tag is set to YES, structs, classes, and unions +# with only public data fields or simple typedef fields will be shown inline in +# the documentation of the scope in which they are defined (i.e. file, +# namespace, or group documentation), provided this scope is documented. If set +# to NO, structs, classes, and unions are shown on a separate page (for HTML and +# Man pages) or section (for LaTeX and RTF). +# The default value is: NO. + +INLINE_SIMPLE_STRUCTS = NO + +# When TYPEDEF_HIDES_STRUCT tag is enabled, a typedef of a struct, union, or +# enum is documented as struct, union, or enum with the name of the typedef. So +# typedef struct TypeS {} TypeT, will appear in the documentation as a struct +# with name TypeT. When disabled the typedef will appear as a member of a file, +# namespace, or class. And the struct will be named TypeS. This can typically be +# useful for C code in case the coding convention dictates that all compound +# types are typedef'ed and only the typedef is referenced, never the tag name. +# The default value is: NO. + +TYPEDEF_HIDES_STRUCT = NO + +# The size of the symbol lookup cache can be set using LOOKUP_CACHE_SIZE. This +# cache is used to resolve symbols given their name and scope. Since this can be +# an expensive process and often the same symbol appears multiple times in the +# code, doxygen keeps a cache of pre-resolved symbols. If the cache is too small +# doxygen will become slower. If the cache is too large, memory is wasted. The +# cache size is given by this formula: 2^(16+LOOKUP_CACHE_SIZE). The valid range +# is 0..9, the default is 0, corresponding to a cache size of 2^16=65536 +# symbols. At the end of a run doxygen will report the cache usage and suggest +# the optimal cache size from a speed point of view. +# Minimum value: 0, maximum value: 9, default value: 0. + +LOOKUP_CACHE_SIZE = 0 + +#--------------------------------------------------------------------------- +# Build related configuration options +#--------------------------------------------------------------------------- + +# If the EXTRACT_ALL tag is set to YES, doxygen will assume all entities in +# documentation are documented, even if no documentation was available. Private +# class members and static file members will be hidden unless the +# EXTRACT_PRIVATE respectively EXTRACT_STATIC tags are set to YES. +# Note: This will also disable the warnings about undocumented members that are +# normally produced when WARNINGS is set to YES. +# The default value is: NO. + +EXTRACT_ALL = NO + +# If the EXTRACT_PRIVATE tag is set to YES, all private members of a class will +# be included in the documentation. +# The default value is: NO. + +EXTRACT_PRIVATE = NO + +# If the EXTRACT_PACKAGE tag is set to YES, all members with package or internal +# scope will be included in the documentation. +# The default value is: NO. + +EXTRACT_PACKAGE = NO + +# If the EXTRACT_STATIC tag is set to YES, all static members of a file will be +# included in the documentation. +# The default value is: NO. + +EXTRACT_STATIC = NO + +# If the EXTRACT_LOCAL_CLASSES tag is set to YES, classes (and structs) defined +# locally in source files will be included in the documentation. If set to NO, +# only classes defined in header files are included. Does not have any effect +# for Java sources. +# The default value is: YES. + +EXTRACT_LOCAL_CLASSES = YES + +# This flag is only useful for Objective-C code. If set to YES, local methods, +# which are defined in the implementation section but not in the interface are +# included in the documentation. If set to NO, only methods in the interface are +# included. +# The default value is: NO. + +EXTRACT_LOCAL_METHODS = NO + +# If this flag is set to YES, the members of anonymous namespaces will be +# extracted and appear in the documentation as a namespace called +# 'anonymous_namespace{file}', where file will be replaced with the base name of +# the file that contains the anonymous namespace. By default anonymous namespace +# are hidden. +# The default value is: NO. + +EXTRACT_ANON_NSPACES = NO + +# If the HIDE_UNDOC_MEMBERS tag is set to YES, doxygen will hide all +# undocumented members inside documented classes or files. If set to NO these +# members will be included in the various overviews, but no documentation +# section is generated. This option has no effect if EXTRACT_ALL is enabled. +# The default value is: NO. + +HIDE_UNDOC_MEMBERS = YES + +# If the HIDE_UNDOC_CLASSES tag is set to YES, doxygen will hide all +# undocumented classes that are normally visible in the class hierarchy. If set +# to NO, these classes will be included in the various overviews. This option +# has no effect if EXTRACT_ALL is enabled. +# The default value is: NO. + +HIDE_UNDOC_CLASSES = YES + +# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, doxygen will hide all friend +# (class|struct|union) declarations. If set to NO, these declarations will be +# included in the documentation. +# The default value is: NO. + +HIDE_FRIEND_COMPOUNDS = NO + +# If the HIDE_IN_BODY_DOCS tag is set to YES, doxygen will hide any +# documentation blocks found inside the body of a function. If set to NO, these +# blocks will be appended to the function's detailed documentation block. +# The default value is: NO. + +HIDE_IN_BODY_DOCS = NO + +# The INTERNAL_DOCS tag determines if documentation that is typed after a +# \internal command is included. If the tag is set to NO then the documentation +# will be excluded. Set it to YES to include the internal documentation. +# The default value is: NO. + +INTERNAL_DOCS = NO + +# If the CASE_SENSE_NAMES tag is set to NO then doxygen will only generate file +# names in lower-case letters. If set to YES, upper-case letters are also +# allowed. This is useful if you have classes or files whose names only differ +# in case and if your file system supports case sensitive file names. Windows +# and Mac users are advised to set this option to NO. +# The default value is: system dependent. + +CASE_SENSE_NAMES = NO + +# If the HIDE_SCOPE_NAMES tag is set to NO then doxygen will show members with +# their full class and namespace scopes in the documentation. If set to YES, the +# scope will be hidden. +# The default value is: NO. + +HIDE_SCOPE_NAMES = NO + +# If the HIDE_COMPOUND_REFERENCE tag is set to NO (default) then doxygen will +# append additional text to a page's title, such as Class Reference. If set to +# YES the compound reference will be hidden. +# The default value is: NO. + +HIDE_COMPOUND_REFERENCE= NO + +# If the SHOW_INCLUDE_FILES tag is set to YES then doxygen will put a list of +# the files that are included by a file in the documentation of that file. +# The default value is: YES. + +SHOW_INCLUDE_FILES = YES + +# If the SHOW_GROUPED_MEMB_INC tag is set to YES then Doxygen will add for each +# grouped member an include statement to the documentation, telling the reader +# which file to include in order to use the member. +# The default value is: NO. + +SHOW_GROUPED_MEMB_INC = NO + +# If the FORCE_LOCAL_INCLUDES tag is set to YES then doxygen will list include +# files with double quotes in the documentation rather than with sharp brackets. +# The default value is: NO. + +FORCE_LOCAL_INCLUDES = NO + +# If the INLINE_INFO tag is set to YES then a tag [inline] is inserted in the +# documentation for inline members. +# The default value is: YES. + +INLINE_INFO = YES + +# If the SORT_MEMBER_DOCS tag is set to YES then doxygen will sort the +# (detailed) documentation of file and class members alphabetically by member +# name. If set to NO, the members will appear in declaration order. +# The default value is: YES. + +SORT_MEMBER_DOCS = YES + +# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the brief +# descriptions of file, namespace and class members alphabetically by member +# name. If set to NO, the members will appear in declaration order. Note that +# this will also influence the order of the classes in the class list. +# The default value is: NO. + +SORT_BRIEF_DOCS = NO + +# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen will sort the +# (brief and detailed) documentation of class members so that constructors and +# destructors are listed first. If set to NO the constructors will appear in the +# respective orders defined by SORT_BRIEF_DOCS and SORT_MEMBER_DOCS. +# Note: If SORT_BRIEF_DOCS is set to NO this option is ignored for sorting brief +# member documentation. +# Note: If SORT_MEMBER_DOCS is set to NO this option is ignored for sorting +# detailed member documentation. +# The default value is: NO. + +SORT_MEMBERS_CTORS_1ST = NO + +# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the hierarchy +# of group names into alphabetical order. If set to NO the group names will +# appear in their defined order. +# The default value is: NO. + +SORT_GROUP_NAMES = NO + +# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be sorted by +# fully-qualified names, including namespaces. If set to NO, the class list will +# be sorted only by class name, not including the namespace part. +# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. +# Note: This option applies only to the class list, not to the alphabetical +# list. +# The default value is: NO. + +SORT_BY_SCOPE_NAME = NO + +# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to do proper +# type resolution of all parameters of a function it will reject a match between +# the prototype and the implementation of a member function even if there is +# only one candidate or it is obvious which candidate to choose by doing a +# simple string match. By disabling STRICT_PROTO_MATCHING doxygen will still +# accept a match between prototype and implementation in such cases. +# The default value is: NO. + +STRICT_PROTO_MATCHING = NO + +# The GENERATE_TODOLIST tag can be used to enable (YES) or disable (NO) the todo +# list. This list is created by putting \todo commands in the documentation. +# The default value is: YES. + +GENERATE_TODOLIST = NO + +# The GENERATE_TESTLIST tag can be used to enable (YES) or disable (NO) the test +# list. This list is created by putting \test commands in the documentation. +# The default value is: YES. + +GENERATE_TESTLIST = YES + +# The GENERATE_BUGLIST tag can be used to enable (YES) or disable (NO) the bug +# list. This list is created by putting \bug commands in the documentation. +# The default value is: YES. + +GENERATE_BUGLIST = YES + +# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or disable (NO) +# the deprecated list. This list is created by putting \deprecated commands in +# the documentation. +# The default value is: YES. + +GENERATE_DEPRECATEDLIST= YES + +# The ENABLED_SECTIONS tag can be used to enable conditional documentation +# sections, marked by \if ... \endif and \cond +# ... \endcond blocks. + +ENABLED_SECTIONS = + +# The MAX_INITIALIZER_LINES tag determines the maximum number of lines that the +# initial value of a variable or macro / define can have for it to appear in the +# documentation. If the initializer consists of more lines than specified here +# it will be hidden. Use a value of 0 to hide initializers completely. The +# appearance of the value of individual variables and macros / defines can be +# controlled using \showinitializer or \hideinitializer command in the +# documentation regardless of this setting. +# Minimum value: 0, maximum value: 10000, default value: 30. + +MAX_INITIALIZER_LINES = 30 + +# Set the SHOW_USED_FILES tag to NO to disable the list of files generated at +# the bottom of the documentation of classes and structs. If set to YES, the +# list will mention the files that were used to generate the documentation. +# The default value is: YES. + +SHOW_USED_FILES = YES + +# Set the SHOW_FILES tag to NO to disable the generation of the Files page. This +# will remove the Files entry from the Quick Index and from the Folder Tree View +# (if specified). +# The default value is: YES. + +SHOW_FILES = YES + +# Set the SHOW_NAMESPACES tag to NO to disable the generation of the Namespaces +# page. This will remove the Namespaces entry from the Quick Index and from the +# Folder Tree View (if specified). +# The default value is: YES. + +SHOW_NAMESPACES = YES + +# The FILE_VERSION_FILTER tag can be used to specify a program or script that +# doxygen should invoke to get the current version for each file (typically from +# the version control system). Doxygen will invoke the program by executing (via +# popen()) the command command input-file, where command is the value of the +# FILE_VERSION_FILTER tag, and input-file is the name of an input file provided +# by doxygen. Whatever the program writes to standard output is used as the file +# version. For an example see the documentation. + +FILE_VERSION_FILTER = + +# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed +# by doxygen. The layout file controls the global structure of the generated +# output files in an output format independent way. To create the layout file +# that represents doxygen's defaults, run doxygen with the -l option. You can +# optionally specify a file name after the option, if omitted DoxygenLayout.xml +# will be used as the name of the layout file. +# +# Note that if you run doxygen from a directory containing a file called +# DoxygenLayout.xml, doxygen will parse it automatically even if the LAYOUT_FILE +# tag is left empty. + +LAYOUT_FILE = + +# The CITE_BIB_FILES tag can be used to specify one or more bib files containing +# the reference definitions. This must be a list of .bib files. The .bib +# extension is automatically appended if omitted. This requires the bibtex tool +# to be installed. See also http://en.wikipedia.org/wiki/BibTeX for more info. +# For LaTeX the style of the bibliography can be controlled using +# LATEX_BIB_STYLE. To use this feature you need bibtex and perl available in the +# search path. See also \cite for info how to create references. + +CITE_BIB_FILES = + +#--------------------------------------------------------------------------- +# Configuration options related to warning and progress messages +#--------------------------------------------------------------------------- + +# The QUIET tag can be used to turn on/off the messages that are generated to +# standard output by doxygen. If QUIET is set to YES this implies that the +# messages are off. +# The default value is: NO. + +QUIET = NO + +# The WARNINGS tag can be used to turn on/off the warning messages that are +# generated to standard error (stderr) by doxygen. If WARNINGS is set to YES +# this implies that the warnings are on. +# +# Tip: Turn warnings on while writing the documentation. +# The default value is: YES. + +WARNINGS = YES + +# If the WARN_IF_UNDOCUMENTED tag is set to YES then doxygen will generate +# warnings for undocumented members. If EXTRACT_ALL is set to YES then this flag +# will automatically be disabled. +# The default value is: YES. + +WARN_IF_UNDOCUMENTED = YES + +# If the WARN_IF_DOC_ERROR tag is set to YES, doxygen will generate warnings for +# potential errors in the documentation, such as not documenting some parameters +# in a documented function, or documenting parameters that don't exist or using +# markup commands wrongly. +# The default value is: YES. + +WARN_IF_DOC_ERROR = YES + +# This WARN_NO_PARAMDOC option can be enabled to get warnings for functions that +# are documented, but have no documentation for their parameters or return +# value. If set to NO, doxygen will only warn about wrong or incomplete +# parameter documentation, but not about the absence of documentation. +# The default value is: NO. + +WARN_NO_PARAMDOC = NO + +# If the WARN_AS_ERROR tag is set to YES then doxygen will immediately stop when +# a warning is encountered. +# The default value is: NO. + +WARN_AS_ERROR = NO + +# The WARN_FORMAT tag determines the format of the warning messages that doxygen +# can produce. The string should contain the $file, $line, and $text tags, which +# will be replaced by the file and line number from which the warning originated +# and the warning text. Optionally the format may contain $version, which will +# be replaced by the version of the file (if it could be obtained via +# FILE_VERSION_FILTER) +# The default value is: $file:$line: $text. + +WARN_FORMAT = "$file:$line: $text " + +# The WARN_LOGFILE tag can be used to specify a file to which warning and error +# messages should be written. If left blank the output is written to standard +# error (stderr). + +WARN_LOGFILE = + +#--------------------------------------------------------------------------- +# Configuration options related to the input files +#--------------------------------------------------------------------------- + +# The INPUT tag is used to specify the files and/or directories that contain +# documented source files. You may enter file names like myfile.cpp or +# directories like /usr/src/myproject. Separate the files or directories with +# spaces. See also FILE_PATTERNS and EXTENSION_MAPPING +# Note: If this tag is empty the current directory is searched. + +INPUT = main_page.h ../../src + +# This tag can be used to specify the character encoding of the source files +# that doxygen parses. Internally doxygen uses the UTF-8 encoding. Doxygen uses +# libiconv (or the iconv built into libc) for the transcoding. See the libiconv +# documentation (see: http://www.gnu.org/software/libiconv) for the list of +# possible encodings. +# The default value is: UTF-8. + +INPUT_ENCODING = UTF-8 + +# If the value of the INPUT tag contains directories, you can use the +# FILE_PATTERNS tag to specify one or more wildcard patterns (like *.cpp and +# *.h) to filter out the source-files in the directories. +# +# Note that for custom extensions or not directly supported extensions you also +# need to set EXTENSION_MAPPING for the extension otherwise the files are not +# read by doxygen. +# +# If left blank the following patterns are tested:*.c, *.cc, *.cxx, *.cpp, +# *.c++, *.java, *.ii, *.ixx, *.ipp, *.i++, *.inl, *.idl, *.ddl, *.odl, *.h, +# *.hh, *.hxx, *.hpp, *.h++, *.cs, *.d, *.php, *.php4, *.php5, *.phtml, *.inc, +# *.m, *.markdown, *.md, *.mm, *.dox, *.py, *.pyw, *.f90, *.f, *.for, *.tcl, +# *.vhd, *.vhdl, *.ucf, *.qsf, *.as and *.js. + +FILE_PATTERNS = *.c \ + *.cc \ + *.cxx \ + *.cpp \ + *.c++ \ + *.java \ + *.ii \ + *.ixx \ + *.ipp \ + *.i++ \ + *.inl \ + *.h \ + *.hh \ + *.hxx \ + *.hpp \ + *.h++ \ + *.idl \ + *.odl \ + *.inc \ + *.m \ + *.mm \ + *.dox + +# The RECURSIVE tag can be used to specify whether or not subdirectories should +# be searched for input files as well. +# The default value is: NO. + +RECURSIVE = YES + +# The EXCLUDE tag can be used to specify files and/or directories that should be +# excluded from the INPUT source files. This way you can easily exclude a +# subdirectory from a directory tree whose root is specified with the INPUT tag. +# +# Note that relative paths are relative to the directory from which doxygen is +# run. + +EXCLUDE = ../../src/include/netif/ppp/polarssl + +# The EXCLUDE_SYMLINKS tag can be used to select whether or not files or +# directories that are symbolic links (a Unix file system feature) are excluded +# from the input. +# The default value is: NO. + +EXCLUDE_SYMLINKS = NO + +# If the value of the INPUT tag contains directories, you can use the +# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude +# certain files from those directories. +# +# Note that the wildcards are matched against the file with absolute path, so to +# exclude all test directories for example use the pattern */test/* + +EXCLUDE_PATTERNS = + +# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names +# (namespaces, classes, functions, etc.) that should be excluded from the +# output. The symbol name can be a fully qualified name, a word, or if the +# wildcard * is used, a substring. Examples: ANamespace, AClass, +# AClass::ANamespace, ANamespace::*Test +# +# Note that the wildcards are matched against the file with absolute path, so to +# exclude all test directories use the pattern */test/* + +EXCLUDE_SYMBOLS = + +# The EXAMPLE_PATH tag can be used to specify one or more files or directories +# that contain example code fragments that are included (see the \include +# command). + +EXAMPLE_PATH = ../ ../../ + +# If the value of the EXAMPLE_PATH tag contains directories, you can use the +# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp and +# *.h) to filter out the source-files in the directories. If left blank all +# files are included. + +EXAMPLE_PATTERNS = * + +# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be +# searched for input files to be used with the \include or \dontinclude commands +# irrespective of the value of the RECURSIVE tag. +# The default value is: NO. + +EXAMPLE_RECURSIVE = NO + +# The IMAGE_PATH tag can be used to specify one or more files or directories +# that contain images that are to be included in the documentation (see the +# \image command). + +IMAGE_PATH = + +# The INPUT_FILTER tag can be used to specify a program that doxygen should +# invoke to filter for each input file. Doxygen will invoke the filter program +# by executing (via popen()) the command: +# +# +# +# where is the value of the INPUT_FILTER tag, and is the +# name of an input file. Doxygen will then use the output that the filter +# program writes to standard output. If FILTER_PATTERNS is specified, this tag +# will be ignored. +# +# Note that the filter must not add or remove lines; it is applied before the +# code is scanned, but not when the output code is generated. If lines are added +# or removed, the anchors will not be placed correctly. +# +# Note that for custom extensions or not directly supported extensions you also +# need to set EXTENSION_MAPPING for the extension otherwise the files are not +# properly processed by doxygen. + +INPUT_FILTER = + +# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern +# basis. Doxygen will compare the file name with each pattern and apply the +# filter if there is a match. The filters are a list of the form: pattern=filter +# (like *.cpp=my_cpp_filter). See INPUT_FILTER for further information on how +# filters are used. If the FILTER_PATTERNS tag is empty or if none of the +# patterns match the file name, INPUT_FILTER is applied. +# +# Note that for custom extensions or not directly supported extensions you also +# need to set EXTENSION_MAPPING for the extension otherwise the files are not +# properly processed by doxygen. + +FILTER_PATTERNS = + +# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using +# INPUT_FILTER) will also be used to filter the input files that are used for +# producing the source files to browse (i.e. when SOURCE_BROWSER is set to YES). +# The default value is: NO. + +FILTER_SOURCE_FILES = NO + +# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file +# pattern. A pattern will override the setting for FILTER_PATTERN (if any) and +# it is also possible to disable source filtering for a specific pattern using +# *.ext= (so without naming a filter). +# This tag requires that the tag FILTER_SOURCE_FILES is set to YES. + +FILTER_SOURCE_PATTERNS = + +# If the USE_MDFILE_AS_MAINPAGE tag refers to the name of a markdown file that +# is part of the input, its contents will be placed on the main page +# (index.html). This can be useful if you have a project on for instance GitHub +# and want to reuse the introduction page also for the doxygen output. + +USE_MDFILE_AS_MAINPAGE = main_page.h + +#--------------------------------------------------------------------------- +# Configuration options related to source browsing +#--------------------------------------------------------------------------- + +# If the SOURCE_BROWSER tag is set to YES then a list of source files will be +# generated. Documented entities will be cross-referenced with these sources. +# +# Note: To get rid of all source code in the generated output, make sure that +# also VERBATIM_HEADERS is set to NO. +# The default value is: NO. + +SOURCE_BROWSER = NO + +# Setting the INLINE_SOURCES tag to YES will include the body of functions, +# classes and enums directly into the documentation. +# The default value is: NO. + +INLINE_SOURCES = NO + +# Setting the STRIP_CODE_COMMENTS tag to YES will instruct doxygen to hide any +# special comment blocks from generated source code fragments. Normal C, C++ and +# Fortran comments will always remain visible. +# The default value is: YES. + +STRIP_CODE_COMMENTS = YES + +# If the REFERENCED_BY_RELATION tag is set to YES then for each documented +# function all documented functions referencing it will be listed. +# The default value is: NO. + +REFERENCED_BY_RELATION = NO + +# If the REFERENCES_RELATION tag is set to YES then for each documented function +# all documented entities called/used by that function will be listed. +# The default value is: NO. + +REFERENCES_RELATION = NO + +# If the REFERENCES_LINK_SOURCE tag is set to YES and SOURCE_BROWSER tag is set +# to YES then the hyperlinks from functions in REFERENCES_RELATION and +# REFERENCED_BY_RELATION lists will link to the source code. Otherwise they will +# link to the documentation. +# The default value is: YES. + +REFERENCES_LINK_SOURCE = YES + +# If SOURCE_TOOLTIPS is enabled (the default) then hovering a hyperlink in the +# source code will show a tooltip with additional information such as prototype, +# brief description and links to the definition and documentation. Since this +# will make the HTML file larger and loading of large files a bit slower, you +# can opt to disable this feature. +# The default value is: YES. +# This tag requires that the tag SOURCE_BROWSER is set to YES. + +SOURCE_TOOLTIPS = YES + +# If the USE_HTAGS tag is set to YES then the references to source code will +# point to the HTML generated by the htags(1) tool instead of doxygen built-in +# source browser. The htags tool is part of GNU's global source tagging system +# (see http://www.gnu.org/software/global/global.html). You will need version +# 4.8.6 or higher. +# +# To use it do the following: +# - Install the latest version of global +# - Enable SOURCE_BROWSER and USE_HTAGS in the config file +# - Make sure the INPUT points to the root of the source tree +# - Run doxygen as normal +# +# Doxygen will invoke htags (and that will in turn invoke gtags), so these +# tools must be available from the command line (i.e. in the search path). +# +# The result: instead of the source browser generated by doxygen, the links to +# source code will now point to the output of htags. +# The default value is: NO. +# This tag requires that the tag SOURCE_BROWSER is set to YES. + +USE_HTAGS = NO + +# If the VERBATIM_HEADERS tag is set the YES then doxygen will generate a +# verbatim copy of the header file for each class for which an include is +# specified. Set to NO to disable this. +# See also: Section \class. +# The default value is: YES. + +VERBATIM_HEADERS = NO + +# If the CLANG_ASSISTED_PARSING tag is set to YES then doxygen will use the +# clang parser (see: http://clang.llvm.org/) for more accurate parsing at the +# cost of reduced performance. This can be particularly helpful with template +# rich C++ code for which doxygen's built-in parser lacks the necessary type +# information. +# Note: The availability of this option depends on whether or not doxygen was +# generated with the -Duse-libclang=ON option for CMake. +# The default value is: NO. + +CLANG_ASSISTED_PARSING = NO + +# If clang assisted parsing is enabled you can provide the compiler with command +# line options that you would normally use when invoking the compiler. Note that +# the include paths will already be set by doxygen for the files and directories +# specified with INPUT and INCLUDE_PATH. +# This tag requires that the tag CLANG_ASSISTED_PARSING is set to YES. + +CLANG_OPTIONS = + +#--------------------------------------------------------------------------- +# Configuration options related to the alphabetical class index +#--------------------------------------------------------------------------- + +# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index of all +# compounds will be generated. Enable this if the project contains a lot of +# classes, structs, unions or interfaces. +# The default value is: YES. + +ALPHABETICAL_INDEX = NO + +# The COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns in +# which the alphabetical index list will be split. +# Minimum value: 1, maximum value: 20, default value: 5. +# This tag requires that the tag ALPHABETICAL_INDEX is set to YES. + +COLS_IN_ALPHA_INDEX = 5 + +# In case all classes in a project start with a common prefix, all classes will +# be put under the same header in the alphabetical index. The IGNORE_PREFIX tag +# can be used to specify a prefix (or a list of prefixes) that should be ignored +# while generating the index headers. +# This tag requires that the tag ALPHABETICAL_INDEX is set to YES. + +IGNORE_PREFIX = + +#--------------------------------------------------------------------------- +# Configuration options related to the HTML output +#--------------------------------------------------------------------------- + +# If the GENERATE_HTML tag is set to YES, doxygen will generate HTML output +# The default value is: YES. + +GENERATE_HTML = YES + +# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. If a +# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of +# it. +# The default directory is: html. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_OUTPUT = html + +# The HTML_FILE_EXTENSION tag can be used to specify the file extension for each +# generated HTML page (for example: .htm, .php, .asp). +# The default value is: .html. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_FILE_EXTENSION = .html + +# The HTML_HEADER tag can be used to specify a user-defined HTML header file for +# each generated HTML page. If the tag is left blank doxygen will generate a +# standard header. +# +# To get valid HTML the header file that includes any scripts and style sheets +# that doxygen needs, which is dependent on the configuration options used (e.g. +# the setting GENERATE_TREEVIEW). It is highly recommended to start with a +# default header using +# doxygen -w html new_header.html new_footer.html new_stylesheet.css +# YourConfigFile +# and then modify the file new_header.html. See also section "Doxygen usage" +# for information on how to generate the default header that doxygen normally +# uses. +# Note: The header is subject to change so you typically have to regenerate the +# default header when upgrading to a newer version of doxygen. For a description +# of the possible markers and block names see the documentation. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_HEADER = + +# The HTML_FOOTER tag can be used to specify a user-defined HTML footer for each +# generated HTML page. If the tag is left blank doxygen will generate a standard +# footer. See HTML_HEADER for more information on how to generate a default +# footer and what special commands can be used inside the footer. See also +# section "Doxygen usage" for information on how to generate the default footer +# that doxygen normally uses. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_FOOTER = + +# The HTML_STYLESHEET tag can be used to specify a user-defined cascading style +# sheet that is used by each HTML page. It can be used to fine-tune the look of +# the HTML output. If left blank doxygen will generate a default style sheet. +# See also section "Doxygen usage" for information on how to generate the style +# sheet that doxygen normally uses. +# Note: It is recommended to use HTML_EXTRA_STYLESHEET instead of this tag, as +# it is more robust and this tag (HTML_STYLESHEET) will in the future become +# obsolete. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_STYLESHEET = + +# The HTML_EXTRA_STYLESHEET tag can be used to specify additional user-defined +# cascading style sheets that are included after the standard style sheets +# created by doxygen. Using this option one can overrule certain style aspects. +# This is preferred over using HTML_STYLESHEET since it does not replace the +# standard style sheet and is therefore more robust against future updates. +# Doxygen will copy the style sheet files to the output directory. +# Note: The order of the extra style sheet files is of importance (e.g. the last +# style sheet in the list overrules the setting of the previous ones in the +# list). For an example see the documentation. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_EXTRA_STYLESHEET = + +# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or +# other source files which should be copied to the HTML output directory. Note +# that these files will be copied to the base HTML output directory. Use the +# $relpath^ marker in the HTML_HEADER and/or HTML_FOOTER files to load these +# files. In the HTML_STYLESHEET file, use the file name only. Also note that the +# files will be copied as-is; there are no commands or markers available. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_EXTRA_FILES = + +# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. Doxygen +# will adjust the colors in the style sheet and background images according to +# this color. Hue is specified as an angle on a colorwheel, see +# http://en.wikipedia.org/wiki/Hue for more information. For instance the value +# 0 represents red, 60 is yellow, 120 is green, 180 is cyan, 240 is blue, 300 +# purple, and 360 is red again. +# Minimum value: 0, maximum value: 359, default value: 220. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_COLORSTYLE_HUE = 220 + +# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of the colors +# in the HTML output. For a value of 0 the output will use grayscales only. A +# value of 255 will produce the most vivid colors. +# Minimum value: 0, maximum value: 255, default value: 100. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_COLORSTYLE_SAT = 100 + +# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to the +# luminance component of the colors in the HTML output. Values below 100 +# gradually make the output lighter, whereas values above 100 make the output +# darker. The value divided by 100 is the actual gamma applied, so 80 represents +# a gamma of 0.8, The value 220 represents a gamma of 2.2, and 100 does not +# change the gamma. +# Minimum value: 40, maximum value: 240, default value: 80. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_COLORSTYLE_GAMMA = 80 + +# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML +# page will contain the date and time when the page was generated. Setting this +# to YES can help to show when doxygen was last run and thus if the +# documentation is up to date. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_TIMESTAMP = NO + +# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML +# documentation will contain sections that can be hidden and shown after the +# page has loaded. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_DYNAMIC_SECTIONS = NO + +# With HTML_INDEX_NUM_ENTRIES one can control the preferred number of entries +# shown in the various tree structured indices initially; the user can expand +# and collapse entries dynamically later on. Doxygen will expand the tree to +# such a level that at most the specified number of entries are visible (unless +# a fully collapsed tree already exceeds this amount). So setting the number of +# entries 1 will produce a full collapsed tree by default. 0 is a special value +# representing an infinite number of entries and will result in a full expanded +# tree by default. +# Minimum value: 0, maximum value: 9999, default value: 100. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_INDEX_NUM_ENTRIES = 100 + +# If the GENERATE_DOCSET tag is set to YES, additional index files will be +# generated that can be used as input for Apple's Xcode 3 integrated development +# environment (see: http://developer.apple.com/tools/xcode/), introduced with +# OSX 10.5 (Leopard). To create a documentation set, doxygen will generate a +# Makefile in the HTML output directory. Running make will produce the docset in +# that directory and running make install will install the docset in +# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find it at +# startup. See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html +# for more information. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +GENERATE_DOCSET = NO + +# This tag determines the name of the docset feed. A documentation feed provides +# an umbrella under which multiple documentation sets from a single provider +# (such as a company or product suite) can be grouped. +# The default value is: Doxygen generated docs. +# This tag requires that the tag GENERATE_DOCSET is set to YES. + +DOCSET_FEEDNAME = "Doxygen generated docs" + +# This tag specifies a string that should uniquely identify the documentation +# set bundle. This should be a reverse domain-name style string, e.g. +# com.mycompany.MyDocSet. Doxygen will append .docset to the name. +# The default value is: org.doxygen.Project. +# This tag requires that the tag GENERATE_DOCSET is set to YES. + +DOCSET_BUNDLE_ID = org.doxygen.Project + +# The DOCSET_PUBLISHER_ID tag specifies a string that should uniquely identify +# the documentation publisher. This should be a reverse domain-name style +# string, e.g. com.mycompany.MyDocSet.documentation. +# The default value is: org.doxygen.Publisher. +# This tag requires that the tag GENERATE_DOCSET is set to YES. + +DOCSET_PUBLISHER_ID = org.doxygen.Publisher + +# The DOCSET_PUBLISHER_NAME tag identifies the documentation publisher. +# The default value is: Publisher. +# This tag requires that the tag GENERATE_DOCSET is set to YES. + +DOCSET_PUBLISHER_NAME = Publisher + +# If the GENERATE_HTMLHELP tag is set to YES then doxygen generates three +# additional HTML index files: index.hhp, index.hhc, and index.hhk. The +# index.hhp is a project file that can be read by Microsoft's HTML Help Workshop +# (see: http://www.microsoft.com/en-us/download/details.aspx?id=21138) on +# Windows. +# +# The HTML Help Workshop contains a compiler that can convert all HTML output +# generated by doxygen into a single compiled HTML file (.chm). Compiled HTML +# files are now used as the Windows 98 help format, and will replace the old +# Windows help format (.hlp) on all Windows platforms in the future. Compressed +# HTML files also contain an index, a table of contents, and you can search for +# words in the documentation. The HTML workshop also contains a viewer for +# compressed HTML files. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +GENERATE_HTMLHELP = NO + +# The CHM_FILE tag can be used to specify the file name of the resulting .chm +# file. You can add a path in front of the file if the result should not be +# written to the html output directory. +# This tag requires that the tag GENERATE_HTMLHELP is set to YES. + +CHM_FILE = lwip.chm + +# The HHC_LOCATION tag can be used to specify the location (absolute path +# including file name) of the HTML help compiler (hhc.exe). If non-empty, +# doxygen will try to run the HTML help compiler on the generated index.hhp. +# The file has to be specified with full path. +# This tag requires that the tag GENERATE_HTMLHELP is set to YES. + +HHC_LOCATION = + +# The GENERATE_CHI flag controls if a separate .chi index file is generated +# (YES) or that it should be included in the master .chm file (NO). +# The default value is: NO. +# This tag requires that the tag GENERATE_HTMLHELP is set to YES. + +GENERATE_CHI = NO + +# The CHM_INDEX_ENCODING is used to encode HtmlHelp index (hhk), content (hhc) +# and project file content. +# This tag requires that the tag GENERATE_HTMLHELP is set to YES. + +CHM_INDEX_ENCODING = + +# The BINARY_TOC flag controls whether a binary table of contents is generated +# (YES) or a normal table of contents (NO) in the .chm file. Furthermore it +# enables the Previous and Next buttons. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTMLHELP is set to YES. + +BINARY_TOC = NO + +# The TOC_EXPAND flag can be set to YES to add extra items for group members to +# the table of contents of the HTML help documentation and to the tree view. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTMLHELP is set to YES. + +TOC_EXPAND = NO + +# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and +# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated that +# can be used as input for Qt's qhelpgenerator to generate a Qt Compressed Help +# (.qch) of the generated HTML documentation. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +GENERATE_QHP = NO + +# If the QHG_LOCATION tag is specified, the QCH_FILE tag can be used to specify +# the file name of the resulting .qch file. The path specified is relative to +# the HTML output folder. +# This tag requires that the tag GENERATE_QHP is set to YES. + +QCH_FILE = + +# The QHP_NAMESPACE tag specifies the namespace to use when generating Qt Help +# Project output. For more information please see Qt Help Project / Namespace +# (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#namespace). +# The default value is: org.doxygen.Project. +# This tag requires that the tag GENERATE_QHP is set to YES. + +QHP_NAMESPACE = org.doxygen.Project + +# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating Qt +# Help Project output. For more information please see Qt Help Project / Virtual +# Folders (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#virtual- +# folders). +# The default value is: doc. +# This tag requires that the tag GENERATE_QHP is set to YES. + +QHP_VIRTUAL_FOLDER = doc + +# If the QHP_CUST_FILTER_NAME tag is set, it specifies the name of a custom +# filter to add. For more information please see Qt Help Project / Custom +# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom- +# filters). +# This tag requires that the tag GENERATE_QHP is set to YES. + +QHP_CUST_FILTER_NAME = + +# The QHP_CUST_FILTER_ATTRS tag specifies the list of the attributes of the +# custom filter to add. For more information please see Qt Help Project / Custom +# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom- +# filters). +# This tag requires that the tag GENERATE_QHP is set to YES. + +QHP_CUST_FILTER_ATTRS = + +# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this +# project's filter section matches. Qt Help Project / Filter Attributes (see: +# http://qt-project.org/doc/qt-4.8/qthelpproject.html#filter-attributes). +# This tag requires that the tag GENERATE_QHP is set to YES. + +QHP_SECT_FILTER_ATTRS = + +# The QHG_LOCATION tag can be used to specify the location of Qt's +# qhelpgenerator. If non-empty doxygen will try to run qhelpgenerator on the +# generated .qhp file. +# This tag requires that the tag GENERATE_QHP is set to YES. + +QHG_LOCATION = + +# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files will be +# generated, together with the HTML files, they form an Eclipse help plugin. To +# install this plugin and make it available under the help contents menu in +# Eclipse, the contents of the directory containing the HTML and XML files needs +# to be copied into the plugins directory of eclipse. The name of the directory +# within the plugins directory should be the same as the ECLIPSE_DOC_ID value. +# After copying Eclipse needs to be restarted before the help appears. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +GENERATE_ECLIPSEHELP = NO + +# A unique identifier for the Eclipse help plugin. When installing the plugin +# the directory name containing the HTML and XML files should also have this +# name. Each documentation set should have its own identifier. +# The default value is: org.doxygen.Project. +# This tag requires that the tag GENERATE_ECLIPSEHELP is set to YES. + +ECLIPSE_DOC_ID = org.doxygen.Project + +# If you want full control over the layout of the generated HTML pages it might +# be necessary to disable the index and replace it with your own. The +# DISABLE_INDEX tag can be used to turn on/off the condensed index (tabs) at top +# of each HTML page. A value of NO enables the index and the value YES disables +# it. Since the tabs in the index contain the same information as the navigation +# tree, you can set this option to YES if you also set GENERATE_TREEVIEW to YES. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +DISABLE_INDEX = NO + +# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index +# structure should be generated to display hierarchical information. If the tag +# value is set to YES, a side panel will be generated containing a tree-like +# index structure (just like the one that is generated for HTML Help). For this +# to work a browser that supports JavaScript, DHTML, CSS and frames is required +# (i.e. any modern browser). Windows users are probably better off using the +# HTML help feature. Via custom style sheets (see HTML_EXTRA_STYLESHEET) one can +# further fine-tune the look of the index. As an example, the default style +# sheet generated by doxygen has an example that shows how to put an image at +# the root of the tree instead of the PROJECT_NAME. Since the tree basically has +# the same information as the tab index, you could consider setting +# DISABLE_INDEX to YES when enabling this option. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +GENERATE_TREEVIEW = YES + +# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values that +# doxygen will group on one line in the generated HTML documentation. +# +# Note that a value of 0 will completely suppress the enum values from appearing +# in the overview section. +# Minimum value: 0, maximum value: 20, default value: 4. +# This tag requires that the tag GENERATE_HTML is set to YES. + +ENUM_VALUES_PER_LINE = 4 + +# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be used +# to set the initial width (in pixels) of the frame in which the tree is shown. +# Minimum value: 0, maximum value: 1500, default value: 250. +# This tag requires that the tag GENERATE_HTML is set to YES. + +TREEVIEW_WIDTH = 250 + +# If the EXT_LINKS_IN_WINDOW option is set to YES, doxygen will open links to +# external symbols imported via tag files in a separate window. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +EXT_LINKS_IN_WINDOW = NO + +# Use this tag to change the font size of LaTeX formulas included as images in +# the HTML documentation. When you change the font size after a successful +# doxygen run you need to manually remove any form_*.png images from the HTML +# output directory to force them to be regenerated. +# Minimum value: 8, maximum value: 50, default value: 10. +# This tag requires that the tag GENERATE_HTML is set to YES. + +FORMULA_FONTSIZE = 10 + +# Use the FORMULA_TRANPARENT tag to determine whether or not the images +# generated for formulas are transparent PNGs. Transparent PNGs are not +# supported properly for IE 6.0, but are supported on all modern browsers. +# +# Note that when changing this option you need to delete any form_*.png files in +# the HTML output directory before the changes have effect. +# The default value is: YES. +# This tag requires that the tag GENERATE_HTML is set to YES. + +FORMULA_TRANSPARENT = YES + +# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see +# http://www.mathjax.org) which uses client side Javascript for the rendering +# instead of using pre-rendered bitmaps. Use this if you do not have LaTeX +# installed or if you want to formulas look prettier in the HTML output. When +# enabled you may also need to install MathJax separately and configure the path +# to it using the MATHJAX_RELPATH option. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +USE_MATHJAX = NO + +# When MathJax is enabled you can set the default output format to be used for +# the MathJax output. See the MathJax site (see: +# http://docs.mathjax.org/en/latest/output.html) for more details. +# Possible values are: HTML-CSS (which is slower, but has the best +# compatibility), NativeMML (i.e. MathML) and SVG. +# The default value is: HTML-CSS. +# This tag requires that the tag USE_MATHJAX is set to YES. + +MATHJAX_FORMAT = HTML-CSS + +# When MathJax is enabled you need to specify the location relative to the HTML +# output directory using the MATHJAX_RELPATH option. The destination directory +# should contain the MathJax.js script. For instance, if the mathjax directory +# is located at the same level as the HTML output directory, then +# MATHJAX_RELPATH should be ../mathjax. The default value points to the MathJax +# Content Delivery Network so you can quickly see the result without installing +# MathJax. However, it is strongly recommended to install a local copy of +# MathJax from http://www.mathjax.org before deployment. +# The default value is: http://cdn.mathjax.org/mathjax/latest. +# This tag requires that the tag USE_MATHJAX is set to YES. + +MATHJAX_RELPATH = http://cdn.mathjax.org/mathjax/latest + +# The MATHJAX_EXTENSIONS tag can be used to specify one or more MathJax +# extension names that should be enabled during MathJax rendering. For example +# MATHJAX_EXTENSIONS = TeX/AMSmath TeX/AMSsymbols +# This tag requires that the tag USE_MATHJAX is set to YES. + +MATHJAX_EXTENSIONS = + +# The MATHJAX_CODEFILE tag can be used to specify a file with javascript pieces +# of code that will be used on startup of the MathJax code. See the MathJax site +# (see: http://docs.mathjax.org/en/latest/output.html) for more details. For an +# example see the documentation. +# This tag requires that the tag USE_MATHJAX is set to YES. + +MATHJAX_CODEFILE = + +# When the SEARCHENGINE tag is enabled doxygen will generate a search box for +# the HTML output. The underlying search engine uses javascript and DHTML and +# should work on any modern browser. Note that when using HTML help +# (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets (GENERATE_DOCSET) +# there is already a search function so this one should typically be disabled. +# For large projects the javascript based search engine can be slow, then +# enabling SERVER_BASED_SEARCH may provide a better solution. It is possible to +# search using the keyboard; to jump to the search box use + S +# (what the is depends on the OS and browser, but it is typically +# , /