mirror of
https://github.com/RT-Thread/rt-thread.git
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import RT-Thread RTOS 0.3.x to Google SVN
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
bernard.xiong
@@ -0,0 +1,170 @@
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||||
;/*
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||||
; * File : context.S
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||||
; * This file is part of RT-Thread RTOS
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||||
; * COPYRIGHT (C) 2006, RT-Thread Development Team
|
||||
; *
|
||||
; * The license and distribution terms for this file may be
|
||||
; * found in the file LICENSE in this distribution or at
|
||||
; * http://www.rt-thread.org/license/LICENSE
|
||||
; *
|
||||
; * Change Logs:
|
||||
; * Date Author Notes
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||||
; * 2009-01-17 Bernard first version
|
||||
; */
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||||
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||||
;/**
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||||
; * @addtogroup STM32
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; */
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||||
;/*@{*/
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||||
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||||
NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
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NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2)
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||||
NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest)
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NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
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SECTION .text:CODE(2)
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THUMB
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REQUIRE8
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PRESERVE8
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||||
IMPORT rt_thread_switch_interrput_flag
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IMPORT rt_interrupt_from_thread
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IMPORT rt_interrupt_to_thread
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;/*
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; * rt_base_t rt_hw_interrupt_disable();
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; */
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EXPORT rt_hw_interrupt_disable
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rt_hw_interrupt_disable:
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MRS r0, PRIMASK
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CPSID I
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BX LR
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;/*
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; * void rt_hw_interrupt_enable(rt_base_t level);
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; */
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EXPORT rt_hw_interrupt_enable
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rt_hw_interrupt_enable:
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MSR PRIMASK, r0
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BX LR
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;/*
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; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
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; * r0 --> from
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; * r1 --> to
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||||
; */
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EXPORT rt_hw_context_switch
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rt_hw_context_switch:
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LDR r2, =rt_interrupt_from_thread
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STR r0, [r2]
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LDR r2, =rt_interrupt_to_thread
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STR r1, [r2]
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LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
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LDR r1, =NVIC_PENDSVSET
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STR r1, [r0]
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CPSIE I ; enable interrupts at processor level
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BX LR
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||||
; r0 --> swith from thread stack
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; r1 --> swith to thread stack
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; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
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EXPORT rt_hw_pend_sv
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rt_hw_pend_sv:
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LDR r0, =rt_interrupt_from_thread
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LDR r1, [r0]
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CBZ r1, swtich_to_thread ; skip register save at the first time
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MRS r1, psp ; get from thread stack pointer
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STMFD r1!, {r4 - r11} ; push r4 - r11 register
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LDR r0, [r0]
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STR r1, [r0] ; update from thread stack pointer
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swtich_to_thread
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LDR r1, =rt_interrupt_to_thread
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LDR r1, [r1]
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LDR r1, [r1] ; load thread stack pointer
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||||
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LDMFD r1!, {r4 - r11} ; pop r4 - r11 register
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MSR psp, r1 ; update stack pointer
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ORR lr, lr, #0x04
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BX lr
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;/*
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; * void rt_hw_context_switch_to(rt_uint32 to);
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; * r0 --> to
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; */
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EXPORT rt_hw_context_switch_to
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rt_hw_context_switch_to:
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LDR r1, =rt_interrupt_to_thread
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STR r0, [r1]
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; set from thread to 0
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LDR r1, =rt_interrupt_from_thread
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MOV r0, #0x0
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STR r0, [r1]
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; set the PendSV exception priority
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LDR r0, =NVIC_SYSPRI2
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LDR r1, =NVIC_PENDSV_PRI
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STR r1, [r0]
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LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
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LDR r1, =NVIC_PENDSVSET
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||||
STR r1, [r0]
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||||
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||||
CPSIE I ; enable interrupts at processor level
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; never reach here!
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||||
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;/*
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; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)
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; * {
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; * if (rt_thread_switch_interrput_flag == 1)
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; * {
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; * rt_interrupt_to_thread = to;
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; * }
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; * else
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||||
; * {
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||||
; * rt_thread_switch_interrput_flag = 1;
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; * rt_interrupt_from_thread = from;
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; * rt_interrupt_to_thread = to;
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; * }
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; * }
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; */
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EXPORT rt_hw_context_switch_interrupt
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rt_hw_context_switch_interrupt:
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LDR r2, =rt_thread_switch_interrput_flag
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LDR r3, [r2]
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CMP r3, #1
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BEQ _reswitch
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MOV r3, #1 ; set rt_thread_switch_interrput_flag to 1
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STR r3, [r2]
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LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread
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STR r0, [r2]
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_reswitch:
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LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
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STR r1, [r2]
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BX lr
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EXPORT rt_hw_interrupt_thread_switch
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rt_hw_interrupt_thread_switch:
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LDR r0, =rt_thread_switch_interrput_flag
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LDR r1, [r0]
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CBZ r1, _no_switch
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; clear rt_thread_switch_interrput_flag to 0
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MOV r1, #0x00
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STR r1, [r0]
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; trigger context switch
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LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
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||||
LDR r1, =NVIC_PENDSVSET
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STR r1, [r0]
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_no_switch:
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BX lr
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END
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||||
@@ -0,0 +1,189 @@
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||||
;/*
|
||||
; * File : context.S
|
||||
; * This file is part of RT-Thread RTOS
|
||||
; * COPYRIGHT (C) 2006, RT-Thread Development Team
|
||||
; *
|
||||
; * The license and distribution terms for this file may be
|
||||
; * found in the file LICENSE in this distribution or at
|
||||
; * http://www.rt-thread.org/license/LICENSE
|
||||
; *
|
||||
; * Change Logs:
|
||||
; * Date Author Notes
|
||||
; * 2009-01-17 Bernard first version
|
||||
; */
|
||||
|
||||
;/**
|
||||
; * @addtogroup STM32
|
||||
; */
|
||||
;/*@{*/
|
||||
|
||||
NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
|
||||
NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2)
|
||||
NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest)
|
||||
NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
|
||||
|
||||
AREA |.text|, CODE, READONLY, ALIGN=2
|
||||
THUMB
|
||||
REQUIRE8
|
||||
PRESERVE8
|
||||
|
||||
IMPORT rt_thread_switch_interrput_flag
|
||||
IMPORT rt_interrupt_from_thread
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||||
IMPORT rt_interrupt_to_thread
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||||
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||||
;/*
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||||
; * rt_base_t rt_hw_interrupt_disable();
|
||||
; */
|
||||
rt_hw_interrupt_disable PROC
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||||
EXPORT rt_hw_interrupt_disable
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||||
MRS r0, PRIMASK
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CPSID I
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BX LR
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||||
ENDP
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||||
|
||||
;/*
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||||
; * void rt_hw_interrupt_enable(rt_base_t level);
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; */
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||||
rt_hw_interrupt_enable PROC
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EXPORT rt_hw_interrupt_enable
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||||
MSR PRIMASK, r0
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BX LR
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ENDP
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||||
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||||
;/*
|
||||
; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
|
||||
; * r0 --> from
|
||||
; * r1 --> to
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||||
; */
|
||||
rt_hw_context_switch PROC
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EXPORT rt_hw_context_switch
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||||
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||||
; set rt_thread_switch_interrput_flag to 1
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LDR r2, =rt_thread_switch_interrput_flag
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LDR r3, [r2]
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MOV r3, #1
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STR r3, [r2]
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|
||||
LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread
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||||
STR r0, [r2]
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||||
LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
|
||||
STR r1, [r2]
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||||
|
||||
LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
|
||||
LDR r1, =NVIC_PENDSVSET
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||||
STR r1, [r0]
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||||
; CPSIE I ; enable interrupts at processor level
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||||
BX LR
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||||
ENDP
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||||
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||||
; r0 --> swith from thread stack
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||||
; r1 --> swith to thread stack
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||||
; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
|
||||
rt_hw_pend_sv PROC
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EXPORT rt_hw_pend_sv
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||||
; clear rt_thread_switch_interrput_flag to 0
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LDR r0, =rt_thread_switch_interrput_flag
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MOV r1, #0x00
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||||
STR r1, [r0]
|
||||
|
||||
LDR r0, =rt_interrupt_from_thread
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||||
LDR r1, [r0]
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||||
CBZ r1, swtich_to_thread ; skip register save at the first time
|
||||
|
||||
MRS r1, psp ; get from thread stack pointer
|
||||
STMFD r1!, {r4 - r11} ; push r4 - r11 register
|
||||
LDR r0, [r0]
|
||||
STR r1, [r0] ; update from thread stack pointer
|
||||
|
||||
swtich_to_thread
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||||
LDR r1, =rt_interrupt_to_thread
|
||||
LDR r1, [r1]
|
||||
LDR r1, [r1] ; load thread stack pointer
|
||||
|
||||
LDMFD r1!, {r4 - r11} ; pop r4 - r11 register
|
||||
MSR psp, r1 ; update stack pointer
|
||||
|
||||
ORR lr, lr, #0x04
|
||||
BX lr
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||||
ENDP
|
||||
|
||||
;/*
|
||||
; * void rt_hw_context_switch_to(rt_uint32 to);
|
||||
; * r0 --> to
|
||||
; */
|
||||
rt_hw_context_switch_to PROC
|
||||
EXPORT rt_hw_context_switch_to
|
||||
LDR r1, =rt_interrupt_to_thread
|
||||
STR r0, [r1]
|
||||
|
||||
; set from thread to 0
|
||||
LDR r1, =rt_interrupt_from_thread
|
||||
MOV r0, #0x0
|
||||
STR r0, [r1]
|
||||
|
||||
; set the PendSV exception priority
|
||||
LDR r0, =NVIC_SYSPRI2
|
||||
LDR r1, =NVIC_PENDSV_PRI
|
||||
STR r1, [r0]
|
||||
|
||||
LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
|
||||
LDR r1, =NVIC_PENDSVSET
|
||||
STR r1, [r0]
|
||||
|
||||
CPSIE I ; enable interrupts at processor level
|
||||
|
||||
; never reach here!
|
||||
ENDP
|
||||
|
||||
;/*
|
||||
; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)
|
||||
; * {
|
||||
; * if (rt_thread_switch_interrput_flag == 1)
|
||||
; * {
|
||||
; * rt_interrupt_to_thread = to;
|
||||
; * }
|
||||
; * else
|
||||
; * {
|
||||
; * rt_thread_switch_interrput_flag = 1;
|
||||
; * rt_interrupt_from_thread = from;
|
||||
; * rt_interrupt_to_thread = to;
|
||||
; * }
|
||||
; * }
|
||||
; */
|
||||
rt_hw_context_switch_interrupt PROC
|
||||
EXPORT rt_hw_context_switch_interrupt
|
||||
LDR r2, =rt_thread_switch_interrput_flag
|
||||
LDR r3, [r2]
|
||||
CMP r3, #1
|
||||
BEQ _reswitch
|
||||
MOV r3, #1 ; set rt_thread_switch_interrput_flag to 1
|
||||
STR r3, [r2]
|
||||
LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread
|
||||
STR r0, [r2]
|
||||
_reswitch
|
||||
LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
|
||||
STR r1, [r2]
|
||||
BX lr
|
||||
ENDP
|
||||
|
||||
rt_hw_interrupt_thread_switch PROC
|
||||
EXPORT rt_hw_interrupt_thread_switch
|
||||
LDR r0, =rt_thread_switch_interrput_flag
|
||||
LDR r1, [r0]
|
||||
CBZ r1, _no_switch
|
||||
|
||||
; clear rt_thread_switch_interrput_flag to 0
|
||||
; MOV r1, #0x00
|
||||
; STR r1, [r0]
|
||||
|
||||
; trigger context switch
|
||||
LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
|
||||
LDR r1, =NVIC_PENDSVSET
|
||||
STR r1, [r0]
|
||||
|
||||
_no_switch
|
||||
BX lr
|
||||
|
||||
ENDP
|
||||
|
||||
END
|
||||
@@ -0,0 +1,42 @@
|
||||
/*
|
||||
* File : cpu.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Develop Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://openlab.rt-thread.com/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2006-03-13 Bernard first version
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
/**
|
||||
* @addtogroup S3C2410
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
/**
|
||||
* reset cpu by dog's time-out
|
||||
*
|
||||
*/
|
||||
void rt_hw_cpu_reset()
|
||||
{
|
||||
/*NOTREACHED*/
|
||||
}
|
||||
|
||||
/**
|
||||
* shutdown CPU
|
||||
*
|
||||
*/
|
||||
void rt_hw_cpu_shutdown()
|
||||
{
|
||||
rt_kprintf("shutdown...\n");
|
||||
|
||||
RT_ASSERT(0);
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
@@ -0,0 +1,34 @@
|
||||
#include <rtthread.h>
|
||||
|
||||
struct stack_contex
|
||||
{
|
||||
rt_uint32_t r0;
|
||||
rt_uint32_t r1;
|
||||
rt_uint32_t r2;
|
||||
rt_uint32_t r3;
|
||||
rt_uint32_t r12;
|
||||
rt_uint32_t lr;
|
||||
rt_uint32_t pc;
|
||||
rt_uint32_t psr;
|
||||
};
|
||||
|
||||
extern void rt_hw_interrupt_thread_switch(void);
|
||||
extern void list_thread(void);
|
||||
extern rt_thread_t rt_current_thread;
|
||||
void rt_hw_hard_fault_exception(struct stack_contex* contex)
|
||||
{
|
||||
rt_kprintf("hard fault on thread: %s\n", rt_current_thread->name);
|
||||
rt_kprintf("psr: 0x%08x\n", contex->psr);
|
||||
rt_kprintf(" pc: 0x%08x\n", contex->pc);
|
||||
rt_kprintf(" lr: 0x%08x\n", contex->lr);
|
||||
rt_kprintf("r12: 0x%08x\n", contex->r12);
|
||||
rt_kprintf("r03: 0x%08x\n", contex->r3);
|
||||
rt_kprintf("r02: 0x%08x\n", contex->r2);
|
||||
rt_kprintf("r01: 0x%08x\n", contex->r1);
|
||||
rt_kprintf("r00: 0x%08x\n", contex->r0);
|
||||
|
||||
#ifdef RT_USING_FINSH
|
||||
list_thread();
|
||||
#endif
|
||||
while (1);
|
||||
}
|
||||
@@ -0,0 +1,31 @@
|
||||
;/*
|
||||
; * File : context.S
|
||||
; * This file is part of RT-Thread RTOS
|
||||
; * COPYRIGHT (C) 2006, RT-Thread Development Team
|
||||
; *
|
||||
; * The license and distribution terms for this file may be
|
||||
; * found in the file LICENSE in this distribution or at
|
||||
; * http://www.rt-thread.org/license/LICENSE
|
||||
; *
|
||||
; * Change Logs:
|
||||
; * Date Author Notes
|
||||
; * 2009-01-17 Bernard first version
|
||||
; */
|
||||
|
||||
AREA |.text|, CODE, READONLY, ALIGN=2
|
||||
THUMB
|
||||
REQUIRE8
|
||||
PRESERVE8
|
||||
|
||||
IMPORT rt_hw_hard_fault_exception
|
||||
|
||||
rt_hw_hard_fault PROC
|
||||
EXPORT rt_hw_hard_fault
|
||||
|
||||
; get current context
|
||||
MRS r0, psp ; get fault thread stack pointer
|
||||
BL rt_hw_hard_fault_exception
|
||||
|
||||
ORR lr, lr, #0x04
|
||||
BX lr
|
||||
|
||||
@@ -0,0 +1,25 @@
|
||||
/*
|
||||
* File : trap.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Development Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://openlab.rt-thread.com/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2006-03-13 Bernard first version
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#define MAX_HANDLERS 32
|
||||
|
||||
extern rt_uint32_t rt_interrupt_nest;
|
||||
|
||||
/* exception and interrupt handler table */
|
||||
rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
|
||||
rt_uint32_t rt_thread_switch_interrput_flag;
|
||||
|
||||
/*@}*/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,69 @@
|
||||
#ifndef __RT_HW_SERIAL_H__
|
||||
#define __RT_HW_SERIAL_H__
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
/* STM32F10x library definitions */
|
||||
#include <stm32f10x_lib.h>
|
||||
|
||||
#define UART_DMA_RX_DESCRIPTOR 2
|
||||
#define UART_DMA_RX_BUFFER_SIZE 16
|
||||
|
||||
#define UART_RX_BUFFER_SIZE 64
|
||||
#define UART_TX_BUFFER_SIZE 64
|
||||
|
||||
struct stm32_serial_dma_rx
|
||||
{
|
||||
DMA_Channel_TypeDef* dma_channel;
|
||||
rt_uint8_t rx_buffer[UART_DMA_RX_DESCRIPTOR][UART_RX_BUFFER_SIZE];
|
||||
rt_uint32_t save_descriptor;
|
||||
rt_uint32_t read_index, read_descriptor;
|
||||
rt_bool_t is_full;
|
||||
};
|
||||
|
||||
/* data node for Tx Mode */
|
||||
struct stm32_serial_data_node
|
||||
{
|
||||
rt_uint8_t *data_ptr;
|
||||
rt_size_t data_size;
|
||||
struct stm32_serial_data_node *next, *prev;
|
||||
};
|
||||
struct stm32_serial_dma_tx
|
||||
{
|
||||
DMA_Channel_TypeDef* dma_channel;
|
||||
struct stm32_serial_data_node *list_head, *list_tail;
|
||||
};
|
||||
|
||||
struct stm32_serial_int_rx
|
||||
{
|
||||
rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE];
|
||||
rt_uint32_t read_index, save_index;
|
||||
};
|
||||
|
||||
struct stm32_serial_int_tx
|
||||
{
|
||||
rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE];
|
||||
rt_uint32_t write_index, save_index;
|
||||
};
|
||||
|
||||
struct stm32_serial_device
|
||||
{
|
||||
USART_TypeDef* uart_device;
|
||||
|
||||
/* rx structure */
|
||||
struct stm32_serial_int_rx* int_rx;
|
||||
struct stm32_serial_dma_rx* dma_rx;
|
||||
|
||||
/* tx structure */
|
||||
struct stm32_serial_int_tx* int_tx;
|
||||
struct stm32_serial_dma_tx* dma_tx;
|
||||
};
|
||||
|
||||
rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct stm32_serial_device *serial);
|
||||
|
||||
void rt_hw_serial_isr(rt_device_t device);
|
||||
void rt_hw_serial_dma_rx_isr(rt_device_t device);
|
||||
void rt_hw_serial_dma_tx_isr(rt_device_t device);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,59 @@
|
||||
/*
|
||||
* File : stack.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Development Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://openlab.rt-thread.com/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2006-08-23 Bernard the first version
|
||||
*/
|
||||
#include <rtthread.h>
|
||||
|
||||
/**
|
||||
* @addtogroup STM32
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
/**
|
||||
* This function will initialize thread stack
|
||||
*
|
||||
* @param tentry the entry of thread
|
||||
* @param parameter the parameter of entry
|
||||
* @param stack_addr the beginning stack address
|
||||
* @param texit the function will be called when thread exit
|
||||
*
|
||||
* @return stack address
|
||||
*/
|
||||
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
|
||||
rt_uint8_t *stack_addr, void *texit)
|
||||
{
|
||||
unsigned long *stk;
|
||||
|
||||
stk = (unsigned long *)stack_addr;
|
||||
*(stk) = 0x01000000L; /* PSR */
|
||||
*(--stk) = (unsigned long)tentry; /* entry point, pc */
|
||||
*(--stk) = (unsigned long)texit; /* lr */
|
||||
*(--stk) = 0; /* r12 */
|
||||
*(--stk) = 0; /* r3 */
|
||||
*(--stk) = 0; /* r2 */
|
||||
*(--stk) = 0; /* r1 */
|
||||
*(--stk) = (unsigned long)parameter; /* r0 : argument */
|
||||
|
||||
*(--stk) = 0; /* r11 */
|
||||
*(--stk) = 0; /* r10 */
|
||||
*(--stk) = 0; /* r9 */
|
||||
*(--stk) = 0; /* r8 */
|
||||
*(--stk) = 0; /* r7 */
|
||||
*(--stk) = 0; /* r6 */
|
||||
*(--stk) = 0; /* r5 */
|
||||
*(--stk) = 0; /* r4 */
|
||||
|
||||
/* return task's current stack address */
|
||||
return (rt_uint8_t *)stk;
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
@@ -0,0 +1,176 @@
|
||||
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
|
||||
* File Name : stm32f10x_vector.c
|
||||
* Author : MCD Application Team
|
||||
* Version : V2.0.3
|
||||
* Date : 09/22/2008
|
||||
* Description : STM32F10x vector table for EWARM5.x toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == __iar_program_start,
|
||||
* - Set the vector table entries with the exceptions ISR address,
|
||||
* - Configure external SRAM mounted on STM3210E-EVAL board
|
||||
* to be used as data memory (optional, to be enabled by user)
|
||||
* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
* priority is Privileged, and the Stack is set to Main.
|
||||
********************************************************************************
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
|
||||
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
|
||||
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
|
||||
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*******************************************************************************/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x_lib.h"
|
||||
#include "stm32f10x_it.h"
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
typedef void( *intfunc )( void );
|
||||
typedef union { intfunc __fun; void * __ptr; } intvec_elem;
|
||||
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Uncomment the following line if you need to use external SRAM mounted on
|
||||
STM3210E-EVAL board as data memory */
|
||||
/* #define DATA_IN_ExtSRAM */
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
|
||||
#pragma language=extended
|
||||
#pragma segment="CSTACK"
|
||||
|
||||
void __iar_program_start( void );
|
||||
|
||||
#pragma location = ".intvec"
|
||||
/* STM32F10x Vector Table entries */
|
||||
const intvec_elem __vector_table[] =
|
||||
{
|
||||
{ .__ptr = __sfe( "CSTACK" ) },
|
||||
__iar_program_start,
|
||||
NMIException,
|
||||
HardFaultException,
|
||||
MemManageException,
|
||||
BusFaultException,
|
||||
UsageFaultException,
|
||||
0, 0, 0, 0, /* Reserved */
|
||||
SVCHandler,
|
||||
DebugMonitor,
|
||||
0, /* Reserved */
|
||||
rt_hw_pend_sv,
|
||||
SysTickHandler,
|
||||
WWDG_IRQHandler,
|
||||
PVD_IRQHandler,
|
||||
TAMPER_IRQHandler,
|
||||
RTC_IRQHandler,
|
||||
FLASH_IRQHandler,
|
||||
RCC_IRQHandler,
|
||||
EXTI0_IRQHandler,
|
||||
EXTI1_IRQHandler,
|
||||
EXTI2_IRQHandler,
|
||||
EXTI3_IRQHandler,
|
||||
EXTI4_IRQHandler,
|
||||
DMA1_Channel1_IRQHandler,
|
||||
DMA1_Channel2_IRQHandler,
|
||||
DMA1_Channel3_IRQHandler,
|
||||
DMA1_Channel4_IRQHandler,
|
||||
DMA1_Channel5_IRQHandler,
|
||||
DMA1_Channel6_IRQHandler,
|
||||
DMA1_Channel7_IRQHandler,
|
||||
ADC1_2_IRQHandler,
|
||||
USB_HP_CAN_TX_IRQHandler,
|
||||
USB_LP_CAN_RX0_IRQHandler,
|
||||
CAN_RX1_IRQHandler,
|
||||
CAN_SCE_IRQHandler,
|
||||
EXTI9_5_IRQHandler,
|
||||
TIM1_BRK_IRQHandler,
|
||||
TIM1_UP_IRQHandler,
|
||||
TIM1_TRG_COM_IRQHandler,
|
||||
TIM1_CC_IRQHandler,
|
||||
TIM2_IRQHandler,
|
||||
TIM3_IRQHandler,
|
||||
TIM4_IRQHandler,
|
||||
I2C1_EV_IRQHandler,
|
||||
I2C1_ER_IRQHandler,
|
||||
I2C2_EV_IRQHandler,
|
||||
I2C2_ER_IRQHandler,
|
||||
SPI1_IRQHandler,
|
||||
SPI2_IRQHandler,
|
||||
USART1_IRQHandler,
|
||||
USART2_IRQHandler,
|
||||
USART3_IRQHandler,
|
||||
EXTI15_10_IRQHandler,
|
||||
RTCAlarm_IRQHandler,
|
||||
USBWakeUp_IRQHandler,
|
||||
TIM8_BRK_IRQHandler,
|
||||
TIM8_UP_IRQHandler,
|
||||
TIM8_TRG_COM_IRQHandler,
|
||||
TIM8_CC_IRQHandler,
|
||||
ADC3_IRQHandler,
|
||||
FSMC_IRQHandler,
|
||||
SDIO_IRQHandler,
|
||||
TIM5_IRQHandler,
|
||||
SPI3_IRQHandler,
|
||||
UART4_IRQHandler,
|
||||
UART5_IRQHandler,
|
||||
TIM6_IRQHandler,
|
||||
TIM7_IRQHandler,
|
||||
DMA2_Channel1_IRQHandler,
|
||||
DMA2_Channel2_IRQHandler,
|
||||
DMA2_Channel3_IRQHandler,
|
||||
DMA2_Channel4_5_IRQHandler,
|
||||
};
|
||||
|
||||
#ifdef DATA_IN_ExtSRAM
|
||||
#pragma language=extended
|
||||
|
||||
__interwork int __low_level_init(void);
|
||||
|
||||
#pragma location="ICODE"
|
||||
__interwork int __low_level_init(void)
|
||||
{
|
||||
|
||||
/* FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
|
||||
required, then adjust the Register Addresses*/
|
||||
|
||||
/* Enable FSMC clock */
|
||||
*(vu32 *)0x40021014 = 0x00000114;
|
||||
|
||||
/* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
|
||||
*(vu32 *)0x40021018 = 0x000001E0;
|
||||
|
||||
/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
|
||||
/*---------------- SRAM Address lines configuration -------------------------*/
|
||||
/*---------------- NOE and NWE configuration --------------------------------*/
|
||||
/*---------------- NE3 configuration ----------------------------------------*/
|
||||
/*---------------- NBL0, NBL1 configuration ---------------------------------*/
|
||||
|
||||
*(vu32 *)0x40011400 = 0x44BB44BB;
|
||||
*(vu32 *)0x40011404 = 0xBBBBBBBB;
|
||||
|
||||
*(vu32 *)0x40011800 = 0xB44444BB;
|
||||
*(vu32 *)0x40011804 = 0xBBBBBBBB;
|
||||
|
||||
*(vu32 *)0x40011C00 = 0x44BBBBBB;
|
||||
*(vu32 *)0x40011C04 = 0xBBBB4444;
|
||||
|
||||
*(vu32 *)0x40012000 = 0x44BBBBBB;
|
||||
*(vu32 *)0x40012004 = 0x44444B44;
|
||||
|
||||
/*---------------- FSMC Configuration ---------------------------------------*/
|
||||
/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
|
||||
|
||||
*(vu32 *)0xA0000010 = 0x00001011;
|
||||
*(vu32 *)0xA0000014 = 0x00000200;
|
||||
|
||||
|
||||
return (1);
|
||||
}
|
||||
#endif /*DATA_IN_ExtSRAM*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
||||
@@ -0,0 +1,250 @@
|
||||
;******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
|
||||
;* File Name : stm32f10x_vector.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V1.1.2
|
||||
;* Date : 09/22/2008
|
||||
;* Description : STM32F10x vector table for RVMDK toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Configure external SRAM mounted on STM3210E-EVAL board
|
||||
;* to be used as data memory (optional, to be enabled by user)
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM3 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;*******************************************************************************
|
||||
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
|
||||
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
|
||||
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
|
||||
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
|
||||
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
;// <h> Stack Configuration
|
||||
;// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
;// </h>
|
||||
Stack_Size EQU 0x00000200
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
|
||||
__initial_sp
|
||||
; If you need to use external SRAM mounted on STM3210E-EVAL board as data memory
|
||||
; and internal SRAM for Stack, uncomment the following line and comment the line above
|
||||
;__initial_sp EQU 0x20000000 + Stack_Size ; "Use MicroLIB" must be checked in
|
||||
; the Project->Options->Target window
|
||||
|
||||
; Amount of memory (in bytes) allocated for Heap
|
||||
; Tailor this value to your application needs
|
||||
;// <h> Heap Configuration
|
||||
;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
;// </h>
|
||||
|
||||
Heap_Size EQU 0x00000000
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
THUMB
|
||||
PRESERVE8
|
||||
|
||||
; Import exceptions handlers
|
||||
IMPORT NMIException
|
||||
IMPORT rt_hw_hard_fault
|
||||
IMPORT MemManageException
|
||||
IMPORT BusFaultException
|
||||
IMPORT UsageFaultException
|
||||
IMPORT SVCHandler
|
||||
IMPORT DebugMonitor
|
||||
IMPORT rt_hw_pend_sv
|
||||
IMPORT SysTickHandler
|
||||
IMPORT WWDG_IRQHandler
|
||||
IMPORT PVD_IRQHandler
|
||||
IMPORT TAMPER_IRQHandler
|
||||
IMPORT RTC_IRQHandler
|
||||
IMPORT FLASH_IRQHandler
|
||||
IMPORT RCC_IRQHandler
|
||||
IMPORT EXTI0_IRQHandler
|
||||
IMPORT EXTI1_IRQHandler
|
||||
IMPORT EXTI2_IRQHandler
|
||||
IMPORT EXTI3_IRQHandler
|
||||
IMPORT EXTI4_IRQHandler
|
||||
IMPORT DMA1_Channel1_IRQHandler
|
||||
IMPORT DMA1_Channel2_IRQHandler
|
||||
IMPORT DMA1_Channel3_IRQHandler
|
||||
IMPORT DMA1_Channel4_IRQHandler
|
||||
IMPORT DMA1_Channel5_IRQHandler
|
||||
IMPORT DMA1_Channel6_IRQHandler
|
||||
IMPORT DMA1_Channel7_IRQHandler
|
||||
IMPORT ADC1_2_IRQHandler
|
||||
IMPORT USB_HP_CAN_TX_IRQHandler
|
||||
IMPORT USB_LP_CAN_RX0_IRQHandler
|
||||
IMPORT CAN_RX1_IRQHandler
|
||||
IMPORT CAN_SCE_IRQHandler
|
||||
IMPORT EXTI9_5_IRQHandler
|
||||
IMPORT TIM1_BRK_IRQHandler
|
||||
IMPORT TIM1_UP_IRQHandler
|
||||
IMPORT TIM1_TRG_COM_IRQHandler
|
||||
IMPORT TIM1_CC_IRQHandler
|
||||
IMPORT TIM2_IRQHandler
|
||||
IMPORT TIM3_IRQHandler
|
||||
IMPORT TIM4_IRQHandler
|
||||
IMPORT I2C1_EV_IRQHandler
|
||||
IMPORT I2C1_ER_IRQHandler
|
||||
IMPORT I2C2_EV_IRQHandler
|
||||
IMPORT I2C2_ER_IRQHandler
|
||||
IMPORT SPI1_IRQHandler
|
||||
IMPORT SPI2_IRQHandler
|
||||
IMPORT USART1_IRQHandler
|
||||
IMPORT USART2_IRQHandler
|
||||
IMPORT USART3_IRQHandler
|
||||
IMPORT EXTI15_10_IRQHandler
|
||||
IMPORT RTCAlarm_IRQHandler
|
||||
IMPORT USBWakeUp_IRQHandler
|
||||
IMPORT TIM8_BRK_IRQHandler
|
||||
IMPORT TIM8_UP_IRQHandler
|
||||
IMPORT TIM8_TRG_COM_IRQHandler
|
||||
IMPORT TIM8_CC_IRQHandler
|
||||
IMPORT ADC3_IRQHandler
|
||||
IMPORT FSMC_IRQHandler
|
||||
IMPORT SDIO_IRQHandler
|
||||
IMPORT TIM5_IRQHandler
|
||||
IMPORT SPI3_IRQHandler
|
||||
IMPORT UART4_IRQHandler
|
||||
IMPORT UART5_IRQHandler
|
||||
IMPORT TIM6_IRQHandler
|
||||
IMPORT TIM7_IRQHandler
|
||||
IMPORT DMA2_Channel1_IRQHandler
|
||||
IMPORT DMA2_Channel2_IRQHandler
|
||||
IMPORT DMA2_Channel3_IRQHandler
|
||||
IMPORT DMA2_Channel4_5_IRQHandler
|
||||
|
||||
;*******************************************************************************
|
||||
; Fill-up the Vector Table entries with the exceptions ISR address
|
||||
;*******************************************************************************
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler
|
||||
DCD NMIException
|
||||
DCD rt_hw_hard_fault
|
||||
DCD MemManageException
|
||||
DCD BusFaultException
|
||||
DCD UsageFaultException
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVCHandler
|
||||
DCD DebugMonitor
|
||||
DCD 0 ; Reserved
|
||||
DCD rt_hw_pend_sv
|
||||
DCD SysTickHandler
|
||||
DCD WWDG_IRQHandler
|
||||
DCD PVD_IRQHandler
|
||||
DCD TAMPER_IRQHandler
|
||||
DCD RTC_IRQHandler
|
||||
DCD FLASH_IRQHandler
|
||||
DCD RCC_IRQHandler
|
||||
DCD EXTI0_IRQHandler
|
||||
DCD EXTI1_IRQHandler
|
||||
DCD EXTI2_IRQHandler
|
||||
DCD EXTI3_IRQHandler
|
||||
DCD EXTI4_IRQHandler
|
||||
DCD DMA1_Channel1_IRQHandler
|
||||
DCD DMA1_Channel2_IRQHandler
|
||||
DCD DMA1_Channel3_IRQHandler
|
||||
DCD DMA1_Channel4_IRQHandler
|
||||
DCD DMA1_Channel5_IRQHandler
|
||||
DCD DMA1_Channel6_IRQHandler
|
||||
DCD DMA1_Channel7_IRQHandler
|
||||
DCD ADC1_2_IRQHandler
|
||||
DCD USB_HP_CAN_TX_IRQHandler
|
||||
DCD USB_LP_CAN_RX0_IRQHandler
|
||||
DCD CAN_RX1_IRQHandler
|
||||
DCD CAN_SCE_IRQHandler
|
||||
DCD EXTI9_5_IRQHandler
|
||||
DCD TIM1_BRK_IRQHandler
|
||||
DCD TIM1_UP_IRQHandler
|
||||
DCD TIM1_TRG_COM_IRQHandler
|
||||
DCD TIM1_CC_IRQHandler
|
||||
DCD TIM2_IRQHandler
|
||||
DCD TIM3_IRQHandler
|
||||
DCD TIM4_IRQHandler
|
||||
DCD I2C1_EV_IRQHandler
|
||||
DCD I2C1_ER_IRQHandler
|
||||
DCD I2C2_EV_IRQHandler
|
||||
DCD I2C2_ER_IRQHandler
|
||||
DCD SPI1_IRQHandler
|
||||
DCD SPI2_IRQHandler
|
||||
DCD USART1_IRQHandler
|
||||
DCD USART2_IRQHandler
|
||||
DCD USART3_IRQHandler
|
||||
DCD EXTI15_10_IRQHandler
|
||||
DCD RTCAlarm_IRQHandler
|
||||
DCD USBWakeUp_IRQHandler
|
||||
DCD TIM8_BRK_IRQHandler
|
||||
DCD TIM8_UP_IRQHandler
|
||||
DCD TIM8_TRG_COM_IRQHandler
|
||||
DCD TIM8_CC_IRQHandler
|
||||
DCD ADC3_IRQHandler
|
||||
DCD FSMC_IRQHandler
|
||||
DCD SDIO_IRQHandler
|
||||
DCD TIM5_IRQHandler
|
||||
DCD SPI3_IRQHandler
|
||||
DCD UART4_IRQHandler
|
||||
DCD UART5_IRQHandler
|
||||
DCD TIM6_IRQHandler
|
||||
DCD TIM7_IRQHandler
|
||||
DCD DMA2_Channel1_IRQHandler
|
||||
DCD DMA2_Channel2_IRQHandler
|
||||
DCD DMA2_Channel3_IRQHandler
|
||||
DCD DMA2_Channel4_5_IRQHandler
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset handler routine
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler
|
||||
|
||||
IMPORT __main
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
ELSE
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, = (Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
|
||||
;******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE*****
|
||||
Reference in New Issue
Block a user