diff --git a/bsp/cvitek/cv18xx_risc-v/.config b/bsp/cvitek/cv18xx_risc-v/.config
index a4c5f3d4af..52f2d18c91 100644
--- a/bsp/cvitek/cv18xx_risc-v/.config
+++ b/bsp/cvitek/cv18xx_risc-v/.config
@@ -301,6 +301,7 @@ CONFIG_NETDEV_USING_IFCONFIG=y
 CONFIG_NETDEV_USING_PING=y
 CONFIG_NETDEV_USING_NETSTAT=y
 CONFIG_NETDEV_USING_AUTO_DEFAULT=y
+# CONFIG_NETDEV_USING_LINK_STATUS_CALLBACK is not set
 # CONFIG_NETDEV_USING_IPV6 is not set
 CONFIG_NETDEV_IPV4=1
 CONFIG_NETDEV_IPV6=0
@@ -561,6 +562,7 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_JSMN is not set
 # CONFIG_PKG_USING_AGILE_JSMN is not set
 # CONFIG_PKG_USING_PARSON is not set
+# CONFIG_PKG_USING_RYAN_JSON is not set
 # end of JSON: JavaScript Object Notation, a lightweight data-interchange format
 
 #
@@ -967,6 +969,7 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_SYSTEM_RUN_LED is not set
 # CONFIG_PKG_USING_BT_MX01 is not set
 # CONFIG_PKG_USING_RGPOWER is not set
+# CONFIG_PKG_USING_BT_MX02 is not set
 # CONFIG_PKG_USING_SPI_TOOLS is not set
 # end of peripheral libraries and drivers
 
@@ -1325,7 +1328,7 @@ CONFIG_UART_IRQ_BASE=44
 
 CONFIG_BSP_USING_CV18XX=y
 CONFIG_C906_PLIC_PHY_ADDR=0x70000000
-CONFIG_IRQ_MAX_NR=64
+CONFIG_IRQ_MAX_NR=101
 CONFIG_TIMER_CLK_FREQ=25000000
 CONFIG_GPIO_IRQ_BASE=60
 CONFIG_SYS_GPIO_IRQ_BASE=70
diff --git a/bsp/cvitek/cv18xx_risc-v/Kconfig b/bsp/cvitek/cv18xx_risc-v/Kconfig
index db5ec22c46..67732b3fbd 100755
--- a/bsp/cvitek/cv18xx_risc-v/Kconfig
+++ b/bsp/cvitek/cv18xx_risc-v/Kconfig
@@ -29,7 +29,7 @@ config C906_PLIC_PHY_ADDR
 
 config IRQ_MAX_NR
     int
-    default 64
+    default 101
 
 config TIMER_CLK_FREQ
     int
diff --git a/bsp/cvitek/cv18xx_risc-v/rtconfig.h b/bsp/cvitek/cv18xx_risc-v/rtconfig.h
index 6a439032db..dc4afaa165 100755
--- a/bsp/cvitek/cv18xx_risc-v/rtconfig.h
+++ b/bsp/cvitek/cv18xx_risc-v/rtconfig.h
@@ -452,7 +452,7 @@
 /* end of General Drivers Configuration */
 #define BSP_USING_CV18XX
 #define C906_PLIC_PHY_ADDR 0x70000000
-#define IRQ_MAX_NR 64
+#define IRQ_MAX_NR 101
 #define TIMER_CLK_FREQ 25000000
 #define GPIO_IRQ_BASE 60
 #define SYS_GPIO_IRQ_BASE 70