Mirrors_Framework/rt-thread
1
0
Fork 0
mirror of https://github.com/RT-Thread/rt-thread.git synced 2026-09-20 09:28:49 +08:00
Code Issues Actions 1 Packages Projects Releases Wiki Activity

Merge pull request #3504 from bigmagic123/add_ls2k_bsp

Browse Source 
Add ls2k bsp
This commit is contained in:
Bernard Xiong
2020-04-07 21:23:05 +08:00
committed by GitHub
parent e382ae08da c27f13c6c9
commit baa3145bfe
31 changed files with 1787 additions and 62 deletions
Download Patch File Download Diff File Expand all files Collapse all files
libcpu/Kconfig
+3
View File
@@ -77,6 +77,9 @@ config ARCH_ARM_CORTEX_A9
config ARCH_MIPS
bool
config ARCH_MIPS64
bool
config ARCH_MIPS_XBURST
bool
select ARCH_MIPS
libcpu/mips/common/asm.h
+93
View File
@@ -14,6 +14,7 @@
#ifndef __ASM_H__
#define __ASM_H__
#include <rtconfig.h>
/*
* LEAF - declare leaf routine
*/
@@ -117,7 +118,94 @@ symbol = value
/*
* Macros to handle different pointer/register sizes for 32/64-bit code
*/
#if defined ARCH_MIPS64
/*
* Size of a register
*/
#define SZREG 8
/*
* Use the following macros in assemblercode to load/store registers,
* pointers etc.
*/
#define REG_S sd
#define REG_L ld
#define REG_SUBU dsubu
#define REG_ADDU daddu
/*
* How to add/sub/load/store/shift C int variables.
*/
#define INT_ADD dadd
#define INT_ADDU daddu
#define INT_ADDI daddi
#define INT_ADDIU daddiu
#define INT_SUB dsub
#define INT_SUBU dsubu
#define INT_L ld
#define INT_S sd
#define INT_SLL dsll
#define INT_SLLV dsllv
#define INT_SRL dsrl
#define INT_SRLV dsrlv
#define INT_SRA dsra
#define INT_SRAV dsrav
/*
* Use the following macros in assemblercode to load/store registers,
* pointers etc.
*/
#define LONG_ADD dadd
#define LONG_ADDU daddu
#define LONG_ADDI daddi
#define LONG_ADDIU daddiu
#define LONG_SUB dsub
#define LONG_SUBU dsubu
#define LONG_L ld
#define LONG_S sd
#define LONG_SP sdp
#define LONG_SLL dsll
#define LONG_SLLV dsllv
#define LONG_SRL dsrl
#define LONG_SRLV dsrlv
#define LONG_SRA dsra
#define LONG_SRAV dsrav
#define LONG .dword
#define LONGSIZE 8
#define LONGMASK 7
#define LONGLOG 3
/*
* How to add/sub/load/store/shift pointers.
*/
#define PTR_ADD dadd
#define PTR_ADDU daddu
#define PTR_ADDI daddi
#define PTR_ADDIU daddiu
#define PTR_SUB dsub
#define PTR_SUBU dsubu
#define PTR_L ld
#define PTR_S sd
#define PTR_LA dla
#define PTR_LI dli
#define PTR_SLL dsll
#define PTR_SLLV dsllv
#define PTR_SRL dsrl
#define PTR_SRLV dsrlv
#define PTR_SRA dsra
#define PTR_SRAV dsrav
#define PTR_SCALESHIFT 3
#define PTR .dword
#define PTRSIZE 8
#define PTRLOG 3
#define MFC0 dmfc0
#define MTC0 dmtc0
#else
/*
* Size of a register
*/
@@ -173,7 +261,11 @@ symbol = value
#define LONG_SRAV srav
#define LONG .word
#ifdef ARCH_MIPS64
#define LONGSIZE 8
#else
#define LONGSIZE 4
#endif
#define LONGMASK 3
#define LONGLOG 2
@@ -211,6 +303,7 @@ symbol = value
#define MFC0 mfc0
#define MTC0 mtc0
#endif
#define SSNOP sll zero, zero, 1
libcpu/mips/common/context_gcc.S
+12 -12
View File
@@ -25,11 +25,11 @@
*/
.globl rt_hw_context_switch
rt_hw_context_switch:
mtc0 ra, CP0_EPC
MTC0 ra, CP0_EPC
SAVE_ALL
sw sp, 0(a0) /* store sp in preempted tasks TCB */
lw sp, 0(a1) /* get new task stack pointer */
REG_S sp, 0(a0) /* store sp in preempted tasks TCB */
REG_L sp, 0(a1) /* get new task stack pointer */
RESTORE_ALL_AND_RET
@@ -39,7 +39,7 @@ rt_hw_context_switch:
*/
.globl rt_hw_context_switch_to
rt_hw_context_switch_to:
lw sp, 0(a0) /* get new task stack pointer */
REG_L sp, 0(a0) /* get new task stack pointer */
RESTORE_ALL_AND_RET
/*
@@ -50,17 +50,17 @@ rt_hw_context_switch_to:
.globl rt_interrupt_to_thread
.globl rt_hw_context_switch_interrupt
rt_hw_context_switch_interrupt:
la t0, rt_thread_switch_interrupt_flag
lw t1, 0(t0)
PTR_LA t0, rt_thread_switch_interrupt_flag
REG_L t1, 0(t0)
nop
bnez t1, _reswitch
nop
li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */
sw t1, 0(t0)
la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */
PTR_LA t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */
sw a0, 0(t0)
_reswitch:
la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */
PTR_LA t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */
sw a1, 0(t0)
jr ra
nop
@@ -78,7 +78,7 @@ mips_irq_handle:
/* let k0 keep the current context sp */
move k0, sp
/* switch to kernel stack */
la sp, _system_stack
PTR_LA sp, _system_stack
jal rt_interrupt_enter
nop
@@ -96,7 +96,7 @@ mips_irq_handle:
* if rt_thread_switch_interrupt_flag set, jump to
* rt_hw_context_switch_interrupt_do and do not return
*/
la k0, rt_thread_switch_interrupt_flag
PTR_LA k0, rt_thread_switch_interrupt_flag
lw k1, 0(k0)
beqz k1, spurious_interrupt
nop
@@ -106,12 +106,12 @@ mips_irq_handle:
/*
* switch to the new thread
*/
la k0, rt_interrupt_from_thread
PTR_LA k0, rt_interrupt_from_thread
lw k1, 0(k0)
nop
sw sp, 0(k1) /* store sp in preempted task TCB */
la k0, rt_interrupt_to_thread
PTR_LA k0, rt_interrupt_to_thread
lw k1, 0(k0)
nop
lw sp, 0(k1) /* get new task stack pointer */
libcpu/mips/common/entry_gcc.S
+19 -10
View File
@@ -13,6 +13,9 @@
#endif
#include <mips.h>
#include <rtconfig.h>
#include "asm.h"
#include <rtconfig.h>
.section ".start", "ax"
@@ -25,27 +28,33 @@ _rtthread_entry:
.globl _start
_start:
#endif
la ra, _rtthread_entry
PTR_LA ra, _rtthread_entry
/* disable interrupt */
mtc0 zero, CP0_CAUSE
mtc0 zero, CP0_STATUS # Set CPU to disable interrupt.
MTC0 zero, CP0_CAUSE
MTC0 zero, CP0_STATUS # Set CPU to disable interrupt.
ehb
#ifdef ARCH_MIPS64
dli t0, ST0_KX
MTC0 t0, CP0_STATUS
#endif
/* setup stack pointer */
la sp, _system_stack
la gp, _gp
PTR_LA sp, _system_stack
PTR_LA gp, _gp
bal rt_cpu_early_init
nop
/* clear bss */
la t0, __bss_start
la t1, __bss_end
PTR_LA t0, __bss_start
PTR_LA t1, __bss_end
_clr_bss_loop:
sw zero, 0(t0)
bne t0, t1, _clr_bss_loop
addiu t0, t0, 4
bne t1, t0, _clr_bss_loop
addu t0, 4
/* jump to RT-Thread RTOS */
jal rtthread_startup
nop
libcpu/mips/common/exception.c
+12 -9
View File
@@ -19,10 +19,10 @@
/*@{*/
extern rt_uint32_t __ebase_entry;
rt_uint32_t rt_interrupt_from_thread;
rt_uint32_t rt_interrupt_to_thread;
rt_uint32_t rt_thread_switch_interrupt_flag;
extern rt_ubase_t __ebase_entry;
rt_ubase_t rt_interrupt_from_thread;
rt_ubase_t rt_interrupt_to_thread;
rt_ubase_t rt_thread_switch_interrupt_flag;
rt_base_t rt_hw_interrupt_disable(void)
{
@@ -101,7 +101,10 @@ static void install_default_exception_handler(void)
int rt_hw_exception_init(void)
{
rt_uint32_t ebase = (rt_uint32_t)&__ebase_entry;
rt_ubase_t ebase = (rt_ubase_t)&__ebase_entry;
#ifdef ARCH_MIPS64
ebase |= 0xffffffff00000000;
#endif
write_c0_ebase(ebase);
clear_c0_status(ST0_BEV | ST0_ERL | ST0_EXL);
clear_c0_status(ST0_IM | ST0_IE);
@@ -114,14 +117,14 @@ int rt_hw_exception_init(void)
void rt_general_exc_dispatch(struct pt_regs *regs)
{
rt_uint32_t cause, exccode;
rt_ubase_t exccode = 0;
exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
if (exccode == 0) {
rt_uint32_t status, pending;
rt_ubase_t status, pending;
status = read_c0_status();
pending = (cause & CAUSEF_IP) & (status & ST0_IM);
pending = (CAUSEF_IP) & (status & ST0_IM);
if (pending & CAUSEF_IP0)
rt_do_mips_cpu_irq(0);
if (pending & CAUSEF_IP1)
libcpu/mips/common/exception_gcc.S
+9 -4
View File
@@ -7,6 +7,11 @@
* Date Author Notes
* 2019-12-04 Jiaxun Yang Initial version
*/
#ifndef __ASSEMBLY__
#define __ASSEMBLY__
#endif
#include <mips.h>
.section ".exc_vectors", "ax"
.extern tlb_refill_handler
@@ -45,15 +50,15 @@ irq_exception:
/* general exception handler */
_general_exception_handler:
.set noreorder
la $k0, mips_irq_handle
jr $k0
PTR_LA k0, mips_irq_handle
jr k0
nop
.set reorder
/* interrupt handler */
_irq_handler:
.set noreorder
la $k0, mips_irq_handle
jr $k0
PTR_LA k0, mips_irq_handle
jr k0
nop
.set reorder
libcpu/mips/common/mips_addrspace.h
+15 -8
View File
@@ -24,7 +24,7 @@
#define _ATYPE_ __PTRDIFF_TYPE__
#define _ATYPE32_ int
#define _ATYPE64_ __s64
#ifdef CONFIG_64BIT
#ifdef ARCH_MIPS64
#define _CONST64_(x) x ## L
#else
#define _CONST64_(x) x ## LL
@@ -54,7 +54,7 @@
#define XPHYSADDR(a) ((_ACAST64_(a)) & \
_CONST64_(0x000000ffffffffff))
#ifdef CONFIG_64BIT
#ifdef ARCH_MIPS64
/*
* Memory segments (64bit kernel mode addresses)
@@ -75,6 +75,12 @@
#define CKSEG2ADDR(a) (CPHYSADDR(a) | CKSEG2)
#define CKSEG3ADDR(a) (CPHYSADDR(a) | CKSEG3)
#define KUSEGBASE 0xffffffff00000000
#define KSEG0BASE 0xffffffff80000000
#define KSEG1BASE 0xffffffffa0000000
#define KSEG2BASE 0xffffffffc0000000
#define KSEG3BASE 0xffffffffe0000000
#else
#define CKSEG0ADDR(a) (CPHYSADDR(a) | KSEG0BASE)
@@ -90,6 +96,12 @@
#define KSEG2ADDR(a) (CPHYSADDR(a) | KSEG2BASE)
#define KSEG3ADDR(a) (CPHYSADDR(a) | KSEG3BASE)
#define CKUSEG 0x00000000
#define CKSEG0 0x80000000
#define CKSEG1 0xa0000000
#define CKSEG2 0xc0000000
#define CKSEG3 0xe0000000
/*
* Memory segments (32bit kernel mode addresses)
* These are the traditional names used in the 32-bit universe.
@@ -100,14 +112,9 @@
#define KSEG2BASE 0xc0000000
#define KSEG3BASE 0xe0000000
#define CKUSEG 0x00000000
#define CKSEG0 0x80000000
#define CKSEG1 0xa0000000
#define CKSEG2 0xc0000000
#define CKSEG3 0xe0000000
#endif
/*
* Cache modes for XKPHYS address conversion macros
*/
libcpu/mips/common/mips_regs.h
+45 -1
View File
@@ -10,13 +10,14 @@
#ifndef _MIPS_REGS_H_
#define _MIPS_REGS_H_
#include <rtconfig.h>
#define REG_A0 4
#define REG_SP 29
#define REG_GP 28
#define REG_FP 30
#define REG_RA 31
#ifndef ARCH_MIPS64
#define zero $0 /* wired zero */
#define AT $1 /* assembler temp - uppercase because of ".set at" */
#define v0 $2 /* return value */
@@ -56,6 +57,49 @@
#define s8 $30 /* same like fp! */
#define ra $31 /* return address */
#else
#define zero $0 /* wired zero */
#define AT $at /* assembler temp - uppercase because of ".set at" */
#define v0 $2 /* return value - caller saved */
#define v1 $3
#define a0 $4 /* argument registers */
#define a1 $5
#define a2 $6
#define a3 $7
#define a4 $8 /* arg reg 64 bit; caller saved in 32 bit */
#define ta0 $8
#define a5 $9
#define ta1 $9
#define a6 $10
#define ta2 $10
#define a7 $11
#define ta3 $11
#define t0 $12 /* caller saved */
#define t1 $13
#define t2 $14
#define t3 $15
#define s0 $16 /* callee saved */
#define s1 $17
#define s2 $18
#define s3 $19
#define s4 $20
#define s5 $21
#define s6 $22
#define s7 $23
#define t8 $24 /* caller saved */
#define t9 $25 /* callee address for PIC/temp */
#define jp $25 /* PIC jump register */
#define k0 $26 /* kernel temporary */
#define k1 $27
#define gp $28 /* global pointer - caller saved for PIC */
#define sp $29 /* stack pointer */
#define fp $30 /* frame pointer */
#define s8 $30 /* callee saved */
#define ra $31 /* return address */
#endif
#define fv0 $f0 /* return value */
#define fv0f $f1
#define fv1 $f2
libcpu/mips/common/ptrace.h
+23 -4
View File
@@ -14,6 +14,8 @@
#include "asm.h"
#include "mips_regs.h"
#define HI_LO_SIZE 4
#define FP_REG_SIZE 8
#define NUM_FPU_REGS 16
@@ -27,6 +29,7 @@ struct mips_fpu_struct {
};
struct pt_regs {
#ifndef ARCH_MIPS64
/* Only O32 Need This! */
/* Pad bytes for argument save space on the stack. */
rt_uint32_t pad0[8];
@@ -41,6 +44,18 @@ struct pt_regs {
rt_uint32_t cp0_badvaddr;
rt_uint32_t cp0_cause;
rt_uint32_t cp0_epc;
#else
/* Saved main processor registers. */
unsigned long regs[32];
/* Saved special registers. */
rt_uint32_t cp0_status;
rt_uint32_t hi;
rt_uint32_t lo;
unsigned long cp0_badvaddr;
rt_uint32_t cp0_cause;
unsigned long cp0_epc;
#endif
#ifdef RT_USING_FPU
/* FPU Registers */
@@ -52,7 +67,11 @@ struct pt_regs {
#endif
/* Note: For call stack o32 ABI has 0x8 shadowsoace Here */
#ifdef ARCH_MIPS64
#define PT_R0 (0x0 * LONGSIZE) /* 0 */
#else
#define PT_R0 (0x8 * LONGSIZE) /* 0 */
#endif
#define PT_R1 ((PT_R0) + LONGSIZE) /* 1 */
#define PT_R2 ((PT_R1) + LONGSIZE) /* 2 */
#define PT_R3 ((PT_R2) + LONGSIZE) /* 3 */
@@ -89,8 +108,8 @@ struct pt_regs {
* Saved special registers
*/
#define PT_STATUS ((PT_R31) + LONGSIZE) /* 32 */
#define PT_HI ((PT_STATUS) + LONGSIZE) /* 33 */
#define PT_LO ((PT_HI) + LONGSIZE) /* 34 */
#define PT_HI ((PT_STATUS) + HI_LO_SIZE) /* 33 */
#define PT_LO ((PT_HI) + HI_LO_SIZE) /* 34 */
#define PT_BADVADDR ((PT_LO) + LONGSIZE) /* 35 */
#define PT_CAUSE ((PT_BADVADDR) + LONGSIZE) /* 36 */
#define PT_EPC ((PT_CAUSE) + LONGSIZE) /* 37 */
@@ -115,9 +134,9 @@ struct pt_regs {
#define PT_FPU_R28 ((PT_FPU_R26) + FP_REG_SIZE)
#define PT_FPU_R30 ((PT_FPU_R28) + FP_REG_SIZE)
#define PT_FPU_FCSR31 ((PT_FPU_R30) + FP_REG_SIZE)
#define PT_FPU_PAD0 ((PT_FPU_FCSR31) + LONGSIZE)
#define PT_FPU_PAD0 ((PT_FPU_FCSR31) + 4)
#define PT_FPU_END ((PT_FPU_PAD0) + LONGSIZE)
#define PT_FPU_END ((PT_FPU_PAD0) + 4)
#define PT_SIZE PT_FPU_END
#else
#define PT_SIZE PT_REG_END
libcpu/mips/common/stack.c
+11 -10
View File
@@ -16,8 +16,8 @@ register rt_uint32_t $GP __asm__ ("$28");
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
{
static rt_uint32_t wSR=0;
static rt_uint32_t wGP;
static rt_ubase_t wSR=0;
static rt_ubase_t wGP;
rt_uint8_t *stk;
struct pt_regs *pt;
@@ -25,26 +25,27 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_ad
rt_uint32_t i;
/* Get stack aligned */
stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8);
stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_ubase_t)stack_addr, 8);
stk -= sizeof(struct pt_regs);
pt = (struct pt_regs*)stk;
#ifndef ARCH_MIPS64
for (i = 0; i < 8; ++i)
{
pt->pad0[i] = 0xdeadbeef;
}
#endif
/* Fill Stack register numbers */
for (i = 0; i < 32; ++i)
{
pt->regs[i] = 0xdeadbeef;
}
pt->regs[REG_SP] = (rt_uint32_t)stk;
pt->regs[REG_A0] = (rt_uint32_t)parameter;
pt->regs[REG_GP] = (rt_uint32_t)$GP;
pt->regs[REG_FP] = (rt_uint32_t)0x0;
pt->regs[REG_RA] = (rt_uint32_t)texit;
pt->regs[REG_SP] = (rt_ubase_t)stk;
pt->regs[REG_A0] = (rt_ubase_t)parameter;
pt->regs[REG_GP] = (rt_ubase_t)$GP;
pt->regs[REG_FP] = (rt_ubase_t)0x0;
pt->regs[REG_RA] = (rt_ubase_t)texit;
pt->hi = 0x0;
pt->lo = 0x0;
@@ -53,7 +54,7 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_ad
pt->cp0_status |= (ST0_CU1 | ST0_FR);
#endif
pt->cp0_cause = read_c0_cause();
pt->cp0_epc = (rt_uint32_t)tentry;
pt->cp0_epc = (rt_ubase_t)tentry;
pt->cp0_badvaddr = 0x0;
return stk;
libcpu/mips/common/stackframe.h
+4 -4
View File
@@ -60,11 +60,11 @@
mfhi v1
LONG_S $8, PT_R8(sp)
LONG_S $9, PT_R9(sp)
LONG_S v1, PT_HI(sp)
sw v1, PT_HI(sp)
mflo v1
LONG_S $10, PT_R10(sp)
LONG_S $11, PT_R11(sp)
LONG_S v1, PT_LO(sp)
sw v1, PT_LO(sp)
LONG_S $12, PT_R12(sp)
LONG_S $13, PT_R13(sp)
LONG_S $14, PT_R14(sp)
@@ -159,11 +159,11 @@
.endm
.macro RESTORE_TEMP
LONG_L $24, PT_LO(sp)
lw $24, PT_LO(sp)
LONG_L $8, PT_R8(sp)
LONG_L $9, PT_R9(sp)
mtlo $24
LONG_L $24, PT_HI(sp)
lw $24, PT_HI(sp)
LONG_L $10, PT_R10(sp)
LONG_L $11, PT_R11(sp)
mthi $24
libcpu/mips/gs264/SConscript
+14
View File
@@ -0,0 +1,14 @@
# RT-Thread building script for component
from building import *
Import('rtconfig')
cwd = GetCurrentDir()
src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
CPPPATH = [cwd]
ASFLAGS = ''
group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
Return('group')
libcpu/mips/gs264/cpuinit_gcc.S
+26
View File
@@ -0,0 +1,26 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-04-05 bigmagic Initial version
*/
#ifndef __ASSEMBLY__
#define __ASSEMBLY__
#endif
#include <mips.h>
.section ".text", "ax"
.set noreorder
.globl rt_cpu_early_init
rt_cpu_early_init:
mfc0 t0, CP0_CONFIG
ori t0, 3
mtc0 t0, CP0_CONFIG
ehb
jr ra