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modified: ../../libcpu/risc-v/e310/context_gcc.S

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fix open timer intrrupt
This commit is contained in:
zhangjun
2017-07-26 16:27:54 +08:00
parent 98a6896cfa
commit b80f83f360
2 changed files with 7 additions and 9 deletions
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libcpu/risc-v/e310/context_gcc.S
+4 -2
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@@ -32,7 +32,8 @@
rt_hw_interrupt_disable:
addi sp, sp, -12
sw a5, (sp)
csrrc a5, mie, MIP_MEIP|MIP_MTIP|MIP_MSIP
li a5, MIP_MEIP|MIP_MTIP|MIP_MSIP
csrrc a5, mie, a5
/* csrrc a5, mstatus, MSTATUS_MIE*/
lw a5, (sp)
addi sp, sp, 12
@@ -45,7 +46,8 @@ rt_hw_interrupt_disable:
rt_hw_interrupt_enable:
addi sp, sp, -12
sw a5, (sp)
csrrs a5, mie, MIP_MEIP|MIP_MTIP|MIP_MSIP
li a5, MIP_MEIP|MIP_MTIP|MIP_MSIP
csrrs a5, mie, a5
/* csrrsi a5, mstatus, MSTATUS_MIE*/
lw a5, (sp)
addi sp, sp, 12