mirror of
https://github.com/RT-Thread/rt-thread.git
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Add dm365 porting.
This commit is contained in:
weety
@@ -0,0 +1,109 @@
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/*
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* File : context.S
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006, RT-Thread Development Team
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||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
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||||
* 2011-01-13 weety
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*/
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/*!
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* \addtogroup DM36X
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*/
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/*@{*/
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#define NOINT 0xc0
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/*
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* rt_base_t rt_hw_interrupt_disable();
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*/
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.globl rt_hw_interrupt_disable
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rt_hw_interrupt_disable:
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mrs r0, cpsr
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orr r1, r0, #NOINT
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msr cpsr_c, r1
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bx lr
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/*
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* void rt_hw_interrupt_enable(rt_base_t level);
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*/
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.globl rt_hw_interrupt_enable
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rt_hw_interrupt_enable:
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msr cpsr, r0
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bx lr
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/*
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* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
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* r0 --> from
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* r1 --> to
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*/
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.globl rt_hw_context_switch
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rt_hw_context_switch:
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stmfd sp!, {lr} @ push pc (lr should be pushed in place of PC)
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stmfd sp!, {r0-r12, lr} @ push lr & register file
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mrs r4, cpsr
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tst lr, #0x01
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orrne r4, r4, #0x20 @ it's thumb code
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stmfd sp!, {r4} @ push cpsr
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str sp, [r0] @ store sp in preempted tasks TCB
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ldr sp, [r1] @ get new task stack pointer
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ldmfd sp!, {r4} @ pop new task cpsr to spsr
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msr spsr_cxsf, r4
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_do_switch:
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ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc, copy spsr to cpsr
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/*
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* void rt_hw_context_switch_to(rt_uint32 to);
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* r0 --> to
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*/
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.globl rt_hw_context_switch_to
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rt_hw_context_switch_to:
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ldr sp, [r0] @ get new task stack pointer
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ldmfd sp!, {r4} @ pop new task spsr
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msr spsr_cxsf, r4
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bic r4, r4, #0x20 @ must be ARM mode
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msr cpsr_cxsf, r4
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ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc
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/*
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* void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
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*/
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.globl rt_thread_switch_interrupt_flag
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.globl rt_interrupt_from_thread
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.globl rt_interrupt_to_thread
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.globl rt_hw_context_switch_interrupt
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rt_hw_context_switch_interrupt:
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ldr r2, =rt_thread_switch_interrupt_flag
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ldr r3, [r2]
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cmp r3, #1
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beq _reswitch
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mov r3, #1 @ set rt_thread_switch_interrupt_flag to 1
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str r3, [r2]
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ldr r2, =rt_interrupt_from_thread @ set rt_interrupt_from_thread
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str r0, [r2]
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_reswitch:
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ldr r2, =rt_interrupt_to_thread @ set rt_interrupt_to_thread
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str r1, [r2]
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bx lr
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@@ -0,0 +1,117 @@
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;/*
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; * File : context_rvds.S
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; * This file is part of RT-Thread RTOS
|
||||
; * COPYRIGHT (C) 2006, RT-Thread Development Team
|
||||
; *
|
||||
; * This program is free software; you can redistribute it and/or modify
|
||||
; * it under the terms of the GNU General Public License as published by
|
||||
; * the Free Software Foundation; either version 2 of the License, or
|
||||
; * (at your option) any later version.
|
||||
; *
|
||||
; * This program is distributed in the hope that it will be useful,
|
||||
; * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
; * GNU General Public License for more details.
|
||||
; *
|
||||
; * You should have received a copy of the GNU General Public License along
|
||||
; * with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
; * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
; *
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||||
; * Change Logs:
|
||||
; * Date Author Notes
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||||
; * 2011-08-14 weety copy from mini2440
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; */
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NOINT EQU 0xc0 ; disable interrupt in psr
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AREA |.text|, CODE, READONLY, ALIGN=2
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ARM
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REQUIRE8
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PRESERVE8
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;/*
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; * rt_base_t rt_hw_interrupt_disable();
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; */
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rt_hw_interrupt_disable PROC
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EXPORT rt_hw_interrupt_disable
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MRS r0, cpsr
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ORR r1, r0, #NOINT
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MSR cpsr_c, r1
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BX lr
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ENDP
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;/*
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; * void rt_hw_interrupt_enable(rt_base_t level);
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; */
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rt_hw_interrupt_enable PROC
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EXPORT rt_hw_interrupt_enable
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MSR cpsr_c, r0
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BX lr
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ENDP
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;/*
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; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
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; * r0 --> from
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; * r1 --> to
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; */
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rt_hw_context_switch PROC
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EXPORT rt_hw_context_switch
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STMFD sp!, {lr} ; push pc (lr should be pushed in place of PC)
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||||
STMFD sp!, {r0-r12, lr} ; push lr & register file
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||||
MRS r4, cpsr
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STMFD sp!, {r4} ; push cpsr
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||||
MRS r4, spsr
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STMFD sp!, {r4} ; push spsr
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||||
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STR sp, [r0] ; store sp in preempted tasks TCB
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LDR sp, [r1] ; get new task stack pointer
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LDMFD sp!, {r4} ; pop new task spsr
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MSR spsr_cxsf, r4
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LDMFD sp!, {r4} ; pop new task cpsr
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MSR spsr_cxsf, r4
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LDMFD sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc
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ENDP
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;/*
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; * void rt_hw_context_switch_to(rt_uint32 to);
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; * r0 --> to
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; */
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rt_hw_context_switch_to PROC
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EXPORT rt_hw_context_switch_to
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LDR sp, [r0] ; get new task stack pointer
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LDMFD sp!, {r4} ; pop new task spsr
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MSR spsr_cxsf, r4
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LDMFD sp!, {r4} ; pop new task cpsr
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MSR cpsr_cxsf, r4
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LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc
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ENDP
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;/*
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; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
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; */
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IMPORT rt_thread_switch_interrupt_flag
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IMPORT rt_interrupt_from_thread
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IMPORT rt_interrupt_to_thread
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rt_hw_context_switch_interrupt PROC
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EXPORT rt_hw_context_switch_interrupt
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LDR r2, =rt_thread_switch_interrupt_flag
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LDR r3, [r2]
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CMP r3, #1
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BEQ _reswitch
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MOV r3, #1 ; set rt_thread_switch_interrupt_flag to 1
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STR r3, [r2]
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LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread
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STR r0, [r2]
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_reswitch
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LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
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STR r1, [r2]
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BX lr
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ENDP
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END
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@@ -0,0 +1,246 @@
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/*
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* File : cpu.c
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||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Develop Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-01-13 weety modified from mini2440
|
||||
*/
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#include <rthw.h>
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#include <rtthread.h>
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#define ICACHE_MASK (rt_uint32_t)(1 << 12)
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#define DCACHE_MASK (rt_uint32_t)(1 << 2)
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extern void machine_reset(void);
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extern void machine_shutdown(void);
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#ifdef __GNUC__
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rt_inline rt_uint32_t cp15_rd(void)
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{
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rt_uint32_t i;
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asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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return i;
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}
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rt_inline void cache_enable(rt_uint32_t bit)
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{
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__asm__ __volatile__( \
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"mrc p15,0,r0,c1,c0,0\n\t" \
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"orr r0,r0,%0\n\t" \
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"mcr p15,0,r0,c1,c0,0" \
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: \
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:"r" (bit) \
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:"memory");
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}
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rt_inline void cache_disable(rt_uint32_t bit)
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{
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__asm__ __volatile__( \
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"mrc p15,0,r0,c1,c0,0\n\t" \
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"bic r0,r0,%0\n\t" \
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"mcr p15,0,r0,c1,c0,0" \
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: \
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:"r" (bit) \
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:"memory");
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}
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#endif
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#ifdef __CC_ARM
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rt_inline rt_uint32_t cp15_rd(void)
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{
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rt_uint32_t i;
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__asm
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{
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mrc p15, 0, i, c1, c0, 0
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}
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return i;
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}
|
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|
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rt_inline void cache_enable(rt_uint32_t bit)
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{
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||||
rt_uint32_t value;
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__asm
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||||
{
|
||||
mrc p15, 0, value, c1, c0, 0
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||||
orr value, value, bit
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||||
mcr p15, 0, value, c1, c0, 0
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||||
}
|
||||
}
|
||||
|
||||
rt_inline void cache_disable(rt_uint32_t bit)
|
||||
{
|
||||
rt_uint32_t value;
|
||||
|
||||
__asm
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||||
{
|
||||
mrc p15, 0, value, c1, c0, 0
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bic value, value, bit
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mcr p15, 0, value, c1, c0, 0
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||||
}
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||||
}
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#endif
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||||
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||||
/**
|
||||
* enable I-Cache
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*
|
||||
*/
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||||
void rt_hw_cpu_icache_enable()
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||||
{
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||||
cache_enable(ICACHE_MASK);
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||||
}
|
||||
|
||||
/**
|
||||
* disable I-Cache
|
||||
*
|
||||
*/
|
||||
void rt_hw_cpu_icache_disable()
|
||||
{
|
||||
cache_disable(ICACHE_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* return the status of I-Cache
|
||||
*
|
||||
*/
|
||||
rt_base_t rt_hw_cpu_icache_status()
|
||||
{
|
||||
return (cp15_rd() & ICACHE_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* enable D-Cache
|
||||
*
|
||||
*/
|
||||
void rt_hw_cpu_dcache_enable()
|
||||
{
|
||||
cache_enable(DCACHE_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* disable D-Cache
|
||||
*
|
||||
*/
|
||||
void rt_hw_cpu_dcache_disable()
|
||||
{
|
||||
cache_disable(DCACHE_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* return the status of D-Cache
|
||||
*
|
||||
*/
|
||||
rt_base_t rt_hw_cpu_dcache_status()
|
||||
{
|
||||
return (cp15_rd() & DCACHE_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* reset cpu by dog's time-out
|
||||
*
|
||||
*/
|
||||
void rt_hw_cpu_reset()
|
||||
{
|
||||
|
||||
rt_kprintf("Restarting system...\n");
|
||||
machine_reset();
|
||||
|
||||
while(1); /* loop forever and wait for reset to happen */
|
||||
|
||||
/* NEVER REACHED */
|
||||
}
|
||||
|
||||
/**
|
||||
* shutdown CPU
|
||||
*
|
||||
*/
|
||||
void rt_hw_cpu_shutdown()
|
||||
{
|
||||
rt_uint32_t level;
|
||||
rt_kprintf("shutdown...\n");
|
||||
|
||||
level = rt_hw_interrupt_disable();
|
||||
machine_shutdown();
|
||||
while (level)
|
||||
{
|
||||
RT_ASSERT(0);
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef RT_USING_CPU_FFS
|
||||
/**
|
||||
* This function finds the first bit set (beginning with the least significant bit)
|
||||
* in value and return the index of that bit.
|
||||
*
|
||||
* Bits are numbered starting at 1 (the least significant bit). A return value of
|
||||
* zero from any of these functions means that the argument was zero.
|
||||
*
|
||||
* @return return the index of the first bit set. If value is 0, then this function
|
||||
* shall return 0.
|
||||
*/
|
||||
#if defined(__CC_ARM)
|
||||
int __rt_ffs(int value)
|
||||
{
|
||||
register rt_uint32_t x;
|
||||
|
||||
if (value == 0)
|
||||
return value;
|
||||
|
||||
__asm
|
||||
{
|
||||
rsb x, value, #0
|
||||
and x, x, value
|
||||
clz x, x
|
||||
rsb x, x, #32
|
||||
}
|
||||
|
||||
return x;
|
||||
}
|
||||
#elif defined(__IAR_SYSTEMS_ICC__)
|
||||
int __rt_ffs(int value)
|
||||
{
|
||||
if (value == 0)
|
||||
return value;
|
||||
|
||||
__ASM("RSB r4, r0, #0");
|
||||
__ASM("AND r4, r4, r0");
|
||||
__ASM("CLZ r4, r4");
|
||||
__ASM("RSB r0, r4, #32");
|
||||
}
|
||||
#elif defined(__GNUC__)
|
||||
int __rt_ffs(int value)
|
||||
{
|
||||
if (value == 0)
|
||||
return value;
|
||||
|
||||
value &= (-value);
|
||||
asm ("clz %0, %1": "=r"(value) :"r"(value));
|
||||
|
||||
return (32 - value);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
/*@}*/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,164 @@
|
||||
/*
|
||||
* File : mmu.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
*/
|
||||
|
||||
#ifndef __MMU_H__
|
||||
#define __MMU_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#define CACHE_LINE_SIZE 32
|
||||
|
||||
/*
|
||||
* Hardware page table definitions.
|
||||
*
|
||||
* + Level 1 descriptor (PGD)
|
||||
* - common
|
||||
*/
|
||||
#define PGD_TYPE_MASK (3 << 0)
|
||||
#define PGD_TYPE_FAULT (0 << 0)
|
||||
#define PGD_TYPE_TABLE (1 << 0)
|
||||
#define PGD_TYPE_SECT (2 << 0)
|
||||
#define PGD_BIT4 (1 << 4)
|
||||
#define PGD_DOMAIN(x) ((x) << 5)
|
||||
#define PGD_PROTECTION (1 << 9) /* ARMv5 */
|
||||
/*
|
||||
* - section
|
||||
*/
|
||||
#define PGD_SECT_BUFFERABLE (1 << 2)
|
||||
#define PGD_SECT_CACHEABLE (1 << 3)
|
||||
#define PGD_SECT_XN (1 << 4) /* ARMv6 */
|
||||
#define PGD_SECT_AP0 (1 << 10)
|
||||
#define PGD_SECT_AP1 (1 << 11)
|
||||
#define PGD_SECT_TEX(x) ((x) << 12) /* ARMv5 */
|
||||
#define PGD_SECT_APX (1 << 15) /* ARMv6 */
|
||||
#define PGD_SECT_S (1 << 16) /* ARMv6 */
|
||||
#define PGD_SECT_nG (1 << 17) /* ARMv6 */
|
||||
#define PGD_SECT_SUPER (1 << 18) /* ARMv6 */
|
||||
|
||||
#define PGD_SECT_UNCACHED (0)
|
||||
#define PGD_SECT_BUFFERED (PGD_SECT_BUFFERABLE)
|
||||
#define PGD_SECT_WT (PGD_SECT_CACHEABLE)
|
||||
#define PGD_SECT_WB (PGD_SECT_CACHEABLE | PGD_SECT_BUFFERABLE)
|
||||
#define PGD_SECT_MINICACHE (PGD_SECT_TEX(1) | PGD_SECT_CACHEABLE)
|
||||
#define PGD_SECT_WBWA (PGD_SECT_TEX(1) | PGD_SECT_CACHEABLE | PGD_SECT_BUFFERABLE)
|
||||
#define PGD_SECT_NONSHARED_DEV (PGD_SECT_TEX(2))
|
||||
|
||||
|
||||
/*
|
||||
* + Level 2 descriptor (PTE)
|
||||
* - common
|
||||
*/
|
||||
#define PTE_TYPE_MASK (3 << 0)
|
||||
#define PTE_TYPE_FAULT (0 << 0)
|
||||
#define PTE_TYPE_LARGE (1 << 0)
|
||||
#define PTE_TYPE_SMALL (2 << 0)
|
||||
#define PTE_TYPE_EXT (3 << 0) /* ARMv5 */
|
||||
#define PTE_BUFFERABLE (1 << 2)
|
||||
#define PTE_CACHEABLE (1 << 3)
|
||||
|
||||
/*
|
||||
* - extended small page/tiny page
|
||||
*/
|
||||
#define PTE_EXT_XN (1 << 0) /* ARMv6 */
|
||||
#define PTE_EXT_AP_MASK (3 << 4)
|
||||
#define PTE_EXT_AP0 (1 << 4)
|
||||
#define PTE_EXT_AP1 (2 << 4)
|
||||
#define PTE_EXT_AP_UNO_SRO (0 << 4)
|
||||
#define PTE_EXT_AP_UNO_SRW (PTE_EXT_AP0)
|
||||
#define PTE_EXT_AP_URO_SRW (PTE_EXT_AP1)
|
||||
#define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0)
|
||||
#define PTE_EXT_TEX(x) ((x) << 6) /* ARMv5 */
|
||||
#define PTE_EXT_APX (1 << 9) /* ARMv6 */
|
||||
#define PTE_EXT_SHARED (1 << 10) /* ARMv6 */
|
||||
#define PTE_EXT_NG (1 << 11) /* ARMv6 */
|
||||
|
||||
/*
|
||||
* - small page
|
||||
*/
|
||||
#define PTE_SMALL_AP_MASK (0xff << 4)
|
||||
#define PTE_SMALL_AP_UNO_SRO (0x00 << 4)
|
||||
#define PTE_SMALL_AP_UNO_SRW (0x55 << 4)
|
||||
#define PTE_SMALL_AP_URO_SRW (0xaa << 4)
|
||||
#define PTE_SMALL_AP_URW_SRW (0xff << 4)
|
||||
|
||||
/*
|
||||
* sector table properities
|
||||
*/
|
||||
#define SECT_CB (PGD_SECT_CACHEABLE|PGD_SECT_BUFFERABLE) //cache_on, write_back
|
||||
#define SECT_CNB (PGD_SECT_CACHEABLE) //cache_on, write_through
|
||||
#define SECT_NCB (PGD_SECT_BUFFERABLE) //cache_off,WR_BUF on
|
||||
#define SECT_NCNB (0 << 2) //cache_off,WR_BUF off
|
||||
|
||||
#define SECT_AP_RW (PGD_SECT_AP0|PGD_SECT_AP1) //supervisor=RW, user=RW
|
||||
#define SECT_AP_RO ((0 << 10)|(0 << 11)) //supervisor=RO, user=NO Access(SR=10)
|
||||
|
||||
#define SECT_RW_CB (SECT_AP_RW|PGD_DOMAIN(0)|PGD_SECT_WB|PGD_TYPE_SECT|PGD_BIT4) /* Read/Write, cache, write back */
|
||||
#define SECT_RW_CNB (SECT_AP_RW|PGD_DOMAIN(0)|PGD_SECT_WT|PGD_TYPE_SECT|PGD_BIT4) /* Read/Write, cache, write through */
|
||||
#define SECT_RW_NCNB (SECT_AP_RW|PGD_DOMAIN(0)|PGD_TYPE_SECT|PGD_BIT4) /* Read/Write without cache and write buffer */
|
||||
#define SECT_RW_FAULT (SECT_AP_RW|PGD_DOMAIN(1)|PGD_TYPE_SECT|PGD_BIT4) /* Read/Write without cache and write buffer */
|
||||
|
||||
#define SECT_RO_CB (SECT_AP_RO|PGD_DOMAIN(0)|PGD_SECT_WB|PGD_TYPE_SECT|PGD_BIT4) /* Read Only, cache, write back */
|
||||
#define SECT_RO_CNB (SECT_AP_RO|PGD_DOMAIN(0)|PGD_SECT_WT|PGD_TYPE_SECT|PGD_BIT4) /* Read Only, cache, write through */
|
||||
#define SECT_RO_NCNB (SECT_AP_RO|PGD_DOMAIN(0)|PGD_TYPE_SECT|PGD_BIT4) /* Read Only without cache and write buffer */
|
||||
#define SECT_RO_FAULT (SECT_AP_RO|PGD_DOMAIN(1)|PGD_TYPE_SECT|PGD_BIT4) /* Read Only without cache and write buffer */
|
||||
|
||||
#define SECT_TO_PAGE (PGD_DOMAIN(0)|PGD_TYPE_TABLE|PGD_BIT4) /* Level 2 descriptor (PTE) entry properity */
|
||||
|
||||
/*
|
||||
* page table properities
|
||||
*/
|
||||
#define PAGE_CB (PTE_BUFFERABLE|PTE_CACHEABLE) //cache_on, write_back
|
||||
#define PAGE_CNB (PTE_CACHEABLE) //cache_on, write_through
|
||||
#define PAGE_NCB (PTE_BUFFERABLE) //cache_off,WR_BUF on
|
||||
#define PAGE_NCNB (0 << 2) //cache_off,WR_BUF off
|
||||
|
||||
#define PAGE_AP_RW PTE_SMALL_AP_URW_SRW //supervisor=RW, user=RW
|
||||
#define PAGE_AP_RO PTE_SMALL_AP_UNO_SRO //supervisor=RO, user=NO Access(SR=10)
|
||||
|
||||
#define PAGE_RW_CB (PAGE_AP_RW|PAGE_CB|PTE_TYPE_SMALL) /* Read/Write, cache, write back */
|
||||
#define PAGE_RW_CNB (PAGE_AP_RW|PAGE_CNB|PTE_TYPE_SMALL) /* Read/Write, cache, write through */
|
||||
#define PAGE_RW_NCNB (PAGE_AP_RW|PTE_TYPE_SMALL) /* Read/Write without cache and write buffer */
|
||||
#define PAGE_RW_FAULT (PAGE_AP_RW|PTE_TYPE_SMALL) /* Read/Write without cache and write buffer */
|
||||
|
||||
|
||||
#define PAGE_RO_CB (PAGE_AP_RO|PAGE_CB|PTE_TYPE_SMALL) /* Read Only, cache, write back */
|
||||
#define PAGE_RO_CNB (PAGE_AP_RO|PAGE_CNB|PTE_TYPE_SMALL) /* Read Only, cache, write through */
|
||||
#define PAGE_RO_NCNB (PAGE_AP_RO|PTE_TYPE_SMALL) /* Read Only without cache and write buffer */
|
||||
#define PAGE_RO_FAULT (PAGE_AP_RO|PTE_TYPE_SMALL) /* Read Only without cache and write buffer */
|
||||
|
||||
struct mem_desc {
|
||||
rt_uint32_t vaddr_start;
|
||||
rt_uint32_t vaddr_end;
|
||||
rt_uint32_t paddr_start;
|
||||
rt_uint32_t sect_attr; /* when page mapped */
|
||||
rt_uint32_t page_attr; /* only sector mapped valid */
|
||||
rt_uint32_t mapped_mode;
|
||||
#define SECT_MAPPED 0
|
||||
#define PAGE_MAPPED 1
|
||||
};
|
||||
|
||||
|
||||
void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size);
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,79 @@
|
||||
/*
|
||||
* File : stack.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-01-13 weety
|
||||
*/
|
||||
#include <rtthread.h>
|
||||
|
||||
/*****************************/
|
||||
/* CPU Mode */
|
||||
/*****************************/
|
||||
#define USERMODE 0x10
|
||||
#define FIQMODE 0x11
|
||||
#define IRQMODE 0x12
|
||||
#define SVCMODE 0x13
|
||||
#define ABORTMODE 0x17
|
||||
#define UNDEFMODE 0x1b
|
||||
#define MODEMASK 0x1f
|
||||
#define NOINT 0xc0
|
||||
|
||||
/**
|
||||
* This function will initialize thread stack
|
||||
*
|
||||
* @param tentry the entry of thread
|
||||
* @param parameter the parameter of entry
|
||||
* @param stack_addr the beginning stack address
|
||||
* @param texit the function will be called when thread exit
|
||||
*
|
||||
* @return stack address
|
||||
*/
|
||||
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
|
||||
rt_uint8_t *stack_addr, void *texit)
|
||||
{
|
||||
rt_uint32_t *stk;
|
||||
|
||||
stk = (rt_uint32_t*)stack_addr;
|
||||
*(stk) = (rt_uint32_t)tentry; /* entry point */
|
||||
*(--stk) = (rt_uint32_t)texit; /* lr */
|
||||
*(--stk) = 0; /* r12 */
|
||||
*(--stk) = 0; /* r11 */
|
||||
*(--stk) = 0; /* r10 */
|
||||
*(--stk) = 0; /* r9 */
|
||||
*(--stk) = 0; /* r8 */
|
||||
*(--stk) = 0; /* r7 */
|
||||
*(--stk) = 0; /* r6 */
|
||||
*(--stk) = 0; /* r5 */
|
||||
*(--stk) = 0; /* r4 */
|
||||
*(--stk) = 0; /* r3 */
|
||||
*(--stk) = 0; /* r2 */
|
||||
*(--stk) = 0; /* r1 */
|
||||
*(--stk) = (rt_uint32_t)parameter; /* r0 : argument */
|
||||
|
||||
/* cpsr */
|
||||
if ((rt_uint32_t)tentry & 0x01)
|
||||
*(--stk) = SVCMODE | 0x20; /* thumb mode */
|
||||
else
|
||||
*(--stk) = SVCMODE; /* arm mode */
|
||||
|
||||
/* return task's current stack address */
|
||||
return (rt_uint8_t *)stk;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user