mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-03-26 17:00:00 +08:00
Re-normalizing the repo
This commit is contained in:
Ming, Bai
@@ -57,11 +57,11 @@ extern "C" {
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#define AT91C_TC2_IER (AT91_REG(0xFFFA00A4)) /* TC2 Interrupt Enable Register */
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#define AT91C_TC2_SR (AT91_REG(0xFFFA00A0)) /* TC2 Status Register */
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/* ========== Register definition for PITC peripheral ========== */
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#define AT91C_PITC_PIVR (AT91_REG(0xFFFFFD38)) /* PITC Period Interval Value Register */
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#define AT91C_PITC_PISR (AT91_REG(0xFFFFFD34)) /* PITC Period Interval Status Register */
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#define AT91C_PITC_PIIR (AT91_REG(0xFFFFFD3C)) /* PITC Period Interval Image Register */
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#define AT91C_PITC_PIMR (AT91_REG(0xFFFFFD30)) /* PITC Period Interval Mode Register */
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/* ========== Register definition for PITC peripheral ========== */
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#define AT91C_PITC_PIVR (AT91_REG(0xFFFFFD38)) /* PITC Period Interval Value Register */
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#define AT91C_PITC_PISR (AT91_REG(0xFFFFFD34)) /* PITC Period Interval Status Register */
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#define AT91C_PITC_PIIR (AT91_REG(0xFFFFFD3C)) /* PITC Period Interval Image Register */
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#define AT91C_PITC_PIMR (AT91_REG(0xFFFFFD30)) /* PITC Period Interval Mode Register */
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/* ========== Register definition for UDP peripheral ========== */
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#define AT91C_UDP_NUM (AT91_REG(0xFFFB0000)) /* UDP Frame Number Register */
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@@ -240,86 +240,86 @@ extern "C" {
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#define AT91C_PMC_IDR (AT91_REG(0xFFFFFC64)) /* PMC Interrupt Disable Register */
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#define AT91C_PMC_SR (AT91_REG(0xFFFFFC68)) /* PMC Status Register */
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#define AT91C_PMC_IMR (AT91_REG(0xFFFFFC6C)) /* PMC Interrupt Mask Register */
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// ========== Register definition for PDC_SPI1 peripheral ==========
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#define AT91C_SPI1_RNPR (AT91_REG(0xFFFE4110)) // (PDC_SPI1) Receive Next Pointer Register
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#define AT91C_SPI1_TPR (AT91_REG(0xFFFE4108)) // (PDC_SPI1) Transmit Pointer Register
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#define AT91C_SPI1_RPR (AT91_REG(0xFFFE4100)) // (PDC_SPI1) Receive Pointer Register
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#define AT91C_SPI1_PTSR (AT91_REG(0xFFFE4124)) // (PDC_SPI1) PDC Transfer Status Register
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#define AT91C_SPI1_RCR (AT91_REG(0xFFFE4104)) // (PDC_SPI1) Receive Counter Register
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#define AT91C_SPI1_TCR (AT91_REG(0xFFFE410C)) // (PDC_SPI1) Transmit Counter Register
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#define AT91C_SPI1_RNCR (AT91_REG(0xFFFE4114)) // (PDC_SPI1) Receive Next Counter Register
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#define AT91C_SPI1_TNCR (AT91_REG(0xFFFE411C)) // (PDC_SPI1) Transmit Next Counter Register
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#define AT91C_SPI1_TNPR (AT91_REG(0xFFFE4118)) // (PDC_SPI1) Transmit Next Pointer Register
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#define AT91C_SPI1_PTCR (AT91_REG(0xFFFE4120)) // (PDC_SPI1) PDC Transfer Control Register
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// ========== Register definition for SPI1 peripheral ==========
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#define AT91C_SPI1_CSR (AT91_REG(0xFFFE4030)) // (SPI1) Chip Select Register
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#define AT91C_SPI1_IDR (AT91_REG(0xFFFE4018)) // (SPI1) Interrupt Disable Register
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#define AT91C_SPI1_SR (AT91_REG(0xFFFE4010)) // (SPI1) Status Register
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#define AT91C_SPI1_RDR (AT91_REG(0xFFFE4008)) // (SPI1) Receive Data Register
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#define AT91C_SPI1_CR (AT91_REG(0xFFFE4000)) // (SPI1) Control Register
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#define AT91C_SPI1_IMR (AT91_REG(0xFFFE401C)) // (SPI1) Interrupt Mask Register
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#define AT91C_SPI1_IER (AT91_REG(0xFFFE4014)) // (SPI1) Interrupt Enable Register
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#define AT91C_SPI1_TDR (AT91_REG(0xFFFE400C)) // (SPI1) Transmit Data Register
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#define AT91C_SPI1_MR (AT91_REG(0xFFFE4004)) // (SPI1) Mode Register
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// ========== Register definition for PDC_SPI0 peripheral ==========
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#define AT91C_SPI0_PTCR (AT91_REG(0xFFFE0120)) // (PDC_SPI0) PDC Transfer Control Register
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#define AT91C_SPI0_TNPR (AT91_REG(0xFFFE0118)) // (PDC_SPI0) Transmit Next Pointer Register
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#define AT91C_SPI0_RNPR (AT91_REG(0xFFFE0110)) // (PDC_SPI0) Receive Next Pointer Register
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#define AT91C_SPI0_TPR (AT91_REG(0xFFFE0108)) // (PDC_SPI0) Transmit Pointer Register
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#define AT91C_SPI0_RPR (AT91_REG(0xFFFE0100)) // (PDC_SPI0) Receive Pointer Register
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#define AT91C_SPI0_PTSR (AT91_REG(0xFFFE0124)) // (PDC_SPI0) PDC Transfer Status Register
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#define AT91C_SPI0_TNCR (AT91_REG(0xFFFE011C)) // (PDC_SPI0) Transmit Next Counter Register
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#define AT91C_SPI0_RNCR (AT91_REG(0xFFFE0114)) // (PDC_SPI0) Receive Next Counter Register
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#define AT91C_SPI0_TCR (AT91_REG(0xFFFE010C)) // (PDC_SPI0) Transmit Counter Register
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#define AT91C_SPI0_RCR (AT91_REG(0xFFFE0104)) // (PDC_SPI0) Receive Counter Register
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// ========== Register definition for SPI0 peripheral ==========
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#define AT91C_SPI0_CSR (AT91_REG(0xFFFE0030)) // (SPI0) Chip Select Register
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#define AT91C_SPI0_IDR (AT91_REG(0xFFFE0018)) // (SPI0) Interrupt Disable Register
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#define AT91C_SPI0_SR (AT91_REG(0xFFFE0010)) // (SPI0) Status Register
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#define AT91C_SPI0_RDR (AT91_REG(0xFFFE0008)) // (SPI0) Receive Data Register
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#define AT91C_SPI0_CR (AT91_REG(0xFFFE0000)) // (SPI0) Control Register
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#define AT91C_SPI0_IMR (AT91_REG(0xFFFE001C)) // (SPI0) Interrupt Mask Register
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#define AT91C_SPI0_IER (AT91_REG(0xFFFE0014)) // (SPI0) Interrupt Enable Register
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#define AT91C_SPI0_TDR (AT91_REG(0xFFFE000C)) // (SPI0) Transmit Data Register
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#define AT91C_SPI0_MR (AT91_REG(0xFFFE0004)) // (SPI0) Mode Register
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/******************************************************************************/
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/* PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 */
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/******************************************************************************/
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#define AT91C_ID_FIQ ( 0) /* Advanced Interrupt Controller (FIQ) */
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#define AT91C_ID_SYS ( 1) /* System Peripheral */
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#define AT91C_ID_PIOA ( 2) /* Parallel IO Controller A */
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#define AT91C_ID_PIOB ( 3) /* Parallel IO Controller B */
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#define AT91C_ID_SPI0 ( 4) /* Serial Peripheral Interface 0 */
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#define AT91C_ID_SPI1 ( 5) /* Serial Peripheral Interface 1 */
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#define AT91C_ID_US0 ( 6) /* USART 0 */
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#define AT91C_ID_US1 ( 7) /* USART 1 */
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#define AT91C_ID_SSC ( 8) /* Serial Synchronous Controller */
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#define AT91C_ID_TWI ( 9) /* Two-Wire Interface */
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#define AT91C_ID_PWMC (10) /* PWM Controller */
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#define AT91C_ID_UDP (11) /* USB Device Port */
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#define AT91C_ID_TC0 (12) /* Timer Counter 0 */
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#define AT91C_ID_TC1 (13) /* Timer Counter 1 */
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#define AT91C_ID_TC2 (14) /* Timer Counter 2 */
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#define AT91C_ID_CAN (15) /* Control Area Network Controller */
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#define AT91C_ID_EMAC (16) /* Ethernet MAC */
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#define AT91C_ID_ADC (17) /* Analog-to-Digital Converter */
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#define AT91C_ID_AES (18) /* Advanced Encryption Standard 128-bit */
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#define AT91C_ID_TDES (19) /* Triple Data Encryption Standard */
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#define AT91C_ID_20_Reserved (20) /* Reserved */
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#define AT91C_ID_21_Reserved (21) /* Reserved */
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#define AT91C_ID_22_Reserved (22) /* Reserved */
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#define AT91C_ID_23_Reserved (23) /* Reserved */
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#define AT91C_ID_24_Reserved (24) /* Reserved */
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#define AT91C_ID_25_Reserved (25) /* Reserved */
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#define AT91C_ID_26_Reserved (26) /* Reserved */
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#define AT91C_ID_27_Reserved (27) /* Reserved */
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#define AT91C_ID_28_Reserved (28) /* Reserved */
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#define AT91C_ID_29_Reserved (29) /* Reserved */
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#define AT91C_ID_IRQ0 (30) /* Advanced Interrupt Controller (IRQ0) */
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#define AT91C_ID_IRQ1 (31) /* Advanced Interrupt Controller (IRQ1) */
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#define AT91C_ALL_INT (0xC00FFFFF) /* ALL VALID INTERRUPTS */
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// ========== Register definition for PDC_SPI1 peripheral ==========
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#define AT91C_SPI1_RNPR (AT91_REG(0xFFFE4110)) // (PDC_SPI1) Receive Next Pointer Register
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#define AT91C_SPI1_TPR (AT91_REG(0xFFFE4108)) // (PDC_SPI1) Transmit Pointer Register
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#define AT91C_SPI1_RPR (AT91_REG(0xFFFE4100)) // (PDC_SPI1) Receive Pointer Register
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#define AT91C_SPI1_PTSR (AT91_REG(0xFFFE4124)) // (PDC_SPI1) PDC Transfer Status Register
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#define AT91C_SPI1_RCR (AT91_REG(0xFFFE4104)) // (PDC_SPI1) Receive Counter Register
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#define AT91C_SPI1_TCR (AT91_REG(0xFFFE410C)) // (PDC_SPI1) Transmit Counter Register
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#define AT91C_SPI1_RNCR (AT91_REG(0xFFFE4114)) // (PDC_SPI1) Receive Next Counter Register
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#define AT91C_SPI1_TNCR (AT91_REG(0xFFFE411C)) // (PDC_SPI1) Transmit Next Counter Register
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#define AT91C_SPI1_TNPR (AT91_REG(0xFFFE4118)) // (PDC_SPI1) Transmit Next Pointer Register
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#define AT91C_SPI1_PTCR (AT91_REG(0xFFFE4120)) // (PDC_SPI1) PDC Transfer Control Register
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// ========== Register definition for SPI1 peripheral ==========
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#define AT91C_SPI1_CSR (AT91_REG(0xFFFE4030)) // (SPI1) Chip Select Register
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#define AT91C_SPI1_IDR (AT91_REG(0xFFFE4018)) // (SPI1) Interrupt Disable Register
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#define AT91C_SPI1_SR (AT91_REG(0xFFFE4010)) // (SPI1) Status Register
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#define AT91C_SPI1_RDR (AT91_REG(0xFFFE4008)) // (SPI1) Receive Data Register
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#define AT91C_SPI1_CR (AT91_REG(0xFFFE4000)) // (SPI1) Control Register
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#define AT91C_SPI1_IMR (AT91_REG(0xFFFE401C)) // (SPI1) Interrupt Mask Register
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#define AT91C_SPI1_IER (AT91_REG(0xFFFE4014)) // (SPI1) Interrupt Enable Register
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#define AT91C_SPI1_TDR (AT91_REG(0xFFFE400C)) // (SPI1) Transmit Data Register
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#define AT91C_SPI1_MR (AT91_REG(0xFFFE4004)) // (SPI1) Mode Register
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// ========== Register definition for PDC_SPI0 peripheral ==========
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#define AT91C_SPI0_PTCR (AT91_REG(0xFFFE0120)) // (PDC_SPI0) PDC Transfer Control Register
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#define AT91C_SPI0_TNPR (AT91_REG(0xFFFE0118)) // (PDC_SPI0) Transmit Next Pointer Register
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#define AT91C_SPI0_RNPR (AT91_REG(0xFFFE0110)) // (PDC_SPI0) Receive Next Pointer Register
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#define AT91C_SPI0_TPR (AT91_REG(0xFFFE0108)) // (PDC_SPI0) Transmit Pointer Register
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#define AT91C_SPI0_RPR (AT91_REG(0xFFFE0100)) // (PDC_SPI0) Receive Pointer Register
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#define AT91C_SPI0_PTSR (AT91_REG(0xFFFE0124)) // (PDC_SPI0) PDC Transfer Status Register
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#define AT91C_SPI0_TNCR (AT91_REG(0xFFFE011C)) // (PDC_SPI0) Transmit Next Counter Register
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#define AT91C_SPI0_RNCR (AT91_REG(0xFFFE0114)) // (PDC_SPI0) Receive Next Counter Register
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#define AT91C_SPI0_TCR (AT91_REG(0xFFFE010C)) // (PDC_SPI0) Transmit Counter Register
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#define AT91C_SPI0_RCR (AT91_REG(0xFFFE0104)) // (PDC_SPI0) Receive Counter Register
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// ========== Register definition for SPI0 peripheral ==========
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#define AT91C_SPI0_CSR (AT91_REG(0xFFFE0030)) // (SPI0) Chip Select Register
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#define AT91C_SPI0_IDR (AT91_REG(0xFFFE0018)) // (SPI0) Interrupt Disable Register
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#define AT91C_SPI0_SR (AT91_REG(0xFFFE0010)) // (SPI0) Status Register
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#define AT91C_SPI0_RDR (AT91_REG(0xFFFE0008)) // (SPI0) Receive Data Register
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#define AT91C_SPI0_CR (AT91_REG(0xFFFE0000)) // (SPI0) Control Register
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#define AT91C_SPI0_IMR (AT91_REG(0xFFFE001C)) // (SPI0) Interrupt Mask Register
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#define AT91C_SPI0_IER (AT91_REG(0xFFFE0014)) // (SPI0) Interrupt Enable Register
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#define AT91C_SPI0_TDR (AT91_REG(0xFFFE000C)) // (SPI0) Transmit Data Register
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#define AT91C_SPI0_MR (AT91_REG(0xFFFE0004)) // (SPI0) Mode Register
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/******************************************************************************/
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/* PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 */
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/******************************************************************************/
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#define AT91C_ID_FIQ ( 0) /* Advanced Interrupt Controller (FIQ) */
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#define AT91C_ID_SYS ( 1) /* System Peripheral */
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#define AT91C_ID_PIOA ( 2) /* Parallel IO Controller A */
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#define AT91C_ID_PIOB ( 3) /* Parallel IO Controller B */
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#define AT91C_ID_SPI0 ( 4) /* Serial Peripheral Interface 0 */
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#define AT91C_ID_SPI1 ( 5) /* Serial Peripheral Interface 1 */
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#define AT91C_ID_US0 ( 6) /* USART 0 */
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#define AT91C_ID_US1 ( 7) /* USART 1 */
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#define AT91C_ID_SSC ( 8) /* Serial Synchronous Controller */
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#define AT91C_ID_TWI ( 9) /* Two-Wire Interface */
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#define AT91C_ID_PWMC (10) /* PWM Controller */
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#define AT91C_ID_UDP (11) /* USB Device Port */
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#define AT91C_ID_TC0 (12) /* Timer Counter 0 */
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#define AT91C_ID_TC1 (13) /* Timer Counter 1 */
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#define AT91C_ID_TC2 (14) /* Timer Counter 2 */
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#define AT91C_ID_CAN (15) /* Control Area Network Controller */
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#define AT91C_ID_EMAC (16) /* Ethernet MAC */
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#define AT91C_ID_ADC (17) /* Analog-to-Digital Converter */
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#define AT91C_ID_AES (18) /* Advanced Encryption Standard 128-bit */
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#define AT91C_ID_TDES (19) /* Triple Data Encryption Standard */
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#define AT91C_ID_20_Reserved (20) /* Reserved */
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#define AT91C_ID_21_Reserved (21) /* Reserved */
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#define AT91C_ID_22_Reserved (22) /* Reserved */
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#define AT91C_ID_23_Reserved (23) /* Reserved */
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#define AT91C_ID_24_Reserved (24) /* Reserved */
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#define AT91C_ID_25_Reserved (25) /* Reserved */
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#define AT91C_ID_26_Reserved (26) /* Reserved */
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#define AT91C_ID_27_Reserved (27) /* Reserved */
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#define AT91C_ID_28_Reserved (28) /* Reserved */
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#define AT91C_ID_29_Reserved (29) /* Reserved */
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#define AT91C_ID_IRQ0 (30) /* Advanced Interrupt Controller (IRQ0) */
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#define AT91C_ID_IRQ1 (31) /* Advanced Interrupt Controller (IRQ1) */
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#define AT91C_ALL_INT (0xC00FFFFF) /* ALL VALID INTERRUPTS */
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#define MCK 48054857
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@@ -1,16 +1,16 @@
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from building import *
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cwd = GetCurrentDir()
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src = Glob('*.c')
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# remove no need file.
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if GetDepend('RT_USING_LWIP') == False:
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SrcRemove(src, 'sam7x_emac.c')
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if GetDepend('RT_USING_DFS') == False:
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SrcRemove(src, 'ssd.c')
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CPPPATH = [cwd]
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group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
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Return('group')
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from building import *
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cwd = GetCurrentDir()
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src = Glob('*.c')
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# remove no need file.
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if GetDepend('RT_USING_LWIP') == False:
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SrcRemove(src, 'sam7x_emac.c')
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if GetDepend('RT_USING_DFS') == False:
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SrcRemove(src, 'ssd.c')
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CPPPATH = [cwd]
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group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
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Return('group')
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@@ -1,156 +1,156 @@
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/*
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ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.
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|
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This file is part of ChibiOS/RT.
|
||||
|
||||
ChibiOS/RT is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS/RT is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
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||||
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||||
/*
|
||||
* Parts of this file are borrowed by the Linux include file linux/mii.h:
|
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* Copyright (C) 1996, 1999, 2001 David S. Miller (davem@redhat.com)
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*/
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||||
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#ifndef _MII_H_
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#define _MII_H_
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/* Generic MII registers. */
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||||
#define MII_BMCR 0x00 /* Basic mode control register */
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#define MII_BMSR 0x01 /* Basic mode status register */
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#define MII_PHYSID1 0x02 /* PHYS ID 1 */
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#define MII_PHYSID2 0x03 /* PHYS ID 2 */
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#define MII_ADVERTISE 0x04 /* Advertisement control reg */
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#define MII_LPA 0x05 /* Link partner ability reg */
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||||
#define MII_EXPANSION 0x06 /* Expansion register */
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#define MII_CTRL1000 0x09 /* 1000BASE-T control */
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#define MII_STAT1000 0x0a /* 1000BASE-T status */
|
||||
#define MII_ESTATUS 0x0f /* Extended Status */
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||||
#define MII_DCOUNTER 0x12 /* Disconnect counter */
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||||
#define MII_FCSCOUNTER 0x13 /* False carrier counter */
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#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
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#define MII_RERRCOUNTER 0x15 /* Receive error counter */
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#define MII_SREVISION 0x16 /* Silicon revision */
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#define MII_RESV1 0x17 /* Reserved... */
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#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
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#define MII_PHYADDR 0x19 /* PHY address */
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#define MII_RESV2 0x1a /* Reserved... */
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||||
#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
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||||
#define MII_NCONFIG 0x1c /* Network interface config */
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||||
|
||||
/* Basic mode control register. */
|
||||
#define BMCR_RESV 0x003f /* Unused... */
|
||||
#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
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||||
#define BMCR_CTST 0x0080 /* Collision test */
|
||||
#define BMCR_FULLDPLX 0x0100 /* Full duplex */
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||||
#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
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||||
#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */
|
||||
#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */
|
||||
#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
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||||
#define BMCR_SPEED100 0x2000 /* Select 100Mbps */
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||||
#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
|
||||
#define BMCR_RESET 0x8000 /* Reset the DP83840 */
|
||||
|
||||
/* Basic mode status register. */
|
||||
#define BMSR_ERCAP 0x0001 /* Ext-reg capability */
|
||||
#define BMSR_JCD 0x0002 /* Jabber detected */
|
||||
#define BMSR_LSTATUS 0x0004 /* Link status */
|
||||
#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
|
||||
#define BMSR_RFAULT 0x0010 /* Remote fault detected */
|
||||
#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
|
||||
#define BMSR_RESV 0x00c0 /* Unused... */
|
||||
#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */
|
||||
#define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
|
||||
#define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */
|
||||
#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
|
||||
#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
|
||||
#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
|
||||
#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
|
||||
#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
|
||||
|
||||
/* Advertisement control register. */
|
||||
#define ADVERTISE_SLCT 0x001f /* Selector bits */
|
||||
#define ADVERTISE_CSMA 0x0001 /* Only selector supported */
|
||||
#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
|
||||
#define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */
|
||||
#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
|
||||
#define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */
|
||||
#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
|
||||
#define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */
|
||||
#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
|
||||
#define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */
|
||||
#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
|
||||
#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */
|
||||
#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */
|
||||
#define ADVERTISE_RESV 0x1000 /* Unused... */
|
||||
#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
|
||||
#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
|
||||
#define ADVERTISE_NPAGE 0x8000 /* Next page bit */
|
||||
|
||||
#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
|
||||
ADVERTISE_CSMA)
|
||||
#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
|
||||
ADVERTISE_100HALF | ADVERTISE_100FULL)
|
||||
|
||||
/* Link partner ability register. */
|
||||
#define LPA_SLCT 0x001f /* Same as advertise selector */
|
||||
#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
|
||||
#define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */
|
||||
#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
|
||||
#define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */
|
||||
#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
|
||||
#define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */
|
||||
#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
|
||||
#define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym*/
|
||||
#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */
|
||||
#define LPA_PAUSE_CAP 0x0400 /* Can pause */
|
||||
#define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */
|
||||
#define LPA_RESV 0x1000 /* Unused... */
|
||||
#define LPA_RFAULT 0x2000 /* Link partner faulted */
|
||||
#define LPA_LPACK 0x4000 /* Link partner acked us */
|
||||
#define LPA_NPAGE 0x8000 /* Next page bit */
|
||||
|
||||
#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
|
||||
#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
|
||||
|
||||
/* Expansion register for auto-negotiation. */
|
||||
#define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */
|
||||
#define EXPANSION_LCWP 0x0002 /* Got new RX page code word */
|
||||
#define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */
|
||||
#define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */
|
||||
#define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */
|
||||
#define EXPANSION_RESV 0xffe0 /* Unused... */
|
||||
|
||||
#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */
|
||||
#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */
|
||||
|
||||
/* N-way test register. */
|
||||
#define NWAYTEST_RESV1 0x00ff /* Unused... */
|
||||
#define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */
|
||||
#define NWAYTEST_RESV2 0xfe00 /* Unused... */
|
||||
|
||||
/* 1000BASE-T Control register */
|
||||
#define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */
|
||||
#define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */
|
||||
|
||||
/* 1000BASE-T Status register */
|
||||
#define LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */
|
||||
#define LPA_1000REMRXOK 0x1000 /* Link partner remote receiver status */
|
||||
#define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */
|
||||
#define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */
|
||||
|
||||
#define MII_DM9161_ID 0x0181b8a0
|
||||
#define MII_AM79C875_ID 0x00225540
|
||||
#define MII_MICREL_ID 0x00221610
|
||||
|
||||
#endif /* _MII_H_ */
|
||||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS/RT.
|
||||
|
||||
ChibiOS/RT is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS/RT is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Parts of this file are borrowed by the Linux include file linux/mii.h:
|
||||
* Copyright (C) 1996, 1999, 2001 David S. Miller (davem@redhat.com)
|
||||
*/
|
||||
|
||||
#ifndef _MII_H_
|
||||
#define _MII_H_
|
||||
|
||||
/* Generic MII registers. */
|
||||
#define MII_BMCR 0x00 /* Basic mode control register */
|
||||
#define MII_BMSR 0x01 /* Basic mode status register */
|
||||
#define MII_PHYSID1 0x02 /* PHYS ID 1 */
|
||||
#define MII_PHYSID2 0x03 /* PHYS ID 2 */
|
||||
#define MII_ADVERTISE 0x04 /* Advertisement control reg */
|
||||
#define MII_LPA 0x05 /* Link partner ability reg */
|
||||
#define MII_EXPANSION 0x06 /* Expansion register */
|
||||
#define MII_CTRL1000 0x09 /* 1000BASE-T control */
|
||||
#define MII_STAT1000 0x0a /* 1000BASE-T status */
|
||||
#define MII_ESTATUS 0x0f /* Extended Status */
|
||||
#define MII_DCOUNTER 0x12 /* Disconnect counter */
|
||||
#define MII_FCSCOUNTER 0x13 /* False carrier counter */
|
||||
#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
|
||||
#define MII_RERRCOUNTER 0x15 /* Receive error counter */
|
||||
#define MII_SREVISION 0x16 /* Silicon revision */
|
||||
#define MII_RESV1 0x17 /* Reserved... */
|
||||
#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
|
||||
#define MII_PHYADDR 0x19 /* PHY address */
|
||||
#define MII_RESV2 0x1a /* Reserved... */
|
||||
#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
|
||||
#define MII_NCONFIG 0x1c /* Network interface config */
|
||||
|
||||
/* Basic mode control register. */
|
||||
#define BMCR_RESV 0x003f /* Unused... */
|
||||
#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
|
||||
#define BMCR_CTST 0x0080 /* Collision test */
|
||||
#define BMCR_FULLDPLX 0x0100 /* Full duplex */
|
||||
#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
|
||||
#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */
|
||||
#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */
|
||||
#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
|
||||
#define BMCR_SPEED100 0x2000 /* Select 100Mbps */
|
||||
#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
|
||||
#define BMCR_RESET 0x8000 /* Reset the DP83840 */
|
||||
|
||||
/* Basic mode status register. */
|
||||
#define BMSR_ERCAP 0x0001 /* Ext-reg capability */
|
||||
#define BMSR_JCD 0x0002 /* Jabber detected */
|
||||
#define BMSR_LSTATUS 0x0004 /* Link status */
|
||||
#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
|
||||
#define BMSR_RFAULT 0x0010 /* Remote fault detected */
|
||||
#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
|
||||
#define BMSR_RESV 0x00c0 /* Unused... */
|
||||
#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */
|
||||
#define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
|
||||
#define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */
|
||||
#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
|
||||
#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
|
||||
#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
|
||||
#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
|
||||
#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
|
||||
|
||||
/* Advertisement control register. */
|
||||
#define ADVERTISE_SLCT 0x001f /* Selector bits */
|
||||
#define ADVERTISE_CSMA 0x0001 /* Only selector supported */
|
||||
#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
|
||||
#define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */
|
||||
#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
|
||||
#define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */
|
||||
#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
|
||||
#define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */
|
||||
#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
|
||||
#define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */
|
||||
#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
|
||||
#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */
|
||||
#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */
|
||||
#define ADVERTISE_RESV 0x1000 /* Unused... */
|
||||
#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
|
||||
#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
|
||||
#define ADVERTISE_NPAGE 0x8000 /* Next page bit */
|
||||
|
||||
#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
|
||||
ADVERTISE_CSMA)
|
||||
#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
|
||||
ADVERTISE_100HALF | ADVERTISE_100FULL)
|
||||
|
||||
/* Link partner ability register. */
|
||||
#define LPA_SLCT 0x001f /* Same as advertise selector */
|
||||
#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
|
||||
#define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */
|
||||
#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
|
||||
#define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */
|
||||
#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
|
||||
#define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */
|
||||
#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
|
||||
#define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym*/
|
||||
#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */
|
||||
#define LPA_PAUSE_CAP 0x0400 /* Can pause */
|
||||
#define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */
|
||||
#define LPA_RESV 0x1000 /* Unused... */
|
||||
#define LPA_RFAULT 0x2000 /* Link partner faulted */
|
||||
#define LPA_LPACK 0x4000 /* Link partner acked us */
|
||||
#define LPA_NPAGE 0x8000 /* Next page bit */
|
||||
|
||||
#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
|
||||
#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
|
||||
|
||||
/* Expansion register for auto-negotiation. */
|
||||
#define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */
|
||||
#define EXPANSION_LCWP 0x0002 /* Got new RX page code word */
|
||||
#define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */
|
||||
#define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */
|
||||
#define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */
|
||||
#define EXPANSION_RESV 0xffe0 /* Unused... */
|
||||
|
||||
#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */
|
||||
#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */
|
||||
|
||||
/* N-way test register. */
|
||||
#define NWAYTEST_RESV1 0x00ff /* Unused... */
|
||||
#define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */
|
||||
#define NWAYTEST_RESV2 0xfe00 /* Unused... */
|
||||
|
||||
/* 1000BASE-T Control register */
|
||||
#define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */
|
||||
#define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */
|
||||
|
||||
/* 1000BASE-T Status register */
|
||||
#define LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */
|
||||
#define LPA_1000REMRXOK 0x1000 /* Link partner remote receiver status */
|
||||
#define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */
|
||||
#define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */
|
||||
|
||||
#define MII_DM9161_ID 0x0181b8a0
|
||||
#define MII_AM79C875_ID 0x00225540
|
||||
#define MII_MICREL_ID 0x00221610
|
||||
|
||||
#endif /* _MII_H_ */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,109 +1,109 @@
|
||||
#ifndef __SAM7X_EMAC_H__
|
||||
#define __SAM7X_EMAC_H__
|
||||
|
||||
//#define DM9161
|
||||
#define RTL8201
|
||||
|
||||
#ifdef DM9161
|
||||
#define AT91C_PHY_ADDR 31
|
||||
#else
|
||||
#define AT91C_PHY_ADDR 0x01
|
||||
#endif
|
||||
|
||||
#define MII_DM9161_ID 0x0181b8a0
|
||||
#define MII_RTL8201_ID 0x82010000
|
||||
|
||||
/* RTL8201 PHY registers. */
|
||||
#define PHY_REG_BMCR 0x00 /* Basic mode control register */
|
||||
#define PHY_REG_BMSR 0x01 /* Basic mode status register */
|
||||
#define PHY_REG_PHYID1 0x02 /* PHY ID identifier #1 */
|
||||
#define PHY_REG_PHYID2 0x03 /* PHY ID identifier #2 */
|
||||
#define PHY_REG_ANAR 0x04 /* AutoNegotiation Advertisement reg.*/
|
||||
#define PHY_REG_ANLPAR 0x05 /* AutoNeg.Link partner ability reg */
|
||||
#define PHY_REG_ANER 0x06 /* AutoNeg. Expansion register */
|
||||
#define PHY_REG_DSCR 0x10 /* DAVICOM Specified Config. reg */
|
||||
#define PHY_REG_DSCSR 0x11 /* DAVICOM Spec. Config/Status reg */
|
||||
#define PHY_REG_10BTCSR 0x12 /* 10BASET Configuration/Status reg */
|
||||
#define PHY_REG_PWDOR 0x13 /* Power Down Control Register */
|
||||
#define PHY_REG_SCR 0x14 /* Specified Config register */
|
||||
#define PHY_REG_INTR 0x15 /* Interrupt register */
|
||||
#define PHY_REG_RECR 0x16 /* Receive Error Counter register */
|
||||
#define PHY_REG_DISCR 0x17 /* Disconnect Counter register */
|
||||
#define PHY_REG_RLSR 0x18 /* Hardware Reset Latch State reg. */
|
||||
|
||||
/* Basic mode control register. */
|
||||
#define BMCR_RESV 0x007f /* Unused... */
|
||||
#define BMCR_CTST 0x0080 /* Collision test */
|
||||
#define BMCR_FULLDPLX 0x0100 /* Full duplex */
|
||||
#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
|
||||
#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */
|
||||
#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */
|
||||
#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
|
||||
#define BMCR_SPEED100 0x2000 /* Select 100Mbps */
|
||||
#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
|
||||
#define BMCR_RESET 0x8000 /* Reset the DP83840 */
|
||||
|
||||
#define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */
|
||||
#define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */
|
||||
#define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */
|
||||
#define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */
|
||||
#define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */
|
||||
|
||||
/* Basic mode status register. */
|
||||
#define BMSR_ERCAP 0x0001 /* Ext-reg capability */
|
||||
#define BMSR_JCD 0x0002 /* Jabber detected */
|
||||
#define BMSR_LINKST 0x0004 /* Link status */
|
||||
#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
|
||||
#define BMSR_RFAULT 0x0010 /* Remote fault detected */
|
||||
#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
|
||||
#define BMSR_MIIPRESUP 0x0040 /* MII Frame Preamble Suppression */
|
||||
#define BMSR_RESV 0x0780 /* Unused... */
|
||||
#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
|
||||
#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
|
||||
#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
|
||||
#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
|
||||
#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
|
||||
|
||||
#define RxDESC_FLAG_ADDR_MASK 0xfffffffc
|
||||
#define RxDESC_FLAG_WARP 0x00000002
|
||||
#define RxDESC_FLAG_OWNSHIP 0x00000001
|
||||
#define RxDESC_STATUS_BUF_SIZE (0x00000FFF)
|
||||
#define RxDESC_STATUS_FRAME_START (1U << 14)
|
||||
#define RxDESC_STATUS_FRAME_END (1U << 15)
|
||||
|
||||
#define TxDESC_STATUS_BUF_SIZE (0x000007FF)
|
||||
#define TxDESC_STATUS_LAST_BUF (1U << 15)
|
||||
#define TxDESC_STATUS_NO_CRC (1U << 16)
|
||||
#define TxDESC_STATUS_BUF_EXHAUSTED (1U << 27)
|
||||
#define TxDESC_STATUS_Tx_UNDERRUN (1U << 28)
|
||||
#define TxDESC_STATUS_Tx_ERROR (1U << 29)
|
||||
#define TxDESC_STATUS_WRAP (1U << 30)
|
||||
#define TxDESC_STATUS_USED (1U << 31)
|
||||
|
||||
//----dm9161 define----
|
||||
#define DM9161_RESET (1 << 15) // 1= Software Reset; 0=Normal Operation
|
||||
#define DM9161_LOOPBACK (1 << 14) // 1=loopback Enabled; 0=Normal Operation
|
||||
#define DM9161_SPEED_SELECT (1 << 13) // 1=100Mbps; 0=10Mbps
|
||||
#define DM9161_AUTONEG (1 << 12) // Auto-negotiation Enable
|
||||
#define DM9161_POWER_DOWN (1 << 11) // 1=Power down 0=Normal operation
|
||||
#define DM9161_ISOLATE (1 << 10) // 1 = Isolates 0 = Normal operation
|
||||
#define DM9161_RESTART_AUTONEG (1 << 9) // 1 = Restart auto-negotiation 0 = Normal operation
|
||||
#define DM9161_DUPLEX_MODE (1 << 8) // 1 = Full duplex operation 0 = Normal operation
|
||||
#define DM9161_COLLISION_TEST (1 << 7) // 1 = Collision test enabled 0 = Normal operation
|
||||
|
||||
#define DM9161_NP (1 << 15) // Next page Indication
|
||||
#define DM9161_ACK (1 << 14) // Acknowledge
|
||||
#define DM9161_RF (1 << 13) // Remote Fault
|
||||
// Reserved 12 to 11 // Write as 0, ignore on read
|
||||
#define DM9161_FCS (1 << 10) // Flow Control Support
|
||||
#define DM9161_T4 (1 << 9) // 100BASE-T4 Support
|
||||
#define DM9161_TX_FDX (1 << 8) // 100BASE-TX Full Duplex Support
|
||||
#define DM9161_TX_HDX (1 << 7) // 100BASE-TX Support
|
||||
#define DM9161_10_FDX (1 << 6) // 10BASE-T Full Duplex Support
|
||||
#define DM9161_10_HDX (1 << 5) // 10BASE-T Support
|
||||
// Selector 4 to 0 // Protocol Selection Bits
|
||||
#define DM9161_AN_IEEE_802_3 0x0001
|
||||
|
||||
int sam7xether_register(char *name);
|
||||
|
||||
#endif
|
||||
#ifndef __SAM7X_EMAC_H__
|
||||
#define __SAM7X_EMAC_H__
|
||||
|
||||
//#define DM9161
|
||||
#define RTL8201
|
||||
|
||||
#ifdef DM9161
|
||||
#define AT91C_PHY_ADDR 31
|
||||
#else
|
||||
#define AT91C_PHY_ADDR 0x01
|
||||
#endif
|
||||
|
||||
#define MII_DM9161_ID 0x0181b8a0
|
||||
#define MII_RTL8201_ID 0x82010000
|
||||
|
||||
/* RTL8201 PHY registers. */
|
||||
#define PHY_REG_BMCR 0x00 /* Basic mode control register */
|
||||
#define PHY_REG_BMSR 0x01 /* Basic mode status register */
|
||||
#define PHY_REG_PHYID1 0x02 /* PHY ID identifier #1 */
|
||||
#define PHY_REG_PHYID2 0x03 /* PHY ID identifier #2 */
|
||||
#define PHY_REG_ANAR 0x04 /* AutoNegotiation Advertisement reg.*/
|
||||
#define PHY_REG_ANLPAR 0x05 /* AutoNeg.Link partner ability reg */
|
||||
#define PHY_REG_ANER 0x06 /* AutoNeg. Expansion register */
|
||||
#define PHY_REG_DSCR 0x10 /* DAVICOM Specified Config. reg */
|
||||
#define PHY_REG_DSCSR 0x11 /* DAVICOM Spec. Config/Status reg */
|
||||
#define PHY_REG_10BTCSR 0x12 /* 10BASET Configuration/Status reg */
|
||||
#define PHY_REG_PWDOR 0x13 /* Power Down Control Register */
|
||||
#define PHY_REG_SCR 0x14 /* Specified Config register */
|
||||
#define PHY_REG_INTR 0x15 /* Interrupt register */
|
||||
#define PHY_REG_RECR 0x16 /* Receive Error Counter register */
|
||||
#define PHY_REG_DISCR 0x17 /* Disconnect Counter register */
|
||||
#define PHY_REG_RLSR 0x18 /* Hardware Reset Latch State reg. */
|
||||
|
||||
/* Basic mode control register. */
|
||||
#define BMCR_RESV 0x007f /* Unused... */
|
||||
#define BMCR_CTST 0x0080 /* Collision test */
|
||||
#define BMCR_FULLDPLX 0x0100 /* Full duplex */
|
||||
#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
|
||||
#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */
|
||||
#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */
|
||||
#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
|
||||
#define BMCR_SPEED100 0x2000 /* Select 100Mbps */
|
||||
#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
|
||||
#define BMCR_RESET 0x8000 /* Reset the DP83840 */
|
||||
|
||||
#define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */
|
||||
#define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */
|
||||
#define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */
|
||||
#define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */
|
||||
#define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */
|
||||
|
||||
/* Basic mode status register. */
|
||||
#define BMSR_ERCAP 0x0001 /* Ext-reg capability */
|
||||
#define BMSR_JCD 0x0002 /* Jabber detected */
|
||||
#define BMSR_LINKST 0x0004 /* Link status */
|
||||
#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
|
||||
#define BMSR_RFAULT 0x0010 /* Remote fault detected */
|
||||
#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
|
||||
#define BMSR_MIIPRESUP 0x0040 /* MII Frame Preamble Suppression */
|
||||
#define BMSR_RESV 0x0780 /* Unused... */
|
||||
#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
|
||||
#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
|
||||
#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
|
||||
#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
|
||||
#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
|
||||
|
||||
#define RxDESC_FLAG_ADDR_MASK 0xfffffffc
|
||||
#define RxDESC_FLAG_WARP 0x00000002
|
||||
#define RxDESC_FLAG_OWNSHIP 0x00000001
|
||||
#define RxDESC_STATUS_BUF_SIZE (0x00000FFF)
|
||||
#define RxDESC_STATUS_FRAME_START (1U << 14)
|
||||
#define RxDESC_STATUS_FRAME_END (1U << 15)
|
||||
|
||||
#define TxDESC_STATUS_BUF_SIZE (0x000007FF)
|
||||
#define TxDESC_STATUS_LAST_BUF (1U << 15)
|
||||
#define TxDESC_STATUS_NO_CRC (1U << 16)
|
||||
#define TxDESC_STATUS_BUF_EXHAUSTED (1U << 27)
|
||||
#define TxDESC_STATUS_Tx_UNDERRUN (1U << 28)
|
||||
#define TxDESC_STATUS_Tx_ERROR (1U << 29)
|
||||
#define TxDESC_STATUS_WRAP (1U << 30)
|
||||
#define TxDESC_STATUS_USED (1U << 31)
|
||||
|
||||
//----dm9161 define----
|
||||
#define DM9161_RESET (1 << 15) // 1= Software Reset; 0=Normal Operation
|
||||
#define DM9161_LOOPBACK (1 << 14) // 1=loopback Enabled; 0=Normal Operation
|
||||
#define DM9161_SPEED_SELECT (1 << 13) // 1=100Mbps; 0=10Mbps
|
||||
#define DM9161_AUTONEG (1 << 12) // Auto-negotiation Enable
|
||||
#define DM9161_POWER_DOWN (1 << 11) // 1=Power down 0=Normal operation
|
||||
#define DM9161_ISOLATE (1 << 10) // 1 = Isolates 0 = Normal operation
|
||||
#define DM9161_RESTART_AUTONEG (1 << 9) // 1 = Restart auto-negotiation 0 = Normal operation
|
||||
#define DM9161_DUPLEX_MODE (1 << 8) // 1 = Full duplex operation 0 = Normal operation
|
||||
#define DM9161_COLLISION_TEST (1 << 7) // 1 = Collision test enabled 0 = Normal operation
|
||||
|
||||
#define DM9161_NP (1 << 15) // Next page Indication
|
||||
#define DM9161_ACK (1 << 14) // Acknowledge
|
||||
#define DM9161_RF (1 << 13) // Remote Fault
|
||||
// Reserved 12 to 11 // Write as 0, ignore on read
|
||||
#define DM9161_FCS (1 << 10) // Flow Control Support
|
||||
#define DM9161_T4 (1 << 9) // 100BASE-T4 Support
|
||||
#define DM9161_TX_FDX (1 << 8) // 100BASE-TX Full Duplex Support
|
||||
#define DM9161_TX_HDX (1 << 7) // 100BASE-TX Support
|
||||
#define DM9161_10_FDX (1 << 6) // 10BASE-T Full Duplex Support
|
||||
#define DM9161_10_HDX (1 << 5) // 10BASE-T Support
|
||||
// Selector 4 to 0 // Protocol Selection Bits
|
||||
#define DM9161_AN_IEEE_802_3 0x0001
|
||||
|
||||
int sam7xether_register(char *name);
|
||||
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,6 +1,6 @@
|
||||
#ifndef __SPI_SD_H__
|
||||
#define __SPI_SD_H__
|
||||
|
||||
void rt_hw_sdcard_init(void);
|
||||
|
||||
#endif
|
||||
#ifndef __SPI_SD_H__
|
||||
#define __SPI_SD_H__
|
||||
|
||||
void rt_hw_sdcard_init(void);
|
||||
|
||||
#endif
|
||||
|
||||
@@ -80,22 +80,22 @@ static void rt_hw_serial_isr(int irqno)
|
||||
{
|
||||
rt_base_t level;
|
||||
struct rt_device* device;
|
||||
struct rt_at91serial* serial = RT_NULL;
|
||||
struct rt_at91serial* serial = RT_NULL;
|
||||
|
||||
#ifdef RT_USING_UART1
|
||||
if (irqno == AT91C_ID_US0)
|
||||
{
|
||||
/* serial 1 */
|
||||
serial = &serial1;
|
||||
}
|
||||
#endif
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_UART2
|
||||
if (irqno == AT91C_ID_US1)
|
||||
{
|
||||
/* serial 2 */
|
||||
serial = &serial2;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
|
||||
|
||||
@@ -1,14 +1,14 @@
|
||||
#ifndef __RT_SERIAL_H__
|
||||
#define __RT_SERIAL_H__
|
||||
|
||||
#ifndef AT91C_BASE_US0
|
||||
#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address
|
||||
#endif
|
||||
|
||||
#ifndef AT91C_BASE_US1
|
||||
#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address
|
||||
#endif
|
||||
|
||||
#ifndef __RT_SERIAL_H__
|
||||
#define __RT_SERIAL_H__
|
||||
|
||||
#ifndef AT91C_BASE_US0
|
||||
#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address
|
||||
#endif
|
||||
|
||||
#ifndef AT91C_BASE_US1
|
||||
#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address
|
||||
#endif
|
||||
|
||||
#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) /* US RXRDY Interrupt */
|
||||
#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) /* US TXRDY Interrupt */
|
||||
#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) /* US Reset Receiver */
|
||||
@@ -52,5 +52,5 @@
|
||||
#define MCK 48054857
|
||||
#define BR 115200 /* Baud Rate */
|
||||
#define BRD (MCK/16/BR) /* Baud Rate Divisor */
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user