mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-09-23 04:04:15 +08:00
port rt-thread to NEC V850E
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@779 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
dzzxzz
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#include "macdefs.inc"
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name OS_Core
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COMMON INTVEC:CODE
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;********************************************************************
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;
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; function:
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; description: Trap 0x10 vector used for context switch
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; Right now, all TRAPs to $1x are trated the same way
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;
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org 50h
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jr OSCtxSW
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;********************************************************************
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;
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; function:
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; description: Timer 40 compare match interrupt used for system
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; tick interrupt
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;
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org 0x220
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jr OSTickIntr
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org 0x0520
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jr uarta1_int_r
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RSEG CODE(1)
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EXTERN rt_thread_switch_interrput_flag
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EXTERN rt_interrupt_from_thread
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EXTERN rt_interrupt_to_thread
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EXTERN rt_interrupt_enter
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EXTERN rt_interrupt_leave
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EXTERN rt_tick_increase
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EXTERN uarta1_receive_handler
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PUBLIC rt_hw_interrupt_disable
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PUBLIC rt_hw_interrupt_enable
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PUBLIC rt_hw_context_switch_to
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PUBLIC rt_hw_context_switch
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PUBLIC rt_hw_context_switch_interrupt
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PUBLIC OSCtxSW
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PUBLIC OS_Restore_CPU_Context
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rt_hw_interrupt_disable:
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stsr psw, r1
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di
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jmp [lp]
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rt_hw_interrupt_enable:
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ldsr r1, psw
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jmp [lp]
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OS_Restore_CPU_Context:
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mov sp, ep
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sld.w 4[ep], r2
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sld.w 8[ep], r5
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sld.w 12[ep],r6
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sld.w 16[ep],r7
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sld.w 20[ep],r8
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sld.w 24[ep],r9
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sld.w 28[ep],r10
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sld.w 32[ep],r11
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sld.w 36[ep],r12
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sld.w 40[ep],r13
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sld.w 44[ep],r14
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sld.w 48[ep],r15
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sld.w 52[ep],r16
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;See what was the latest interruption (trap or interrupt)
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stsr ecr, r17 ;Move ecr to r17
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mov 0x050,r1
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cmp r1, r17 ;If latest break was due to TRAP, set EP
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be _SetEP
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_ClrEP:
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mov 0x20, r17 ;Set only ID
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ldsr r17, psw
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;Restore caller address
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sld.w 56[ep], r1
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ldsr r1, EIPC
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;Restore PSW
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sld.w 60[ep], r1
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andi 0xffdf,r1,r1
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ldsr r1, EIPSW
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sld.w 0[ep], r1
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dispose (8+(4*14)),{r23,r24,r25,r26,r27,r28,r29,r30,r31}
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;Return from interrupt starts new task!
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reti
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_SetEP:
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mov 0x60, r17 ;Set both EIPC and ID bits
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ldsr r17, psw
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;Restore caller address
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sld.w 56[ep], r1
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ldsr r1, EIPC
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;Restore PSW
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sld.w 60[ep], r1
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andi 0xffdf,r1,r1
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ldsr r1, EIPSW
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sld.w 0[ep], r1
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dispose (8+(4*14)),{r23,r24,r25,r26,r27,r28,r29,r30,r31}
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;Return from interrupt starts new task!
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reti
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//rseg CODE:CODE
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//public rt_hw_context_switch_to
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rt_hw_context_switch_to:
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;Load stack pointer of the task to run
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ld.w 0[r1], sp ;load sp from struct
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;Restore all Processor registers from stack and return from interrupt
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jr OS_Restore_CPU_Context
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OSCtxSW:
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SAVE_CPU_CTX ;Save all CPU registers
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mov rt_thread_switch_interrput_flag, r1
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ld.w 0[r1],r5
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cmp 0, r5
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be exit
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mov 0, r5
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st.b r5, 0[r1]
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mov rt_interrupt_from_thread, r21
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ld.w 0[r21], r21
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st.w sp, 0[r21]
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mov rt_interrupt_to_thread, r1
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ld.w 0[r1], r1
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ld.w 0[r1], sp
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exit:
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;Restore all Processor registers from stack and return from interrupt
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jr OS_Restore_CPU_Context
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;R1 -> rt_interrupt_from_thread
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;R5 -> rt_interrupt_to_thread
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rt_hw_context_switch:
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mov rt_thread_switch_interrput_flag, r8
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ld.w 0[r8],r9
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cmp 1, r9
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be jump1
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;mov rt_thread_switch_interrput_flag, r1
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mov 1, r9
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st.b r9, 0[r8]
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mov rt_interrupt_from_thread, r10
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st.w r1, 0[r10]
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jump1
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mov rt_interrupt_to_thread, r11
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st.w r5, 0[r11]
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trap 0x10
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jmp [lp]
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rt_hw_context_switch_interrupt:
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mov rt_thread_switch_interrput_flag, r8
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ld.w 0[r8],r9
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cmp 1, r9
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be jump2
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;mov rt_thread_switch_interrput_flag, r1
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mov 1, r9
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st.b r9, 0[r8]
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mov rt_interrupt_from_thread, r10
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st.w r1, 0[r10]
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jump2
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mov rt_interrupt_to_thread, r11
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st.w r5, 0[r11]
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jmp [lp]
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rt_hw_context_switch_interrupt_do
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mov rt_thread_switch_interrput_flag, r8
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mov 0, r9
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st.b r9, 0[r8]
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mov rt_interrupt_from_thread, r21
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ld.w 0[r21], r21
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st.w sp, 0[r21]
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mov rt_interrupt_to_thread, r1
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ld.w 0[r1], r1
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ld.w 0[r1], sp
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jr OS_Restore_CPU_Context
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OSTickIntr:
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SAVE_CPU_CTX ;Save current task's registers
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jarl rt_interrupt_enter,lp
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jarl rt_tick_increase,lp
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jarl rt_interrupt_leave,lp
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mov rt_thread_switch_interrput_flag, r8
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ld.w 0[r8],r9
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cmp 1, r9
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be rt_hw_context_switch_interrupt_do
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jr OS_Restore_CPU_Context
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uarta1_int_r:
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SAVE_CPU_CTX ;Save current task's registers
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jarl rt_interrupt_enter,lp
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jarl uarta1_receive_handler,lp
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jarl rt_interrupt_leave,lp
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mov rt_thread_switch_interrput_flag, r8
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ld.w 0[r8],r9
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cmp 1, r9
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be rt_hw_context_switch_interrupt_do
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jr OS_Restore_CPU_Context
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END
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@@ -0,0 +1,22 @@
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/*
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* File : interrupt.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2009, RT-Thread Development Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2010-06-29 lgnq the first version
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*
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* For : NEC V850E
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* Toolchain : IAR Embedded Workbench for V850 v3.71
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*/
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#include <rtthread.h>
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rt_uint32_t rt_interrupt_from_thread;
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rt_uint32_t rt_interrupt_to_thread;
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rt_uint32_t rt_thread_switch_interrput_flag;
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@@ -0,0 +1,125 @@
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;
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; These are the macros used by the v850 port of the uCOS/II.
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;
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;********************************************************************
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; function:
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; description:
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; --- Modifies ----------------------------------------------
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; IO :
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; Mem:
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; CPU:
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; --- Uses --------------------------------------------------
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; IO :
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; Mem:
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; --- Input -------------------------------------------------
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; --- Output ------------------------------------------------
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; --- Notes -------------------------------------------------
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;====================================================================
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SAVE_CPU_CTX MACRO
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;Save all registers on entry (r3 is the stack pointer)
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prepare {r23,r24,r25,r26,r27,r28,r29,r30,r31},(8+(4*14)) ;Add 8 bytes for 2 more registers
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mov sp, ep
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sst.w r1, 0[ep]
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sst.w r2, 4[ep]
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sst.w r5, 8[ep]
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sst.w r6, 12[ep]
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sst.w r7, 16[ep]
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sst.w r8, 20[ep]
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sst.w r9, 24[ep]
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sst.w r10, 28[ep]
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sst.w r11, 32[ep]
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sst.w r12, 36[ep]
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sst.w r13, 40[ep]
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sst.w r14, 44[ep]
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sst.w r15, 48[ep]
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sst.w r16, 52[ep]
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;Save caller's PC
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stsr EIPC, r1
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sst.w r1, 56[ep]
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;Save caller's PSW
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stsr EIPSW, r1
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sst.w r1, 60[ep]
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ENDMAC
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;********************************************************************
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; function:
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; description:
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; --- Modifies ----------------------------------------------
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; IO :
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; Mem:
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; CPU:
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; --- Uses --------------------------------------------------
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; IO :
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; Mem:
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; --- Input -------------------------------------------------
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; --- Output ------------------------------------------------
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; --- Notes -------------------------------------------------
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;====================================================================
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SAVE_SP MACRO
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;Save stack pointer on OSTCBCur->OSTCBStkPtr (OSTCBStkPtr=0)
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mov OSTCBCur, r21
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ld.w 0[r21], r21
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st.w sp, 0[r21]
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ENDMAC
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;********************************************************************
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; function:
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; description:
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; --- Modifies ----------------------------------------------
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; IO :
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; Mem:
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; CPU:
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; --- Uses --------------------------------------------------
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; IO :
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; Mem:
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; --- Input -------------------------------------------------
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; --- Output ------------------------------------------------
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; --- Notes -------------------------------------------------
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;====================================================================
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ISR_ENTRY MACRO
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LOCAL _DontSaveSP
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;Save all CPU registers according to the standard stack frame
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SAVE_CPU_CTX
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mov OSIntNesting, r1 ;Increment OSNesting by one
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LD.BU 0[r1],r2
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add 1, r2
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ST.B r2, 0[r1]
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cmp 1, r2 ;If OSNesting==1 save SP in current TCB
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bne _DontSaveSP
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SAVE_SP
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_DontSaveSP:
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ENDMAC
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;********************************************************************
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; function:
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; description:
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; --- Modifies ----------------------------------------------
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; IO :
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; Mem:
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; CPU:
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; --- Uses --------------------------------------------------
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; IO :
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; Mem:
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; --- Input -------------------------------------------------
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; --- Output ------------------------------------------------
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; --- Notes -------------------------------------------------
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;====================================================================
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ISR_EXIT MACRO
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jarl OSIntExit, lp ;Call OSIntExit()
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jr OS_Restore_CPU_Context ;Restore processors registers and execute RETI
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ENDMAC
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@@ -0,0 +1,61 @@
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/*
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* File : stack.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2009, RT-Thread Development Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2010-06-29 lgnq the first version
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*
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* For : NEC V850E
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* Toolchain : IAR Embedded Workbench for V850 v3.71
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*/
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#include <rtthread.h>
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/**
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* This function will initialize thread stack
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*
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* @param tentry the entry of thread
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* @param parameter the parameter of entry
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* @param stack_addr the beginning stack address
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* @param texit the function will be called when thread exit
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*
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* @return stack address
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*/
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rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
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{
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rt_uint32_t *stk;
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stk = (rt_uint32_t *)stack_addr; /* Load stack pointer */
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*(--stk) = (rt_uint32_t) 0x23232323; /* r23 */
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*(--stk) = (rt_uint32_t) 0x24242424; /* r24 */
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*(--stk) = (rt_uint32_t) 0x25252525; /* r25 */
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*(--stk) = (rt_uint32_t) 0x26262626; /* r26 */
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*(--stk) = (rt_uint32_t) 0x27272727; /* r27 */
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*(--stk) = (rt_uint32_t) 0x28282828; /* r28 */
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*(--stk) = (rt_uint32_t) 0x29292929; /* r29 */
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*(--stk) = (rt_uint32_t) 0x30303030; /* r30 */
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*(--stk) = (rt_uint32_t) 0x31313131; /* r31 */
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*(--stk) = (rt_uint32_t) 0x00000000; /* Task PSW = Interrupts enabled */
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*(--stk) = (rt_uint32_t) tentry; /* Task's PC */
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*(--stk) = (rt_uint32_t) 0x16161616; /* r16 */
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*(--stk) = (rt_uint32_t) 0x15151515; /* r15 */
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*(--stk) = (rt_uint32_t) 0x14141414; /* r14 */
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*(--stk) = (rt_uint32_t) 0x13131313; /* r13 */
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*(--stk) = (rt_uint32_t) 0x12121212; /* r12 */
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*(--stk) = (rt_uint32_t) 0x11111111; /* r11 */
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*(--stk) = (rt_uint32_t) 0x10101010; /* r10 */
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*(--stk) = (rt_uint32_t) 0x09090909; /* r9 */
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*(--stk) = (rt_uint32_t) 0x08080808; /* r8 */
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*(--stk) = (rt_uint32_t) 0x07070707; /* r7 */
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*(--stk) = (rt_uint32_t) 0x06060606; /* r6 */
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*(--stk) = (rt_uint32_t) 0x05050505; /* r5 */
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*(--stk) = (rt_uint32_t) 0x02020202; /* r2 */
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*(--stk) = (rt_uint32_t) parameter; /* r1 */
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return ((rt_uint8_t *)stk);
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}
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