diff --git a/.gitee/PULL_REQUEST_TEMPLATE.en.md b/.gitee/PULL_REQUEST_TEMPLATE.en.md index b621e6f035..9d72f03307 100644 --- a/.gitee/PULL_REQUEST_TEMPLATE.en.md +++ b/.gitee/PULL_REQUEST_TEMPLATE.en.md @@ -27,3 +27,4 @@ As part of this pull request, I've considered the following: - [ ] All modifications to BSP are justified and do not affect other components or BSPs. - [ ] I've commented appropriately where code is tricky. - [ ] Code in this PR is of high quality. +- [ ] This PR complies with [RT-Thread code specification](../documentation/coding_style_en.txt) diff --git a/.gitee/PULL_REQUEST_TEMPLATE.zh-CN.md b/.gitee/PULL_REQUEST_TEMPLATE.zh-CN.md index a992458ef4..b64136d96d 100644 --- a/.gitee/PULL_REQUEST_TEMPLATE.zh-CN.md +++ b/.gitee/PULL_REQUEST_TEMPLATE.zh-CN.md @@ -27,3 +27,4 @@ - [ ] 所有变更均有原因及合理的，并且不会影响到其他软件组件代码或 - [ ] 对难懂代码均提供对应的注释 - [ ] 本拉取/合并请求代码是高质量的 +- [ ] 本拉取/合并符合[RT-Thread代码规范](../documentation/coding_style_cn.md) diff --git a/.gitee/PULL_REQUEST_TEMPLATE.zh-TW.md b/.gitee/PULL_REQUEST_TEMPLATE.zh-TW.md index 9788e1a39f..2bbf94f5fc 100644 --- a/.gitee/PULL_REQUEST_TEMPLATE.zh-TW.md +++ b/.gitee/PULL_REQUEST_TEMPLATE.zh-TW.md @@ -27,3 +27,4 @@ - [ ] 所有變更均有原因及合理的，並且不會影響到其他軟件組件代碼或 - [ ] 對難懂代碼均提供對應的註釋 - [ ] 本拉取/合並請求代碼是高質量的 +- [ ] 本拉取/合並符合[RT-Thread代碼規範](../documentation/coding_style_cn.md) diff --git a/.github/PULL_REQUEST_TEMPLATE.md b/.github/PULL_REQUEST_TEMPLATE.md index 59f2b88a13..1f092851b0 100644 --- a/.github/PULL_REQUEST_TEMPLATE.md +++ b/.github/PULL_REQUEST_TEMPLATE.md @@ -31,3 +31,4 @@ The following content must not be changed in the submitted PR message. Otherwise - [ ] 所有变更均有原因及合理的，并且不会影响到其他软件组件代码或BSP All modifications are justified and not affect other components or BSP - [ ] 对难懂代码均提供对应的注释 I've commented appropriately where code is tricky - [ ] 本拉取/合并请求代码是高质量的 Code in this PR is of high quality +- [ ] 本拉取/合并符合[RT-Thread代码规范](../documentation/coding_style_cn.md) This PR complies with [RT-Thread code specification](../documentation/coding_style_en.txt) diff --git a/.github/workflows/file_check.yml b/.github/workflows/file_check.yml index 90576c4eda..f1f1994af8 100644 --- a/.github/workflows/file_check.yml +++ b/.github/workflows/file_check.yml @@ -16,5 +16,5 @@ jobs: - name: Check Format and License shell: bash run: | - pip install click chardet + pip install click chardet PyYaml python tools/file_check.py check 'https://github.com/RT-Thread/rt-thread' 'master' diff --git a/.ignore_format.yml b/.ignore_format.yml new file mode 100644 index 0000000000..4a0e8bbec7 --- /dev/null +++ b/.ignore_format.yml @@ -0,0 +1,9 @@ +# files format check exclude path, please follow the instructions below to modify; +# If you need to exclude an entire folder, add the folder path in dir_path; +# If you need to exclude a file, add the path to the file in file_path. + +file_path: +- bsp/allwinner_tina/libcpu/cpu.c + +dir_path: +- tools \ No newline at end of file diff --git a/bsp/CME_M7/applications/application.c b/bsp/CME_M7/applications/application.c index 13526c5793..c5346448c3 100644 --- a/bsp/CME_M7/applications/application.c +++ b/bsp/CME_M7/applications/application.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2014, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -32,10 +28,10 @@ int rt_application_init() tid = rt_thread_create("init", rt_init_thread_entry, - RT_NULL, + RT_NULL, 2048, - RT_THREAD_PRIORITY_MAX/3, - 20); + RT_THREAD_PRIORITY_MAX/3, + 20); if (tid != RT_NULL) rt_thread_startup(tid); diff --git a/bsp/CME_M7/drivers/board.c b/bsp/CME_M7/drivers/board.c index 42ff994b4c..a9c81cdd0a 100644 --- a/bsp/CME_M7/drivers/board.c +++ b/bsp/CME_M7/drivers/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009-2014, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/CME_M7/drivers/board.h b/bsp/CME_M7/drivers/board.h index 8e7425674c..c622b546dd 100644 --- a/bsp/CME_M7/drivers/board.h +++ b/bsp/CME_M7/drivers/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009-2014, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -18,7 +14,7 @@ #include "cmem7_includes.h" //#include "cmem7_retarget.h" -#define SRAM_SIZE 64 // KB +#define SRAM_SIZE 64 // KB #define SRAM_END (0x20000000 + SRAM_SIZE * 1024) //#define RT_USING_UART0 diff --git a/bsp/allwinner_tina/libcpu/context_gcc.S b/bsp/allwinner_tina/libcpu/context_gcc.S index 5152618d24..c874b16b4b 100644 --- a/bsp/allwinner_tina/libcpu/context_gcc.S +++ b/bsp/allwinner_tina/libcpu/context_gcc.S @@ -1,21 +1,7 @@ ;/* -; * File : context_iar.S -; * This file is part of RT-Thread RTOS -; * COPYRIGHT (C) 2006, RT-Thread Development Team +; * Copyright (c) 2006-2021, RT-Thread Development Team ; * -; * This program is free software; you can redistribute it and/or modify -; * it under the terms of the GNU General Public License as published by -; * the Free Software Foundation; either version 2 of the License, or -; * (at your option) any later version. -; * -; * This program is distributed in the hope that it will be useful, -; * but WITHOUT ANY WARRANTY; without even the implied warranty of -; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; * GNU General Public License for more details. -; * -; * You should have received a copy of the GNU General Public License along -; * with this program; if not, write to the Free Software Foundation, Inc., -; * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +; * SPDX-License-Identifier: Apache-2.0 ; * ; * Change Logs: ; * Date Author Notes diff --git a/bsp/amebaz/libraries/smartconfig/inc/smartconfig.h b/bsp/amebaz/libraries/smartconfig/inc/smartconfig.h index b215e983c4..214c46f50f 100644 --- a/bsp/amebaz/libraries/smartconfig/inc/smartconfig.h +++ b/bsp/amebaz/libraries/smartconfig/inc/smartconfig.h @@ -1,21 +1,7 @@ /* - * File : smartconfig.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/asm9260t/applications/application.c b/bsp/asm9260t/applications/application.c index 18a9fbdf23..d60546ca76 100644 --- a/bsp/asm9260t/applications/application.c +++ b/bsp/asm9260t/applications/application.c @@ -1,25 +1,11 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version + * Date Author Notes + * 2011-01-13 weety first version * 2015-04-27 ArdaFu Port bsp from at91sam9260 to asm9260t */ diff --git a/bsp/asm9260t/drivers/board.c b/bsp/asm9260t/drivers/board.c index f3fc53c51a..652be94767 100644 --- a/bsp/asm9260t/drivers/board.c +++ b/bsp/asm9260t/drivers/board.c @@ -1,21 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2009 RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/asm9260t/drivers/board.h b/bsp/asm9260t/drivers/board.h index 0af63a9480..9682b68326 100644 --- a/bsp/asm9260t/drivers/board.h +++ b/bsp/asm9260t/drivers/board.h @@ -1,21 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/asm9260t/drivers/led.c b/bsp/asm9260t/drivers/led.c index e2d6d7a79d..80fd98fd07 100644 --- a/bsp/asm9260t/drivers/led.c +++ b/bsp/asm9260t/drivers/led.c @@ -1,21 +1,7 @@ /* - * File : led.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2015, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/asm9260t/drivers/led.h b/bsp/asm9260t/drivers/led.h index f2967bc92d..9836eff709 100644 --- a/bsp/asm9260t/drivers/led.h +++ b/bsp/asm9260t/drivers/led.h @@ -1,21 +1,7 @@ /* - * File : led.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/asm9260t/drivers/usart.c b/bsp/asm9260t/drivers/usart.c index 617e526afc..3a17f97b38 100644 --- a/bsp/asm9260t/drivers/usart.c +++ b/bsp/asm9260t/drivers/usart.c @@ -1,21 +1,7 @@ /* - * File : usart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -72,12 +58,12 @@ static rt_err_t asm_usart_configure(struct rt_serial_device *serial, RT_ASSERT(serial != RT_NULL); RT_ASSERT(cfg != RT_NULL); uart = (asm_uart_t *)serial->parent.user_data; - + Hw_UartDisable(uart->port); Hw_UartReset(uart->port); - - Hw_UartConfig(uart->port, cfg->baud_rate, cfg->data_bits, + + Hw_UartConfig(uart->port, cfg->baud_rate, cfg->data_bits, cfg->stop_bits, cfg->parity); Hw_UartEnable(uart->port); diff --git a/bsp/asm9260t/platform/gpio.c b/bsp/asm9260t/platform/gpio.c index 2a341dcdf5..8361a59589 100644 --- a/bsp/asm9260t/platform/gpio.c +++ b/bsp/asm9260t/platform/gpio.c @@ -1,27 +1,13 @@ /* - * File : interrupt.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2015-04-14 ArdaFu first version */ - + #include "asm9260t.h" #include "rtthread.h" diff --git a/bsp/asm9260t/platform/gpio.h b/bsp/asm9260t/platform/gpio.h index 26fccff477..f5480bb4e9 100644 --- a/bsp/asm9260t/platform/gpio.h +++ b/bsp/asm9260t/platform/gpio.h @@ -1,21 +1,7 @@ /* - * File : interrupt.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/asm9260t/platform/interrupt.c b/bsp/asm9260t/platform/interrupt.c index 6121203c23..76b18bc7a0 100644 --- a/bsp/asm9260t/platform/interrupt.c +++ b/bsp/asm9260t/platform/interrupt.c @@ -1,21 +1,7 @@ /* - * File : interrupt.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/asm9260t/platform/interrupt.h b/bsp/asm9260t/platform/interrupt.h index 85aa48f371..fba92d1f2c 100644 --- a/bsp/asm9260t/platform/interrupt.h +++ b/bsp/asm9260t/platform/interrupt.h @@ -1,21 +1,7 @@ /* - * File : interrupt.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -29,69 +15,69 @@ // IRQ Source -#define INT_ARM_COMMRX 0 -#define INT_ARM_COMMTX 1 -#define INT_RTC 2 -#define INT_GPIO0 3 -#define INT_GPIO1 4 -#define INT_GPIO2 5 -#define INT_GPIO3 6 -#define INT_GPIO4_IIS1 7 -#define INT_USB0 8 -#define INT_USB1 9 -#define INT_USB0_DMA 10 -#define INT_USB1_DMA 11 -#define INT_MAC 12 -#define INT_MAC_PMT 13 -#define INT_NAND 14 -#define INT_UART0 15 -#define INT_UART1 16 -#define INT_UART2 17 -#define INT_UART3 18 -#define INT_UART4 19 -#define INT_UART5 20 -#define INT_UART6 21 -#define INT_UART7 22 -#define INT_UART8 23 -#define INT_UART9 24 -#define INT_I2S0 25 -#define INT_I2C0 26 -#define INT_I2C1 27 -#define INT_CAMIF 28 -#define INT_TIMER0 29 -#define INT_TIMER1 30 -#define INT_TIMER2 31 -#define INT_TIMER3 32 -#define INT_ADC0 33 -#define INT_DAC0 34 -#define INT_USB0_RESUME_HOSTDISCONNECT 35 -#define INT_USB0_VBUSVALID 36 -#define INT_USB1_RESUME_HOSTDISCONNECT 37 -#define INT_USB1_VBUSVALID 38 -#define INT_DMA0_CH0 39 -#define INT_DMA0_CH1 40 -#define INT_DMA0_CH2 41 -#define INT_DMA0_CH3 42 -#define INT_DMA0_CH4 43 -#define INT_DMA0_CH5 44 -#define INT_DMA0_CH6 45 -#define INT_DMA0_CH7 46 -#define INT_DMA1_CH0 47 -#define INT_DMA1_CH1 48 -#define INT_DMA1_CH2 49 -#define INT_DMA1_CH3 50 -#define INT_DMA1_CH4 51 -#define INT_DMA1_CH5 52 -#define INT_DMA1_CH6 53 -#define INT_DMA1_CH7 54 -#define INT_WATCHDOG 55 -#define INT_CAN0 56 -#define INT_CAN1 57 -#define INT_QEI 58 -#define INT_MCPWM 59 -#define INT_SPI0 60 -#define INT_SPI1 61 -#define INT_QUADSPI0 62 +#define INT_ARM_COMMRX 0 +#define INT_ARM_COMMTX 1 +#define INT_RTC 2 +#define INT_GPIO0 3 +#define INT_GPIO1 4 +#define INT_GPIO2 5 +#define INT_GPIO3 6 +#define INT_GPIO4_IIS1 7 +#define INT_USB0 8 +#define INT_USB1 9 +#define INT_USB0_DMA 10 +#define INT_USB1_DMA 11 +#define INT_MAC 12 +#define INT_MAC_PMT 13 +#define INT_NAND 14 +#define INT_UART0 15 +#define INT_UART1 16 +#define INT_UART2 17 +#define INT_UART3 18 +#define INT_UART4 19 +#define INT_UART5 20 +#define INT_UART6 21 +#define INT_UART7 22 +#define INT_UART8 23 +#define INT_UART9 24 +#define INT_I2S0 25 +#define INT_I2C0 26 +#define INT_I2C1 27 +#define INT_CAMIF 28 +#define INT_TIMER0 29 +#define INT_TIMER1 30 +#define INT_TIMER2 31 +#define INT_TIMER3 32 +#define INT_ADC0 33 +#define INT_DAC0 34 +#define INT_USB0_RESUME_HOSTDISCONNECT 35 +#define INT_USB0_VBUSVALID 36 +#define INT_USB1_RESUME_HOSTDISCONNECT 37 +#define INT_USB1_VBUSVALID 38 +#define INT_DMA0_CH0 39 +#define INT_DMA0_CH1 40 +#define INT_DMA0_CH2 41 +#define INT_DMA0_CH3 42 +#define INT_DMA0_CH4 43 +#define INT_DMA0_CH5 44 +#define INT_DMA0_CH6 45 +#define INT_DMA0_CH7 46 +#define INT_DMA1_CH0 47 +#define INT_DMA1_CH1 48 +#define INT_DMA1_CH2 49 +#define INT_DMA1_CH3 50 +#define INT_DMA1_CH4 51 +#define INT_DMA1_CH5 52 +#define INT_DMA1_CH6 53 +#define INT_DMA1_CH7 54 +#define INT_WATCHDOG 55 +#define INT_CAN0 56 +#define INT_CAN1 57 +#define INT_QEI 58 +#define INT_MCPWM 59 +#define INT_SPI0 60 +#define INT_SPI1 61 +#define INT_QUADSPI0 62 #define INT_SSP0 63 #endif diff --git a/bsp/asm9260t/platform/reset.c b/bsp/asm9260t/platform/reset.c index 2f5adc6231..e2611af4a3 100644 --- a/bsp/asm9260t/platform/reset.c +++ b/bsp/asm9260t/platform/reset.c @@ -1,21 +1,7 @@ /* - * File : reset.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2015, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/asm9260t/platform/rt_low_level_init.c b/bsp/asm9260t/platform/rt_low_level_init.c index 926c1af6fa..822f8ac733 100644 --- a/bsp/asm9260t/platform/rt_low_level_init.c +++ b/bsp/asm9260t/platform/rt_low_level_init.c @@ -1,21 +1,7 @@ /* - * File : rt_low_level_init.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/asm9260t/platform/rt_low_level_init.h b/bsp/asm9260t/platform/rt_low_level_init.h index 86dcfb59dc..c79adf5284 100644 --- a/bsp/asm9260t/platform/rt_low_level_init.h +++ b/bsp/asm9260t/platform/rt_low_level_init.h @@ -1,21 +1,7 @@ /* - * File : rt_low_level_init.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -23,7 +9,7 @@ */ #ifndef __RT_LOW_LEVEL_INIT_H__ #define __RT_LOW_LEVEL_INIT_H__ - + /*-------- Stack size of CPU modes -------------------------------------------*/ #define UND_STK_SIZE 512 #define SVC_STK_SIZE 4096 diff --git a/bsp/asm9260t/platform/system_clock.c b/bsp/asm9260t/platform/system_clock.c index e51cf7c892..3a3340f48d 100644 --- a/bsp/asm9260t/platform/system_clock.c +++ b/bsp/asm9260t/platform/system_clock.c @@ -1,21 +1,7 @@ /* - * File : clock.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -28,269 +14,269 @@ static rt_list_t clocks; struct clk { - char name[32]; - rt_uint32_t rate_hz; - struct clk *parent; - rt_list_t node; + char name[32]; + rt_uint32_t rate_hz; + struct clk *parent; + rt_list_t node; }; static struct clk clk32k = { - "clk32k", - AT91_SLOW_CLOCK, - RT_NULL, - {RT_NULL, RT_NULL}, + "clk32k", + AT91_SLOW_CLOCK, + RT_NULL, + {RT_NULL, RT_NULL}, }; static struct clk main_clk = { - "main", - 0, - RT_NULL, - {RT_NULL, RT_NULL}, + "main", + 0, + RT_NULL, + {RT_NULL, RT_NULL}, }; static struct clk plla = { - "plla", - 0, - RT_NULL, - {RT_NULL, RT_NULL}, + "plla", + 0, + RT_NULL, + {RT_NULL, RT_NULL}, }; static struct clk mck = { - "mck", - 0, - RT_NULL, - {RT_NULL, RT_NULL}, + "mck", + 0, + RT_NULL, + {RT_NULL, RT_NULL}, }; static struct clk uhpck = { - "uhpck", - 0, - RT_NULL, - {RT_NULL, RT_NULL}, + "uhpck", + 0, + RT_NULL, + {RT_NULL, RT_NULL}, }; static struct clk pllb = { - "pllb", - 0, - &main_clk, - {RT_NULL, RT_NULL}, + "pllb", + 0, + &main_clk, + {RT_NULL, RT_NULL}, }; static struct clk udpck = { - "udpck", - 0, - &pllb, - {RT_NULL, RT_NULL}, + "udpck", + 0, + &pllb, + {RT_NULL, RT_NULL}, }; static struct clk *const standard_pmc_clocks[] = { - // four primary clocks - &clk32k, - &main_clk, - &plla, + // four primary clocks + &clk32k, + &main_clk, + &plla, - // MCK - &mck + // MCK + &mck }; // clocks cannot be de-registered no refcounting necessary struct clk *clk_get(const char *id) { - struct clk *clk; - rt_list_t *list; - - for (list = (&clocks)->next; list != &clocks; list = list->next) - { - clk = (struct clk *)rt_list_entry(list, struct clk, node); - if (rt_strcmp(id, clk->name) == 0) - return clk; - } + struct clk *clk; + rt_list_t *list; - return RT_NULL; + for (list = (&clocks)->next; list != &clocks; list = list->next) + { + clk = (struct clk *)rt_list_entry(list, struct clk, node); + if (rt_strcmp(id, clk->name) == 0) + return clk; + } + + return RT_NULL; } rt_uint32_t clk_get_rate(struct clk *clk) { - rt_uint32_t rate; + rt_uint32_t rate; - for (;;) { - rate = clk->rate_hz; - if (rate || !clk->parent) - break; - clk = clk->parent; - } - return rate; + for (;;) { + rate = clk->rate_hz; + if (rate || !clk->parent) + break; + clk = clk->parent; + } + return rate; } static rt_uint32_t at91_pll_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg) { - unsigned mul, div; + unsigned mul, div; - div = reg & 0xff; - mul = (reg >> 16) & 0x7ff; - if (div && mul) { - freq /= div; - freq *= mul + 1; - } else - freq = 0; + div = reg & 0xff; + mul = (reg >> 16) & 0x7ff; + if (div && mul) { + freq /= div; + freq *= mul + 1; + } else + freq = 0; - return freq; + return freq; } static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq) { - unsigned i, div = 0, mul = 0, diff = 1 << 30; - unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00; + unsigned i, div = 0, mul = 0, diff = 1 << 30; + unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00; - //PLL output max 240 MHz (or 180 MHz per errata) - if (out_freq > 240000000) - goto fail; + //PLL output max 240 MHz (or 180 MHz per errata) + if (out_freq > 240000000) + goto fail; - for (i = 1; i < 256; i++) { - int diff1; - unsigned input, mul1; + for (i = 1; i < 256; i++) { + int diff1; + unsigned input, mul1; - // - // PLL input between 1MHz and 32MHz per spec, but lower - // frequences seem necessary in some cases so allow 100K. - // Warning: some newer products need 2MHz min. - // - input = main_freq / i; - if (input < 100000) - continue; - if (input > 32000000) - continue; + // + // PLL input between 1MHz and 32MHz per spec, but lower + // frequences seem necessary in some cases so allow 100K. + // Warning: some newer products need 2MHz min. + // + input = main_freq / i; + if (input < 100000) + continue; + if (input > 32000000) + continue; - mul1 = out_freq / input; - if (mul1 > 2048) - continue; - if (mul1 < 2) - goto fail; + mul1 = out_freq / input; + if (mul1 > 2048) + continue; + if (mul1 < 2) + goto fail; - diff1 = out_freq - input * mul1; - if (diff1 < 0) - diff1 = -diff1; - if (diff > diff1) { - diff = diff1; - div = i; - mul = mul1; - if (diff == 0) - break; - } - } - if (i == 256 && diff > (out_freq >> 5)) - goto fail; - return ret | ((mul - 1) << 16) | div; + diff1 = out_freq - input * mul1; + if (diff1 < 0) + diff1 = -diff1; + if (diff > diff1) { + diff = diff1; + div = i; + mul = mul1; + if (diff == 0) + break; + } + } + if (i == 256 && diff > (out_freq >> 5)) + goto fail; + return ret | ((mul - 1) << 16) | div; fail: - return 0; + return 0; } static rt_uint32_t at91_usb_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg) { - if (pll == &pllb && (reg & AT91_PMC_USB96M)) - return freq / 2; - else - return freq; + if (pll == &pllb && (reg & AT91_PMC_USB96M)) + return freq / 2; + else + return freq; } // PLLB generated USB full speed clock init static void at91_pllb_usbfs_clock_init(rt_uint32_t main_clock) { - rt_uint32_t at91_pllb_usb_init; - // - // USB clock init: choose 48 MHz PLLB value, - // disable 48MHz clock during usb peripheral suspend. - // - // REVISIT: assumes MCK doesn't derive from PLLB! - // - uhpck.parent = &pllb; + rt_uint32_t at91_pllb_usb_init; + // + // USB clock init: choose 48 MHz PLLB value, + // disable 48MHz clock during usb peripheral suspend. + // + // REVISIT: assumes MCK doesn't derive from PLLB! + // + uhpck.parent = &pllb; - at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M; - pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init); - - at91_sys_write(AT91_CKGR_PLLBR, 0); + at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M; + pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init); - udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); - uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); + at91_sys_write(AT91_CKGR_PLLBR, 0); + + udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); + uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); } static struct clk *at91_css_to_clk(unsigned long css) { - switch (css) { - case AT91_PMC_CSS_SLOW: - return &clk32k; - case AT91_PMC_CSS_MAIN: - return &main_clk; - case AT91_PMC_CSS_PLLA: - return &plla; - case AT91_PMC_CSS_PLLB: - return &pllb; - } + switch (css) { + case AT91_PMC_CSS_SLOW: + return &clk32k; + case AT91_PMC_CSS_MAIN: + return &main_clk; + case AT91_PMC_CSS_PLLA: + return &plla; + case AT91_PMC_CSS_PLLB: + return &pllb; + } - return RT_NULL; + return RT_NULL; } #define false 0 #define true 1 int at91_clock_init(rt_uint32_t main_clock) { - unsigned tmp, freq, mckr; - int i; - int pll_overclock = false; + unsigned tmp, freq, mckr; + int i; + int pll_overclock = false; - // - // When the bootloader initialized the main oscillator correctly, - // there's no problem using the cycle counter. But if it didn't, - // or when using oscillator bypass mode, we must be told the speed - // of the main clock. - // - if (!main_clock) { - do { - tmp = at91_sys_read(AT91_CKGR_MCFR); - } while (!(tmp & AT91_PMC_MAINRDY)); - main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16); - } - main_clk.rate_hz = main_clock; + // + // When the bootloader initialized the main oscillator correctly, + // there's no problem using the cycle counter. But if it didn't, + // or when using oscillator bypass mode, we must be told the speed + // of the main clock. + // + if (!main_clock) { + do { + tmp = at91_sys_read(AT91_CKGR_MCFR); + } while (!(tmp & AT91_PMC_MAINRDY)); + main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16); + } + main_clk.rate_hz = main_clock; - // report if PLLA is more than mildly overclocked - plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR)); - if (plla.rate_hz > 209000000) - pll_overclock = true; - if (pll_overclock) - ;//rt_kprintf("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000); + // report if PLLA is more than mildly overclocked + plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR)); + if (plla.rate_hz > 209000000) + pll_overclock = true; + if (pll_overclock) + ;//rt_kprintf("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000); - at91_pllb_usbfs_clock_init(main_clock); + at91_pllb_usbfs_clock_init(main_clock); - // - // MCK and CPU derive from one of those primary clocks. - // For now, assume this parentage won't change. - // - mckr = at91_sys_read(AT91_PMC_MCKR); - mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS); - freq = mck.parent->rate_hz; - freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); // prescale - - mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); // mdiv + // + // MCK and CPU derive from one of those primary clocks. + // For now, assume this parentage won't change. + // + mckr = at91_sys_read(AT91_PMC_MCKR); + mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS); + freq = mck.parent->rate_hz; + freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); // prescale - // Register the PMC's standard clocks - rt_list_init(&clocks); - for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) - rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node); + mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); // mdiv - rt_list_insert_after(&clocks, &pllb.node); - rt_list_insert_after(&clocks, &uhpck.node); - rt_list_insert_after(&clocks, &udpck.node); + // Register the PMC's standard clocks + rt_list_init(&clocks); + for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) + rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node); - // MCK and CPU clock are "always on" - //clk_enable(&mck); + rt_list_insert_after(&clocks, &pllb.node); + rt_list_insert_after(&clocks, &uhpck.node); + rt_list_insert_after(&clocks, &udpck.node); - //rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n", - // freq / 1000000, (unsigned) mck.rate_hz / 1000000, - // (unsigned) main_clock / 1000000, - // ((unsigned) main_clock % 1000000) / 1000); //cause blocked + // MCK and CPU clock are "always on" + //clk_enable(&mck); - return 0; + //rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n", + // freq / 1000000, (unsigned) mck.rate_hz / 1000000, + // (unsigned) main_clock / 1000000, + // ((unsigned) main_clock % 1000000) / 1000); //cause blocked + + return 0; } */ @@ -298,6 +284,6 @@ int at91_clock_init(rt_uint32_t main_clock) void rt_hw_clock_init(void) { - //at91_clock_init(18432000); + //at91_clock_init(18432000); } diff --git a/bsp/asm9260t/platform/timer0.c b/bsp/asm9260t/platform/timer0.c index cccbed9e57..91eaa19ad6 100644 --- a/bsp/asm9260t/platform/timer0.c +++ b/bsp/asm9260t/platform/timer0.c @@ -1,21 +1,7 @@ /* - * File : timer0.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/asm9260t/platform/timer0.h b/bsp/asm9260t/platform/timer0.h index 338ef05816..85cd955f46 100644 --- a/bsp/asm9260t/platform/timer0.h +++ b/bsp/asm9260t/platform/timer0.h @@ -1,21 +1,7 @@ /* - * File : timer0.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/asm9260t/platform/uart.c b/bsp/asm9260t/platform/uart.c index 7f39ef9c11..08613200db 100644 --- a/bsp/asm9260t/platform/uart.c +++ b/bsp/asm9260t/platform/uart.c @@ -1,27 +1,13 @@ /* - * File : interrupt.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2015-04-14 ArdaFu first version */ - + #include "asm9260t.h" #include "rtthread.h" #include "uart.h" diff --git a/bsp/asm9260t/platform/uart.h b/bsp/asm9260t/platform/uart.h index b1645e2ec5..b938483882 100644 --- a/bsp/asm9260t/platform/uart.h +++ b/bsp/asm9260t/platform/uart.h @@ -1,21 +1,7 @@ /* - * File : interrupt.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -50,16 +36,16 @@ typedef struct volatile rt_uint32_t ISO7816STATUS[4]; } HW_USART_TypeDef; -#define USART0 ((HW_USART_TypeDef *)UART0_BASE) -#define USART1 ((HW_USART_TypeDef *)UART1_BASE) -#define USART2 ((HW_USART_TypeDef *)UART2_BASE) -#define USART3 ((HW_USART_TypeDef *)UART3_BASE) -#define USART4 ((HW_USART_TypeDef *)UART4_BASE) -#define USART5 ((HW_USART_TypeDef *)UART5_BASE) -#define USART6 ((HW_USART_TypeDef *)UART6_BASE) -#define USART7 ((HW_USART_TypeDef *)UART7_BASE) -#define USART8 ((HW_USART_TypeDef *)UART8_BASE) -#define USART9 ((HW_USART_TypeDef *)UART9_BASE) +#define USART0 ((HW_USART_TypeDef *)UART0_BASE) +#define USART1 ((HW_USART_TypeDef *)UART1_BASE) +#define USART2 ((HW_USART_TypeDef *)UART2_BASE) +#define USART3 ((HW_USART_TypeDef *)UART3_BASE) +#define USART4 ((HW_USART_TypeDef *)UART4_BASE) +#define USART5 ((HW_USART_TypeDef *)UART5_BASE) +#define USART6 ((HW_USART_TypeDef *)UART6_BASE) +#define USART7 ((HW_USART_TypeDef *)UART7_BASE) +#define USART8 ((HW_USART_TypeDef *)UART8_BASE) +#define USART9 ((HW_USART_TypeDef *)UART9_BASE) #define ASM_UART_INTR_RXIS (1UL << 4) @@ -105,7 +91,7 @@ typedef struct extern void Hw_UartDisable(HW_USART_TypeDef* uartBase); extern void Hw_UartEnable(HW_USART_TypeDef* uartBase); extern void Hw_UartReset(HW_USART_TypeDef* uartBase); -extern void Hw_UartConfig(HW_USART_TypeDef* uartBase, int baudRate, +extern void Hw_UartConfig(HW_USART_TypeDef* uartBase, int baudRate, int dataBits, int stopBits, int parity); extern void Hw_UartInit(int index); #endif diff --git a/bsp/at91sam9260/applications/application.c b/bsp/at91sam9260/applications/application.c index 48c526957a..f1a377e1e9 100644 --- a/bsp/at91sam9260/applications/application.c +++ b/bsp/at91sam9260/applications/application.c @@ -1,25 +1,11 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version + * Date Author Notes + * 2011-01-13 weety first version */ /** @@ -48,106 +34,106 @@ static int rt_led_app_init(void); int main(void) { - int timeout = 0; + int timeout = 0; /* Filesystem Initialization */ #ifdef RT_USING_DFS - { + { #if defined(RT_USING_DFS_ROMFS) - if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0) - { - rt_kprintf("ROM File System initialized!\n"); - } - else - rt_kprintf("ROM File System initialzation failed!\n"); + if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0) + { + rt_kprintf("ROM File System initialized!\n"); + } + else + rt_kprintf("ROM File System initialzation failed!\n"); #endif #if defined(RT_USING_DFS_UFFS) - { - /* mount flash device as flash directory */ - if(dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0) - rt_kprintf("UFFS File System initialized!\n"); - else - rt_kprintf("UFFS File System initialzation failed!\n"); - } + { + /* mount flash device as flash directory */ + if(dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0) + rt_kprintf("UFFS File System initialized!\n"); + else + rt_kprintf("UFFS File System initialzation failed!\n"); + } #endif #ifdef RT_USING_SDIO - timeout = 0; - while ((rt_device_find("sd0") == RT_NULL) && (timeout++ < RT_TICK_PER_SECOND*2)) - { - rt_thread_delay(1); - } + timeout = 0; + while ((rt_device_find("sd0") == RT_NULL) && (timeout++ < RT_TICK_PER_SECOND*2)) + { + rt_thread_delay(1); + } - if (timeout < RT_TICK_PER_SECOND*2) - { - /* mount sd card fat partition 1 as root directory */ - if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) - { - rt_kprintf("File System initialized!\n"); - } - else - rt_kprintf("File System initialzation failed!%d\n", rt_get_errno()); - } - else - { - rt_kprintf("No SD card found.\n"); - } + if (timeout < RT_TICK_PER_SECOND*2) + { + /* mount sd card fat partition 1 as root directory */ + if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) + { + rt_kprintf("File System initialized!\n"); + } + else + rt_kprintf("File System initialzation failed!%d\n", rt_get_errno()); + } + else + { + rt_kprintf("No SD card found.\n"); + } #endif - } + } #endif - + #ifdef RT_USING_LED - rt_led_app_init(); + rt_led_app_init(); #endif } #ifdef RT_USING_LED void rt_led_thread_entry(void* parameter) { - rt_uint8_t cnt = 0; - led_init(); - while(1) - { - /* light on leds for one second */ - rt_thread_delay(40); - cnt++; - if (cnt&0x01) - led_on(1); - else - led_off(1); - if (cnt&0x02) - led_on(2); - else - led_off(2); - if (cnt&0x04) - led_on(3); - else - led_off(3); - } + rt_uint8_t cnt = 0; + led_init(); + while(1) + { + /* light on leds for one second */ + rt_thread_delay(40); + cnt++; + if (cnt&0x01) + led_on(1); + else + led_off(1); + if (cnt&0x02) + led_on(2); + else + led_off(2); + if (cnt&0x04) + led_on(3); + else + led_off(3); + } } #endif static int rt_led_app_init(void) { #ifdef RT_USING_LED - rt_thread_t led_thread; + rt_thread_t led_thread; #if (RT_THREAD_PRIORITY_MAX == 32) - led_thread = rt_thread_create("led", - rt_led_thread_entry, RT_NULL, - 512, 20, 20); + led_thread = rt_thread_create("led", + rt_led_thread_entry, RT_NULL, + 512, 20, 20); #else - led_thread = rt_thread_create("led", - rt_led_thread_entry, RT_NULL, - 512, 200, 20); + led_thread = rt_thread_create("led", + rt_led_thread_entry, RT_NULL, + 512, 200, 20); #endif - if(led_thread != RT_NULL) - rt_thread_startup(led_thread); + if(led_thread != RT_NULL) + rt_thread_startup(led_thread); #endif - return 0; + return 0; } /* NFSv3 Initialization */ @@ -155,14 +141,14 @@ static int rt_led_app_init(void) #include void nfs_start(void) { - nfs_init(); + nfs_init(); - if (dfs_mount(RT_NULL, "/nfs", "nfs", 0, RT_NFS_HOST_EXPORT) == 0) - { - rt_kprintf("NFSv3 File System initialized!\n"); - } - else - rt_kprintf("NFSv3 File System initialzation failed!\n"); + if (dfs_mount(RT_NULL, "/nfs", "nfs", 0, RT_NFS_HOST_EXPORT) == 0) + { + rt_kprintf("NFSv3 File System initialized!\n"); + } + else + rt_kprintf("NFSv3 File System initialzation failed!\n"); } #include "finsh.h" diff --git a/bsp/at91sam9260/drivers/at91_i2c_gpio.c b/bsp/at91sam9260/drivers/at91_i2c_gpio.c index 1c11f4ad79..d863ffed88 100644 --- a/bsp/at91sam9260/drivers/at91_i2c_gpio.c +++ b/bsp/at91sam9260/drivers/at91_i2c_gpio.c @@ -1,25 +1,11 @@ /* - * File : at91_i2c_gpio.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2012-04-25 weety first version + * Date Author Notes + * 2012-04-25 weety first version */ #include @@ -29,101 +15,101 @@ static void at91_i2c_gpio_init() { - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOA); //enable PIOA clock - at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 23)); - at91_sys_write(AT91_PIOA + PIO_PER, (1 << 23)); - at91_sys_write(AT91_PIOA + PIO_MDER, (1 << 23)); - at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 24)); - at91_sys_write(AT91_PIOA + PIO_PER, (1 << 24)); - at91_sys_write(AT91_PIOA + PIO_MDER, (1 << 24)); + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOA); //enable PIOA clock + at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 23)); + at91_sys_write(AT91_PIOA + PIO_PER, (1 << 23)); + at91_sys_write(AT91_PIOA + PIO_MDER, (1 << 23)); + at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 24)); + at91_sys_write(AT91_PIOA + PIO_PER, (1 << 24)); + at91_sys_write(AT91_PIOA + PIO_MDER, (1 << 24)); - at91_sys_write(AT91_PIOA + PIO_OER, (1 << 23)); - at91_sys_write(AT91_PIOA + PIO_OER, (1 << 24)); + at91_sys_write(AT91_PIOA + PIO_OER, (1 << 23)); + at91_sys_write(AT91_PIOA + PIO_OER, (1 << 24)); - at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 23)); - at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 24)); + at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 23)); + at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 24)); } static void at91_set_sda(void *data, rt_int32_t state) { - if (state) - { - at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 23)); - } - else - { - at91_sys_write(AT91_PIOA + PIO_CODR, (1 << 23)); - } + if (state) + { + at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 23)); + } + else + { + at91_sys_write(AT91_PIOA + PIO_CODR, (1 << 23)); + } } static void at91_set_scl(void *data, rt_int32_t state) { - if (state) - { - at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 24)); - } - else - { - at91_sys_write(AT91_PIOA + PIO_CODR, (1 << 24)); - } + if (state) + { + at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 24)); + } + else + { + at91_sys_write(AT91_PIOA + PIO_CODR, (1 << 24)); + } } static rt_int32_t at91_get_sda(void *data) { - return at91_sys_read(AT91_PIOA + PIO_PDSR) & (1 << 23); + return at91_sys_read(AT91_PIOA + PIO_PDSR) & (1 << 23); } static rt_int32_t at91_get_scl(void *data) { - return at91_sys_read(AT91_PIOA + PIO_PDSR) & (1 << 24); + return at91_sys_read(AT91_PIOA + PIO_PDSR) & (1 << 24); } static void at91_udelay (rt_uint32_t us) { - rt_int32_t i; - for (; us > 0; us--) - { - i = 50000; - while(i > 0) - { - i--; - } - } + rt_int32_t i; + for (; us > 0; us--) + { + i = 50000; + while(i > 0) + { + i--; + } + } } static const struct rt_i2c_bit_ops bit_ops = { - RT_NULL, - at91_set_sda, - at91_set_scl, - at91_get_sda, - at91_get_scl, - - at91_udelay, + RT_NULL, + at91_set_sda, + at91_set_scl, + at91_get_sda, + at91_get_scl, - 5, - 100 + at91_udelay, + + 5, + 100 }; int at91_i2c_init(void) { - struct rt_i2c_bus_device *bus; + struct rt_i2c_bus_device *bus; - bus = rt_malloc(sizeof(struct rt_i2c_bus_device)); - if (bus == RT_NULL) - { - rt_kprintf("rt_malloc failed\n"); - return -RT_ENOMEM; - } - - rt_memset((void *)bus, 0, sizeof(struct rt_i2c_bus_device)); + bus = rt_malloc(sizeof(struct rt_i2c_bus_device)); + if (bus == RT_NULL) + { + rt_kprintf("rt_malloc failed\n"); + return -RT_ENOMEM; + } - bus->priv = (void *)&bit_ops; + rt_memset((void *)bus, 0, sizeof(struct rt_i2c_bus_device)); - at91_i2c_gpio_init(); + bus->priv = (void *)&bit_ops; - rt_i2c_bit_add_bus(bus, "i2c0"); + at91_i2c_gpio_init(); - return 0; + rt_i2c_bit_add_bus(bus, "i2c0"); + + return 0; } INIT_DEVICE_EXPORT(at91_i2c_init); diff --git a/bsp/at91sam9260/drivers/at91_mci.c b/bsp/at91sam9260/drivers/at91_mci.c index 25d408810c..92f7abdfec 100644 --- a/bsp/at91sam9260/drivers/at91_mci.c +++ b/bsp/at91sam9260/drivers/at91_mci.c @@ -1,25 +1,11 @@ /* - * File : at91_mci.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-07-25 weety first version + * Date Author Notes + * 2011-07-25 weety first version */ #include @@ -37,32 +23,32 @@ #define mci_dbg(fmt, ...) #endif -#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<31)) +#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<31)) extern void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size); extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size); -#define AT91_MCI_ERRORS (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE \ - | AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE \ - | AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE) +#define AT91_MCI_ERRORS (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE \ + | AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE \ + | AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE) -#define at91_mci_read(reg) readl(AT91SAM9260_BASE_MCI + (reg)) -#define at91_mci_write(reg, val) writel((val), AT91SAM9260_BASE_MCI + (reg)) +#define at91_mci_read(reg) readl(AT91SAM9260_BASE_MCI + (reg)) +#define at91_mci_write(reg, val) writel((val), AT91SAM9260_BASE_MCI + (reg)) -#define REQ_ST_INIT (1U << 0) -#define REQ_ST_CMD (1U << 1) -#define REQ_ST_STOP (1U << 2) +#define REQ_ST_INIT (1U << 0) +#define REQ_ST_CMD (1U << 1) +#define REQ_ST_STOP (1U << 2) struct at91_mci { - struct rt_mmcsd_host *host; - struct rt_mmcsd_req *req; - struct rt_mmcsd_cmd *cmd; - struct rt_timer timer; - //struct rt_semaphore sem_ack; - rt_uint32_t *buf; - rt_uint32_t current_status; + struct rt_mmcsd_host *host; + struct rt_mmcsd_req *req; + struct rt_mmcsd_cmd *cmd; + struct rt_timer timer; + //struct rt_semaphore sem_ack; + rt_uint32_t *buf; + rt_uint32_t current_status; }; /* @@ -70,36 +56,36 @@ struct at91_mci { */ static void at91_reset_host() { - rt_uint32_t mr; - rt_uint32_t sdcr; - rt_uint32_t dtor; - rt_uint32_t imr; - rt_uint32_t level; + rt_uint32_t mr; + rt_uint32_t sdcr; + rt_uint32_t dtor; + rt_uint32_t imr; + rt_uint32_t level; - level = rt_hw_interrupt_disable(); + level = rt_hw_interrupt_disable(); - imr = at91_mci_read(AT91_MCI_IMR); + imr = at91_mci_read(AT91_MCI_IMR); - at91_mci_write(AT91_MCI_IDR, 0xffffffff); + at91_mci_write(AT91_MCI_IDR, 0xffffffff); - /* save current state */ - mr = at91_mci_read(AT91_MCI_MR) & 0x7fff; - sdcr = at91_mci_read(AT91_MCI_SDCR); - dtor = at91_mci_read(AT91_MCI_DTOR); + /* save current state */ + mr = at91_mci_read(AT91_MCI_MR) & 0x7fff; + sdcr = at91_mci_read(AT91_MCI_SDCR); + dtor = at91_mci_read(AT91_MCI_DTOR); - /* reset the controller */ - at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST); + /* reset the controller */ + at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST); - /* restore state */ - at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN); - at91_mci_write(AT91_MCI_MR, mr); - at91_mci_write(AT91_MCI_SDCR, sdcr); - at91_mci_write(AT91_MCI_DTOR, dtor); - at91_mci_write(AT91_MCI_IER, imr); + /* restore state */ + at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN); + at91_mci_write(AT91_MCI_MR, mr); + at91_mci_write(AT91_MCI_SDCR, sdcr); + at91_mci_write(AT91_MCI_DTOR, dtor); + at91_mci_write(AT91_MCI_IER, imr); - /* make sure sdio interrupts will fire */ - at91_mci_read(AT91_MCI_SR); - rt_hw_interrupt_enable(level); + /* make sure sdio interrupts will fire */ + at91_mci_read(AT91_MCI_SR); + rt_hw_interrupt_enable(level); } @@ -109,19 +95,19 @@ static void at91_reset_host() */ static void at91_mci_enable() { - rt_uint32_t mr; + rt_uint32_t mr; - at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN); - at91_mci_write(AT91_MCI_IDR, 0xffffffff); - at91_mci_write(AT91_MCI_DTOR, AT91_MCI_DTOMUL_1M | AT91_MCI_DTOCYC); - mr = AT91_MCI_PDCMODE | 0x34a; + at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN); + at91_mci_write(AT91_MCI_IDR, 0xffffffff); + at91_mci_write(AT91_MCI_DTOR, AT91_MCI_DTOMUL_1M | AT91_MCI_DTOCYC); + mr = AT91_MCI_PDCMODE | 0x34a; - mr |= AT91_MCI_RDPROOF | AT91_MCI_WRPROOF; + mr |= AT91_MCI_RDPROOF | AT91_MCI_WRPROOF; - at91_mci_write(AT91_MCI_MR, mr); + at91_mci_write(AT91_MCI_MR, mr); - /* use Slot A or B (only one at same time) */ - at91_mci_write(AT91_MCI_SDCR, 1); /* use slot b */ + /* use Slot A or B (only one at same time) */ + at91_mci_write(AT91_MCI_SDCR, 1); /* use slot b */ } /* @@ -129,39 +115,39 @@ static void at91_mci_enable() */ static void at91_mci_disable() { - at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST); + at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST); } static void at91_timeout_timer(void *data) { - struct at91_mci *mci; + struct at91_mci *mci; - mci = (struct at91_mci *)data; + mci = (struct at91_mci *)data; - if (mci->req) - { - rt_kprintf("Timeout waiting end of packet\n"); + if (mci->req) + { + rt_kprintf("Timeout waiting end of packet\n"); - if (mci->current_status == REQ_ST_CMD) - { - if (mci->req->cmd && mci->req->data) - { - mci->req->data->err = -RT_ETIMEOUT; - } - else - { - if (mci->req->cmd) - mci->req->cmd->err = -RT_ETIMEOUT; - } - } - else if (mci->current_status == REQ_ST_STOP) - { - mci->req->stop->err = -RT_ETIMEOUT; - } + if (mci->current_status == REQ_ST_CMD) + { + if (mci->req->cmd && mci->req->data) + { + mci->req->data->err = -RT_ETIMEOUT; + } + else + { + if (mci->req->cmd) + mci->req->cmd->err = -RT_ETIMEOUT; + } + } + else if (mci->current_status == REQ_ST_STOP) + { + mci->req->stop->err = -RT_ETIMEOUT; + } - at91_reset_host(); - mmcsd_req_complete(mci->host); - } + at91_reset_host(); + mmcsd_req_complete(mci->host); + } } /* @@ -169,62 +155,62 @@ static void at91_timeout_timer(void *data) */ static void at91_mci_init_dma_read(struct at91_mci *mci) { - rt_uint8_t i; - struct rt_mmcsd_cmd *cmd; - struct rt_mmcsd_data *data; - rt_uint32_t length; + rt_uint8_t i; + struct rt_mmcsd_cmd *cmd; + struct rt_mmcsd_data *data; + rt_uint32_t length; - mci_dbg("pre dma read\n"); + mci_dbg("pre dma read\n"); - cmd = mci->cmd; - if (!cmd) - { - mci_dbg("no command\n"); - return; - } + cmd = mci->cmd; + if (!cmd) + { + mci_dbg("no command\n"); + return; + } - data = cmd->data; - if (!data) - { - mci_dbg("no data\n"); - return; - } + data = cmd->data; + if (!data) + { + mci_dbg("no data\n"); + return; + } - for (i = 0; i < 1; i++) - { - /* Check to see if this needs filling */ - if (i == 0) - { - if (at91_mci_read(AT91_PDC_RCR) != 0) - { - mci_dbg("Transfer active in current\n"); - continue; - } - } - else { - if (at91_mci_read(AT91_PDC_RNCR) != 0) - { - mci_dbg("Transfer active in next\n"); - continue; - } - } + for (i = 0; i < 1; i++) + { + /* Check to see if this needs filling */ + if (i == 0) + { + if (at91_mci_read(AT91_PDC_RCR) != 0) + { + mci_dbg("Transfer active in current\n"); + continue; + } + } + else { + if (at91_mci_read(AT91_PDC_RNCR) != 0) + { + mci_dbg("Transfer active in next\n"); + continue; + } + } - length = data->blksize * data->blks; - mci_dbg("dma address = %08X, length = %d\n", data->buf, length); + length = data->blksize * data->blks; + mci_dbg("dma address = %08X, length = %d\n", data->buf, length); - if (i == 0) - { - at91_mci_write(AT91_PDC_RPR, (rt_uint32_t)(data->buf)); - at91_mci_write(AT91_PDC_RCR, (data->blksize & 0x3) ? length : length / 4); - } - else - { - at91_mci_write(AT91_PDC_RNPR, (rt_uint32_t)(data->buf)); - at91_mci_write(AT91_PDC_RNCR, (data->blksize & 0x3) ? length : length / 4); - } - } + if (i == 0) + { + at91_mci_write(AT91_PDC_RPR, (rt_uint32_t)(data->buf)); + at91_mci_write(AT91_PDC_RCR, (data->blksize & 0x3) ? length : length / 4); + } + else + { + at91_mci_write(AT91_PDC_RNPR, (rt_uint32_t)(data->buf)); + at91_mci_write(AT91_PDC_RNCR, (data->blksize & 0x3) ? length : length / 4); + } + } - mci_dbg("pre dma read done\n"); + mci_dbg("pre dma read done\n"); } /* @@ -232,185 +218,185 @@ static void at91_mci_init_dma_read(struct at91_mci *mci) */ static void at91_mci_send_command(struct at91_mci *mci, struct rt_mmcsd_cmd *cmd) { - rt_uint32_t cmdr, mr; - rt_uint32_t block_length; - struct rt_mmcsd_data *data = cmd->data; - struct rt_mmcsd_host *host = mci->host; + rt_uint32_t cmdr, mr; + rt_uint32_t block_length; + struct rt_mmcsd_data *data = cmd->data; + struct rt_mmcsd_host *host = mci->host; - rt_uint32_t blocks; - rt_uint32_t ier = 0; - rt_uint32_t length; + rt_uint32_t blocks; + rt_uint32_t ier = 0; + rt_uint32_t length; - mci->cmd = cmd; + mci->cmd = cmd; - /* Needed for leaving busy state before CMD1 */ - if ((at91_mci_read(AT91_MCI_SR) & AT91_MCI_RTOE) && (cmd->cmd_code == 1)) - { - mci_dbg("Clearing timeout\n"); - at91_mci_write(AT91_MCI_ARGR, 0); - at91_mci_write(AT91_MCI_CMDR, AT91_MCI_OPDCMD); - while (!(at91_mci_read(AT91_MCI_SR) & AT91_MCI_CMDRDY)) - { - /* spin */ - mci_dbg("Clearing: SR = %08X\n", at91_mci_read(AT91_MCI_SR)); - } - } + /* Needed for leaving busy state before CMD1 */ + if ((at91_mci_read(AT91_MCI_SR) & AT91_MCI_RTOE) && (cmd->cmd_code == 1)) + { + mci_dbg("Clearing timeout\n"); + at91_mci_write(AT91_MCI_ARGR, 0); + at91_mci_write(AT91_MCI_CMDR, AT91_MCI_OPDCMD); + while (!(at91_mci_read(AT91_MCI_SR) & AT91_MCI_CMDRDY)) + { + /* spin */ + mci_dbg("Clearing: SR = %08X\n", at91_mci_read(AT91_MCI_SR)); + } + } - cmdr = cmd->cmd_code; + cmdr = cmd->cmd_code; - if (resp_type(cmd) == RESP_NONE) - cmdr |= AT91_MCI_RSPTYP_NONE; - else - { - /* if a response is expected then allow maximum response latancy */ - cmdr |= AT91_MCI_MAXLAT; - /* set 136 bit response for R2, 48 bit response otherwise */ - if (resp_type(cmd) == RESP_R2) - cmdr |= AT91_MCI_RSPTYP_136; - else - cmdr |= AT91_MCI_RSPTYP_48; - } + if (resp_type(cmd) == RESP_NONE) + cmdr |= AT91_MCI_RSPTYP_NONE; + else + { + /* if a response is expected then allow maximum response latancy */ + cmdr |= AT91_MCI_MAXLAT; + /* set 136 bit response for R2, 48 bit response otherwise */ + if (resp_type(cmd) == RESP_R2) + cmdr |= AT91_MCI_RSPTYP_136; + else + cmdr |= AT91_MCI_RSPTYP_48; + } - if (data) - { + if (data) + { - block_length = data->blksize; - blocks = data->blks; + block_length = data->blksize; + blocks = data->blks; - /* always set data start - also set direction flag for read */ - if (data->flags & DATA_DIR_READ) - cmdr |= (AT91_MCI_TRDIR | AT91_MCI_TRCMD_START); - else if (data->flags & DATA_DIR_WRITE) - cmdr |= AT91_MCI_TRCMD_START; + /* always set data start - also set direction flag for read */ + if (data->flags & DATA_DIR_READ) + cmdr |= (AT91_MCI_TRDIR | AT91_MCI_TRCMD_START); + else if (data->flags & DATA_DIR_WRITE) + cmdr |= AT91_MCI_TRCMD_START; - if (data->flags & DATA_STREAM) - cmdr |= AT91_MCI_TRTYP_STREAM; - if (data->blks > 1) - cmdr |= AT91_MCI_TRTYP_MULTIPLE; - } - else - { - block_length = 0; - blocks = 0; - } + if (data->flags & DATA_STREAM) + cmdr |= AT91_MCI_TRTYP_STREAM; + if (data->blks > 1) + cmdr |= AT91_MCI_TRTYP_MULTIPLE; + } + else + { + block_length = 0; + blocks = 0; + } - /*if (cmd->cmd_code == GO_IDLE_STATE) - { - cmdr |= AT91_MCI_SPCMD_INIT; - }*/ + /*if (cmd->cmd_code == GO_IDLE_STATE) + { + cmdr |= AT91_MCI_SPCMD_INIT; + }*/ - if (cmd->cmd_code == STOP_TRANSMISSION) - cmdr |= AT91_MCI_TRCMD_STOP; + if (cmd->cmd_code == STOP_TRANSMISSION) + cmdr |= AT91_MCI_TRCMD_STOP; - if (host->io_cfg.bus_mode == MMCSD_BUSMODE_OPENDRAIN) - cmdr |= AT91_MCI_OPDCMD; + if (host->io_cfg.bus_mode == MMCSD_BUSMODE_OPENDRAIN) + cmdr |= AT91_MCI_OPDCMD; - /* - * Set the arguments and send the command - */ - mci_dbg("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08X)\n", - cmd->cmd_code, cmdr, cmd->arg, blocks, block_length, at91_mci_read(AT91_MCI_MR)); + /* + * Set the arguments and send the command + */ + mci_dbg("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08X)\n", + cmd->cmd_code, cmdr, cmd->arg, blocks, block_length, at91_mci_read(AT91_MCI_MR)); - if (!data) - { - at91_mci_write(AT91_PDC_PTCR, AT91_PDC_TXTDIS | AT91_PDC_RXTDIS); - at91_mci_write(AT91_PDC_RPR, 0); - at91_mci_write(AT91_PDC_RCR, 0); - at91_mci_write(AT91_PDC_RNPR, 0); - at91_mci_write(AT91_PDC_RNCR, 0); - at91_mci_write(AT91_PDC_TPR, 0); - at91_mci_write(AT91_PDC_TCR, 0); - at91_mci_write(AT91_PDC_TNPR, 0); - at91_mci_write(AT91_PDC_TNCR, 0); - ier = AT91_MCI_CMDRDY; - } - else - { - /* zero block length and PDC mode */ - mr = at91_mci_read(AT91_MCI_MR) & 0x5fff; - mr |= (data->blksize & 0x3) ? AT91_MCI_PDCFBYTE : 0; - mr |= (block_length << 16); - mr |= AT91_MCI_PDCMODE; - at91_mci_write(AT91_MCI_MR, mr); + if (!data) + { + at91_mci_write(AT91_PDC_PTCR, AT91_PDC_TXTDIS | AT91_PDC_RXTDIS); + at91_mci_write(AT91_PDC_RPR, 0); + at91_mci_write(AT91_PDC_RCR, 0); + at91_mci_write(AT91_PDC_RNPR, 0); + at91_mci_write(AT91_PDC_RNCR, 0); + at91_mci_write(AT91_PDC_TPR, 0); + at91_mci_write(AT91_PDC_TCR, 0); + at91_mci_write(AT91_PDC_TNPR, 0); + at91_mci_write(AT91_PDC_TNCR, 0); + ier = AT91_MCI_CMDRDY; + } + else + { + /* zero block length and PDC mode */ + mr = at91_mci_read(AT91_MCI_MR) & 0x5fff; + mr |= (data->blksize & 0x3) ? AT91_MCI_PDCFBYTE : 0; + mr |= (block_length << 16); + mr |= AT91_MCI_PDCMODE; + at91_mci_write(AT91_MCI_MR, mr); - at91_mci_write(AT91_MCI_BLKR, - AT91_MCI_BLKR_BCNT(blocks) | - AT91_MCI_BLKR_BLKLEN(block_length)); + at91_mci_write(AT91_MCI_BLKR, + AT91_MCI_BLKR_BCNT(blocks) | + AT91_MCI_BLKR_BLKLEN(block_length)); - /* - * Disable the PDC controller - */ - at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS); + /* + * Disable the PDC controller + */ + at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS); - if (cmdr & AT91_MCI_TRCMD_START) - { - if (cmdr & AT91_MCI_TRDIR) - { - /* - * Handle a read - */ + if (cmdr & AT91_MCI_TRCMD_START) + { + if (cmdr & AT91_MCI_TRDIR) + { + /* + * Handle a read + */ - mmu_invalidate_dcache((rt_uint32_t)data->buf, data->blksize*data->blks); - at91_mci_init_dma_read(mci); - ier = AT91_MCI_ENDRX /* | AT91_MCI_RXBUFF */; - } - else - { - /* - * Handle a write - */ - length = block_length * blocks; - /* - * at91mci MCI1 rev2xx Data Write Operation and - * number of bytes erratum - */ - if (length < 12) - { - length = 12; - mci->buf = rt_malloc(length); - if (!mci->buf) - { - rt_kprintf("rt alloc tx buffer failed\n"); - cmd->err = -RT_ENOMEM; - mmcsd_req_complete(mci->host); - return; - } - rt_memset(mci->buf, 0, 12); - rt_memcpy(mci->buf, data->buf, length); - mmu_clean_dcache((rt_uint32_t)mci->buf, length); - at91_mci_write(AT91_PDC_TPR, (rt_uint32_t)(mci->buf)); - at91_mci_write(AT91_PDC_TCR, (data->blksize & 0x3) ? - length : length / 4); - } - else - { - mmu_clean_dcache((rt_uint32_t)data->buf, data->blksize*data->blks); - at91_mci_write(AT91_PDC_TPR, (rt_uint32_t)(data->buf)); - at91_mci_write(AT91_PDC_TCR, (data->blksize & 0x3) ? - length : length / 4); - } - mci_dbg("Transmitting %d bytes\n", length); - ier = AT91_MCI_CMDRDY; - } - } - } + mmu_invalidate_dcache((rt_uint32_t)data->buf, data->blksize*data->blks); + at91_mci_init_dma_read(mci); + ier = AT91_MCI_ENDRX /* | AT91_MCI_RXBUFF */; + } + else + { + /* + * Handle a write + */ + length = block_length * blocks; + /* + * at91mci MCI1 rev2xx Data Write Operation and + * number of bytes erratum + */ + if (length < 12) + { + length = 12; + mci->buf = rt_malloc(length); + if (!mci->buf) + { + rt_kprintf("rt alloc tx buffer failed\n"); + cmd->err = -RT_ENOMEM; + mmcsd_req_complete(mci->host); + return; + } + rt_memset(mci->buf, 0, 12); + rt_memcpy(mci->buf, data->buf, length); + mmu_clean_dcache((rt_uint32_t)mci->buf, length); + at91_mci_write(AT91_PDC_TPR, (rt_uint32_t)(mci->buf)); + at91_mci_write(AT91_PDC_TCR, (data->blksize & 0x3) ? + length : length / 4); + } + else + { + mmu_clean_dcache((rt_uint32_t)data->buf, data->blksize*data->blks); + at91_mci_write(AT91_PDC_TPR, (rt_uint32_t)(data->buf)); + at91_mci_write(AT91_PDC_TCR, (data->blksize & 0x3) ? + length : length / 4); + } + mci_dbg("Transmitting %d bytes\n", length); + ier = AT91_MCI_CMDRDY; + } + } + } - /* - * Send the command and then enable the PDC - not the other way round as - * the data sheet says - */ + /* + * Send the command and then enable the PDC - not the other way round as + * the data sheet says + */ - at91_mci_write(AT91_MCI_ARGR, cmd->arg); - at91_mci_write(AT91_MCI_CMDR, cmdr); + at91_mci_write(AT91_MCI_ARGR, cmd->arg); + at91_mci_write(AT91_MCI_CMDR, cmdr); - if (cmdr & AT91_MCI_TRCMD_START) - { - if (cmdr & AT91_MCI_TRDIR) - at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTEN); - } + if (cmdr & AT91_MCI_TRCMD_START) + { + if (cmdr & AT91_MCI_TRDIR) + at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTEN); + } - /* Enable selected interrupts */ - at91_mci_write(AT91_MCI_IER, AT91_MCI_ERRORS | ier); + /* Enable selected interrupts */ + at91_mci_write(AT91_MCI_IER, AT91_MCI_ERRORS | ier); } /* @@ -418,25 +404,25 @@ static void at91_mci_send_command(struct at91_mci *mci, struct rt_mmcsd_cmd *cmd */ static void at91_mci_process_next(struct at91_mci *mci) { - if (mci->current_status == REQ_ST_INIT) - { - mci->current_status = REQ_ST_CMD; - at91_mci_send_command(mci, mci->req->cmd); - } - else if ((mci->current_status == REQ_ST_CMD) && mci->req->stop) - { - mci->current_status = REQ_ST_STOP; - at91_mci_send_command(mci, mci->req->stop); - } - else - { - rt_timer_stop(&mci->timer); - /* the mci controller hangs after some transfers, - * and the workaround is to reset it after each transfer. - */ - at91_reset_host(); - mmcsd_req_complete(mci->host); - } + if (mci->current_status == REQ_ST_INIT) + { + mci->current_status = REQ_ST_CMD; + at91_mci_send_command(mci, mci->req->cmd); + } + else if ((mci->current_status == REQ_ST_CMD) && mci->req->stop) + { + mci->current_status = REQ_ST_STOP; + at91_mci_send_command(mci, mci->req->stop); + } + else + { + rt_timer_stop(&mci->timer); + /* the mci controller hangs after some transfers, + * and the workaround is to reset it after each transfer. + */ + at91_reset_host(); + mmcsd_req_complete(mci->host); + } } /* @@ -444,15 +430,15 @@ static void at91_mci_process_next(struct at91_mci *mci) */ static void at91_mci_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) { - rt_uint32_t timeout = RT_TICK_PER_SECOND; - struct at91_mci *mci = host->private_data; - mci->req = req; - mci->current_status = REQ_ST_INIT; + rt_uint32_t timeout = RT_TICK_PER_SECOND; + struct at91_mci *mci = host->private_data; + mci->req = req; + mci->current_status = REQ_ST_INIT; - rt_timer_control(&mci->timer, RT_TIMER_CTRL_SET_TIME, (void*)&timeout); - rt_timer_start(&mci->timer); + rt_timer_control(&mci->timer, RT_TIMER_CTRL_SET_TIME, (void*)&timeout); + rt_timer_start(&mci->timer); - at91_mci_process_next(mci); + at91_mci_process_next(mci); } /* @@ -460,29 +446,29 @@ static void at91_mci_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *re */ static void at91_mci_handle_transmitted(struct at91_mci *mci) { - struct rt_mmcsd_cmd *cmd; - struct rt_mmcsd_data *data; + struct rt_mmcsd_cmd *cmd; + struct rt_mmcsd_data *data; - mci_dbg("Handling the transmit\n"); + mci_dbg("Handling the transmit\n"); - /* Disable the transfer */ - at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS); + /* Disable the transfer */ + at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS); - /* Now wait for cmd ready */ - at91_mci_write(AT91_MCI_IDR, AT91_MCI_TXBUFE); + /* Now wait for cmd ready */ + at91_mci_write(AT91_MCI_IDR, AT91_MCI_TXBUFE); - cmd = mci->cmd; - if (!cmd) return; + cmd = mci->cmd; + if (!cmd) return; - data = cmd->data; - if (!data) return; + data = cmd->data; + if (!data) return; - if (data->blks > 1) - { - mci_dbg("multiple write : wait for BLKE...\n"); - at91_mci_write(AT91_MCI_IER, AT91_MCI_BLKE); - } else - at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY); + if (data->blks > 1) + { + mci_dbg("multiple write : wait for BLKE...\n"); + at91_mci_write(AT91_MCI_IER, AT91_MCI_BLKE); + } else + at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY); } @@ -491,54 +477,54 @@ static void at91_mci_handle_transmitted(struct at91_mci *mci) */ static void at91_mci_post_dma_read(struct at91_mci *mci) { - struct rt_mmcsd_cmd *cmd; - struct rt_mmcsd_data *data; + struct rt_mmcsd_cmd *cmd; + struct rt_mmcsd_data *data; - mci_dbg("post dma read\n"); + mci_dbg("post dma read\n"); - cmd = mci->cmd; - if (!cmd) - { - mci_dbg("no command\n"); - return; - } + cmd = mci->cmd; + if (!cmd) + { + mci_dbg("no command\n"); + return; + } - data = cmd->data; - if (!data) - { - mci_dbg("no data\n"); - return; - } + data = cmd->data; + if (!data) + { + mci_dbg("no data\n"); + return; + } - at91_mci_write(AT91_MCI_IDR, AT91_MCI_ENDRX); - at91_mci_write(AT91_MCI_IER, AT91_MCI_RXBUFF); + at91_mci_write(AT91_MCI_IDR, AT91_MCI_ENDRX); + at91_mci_write(AT91_MCI_IER, AT91_MCI_RXBUFF); - mci_dbg("post dma read done\n"); + mci_dbg("post dma read done\n"); } /*Handle after command sent ready*/ static int at91_mci_handle_cmdrdy(struct at91_mci *mci) { - if (!mci->cmd) - return 1; - else if (!mci->cmd->data) - { - if (mci->current_status == REQ_ST_STOP) - { - /*After multi block write, we must wait for NOTBUSY*/ - at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY); - } - else return 1; - } - else if (mci->cmd->data->flags & DATA_DIR_WRITE) - { - /*After sendding multi-block-write command, start DMA transfer*/ - at91_mci_write(AT91_MCI_IER, AT91_MCI_TXBUFE | AT91_MCI_BLKE); - at91_mci_write(AT91_PDC_PTCR, AT91_PDC_TXTEN); - } + if (!mci->cmd) + return 1; + else if (!mci->cmd->data) + { + if (mci->current_status == REQ_ST_STOP) + { + /*After multi block write, we must wait for NOTBUSY*/ + at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY); + } + else return 1; + } + else if (mci->cmd->data->flags & DATA_DIR_WRITE) + { + /*After sendding multi-block-write command, start DMA transfer*/ + at91_mci_write(AT91_MCI_IER, AT91_MCI_TXBUFE | AT91_MCI_BLKE); + at91_mci_write(AT91_PDC_PTCR, AT91_PDC_TXTEN); + } - /* command not completed, have to wait */ - return 0; + /* command not completed, have to wait */ + return 0; } /* @@ -546,64 +532,64 @@ static int at91_mci_handle_cmdrdy(struct at91_mci *mci) */ static void at91_mci_completed_command(struct at91_mci *mci, rt_uint32_t status) { - struct rt_mmcsd_cmd *cmd = mci->cmd; - struct rt_mmcsd_data *data = cmd->data; + struct rt_mmcsd_cmd *cmd = mci->cmd; + struct rt_mmcsd_data *data = cmd->data; - at91_mci_write(AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); + at91_mci_write(AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); - cmd->resp[0] = at91_mci_read(AT91_MCI_RSPR(0)); - cmd->resp[1] = at91_mci_read(AT91_MCI_RSPR(1)); - cmd->resp[2] = at91_mci_read(AT91_MCI_RSPR(2)); - cmd->resp[3] = at91_mci_read(AT91_MCI_RSPR(3)); + cmd->resp[0] = at91_mci_read(AT91_MCI_RSPR(0)); + cmd->resp[1] = at91_mci_read(AT91_MCI_RSPR(1)); + cmd->resp[2] = at91_mci_read(AT91_MCI_RSPR(2)); + cmd->resp[3] = at91_mci_read(AT91_MCI_RSPR(3)); - if (mci->buf) - { - //rt_memcpy(data->buf, mci->buf, data->blksize*data->blks); - rt_free(mci->buf); - mci->buf = RT_NULL; - } + if (mci->buf) + { + //rt_memcpy(data->buf, mci->buf, data->blksize*data->blks); + rt_free(mci->buf); + mci->buf = RT_NULL; + } - mci_dbg("Status = %08X/%08x [%08X %08X %08X %08X]\n", - status, at91_mci_read(AT91_MCI_SR), - cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); + mci_dbg("Status = %08X/%08x [%08X %08X %08X %08X]\n", + status, at91_mci_read(AT91_MCI_SR), + cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); - if (status & AT91_MCI_ERRORS) - { - if ((status & AT91_MCI_RCRCE) && (resp_type(cmd) & (RESP_R3|RESP_R4))) - { - cmd->err = 0; - } - else - { - if (status & (AT91_MCI_DTOE | AT91_MCI_DCRCE)) - { - if (data) - { - if (status & AT91_MCI_DTOE) - data->err = -RT_ETIMEOUT; - else if (status & AT91_MCI_DCRCE) - data->err = -RT_ERROR; - } - } - else - { - if (status & AT91_MCI_RTOE) - cmd->err = -RT_ETIMEOUT; - else if (status & AT91_MCI_RCRCE) - cmd->err = -RT_ERROR; - else - cmd->err = -RT_ERROR; - } + if (status & AT91_MCI_ERRORS) + { + if ((status & AT91_MCI_RCRCE) && (resp_type(cmd) & (RESP_R3|RESP_R4))) + { + cmd->err = 0; + } + else + { + if (status & (AT91_MCI_DTOE | AT91_MCI_DCRCE)) + { + if (data) + { + if (status & AT91_MCI_DTOE) + data->err = -RT_ETIMEOUT; + else if (status & AT91_MCI_DCRCE) + data->err = -RT_ERROR; + } + } + else + { + if (status & AT91_MCI_RTOE) + cmd->err = -RT_ETIMEOUT; + else if (status & AT91_MCI_RCRCE) + cmd->err = -RT_ERROR; + else + cmd->err = -RT_ERROR; + } - rt_kprintf("error detected and set to %d/%d (cmd = %d)\n", - cmd->err, data ? data->err : 0, - cmd->cmd_code); - } - } - else - cmd->err = 0; + rt_kprintf("error detected and set to %d/%d (cmd = %d)\n", + cmd->err, data ? data->err : 0, + cmd->cmd_code); + } + } + else + cmd->err = 0; - at91_mci_process_next(mci); + at91_mci_process_next(mci); } /* @@ -611,120 +597,120 @@ static void at91_mci_completed_command(struct at91_mci *mci, rt_uint32_t status) */ static void at91_mci_irq(int irq, void *param) { - struct at91_mci *mci = (struct at91_mci *)param; - rt_int32_t completed = 0; - rt_uint32_t int_status, int_mask; + struct at91_mci *mci = (struct at91_mci *)param; + rt_int32_t completed = 0; + rt_uint32_t int_status, int_mask; - int_status = at91_mci_read(AT91_MCI_SR); - int_mask = at91_mci_read(AT91_MCI_IMR); + int_status = at91_mci_read(AT91_MCI_SR); + int_mask = at91_mci_read(AT91_MCI_IMR); - mci_dbg("MCI irq: status = %08X, %08X, %08X\n", int_status, int_mask, - int_status & int_mask); + mci_dbg("MCI irq: status = %08X, %08X, %08X\n", int_status, int_mask, + int_status & int_mask); - int_status = int_status & int_mask; + int_status = int_status & int_mask; - if (int_status & AT91_MCI_ERRORS) - { - completed = 1; + if (int_status & AT91_MCI_ERRORS) + { + completed = 1; - if (int_status & AT91_MCI_UNRE) - mci_dbg("MMC: Underrun error\n"); - if (int_status & AT91_MCI_OVRE) - mci_dbg("MMC: Overrun error\n"); - if (int_status & AT91_MCI_DTOE) - mci_dbg("MMC: Data timeout\n"); - if (int_status & AT91_MCI_DCRCE) - mci_dbg("MMC: CRC error in data\n"); - if (int_status & AT91_MCI_RTOE) - mci_dbg("MMC: Response timeout\n"); - if (int_status & AT91_MCI_RENDE) - mci_dbg("MMC: Response end bit error\n"); - if (int_status & AT91_MCI_RCRCE) - mci_dbg("MMC: Response CRC error\n"); - if (int_status & AT91_MCI_RDIRE) - mci_dbg("MMC: Response direction error\n"); - if (int_status & AT91_MCI_RINDE) - mci_dbg("MMC: Response index error\n"); - } - else - { - /* Only continue processing if no errors */ + if (int_status & AT91_MCI_UNRE) + mci_dbg("MMC: Underrun error\n"); + if (int_status & AT91_MCI_OVRE) + mci_dbg("MMC: Overrun error\n"); + if (int_status & AT91_MCI_DTOE) + mci_dbg("MMC: Data timeout\n"); + if (int_status & AT91_MCI_DCRCE) + mci_dbg("MMC: CRC error in data\n"); + if (int_status & AT91_MCI_RTOE) + mci_dbg("MMC: Response timeout\n"); + if (int_status & AT91_MCI_RENDE) + mci_dbg("MMC: Response end bit error\n"); + if (int_status & AT91_MCI_RCRCE) + mci_dbg("MMC: Response CRC error\n"); + if (int_status & AT91_MCI_RDIRE) + mci_dbg("MMC: Response direction error\n"); + if (int_status & AT91_MCI_RINDE) + mci_dbg("MMC: Response index error\n"); + } + else + { + /* Only continue processing if no errors */ - if (int_status & AT91_MCI_TXBUFE) - { - mci_dbg("TX buffer empty\n"); - at91_mci_handle_transmitted(mci); - } + if (int_status & AT91_MCI_TXBUFE) + { + mci_dbg("TX buffer empty\n"); + at91_mci_handle_transmitted(mci); + } - if (int_status & AT91_MCI_ENDRX) - { - mci_dbg("ENDRX\n"); - at91_mci_post_dma_read(mci); - } + if (int_status & AT91_MCI_ENDRX) + { + mci_dbg("ENDRX\n"); + at91_mci_post_dma_read(mci); + } - if (int_status & AT91_MCI_RXBUFF) - { - mci_dbg("RX buffer full\n"); - at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS); - at91_mci_write(AT91_MCI_IDR, AT91_MCI_RXBUFF | AT91_MCI_ENDRX); - completed = 1; - } + if (int_status & AT91_MCI_RXBUFF) + { + mci_dbg("RX buffer full\n"); + at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS); + at91_mci_write(AT91_MCI_IDR, AT91_MCI_RXBUFF | AT91_MCI_ENDRX); + completed = 1; + } - if (int_status & AT91_MCI_ENDTX) - mci_dbg("Transmit has ended\n"); + if (int_status & AT91_MCI_ENDTX) + mci_dbg("Transmit has ended\n"); - if (int_status & AT91_MCI_NOTBUSY) - { - mci_dbg("Card is ready\n"); - //at91_mci_update_bytes_xfered(host); - completed = 1; - } + if (int_status & AT91_MCI_NOTBUSY) + { + mci_dbg("Card is ready\n"); + //at91_mci_update_bytes_xfered(host); + completed = 1; + } - if (int_status & AT91_MCI_DTIP) - mci_dbg("Data transfer in progress\n"); + if (int_status & AT91_MCI_DTIP) + mci_dbg("Data transfer in progress\n"); - if (int_status & AT91_MCI_BLKE) - { - mci_dbg("Block transfer has ended\n"); - if (mci->req->data && mci->req->data->blks > 1) - { - /* multi block write : complete multi write - * command and send stop */ - completed = 1; - } - else - { - at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY); - } - } + if (int_status & AT91_MCI_BLKE) + { + mci_dbg("Block transfer has ended\n"); + if (mci->req->data && mci->req->data->blks > 1) + { + /* multi block write : complete multi write + * command and send stop */ + completed = 1; + } + else + { + at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY); + } + } - /*if (int_status & AT91_MCI_SDIOIRQA) - rt_mmcsd_signal_sdio_irq(host->mmc);*/ + /*if (int_status & AT91_MCI_SDIOIRQA) + rt_mmcsd_signal_sdio_irq(host->mmc);*/ - if (int_status & AT91_MCI_SDIOIRQB) - sdio_irq_wakeup(mci->host); + if (int_status & AT91_MCI_SDIOIRQB) + sdio_irq_wakeup(mci->host); - if (int_status & AT91_MCI_TXRDY) - mci_dbg("Ready to transmit\n"); + if (int_status & AT91_MCI_TXRDY) + mci_dbg("Ready to transmit\n"); - if (int_status & AT91_MCI_RXRDY) - mci_dbg("Ready to receive\n"); + if (int_status & AT91_MCI_RXRDY) + mci_dbg("Ready to receive\n"); - if (int_status & AT91_MCI_CMDRDY) - { - mci_dbg("Command ready\n"); - completed = at91_mci_handle_cmdrdy(mci); - } - } + if (int_status & AT91_MCI_CMDRDY) + { + mci_dbg("Command ready\n"); + completed = at91_mci_handle_cmdrdy(mci); + } + } - if (completed) - { - mci_dbg("Completed command\n"); - at91_mci_write(AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); - at91_mci_completed_command(mci, int_status); - } - else - at91_mci_write(AT91_MCI_IDR, int_status & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); + if (completed) + { + mci_dbg("Completed command\n"); + at91_mci_write(AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); + at91_mci_completed_command(mci, int_status); + } + else + at91_mci_write(AT91_MCI_IDR, int_status & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); } @@ -734,173 +720,173 @@ static void at91_mci_irq(int irq, void *param) */ static void at91_mci_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg) { - rt_uint32_t clkdiv; - //struct at91_mci *mci = host->private_data; - rt_uint32_t at91_master_clock = clk_get_rate(clk_get("mck")); + rt_uint32_t clkdiv; + //struct at91_mci *mci = host->private_data; + rt_uint32_t at91_master_clock = clk_get_rate(clk_get("mck")); - if (io_cfg->clock == 0) - { - /* Disable the MCI controller */ - at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS); - clkdiv = 0; - } - else - { - /* Enable the MCI controller */ - at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN); + if (io_cfg->clock == 0) + { + /* Disable the MCI controller */ + at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS); + clkdiv = 0; + } + else + { + /* Enable the MCI controller */ + at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN); - if ((at91_master_clock % (io_cfg->clock * 2)) == 0) - clkdiv = ((at91_master_clock / io_cfg->clock) / 2) - 1; - else - clkdiv = (at91_master_clock / io_cfg->clock) / 2; + if ((at91_master_clock % (io_cfg->clock * 2)) == 0) + clkdiv = ((at91_master_clock / io_cfg->clock) / 2) - 1; + else + clkdiv = (at91_master_clock / io_cfg->clock) / 2; - mci_dbg("clkdiv = %d. mcck = %ld\n", clkdiv, - at91_master_clock / (2 * (clkdiv + 1))); - } - if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4) - { - mci_dbg("MMC: Setting controller bus width to 4\n"); - at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) | AT91_MCI_SDCBUS); - } - else - { - mci_dbg("MMC: Setting controller bus width to 1\n"); - at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS); - } + mci_dbg("clkdiv = %d. mcck = %ld\n", clkdiv, + at91_master_clock / (2 * (clkdiv + 1))); + } + if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4) + { + mci_dbg("MMC: Setting controller bus width to 4\n"); + at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) | AT91_MCI_SDCBUS); + } + else + { + mci_dbg("MMC: Setting controller bus width to 1\n"); + at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS); + } - /* Set the clock divider */ - at91_mci_write(AT91_MCI_MR, (at91_mci_read(AT91_MCI_MR) & ~AT91_MCI_CLKDIV) | clkdiv); + /* Set the clock divider */ + at91_mci_write(AT91_MCI_MR, (at91_mci_read(AT91_MCI_MR) & ~AT91_MCI_CLKDIV) | clkdiv); - /* maybe switch power to the card */ - switch (io_cfg->power_mode) - { - case MMCSD_POWER_OFF: - break; - case MMCSD_POWER_UP: - break; - case MMCSD_POWER_ON: - /*at91_mci_write(AT91_MCI_ARGR, 0); - at91_mci_write(AT91_MCI_CMDR, 0|AT91_MCI_SPCMD_INIT|AT91_MCI_OPDCMD); - mci_dbg("MCI_SR=0x%08x\n", at91_mci_read(AT91_MCI_SR)); - while (!(at91_mci_read(AT91_MCI_SR) & AT91_MCI_CMDRDY)) - { - - } - mci_dbg("at91 mci power on\n");*/ - break; - default: - rt_kprintf("unknown power_mode %d\n", io_cfg->power_mode); - break; - } + /* maybe switch power to the card */ + switch (io_cfg->power_mode) + { + case MMCSD_POWER_OFF: + break; + case MMCSD_POWER_UP: + break; + case MMCSD_POWER_ON: + /*at91_mci_write(AT91_MCI_ARGR, 0); + at91_mci_write(AT91_MCI_CMDR, 0|AT91_MCI_SPCMD_INIT|AT91_MCI_OPDCMD); + mci_dbg("MCI_SR=0x%08x\n", at91_mci_read(AT91_MCI_SR)); + while (!(at91_mci_read(AT91_MCI_SR) & AT91_MCI_CMDRDY)) + { + + } + mci_dbg("at91 mci power on\n");*/ + break; + default: + rt_kprintf("unknown power_mode %d\n", io_cfg->power_mode); + break; + } } static void at91_mci_enable_sdio_irq(struct rt_mmcsd_host *host, rt_int32_t enable) { - at91_mci_write(enable ? AT91_MCI_IER : AT91_MCI_IDR, AT91_MCI_SDIOIRQB); + at91_mci_write(enable ? AT91_MCI_IER : AT91_MCI_IDR, AT91_MCI_SDIOIRQB); } static const struct rt_mmcsd_host_ops ops = { - at91_mci_request, - at91_mci_set_iocfg, + at91_mci_request, + at91_mci_set_iocfg, RT_NULL, - at91_mci_enable_sdio_irq, + at91_mci_enable_sdio_irq, }; void at91_mci_detect(int irq, void *param) { - rt_kprintf("mmcsd gpio detected\n"); + rt_kprintf("mmcsd gpio detected\n"); } static void mci_gpio_init() { #ifdef USE_SLOT_B - at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5)); - at91_sys_write(AT91_PIOA + PIO_PUDR, (1 << 8)); - at91_sys_write(AT91_PIOA + PIO_BSR, (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5)); - at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 8)); - at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5)|(1 << 8)); + at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5)); + at91_sys_write(AT91_PIOA + PIO_PUDR, (1 << 8)); + at91_sys_write(AT91_PIOA + PIO_BSR, (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5)); + at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 8)); + at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5)|(1 << 8)); - at91_sys_write(AT91_PIOA + PIO_IDR, (1 << 6)|(1 << 7)); - at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 6)|(1 << 7)); - at91_sys_write(AT91_PIOA + PIO_ODR, (1 << 6)|(1 << 7)); - at91_sys_write(AT91_PIOA + PIO_PER, (1 << 6)|(1 << 7)); + at91_sys_write(AT91_PIOA + PIO_IDR, (1 << 6)|(1 << 7)); + at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 6)|(1 << 7)); + at91_sys_write(AT91_PIOA + PIO_ODR, (1 << 6)|(1 << 7)); + at91_sys_write(AT91_PIOA + PIO_PER, (1 << 6)|(1 << 7)); #else - at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)); - at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 8)); - at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 8)); + at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)); + at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 8)); + at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 8)); #endif } int at91_mci_init(void) { - struct rt_mmcsd_host *host; - struct at91_mci *mci; + struct rt_mmcsd_host *host; + struct at91_mci *mci; - host = mmcsd_alloc_host(); - if (!host) - { - return -RT_ERROR; - } + host = mmcsd_alloc_host(); + if (!host) + { + return -RT_ERROR; + } - mci = rt_malloc(sizeof(struct at91_mci)); - if (!mci) - { - rt_kprintf("alloc mci failed\n"); - goto err; - } + mci = rt_malloc(sizeof(struct at91_mci)); + if (!mci) + { + rt_kprintf("alloc mci failed\n"); + goto err; + } - rt_memset(mci, 0, sizeof(struct at91_mci)); + rt_memset(mci, 0, sizeof(struct at91_mci)); - host->ops = &ops; - host->freq_min = 375000; - host->freq_max = 25000000; - host->valid_ocr = VDD_32_33 | VDD_33_34; - host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | \ - MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ; - host->max_seg_size = 65535; - host->max_dma_segs = 2; - host->max_blk_size = 512; - host->max_blk_count = 4096; + host->ops = &ops; + host->freq_min = 375000; + host->freq_max = 25000000; + host->valid_ocr = VDD_32_33 | VDD_33_34; + host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | \ + MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ; + host->max_seg_size = 65535; + host->max_dma_segs = 2; + host->max_blk_size = 512; + host->max_blk_count = 4096; - mci->host = host; + mci->host = host; - mci_gpio_init(); - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_MCI); //enable MCI clock - - at91_mci_disable(); - at91_mci_enable(); + mci_gpio_init(); + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_MCI); //enable MCI clock - /* instal interrupt */ - rt_hw_interrupt_install(AT91SAM9260_ID_MCI, at91_mci_irq, - (void *)mci, "MMC"); - rt_hw_interrupt_umask(AT91SAM9260_ID_MCI); - rt_hw_interrupt_install(gpio_to_irq(AT91_PIN_PA7), - at91_mci_detect, RT_NULL, "MMC_DETECT"); - rt_hw_interrupt_umask(gpio_to_irq(AT91_PIN_PA7)); + at91_mci_disable(); + at91_mci_enable(); - rt_timer_init(&mci->timer, "mci_timer", - at91_timeout_timer, - mci, - RT_TICK_PER_SECOND, - RT_TIMER_FLAG_PERIODIC); + /* instal interrupt */ + rt_hw_interrupt_install(AT91SAM9260_ID_MCI, at91_mci_irq, + (void *)mci, "MMC"); + rt_hw_interrupt_umask(AT91SAM9260_ID_MCI); + rt_hw_interrupt_install(gpio_to_irq(AT91_PIN_PA7), + at91_mci_detect, RT_NULL, "MMC_DETECT"); + rt_hw_interrupt_umask(gpio_to_irq(AT91_PIN_PA7)); - //rt_timer_start(&mci->timer); + rt_timer_init(&mci->timer, "mci_timer", + at91_timeout_timer, + mci, + RT_TICK_PER_SECOND, + RT_TIMER_FLAG_PERIODIC); - //rt_sem_init(&mci->sem_ack, "sd_ack", 0, RT_IPC_FLAG_FIFO); + //rt_timer_start(&mci->timer); - host->private_data = mci; + //rt_sem_init(&mci->sem_ack, "sd_ack", 0, RT_IPC_FLAG_FIFO); - mmcsd_change(host); + host->private_data = mci; - return 0; + mmcsd_change(host); + + return 0; err: - mmcsd_free_host(host); + mmcsd_free_host(host); - return -RT_ENOMEM; + return -RT_ENOMEM; } INIT_DEVICE_EXPORT(at91_mci_init); @@ -910,15 +896,15 @@ FINSH_FUNCTION_EXPORT(at91_mci_init, at91sam9260 sd init); void mci_dump(void) { - rt_uint32_t i; + rt_uint32_t i; - rt_kprintf("PIOA_PSR=0x%08x\n", at91_sys_read(AT91_PIOA+PIO_PSR)); - rt_kprintf("PIOA_ABSR=0x%08x\n", at91_sys_read(AT91_PIOA+PIO_ABSR)); - rt_kprintf("PIOA_PUSR=0x%08x\n", at91_sys_read(AT91_PIOA+PIO_PUSR)); + rt_kprintf("PIOA_PSR=0x%08x\n", at91_sys_read(AT91_PIOA+PIO_PSR)); + rt_kprintf("PIOA_ABSR=0x%08x\n", at91_sys_read(AT91_PIOA+PIO_ABSR)); + rt_kprintf("PIOA_PUSR=0x%08x\n", at91_sys_read(AT91_PIOA+PIO_PUSR)); - for (i = 0; i <= 0x4c; i += 4) { - rt_kprintf("0x%08x:0x%08x\n", AT91SAM9260_BASE_MCI+i, at91_mci_read(i)); - } + for (i = 0; i <= 0x4c; i += 4) { + rt_kprintf("0x%08x:0x%08x\n", AT91SAM9260_BASE_MCI+i, at91_mci_read(i)); + } } FINSH_FUNCTION_EXPORT(mci_dump, dump register for mci); diff --git a/bsp/at91sam9260/drivers/at91_mci.h b/bsp/at91sam9260/drivers/at91_mci.h index 4e3bae9999..80eb07385d 100644 --- a/bsp/at91sam9260/drivers/at91_mci.h +++ b/bsp/at91sam9260/drivers/at91_mci.h @@ -1,21 +1,7 @@ /* - * File : at91_mci.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -25,99 +11,99 @@ #ifndef __AT91_MCI_H__ #define __AT91_MCI_H__ -#define AT91_MCI_CR 0x00 /* Control Register */ -#define AT91_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */ -#define AT91_MCI_MCIDIS (1 << 1) /* Multi-Media Interface Disable */ -#define AT91_MCI_PWSEN (1 << 2) /* Power Save Mode Enable */ -#define AT91_MCI_PWSDIS (1 << 3) /* Power Save Mode Disable */ -#define AT91_MCI_SWRST (1 << 7) /* Software Reset */ +#define AT91_MCI_CR 0x00 /* Control Register */ +#define AT91_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */ +#define AT91_MCI_MCIDIS (1 << 1) /* Multi-Media Interface Disable */ +#define AT91_MCI_PWSEN (1 << 2) /* Power Save Mode Enable */ +#define AT91_MCI_PWSDIS (1 << 3) /* Power Save Mode Disable */ +#define AT91_MCI_SWRST (1 << 7) /* Software Reset */ -#define AT91_MCI_MR 0x04 /* Mode Register */ -#define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */ -#define AT91_MCI_PWSDIV (7 << 8) /* Power Saving Divider */ -#define AT91_MCI_RDPROOF (1 << 11) /* Read Proof Enable [SAM926[03] only] */ -#define AT91_MCI_WRPROOF (1 << 12) /* Write Proof Enable [SAM926[03] only] */ -#define AT91_MCI_PDCFBYTE (1 << 13) /* PDC Force Byte Transfer [SAM926[03] only] */ -#define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */ -#define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */ -#define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */ +#define AT91_MCI_MR 0x04 /* Mode Register */ +#define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */ +#define AT91_MCI_PWSDIV (7 << 8) /* Power Saving Divider */ +#define AT91_MCI_RDPROOF (1 << 11) /* Read Proof Enable [SAM926[03] only] */ +#define AT91_MCI_WRPROOF (1 << 12) /* Write Proof Enable [SAM926[03] only] */ +#define AT91_MCI_PDCFBYTE (1 << 13) /* PDC Force Byte Transfer [SAM926[03] only] */ +#define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */ +#define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */ +#define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */ -#define AT91_MCI_DTOR 0x08 /* Data Timeout Register */ -#define AT91_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */ -#define AT91_MCI_DTOMUL (7 << 4) /* Data Timeout Multiplier */ -#define AT91_MCI_DTOMUL_1 (0 << 4) -#define AT91_MCI_DTOMUL_16 (1 << 4) -#define AT91_MCI_DTOMUL_128 (2 << 4) -#define AT91_MCI_DTOMUL_256 (3 << 4) -#define AT91_MCI_DTOMUL_1K (4 << 4) -#define AT91_MCI_DTOMUL_4K (5 << 4) -#define AT91_MCI_DTOMUL_64K (6 << 4) -#define AT91_MCI_DTOMUL_1M (7 << 4) +#define AT91_MCI_DTOR 0x08 /* Data Timeout Register */ +#define AT91_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */ +#define AT91_MCI_DTOMUL (7 << 4) /* Data Timeout Multiplier */ +#define AT91_MCI_DTOMUL_1 (0 << 4) +#define AT91_MCI_DTOMUL_16 (1 << 4) +#define AT91_MCI_DTOMUL_128 (2 << 4) +#define AT91_MCI_DTOMUL_256 (3 << 4) +#define AT91_MCI_DTOMUL_1K (4 << 4) +#define AT91_MCI_DTOMUL_4K (5 << 4) +#define AT91_MCI_DTOMUL_64K (6 << 4) +#define AT91_MCI_DTOMUL_1M (7 << 4) -#define AT91_MCI_SDCR 0x0c /* SD Card Register */ -#define AT91_MCI_SDCSEL (3 << 0) /* SD Card Selector */ -#define AT91_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */ +#define AT91_MCI_SDCR 0x0c /* SD Card Register */ +#define AT91_MCI_SDCSEL (3 << 0) /* SD Card Selector */ +#define AT91_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */ -#define AT91_MCI_ARGR 0x10 /* Argument Register */ +#define AT91_MCI_ARGR 0x10 /* Argument Register */ -#define AT91_MCI_CMDR 0x14 /* Command Register */ -#define AT91_MCI_CMDNB (0x3f << 0) /* Command Number */ -#define AT91_MCI_RSPTYP (3 << 6) /* Response Type */ -#define AT91_MCI_RSPTYP_NONE (0 << 6) -#define AT91_MCI_RSPTYP_48 (1 << 6) -#define AT91_MCI_RSPTYP_136 (2 << 6) -#define AT91_MCI_SPCMD (7 << 8) /* Special Command */ -#define AT91_MCI_SPCMD_NONE (0 << 8) -#define AT91_MCI_SPCMD_INIT (1 << 8) -#define AT91_MCI_SPCMD_SYNC (2 << 8) -#define AT91_MCI_SPCMD_ICMD (4 << 8) -#define AT91_MCI_SPCMD_IRESP (5 << 8) -#define AT91_MCI_OPDCMD (1 << 11) /* Open Drain Command */ -#define AT91_MCI_MAXLAT (1 << 12) /* Max Latency for Command to Response */ -#define AT91_MCI_TRCMD (3 << 16) /* Transfer Command */ -#define AT91_MCI_TRCMD_NONE (0 << 16) -#define AT91_MCI_TRCMD_START (1 << 16) -#define AT91_MCI_TRCMD_STOP (2 << 16) -#define AT91_MCI_TRDIR (1 << 18) /* Transfer Direction */ -#define AT91_MCI_TRTYP (3 << 19) /* Transfer Type */ -#define AT91_MCI_TRTYP_BLOCK (0 << 19) -#define AT91_MCI_TRTYP_MULTIPLE (1 << 19) -#define AT91_MCI_TRTYP_STREAM (2 << 19) +#define AT91_MCI_CMDR 0x14 /* Command Register */ +#define AT91_MCI_CMDNB (0x3f << 0) /* Command Number */ +#define AT91_MCI_RSPTYP (3 << 6) /* Response Type */ +#define AT91_MCI_RSPTYP_NONE (0 << 6) +#define AT91_MCI_RSPTYP_48 (1 << 6) +#define AT91_MCI_RSPTYP_136 (2 << 6) +#define AT91_MCI_SPCMD (7 << 8) /* Special Command */ +#define AT91_MCI_SPCMD_NONE (0 << 8) +#define AT91_MCI_SPCMD_INIT (1 << 8) +#define AT91_MCI_SPCMD_SYNC (2 << 8) +#define AT91_MCI_SPCMD_ICMD (4 << 8) +#define AT91_MCI_SPCMD_IRESP (5 << 8) +#define AT91_MCI_OPDCMD (1 << 11) /* Open Drain Command */ +#define AT91_MCI_MAXLAT (1 << 12) /* Max Latency for Command to Response */ +#define AT91_MCI_TRCMD (3 << 16) /* Transfer Command */ +#define AT91_MCI_TRCMD_NONE (0 << 16) +#define AT91_MCI_TRCMD_START (1 << 16) +#define AT91_MCI_TRCMD_STOP (2 << 16) +#define AT91_MCI_TRDIR (1 << 18) /* Transfer Direction */ +#define AT91_MCI_TRTYP (3 << 19) /* Transfer Type */ +#define AT91_MCI_TRTYP_BLOCK (0 << 19) +#define AT91_MCI_TRTYP_MULTIPLE (1 << 19) +#define AT91_MCI_TRTYP_STREAM (2 << 19) -#define AT91_MCI_BLKR 0x18 /* Block Register */ -#define AT91_MCI_BLKR_BCNT(n) ((0xffff & (n)) << 0) /* Block count */ -#define AT91_MCI_BLKR_BLKLEN(n) ((0xffff & (n)) << 16) /* Block lenght */ +#define AT91_MCI_BLKR 0x18 /* Block Register */ +#define AT91_MCI_BLKR_BCNT(n) ((0xffff & (n)) << 0) /* Block count */ +#define AT91_MCI_BLKR_BLKLEN(n) ((0xffff & (n)) << 16) /* Block lenght */ -#define AT91_MCI_RSPR(n) (0x20 + ((n) * 4)) /* Response Registers 0-3 */ -#define AT91_MCR_RDR 0x30 /* Receive Data Register */ -#define AT91_MCR_TDR 0x34 /* Transmit Data Register */ +#define AT91_MCI_RSPR(n) (0x20 + ((n) * 4)) /* Response Registers 0-3 */ +#define AT91_MCR_RDR 0x30 /* Receive Data Register */ +#define AT91_MCR_TDR 0x34 /* Transmit Data Register */ -#define AT91_MCI_SR 0x40 /* Status Register */ -#define AT91_MCI_CMDRDY (1U << 0) /* Command Ready */ -#define AT91_MCI_RXRDY (1U << 1) /* Receiver Ready */ -#define AT91_MCI_TXRDY (1U << 2) /* Transmit Ready */ -#define AT91_MCI_BLKE (1U << 3) /* Data Block Ended */ -#define AT91_MCI_DTIP (1U << 4) /* Data Transfer in Progress */ -#define AT91_MCI_NOTBUSY (1U << 5) /* Data Not Busy */ -#define AT91_MCI_ENDRX (1U << 6) /* End of RX Buffer */ -#define AT91_MCI_ENDTX (1U << 7) /* End fo TX Buffer */ -#define AT91_MCI_SDIOIRQA (1U << 8) /* SDIO Interrupt for Slot A */ -#define AT91_MCI_SDIOIRQB (1U << 9) /* SDIO Interrupt for Slot B */ -#define AT91_MCI_RXBUFF (1U << 14) /* RX Buffer Full */ -#define AT91_MCI_TXBUFE (1U << 15) /* TX Buffer Empty */ -#define AT91_MCI_RINDE (1U << 16) /* Response Index Error */ -#define AT91_MCI_RDIRE (1U << 17) /* Response Direction Error */ -#define AT91_MCI_RCRCE (1U << 18) /* Response CRC Error */ -#define AT91_MCI_RENDE (1U << 19) /* Response End Bit Error */ -#define AT91_MCI_RTOE (1U << 20) /* Reponse Time-out Error */ -#define AT91_MCI_DCRCE (1U << 21) /* Data CRC Error */ -#define AT91_MCI_DTOE (1U << 22) /* Data Time-out Error */ -#define AT91_MCI_OVRE (1U << 30) /* Overrun */ -#define AT91_MCI_UNRE (1U << 31) /* Underrun */ +#define AT91_MCI_SR 0x40 /* Status Register */ +#define AT91_MCI_CMDRDY (1U << 0) /* Command Ready */ +#define AT91_MCI_RXRDY (1U << 1) /* Receiver Ready */ +#define AT91_MCI_TXRDY (1U << 2) /* Transmit Ready */ +#define AT91_MCI_BLKE (1U << 3) /* Data Block Ended */ +#define AT91_MCI_DTIP (1U << 4) /* Data Transfer in Progress */ +#define AT91_MCI_NOTBUSY (1U << 5) /* Data Not Busy */ +#define AT91_MCI_ENDRX (1U << 6) /* End of RX Buffer */ +#define AT91_MCI_ENDTX (1U << 7) /* End fo TX Buffer */ +#define AT91_MCI_SDIOIRQA (1U << 8) /* SDIO Interrupt for Slot A */ +#define AT91_MCI_SDIOIRQB (1U << 9) /* SDIO Interrupt for Slot B */ +#define AT91_MCI_RXBUFF (1U << 14) /* RX Buffer Full */ +#define AT91_MCI_TXBUFE (1U << 15) /* TX Buffer Empty */ +#define AT91_MCI_RINDE (1U << 16) /* Response Index Error */ +#define AT91_MCI_RDIRE (1U << 17) /* Response Direction Error */ +#define AT91_MCI_RCRCE (1U << 18) /* Response CRC Error */ +#define AT91_MCI_RENDE (1U << 19) /* Response End Bit Error */ +#define AT91_MCI_RTOE (1U << 20) /* Reponse Time-out Error */ +#define AT91_MCI_DCRCE (1U << 21) /* Data CRC Error */ +#define AT91_MCI_DTOE (1U << 22) /* Data Time-out Error */ +#define AT91_MCI_OVRE (1U << 30) /* Overrun */ +#define AT91_MCI_UNRE (1U << 31) /* Underrun */ -#define AT91_MCI_IER 0x44 /* Interrupt Enable Register */ -#define AT91_MCI_IDR 0x48 /* Interrupt Disable Register */ -#define AT91_MCI_IMR 0x4c /* Interrupt Mask Register */ +#define AT91_MCI_IER 0x44 /* Interrupt Enable Register */ +#define AT91_MCI_IDR 0x48 /* Interrupt Disable Register */ +#define AT91_MCI_IMR 0x4c /* Interrupt Mask Register */ extern int at91_mci_init(void); diff --git a/bsp/at91sam9260/drivers/board.c b/bsp/at91sam9260/drivers/board.c index a7ec6008da..8a063cfc86 100644 --- a/bsp/at91sam9260/drivers/board.c +++ b/bsp/at91sam9260/drivers/board.c @@ -1,21 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2009 RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -54,56 +40,56 @@ extern void rt_hw_set_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv); extern void rt_dbgu_isr(void); static struct mem_desc at91_mem_desc[] = { - { 0x00000000, 0xFFFFFFFF, 0x00000000, RW_NCNB }, /* None cached for 4G memory */ - { 0x20000000, 0x24000000-1, 0x20000000, RW_CB }, /* 64M cached SDRAM memory */ - { 0x00000000, 0x100000, 0x20000000, RW_CB }, /* isr vector table */ - { 0x90000000, 0x90400000-1, 0x00200000, RW_NCNB }, /* 4K SRAM0@2M + 4k SRAM1@3M + 16k UHP@5M */ - { 0xA0000000, 0xA4000000-1, 0x20000000, RW_NCNB } /* 64M none-cached SDRAM memory */ + { 0x00000000, 0xFFFFFFFF, 0x00000000, RW_NCNB }, /* None cached for 4G memory */ + { 0x20000000, 0x24000000-1, 0x20000000, RW_CB }, /* 64M cached SDRAM memory */ + { 0x00000000, 0x100000, 0x20000000, RW_CB }, /* isr vector table */ + { 0x90000000, 0x90400000-1, 0x00200000, RW_NCNB }, /* 4K SRAM0@2M + 4k SRAM1@3M + 16k UHP@5M */ + { 0xA0000000, 0xA4000000-1, 0x20000000, RW_NCNB } /* 64M none-cached SDRAM memory */ }; -#define PIT_CPIV(x) ((x) & AT91_PIT_CPIV) -#define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20) +#define PIT_CPIV(x) ((x) & AT91_PIT_CPIV) +#define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20) -static rt_uint32_t pit_cycle; /* write-once */ -static rt_uint32_t pit_cnt; /* access only w/system irq blocked */ +static rt_uint32_t pit_cycle; /* write-once */ +static rt_uint32_t pit_cnt; /* access only w/system irq blocked */ /** * This function will handle rtos timer */ void rt_timer_handler(int vector, void *param) { - #ifdef RT_USING_DBGU - if (at91_sys_read(AT91_DBGU + AT91_US_CSR) & 0x1) - { - rt_dbgu_isr(); - } - #endif - if (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS) - { - unsigned nr_ticks; + #ifdef RT_USING_DBGU + if (at91_sys_read(AT91_DBGU + AT91_US_CSR) & 0x1) + { + rt_dbgu_isr(); + } + #endif + if (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS) + { + unsigned nr_ticks; - /* Get number of ticks performed before irq, and ack it */ - nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR)); - rt_tick_increase(); - } + /* Get number of ticks performed before irq, and ack it */ + nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR)); + rt_tick_increase(); + } } static void at91sam926x_pit_reset(void) { - /* Disable timer and irqs */ - at91_sys_write(AT91_PIT_MR, 0); + /* Disable timer and irqs */ + at91_sys_write(AT91_PIT_MR, 0); - /* Clear any pending interrupts, wait for PIT to stop counting */ - while (PIT_CPIV(at91_sys_read(AT91_PIT_PIVR)) != 0) - ; + /* Clear any pending interrupts, wait for PIT to stop counting */ + while (PIT_CPIV(at91_sys_read(AT91_PIT_PIVR)) != 0) + ; - /* Start PIT but don't enable IRQ */ - //at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN); - pit_cnt += pit_cycle * PIT_PICNT(at91_sys_read(AT91_PIT_PIVR)); - at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN - | AT91_PIT_PITIEN); - rt_kprintf("PIT_MR=0x%08x\n", at91_sys_read(AT91_PIT_MR)); + /* Start PIT but don't enable IRQ */ + //at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN); + pit_cnt += pit_cycle * PIT_PICNT(at91_sys_read(AT91_PIT_PIVR)); + at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN + | AT91_PIT_PITIEN); + rt_kprintf("PIT_MR=0x%08x\n", at91_sys_read(AT91_PIT_MR)); } /* @@ -111,19 +97,19 @@ static void at91sam926x_pit_reset(void) */ static void at91sam926x_pit_init(void) { - rt_uint32_t pit_rate; - rt_uint32_t bits; + rt_uint32_t pit_rate; + rt_uint32_t bits; - /* - * Use our actual MCK to figure out how many MCK/16 ticks per - * 1/HZ period (instead of a compile-time constant LATCH). - */ - pit_rate = clk_get_rate(clk_get("mck")) / 16; - rt_kprintf("pit_rate=%dHZ\n", pit_rate); - pit_cycle = (pit_rate + RT_TICK_PER_SECOND/2) / RT_TICK_PER_SECOND; + /* + * Use our actual MCK to figure out how many MCK/16 ticks per + * 1/HZ period (instead of a compile-time constant LATCH). + */ + pit_rate = clk_get_rate(clk_get("mck")) / 16; + rt_kprintf("pit_rate=%dHZ\n", pit_rate); + pit_cycle = (pit_rate + RT_TICK_PER_SECOND/2) / RT_TICK_PER_SECOND; - /* Initialize and enable the timer */ - at91sam926x_pit_reset(); + /* Initialize and enable the timer */ + at91sam926x_pit_reset(); } @@ -132,69 +118,69 @@ static void at91sam926x_pit_init(void) */ void rt_hw_timer_init() { - at91sam926x_pit_init(); + at91sam926x_pit_init(); - /* install interrupt handler */ - rt_hw_interrupt_install(AT91_ID_SYS, rt_timer_handler, - RT_NULL, "system"); - rt_hw_interrupt_umask(AT91_ID_SYS); + /* install interrupt handler */ + rt_hw_interrupt_install(AT91_ID_SYS, rt_timer_handler, + RT_NULL, "system"); + rt_hw_interrupt_umask(AT91_ID_SYS); } - + void at91_tc1_init() { - at91_sys_write(AT91_PMC_PCER, 1<CSR & TXRDY)); - DBGU->THR = c; + DBGU->THR = c; } /** @@ -205,33 +191,33 @@ static void at91_usart_putc(char c) */ void rt_hw_console_output(const char* str) { - while (*str) - { - if (*str=='\n') - { - at91_usart_putc('\r'); - } + while (*str) + { + if (*str=='\n') + { + at91_usart_putc('\r'); + } - at91_usart_putc(*str++); - } + at91_usart_putc(*str++); + } } static void rt_hw_console_init(void) { - int div; - int mode = 0; + int div; + int mode = 0; - DBGU->CR = AT91_US_RSTTX | AT91_US_RSTRX | - AT91_US_RXDIS | AT91_US_TXDIS; - mode |= AT91_US_USMODE_NORMAL | AT91_US_USCLKS_MCK | - AT91_US_CHMODE_NORMAL; - mode |= AT91_US_CHRL_8; - mode |= AT91_US_NBSTOP_1; - mode |= AT91_US_PAR_NONE; - DBGU->MR = mode; - div = (clk_get_rate(clk_get("mck")) / 16 + BPS/2) / BPS; - DBGU->BRGR = div; - DBGU->CR = AT91_US_RXEN | AT91_US_TXEN; + DBGU->CR = AT91_US_RSTTX | AT91_US_RSTRX | + AT91_US_RXDIS | AT91_US_TXDIS; + mode |= AT91_US_USMODE_NORMAL | AT91_US_USCLKS_MCK | + AT91_US_CHMODE_NORMAL; + mode |= AT91_US_CHRL_8; + mode |= AT91_US_NBSTOP_1; + mode |= AT91_US_PAR_NONE; + DBGU->MR = mode; + div = (clk_get_rate(clk_get("mck")) / 16 + BPS/2) / BPS; + DBGU->BRGR = div; + DBGU->CR = AT91_US_RXEN | AT91_US_TXEN; } @@ -240,31 +226,31 @@ static void rt_hw_console_init(void) */ void rt_hw_board_init() { - /* initialize the system clock */ - rt_hw_clock_init(); + /* initialize the system clock */ + rt_hw_clock_init(); - /* initialize console */ - rt_hw_console_init(); + /* initialize console */ + rt_hw_console_init(); - /* initialize mmu */ - rt_hw_mmu_init(at91_mem_desc, sizeof(at91_mem_desc)/sizeof(at91_mem_desc[0])); + /* initialize mmu */ + rt_hw_mmu_init(at91_mem_desc, sizeof(at91_mem_desc)/sizeof(at91_mem_desc[0])); - /* initialize hardware interrupt */ - rt_hw_interrupt_init(); + /* initialize hardware interrupt */ + rt_hw_interrupt_init(); - /* initialize early device */ + /* initialize early device */ #ifdef RT_USING_COMPONENTS_INIT - rt_components_board_init(); + rt_components_board_init(); #endif #ifdef RT_USING_CONSOLE - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); #endif - /* initialize timer0 */ - rt_hw_timer_init(); + /* initialize timer0 */ + rt_hw_timer_init(); /* initialize board */ #ifdef RT_USING_HEAP - rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); #endif } diff --git a/bsp/at91sam9260/drivers/board.h b/bsp/at91sam9260/drivers/board.h index e6c8f77865..c3f4435077 100644 --- a/bsp/at91sam9260/drivers/board.h +++ b/bsp/at91sam9260/drivers/board.h @@ -1,21 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/at91sam9260/drivers/led.c b/bsp/at91sam9260/drivers/led.c index 3791b2a568..10277813d4 100644 --- a/bsp/at91sam9260/drivers/led.c +++ b/bsp/at91sam9260/drivers/led.c @@ -1,21 +1,7 @@ /* - * File : led.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -28,59 +14,59 @@ #if 1 // GB9260 board -#define PIO_LED AT91_PIOB -#define LED1 (1 << 25) // LED_SYS -#define LED2 (0) -#define LED3 (1 << 23) // LED_USR -#define LED_ALL (LED1 | LED2 | LED3) +#define PIO_LED AT91_PIOB +#define LED1 (1 << 25) // LED_SYS +#define LED2 (0) +#define LED3 (1 << 23) // LED_USR +#define LED_ALL (LED1 | LED2 | LED3) #else -#define PIO_LED AT91_PIOC -#define LED1 (1 << 8) -#define LED2 (1 << 11) -#define LED3 (1 << 6) -#define LED_ALL (LED1 | LED2 | LED3) +#define PIO_LED AT91_PIOC +#define LED1 (1 << 8) +#define LED2 (1 << 11) +#define LED3 (1 << 6) +#define LED_ALL (LED1 | LED2 | LED3) #endif void led_init(void) { - at91_sys_write(PIO_LED+0x00, LED_ALL); - at91_sys_write(PIO_LED+0x10, LED_ALL); - at91_sys_write(PIO_LED+0x64, LED_ALL); - at91_sys_write(PIO_LED+0x30, LED_ALL); + at91_sys_write(PIO_LED+0x00, LED_ALL); + at91_sys_write(PIO_LED+0x10, LED_ALL); + at91_sys_write(PIO_LED+0x64, LED_ALL); + at91_sys_write(PIO_LED+0x30, LED_ALL); } void led_on(int num) { - switch(num) - { - case 1: - at91_sys_write(PIO_LED+0x34, LED1); - break; - case 2: - at91_sys_write(PIO_LED+0x34, LED2); - break; - case 3: - at91_sys_write(PIO_LED+0x34, LED3); - break; - default: - break; - } + switch(num) + { + case 1: + at91_sys_write(PIO_LED+0x34, LED1); + break; + case 2: + at91_sys_write(PIO_LED+0x34, LED2); + break; + case 3: + at91_sys_write(PIO_LED+0x34, LED3); + break; + default: + break; + } } void led_off(int num) { - switch(num) - { - case 1: - at91_sys_write(PIO_LED+0x30, LED1); - break; - case 2: - at91_sys_write(PIO_LED+0x30, LED2); - break; - case 3: - at91_sys_write(PIO_LED+0x30, LED3); - break; - default: - break; - } + switch(num) + { + case 1: + at91_sys_write(PIO_LED+0x30, LED1); + break; + case 2: + at91_sys_write(PIO_LED+0x30, LED2); + break; + case 3: + at91_sys_write(PIO_LED+0x30, LED3); + break; + default: + break; + } } diff --git a/bsp/at91sam9260/drivers/led.h b/bsp/at91sam9260/drivers/led.h index f2967bc92d..9836eff709 100644 --- a/bsp/at91sam9260/drivers/led.h +++ b/bsp/at91sam9260/drivers/led.h @@ -1,21 +1,7 @@ /* - * File : led.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/at91sam9260/drivers/macb.c b/bsp/at91sam9260/drivers/macb.c index 26400c62de..702d7e04a4 100644 --- a/bsp/at91sam9260/drivers/macb.c +++ b/bsp/at91sam9260/drivers/macb.c @@ -1,21 +1,7 @@ /* - * File : macb.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -28,7 +14,7 @@ #include #include "macb.h" -#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<31)) +#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<31)) extern void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size); extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size); @@ -36,11 +22,11 @@ extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size); /* Cache macros - Packet buffers would be from pbuf pool which is cached */ #define EMAC_VIRT_NOCACHE(addr) (addr) #define EMAC_CACHE_INVALIDATE(addr, size) \ - mmu_invalidate_dcache((rt_uint32_t)addr, size) + mmu_invalidate_dcache((rt_uint32_t)addr, size) #define EMAC_CACHE_WRITEBACK(addr, size) \ - mmu_clean_dcache((rt_uint32_t)addr, size) + mmu_clean_dcache((rt_uint32_t)addr, size) #define EMAC_CACHE_WRITEBACK_INVALIDATE(addr, size) \ - mmu_clean_invalidated_dcache((rt_uint32_t)addr, size) + mmu_clean_invalidated_dcache((rt_uint32_t)addr, size) /* EMAC has BD's in cached memory - so need cache functions */ #define BD_CACHE_INVALIDATE(addr, size) @@ -50,7 +36,7 @@ extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size); /* EMAC internal utility function */ rt_inline unsigned long emac_virt_to_phys(unsigned long addr) { - return addr; + return addr; } @@ -59,112 +45,112 @@ rt_inline unsigned long emac_virt_to_phys(unsigned long addr) #define MACB_TX_SRAM #if defined(MACB_TX_SRAM) -#define MACB_TX_RING_SIZE 2 -#define MACB_TX_BUFFER_SIZE (1536 * MACB_TX_RING_SIZE) -#define TX_RING_BYTES (sizeof(struct macb_dma_desc) * MACB_TX_RING_SIZE) +#define MACB_TX_RING_SIZE 2 +#define MACB_TX_BUFFER_SIZE (1536 * MACB_TX_RING_SIZE) +#define TX_RING_BYTES (sizeof(struct macb_dma_desc) * MACB_TX_RING_SIZE) #else -#define MACB_TX_RING_SIZE 16 -#define MACB_TX_BUFFER_SIZE (1536 * MACB_TX_RING_SIZE) +#define MACB_TX_RING_SIZE 16 +#define MACB_TX_BUFFER_SIZE (1536 * MACB_TX_RING_SIZE) #endif -#define MACB_RX_BUFFER_SIZE (4096*4) -#define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128) +#define MACB_RX_BUFFER_SIZE (4096*4) +#define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128) -#define DEF_TX_RING_PENDING (MACB_TX_RING_SIZE) +#define DEF_TX_RING_PENDING (MACB_TX_RING_SIZE) -#define TX_RING_GAP(macb) \ - (MACB_TX_RING_SIZE - (macb)->tx_pending) +#define TX_RING_GAP(macb) \ + (MACB_TX_RING_SIZE - (macb)->tx_pending) -#define TX_BUFFS_AVAIL(macb) \ - (((macb)->tx_tail <= (macb)->tx_head) ? \ - (macb)->tx_tail + (macb)->tx_pending - (macb)->tx_head : \ - (macb)->tx_tail - (macb)->tx_head - TX_RING_GAP(macb)) +#define TX_BUFFS_AVAIL(macb) \ + (((macb)->tx_tail <= (macb)->tx_head) ? \ + (macb)->tx_tail + (macb)->tx_pending - (macb)->tx_head : \ + (macb)->tx_tail - (macb)->tx_head - TX_RING_GAP(macb)) -#define NEXT_TX(n) (((n) + 1) & (MACB_TX_RING_SIZE - 1)) +#define NEXT_TX(n) (((n) + 1) & (MACB_TX_RING_SIZE - 1)) -#define NEXT_RX(n) (((n) + 1) & (MACB_RX_RING_SIZE - 1)) +#define NEXT_RX(n) (((n) + 1) & (MACB_RX_RING_SIZE - 1)) /* minimum number of free TX descriptors before waking up TX process */ -#define MACB_TX_WAKEUP_THRESH (MACB_TX_RING_SIZE / 4) +#define MACB_TX_WAKEUP_THRESH (MACB_TX_RING_SIZE / 4) -#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \ - | MACB_BIT(ISR_ROVR)) +#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \ + | MACB_BIT(ISR_ROVR)) -#define MACB_TX_TIMEOUT 1000 -#define MACB_AUTONEG_TIMEOUT 5000000 -#define MACB_LINK_TIMEOUT 500000 +#define MACB_TX_TIMEOUT 1000 +#define MACB_AUTONEG_TIMEOUT 5000000 +#define MACB_LINK_TIMEOUT 500000 #define CONFIG_RMII struct macb_dma_desc { - rt_uint32_t addr; - rt_uint32_t ctrl; + rt_uint32_t addr; + rt_uint32_t ctrl; }; -#define RXADDR_USED 0x00000001 -#define RXADDR_WRAP 0x00000002 +#define RXADDR_USED 0x00000001 +#define RXADDR_WRAP 0x00000002 -#define RXBUF_FRMLEN_MASK 0x00000fff -#define RXBUF_FRAME_START 0x00004000 -#define RXBUF_FRAME_END 0x00008000 -#define RXBUF_TYPEID_MATCH 0x00400000 -#define RXBUF_ADDR4_MATCH 0x00800000 -#define RXBUF_ADDR3_MATCH 0x01000000 -#define RXBUF_ADDR2_MATCH 0x02000000 -#define RXBUF_ADDR1_MATCH 0x04000000 -#define RXBUF_BROADCAST 0x80000000 +#define RXBUF_FRMLEN_MASK 0x00000fff +#define RXBUF_FRAME_START 0x00004000 +#define RXBUF_FRAME_END 0x00008000 +#define RXBUF_TYPEID_MATCH 0x00400000 +#define RXBUF_ADDR4_MATCH 0x00800000 +#define RXBUF_ADDR3_MATCH 0x01000000 +#define RXBUF_ADDR2_MATCH 0x02000000 +#define RXBUF_ADDR1_MATCH 0x04000000 +#define RXBUF_BROADCAST 0x80000000 -#define TXBUF_FRMLEN_MASK 0x000007ff -#define TXBUF_FRAME_END 0x00008000 -#define TXBUF_NOCRC 0x00010000 -#define TXBUF_EXHAUSTED 0x08000000 -#define TXBUF_UNDERRUN 0x10000000 -#define TXBUF_MAXRETRY 0x20000000 -#define TXBUF_WRAP 0x40000000 -#define TXBUF_USED 0x80000000 +#define TXBUF_FRMLEN_MASK 0x000007ff +#define TXBUF_FRAME_END 0x00008000 +#define TXBUF_NOCRC 0x00010000 +#define TXBUF_EXHAUSTED 0x08000000 +#define TXBUF_UNDERRUN 0x10000000 +#define TXBUF_MAXRETRY 0x20000000 +#define TXBUF_WRAP 0x40000000 +#define TXBUF_USED 0x80000000 /* Duplex, half or full. */ -#define DUPLEX_HALF 0x00 -#define DUPLEX_FULL 0x01 +#define DUPLEX_HALF 0x00 +#define DUPLEX_FULL 0x01 #define MAX_ADDR_LEN 6 struct rt_macb_eth { - /* inherit from ethernet device */ - struct eth_device parent; + /* inherit from ethernet device */ + struct eth_device parent; - unsigned int regs; + unsigned int regs; - unsigned int rx_tail; - unsigned int tx_head; - unsigned int tx_tail; - unsigned int rx_pending; - unsigned int tx_pending; + unsigned int rx_tail; + unsigned int tx_head; + unsigned int tx_tail; + unsigned int rx_pending; + unsigned int tx_pending; - void *rx_buffer; - void *tx_buffer; - struct macb_dma_desc *rx_ring; - struct macb_dma_desc *tx_ring; + void *rx_buffer; + void *tx_buffer; + struct macb_dma_desc *rx_ring; + struct macb_dma_desc *tx_ring; - unsigned long rx_buffer_dma; - unsigned long tx_buffer_dma; - unsigned long rx_ring_dma; - unsigned long tx_ring_dma; + unsigned long rx_buffer_dma; + unsigned long tx_buffer_dma; + unsigned long rx_ring_dma; + unsigned long tx_ring_dma; - unsigned int tx_stop; + unsigned int tx_stop; - /* interface address info. */ - rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ - unsigned short phy_addr; + /* interface address info. */ + rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ + unsigned short phy_addr; - struct rt_semaphore mdio_bus_lock; - struct rt_semaphore tx_lock; - struct rt_semaphore rx_lock; - struct rt_semaphore tx_ack; - rt_uint32_t speed; - rt_uint32_t duplex; - rt_uint32_t link; - struct rt_timer timer; + struct rt_semaphore mdio_bus_lock; + struct rt_semaphore tx_lock; + struct rt_semaphore rx_lock; + struct rt_semaphore tx_ack; + rt_uint32_t speed; + rt_uint32_t duplex; + rt_uint32_t link; + struct rt_timer timer; }; static struct rt_macb_eth macb_device; @@ -179,253 +165,253 @@ static void udelay(rt_uint32_t us) static void rt_macb_isr(int irq, void *param) { - struct rt_macb_eth *macb = (struct rt_macb_eth *)param; - rt_device_t dev = &(macb->parent.parent); - rt_uint32_t status, rsr, tsr; + struct rt_macb_eth *macb = (struct rt_macb_eth *)param; + rt_device_t dev = &(macb->parent.parent); + rt_uint32_t status, rsr, tsr; - status = macb_readl(macb, ISR); + status = macb_readl(macb, ISR); - while (status) { + while (status) { - if (status & MACB_RX_INT_FLAGS) - { - rsr = macb_readl(macb, RSR); - macb_writel(macb, RSR, rsr); - /* a frame has been received */ - eth_device_ready(&(macb_device.parent)); - - } + if (status & MACB_RX_INT_FLAGS) + { + rsr = macb_readl(macb, RSR); + macb_writel(macb, RSR, rsr); + /* a frame has been received */ + eth_device_ready(&(macb_device.parent)); - if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND) | - MACB_BIT(ISR_RLE))) - { - macb_tx(macb); - } + } - /* - * Link change detection isn't possible with RMII, so we'll - * add that if/when we get our hands on a full-blown MII PHY. - */ + if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND) | + MACB_BIT(ISR_RLE))) + { + macb_tx(macb); + } - if (status & MACB_BIT(HRESP)) - { - /* - * TODO: Reset the hardware, and maybe move the printk - * to a lower-priority context as well (work queue?) - */ - rt_kprintf("%s: DMA bus error: HRESP not OK\n", - dev->parent.name); - } + /* + * Link change detection isn't possible with RMII, so we'll + * add that if/when we get our hands on a full-blown MII PHY. + */ - status = macb_readl(macb, ISR); - } + if (status & MACB_BIT(HRESP)) + { + /* + * TODO: Reset the hardware, and maybe move the printk + * to a lower-priority context as well (work queue?) + */ + rt_kprintf("%s: DMA bus error: HRESP not OK\n", + dev->parent.name); + } + + status = macb_readl(macb, ISR); + } } static int macb_mdio_write(struct rt_macb_eth *macb, rt_uint8_t reg, rt_uint16_t value) { - unsigned long netctl; - unsigned long netstat; - unsigned long frame; + unsigned long netctl; + unsigned long netstat; + unsigned long frame; - rt_sem_take(&macb->mdio_bus_lock, RT_WAITING_FOREVER); - netctl = macb_readl(macb, NCR); - netctl |= MACB_BIT(MPE); - macb_writel(macb, NCR, netctl); + rt_sem_take(&macb->mdio_bus_lock, RT_WAITING_FOREVER); + netctl = macb_readl(macb, NCR); + netctl |= MACB_BIT(MPE); + macb_writel(macb, NCR, netctl); - frame = (MACB_BF(SOF, 1) - | MACB_BF(RW, 1) - | MACB_BF(PHYA, macb->phy_addr) - | MACB_BF(REGA, reg) - | MACB_BF(CODE, 2) - | MACB_BF(DATA, value)); - macb_writel(macb, MAN, frame); + frame = (MACB_BF(SOF, 1) + | MACB_BF(RW, 1) + | MACB_BF(PHYA, macb->phy_addr) + | MACB_BF(REGA, reg) + | MACB_BF(CODE, 2) + | MACB_BF(DATA, value)); + macb_writel(macb, MAN, frame); - do { - netstat = macb_readl(macb, NSR); - } while (!(netstat & MACB_BIT(IDLE))); + do { + netstat = macb_readl(macb, NSR); + } while (!(netstat & MACB_BIT(IDLE))); - netctl = macb_readl(macb, NCR); - netctl &= ~MACB_BIT(MPE); - macb_writel(macb, NCR, netctl); - rt_sem_release(&macb->mdio_bus_lock); + netctl = macb_readl(macb, NCR); + netctl &= ~MACB_BIT(MPE); + macb_writel(macb, NCR, netctl); + rt_sem_release(&macb->mdio_bus_lock); } static int macb_mdio_read(struct rt_macb_eth *macb, rt_uint8_t reg) { - unsigned long netctl; - unsigned long netstat; - unsigned long frame; + unsigned long netctl; + unsigned long netstat; + unsigned long frame; - rt_sem_take(&macb->mdio_bus_lock, RT_WAITING_FOREVER); - netctl = macb_readl(macb, NCR); - netctl |= MACB_BIT(MPE); - macb_writel(macb, NCR, netctl); + rt_sem_take(&macb->mdio_bus_lock, RT_WAITING_FOREVER); + netctl = macb_readl(macb, NCR); + netctl |= MACB_BIT(MPE); + macb_writel(macb, NCR, netctl); - frame = (MACB_BF(SOF, 1) - | MACB_BF(RW, 2) - | MACB_BF(PHYA, macb->phy_addr) - | MACB_BF(REGA, reg) - | MACB_BF(CODE, 2)); - macb_writel(macb, MAN, frame); + frame = (MACB_BF(SOF, 1) + | MACB_BF(RW, 2) + | MACB_BF(PHYA, macb->phy_addr) + | MACB_BF(REGA, reg) + | MACB_BF(CODE, 2)); + macb_writel(macb, MAN, frame); - do { - netstat = macb_readl(macb, NSR); - } while (!(netstat & MACB_BIT(IDLE))); + do { + netstat = macb_readl(macb, NSR); + } while (!(netstat & MACB_BIT(IDLE))); - frame = macb_readl(macb, MAN); + frame = macb_readl(macb, MAN); - netctl = macb_readl(macb, NCR); - netctl &= ~MACB_BIT(MPE); - macb_writel(macb, NCR, netctl); - rt_sem_release(&macb->mdio_bus_lock); + netctl = macb_readl(macb, NCR); + netctl &= ~MACB_BIT(MPE); + macb_writel(macb, NCR, netctl); + rt_sem_release(&macb->mdio_bus_lock); - return MACB_BFEXT(DATA, frame); + return MACB_BFEXT(DATA, frame); } static void macb_phy_reset(rt_device_t dev) { - int i; - rt_uint16_t status, adv; - struct rt_macb_eth *macb = dev->user_data;; + int i; + rt_uint16_t status, adv; + struct rt_macb_eth *macb = dev->user_data;; - adv = ADVERTISE_CSMA | ADVERTISE_ALL; - macb_mdio_write(macb, MII_ADVERTISE, adv); - rt_kprintf("%s: Starting autonegotiation...\n", dev->parent.name); - macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE - | BMCR_ANRESTART)); + adv = ADVERTISE_CSMA | ADVERTISE_ALL; + macb_mdio_write(macb, MII_ADVERTISE, adv); + rt_kprintf("%s: Starting autonegotiation...\n", dev->parent.name); + macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE + | BMCR_ANRESTART)); - for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) - { - status = macb_mdio_read(macb, MII_BMSR); - if (status & BMSR_ANEGCOMPLETE) - break; - udelay(100); - } + for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) + { + status = macb_mdio_read(macb, MII_BMSR); + if (status & BMSR_ANEGCOMPLETE) + break; + udelay(100); + } - if (status & BMSR_ANEGCOMPLETE) - rt_kprintf("%s: Autonegotiation complete\n", dev->parent.name); - else - rt_kprintf("%s: Autonegotiation timed out (status=0x%04x)\n", - dev->parent.name, status); + if (status & BMSR_ANEGCOMPLETE) + rt_kprintf("%s: Autonegotiation complete\n", dev->parent.name); + else + rt_kprintf("%s: Autonegotiation timed out (status=0x%04x)\n", + dev->parent.name, status); } static int macb_phy_init(rt_device_t dev) { - struct rt_macb_eth *macb = dev->user_data; - rt_uint32_t ncfgr; - rt_uint16_t phy_id, status, adv, lpa; - int media, speed, duplex; - int i; + struct rt_macb_eth *macb = dev->user_data; + rt_uint32_t ncfgr; + rt_uint16_t phy_id, status, adv, lpa; + int media, speed, duplex; + int i; - /* Check if the PHY is up to snuff... */ - phy_id = macb_mdio_read(macb, MII_PHYSID1); - if (phy_id == 0xffff) - { - rt_kprintf("%s: No PHY present\n", dev->parent.name); - return 0; - } + /* Check if the PHY is up to snuff... */ + phy_id = macb_mdio_read(macb, MII_PHYSID1); + if (phy_id == 0xffff) + { + rt_kprintf("%s: No PHY present\n", dev->parent.name); + return 0; + } - status = macb_mdio_read(macb, MII_BMSR); - if (!(status & BMSR_LSTATUS)) - { - /* Try to re-negotiate if we don't have link already. */ - macb_phy_reset(dev); + status = macb_mdio_read(macb, MII_BMSR); + if (!(status & BMSR_LSTATUS)) + { + /* Try to re-negotiate if we don't have link already. */ + macb_phy_reset(dev); - for (i = 0; i < MACB_LINK_TIMEOUT / 100; i++) - { - status = macb_mdio_read(macb, MII_BMSR); - if (status & BMSR_LSTATUS) - break; - udelay(100); - } - } + for (i = 0; i < MACB_LINK_TIMEOUT / 100; i++) + { + status = macb_mdio_read(macb, MII_BMSR); + if (status & BMSR_LSTATUS) + break; + udelay(100); + } + } - if (!(status & BMSR_LSTATUS)) - { - rt_kprintf("%s: link down (status: 0x%04x)\n", - dev->parent.name, status); - return 0; - } - else - { - adv = macb_mdio_read(macb, MII_ADVERTISE); - lpa = macb_mdio_read(macb, MII_LPA); - media = mii_nway_result(lpa & adv); - speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) - ? 1 : 0); - duplex = (media & ADVERTISE_FULL) ? 1 : 0; - rt_kprintf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n", - dev->parent.name, - speed ? "100" : "10", - duplex ? "full" : "half", - lpa); + if (!(status & BMSR_LSTATUS)) + { + rt_kprintf("%s: link down (status: 0x%04x)\n", + dev->parent.name, status); + return 0; + } + else + { + adv = macb_mdio_read(macb, MII_ADVERTISE); + lpa = macb_mdio_read(macb, MII_LPA); + media = mii_nway_result(lpa & adv); + speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) + ? 1 : 0); + duplex = (media & ADVERTISE_FULL) ? 1 : 0; + rt_kprintf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n", + dev->parent.name, + speed ? "100" : "10", + duplex ? "full" : "half", + lpa); - ncfgr = macb_readl(macb, NCFGR); - ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); - if (speed) - ncfgr |= MACB_BIT(SPD); - if (duplex) - ncfgr |= MACB_BIT(FD); - macb_writel(macb, NCFGR, ncfgr); - return 1; - } + ncfgr = macb_readl(macb, NCFGR); + ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); + if (speed) + ncfgr |= MACB_BIT(SPD); + if (duplex) + ncfgr |= MACB_BIT(FD); + macb_writel(macb, NCFGR, ncfgr); + return 1; + } } void macb_update_link(void *param) { - struct rt_macb_eth *macb = (struct rt_macb_eth *)param; - rt_device_t dev = &macb->parent.parent; - int status, status_change = 0; - rt_uint32_t link; - rt_uint32_t media; - rt_uint16_t adv, lpa; + struct rt_macb_eth *macb = (struct rt_macb_eth *)param; + rt_device_t dev = &macb->parent.parent; + int status, status_change = 0; + rt_uint32_t link; + rt_uint32_t media; + rt_uint16_t adv, lpa; - /* Do a fake read */ - status = macb_mdio_read(macb, MII_BMSR); - if (status < 0) - return; + /* Do a fake read */ + status = macb_mdio_read(macb, MII_BMSR); + if (status < 0) + return; - /* Read link and autonegotiation status */ - status = macb_mdio_read(macb, MII_BMSR); - if (status < 0) - return; - - if ((status & BMSR_LSTATUS) == 0) - link = 0; - else - link = 1; + /* Read link and autonegotiation status */ + status = macb_mdio_read(macb, MII_BMSR); + if (status < 0) + return; - if (link != macb->link) - { - macb->link = link; - status_change = 1; - } + if ((status & BMSR_LSTATUS) == 0) + link = 0; + else + link = 1; - if (status_change) - { - if (macb->link) - { - adv = macb_mdio_read(macb, MII_ADVERTISE); - lpa = macb_mdio_read(macb, MII_LPA); - media = mii_nway_result(lpa & adv); - macb->speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) - ? 100 : 10); - macb->duplex = (media & ADVERTISE_FULL) ? 1 : 0; - rt_kprintf("%s: link up (%dMbps/%s-duplex)\n", - dev->parent.name, macb->speed, - DUPLEX_FULL == macb->duplex ? "Full":"Half"); - eth_device_linkchange(&macb->parent, RT_TRUE); - } - else - { - rt_kprintf("%s: link down\n", dev->parent.name); - eth_device_linkchange(&macb->parent, RT_FALSE); - } + if (link != macb->link) + { + macb->link = link; + status_change = 1; + } - } + if (status_change) + { + if (macb->link) + { + adv = macb_mdio_read(macb, MII_ADVERTISE); + lpa = macb_mdio_read(macb, MII_LPA); + media = mii_nway_result(lpa & adv); + macb->speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) + ? 100 : 10); + macb->duplex = (media & ADVERTISE_FULL) ? 1 : 0; + rt_kprintf("%s: link up (%dMbps/%s-duplex)\n", + dev->parent.name, macb->speed, + DUPLEX_FULL == macb->duplex ? "Full":"Half"); + eth_device_linkchange(&macb->parent, RT_TRUE); + } + else + { + rt_kprintf("%s: link down\n", dev->parent.name); + eth_device_linkchange(&macb->parent, RT_FALSE); + } + + } } @@ -434,190 +420,190 @@ void macb_update_link(void *param) static rt_err_t rt_macb_init(rt_device_t dev) { - struct rt_macb_eth *macb = dev->user_data; - unsigned long paddr; - rt_uint32_t hwaddr_bottom; - rt_uint16_t hwaddr_top; - int i; + struct rt_macb_eth *macb = dev->user_data; + unsigned long paddr; + rt_uint32_t hwaddr_bottom; + rt_uint16_t hwaddr_top; + int i; - /* - * macb_halt should have been called at some point before now, - * so we'll assume the controller is idle. - */ + /* + * macb_halt should have been called at some point before now, + * so we'll assume the controller is idle. + */ - /* initialize DMA descriptors */ - paddr = macb->rx_buffer_dma; - for (i = 0; i < MACB_RX_RING_SIZE; i++) - { - if (i == (MACB_RX_RING_SIZE - 1)) - paddr |= RXADDR_WRAP; - macb->rx_ring[i].addr = paddr; - macb->rx_ring[i].ctrl = 0; - paddr += 128; - } - paddr = macb->tx_buffer_dma; - for (i = 0; i < MACB_TX_RING_SIZE; i++) - { - macb->tx_ring[i].addr = paddr; - if (i == (MACB_TX_RING_SIZE - 1)) - macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP; - else - macb->tx_ring[i].ctrl = TXBUF_USED; - paddr += 1536; - } - macb->rx_tail = macb->tx_head = macb->tx_tail = 0; + /* initialize DMA descriptors */ + paddr = macb->rx_buffer_dma; + for (i = 0; i < MACB_RX_RING_SIZE; i++) + { + if (i == (MACB_RX_RING_SIZE - 1)) + paddr |= RXADDR_WRAP; + macb->rx_ring[i].addr = paddr; + macb->rx_ring[i].ctrl = 0; + paddr += 128; + } + paddr = macb->tx_buffer_dma; + for (i = 0; i < MACB_TX_RING_SIZE; i++) + { + macb->tx_ring[i].addr = paddr; + if (i == (MACB_TX_RING_SIZE - 1)) + macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP; + else + macb->tx_ring[i].ctrl = TXBUF_USED; + paddr += 1536; + } + macb->rx_tail = macb->tx_head = macb->tx_tail = 0; - BD_CACHE_WRITEBACK_INVALIDATE(macb->rx_ring, MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); - BD_CACHE_WRITEBACK_INVALIDATE(macb->tx_ring, MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc)); - macb_writel(macb, RBQP, macb->rx_ring_dma); - macb_writel(macb, TBQP, macb->tx_ring_dma); - - /* set hardware address */ - hwaddr_bottom = (*((rt_uint32_t *)macb->dev_addr)); - macb_writel(macb, SA1B, hwaddr_bottom); - hwaddr_top = (*((rt_uint16_t *)(macb->dev_addr + 4))); - macb_writel(macb, SA1T, hwaddr_top); + BD_CACHE_WRITEBACK_INVALIDATE(macb->rx_ring, MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); + BD_CACHE_WRITEBACK_INVALIDATE(macb->tx_ring, MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc)); + macb_writel(macb, RBQP, macb->rx_ring_dma); + macb_writel(macb, TBQP, macb->tx_ring_dma); - - /* choose RMII or MII mode. This depends on the board */ + /* set hardware address */ + hwaddr_bottom = (*((rt_uint32_t *)macb->dev_addr)); + macb_writel(macb, SA1B, hwaddr_bottom); + hwaddr_top = (*((rt_uint16_t *)(macb->dev_addr + 4))); + macb_writel(macb, SA1T, hwaddr_top); + + + /* choose RMII or MII mode. This depends on the board */ #ifdef CONFIG_RMII - macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN)); + macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN)); #else - macb_writel(macb, USRIO, MACB_BIT(CLKEN)); + macb_writel(macb, USRIO, MACB_BIT(CLKEN)); #endif /* CONFIG_RMII */ - if (!macb_phy_init(dev)) - return -RT_ERROR; + if (!macb_phy_init(dev)) + return -RT_ERROR; - /* Enable TX and RX */ - macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(MPE)); - - /* Enable interrupts */ - macb_writel(macb, IER, (MACB_BIT(RCOMP) - | MACB_BIT(RXUBR) - | MACB_BIT(ISR_TUND) - | MACB_BIT(ISR_RLE) - | MACB_BIT(TXERR) - | MACB_BIT(TCOMP) - | MACB_BIT(ISR_ROVR) - | MACB_BIT(HRESP))); - - /* instal interrupt */ - rt_hw_interrupt_install(AT91SAM9260_ID_EMAC, rt_macb_isr, - (void *)macb, "emac"); - rt_hw_interrupt_umask(AT91SAM9260_ID_EMAC); + /* Enable TX and RX */ + macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(MPE)); - rt_timer_init(&macb->timer, "link_timer", - macb_update_link, - (void *)macb, - RT_TICK_PER_SECOND, - RT_TIMER_FLAG_PERIODIC); + /* Enable interrupts */ + macb_writel(macb, IER, (MACB_BIT(RCOMP) + | MACB_BIT(RXUBR) + | MACB_BIT(ISR_TUND) + | MACB_BIT(ISR_RLE) + | MACB_BIT(TXERR) + | MACB_BIT(TCOMP) + | MACB_BIT(ISR_ROVR) + | MACB_BIT(HRESP))); - rt_timer_start(&macb->timer); - - return RT_EOK; + /* instal interrupt */ + rt_hw_interrupt_install(AT91SAM9260_ID_EMAC, rt_macb_isr, + (void *)macb, "emac"); + rt_hw_interrupt_umask(AT91SAM9260_ID_EMAC); + + rt_timer_init(&macb->timer, "link_timer", + macb_update_link, + (void *)macb, + RT_TICK_PER_SECOND, + RT_TIMER_FLAG_PERIODIC); + + rt_timer_start(&macb->timer); + + return RT_EOK; } static rt_err_t rt_macb_open(rt_device_t dev, rt_uint16_t oflag) { - return RT_EOK; + return RT_EOK; } static rt_err_t rt_macb_close(rt_device_t dev) { - return RT_EOK; + return RT_EOK; } static rt_size_t rt_macb_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_size_t rt_macb_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_err_t rt_macb_control(rt_device_t dev, int cmd, void *args) { - switch(cmd) - { - case NIOCTL_GADDR: - /* get mac address */ - if(args) rt_memcpy(args, macb_device.dev_addr, 6); - else return -RT_ERROR; - break; + switch(cmd) + { + case NIOCTL_GADDR: + /* get mac address */ + if(args) rt_memcpy(args, macb_device.dev_addr, 6); + else return -RT_ERROR; + break; - default : - break; - } + default : + break; + } - return RT_EOK; + return RT_EOK; } static void macb_tx(struct rt_macb_eth *macb) { - unsigned int tail; - unsigned int head; - rt_uint32_t status; + unsigned int tail; + unsigned int head; + rt_uint32_t status; - status = macb_readl(macb, TSR); - macb_writel(macb, TSR, status); + status = macb_readl(macb, TSR); + macb_writel(macb, TSR, status); - /*rt_kprintf("macb_tx status = %02lx\n", - (unsigned long)status);*/ + /*rt_kprintf("macb_tx status = %02lx\n", + (unsigned long)status);*/ - if (status & (MACB_BIT(UND) | MACB_BIT(TSR_RLE))) - { - int i; - rt_kprintf("%s: TX %s, resetting buffers\n", - macb->parent.parent.parent.name, status & MACB_BIT(UND) ? - "underrun" : "retry limit exceeded"); + if (status & (MACB_BIT(UND) | MACB_BIT(TSR_RLE))) + { + int i; + rt_kprintf("%s: TX %s, resetting buffers\n", + macb->parent.parent.parent.name, status & MACB_BIT(UND) ? + "underrun" : "retry limit exceeded"); - /* Transfer ongoing, disable transmitter, to avoid confusion */ - if (status & MACB_BIT(TGO)) - macb_writel(macb, NCR, macb_readl(macb, NCR) & ~MACB_BIT(TE)); + /* Transfer ongoing, disable transmitter, to avoid confusion */ + if (status & MACB_BIT(TGO)) + macb_writel(macb, NCR, macb_readl(macb, NCR) & ~MACB_BIT(TE)); - head = macb->tx_head; + head = macb->tx_head; - /*Mark all the buffer as used to avoid sending a lost buffer*/ - for (i = 0; i < MACB_TX_RING_SIZE; i++) - macb->tx_ring[i].ctrl = MACB_BIT(TX_USED); + /*Mark all the buffer as used to avoid sending a lost buffer*/ + for (i = 0; i < MACB_TX_RING_SIZE; i++) + macb->tx_ring[i].ctrl = MACB_BIT(TX_USED); - /* free transmit buffer in upper layer*/ + /* free transmit buffer in upper layer*/ - macb->tx_head = macb->tx_tail = 0; + macb->tx_head = macb->tx_tail = 0; - /* Enable the transmitter again */ - if (status & MACB_BIT(TGO)) - macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TE)); - } + /* Enable the transmitter again */ + if (status & MACB_BIT(TGO)) + macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TE)); + } - if (!(status & MACB_BIT(COMP))) - /* - * This may happen when a buffer becomes complete - * between reading the ISR and scanning the - * descriptors. Nothing to worry about. - */ - return; + if (!(status & MACB_BIT(COMP))) + /* + * This may happen when a buffer becomes complete + * between reading the ISR and scanning the + * descriptors. Nothing to worry about. + */ + return; - head = macb->tx_head; - for (tail = macb->tx_tail; tail != head; tail = NEXT_TX(tail)) - { - rt_uint32_t bufstat; + head = macb->tx_head; + for (tail = macb->tx_tail; tail != head; tail = NEXT_TX(tail)) + { + rt_uint32_t bufstat; - bufstat = macb->tx_ring[tail].ctrl; + bufstat = macb->tx_ring[tail].ctrl; - if (!(bufstat & MACB_BIT(TX_USED))) - break; - } + if (!(bufstat & MACB_BIT(TX_USED))) + break; + } - macb->tx_tail = tail; - if ((macb->tx_stop == 1) && - TX_BUFFS_AVAIL(macb) > MACB_TX_WAKEUP_THRESH) - rt_sem_release(&macb->tx_ack); + macb->tx_tail = tail; + if ((macb->tx_stop == 1) && + TX_BUFFS_AVAIL(macb) > MACB_TX_WAKEUP_THRESH) + rt_sem_release(&macb->tx_ack); } @@ -625,286 +611,286 @@ static void macb_tx(struct rt_macb_eth *macb) /* transmit packet. */ rt_err_t rt_macb_tx( rt_device_t dev, struct pbuf* p) { - unsigned long ctrl; - struct pbuf* q; - rt_uint8_t* bufptr; - rt_uint32_t mapping; - struct rt_macb_eth *macb = dev->user_data; - unsigned int tx_head = macb->tx_head; + unsigned long ctrl; + struct pbuf* q; + rt_uint8_t* bufptr; + rt_uint32_t mapping; + struct rt_macb_eth *macb = dev->user_data; + unsigned int tx_head = macb->tx_head; - rt_sem_take(&macb->tx_lock, RT_WAITING_FOREVER); - if (TX_BUFFS_AVAIL(macb) < 1) - { - rt_sem_release(&macb->tx_lock); - rt_kprintf("Tx Ring full!\n"); - rt_kprintf("tx_head = %u, tx_tail = %u\n", - macb->tx_head, macb->tx_tail); - return -RT_ERROR; - } + rt_sem_take(&macb->tx_lock, RT_WAITING_FOREVER); + if (TX_BUFFS_AVAIL(macb) < 1) + { + rt_sem_release(&macb->tx_lock); + rt_kprintf("Tx Ring full!\n"); + rt_kprintf("tx_head = %u, tx_tail = %u\n", + macb->tx_head, macb->tx_tail); + return -RT_ERROR; + } - macb->tx_stop = 0; + macb->tx_stop = 0; - ctrl = p->tot_len & TXBUF_FRMLEN_MASK; - ctrl |= TXBUF_FRAME_END; - if (tx_head == (MACB_TX_RING_SIZE - 1)) - { - ctrl |= TXBUF_WRAP; - } + ctrl = p->tot_len & TXBUF_FRMLEN_MASK; + ctrl |= TXBUF_FRAME_END; + if (tx_head == (MACB_TX_RING_SIZE - 1)) + { + ctrl |= TXBUF_WRAP; + } #if defined(MACB_TX_SRAM) - bufptr = macb->tx_buffer + tx_head * 1536; + bufptr = macb->tx_buffer + tx_head * 1536; #else - mapping = (unsigned long)macb->tx_buffer + tx_head * 1536; - bufptr = (rt_uint8_t *)mapping; + mapping = (unsigned long)macb->tx_buffer + tx_head * 1536; + bufptr = (rt_uint8_t *)mapping; #endif - for (q = p; q != NULL; q = q->next) - { - memcpy(bufptr, q->payload, q->len); - bufptr += q->len; - } + for (q = p; q != NULL; q = q->next) + { + memcpy(bufptr, q->payload, q->len); + bufptr += q->len; + } #if !defined(MACB_TX_SRAM) - EMAC_CACHE_WRITEBACK(mapping, p->tot_len); + EMAC_CACHE_WRITEBACK(mapping, p->tot_len); #endif - macb->tx_ring[tx_head].ctrl = ctrl; - BD_CACHE_WRITEBACK_INVALIDATE(&macb->tx_ring[tx_head], sizeof(struct macb_dma_desc)); - tx_head = NEXT_TX(tx_head); - macb->tx_head = tx_head; - macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TSTART)); - macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TSTART)); + macb->tx_ring[tx_head].ctrl = ctrl; + BD_CACHE_WRITEBACK_INVALIDATE(&macb->tx_ring[tx_head], sizeof(struct macb_dma_desc)); + tx_head = NEXT_TX(tx_head); + macb->tx_head = tx_head; + macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TSTART)); + macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TSTART)); - if (TX_BUFFS_AVAIL(macb) < 1) - { - macb->tx_stop = 1; - rt_sem_take(&macb->tx_ack, RT_WAITING_FOREVER); - } - rt_sem_release(&macb->tx_lock); + if (TX_BUFFS_AVAIL(macb) < 1) + { + macb->tx_stop = 1; + rt_sem_take(&macb->tx_ack, RT_WAITING_FOREVER); + } + rt_sem_release(&macb->tx_lock); - return RT_EOK; + return RT_EOK; } static void reclaim_rx_buffers(struct rt_macb_eth *macb, - unsigned int new_tail) + unsigned int new_tail) { - unsigned int i; + unsigned int i; - i = macb->rx_tail; - while (i > new_tail) - { - macb->rx_ring[i].addr &= ~RXADDR_USED; - i++; - if (i > MACB_RX_RING_SIZE) - i = 0; - } + i = macb->rx_tail; + while (i > new_tail) + { + macb->rx_ring[i].addr &= ~RXADDR_USED; + i++; + if (i > MACB_RX_RING_SIZE) + i = 0; + } - while (i < new_tail) - { - macb->rx_ring[i].addr &= ~RXADDR_USED; - i++; - } + while (i < new_tail) + { + macb->rx_ring[i].addr &= ~RXADDR_USED; + i++; + } - macb->rx_tail = new_tail; + macb->rx_tail = new_tail; } /* reception packet. */ struct pbuf *rt_macb_rx(rt_device_t dev) { - struct rt_macb_eth *macb = dev->user_data; - struct pbuf* p = RT_NULL; - rt_uint32_t len; - unsigned int rx_tail = macb->rx_tail; - void *buffer; - int wrapped = 0; - rt_uint32_t status; + struct rt_macb_eth *macb = dev->user_data; + struct pbuf* p = RT_NULL; + rt_uint32_t len; + unsigned int rx_tail = macb->rx_tail; + void *buffer; + int wrapped = 0; + rt_uint32_t status; - rt_sem_take(&macb->rx_lock, RT_WAITING_FOREVER); - for (;;) - { - if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED)) - break; + rt_sem_take(&macb->rx_lock, RT_WAITING_FOREVER); + for (;;) + { + if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED)) + break; - status = macb->rx_ring[rx_tail].ctrl; - if (status & RXBUF_FRAME_START) - { - if (rx_tail != macb->rx_tail) - reclaim_rx_buffers(macb, rx_tail); - wrapped = 0; - } + status = macb->rx_ring[rx_tail].ctrl; + if (status & RXBUF_FRAME_START) + { + if (rx_tail != macb->rx_tail) + reclaim_rx_buffers(macb, rx_tail); + wrapped = 0; + } - if (status & RXBUF_FRAME_END) - { - buffer = (void *)((unsigned int)macb->rx_buffer + 128 * macb->rx_tail); - len = status & RXBUF_FRMLEN_MASK; - p = pbuf_alloc(PBUF_LINK, len, PBUF_RAM); - if (!p) - { - rt_kprintf("alloc pbuf failed\n"); - break; - } - if (wrapped) - { - unsigned int headlen, taillen; + if (status & RXBUF_FRAME_END) + { + buffer = (void *)((unsigned int)macb->rx_buffer + 128 * macb->rx_tail); + len = status & RXBUF_FRMLEN_MASK; + p = pbuf_alloc(PBUF_LINK, len, PBUF_RAM); + if (!p) + { + rt_kprintf("alloc pbuf failed\n"); + break; + } + if (wrapped) + { + unsigned int headlen, taillen; - headlen = 128 * (MACB_RX_RING_SIZE - - macb->rx_tail); - taillen = len - headlen; - EMAC_CACHE_INVALIDATE(buffer, headlen); - EMAC_CACHE_INVALIDATE(macb->rx_buffer, taillen); - memcpy((void *)p->payload, buffer, headlen); - memcpy((void *)((unsigned int)p->payload + headlen), - macb->rx_buffer, taillen); - } - else - { - EMAC_CACHE_INVALIDATE(buffer, len); - memcpy((void *)p->payload, buffer, p->len); - } - - if (++rx_tail >= MACB_RX_RING_SIZE) - rx_tail = 0; - reclaim_rx_buffers(macb, rx_tail); - break; - } - else - { - if (++rx_tail >= MACB_RX_RING_SIZE) - { - wrapped = 1; - rx_tail = 0; - } - } - } + headlen = 128 * (MACB_RX_RING_SIZE + - macb->rx_tail); + taillen = len - headlen; + EMAC_CACHE_INVALIDATE(buffer, headlen); + EMAC_CACHE_INVALIDATE(macb->rx_buffer, taillen); + memcpy((void *)p->payload, buffer, headlen); + memcpy((void *)((unsigned int)p->payload + headlen), + macb->rx_buffer, taillen); + } + else + { + EMAC_CACHE_INVALIDATE(buffer, len); + memcpy((void *)p->payload, buffer, p->len); + } - rt_sem_release(&macb->rx_lock); + if (++rx_tail >= MACB_RX_RING_SIZE) + rx_tail = 0; + reclaim_rx_buffers(macb, rx_tail); + break; + } + else + { + if (++rx_tail >= MACB_RX_RING_SIZE) + { + wrapped = 1; + rx_tail = 0; + } + } + } - return p; + rt_sem_release(&macb->rx_lock); + + return p; } void macb_gpio_init() { - /* Pins used for MII and RMII */ - at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 19)|(1 << 17)|(1 << 14)|(1 << 15)|(1 << 18)|(1 << 16)|(1 << 12)|(1 << 13)|(1 << 21)|(1 << 20)); - at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 19)|(1 << 17)|(1 << 14)|(1 << 15)|(1 << 18)|(1 << 16)|(1 << 12)|(1 << 13)|(1 << 21)|(1 << 20)); + /* Pins used for MII and RMII */ + at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 19)|(1 << 17)|(1 << 14)|(1 << 15)|(1 << 18)|(1 << 16)|(1 << 12)|(1 << 13)|(1 << 21)|(1 << 20)); + at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 19)|(1 << 17)|(1 << 14)|(1 << 15)|(1 << 18)|(1 << 16)|(1 << 12)|(1 << 13)|(1 << 21)|(1 << 20)); #ifndef GONFIG_RMII - at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 22)|(1 << 23)|(1 << 24)|(1 << 25)|(1 << 26)|(1 << 27)|(1 << 28)|(1 << 29)); - at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 22)|(1 << 23)|(1 << 24)|(1 << 25)|(1 << 26)|(1 << 27)|(1 << 28)|(1 << 29)); + at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 22)|(1 << 23)|(1 << 24)|(1 << 25)|(1 << 26)|(1 << 27)|(1 << 28)|(1 << 29)); + at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 22)|(1 << 23)|(1 << 24)|(1 << 25)|(1 << 26)|(1 << 27)|(1 << 28)|(1 << 29)); #endif } rt_err_t macb_initialize() { - struct rt_macb_eth *macb = &macb_device; - unsigned long macb_hz; - rt_uint32_t ncfgr; - + struct rt_macb_eth *macb = &macb_device; + unsigned long macb_hz; + rt_uint32_t ncfgr; + #if defined(MACB_TX_SRAM) - macb->tx_ring_dma = AT91SAM9260_SRAM0_BASE; - macb->tx_ring = (struct macb_dma_desc *)AT91SAM9260_SRAM0_VIRT_BASE; - macb->tx_buffer = (char *) macb->tx_ring + TX_RING_BYTES; - macb->tx_buffer_dma = macb->tx_ring_dma + TX_RING_BYTES; + macb->tx_ring_dma = AT91SAM9260_SRAM0_BASE; + macb->tx_ring = (struct macb_dma_desc *)AT91SAM9260_SRAM0_VIRT_BASE; + macb->tx_buffer = (char *) macb->tx_ring + TX_RING_BYTES; + macb->tx_buffer_dma = macb->tx_ring_dma + TX_RING_BYTES; #else - macb->tx_ring = rt_malloc(MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); - if (macb->tx_ring == RT_NULL) - goto err1; - EMAC_CACHE_INVALIDATE(macb->tx_ring, MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc)); - macb->tx_ring_dma = emac_virt_to_phys((unsigned long)macb->tx_ring); - macb->tx_ring = (struct macb_dma_desc *)MMU_NOCACHE_ADDR((unsigned long)macb->tx_ring); - macb->tx_buffer = rt_malloc(MACB_TX_BUFFER_SIZE); - if (macb->tx_buffer == RT_NULL) - goto err2; - macb->tx_buffer_dma = emac_virt_to_phys((unsigned long)macb->tx_buffer); + macb->tx_ring = rt_malloc(MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); + if (macb->tx_ring == RT_NULL) + goto err1; + EMAC_CACHE_INVALIDATE(macb->tx_ring, MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc)); + macb->tx_ring_dma = emac_virt_to_phys((unsigned long)macb->tx_ring); + macb->tx_ring = (struct macb_dma_desc *)MMU_NOCACHE_ADDR((unsigned long)macb->tx_ring); + macb->tx_buffer = rt_malloc(MACB_TX_BUFFER_SIZE); + if (macb->tx_buffer == RT_NULL) + goto err2; + macb->tx_buffer_dma = emac_virt_to_phys((unsigned long)macb->tx_buffer); #endif - macb->rx_ring = rt_malloc(MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); - if (macb->rx_ring == RT_NULL) - goto err3; - EMAC_CACHE_INVALIDATE(macb->rx_ring, MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); - macb->rx_ring_dma = emac_virt_to_phys((unsigned long)macb->rx_ring); - macb->rx_ring = (struct macb_dma_desc *)MMU_NOCACHE_ADDR((unsigned long)macb->rx_ring); - macb->rx_buffer = rt_malloc(MACB_RX_BUFFER_SIZE); - if (macb->rx_buffer == RT_NULL) - goto err4; - macb->rx_buffer_dma = emac_virt_to_phys((unsigned long)macb->rx_buffer); + macb->rx_ring = rt_malloc(MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); + if (macb->rx_ring == RT_NULL) + goto err3; + EMAC_CACHE_INVALIDATE(macb->rx_ring, MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); + macb->rx_ring_dma = emac_virt_to_phys((unsigned long)macb->rx_ring); + macb->rx_ring = (struct macb_dma_desc *)MMU_NOCACHE_ADDR((unsigned long)macb->rx_ring); + macb->rx_buffer = rt_malloc(MACB_RX_BUFFER_SIZE); + if (macb->rx_buffer == RT_NULL) + goto err4; + macb->rx_buffer_dma = emac_virt_to_phys((unsigned long)macb->rx_buffer); - macb->tx_pending = DEF_TX_RING_PENDING; + macb->tx_pending = DEF_TX_RING_PENDING; - macb->regs = AT91SAM9260_BASE_EMAC; - macb->phy_addr = 0x00; - - /* - * Do some basic initialization so that we at least can talk - * to the PHY - */ - macb_hz = clk_get_rate(clk_get("mck")); - if (macb_hz < 20000000) - ncfgr = MACB_BF(CLK, MACB_CLK_DIV8); - else if (macb_hz < 40000000) - ncfgr = MACB_BF(CLK, MACB_CLK_DIV16); - else if (macb_hz < 80000000) - ncfgr = MACB_BF(CLK, MACB_CLK_DIV32); - else - ncfgr = MACB_BF(CLK, MACB_CLK_DIV64); + macb->regs = AT91SAM9260_BASE_EMAC; + macb->phy_addr = 0x00; - macb_writel(macb, NCFGR, ncfgr); + /* + * Do some basic initialization so that we at least can talk + * to the PHY + */ + macb_hz = clk_get_rate(clk_get("mck")); + if (macb_hz < 20000000) + ncfgr = MACB_BF(CLK, MACB_CLK_DIV8); + else if (macb_hz < 40000000) + ncfgr = MACB_BF(CLK, MACB_CLK_DIV16); + else if (macb_hz < 80000000) + ncfgr = MACB_BF(CLK, MACB_CLK_DIV32); + else + ncfgr = MACB_BF(CLK, MACB_CLK_DIV64); - macb->link = 0; + macb_writel(macb, NCFGR, ncfgr); - return RT_EOK; + macb->link = 0; + + return RT_EOK; err4: - rt_free(macb->rx_ring); - macb->rx_ring = RT_NULL; + rt_free(macb->rx_ring); + macb->rx_ring = RT_NULL; err3: #if !defined(MACB_TX_SRAM) - rt_free(macb->tx_buffer); - macb->tx_buffer = RT_NULL; + rt_free(macb->tx_buffer); + macb->tx_buffer = RT_NULL; err2: - rt_free(macb->tx_ring); - macb->tx_ring = RT_NULL; + rt_free(macb->tx_ring); + macb->tx_ring = RT_NULL; err1: #endif - return -RT_ENOMEM; + return -RT_ENOMEM; } int rt_hw_macb_init(void) { - rt_err_t ret; - at91_sys_write(AT91_PMC + AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC); //enable macb clock - macb_gpio_init(); - rt_memset(&macb_device, 0, sizeof(macb_device)); - ret = macb_initialize(); - if (ret != RT_EOK) - { - rt_kprintf("AT91 EMAC initialized failed\n"); - return -1; - } - rt_sem_init(&macb_device.tx_ack, "tx_ack", 0, RT_IPC_FLAG_FIFO); - rt_sem_init(&macb_device.tx_lock, "tx_lock", 1, RT_IPC_FLAG_FIFO); - rt_sem_init(&macb_device.rx_lock, "rx_lock", 1, RT_IPC_FLAG_FIFO); + rt_err_t ret; + at91_sys_write(AT91_PMC + AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC); //enable macb clock + macb_gpio_init(); + rt_memset(&macb_device, 0, sizeof(macb_device)); + ret = macb_initialize(); + if (ret != RT_EOK) + { + rt_kprintf("AT91 EMAC initialized failed\n"); + return -1; + } + rt_sem_init(&macb_device.tx_ack, "tx_ack", 0, RT_IPC_FLAG_FIFO); + rt_sem_init(&macb_device.tx_lock, "tx_lock", 1, RT_IPC_FLAG_FIFO); + rt_sem_init(&macb_device.rx_lock, "rx_lock", 1, RT_IPC_FLAG_FIFO); - macb_device.dev_addr[0] = 0x00; - macb_device.dev_addr[1] = 0x60; - macb_device.dev_addr[2] = 0x6E; - macb_device.dev_addr[3] = 0x11; - macb_device.dev_addr[4] = 0x22; - macb_device.dev_addr[5] = 0x33; - - macb_device.parent.parent.init = rt_macb_init; - macb_device.parent.parent.open = rt_macb_open; - macb_device.parent.parent.close = rt_macb_close; - macb_device.parent.parent.read = rt_macb_read; - macb_device.parent.parent.write = rt_macb_write; - macb_device.parent.parent.control = rt_macb_control; - macb_device.parent.parent.user_data = &macb_device; + macb_device.dev_addr[0] = 0x00; + macb_device.dev_addr[1] = 0x60; + macb_device.dev_addr[2] = 0x6E; + macb_device.dev_addr[3] = 0x11; + macb_device.dev_addr[4] = 0x22; + macb_device.dev_addr[5] = 0x33; - macb_device.parent.eth_rx = rt_macb_rx; - macb_device.parent.eth_tx = rt_macb_tx; + macb_device.parent.parent.init = rt_macb_init; + macb_device.parent.parent.open = rt_macb_open; + macb_device.parent.parent.close = rt_macb_close; + macb_device.parent.parent.read = rt_macb_read; + macb_device.parent.parent.write = rt_macb_write; + macb_device.parent.parent.control = rt_macb_control; + macb_device.parent.parent.user_data = &macb_device; - rt_sem_init(&macb_device.mdio_bus_lock, "mdio_bus_lock", 1, RT_IPC_FLAG_FIFO); + macb_device.parent.eth_rx = rt_macb_rx; + macb_device.parent.eth_tx = rt_macb_tx; - eth_device_init(&(macb_device.parent), "e0"); + rt_sem_init(&macb_device.mdio_bus_lock, "mdio_bus_lock", 1, RT_IPC_FLAG_FIFO); - return 0; + eth_device_init(&(macb_device.parent), "e0"); + + return 0; } INIT_DEVICE_EXPORT(rt_hw_macb_init); diff --git a/bsp/at91sam9260/drivers/macb.h b/bsp/at91sam9260/drivers/macb.h index 9df2883534..ed2ad390b7 100644 --- a/bsp/at91sam9260/drivers/macb.h +++ b/bsp/at91sam9260/drivers/macb.h @@ -1,21 +1,7 @@ /* - * File : macb.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -26,319 +12,319 @@ #include /* MACB register offsets */ -#define MACB_NCR 0x0000 -#define MACB_NCFGR 0x0004 -#define MACB_NSR 0x0008 -#define MACB_TSR 0x0014 -#define MACB_RBQP 0x0018 -#define MACB_TBQP 0x001c -#define MACB_RSR 0x0020 -#define MACB_ISR 0x0024 -#define MACB_IER 0x0028 -#define MACB_IDR 0x002c -#define MACB_IMR 0x0030 -#define MACB_MAN 0x0034 -#define MACB_PTR 0x0038 -#define MACB_PFR 0x003c -#define MACB_FTO 0x0040 -#define MACB_SCF 0x0044 -#define MACB_MCF 0x0048 -#define MACB_FRO 0x004c -#define MACB_FCSE 0x0050 -#define MACB_ALE 0x0054 -#define MACB_DTF 0x0058 -#define MACB_LCOL 0x005c -#define MACB_EXCOL 0x0060 -#define MACB_TUND 0x0064 -#define MACB_CSE 0x0068 -#define MACB_RRE 0x006c -#define MACB_ROVR 0x0070 -#define MACB_RSE 0x0074 -#define MACB_ELE 0x0078 -#define MACB_RJA 0x007c -#define MACB_USF 0x0080 -#define MACB_STE 0x0084 -#define MACB_RLE 0x0088 -#define MACB_TPF 0x008c -#define MACB_HRB 0x0090 -#define MACB_HRT 0x0094 -#define MACB_SA1B 0x0098 -#define MACB_SA1T 0x009c -#define MACB_SA2B 0x00a0 -#define MACB_SA2T 0x00a4 -#define MACB_SA3B 0x00a8 -#define MACB_SA3T 0x00ac -#define MACB_SA4B 0x00b0 -#define MACB_SA4T 0x00b4 -#define MACB_TID 0x00b8 -#define MACB_TPQ 0x00bc -#define MACB_USRIO 0x00c0 -#define MACB_WOL 0x00c4 +#define MACB_NCR 0x0000 +#define MACB_NCFGR 0x0004 +#define MACB_NSR 0x0008 +#define MACB_TSR 0x0014 +#define MACB_RBQP 0x0018 +#define MACB_TBQP 0x001c +#define MACB_RSR 0x0020 +#define MACB_ISR 0x0024 +#define MACB_IER 0x0028 +#define MACB_IDR 0x002c +#define MACB_IMR 0x0030 +#define MACB_MAN 0x0034 +#define MACB_PTR 0x0038 +#define MACB_PFR 0x003c +#define MACB_FTO 0x0040 +#define MACB_SCF 0x0044 +#define MACB_MCF 0x0048 +#define MACB_FRO 0x004c +#define MACB_FCSE 0x0050 +#define MACB_ALE 0x0054 +#define MACB_DTF 0x0058 +#define MACB_LCOL 0x005c +#define MACB_EXCOL 0x0060 +#define MACB_TUND 0x0064 +#define MACB_CSE 0x0068 +#define MACB_RRE 0x006c +#define MACB_ROVR 0x0070 +#define MACB_RSE 0x0074 +#define MACB_ELE 0x0078 +#define MACB_RJA 0x007c +#define MACB_USF 0x0080 +#define MACB_STE 0x0084 +#define MACB_RLE 0x0088 +#define MACB_TPF 0x008c +#define MACB_HRB 0x0090 +#define MACB_HRT 0x0094 +#define MACB_SA1B 0x0098 +#define MACB_SA1T 0x009c +#define MACB_SA2B 0x00a0 +#define MACB_SA2T 0x00a4 +#define MACB_SA3B 0x00a8 +#define MACB_SA3T 0x00ac +#define MACB_SA4B 0x00b0 +#define MACB_SA4T 0x00b4 +#define MACB_TID 0x00b8 +#define MACB_TPQ 0x00bc +#define MACB_USRIO 0x00c0 +#define MACB_WOL 0x00c4 /* Bitfields in NCR */ -#define MACB_LB_OFFSET 0 -#define MACB_LB_SIZE 1 -#define MACB_LLB_OFFSET 1 -#define MACB_LLB_SIZE 1 -#define MACB_RE_OFFSET 2 -#define MACB_RE_SIZE 1 -#define MACB_TE_OFFSET 3 -#define MACB_TE_SIZE 1 -#define MACB_MPE_OFFSET 4 -#define MACB_MPE_SIZE 1 -#define MACB_CLRSTAT_OFFSET 5 -#define MACB_CLRSTAT_SIZE 1 -#define MACB_INCSTAT_OFFSET 6 -#define MACB_INCSTAT_SIZE 1 -#define MACB_WESTAT_OFFSET 7 -#define MACB_WESTAT_SIZE 1 -#define MACB_BP_OFFSET 8 -#define MACB_BP_SIZE 1 -#define MACB_TSTART_OFFSET 9 -#define MACB_TSTART_SIZE 1 -#define MACB_THALT_OFFSET 10 -#define MACB_THALT_SIZE 1 -#define MACB_NCR_TPF_OFFSET 11 -#define MACB_NCR_TPF_SIZE 1 -#define MACB_TZQ_OFFSET 12 -#define MACB_TZQ_SIZE 1 +#define MACB_LB_OFFSET 0 +#define MACB_LB_SIZE 1 +#define MACB_LLB_OFFSET 1 +#define MACB_LLB_SIZE 1 +#define MACB_RE_OFFSET 2 +#define MACB_RE_SIZE 1 +#define MACB_TE_OFFSET 3 +#define MACB_TE_SIZE 1 +#define MACB_MPE_OFFSET 4 +#define MACB_MPE_SIZE 1 +#define MACB_CLRSTAT_OFFSET 5 +#define MACB_CLRSTAT_SIZE 1 +#define MACB_INCSTAT_OFFSET 6 +#define MACB_INCSTAT_SIZE 1 +#define MACB_WESTAT_OFFSET 7 +#define MACB_WESTAT_SIZE 1 +#define MACB_BP_OFFSET 8 +#define MACB_BP_SIZE 1 +#define MACB_TSTART_OFFSET 9 +#define MACB_TSTART_SIZE 1 +#define MACB_THALT_OFFSET 10 +#define MACB_THALT_SIZE 1 +#define MACB_NCR_TPF_OFFSET 11 +#define MACB_NCR_TPF_SIZE 1 +#define MACB_TZQ_OFFSET 12 +#define MACB_TZQ_SIZE 1 /* Bitfields in NCFGR */ -#define MACB_SPD_OFFSET 0 -#define MACB_SPD_SIZE 1 -#define MACB_FD_OFFSET 1 -#define MACB_FD_SIZE 1 -#define MACB_BIT_RATE_OFFSET 2 -#define MACB_BIT_RATE_SIZE 1 -#define MACB_JFRAME_OFFSET 3 -#define MACB_JFRAME_SIZE 1 -#define MACB_CAF_OFFSET 4 -#define MACB_CAF_SIZE 1 -#define MACB_NBC_OFFSET 5 -#define MACB_NBC_SIZE 1 -#define MACB_NCFGR_MTI_OFFSET 6 -#define MACB_NCFGR_MTI_SIZE 1 -#define MACB_UNI_OFFSET 7 -#define MACB_UNI_SIZE 1 -#define MACB_BIG_OFFSET 8 -#define MACB_BIG_SIZE 1 -#define MACB_EAE_OFFSET 9 -#define MACB_EAE_SIZE 1 -#define MACB_CLK_OFFSET 10 -#define MACB_CLK_SIZE 2 -#define MACB_RTY_OFFSET 12 -#define MACB_RTY_SIZE 1 -#define MACB_PAE_OFFSET 13 -#define MACB_PAE_SIZE 1 -#define MACB_RBOF_OFFSET 14 -#define MACB_RBOF_SIZE 2 -#define MACB_RLCE_OFFSET 16 -#define MACB_RLCE_SIZE 1 -#define MACB_DRFCS_OFFSET 17 -#define MACB_DRFCS_SIZE 1 -#define MACB_EFRHD_OFFSET 18 -#define MACB_EFRHD_SIZE 1 -#define MACB_IRXFCS_OFFSET 19 -#define MACB_IRXFCS_SIZE 1 +#define MACB_SPD_OFFSET 0 +#define MACB_SPD_SIZE 1 +#define MACB_FD_OFFSET 1 +#define MACB_FD_SIZE 1 +#define MACB_BIT_RATE_OFFSET 2 +#define MACB_BIT_RATE_SIZE 1 +#define MACB_JFRAME_OFFSET 3 +#define MACB_JFRAME_SIZE 1 +#define MACB_CAF_OFFSET 4 +#define MACB_CAF_SIZE 1 +#define MACB_NBC_OFFSET 5 +#define MACB_NBC_SIZE 1 +#define MACB_NCFGR_MTI_OFFSET 6 +#define MACB_NCFGR_MTI_SIZE 1 +#define MACB_UNI_OFFSET 7 +#define MACB_UNI_SIZE 1 +#define MACB_BIG_OFFSET 8 +#define MACB_BIG_SIZE 1 +#define MACB_EAE_OFFSET 9 +#define MACB_EAE_SIZE 1 +#define MACB_CLK_OFFSET 10 +#define MACB_CLK_SIZE 2 +#define MACB_RTY_OFFSET 12 +#define MACB_RTY_SIZE 1 +#define MACB_PAE_OFFSET 13 +#define MACB_PAE_SIZE 1 +#define MACB_RBOF_OFFSET 14 +#define MACB_RBOF_SIZE 2 +#define MACB_RLCE_OFFSET 16 +#define MACB_RLCE_SIZE 1 +#define MACB_DRFCS_OFFSET 17 +#define MACB_DRFCS_SIZE 1 +#define MACB_EFRHD_OFFSET 18 +#define MACB_EFRHD_SIZE 1 +#define MACB_IRXFCS_OFFSET 19 +#define MACB_IRXFCS_SIZE 1 /* Bitfields in NSR */ -#define MACB_NSR_LINK_OFFSET 0 -#define MACB_NSR_LINK_SIZE 1 -#define MACB_MDIO_OFFSET 1 -#define MACB_MDIO_SIZE 1 -#define MACB_IDLE_OFFSET 2 -#define MACB_IDLE_SIZE 1 +#define MACB_NSR_LINK_OFFSET 0 +#define MACB_NSR_LINK_SIZE 1 +#define MACB_MDIO_OFFSET 1 +#define MACB_MDIO_SIZE 1 +#define MACB_IDLE_OFFSET 2 +#define MACB_IDLE_SIZE 1 /* Bitfields in TSR */ -#define MACB_UBR_OFFSET 0 -#define MACB_UBR_SIZE 1 -#define MACB_COL_OFFSET 1 -#define MACB_COL_SIZE 1 -#define MACB_TSR_RLE_OFFSET 2 -#define MACB_TSR_RLE_SIZE 1 -#define MACB_TGO_OFFSET 3 -#define MACB_TGO_SIZE 1 -#define MACB_BEX_OFFSET 4 -#define MACB_BEX_SIZE 1 -#define MACB_COMP_OFFSET 5 -#define MACB_COMP_SIZE 1 -#define MACB_UND_OFFSET 6 -#define MACB_UND_SIZE 1 +#define MACB_UBR_OFFSET 0 +#define MACB_UBR_SIZE 1 +#define MACB_COL_OFFSET 1 +#define MACB_COL_SIZE 1 +#define MACB_TSR_RLE_OFFSET 2 +#define MACB_TSR_RLE_SIZE 1 +#define MACB_TGO_OFFSET 3 +#define MACB_TGO_SIZE 1 +#define MACB_BEX_OFFSET 4 +#define MACB_BEX_SIZE 1 +#define MACB_COMP_OFFSET 5 +#define MACB_COMP_SIZE 1 +#define MACB_UND_OFFSET 6 +#define MACB_UND_SIZE 1 /* Bitfields in RSR */ -#define MACB_BNA_OFFSET 0 -#define MACB_BNA_SIZE 1 -#define MACB_REC_OFFSET 1 -#define MACB_REC_SIZE 1 -#define MACB_OVR_OFFSET 2 -#define MACB_OVR_SIZE 1 +#define MACB_BNA_OFFSET 0 +#define MACB_BNA_SIZE 1 +#define MACB_REC_OFFSET 1 +#define MACB_REC_SIZE 1 +#define MACB_OVR_OFFSET 2 +#define MACB_OVR_SIZE 1 /* Bitfields in ISR/IER/IDR/IMR */ -#define MACB_MFD_OFFSET 0 -#define MACB_MFD_SIZE 1 -#define MACB_RCOMP_OFFSET 1 -#define MACB_RCOMP_SIZE 1 -#define MACB_RXUBR_OFFSET 2 -#define MACB_RXUBR_SIZE 1 -#define MACB_TXUBR_OFFSET 3 -#define MACB_TXUBR_SIZE 1 -#define MACB_ISR_TUND_OFFSET 4 -#define MACB_ISR_TUND_SIZE 1 -#define MACB_ISR_RLE_OFFSET 5 -#define MACB_ISR_RLE_SIZE 1 -#define MACB_TXERR_OFFSET 6 -#define MACB_TXERR_SIZE 1 -#define MACB_TCOMP_OFFSET 7 -#define MACB_TCOMP_SIZE 1 -#define MACB_ISR_LINK_OFFSET 9 -#define MACB_ISR_LINK_SIZE 1 -#define MACB_ISR_ROVR_OFFSET 10 -#define MACB_ISR_ROVR_SIZE 1 -#define MACB_HRESP_OFFSET 11 -#define MACB_HRESP_SIZE 1 -#define MACB_PFR_OFFSET 12 -#define MACB_PFR_SIZE 1 -#define MACB_PTZ_OFFSET 13 -#define MACB_PTZ_SIZE 1 +#define MACB_MFD_OFFSET 0 +#define MACB_MFD_SIZE 1 +#define MACB_RCOMP_OFFSET 1 +#define MACB_RCOMP_SIZE 1 +#define MACB_RXUBR_OFFSET 2 +#define MACB_RXUBR_SIZE 1 +#define MACB_TXUBR_OFFSET 3 +#define MACB_TXUBR_SIZE 1 +#define MACB_ISR_TUND_OFFSET 4 +#define MACB_ISR_TUND_SIZE 1 +#define MACB_ISR_RLE_OFFSET 5 +#define MACB_ISR_RLE_SIZE 1 +#define MACB_TXERR_OFFSET 6 +#define MACB_TXERR_SIZE 1 +#define MACB_TCOMP_OFFSET 7 +#define MACB_TCOMP_SIZE 1 +#define MACB_ISR_LINK_OFFSET 9 +#define MACB_ISR_LINK_SIZE 1 +#define MACB_ISR_ROVR_OFFSET 10 +#define MACB_ISR_ROVR_SIZE 1 +#define MACB_HRESP_OFFSET 11 +#define MACB_HRESP_SIZE 1 +#define MACB_PFR_OFFSET 12 +#define MACB_PFR_SIZE 1 +#define MACB_PTZ_OFFSET 13 +#define MACB_PTZ_SIZE 1 /* Bitfields in MAN */ -#define MACB_DATA_OFFSET 0 -#define MACB_DATA_SIZE 16 -#define MACB_CODE_OFFSET 16 -#define MACB_CODE_SIZE 2 -#define MACB_REGA_OFFSET 18 -#define MACB_REGA_SIZE 5 -#define MACB_PHYA_OFFSET 23 -#define MACB_PHYA_SIZE 5 -#define MACB_RW_OFFSET 28 -#define MACB_RW_SIZE 2 -#define MACB_SOF_OFFSET 30 -#define MACB_SOF_SIZE 2 +#define MACB_DATA_OFFSET 0 +#define MACB_DATA_SIZE 16 +#define MACB_CODE_OFFSET 16 +#define MACB_CODE_SIZE 2 +#define MACB_REGA_OFFSET 18 +#define MACB_REGA_SIZE 5 +#define MACB_PHYA_OFFSET 23 +#define MACB_PHYA_SIZE 5 +#define MACB_RW_OFFSET 28 +#define MACB_RW_SIZE 2 +#define MACB_SOF_OFFSET 30 +#define MACB_SOF_SIZE 2 /* Bitfields in USRIO (AVR32) */ -#define MACB_MII_OFFSET 0 -#define MACB_MII_SIZE 1 -#define MACB_EAM_OFFSET 1 -#define MACB_EAM_SIZE 1 -#define MACB_TX_PAUSE_OFFSET 2 -#define MACB_TX_PAUSE_SIZE 1 -#define MACB_TX_PAUSE_ZERO_OFFSET 3 -#define MACB_TX_PAUSE_ZERO_SIZE 1 +#define MACB_MII_OFFSET 0 +#define MACB_MII_SIZE 1 +#define MACB_EAM_OFFSET 1 +#define MACB_EAM_SIZE 1 +#define MACB_TX_PAUSE_OFFSET 2 +#define MACB_TX_PAUSE_SIZE 1 +#define MACB_TX_PAUSE_ZERO_OFFSET 3 +#define MACB_TX_PAUSE_ZERO_SIZE 1 /* Bitfields in USRIO (AT91) */ -#define MACB_RMII_OFFSET 0 -#define MACB_RMII_SIZE 1 -#define MACB_CLKEN_OFFSET 1 -#define MACB_CLKEN_SIZE 1 +#define MACB_RMII_OFFSET 0 +#define MACB_RMII_SIZE 1 +#define MACB_CLKEN_OFFSET 1 +#define MACB_CLKEN_SIZE 1 /* Bitfields in WOL */ -#define MACB_IP_OFFSET 0 -#define MACB_IP_SIZE 16 -#define MACB_MAG_OFFSET 16 -#define MACB_MAG_SIZE 1 -#define MACB_ARP_OFFSET 17 -#define MACB_ARP_SIZE 1 -#define MACB_SA1_OFFSET 18 -#define MACB_SA1_SIZE 1 -#define MACB_WOL_MTI_OFFSET 19 -#define MACB_WOL_MTI_SIZE 1 +#define MACB_IP_OFFSET 0 +#define MACB_IP_SIZE 16 +#define MACB_MAG_OFFSET 16 +#define MACB_MAG_SIZE 1 +#define MACB_ARP_OFFSET 17 +#define MACB_ARP_SIZE 1 +#define MACB_SA1_OFFSET 18 +#define MACB_SA1_SIZE 1 +#define MACB_WOL_MTI_OFFSET 19 +#define MACB_WOL_MTI_SIZE 1 /* Constants for CLK */ -#define MACB_CLK_DIV8 0 -#define MACB_CLK_DIV16 1 -#define MACB_CLK_DIV32 2 -#define MACB_CLK_DIV64 3 +#define MACB_CLK_DIV8 0 +#define MACB_CLK_DIV16 1 +#define MACB_CLK_DIV32 2 +#define MACB_CLK_DIV64 3 /* Constants for MAN register */ -#define MACB_MAN_SOF 1 -#define MACB_MAN_WRITE 1 -#define MACB_MAN_READ 2 -#define MACB_MAN_CODE 2 +#define MACB_MAN_SOF 1 +#define MACB_MAN_WRITE 1 +#define MACB_MAN_READ 2 +#define MACB_MAN_CODE 2 /* Bit manipulation macros */ -#define MACB_BIT(name) \ - (1 << MACB_##name##_OFFSET) -#define MACB_BF(name,value) \ - (((value) & ((1 << MACB_##name##_SIZE) - 1)) \ - << MACB_##name##_OFFSET) +#define MACB_BIT(name) \ + (1 << MACB_##name##_OFFSET) +#define MACB_BF(name,value) \ + (((value) & ((1 << MACB_##name##_SIZE) - 1)) \ + << MACB_##name##_OFFSET) #define MACB_BFEXT(name,value)\ - (((value) >> MACB_##name##_OFFSET) \ - & ((1 << MACB_##name##_SIZE) - 1)) -#define MACB_BFINS(name,value,old) \ - (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \ - << MACB_##name##_OFFSET)) \ - | MACB_BF(name,value)) + (((value) >> MACB_##name##_OFFSET) \ + & ((1 << MACB_##name##_SIZE) - 1)) +#define MACB_BFINS(name,value,old) \ + (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \ + << MACB_##name##_OFFSET)) \ + | MACB_BF(name,value)) /* Register access macros */ -#define macb_readl(port,reg) \ - readl((port)->regs + MACB_##reg) -#define macb_writel(port,reg,value) \ - writel((value), (port)->regs + MACB_##reg) +#define macb_readl(port,reg) \ + readl((port)->regs + MACB_##reg) +#define macb_writel(port,reg,value) \ + writel((value), (port)->regs + MACB_##reg) struct dma_desc { - rt_uint32_t addr; - rt_uint32_t ctrl; + rt_uint32_t addr; + rt_uint32_t ctrl; }; /* DMA descriptor bitfields */ -#define MACB_RX_USED_OFFSET 0 -#define MACB_RX_USED_SIZE 1 -#define MACB_RX_WRAP_OFFSET 1 -#define MACB_RX_WRAP_SIZE 1 -#define MACB_RX_WADDR_OFFSET 2 -#define MACB_RX_WADDR_SIZE 30 +#define MACB_RX_USED_OFFSET 0 +#define MACB_RX_USED_SIZE 1 +#define MACB_RX_WRAP_OFFSET 1 +#define MACB_RX_WRAP_SIZE 1 +#define MACB_RX_WADDR_OFFSET 2 +#define MACB_RX_WADDR_SIZE 30 -#define MACB_RX_FRMLEN_OFFSET 0 -#define MACB_RX_FRMLEN_SIZE 12 -#define MACB_RX_OFFSET_OFFSET 12 -#define MACB_RX_OFFSET_SIZE 2 -#define MACB_RX_SOF_OFFSET 14 -#define MACB_RX_SOF_SIZE 1 -#define MACB_RX_EOF_OFFSET 15 -#define MACB_RX_EOF_SIZE 1 -#define MACB_RX_CFI_OFFSET 16 -#define MACB_RX_CFI_SIZE 1 -#define MACB_RX_VLAN_PRI_OFFSET 17 -#define MACB_RX_VLAN_PRI_SIZE 3 -#define MACB_RX_PRI_TAG_OFFSET 20 -#define MACB_RX_PRI_TAG_SIZE 1 -#define MACB_RX_VLAN_TAG_OFFSET 21 -#define MACB_RX_VLAN_TAG_SIZE 1 -#define MACB_RX_TYPEID_MATCH_OFFSET 22 -#define MACB_RX_TYPEID_MATCH_SIZE 1 -#define MACB_RX_SA4_MATCH_OFFSET 23 -#define MACB_RX_SA4_MATCH_SIZE 1 -#define MACB_RX_SA3_MATCH_OFFSET 24 -#define MACB_RX_SA3_MATCH_SIZE 1 -#define MACB_RX_SA2_MATCH_OFFSET 25 -#define MACB_RX_SA2_MATCH_SIZE 1 -#define MACB_RX_SA1_MATCH_OFFSET 26 -#define MACB_RX_SA1_MATCH_SIZE 1 -#define MACB_RX_EXT_MATCH_OFFSET 28 -#define MACB_RX_EXT_MATCH_SIZE 1 -#define MACB_RX_UHASH_MATCH_OFFSET 29 -#define MACB_RX_UHASH_MATCH_SIZE 1 -#define MACB_RX_MHASH_MATCH_OFFSET 30 -#define MACB_RX_MHASH_MATCH_SIZE 1 -#define MACB_RX_BROADCAST_OFFSET 31 -#define MACB_RX_BROADCAST_SIZE 1 +#define MACB_RX_FRMLEN_OFFSET 0 +#define MACB_RX_FRMLEN_SIZE 12 +#define MACB_RX_OFFSET_OFFSET 12 +#define MACB_RX_OFFSET_SIZE 2 +#define MACB_RX_SOF_OFFSET 14 +#define MACB_RX_SOF_SIZE 1 +#define MACB_RX_EOF_OFFSET 15 +#define MACB_RX_EOF_SIZE 1 +#define MACB_RX_CFI_OFFSET 16 +#define MACB_RX_CFI_SIZE 1 +#define MACB_RX_VLAN_PRI_OFFSET 17 +#define MACB_RX_VLAN_PRI_SIZE 3 +#define MACB_RX_PRI_TAG_OFFSET 20 +#define MACB_RX_PRI_TAG_SIZE 1 +#define MACB_RX_VLAN_TAG_OFFSET 21 +#define MACB_RX_VLAN_TAG_SIZE 1 +#define MACB_RX_TYPEID_MATCH_OFFSET 22 +#define MACB_RX_TYPEID_MATCH_SIZE 1 +#define MACB_RX_SA4_MATCH_OFFSET 23 +#define MACB_RX_SA4_MATCH_SIZE 1 +#define MACB_RX_SA3_MATCH_OFFSET 24 +#define MACB_RX_SA3_MATCH_SIZE 1 +#define MACB_RX_SA2_MATCH_OFFSET 25 +#define MACB_RX_SA2_MATCH_SIZE 1 +#define MACB_RX_SA1_MATCH_OFFSET 26 +#define MACB_RX_SA1_MATCH_SIZE 1 +#define MACB_RX_EXT_MATCH_OFFSET 28 +#define MACB_RX_EXT_MATCH_SIZE 1 +#define MACB_RX_UHASH_MATCH_OFFSET 29 +#define MACB_RX_UHASH_MATCH_SIZE 1 +#define MACB_RX_MHASH_MATCH_OFFSET 30 +#define MACB_RX_MHASH_MATCH_SIZE 1 +#define MACB_RX_BROADCAST_OFFSET 31 +#define MACB_RX_BROADCAST_SIZE 1 -#define MACB_TX_FRMLEN_OFFSET 0 -#define MACB_TX_FRMLEN_SIZE 11 -#define MACB_TX_LAST_OFFSET 15 -#define MACB_TX_LAST_SIZE 1 -#define MACB_TX_NOCRC_OFFSET 16 -#define MACB_TX_NOCRC_SIZE 1 -#define MACB_TX_BUF_EXHAUSTED_OFFSET 27 -#define MACB_TX_BUF_EXHAUSTED_SIZE 1 -#define MACB_TX_UNDERRUN_OFFSET 28 -#define MACB_TX_UNDERRUN_SIZE 1 -#define MACB_TX_ERROR_OFFSET 29 -#define MACB_TX_ERROR_SIZE 1 -#define MACB_TX_WRAP_OFFSET 30 -#define MACB_TX_WRAP_SIZE 1 -#define MACB_TX_USED_OFFSET 31 -#define MACB_TX_USED_SIZE 1 +#define MACB_TX_FRMLEN_OFFSET 0 +#define MACB_TX_FRMLEN_SIZE 11 +#define MACB_TX_LAST_OFFSET 15 +#define MACB_TX_LAST_SIZE 1 +#define MACB_TX_NOCRC_OFFSET 16 +#define MACB_TX_NOCRC_SIZE 1 +#define MACB_TX_BUF_EXHAUSTED_OFFSET 27 +#define MACB_TX_BUF_EXHAUSTED_SIZE 1 +#define MACB_TX_UNDERRUN_OFFSET 28 +#define MACB_TX_UNDERRUN_SIZE 1 +#define MACB_TX_ERROR_OFFSET 29 +#define MACB_TX_ERROR_SIZE 1 +#define MACB_TX_WRAP_OFFSET 30 +#define MACB_TX_WRAP_SIZE 1 +#define MACB_TX_USED_OFFSET 31 +#define MACB_TX_USED_SIZE 1 extern int rt_hw_macb_init(); diff --git a/bsp/at91sam9260/drivers/mii.h b/bsp/at91sam9260/drivers/mii.h index 2f6dd18e71..03d914b7c3 100644 --- a/bsp/at91sam9260/drivers/mii.h +++ b/bsp/at91sam9260/drivers/mii.h @@ -1,21 +1,7 @@ /* - * File : mii.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -36,7 +22,7 @@ #define MII_EXPANSION 0x06 /* Expansion register */ #define MII_CTRL1000 0x09 /* 1000BASE-T control */ #define MII_STAT1000 0x0a /* 1000BASE-T status */ -#define MII_ESTATUS 0x0f /* Extended Status */ +#define MII_ESTATUS 0x0f /* Extended Status */ #define MII_DCOUNTER 0x12 /* Disconnect counter */ #define MII_FCSCOUNTER 0x13 /* False carrier counter */ #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ @@ -51,7 +37,7 @@ /* Basic mode control register. */ #define BMCR_RESV 0x003f /* Unused... */ -#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ +#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ #define BMCR_CTST 0x0080 /* Collision test */ #define BMCR_FULLDPLX 0x0100 /* Full duplex */ #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ @@ -70,7 +56,7 @@ #define BMSR_RFAULT 0x0010 /* Remote fault detected */ #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ #define BMSR_RESV 0x00c0 /* Unused... */ -#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ +#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */ #define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */ #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ @@ -99,7 +85,7 @@ #define ADVERTISE_NPAGE 0x8000 /* Next page bit */ #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ - ADVERTISE_CSMA) + ADVERTISE_CSMA) #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ ADVERTISE_100HALF | ADVERTISE_100FULL) @@ -121,8 +107,8 @@ #define LPA_LPACK 0x4000 /* Link partner acked us */ #define LPA_NPAGE 0x8000 /* Next page bit */ -#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) -#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) +#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) +#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) /* Expansion register for auto-negotiation. */ #define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */ @@ -132,8 +118,8 @@ #define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */ #define EXPANSION_RESV 0xffe0 /* Unused... */ -#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ -#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ +#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ +#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ /* N-way test register. */ #define NWAYTEST_RESV1 0x00ff /* Unused... */ @@ -151,8 +137,8 @@ #define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */ /* Flow control flags */ -#define FLOW_CTRL_TX 0x01 -#define FLOW_CTRL_RX 0x02 +#define FLOW_CTRL_TX 0x01 +#define FLOW_CTRL_RX 0x02 /** * mii_nway_result diff --git a/bsp/at91sam9260/drivers/usart.c b/bsp/at91sam9260/drivers/usart.c index fb91393b3c..2d493a21bb 100644 --- a/bsp/at91sam9260/drivers/usart.c +++ b/bsp/at91sam9260/drivers/usart.c @@ -1,21 +1,7 @@ /* - * File : usart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -28,54 +14,54 @@ #include #include -#define RXRDY 0x01 -#define TXRDY (1 << 1) +#define RXRDY 0x01 +#define TXRDY (1 << 1) typedef struct uartport { - volatile rt_uint32_t CR; - volatile rt_uint32_t MR; - volatile rt_uint32_t IER; - volatile rt_uint32_t IDR; - volatile rt_uint32_t IMR; - volatile rt_uint32_t CSR; - volatile rt_uint32_t RHR; - volatile rt_uint32_t THR; - volatile rt_uint32_t BRGR; - volatile rt_uint32_t RTOR; - volatile rt_uint32_t TTGR; - volatile rt_uint32_t reserved0[5]; - volatile rt_uint32_t FIDI; - volatile rt_uint32_t NER; - volatile rt_uint32_t reserved1; - volatile rt_uint32_t IFR; - volatile rt_uint32_t reserved2[44]; - volatile rt_uint32_t RPR; - volatile rt_uint32_t RCR; - volatile rt_uint32_t TPR; - volatile rt_uint32_t TCR; - volatile rt_uint32_t RNPR; - volatile rt_uint32_t RNCR; - volatile rt_uint32_t TNPR; - volatile rt_uint32_t TNCR; - volatile rt_uint32_t PTCR; - volatile rt_uint32_t PTSR; + volatile rt_uint32_t CR; + volatile rt_uint32_t MR; + volatile rt_uint32_t IER; + volatile rt_uint32_t IDR; + volatile rt_uint32_t IMR; + volatile rt_uint32_t CSR; + volatile rt_uint32_t RHR; + volatile rt_uint32_t THR; + volatile rt_uint32_t BRGR; + volatile rt_uint32_t RTOR; + volatile rt_uint32_t TTGR; + volatile rt_uint32_t reserved0[5]; + volatile rt_uint32_t FIDI; + volatile rt_uint32_t NER; + volatile rt_uint32_t reserved1; + volatile rt_uint32_t IFR; + volatile rt_uint32_t reserved2[44]; + volatile rt_uint32_t RPR; + volatile rt_uint32_t RCR; + volatile rt_uint32_t TPR; + volatile rt_uint32_t TCR; + volatile rt_uint32_t RNPR; + volatile rt_uint32_t RNCR; + volatile rt_uint32_t TNPR; + volatile rt_uint32_t TNCR; + volatile rt_uint32_t PTCR; + volatile rt_uint32_t PTSR; }uartport; #define CIDR FIDI #define EXID NER #define FNR reserved1 -#define DBGU ((struct uartport *)AT91SAM9260_BASE_DBGU) +#define DBGU ((struct uartport *)AT91SAM9260_BASE_DBGU) -#define UART0 ((struct uartport *)AT91SAM9260_BASE_US0) -#define UART1 ((struct uartport *)AT91SAM9260_BASE_US1) -#define UART2 ((struct uartport *)AT91SAM9260_BASE_US2) -#define UART3 ((struct uartport *)AT91SAM9260_BASE_US3) +#define UART0 ((struct uartport *)AT91SAM9260_BASE_US0) +#define UART1 ((struct uartport *)AT91SAM9260_BASE_US1) +#define UART2 ((struct uartport *)AT91SAM9260_BASE_US2) +#define UART3 ((struct uartport *)AT91SAM9260_BASE_US3) struct at91_uart { - uartport *port; - int irq; + uartport *port; + int irq; }; @@ -85,18 +71,18 @@ struct at91_uart { */ void rt_at91_usart_handler(int vector, void *param) { - int status; - struct at91_uart *uart; - rt_device_t dev = (rt_device_t)param; - uart = (struct at91_uart *)dev->user_data; - status = uart->port->CSR; - if (!(status & uart->port->IMR)) - { - return; - } - rt_interrupt_enter(); - rt_hw_serial_isr((struct rt_serial_device *)dev, RT_SERIAL_EVENT_RX_IND); - rt_interrupt_leave(); + int status; + struct at91_uart *uart; + rt_device_t dev = (rt_device_t)param; + uart = (struct at91_uart *)dev->user_data; + status = uart->port->CSR; + if (!(status & uart->port->IMR)) + { + return; + } + rt_interrupt_enter(); + rt_hw_serial_isr((struct rt_serial_device *)dev, RT_SERIAL_EVENT_RX_IND); + rt_interrupt_leave(); } /** @@ -105,67 +91,67 @@ void rt_at91_usart_handler(int vector, void *param) static rt_err_t at91_usart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) { - int div; - int mode = 0; - struct at91_uart *uart; + int div; + int mode = 0; + struct at91_uart *uart; - RT_ASSERT(serial != RT_NULL); + RT_ASSERT(serial != RT_NULL); RT_ASSERT(cfg != RT_NULL); - uart = (struct at91_uart *)serial->parent.user_data; + uart = (struct at91_uart *)serial->parent.user_data; - uart->port->CR = AT91_US_RSTTX | AT91_US_RSTRX | - AT91_US_RXDIS | AT91_US_TXDIS; - mode |= AT91_US_USMODE_NORMAL | AT91_US_USCLKS_MCK | - AT91_US_CHMODE_NORMAL; - switch (cfg->data_bits) - { - case DATA_BITS_8: - mode |= AT91_US_CHRL_8; - break; - case DATA_BITS_7: - mode |= AT91_US_CHRL_7; - break; - case DATA_BITS_6: - mode |= AT91_US_CHRL_6; - break; - case DATA_BITS_5: - mode |= AT91_US_CHRL_5; - break; - default: - mode |= AT91_US_CHRL_8; - break; - } + uart->port->CR = AT91_US_RSTTX | AT91_US_RSTRX | + AT91_US_RXDIS | AT91_US_TXDIS; + mode |= AT91_US_USMODE_NORMAL | AT91_US_USCLKS_MCK | + AT91_US_CHMODE_NORMAL; + switch (cfg->data_bits) + { + case DATA_BITS_8: + mode |= AT91_US_CHRL_8; + break; + case DATA_BITS_7: + mode |= AT91_US_CHRL_7; + break; + case DATA_BITS_6: + mode |= AT91_US_CHRL_6; + break; + case DATA_BITS_5: + mode |= AT91_US_CHRL_5; + break; + default: + mode |= AT91_US_CHRL_8; + break; + } - switch (cfg->stop_bits) - { - case STOP_BITS_2: - mode |= AT91_US_NBSTOP_2; - break; - case STOP_BITS_1: - default: - mode |= AT91_US_NBSTOP_1; - break; - } + switch (cfg->stop_bits) + { + case STOP_BITS_2: + mode |= AT91_US_NBSTOP_2; + break; + case STOP_BITS_1: + default: + mode |= AT91_US_NBSTOP_1; + break; + } - switch (cfg->parity) - { - case PARITY_ODD: - mode |= AT91_US_PAR_ODD; - break; - case PARITY_EVEN: - mode |= AT91_US_PAR_EVEN; - break; - case PARITY_NONE: - default: - mode |= AT91_US_PAR_NONE; - break; - } + switch (cfg->parity) + { + case PARITY_ODD: + mode |= AT91_US_PAR_ODD; + break; + case PARITY_EVEN: + mode |= AT91_US_PAR_EVEN; + break; + case PARITY_NONE: + default: + mode |= AT91_US_PAR_NONE; + break; + } - uart->port->MR = mode; - div = (clk_get_rate(clk_get("mck")) / 16 + cfg->baud_rate/2) / cfg->baud_rate; - uart->port->BRGR = div; - uart->port->CR = AT91_US_RXEN | AT91_US_TXEN; - uart->port->IER = 0x01; + uart->port->MR = mode; + div = (clk_get_rate(clk_get("mck")) / 16 + cfg->baud_rate/2) / cfg->baud_rate; + uart->port->BRGR = div; + uart->port->CR = AT91_US_RXEN | AT91_US_TXEN; + uart->port->IER = 0x01; return RT_EOK; } @@ -182,11 +168,11 @@ static rt_err_t at91_usart_control(struct rt_serial_device *serial, { case RT_DEVICE_CTRL_CLR_INT: /* disable rx irq */ - rt_hw_interrupt_mask(uart->irq); + rt_hw_interrupt_mask(uart->irq); break; case RT_DEVICE_CTRL_SET_INT: /* enable rx irq */ - rt_hw_interrupt_umask(uart->irq); + rt_hw_interrupt_umask(uart->irq); break; } @@ -196,10 +182,10 @@ static rt_err_t at91_usart_control(struct rt_serial_device *serial, static int at91_usart_putc(struct rt_serial_device *serial, char c) { rt_uint32_t level; - struct at91_uart *uart = serial->parent.user_data; + struct at91_uart *uart = serial->parent.user_data; while (!(uart->port->CSR & TXRDY)); - uart->port->THR = c; + uart->port->THR = c; return 1; } @@ -207,16 +193,16 @@ static int at91_usart_putc(struct rt_serial_device *serial, char c) static int at91_usart_getc(struct rt_serial_device *serial) { int result; - struct at91_uart *uart = serial->parent.user_data; + struct at91_uart *uart = serial->parent.user_data; if (uart->port->CSR & RXRDY) - { - result = uart->port->RHR & 0xff; - } - else - { - result = -1; - } + { + result = uart->port->RHR & 0xff; + } + else + { + result = -1; + } return result; } @@ -232,8 +218,8 @@ static const struct rt_uart_ops at91_usart_ops = #if defined(RT_USING_DBGU) static struct rt_serial_device serial_dbgu; struct at91_uart dbgu = { - DBGU, - AT91_ID_SYS + DBGU, + AT91_ID_SYS }; #endif @@ -241,82 +227,82 @@ struct at91_uart dbgu = { #if defined(RT_USING_UART0) static struct rt_serial_device serial0; struct at91_uart uart0 = { - UART0, - AT91SAM9260_ID_US0 + UART0, + AT91SAM9260_ID_US0 }; #endif #if defined(RT_USING_UART1) static struct rt_serial_device serial1; struct at91_uart uart1 = { - UART1, - AT91SAM9260_ID_US1 + UART1, + AT91SAM9260_ID_US1 }; #endif #if defined(RT_USING_UART2) static struct rt_serial_device serial2; struct at91_uart uart2 = { - UART2, - AT91SAM9260_ID_US2 + UART2, + AT91SAM9260_ID_US2 }; #endif #if defined(RT_USING_UART3) static struct rt_serial_device serial3; struct at91_uart uart3 = { - UART3, - AT91SAM9260_ID_US3 + UART3, + AT91SAM9260_ID_US3 }; #endif void at91_usart_gpio_init(void) { - rt_uint32_t val; + rt_uint32_t val; #ifdef RT_USING_DBGU - at91_sys_write(AT91_PIOB + PIO_IDR, (1<<14)|(1<<15)); - //at91_sys_write(AT91_PIOB + PIO_PUER, (1<<6)); - at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<14)|(1<<15)); - at91_sys_write(AT91_PIOB + PIO_ASR, (1<<14)|(1<<15)); - at91_sys_write(AT91_PIOB + PIO_PDR, (1<<14)|(1<<15)); - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); + at91_sys_write(AT91_PIOB + PIO_IDR, (1<<14)|(1<<15)); + //at91_sys_write(AT91_PIOB + PIO_PUER, (1<<6)); + at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<14)|(1<<15)); + at91_sys_write(AT91_PIOB + PIO_ASR, (1<<14)|(1<<15)); + at91_sys_write(AT91_PIOB + PIO_PDR, (1<<14)|(1<<15)); + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); #endif #ifdef RT_USING_UART0 - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US0); - at91_sys_write(AT91_PIOB + PIO_IDR, (1<<4)|(1<<5)); - at91_sys_write(AT91_PIOB + PIO_PUER, (1<<4)); - at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<5)); - at91_sys_write(AT91_PIOB + PIO_ASR, (1<<4)|(1<<5)); - at91_sys_write(AT91_PIOB + PIO_PDR, (1<<4)|(1<<5)); + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US0); + at91_sys_write(AT91_PIOB + PIO_IDR, (1<<4)|(1<<5)); + at91_sys_write(AT91_PIOB + PIO_PUER, (1<<4)); + at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<5)); + at91_sys_write(AT91_PIOB + PIO_ASR, (1<<4)|(1<<5)); + at91_sys_write(AT91_PIOB + PIO_PDR, (1<<4)|(1<<5)); #endif #ifdef RT_USING_UART1 - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US1); - at91_sys_write(AT91_PIOB + PIO_IDR, (1<<6)|(1<<7)); - at91_sys_write(AT91_PIOB + PIO_PUER, (1<<6)); - at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<7)); - at91_sys_write(AT91_PIOB + PIO_ASR, (1<<6)|(1<<7)); - at91_sys_write(AT91_PIOB + PIO_PDR, (1<<6)|(1<<7)); + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US1); + at91_sys_write(AT91_PIOB + PIO_IDR, (1<<6)|(1<<7)); + at91_sys_write(AT91_PIOB + PIO_PUER, (1<<6)); + at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<7)); + at91_sys_write(AT91_PIOB + PIO_ASR, (1<<6)|(1<<7)); + at91_sys_write(AT91_PIOB + PIO_PDR, (1<<6)|(1<<7)); #endif #ifdef RT_USING_UART2 - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US2); - at91_sys_write(AT91_PIOB + PIO_IDR, (1<<8)|(1<<9)); - at91_sys_write(AT91_PIOB + PIO_PUER, (1<<8)); - at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<9)); - at91_sys_write(AT91_PIOB + PIO_ASR, (1<<8)|(1<<9)); - at91_sys_write(AT91_PIOB + PIO_PDR, (1<<8)|(1<<9)); + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US2); + at91_sys_write(AT91_PIOB + PIO_IDR, (1<<8)|(1<<9)); + at91_sys_write(AT91_PIOB + PIO_PUER, (1<<8)); + at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<9)); + at91_sys_write(AT91_PIOB + PIO_ASR, (1<<8)|(1<<9)); + at91_sys_write(AT91_PIOB + PIO_PDR, (1<<8)|(1<<9)); #endif #ifdef RT_USING_UART3 - at91_sys_write(AT91_PMC_PCER, 1< #include -#define PIN_BASE AIC_IRQS +#define PIN_BASE AIC_IRQS -#define MAX_GPIO_BANKS 3 +#define MAX_GPIO_BANKS 3 -#define PIN_IRQS (MAX_GPIO_BANKS*32) +#define PIN_IRQS (MAX_GPIO_BANKS*32) /* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */ -#define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0) -#define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1) -#define AT91_PIN_PA2 (PIN_BASE + 0x00 + 2) -#define AT91_PIN_PA3 (PIN_BASE + 0x00 + 3) -#define AT91_PIN_PA4 (PIN_BASE + 0x00 + 4) -#define AT91_PIN_PA5 (PIN_BASE + 0x00 + 5) -#define AT91_PIN_PA6 (PIN_BASE + 0x00 + 6) -#define AT91_PIN_PA7 (PIN_BASE + 0x00 + 7) -#define AT91_PIN_PA8 (PIN_BASE + 0x00 + 8) -#define AT91_PIN_PA9 (PIN_BASE + 0x00 + 9) -#define AT91_PIN_PA10 (PIN_BASE + 0x00 + 10) -#define AT91_PIN_PA11 (PIN_BASE + 0x00 + 11) -#define AT91_PIN_PA12 (PIN_BASE + 0x00 + 12) -#define AT91_PIN_PA13 (PIN_BASE + 0x00 + 13) -#define AT91_PIN_PA14 (PIN_BASE + 0x00 + 14) -#define AT91_PIN_PA15 (PIN_BASE + 0x00 + 15) -#define AT91_PIN_PA16 (PIN_BASE + 0x00 + 16) -#define AT91_PIN_PA17 (PIN_BASE + 0x00 + 17) -#define AT91_PIN_PA18 (PIN_BASE + 0x00 + 18) -#define AT91_PIN_PA19 (PIN_BASE + 0x00 + 19) -#define AT91_PIN_PA20 (PIN_BASE + 0x00 + 20) -#define AT91_PIN_PA21 (PIN_BASE + 0x00 + 21) -#define AT91_PIN_PA22 (PIN_BASE + 0x00 + 22) -#define AT91_PIN_PA23 (PIN_BASE + 0x00 + 23) -#define AT91_PIN_PA24 (PIN_BASE + 0x00 + 24) -#define AT91_PIN_PA25 (PIN_BASE + 0x00 + 25) -#define AT91_PIN_PA26 (PIN_BASE + 0x00 + 26) -#define AT91_PIN_PA27 (PIN_BASE + 0x00 + 27) -#define AT91_PIN_PA28 (PIN_BASE + 0x00 + 28) -#define AT91_PIN_PA29 (PIN_BASE + 0x00 + 29) -#define AT91_PIN_PA30 (PIN_BASE + 0x00 + 30) -#define AT91_PIN_PA31 (PIN_BASE + 0x00 + 31) +#define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0) +#define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1) +#define AT91_PIN_PA2 (PIN_BASE + 0x00 + 2) +#define AT91_PIN_PA3 (PIN_BASE + 0x00 + 3) +#define AT91_PIN_PA4 (PIN_BASE + 0x00 + 4) +#define AT91_PIN_PA5 (PIN_BASE + 0x00 + 5) +#define AT91_PIN_PA6 (PIN_BASE + 0x00 + 6) +#define AT91_PIN_PA7 (PIN_BASE + 0x00 + 7) +#define AT91_PIN_PA8 (PIN_BASE + 0x00 + 8) +#define AT91_PIN_PA9 (PIN_BASE + 0x00 + 9) +#define AT91_PIN_PA10 (PIN_BASE + 0x00 + 10) +#define AT91_PIN_PA11 (PIN_BASE + 0x00 + 11) +#define AT91_PIN_PA12 (PIN_BASE + 0x00 + 12) +#define AT91_PIN_PA13 (PIN_BASE + 0x00 + 13) +#define AT91_PIN_PA14 (PIN_BASE + 0x00 + 14) +#define AT91_PIN_PA15 (PIN_BASE + 0x00 + 15) +#define AT91_PIN_PA16 (PIN_BASE + 0x00 + 16) +#define AT91_PIN_PA17 (PIN_BASE + 0x00 + 17) +#define AT91_PIN_PA18 (PIN_BASE + 0x00 + 18) +#define AT91_PIN_PA19 (PIN_BASE + 0x00 + 19) +#define AT91_PIN_PA20 (PIN_BASE + 0x00 + 20) +#define AT91_PIN_PA21 (PIN_BASE + 0x00 + 21) +#define AT91_PIN_PA22 (PIN_BASE + 0x00 + 22) +#define AT91_PIN_PA23 (PIN_BASE + 0x00 + 23) +#define AT91_PIN_PA24 (PIN_BASE + 0x00 + 24) +#define AT91_PIN_PA25 (PIN_BASE + 0x00 + 25) +#define AT91_PIN_PA26 (PIN_BASE + 0x00 + 26) +#define AT91_PIN_PA27 (PIN_BASE + 0x00 + 27) +#define AT91_PIN_PA28 (PIN_BASE + 0x00 + 28) +#define AT91_PIN_PA29 (PIN_BASE + 0x00 + 29) +#define AT91_PIN_PA30 (PIN_BASE + 0x00 + 30) +#define AT91_PIN_PA31 (PIN_BASE + 0x00 + 31) -#define AT91_PIN_PB0 (PIN_BASE + 0x20 + 0) -#define AT91_PIN_PB1 (PIN_BASE + 0x20 + 1) -#define AT91_PIN_PB2 (PIN_BASE + 0x20 + 2) -#define AT91_PIN_PB3 (PIN_BASE + 0x20 + 3) -#define AT91_PIN_PB4 (PIN_BASE + 0x20 + 4) -#define AT91_PIN_PB5 (PIN_BASE + 0x20 + 5) -#define AT91_PIN_PB6 (PIN_BASE + 0x20 + 6) -#define AT91_PIN_PB7 (PIN_BASE + 0x20 + 7) -#define AT91_PIN_PB8 (PIN_BASE + 0x20 + 8) -#define AT91_PIN_PB9 (PIN_BASE + 0x20 + 9) -#define AT91_PIN_PB10 (PIN_BASE + 0x20 + 10) -#define AT91_PIN_PB11 (PIN_BASE + 0x20 + 11) -#define AT91_PIN_PB12 (PIN_BASE + 0x20 + 12) -#define AT91_PIN_PB13 (PIN_BASE + 0x20 + 13) -#define AT91_PIN_PB14 (PIN_BASE + 0x20 + 14) -#define AT91_PIN_PB15 (PIN_BASE + 0x20 + 15) -#define AT91_PIN_PB16 (PIN_BASE + 0x20 + 16) -#define AT91_PIN_PB17 (PIN_BASE + 0x20 + 17) -#define AT91_PIN_PB18 (PIN_BASE + 0x20 + 18) -#define AT91_PIN_PB19 (PIN_BASE + 0x20 + 19) -#define AT91_PIN_PB20 (PIN_BASE + 0x20 + 20) -#define AT91_PIN_PB21 (PIN_BASE + 0x20 + 21) -#define AT91_PIN_PB22 (PIN_BASE + 0x20 + 22) -#define AT91_PIN_PB23 (PIN_BASE + 0x20 + 23) -#define AT91_PIN_PB24 (PIN_BASE + 0x20 + 24) -#define AT91_PIN_PB25 (PIN_BASE + 0x20 + 25) -#define AT91_PIN_PB26 (PIN_BASE + 0x20 + 26) -#define AT91_PIN_PB27 (PIN_BASE + 0x20 + 27) -#define AT91_PIN_PB28 (PIN_BASE + 0x20 + 28) -#define AT91_PIN_PB29 (PIN_BASE + 0x20 + 29) -#define AT91_PIN_PB30 (PIN_BASE + 0x20 + 30) -#define AT91_PIN_PB31 (PIN_BASE + 0x20 + 31) +#define AT91_PIN_PB0 (PIN_BASE + 0x20 + 0) +#define AT91_PIN_PB1 (PIN_BASE + 0x20 + 1) +#define AT91_PIN_PB2 (PIN_BASE + 0x20 + 2) +#define AT91_PIN_PB3 (PIN_BASE + 0x20 + 3) +#define AT91_PIN_PB4 (PIN_BASE + 0x20 + 4) +#define AT91_PIN_PB5 (PIN_BASE + 0x20 + 5) +#define AT91_PIN_PB6 (PIN_BASE + 0x20 + 6) +#define AT91_PIN_PB7 (PIN_BASE + 0x20 + 7) +#define AT91_PIN_PB8 (PIN_BASE + 0x20 + 8) +#define AT91_PIN_PB9 (PIN_BASE + 0x20 + 9) +#define AT91_PIN_PB10 (PIN_BASE + 0x20 + 10) +#define AT91_PIN_PB11 (PIN_BASE + 0x20 + 11) +#define AT91_PIN_PB12 (PIN_BASE + 0x20 + 12) +#define AT91_PIN_PB13 (PIN_BASE + 0x20 + 13) +#define AT91_PIN_PB14 (PIN_BASE + 0x20 + 14) +#define AT91_PIN_PB15 (PIN_BASE + 0x20 + 15) +#define AT91_PIN_PB16 (PIN_BASE + 0x20 + 16) +#define AT91_PIN_PB17 (PIN_BASE + 0x20 + 17) +#define AT91_PIN_PB18 (PIN_BASE + 0x20 + 18) +#define AT91_PIN_PB19 (PIN_BASE + 0x20 + 19) +#define AT91_PIN_PB20 (PIN_BASE + 0x20 + 20) +#define AT91_PIN_PB21 (PIN_BASE + 0x20 + 21) +#define AT91_PIN_PB22 (PIN_BASE + 0x20 + 22) +#define AT91_PIN_PB23 (PIN_BASE + 0x20 + 23) +#define AT91_PIN_PB24 (PIN_BASE + 0x20 + 24) +#define AT91_PIN_PB25 (PIN_BASE + 0x20 + 25) +#define AT91_PIN_PB26 (PIN_BASE + 0x20 + 26) +#define AT91_PIN_PB27 (PIN_BASE + 0x20 + 27) +#define AT91_PIN_PB28 (PIN_BASE + 0x20 + 28) +#define AT91_PIN_PB29 (PIN_BASE + 0x20 + 29) +#define AT91_PIN_PB30 (PIN_BASE + 0x20 + 30) +#define AT91_PIN_PB31 (PIN_BASE + 0x20 + 31) -#define AT91_PIN_PC0 (PIN_BASE + 0x40 + 0) -#define AT91_PIN_PC1 (PIN_BASE + 0x40 + 1) -#define AT91_PIN_PC2 (PIN_BASE + 0x40 + 2) -#define AT91_PIN_PC3 (PIN_BASE + 0x40 + 3) -#define AT91_PIN_PC4 (PIN_BASE + 0x40 + 4) -#define AT91_PIN_PC5 (PIN_BASE + 0x40 + 5) -#define AT91_PIN_PC6 (PIN_BASE + 0x40 + 6) -#define AT91_PIN_PC7 (PIN_BASE + 0x40 + 7) -#define AT91_PIN_PC8 (PIN_BASE + 0x40 + 8) -#define AT91_PIN_PC9 (PIN_BASE + 0x40 + 9) -#define AT91_PIN_PC10 (PIN_BASE + 0x40 + 10) -#define AT91_PIN_PC11 (PIN_BASE + 0x40 + 11) -#define AT91_PIN_PC12 (PIN_BASE + 0x40 + 12) -#define AT91_PIN_PC13 (PIN_BASE + 0x40 + 13) -#define AT91_PIN_PC14 (PIN_BASE + 0x40 + 14) -#define AT91_PIN_PC15 (PIN_BASE + 0x40 + 15) -#define AT91_PIN_PC16 (PIN_BASE + 0x40 + 16) -#define AT91_PIN_PC17 (PIN_BASE + 0x40 + 17) -#define AT91_PIN_PC18 (PIN_BASE + 0x40 + 18) -#define AT91_PIN_PC19 (PIN_BASE + 0x40 + 19) -#define AT91_PIN_PC20 (PIN_BASE + 0x40 + 20) -#define AT91_PIN_PC21 (PIN_BASE + 0x40 + 21) -#define AT91_PIN_PC22 (PIN_BASE + 0x40 + 22) -#define AT91_PIN_PC23 (PIN_BASE + 0x40 + 23) -#define AT91_PIN_PC24 (PIN_BASE + 0x40 + 24) -#define AT91_PIN_PC25 (PIN_BASE + 0x40 + 25) -#define AT91_PIN_PC26 (PIN_BASE + 0x40 + 26) -#define AT91_PIN_PC27 (PIN_BASE + 0x40 + 27) -#define AT91_PIN_PC28 (PIN_BASE + 0x40 + 28) -#define AT91_PIN_PC29 (PIN_BASE + 0x40 + 29) -#define AT91_PIN_PC30 (PIN_BASE + 0x40 + 30) -#define AT91_PIN_PC31 (PIN_BASE + 0x40 + 31) +#define AT91_PIN_PC0 (PIN_BASE + 0x40 + 0) +#define AT91_PIN_PC1 (PIN_BASE + 0x40 + 1) +#define AT91_PIN_PC2 (PIN_BASE + 0x40 + 2) +#define AT91_PIN_PC3 (PIN_BASE + 0x40 + 3) +#define AT91_PIN_PC4 (PIN_BASE + 0x40 + 4) +#define AT91_PIN_PC5 (PIN_BASE + 0x40 + 5) +#define AT91_PIN_PC6 (PIN_BASE + 0x40 + 6) +#define AT91_PIN_PC7 (PIN_BASE + 0x40 + 7) +#define AT91_PIN_PC8 (PIN_BASE + 0x40 + 8) +#define AT91_PIN_PC9 (PIN_BASE + 0x40 + 9) +#define AT91_PIN_PC10 (PIN_BASE + 0x40 + 10) +#define AT91_PIN_PC11 (PIN_BASE + 0x40 + 11) +#define AT91_PIN_PC12 (PIN_BASE + 0x40 + 12) +#define AT91_PIN_PC13 (PIN_BASE + 0x40 + 13) +#define AT91_PIN_PC14 (PIN_BASE + 0x40 + 14) +#define AT91_PIN_PC15 (PIN_BASE + 0x40 + 15) +#define AT91_PIN_PC16 (PIN_BASE + 0x40 + 16) +#define AT91_PIN_PC17 (PIN_BASE + 0x40 + 17) +#define AT91_PIN_PC18 (PIN_BASE + 0x40 + 18) +#define AT91_PIN_PC19 (PIN_BASE + 0x40 + 19) +#define AT91_PIN_PC20 (PIN_BASE + 0x40 + 20) +#define AT91_PIN_PC21 (PIN_BASE + 0x40 + 21) +#define AT91_PIN_PC22 (PIN_BASE + 0x40 + 22) +#define AT91_PIN_PC23 (PIN_BASE + 0x40 + 23) +#define AT91_PIN_PC24 (PIN_BASE + 0x40 + 24) +#define AT91_PIN_PC25 (PIN_BASE + 0x40 + 25) +#define AT91_PIN_PC26 (PIN_BASE + 0x40 + 26) +#define AT91_PIN_PC27 (PIN_BASE + 0x40 + 27) +#define AT91_PIN_PC28 (PIN_BASE + 0x40 + 28) +#define AT91_PIN_PC29 (PIN_BASE + 0x40 + 29) +#define AT91_PIN_PC30 (PIN_BASE + 0x40 + 30) +#define AT91_PIN_PC31 (PIN_BASE + 0x40 + 31) rt_inline rt_uint32_t gpio_to_irq(rt_uint32_t gpio) { - return gpio; + return gpio; } #endif diff --git a/bsp/at91sam9260/platform/interrupt.c b/bsp/at91sam9260/platform/interrupt.c index 0708460578..7c40ffbdad 100644 --- a/bsp/at91sam9260/platform/interrupt.c +++ b/bsp/at91sam9260/platform/interrupt.c @@ -1,21 +1,7 @@ /* - * File : interrupt.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -189,7 +175,7 @@ static void at91_gpio_irq_init() rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, name[i]); irq_desc[idx].counter = 0; #endif - idx++; + idx++; } rt_hw_interrupt_umask(AT91SAM9260_ID_PIOA); @@ -322,7 +308,7 @@ void rt_hw_interrupt_umask(int irq) * @param name the interrupt name * @return old handler */ -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, void *param, const char *name) { rt_isr_handler_t old_handler = RT_NULL; @@ -336,7 +322,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, irq_desc[vector].param = param; #ifdef RT_USING_INTERRUPT_INFO rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name); - irq_desc[vector].counter = 0; + irq_desc[vector].counter = 0; #endif } } @@ -414,16 +400,16 @@ void rt_hw_interrupt_ack(rt_uint32_t fiq_irq, rt_uint32_t id) #ifdef RT_USING_INTERRUPT_INFO void list_irq(void) { - int irq; + int irq; - rt_kprintf("number\tcount\tname\n"); - for (irq = 0; irq < MAX_HANDLERS; irq++) - { - if (rt_strncmp(irq_desc[irq].name, "default", sizeof("default"))) - { - rt_kprintf("%02ld: %10ld %s\n", irq, irq_desc[irq].counter, irq_desc[irq].name); - } - } + rt_kprintf("number\tcount\tname\n"); + for (irq = 0; irq < MAX_HANDLERS; irq++) + { + if (rt_strncmp(irq_desc[irq].name, "default", sizeof("default"))) + { + rt_kprintf("%02ld: %10ld %s\n", irq, irq_desc[irq].counter, irq_desc[irq].name); + } + } } #include diff --git a/bsp/at91sam9260/platform/interrupt.h b/bsp/at91sam9260/platform/interrupt.h index 7780e7a3a8..0375164e00 100644 --- a/bsp/at91sam9260/platform/interrupt.h +++ b/bsp/at91sam9260/platform/interrupt.h @@ -1,21 +1,7 @@ /* - * File : interrupt.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/at91sam9260/platform/io.h b/bsp/at91sam9260/platform/io.h index 5cb9cac782..3e41feee90 100644 --- a/bsp/at91sam9260/platform/io.h +++ b/bsp/at91sam9260/platform/io.h @@ -1,21 +1,7 @@ /* - * File : io.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -25,31 +11,31 @@ #ifndef __ASM_ARCH_IO_H #define __ASM_ARCH_IO_H -#define AT91_BASE_SYS 0xffffe800 +#define AT91_BASE_SYS 0xffffe800 -#define IO_SPACE_LIMIT 0xFFFFFFFF +#define IO_SPACE_LIMIT 0xFFFFFFFF -#define readb(a) (*(volatile unsigned char *)(a)) -#define readw(a) (*(volatile unsigned short *)(a)) -#define readl(a) (*(volatile unsigned int *)(a)) +#define readb(a) (*(volatile unsigned char *)(a)) +#define readw(a) (*(volatile unsigned short *)(a)) +#define readl(a) (*(volatile unsigned int *)(a)) -#define writeb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define writew(v,a) (*(volatile unsigned short *)(a) = (v)) -#define writel(v,a) (*(volatile unsigned int *)(a) = (v)) +#define writeb(v,a) (*(volatile unsigned char *)(a) = (v)) +#define writew(v,a) (*(volatile unsigned short *)(a) = (v)) +#define writel(v,a) (*(volatile unsigned int *)(a) = (v)) rt_inline unsigned int at91_sys_read(unsigned int reg_offset) { - unsigned int addr = AT91_BASE_SYS; + unsigned int addr = AT91_BASE_SYS; - return readl(addr + reg_offset); + return readl(addr + reg_offset); } rt_inline void at91_sys_write(unsigned int reg_offset, unsigned long value) { - unsigned int addr = AT91_BASE_SYS; + unsigned int addr = AT91_BASE_SYS; - writel(value, addr + reg_offset); + writel(value, addr + reg_offset); } diff --git a/bsp/at91sam9260/platform/irq.h b/bsp/at91sam9260/platform/irq.h index fe1fea41d0..76d4200d3b 100644 --- a/bsp/at91sam9260/platform/irq.h +++ b/bsp/at91sam9260/platform/irq.h @@ -1,27 +1,13 @@ /* - * File : irq.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2011-01-13 weety first version */ - + #ifndef __IRQ_H__ #define __IRQ_H__ @@ -32,18 +18,18 @@ extern "C" { /* * IRQ line status. * - * Bits 0-7 are reserved + * Bits 0-7 are reserved * * IRQ types */ -#define IRQ_TYPE_NONE 0x00000000 /* Default, unspecified type */ -#define IRQ_TYPE_EDGE_RISING 0x00000001 /* Edge rising type */ -#define IRQ_TYPE_EDGE_FALLING 0x00000002 /* Edge falling type */ +#define IRQ_TYPE_NONE 0x00000000 /* Default, unspecified type */ +#define IRQ_TYPE_EDGE_RISING 0x00000001 /* Edge rising type */ +#define IRQ_TYPE_EDGE_FALLING 0x00000002 /* Edge falling type */ #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) -#define IRQ_TYPE_LEVEL_HIGH 0x00000004 /* Level high type */ -#define IRQ_TYPE_LEVEL_LOW 0x00000008 /* Level low type */ -#define IRQ_TYPE_SENSE_MASK 0x0000000f /* Mask of the above */ -#define IRQ_TYPE_PROBE 0x00000010 /* Probing in progress */ +#define IRQ_TYPE_LEVEL_HIGH 0x00000004 /* Level high type */ +#define IRQ_TYPE_LEVEL_LOW 0x00000008 /* Level low type */ +#define IRQ_TYPE_SENSE_MASK 0x0000000f /* Mask of the above */ +#define IRQ_TYPE_PROBE 0x00000010 /* Probing in progress */ #ifdef __cplusplus } diff --git a/bsp/at91sam9260/platform/reset.c b/bsp/at91sam9260/platform/reset.c index 699e29efd4..4b5462a9e1 100644 --- a/bsp/at91sam9260/platform/reset.c +++ b/bsp/at91sam9260/platform/reset.c @@ -1,21 +1,7 @@ /* - * File : reset.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -33,12 +19,12 @@ void machine_reset(void) { - at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); + at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); } void machine_shutdown(void) { - at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); + at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); } #ifdef RT_USING_FINSH @@ -49,14 +35,14 @@ FINSH_FUNCTION_EXPORT_ALIAS(rt_hw_cpu_reset, reset, restart the system); #ifdef FINSH_USING_MSH int cmd_reset(int argc, char** argv) { - rt_hw_cpu_reset(); - return 0; + rt_hw_cpu_reset(); + return 0; } int cmd_shutdown(int argc, char** argv) { - rt_hw_cpu_shutdown(); - return 0; + rt_hw_cpu_shutdown(); + return 0; } FINSH_FUNCTION_EXPORT_ALIAS(cmd_reset, __cmd_reset, restart the system.); diff --git a/bsp/at91sam9260/platform/rt_low_level_init.c b/bsp/at91sam9260/platform/rt_low_level_init.c index b7bc8e0a1a..31ddf27ae6 100644 --- a/bsp/at91sam9260/platform/rt_low_level_init.c +++ b/bsp/at91sam9260/platform/rt_low_level_init.c @@ -1,29 +1,15 @@ /* - * File : rt_low_level_init.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2015-04-14 ArdaFu first version */ - + /* write register a=address, v=value */ -#define write_reg(a,v) (*(volatile unsigned int *)(a) = (v)) +#define write_reg(a,v) (*(volatile unsigned int *)(a) = (v)) /* Processor Reset */ #define AT91_RSTC_PROCRST (1 << 0) #define AT91_RSTC_PERRST (1 << 2) diff --git a/bsp/at91sam9260/platform/rt_low_level_init.h b/bsp/at91sam9260/platform/rt_low_level_init.h index 86dcfb59dc..c79adf5284 100644 --- a/bsp/at91sam9260/platform/rt_low_level_init.h +++ b/bsp/at91sam9260/platform/rt_low_level_init.h @@ -1,21 +1,7 @@ /* - * File : rt_low_level_init.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -23,7 +9,7 @@ */ #ifndef __RT_LOW_LEVEL_INIT_H__ #define __RT_LOW_LEVEL_INIT_H__ - + /*-------- Stack size of CPU modes -------------------------------------------*/ #define UND_STK_SIZE 512 #define SVC_STK_SIZE 4096 diff --git a/bsp/at91sam9260/platform/system_clock.c b/bsp/at91sam9260/platform/system_clock.c index 13f11609d2..a8f866fdd6 100644 --- a/bsp/at91sam9260/platform/system_clock.c +++ b/bsp/at91sam9260/platform/system_clock.c @@ -1,21 +1,7 @@ /* - * File : clock.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -28,270 +14,270 @@ static rt_list_t clocks; struct clk { - char name[32]; - rt_uint32_t rate_hz; - struct clk *parent; - rt_list_t node; + char name[32]; + rt_uint32_t rate_hz; + struct clk *parent; + rt_list_t node; }; static struct clk clk32k = { - "clk32k", - AT91_SLOW_CLOCK, - RT_NULL, - {RT_NULL, RT_NULL}, + "clk32k", + AT91_SLOW_CLOCK, + RT_NULL, + {RT_NULL, RT_NULL}, }; static struct clk main_clk = { - "main", - 0, - RT_NULL, - {RT_NULL, RT_NULL}, + "main", + 0, + RT_NULL, + {RT_NULL, RT_NULL}, }; static struct clk plla = { - "plla", - 0, - RT_NULL, - {RT_NULL, RT_NULL}, + "plla", + 0, + RT_NULL, + {RT_NULL, RT_NULL}, }; static struct clk mck = { - "mck", - 0, - RT_NULL, - {RT_NULL, RT_NULL}, + "mck", + 0, + RT_NULL, + {RT_NULL, RT_NULL}, }; static struct clk uhpck = { - "uhpck", - 0, - RT_NULL, - {RT_NULL, RT_NULL}, + "uhpck", + 0, + RT_NULL, + {RT_NULL, RT_NULL}, }; static struct clk pllb = { - "pllb", - 0, - &main_clk, - {RT_NULL, RT_NULL}, + "pllb", + 0, + &main_clk, + {RT_NULL, RT_NULL}, }; static struct clk udpck = { - "udpck", - 0, - &pllb, - {RT_NULL, RT_NULL}, + "udpck", + 0, + &pllb, + {RT_NULL, RT_NULL}, }; static struct clk *const standard_pmc_clocks[] = { - /* four primary clocks */ - &clk32k, - &main_clk, - &plla, + /* four primary clocks */ + &clk32k, + &main_clk, + &plla, - /* MCK */ - &mck + /* MCK */ + &mck }; /* clocks cannot be de-registered no refcounting necessary */ struct clk *clk_get(const char *id) { - struct clk *clk; - rt_list_t *list; - - for (list = (&clocks)->next; list != &clocks; list = list->next) - { - clk = (struct clk *)rt_list_entry(list, struct clk, node); - if (rt_strcmp(id, clk->name) == 0) - return clk; - } + struct clk *clk; + rt_list_t *list; - return RT_NULL; + for (list = (&clocks)->next; list != &clocks; list = list->next) + { + clk = (struct clk *)rt_list_entry(list, struct clk, node); + if (rt_strcmp(id, clk->name) == 0) + return clk; + } + + return RT_NULL; } rt_uint32_t clk_get_rate(struct clk *clk) { - rt_uint32_t flags; - rt_uint32_t rate; + rt_uint32_t flags; + rt_uint32_t rate; - for (;;) { - rate = clk->rate_hz; - if (rate || !clk->parent) - break; - clk = clk->parent; - } - return rate; + for (;;) { + rate = clk->rate_hz; + if (rate || !clk->parent) + break; + clk = clk->parent; + } + return rate; } static rt_uint32_t at91_pll_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg) { - unsigned mul, div; + unsigned mul, div; - div = reg & 0xff; - mul = (reg >> 16) & 0x7ff; - if (div && mul) { - freq /= div; - freq *= mul + 1; - } else - freq = 0; + div = reg & 0xff; + mul = (reg >> 16) & 0x7ff; + if (div && mul) { + freq /= div; + freq *= mul + 1; + } else + freq = 0; - return freq; + return freq; } static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq) { - unsigned i, div = 0, mul = 0, diff = 1 << 30; - unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00; + unsigned i, div = 0, mul = 0, diff = 1 << 30; + unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00; - /* PLL output max 240 MHz (or 180 MHz per errata) */ - if (out_freq > 240000000) - goto fail; + /* PLL output max 240 MHz (or 180 MHz per errata) */ + if (out_freq > 240000000) + goto fail; - for (i = 1; i < 256; i++) { - int diff1; - unsigned input, mul1; + for (i = 1; i < 256; i++) { + int diff1; + unsigned input, mul1; - /* - * PLL input between 1MHz and 32MHz per spec, but lower - * frequences seem necessary in some cases so allow 100K. - * Warning: some newer products need 2MHz min. - */ - input = main_freq / i; - if (input < 100000) - continue; - if (input > 32000000) - continue; + /* + * PLL input between 1MHz and 32MHz per spec, but lower + * frequences seem necessary in some cases so allow 100K. + * Warning: some newer products need 2MHz min. + */ + input = main_freq / i; + if (input < 100000) + continue; + if (input > 32000000) + continue; - mul1 = out_freq / input; - if (mul1 > 2048) - continue; - if (mul1 < 2) - goto fail; + mul1 = out_freq / input; + if (mul1 > 2048) + continue; + if (mul1 < 2) + goto fail; - diff1 = out_freq - input * mul1; - if (diff1 < 0) - diff1 = -diff1; - if (diff > diff1) { - diff = diff1; - div = i; - mul = mul1; - if (diff == 0) - break; - } - } - if (i == 256 && diff > (out_freq >> 5)) - goto fail; - return ret | ((mul - 1) << 16) | div; + diff1 = out_freq - input * mul1; + if (diff1 < 0) + diff1 = -diff1; + if (diff > diff1) { + diff = diff1; + div = i; + mul = mul1; + if (diff == 0) + break; + } + } + if (i == 256 && diff > (out_freq >> 5)) + goto fail; + return ret | ((mul - 1) << 16) | div; fail: - return 0; + return 0; } static rt_uint32_t at91_usb_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg) { - if (pll == &pllb && (reg & AT91_PMC_USB96M)) - return freq / 2; - else - return freq; + if (pll == &pllb && (reg & AT91_PMC_USB96M)) + return freq / 2; + else + return freq; } /* PLLB generated USB full speed clock init */ static void at91_pllb_usbfs_clock_init(rt_uint32_t main_clock) { - rt_uint32_t at91_pllb_usb_init; - /* - * USB clock init: choose 48 MHz PLLB value, - * disable 48MHz clock during usb peripheral suspend. - * - * REVISIT: assumes MCK doesn't derive from PLLB! - */ - uhpck.parent = &pllb; + rt_uint32_t at91_pllb_usb_init; + /* + * USB clock init: choose 48 MHz PLLB value, + * disable 48MHz clock during usb peripheral suspend. + * + * REVISIT: assumes MCK doesn't derive from PLLB! + */ + uhpck.parent = &pllb; - at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M; - pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init); - - at91_sys_write(AT91_CKGR_PLLBR, 0); + at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M; + pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init); - udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); - uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); + at91_sys_write(AT91_CKGR_PLLBR, 0); + + udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); + uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); } static struct clk *at91_css_to_clk(unsigned long css) { - switch (css) { - case AT91_PMC_CSS_SLOW: - return &clk32k; - case AT91_PMC_CSS_MAIN: - return &main_clk; - case AT91_PMC_CSS_PLLA: - return &plla; - case AT91_PMC_CSS_PLLB: - return &pllb; - } + switch (css) { + case AT91_PMC_CSS_SLOW: + return &clk32k; + case AT91_PMC_CSS_MAIN: + return &main_clk; + case AT91_PMC_CSS_PLLA: + return &plla; + case AT91_PMC_CSS_PLLB: + return &pllb; + } - return RT_NULL; + return RT_NULL; } #define false 0 #define true 1 int at91_clock_init(rt_uint32_t main_clock) { - unsigned tmp, freq, mckr; - int i; - int pll_overclock = false; + unsigned tmp, freq, mckr; + int i; + int pll_overclock = false; - /* - * When the bootloader initialized the main oscillator correctly, - * there's no problem using the cycle counter. But if it didn't, - * or when using oscillator bypass mode, we must be told the speed - * of the main clock. - */ - if (!main_clock) { - do { - tmp = at91_sys_read(AT91_CKGR_MCFR); - } while (!(tmp & AT91_PMC_MAINRDY)); - main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16); - } - main_clk.rate_hz = main_clock; + /* + * When the bootloader initialized the main oscillator correctly, + * there's no problem using the cycle counter. But if it didn't, + * or when using oscillator bypass mode, we must be told the speed + * of the main clock. + */ + if (!main_clock) { + do { + tmp = at91_sys_read(AT91_CKGR_MCFR); + } while (!(tmp & AT91_PMC_MAINRDY)); + main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16); + } + main_clk.rate_hz = main_clock; - /* report if PLLA is more than mildly overclocked */ - plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR)); - if (plla.rate_hz > 209000000) - pll_overclock = true; - if (pll_overclock) - ;//rt_kprintf("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000); + /* report if PLLA is more than mildly overclocked */ + plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR)); + if (plla.rate_hz > 209000000) + pll_overclock = true; + if (pll_overclock) + ;//rt_kprintf("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000); - at91_pllb_usbfs_clock_init(main_clock); + at91_pllb_usbfs_clock_init(main_clock); - /* - * MCK and CPU derive from one of those primary clocks. - * For now, assume this parentage won't change. - */ - mckr = at91_sys_read(AT91_PMC_MCKR); - mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS); - freq = mck.parent->rate_hz; - freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */ - - mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ + /* + * MCK and CPU derive from one of those primary clocks. + * For now, assume this parentage won't change. + */ + mckr = at91_sys_read(AT91_PMC_MCKR); + mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS); + freq = mck.parent->rate_hz; + freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */ - /* Register the PMC's standard clocks */ - rt_list_init(&clocks); - for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) - rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node); + mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ - rt_list_insert_after(&clocks, &pllb.node); - rt_list_insert_after(&clocks, &uhpck.node); - rt_list_insert_after(&clocks, &udpck.node); + /* Register the PMC's standard clocks */ + rt_list_init(&clocks); + for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) + rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node); - /* MCK and CPU clock are "always on" */ - //clk_enable(&mck); + rt_list_insert_after(&clocks, &pllb.node); + rt_list_insert_after(&clocks, &uhpck.node); + rt_list_insert_after(&clocks, &udpck.node); - /*rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n", - freq / 1000000, (unsigned) mck.rate_hz / 1000000, - (unsigned) main_clock / 1000000, - ((unsigned) main_clock % 1000000) / 1000);*///cause blocked + /* MCK and CPU clock are "always on" */ + //clk_enable(&mck); - return 0; + /*rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n", + freq / 1000000, (unsigned) mck.rate_hz / 1000000, + (unsigned) main_clock / 1000000, + ((unsigned) main_clock % 1000000) / 1000);*///cause blocked + + return 0; } /** @@ -299,6 +285,6 @@ int at91_clock_init(rt_uint32_t main_clock) */ void rt_hw_clock_init(void) { - at91_clock_init(18432000); + at91_clock_init(18432000); } diff --git a/bsp/at91sam9g45/applications/application.c b/bsp/at91sam9g45/applications/application.c index ec878faa85..6bc312b997 100644 --- a/bsp/at91sam9g45/applications/application.c +++ b/bsp/at91sam9g45/applications/application.c @@ -1,25 +1,11 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version + * Date Author Notes + * 2011-01-13 weety first version */ /** @@ -49,106 +35,106 @@ static int rt_led_app_init(void); RT_WEAK int main(void) { #ifdef RT_USING_SDIO - int timeout = 0; + int timeout = 0; #endif /* Filesystem Initialization */ #ifdef RT_USING_DFS - { + { #if defined(RT_USING_DFS_ROMFS) - if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0) - { - rt_kprintf("ROM File System initialized!\n"); - } - else - rt_kprintf("ROM File System initialzation failed!\n"); + if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0) + { + rt_kprintf("ROM File System initialized!\n"); + } + else + rt_kprintf("ROM File System initialzation failed!\n"); #endif #if defined(RT_USING_DFS_UFFS) - { - /* mount flash device as flash directory */ - if(dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0) - rt_kprintf("UFFS File System initialized!\n"); - else - rt_kprintf("UFFS File System initialzation failed!\n"); - } + { + /* mount flash device as flash directory */ + if(dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0) + rt_kprintf("UFFS File System initialized!\n"); + else + rt_kprintf("UFFS File System initialzation failed!\n"); + } #endif #ifdef RT_USING_SDIO - timeout = 0; - while ((rt_device_find("sd0") == RT_NULL) && (timeout++ < RT_TICK_PER_SECOND*2)) - { - rt_thread_delay(1); - } + timeout = 0; + while ((rt_device_find("sd0") == RT_NULL) && (timeout++ < RT_TICK_PER_SECOND*2)) + { + rt_thread_delay(1); + } - if (timeout < RT_TICK_PER_SECOND*2) - { - /* mount sd card fat partition 1 as root directory */ - if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) - { - rt_kprintf("File System initialized!\n"); - } - else - rt_kprintf("File System initialzation failed!%d\n", rt_get_errno()); - } - else - { - rt_kprintf("No SD card found.\n"); - } + if (timeout < RT_TICK_PER_SECOND*2) + { + /* mount sd card fat partition 1 as root directory */ + if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) + { + rt_kprintf("File System initialized!\n"); + } + else + rt_kprintf("File System initialzation failed!%d\n", rt_get_errno()); + } + else + { + rt_kprintf("No SD card found.\n"); + } #endif - } + } #endif - rt_led_app_init(); + rt_led_app_init(); } #ifdef RT_USING_LED void rt_led_thread_entry(void* parameter) { - rt_uint8_t cnt = 0; - led_init(); - while(1) - { - /* light on leds for one second */ - rt_thread_delay(40); - cnt++; - if (cnt&0x01) - led_on(1); - else - led_off(1); - if (cnt&0x02) - led_on(2); - else - led_off(2); - if (cnt&0x04) - led_on(3); - else - led_off(3); - - } + rt_uint8_t cnt = 0; + led_init(); + while(1) + { + /* light on leds for one second */ + rt_thread_delay(40); + cnt++; + if (cnt&0x01) + led_on(1); + else + led_off(1); + if (cnt&0x02) + led_on(2); + else + led_off(2); + if (cnt&0x04) + led_on(3); + else + led_off(3); + + } } #endif static int rt_led_app_init(void) { #ifdef RT_USING_LED - rt_thread_t led_thread; + rt_thread_t led_thread; #if (RT_THREAD_PRIORITY_MAX == 32) - led_thread = rt_thread_create("led", - rt_led_thread_entry, RT_NULL, - 512, 20, 20); + led_thread = rt_thread_create("led", + rt_led_thread_entry, RT_NULL, + 512, 20, 20); #else - led_thread = rt_thread_create("led", - rt_led_thread_entry, RT_NULL, - 512, 200, 20); + led_thread = rt_thread_create("led", + rt_led_thread_entry, RT_NULL, + 512, 200, 20); #endif - if(led_thread != RT_NULL) - rt_thread_startup(led_thread); + if(led_thread != RT_NULL) + rt_thread_startup(led_thread); #endif - return 0; + return 0; } /* NFSv3 Initialization */ @@ -156,14 +142,14 @@ static int rt_led_app_init(void) #include void nfs_start(void) { - nfs_init(); + nfs_init(); - if (dfs_mount(RT_NULL, "/nfs", "nfs", 0, RT_NFS_HOST_EXPORT) == 0) - { - rt_kprintf("NFSv3 File System initialized!\n"); - } - else - rt_kprintf("NFSv3 File System initialzation failed!\n"); + if (dfs_mount(RT_NULL, "/nfs", "nfs", 0, RT_NFS_HOST_EXPORT) == 0) + { + rt_kprintf("NFSv3 File System initialized!\n"); + } + else + rt_kprintf("NFSv3 File System initialzation failed!\n"); } #include "finsh.h" diff --git a/bsp/at91sam9g45/drivers/at91_i2c_gpio.c b/bsp/at91sam9g45/drivers/at91_i2c_gpio.c index 91ca646c7a..d229cbd1bb 100644 --- a/bsp/at91sam9g45/drivers/at91_i2c_gpio.c +++ b/bsp/at91sam9g45/drivers/at91_i2c_gpio.c @@ -1,25 +1,11 @@ /* - * File : at91_i2c_gpio.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2012-04-25 weety first version + * Date Author Notes + * 2012-04-25 weety first version */ #include @@ -29,101 +15,101 @@ static void at91_i2c_gpio_init() { - AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOA; //enable PIOA clock - AT91C_BASE_PIOA->PIO_PUER = (1 << 23); - AT91C_BASE_PIOA->PIO_PER = (1 << 23); - AT91C_BASE_PIOA->PIO_MDER = (1 << 23); - AT91C_BASE_PIOA->PIO_PUER = (1 << 24); - AT91C_BASE_PIOA->PIO_PER = (1 << 24); - AT91C_BASE_PIOA->PIO_MDER = (1 << 24); + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOA; //enable PIOA clock + AT91C_BASE_PIOA->PIO_PUER = (1 << 23); + AT91C_BASE_PIOA->PIO_PER = (1 << 23); + AT91C_BASE_PIOA->PIO_MDER = (1 << 23); + AT91C_BASE_PIOA->PIO_PUER = (1 << 24); + AT91C_BASE_PIOA->PIO_PER = (1 << 24); + AT91C_BASE_PIOA->PIO_MDER = (1 << 24); - AT91C_BASE_PIOA->PIO_OER = (1 << 23); - AT91C_BASE_PIOA->PIO_OER = (1 << 24); + AT91C_BASE_PIOA->PIO_OER = (1 << 23); + AT91C_BASE_PIOA->PIO_OER = (1 << 24); - AT91C_BASE_PIOA->PIO_SODR = (1 << 23); - AT91C_BASE_PIOA->PIO_SODR = (1 << 24); + AT91C_BASE_PIOA->PIO_SODR = (1 << 23); + AT91C_BASE_PIOA->PIO_SODR = (1 << 24); } static void at91_set_sda(void *data, rt_int32_t state) { - if (state) - { - AT91C_BASE_PIOA->PIO_SODR = (1 << 23); - } - else - { - AT91C_BASE_PIOA->PIO_CODR = (1 << 23); - } + if (state) + { + AT91C_BASE_PIOA->PIO_SODR = (1 << 23); + } + else + { + AT91C_BASE_PIOA->PIO_CODR = (1 << 23); + } } static void at91_set_scl(void *data, rt_int32_t state) { - if (state) - { - AT91C_BASE_PIOA->PIO_SODR = (1 << 24); - } - else - { - AT91C_BASE_PIOA->PIO_CODR = (1 << 24); - } + if (state) + { + AT91C_BASE_PIOA->PIO_SODR = (1 << 24); + } + else + { + AT91C_BASE_PIOA->PIO_CODR = (1 << 24); + } } static rt_int32_t at91_get_sda(void *data) { - return AT91C_BASE_PIOA->PIO_PDSR & (1 << 23); + return AT91C_BASE_PIOA->PIO_PDSR & (1 << 23); } static rt_int32_t at91_get_scl(void *data) { - return AT91C_BASE_PIOA->PIO_PDSR & (1 << 24); + return AT91C_BASE_PIOA->PIO_PDSR & (1 << 24); } static void at91_udelay (rt_uint32_t us) { - rt_int32_t i; - for (; us > 0; us--) - { - i = 50000; - while(i > 0) - { - i--; - } - } + rt_int32_t i; + for (; us > 0; us--) + { + i = 50000; + while(i > 0) + { + i--; + } + } } static const struct rt_i2c_bit_ops bit_ops = { - RT_NULL, - at91_set_sda, - at91_set_scl, - at91_get_sda, - at91_get_scl, - - at91_udelay, + RT_NULL, + at91_set_sda, + at91_set_scl, + at91_get_sda, + at91_get_scl, - 5, - 100 + at91_udelay, + + 5, + 100 }; int at91_i2c_init(void) { - struct rt_i2c_bus_device *bus; + struct rt_i2c_bus_device *bus; - bus = rt_malloc(sizeof(struct rt_i2c_bus_device)); - if (bus == RT_NULL) - { - rt_kprintf("rt_malloc failed\n"); - return -RT_ENOMEM; - } - - rt_memset((void *)bus, 0, sizeof(struct rt_i2c_bus_device)); + bus = rt_malloc(sizeof(struct rt_i2c_bus_device)); + if (bus == RT_NULL) + { + rt_kprintf("rt_malloc failed\n"); + return -RT_ENOMEM; + } - bus->priv = (void *)&bit_ops; + rt_memset((void *)bus, 0, sizeof(struct rt_i2c_bus_device)); - at91_i2c_gpio_init(); + bus->priv = (void *)&bit_ops; - rt_i2c_bit_add_bus(bus, "i2c0"); + at91_i2c_gpio_init(); - return 0; + rt_i2c_bit_add_bus(bus, "i2c0"); + + return 0; } INIT_DEVICE_EXPORT(at91_i2c_init); diff --git a/bsp/at91sam9g45/drivers/at91_mci.c b/bsp/at91sam9g45/drivers/at91_mci.c index 0ad5590df6..55c698832f 100644 --- a/bsp/at91sam9g45/drivers/at91_mci.c +++ b/bsp/at91sam9g45/drivers/at91_mci.c @@ -1,25 +1,11 @@ /* - * File : at91_mci.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-07-25 weety first version + * Date Author Notes + * 2011-07-25 weety first version */ #include @@ -37,32 +23,32 @@ #define mci_dbg(fmt, ...) #endif -#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<31)) +#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<31)) extern void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size); extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size); -#define AT91C_MCI_ERRORS (AT91C_MCI_RINDE | AT91C_MCI_RDIRE | AT91C_MCI_RCRCE \ - | AT91C_MCI_RENDE | AT91C_MCI_RTOE | AT91C_MCI_DCRCE \ - | AT91C_MCI_DTOE | AT91C_MCI_OVRE | AT91C_MCI_UNRE) +#define AT91C_MCI_ERRORS (AT91C_MCI_RINDE | AT91C_MCI_RDIRE | AT91C_MCI_RCRCE \ + | AT91C_MCI_RENDE | AT91C_MCI_RTOE | AT91C_MCI_DCRCE \ + | AT91C_MCI_DTOE | AT91C_MCI_OVRE | AT91C_MCI_UNRE) -#define at91_mci_read(reg) readl(AT91C_BASE_MCI + (reg)) -#define at91_mci_write(reg, val) writel((val), AT91C_BASE_MCI + (reg)) +#define at91_mci_read(reg) readl(AT91C_BASE_MCI + (reg)) +#define at91_mci_write(reg, val) writel((val), AT91C_BASE_MCI + (reg)) -#define REQ_ST_INIT (1U << 0) -#define REQ_ST_CMD (1U << 1) -#define REQ_ST_STOP (1U << 2) +#define REQ_ST_INIT (1U << 0) +#define REQ_ST_CMD (1U << 1) +#define REQ_ST_STOP (1U << 2) struct at91_mci { - struct rt_mmcsd_host *host; - struct rt_mmcsd_req *req; - struct rt_mmcsd_cmd *cmd; - struct rt_timer timer; - //struct rt_semaphore sem_ack; - rt_uint32_t *buf; - rt_uint32_t current_status; + struct rt_mmcsd_host *host; + struct rt_mmcsd_req *req; + struct rt_mmcsd_cmd *cmd; + struct rt_timer timer; + //struct rt_semaphore sem_ack; + rt_uint32_t *buf; + rt_uint32_t current_status; }; /* @@ -70,36 +56,36 @@ struct at91_mci { */ static void at91_reset_host() { - rt_uint32_t mr; - rt_uint32_t sdcr; - rt_uint32_t dtor; - rt_uint32_t imr; - rt_uint32_t level; + rt_uint32_t mr; + rt_uint32_t sdcr; + rt_uint32_t dtor; + rt_uint32_t imr; + rt_uint32_t level; - level = rt_hw_interrupt_disable(); + level = rt_hw_interrupt_disable(); - imr = at91_mci_read(AT91C_MCI_IMR); + imr = at91_mci_read(AT91C_MCI_IMR); - at91_mci_write(AT91C_MCI_IDR, 0xffffffff); + at91_mci_write(AT91C_MCI_IDR, 0xffffffff); - /* save current state */ - mr = at91_mci_read(AT91C_MCI_MR) & 0x7fff; - sdcr = at91_mci_read(AT91C_MCI_SDCR); - dtor = at91_mci_read(AT91C_MCI_DTOR); + /* save current state */ + mr = at91_mci_read(AT91C_MCI_MR) & 0x7fff; + sdcr = at91_mci_read(AT91C_MCI_SDCR); + dtor = at91_mci_read(AT91C_MCI_DTOR); - /* reset the controller */ - at91_mci_write(AT91C_MCI_CR, AT91C_MCI_MCIDIS | AT91C_MCI_SWRST); + /* reset the controller */ + at91_mci_write(AT91C_MCI_CR, AT91C_MCI_MCIDIS | AT91C_MCI_SWRST); - /* restore state */ - at91_mci_write(AT91C_MCI_CR, AT91C_MCI_MCIEN); - at91_mci_write(AT91C_MCI_MR, mr); - at91_mci_write(AT91C_MCI_SDCR, sdcr); - at91_mci_write(AT91C_MCI_DTOR, dtor); - at91_mci_write(AT91C_MCI_IER, imr); + /* restore state */ + at91_mci_write(AT91C_MCI_CR, AT91C_MCI_MCIEN); + at91_mci_write(AT91C_MCI_MR, mr); + at91_mci_write(AT91C_MCI_SDCR, sdcr); + at91_mci_write(AT91C_MCI_DTOR, dtor); + at91_mci_write(AT91C_MCI_IER, imr); - /* make sure sdio interrupts will fire */ - at91_mci_read(AT91C_MCI_SR); - rt_hw_interrupt_enable(level); + /* make sure sdio interrupts will fire */ + at91_mci_read(AT91C_MCI_SR); + rt_hw_interrupt_enable(level); } @@ -109,19 +95,19 @@ static void at91_reset_host() */ static void at91_mci_enable() { - rt_uint32_t mr; + rt_uint32_t mr; - at91_mci_write(AT91C_MCI_CR, AT91C_MCI_MCIEN); - at91_mci_write(AT91C_MCI_IDR, 0xffffffff); - at91_mci_write(AT91C_MCI_DTOR, AT91C_MCI_DTOMUL_1M | AT91C_MCI_DTOCYC); - mr = AT91C_MCI_PDCMODE | 0x34a; + at91_mci_write(AT91C_MCI_CR, AT91C_MCI_MCIEN); + at91_mci_write(AT91C_MCI_IDR, 0xffffffff); + at91_mci_write(AT91C_MCI_DTOR, AT91C_MCI_DTOMUL_1M | AT91C_MCI_DTOCYC); + mr = AT91C_MCI_PDCMODE | 0x34a; - mr |= AT91C_MCI_RDPROOF | AT91C_MCI_WRPROOF; + mr |= AT91C_MCI_RDPROOF | AT91C_MCI_WRPROOF; - at91_mci_write(AT91C_MCI_MR, mr); + at91_mci_write(AT91C_MCI_MR, mr); - /* use Slot A or B (only one at same time) */ - at91_mci_write(AT91C_MCI_SDCR, 1); /* use slot b */ + /* use Slot A or B (only one at same time) */ + at91_mci_write(AT91C_MCI_SDCR, 1); /* use slot b */ } /* @@ -129,39 +115,39 @@ static void at91_mci_enable() */ static void at91_mci_disable() { - at91_mci_write(AT91C_MCI_CR, AT91C_MCI_MCIDIS | AT91C_MCI_SWRST); + at91_mci_write(AT91C_MCI_CR, AT91C_MCI_MCIDIS | AT91C_MCI_SWRST); } static void at91_timeout_timer(void *data) { - struct at91_mci *mci; + struct at91_mci *mci; - mci = (struct at91_mci *)data; + mci = (struct at91_mci *)data; - if (mci->req) - { - rt_kprintf("Timeout waiting end of packet\n"); + if (mci->req) + { + rt_kprintf("Timeout waiting end of packet\n"); - if (mci->current_status == REQ_ST_CMD) - { - if (mci->req->cmd && mci->req->data) - { - mci->req->data->err = -RT_ETIMEOUT; - } - else - { - if (mci->req->cmd) - mci->req->cmd->err = -RT_ETIMEOUT; - } - } - else if (mci->current_status == REQ_ST_STOP) - { - mci->req->stop->err = -RT_ETIMEOUT; - } + if (mci->current_status == REQ_ST_CMD) + { + if (mci->req->cmd && mci->req->data) + { + mci->req->data->err = -RT_ETIMEOUT; + } + else + { + if (mci->req->cmd) + mci->req->cmd->err = -RT_ETIMEOUT; + } + } + else if (mci->current_status == REQ_ST_STOP) + { + mci->req->stop->err = -RT_ETIMEOUT; + } - at91_reset_host(); - mmcsd_req_complete(mci->host); - } + at91_reset_host(); + mmcsd_req_complete(mci->host); + } } /* @@ -169,62 +155,62 @@ static void at91_timeout_timer(void *data) */ static void at91_mci_init_dma_read(struct at91_mci *mci) { - rt_uint8_t i; - struct rt_mmcsd_cmd *cmd; - struct rt_mmcsd_data *data; - rt_uint32_t length; + rt_uint8_t i; + struct rt_mmcsd_cmd *cmd; + struct rt_mmcsd_data *data; + rt_uint32_t length; - mci_dbg("pre dma read\n"); + mci_dbg("pre dma read\n"); - cmd = mci->cmd; - if (!cmd) - { - mci_dbg("no command\n"); - return; - } + cmd = mci->cmd; + if (!cmd) + { + mci_dbg("no command\n"); + return; + } - data = cmd->data; - if (!data) - { - mci_dbg("no data\n"); - return; - } + data = cmd->data; + if (!data) + { + mci_dbg("no data\n"); + return; + } - for (i = 0; i < 1; i++) - { - /* Check to see if this needs filling */ - if (i == 0) - { - if (at91_mci_read(AT91C_PDC_RCR) != 0) - { - mci_dbg("Transfer active in current\n"); - continue; - } - } - else { - if (at91_mci_read(AT91C_PDC_RNCR) != 0) - { - mci_dbg("Transfer active in next\n"); - continue; - } - } + for (i = 0; i < 1; i++) + { + /* Check to see if this needs filling */ + if (i == 0) + { + if (at91_mci_read(AT91C_PDC_RCR) != 0) + { + mci_dbg("Transfer active in current\n"); + continue; + } + } + else { + if (at91_mci_read(AT91C_PDC_RNCR) != 0) + { + mci_dbg("Transfer active in next\n"); + continue; + } + } - length = data->blksize * data->blks; - mci_dbg("dma address = %08X, length = %d\n", data->buf, length); + length = data->blksize * data->blks; + mci_dbg("dma address = %08X, length = %d\n", data->buf, length); - if (i == 0) - { - at91_mci_write(AT91C_PDC_RPR, (rt_uint32_t)(data->buf)); - at91_mci_write(AT91C_PDC_RCR, (data->blksize & 0x3) ? length : length / 4); - } - else - { - at91_mci_write(AT91C_PDC_RNPR, (rt_uint32_t)(data->buf)); - at91_mci_write(AT91C_PDC_RNCR, (data->blksize & 0x3) ? length : length / 4); - } - } + if (i == 0) + { + at91_mci_write(AT91C_PDC_RPR, (rt_uint32_t)(data->buf)); + at91_mci_write(AT91C_PDC_RCR, (data->blksize & 0x3) ? length : length / 4); + } + else + { + at91_mci_write(AT91C_PDC_RNPR, (rt_uint32_t)(data->buf)); + at91_mci_write(AT91C_PDC_RNCR, (data->blksize & 0x3) ? length : length / 4); + } + } - mci_dbg("pre dma read done\n"); + mci_dbg("pre dma read done\n"); } /* @@ -232,185 +218,185 @@ static void at91_mci_init_dma_read(struct at91_mci *mci) */ static void at91_mci_send_command(struct at91_mci *mci, struct rt_mmcsd_cmd *cmd) { - rt_uint32_t cmdr, mr; - rt_uint32_t block_length; - struct rt_mmcsd_data *data = cmd->data; - struct rt_mmcsd_host *host = mci->host; + rt_uint32_t cmdr, mr; + rt_uint32_t block_length; + struct rt_mmcsd_data *data = cmd->data; + struct rt_mmcsd_host *host = mci->host; - rt_uint32_t blocks; - rt_uint32_t ier = 0; - rt_uint32_t length; + rt_uint32_t blocks; + rt_uint32_t ier = 0; + rt_uint32_t length; - mci->cmd = cmd; + mci->cmd = cmd; - /* Needed for leaving busy state before CMD1 */ - if ((at91_mci_read(AT91C_MCI_SR) & AT91C_MCI_RTOE) && (cmd->cmd_code == 1)) - { - mci_dbg("Clearing timeout\n"); - at91_mci_write(AT91C_MCI_ARGR, 0); - at91_mci_write(AT91C_MCI_CMDR, AT91C_MCI_OPDCMD); - while (!(at91_mci_read(AT91C_MCI_SR) & AT91C_MCI_CMDRDY)) - { - /* spin */ - mci_dbg("Clearing: SR = %08X\n", at91_mci_read(AT91C_MCI_SR)); - } - } + /* Needed for leaving busy state before CMD1 */ + if ((at91_mci_read(AT91C_MCI_SR) & AT91C_MCI_RTOE) && (cmd->cmd_code == 1)) + { + mci_dbg("Clearing timeout\n"); + at91_mci_write(AT91C_MCI_ARGR, 0); + at91_mci_write(AT91C_MCI_CMDR, AT91C_MCI_OPDCMD); + while (!(at91_mci_read(AT91C_MCI_SR) & AT91C_MCI_CMDRDY)) + { + /* spin */ + mci_dbg("Clearing: SR = %08X\n", at91_mci_read(AT91C_MCI_SR)); + } + } - cmdr = cmd->cmd_code; + cmdr = cmd->cmd_code; - if (resp_type(cmd) == RESP_NONE) - cmdr |= AT91C_MCI_RSPTYP_NONE; - else - { - /* if a response is expected then allow maximum response latancy */ - cmdr |= AT91C_MCI_MAXLAT; - /* set 136 bit response for R2, 48 bit response otherwise */ - if (resp_type(cmd) == RESP_R2) - cmdr |= AT91C_MCI_RSPTYP_136; - else - cmdr |= AT91C_MCI_RSPTYP_48; - } + if (resp_type(cmd) == RESP_NONE) + cmdr |= AT91C_MCI_RSPTYP_NONE; + else + { + /* if a response is expected then allow maximum response latancy */ + cmdr |= AT91C_MCI_MAXLAT; + /* set 136 bit response for R2, 48 bit response otherwise */ + if (resp_type(cmd) == RESP_R2) + cmdr |= AT91C_MCI_RSPTYP_136; + else + cmdr |= AT91C_MCI_RSPTYP_48; + } - if (data) - { + if (data) + { - block_length = data->blksize; - blocks = data->blks; + block_length = data->blksize; + blocks = data->blks; - /* always set data start - also set direction flag for read */ - if (data->flags & DATA_DIR_READ) - cmdr |= (AT91C_MCI_TRDIR | AT91C_MCI_TRCMD_START); - else if (data->flags & DATA_DIR_WRITE) - cmdr |= AT91C_MCI_TRCMD_START; + /* always set data start - also set direction flag for read */ + if (data->flags & DATA_DIR_READ) + cmdr |= (AT91C_MCI_TRDIR | AT91C_MCI_TRCMD_START); + else if (data->flags & DATA_DIR_WRITE) + cmdr |= AT91C_MCI_TRCMD_START; - if (data->flags & DATA_STREAM) - cmdr |= AT91C_MCI_TRTYP_STREAM; - if (data->blks > 1) - cmdr |= AT91C_MCI_TRTYP_MULTIPLE; - } - else - { - block_length = 0; - blocks = 0; - } + if (data->flags & DATA_STREAM) + cmdr |= AT91C_MCI_TRTYP_STREAM; + if (data->blks > 1) + cmdr |= AT91C_MCI_TRTYP_MULTIPLE; + } + else + { + block_length = 0; + blocks = 0; + } - /*if (cmd->cmd_code == GO_IDLE_STATE) - { - cmdr |= AT91C_MCI_SPCMD_INIT; - }*/ + /*if (cmd->cmd_code == GO_IDLE_STATE) + { + cmdr |= AT91C_MCI_SPCMD_INIT; + }*/ - if (cmd->cmd_code == STOP_TRANSMISSION) - cmdr |= AT91C_MCI_TRCMD_STOP; + if (cmd->cmd_code == STOP_TRANSMISSION) + cmdr |= AT91C_MCI_TRCMD_STOP; - if (host->io_cfg.bus_mode == MMCSD_BUSMODE_OPENDRAIN) - cmdr |= AT91C_MCI_OPDCMD; + if (host->io_cfg.bus_mode == MMCSD_BUSMODE_OPENDRAIN) + cmdr |= AT91C_MCI_OPDCMD; - /* - * Set the arguments and send the command - */ - mci_dbg("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08X)\n", - cmd->cmd_code, cmdr, cmd->arg, blocks, block_length, at91_mci_read(AT91C_MCI_MR)); + /* + * Set the arguments and send the command + */ + mci_dbg("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08X)\n", + cmd->cmd_code, cmdr, cmd->arg, blocks, block_length, at91_mci_read(AT91C_MCI_MR)); - if (!data) - { - at91_mci_write(AT91C_PDC_PTCR, AT91C_PDC_TXTDIS | AT91C_PDC_RXTDIS); - at91_mci_write(AT91C_PDC_RPR, 0); - at91_mci_write(AT91C_PDC_RCR, 0); - at91_mci_write(AT91C_PDC_RNPR, 0); - at91_mci_write(AT91C_PDC_RNCR, 0); - at91_mci_write(AT91C_PDC_TPR, 0); - at91_mci_write(AT91C_PDC_TCR, 0); - at91_mci_write(AT91C_PDC_TNPR, 0); - at91_mci_write(AT91C_PDC_TNCR, 0); - ier = AT91C_MCI_CMDRDY; - } - else - { - /* zero block length and PDC mode */ - mr = at91_mci_read(AT91C_MCI_MR) & 0x5fff; - mr |= (data->blksize & 0x3) ? AT91C_MCI_PDCFBYTE : 0; - mr |= (block_length << 16); - mr |= AT91C_MCI_PDCMODE; - at91_mci_write(AT91C_MCI_MR, mr); + if (!data) + { + at91_mci_write(AT91C_PDC_PTCR, AT91C_PDC_TXTDIS | AT91C_PDC_RXTDIS); + at91_mci_write(AT91C_PDC_RPR, 0); + at91_mci_write(AT91C_PDC_RCR, 0); + at91_mci_write(AT91C_PDC_RNPR, 0); + at91_mci_write(AT91C_PDC_RNCR, 0); + at91_mci_write(AT91C_PDC_TPR, 0); + at91_mci_write(AT91C_PDC_TCR, 0); + at91_mci_write(AT91C_PDC_TNPR, 0); + at91_mci_write(AT91C_PDC_TNCR, 0); + ier = AT91C_MCI_CMDRDY; + } + else + { + /* zero block length and PDC mode */ + mr = at91_mci_read(AT91C_MCI_MR) & 0x5fff; + mr |= (data->blksize & 0x3) ? AT91C_MCI_PDCFBYTE : 0; + mr |= (block_length << 16); + mr |= AT91C_MCI_PDCMODE; + at91_mci_write(AT91C_MCI_MR, mr); - at91_mci_write(AT91C_MCI_BLKR, - AT91C_MCI_BLKR_BCNT(blocks) | - AT91C_MCI_BLKR_BLKLEN(block_length)); + at91_mci_write(AT91C_MCI_BLKR, + AT91C_MCI_BLKR_BCNT(blocks) | + AT91C_MCI_BLKR_BLKLEN(block_length)); - /* - * Disable the PDC controller - */ - at91_mci_write(AT91C_PDC_PTCR, AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS); + /* + * Disable the PDC controller + */ + at91_mci_write(AT91C_PDC_PTCR, AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS); - if (cmdr & AT91C_MCI_TRCMD_START) - { - if (cmdr & AT91C_MCI_TRDIR) - { - /* - * Handle a read - */ + if (cmdr & AT91C_MCI_TRCMD_START) + { + if (cmdr & AT91C_MCI_TRDIR) + { + /* + * Handle a read + */ - mmu_invalidate_dcache((rt_uint32_t)data->buf, data->blksize*data->blks); - at91_mci_init_dma_read(mci); - ier = AT91C_MCI_ENDRX /* | AT91C_MCI_RXBUFF */; - } - else - { - /* - * Handle a write - */ - length = block_length * blocks; - /* - * at91mci MCI1 rev2xx Data Write Operation and - * number of bytes erratum - */ - if (length < 12) - { - length = 12; - mci->buf = rt_malloc(length); - if (!mci->buf) - { - rt_kprintf("rt alloc tx buffer failed\n"); - cmd->err = -RT_ENOMEM; - mmcsd_req_complete(mci->host); - return; - } - rt_memset(mci->buf, 0, 12); - rt_memcpy(mci->buf, data->buf, length); - mmu_clean_dcache((rt_uint32_t)mci->buf, length); - at91_mci_write(AT91C_PDC_TPR, (rt_uint32_t)(mci->buf)); - at91_mci_write(AT91C_PDC_TCR, (data->blksize & 0x3) ? - length : length / 4); - } - else - { - mmu_clean_dcache((rt_uint32_t)data->buf, data->blksize*data->blks); - at91_mci_write(AT91C_PDC_TPR, (rt_uint32_t)(data->buf)); - at91_mci_write(AT91C_PDC_TCR, (data->blksize & 0x3) ? - length : length / 4); - } - mci_dbg("Transmitting %d bytes\n", length); - ier = AT91C_MCI_CMDRDY; - } - } - } + mmu_invalidate_dcache((rt_uint32_t)data->buf, data->blksize*data->blks); + at91_mci_init_dma_read(mci); + ier = AT91C_MCI_ENDRX /* | AT91C_MCI_RXBUFF */; + } + else + { + /* + * Handle a write + */ + length = block_length * blocks; + /* + * at91mci MCI1 rev2xx Data Write Operation and + * number of bytes erratum + */ + if (length < 12) + { + length = 12; + mci->buf = rt_malloc(length); + if (!mci->buf) + { + rt_kprintf("rt alloc tx buffer failed\n"); + cmd->err = -RT_ENOMEM; + mmcsd_req_complete(mci->host); + return; + } + rt_memset(mci->buf, 0, 12); + rt_memcpy(mci->buf, data->buf, length); + mmu_clean_dcache((rt_uint32_t)mci->buf, length); + at91_mci_write(AT91C_PDC_TPR, (rt_uint32_t)(mci->buf)); + at91_mci_write(AT91C_PDC_TCR, (data->blksize & 0x3) ? + length : length / 4); + } + else + { + mmu_clean_dcache((rt_uint32_t)data->buf, data->blksize*data->blks); + at91_mci_write(AT91C_PDC_TPR, (rt_uint32_t)(data->buf)); + at91_mci_write(AT91C_PDC_TCR, (data->blksize & 0x3) ? + length : length / 4); + } + mci_dbg("Transmitting %d bytes\n", length); + ier = AT91C_MCI_CMDRDY; + } + } + } - /* - * Send the command and then enable the PDC - not the other way round as - * the data sheet says - */ + /* + * Send the command and then enable the PDC - not the other way round as + * the data sheet says + */ - at91_mci_write(AT91C_MCI_ARGR, cmd->arg); - at91_mci_write(AT91C_MCI_CMDR, cmdr); + at91_mci_write(AT91C_MCI_ARGR, cmd->arg); + at91_mci_write(AT91C_MCI_CMDR, cmdr); - if (cmdr & AT91C_MCI_TRCMD_START) - { - if (cmdr & AT91C_MCI_TRDIR) - at91_mci_write(AT91C_PDC_PTCR, AT91C_PDC_RXTEN); - } + if (cmdr & AT91C_MCI_TRCMD_START) + { + if (cmdr & AT91C_MCI_TRDIR) + at91_mci_write(AT91C_PDC_PTCR, AT91C_PDC_RXTEN); + } - /* Enable selected interrupts */ - at91_mci_write(AT91C_MCI_IER, AT91C_MCI_ERRORS | ier); + /* Enable selected interrupts */ + at91_mci_write(AT91C_MCI_IER, AT91C_MCI_ERRORS | ier); } /* @@ -418,25 +404,25 @@ static void at91_mci_send_command(struct at91_mci *mci, struct rt_mmcsd_cmd *cmd */ static void at91_mci_process_next(struct at91_mci *mci) { - if (mci->current_status == REQ_ST_INIT) - { - mci->current_status = REQ_ST_CMD; - at91_mci_send_command(mci, mci->req->cmd); - } - else if ((mci->current_status == REQ_ST_CMD) && mci->req->stop) - { - mci->current_status = REQ_ST_STOP; - at91_mci_send_command(mci, mci->req->stop); - } - else - { - rt_timer_stop(&mci->timer); - /* the mci controller hangs after some transfers, - * and the workaround is to reset it after each transfer. - */ - at91_reset_host(); - mmcsd_req_complete(mci->host); - } + if (mci->current_status == REQ_ST_INIT) + { + mci->current_status = REQ_ST_CMD; + at91_mci_send_command(mci, mci->req->cmd); + } + else if ((mci->current_status == REQ_ST_CMD) && mci->req->stop) + { + mci->current_status = REQ_ST_STOP; + at91_mci_send_command(mci, mci->req->stop); + } + else + { + rt_timer_stop(&mci->timer); + /* the mci controller hangs after some transfers, + * and the workaround is to reset it after each transfer. + */ + at91_reset_host(); + mmcsd_req_complete(mci->host); + } } /* @@ -444,15 +430,15 @@ static void at91_mci_process_next(struct at91_mci *mci) */ static void at91_mci_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) { - rt_uint32_t timeout = RT_TICK_PER_SECOND; - struct at91_mci *mci = host->private_data; - mci->req = req; - mci->current_status = REQ_ST_INIT; + rt_uint32_t timeout = RT_TICK_PER_SECOND; + struct at91_mci *mci = host->private_data; + mci->req = req; + mci->current_status = REQ_ST_INIT; - rt_timer_control(&mci->timer, RT_TIMER_CTRL_SET_TIME, (void*)&timeout); - rt_timer_start(&mci->timer); + rt_timer_control(&mci->timer, RT_TIMER_CTRL_SET_TIME, (void*)&timeout); + rt_timer_start(&mci->timer); - at91_mci_process_next(mci); + at91_mci_process_next(mci); } /* @@ -460,29 +446,29 @@ static void at91_mci_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *re */ static void at91_mci_handle_transmitted(struct at91_mci *mci) { - struct rt_mmcsd_cmd *cmd; - struct rt_mmcsd_data *data; + struct rt_mmcsd_cmd *cmd; + struct rt_mmcsd_data *data; - mci_dbg("Handling the transmit\n"); + mci_dbg("Handling the transmit\n"); - /* Disable the transfer */ - at91_mci_write(AT91C_PDC_PTCR, AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS); + /* Disable the transfer */ + at91_mci_write(AT91C_PDC_PTCR, AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS); - /* Now wait for cmd ready */ - at91_mci_write(AT91C_MCI_IDR, AT91C_MCI_TXBUFE); + /* Now wait for cmd ready */ + at91_mci_write(AT91C_MCI_IDR, AT91C_MCI_TXBUFE); - cmd = mci->cmd; - if (!cmd) return; + cmd = mci->cmd; + if (!cmd) return; - data = cmd->data; - if (!data) return; + data = cmd->data; + if (!data) return; - if (data->blks > 1) - { - mci_dbg("multiple write : wait for BLKE...\n"); - at91_mci_write(AT91C_MCI_IER, AT91C_MCI_BLKE); - } else - at91_mci_write(AT91C_MCI_IER, AT91C_MCI_NOTBUSY); + if (data->blks > 1) + { + mci_dbg("multiple write : wait for BLKE...\n"); + at91_mci_write(AT91C_MCI_IER, AT91C_MCI_BLKE); + } else + at91_mci_write(AT91C_MCI_IER, AT91C_MCI_NOTBUSY); } @@ -491,54 +477,54 @@ static void at91_mci_handle_transmitted(struct at91_mci *mci) */ static void at91_mci_post_dma_read(struct at91_mci *mci) { - struct rt_mmcsd_cmd *cmd; - struct rt_mmcsd_data *data; + struct rt_mmcsd_cmd *cmd; + struct rt_mmcsd_data *data; - mci_dbg("post dma read\n"); + mci_dbg("post dma read\n"); - cmd = mci->cmd; - if (!cmd) - { - mci_dbg("no command\n"); - return; - } + cmd = mci->cmd; + if (!cmd) + { + mci_dbg("no command\n"); + return; + } - data = cmd->data; - if (!data) - { - mci_dbg("no data\n"); - return; - } + data = cmd->data; + if (!data) + { + mci_dbg("no data\n"); + return; + } - at91_mci_write(AT91C_MCI_IDR, AT91C_MCI_ENDRX); - at91_mci_write(AT91C_MCI_IER, AT91C_MCI_RXBUFF); + at91_mci_write(AT91C_MCI_IDR, AT91C_MCI_ENDRX); + at91_mci_write(AT91C_MCI_IER, AT91C_MCI_RXBUFF); - mci_dbg("post dma read done\n"); + mci_dbg("post dma read done\n"); } /*Handle after command sent ready*/ static int at91_mci_handle_cmdrdy(struct at91_mci *mci) { - if (!mci->cmd) - return 1; - else if (!mci->cmd->data) - { - if (mci->current_status == REQ_ST_STOP) - { - /*After multi block write, we must wait for NOTBUSY*/ - at91_mci_write(AT91C_MCI_IER, AT91C_MCI_NOTBUSY); - } - else return 1; - } - else if (mci->cmd->data->flags & DATA_DIR_WRITE) - { - /*After sendding multi-block-write command, start DMA transfer*/ - at91_mci_write(AT91C_MCI_IER, AT91C_MCI_TXBUFE | AT91C_MCI_BLKE); - at91_mci_write(AT91C_PDC_PTCR, AT91C_PDC_TXTEN); - } + if (!mci->cmd) + return 1; + else if (!mci->cmd->data) + { + if (mci->current_status == REQ_ST_STOP) + { + /*After multi block write, we must wait for NOTBUSY*/ + at91_mci_write(AT91C_MCI_IER, AT91C_MCI_NOTBUSY); + } + else return 1; + } + else if (mci->cmd->data->flags & DATA_DIR_WRITE) + { + /*After sendding multi-block-write command, start DMA transfer*/ + at91_mci_write(AT91C_MCI_IER, AT91C_MCI_TXBUFE | AT91C_MCI_BLKE); + at91_mci_write(AT91C_PDC_PTCR, AT91C_PDC_TXTEN); + } - /* command not completed, have to wait */ - return 0; + /* command not completed, have to wait */ + return 0; } /* @@ -546,64 +532,64 @@ static int at91_mci_handle_cmdrdy(struct at91_mci *mci) */ static void at91_mci_completed_command(struct at91_mci *mci, rt_uint32_t status) { - struct rt_mmcsd_cmd *cmd = mci->cmd; - struct rt_mmcsd_data *data = cmd->data; + struct rt_mmcsd_cmd *cmd = mci->cmd; + struct rt_mmcsd_data *data = cmd->data; - at91_mci_write(AT91C_MCI_IDR, 0xffffffff & ~(AT91C_MCI_SDIOIRQA | AT91C_MCI_SDIOIRQB)); + at91_mci_write(AT91C_MCI_IDR, 0xffffffff & ~(AT91C_MCI_SDIOIRQA | AT91C_MCI_SDIOIRQB)); - cmd->resp[0] = at91_mci_read(AT91C_MCI_RSPR(0)); - cmd->resp[1] = at91_mci_read(AT91C_MCI_RSPR(1)); - cmd->resp[2] = at91_mci_read(AT91C_MCI_RSPR(2)); - cmd->resp[3] = at91_mci_read(AT91C_MCI_RSPR(3)); + cmd->resp[0] = at91_mci_read(AT91C_MCI_RSPR(0)); + cmd->resp[1] = at91_mci_read(AT91C_MCI_RSPR(1)); + cmd->resp[2] = at91_mci_read(AT91C_MCI_RSPR(2)); + cmd->resp[3] = at91_mci_read(AT91C_MCI_RSPR(3)); - if (mci->buf) - { - //rt_memcpy(data->buf, mci->buf, data->blksize*data->blks); - rt_free(mci->buf); - mci->buf = RT_NULL; - } + if (mci->buf) + { + //rt_memcpy(data->buf, mci->buf, data->blksize*data->blks); + rt_free(mci->buf); + mci->buf = RT_NULL; + } - mci_dbg("Status = %08X/%08x [%08X %08X %08X %08X]\n", - status, at91_mci_read(AT91C_MCI_SR), - cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); + mci_dbg("Status = %08X/%08x [%08X %08X %08X %08X]\n", + status, at91_mci_read(AT91C_MCI_SR), + cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); - if (status & AT91C_MCI_ERRORS) - { - if ((status & AT91C_MCI_RCRCE) && (resp_type(cmd) & (RESP_R3|RESP_R4))) - { - cmd->err = 0; - } - else - { - if (status & (AT91C_MCI_DTOE | AT91C_MCI_DCRCE)) - { - if (data) - { - if (status & AT91C_MCI_DTOE) - data->err = -RT_ETIMEOUT; - else if (status & AT91C_MCI_DCRCE) - data->err = -RT_ERROR; - } - } - else - { - if (status & AT91C_MCI_RTOE) - cmd->err = -RT_ETIMEOUT; - else if (status & AT91C_MCI_RCRCE) - cmd->err = -RT_ERROR; - else - cmd->err = -RT_ERROR; - } + if (status & AT91C_MCI_ERRORS) + { + if ((status & AT91C_MCI_RCRCE) && (resp_type(cmd) & (RESP_R3|RESP_R4))) + { + cmd->err = 0; + } + else + { + if (status & (AT91C_MCI_DTOE | AT91C_MCI_DCRCE)) + { + if (data) + { + if (status & AT91C_MCI_DTOE) + data->err = -RT_ETIMEOUT; + else if (status & AT91C_MCI_DCRCE) + data->err = -RT_ERROR; + } + } + else + { + if (status & AT91C_MCI_RTOE) + cmd->err = -RT_ETIMEOUT; + else if (status & AT91C_MCI_RCRCE) + cmd->err = -RT_ERROR; + else + cmd->err = -RT_ERROR; + } - rt_kprintf("error detected and set to %d/%d (cmd = %d)\n", - cmd->err, data ? data->err : 0, - cmd->cmd_code); - } - } - else - cmd->err = 0; + rt_kprintf("error detected and set to %d/%d (cmd = %d)\n", + cmd->err, data ? data->err : 0, + cmd->cmd_code); + } + } + else + cmd->err = 0; - at91_mci_process_next(mci); + at91_mci_process_next(mci); } /* @@ -611,120 +597,120 @@ static void at91_mci_completed_command(struct at91_mci *mci, rt_uint32_t status) */ static void at91_mci_irq(int irq, void *param) { - struct at91_mci *mci = (struct at91_mci *)param; - rt_int32_t completed = 0; - rt_uint32_t int_status, int_mask; + struct at91_mci *mci = (struct at91_mci *)param; + rt_int32_t completed = 0; + rt_uint32_t int_status, int_mask; - int_status = at91_mci_read(AT91C_MCI_SR); - int_mask = at91_mci_read(AT91C_MCI_IMR); + int_status = at91_mci_read(AT91C_MCI_SR); + int_mask = at91_mci_read(AT91C_MCI_IMR); - mci_dbg("MCI irq: status = %08X, %08X, %08X\n", int_status, int_mask, - int_status & int_mask); + mci_dbg("MCI irq: status = %08X, %08X, %08X\n", int_status, int_mask, + int_status & int_mask); - int_status = int_status & int_mask; + int_status = int_status & int_mask; - if (int_status & AT91C_MCI_ERRORS) - { - completed = 1; + if (int_status & AT91C_MCI_ERRORS) + { + completed = 1; - if (int_status & AT91C_MCI_UNRE) - mci_dbg("MMC: Underrun error\n"); - if (int_status & AT91C_MCI_OVRE) - mci_dbg("MMC: Overrun error\n"); - if (int_status & AT91C_MCI_DTOE) - mci_dbg("MMC: Data timeout\n"); - if (int_status & AT91C_MCI_DCRCE) - mci_dbg("MMC: CRC error in data\n"); - if (int_status & AT91C_MCI_RTOE) - mci_dbg("MMC: Response timeout\n"); - if (int_status & AT91C_MCI_RENDE) - mci_dbg("MMC: Response end bit error\n"); - if (int_status & AT91C_MCI_RCRCE) - mci_dbg("MMC: Response CRC error\n"); - if (int_status & AT91C_MCI_RDIRE) - mci_dbg("MMC: Response direction error\n"); - if (int_status & AT91C_MCI_RINDE) - mci_dbg("MMC: Response index error\n"); - } - else - { - /* Only continue processing if no errors */ + if (int_status & AT91C_MCI_UNRE) + mci_dbg("MMC: Underrun error\n"); + if (int_status & AT91C_MCI_OVRE) + mci_dbg("MMC: Overrun error\n"); + if (int_status & AT91C_MCI_DTOE) + mci_dbg("MMC: Data timeout\n"); + if (int_status & AT91C_MCI_DCRCE) + mci_dbg("MMC: CRC error in data\n"); + if (int_status & AT91C_MCI_RTOE) + mci_dbg("MMC: Response timeout\n"); + if (int_status & AT91C_MCI_RENDE) + mci_dbg("MMC: Response end bit error\n"); + if (int_status & AT91C_MCI_RCRCE) + mci_dbg("MMC: Response CRC error\n"); + if (int_status & AT91C_MCI_RDIRE) + mci_dbg("MMC: Response direction error\n"); + if (int_status & AT91C_MCI_RINDE) + mci_dbg("MMC: Response index error\n"); + } + else + { + /* Only continue processing if no errors */ - if (int_status & AT91C_MCI_TXBUFE) - { - mci_dbg("TX buffer empty\n"); - at91_mci_handle_transmitted(mci); - } + if (int_status & AT91C_MCI_TXBUFE) + { + mci_dbg("TX buffer empty\n"); + at91_mci_handle_transmitted(mci); + } - if (int_status & AT91C_MCI_ENDRX) - { - mci_dbg("ENDRX\n"); - at91_mci_post_dma_read(mci); - } + if (int_status & AT91C_MCI_ENDRX) + { + mci_dbg("ENDRX\n"); + at91_mci_post_dma_read(mci); + } - if (int_status & AT91C_MCI_RXBUFF) - { - mci_dbg("RX buffer full\n"); - at91_mci_write(AT91C_PDC_PTCR, AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS); - at91_mci_write(AT91C_MCI_IDR, AT91C_MCI_RXBUFF | AT91C_MCI_ENDRX); - completed = 1; - } + if (int_status & AT91C_MCI_RXBUFF) + { + mci_dbg("RX buffer full\n"); + at91_mci_write(AT91C_PDC_PTCR, AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS); + at91_mci_write(AT91C_MCI_IDR, AT91C_MCI_RXBUFF | AT91C_MCI_ENDRX); + completed = 1; + } - if (int_status & AT91C_MCI_ENDTX) - mci_dbg("Transmit has ended\n"); + if (int_status & AT91C_MCI_ENDTX) + mci_dbg("Transmit has ended\n"); - if (int_status & AT91C_MCI_NOTBUSY) - { - mci_dbg("Card is ready\n"); - //at91_mci_update_bytes_xfered(host); - completed = 1; - } + if (int_status & AT91C_MCI_NOTBUSY) + { + mci_dbg("Card is ready\n"); + //at91_mci_update_bytes_xfered(host); + completed = 1; + } - if (int_status & AT91C_MCI_DTIP) - mci_dbg("Data transfer in progress\n"); + if (int_status & AT91C_MCI_DTIP) + mci_dbg("Data transfer in progress\n"); - if (int_status & AT91C_MCI_BLKE) - { - mci_dbg("Block transfer has ended\n"); - if (mci->req->data && mci->req->data->blks > 1) - { - /* multi block write : complete multi write - * command and send stop */ - completed = 1; - } - else - { - at91_mci_write(AT91C_MCI_IER, AT91C_MCI_NOTBUSY); - } - } + if (int_status & AT91C_MCI_BLKE) + { + mci_dbg("Block transfer has ended\n"); + if (mci->req->data && mci->req->data->blks > 1) + { + /* multi block write : complete multi write + * command and send stop */ + completed = 1; + } + else + { + at91_mci_write(AT91C_MCI_IER, AT91C_MCI_NOTBUSY); + } + } - /*if (int_status & AT91C_MCI_SDIOIRQA) - rt_mmcsd_signal_sdio_irq(host->mmc);*/ + /*if (int_status & AT91C_MCI_SDIOIRQA) + rt_mmcsd_signal_sdio_irq(host->mmc);*/ - if (int_status & AT91C_MCI_SDIOIRQB) - sdio_irq_wakeup(mci->host); + if (int_status & AT91C_MCI_SDIOIRQB) + sdio_irq_wakeup(mci->host); - if (int_status & AT91C_MCI_TXRDY) - mci_dbg("Ready to transmit\n"); + if (int_status & AT91C_MCI_TXRDY) + mci_dbg("Ready to transmit\n"); - if (int_status & AT91C_MCI_RXRDY) - mci_dbg("Ready to receive\n"); + if (int_status & AT91C_MCI_RXRDY) + mci_dbg("Ready to receive\n"); - if (int_status & AT91C_MCI_CMDRDY) - { - mci_dbg("Command ready\n"); - completed = at91_mci_handle_cmdrdy(mci); - } - } + if (int_status & AT91C_MCI_CMDRDY) + { + mci_dbg("Command ready\n"); + completed = at91_mci_handle_cmdrdy(mci); + } + } - if (completed) - { - mci_dbg("Completed command\n"); - at91_mci_write(AT91C_MCI_IDR, 0xffffffff & ~(AT91C_MCI_SDIOIRQA | AT91C_MCI_SDIOIRQB)); - at91_mci_completed_command(mci, int_status); - } - else - at91_mci_write(AT91C_MCI_IDR, int_status & ~(AT91C_MCI_SDIOIRQA | AT91C_MCI_SDIOIRQB)); + if (completed) + { + mci_dbg("Completed command\n"); + at91_mci_write(AT91C_MCI_IDR, 0xffffffff & ~(AT91C_MCI_SDIOIRQA | AT91C_MCI_SDIOIRQB)); + at91_mci_completed_command(mci, int_status); + } + else + at91_mci_write(AT91C_MCI_IDR, int_status & ~(AT91C_MCI_SDIOIRQA | AT91C_MCI_SDIOIRQB)); } @@ -734,173 +720,173 @@ static void at91_mci_irq(int irq, void *param) */ static void at91_mci_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg) { - rt_uint32_t clkdiv; - //struct at91_mci *mci = host->private_data; - rt_uint32_t at91_master_clock = clk_get_rate(clk_get("mck")); + rt_uint32_t clkdiv; + //struct at91_mci *mci = host->private_data; + rt_uint32_t at91_master_clock = clk_get_rate(clk_get("mck")); - if (io_cfg->clock == 0) - { - /* Disable the MCI controller */ - at91_mci_write(AT91C_MCI_CR, AT91C_MCI_MCIDIS); - clkdiv = 0; - } - else - { - /* Enable the MCI controller */ - at91_mci_write(AT91C_MCI_CR, AT91C_MCI_MCIEN); + if (io_cfg->clock == 0) + { + /* Disable the MCI controller */ + at91_mci_write(AT91C_MCI_CR, AT91C_MCI_MCIDIS); + clkdiv = 0; + } + else + { + /* Enable the MCI controller */ + at91_mci_write(AT91C_MCI_CR, AT91C_MCI_MCIEN); - if ((at91_master_clock % (io_cfg->clock * 2)) == 0) - clkdiv = ((at91_master_clock / io_cfg->clock) / 2) - 1; - else - clkdiv = (at91_master_clock / io_cfg->clock) / 2; + if ((at91_master_clock % (io_cfg->clock * 2)) == 0) + clkdiv = ((at91_master_clock / io_cfg->clock) / 2) - 1; + else + clkdiv = (at91_master_clock / io_cfg->clock) / 2; - mci_dbg("clkdiv = %d. mcck = %ld\n", clkdiv, - at91_master_clock / (2 * (clkdiv + 1))); - } - if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4) - { - mci_dbg("MMC: Setting controller bus width to 4\n"); - at91_mci_write(AT91C_MCI_SDCR, at91_mci_read(AT91C_MCI_SDCR) | AT91C_MCI_SDCBUS); - } - else - { - mci_dbg("MMC: Setting controller bus width to 1\n"); - at91_mci_write(AT91C_MCI_SDCR, at91_mci_read(AT91C_MCI_SDCR) & ~AT91C_MCI_SDCBUS); - } + mci_dbg("clkdiv = %d. mcck = %ld\n", clkdiv, + at91_master_clock / (2 * (clkdiv + 1))); + } + if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4) + { + mci_dbg("MMC: Setting controller bus width to 4\n"); + at91_mci_write(AT91C_MCI_SDCR, at91_mci_read(AT91C_MCI_SDCR) | AT91C_MCI_SDCBUS); + } + else + { + mci_dbg("MMC: Setting controller bus width to 1\n"); + at91_mci_write(AT91C_MCI_SDCR, at91_mci_read(AT91C_MCI_SDCR) & ~AT91C_MCI_SDCBUS); + } - /* Set the clock divider */ - at91_mci_write(AT91C_MCI_MR, (at91_mci_read(AT91C_MCI_MR) & ~AT91C_MCI_CLKDIV) | clkdiv); + /* Set the clock divider */ + at91_mci_write(AT91C_MCI_MR, (at91_mci_read(AT91C_MCI_MR) & ~AT91C_MCI_CLKDIV) | clkdiv); - /* maybe switch power to the card */ - switch (io_cfg->power_mode) - { - case MMCSD_POWER_OFF: - break; - case MMCSD_POWER_UP: - break; - case MMCSD_POWER_ON: - /*at91_mci_write(AT91C_MCI_ARGR, 0); - at91_mci_write(AT91C_MCI_CMDR, 0|AT91C_MCI_SPCMD_INIT|AT91C_MCI_OPDCMD); - mci_dbg("MCI_SR=0x%08x\n", at91_mci_read(AT91C_MCI_SR)); - while (!(at91_mci_read(AT91C_MCI_SR) & AT91C_MCI_CMDRDY)) - { - - } - mci_dbg("at91 mci power on\n");*/ - break; - default: - rt_kprintf("unknown power_mode %d\n", io_cfg->power_mode); - break; - } + /* maybe switch power to the card */ + switch (io_cfg->power_mode) + { + case MMCSD_POWER_OFF: + break; + case MMCSD_POWER_UP: + break; + case MMCSD_POWER_ON: + /*at91_mci_write(AT91C_MCI_ARGR, 0); + at91_mci_write(AT91C_MCI_CMDR, 0|AT91C_MCI_SPCMD_INIT|AT91C_MCI_OPDCMD); + mci_dbg("MCI_SR=0x%08x\n", at91_mci_read(AT91C_MCI_SR)); + while (!(at91_mci_read(AT91C_MCI_SR) & AT91C_MCI_CMDRDY)) + { + + } + mci_dbg("at91 mci power on\n");*/ + break; + default: + rt_kprintf("unknown power_mode %d\n", io_cfg->power_mode); + break; + } } static void at91_mci_enable_sdio_irq(struct rt_mmcsd_host *host, rt_int32_t enable) { - at91_mci_write(enable ? AT91C_MCI_IER : AT91C_MCI_IDR, AT91C_MCI_SDIOIRQB); + at91_mci_write(enable ? AT91C_MCI_IER : AT91C_MCI_IDR, AT91C_MCI_SDIOIRQB); } static const struct rt_mmcsd_host_ops ops = { - at91_mci_request, - at91_mci_set_iocfg, + at91_mci_request, + at91_mci_set_iocfg, RT_NULL, - at91_mci_enable_sdio_irq, + at91_mci_enable_sdio_irq, }; void at91_mci_detect(int irq, void *param) { - rt_kprintf("mmcsd gpio detected\n"); + rt_kprintf("mmcsd gpio detected\n"); } static void mci_gpio_init() { #ifdef USE_SLOT_B - AT91C_BASE_PIOA->PIO_PUER = (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5); - AT91C_BASE_PIOA->PIO_PUDR = (1 << 8); - AT91C_BASE_PIOA->PIO_BSR = (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5); - AT91C_BASE_PIOA->PIO_ASR = (1 << 8); - AT91C_BASE_PIOA->PIO_PDR = (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5)|(1 << 8); + AT91C_BASE_PIOA->PIO_PUER = (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5); + AT91C_BASE_PIOA->PIO_PUDR = (1 << 8); + AT91C_BASE_PIOA->PIO_BSR = (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5); + AT91C_BASE_PIOA->PIO_ASR = (1 << 8); + AT91C_BASE_PIOA->PIO_PDR = (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5)|(1 << 8); - AT91C_BASE_PIOA->PIO_IDR = (1 << 6)|(1 << 7); - AT91C_BASE_PIOA->PIO_PUER = (1 << 6)|(1 << 7); - AT91C_BASE_PIOA->PIO_ODR = (1 << 6)|(1 << 7); - AT91C_BASE_PIOA->PIO_PER = (1 << 6)|(1 << 7); + AT91C_BASE_PIOA->PIO_IDR = (1 << 6)|(1 << 7); + AT91C_BASE_PIOA->PIO_PUER = (1 << 6)|(1 << 7); + AT91C_BASE_PIOA->PIO_ODR = (1 << 6)|(1 << 7); + AT91C_BASE_PIOA->PIO_PER = (1 << 6)|(1 << 7); #else - AT91C_BASE_PIOA->PIO_PUER = (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11); - AT91C_BASE_PIOA->PIO_ASR = (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 8); - AT91C_BASE_PIOA->PIO_PDR = (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 8); + AT91C_BASE_PIOA->PIO_PUER = (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11); + AT91C_BASE_PIOA->PIO_ASR = (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 8); + AT91C_BASE_PIOA->PIO_PDR = (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 8); #endif } int at91_mci_init(void) { - struct rt_mmcsd_host *host; - struct at91_mci *mci; + struct rt_mmcsd_host *host; + struct at91_mci *mci; - host = mmcsd_alloc_host(); - if (!host) - { - return -RT_ERROR; - } + host = mmcsd_alloc_host(); + if (!host) + { + return -RT_ERROR; + } - mci = rt_malloc(sizeof(struct at91_mci)); - if (!mci) - { - rt_kprintf("alloc mci failed\n"); - goto err; - } + mci = rt_malloc(sizeof(struct at91_mci)); + if (!mci) + { + rt_kprintf("alloc mci failed\n"); + goto err; + } - rt_memset(mci, 0, sizeof(struct at91_mci)); + rt_memset(mci, 0, sizeof(struct at91_mci)); - host->ops = &ops; - host->freq_min = 375000; - host->freq_max = 25000000; - host->valid_ocr = VDD_32_33 | VDD_33_34; - host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | \ - MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ; - host->max_seg_size = 65535; - host->max_dma_segs = 2; - host->max_blk_size = 512; - host->max_blk_count = 4096; + host->ops = &ops; + host->freq_min = 375000; + host->freq_max = 25000000; + host->valid_ocr = VDD_32_33 | VDD_33_34; + host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | \ + MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ; + host->max_seg_size = 65535; + host->max_dma_segs = 2; + host->max_blk_size = 512; + host->max_blk_count = 4096; - mci->host = host; + mci->host = host; - mci_gpio_init(); - AT91C_BASE_PMC->AT91C_PMC_PCER = 1 << AT91C_ID_MCI; //enable MCI clock - - at91_mci_disable(); - at91_mci_enable(); + mci_gpio_init(); + AT91C_BASE_PMC->AT91C_PMC_PCER = 1 << AT91C_ID_MCI; //enable MCI clock - /* instal interrupt */ - rt_hw_interrupt_install(AT91SAM9260_ID_MCI, at91_mci_irq, - (void *)mci, "MMC"); - rt_hw_interrupt_umask(AT91SAM9260_ID_MCI); - rt_hw_interrupt_install(gpio_to_irq(AT91C_PIN_PA7), - at91_mci_detect, RT_NULL, "MMC_DETECT"); - rt_hw_interrupt_umask(gpio_to_irq(AT91C_PIN_PA7)); + at91_mci_disable(); + at91_mci_enable(); - rt_timer_init(&mci->timer, "mci_timer", - at91_timeout_timer, - mci, - RT_TICK_PER_SECOND, - RT_TIMER_FLAG_PERIODIC); + /* instal interrupt */ + rt_hw_interrupt_install(AT91SAM9260_ID_MCI, at91_mci_irq, + (void *)mci, "MMC"); + rt_hw_interrupt_umask(AT91SAM9260_ID_MCI); + rt_hw_interrupt_install(gpio_to_irq(AT91C_PIN_PA7), + at91_mci_detect, RT_NULL, "MMC_DETECT"); + rt_hw_interrupt_umask(gpio_to_irq(AT91C_PIN_PA7)); - //rt_timer_start(&mci->timer); + rt_timer_init(&mci->timer, "mci_timer", + at91_timeout_timer, + mci, + RT_TICK_PER_SECOND, + RT_TIMER_FLAG_PERIODIC); - //rt_sem_init(&mci->sem_ack, "sd_ack", 0, RT_IPC_FLAG_FIFO); + //rt_timer_start(&mci->timer); - host->private_data = mci; + //rt_sem_init(&mci->sem_ack, "sd_ack", 0, RT_IPC_FLAG_FIFO); - mmcsd_change(host); + host->private_data = mci; - return 0; + mmcsd_change(host); + + return 0; err: - mmcsd_free_host(host); + mmcsd_free_host(host); - return -RT_ENOMEM; + return -RT_ENOMEM; } INIT_DEVICE_EXPORT(at91_mci_init); @@ -910,15 +896,15 @@ FINSH_FUNCTION_EXPORT(at91_mci_init, at91sam9260 sd init); void mci_dump(void) { - rt_uint32_t i; + rt_uint32_t i; - rt_kprintf("PIOA_PSR=0x%08x\n", readl(AT91C_PIOA+PIO_PSR)); - rt_kprintf("PIOA_ABSR=0x%08x\n", readl(AT91C_PIOA+PIO_ABSR)); - rt_kprintf("PIOA_PUSR=0x%08x\n", readl(AT91C_PIOA+PIO_PUSR)); + rt_kprintf("PIOA_PSR=0x%08x\n", readl(AT91C_PIOA+PIO_PSR)); + rt_kprintf("PIOA_ABSR=0x%08x\n", readl(AT91C_PIOA+PIO_ABSR)); + rt_kprintf("PIOA_PUSR=0x%08x\n", readl(AT91C_PIOA+PIO_PUSR)); - for (i = 0; i <= 0x4c; i += 4) { - rt_kprintf("0x%08x:0x%08x\n", AT91SAM9260_BASE_MCI+i, at91_mci_read(i)); - } + for (i = 0; i <= 0x4c; i += 4) { + rt_kprintf("0x%08x:0x%08x\n", AT91SAM9260_BASE_MCI+i, at91_mci_read(i)); + } } FINSH_FUNCTION_EXPORT(mci_dump, dump register for mci); diff --git a/bsp/at91sam9g45/drivers/at91_mci.h b/bsp/at91sam9g45/drivers/at91_mci.h index b3bfd289b1..3a4cc1705a 100644 --- a/bsp/at91sam9g45/drivers/at91_mci.h +++ b/bsp/at91sam9g45/drivers/at91_mci.h @@ -1,21 +1,7 @@ /* - * File : at91_mci.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -25,99 +11,99 @@ #ifndef __AT91C_MCI_H__ #define __AT91C_MCI_H__ -#define AT91C_MCI_CR 0x00 /* Control Register */ -#define AT91C_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */ -#define AT91C_MCI_MCIDIS (1 << 1) /* Multi-Media Interface Disable */ -#define AT91C_MCI_PWSEN (1 << 2) /* Power Save Mode Enable */ -#define AT91C_MCI_PWSDIS (1 << 3) /* Power Save Mode Disable */ -#define AT91C_MCI_SWRST (1 << 7) /* Software Reset */ +#define AT91C_MCI_CR 0x00 /* Control Register */ +#define AT91C_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */ +#define AT91C_MCI_MCIDIS (1 << 1) /* Multi-Media Interface Disable */ +#define AT91C_MCI_PWSEN (1 << 2) /* Power Save Mode Enable */ +#define AT91C_MCI_PWSDIS (1 << 3) /* Power Save Mode Disable */ +#define AT91C_MCI_SWRST (1 << 7) /* Software Reset */ -#define AT91C_MCI_MR 0x04 /* Mode Register */ -#define AT91C_MCI_CLKDIV (0xff << 0) /* Clock Divider */ -#define AT91C_MCI_PWSDIV (7 << 8) /* Power Saving Divider */ -#define AT91C_MCI_RDPROOF (1 << 11) /* Read Proof Enable [SAM926[03] only] */ -#define AT91C_MCI_WRPROOF (1 << 12) /* Write Proof Enable [SAM926[03] only] */ -#define AT91C_MCI_PDCFBYTE (1 << 13) /* PDC Force Byte Transfer [SAM926[03] only] */ -#define AT91C_MCI_PDCPADV (1 << 14) /* PDC Padding Value */ -#define AT91C_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */ -#define AT91C_MCI_BLKLEN (0xfff << 18) /* Data Block Length */ +#define AT91C_MCI_MR 0x04 /* Mode Register */ +#define AT91C_MCI_CLKDIV (0xff << 0) /* Clock Divider */ +#define AT91C_MCI_PWSDIV (7 << 8) /* Power Saving Divider */ +#define AT91C_MCI_RDPROOF (1 << 11) /* Read Proof Enable [SAM926[03] only] */ +#define AT91C_MCI_WRPROOF (1 << 12) /* Write Proof Enable [SAM926[03] only] */ +#define AT91C_MCI_PDCFBYTE (1 << 13) /* PDC Force Byte Transfer [SAM926[03] only] */ +#define AT91C_MCI_PDCPADV (1 << 14) /* PDC Padding Value */ +#define AT91C_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */ +#define AT91C_MCI_BLKLEN (0xfff << 18) /* Data Block Length */ -#define AT91C_MCI_DTOR 0x08 /* Data Timeout Register */ -#define AT91C_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */ -#define AT91C_MCI_DTOMUL (7 << 4) /* Data Timeout Multiplier */ -#define AT91C_MCI_DTOMUL_1 (0 << 4) -#define AT91C_MCI_DTOMUL_16 (1 << 4) -#define AT91C_MCI_DTOMUL_128 (2 << 4) -#define AT91C_MCI_DTOMUL_256 (3 << 4) -#define AT91C_MCI_DTOMUL_1K (4 << 4) -#define AT91C_MCI_DTOMUL_4K (5 << 4) -#define AT91C_MCI_DTOMUL_64K (6 << 4) -#define AT91C_MCI_DTOMUL_1M (7 << 4) +#define AT91C_MCI_DTOR 0x08 /* Data Timeout Register */ +#define AT91C_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */ +#define AT91C_MCI_DTOMUL (7 << 4) /* Data Timeout Multiplier */ +#define AT91C_MCI_DTOMUL_1 (0 << 4) +#define AT91C_MCI_DTOMUL_16 (1 << 4) +#define AT91C_MCI_DTOMUL_128 (2 << 4) +#define AT91C_MCI_DTOMUL_256 (3 << 4) +#define AT91C_MCI_DTOMUL_1K (4 << 4) +#define AT91C_MCI_DTOMUL_4K (5 << 4) +#define AT91C_MCI_DTOMUL_64K (6 << 4) +#define AT91C_MCI_DTOMUL_1M (7 << 4) -#define AT91C_MCI_SDCR 0x0c /* SD Card Register */ -#define AT91C_MCI_SDCSEL (3 << 0) /* SD Card Selector */ -#define AT91C_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */ +#define AT91C_MCI_SDCR 0x0c /* SD Card Register */ +#define AT91C_MCI_SDCSEL (3 << 0) /* SD Card Selector */ +#define AT91C_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */ -#define AT91C_MCI_ARGR 0x10 /* Argument Register */ +#define AT91C_MCI_ARGR 0x10 /* Argument Register */ -#define AT91C_MCI_CMDR 0x14 /* Command Register */ -#define AT91C_MCI_CMDNB (0x3f << 0) /* Command Number */ -#define AT91C_MCI_RSPTYP (3 << 6) /* Response Type */ -#define AT91C_MCI_RSPTYP_NONE (0 << 6) -#define AT91C_MCI_RSPTYP_48 (1 << 6) -#define AT91C_MCI_RSPTYP_136 (2 << 6) -#define AT91C_MCI_SPCMD (7 << 8) /* Special Command */ -#define AT91C_MCI_SPCMD_NONE (0 << 8) -#define AT91C_MCI_SPCMD_INIT (1 << 8) -#define AT91C_MCI_SPCMD_SYNC (2 << 8) -#define AT91C_MCI_SPCMD_ICMD (4 << 8) -#define AT91C_MCI_SPCMD_IRESP (5 << 8) -#define AT91C_MCI_OPDCMD (1 << 11) /* Open Drain Command */ -#define AT91C_MCI_MAXLAT (1 << 12) /* Max Latency for Command to Response */ -#define AT91C_MCI_TRCMD (3 << 16) /* Transfer Command */ -#define AT91C_MCI_TRCMD_NONE (0 << 16) -#define AT91C_MCI_TRCMD_START (1 << 16) -#define AT91C_MCI_TRCMD_STOP (2 << 16) -#define AT91C_MCI_TRDIR (1 << 18) /* Transfer Direction */ -#define AT91C_MCI_TRTYP (3 << 19) /* Transfer Type */ -#define AT91C_MCI_TRTYP_BLOCK (0 << 19) -#define AT91C_MCI_TRTYP_MULTIPLE (1 << 19) -#define AT91C_MCI_TRTYP_STREAM (2 << 19) +#define AT91C_MCI_CMDR 0x14 /* Command Register */ +#define AT91C_MCI_CMDNB (0x3f << 0) /* Command Number */ +#define AT91C_MCI_RSPTYP (3 << 6) /* Response Type */ +#define AT91C_MCI_RSPTYP_NONE (0 << 6) +#define AT91C_MCI_RSPTYP_48 (1 << 6) +#define AT91C_MCI_RSPTYP_136 (2 << 6) +#define AT91C_MCI_SPCMD (7 << 8) /* Special Command */ +#define AT91C_MCI_SPCMD_NONE (0 << 8) +#define AT91C_MCI_SPCMD_INIT (1 << 8) +#define AT91C_MCI_SPCMD_SYNC (2 << 8) +#define AT91C_MCI_SPCMD_ICMD (4 << 8) +#define AT91C_MCI_SPCMD_IRESP (5 << 8) +#define AT91C_MCI_OPDCMD (1 << 11) /* Open Drain Command */ +#define AT91C_MCI_MAXLAT (1 << 12) /* Max Latency for Command to Response */ +#define AT91C_MCI_TRCMD (3 << 16) /* Transfer Command */ +#define AT91C_MCI_TRCMD_NONE (0 << 16) +#define AT91C_MCI_TRCMD_START (1 << 16) +#define AT91C_MCI_TRCMD_STOP (2 << 16) +#define AT91C_MCI_TRDIR (1 << 18) /* Transfer Direction */ +#define AT91C_MCI_TRTYP (3 << 19) /* Transfer Type */ +#define AT91C_MCI_TRTYP_BLOCK (0 << 19) +#define AT91C_MCI_TRTYP_MULTIPLE (1 << 19) +#define AT91C_MCI_TRTYP_STREAM (2 << 19) -#define AT91C_MCI_BLKR 0x18 /* Block Register */ -#define AT91C_MCI_BLKR_BCNT(n) ((0xffff & (n)) << 0) /* Block count */ -#define AT91C_MCI_BLKR_BLKLEN(n) ((0xffff & (n)) << 16) /* Block lenght */ +#define AT91C_MCI_BLKR 0x18 /* Block Register */ +#define AT91C_MCI_BLKR_BCNT(n) ((0xffff & (n)) << 0) /* Block count */ +#define AT91C_MCI_BLKR_BLKLEN(n) ((0xffff & (n)) << 16) /* Block lenght */ -#define AT91C_MCI_RSPR(n) (0x20 + ((n) * 4)) /* Response Registers 0-3 */ -#define AT91C_MCR_RDR 0x30 /* Receive Data Register */ -#define AT91C_MCR_TDR 0x34 /* Transmit Data Register */ +#define AT91C_MCI_RSPR(n) (0x20 + ((n) * 4)) /* Response Registers 0-3 */ +#define AT91C_MCR_RDR 0x30 /* Receive Data Register */ +#define AT91C_MCR_TDR 0x34 /* Transmit Data Register */ -#define AT91C_MCI_SR 0x40 /* Status Register */ -#define AT91C_MCI_CMDRDY (1U << 0) /* Command Ready */ -#define AT91C_MCI_RXRDY (1U << 1) /* Receiver Ready */ -#define AT91C_MCI_TXRDY (1U << 2) /* Transmit Ready */ -#define AT91C_MCI_BLKE (1U << 3) /* Data Block Ended */ -#define AT91C_MCI_DTIP (1U << 4) /* Data Transfer in Progress */ -#define AT91C_MCI_NOTBUSY (1U << 5) /* Data Not Busy */ -#define AT91C_MCI_ENDRX (1U << 6) /* End of RX Buffer */ -#define AT91C_MCI_ENDTX (1U << 7) /* End fo TX Buffer */ -#define AT91C_MCI_SDIOIRQA (1U << 8) /* SDIO Interrupt for Slot A */ -#define AT91C_MCI_SDIOIRQB (1U << 9) /* SDIO Interrupt for Slot B */ -#define AT91C_MCI_RXBUFF (1U << 14) /* RX Buffer Full */ -#define AT91C_MCI_TXBUFE (1U << 15) /* TX Buffer Empty */ -#define AT91C_MCI_RINDE (1U << 16) /* Response Index Error */ -#define AT91C_MCI_RDIRE (1U << 17) /* Response Direction Error */ -#define AT91C_MCI_RCRCE (1U << 18) /* Response CRC Error */ -#define AT91C_MCI_RENDE (1U << 19) /* Response End Bit Error */ -#define AT91C_MCI_RTOE (1U << 20) /* Reponse Time-out Error */ -#define AT91C_MCI_DCRCE (1U << 21) /* Data CRC Error */ -#define AT91C_MCI_DTOE (1U << 22) /* Data Time-out Error */ -#define AT91C_MCI_OVRE (1U << 30) /* Overrun */ -#define AT91C_MCI_UNRE (1U << 31) /* Underrun */ +#define AT91C_MCI_SR 0x40 /* Status Register */ +#define AT91C_MCI_CMDRDY (1U << 0) /* Command Ready */ +#define AT91C_MCI_RXRDY (1U << 1) /* Receiver Ready */ +#define AT91C_MCI_TXRDY (1U << 2) /* Transmit Ready */ +#define AT91C_MCI_BLKE (1U << 3) /* Data Block Ended */ +#define AT91C_MCI_DTIP (1U << 4) /* Data Transfer in Progress */ +#define AT91C_MCI_NOTBUSY (1U << 5) /* Data Not Busy */ +#define AT91C_MCI_ENDRX (1U << 6) /* End of RX Buffer */ +#define AT91C_MCI_ENDTX (1U << 7) /* End fo TX Buffer */ +#define AT91C_MCI_SDIOIRQA (1U << 8) /* SDIO Interrupt for Slot A */ +#define AT91C_MCI_SDIOIRQB (1U << 9) /* SDIO Interrupt for Slot B */ +#define AT91C_MCI_RXBUFF (1U << 14) /* RX Buffer Full */ +#define AT91C_MCI_TXBUFE (1U << 15) /* TX Buffer Empty */ +#define AT91C_MCI_RINDE (1U << 16) /* Response Index Error */ +#define AT91C_MCI_RDIRE (1U << 17) /* Response Direction Error */ +#define AT91C_MCI_RCRCE (1U << 18) /* Response CRC Error */ +#define AT91C_MCI_RENDE (1U << 19) /* Response End Bit Error */ +#define AT91C_MCI_RTOE (1U << 20) /* Reponse Time-out Error */ +#define AT91C_MCI_DCRCE (1U << 21) /* Data CRC Error */ +#define AT91C_MCI_DTOE (1U << 22) /* Data Time-out Error */ +#define AT91C_MCI_OVRE (1U << 30) /* Overrun */ +#define AT91C_MCI_UNRE (1U << 31) /* Underrun */ -#define AT91C_MCI_IER 0x44 /* Interrupt Enable Register */ -#define AT91C_MCI_IDR 0x48 /* Interrupt Disable Register */ -#define AT91C_MCI_IMR 0x4c /* Interrupt Mask Register */ +#define AT91C_MCI_IER 0x44 /* Interrupt Enable Register */ +#define AT91C_MCI_IDR 0x48 /* Interrupt Disable Register */ +#define AT91C_MCI_IMR 0x4c /* Interrupt Mask Register */ extern int at91_mci_init(void); diff --git a/bsp/at91sam9g45/drivers/board.c b/bsp/at91sam9g45/drivers/board.c index 59ac3f1ba4..5d97e1d115 100644 --- a/bsp/at91sam9g45/drivers/board.c +++ b/bsp/at91sam9g45/drivers/board.c @@ -1,21 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2009 RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -53,36 +39,36 @@ extern void rt_hw_set_dividor(rt_uint8_t hdivn, rt_uint8_t pdivn); extern void rt_hw_set_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv); extern void rt_dbgu_isr(void); -#define SAM9G45_BLOCK_SIZE 0x10000000 // 256M -#define MMU_SECTION_SIZE 0x100000 // 1M -#define PERIPHERALS_ADDR // 1M +#define SAM9G45_BLOCK_SIZE 0x10000000 // 256M +#define MMU_SECTION_SIZE 0x100000 // 1M +#define PERIPHERALS_ADDR // 1M -#define SECTION_END(sa) ((sa) + MMU_SECTION_SIZE - 1) // sa: start address -#define BLOCK_END(ba) ((ba) + SAM9G45_BLOCK_SIZE - 1) // ba: block address +#define SECTION_END(sa) ((sa) + MMU_SECTION_SIZE - 1) // sa: start address +#define BLOCK_END(ba) ((ba) + SAM9G45_BLOCK_SIZE - 1) // ba: block address -static struct mem_desc at91_mem_desc[] = { /* FIXME, hornby, to confirm MMU and memory */ - { 0x00000000, 0xFFFFFFFF , 0x00000000, RW_NCNB }, /* None cached for 4G memory */ - //{ 0x00000000, SECTION_END(0x00000000), 0x00000000, RW_CNB }, /* TLB for ITCM, ITCM map to address zero, 32KB */ - //{ 0x00200000, SECTION_END(0x00200000), 0x00200000, RW_CNB }, /* TLB for DTCM, 32KB */ - //{ 0x00300000, SECTION_END(0x00300000), 0x00300000, RW_CNB }, /* TLB for internal RAM, 64KB, we use it as global variable area */ - //{ 0x00600000, SECTION_END(0x00600000), 0x00600000, RW_NCNB }, /* TLB for UDPHS(DMA) */ - //{ 0x00700000, SECTION_END(0x00700000), 0x00700000, RW_NCNB }, /* TLB for UHP OHCI */ - //{ 0x00800000, SECTION_END(0x00800000), 0x00800000, RW_NCNB }, /* TLB for UHP EHCI */ - //{ 0x30000000, 0x30000000+0x00100000-1, 0x30000000, RW_CB }, /* 1M external SRAM for program code and stack */ - //{ 0x40000000, BLOCK_END(0x40000000), 0x40000000, RW_NCNB }, /* 256M for nand-flash controller */ - //{ 0x60000000, BLOCK_END(0x60000000), 0x60000000, RW_NCNB }, /* 256M for FPGA */ - //{ 0x70000000, 0x70000000+0x08000000-1, 0x70000000, RW_NCNB }, /* 128M for main DDR-SDRAM for print data */ - { 0x00000000, SECTION_END(0x00000000), 0x70000000, RW_CB }, /* isr */ - { 0x70000000, 0x70000000+0x08000000-1, 0x70000000, RW_CB }, /* 128M for main DDR-SDRAM for print data */ - //{ 0xFFF00000, SECTION_END(0xFFF00000), 0xFFF00000, RW_NCNB }, /* Internal Peripherals, 1MB */ +static struct mem_desc at91_mem_desc[] = { /* FIXME, hornby, to confirm MMU and memory */ + { 0x00000000, 0xFFFFFFFF , 0x00000000, RW_NCNB }, /* None cached for 4G memory */ + //{ 0x00000000, SECTION_END(0x00000000), 0x00000000, RW_CNB }, /* TLB for ITCM, ITCM map to address zero, 32KB */ + //{ 0x00200000, SECTION_END(0x00200000), 0x00200000, RW_CNB }, /* TLB for DTCM, 32KB */ + //{ 0x00300000, SECTION_END(0x00300000), 0x00300000, RW_CNB }, /* TLB for internal RAM, 64KB, we use it as global variable area */ + //{ 0x00600000, SECTION_END(0x00600000), 0x00600000, RW_NCNB }, /* TLB for UDPHS(DMA) */ + //{ 0x00700000, SECTION_END(0x00700000), 0x00700000, RW_NCNB }, /* TLB for UHP OHCI */ + //{ 0x00800000, SECTION_END(0x00800000), 0x00800000, RW_NCNB }, /* TLB for UHP EHCI */ + //{ 0x30000000, 0x30000000+0x00100000-1, 0x30000000, RW_CB }, /* 1M external SRAM for program code and stack */ + //{ 0x40000000, BLOCK_END(0x40000000), 0x40000000, RW_NCNB }, /* 256M for nand-flash controller */ + //{ 0x60000000, BLOCK_END(0x60000000), 0x60000000, RW_NCNB }, /* 256M for FPGA */ + //{ 0x70000000, 0x70000000+0x08000000-1, 0x70000000, RW_NCNB }, /* 128M for main DDR-SDRAM for print data */ + { 0x00000000, SECTION_END(0x00000000), 0x70000000, RW_CB }, /* isr */ + { 0x70000000, 0x70000000+0x08000000-1, 0x70000000, RW_CB }, /* 128M for main DDR-SDRAM for print data */ + //{ 0xFFF00000, SECTION_END(0xFFF00000), 0xFFF00000, RW_NCNB }, /* Internal Peripherals, 1MB */ }; -#define PIT_CPIV(x) ((x) & AT91C_PITC_CPIV) -#define PIT_PICNT(x) (((x) & AT91C_PITC_PICNT) >> 20) +#define PIT_CPIV(x) ((x) & AT91C_PITC_CPIV) +#define PIT_PICNT(x) (((x) & AT91C_PITC_PICNT) >> 20) -static rt_uint32_t pit_cycle; /* write-once */ -static rt_uint32_t pit_cnt; /* access only w/system irq blocked */ +static rt_uint32_t pit_cycle; /* write-once */ +static rt_uint32_t pit_cnt; /* access only w/system irq blocked */ /** * This function will handle rtos timer @@ -90,37 +76,37 @@ static rt_uint32_t pit_cnt; /* access only w/system irq blocked */ void rt_timer_handler(int vector, void *param) { #ifdef RT_USING_DBGU - if (readl(AT91C_DBGU_CSR) & AT91C_US_RXRDY) - { - rt_dbgu_isr(); - } + if (readl(AT91C_DBGU_CSR) & AT91C_US_RXRDY) + { + rt_dbgu_isr(); + } #endif - if (readl(AT91C_PITC_PISR) & AT91C_PITC_PITS) - { - unsigned nr_ticks; + if (readl(AT91C_PITC_PISR) & AT91C_PITC_PITS) + { + unsigned nr_ticks; - /* Get number of ticks performed before irq, and ack it */ - nr_ticks = PIT_PICNT(readl(AT91C_PITC_PIVR)); + /* Get number of ticks performed before irq, and ack it */ + nr_ticks = PIT_PICNT(readl(AT91C_PITC_PIVR)); while (nr_ticks--) - rt_tick_increase(); - } + rt_tick_increase(); + } } static void at91sam9g45_pit_reset(void) { - /* Disable timer and irqs */ - AT91C_BASE_PITC->PITC_PIMR = 0; + /* Disable timer and irqs */ + AT91C_BASE_PITC->PITC_PIMR = 0; - /* Clear any pending interrupts, wait for PIT to stop counting */ - while (PIT_CPIV(readl(AT91C_PITC_PIVR)) != 0) - ; + /* Clear any pending interrupts, wait for PIT to stop counting */ + while (PIT_CPIV(readl(AT91C_PITC_PIVR)) != 0) + ; - /* Start PIT but don't enable IRQ */ - //AT91C_BASE_PITC->PITC_PIMR = (pit_cycle - 1) | AT91C_PITC_PITEN; - pit_cnt += pit_cycle * PIT_PICNT(readl(AT91C_PITC_PIVR)); - AT91C_BASE_PITC->PITC_PIMR = - (pit_cycle - 1) | AT91C_PITC_PITEN | AT91C_PITC_PITIEN; - rt_kprintf("PIT_MR=0x%08x\n", readl(AT91C_PITC_PIMR)); + /* Start PIT but don't enable IRQ */ + //AT91C_BASE_PITC->PITC_PIMR = (pit_cycle - 1) | AT91C_PITC_PITEN; + pit_cnt += pit_cycle * PIT_PICNT(readl(AT91C_PITC_PIVR)); + AT91C_BASE_PITC->PITC_PIMR = + (pit_cycle - 1) | AT91C_PITC_PITEN | AT91C_PITC_PITIEN; + rt_kprintf("PIT_MR=0x%08x\n", readl(AT91C_PITC_PIMR)); } /* @@ -128,19 +114,19 @@ static void at91sam9g45_pit_reset(void) */ static void at91sam9g45_pit_init(void) { - rt_uint32_t pit_rate; - //rt_uint32_t bits; + rt_uint32_t pit_rate; + //rt_uint32_t bits; - /* - * Use our actual MCK to figure out how many MCK/16 ticks per - * 1/HZ period (instead of a compile-time constant LATCH). - */ - pit_rate = clk_get_rate(clk_get("mck")) / 16; - rt_kprintf("pit_rate=%dHZ\n", pit_rate); - pit_cycle = (pit_rate + RT_TICK_PER_SECOND/2) / RT_TICK_PER_SECOND; + /* + * Use our actual MCK to figure out how many MCK/16 ticks per + * 1/HZ period (instead of a compile-time constant LATCH). + */ + pit_rate = clk_get_rate(clk_get("mck")) / 16; + rt_kprintf("pit_rate=%dHZ\n", pit_rate); + pit_cycle = (pit_rate + RT_TICK_PER_SECOND/2) / RT_TICK_PER_SECOND; - /* Initialize and enable the timer */ - at91sam9g45_pit_reset(); + /* Initialize and enable the timer */ + at91sam9g45_pit_reset(); } /** @@ -148,30 +134,30 @@ static void at91sam9g45_pit_init(void) */ void rt_hw_timer_init() { - at91sam9g45_pit_init(); + at91sam9g45_pit_init(); - /* install interrupt handler */ - rt_hw_interrupt_install(AT91C_ID_SYS, rt_timer_handler, - RT_NULL, "system"); - rt_hw_interrupt_umask(AT91C_ID_SYS); + /* install interrupt handler */ + rt_hw_interrupt_install(AT91C_ID_SYS, rt_timer_handler, + RT_NULL, "system"); + rt_hw_interrupt_umask(AT91C_ID_SYS); } void at91_tc1_init() { - AT91C_BASE_PMC->PMC_PCER = 1<PMC_PCER = 1<DBGU_CSR & AT91C_US_TXRDY)) - ; - AT91C_BASE_DBGU->DBGU_THR = c; + while (!(AT91C_BASE_DBGU->DBGU_CSR & AT91C_US_TXRDY)) + ; + AT91C_BASE_DBGU->DBGU_THR = c; } /** @@ -182,33 +168,33 @@ static void at91_usart_putc(char c) */ void rt_hw_console_output(const char* str) { - while (*str) - { - if (*str=='\n') - { - at91_usart_putc('\r'); - } + while (*str) + { + if (*str=='\n') + { + at91_usart_putc('\r'); + } - at91_usart_putc(*str++); - } + at91_usart_putc(*str++); + } } static void rt_hw_console_init(void) { - int div; - int mode = 0; + int div; + int mode = 0; - AT91C_BASE_DBGU->DBGU_CR = AT91C_US_RSTTX | AT91C_US_RSTRX | - AT91C_US_RXDIS | AT91C_US_TXDIS; - mode |= AT91C_US_USMODE_NORMAL | AT91C_US_CLKS_CLOCK | - AT91C_US_CHMODE_NORMAL; - mode |= AT91C_US_CHRL_8_BITS; - mode |= AT91C_US_NBSTOP_1_BIT; - mode |= AT91C_US_PAR_NONE; - AT91C_BASE_DBGU->DBGU_MR = mode; - div = (clk_get_rate(clk_get("mck")) / 16 + BPS/2) / BPS; - AT91C_BASE_DBGU->DBGU_BRGR = div; - AT91C_BASE_DBGU->DBGU_CR = AT91C_US_RXEN | AT91C_US_TXEN; + AT91C_BASE_DBGU->DBGU_CR = AT91C_US_RSTTX | AT91C_US_RSTRX | + AT91C_US_RXDIS | AT91C_US_TXDIS; + mode |= AT91C_US_USMODE_NORMAL | AT91C_US_CLKS_CLOCK | + AT91C_US_CHMODE_NORMAL; + mode |= AT91C_US_CHRL_8_BITS; + mode |= AT91C_US_NBSTOP_1_BIT; + mode |= AT91C_US_PAR_NONE; + AT91C_BASE_DBGU->DBGU_MR = mode; + div = (clk_get_rate(clk_get("mck")) / 16 + BPS/2) / BPS; + AT91C_BASE_DBGU->DBGU_BRGR = div; + AT91C_BASE_DBGU->DBGU_CR = AT91C_US_RXEN | AT91C_US_TXEN; } @@ -217,31 +203,31 @@ static void rt_hw_console_init(void) */ void rt_hw_board_init() { - /* initialize the system clock */ - rt_hw_clock_init(); + /* initialize the system clock */ + rt_hw_clock_init(); - /* initialize console */ - rt_hw_console_init(); + /* initialize console */ + rt_hw_console_init(); - /* initialize mmu */ - rt_hw_mmu_init(at91_mem_desc, sizeof(at91_mem_desc)/sizeof(at91_mem_desc[0])); + /* initialize mmu */ + rt_hw_mmu_init(at91_mem_desc, sizeof(at91_mem_desc)/sizeof(at91_mem_desc[0])); - /* initialize hardware interrupt */ - rt_hw_interrupt_init(); + /* initialize hardware interrupt */ + rt_hw_interrupt_init(); - /* initialize early device */ + /* initialize early device */ #ifdef RT_USING_COMPONENTS_INIT - rt_components_board_init(); + rt_components_board_init(); #endif #ifdef RT_USING_CONSOLE - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); #endif - /* initialize timer0 */ - rt_hw_timer_init(); + /* initialize timer0 */ + rt_hw_timer_init(); /* initialize board */ #ifdef RT_USING_HEAP - rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); #endif } diff --git a/bsp/at91sam9g45/drivers/board.h b/bsp/at91sam9g45/drivers/board.h index a6ec4e0ef7..1c3147b8f5 100644 --- a/bsp/at91sam9g45/drivers/board.h +++ b/bsp/at91sam9g45/drivers/board.h @@ -1,21 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/at91sam9g45/drivers/led.c b/bsp/at91sam9g45/drivers/led.c index fb8b417033..d4b377e629 100644 --- a/bsp/at91sam9g45/drivers/led.c +++ b/bsp/at91sam9g45/drivers/led.c @@ -1,21 +1,7 @@ /* - * File : led.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -35,10 +21,10 @@ void led_init(void) { - AT91C_BASE_PIOC->PIO_PER = LED_ALL; - AT91C_BASE_PIOC->PIO_OER = LED_ALL; - AT91C_BASE_PIOC->PIO_PPUER = LED_ALL; - AT91C_BASE_PIOC->PIO_SODR = LED_ALL; + AT91C_BASE_PIOC->PIO_PER = LED_ALL; + AT91C_BASE_PIOC->PIO_OER = LED_ALL; + AT91C_BASE_PIOC->PIO_PPUER = LED_ALL; + AT91C_BASE_PIOC->PIO_SODR = LED_ALL; } const static rt_uint32_t m_leds[] = { LED0, LED1, LED2, LED3 }; diff --git a/bsp/at91sam9g45/drivers/led.h b/bsp/at91sam9g45/drivers/led.h index f2967bc92d..9836eff709 100644 --- a/bsp/at91sam9g45/drivers/led.h +++ b/bsp/at91sam9g45/drivers/led.h @@ -1,21 +1,7 @@ /* - * File : led.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/at91sam9g45/drivers/macb.c b/bsp/at91sam9g45/drivers/macb.c index b5cffaa1d2..8a300725c3 100644 --- a/bsp/at91sam9g45/drivers/macb.c +++ b/bsp/at91sam9g45/drivers/macb.c @@ -1,21 +1,7 @@ /* - * File : macb.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -28,7 +14,7 @@ #include #include "macb.h" -#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<31)) +#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<31)) extern void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size); extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size); @@ -36,11 +22,11 @@ extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size); /* Cache macros - Packet buffers would be from pbuf pool which is cached */ #define EMAC_VIRT_NOCACHE(addr) (addr) #define EMAC_CACHE_INVALIDATE(addr, size) \ - mmu_invalidate_dcache((rt_uint32_t)addr, size) + mmu_invalidate_dcache((rt_uint32_t)addr, size) #define EMAC_CACHE_WRITEBACK(addr, size) \ - mmu_clean_dcache((rt_uint32_t)addr, size) + mmu_clean_dcache((rt_uint32_t)addr, size) #define EMAC_CACHE_WRITEBACK_INVALIDATE(addr, size) \ - mmu_clean_invalidated_dcache((rt_uint32_t)addr, size) + mmu_clean_invalidated_dcache((rt_uint32_t)addr, size) /* EMAC has BD's in cached memory - so need cache functions */ #define BD_CACHE_INVALIDATE(addr, size) @@ -50,7 +36,7 @@ extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size); /* EMAC internal utility function */ rt_inline unsigned long emac_virt_to_phys(unsigned long addr) { - return addr; + return addr; } @@ -59,112 +45,112 @@ rt_inline unsigned long emac_virt_to_phys(unsigned long addr) #define MACB_TX_SRAM #if defined(MACB_TX_SRAM) -#define MACB_TX_RING_SIZE 2 -#define MACB_TX_BUFFER_SIZE (1536 * MACB_TX_RING_SIZE) -#define TX_RING_BYTES (sizeof(struct macb_dma_desc) * MACB_TX_RING_SIZE) +#define MACB_TX_RING_SIZE 2 +#define MACB_TX_BUFFER_SIZE (1536 * MACB_TX_RING_SIZE) +#define TX_RING_BYTES (sizeof(struct macb_dma_desc) * MACB_TX_RING_SIZE) #else -#define MACB_TX_RING_SIZE 16 -#define MACB_TX_BUFFER_SIZE (1536 * MACB_TX_RING_SIZE) +#define MACB_TX_RING_SIZE 16 +#define MACB_TX_BUFFER_SIZE (1536 * MACB_TX_RING_SIZE) #endif -#define MACB_RX_BUFFER_SIZE (4096*4) -#define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128) +#define MACB_RX_BUFFER_SIZE (4096*4) +#define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128) -#define DEF_TX_RING_PENDING (MACB_TX_RING_SIZE) +#define DEF_TX_RING_PENDING (MACB_TX_RING_SIZE) -#define TX_RING_GAP(macb) \ - (MACB_TX_RING_SIZE - (macb)->tx_pending) +#define TX_RING_GAP(macb) \ + (MACB_TX_RING_SIZE - (macb)->tx_pending) -#define TX_BUFFS_AVAIL(macb) \ - (((macb)->tx_tail <= (macb)->tx_head) ? \ - (macb)->tx_tail + (macb)->tx_pending - (macb)->tx_head : \ - (macb)->tx_tail - (macb)->tx_head - TX_RING_GAP(macb)) +#define TX_BUFFS_AVAIL(macb) \ + (((macb)->tx_tail <= (macb)->tx_head) ? \ + (macb)->tx_tail + (macb)->tx_pending - (macb)->tx_head : \ + (macb)->tx_tail - (macb)->tx_head - TX_RING_GAP(macb)) -#define NEXT_TX(n) (((n) + 1) & (MACB_TX_RING_SIZE - 1)) +#define NEXT_TX(n) (((n) + 1) & (MACB_TX_RING_SIZE - 1)) -#define NEXT_RX(n) (((n) + 1) & (MACB_RX_RING_SIZE - 1)) +#define NEXT_RX(n) (((n) + 1) & (MACB_RX_RING_SIZE - 1)) /* minimum number of free TX descriptors before waking up TX process */ -#define MACB_TX_WAKEUP_THRESH (MACB_TX_RING_SIZE / 4) +#define MACB_TX_WAKEUP_THRESH (MACB_TX_RING_SIZE / 4) -#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \ - | MACB_BIT(ISR_ROVR)) +#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \ + | MACB_BIT(ISR_ROVR)) -#define MACB_TX_TIMEOUT 1000 -#define MACB_AUTONEG_TIMEOUT 5000000 -#define MACB_LINK_TIMEOUT 500000 +#define MACB_TX_TIMEOUT 1000 +#define MACB_AUTONEG_TIMEOUT 5000000 +#define MACB_LINK_TIMEOUT 500000 #define CONFIG_RMII struct macb_dma_desc { - rt_uint32_t addr; - rt_uint32_t ctrl; + rt_uint32_t addr; + rt_uint32_t ctrl; }; -#define RXADDR_USED 0x00000001 -#define RXADDR_WRAP 0x00000002 +#define RXADDR_USED 0x00000001 +#define RXADDR_WRAP 0x00000002 -#define RXBUF_FRMLEN_MASK 0x00000fff -#define RXBUF_FRAME_START 0x00004000 -#define RXBUF_FRAME_END 0x00008000 -#define RXBUF_TYPEID_MATCH 0x00400000 -#define RXBUF_ADDR4_MATCH 0x00800000 -#define RXBUF_ADDR3_MATCH 0x01000000 -#define RXBUF_ADDR2_MATCH 0x02000000 -#define RXBUF_ADDR1_MATCH 0x04000000 -#define RXBUF_BROADCAST 0x80000000 +#define RXBUF_FRMLEN_MASK 0x00000fff +#define RXBUF_FRAME_START 0x00004000 +#define RXBUF_FRAME_END 0x00008000 +#define RXBUF_TYPEID_MATCH 0x00400000 +#define RXBUF_ADDR4_MATCH 0x00800000 +#define RXBUF_ADDR3_MATCH 0x01000000 +#define RXBUF_ADDR2_MATCH 0x02000000 +#define RXBUF_ADDR1_MATCH 0x04000000 +#define RXBUF_BROADCAST 0x80000000 -#define TXBUF_FRMLEN_MASK 0x000007ff -#define TXBUF_FRAME_END 0x00008000 -#define TXBUF_NOCRC 0x00010000 -#define TXBUF_EXHAUSTED 0x08000000 -#define TXBUF_UNDERRUN 0x10000000 -#define TXBUF_MAXRETRY 0x20000000 -#define TXBUF_WRAP 0x40000000 -#define TXBUF_USED 0x80000000 +#define TXBUF_FRMLEN_MASK 0x000007ff +#define TXBUF_FRAME_END 0x00008000 +#define TXBUF_NOCRC 0x00010000 +#define TXBUF_EXHAUSTED 0x08000000 +#define TXBUF_UNDERRUN 0x10000000 +#define TXBUF_MAXRETRY 0x20000000 +#define TXBUF_WRAP 0x40000000 +#define TXBUF_USED 0x80000000 /* Duplex, half or full. */ -#define DUPLEX_HALF 0x00 -#define DUPLEX_FULL 0x01 +#define DUPLEX_HALF 0x00 +#define DUPLEX_FULL 0x01 #define MAX_ADDR_LEN 6 struct rt_macb_eth { - /* inherit from ethernet device */ - struct eth_device parent; + /* inherit from ethernet device */ + struct eth_device parent; - unsigned int regs; + unsigned int regs; - unsigned int rx_tail; - unsigned int tx_head; - unsigned int tx_tail; - unsigned int rx_pending; - unsigned int tx_pending; + unsigned int rx_tail; + unsigned int tx_head; + unsigned int tx_tail; + unsigned int rx_pending; + unsigned int tx_pending; - void *rx_buffer; - void *tx_buffer; - struct macb_dma_desc *rx_ring; - struct macb_dma_desc *tx_ring; + void *rx_buffer; + void *tx_buffer; + struct macb_dma_desc *rx_ring; + struct macb_dma_desc *tx_ring; - unsigned long rx_buffer_dma; - unsigned long tx_buffer_dma; - unsigned long rx_ring_dma; - unsigned long tx_ring_dma; + unsigned long rx_buffer_dma; + unsigned long tx_buffer_dma; + unsigned long rx_ring_dma; + unsigned long tx_ring_dma; - unsigned int tx_stop; + unsigned int tx_stop; - /* interface address info. */ - rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ - unsigned short phy_addr; + /* interface address info. */ + rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ + unsigned short phy_addr; - struct rt_semaphore mdio_bus_lock; - struct rt_semaphore tx_lock; - struct rt_semaphore rx_lock; - struct rt_semaphore tx_ack; - rt_uint32_t speed; - rt_uint32_t duplex; - rt_uint32_t link; - struct rt_timer timer; + struct rt_semaphore mdio_bus_lock; + struct rt_semaphore tx_lock; + struct rt_semaphore rx_lock; + struct rt_semaphore tx_ack; + rt_uint32_t speed; + rt_uint32_t duplex; + rt_uint32_t link; + struct rt_timer timer; }; static struct rt_macb_eth macb_device; @@ -179,253 +165,253 @@ static void udelay(rt_uint32_t us) static void rt_macb_isr(int irq, void *param) { - struct rt_macb_eth *macb = (struct rt_macb_eth *)param; - rt_device_t dev = &(macb->parent.parent); - rt_uint32_t status, rsr, tsr; + struct rt_macb_eth *macb = (struct rt_macb_eth *)param; + rt_device_t dev = &(macb->parent.parent); + rt_uint32_t status, rsr, tsr; - status = macb_readl(macb, ISR); + status = macb_readl(macb, ISR); - while (status) { + while (status) { - if (status & MACB_RX_INT_FLAGS) - { - rsr = macb_readl(macb, RSR); - macb_writel(macb, RSR, rsr); - /* a frame has been received */ - eth_device_ready(&(macb_device.parent)); - - } + if (status & MACB_RX_INT_FLAGS) + { + rsr = macb_readl(macb, RSR); + macb_writel(macb, RSR, rsr); + /* a frame has been received */ + eth_device_ready(&(macb_device.parent)); - if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND) | - MACB_BIT(ISR_RLE))) - { - macb_tx(macb); - } + } - /* - * Link change detection isn't possible with RMII, so we'll - * add that if/when we get our hands on a full-blown MII PHY. - */ + if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND) | + MACB_BIT(ISR_RLE))) + { + macb_tx(macb); + } - if (status & MACB_BIT(HRESP)) - { - /* - * TODO: Reset the hardware, and maybe move the printk - * to a lower-priority context as well (work queue?) - */ - rt_kprintf("%s: DMA bus error: HRESP not OK\n", - dev->parent.name); - } + /* + * Link change detection isn't possible with RMII, so we'll + * add that if/when we get our hands on a full-blown MII PHY. + */ - status = macb_readl(macb, ISR); - } + if (status & MACB_BIT(HRESP)) + { + /* + * TODO: Reset the hardware, and maybe move the printk + * to a lower-priority context as well (work queue?) + */ + rt_kprintf("%s: DMA bus error: HRESP not OK\n", + dev->parent.name); + } + + status = macb_readl(macb, ISR); + } } static int macb_mdio_write(struct rt_macb_eth *macb, rt_uint8_t reg, rt_uint16_t value) { - unsigned long netctl; - unsigned long netstat; - unsigned long frame; + unsigned long netctl; + unsigned long netstat; + unsigned long frame; - rt_sem_take(&macb->mdio_bus_lock, RT_WAITING_FOREVER); - netctl = macb_readl(macb, NCR); - netctl |= MACB_BIT(MPE); - macb_writel(macb, NCR, netctl); + rt_sem_take(&macb->mdio_bus_lock, RT_WAITING_FOREVER); + netctl = macb_readl(macb, NCR); + netctl |= MACB_BIT(MPE); + macb_writel(macb, NCR, netctl); - frame = (MACB_BF(SOF, 1) - | MACB_BF(RW, 1) - | MACB_BF(PHYA, macb->phy_addr) - | MACB_BF(REGA, reg) - | MACB_BF(CODE, 2) - | MACB_BF(DATA, value)); - macb_writel(macb, MAN, frame); + frame = (MACB_BF(SOF, 1) + | MACB_BF(RW, 1) + | MACB_BF(PHYA, macb->phy_addr) + | MACB_BF(REGA, reg) + | MACB_BF(CODE, 2) + | MACB_BF(DATA, value)); + macb_writel(macb, MAN, frame); - do { - netstat = macb_readl(macb, NSR); - } while (!(netstat & MACB_BIT(IDLE))); + do { + netstat = macb_readl(macb, NSR); + } while (!(netstat & MACB_BIT(IDLE))); - netctl = macb_readl(macb, NCR); - netctl &= ~MACB_BIT(MPE); - macb_writel(macb, NCR, netctl); - rt_sem_release(&macb->mdio_bus_lock); + netctl = macb_readl(macb, NCR); + netctl &= ~MACB_BIT(MPE); + macb_writel(macb, NCR, netctl); + rt_sem_release(&macb->mdio_bus_lock); } static int macb_mdio_read(struct rt_macb_eth *macb, rt_uint8_t reg) { - unsigned long netctl; - unsigned long netstat; - unsigned long frame; + unsigned long netctl; + unsigned long netstat; + unsigned long frame; - rt_sem_take(&macb->mdio_bus_lock, RT_WAITING_FOREVER); - netctl = macb_readl(macb, NCR); - netctl |= MACB_BIT(MPE); - macb_writel(macb, NCR, netctl); + rt_sem_take(&macb->mdio_bus_lock, RT_WAITING_FOREVER); + netctl = macb_readl(macb, NCR); + netctl |= MACB_BIT(MPE); + macb_writel(macb, NCR, netctl); - frame = (MACB_BF(SOF, 1) - | MACB_BF(RW, 2) - | MACB_BF(PHYA, macb->phy_addr) - | MACB_BF(REGA, reg) - | MACB_BF(CODE, 2)); - macb_writel(macb, MAN, frame); + frame = (MACB_BF(SOF, 1) + | MACB_BF(RW, 2) + | MACB_BF(PHYA, macb->phy_addr) + | MACB_BF(REGA, reg) + | MACB_BF(CODE, 2)); + macb_writel(macb, MAN, frame); - do { - netstat = macb_readl(macb, NSR); - } while (!(netstat & MACB_BIT(IDLE))); + do { + netstat = macb_readl(macb, NSR); + } while (!(netstat & MACB_BIT(IDLE))); - frame = macb_readl(macb, MAN); + frame = macb_readl(macb, MAN); - netctl = macb_readl(macb, NCR); - netctl &= ~MACB_BIT(MPE); - macb_writel(macb, NCR, netctl); - rt_sem_release(&macb->mdio_bus_lock); + netctl = macb_readl(macb, NCR); + netctl &= ~MACB_BIT(MPE); + macb_writel(macb, NCR, netctl); + rt_sem_release(&macb->mdio_bus_lock); - return MACB_BFEXT(DATA, frame); + return MACB_BFEXT(DATA, frame); } static void macb_phy_reset(rt_device_t dev) { - int i; - rt_uint16_t status, adv; - struct rt_macb_eth *macb = dev->user_data;; + int i; + rt_uint16_t status, adv; + struct rt_macb_eth *macb = dev->user_data;; - adv = ADVERTISE_CSMA | ADVERTISE_ALL; - macb_mdio_write(macb, MII_ADVERTISE, adv); - rt_kprintf("%s: Starting autonegotiation...\n", dev->parent.name); - macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE - | BMCR_ANRESTART)); + adv = ADVERTISE_CSMA | ADVERTISE_ALL; + macb_mdio_write(macb, MII_ADVERTISE, adv); + rt_kprintf("%s: Starting autonegotiation...\n", dev->parent.name); + macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE + | BMCR_ANRESTART)); - for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) - { - status = macb_mdio_read(macb, MII_BMSR); - if (status & BMSR_ANEGCOMPLETE) - break; - udelay(100); - } + for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) + { + status = macb_mdio_read(macb, MII_BMSR); + if (status & BMSR_ANEGCOMPLETE) + break; + udelay(100); + } - if (status & BMSR_ANEGCOMPLETE) - rt_kprintf("%s: Autonegotiation complete\n", dev->parent.name); - else - rt_kprintf("%s: Autonegotiation timed out (status=0x%04x)\n", - dev->parent.name, status); + if (status & BMSR_ANEGCOMPLETE) + rt_kprintf("%s: Autonegotiation complete\n", dev->parent.name); + else + rt_kprintf("%s: Autonegotiation timed out (status=0x%04x)\n", + dev->parent.name, status); } static int macb_phy_init(rt_device_t dev) { - struct rt_macb_eth *macb = dev->user_data; - rt_uint32_t ncfgr; - rt_uint16_t phy_id, status, adv, lpa; - int media, speed, duplex; - int i; + struct rt_macb_eth *macb = dev->user_data; + rt_uint32_t ncfgr; + rt_uint16_t phy_id, status, adv, lpa; + int media, speed, duplex; + int i; - /* Check if the PHY is up to snuff... */ - phy_id = macb_mdio_read(macb, MII_PHYSID1); - if (phy_id == 0xffff) - { - rt_kprintf("%s: No PHY present\n", dev->parent.name); - return 0; - } + /* Check if the PHY is up to snuff... */ + phy_id = macb_mdio_read(macb, MII_PHYSID1); + if (phy_id == 0xffff) + { + rt_kprintf("%s: No PHY present\n", dev->parent.name); + return 0; + } - status = macb_mdio_read(macb, MII_BMSR); - if (!(status & BMSR_LSTATUS)) - { - /* Try to re-negotiate if we don't have link already. */ - macb_phy_reset(dev); + status = macb_mdio_read(macb, MII_BMSR); + if (!(status & BMSR_LSTATUS)) + { + /* Try to re-negotiate if we don't have link already. */ + macb_phy_reset(dev); - for (i = 0; i < MACB_LINK_TIMEOUT / 100; i++) - { - status = macb_mdio_read(macb, MII_BMSR); - if (status & BMSR_LSTATUS) - break; - udelay(100); - } - } + for (i = 0; i < MACB_LINK_TIMEOUT / 100; i++) + { + status = macb_mdio_read(macb, MII_BMSR); + if (status & BMSR_LSTATUS) + break; + udelay(100); + } + } - if (!(status & BMSR_LSTATUS)) - { - rt_kprintf("%s: link down (status: 0x%04x)\n", - dev->parent.name, status); - return 0; - } - else - { - adv = macb_mdio_read(macb, MII_ADVERTISE); - lpa = macb_mdio_read(macb, MII_LPA); - media = mii_nway_result(lpa & adv); - speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) - ? 1 : 0); - duplex = (media & ADVERTISE_FULL) ? 1 : 0; - rt_kprintf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n", - dev->parent.name, - speed ? "100" : "10", - duplex ? "full" : "half", - lpa); + if (!(status & BMSR_LSTATUS)) + { + rt_kprintf("%s: link down (status: 0x%04x)\n", + dev->parent.name, status); + return 0; + } + else + { + adv = macb_mdio_read(macb, MII_ADVERTISE); + lpa = macb_mdio_read(macb, MII_LPA); + media = mii_nway_result(lpa & adv); + speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) + ? 1 : 0); + duplex = (media & ADVERTISE_FULL) ? 1 : 0; + rt_kprintf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n", + dev->parent.name, + speed ? "100" : "10", + duplex ? "full" : "half", + lpa); - ncfgr = macb_readl(macb, NCFGR); - ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); - if (speed) - ncfgr |= MACB_BIT(SPD); - if (duplex) - ncfgr |= MACB_BIT(FD); - macb_writel(macb, NCFGR, ncfgr); - return 1; - } + ncfgr = macb_readl(macb, NCFGR); + ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); + if (speed) + ncfgr |= MACB_BIT(SPD); + if (duplex) + ncfgr |= MACB_BIT(FD); + macb_writel(macb, NCFGR, ncfgr); + return 1; + } } void macb_update_link(void *param) { - struct rt_macb_eth *macb = (struct rt_macb_eth *)param; - rt_device_t dev = &macb->parent.parent; - int status, status_change = 0; - rt_uint32_t link; - rt_uint32_t media; - rt_uint16_t adv, lpa; + struct rt_macb_eth *macb = (struct rt_macb_eth *)param; + rt_device_t dev = &macb->parent.parent; + int status, status_change = 0; + rt_uint32_t link; + rt_uint32_t media; + rt_uint16_t adv, lpa; - /* Do a fake read */ - status = macb_mdio_read(macb, MII_BMSR); - if (status < 0) - return; + /* Do a fake read */ + status = macb_mdio_read(macb, MII_BMSR); + if (status < 0) + return; - /* Read link and autonegotiation status */ - status = macb_mdio_read(macb, MII_BMSR); - if (status < 0) - return; - - if ((status & BMSR_LSTATUS) == 0) - link = 0; - else - link = 1; + /* Read link and autonegotiation status */ + status = macb_mdio_read(macb, MII_BMSR); + if (status < 0) + return; - if (link != macb->link) - { - macb->link = link; - status_change = 1; - } + if ((status & BMSR_LSTATUS) == 0) + link = 0; + else + link = 1; - if (status_change) - { - if (macb->link) - { - adv = macb_mdio_read(macb, MII_ADVERTISE); - lpa = macb_mdio_read(macb, MII_LPA); - media = mii_nway_result(lpa & adv); - macb->speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) - ? 100 : 10); - macb->duplex = (media & ADVERTISE_FULL) ? 1 : 0; - rt_kprintf("%s: link up (%dMbps/%s-duplex)\n", - dev->parent.name, macb->speed, - DUPLEX_FULL == macb->duplex ? "Full":"Half"); - eth_device_linkchange(&macb->parent, RT_TRUE); - } - else - { - rt_kprintf("%s: link down\n", dev->parent.name); - eth_device_linkchange(&macb->parent, RT_FALSE); - } + if (link != macb->link) + { + macb->link = link; + status_change = 1; + } - } + if (status_change) + { + if (macb->link) + { + adv = macb_mdio_read(macb, MII_ADVERTISE); + lpa = macb_mdio_read(macb, MII_LPA); + media = mii_nway_result(lpa & adv); + macb->speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) + ? 100 : 10); + macb->duplex = (media & ADVERTISE_FULL) ? 1 : 0; + rt_kprintf("%s: link up (%dMbps/%s-duplex)\n", + dev->parent.name, macb->speed, + DUPLEX_FULL == macb->duplex ? "Full":"Half"); + eth_device_linkchange(&macb->parent, RT_TRUE); + } + else + { + rt_kprintf("%s: link down\n", dev->parent.name); + eth_device_linkchange(&macb->parent, RT_FALSE); + } + + } } @@ -434,190 +420,190 @@ void macb_update_link(void *param) static rt_err_t rt_macb_init(rt_device_t dev) { - struct rt_macb_eth *macb = dev->user_data; - unsigned long paddr; - rt_uint32_t hwaddr_bottom; - rt_uint16_t hwaddr_top; - int i; + struct rt_macb_eth *macb = dev->user_data; + unsigned long paddr; + rt_uint32_t hwaddr_bottom; + rt_uint16_t hwaddr_top; + int i; - /* - * macb_halt should have been called at some point before now, - * so we'll assume the controller is idle. - */ + /* + * macb_halt should have been called at some point before now, + * so we'll assume the controller is idle. + */ - /* initialize DMA descriptors */ - paddr = macb->rx_buffer_dma; - for (i = 0; i < MACB_RX_RING_SIZE; i++) - { - if (i == (MACB_RX_RING_SIZE - 1)) - paddr |= RXADDR_WRAP; - macb->rx_ring[i].addr = paddr; - macb->rx_ring[i].ctrl = 0; - paddr += 128; - } - paddr = macb->tx_buffer_dma; - for (i = 0; i < MACB_TX_RING_SIZE; i++) - { - macb->tx_ring[i].addr = paddr; - if (i == (MACB_TX_RING_SIZE - 1)) - macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP; - else - macb->tx_ring[i].ctrl = TXBUF_USED; - paddr += 1536; - } - macb->rx_tail = macb->tx_head = macb->tx_tail = 0; + /* initialize DMA descriptors */ + paddr = macb->rx_buffer_dma; + for (i = 0; i < MACB_RX_RING_SIZE; i++) + { + if (i == (MACB_RX_RING_SIZE - 1)) + paddr |= RXADDR_WRAP; + macb->rx_ring[i].addr = paddr; + macb->rx_ring[i].ctrl = 0; + paddr += 128; + } + paddr = macb->tx_buffer_dma; + for (i = 0; i < MACB_TX_RING_SIZE; i++) + { + macb->tx_ring[i].addr = paddr; + if (i == (MACB_TX_RING_SIZE - 1)) + macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP; + else + macb->tx_ring[i].ctrl = TXBUF_USED; + paddr += 1536; + } + macb->rx_tail = macb->tx_head = macb->tx_tail = 0; - BD_CACHE_WRITEBACK_INVALIDATE(macb->rx_ring, MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); - BD_CACHE_WRITEBACK_INVALIDATE(macb->tx_ring, MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc)); - macb_writel(macb, RBQP, macb->rx_ring_dma); - macb_writel(macb, TBQP, macb->tx_ring_dma); - - /* set hardware address */ - hwaddr_bottom = (*((rt_uint32_t *)macb->dev_addr)); - macb_writel(macb, SA1B, hwaddr_bottom); - hwaddr_top = (*((rt_uint16_t *)(macb->dev_addr + 4))); - macb_writel(macb, SA1T, hwaddr_top); + BD_CACHE_WRITEBACK_INVALIDATE(macb->rx_ring, MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); + BD_CACHE_WRITEBACK_INVALIDATE(macb->tx_ring, MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc)); + macb_writel(macb, RBQP, macb->rx_ring_dma); + macb_writel(macb, TBQP, macb->tx_ring_dma); - - /* choose RMII or MII mode. This depends on the board */ + /* set hardware address */ + hwaddr_bottom = (*((rt_uint32_t *)macb->dev_addr)); + macb_writel(macb, SA1B, hwaddr_bottom); + hwaddr_top = (*((rt_uint16_t *)(macb->dev_addr + 4))); + macb_writel(macb, SA1T, hwaddr_top); + + + /* choose RMII or MII mode. This depends on the board */ #ifdef CONFIG_RMII - macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN)); + macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN)); #else - macb_writel(macb, USRIO, MACB_BIT(CLKEN)); + macb_writel(macb, USRIO, MACB_BIT(CLKEN)); #endif /* CONFIG_RMII */ - if (!macb_phy_init(dev)) - return -RT_ERROR; + if (!macb_phy_init(dev)) + return -RT_ERROR; - /* Enable TX and RX */ - macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(MPE)); - - /* Enable interrupts */ - macb_writel(macb, IER, (MACB_BIT(RCOMP) - | MACB_BIT(RXUBR) - | MACB_BIT(ISR_TUND) - | MACB_BIT(ISR_RLE) - | MACB_BIT(TXERR) - | MACB_BIT(TCOMP) - | MACB_BIT(ISR_ROVR) - | MACB_BIT(HRESP))); - - /* instal interrupt */ - rt_hw_interrupt_install(AT91SAM9260_ID_EMAC, rt_macb_isr, - (void *)macb, "emac"); - rt_hw_interrupt_umask(AT91SAM9260_ID_EMAC); + /* Enable TX and RX */ + macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(MPE)); - rt_timer_init(&macb->timer, "link_timer", - macb_update_link, - (void *)macb, - RT_TICK_PER_SECOND, - RT_TIMER_FLAG_PERIODIC); + /* Enable interrupts */ + macb_writel(macb, IER, (MACB_BIT(RCOMP) + | MACB_BIT(RXUBR) + | MACB_BIT(ISR_TUND) + | MACB_BIT(ISR_RLE) + | MACB_BIT(TXERR) + | MACB_BIT(TCOMP) + | MACB_BIT(ISR_ROVR) + | MACB_BIT(HRESP))); - rt_timer_start(&macb->timer); - - return RT_EOK; + /* instal interrupt */ + rt_hw_interrupt_install(AT91SAM9260_ID_EMAC, rt_macb_isr, + (void *)macb, "emac"); + rt_hw_interrupt_umask(AT91SAM9260_ID_EMAC); + + rt_timer_init(&macb->timer, "link_timer", + macb_update_link, + (void *)macb, + RT_TICK_PER_SECOND, + RT_TIMER_FLAG_PERIODIC); + + rt_timer_start(&macb->timer); + + return RT_EOK; } static rt_err_t rt_macb_open(rt_device_t dev, rt_uint16_t oflag) { - return RT_EOK; + return RT_EOK; } static rt_err_t rt_macb_close(rt_device_t dev) { - return RT_EOK; + return RT_EOK; } static rt_size_t rt_macb_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_size_t rt_macb_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_err_t rt_macb_control(rt_device_t dev, int cmd, void *args) { - switch(cmd) - { - case NIOCTL_GADDR: - /* get mac address */ - if(args) rt_memcpy(args, macb_device.dev_addr, 6); - else return -RT_ERROR; - break; + switch(cmd) + { + case NIOCTL_GADDR: + /* get mac address */ + if(args) rt_memcpy(args, macb_device.dev_addr, 6); + else return -RT_ERROR; + break; - default : - break; - } + default : + break; + } - return RT_EOK; + return RT_EOK; } static void macb_tx(struct rt_macb_eth *macb) { - unsigned int tail; - unsigned int head; - rt_uint32_t status; + unsigned int tail; + unsigned int head; + rt_uint32_t status; - status = macb_readl(macb, TSR); - macb_writel(macb, TSR, status); + status = macb_readl(macb, TSR); + macb_writel(macb, TSR, status); - /*rt_kprintf("macb_tx status = %02lx\n", - (unsigned long)status);*/ + /*rt_kprintf("macb_tx status = %02lx\n", + (unsigned long)status);*/ - if (status & (MACB_BIT(UND) | MACB_BIT(TSR_RLE))) - { - int i; - rt_kprintf("%s: TX %s, resetting buffers\n", - macb->parent.parent.parent.name, status & MACB_BIT(UND) ? - "underrun" : "retry limit exceeded"); + if (status & (MACB_BIT(UND) | MACB_BIT(TSR_RLE))) + { + int i; + rt_kprintf("%s: TX %s, resetting buffers\n", + macb->parent.parent.parent.name, status & MACB_BIT(UND) ? + "underrun" : "retry limit exceeded"); - /* Transfer ongoing, disable transmitter, to avoid confusion */ - if (status & MACB_BIT(TGO)) - macb_writel(macb, NCR, macb_readl(macb, NCR) & ~MACB_BIT(TE)); + /* Transfer ongoing, disable transmitter, to avoid confusion */ + if (status & MACB_BIT(TGO)) + macb_writel(macb, NCR, macb_readl(macb, NCR) & ~MACB_BIT(TE)); - head = macb->tx_head; + head = macb->tx_head; - /*Mark all the buffer as used to avoid sending a lost buffer*/ - for (i = 0; i < MACB_TX_RING_SIZE; i++) - macb->tx_ring[i].ctrl = MACB_BIT(TX_USED); + /*Mark all the buffer as used to avoid sending a lost buffer*/ + for (i = 0; i < MACB_TX_RING_SIZE; i++) + macb->tx_ring[i].ctrl = MACB_BIT(TX_USED); - /* free transmit buffer in upper layer*/ + /* free transmit buffer in upper layer*/ - macb->tx_head = macb->tx_tail = 0; + macb->tx_head = macb->tx_tail = 0; - /* Enable the transmitter again */ - if (status & MACB_BIT(TGO)) - macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TE)); - } + /* Enable the transmitter again */ + if (status & MACB_BIT(TGO)) + macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TE)); + } - if (!(status & MACB_BIT(COMP))) - /* - * This may happen when a buffer becomes complete - * between reading the ISR and scanning the - * descriptors. Nothing to worry about. - */ - return; + if (!(status & MACB_BIT(COMP))) + /* + * This may happen when a buffer becomes complete + * between reading the ISR and scanning the + * descriptors. Nothing to worry about. + */ + return; - head = macb->tx_head; - for (tail = macb->tx_tail; tail != head; tail = NEXT_TX(tail)) - { - rt_uint32_t bufstat; + head = macb->tx_head; + for (tail = macb->tx_tail; tail != head; tail = NEXT_TX(tail)) + { + rt_uint32_t bufstat; - bufstat = macb->tx_ring[tail].ctrl; + bufstat = macb->tx_ring[tail].ctrl; - if (!(bufstat & MACB_BIT(TX_USED))) - break; - } + if (!(bufstat & MACB_BIT(TX_USED))) + break; + } - macb->tx_tail = tail; - if ((macb->tx_stop == 1) && - TX_BUFFS_AVAIL(macb) > MACB_TX_WAKEUP_THRESH) - rt_sem_release(&macb->tx_ack); + macb->tx_tail = tail; + if ((macb->tx_stop == 1) && + TX_BUFFS_AVAIL(macb) > MACB_TX_WAKEUP_THRESH) + rt_sem_release(&macb->tx_ack); } @@ -625,286 +611,286 @@ static void macb_tx(struct rt_macb_eth *macb) /* transmit packet. */ rt_err_t rt_macb_tx( rt_device_t dev, struct pbuf* p) { - unsigned long ctrl; - struct pbuf* q; - rt_uint8_t* bufptr; - rt_uint32_t mapping; - struct rt_macb_eth *macb = dev->user_data; - unsigned int tx_head = macb->tx_head; + unsigned long ctrl; + struct pbuf* q; + rt_uint8_t* bufptr; + rt_uint32_t mapping; + struct rt_macb_eth *macb = dev->user_data; + unsigned int tx_head = macb->tx_head; - rt_sem_take(&macb->tx_lock, RT_WAITING_FOREVER); - if (TX_BUFFS_AVAIL(macb) < 1) - { - rt_sem_release(&macb->tx_lock); - rt_kprintf("Tx Ring full!\n"); - rt_kprintf("tx_head = %u, tx_tail = %u\n", - macb->tx_head, macb->tx_tail); - return -RT_ERROR; - } + rt_sem_take(&macb->tx_lock, RT_WAITING_FOREVER); + if (TX_BUFFS_AVAIL(macb) < 1) + { + rt_sem_release(&macb->tx_lock); + rt_kprintf("Tx Ring full!\n"); + rt_kprintf("tx_head = %u, tx_tail = %u\n", + macb->tx_head, macb->tx_tail); + return -RT_ERROR; + } - macb->tx_stop = 0; + macb->tx_stop = 0; - ctrl = p->tot_len & TXBUF_FRMLEN_MASK; - ctrl |= TXBUF_FRAME_END; - if (tx_head == (MACB_TX_RING_SIZE - 1)) - { - ctrl |= TXBUF_WRAP; - } + ctrl = p->tot_len & TXBUF_FRMLEN_MASK; + ctrl |= TXBUF_FRAME_END; + if (tx_head == (MACB_TX_RING_SIZE - 1)) + { + ctrl |= TXBUF_WRAP; + } #if defined(MACB_TX_SRAM) - bufptr = macb->tx_buffer + tx_head * 1536; + bufptr = macb->tx_buffer + tx_head * 1536; #else - mapping = (unsigned long)macb->tx_buffer + tx_head * 1536; - bufptr = (rt_uint8_t *)mapping; + mapping = (unsigned long)macb->tx_buffer + tx_head * 1536; + bufptr = (rt_uint8_t *)mapping; #endif - for (q = p; q != NULL; q = q->next) - { - memcpy(bufptr, q->payload, q->len); - bufptr += q->len; - } + for (q = p; q != NULL; q = q->next) + { + memcpy(bufptr, q->payload, q->len); + bufptr += q->len; + } #if !defined(MACB_TX_SRAM) - EMAC_CACHE_WRITEBACK(mapping, p->tot_len); + EMAC_CACHE_WRITEBACK(mapping, p->tot_len); #endif - macb->tx_ring[tx_head].ctrl = ctrl; - BD_CACHE_WRITEBACK_INVALIDATE(&macb->tx_ring[tx_head], sizeof(struct macb_dma_desc)); - tx_head = NEXT_TX(tx_head); - macb->tx_head = tx_head; - macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TSTART)); - macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TSTART)); + macb->tx_ring[tx_head].ctrl = ctrl; + BD_CACHE_WRITEBACK_INVALIDATE(&macb->tx_ring[tx_head], sizeof(struct macb_dma_desc)); + tx_head = NEXT_TX(tx_head); + macb->tx_head = tx_head; + macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TSTART)); + macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TSTART)); - if (TX_BUFFS_AVAIL(macb) < 1) - { - macb->tx_stop = 1; - rt_sem_take(&macb->tx_ack, RT_WAITING_FOREVER); - } - rt_sem_release(&macb->tx_lock); + if (TX_BUFFS_AVAIL(macb) < 1) + { + macb->tx_stop = 1; + rt_sem_take(&macb->tx_ack, RT_WAITING_FOREVER); + } + rt_sem_release(&macb->tx_lock); - return RT_EOK; + return RT_EOK; } static void reclaim_rx_buffers(struct rt_macb_eth *macb, - unsigned int new_tail) + unsigned int new_tail) { - unsigned int i; + unsigned int i; - i = macb->rx_tail; - while (i > new_tail) - { - macb->rx_ring[i].addr &= ~RXADDR_USED; - i++; - if (i > MACB_RX_RING_SIZE) - i = 0; - } + i = macb->rx_tail; + while (i > new_tail) + { + macb->rx_ring[i].addr &= ~RXADDR_USED; + i++; + if (i > MACB_RX_RING_SIZE) + i = 0; + } - while (i < new_tail) - { - macb->rx_ring[i].addr &= ~RXADDR_USED; - i++; - } + while (i < new_tail) + { + macb->rx_ring[i].addr &= ~RXADDR_USED; + i++; + } - macb->rx_tail = new_tail; + macb->rx_tail = new_tail; } /* reception packet. */ struct pbuf *rt_macb_rx(rt_device_t dev) { - struct rt_macb_eth *macb = dev->user_data; - struct pbuf* p = RT_NULL; - rt_uint32_t len; - unsigned int rx_tail = macb->rx_tail; - void *buffer; - int wrapped = 0; - rt_uint32_t status; + struct rt_macb_eth *macb = dev->user_data; + struct pbuf* p = RT_NULL; + rt_uint32_t len; + unsigned int rx_tail = macb->rx_tail; + void *buffer; + int wrapped = 0; + rt_uint32_t status; - rt_sem_take(&macb->rx_lock, RT_WAITING_FOREVER); - for (;;) - { - if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED)) - break; + rt_sem_take(&macb->rx_lock, RT_WAITING_FOREVER); + for (;;) + { + if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED)) + break; - status = macb->rx_ring[rx_tail].ctrl; - if (status & RXBUF_FRAME_START) - { - if (rx_tail != macb->rx_tail) - reclaim_rx_buffers(macb, rx_tail); - wrapped = 0; - } + status = macb->rx_ring[rx_tail].ctrl; + if (status & RXBUF_FRAME_START) + { + if (rx_tail != macb->rx_tail) + reclaim_rx_buffers(macb, rx_tail); + wrapped = 0; + } - if (status & RXBUF_FRAME_END) - { - buffer = (void *)((unsigned int)macb->rx_buffer + 128 * macb->rx_tail); - len = status & RXBUF_FRMLEN_MASK; - p = pbuf_alloc(PBUF_LINK, len, PBUF_RAM); - if (!p) - { - rt_kprintf("alloc pbuf failed\n"); - break; - } - if (wrapped) - { - unsigned int headlen, taillen; + if (status & RXBUF_FRAME_END) + { + buffer = (void *)((unsigned int)macb->rx_buffer + 128 * macb->rx_tail); + len = status & RXBUF_FRMLEN_MASK; + p = pbuf_alloc(PBUF_LINK, len, PBUF_RAM); + if (!p) + { + rt_kprintf("alloc pbuf failed\n"); + break; + } + if (wrapped) + { + unsigned int headlen, taillen; - headlen = 128 * (MACB_RX_RING_SIZE - - macb->rx_tail); - taillen = len - headlen; - EMAC_CACHE_INVALIDATE(buffer, headlen); - EMAC_CACHE_INVALIDATE(macb->rx_buffer, taillen); - memcpy((void *)p->payload, buffer, headlen); - memcpy((void *)((unsigned int)p->payload + headlen), - macb->rx_buffer, taillen); - } - else - { - EMAC_CACHE_INVALIDATE(buffer, len); - memcpy((void *)p->payload, buffer, p->len); - } - - if (++rx_tail >= MACB_RX_RING_SIZE) - rx_tail = 0; - reclaim_rx_buffers(macb, rx_tail); - break; - } - else - { - if (++rx_tail >= MACB_RX_RING_SIZE) - { - wrapped = 1; - rx_tail = 0; - } - } - } + headlen = 128 * (MACB_RX_RING_SIZE + - macb->rx_tail); + taillen = len - headlen; + EMAC_CACHE_INVALIDATE(buffer, headlen); + EMAC_CACHE_INVALIDATE(macb->rx_buffer, taillen); + memcpy((void *)p->payload, buffer, headlen); + memcpy((void *)((unsigned int)p->payload + headlen), + macb->rx_buffer, taillen); + } + else + { + EMAC_CACHE_INVALIDATE(buffer, len); + memcpy((void *)p->payload, buffer, p->len); + } - rt_sem_release(&macb->rx_lock); + if (++rx_tail >= MACB_RX_RING_SIZE) + rx_tail = 0; + reclaim_rx_buffers(macb, rx_tail); + break; + } + else + { + if (++rx_tail >= MACB_RX_RING_SIZE) + { + wrapped = 1; + rx_tail = 0; + } + } + } - return p; + rt_sem_release(&macb->rx_lock); + + return p; } void macb_gpio_init() { - /* Pins used for MII and RMII */ - AT91C_BASE_PIOA->PIO_PDR, (1 << 19)|(1 << 17)|(1 << 14)|(1 << 15)|(1 << 18)|(1 << 16)|(1 << 12)|(1 << 13)|(1 << 21)|(1 << 20); - AT91C_BASE_PIOA->PIO_ASR, (1 << 19)|(1 << 17)|(1 << 14)|(1 << 15)|(1 << 18)|(1 << 16)|(1 << 12)|(1 << 13)|(1 << 21)|(1 << 20); + /* Pins used for MII and RMII */ + AT91C_BASE_PIOA->PIO_PDR, (1 << 19)|(1 << 17)|(1 << 14)|(1 << 15)|(1 << 18)|(1 << 16)|(1 << 12)|(1 << 13)|(1 << 21)|(1 << 20); + AT91C_BASE_PIOA->PIO_ASR, (1 << 19)|(1 << 17)|(1 << 14)|(1 << 15)|(1 << 18)|(1 << 16)|(1 << 12)|(1 << 13)|(1 << 21)|(1 << 20); #ifndef GONFIG_RMII - AT91C_BASE_PIOA->PIO_PDR, (1 << 22)|(1 << 23)|(1 << 24)|(1 << 25)|(1 << 26)|(1 << 27)|(1 << 28)|(1 << 29); - AT91C_BASE_PIOA->PIO_ASR, (1 << 22)|(1 << 23)|(1 << 24)|(1 << 25)|(1 << 26)|(1 << 27)|(1 << 28)|(1 << 29); + AT91C_BASE_PIOA->PIO_PDR, (1 << 22)|(1 << 23)|(1 << 24)|(1 << 25)|(1 << 26)|(1 << 27)|(1 << 28)|(1 << 29); + AT91C_BASE_PIOA->PIO_ASR, (1 << 22)|(1 << 23)|(1 << 24)|(1 << 25)|(1 << 26)|(1 << 27)|(1 << 28)|(1 << 29); #endif } rt_err_t macb_initialize() { - struct rt_macb_eth *macb = &macb_device; - unsigned long macb_hz; - rt_uint32_t ncfgr; - + struct rt_macb_eth *macb = &macb_device; + unsigned long macb_hz; + rt_uint32_t ncfgr; + #if defined(MACB_TX_SRAM) - macb->tx_ring_dma = AT91SAM9260_SRAM0_BASE; - macb->tx_ring = (struct macb_dma_desc *)AT91SAM9260_SRAM0_VIRT_BASE; - macb->tx_buffer = (char *) macb->tx_ring + TX_RING_BYTES; - macb->tx_buffer_dma = macb->tx_ring_dma + TX_RING_BYTES; + macb->tx_ring_dma = AT91SAM9260_SRAM0_BASE; + macb->tx_ring = (struct macb_dma_desc *)AT91SAM9260_SRAM0_VIRT_BASE; + macb->tx_buffer = (char *) macb->tx_ring + TX_RING_BYTES; + macb->tx_buffer_dma = macb->tx_ring_dma + TX_RING_BYTES; #else - macb->tx_ring = rt_malloc(MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); - if (macb->tx_ring == RT_NULL) - goto err1; - EMAC_CACHE_INVALIDATE(macb->tx_ring, MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc)); - macb->tx_ring_dma = emac_virt_to_phys((unsigned long)macb->tx_ring); - macb->tx_ring = (struct macb_dma_desc *)MMU_NOCACHE_ADDR((unsigned long)macb->tx_ring); - macb->tx_buffer = rt_malloc(MACB_TX_BUFFER_SIZE); - if (macb->tx_buffer == RT_NULL) - goto err2; - macb->tx_buffer_dma = emac_virt_to_phys((unsigned long)macb->tx_buffer); + macb->tx_ring = rt_malloc(MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); + if (macb->tx_ring == RT_NULL) + goto err1; + EMAC_CACHE_INVALIDATE(macb->tx_ring, MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc)); + macb->tx_ring_dma = emac_virt_to_phys((unsigned long)macb->tx_ring); + macb->tx_ring = (struct macb_dma_desc *)MMU_NOCACHE_ADDR((unsigned long)macb->tx_ring); + macb->tx_buffer = rt_malloc(MACB_TX_BUFFER_SIZE); + if (macb->tx_buffer == RT_NULL) + goto err2; + macb->tx_buffer_dma = emac_virt_to_phys((unsigned long)macb->tx_buffer); #endif - macb->rx_ring = rt_malloc(MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); - if (macb->rx_ring == RT_NULL) - goto err3; - EMAC_CACHE_INVALIDATE(macb->rx_ring, MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); - macb->rx_ring_dma = emac_virt_to_phys((unsigned long)macb->rx_ring); - macb->rx_ring = (struct macb_dma_desc *)MMU_NOCACHE_ADDR((unsigned long)macb->rx_ring); - macb->rx_buffer = rt_malloc(MACB_RX_BUFFER_SIZE); - if (macb->rx_buffer == RT_NULL) - goto err4; - macb->rx_buffer_dma = emac_virt_to_phys((unsigned long)macb->rx_buffer); + macb->rx_ring = rt_malloc(MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); + if (macb->rx_ring == RT_NULL) + goto err3; + EMAC_CACHE_INVALIDATE(macb->rx_ring, MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); + macb->rx_ring_dma = emac_virt_to_phys((unsigned long)macb->rx_ring); + macb->rx_ring = (struct macb_dma_desc *)MMU_NOCACHE_ADDR((unsigned long)macb->rx_ring); + macb->rx_buffer = rt_malloc(MACB_RX_BUFFER_SIZE); + if (macb->rx_buffer == RT_NULL) + goto err4; + macb->rx_buffer_dma = emac_virt_to_phys((unsigned long)macb->rx_buffer); - macb->tx_pending = DEF_TX_RING_PENDING; + macb->tx_pending = DEF_TX_RING_PENDING; - macb->regs = AT91SAM9260_BASE_EMAC; - macb->phy_addr = 0x00; - - /* - * Do some basic initialization so that we at least can talk - * to the PHY - */ - macb_hz = clk_get_rate(clk_get("mck")); - if (macb_hz < 20000000) - ncfgr = MACB_BF(CLK, MACB_CLK_DIV8); - else if (macb_hz < 40000000) - ncfgr = MACB_BF(CLK, MACB_CLK_DIV16); - else if (macb_hz < 80000000) - ncfgr = MACB_BF(CLK, MACB_CLK_DIV32); - else - ncfgr = MACB_BF(CLK, MACB_CLK_DIV64); + macb->regs = AT91SAM9260_BASE_EMAC; + macb->phy_addr = 0x00; - macb_writel(macb, NCFGR, ncfgr); + /* + * Do some basic initialization so that we at least can talk + * to the PHY + */ + macb_hz = clk_get_rate(clk_get("mck")); + if (macb_hz < 20000000) + ncfgr = MACB_BF(CLK, MACB_CLK_DIV8); + else if (macb_hz < 40000000) + ncfgr = MACB_BF(CLK, MACB_CLK_DIV16); + else if (macb_hz < 80000000) + ncfgr = MACB_BF(CLK, MACB_CLK_DIV32); + else + ncfgr = MACB_BF(CLK, MACB_CLK_DIV64); - macb->link = 0; + macb_writel(macb, NCFGR, ncfgr); - return RT_EOK; + macb->link = 0; + + return RT_EOK; err4: - rt_free(macb->rx_ring); - macb->rx_ring = RT_NULL; + rt_free(macb->rx_ring); + macb->rx_ring = RT_NULL; err3: #if !defined(MACB_TX_SRAM) - rt_free(macb->tx_buffer); - macb->tx_buffer = RT_NULL; + rt_free(macb->tx_buffer); + macb->tx_buffer = RT_NULL; err2: - rt_free(macb->tx_ring); - macb->tx_ring = RT_NULL; + rt_free(macb->tx_ring); + macb->tx_ring = RT_NULL; err1: #endif - return -RT_ENOMEM; + return -RT_ENOMEM; } int rt_hw_macb_init(void) { - rt_err_t ret; - AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_EMAC; //enable macb clock - macb_gpio_init(); - rt_memset(&macb_device, 0, sizeof(macb_device)); - ret = macb_initialize(); - if (ret != RT_EOK) - { - rt_kprintf("AT91 EMAC initialized failed\n"); - return -1; - } - rt_sem_init(&macb_device.tx_ack, "tx_ack", 0, RT_IPC_FLAG_FIFO); - rt_sem_init(&macb_device.tx_lock, "tx_lock", 1, RT_IPC_FLAG_FIFO); - rt_sem_init(&macb_device.rx_lock, "rx_lock", 1, RT_IPC_FLAG_FIFO); + rt_err_t ret; + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_EMAC; //enable macb clock + macb_gpio_init(); + rt_memset(&macb_device, 0, sizeof(macb_device)); + ret = macb_initialize(); + if (ret != RT_EOK) + { + rt_kprintf("AT91 EMAC initialized failed\n"); + return -1; + } + rt_sem_init(&macb_device.tx_ack, "tx_ack", 0, RT_IPC_FLAG_FIFO); + rt_sem_init(&macb_device.tx_lock, "tx_lock", 1, RT_IPC_FLAG_FIFO); + rt_sem_init(&macb_device.rx_lock, "rx_lock", 1, RT_IPC_FLAG_FIFO); - macb_device.dev_addr[0] = 0x00; - macb_device.dev_addr[1] = 0x60; - macb_device.dev_addr[2] = 0x6E; - macb_device.dev_addr[3] = 0x11; - macb_device.dev_addr[4] = 0x22; - macb_device.dev_addr[5] = 0x33; - - macb_device.parent.parent.init = rt_macb_init; - macb_device.parent.parent.open = rt_macb_open; - macb_device.parent.parent.close = rt_macb_close; - macb_device.parent.parent.read = rt_macb_read; - macb_device.parent.parent.write = rt_macb_write; - macb_device.parent.parent.control = rt_macb_control; - macb_device.parent.parent.user_data = &macb_device; + macb_device.dev_addr[0] = 0x00; + macb_device.dev_addr[1] = 0x60; + macb_device.dev_addr[2] = 0x6E; + macb_device.dev_addr[3] = 0x11; + macb_device.dev_addr[4] = 0x22; + macb_device.dev_addr[5] = 0x33; - macb_device.parent.eth_rx = rt_macb_rx; - macb_device.parent.eth_tx = rt_macb_tx; + macb_device.parent.parent.init = rt_macb_init; + macb_device.parent.parent.open = rt_macb_open; + macb_device.parent.parent.close = rt_macb_close; + macb_device.parent.parent.read = rt_macb_read; + macb_device.parent.parent.write = rt_macb_write; + macb_device.parent.parent.control = rt_macb_control; + macb_device.parent.parent.user_data = &macb_device; - rt_sem_init(&macb_device.mdio_bus_lock, "mdio_bus_lock", 1, RT_IPC_FLAG_FIFO); + macb_device.parent.eth_rx = rt_macb_rx; + macb_device.parent.eth_tx = rt_macb_tx; - eth_device_init(&(macb_device.parent), "e0"); + rt_sem_init(&macb_device.mdio_bus_lock, "mdio_bus_lock", 1, RT_IPC_FLAG_FIFO); - return 0; + eth_device_init(&(macb_device.parent), "e0"); + + return 0; } INIT_DEVICE_EXPORT(rt_hw_macb_init); diff --git a/bsp/at91sam9g45/drivers/macb.h b/bsp/at91sam9g45/drivers/macb.h index 9df2883534..ed2ad390b7 100644 --- a/bsp/at91sam9g45/drivers/macb.h +++ b/bsp/at91sam9g45/drivers/macb.h @@ -1,21 +1,7 @@ /* - * File : macb.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -26,319 +12,319 @@ #include /* MACB register offsets */ -#define MACB_NCR 0x0000 -#define MACB_NCFGR 0x0004 -#define MACB_NSR 0x0008 -#define MACB_TSR 0x0014 -#define MACB_RBQP 0x0018 -#define MACB_TBQP 0x001c -#define MACB_RSR 0x0020 -#define MACB_ISR 0x0024 -#define MACB_IER 0x0028 -#define MACB_IDR 0x002c -#define MACB_IMR 0x0030 -#define MACB_MAN 0x0034 -#define MACB_PTR 0x0038 -#define MACB_PFR 0x003c -#define MACB_FTO 0x0040 -#define MACB_SCF 0x0044 -#define MACB_MCF 0x0048 -#define MACB_FRO 0x004c -#define MACB_FCSE 0x0050 -#define MACB_ALE 0x0054 -#define MACB_DTF 0x0058 -#define MACB_LCOL 0x005c -#define MACB_EXCOL 0x0060 -#define MACB_TUND 0x0064 -#define MACB_CSE 0x0068 -#define MACB_RRE 0x006c -#define MACB_ROVR 0x0070 -#define MACB_RSE 0x0074 -#define MACB_ELE 0x0078 -#define MACB_RJA 0x007c -#define MACB_USF 0x0080 -#define MACB_STE 0x0084 -#define MACB_RLE 0x0088 -#define MACB_TPF 0x008c -#define MACB_HRB 0x0090 -#define MACB_HRT 0x0094 -#define MACB_SA1B 0x0098 -#define MACB_SA1T 0x009c -#define MACB_SA2B 0x00a0 -#define MACB_SA2T 0x00a4 -#define MACB_SA3B 0x00a8 -#define MACB_SA3T 0x00ac -#define MACB_SA4B 0x00b0 -#define MACB_SA4T 0x00b4 -#define MACB_TID 0x00b8 -#define MACB_TPQ 0x00bc -#define MACB_USRIO 0x00c0 -#define MACB_WOL 0x00c4 +#define MACB_NCR 0x0000 +#define MACB_NCFGR 0x0004 +#define MACB_NSR 0x0008 +#define MACB_TSR 0x0014 +#define MACB_RBQP 0x0018 +#define MACB_TBQP 0x001c +#define MACB_RSR 0x0020 +#define MACB_ISR 0x0024 +#define MACB_IER 0x0028 +#define MACB_IDR 0x002c +#define MACB_IMR 0x0030 +#define MACB_MAN 0x0034 +#define MACB_PTR 0x0038 +#define MACB_PFR 0x003c +#define MACB_FTO 0x0040 +#define MACB_SCF 0x0044 +#define MACB_MCF 0x0048 +#define MACB_FRO 0x004c +#define MACB_FCSE 0x0050 +#define MACB_ALE 0x0054 +#define MACB_DTF 0x0058 +#define MACB_LCOL 0x005c +#define MACB_EXCOL 0x0060 +#define MACB_TUND 0x0064 +#define MACB_CSE 0x0068 +#define MACB_RRE 0x006c +#define MACB_ROVR 0x0070 +#define MACB_RSE 0x0074 +#define MACB_ELE 0x0078 +#define MACB_RJA 0x007c +#define MACB_USF 0x0080 +#define MACB_STE 0x0084 +#define MACB_RLE 0x0088 +#define MACB_TPF 0x008c +#define MACB_HRB 0x0090 +#define MACB_HRT 0x0094 +#define MACB_SA1B 0x0098 +#define MACB_SA1T 0x009c +#define MACB_SA2B 0x00a0 +#define MACB_SA2T 0x00a4 +#define MACB_SA3B 0x00a8 +#define MACB_SA3T 0x00ac +#define MACB_SA4B 0x00b0 +#define MACB_SA4T 0x00b4 +#define MACB_TID 0x00b8 +#define MACB_TPQ 0x00bc +#define MACB_USRIO 0x00c0 +#define MACB_WOL 0x00c4 /* Bitfields in NCR */ -#define MACB_LB_OFFSET 0 -#define MACB_LB_SIZE 1 -#define MACB_LLB_OFFSET 1 -#define MACB_LLB_SIZE 1 -#define MACB_RE_OFFSET 2 -#define MACB_RE_SIZE 1 -#define MACB_TE_OFFSET 3 -#define MACB_TE_SIZE 1 -#define MACB_MPE_OFFSET 4 -#define MACB_MPE_SIZE 1 -#define MACB_CLRSTAT_OFFSET 5 -#define MACB_CLRSTAT_SIZE 1 -#define MACB_INCSTAT_OFFSET 6 -#define MACB_INCSTAT_SIZE 1 -#define MACB_WESTAT_OFFSET 7 -#define MACB_WESTAT_SIZE 1 -#define MACB_BP_OFFSET 8 -#define MACB_BP_SIZE 1 -#define MACB_TSTART_OFFSET 9 -#define MACB_TSTART_SIZE 1 -#define MACB_THALT_OFFSET 10 -#define MACB_THALT_SIZE 1 -#define MACB_NCR_TPF_OFFSET 11 -#define MACB_NCR_TPF_SIZE 1 -#define MACB_TZQ_OFFSET 12 -#define MACB_TZQ_SIZE 1 +#define MACB_LB_OFFSET 0 +#define MACB_LB_SIZE 1 +#define MACB_LLB_OFFSET 1 +#define MACB_LLB_SIZE 1 +#define MACB_RE_OFFSET 2 +#define MACB_RE_SIZE 1 +#define MACB_TE_OFFSET 3 +#define MACB_TE_SIZE 1 +#define MACB_MPE_OFFSET 4 +#define MACB_MPE_SIZE 1 +#define MACB_CLRSTAT_OFFSET 5 +#define MACB_CLRSTAT_SIZE 1 +#define MACB_INCSTAT_OFFSET 6 +#define MACB_INCSTAT_SIZE 1 +#define MACB_WESTAT_OFFSET 7 +#define MACB_WESTAT_SIZE 1 +#define MACB_BP_OFFSET 8 +#define MACB_BP_SIZE 1 +#define MACB_TSTART_OFFSET 9 +#define MACB_TSTART_SIZE 1 +#define MACB_THALT_OFFSET 10 +#define MACB_THALT_SIZE 1 +#define MACB_NCR_TPF_OFFSET 11 +#define MACB_NCR_TPF_SIZE 1 +#define MACB_TZQ_OFFSET 12 +#define MACB_TZQ_SIZE 1 /* Bitfields in NCFGR */ -#define MACB_SPD_OFFSET 0 -#define MACB_SPD_SIZE 1 -#define MACB_FD_OFFSET 1 -#define MACB_FD_SIZE 1 -#define MACB_BIT_RATE_OFFSET 2 -#define MACB_BIT_RATE_SIZE 1 -#define MACB_JFRAME_OFFSET 3 -#define MACB_JFRAME_SIZE 1 -#define MACB_CAF_OFFSET 4 -#define MACB_CAF_SIZE 1 -#define MACB_NBC_OFFSET 5 -#define MACB_NBC_SIZE 1 -#define MACB_NCFGR_MTI_OFFSET 6 -#define MACB_NCFGR_MTI_SIZE 1 -#define MACB_UNI_OFFSET 7 -#define MACB_UNI_SIZE 1 -#define MACB_BIG_OFFSET 8 -#define MACB_BIG_SIZE 1 -#define MACB_EAE_OFFSET 9 -#define MACB_EAE_SIZE 1 -#define MACB_CLK_OFFSET 10 -#define MACB_CLK_SIZE 2 -#define MACB_RTY_OFFSET 12 -#define MACB_RTY_SIZE 1 -#define MACB_PAE_OFFSET 13 -#define MACB_PAE_SIZE 1 -#define MACB_RBOF_OFFSET 14 -#define MACB_RBOF_SIZE 2 -#define MACB_RLCE_OFFSET 16 -#define MACB_RLCE_SIZE 1 -#define MACB_DRFCS_OFFSET 17 -#define MACB_DRFCS_SIZE 1 -#define MACB_EFRHD_OFFSET 18 -#define MACB_EFRHD_SIZE 1 -#define MACB_IRXFCS_OFFSET 19 -#define MACB_IRXFCS_SIZE 1 +#define MACB_SPD_OFFSET 0 +#define MACB_SPD_SIZE 1 +#define MACB_FD_OFFSET 1 +#define MACB_FD_SIZE 1 +#define MACB_BIT_RATE_OFFSET 2 +#define MACB_BIT_RATE_SIZE 1 +#define MACB_JFRAME_OFFSET 3 +#define MACB_JFRAME_SIZE 1 +#define MACB_CAF_OFFSET 4 +#define MACB_CAF_SIZE 1 +#define MACB_NBC_OFFSET 5 +#define MACB_NBC_SIZE 1 +#define MACB_NCFGR_MTI_OFFSET 6 +#define MACB_NCFGR_MTI_SIZE 1 +#define MACB_UNI_OFFSET 7 +#define MACB_UNI_SIZE 1 +#define MACB_BIG_OFFSET 8 +#define MACB_BIG_SIZE 1 +#define MACB_EAE_OFFSET 9 +#define MACB_EAE_SIZE 1 +#define MACB_CLK_OFFSET 10 +#define MACB_CLK_SIZE 2 +#define MACB_RTY_OFFSET 12 +#define MACB_RTY_SIZE 1 +#define MACB_PAE_OFFSET 13 +#define MACB_PAE_SIZE 1 +#define MACB_RBOF_OFFSET 14 +#define MACB_RBOF_SIZE 2 +#define MACB_RLCE_OFFSET 16 +#define MACB_RLCE_SIZE 1 +#define MACB_DRFCS_OFFSET 17 +#define MACB_DRFCS_SIZE 1 +#define MACB_EFRHD_OFFSET 18 +#define MACB_EFRHD_SIZE 1 +#define MACB_IRXFCS_OFFSET 19 +#define MACB_IRXFCS_SIZE 1 /* Bitfields in NSR */ -#define MACB_NSR_LINK_OFFSET 0 -#define MACB_NSR_LINK_SIZE 1 -#define MACB_MDIO_OFFSET 1 -#define MACB_MDIO_SIZE 1 -#define MACB_IDLE_OFFSET 2 -#define MACB_IDLE_SIZE 1 +#define MACB_NSR_LINK_OFFSET 0 +#define MACB_NSR_LINK_SIZE 1 +#define MACB_MDIO_OFFSET 1 +#define MACB_MDIO_SIZE 1 +#define MACB_IDLE_OFFSET 2 +#define MACB_IDLE_SIZE 1 /* Bitfields in TSR */ -#define MACB_UBR_OFFSET 0 -#define MACB_UBR_SIZE 1 -#define MACB_COL_OFFSET 1 -#define MACB_COL_SIZE 1 -#define MACB_TSR_RLE_OFFSET 2 -#define MACB_TSR_RLE_SIZE 1 -#define MACB_TGO_OFFSET 3 -#define MACB_TGO_SIZE 1 -#define MACB_BEX_OFFSET 4 -#define MACB_BEX_SIZE 1 -#define MACB_COMP_OFFSET 5 -#define MACB_COMP_SIZE 1 -#define MACB_UND_OFFSET 6 -#define MACB_UND_SIZE 1 +#define MACB_UBR_OFFSET 0 +#define MACB_UBR_SIZE 1 +#define MACB_COL_OFFSET 1 +#define MACB_COL_SIZE 1 +#define MACB_TSR_RLE_OFFSET 2 +#define MACB_TSR_RLE_SIZE 1 +#define MACB_TGO_OFFSET 3 +#define MACB_TGO_SIZE 1 +#define MACB_BEX_OFFSET 4 +#define MACB_BEX_SIZE 1 +#define MACB_COMP_OFFSET 5 +#define MACB_COMP_SIZE 1 +#define MACB_UND_OFFSET 6 +#define MACB_UND_SIZE 1 /* Bitfields in RSR */ -#define MACB_BNA_OFFSET 0 -#define MACB_BNA_SIZE 1 -#define MACB_REC_OFFSET 1 -#define MACB_REC_SIZE 1 -#define MACB_OVR_OFFSET 2 -#define MACB_OVR_SIZE 1 +#define MACB_BNA_OFFSET 0 +#define MACB_BNA_SIZE 1 +#define MACB_REC_OFFSET 1 +#define MACB_REC_SIZE 1 +#define MACB_OVR_OFFSET 2 +#define MACB_OVR_SIZE 1 /* Bitfields in ISR/IER/IDR/IMR */ -#define MACB_MFD_OFFSET 0 -#define MACB_MFD_SIZE 1 -#define MACB_RCOMP_OFFSET 1 -#define MACB_RCOMP_SIZE 1 -#define MACB_RXUBR_OFFSET 2 -#define MACB_RXUBR_SIZE 1 -#define MACB_TXUBR_OFFSET 3 -#define MACB_TXUBR_SIZE 1 -#define MACB_ISR_TUND_OFFSET 4 -#define MACB_ISR_TUND_SIZE 1 -#define MACB_ISR_RLE_OFFSET 5 -#define MACB_ISR_RLE_SIZE 1 -#define MACB_TXERR_OFFSET 6 -#define MACB_TXERR_SIZE 1 -#define MACB_TCOMP_OFFSET 7 -#define MACB_TCOMP_SIZE 1 -#define MACB_ISR_LINK_OFFSET 9 -#define MACB_ISR_LINK_SIZE 1 -#define MACB_ISR_ROVR_OFFSET 10 -#define MACB_ISR_ROVR_SIZE 1 -#define MACB_HRESP_OFFSET 11 -#define MACB_HRESP_SIZE 1 -#define MACB_PFR_OFFSET 12 -#define MACB_PFR_SIZE 1 -#define MACB_PTZ_OFFSET 13 -#define MACB_PTZ_SIZE 1 +#define MACB_MFD_OFFSET 0 +#define MACB_MFD_SIZE 1 +#define MACB_RCOMP_OFFSET 1 +#define MACB_RCOMP_SIZE 1 +#define MACB_RXUBR_OFFSET 2 +#define MACB_RXUBR_SIZE 1 +#define MACB_TXUBR_OFFSET 3 +#define MACB_TXUBR_SIZE 1 +#define MACB_ISR_TUND_OFFSET 4 +#define MACB_ISR_TUND_SIZE 1 +#define MACB_ISR_RLE_OFFSET 5 +#define MACB_ISR_RLE_SIZE 1 +#define MACB_TXERR_OFFSET 6 +#define MACB_TXERR_SIZE 1 +#define MACB_TCOMP_OFFSET 7 +#define MACB_TCOMP_SIZE 1 +#define MACB_ISR_LINK_OFFSET 9 +#define MACB_ISR_LINK_SIZE 1 +#define MACB_ISR_ROVR_OFFSET 10 +#define MACB_ISR_ROVR_SIZE 1 +#define MACB_HRESP_OFFSET 11 +#define MACB_HRESP_SIZE 1 +#define MACB_PFR_OFFSET 12 +#define MACB_PFR_SIZE 1 +#define MACB_PTZ_OFFSET 13 +#define MACB_PTZ_SIZE 1 /* Bitfields in MAN */ -#define MACB_DATA_OFFSET 0 -#define MACB_DATA_SIZE 16 -#define MACB_CODE_OFFSET 16 -#define MACB_CODE_SIZE 2 -#define MACB_REGA_OFFSET 18 -#define MACB_REGA_SIZE 5 -#define MACB_PHYA_OFFSET 23 -#define MACB_PHYA_SIZE 5 -#define MACB_RW_OFFSET 28 -#define MACB_RW_SIZE 2 -#define MACB_SOF_OFFSET 30 -#define MACB_SOF_SIZE 2 +#define MACB_DATA_OFFSET 0 +#define MACB_DATA_SIZE 16 +#define MACB_CODE_OFFSET 16 +#define MACB_CODE_SIZE 2 +#define MACB_REGA_OFFSET 18 +#define MACB_REGA_SIZE 5 +#define MACB_PHYA_OFFSET 23 +#define MACB_PHYA_SIZE 5 +#define MACB_RW_OFFSET 28 +#define MACB_RW_SIZE 2 +#define MACB_SOF_OFFSET 30 +#define MACB_SOF_SIZE 2 /* Bitfields in USRIO (AVR32) */ -#define MACB_MII_OFFSET 0 -#define MACB_MII_SIZE 1 -#define MACB_EAM_OFFSET 1 -#define MACB_EAM_SIZE 1 -#define MACB_TX_PAUSE_OFFSET 2 -#define MACB_TX_PAUSE_SIZE 1 -#define MACB_TX_PAUSE_ZERO_OFFSET 3 -#define MACB_TX_PAUSE_ZERO_SIZE 1 +#define MACB_MII_OFFSET 0 +#define MACB_MII_SIZE 1 +#define MACB_EAM_OFFSET 1 +#define MACB_EAM_SIZE 1 +#define MACB_TX_PAUSE_OFFSET 2 +#define MACB_TX_PAUSE_SIZE 1 +#define MACB_TX_PAUSE_ZERO_OFFSET 3 +#define MACB_TX_PAUSE_ZERO_SIZE 1 /* Bitfields in USRIO (AT91) */ -#define MACB_RMII_OFFSET 0 -#define MACB_RMII_SIZE 1 -#define MACB_CLKEN_OFFSET 1 -#define MACB_CLKEN_SIZE 1 +#define MACB_RMII_OFFSET 0 +#define MACB_RMII_SIZE 1 +#define MACB_CLKEN_OFFSET 1 +#define MACB_CLKEN_SIZE 1 /* Bitfields in WOL */ -#define MACB_IP_OFFSET 0 -#define MACB_IP_SIZE 16 -#define MACB_MAG_OFFSET 16 -#define MACB_MAG_SIZE 1 -#define MACB_ARP_OFFSET 17 -#define MACB_ARP_SIZE 1 -#define MACB_SA1_OFFSET 18 -#define MACB_SA1_SIZE 1 -#define MACB_WOL_MTI_OFFSET 19 -#define MACB_WOL_MTI_SIZE 1 +#define MACB_IP_OFFSET 0 +#define MACB_IP_SIZE 16 +#define MACB_MAG_OFFSET 16 +#define MACB_MAG_SIZE 1 +#define MACB_ARP_OFFSET 17 +#define MACB_ARP_SIZE 1 +#define MACB_SA1_OFFSET 18 +#define MACB_SA1_SIZE 1 +#define MACB_WOL_MTI_OFFSET 19 +#define MACB_WOL_MTI_SIZE 1 /* Constants for CLK */ -#define MACB_CLK_DIV8 0 -#define MACB_CLK_DIV16 1 -#define MACB_CLK_DIV32 2 -#define MACB_CLK_DIV64 3 +#define MACB_CLK_DIV8 0 +#define MACB_CLK_DIV16 1 +#define MACB_CLK_DIV32 2 +#define MACB_CLK_DIV64 3 /* Constants for MAN register */ -#define MACB_MAN_SOF 1 -#define MACB_MAN_WRITE 1 -#define MACB_MAN_READ 2 -#define MACB_MAN_CODE 2 +#define MACB_MAN_SOF 1 +#define MACB_MAN_WRITE 1 +#define MACB_MAN_READ 2 +#define MACB_MAN_CODE 2 /* Bit manipulation macros */ -#define MACB_BIT(name) \ - (1 << MACB_##name##_OFFSET) -#define MACB_BF(name,value) \ - (((value) & ((1 << MACB_##name##_SIZE) - 1)) \ - << MACB_##name##_OFFSET) +#define MACB_BIT(name) \ + (1 << MACB_##name##_OFFSET) +#define MACB_BF(name,value) \ + (((value) & ((1 << MACB_##name##_SIZE) - 1)) \ + << MACB_##name##_OFFSET) #define MACB_BFEXT(name,value)\ - (((value) >> MACB_##name##_OFFSET) \ - & ((1 << MACB_##name##_SIZE) - 1)) -#define MACB_BFINS(name,value,old) \ - (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \ - << MACB_##name##_OFFSET)) \ - | MACB_BF(name,value)) + (((value) >> MACB_##name##_OFFSET) \ + & ((1 << MACB_##name##_SIZE) - 1)) +#define MACB_BFINS(name,value,old) \ + (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \ + << MACB_##name##_OFFSET)) \ + | MACB_BF(name,value)) /* Register access macros */ -#define macb_readl(port,reg) \ - readl((port)->regs + MACB_##reg) -#define macb_writel(port,reg,value) \ - writel((value), (port)->regs + MACB_##reg) +#define macb_readl(port,reg) \ + readl((port)->regs + MACB_##reg) +#define macb_writel(port,reg,value) \ + writel((value), (port)->regs + MACB_##reg) struct dma_desc { - rt_uint32_t addr; - rt_uint32_t ctrl; + rt_uint32_t addr; + rt_uint32_t ctrl; }; /* DMA descriptor bitfields */ -#define MACB_RX_USED_OFFSET 0 -#define MACB_RX_USED_SIZE 1 -#define MACB_RX_WRAP_OFFSET 1 -#define MACB_RX_WRAP_SIZE 1 -#define MACB_RX_WADDR_OFFSET 2 -#define MACB_RX_WADDR_SIZE 30 +#define MACB_RX_USED_OFFSET 0 +#define MACB_RX_USED_SIZE 1 +#define MACB_RX_WRAP_OFFSET 1 +#define MACB_RX_WRAP_SIZE 1 +#define MACB_RX_WADDR_OFFSET 2 +#define MACB_RX_WADDR_SIZE 30 -#define MACB_RX_FRMLEN_OFFSET 0 -#define MACB_RX_FRMLEN_SIZE 12 -#define MACB_RX_OFFSET_OFFSET 12 -#define MACB_RX_OFFSET_SIZE 2 -#define MACB_RX_SOF_OFFSET 14 -#define MACB_RX_SOF_SIZE 1 -#define MACB_RX_EOF_OFFSET 15 -#define MACB_RX_EOF_SIZE 1 -#define MACB_RX_CFI_OFFSET 16 -#define MACB_RX_CFI_SIZE 1 -#define MACB_RX_VLAN_PRI_OFFSET 17 -#define MACB_RX_VLAN_PRI_SIZE 3 -#define MACB_RX_PRI_TAG_OFFSET 20 -#define MACB_RX_PRI_TAG_SIZE 1 -#define MACB_RX_VLAN_TAG_OFFSET 21 -#define MACB_RX_VLAN_TAG_SIZE 1 -#define MACB_RX_TYPEID_MATCH_OFFSET 22 -#define MACB_RX_TYPEID_MATCH_SIZE 1 -#define MACB_RX_SA4_MATCH_OFFSET 23 -#define MACB_RX_SA4_MATCH_SIZE 1 -#define MACB_RX_SA3_MATCH_OFFSET 24 -#define MACB_RX_SA3_MATCH_SIZE 1 -#define MACB_RX_SA2_MATCH_OFFSET 25 -#define MACB_RX_SA2_MATCH_SIZE 1 -#define MACB_RX_SA1_MATCH_OFFSET 26 -#define MACB_RX_SA1_MATCH_SIZE 1 -#define MACB_RX_EXT_MATCH_OFFSET 28 -#define MACB_RX_EXT_MATCH_SIZE 1 -#define MACB_RX_UHASH_MATCH_OFFSET 29 -#define MACB_RX_UHASH_MATCH_SIZE 1 -#define MACB_RX_MHASH_MATCH_OFFSET 30 -#define MACB_RX_MHASH_MATCH_SIZE 1 -#define MACB_RX_BROADCAST_OFFSET 31 -#define MACB_RX_BROADCAST_SIZE 1 +#define MACB_RX_FRMLEN_OFFSET 0 +#define MACB_RX_FRMLEN_SIZE 12 +#define MACB_RX_OFFSET_OFFSET 12 +#define MACB_RX_OFFSET_SIZE 2 +#define MACB_RX_SOF_OFFSET 14 +#define MACB_RX_SOF_SIZE 1 +#define MACB_RX_EOF_OFFSET 15 +#define MACB_RX_EOF_SIZE 1 +#define MACB_RX_CFI_OFFSET 16 +#define MACB_RX_CFI_SIZE 1 +#define MACB_RX_VLAN_PRI_OFFSET 17 +#define MACB_RX_VLAN_PRI_SIZE 3 +#define MACB_RX_PRI_TAG_OFFSET 20 +#define MACB_RX_PRI_TAG_SIZE 1 +#define MACB_RX_VLAN_TAG_OFFSET 21 +#define MACB_RX_VLAN_TAG_SIZE 1 +#define MACB_RX_TYPEID_MATCH_OFFSET 22 +#define MACB_RX_TYPEID_MATCH_SIZE 1 +#define MACB_RX_SA4_MATCH_OFFSET 23 +#define MACB_RX_SA4_MATCH_SIZE 1 +#define MACB_RX_SA3_MATCH_OFFSET 24 +#define MACB_RX_SA3_MATCH_SIZE 1 +#define MACB_RX_SA2_MATCH_OFFSET 25 +#define MACB_RX_SA2_MATCH_SIZE 1 +#define MACB_RX_SA1_MATCH_OFFSET 26 +#define MACB_RX_SA1_MATCH_SIZE 1 +#define MACB_RX_EXT_MATCH_OFFSET 28 +#define MACB_RX_EXT_MATCH_SIZE 1 +#define MACB_RX_UHASH_MATCH_OFFSET 29 +#define MACB_RX_UHASH_MATCH_SIZE 1 +#define MACB_RX_MHASH_MATCH_OFFSET 30 +#define MACB_RX_MHASH_MATCH_SIZE 1 +#define MACB_RX_BROADCAST_OFFSET 31 +#define MACB_RX_BROADCAST_SIZE 1 -#define MACB_TX_FRMLEN_OFFSET 0 -#define MACB_TX_FRMLEN_SIZE 11 -#define MACB_TX_LAST_OFFSET 15 -#define MACB_TX_LAST_SIZE 1 -#define MACB_TX_NOCRC_OFFSET 16 -#define MACB_TX_NOCRC_SIZE 1 -#define MACB_TX_BUF_EXHAUSTED_OFFSET 27 -#define MACB_TX_BUF_EXHAUSTED_SIZE 1 -#define MACB_TX_UNDERRUN_OFFSET 28 -#define MACB_TX_UNDERRUN_SIZE 1 -#define MACB_TX_ERROR_OFFSET 29 -#define MACB_TX_ERROR_SIZE 1 -#define MACB_TX_WRAP_OFFSET 30 -#define MACB_TX_WRAP_SIZE 1 -#define MACB_TX_USED_OFFSET 31 -#define MACB_TX_USED_SIZE 1 +#define MACB_TX_FRMLEN_OFFSET 0 +#define MACB_TX_FRMLEN_SIZE 11 +#define MACB_TX_LAST_OFFSET 15 +#define MACB_TX_LAST_SIZE 1 +#define MACB_TX_NOCRC_OFFSET 16 +#define MACB_TX_NOCRC_SIZE 1 +#define MACB_TX_BUF_EXHAUSTED_OFFSET 27 +#define MACB_TX_BUF_EXHAUSTED_SIZE 1 +#define MACB_TX_UNDERRUN_OFFSET 28 +#define MACB_TX_UNDERRUN_SIZE 1 +#define MACB_TX_ERROR_OFFSET 29 +#define MACB_TX_ERROR_SIZE 1 +#define MACB_TX_WRAP_OFFSET 30 +#define MACB_TX_WRAP_SIZE 1 +#define MACB_TX_USED_OFFSET 31 +#define MACB_TX_USED_SIZE 1 extern int rt_hw_macb_init(); diff --git a/bsp/at91sam9g45/drivers/mii.h b/bsp/at91sam9g45/drivers/mii.h index 2f6dd18e71..03d914b7c3 100644 --- a/bsp/at91sam9g45/drivers/mii.h +++ b/bsp/at91sam9g45/drivers/mii.h @@ -1,21 +1,7 @@ /* - * File : mii.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -36,7 +22,7 @@ #define MII_EXPANSION 0x06 /* Expansion register */ #define MII_CTRL1000 0x09 /* 1000BASE-T control */ #define MII_STAT1000 0x0a /* 1000BASE-T status */ -#define MII_ESTATUS 0x0f /* Extended Status */ +#define MII_ESTATUS 0x0f /* Extended Status */ #define MII_DCOUNTER 0x12 /* Disconnect counter */ #define MII_FCSCOUNTER 0x13 /* False carrier counter */ #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ @@ -51,7 +37,7 @@ /* Basic mode control register. */ #define BMCR_RESV 0x003f /* Unused... */ -#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ +#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ #define BMCR_CTST 0x0080 /* Collision test */ #define BMCR_FULLDPLX 0x0100 /* Full duplex */ #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ @@ -70,7 +56,7 @@ #define BMSR_RFAULT 0x0010 /* Remote fault detected */ #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ #define BMSR_RESV 0x00c0 /* Unused... */ -#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ +#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */ #define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */ #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ @@ -99,7 +85,7 @@ #define ADVERTISE_NPAGE 0x8000 /* Next page bit */ #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ - ADVERTISE_CSMA) + ADVERTISE_CSMA) #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ ADVERTISE_100HALF | ADVERTISE_100FULL) @@ -121,8 +107,8 @@ #define LPA_LPACK 0x4000 /* Link partner acked us */ #define LPA_NPAGE 0x8000 /* Next page bit */ -#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) -#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) +#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) +#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) /* Expansion register for auto-negotiation. */ #define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */ @@ -132,8 +118,8 @@ #define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */ #define EXPANSION_RESV 0xffe0 /* Unused... */ -#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ -#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ +#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ +#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ /* N-way test register. */ #define NWAYTEST_RESV1 0x00ff /* Unused... */ @@ -151,8 +137,8 @@ #define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */ /* Flow control flags */ -#define FLOW_CTRL_TX 0x01 -#define FLOW_CTRL_RX 0x02 +#define FLOW_CTRL_TX 0x01 +#define FLOW_CTRL_RX 0x02 /** * mii_nway_result diff --git a/bsp/at91sam9g45/drivers/usart.c b/bsp/at91sam9g45/drivers/usart.c index d4ba657232..fdcb2f8537 100644 --- a/bsp/at91sam9g45/drivers/usart.c +++ b/bsp/at91sam9g45/drivers/usart.c @@ -1,21 +1,7 @@ /* - * File : usart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -30,8 +16,8 @@ struct at91_uart { - AT91S_USART *port; - int irq; + AT91S_USART *port; + int irq; }; @@ -40,18 +26,18 @@ struct at91_uart { */ void rt_at91_usart_handler(int vector, void *param) { - int status; - struct at91_uart *uart; - rt_device_t dev = (rt_device_t)param; - uart = (struct at91_uart *)dev->user_data; - status = uart->port->US_CSR; - if (!(status & uart->port->US_IMR)) /* check actived and enabled interrupt */ - { - return; - } - rt_interrupt_enter(); - rt_hw_serial_isr((struct rt_serial_device *)dev, RT_SERIAL_EVENT_RX_IND); - rt_interrupt_leave(); + int status; + struct at91_uart *uart; + rt_device_t dev = (rt_device_t)param; + uart = (struct at91_uart *)dev->user_data; + status = uart->port->US_CSR; + if (!(status & uart->port->US_IMR)) /* check actived and enabled interrupt */ + { + return; + } + rt_interrupt_enter(); + rt_hw_serial_isr((struct rt_serial_device *)dev, RT_SERIAL_EVENT_RX_IND); + rt_interrupt_leave(); } /** @@ -60,68 +46,68 @@ void rt_at91_usart_handler(int vector, void *param) static rt_err_t at91_usart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) { - int div; - int mode = 0; - struct at91_uart *uart; + int div; + int mode = 0; + struct at91_uart *uart; - RT_ASSERT(serial != RT_NULL); + RT_ASSERT(serial != RT_NULL); RT_ASSERT(cfg != RT_NULL); - uart = (struct at91_uart *)serial->parent.user_data; + uart = (struct at91_uart *)serial->parent.user_data; - uart->port->US_CR = AT91C_US_RSTTX | AT91C_US_RSTRX | - AT91C_US_RXDIS | AT91C_US_TXDIS; - mode |= AT91C_US_USMODE_NORMAL | AT91C_US_CLKS_CLOCK | - AT91C_US_CHMODE_NORMAL; - switch (cfg->data_bits) - { - case DATA_BITS_8: - mode |= AT91C_US_CHRL_8_BITS; - break; - case DATA_BITS_7: - mode |= AT91C_US_CHRL_7_BITS; - break; - case DATA_BITS_6: - mode |= AT91C_US_CHRL_6_BITS; - break; - case DATA_BITS_5: - mode |= AT91C_US_CHRL_5_BITS; - break; - default: - mode |= AT91C_US_CHRL_8_BITS; - break; - } + uart->port->US_CR = AT91C_US_RSTTX | AT91C_US_RSTRX | + AT91C_US_RXDIS | AT91C_US_TXDIS; + mode |= AT91C_US_USMODE_NORMAL | AT91C_US_CLKS_CLOCK | + AT91C_US_CHMODE_NORMAL; + switch (cfg->data_bits) + { + case DATA_BITS_8: + mode |= AT91C_US_CHRL_8_BITS; + break; + case DATA_BITS_7: + mode |= AT91C_US_CHRL_7_BITS; + break; + case DATA_BITS_6: + mode |= AT91C_US_CHRL_6_BITS; + break; + case DATA_BITS_5: + mode |= AT91C_US_CHRL_5_BITS; + break; + default: + mode |= AT91C_US_CHRL_8_BITS; + break; + } - switch (cfg->stop_bits) - { - case STOP_BITS_2: - mode |= AT91C_US_NBSTOP_2_BIT; - break; - case STOP_BITS_1: - default: - mode |= AT91C_US_NBSTOP_1_BIT; - break; - } + switch (cfg->stop_bits) + { + case STOP_BITS_2: + mode |= AT91C_US_NBSTOP_2_BIT; + break; + case STOP_BITS_1: + default: + mode |= AT91C_US_NBSTOP_1_BIT; + break; + } - switch (cfg->parity) - { - case PARITY_ODD: - mode |= AT91C_US_PAR_ODD; - break; - case PARITY_EVEN: - mode |= AT91C_US_PAR_EVEN; - break; - case PARITY_NONE: - default: - mode |= AT91C_US_PAR_NONE; - break; - } + switch (cfg->parity) + { + case PARITY_ODD: + mode |= AT91C_US_PAR_ODD; + break; + case PARITY_EVEN: + mode |= AT91C_US_PAR_EVEN; + break; + case PARITY_NONE: + default: + mode |= AT91C_US_PAR_NONE; + break; + } - uart->port->US_MR = mode; + uart->port->US_MR = mode; /* Assume OVER is cleared and fractional baudrate generator is disabled */ - div = (clk_get_rate(clk_get("mck")) / 16 + cfg->baud_rate/2) / cfg->baud_rate; - uart->port->US_BRGR = div; - uart->port->US_CR = AT91C_US_RXEN | AT91C_US_TXEN; - uart->port->US_IER = AT91C_US_RXRDY; + div = (clk_get_rate(clk_get("mck")) / 16 + cfg->baud_rate/2) / cfg->baud_rate; + uart->port->US_BRGR = div; + uart->port->US_CR = AT91C_US_RXEN | AT91C_US_TXEN; + uart->port->US_IER = AT91C_US_RXRDY; return RT_EOK; } @@ -138,11 +124,11 @@ static rt_err_t at91_usart_control(struct rt_serial_device *serial, { case RT_DEVICE_CTRL_CLR_INT: /* disable rx irq */ - rt_hw_interrupt_mask(uart->irq); + rt_hw_interrupt_mask(uart->irq); break; case RT_DEVICE_CTRL_SET_INT: /* enable rx irq */ - rt_hw_interrupt_umask(uart->irq); + rt_hw_interrupt_umask(uart->irq); break; } @@ -152,10 +138,10 @@ static rt_err_t at91_usart_control(struct rt_serial_device *serial, static int at91_usart_putc(struct rt_serial_device *serial, char c) { //rt_uint32_t level; - struct at91_uart *uart = serial->parent.user_data; + struct at91_uart *uart = serial->parent.user_data; while (!(uart->port->US_CSR & AT91C_US_TXRDY)); - uart->port->US_THR = c; + uart->port->US_THR = c; return 1; } @@ -163,16 +149,16 @@ static int at91_usart_putc(struct rt_serial_device *serial, char c) static int at91_usart_getc(struct rt_serial_device *serial) { int result; - struct at91_uart *uart = serial->parent.user_data; + struct at91_uart *uart = serial->parent.user_data; if (uart->port->US_CSR & AT91C_US_RXRDY) - { - result = uart->port->US_RHR & 0xff; - } - else - { - result = -1; - } + { + result = uart->port->US_RHR & 0xff; + } + else + { + result = -1; + } return result; } @@ -188,8 +174,8 @@ static const struct rt_uart_ops at91_usart_ops = #if defined(RT_USING_DBGU) static struct rt_serial_device serial_dbgu; struct at91_uart dbgu = { - (AT91PS_USART)AT91C_BASE_DBGU, - AT91C_ID_SYS + (AT91PS_USART)AT91C_BASE_DBGU, + AT91C_ID_SYS }; #endif @@ -197,32 +183,32 @@ struct at91_uart dbgu = { #if defined(RT_USING_UART0) static struct rt_serial_device serial0; struct at91_uart uart0 = { - AT91C_BASE_US0, - AT91C_ID_US0 + AT91C_BASE_US0, + AT91C_ID_US0 }; #endif #if defined(RT_USING_UART1) static struct rt_serial_device serial1; struct at91_uart uart1 = { - AT91C_BASE_US1, - AT91C_ID_US1 + AT91C_BASE_US1, + AT91C_ID_US1 }; #endif #if defined(RT_USING_UART2) static struct rt_serial_device serial2; struct at91_uart uart2 = { - AT91C_BASE_US2, - AT91C_ID_US2 + AT91C_BASE_US2, + AT91C_ID_US2 }; #endif #if defined(RT_USING_UART3) static struct rt_serial_device serial3; struct at91_uart uart3 = { - AT91C_BASE_US3, - AT91C_ID_US3 + AT91C_BASE_US3, + AT91C_ID_US3 }; #endif @@ -230,57 +216,57 @@ struct at91_uart uart3 = { void at91_usart_gpio_init(void) { #ifdef RT_USING_DBGU -#define DRXD 12 // DBGU rx as Peripheral A on PB12 -#define DTXD 13 // DBGU tx as Peripheral A on PB13 - AT91C_BASE_PIOB->PIO_IDR, (1<PIO_PPUDR, (1<PIO_ASR, (1<PIO_PDR, (1<PMC_PCER, 1 << AT91C_ID_SYS; +#define DRXD 12 // DBGU rx as Peripheral A on PB12 +#define DTXD 13 // DBGU tx as Peripheral A on PB13 + AT91C_BASE_PIOB->PIO_IDR, (1<PIO_PPUDR, (1<PIO_ASR, (1<PIO_PDR, (1<PMC_PCER, 1 << AT91C_ID_SYS; #endif #ifdef RT_USING_UART0 -#define RXD0 18 // UART0 rx as Peripheral A on PB18 -#define TXD0 19 // UART0 tx as Peripheral A on PB19 - AT91C_BASE_PMC->PMC_PCER, 1 << AT91C_ID_US0; - AT91C_BASE_PIOB->PIO_IDR, (1<PIO_PPUER, (1<PIO_PPUDR, (1<PIO_ASR, (1<PIO_PDR, (1<PMC_PCER, 1 << AT91C_ID_US0; + AT91C_BASE_PIOB->PIO_IDR, (1<PIO_PPUER, (1<PIO_PPUDR, (1<PIO_ASR, (1<PIO_PDR, (1<PMC_PCER, 1 << AT91C_ID_US1; - AT91C_BASE_PIOB->PIO_IDR, (1<PIO_PPUER, (1<PIO_PPUDR, (1<PIO_ASR, (1<PIO_PDR, (1<PMC_PCER, 1 << AT91C_ID_US1; + AT91C_BASE_PIOB->PIO_IDR, (1<PIO_PPUER, (1<PIO_PPUDR, (1<PIO_ASR, (1<PIO_PDR, (1<PMC_PCER, 1 << AT91C_ID_US2; - AT91C_BASE_PIOB->PIO_IDR, (1<PIO_PPUER, (1<PIO_PPUDR, (1<PIO_ASR, (1<PIO_PDR, (1<PMC_PCER, 1 << AT91C_ID_US2; + AT91C_BASE_PIOB->PIO_IDR, (1<PIO_PPUER, (1<PIO_PPUDR, (1<PIO_ASR, (1<PIO_PDR, (1<PMC_PCER, 1<PIO_IDR, (1<PIO_PPUER, (1<PIO_PPUDR, (1<PIO_ASR, (1<PIO_PDR, (1<PMC_PCER, 1<PIO_IDR, (1<PIO_PPUER, (1<PIO_PPUDR, (1<PIO_ASR, (1<PIO_PDR, (1< -#define PIN_BASE AIC_IRQS +#define PIN_BASE AIC_IRQS -#define MAX_GPIO_BANKS 5 +#define MAX_GPIO_BANKS 5 -#define PIN_IRQS (MAX_GPIO_BANKS*32) +#define PIN_IRQS (MAX_GPIO_BANKS*32) /* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */ -#define AT91C_PIN_PA0 (PIN_BASE + 0x00 + 0) -#define AT91C_PIN_PA1 (PIN_BASE + 0x00 + 1) -#define AT91C_PIN_PA2 (PIN_BASE + 0x00 + 2) -#define AT91C_PIN_PA3 (PIN_BASE + 0x00 + 3) -#define AT91C_PIN_PA4 (PIN_BASE + 0x00 + 4) -#define AT91C_PIN_PA5 (PIN_BASE + 0x00 + 5) -#define AT91C_PIN_PA6 (PIN_BASE + 0x00 + 6) -#define AT91C_PIN_PA7 (PIN_BASE + 0x00 + 7) -#define AT91C_PIN_PA8 (PIN_BASE + 0x00 + 8) -#define AT91C_PIN_PA9 (PIN_BASE + 0x00 + 9) -#define AT91C_PIN_PA10 (PIN_BASE + 0x00 + 10) -#define AT91C_PIN_PA11 (PIN_BASE + 0x00 + 11) -#define AT91C_PIN_PA12 (PIN_BASE + 0x00 + 12) -#define AT91C_PIN_PA13 (PIN_BASE + 0x00 + 13) -#define AT91C_PIN_PA14 (PIN_BASE + 0x00 + 14) -#define AT91C_PIN_PA15 (PIN_BASE + 0x00 + 15) -#define AT91C_PIN_PA16 (PIN_BASE + 0x00 + 16) -#define AT91C_PIN_PA17 (PIN_BASE + 0x00 + 17) -#define AT91C_PIN_PA18 (PIN_BASE + 0x00 + 18) -#define AT91C_PIN_PA19 (PIN_BASE + 0x00 + 19) -#define AT91C_PIN_PA20 (PIN_BASE + 0x00 + 20) -#define AT91C_PIN_PA21 (PIN_BASE + 0x00 + 21) -#define AT91C_PIN_PA22 (PIN_BASE + 0x00 + 22) -#define AT91C_PIN_PA23 (PIN_BASE + 0x00 + 23) -#define AT91C_PIN_PA24 (PIN_BASE + 0x00 + 24) -#define AT91C_PIN_PA25 (PIN_BASE + 0x00 + 25) -#define AT91C_PIN_PA26 (PIN_BASE + 0x00 + 26) -#define AT91C_PIN_PA27 (PIN_BASE + 0x00 + 27) -#define AT91C_PIN_PA28 (PIN_BASE + 0x00 + 28) -#define AT91C_PIN_PA29 (PIN_BASE + 0x00 + 29) -#define AT91C_PIN_PA30 (PIN_BASE + 0x00 + 30) -#define AT91C_PIN_PA31 (PIN_BASE + 0x00 + 31) +#define AT91C_PIN_PA0 (PIN_BASE + 0x00 + 0) +#define AT91C_PIN_PA1 (PIN_BASE + 0x00 + 1) +#define AT91C_PIN_PA2 (PIN_BASE + 0x00 + 2) +#define AT91C_PIN_PA3 (PIN_BASE + 0x00 + 3) +#define AT91C_PIN_PA4 (PIN_BASE + 0x00 + 4) +#define AT91C_PIN_PA5 (PIN_BASE + 0x00 + 5) +#define AT91C_PIN_PA6 (PIN_BASE + 0x00 + 6) +#define AT91C_PIN_PA7 (PIN_BASE + 0x00 + 7) +#define AT91C_PIN_PA8 (PIN_BASE + 0x00 + 8) +#define AT91C_PIN_PA9 (PIN_BASE + 0x00 + 9) +#define AT91C_PIN_PA10 (PIN_BASE + 0x00 + 10) +#define AT91C_PIN_PA11 (PIN_BASE + 0x00 + 11) +#define AT91C_PIN_PA12 (PIN_BASE + 0x00 + 12) +#define AT91C_PIN_PA13 (PIN_BASE + 0x00 + 13) +#define AT91C_PIN_PA14 (PIN_BASE + 0x00 + 14) +#define AT91C_PIN_PA15 (PIN_BASE + 0x00 + 15) +#define AT91C_PIN_PA16 (PIN_BASE + 0x00 + 16) +#define AT91C_PIN_PA17 (PIN_BASE + 0x00 + 17) +#define AT91C_PIN_PA18 (PIN_BASE + 0x00 + 18) +#define AT91C_PIN_PA19 (PIN_BASE + 0x00 + 19) +#define AT91C_PIN_PA20 (PIN_BASE + 0x00 + 20) +#define AT91C_PIN_PA21 (PIN_BASE + 0x00 + 21) +#define AT91C_PIN_PA22 (PIN_BASE + 0x00 + 22) +#define AT91C_PIN_PA23 (PIN_BASE + 0x00 + 23) +#define AT91C_PIN_PA24 (PIN_BASE + 0x00 + 24) +#define AT91C_PIN_PA25 (PIN_BASE + 0x00 + 25) +#define AT91C_PIN_PA26 (PIN_BASE + 0x00 + 26) +#define AT91C_PIN_PA27 (PIN_BASE + 0x00 + 27) +#define AT91C_PIN_PA28 (PIN_BASE + 0x00 + 28) +#define AT91C_PIN_PA29 (PIN_BASE + 0x00 + 29) +#define AT91C_PIN_PA30 (PIN_BASE + 0x00 + 30) +#define AT91C_PIN_PA31 (PIN_BASE + 0x00 + 31) -#define AT91C_PIN_PB0 (PIN_BASE + 0x20 + 0) -#define AT91C_PIN_PB1 (PIN_BASE + 0x20 + 1) -#define AT91C_PIN_PB2 (PIN_BASE + 0x20 + 2) -#define AT91C_PIN_PB3 (PIN_BASE + 0x20 + 3) -#define AT91C_PIN_PB4 (PIN_BASE + 0x20 + 4) -#define AT91C_PIN_PB5 (PIN_BASE + 0x20 + 5) -#define AT91C_PIN_PB6 (PIN_BASE + 0x20 + 6) -#define AT91C_PIN_PB7 (PIN_BASE + 0x20 + 7) -#define AT91C_PIN_PB8 (PIN_BASE + 0x20 + 8) -#define AT91C_PIN_PB9 (PIN_BASE + 0x20 + 9) -#define AT91C_PIN_PB10 (PIN_BASE + 0x20 + 10) -#define AT91C_PIN_PB11 (PIN_BASE + 0x20 + 11) -#define AT91C_PIN_PB12 (PIN_BASE + 0x20 + 12) -#define AT91C_PIN_PB13 (PIN_BASE + 0x20 + 13) -#define AT91C_PIN_PB14 (PIN_BASE + 0x20 + 14) -#define AT91C_PIN_PB15 (PIN_BASE + 0x20 + 15) -#define AT91C_PIN_PB16 (PIN_BASE + 0x20 + 16) -#define AT91C_PIN_PB17 (PIN_BASE + 0x20 + 17) -#define AT91C_PIN_PB18 (PIN_BASE + 0x20 + 18) -#define AT91C_PIN_PB19 (PIN_BASE + 0x20 + 19) -#define AT91C_PIN_PB20 (PIN_BASE + 0x20 + 20) -#define AT91C_PIN_PB21 (PIN_BASE + 0x20 + 21) -#define AT91C_PIN_PB22 (PIN_BASE + 0x20 + 22) -#define AT91C_PIN_PB23 (PIN_BASE + 0x20 + 23) -#define AT91C_PIN_PB24 (PIN_BASE + 0x20 + 24) -#define AT91C_PIN_PB25 (PIN_BASE + 0x20 + 25) -#define AT91C_PIN_PB26 (PIN_BASE + 0x20 + 26) -#define AT91C_PIN_PB27 (PIN_BASE + 0x20 + 27) -#define AT91C_PIN_PB28 (PIN_BASE + 0x20 + 28) -#define AT91C_PIN_PB29 (PIN_BASE + 0x20 + 29) -#define AT91C_PIN_PB30 (PIN_BASE + 0x20 + 30) -#define AT91C_PIN_PB31 (PIN_BASE + 0x20 + 31) +#define AT91C_PIN_PB0 (PIN_BASE + 0x20 + 0) +#define AT91C_PIN_PB1 (PIN_BASE + 0x20 + 1) +#define AT91C_PIN_PB2 (PIN_BASE + 0x20 + 2) +#define AT91C_PIN_PB3 (PIN_BASE + 0x20 + 3) +#define AT91C_PIN_PB4 (PIN_BASE + 0x20 + 4) +#define AT91C_PIN_PB5 (PIN_BASE + 0x20 + 5) +#define AT91C_PIN_PB6 (PIN_BASE + 0x20 + 6) +#define AT91C_PIN_PB7 (PIN_BASE + 0x20 + 7) +#define AT91C_PIN_PB8 (PIN_BASE + 0x20 + 8) +#define AT91C_PIN_PB9 (PIN_BASE + 0x20 + 9) +#define AT91C_PIN_PB10 (PIN_BASE + 0x20 + 10) +#define AT91C_PIN_PB11 (PIN_BASE + 0x20 + 11) +#define AT91C_PIN_PB12 (PIN_BASE + 0x20 + 12) +#define AT91C_PIN_PB13 (PIN_BASE + 0x20 + 13) +#define AT91C_PIN_PB14 (PIN_BASE + 0x20 + 14) +#define AT91C_PIN_PB15 (PIN_BASE + 0x20 + 15) +#define AT91C_PIN_PB16 (PIN_BASE + 0x20 + 16) +#define AT91C_PIN_PB17 (PIN_BASE + 0x20 + 17) +#define AT91C_PIN_PB18 (PIN_BASE + 0x20 + 18) +#define AT91C_PIN_PB19 (PIN_BASE + 0x20 + 19) +#define AT91C_PIN_PB20 (PIN_BASE + 0x20 + 20) +#define AT91C_PIN_PB21 (PIN_BASE + 0x20 + 21) +#define AT91C_PIN_PB22 (PIN_BASE + 0x20 + 22) +#define AT91C_PIN_PB23 (PIN_BASE + 0x20 + 23) +#define AT91C_PIN_PB24 (PIN_BASE + 0x20 + 24) +#define AT91C_PIN_PB25 (PIN_BASE + 0x20 + 25) +#define AT91C_PIN_PB26 (PIN_BASE + 0x20 + 26) +#define AT91C_PIN_PB27 (PIN_BASE + 0x20 + 27) +#define AT91C_PIN_PB28 (PIN_BASE + 0x20 + 28) +#define AT91C_PIN_PB29 (PIN_BASE + 0x20 + 29) +#define AT91C_PIN_PB30 (PIN_BASE + 0x20 + 30) +#define AT91C_PIN_PB31 (PIN_BASE + 0x20 + 31) -#define AT91C_PIN_PC0 (PIN_BASE + 0x40 + 0) -#define AT91C_PIN_PC1 (PIN_BASE + 0x40 + 1) -#define AT91C_PIN_PC2 (PIN_BASE + 0x40 + 2) -#define AT91C_PIN_PC3 (PIN_BASE + 0x40 + 3) -#define AT91C_PIN_PC4 (PIN_BASE + 0x40 + 4) -#define AT91C_PIN_PC5 (PIN_BASE + 0x40 + 5) -#define AT91C_PIN_PC6 (PIN_BASE + 0x40 + 6) -#define AT91C_PIN_PC7 (PIN_BASE + 0x40 + 7) -#define AT91C_PIN_PC8 (PIN_BASE + 0x40 + 8) -#define AT91C_PIN_PC9 (PIN_BASE + 0x40 + 9) -#define AT91C_PIN_PC10 (PIN_BASE + 0x40 + 10) -#define AT91C_PIN_PC11 (PIN_BASE + 0x40 + 11) -#define AT91C_PIN_PC12 (PIN_BASE + 0x40 + 12) -#define AT91C_PIN_PC13 (PIN_BASE + 0x40 + 13) -#define AT91C_PIN_PC14 (PIN_BASE + 0x40 + 14) -#define AT91C_PIN_PC15 (PIN_BASE + 0x40 + 15) -#define AT91C_PIN_PC16 (PIN_BASE + 0x40 + 16) -#define AT91C_PIN_PC17 (PIN_BASE + 0x40 + 17) -#define AT91C_PIN_PC18 (PIN_BASE + 0x40 + 18) -#define AT91C_PIN_PC19 (PIN_BASE + 0x40 + 19) -#define AT91C_PIN_PC20 (PIN_BASE + 0x40 + 20) -#define AT91C_PIN_PC21 (PIN_BASE + 0x40 + 21) -#define AT91C_PIN_PC22 (PIN_BASE + 0x40 + 22) -#define AT91C_PIN_PC23 (PIN_BASE + 0x40 + 23) -#define AT91C_PIN_PC24 (PIN_BASE + 0x40 + 24) -#define AT91C_PIN_PC25 (PIN_BASE + 0x40 + 25) -#define AT91C_PIN_PC26 (PIN_BASE + 0x40 + 26) -#define AT91C_PIN_PC27 (PIN_BASE + 0x40 + 27) -#define AT91C_PIN_PC28 (PIN_BASE + 0x40 + 28) -#define AT91C_PIN_PC29 (PIN_BASE + 0x40 + 29) -#define AT91C_PIN_PC30 (PIN_BASE + 0x40 + 30) -#define AT91C_PIN_PC31 (PIN_BASE + 0x40 + 31) +#define AT91C_PIN_PC0 (PIN_BASE + 0x40 + 0) +#define AT91C_PIN_PC1 (PIN_BASE + 0x40 + 1) +#define AT91C_PIN_PC2 (PIN_BASE + 0x40 + 2) +#define AT91C_PIN_PC3 (PIN_BASE + 0x40 + 3) +#define AT91C_PIN_PC4 (PIN_BASE + 0x40 + 4) +#define AT91C_PIN_PC5 (PIN_BASE + 0x40 + 5) +#define AT91C_PIN_PC6 (PIN_BASE + 0x40 + 6) +#define AT91C_PIN_PC7 (PIN_BASE + 0x40 + 7) +#define AT91C_PIN_PC8 (PIN_BASE + 0x40 + 8) +#define AT91C_PIN_PC9 (PIN_BASE + 0x40 + 9) +#define AT91C_PIN_PC10 (PIN_BASE + 0x40 + 10) +#define AT91C_PIN_PC11 (PIN_BASE + 0x40 + 11) +#define AT91C_PIN_PC12 (PIN_BASE + 0x40 + 12) +#define AT91C_PIN_PC13 (PIN_BASE + 0x40 + 13) +#define AT91C_PIN_PC14 (PIN_BASE + 0x40 + 14) +#define AT91C_PIN_PC15 (PIN_BASE + 0x40 + 15) +#define AT91C_PIN_PC16 (PIN_BASE + 0x40 + 16) +#define AT91C_PIN_PC17 (PIN_BASE + 0x40 + 17) +#define AT91C_PIN_PC18 (PIN_BASE + 0x40 + 18) +#define AT91C_PIN_PC19 (PIN_BASE + 0x40 + 19) +#define AT91C_PIN_PC20 (PIN_BASE + 0x40 + 20) +#define AT91C_PIN_PC21 (PIN_BASE + 0x40 + 21) +#define AT91C_PIN_PC22 (PIN_BASE + 0x40 + 22) +#define AT91C_PIN_PC23 (PIN_BASE + 0x40 + 23) +#define AT91C_PIN_PC24 (PIN_BASE + 0x40 + 24) +#define AT91C_PIN_PC25 (PIN_BASE + 0x40 + 25) +#define AT91C_PIN_PC26 (PIN_BASE + 0x40 + 26) +#define AT91C_PIN_PC27 (PIN_BASE + 0x40 + 27) +#define AT91C_PIN_PC28 (PIN_BASE + 0x40 + 28) +#define AT91C_PIN_PC29 (PIN_BASE + 0x40 + 29) +#define AT91C_PIN_PC30 (PIN_BASE + 0x40 + 30) +#define AT91C_PIN_PC31 (PIN_BASE + 0x40 + 31) -#define AT91C_PIN_PD0 (PIN_BASE + 0x60 + 0) -#define AT91C_PIN_PD1 (PIN_BASE + 0x60 + 1) -#define AT91C_PIN_PD2 (PIN_BASE + 0x60 + 2) -#define AT91C_PIN_PD3 (PIN_BASE + 0x60 + 3) -#define AT91C_PIN_PD4 (PIN_BASE + 0x60 + 4) -#define AT91C_PIN_PD5 (PIN_BASE + 0x60 + 5) -#define AT91C_PIN_PD6 (PIN_BASE + 0x60 + 6) -#define AT91C_PIN_PD7 (PIN_BASE + 0x60 + 7) -#define AT91C_PIN_PD8 (PIN_BASE + 0x60 + 8) -#define AT91C_PIN_PD9 (PIN_BASE + 0x60 + 9) -#define AT91C_PIN_PD10 (PIN_BASE + 0x60 + 10) -#define AT91C_PIN_PD11 (PIN_BASE + 0x60 + 11) -#define AT91C_PIN_PD12 (PIN_BASE + 0x60 + 12) -#define AT91C_PIN_PD13 (PIN_BASE + 0x60 + 13) -#define AT91C_PIN_PD14 (PIN_BASE + 0x60 + 14) -#define AT91C_PIN_PD15 (PIN_BASE + 0x60 + 15) -#define AT91C_PIN_PD16 (PIN_BASE + 0x60 + 16) -#define AT91C_PIN_PD17 (PIN_BASE + 0x60 + 17) -#define AT91C_PIN_PD18 (PIN_BASE + 0x60 + 18) -#define AT91C_PIN_PD19 (PIN_BASE + 0x60 + 19) -#define AT91C_PIN_PD20 (PIN_BASE + 0x60 + 20) -#define AT91C_PIN_PD21 (PIN_BASE + 0x60 + 21) -#define AT91C_PIN_PD22 (PIN_BASE + 0x60 + 22) -#define AT91C_PIN_PD23 (PIN_BASE + 0x60 + 23) -#define AT91C_PIN_PD24 (PIN_BASE + 0x60 + 24) -#define AT91C_PIN_PD25 (PIN_BASE + 0x60 + 25) -#define AT91C_PIN_PD26 (PIN_BASE + 0x60 + 26) -#define AT91C_PIN_PD27 (PIN_BASE + 0x60 + 27) -#define AT91C_PIN_PD28 (PIN_BASE + 0x60 + 28) -#define AT91C_PIN_PD29 (PIN_BASE + 0x60 + 29) -#define AT91C_PIN_PD30 (PIN_BASE + 0x60 + 30) -#define AT91C_PIN_PD31 (PIN_BASE + 0x60 + 31) +#define AT91C_PIN_PD0 (PIN_BASE + 0x60 + 0) +#define AT91C_PIN_PD1 (PIN_BASE + 0x60 + 1) +#define AT91C_PIN_PD2 (PIN_BASE + 0x60 + 2) +#define AT91C_PIN_PD3 (PIN_BASE + 0x60 + 3) +#define AT91C_PIN_PD4 (PIN_BASE + 0x60 + 4) +#define AT91C_PIN_PD5 (PIN_BASE + 0x60 + 5) +#define AT91C_PIN_PD6 (PIN_BASE + 0x60 + 6) +#define AT91C_PIN_PD7 (PIN_BASE + 0x60 + 7) +#define AT91C_PIN_PD8 (PIN_BASE + 0x60 + 8) +#define AT91C_PIN_PD9 (PIN_BASE + 0x60 + 9) +#define AT91C_PIN_PD10 (PIN_BASE + 0x60 + 10) +#define AT91C_PIN_PD11 (PIN_BASE + 0x60 + 11) +#define AT91C_PIN_PD12 (PIN_BASE + 0x60 + 12) +#define AT91C_PIN_PD13 (PIN_BASE + 0x60 + 13) +#define AT91C_PIN_PD14 (PIN_BASE + 0x60 + 14) +#define AT91C_PIN_PD15 (PIN_BASE + 0x60 + 15) +#define AT91C_PIN_PD16 (PIN_BASE + 0x60 + 16) +#define AT91C_PIN_PD17 (PIN_BASE + 0x60 + 17) +#define AT91C_PIN_PD18 (PIN_BASE + 0x60 + 18) +#define AT91C_PIN_PD19 (PIN_BASE + 0x60 + 19) +#define AT91C_PIN_PD20 (PIN_BASE + 0x60 + 20) +#define AT91C_PIN_PD21 (PIN_BASE + 0x60 + 21) +#define AT91C_PIN_PD22 (PIN_BASE + 0x60 + 22) +#define AT91C_PIN_PD23 (PIN_BASE + 0x60 + 23) +#define AT91C_PIN_PD24 (PIN_BASE + 0x60 + 24) +#define AT91C_PIN_PD25 (PIN_BASE + 0x60 + 25) +#define AT91C_PIN_PD26 (PIN_BASE + 0x60 + 26) +#define AT91C_PIN_PD27 (PIN_BASE + 0x60 + 27) +#define AT91C_PIN_PD28 (PIN_BASE + 0x60 + 28) +#define AT91C_PIN_PD29 (PIN_BASE + 0x60 + 29) +#define AT91C_PIN_PD30 (PIN_BASE + 0x60 + 30) +#define AT91C_PIN_PD31 (PIN_BASE + 0x60 + 31) -#define AT91C_PIN_PE0 (PIN_BASE + 0x80 + 0) -#define AT91C_PIN_PE1 (PIN_BASE + 0x80 + 1) -#define AT91C_PIN_PE2 (PIN_BASE + 0x80 + 2) -#define AT91C_PIN_PE3 (PIN_BASE + 0x80 + 3) -#define AT91C_PIN_PE4 (PIN_BASE + 0x80 + 4) -#define AT91C_PIN_PE5 (PIN_BASE + 0x80 + 5) -#define AT91C_PIN_PE6 (PIN_BASE + 0x80 + 6) -#define AT91C_PIN_PE7 (PIN_BASE + 0x80 + 7) -#define AT91C_PIN_PE8 (PIN_BASE + 0x80 + 8) -#define AT91C_PIN_PE9 (PIN_BASE + 0x80 + 9) -#define AT91C_PIN_PE10 (PIN_BASE + 0x80 + 10) -#define AT91C_PIN_PE11 (PIN_BASE + 0x80 + 11) -#define AT91C_PIN_PE12 (PIN_BASE + 0x80 + 12) -#define AT91C_PIN_PE13 (PIN_BASE + 0x80 + 13) -#define AT91C_PIN_PE14 (PIN_BASE + 0x80 + 14) -#define AT91C_PIN_PE15 (PIN_BASE + 0x80 + 15) -#define AT91C_PIN_PE16 (PIN_BASE + 0x80 + 16) -#define AT91C_PIN_PE17 (PIN_BASE + 0x80 + 17) -#define AT91C_PIN_PE18 (PIN_BASE + 0x80 + 18) -#define AT91C_PIN_PE19 (PIN_BASE + 0x80 + 19) -#define AT91C_PIN_PE20 (PIN_BASE + 0x80 + 20) -#define AT91C_PIN_PE21 (PIN_BASE + 0x80 + 21) -#define AT91C_PIN_PE22 (PIN_BASE + 0x80 + 22) -#define AT91C_PIN_PE23 (PIN_BASE + 0x80 + 23) -#define AT91C_PIN_PE24 (PIN_BASE + 0x80 + 24) -#define AT91C_PIN_PE25 (PIN_BASE + 0x80 + 25) -#define AT91C_PIN_PE26 (PIN_BASE + 0x80 + 26) -#define AT91C_PIN_PE27 (PIN_BASE + 0x80 + 27) -#define AT91C_PIN_PE28 (PIN_BASE + 0x80 + 28) -#define AT91C_PIN_PE29 (PIN_BASE + 0x80 + 29) -#define AT91C_PIN_PE30 (PIN_BASE + 0x80 + 30) -#define AT91C_PIN_PE31 (PIN_BASE + 0x80 + 31) +#define AT91C_PIN_PE0 (PIN_BASE + 0x80 + 0) +#define AT91C_PIN_PE1 (PIN_BASE + 0x80 + 1) +#define AT91C_PIN_PE2 (PIN_BASE + 0x80 + 2) +#define AT91C_PIN_PE3 (PIN_BASE + 0x80 + 3) +#define AT91C_PIN_PE4 (PIN_BASE + 0x80 + 4) +#define AT91C_PIN_PE5 (PIN_BASE + 0x80 + 5) +#define AT91C_PIN_PE6 (PIN_BASE + 0x80 + 6) +#define AT91C_PIN_PE7 (PIN_BASE + 0x80 + 7) +#define AT91C_PIN_PE8 (PIN_BASE + 0x80 + 8) +#define AT91C_PIN_PE9 (PIN_BASE + 0x80 + 9) +#define AT91C_PIN_PE10 (PIN_BASE + 0x80 + 10) +#define AT91C_PIN_PE11 (PIN_BASE + 0x80 + 11) +#define AT91C_PIN_PE12 (PIN_BASE + 0x80 + 12) +#define AT91C_PIN_PE13 (PIN_BASE + 0x80 + 13) +#define AT91C_PIN_PE14 (PIN_BASE + 0x80 + 14) +#define AT91C_PIN_PE15 (PIN_BASE + 0x80 + 15) +#define AT91C_PIN_PE16 (PIN_BASE + 0x80 + 16) +#define AT91C_PIN_PE17 (PIN_BASE + 0x80 + 17) +#define AT91C_PIN_PE18 (PIN_BASE + 0x80 + 18) +#define AT91C_PIN_PE19 (PIN_BASE + 0x80 + 19) +#define AT91C_PIN_PE20 (PIN_BASE + 0x80 + 20) +#define AT91C_PIN_PE21 (PIN_BASE + 0x80 + 21) +#define AT91C_PIN_PE22 (PIN_BASE + 0x80 + 22) +#define AT91C_PIN_PE23 (PIN_BASE + 0x80 + 23) +#define AT91C_PIN_PE24 (PIN_BASE + 0x80 + 24) +#define AT91C_PIN_PE25 (PIN_BASE + 0x80 + 25) +#define AT91C_PIN_PE26 (PIN_BASE + 0x80 + 26) +#define AT91C_PIN_PE27 (PIN_BASE + 0x80 + 27) +#define AT91C_PIN_PE28 (PIN_BASE + 0x80 + 28) +#define AT91C_PIN_PE29 (PIN_BASE + 0x80 + 29) +#define AT91C_PIN_PE30 (PIN_BASE + 0x80 + 30) +#define AT91C_PIN_PE31 (PIN_BASE + 0x80 + 31) rt_inline rt_uint32_t gpio_to_irq(rt_uint32_t gpio) { - return gpio; + return gpio; } #endif diff --git a/bsp/at91sam9g45/platform/interrupt.c b/bsp/at91sam9g45/platform/interrupt.c index 9f7cabf3f8..c8afc998f1 100644 --- a/bsp/at91sam9g45/platform/interrupt.c +++ b/bsp/at91sam9g45/platform/interrupt.c @@ -1,21 +1,7 @@ /* - * File : interrupt.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -26,7 +12,7 @@ #include "at91sam9g45.h" #include "interrupt.h" -#define AIC_IRQS 32 +#define AIC_IRQS 32 #define MAX_HANDLERS (AIC_IRQS + PIN_IRQS) extern rt_uint32_t rt_interrupt_nest; @@ -101,17 +87,17 @@ rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector, void *param) rt_isr_handler_t at91_gpio_irq_handle(rt_uint32_t bank, void *param) { rt_uint32_t isr, irq_n; - AT91PS_PIO pio; + AT91PS_PIO pio; void *parameter; switch (bank) { - case 0: pio = AT91C_BASE_PIOA; break; - case 1: pio = AT91C_BASE_PIOB; break; - case 2: pio = AT91C_BASE_PIOC; break; - case 3: pio = AT91C_BASE_PIOD; break; - case 4: pio = AT91C_BASE_PIOE; break; - default: return RT_NULL; + case 0: pio = AT91C_BASE_PIOA; break; + case 1: pio = AT91C_BASE_PIOB; break; + case 2: pio = AT91C_BASE_PIOC; break; + case 3: pio = AT91C_BASE_PIOD; break; + case 4: pio = AT91C_BASE_PIOE; break; + default: return RT_NULL; } irq_n = AIC_IRQS + 32*bank; isr = readl(pio->PIO_ISR); @@ -133,21 +119,21 @@ rt_isr_handler_t at91_gpio_irq_handle(rt_uint32_t bank, void *param) unsigned int SpuriousCount = 0; static void DefaultSpuriousHandler( void ) { - SpuriousCount++; - rt_kprintf("Spurious interrupt %d occured!!!\n", SpuriousCount); - return ; + SpuriousCount++; + rt_kprintf("Spurious interrupt %d occured!!!\n", SpuriousCount); + return ; } static void DefaultFiqHandler(void) { - rt_kprintf("Unhandled FIQ occured!!!\n"); - while (1); + rt_kprintf("Unhandled FIQ occured!!!\n"); + while (1); } static void DefaultIrqHandler(void) { - rt_kprintf("Unhandled IRQ %d occured!!!\n", AT91C_BASE_AIC->AIC_ISR); - while (1); + rt_kprintf("Unhandled IRQ %d occured!!!\n", AT91C_BASE_AIC->AIC_ISR); + while (1); } /* @@ -345,7 +331,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, irq_desc[vector].param = param; #ifdef RT_USING_INTERRUPT_INFO rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name); - irq_desc[vector].counter = 0; + irq_desc[vector].counter = 0; #endif } } @@ -446,16 +432,16 @@ void rt_interrupt_dispatch(rt_uint32_t fiq_irq) #ifdef RT_USING_INTERRUPT_INFO void list_irq(void) { - int irq; + int irq; - rt_kprintf("number\tcount\tname\n"); - for (irq = 0; irq < MAX_HANDLERS; irq++) - { - if (rt_strncmp(irq_desc[irq].name, "default", sizeof("default"))) - { - rt_kprintf("%02ld: %10ld %s\n", irq, irq_desc[irq].counter, irq_desc[irq].name); - } - } + rt_kprintf("number\tcount\tname\n"); + for (irq = 0; irq < MAX_HANDLERS; irq++) + { + if (rt_strncmp(irq_desc[irq].name, "default", sizeof("default"))) + { + rt_kprintf("%02ld: %10ld %s\n", irq, irq_desc[irq].counter, irq_desc[irq].name); + } + } } #include diff --git a/bsp/at91sam9g45/platform/interrupt.h b/bsp/at91sam9g45/platform/interrupt.h index 7780e7a3a8..0375164e00 100644 --- a/bsp/at91sam9g45/platform/interrupt.h +++ b/bsp/at91sam9g45/platform/interrupt.h @@ -1,21 +1,7 @@ /* - * File : interrupt.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/at91sam9g45/platform/io.h b/bsp/at91sam9g45/platform/io.h index 80919c52cb..b3a9188299 100644 --- a/bsp/at91sam9g45/platform/io.h +++ b/bsp/at91sam9g45/platform/io.h @@ -1,21 +1,7 @@ /* - * File : io.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -25,15 +11,15 @@ #ifndef __ASM_ARCH_IO_H #define __ASM_ARCH_IO_H -#define IO_SPACE_LIMIT 0xFFFFFFFF +#define IO_SPACE_LIMIT 0xFFFFFFFF -#define readb(a) (*(volatile unsigned char *)(a)) -#define readw(a) (*(volatile unsigned short *)(a)) -#define readl(a) (*(volatile unsigned int *)(a)) +#define readb(a) (*(volatile unsigned char *)(a)) +#define readw(a) (*(volatile unsigned short *)(a)) +#define readl(a) (*(volatile unsigned int *)(a)) -#define writeb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define writew(v,a) (*(volatile unsigned short *)(a) = (v)) -#define writel(v,a) (*(volatile unsigned int *)(a) = (v)) +#define writeb(v,a) (*(volatile unsigned char *)(a) = (v)) +#define writew(v,a) (*(volatile unsigned short *)(a) = (v)) +#define writel(v,a) (*(volatile unsigned int *)(a) = (v)) #endif diff --git a/bsp/at91sam9g45/platform/irq.h b/bsp/at91sam9g45/platform/irq.h index fe1fea41d0..76d4200d3b 100644 --- a/bsp/at91sam9g45/platform/irq.h +++ b/bsp/at91sam9g45/platform/irq.h @@ -1,27 +1,13 @@ /* - * File : irq.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2011-01-13 weety first version */ - + #ifndef __IRQ_H__ #define __IRQ_H__ @@ -32,18 +18,18 @@ extern "C" { /* * IRQ line status. * - * Bits 0-7 are reserved + * Bits 0-7 are reserved * * IRQ types */ -#define IRQ_TYPE_NONE 0x00000000 /* Default, unspecified type */ -#define IRQ_TYPE_EDGE_RISING 0x00000001 /* Edge rising type */ -#define IRQ_TYPE_EDGE_FALLING 0x00000002 /* Edge falling type */ +#define IRQ_TYPE_NONE 0x00000000 /* Default, unspecified type */ +#define IRQ_TYPE_EDGE_RISING 0x00000001 /* Edge rising type */ +#define IRQ_TYPE_EDGE_FALLING 0x00000002 /* Edge falling type */ #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) -#define IRQ_TYPE_LEVEL_HIGH 0x00000004 /* Level high type */ -#define IRQ_TYPE_LEVEL_LOW 0x00000008 /* Level low type */ -#define IRQ_TYPE_SENSE_MASK 0x0000000f /* Mask of the above */ -#define IRQ_TYPE_PROBE 0x00000010 /* Probing in progress */ +#define IRQ_TYPE_LEVEL_HIGH 0x00000004 /* Level high type */ +#define IRQ_TYPE_LEVEL_LOW 0x00000008 /* Level low type */ +#define IRQ_TYPE_SENSE_MASK 0x0000000f /* Mask of the above */ +#define IRQ_TYPE_PROBE 0x00000010 /* Probing in progress */ #ifdef __cplusplus } diff --git a/bsp/at91sam9g45/platform/reset.c b/bsp/at91sam9g45/platform/reset.c index 2e7bec1e5d..8abbf7a9fb 100644 --- a/bsp/at91sam9g45/platform/reset.c +++ b/bsp/at91sam9g45/platform/reset.c @@ -1,21 +1,7 @@ /* - * File : reset.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -33,12 +19,12 @@ void machine_reset(void) { - AT91C_BASE_RSTC->RSTC_RCR = AT91C_RSTC_KEY | AT91C_RSTC_PROCRST | AT91C_RSTC_PERRST; + AT91C_BASE_RSTC->RSTC_RCR = AT91C_RSTC_KEY | AT91C_RSTC_PROCRST | AT91C_RSTC_PERRST; } void machine_shutdown(void) { - AT91C_BASE_SHDWC->SHDWC_SHCR = AT91C_SHDWC_KEY | AT91C_SHDWC_SHDW; + AT91C_BASE_SHDWC->SHDWC_SHCR = AT91C_SHDWC_KEY | AT91C_SHDWC_SHDW; } #ifdef RT_USING_FINSH @@ -49,14 +35,14 @@ FINSH_FUNCTION_EXPORT_ALIAS(rt_hw_cpu_reset, reset, restart the system); #ifdef FINSH_USING_MSH int cmd_reset(int argc, char** argv) { - rt_hw_cpu_reset(); - return 0; + rt_hw_cpu_reset(); + return 0; } int cmd_shutdown(int argc, char** argv) { - rt_hw_cpu_shutdown(); - return 0; + rt_hw_cpu_shutdown(); + return 0; } FINSH_FUNCTION_EXPORT_ALIAS(cmd_reset, __cmd_reset, restart the system.); diff --git a/bsp/at91sam9g45/platform/rt_low_level_init.c b/bsp/at91sam9g45/platform/rt_low_level_init.c index 5df468d771..b76b84fe5c 100644 --- a/bsp/at91sam9g45/platform/rt_low_level_init.c +++ b/bsp/at91sam9g45/platform/rt_low_level_init.c @@ -1,29 +1,15 @@ /* - * File : rt_low_level_init.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2015-04-14 ArdaFu first version */ - + /* write register a=address, v=value */ -#define write_reg(a,v) (*(volatile unsigned int *)(a) = (v)) +#define write_reg(a,v) (*(volatile unsigned int *)(a) = (v)) /* Processor Reset */ #define AT91C_RSTC_PROCRST (1 << 0) #define AT91C_RSTC_PERRST (1 << 2) diff --git a/bsp/at91sam9g45/platform/rt_low_level_init.h b/bsp/at91sam9g45/platform/rt_low_level_init.h index 86dcfb59dc..c79adf5284 100644 --- a/bsp/at91sam9g45/platform/rt_low_level_init.h +++ b/bsp/at91sam9g45/platform/rt_low_level_init.h @@ -1,21 +1,7 @@ /* - * File : rt_low_level_init.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -23,7 +9,7 @@ */ #ifndef __RT_LOW_LEVEL_INIT_H__ #define __RT_LOW_LEVEL_INIT_H__ - + /*-------- Stack size of CPU modes -------------------------------------------*/ #define UND_STK_SIZE 512 #define SVC_STK_SIZE 4096 diff --git a/bsp/at91sam9g45/platform/system_clock.c b/bsp/at91sam9g45/platform/system_clock.c index 59c3c320ab..551daf31e4 100644 --- a/bsp/at91sam9g45/platform/system_clock.c +++ b/bsp/at91sam9g45/platform/system_clock.c @@ -1,21 +1,7 @@ /* - * File : clock.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -28,236 +14,236 @@ static rt_list_t clocks; struct clk { - char name[32]; - rt_uint32_t rate_hz; - struct clk *parent; - rt_list_t node; + char name[32]; + rt_uint32_t rate_hz; + struct clk *parent; + rt_list_t node; }; static struct clk clk32k = { - "clk32k", - AT91C_SLOW_CLOCK, - RT_NULL, - {RT_NULL, RT_NULL}, + "clk32k", + AT91C_SLOW_CLOCK, + RT_NULL, + {RT_NULL, RT_NULL}, }; static struct clk main_clk = { - "main", - 0, - RT_NULL, - {RT_NULL, RT_NULL}, + "main", + 0, + RT_NULL, + {RT_NULL, RT_NULL}, }; static struct clk plla = { - "plla", - 0, - &main_clk, - {RT_NULL, RT_NULL}, + "plla", + 0, + &main_clk, + {RT_NULL, RT_NULL}, }; static struct clk mck = { - "mck", - 0, - NULL, - {RT_NULL, RT_NULL}, + "mck", + 0, + NULL, + {RT_NULL, RT_NULL}, }; static struct clk upllck = { - "upllck", - 480*1000*1000, - &main_clk, - {RT_NULL, RT_NULL}, + "upllck", + 480*1000*1000, + &main_clk, + {RT_NULL, RT_NULL}, }; static struct clk *const standard_pmc_clocks[] = { - /* four primary clocks */ - &clk32k, - &main_clk, - &plla, + /* four primary clocks */ + &clk32k, + &main_clk, + &plla, - /* MCK */ - &mck + /* MCK */ + &mck }; /* clocks cannot be de-registered no refcounting necessary */ struct clk *clk_get(const char *id) { - struct clk *clk; - rt_list_t *list; - - for (list = (&clocks)->next; list != &clocks; list = list->next) - { - clk = (struct clk *)rt_list_entry(list, struct clk, node); - if (rt_strcmp(id, clk->name) == 0) - return clk; - } + struct clk *clk; + rt_list_t *list; - return RT_NULL; + for (list = (&clocks)->next; list != &clocks; list = list->next) + { + clk = (struct clk *)rt_list_entry(list, struct clk, node); + if (rt_strcmp(id, clk->name) == 0) + return clk; + } + + return RT_NULL; } rt_uint32_t clk_get_rate(struct clk *clk) { - rt_uint32_t rate; + rt_uint32_t rate; - for (;;) { - rate = clk->rate_hz; - if (rate || !clk->parent) - break; - clk = clk->parent; - } - return rate; + for (;;) { + rate = clk->rate_hz; + if (rate || !clk->parent) + break; + clk = clk->parent; + } + return rate; } static void at91_upllck_init(rt_uint32_t main_clock) { - // EHCI USB use fixed 480MHz clock + // EHCI USB use fixed 480MHz clock } static struct clk *at91_css_to_clk(unsigned long css) { - switch (css) { - case AT91C_PMC_CSS_SLOW_CLK: - return &clk32k; - case AT91C_PMC_CSS_MAIN_CLK: - return &main_clk; - case AT91C_PMC_CSS_PLLA_CLK: - return &plla; - case AT91C_PMC_CSS_UPLL_CLK: - return &upllck; - } + switch (css) { + case AT91C_PMC_CSS_SLOW_CLK: + return &clk32k; + case AT91C_PMC_CSS_MAIN_CLK: + return &main_clk; + case AT91C_PMC_CSS_PLLA_CLK: + return &plla; + case AT91C_PMC_CSS_UPLL_CLK: + return &upllck; + } - return RT_NULL; + return RT_NULL; } // TODO: how to auto-set register value by OSC and MCK /* Settings at 400/133MHz */ // In datasheet, ATMEL says 12MHz main crystal startup time less than 2ms, so we // configure OSC startup timeout to 64*8/32768=15.6ms, should enough -#define BOARD_OSCOUNT (AT91C_CKGR_OSCOUNT & (64 << 8)) +#define BOARD_OSCOUNT (AT91C_CKGR_OSCOUNT & (64 << 8)) // MAINCK => Divider(DIVA) => PLLA(MULA, OUTA) => /1/2 Divider(PLLADIV2) => PLLACK -// pls. refer to doc6438G figure 24-6 on pg294. ICPLLA in reg PMC_PLLICPR +// pls. refer to doc6438G figure 24-6 on pg294. ICPLLA in reg PMC_PLLICPR // 12MHz / 3 * (199 + 1) = 800MHz // OUTA/ICPLLA can as ICPLLA:OUTA[1]:OUTA[0] = (800-PLLAOUT(MHz))/50 // PLLACOUNT field occupy bit[13:8], max value is 0x3F, then about 19.2ms -#define BOARD_CKGR_PLLA (AT91C_CKGR_SRCA | AT91C_CKGR_OUTA_0) -#define BOARD_PLLACOUNT (0x3F << 8) -#define BOARD_MULA (AT91C_CKGR_MULA & (199 << 16)) -#define BOARD_DIVA (AT91C_CKGR_DIVA & 3) +#define BOARD_CKGR_PLLA (AT91C_CKGR_SRCA | AT91C_CKGR_OUTA_0) +#define BOARD_PLLACOUNT (0x3F << 8) +#define BOARD_MULA (AT91C_CKGR_MULA & (199 << 16)) +#define BOARD_DIVA (AT91C_CKGR_DIVA & 3) // Clock Source => select(CCS) => Prescaler(PRES) => Master Clock Divider(MDIV) => MCK // => Processor Clock Divider => PCK // Master clock can refer to doc6438G figure 25-2 on pg298 // PLLADIV2=1(div 2, 400MHz), PRES=0(no div, 400MHz), // MDIV=3(Master Clock divided by 3, 133MHz), CSS=0(still Slow Clock) -#define BOARD_PRESCALER (0x00001300) //400/133MHz +#define BOARD_PRESCALER (0x00001300) //400/133MHz -#define MHz(n) ((n) * 1000 * 1000) -#define OSC_FREQ MHz(12) -#define PLLA_FREQ MHz(800) +#define MHz(n) ((n) * 1000 * 1000) +#define OSC_FREQ MHz(12) +#define PLLA_FREQ MHz(800) static void at91_plla_init(void) { - rt_uint32_t pllar, mckr; + rt_uint32_t pllar, mckr; - // Code refer to doc6438G, 25.10 Programming Sequence - /* Initialize main oscillator - ****************************/ - // enable main OSC and wait OSC startup time timeout. - AT91C_BASE_PMC->PMC_MOR = BOARD_OSCOUNT | AT91C_CKGR_MOSCEN; - while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS)); + // Code refer to doc6438G, 25.10 Programming Sequence + /* Initialize main oscillator + ****************************/ + // enable main OSC and wait OSC startup time timeout. + AT91C_BASE_PMC->PMC_MOR = BOARD_OSCOUNT | AT91C_CKGR_MOSCEN; + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS)); - /* Initialize PLLA, Set PLL to 800MHz and wait PLL stable */ - pllar = (MHz(800) - PLLA_FREQ) / MHz(50); // please refer to Table 46-15 of doc 6438G - AT91C_BASE_PMC->PMC_PLLICPR = (pllar >> 2) & 1; // ICPLLA - pllar = (pllar & 3) << 14; // OUTA - pllar |= BOARD_DIVA; // PLLA input clock as 4MHz - pllar |= BOARD_MULA; // PLLA output clock as 800MHz - pllar |= BOARD_PLLACOUNT; - pllar |= AT91C_CKGR_SRCA; // I don't known what means, but seems must set it - AT91C_BASE_PMC->PMC_PLLAR = pllar; + /* Initialize PLLA, Set PLL to 800MHz and wait PLL stable */ + pllar = (MHz(800) - PLLA_FREQ) / MHz(50); // please refer to Table 46-15 of doc 6438G + AT91C_BASE_PMC->PMC_PLLICPR = (pllar >> 2) & 1; // ICPLLA + pllar = (pllar & 3) << 14; // OUTA + pllar |= BOARD_DIVA; // PLLA input clock as 4MHz + pllar |= BOARD_MULA; // PLLA output clock as 800MHz + pllar |= BOARD_PLLACOUNT; + pllar |= AT91C_CKGR_SRCA; // I don't known what means, but seems must set it + AT91C_BASE_PMC->PMC_PLLAR = pllar; - while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKA)); + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKA)); - /* Wait for the master clock if it was already initialized */ - // make sure Master clock in READY status before operate it - while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)); + /* Wait for the master clock if it was already initialized */ + // make sure Master clock in READY status before operate it + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)); - /* Switch to fast clock - **********************/ - /* setup main clock divisor and prescaler, 400MHz/133MHz, but don't switch */ - mckr = AT91C_BASE_PMC->PMC_MCKR; - if ((mckr & AT91C_PMC_MDIV) != (BOARD_PRESCALER & AT91C_PMC_MDIV)) - { - mckr = (mckr & ~(unsigned int)AT91C_PMC_MDIV) | (BOARD_PRESCALER & AT91C_PMC_MDIV); - AT91C_BASE_PMC->PMC_MCKR = mckr; - while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)); - } + /* Switch to fast clock + **********************/ + /* setup main clock divisor and prescaler, 400MHz/133MHz, but don't switch */ + mckr = AT91C_BASE_PMC->PMC_MCKR; + if ((mckr & AT91C_PMC_MDIV) != (BOARD_PRESCALER & AT91C_PMC_MDIV)) + { + mckr = (mckr & ~(unsigned int)AT91C_PMC_MDIV) | (BOARD_PRESCALER & AT91C_PMC_MDIV); + AT91C_BASE_PMC->PMC_MCKR = mckr; + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)); + } - /* Switch to PLL + prescaler, now Switch to PLLA as source, run on the fly */ - if ((mckr & AT91C_PMC_CSS) != AT91C_PMC_CSS_PLLA_CLK) - { - mckr = (mckr & ~(unsigned int)AT91C_PMC_CSS) | AT91C_PMC_CSS_PLLA_CLK; - AT91C_BASE_PMC->PMC_MCKR = mckr; - while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)); - } + /* Switch to PLL + prescaler, now Switch to PLLA as source, run on the fly */ + if ((mckr & AT91C_PMC_CSS) != AT91C_PMC_CSS_PLLA_CLK) + { + mckr = (mckr & ~(unsigned int)AT91C_PMC_CSS) | AT91C_PMC_CSS_PLLA_CLK; + AT91C_BASE_PMC->PMC_MCKR = mckr; + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)); + } - plla.rate_hz = PLLA_FREQ; + plla.rate_hz = PLLA_FREQ; } - + #define false 0 #define true 1 int at91_clock_init(rt_uint32_t main_clock) { - unsigned tmp, freq, mckr, mdiv; - int i; + unsigned tmp, freq, mckr, mdiv; + int i; - /* - * When the bootloader initialized the main oscillator correctly, - * there's no problem using the cycle counter. But if it didn't, - * or when using oscillator bypass mode, we must be told the speed - * of the main clock. - */ - if (!main_clock) { - do { - tmp = readl(AT91C_CKGR_MCFR); - } while (!(tmp & AT91C_CKGR_MAINRDY)); - main_clock = (tmp & AT91C_CKGR_MAINF) * (AT91C_SLOW_CLOCK / 16); - } - main_clk.rate_hz = main_clock; + /* + * When the bootloader initialized the main oscillator correctly, + * there's no problem using the cycle counter. But if it didn't, + * or when using oscillator bypass mode, we must be told the speed + * of the main clock. + */ + if (!main_clock) { + do { + tmp = readl(AT91C_CKGR_MCFR); + } while (!(tmp & AT91C_CKGR_MAINRDY)); + main_clock = (tmp & AT91C_CKGR_MAINF) * (AT91C_SLOW_CLOCK / 16); + } + main_clk.rate_hz = main_clock; - at91_plla_init(); + at91_plla_init(); - at91_upllck_init(main_clock); + at91_upllck_init(main_clock); - /* - * MCK and CPU derive from one of those primary clocks. - * For now, assume this parentage won't change. - */ - mckr = readl(AT91C_PMC_MCKR); - mck.parent = at91_css_to_clk(mckr & AT91C_PMC_CSS); - freq = mck.parent->rate_hz; - freq /= (1 << ((mckr & AT91C_PMC_PRES) >> 2)); /* prescale */ - mdiv = 1 << ((mckr & AT91C_PMC_MDIV) >> 8); - if (mdiv == 8) mdiv = 3; - freq /= mdiv; /* mdiv */ - if (mckr & AT91C_PMC_PLLADIV2) freq /= 2; /* plla_div2 */ - mck.rate_hz = freq; + /* + * MCK and CPU derive from one of those primary clocks. + * For now, assume this parentage won't change. + */ + mckr = readl(AT91C_PMC_MCKR); + mck.parent = at91_css_to_clk(mckr & AT91C_PMC_CSS); + freq = mck.parent->rate_hz; + freq /= (1 << ((mckr & AT91C_PMC_PRES) >> 2)); /* prescale */ + mdiv = 1 << ((mckr & AT91C_PMC_MDIV) >> 8); + if (mdiv == 8) mdiv = 3; + freq /= mdiv; /* mdiv */ + if (mckr & AT91C_PMC_PLLADIV2) freq /= 2; /* plla_div2 */ + mck.rate_hz = freq; - /* Register the PMC's standard clocks */ - rt_list_init(&clocks); - for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) - rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node); + /* Register the PMC's standard clocks */ + rt_list_init(&clocks); + for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) + rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node); - rt_list_insert_after(&clocks, &upllck.node); + rt_list_insert_after(&clocks, &upllck.node); - /* MCK and CPU clock are "always on" */ - //clk_enable(&mck); + /* MCK and CPU clock are "always on" */ + //clk_enable(&mck); - /*rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n", - freq / 1000000, (unsigned) mck.rate_hz / 1000000, - (unsigned) main_clock / 1000000, - ((unsigned) main_clock % 1000000) / 1000);*///cause blocked + /*rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n", + freq / 1000000, (unsigned) mck.rate_hz / 1000000, + (unsigned) main_clock / 1000000, + ((unsigned) main_clock % 1000000) / 1000);*///cause blocked - return 0; + return 0; } /** @@ -265,6 +251,6 @@ int at91_clock_init(rt_uint32_t main_clock) */ void rt_hw_clock_init(void) { - at91_clock_init(MHz(12)); + at91_clock_init(MHz(12)); } diff --git a/bsp/avr32uc3b0/application.c b/bsp/avr32uc3b0/application.c index 4853570b19..6b87b226f4 100644 --- a/bsp/avr32uc3b0/application.c +++ b/bsp/avr32uc3b0/application.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2010, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -56,7 +52,7 @@ int rt_application_init() { /* create led1 thread */ rt_thread_init(&thread_led1, - "led1", + "led1", rt_thread_entry_led1, RT_NULL, &thread_led1_stack[0], diff --git a/bsp/avr32uc3b0/board.c b/bsp/avr32uc3b0/board.c index bc510b1ed5..226e59e551 100644 --- a/bsp/avr32uc3b0/board.c +++ b/bsp/avr32uc3b0/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2010, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -20,11 +16,11 @@ #include "intc.h" #include "serial.h" -#define FOSC0 12000000 -#define FCPU 60000000 -#define FHSB FCPU -#define FPBA FCPU -#define FPBB FCPU +#define FOSC0 12000000 +#define FCPU 60000000 +#define FHSB FCPU +#define FPBA FCPU +#define FPBB FCPU extern void rt_hw_serial_isr(void); extern void rt_hw_usart_init(void); @@ -34,10 +30,10 @@ extern void rt_hw_usart_init(void); */ static void rt_hw_timer_handler(void) { - // Clears the interrupt request. - Set_system_register(AVR32_COMPARE, FCPU / RT_TICK_PER_SECOND); + // Clears the interrupt request. + Set_system_register(AVR32_COMPARE, FCPU / RT_TICK_PER_SECOND); - rt_tick_increase(); + rt_tick_increase(); } /** @@ -45,35 +41,35 @@ static void rt_hw_timer_handler(void) */ static void peripherals_init(void) { - /* - * PM initialization: OSC0 = 12MHz XTAL, PLL0 = 60MHz System Clock - */ - pm_freq_param_t pm_freq_param = - { - .cpu_f = FCPU, - .pba_f = FPBA, - .osc0_f = FOSC0, - .osc0_startup = AVR32_PM_OSCCTRL0_STARTUP_2048_RCOSC - }; - pm_configure_clocks(&pm_freq_param); + /* + * PM initialization: OSC0 = 12MHz XTAL, PLL0 = 60MHz System Clock + */ + pm_freq_param_t pm_freq_param = + { + .cpu_f = FCPU, + .pba_f = FPBA, + .osc0_f = FOSC0, + .osc0_startup = AVR32_PM_OSCCTRL0_STARTUP_2048_RCOSC + }; + pm_configure_clocks(&pm_freq_param); - /* - * USART1 initialization - */ - gpio_enable_module_pin(AVR32_USART1_TXD_0_1_PIN, AVR32_USART1_TXD_0_1_FUNCTION); - gpio_enable_module_pin(AVR32_USART1_RXD_0_1_PIN, AVR32_USART1_RXD_0_1_FUNCTION); - static const usart_options_t usartOptions = { - .baudrate = 115200, - .charlength = 8, - .paritytype = USART_NO_PARITY, - .stopbits = USART_1_STOPBIT, - .channelmode = USART_NORMAL_CHMODE - }; - usart_init_rs232(&AVR32_USART1, &usartOptions, FCPU); + /* + * USART1 initialization + */ + gpio_enable_module_pin(AVR32_USART1_TXD_0_1_PIN, AVR32_USART1_TXD_0_1_FUNCTION); + gpio_enable_module_pin(AVR32_USART1_RXD_0_1_PIN, AVR32_USART1_RXD_0_1_FUNCTION); + static const usart_options_t usartOptions = { + .baudrate = 115200, + .charlength = 8, + .paritytype = USART_NO_PARITY, + .stopbits = USART_1_STOPBIT, + .channelmode = USART_NORMAL_CHMODE + }; + usart_init_rs232(&AVR32_USART1, &usartOptions, FCPU); - INTC_init_interrupts(); - INTC_register_interrupt(&rt_hw_serial_isr, AVR32_USART1_IRQ, AVR32_INTC_INT0); - AVR32_USART1.ier = AVR32_USART_IER_RXRDY_MASK; + INTC_init_interrupts(); + INTC_register_interrupt(&rt_hw_serial_isr, AVR32_USART1_IRQ, AVR32_INTC_INT0); + AVR32_USART1.ier = AVR32_USART_IER_RXRDY_MASK; } /** @@ -81,21 +77,21 @@ static void peripherals_init(void) */ static void cpu_counter_init(void) { - INTC_register_interrupt(&rt_hw_timer_handler, AVR32_CORE_COMPARE_IRQ, AVR32_INTC_INT3); - Set_system_register(AVR32_COMPARE, FCPU / RT_TICK_PER_SECOND); - Set_system_register(AVR32_COUNT, 0); + INTC_register_interrupt(&rt_hw_timer_handler, AVR32_CORE_COMPARE_IRQ, AVR32_INTC_INT3); + Set_system_register(AVR32_COMPARE, FCPU / RT_TICK_PER_SECOND); + Set_system_register(AVR32_COUNT, 0); } void rt_hw_board_init(void) { - extern struct rt_device _rt_usart_device; - extern struct avr32_serial_device uart; + extern struct rt_device _rt_usart_device; + extern struct avr32_serial_device uart; - Disable_global_interrupt(); + Disable_global_interrupt(); - peripherals_init(); - cpu_counter_init(); + peripherals_init(); + cpu_counter_init(); - rt_hw_serial_register(&_rt_usart_device, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, &uart); - rt_console_set_device("uart1"); + rt_hw_serial_register(&_rt_usart_device, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, &uart); + rt_console_set_device("uart1"); } diff --git a/bsp/avr32uc3b0/rtconfig.h b/bsp/avr32uc3b0/rtconfig.h index 621ffc2af0..16e8194a89 100644 --- a/bsp/avr32uc3b0/rtconfig.h +++ b/bsp/avr32uc3b0/rtconfig.h @@ -1,11 +1,7 @@ /* - * File : rtconfig.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2010, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -16,16 +12,16 @@ #define RTCONFIG_H_ /* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 8 /* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 /* PRIORITY_MAX*/ -#define RT_THREAD_PRIORITY_MAX 32 +#define RT_THREAD_PRIORITY_MAX 32 /* Tick per Second*/ -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 /* SECTION: RT_DEBUG */ /* Thread Debug*/ @@ -73,7 +69,7 @@ /* SECTION: Console options */ /* the buffer size of console*/ #define RT_USING_CONSOLE -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 /* SECTION: FinSH shell options */ /* Using FinSH as Shell*/ @@ -88,21 +84,21 @@ #define RT_USING_DFS_ELMFAT #define RT_DFS_ELM_WORD_ACCESS -#define RT_DFS_ELM_DRIVES 2 +#define RT_DFS_ELM_DRIVES 2 /* SECTION: DFS options */ /* the max number of mounted filesystem */ -#define DFS_FILESYSTEMS_MAX 2 -/* the max number of opened files */ -#define DFS_FD_MAX 8 -/* the max number of cached sector */ -#define DFS_CACHE_MAX_NUM 4 +#define DFS_FILESYSTEMS_MAX 2 +/* the max number of opened files */ +#define DFS_FD_MAX 8 +/* the max number of cached sector */ +#define DFS_CACHE_MAX_NUM 4 /* SECTION: RT-Thread/GUI */ //#define RT_USING_RTGUI /* name length of RTGUI object */ -#define RTGUI_NAME_MAX 12 +#define RTGUI_NAME_MAX 12 /* support 16 weight font */ #define RTGUI_USING_FONT16 /* support Chinese font */ @@ -116,6 +112,6 @@ /* use mouse cursor */ /* #define RTGUI_USING_MOUSE_CURSOR */ /* default font size in RTGUI */ -#define RTGUI_DEFAULT_FONT_SIZE 16 +#define RTGUI_DEFAULT_FONT_SIZE 16 #endif /* RTCONFIG_H_ */ diff --git a/bsp/avr32uc3b0/startup.c b/bsp/avr32uc3b0/startup.c index 0411b5d1ce..efa76a4e27 100644 --- a/bsp/avr32uc3b0/startup.c +++ b/bsp/avr32uc3b0/startup.c @@ -1,11 +1,7 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2010, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -25,19 +21,19 @@ extern void finsh_set_device(const char* device); int main(void) { #ifdef RT_USING_HEAP - extern void __heap_start__; - extern void __heap_end__; + extern void __heap_start__; + extern void __heap_end__; #endif - rt_hw_board_init(); - rt_system_timer_init(); + rt_hw_board_init(); + rt_system_timer_init(); #ifdef RT_USING_HEAP - rt_system_heap_init(&__heap_start__, &__heap_end__); + rt_system_heap_init(&__heap_start__, &__heap_end__); #endif - rt_system_scheduler_init(); - rt_application_init(); + rt_system_scheduler_init(); + rt_application_init(); #ifdef RT_USING_FINSH /* init finsh */ @@ -46,7 +42,7 @@ int main(void) #endif rt_thread_idle_init(); - rt_system_scheduler_start(); + rt_system_scheduler_start(); - return 0; + return 0; } diff --git a/bsp/beaglebone/applications/board.c b/bsp/beaglebone/applications/board.c index 7a7380c5f8..ff25dd7dd7 100644 --- a/bsp/beaglebone/applications/board.c +++ b/bsp/beaglebone/applications/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -49,7 +45,7 @@ static rt_uint32_t DMTIMER = 0; static void rt_hw_timer_isr(int vector, void* param) { - rt_tick_increase(); + rt_tick_increase(); DMTIMER_IRQSTATUS(TIMER_HW_BASE) = DMTIMER_IRQSTATUS_RAW_OVF_IT_FLAG; } @@ -71,73 +67,73 @@ static void timer_clk_init(void) while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & (1<<8))) ; - /* Select the clock source for the Timer2 instance. */ - CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) &= ~(CM_DPLL_CLKSEL_CLK_CLKSEL); - /* 32k clock source */ - CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) |= CM_DPLL_CLKSEL_CLK_CLKSEL_SEL3; + /* Select the clock source for the Timer2 instance. */ + CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) &= ~(CM_DPLL_CLKSEL_CLK_CLKSEL); + /* 32k clock source */ + CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) |= CM_DPLL_CLKSEL_CLK_CLKSEL_SEL3; - while ((CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) & CM_DPLL_CLKSEL_CLK_CLKSEL) != - CM_DPLL_CLKSEL_CLK_CLKSEL_SEL3); + while ((CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) & CM_DPLL_CLKSEL_CLK_CLKSEL) != + CM_DPLL_CLKSEL_CLK_CLKSEL_SEL3); - /* Writing to MODULEMODE field of CM_PER_TIMER7_CLKCTRL register. */ - CM_PER_TIMER7_CLKCTRL(prcm_base) |= CM_PER_CLKCTRL_MODULEMODE_ENABLE; + /* Writing to MODULEMODE field of CM_PER_TIMER7_CLKCTRL register. */ + CM_PER_TIMER7_CLKCTRL(prcm_base) |= CM_PER_CLKCTRL_MODULEMODE_ENABLE; - /* Waiting for MODULEMODE field to reflect the written value. */ - while ((CM_PER_TIMER7_CLKCTRL(prcm_base) & CM_PER_CLKCTRL_MODULEMODE) != - CM_PER_CLKCTRL_MODULEMODE_ENABLE); + /* Waiting for MODULEMODE field to reflect the written value. */ + while ((CM_PER_TIMER7_CLKCTRL(prcm_base) & CM_PER_CLKCTRL_MODULEMODE) != + CM_PER_CLKCTRL_MODULEMODE_ENABLE); - /* - * Waiting for IDLEST field in CM_PER_TIMER7_CLKCTRL register - * for the module is fully functional. - */ - while ((CM_PER_TIMER7_CLKCTRL(prcm_base) & CM_PER_CLKCTRL_IDLEST) != - CM_PER_CLKCTRL_IDLEST_FUNC); + /* + * Waiting for IDLEST field in CM_PER_TIMER7_CLKCTRL register + * for the module is fully functional. + */ + while ((CM_PER_TIMER7_CLKCTRL(prcm_base) & CM_PER_CLKCTRL_IDLEST) != + CM_PER_CLKCTRL_IDLEST_FUNC); - /* Waiting for the L4LS clock */ - while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK)); - /* Waiting for the TIMER7 clock */ - while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER7_GCLK)); + /* Waiting for the L4LS clock */ + while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK)); + /* Waiting for the TIMER7 clock */ + while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER7_GCLK)); } int rt_hw_timer_init(void) { - rt_uint32_t counter; + rt_uint32_t counter; #ifdef RT_USING_VMM DMTIMER = vmm_find_iomap("TIMER7"); #endif - timer_clk_init(); + timer_clk_init(); - /* soft reset the timer */ - DMTIMER_TIOCP_CFG(TIMER_HW_BASE) |= 1; + /* soft reset the timer */ + DMTIMER_TIOCP_CFG(TIMER_HW_BASE) |= 1; while ((DMTIMER_TIOCP_CFG(TIMER_HW_BASE) & 0x1) == 1) ; - /* calculate count */ - counter = 0xffffffff - (32768UL/RT_TICK_PER_SECOND); + /* calculate count */ + counter = 0xffffffff - (32768UL/RT_TICK_PER_SECOND); - /* set initial count */ - DMTIMER_TCRR(TIMER_HW_BASE) = counter; - /* set reload count */ - DMTIMER_TLDR(TIMER_HW_BASE) = counter; + /* set initial count */ + DMTIMER_TCRR(TIMER_HW_BASE) = counter; + /* set reload count */ + DMTIMER_TLDR(TIMER_HW_BASE) = counter; - /* set mode: auto reload */ - DMTIMER_TCLR(TIMER_HW_BASE) |= DMTIMER_TCLR_AR; + /* set mode: auto reload */ + DMTIMER_TCLR(TIMER_HW_BASE) |= DMTIMER_TCLR_AR; - /* interrupt enable for match */ - DMTIMER_IRQENABLE_SET(TIMER_HW_BASE) = DMTIMER_IRQENABLE_SET_OVF_EN_FLAG; + /* interrupt enable for match */ + DMTIMER_IRQENABLE_SET(TIMER_HW_BASE) = DMTIMER_IRQENABLE_SET_OVF_EN_FLAG; DMTIMER_IRQSTATUS(TIMER_HW_BASE) = DMTIMER_IRQSTATUS_RAW_OVF_IT_FLAG; - rt_hw_interrupt_install(TINT7, rt_hw_timer_isr, RT_NULL, "tick"); - rt_hw_interrupt_control(TINT7, 0, 0); - rt_hw_interrupt_umask(TINT7); + rt_hw_interrupt_install(TINT7, rt_hw_timer_isr, RT_NULL, "tick"); + rt_hw_interrupt_control(TINT7, 0, 0); + rt_hw_interrupt_umask(TINT7); while (DMTIMER_TWPS(TIMER_HW_BASE) != 0) ; - /* start timer */ - DMTIMER_TCLR(TIMER_HW_BASE) |= DMTIMER_TCLR_ST; + /* start timer */ + DMTIMER_TCLR(TIMER_HW_BASE) |= DMTIMER_TCLR_ST; while (DMTIMER_TWPS(TIMER_HW_BASE) != 0) ; @@ -152,7 +148,7 @@ INIT_BOARD_EXPORT(rt_hw_timer_init); void rt_hw_board_init(void) { rt_components_board_init(); - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); } void rt_hw_cpu_reset(void) diff --git a/bsp/beaglebone/applications/board.h b/bsp/beaglebone/applications/board.h index 765ab962b0..cfd794fc5b 100644 --- a/bsp/beaglebone/applications/board.h +++ b/bsp/beaglebone/applications/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2013, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/beaglebone/drivers/gpio.c b/bsp/beaglebone/drivers/gpio.c index 425fbb4f4e..9fc0280b7d 100644 --- a/bsp/beaglebone/drivers/gpio.c +++ b/bsp/beaglebone/drivers/gpio.c @@ -1,11 +1,7 @@ /* - * File : gpio.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * */ diff --git a/bsp/beaglebone/drivers/gpio.h b/bsp/beaglebone/drivers/gpio.h index afe929c45e..ffc4fce780 100644 --- a/bsp/beaglebone/drivers/gpio.h +++ b/bsp/beaglebone/drivers/gpio.h @@ -1,11 +1,7 @@ /* - * File : gpio.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * */ diff --git a/bsp/beaglebone/drivers/uart.c b/bsp/beaglebone/drivers/uart.c index b623e1571f..887bf2b1cd 100644 --- a/bsp/beaglebone/drivers/uart.c +++ b/bsp/beaglebone/drivers/uart.c @@ -1,11 +1,7 @@ /* - * File : serial.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2013, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/beaglebone/drivers/uart.h b/bsp/beaglebone/drivers/uart.h index 15f7f2c399..598bbb6532 100644 --- a/bsp/beaglebone/drivers/uart.h +++ b/bsp/beaglebone/drivers/uart.h @@ -1,11 +1,7 @@ /* - * File : serial.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2013, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/bf533/application.c b/bsp/bf533/application.c index efa5ba829f..2cdc2590e3 100644 --- a/bsp/bf533/application.c +++ b/bsp/bf533/application.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/bf533/application.h b/bsp/bf533/application.h index 31dd155126..4972ca455e 100644 --- a/bsp/bf533/application.h +++ b/bsp/bf533/application.h @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/bf533/board.c b/bsp/bf533/board.c index d920426232..5542079435 100644 --- a/bsp/bf533/board.c +++ b/bsp/bf533/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -242,7 +238,7 @@ void rt_hw_isr_install(void) *pSIC_IAR1 &= IVG_CLR(IAR1_DMA6_UARTRX_IVG); *pSIC_IAR1 |= IVG_SET(IAR1_DMA6_UARTRX_IVG,ik_ivg9); register_handler(ik_ivg9,uart_rx_isr); - *pSIC_IMASK |= DMA6_UART_RX_INT_MASK;/* ж */ + *pSIC_IMASK |= DMA6_UART_RX_INT_MASK;/* 开中断 */ } void rt_hw_board_init(void) diff --git a/bsp/bf533/board.h b/bsp/bf533/board.h index 5867259609..8ff522c01b 100644 --- a/bsp/bf533/board.h +++ b/bsp/bf533/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -23,7 +19,7 @@ #define CLOCKS_PER_SECD CCLKSPEED #define SCLOCKS_PER_SEC SCLKSPEED -//SIC_IMASKĴ +//SIC_IMASK寄存器 #define PLL_WAKEUP_INT_MASK 0x00000001 #define DMA_ERROR_INT_MASK 0x00000002 #define PPI_ERROR_INT_MASK 0x00000004 diff --git a/bsp/bf533/startup.c b/bsp/bf533/startup.c index 7d90dd2493..a56b123035 100644 --- a/bsp/bf533/startup.c +++ b/bsp/bf533/startup.c @@ -1,11 +1,7 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/bluetrum/ab32vg1-ab-prougen/.config b/bsp/bluetrum/ab32vg1-ab-prougen/.config index c5bca5ae40..5e9bfa2384 100644 --- a/bsp/bluetrum/ab32vg1-ab-prougen/.config +++ b/bsp/bluetrum/ab32vg1-ab-prougen/.config @@ -23,6 +23,7 @@ CONFIG_IDLE_THREAD_STACK_SIZE=512 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=256 +# CONFIG_RT_KSERVICE_USING_STDLIB is not set CONFIG_RT_DEBUG=y # CONFIG_RT_DEBUG_COLOR is not set # CONFIG_RT_DEBUG_INIT_CONFIG is not set @@ -258,8 +259,6 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_LIBRWS is not set # CONFIG_PKG_USING_TCPSERVER is not set # CONFIG_PKG_USING_PROTOBUF_C is not set -# CONFIG_PKG_USING_ONNX_PARSER is not set -# CONFIG_PKG_USING_ONNX_BACKEND is not set # CONFIG_PKG_USING_DLT645 is not set # CONFIG_PKG_USING_QXWZ is not set # CONFIG_PKG_USING_SMTP_CLIENT is not set @@ -274,6 +273,12 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_BTSTACK is not set # CONFIG_PKG_USING_LORAWAN_ED_STACK is not set # CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set # # security packages @@ -332,6 +337,13 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_VCONSOLE is not set # CONFIG_PKG_USING_KDB is not set # CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set # # system packages @@ -339,7 +351,6 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_GUIENGINE is not set # CONFIG_PKG_USING_CAIRO is not set # CONFIG_PKG_USING_PIXMAN is not set -# CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_FAL is not set # CONFIG_PKG_USING_FLASHDB is not set @@ -349,6 +360,9 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_CMSIS is not set # CONFIG_PKG_USING_DFS_YAFFS is not set # CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_THREAD_POOL is not set # CONFIG_PKG_USING_ROBOTS is not set # CONFIG_PKG_USING_EV is not set @@ -370,12 +384,13 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_UC_MODBUS is not set # CONFIG_PKG_USING_PPOOL is not set # CONFIG_PKG_USING_OPENAMP is not set -# CONFIG_PKG_USING_RT_PRINTF is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set # CONFIG_PKG_USING_RT_MEMCPY_CM is not set # CONFIG_PKG_USING_QFPLIB_M0_FULL is not set # CONFIG_PKG_USING_QFPLIB_M0_TINY is not set # CONFIG_PKG_USING_QFPLIB_M3 is not set # CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set # # peripheral libraries and drivers @@ -438,6 +453,24 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_VIRTUAL_SENSOR is not set # CONFIG_PKG_USING_VDEVICE is not set # CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set # # miscellaneous packages @@ -469,25 +502,24 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_HELLO is not set # CONFIG_PKG_USING_VI is not set # CONFIG_PKG_USING_KI is not set -# CONFIG_PKG_USING_NNOM is not set -# CONFIG_PKG_USING_LIBANN is not set -# CONFIG_PKG_USING_ELAPACK is not set # CONFIG_PKG_USING_ARMv7M_DWT is not set # CONFIG_PKG_USING_VT100 is not set -# CONFIG_PKG_USING_ULAPACK is not set # CONFIG_PKG_USING_UKAL is not set # CONFIG_PKG_USING_CRCLIB is not set # -# games: games run on RT-Thread console +# entertainment: terminal games and other interesting software packages # # CONFIG_PKG_USING_THREES is not set # CONFIG_PKG_USING_2048 is not set # CONFIG_PKG_USING_SNAKE is not set # CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_ACLOCK is not set # CONFIG_PKG_USING_LWGPS is not set -# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set # CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set # # Hardware Drivers Config @@ -496,14 +528,16 @@ CONFIG_RT_USING_LIBC=y # # Onboard Peripheral Drivers # -CONFIG_BSP_USING_USB_TO_USART=y # CONFIG_BSP_USING_AUDIO is not set # CONFIG_BSP_USING_SDCARD is not set # # On-chip Peripheral Drivers # +CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART0=y +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_UART2 is not set # CONFIG_BSP_USING_SDIO is not set # CONFIG_BSP_USING_I2C1 is not set # CONFIG_BSP_USING_PWM is not set diff --git a/bsp/bluetrum/ab32vg1-ab-prougen/.cproject b/bsp/bluetrum/ab32vg1-ab-prougen/.cproject index 6e4d4ca5fe..9d6c45a102 100644 --- a/bsp/bluetrum/ab32vg1-ab-prougen/.cproject +++ b/bsp/bluetrum/ab32vg1-ab-prougen/.cproject @@ -1,158 +1,157 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/bluetrum/ab32vg1-ab-prougen/README.md b/bsp/bluetrum/ab32vg1-ab-prougen/README.md index 1e56724f35..c108ff57ba 100644 --- a/bsp/bluetrum/ab32vg1-ab-prougen/README.md +++ b/bsp/bluetrum/ab32vg1-ab-prougen/README.md @@ -35,19 +35,20 @@ ab32vg1-prougen 是 中科蓝讯(Bluetrum) 推出的一款基于 RISC-V 内核 | USB 转串口 | 支持 | | | SD卡 | 支持 | | | IRDA | 即将支持 | | -| 音频接口 | 支持 | | +| 音频接口 | 支持 | 支持音频输出 | | **片上外设** | **支持情况** | **备注** | | GPIO | 支持 | PA PB PE PF | | UART | 支持 | UART0/1/2 | | SDIO | 支持 | | -| ADC | 即将支持 | | +| ADC | 支持 | 10bit ADC | | SPI | 即将支持 | 软件 SPI | | I2C | 支持 | 软件 I2C | -| RTC | 即将支持 | | +| RTC | 支持 | | | WDT | 支持 | | -| FLASH | 即将支持 | | +| FLASH | 即将支持 | 对接 FAL | | TIMER | 支持 | | | PWM | 支持 | LPWM 的 G1 G2 G3 之间是互斥的，只能三选一 | +| FM receive | 即将支持 | | | USB Device | 暂不支持 | | | USB Host | 暂不支持 | | @@ -68,8 +69,6 @@ ab32vg1-prougen 是 中科蓝讯(Bluetrum) 推出的一款基于 RISC-V 内核 本 BSP 为开发者提供 GCC 开发环境。下面介绍如何将系统运行起来。 -教学视频：https://www.bilibili.com/video/BV1RV411v75P/ - #### 硬件连接 使用数据线连接开发板到 PC，打开电源开关。 @@ -96,11 +95,12 @@ msh > 此 BSP 默认只开启了 GPIO 和 串口0 的功能，如果需使用 SD 卡、Flash 等更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下： 1. 在 bsp 下打开 env 工具。 -2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 -3. 输入`pkgs --update`命令更新软件包。 -4. 输入`scons` 命令重新编译工程。 -更多细节请参见使用指南：https://ab32vg1-example.readthedocs.io/zh/latest/introduction.html +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons` 命令重新编译工程。 ## 注意事项 @@ -110,12 +110,26 @@ msh > 编译报错的时候，如果出现重复定义的报错，可能需要在 `cconfig.h` 中手动添加以下配置 -``` +``` c #define HAVE_SIGEVENT 1 #define HAVE_SIGINFO 1 #define HAVE_SIGVAL 1 ``` +所有在中断中使用的函数或数据需要放在 RAM 中，否则会导致系统运行报错。具体做法可以参考下面 + +``` c +RT_SECTION(".irq.example.str") +static const char example_info[] = "example 0x%x"; + +RT_SECTION(".irq.example") +void example_isr(void) +{ + rt_kprintf(example_info, 11); + ... +} +``` + ## 维护人信息 - [greedyhao](https://github.com/greedyhao) diff --git a/bsp/bluetrum/ab32vg1-ab-prougen/applications/main.c b/bsp/bluetrum/ab32vg1-ab-prougen/applications/main.c index 4c330f0d44..9fa2a7204e 100644 --- a/bsp/bluetrum/ab32vg1-ab-prougen/applications/main.c +++ b/bsp/bluetrum/ab32vg1-ab-prougen/applications/main.c @@ -8,6 +8,12 @@ * 2020/12/10 greedyhao The first version */ +/** + * Notice! + * All functions or data that are called during an interrupt need to be in RAM. + * You can do it the way exception_isr() does. + */ + #include #include "board.h" diff --git a/bsp/bluetrum/ab32vg1-ab-prougen/board/Kconfig b/bsp/bluetrum/ab32vg1-ab-prougen/board/Kconfig index 2bdce74a2d..89e651a996 100644 --- a/bsp/bluetrum/ab32vg1-ab-prougen/board/Kconfig +++ b/bsp/bluetrum/ab32vg1-ab-prougen/board/Kconfig @@ -90,16 +90,16 @@ menu "On-chip Peripheral Drivers" if BSP_USING_T4_PWM config BSP_USING_T4_PWM1 bool "Enable Timer4 PWM1 (PA6)(Confit with uart0 rx)" - default n + default y endif menuconfig BSP_USING_T5_PWM bool "Enable Timer5 PWM" - default n + default y if BSP_USING_T5_PWM config BSP_USING_T5_PWM0 bool "Enable Timer5 PWM2 (PE1)" - default n + default y endif menuconfig BSP_USING_LPWM0 @@ -109,7 +109,7 @@ menu "On-chip Peripheral Drivers" comment "G1, G2 and G3 are mutually exclusive" config BSP_USING_LPWM0_G1 bool "Enable LPWM0 G1 (PE4)" - default n + default y endif menuconfig BSP_USING_LPWM1 @@ -119,7 +119,7 @@ menu "On-chip Peripheral Drivers" comment "G1, G2 and G3 are mutually exclusive" config BSP_USING_LPWM1_G3 bool "Enable LPWM1 G3 (PA1)" - default n + default y endif menuconfig BSP_USING_LPWM2 @@ -129,7 +129,7 @@ menu "On-chip Peripheral Drivers" comment "G1, G2 and G3 are mutually exclusive" config BSP_USING_LPWM2_G2 bool "Enable LPWM2 G2 (PE0)" - default n + default y config BSP_USING_LPWM2_G3 bool "Enable LPWM2 G3 (PA2)" default n @@ -148,7 +148,7 @@ menu "On-chip Peripheral Drivers" if BSP_USING_TIM config BSP_USING_TIM1 bool "Enable TIM1" - default n + default y config BSP_USING_TIM2 bool "Enable TIM2" @@ -189,7 +189,7 @@ menu "On-chip Peripheral Drivers" if BSP_USING_ADC config BSP_USING_ADC0 bool "Enable ADC0" - default n + default y endif endmenu diff --git a/bsp/bluetrum/ab32vg1-ab-prougen/board/board.c b/bsp/bluetrum/ab32vg1-ab-prougen/board/board.c index ec128bb1f0..f10ea4a6c8 100644 --- a/bsp/bluetrum/ab32vg1-ab-prougen/board/board.c +++ b/bsp/bluetrum/ab32vg1-ab-prougen/board/board.c @@ -13,10 +13,21 @@ int rt_hw_usart_init(void); void my_printf(const char *format, ...); +void my_print_r(const void *buf, uint16_t cnt); void timer0_cfg(uint32_t ticks); void rt_soft_isr(int vector, void *param); void cpu_irq_comm(void); void set_cpu_irq_comm(void (*irq_hook)(void)); +void load_cache(); +void sys_error_hook(uint8_t err_no); + +typedef void (*os_cache_setfunc_func)(void *load_cache_func, void *io_read); +typedef void (*spiflash_init_func)(uint8_t sf_read, uint8_t dummy); + +#define os_cache_setfunc ((os_cache_setfunc_func) 0x84024) + +static struct rt_mutex mutex_spiflash = {0}; +extern volatile rt_uint8_t rt_interrupt_nest; extern uint32_t __heap_start, __heap_end; void hal_printf(const char *fmt, ...) @@ -55,6 +66,7 @@ void hal_printf(const char *fmt, ...) va_end(args); } +RT_SECTION(".irq.timer") void timer0_isr(int vector, void *param) { rt_interrupt_enter(); @@ -132,3 +144,52 @@ void rt_hw_us_delay(rt_uint32_t us) { } + +RT_SECTION(".irq.cache") +void cache_init(void) +{ + os_cache_setfunc(load_cache, NULL); + rt_mutex_init(&mutex_spiflash, "flash_mutex", RT_IPC_FLAG_FIFO); +} + +RT_SECTION(".irq.cache") +void os_spiflash_lock(void) +{ + // if (rt_thread_self()->stat == RT_THREAD_RUNNING) { + if ((rt_thread_self() != RT_NULL) && (rt_interrupt_nest == 0)) { + rt_mutex_take(&mutex_spiflash, RT_WAITING_FOREVER); + } +} + +RT_SECTION(".irq.cache") +void os_spiflash_unlock(void) +{ + // if (rt_thread_self()->stat == RT_THREAD_RUNNING) { + if ((rt_thread_self() != RT_NULL) && (rt_interrupt_nest == 0)) { + rt_mutex_release(&mutex_spiflash); + } +} + +RT_SECTION(".irq.err.str") +static const char stack_info[] = "thread sp=0x%x name=%s"; + +void rt_hw_console_output(const char *str) +{ + my_printf(str); +} + +/** + * @brief print exception error + * @note Every message needed to print, must put in .comm exction. + */ +RT_SECTION(".irq.err") +void exception_isr(void) +{ + extern long list_thread(void); + sys_error_hook(1); + + rt_console_set_device(RT_NULL); + rt_kprintf(stack_info, rt_thread_self()->sp, rt_thread_self()->name); + + while(1); +} diff --git a/bsp/bluetrum/ab32vg1-ab-prougen/board/ports/audio/drv_sound.c b/bsp/bluetrum/ab32vg1-ab-prougen/board/ports/audio/drv_sound.c index 10dbcf63fb..d250a3fc94 100644 --- a/bsp/bluetrum/ab32vg1-ab-prougen/board/ports/audio/drv_sound.c +++ b/bsp/bluetrum/ab32vg1-ab-prougen/board/ports/audio/drv_sound.c @@ -15,15 +15,17 @@ #define SAI_AUDIO_FREQUENCY_44K ((uint32_t)44100u) #define SAI_AUDIO_FREQUENCY_48K ((uint32_t)48000u) -#define TX_FIFO_SIZE (1024) +#define TX_FIFO_SIZE (1024) struct sound_device { struct rt_audio_device audio; struct rt_audio_configure replay_config; + rt_sem_t semaphore; + rt_thread_t thread; rt_uint8_t *tx_fifo; rt_uint8_t *rx_fifo; - rt_uint8_t volume; + rt_uint8_t volume; }; static struct sound_device snd_dev = {0}; @@ -105,6 +107,17 @@ void dac_start(void) //AUANGCON1 |= BIT(3); // pa mute } +RT_SECTION(".irq.audio") +void audio_sem_post(void) +{ + rt_sem_release(snd_dev.semaphore); +} + +void audio_sem_pend(void) +{ + rt_sem_take(snd_dev.semaphore, RT_WAITING_FOREVER); +} + void saia_frequency_set(uint32_t frequency) { if (frequency == SAI_AUDIO_FREQUENCY_48K) { @@ -359,7 +372,7 @@ static rt_err_t sound_start(struct rt_audio_device *audio, int stream) DACVOLCON = 0x7fff; // -60DB DACVOLCON |= BIT(20); - AUBUFCON |= BIT(1) | BIT(4); + AUBUFCON |= BIT(1); } return RT_EOK; @@ -391,7 +404,10 @@ rt_size_t sound_transmit(struct rt_audio_device *audio, const void *writeBuf, vo snd_dev = (struct sound_device *)audio->parent.user_data; while (tmp_size-- > 0) { - while(AUBUFCON & BIT(8)); // aubuf full + if (AUBUFCON & BIT(8)) { // aubuf full + AUBUFCON |= BIT(1) | BIT(4); + audio_sem_pend(); + } AUBUFDATA = ((const uint32_t *)writeBuf)[count++]; } @@ -429,18 +445,32 @@ static struct rt_audio_ops ops = .buffer_info = sound_buffer_info, }; -void audio_isr(int vector, void *param) +RT_SECTION(".irq.audio") +static void audio_isr(int vector, void *param) { rt_interrupt_enter(); //Audio buffer pend if (AUBUFCON & BIT(5)) { AUBUFCON |= BIT(1); //Audio Buffer Pend Clear - rt_audio_tx_complete(&snd_dev.audio); + AUBUFCON &= ~BIT(4); + audio_sem_post(); } rt_interrupt_leave(); } +static void audio_thread_entry(void *parameter) +{ + while (1) + { + if (snd_dev.audio.replay->activated == RT_TRUE) { + rt_audio_tx_complete(&snd_dev.audio); + } else { + rt_thread_mdelay(50); + } + } +} + static int rt_hw_sound_init(void) { rt_uint8_t *tx_fifo = RT_NULL; @@ -464,6 +494,26 @@ static int rt_hw_sound_init(void) snd_dev.rx_fifo = rx_fifo; + snd_dev.semaphore = rt_sem_create("snd", 0, RT_IPC_FLAG_FIFO); + if (snd_dev.semaphore == RT_NULL) + { + return -RT_ENOMEM; + } + + snd_dev.thread = rt_thread_create( + "audio", + audio_thread_entry, + RT_NULL, + 1024, + 20, // must equal or lower than tshell priority + 5 + ); + + if (snd_dev.thread != RT_NULL) + { + rt_thread_startup(snd_dev.thread); + } + /* init default configuration */ { snd_dev.replay_config.samplerate = 48000; diff --git a/bsp/bluetrum/ab32vg1-ab-prougen/link.lds b/bsp/bluetrum/ab32vg1-ab-prougen/link.lds index 4f79ad883a..d785c3d92c 100644 --- a/bsp/bluetrum/ab32vg1-ab-prougen/link.lds +++ b/bsp/bluetrum/ab32vg1-ab-prougen/link.lds @@ -3,8 +3,8 @@ __max_flash_size = 1024k; __data_ram_size = 8k; __stack_ram_size = 4k; -__comm_ram_size = 83k; -__heap_ram_size = 29k; +__comm_ram_size = 42k; +__heap_ram_size = 70k; __base = 0x10000000; @@ -47,26 +47,43 @@ SECTIONS PROVIDE(__ctors_end__ = .); . = ALIGN(4); - *components*drivers**.o (.text*) - *components.o (.text*) + *save-restore.o (.text* .rodata*) + *libcpu*cpu*context_gcc.o (.text* .rodata*) + *libcpu*cpu*interrupt.o (.text* .rodata*) + *libcpu**.o (.rodata*) + + *components*drivers*misc*pin.o(.text*) + *components*drivers*misc*adc.o(.text*) + + . = ALIGN(4); + *src*ipc.o (.text* .rodata*) + *src*irq.o (.text* .rodata*) + *src*object.o (.text* .rodata*) + *src*thread.o (.text* .rodata*) + *src*timer.o (.text* .rodata*) + *src*mempool.o (.text* .rodata*) + *src*scheduler.o (.text* .rodata*) + *src*clock.o (.text* .rodata*) + *src*kservice.o (.text* .rodata*) + *src*device.o (.text* .rodata*) + *src*idle.o (.text* .rodata*) + *src*components.o (.text* .rodata*) } > ram1 AT > flash .comm __comm_vma : { . = ALIGN(4); KEEP(*(.vector)) - EXCLUDE_FILE(*components*finsh**.o *components*libc**.o *dfs*filesystems**.o - *romfs.o *lib_a**.o *divdi3.o *moddi3.o *divdf3.o *muldf3.o *eqtf2.o *getf2.o - *letf2.o *multf3.o *subtf3.o *fixtfsi.o *floatsitf.o *extenddftf2.o - *trunctfdf2.o *_clzsi2.o *cp-demangle.o *unwind*.o - *fixdfsi.o *addsf3.o *divsf3.o *eqsf2.o *gesf2.o *float*.o - *lesf2.o *mulsf3.o *subsf3.o *fixsfsi.o *fixunssfsi.o) *(.text) - *finsh*shell.o (.text*) + *(.irq*) + /*applications**.o (.text .rodata)*/ + *hal_libraries*ab32vg1_hal**.o (.text .rodata) *(.text.unlikely) *(.text.startup) - EXCLUDE_FILE (*components*libc**.o *dfs*filesystems**.o *romfs.o *lib_a**.o - *cp-demangle.o *divdf3.o *muldf3.o *multf3.o *unwind*.o *_clz.o) *(.rodata) - *(.rodata.name) - EXCLUDE_FILE(*lib_a**.o *cp-demangle.o *cp-demangle.o) *(.rodata.str1.4) + *hal_drivers**.o (.rodata) + *audio*drv_sound.o (.rodata) + *system_ab32vgx.o (.rodata) + EXCLUDE_FILE(*lib_a**.o *cp-demangle.o *cp-demangle.o + *src*mem.o *src*memheap.o *dfs**.o *components.o *drivers*sdio**.o *cmd.o *msh_file.o + *drv_sdio.o *drv_wdt.o) *(.rodata.str1.4) EXCLUDE_FILE(*lib_a**.o *unwind*.o) *(.srodata) *(.rela*) *(.data*) @@ -98,7 +115,6 @@ SECTIONS } > heap .flash : { - . = ALIGN(4); __fsymtab_start = .; KEEP(*(FSymTab)) @@ -109,6 +125,7 @@ SECTIONS KEEP(*(VSymTab)) __vsymtab_end = .; + . = ALIGN(4); *(.text*) *(.rodata*) *(.srodata*) diff --git a/bsp/bluetrum/ab32vg1-ab-prougen/rtconfig.h b/bsp/bluetrum/ab32vg1-ab-prougen/rtconfig.h index 272966b74c..f2fa939c6e 100644 --- a/bsp/bluetrum/ab32vg1-ab-prougen/rtconfig.h +++ b/bsp/bluetrum/ab32vg1-ab-prougen/rtconfig.h @@ -145,23 +145,26 @@ /* peripheral libraries and drivers */ +/* AI packages */ + + /* miscellaneous packages */ /* samples: kernel and components samples */ -/* games: games run on RT-Thread console */ +/* entertainment: terminal games and other interesting software packages */ /* Hardware Drivers Config */ /* Onboard Peripheral Drivers */ -#define BSP_USING_USB_TO_USART /* On-chip Peripheral Drivers */ +#define BSP_USING_UART #define BSP_USING_UART0 /* Board extended module Drivers */ diff --git a/bsp/bluetrum/ab32vg1-ab-prougen/rtconfig.py b/bsp/bluetrum/ab32vg1-ab-prougen/rtconfig.py index 0642f6429a..5afb84e1ba 100644 --- a/bsp/bluetrum/ab32vg1-ab-prougen/rtconfig.py +++ b/bsp/bluetrum/ab32vg1-ab-prougen/rtconfig.py @@ -15,7 +15,7 @@ if os.getenv('RTT_CC'): if CROSS_TOOL == 'gcc': PLATFORM = 'gcc' - EXEC_PATH = r'D:/Softwares/RT-ThreadStudio/repo/Extract/ToolChain_Support_Packages/RISC-V/RISC-V-GCC/10.1.0/bin' + EXEC_PATH = r'D:/program_files/programming/RT-ThreadStudio/repo/Extract/ToolChain_Support_Packages/RISC-V/RISC-V-GCC/10.1.0/bin' else: print('Please make sure your toolchains is GNU GCC!') exit(0) @@ -39,7 +39,7 @@ if PLATFORM == 'gcc': OBJCPY = PREFIX + 'objcopy' # DEVICE = ' -mcmodel=medany -march=rv32imc -mabi=ilp32 -fsingle-precision-constant' - DEVICE = ' -mcmodel=medany -march=rv32imc -mabi=ilp32' + DEVICE = ' -mcmodel=medany -march=rv32imc -mabi=ilp32 -msave-restore' # CFLAGS = DEVICE + ' -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields' CFLAGS = DEVICE + ' -D_USE_LONG_TIME_T' AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' diff --git a/bsp/bluetrum/libraries/hal_drivers/drv_hwtimer.c b/bsp/bluetrum/libraries/hal_drivers/drv_hwtimer.c index aaa3ddbea2..856307e0db 100644 --- a/bsp/bluetrum/libraries/hal_drivers/drv_hwtimer.c +++ b/bsp/bluetrum/libraries/hal_drivers/drv_hwtimer.c @@ -68,6 +68,37 @@ static struct ab32_hwtimer ab32_hwtimer_obj[] = #endif }; +RT_SECTION(".irq.timer") +static void _rt_device_hwtimer_isr(rt_hwtimer_t *timer) +{ + RT_ASSERT(timer != RT_NULL); + + timer->overflow ++; + + if (timer->cycles != 0) + { + timer->cycles --; + } + + if (timer->cycles == 0) + { + timer->cycles = timer->reload; + + if (timer->mode == HWTIMER_MODE_ONESHOT) + { + if (timer->ops->stop != RT_NULL) + { + timer->ops->stop(timer); + } + } + + if (timer->parent.rx_indicate != RT_NULL) + { + timer->parent.rx_indicate(&timer->parent, sizeof(struct rt_hwtimerval)); + } + } +} + static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) { uint32_t prescaler_value = 0; @@ -185,25 +216,26 @@ static const struct rt_hwtimer_ops _ops = }; #if defined(BSP_USING_TIM2) || defined(BSP_USING_TIM4) || defined(BSP_USING_TIM5) +RT_SECTION(".irq.timer") void timer2_4_5_isr(int vector, void *param) { rt_interrupt_enter(); #ifdef BSP_USING_TIM2 if (ab32_hwtimer_obj[TIM2_INDEX].tim_handle[TMRxCON] != 0) { ab32_hwtimer_obj[TIM2_INDEX].tim_handle[TMRxCPND] = BIT(9); - rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM2_INDEX].time_device); + _rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM2_INDEX].time_device); } #endif #ifdef BSP_USING_TIM4 if (ab32_hwtimer_obj[TIM4_INDEX].tim_handle[TMRxCON] != 0) { ab32_hwtimer_obj[TIM4_INDEX].tim_handle[TMRxCPND] = BIT(9); - rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM4_INDEX].time_device); + _rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM4_INDEX].time_device); } #endif #ifdef BSP_USING_TIM5 if (ab32_hwtimer_obj[TIM5_INDEX].tim_handle[TMRxCON] != 0) { ab32_hwtimer_obj[TIM5_INDEX].tim_handle[TMRxCPND] = BIT(9); - rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM5_INDEX].time_device); + _rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM5_INDEX].time_device); } #endif rt_interrupt_leave(); @@ -211,21 +243,23 @@ void timer2_4_5_isr(int vector, void *param) #endif #ifdef BSP_USING_TIM3 +RT_SECTION(".irq.timer") void timer3_isr(int vector, void *param) { rt_interrupt_enter(); ab32_hwtimer_obj[TIM3_INDEX].tim_handle[TMRxCPND] = BIT(9); - rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM3_INDEX].time_device); + _rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM3_INDEX].time_device); rt_interrupt_leave(); } #endif #ifdef BSP_USING_TIM1 +RT_SECTION(".irq.timer") void timer1_isr(int vector, void *param) { rt_interrupt_enter(); ab32_hwtimer_obj[TIM1_INDEX].tim_handle[TMRxCPND] = BIT(9); - rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM1_INDEX].time_device); + _rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM1_INDEX].time_device); rt_interrupt_leave(); } #endif diff --git a/bsp/bluetrum/libraries/hal_drivers/drv_rtc.c b/bsp/bluetrum/libraries/hal_drivers/drv_rtc.c index 9b4eb0a15f..ccbaac1909 100644 --- a/bsp/bluetrum/libraries/hal_drivers/drv_rtc.c +++ b/bsp/bluetrum/libraries/hal_drivers/drv_rtc.c @@ -253,6 +253,7 @@ static rt_err_t rt_hw_rtc_register(rt_device_t device, const char *name, rt_uint } #ifdef RT_USING_ALARM +RT_SECTION(".irq.rtc") static void rtc_isr(int vector, void *param) { rt_interrupt_enter(); diff --git a/bsp/bluetrum/libraries/hal_drivers/drv_sdio.c b/bsp/bluetrum/libraries/hal_drivers/drv_sdio.c index a9ca1a2b6d..fed9eae2d4 100644 --- a/bsp/bluetrum/libraries/hal_drivers/drv_sdio.c +++ b/bsp/bluetrum/libraries/hal_drivers/drv_sdio.c @@ -496,6 +496,7 @@ static rt_int32_t rthw_sd_detect(struct rt_mmcsd_host *host) * @param host rt_mmcsd_host * @retval None */ +RT_SECTION(".irq.sdio") void rthw_sdio_irq_process(struct rt_mmcsd_host *host) { int complete = 0; @@ -616,6 +617,7 @@ static rt_err_t _dma_rxconfig(rt_uint32_t *dst, int Size) return RT_EOK; } +RT_SECTION(".irq.sdio") void sdio_isr(int vector, void *param) { /* enter interrupt */ diff --git a/bsp/bluetrum/libraries/hal_drivers/drv_usart.c b/bsp/bluetrum/libraries/hal_drivers/drv_usart.c index 4b790830fc..f09cffee61 100644 --- a/bsp/bluetrum/libraries/hal_drivers/drv_usart.c +++ b/bsp/bluetrum/libraries/hal_drivers/drv_usart.c @@ -10,6 +10,7 @@ #include "board.h" #include "drv_usart.h" +#include #ifdef RT_USING_SERIAL @@ -147,6 +148,7 @@ static int ab32_putc(struct rt_serial_device *serial, char ch) return 1; } +RT_SECTION(".irq.usart") static int ab32_getc(struct rt_serial_device *serial) { int ch; @@ -168,6 +170,72 @@ static rt_size_t ab32_dma_transmit(struct rt_serial_device *serial, rt_uint8_t * return -1; } +extern struct finsh_shell *shell; + +RT_SECTION(".irq.usart") +static rt_err_t shell_rx_ind(void) +{ + RT_ASSERT(shell != RT_NULL); + + /* release semaphore to let finsh thread rx data */ + rt_sem_release(&shell->rx_sem); + + return RT_EOK; +} + +RT_SECTION(".irq.usart") +void uart_irq_process(struct rt_serial_device *serial) +{ + int ch = -1; + rt_base_t level; + struct rt_serial_rx_fifo* rx_fifo; + + /* interrupt mode receive */ + rx_fifo = (struct rt_serial_rx_fifo*)serial->serial_rx; + RT_ASSERT(rx_fifo != RT_NULL); + + while (1) + { + ch = serial->ops->getc(serial); + if (ch == -1) break; + + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + rx_fifo->buffer[rx_fifo->put_index] = ch; + rx_fifo->put_index += 1; + if (rx_fifo->put_index >= serial->config.bufsz) rx_fifo->put_index = 0; + + /* if the next position is read index, discard this 'read char' */ + if (rx_fifo->put_index == rx_fifo->get_index) + { + rx_fifo->get_index += 1; + rx_fifo->is_full = RT_TRUE; + if (rx_fifo->get_index >= serial->config.bufsz) rx_fifo->get_index = 0; + + // _serial_check_buffer_size(); + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } + + rt_size_t rx_length; + + /* get rx length */ + level = rt_hw_interrupt_disable(); + rx_length = (rx_fifo->put_index >= rx_fifo->get_index)? (rx_fifo->put_index - rx_fifo->get_index): + (serial->config.bufsz - (rx_fifo->get_index - rx_fifo->put_index)); + rt_hw_interrupt_enable(level); + + if (rx_length) + { + shell_rx_ind(); + } +} + +RT_SECTION(".irq.usart") static void uart_isr(int vector, void *param) { rt_interrupt_enter(); @@ -175,19 +243,19 @@ static void uart_isr(int vector, void *param) #ifdef BSP_USING_UART0 if(hal_uart_getflag(UART0_BASE, UART_FLAG_RXPND)) //RX one byte finish { - rt_hw_serial_isr(&(uart_obj[UART0_INDEX].serial), RT_SERIAL_EVENT_RX_IND); + uart_irq_process(&(uart_obj[UART0_INDEX].serial)); } #endif #ifdef BSP_USING_UART1 if(hal_uart_getflag(UART1_BASE, UART_FLAG_RXPND)) //RX one byte finish { - rt_hw_serial_isr(&(uart_obj[UART1_INDEX].serial), RT_SERIAL_EVENT_RX_IND); + uart_irq_process(&(uart_obj[UART1_INDEX].serial)); } #endif #ifdef BSP_USING_UART2 if(hal_uart_getflag(UART2_BASE, UART_FLAG_RXPND)) //RX one byte finish { - rt_hw_serial_isr(&(uart_obj[UART2_INDEX].serial), RT_SERIAL_EVENT_RX_IND); + uart_irq_process(&(uart_obj[UART2_INDEX].serial)); } #endif diff --git a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_adc.h b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_adc.h index b1b68b844b..0329c5ff20 100644 --- a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_adc.h +++ b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_adc.h @@ -13,22 +13,22 @@ * @defgroup ADC_channels * @{ */ -#define ADC_CHANNEL_0 (1u << 0) -#define ADC_CHANNEL_1 (1u << 1) -#define ADC_CHANNEL_2 (1u << 2) -#define ADC_CHANNEL_3 (1u << 3) -#define ADC_CHANNEL_4 (1u << 4) -#define ADC_CHANNEL_5 (1u << 5) -#define ADC_CHANNEL_6 (1u << 6) -#define ADC_CHANNEL_7 (1u << 7) -#define ADC_CHANNEL_8 (1u << 8) -#define ADC_CHANNEL_9 (1u << 9) -#define ADC_CHANNEL_10 (1u << 10) -#define ADC_CHANNEL_11 (1u << 11) -#define ADC_CHANNEL_12 (1u << 12) -#define ADC_CHANNEL_13 (1u << 13) -#define ADC_CHANNEL_14 (1u << 14) -#define ADC_CHANNEL_15 (1u << 15) +#define ADC_CHANNEL_0 (1u << 0) /* PA5 */ +#define ADC_CHANNEL_1 (1u << 1) /* PA6 */ +#define ADC_CHANNEL_2 (1u << 2) /* PA7 */ +#define ADC_CHANNEL_3 (1u << 3) /* PB1 */ +#define ADC_CHANNEL_4 (1u << 4) /* PB2 */ +#define ADC_CHANNEL_5 (1u << 5) /* PB3 */ +#define ADC_CHANNEL_6 (1u << 6) /* PB4 */ +#define ADC_CHANNEL_7 (1u << 7) /* PE5 */ +#define ADC_CHANNEL_8 (1u << 8) /* PE6 */ +#define ADC_CHANNEL_9 (1u << 9) /* PE7 */ +#define ADC_CHANNEL_10 (1u << 10) /* PF2 */ +#define ADC_CHANNEL_11 (1u << 11) /* VRTC */ +#define ADC_CHANNEL_12 (1u << 12) /* WKO */ +#define ADC_CHANNEL_13 (1u << 13) /* BGOP */ +#define ADC_CHANNEL_14 (1u << 14) /* VBAT */ +#define ADC_CHANNEL_15 (1u << 15) /* VUSB */ /** * @} * diff --git a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_rtc.h b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_rtc.h index 6961d8da90..3bb686e593 100644 --- a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_rtc.h +++ b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_rtc.h @@ -34,7 +34,7 @@ enum // RTCCPND #define RTC_CPND_1S (0x1u << 18) /*!< Clear RTC 1S pending */ -#define RTC_CPND_ALM (0x1u << 17) /*!< Clear RTC alarm pendind */ +#define RTC_CPND_ALM (0x1u << 17) /*!< Clear RTC alarm pendind */ // RTCCON0 #define RTC_CON0_PWRUP_FIRST (0x01u << 7) /*!< RTC first power up flag */ diff --git a/bsp/bluetrum/libraries/hal_libraries/bmsis/source/startup.S b/bsp/bluetrum/libraries/hal_libraries/bmsis/source/startup.S index fe42435c07..3245135038 100644 --- a/bsp/bluetrum/libraries/hal_libraries/bmsis/source/startup.S +++ b/bsp/bluetrum/libraries/hal_libraries/bmsis/source/startup.S @@ -37,20 +37,22 @@ _start: la a2, __bss_size call memset + call cache_init + la a0, __comm_vma sw a0, PICADR(zero) call entry -// la ra, __exception -// jr ra + la ra, __exception + jr ra .section .vector, "ax" -// .org 0x10 -//__exception: -// li sp, 0x10600 //出错后，不破坏错误点的堆栈数据 -// jal exception_isr -// 1: j 1b -// mret + .org 0x10 +__exception: + li sp, 0x10600 //出错后，不破坏错误点的堆栈数据 + jal exception_isr + 1: j 1b + mret .org 0x40 jal x0, low_prio_irq diff --git a/bsp/ck802/applications/main.c b/bsp/ck802/applications/main.c index 65d7985e43..174a00cf97 100644 --- a/bsp/ck802/applications/main.c +++ b/bsp/ck802/applications/main.c @@ -1,22 +1,8 @@ /* - * File : clock.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/ck802/drivers/board.c b/bsp/ck802/drivers/board.c index 55f0e47331..df1a263f73 100644 --- a/bsp/ck802/drivers/board.c +++ b/bsp/ck802/drivers/board.c @@ -1,21 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/ck802/drivers/board.h b/bsp/ck802/drivers/board.h index 9c404a29c7..431fa6221a 100644 --- a/bsp/ck802/drivers/board.h +++ b/bsp/ck802/drivers/board.h @@ -1,21 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/ck802/drivers/board_coretimer.c b/bsp/ck802/drivers/board_coretimer.c index d3275e68d8..2a0bdb0ccb 100644 --- a/bsp/ck802/drivers/board_coretimer.c +++ b/bsp/ck802/drivers/board_coretimer.c @@ -1,21 +1,7 @@ /* - * File : board_coretimer.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/ck802/drivers/board_coretimer.h b/bsp/ck802/drivers/board_coretimer.h index e911c8e838..264486632c 100644 --- a/bsp/ck802/drivers/board_coretimer.h +++ b/bsp/ck802/drivers/board_coretimer.h @@ -1,21 +1,7 @@ /* - * File : board_coretimer.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/ck802/drivers/board_uart.c b/bsp/ck802/drivers/board_uart.c index 5dd7018f56..3d6f20e820 100644 --- a/bsp/ck802/drivers/board_uart.c +++ b/bsp/ck802/drivers/board_uart.c @@ -1,21 +1,7 @@ /* - * File : board_uart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/ck802/libraries/startup_gcc.S b/bsp/ck802/libraries/startup_gcc.S index 07122fcf98..577d85ed5e 100644 --- a/bsp/ck802/libraries/startup_gcc.S +++ b/bsp/ck802/libraries/startup_gcc.S @@ -1,21 +1,7 @@ /* - * File : startup.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -24,10 +10,10 @@ #undef VIC_TSPR -#define VIC_TSPR 0xE000EC10 +#define VIC_TSPR 0xE000EC10 #ifndef CONFIG_SEPARATE_IRQ_SP -#define CONFIG_SEPARATE_IRQ_SP 1 +#define CONFIG_SEPARATE_IRQ_SP 1 #endif #ifndef CONFIG_ARCH_INTERRUPTSTACK @@ -37,81 +23,81 @@ .import SysTick_Handler .import PendSV_Handler - .section .vectors - .align 10 - .globl __Vectors - .type __Vectors, @object + .section .vectors + .align 10 + .globl __Vectors + .type __Vectors, @object __Vectors: - .long Reset_Handler /* 0: Reset Handler */ - - .rept 15 - .long Default_Handler /* 60 0x40 */ - .endr /* 64 0x40 */ - - .long Default_Handler /* 64 0x44 */ - - .rept 5 - .long Default_Handler /* 88 0x58 */ - .endr /* 92 0x5C */ - - .long PendSV_Handler /* 92 0x5C */ - - .rept 9 - .long Default_Handler /* 128 0x80 */ - .endr + .long Reset_Handler /* 0: Reset Handler */ - /* External interrupts */ - .long GPIOA_IRQHandler /* 32# 0: GPIOA */ /*128 0x80 */ - .long SysTick_Handler /* 1: System Tick */ - .long TIMA0_IRQHandler /* 2: TimerA0 */ - .long TIMA1_IRQHandler /* 3: TimerA1 */ - .long Default_Handler - .long WDT_IRQHandler /* 5: WDT */ - .long USART0_IRQHandler /* 6: UART0 */ - .long USART1_IRQHandler /* 0x27 39 7: UART1 */ - .long USART2_IRQHandler /* 8: UART2 */ - .long I2C0_IRQHandler /* 9: I2C0 */ - .long I2C1_IRQHandler /* 10: I2C1 */ - .long SPI1_IRQHandler /* 11: SPI1 */ - .long SPI0_IRQHandler /* 12: SPI0 */ - .long RTC_IRQHandler /* 13: RTC */ - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long DMAC_IRQHandler /* 17: DMAC */ - .long Default_Handler - .long PWM_IRQHandler /* 19: PWM */ - .long Default_Handler - .long USART3_IRQHandler /* 21: UART3 */ - .long Default_Handler - .long TIMB0_IRQHandler /* 23: TimerB0 */ - .long TIMB1_IRQHandler /* 24: TimerB1 */ - .long Default_Handler - .long AES_IRQHandler /* 26: AES */ - .long GPIOB_IRQHandler /* 27: GPIOB */ - .long Default_Handler - .long SHA_IRQHandler /* 29: SHA */ + .rept 15 + .long Default_Handler /* 60 0x40 */ + .endr /* 64 0x40 */ - .size __Vectors, . - __Vectors + .long Default_Handler /* 64 0x44 */ - .text - .align 1 + .rept 5 + .long Default_Handler /* 88 0x58 */ + .endr /* 92 0x5C */ + + .long PendSV_Handler /* 92 0x5C */ + + .rept 9 + .long Default_Handler /* 128 0x80 */ + .endr + + /* External interrupts */ + .long GPIOA_IRQHandler /* 32# 0: GPIOA */ /*128 0x80 */ + .long SysTick_Handler /* 1: System Tick */ + .long TIMA0_IRQHandler /* 2: TimerA0 */ + .long TIMA1_IRQHandler /* 3: TimerA1 */ + .long Default_Handler + .long WDT_IRQHandler /* 5: WDT */ + .long USART0_IRQHandler /* 6: UART0 */ + .long USART1_IRQHandler /* 0x27 39 7: UART1 */ + .long USART2_IRQHandler /* 8: UART2 */ + .long I2C0_IRQHandler /* 9: I2C0 */ + .long I2C1_IRQHandler /* 10: I2C1 */ + .long SPI1_IRQHandler /* 11: SPI1 */ + .long SPI0_IRQHandler /* 12: SPI0 */ + .long RTC_IRQHandler /* 13: RTC */ + .long Default_Handler + .long Default_Handler + .long Default_Handler + .long DMAC_IRQHandler /* 17: DMAC */ + .long Default_Handler + .long PWM_IRQHandler /* 19: PWM */ + .long Default_Handler + .long USART3_IRQHandler /* 21: UART3 */ + .long Default_Handler + .long TIMB0_IRQHandler /* 23: TimerB0 */ + .long TIMB1_IRQHandler /* 24: TimerB1 */ + .long Default_Handler + .long AES_IRQHandler /* 26: AES */ + .long GPIOB_IRQHandler /* 27: GPIOB */ + .long Default_Handler + .long SHA_IRQHandler /* 29: SHA */ + + .size __Vectors, . - __Vectors + + .text + .align 1 _start: - .text - .align 1 - .globl Reset_Handler - .type Reset_Handler, %function + .text + .align 1 + .globl Reset_Handler + .type Reset_Handler, %function Reset_Handler: /* under normal circumstances, it should not be opened */ #ifndef CONFIG_SYSTEM_SECURE - lrw r0, 0x80000000 - mtcr r0, psr + lrw r0, 0x80000000 + mtcr r0, psr #endif /* Initialize the normal stack pointer from the linker definition. */ - lrw a1, __StackTop - mov sp, a1 + lrw a1, __StackTop + mov sp, a1 /* * The ranges of copy from/to are specified by following symbols @@ -121,22 +107,22 @@ Reset_Handler: * * All addresses must be aligned to 4 bytes boundary. */ - lrw r1, __erodata - lrw r2, __data_start__ - lrw r3, __data_end__ + lrw r1, __erodata + lrw r2, __data_start__ + lrw r3, __data_end__ - subu r3, r2 - cmpnei r3, 0 - bf .L_loop0_done + subu r3, r2 + cmpnei r3, 0 + bf .L_loop0_done .L_loop0: - ldw r0, (r1, 0) - stw r0, (r2, 0) - addi r1, 4 - addi r2, 4 - subi r3, 4 - cmpnei r3, 0 - bt .L_loop0 + ldw r0, (r1, 0) + stw r0, (r2, 0) + addi r1, 4 + addi r2, 4 + subi r3, 4 + cmpnei r3, 0 + bt .L_loop0 .L_loop0_done: @@ -147,98 +133,98 @@ Reset_Handler: * * Both addresses must be aligned to 4 bytes boundary. */ - lrw r1, __bss_start__ - lrw r2, __bss_end__ + lrw r1, __bss_start__ + lrw r2, __bss_end__ - movi r0, 0 + movi r0, 0 - subu r2, r1 - cmpnei r2, 0 - bf .L_loop1_done + subu r2, r1 + cmpnei r2, 0 + bf .L_loop1_done .L_loop1: - stw r0, (r1, 0) - addi r1, 4 - subi r2, 4 - cmpnei r2, 0 - bt .L_loop1 + stw r0, (r1, 0) + addi r1, 4 + subi r2, 4 + cmpnei r2, 0 + bt .L_loop1 .L_loop1_done: #ifdef CONFIG_SEPARATE_IRQ_SP - lrw r0, g_top_irqstack - mtcr r0, cr<15, 1> + lrw r0, g_top_irqstack + mtcr r0, cr<15, 1> - mfcr r0, cr<31, 0> - bseti r0, 14 - mtcr r0, cr<31, 0> + mfcr r0, cr<31, 0> + bseti r0, 14 + mtcr r0, cr<31, 0> #endif #ifndef __NO_SYSTEM_INIT - bsr SystemInit + bsr SystemInit #endif //#ifndef __NO_BOARD_INIT -// bsr board_init +// bsr board_init //#endif //VIC init... - lrw r0, VIC_TSPR - movi r1, 0xb00 - stw r1, (r0) + lrw r0, VIC_TSPR + movi r1, 0xb00 + stw r1, (r0) - bsr entry + bsr entry __exit: - bkpt - .size Reset_Handler, . - Reset_Handler + bkpt + .size Reset_Handler, . - Reset_Handler - .align 1 - .weak Default_Handler - .type Default_Handler, %function + .align 1 + .weak Default_Handler + .type Default_Handler, %function Default_Handler: - br Default_Handler - .size Default_Handler, . - Default_Handler + br Default_Handler + .size Default_Handler, . - Default_Handler .section .bss - .align 2 - .globl g_intstackalloc - .global g_intstackbase - .global g_top_irqstack + .align 2 + .globl g_intstackalloc + .global g_intstackbase + .global g_top_irqstack g_intstackalloc: g_intstackbase: - .space CONFIG_ARCH_INTERRUPTSTACK + .space CONFIG_ARCH_INTERRUPTSTACK g_top_irqstack: /* Macro to define default handlers. Default handler * will be weak symbol and just dead loops. They can be * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm - def_irq_handler CORET_IRQHandler - def_irq_handler TIMA0_IRQHandler - def_irq_handler TIMA1_IRQHandler - def_irq_handler TIMB0_IRQHandler - def_irq_handler TIMB1_IRQHandler - def_irq_handler USART0_IRQHandler - def_irq_handler USART1_IRQHandler - def_irq_handler USART2_IRQHandler - def_irq_handler USART3_IRQHandler - def_irq_handler GPIOA_IRQHandler - def_irq_handler GPIOB_IRQHandler - def_irq_handler I2C0_IRQHandler - def_irq_handler I2C1_IRQHandler - def_irq_handler SPI0_IRQHandler - def_irq_handler SPI1_IRQHandler - def_irq_handler RTC_IRQHandler - def_irq_handler WDT_IRQHandler - def_irq_handler PWM_IRQHandler - def_irq_handler DMAC_IRQHandler - def_irq_handler AES_IRQHandler - def_irq_handler SHA_IRQHandler + def_irq_handler CORET_IRQHandler + def_irq_handler TIMA0_IRQHandler + def_irq_handler TIMA1_IRQHandler + def_irq_handler TIMB0_IRQHandler + def_irq_handler TIMB1_IRQHandler + def_irq_handler USART0_IRQHandler + def_irq_handler USART1_IRQHandler + def_irq_handler USART2_IRQHandler + def_irq_handler USART3_IRQHandler + def_irq_handler GPIOA_IRQHandler + def_irq_handler GPIOB_IRQHandler + def_irq_handler I2C0_IRQHandler + def_irq_handler I2C1_IRQHandler + def_irq_handler SPI0_IRQHandler + def_irq_handler SPI1_IRQHandler + def_irq_handler RTC_IRQHandler + def_irq_handler WDT_IRQHandler + def_irq_handler PWM_IRQHandler + def_irq_handler DMAC_IRQHandler + def_irq_handler AES_IRQHandler + def_irq_handler SHA_IRQHandler - .end + .end diff --git a/bsp/dm365/applications/application.c b/bsp/dm365/applications/application.c index 897f5ef149..3d5207b516 100644 --- a/bsp/dm365/applications/application.c +++ b/bsp/dm365/applications/application.c @@ -1,25 +1,11 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version + * Date Author Notes + * 2011-01-13 weety first version */ @@ -41,57 +27,57 @@ int main(void) { - int timeout = 0; + int timeout = 0; /* Filesystem Initialization */ #ifdef RT_USING_DFS - { + { #if defined(RT_USING_DFS_ROMFS) - if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0) - { - rt_kprintf("ROM File System initialized!\n"); - } - else - rt_kprintf("ROM File System initialzation failed!\n"); + if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0) + { + rt_kprintf("ROM File System initialized!\n"); + } + else + rt_kprintf("ROM File System initialzation failed!\n"); #endif #if defined(RT_USING_DFS_UFFS) - { - /* mount flash device as flash directory */ - if(dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0) - rt_kprintf("UFFS File System initialized!\n"); - else - rt_kprintf("UFFS File System initialzation failed!\n"); - } + { + /* mount flash device as flash directory */ + if(dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0) + rt_kprintf("UFFS File System initialized!\n"); + else + rt_kprintf("UFFS File System initialzation failed!\n"); + } #endif #ifdef RT_USING_SDIO - timeout = 0; - while ((rt_device_find("sd0") == RT_NULL) && (timeout++ < RT_TICK_PER_SECOND*2)) - { - rt_thread_delay(1); - } + timeout = 0; + while ((rt_device_find("sd0") == RT_NULL) && (timeout++ < RT_TICK_PER_SECOND*2)) + { + rt_thread_delay(1); + } - if (timeout < RT_TICK_PER_SECOND*2) - { - /* mount sd card fat partition 1 as root directory */ - if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) - { - rt_kprintf("File System initialized!\n"); - } - else - rt_kprintf("File System initialzation failed!%d\n", rt_get_errno()); - } - else - { - rt_kprintf("No SD card found.\n"); - } + if (timeout < RT_TICK_PER_SECOND*2) + { + /* mount sd card fat partition 1 as root directory */ + if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) + { + rt_kprintf("File System initialized!\n"); + } + else + rt_kprintf("File System initialzation failed!%d\n", rt_get_errno()); + } + else + { + rt_kprintf("No SD card found.\n"); + } #endif - } + } #endif - /* put user application code here */ + /* put user application code here */ } @@ -101,14 +87,14 @@ int main(void) #include void nfs_start(void) { - nfs_init(); + nfs_init(); - if (dfs_mount(RT_NULL, "/nfs", "nfs", 0, RT_NFS_HOST_EXPORT) == 0) - { - rt_kprintf("NFSv3 File System initialized!\n"); - } - else - rt_kprintf("NFSv3 File System initialzation failed!\n"); + if (dfs_mount(RT_NULL, "/nfs", "nfs", 0, RT_NFS_HOST_EXPORT) == 0) + { + rt_kprintf("NFSv3 File System initialized!\n"); + } + else + rt_kprintf("NFSv3 File System initialzation failed!\n"); } #include "finsh.h" diff --git a/bsp/dm365/applications/board.c b/bsp/dm365/applications/board.c index 53b45c875e..0a4d9596b1 100644 --- a/bsp/dm365/applications/board.c +++ b/bsp/dm365/applications/board.c @@ -1,25 +1,11 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2010-11-13 weety first version + * Date Author Notes + * 2010-11-13 weety first version */ @@ -33,28 +19,28 @@ */ /*@{*/ #if defined(__CC_ARM) - extern int Image$$ER_ZI$$ZI$$Base; - extern int Image$$ER_ZI$$ZI$$Length; - extern int Image$$ER_ZI$$ZI$$Limit; + extern int Image$$ER_ZI$$ZI$$Base; + extern int Image$$ER_ZI$$ZI$$Length; + extern int Image$$ER_ZI$$ZI$$Limit; #elif (defined (__GNUC__)) - rt_uint8_t _irq_stack_start[1024]; - rt_uint8_t _fiq_stack_start[1024]; - rt_uint8_t _undefined_stack_start[512]; - rt_uint8_t _abort_stack_start[512]; - rt_uint8_t _svc_stack_start[1024] RT_SECTION(".nobss"); - extern unsigned char __bss_start; - extern unsigned char __bss_end; + rt_uint8_t _irq_stack_start[1024]; + rt_uint8_t _fiq_stack_start[1024]; + rt_uint8_t _undefined_stack_start[512]; + rt_uint8_t _abort_stack_start[512]; + rt_uint8_t _svc_stack_start[1024] RT_SECTION(".nobss"); + extern unsigned char __bss_start; + extern unsigned char __bss_end; #endif extern void rt_hw_clock_init(void); extern void rt_hw_uart_init(void); static struct mem_desc dm365_mem_desc[] = { - { 0x80000000, 0x88000000-1, 0x80000000, SECT_RW_CB, 0, SECT_MAPPED }, /* 128M cached SDRAM memory */ - { 0xA0000000, 0xA8000000-1, 0x80000000, SECT_RW_NCNB, 0, SECT_MAPPED }, /* 128M No cached SDRAM memory */ - { 0xFFFF0000, 0xFFFF1000-1, 0x80000000, SECT_TO_PAGE, PAGE_RO_CB, PAGE_MAPPED }, /* isr vector table */ - { 0x01C00000, 0x02000000-1, 0x01C00000, SECT_RW_NCNB, 0, SECT_MAPPED }, /* CFG BUS peripherals */ - { 0x02000000, 0x0A000000-1, 0x02000000, SECT_RW_NCNB, 0, SECT_MAPPED }, /* AEMIF */ + { 0x80000000, 0x88000000-1, 0x80000000, SECT_RW_CB, 0, SECT_MAPPED }, /* 128M cached SDRAM memory */ + { 0xA0000000, 0xA8000000-1, 0x80000000, SECT_RW_NCNB, 0, SECT_MAPPED }, /* 128M No cached SDRAM memory */ + { 0xFFFF0000, 0xFFFF1000-1, 0x80000000, SECT_TO_PAGE, PAGE_RO_CB, PAGE_MAPPED }, /* isr vector table */ + { 0x01C00000, 0x02000000-1, 0x01C00000, SECT_RW_NCNB, 0, SECT_MAPPED }, /* CFG BUS peripherals */ + { 0x02000000, 0x0A000000-1, 0x02000000, SECT_RW_NCNB, 0, SECT_MAPPED }, /* AEMIF */ }; @@ -63,7 +49,7 @@ static struct mem_desc dm365_mem_desc[] = { */ void rt_timer_handler(int vector, void *param) { - rt_tick_increase(); + rt_tick_increase(); } /** @@ -71,70 +57,70 @@ void rt_timer_handler(int vector, void *param) */ void rt_hw_timer_init() { - /* timer0, input clocks 24MHz */ - volatile timer_regs_t *regs = - (volatile timer_regs_t*)DAVINCI_TIMER1_BASE;//DAVINCI_TIMER0_BASE; + /* timer0, input clocks 24MHz */ + volatile timer_regs_t *regs = + (volatile timer_regs_t*)DAVINCI_TIMER1_BASE;//DAVINCI_TIMER0_BASE; - psc_change_state(DAVINCI_DM365_LPSC_TIMER0, 3); - psc_change_state(DAVINCI_DM365_LPSC_TIMER1, 3); + psc_change_state(DAVINCI_DM365_LPSC_TIMER0, 3); + psc_change_state(DAVINCI_DM365_LPSC_TIMER1, 3); - /*disable timer*/ - regs->tcr &= ~(0x3UL << 6); + /*disable timer*/ + regs->tcr &= ~(0x3UL << 6); - //TIMMODE 32BIT UNCHAINED MODE - regs->tgcr |=(0x1UL << 2); + //TIMMODE 32BIT UNCHAINED MODE + regs->tgcr |=(0x1UL << 2); - /*not in reset timer */ - regs->tgcr |= (0x1UL << 0); + /*not in reset timer */ + regs->tgcr |= (0x1UL << 0); - //regs->tgcr &= ~(0x1UL << 1); + //regs->tgcr &= ~(0x1UL << 1); - /* set Period Registers */ - regs->prd12 = 24000000/RT_TICK_PER_SECOND; - regs->tim12 = 0; + /* set Period Registers */ + regs->prd12 = 24000000/RT_TICK_PER_SECOND; + regs->tim12 = 0; - /* Set enable mode */ - regs->tcr |= (0x2UL << 6); //period mode - + /* Set enable mode */ + regs->tcr |= (0x2UL << 6); //period mode - /* install interrupt handler */ - rt_hw_interrupt_install(IRQ_DM365_TINT2, rt_timer_handler, - RT_NULL, "timer1_12");//IRQ_DM365_TINT0_TINT12 - rt_hw_interrupt_umask(IRQ_DM365_TINT2);//IRQ_DM365_TINT2 + + /* install interrupt handler */ + rt_hw_interrupt_install(IRQ_DM365_TINT2, rt_timer_handler, + RT_NULL, "timer1_12");//IRQ_DM365_TINT0_TINT12 + rt_hw_interrupt_umask(IRQ_DM365_TINT2);//IRQ_DM365_TINT2 } -#define LSR_DR 0x01 /* Data ready */ -#define LSR_THRE 0x20 /* Xmit holding register empty */ -#define BPS 115200 /* serial baudrate */ +#define LSR_DR 0x01 /* Data ready */ +#define LSR_THRE 0x20 /* Xmit holding register empty */ +#define BPS 115200 /* serial baudrate */ typedef struct uartport { - volatile rt_uint32_t rbr; - volatile rt_uint32_t ier; - volatile rt_uint32_t fcr; - volatile rt_uint32_t lcr; - volatile rt_uint32_t mcr; - volatile rt_uint32_t lsr; - volatile rt_uint32_t msr; - volatile rt_uint32_t scr; - volatile rt_uint32_t dll; - volatile rt_uint32_t dlh; - - volatile rt_uint32_t res[2]; - volatile rt_uint32_t pwremu_mgmt; - volatile rt_uint32_t mdr; + volatile rt_uint32_t rbr; + volatile rt_uint32_t ier; + volatile rt_uint32_t fcr; + volatile rt_uint32_t lcr; + volatile rt_uint32_t mcr; + volatile rt_uint32_t lsr; + volatile rt_uint32_t msr; + volatile rt_uint32_t scr; + volatile rt_uint32_t dll; + volatile rt_uint32_t dlh; + + volatile rt_uint32_t res[2]; + volatile rt_uint32_t pwremu_mgmt; + volatile rt_uint32_t mdr; }uartport; #define thr rbr #define iir fcr -#define UART0 ((struct uartport *)DAVINCI_UART0_BASE) +#define UART0 ((struct uartport *)DAVINCI_UART0_BASE) static void davinci_uart_putc(char c) { while (!(UART0->lsr & LSR_THRE)); - UART0->thr = c; + UART0->thr = c; } /** @@ -145,35 +131,35 @@ static void davinci_uart_putc(char c) */ void rt_hw_console_output(const char* str) { - while (*str) - { - if (*str=='\n') - { - davinci_uart_putc('\r'); - } + while (*str) + { + if (*str=='\n') + { + davinci_uart_putc('\r'); + } - davinci_uart_putc(*str++); - } + davinci_uart_putc(*str++); + } } static void rt_hw_console_init(void) { - rt_uint32_t divisor; - - divisor = (24000000 + (BPS * (16 / 2))) / (16 * BPS); - UART0->ier = 0; - UART0->lcr = 0x83; //8N1 - UART0->dll = 0; - UART0->dlh = 0; - UART0->lcr = 0x03; - UART0->mcr = 0x03; //RTS,CTS - UART0->fcr = 0x07; //FIFO - UART0->lcr = 0x83; - UART0->dll = divisor & 0xff; - UART0->dlh = (divisor >> 8) & 0xff; - UART0->lcr = 0x03; - UART0->mdr = 0; //16x over-sampling - UART0->pwremu_mgmt = 0x6000; + rt_uint32_t divisor; + + divisor = (24000000 + (BPS * (16 / 2))) / (16 * BPS); + UART0->ier = 0; + UART0->lcr = 0x83; //8N1 + UART0->dll = 0; + UART0->dlh = 0; + UART0->lcr = 0x03; + UART0->mcr = 0x03; //RTS,CTS + UART0->fcr = 0x07; //FIFO + UART0->lcr = 0x83; + UART0->dll = divisor & 0xff; + UART0->dlh = (divisor >> 8) & 0xff; + UART0->lcr = 0x03; + UART0->mdr = 0; //16x over-sampling + UART0->pwremu_mgmt = 0x6000; } /** @@ -181,35 +167,35 @@ static void rt_hw_console_init(void) */ void rt_hw_board_init() { - /* initialize console */ - rt_hw_console_init(); + /* initialize console */ + rt_hw_console_init(); - /* initialize mmu */ - rt_hw_mmu_init(dm365_mem_desc, sizeof(dm365_mem_desc)/sizeof(dm365_mem_desc[0])); + /* initialize mmu */ + rt_hw_mmu_init(dm365_mem_desc, sizeof(dm365_mem_desc)/sizeof(dm365_mem_desc[0])); - /* initialize hardware interrupt */ - rt_hw_interrupt_init(); + /* initialize hardware interrupt */ + rt_hw_interrupt_init(); - /* initialize the system clock */ - rt_hw_clock_init(); + /* initialize the system clock */ + rt_hw_clock_init(); - /* initialize heap memory system */ + /* initialize heap memory system */ #ifdef __CC_ARM - rt_system_heap_init((void*)&Image$$ER_ZI$$ZI$$Limit, (void*)0x88000000); + rt_system_heap_init((void*)&Image$$ER_ZI$$ZI$$Limit, (void*)0x88000000); #else - rt_system_heap_init((void*)&__bss_end, (void*)0x88000000); + rt_system_heap_init((void*)&__bss_end, (void*)0x88000000); #endif - /* initialize early device */ + /* initialize early device */ #ifdef RT_USING_COMPONENTS_INIT - rt_components_board_init(); + rt_components_board_init(); #endif #ifdef RT_USING_CONSOLE - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); #endif - /* initialize timer0 */ - rt_hw_timer_init(); + /* initialize timer0 */ + rt_hw_timer_init(); } diff --git a/bsp/dm365/applications/board.h b/bsp/dm365/applications/board.h index 9eb29d9522..b8763d9938 100644 --- a/bsp/dm365/applications/board.h +++ b/bsp/dm365/applications/board.h @@ -1,25 +1,11 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version + * Date Author Notes + * 2011-01-13 weety first version */ diff --git a/bsp/dm365/drivers/davinci_emac.c b/bsp/dm365/drivers/davinci_emac.c index 67e803e3c3..7ad539fb09 100644 --- a/bsp/dm365/drivers/davinci_emac.c +++ b/bsp/dm365/drivers/davinci_emac.c @@ -1,25 +1,11 @@ /* - * File : davinci_emac.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version + * Date Author Notes + * 2011-01-13 weety first version */ @@ -29,8 +15,8 @@ #include #include "davinci_emac.h" -#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<29)) -#define CACHE_LINE_SIZE 32 +#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<29)) +#define CACHE_LINE_SIZE 32 extern void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size); extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size); @@ -38,22 +24,22 @@ extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size); /* EMAC internal utility function */ static inline rt_uint32_t emac_virt_to_phys(void *addr) { - return (rt_uint32_t)addr; + return (rt_uint32_t)addr; } static inline rt_uint32_t virt_to_phys(void *addr) { - return (rt_uint32_t)addr; + return (rt_uint32_t)addr; } /* Cache macros - Packet buffers would be from pbuf pool which is cached */ #define EMAC_VIRT_NOCACHE(addr) (addr) #define EMAC_CACHE_INVALIDATE(addr, size) \ - mmu_invalidate_dcache(addr, size) + mmu_invalidate_dcache(addr, size) #define EMAC_CACHE_WRITEBACK(addr, size) \ - mmu_clean_dcache(addr, size) + mmu_clean_dcache(addr, size) #define EMAC_CACHE_WRITEBACK_INVALIDATE(addr, size) \ - mmu_clean_invalidated_dcache(addr, size) + mmu_clean_invalidated_dcache(addr, size) /* DM644x does not have BD's in cached memory - so no cache functions */ #define BD_CACHE_INVALIDATE(addr, size) @@ -67,34 +53,34 @@ static struct emac_priv davinci_emac_device; static unsigned long emac_bus_frequency; static unsigned long mdio_max_freq; -#define EMAC_AUTONEG_TIMEOUT 5000000 -#define EMAC_LINK_TIMEOUT 500000 +#define EMAC_AUTONEG_TIMEOUT 5000000 +#define EMAC_LINK_TIMEOUT 500000 /* EMAC TX Host Error description strings */ static char *emac_txhost_errcodes[16] = { - "No error", "SOP error", "Ownership bit not set in SOP buffer", - "Zero Next Buffer Descriptor Pointer Without EOP", - "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error", - "Reserved", "Reserved", "Reserved", "Reserved", "Reserved", - "Reserved", "Reserved", "Reserved", "Reserved" + "No error", "SOP error", "Ownership bit not set in SOP buffer", + "Zero Next Buffer Descriptor Pointer Without EOP", + "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error", + "Reserved", "Reserved", "Reserved", "Reserved", "Reserved", + "Reserved", "Reserved", "Reserved", "Reserved" }; /* EMAC RX Host Error description strings */ static char *emac_rxhost_errcodes[16] = { - "No error", "Reserved", "Ownership bit not set in input buffer", - "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved", - "Reserved", "Reserved", "Reserved", "Reserved", "Reserved", - "Reserved", "Reserved", "Reserved", "Reserved" + "No error", "Reserved", "Ownership bit not set in input buffer", + "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved", + "Reserved", "Reserved", "Reserved", "Reserved", "Reserved", + "Reserved", "Reserved", "Reserved", "Reserved" }; -#define emac_read(reg) davinci_readl(priv->emac_base + (reg)) +#define emac_read(reg) davinci_readl(priv->emac_base + (reg)) #define emac_write(reg, val) davinci_writel(val, priv->emac_base + (reg)) -#define emac_ctrl_read(reg) davinci_readl((priv->ctrl_base + (reg))) +#define emac_ctrl_read(reg) davinci_readl((priv->ctrl_base + (reg))) #define emac_ctrl_write(reg, val) davinci_writel(val, (priv->ctrl_base + (reg))) -#define emac_mdio_read(reg) davinci_readl(priv->mdio_base + (reg)) +#define emac_mdio_read(reg) davinci_readl(priv->mdio_base + (reg)) #define emac_mdio_write(reg, val) davinci_writel(val, (priv->mdio_base + (reg))) static void emac_int_enable(struct emac_priv *priv); @@ -105,74 +91,74 @@ static int emac_init_txch(struct emac_priv *priv, rt_uint32_t ch); /* Wait until mdio is ready for next command */ #define MDIO_WAIT_FOR_USER_ACCESS\ - while ((emac_mdio_read((MDIO_USERACCESS(0))) &\ - MDIO_USERACCESS_GO) != 0) + while ((emac_mdio_read((MDIO_USERACCESS(0))) &\ + MDIO_USERACCESS_GO) != 0) static int emac_mii_read(struct emac_priv *priv, int phy_id, int phy_reg) { - unsigned int phy_data = 0; - unsigned int phy_control; + unsigned int phy_data = 0; + unsigned int phy_control; - /* Wait until mdio is ready for next command */ - MDIO_WAIT_FOR_USER_ACCESS; + /* Wait until mdio is ready for next command */ + MDIO_WAIT_FOR_USER_ACCESS; - phy_control = (MDIO_USERACCESS_GO | - MDIO_USERACCESS_READ | - ((phy_reg << 21) & MDIO_USERACCESS_REGADR) | - ((phy_id << 16) & MDIO_USERACCESS_PHYADR) | - (phy_data & MDIO_USERACCESS_DATA)); - emac_mdio_write(MDIO_USERACCESS(0), phy_control); + phy_control = (MDIO_USERACCESS_GO | + MDIO_USERACCESS_READ | + ((phy_reg << 21) & MDIO_USERACCESS_REGADR) | + ((phy_id << 16) & MDIO_USERACCESS_PHYADR) | + (phy_data & MDIO_USERACCESS_DATA)); + emac_mdio_write(MDIO_USERACCESS(0), phy_control); - /* Wait until mdio is ready for next command */ - MDIO_WAIT_FOR_USER_ACCESS; + /* Wait until mdio is ready for next command */ + MDIO_WAIT_FOR_USER_ACCESS; - return emac_mdio_read(MDIO_USERACCESS(0)) & MDIO_USERACCESS_DATA; + return emac_mdio_read(MDIO_USERACCESS(0)) & MDIO_USERACCESS_DATA; } static int emac_mii_write(struct emac_priv *priv, int phy_id, - int phy_reg, rt_uint16_t phy_data) + int phy_reg, rt_uint16_t phy_data) { - unsigned int control; + unsigned int control; - /* until mdio is ready for next command */ - MDIO_WAIT_FOR_USER_ACCESS; + /* until mdio is ready for next command */ + MDIO_WAIT_FOR_USER_ACCESS; - control = (MDIO_USERACCESS_GO | - MDIO_USERACCESS_WRITE | - ((phy_reg << 21) & MDIO_USERACCESS_REGADR) | - ((phy_id << 16) & MDIO_USERACCESS_PHYADR) | - (phy_data & MDIO_USERACCESS_DATA)); - emac_mdio_write(MDIO_USERACCESS(0), control); + control = (MDIO_USERACCESS_GO | + MDIO_USERACCESS_WRITE | + ((phy_reg << 21) & MDIO_USERACCESS_REGADR) | + ((phy_id << 16) & MDIO_USERACCESS_PHYADR) | + (phy_data & MDIO_USERACCESS_DATA)); + emac_mdio_write(MDIO_USERACCESS(0), control); - return 0; + return 0; } static int emac_mii_reset(struct emac_priv *priv) { - unsigned int clk_div; - int mdio_bus_freq = emac_bus_frequency; + unsigned int clk_div; + int mdio_bus_freq = emac_bus_frequency; - if (mdio_max_freq && mdio_bus_freq) - clk_div = ((mdio_bus_freq / mdio_max_freq) - 1); - else - clk_div = 0xFF; + if (mdio_max_freq && mdio_bus_freq) + clk_div = ((mdio_bus_freq / mdio_max_freq) - 1); + else + clk_div = 0xFF; - clk_div &= MDIO_CONTROL_CLKDIV; + clk_div &= MDIO_CONTROL_CLKDIV; - /* Set enable and clock divider in MDIOControl */ - emac_mdio_write(MDIO_CONTROL, (clk_div | MDIO_CONTROL_ENABLE)); + /* Set enable and clock divider in MDIOControl */ + emac_mdio_write(MDIO_CONTROL, (clk_div | MDIO_CONTROL_ENABLE)); - return 0; + return 0; } /* Duplex, half or full. */ -#define DUPLEX_HALF 0x00 -#define DUPLEX_FULL 0x01 +#define DUPLEX_HALF 0x00 +#define DUPLEX_FULL 0x01 static void udelay(rt_uint32_t us) { @@ -183,83 +169,83 @@ static void udelay(rt_uint32_t us) static void davinci_emac_phy_reset(rt_device_t dev) { - int i; - rt_uint16_t status, adv; - struct emac_priv *priv = dev->user_data;; + int i; + rt_uint16_t status, adv; + struct emac_priv *priv = dev->user_data;; - adv = ADVERTISE_CSMA | ADVERTISE_ALL; - emac_mii_write(priv, priv->phy_addr, MII_ADVERTISE, adv); - rt_kprintf("%s: Starting autonegotiation...\n", dev->parent.name); - emac_mii_write(priv, priv->phy_addr, MII_BMCR, (BMCR_ANENABLE - | BMCR_ANRESTART)); + adv = ADVERTISE_CSMA | ADVERTISE_ALL; + emac_mii_write(priv, priv->phy_addr, MII_ADVERTISE, adv); + rt_kprintf("%s: Starting autonegotiation...\n", dev->parent.name); + emac_mii_write(priv, priv->phy_addr, MII_BMCR, (BMCR_ANENABLE + | BMCR_ANRESTART)); - for (i = 0; i < EMAC_AUTONEG_TIMEOUT / 100; i++) { - status = emac_mii_read(priv, priv->phy_addr, MII_BMSR); - if (status & BMSR_ANEGCOMPLETE) - break; - udelay(100); - } + for (i = 0; i < EMAC_AUTONEG_TIMEOUT / 100; i++) { + status = emac_mii_read(priv, priv->phy_addr, MII_BMSR); + if (status & BMSR_ANEGCOMPLETE) + break; + udelay(100); + } - if (status & BMSR_ANEGCOMPLETE) - rt_kprintf("%s: Autonegotiation complete\n", dev->parent.name); - else - rt_kprintf("%s: Autonegotiation timed out (status=0x%04x)\n", - dev->parent.name, status); + if (status & BMSR_ANEGCOMPLETE) + rt_kprintf("%s: Autonegotiation complete\n", dev->parent.name); + else + rt_kprintf("%s: Autonegotiation timed out (status=0x%04x)\n", + dev->parent.name, status); } static int davinci_emac_phy_init(rt_device_t dev) { - struct emac_priv *priv = dev->user_data; - rt_uint16_t phy_id, status, adv, lpa; - int media, speed, duplex; - int i; + struct emac_priv *priv = dev->user_data; + rt_uint16_t phy_id, status, adv, lpa; + int media, speed, duplex; + int i; - /* Check if the PHY is up to snuff... */ - phy_id = emac_mii_read(priv, priv->phy_addr, MII_PHYSID1); - if (phy_id == 0xffff) { - rt_kprintf("%s: No PHY present\n", dev->parent.name); - return 0; - } + /* Check if the PHY is up to snuff... */ + phy_id = emac_mii_read(priv, priv->phy_addr, MII_PHYSID1); + if (phy_id == 0xffff) { + rt_kprintf("%s: No PHY present\n", dev->parent.name); + return 0; + } - status = emac_mii_read(priv, priv->phy_addr, MII_BMSR); - if (!(status & BMSR_LSTATUS)) { - /* Try to re-negotiate if we don't have link already. */ - davinci_emac_phy_reset(dev); + status = emac_mii_read(priv, priv->phy_addr, MII_BMSR); + if (!(status & BMSR_LSTATUS)) { + /* Try to re-negotiate if we don't have link already. */ + davinci_emac_phy_reset(dev); - for (i = 0; i < EMAC_LINK_TIMEOUT / 100; i++) { - status = emac_mii_read(priv, priv->phy_addr, MII_BMSR); - if (status & BMSR_LSTATUS) - break; - udelay(100); - } - } + for (i = 0; i < EMAC_LINK_TIMEOUT / 100; i++) { + status = emac_mii_read(priv, priv->phy_addr, MII_BMSR); + if (status & BMSR_LSTATUS) + break; + udelay(100); + } + } - if (!(status & BMSR_LSTATUS)) { - rt_kprintf("%s: link down (status: 0x%04x)\n", - dev->parent.name, status); - priv->link = 0; - eth_device_linkchange(&priv->parent, RT_FALSE); - return 0; - } else { - adv = emac_mii_read(priv, priv->phy_addr, MII_ADVERTISE); - lpa = emac_mii_read(priv, priv->phy_addr, MII_LPA); - media = mii_nway_result(lpa & adv); - speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) - ? 1 : 0); - duplex = (media & ADVERTISE_FULL) ? 1 : 0; - rt_kprintf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n", - dev->parent.name, - speed ? "100" : "10", - duplex ? "full" : "half", - lpa); - priv->speed = speed; - priv->duplex = duplex; - priv->link = 1; - eth_device_linkchange(&priv->parent, RT_TRUE); + if (!(status & BMSR_LSTATUS)) { + rt_kprintf("%s: link down (status: 0x%04x)\n", + dev->parent.name, status); + priv->link = 0; + eth_device_linkchange(&priv->parent, RT_FALSE); + return 0; + } else { + adv = emac_mii_read(priv, priv->phy_addr, MII_ADVERTISE); + lpa = emac_mii_read(priv, priv->phy_addr, MII_LPA); + media = mii_nway_result(lpa & adv); + speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) + ? 1 : 0); + duplex = (media & ADVERTISE_FULL) ? 1 : 0; + rt_kprintf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n", + dev->parent.name, + speed ? "100" : "10", + duplex ? "full" : "half", + lpa); + priv->speed = speed; + priv->duplex = duplex; + priv->link = 1; + eth_device_linkchange(&priv->parent, RT_TRUE); - return 1; - } + return 1; + } } /** @@ -272,94 +258,94 @@ static int davinci_emac_phy_init(rt_device_t dev) */ static void emac_update_phystatus(struct emac_priv *priv) { - rt_uint32_t mac_control; - rt_uint32_t new_duplex; - rt_uint32_t cur_duplex; + rt_uint32_t mac_control; + rt_uint32_t new_duplex; + rt_uint32_t cur_duplex; - mac_control = emac_read(EMAC_MACCONTROL); - cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ? - DUPLEX_FULL : DUPLEX_HALF; - if (priv->phy_mask) - new_duplex = priv->duplex; - else - new_duplex = DUPLEX_FULL; + mac_control = emac_read(EMAC_MACCONTROL); + cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ? + DUPLEX_FULL : DUPLEX_HALF; + if (priv->phy_mask) + new_duplex = priv->duplex; + else + new_duplex = DUPLEX_FULL; - /* We get called only if link has changed (speed/duplex/status) */ - if ((priv->link) && (new_duplex != cur_duplex)) { - priv->duplex = new_duplex; - if (DUPLEX_FULL == priv->duplex) - mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN); - else - mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN); - } + /* We get called only if link has changed (speed/duplex/status) */ + if ((priv->link) && (new_duplex != cur_duplex)) { + priv->duplex = new_duplex; + if (DUPLEX_FULL == priv->duplex) + mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN); + else + mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN); + } - if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) { - mac_control = emac_read(EMAC_MACCONTROL); - mac_control |= (EMAC_DM646X_MACCONTORL_GIG | - EMAC_DM646X_MACCONTORL_GIGFORCE); - } else { - /* Clear the GIG bit and GIGFORCE bit */ - mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE | - EMAC_DM646X_MACCONTORL_GIG); + if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) { + mac_control = emac_read(EMAC_MACCONTROL); + mac_control |= (EMAC_DM646X_MACCONTORL_GIG | + EMAC_DM646X_MACCONTORL_GIGFORCE); + } else { + /* Clear the GIG bit and GIGFORCE bit */ + mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE | + EMAC_DM646X_MACCONTORL_GIG); - if (priv->rmii_en && (priv->speed == SPEED_100)) - mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK; - else - mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK; - } + if (priv->rmii_en && (priv->speed == SPEED_100)) + mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK; + else + mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK; + } - /* Update mac_control if changed */ - emac_write(EMAC_MACCONTROL, mac_control); + /* Update mac_control if changed */ + emac_write(EMAC_MACCONTROL, mac_control); #if 0 - if (priv->link) { - /* link ON */ - /* reactivate the transmit queue if it is stopped */ - } else { - /* link OFF */ - } + if (priv->link) { + /* link ON */ + /* reactivate the transmit queue if it is stopped */ + } else { + /* link OFF */ + } #endif } void davinci_emac_update_link(void *param) { - struct emac_priv *priv = param; - rt_device_t dev = &(priv->parent.parent); - rt_uint32_t status, status_change = 0; - rt_uint32_t link; - rt_uint32_t media; - rt_uint16_t adv, lpa; + struct emac_priv *priv = param; + rt_device_t dev = &(priv->parent.parent); + rt_uint32_t status, status_change = 0; + rt_uint32_t link; + rt_uint32_t media; + rt_uint16_t adv, lpa; - status = emac_mii_read(priv, priv->phy_addr, MII_BMSR); - if ((status & BMSR_LSTATUS) == 0) - link = 0; - else - link = 1; + status = emac_mii_read(priv, priv->phy_addr, MII_BMSR); + if ((status & BMSR_LSTATUS) == 0) + link = 0; + else + link = 1; - if (link != priv->link) { - priv->link = link; - status_change = 1; - } + if (link != priv->link) { + priv->link = link; + status_change = 1; + } - if (status_change) { - if (priv->link) { - adv = emac_mii_read(priv, priv->phy_addr, MII_ADVERTISE); - lpa = emac_mii_read(priv, priv->phy_addr, MII_LPA); - media = mii_nway_result(lpa & adv); - priv->speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) - ? 100 : 10); - priv->duplex = (media & ADVERTISE_FULL) ? 1 : 0; - rt_kprintf("%s: link up (%dMbps/%s-duplex)\n", - dev->parent.name, priv->speed, - DUPLEX_FULL == priv->duplex ? "Full":"Half"); - eth_device_linkchange(&priv->parent, RT_TRUE); - } else { - rt_kprintf("%s: link down\n", dev->parent.name); - eth_device_linkchange(&priv->parent, RT_FALSE); - } - emac_update_phystatus(priv); + if (status_change) { + if (priv->link) { + adv = emac_mii_read(priv, priv->phy_addr, MII_ADVERTISE); + lpa = emac_mii_read(priv, priv->phy_addr, MII_LPA); + media = mii_nway_result(lpa & adv); + priv->speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) + ? 100 : 10); + priv->duplex = (media & ADVERTISE_FULL) ? 1 : 0; + rt_kprintf("%s: link up (%dMbps/%s-duplex)\n", + dev->parent.name, priv->speed, + DUPLEX_FULL == priv->duplex ? "Full":"Half"); + eth_device_linkchange(&priv->parent, RT_TRUE); + } else { + rt_kprintf("%s: link down\n", dev->parent.name); + eth_device_linkchange(&priv->parent, RT_FALSE); + } + emac_update_phystatus(priv); - } + } } @@ -375,21 +361,21 @@ void davinci_emac_update_link(void *param) * */ static int emac_net_tx_complete(struct emac_priv *priv, - void **net_data_tokens, - int num_tokens, rt_uint32_t ch) + void **net_data_tokens, + int num_tokens, rt_uint32_t ch) { - rt_uint32_t cnt; + rt_uint32_t cnt; - for (cnt = 0; cnt < num_tokens; cnt++) { - struct pbuf *p = (struct pbuf *)net_data_tokens[cnt]; - if (p == RT_NULL) - continue; - priv->net_dev_stats.tx_packets++; - priv->net_dev_stats.tx_bytes += p->len; - //free pbuf - } + for (cnt = 0; cnt < num_tokens; cnt++) { + struct pbuf *p = (struct pbuf *)net_data_tokens[cnt]; + if (p == RT_NULL) + continue; + priv->net_dev_stats.tx_packets++; + priv->net_dev_stats.tx_bytes += p->len; + //free pbuf + } - return 0; + return 0; } /** @@ -402,36 +388,36 @@ static int emac_net_tx_complete(struct emac_priv *priv, */ static void emac_txch_teardown(struct emac_priv *priv, rt_uint32_t ch) { - rt_uint32_t teardown_cnt = 0xFFFFFFF0; /* Some high value */ - struct emac_txch *txch = priv->txch[ch]; - struct emac_tx_bd __iomem *curr_bd; + rt_uint32_t teardown_cnt = 0xFFFFFFF0; /* Some high value */ + struct emac_txch *txch = priv->txch[ch]; + struct emac_tx_bd __iomem *curr_bd; - while ((emac_read(EMAC_TXCP(ch)) & EMAC_TEARDOWN_VALUE) != - EMAC_TEARDOWN_VALUE) { - /* wait till tx teardown complete */ - --teardown_cnt; - if (0 == teardown_cnt) { - rt_kprintf("EMAC: TX teardown aborted\n"); - break; - } - } - emac_write(EMAC_TXCP(ch), EMAC_TEARDOWN_VALUE); + while ((emac_read(EMAC_TXCP(ch)) & EMAC_TEARDOWN_VALUE) != + EMAC_TEARDOWN_VALUE) { + /* wait till tx teardown complete */ + --teardown_cnt; + if (0 == teardown_cnt) { + rt_kprintf("EMAC: TX teardown aborted\n"); + break; + } + } + emac_write(EMAC_TXCP(ch), EMAC_TEARDOWN_VALUE); - /* process sent packets and return pbuf's to upper layer */ - if (1 == txch->queue_active) { - curr_bd = txch->active_queue_head; - while (curr_bd != RT_NULL) { - emac_net_tx_complete(priv, (void *) - &curr_bd->buf_token, 1, ch); - if (curr_bd != txch->active_queue_tail) - curr_bd = curr_bd->next; - else - break; - } - txch->bd_pool_head = txch->active_queue_head; - txch->active_queue_head = - txch->active_queue_tail = RT_NULL; - } + /* process sent packets and return pbuf's to upper layer */ + if (1 == txch->queue_active) { + curr_bd = txch->active_queue_head; + while (curr_bd != RT_NULL) { + emac_net_tx_complete(priv, (void *) + &curr_bd->buf_token, 1, ch); + if (curr_bd != txch->active_queue_tail) + curr_bd = curr_bd->next; + else + break; + } + txch->bd_pool_head = txch->active_queue_head; + txch->active_queue_head = + txch->active_queue_tail = RT_NULL; + } } @@ -445,15 +431,15 @@ static void emac_txch_teardown(struct emac_priv *priv, rt_uint32_t ch) */ static void emac_stop_txch(struct emac_priv *priv, rt_uint32_t ch) { - struct emac_txch *txch = priv->txch[ch]; + struct emac_txch *txch = priv->txch[ch]; - if (txch) { - txch->teardown_pending = 1; - emac_write(EMAC_TXTEARDOWN, 0); - emac_txch_teardown(priv, ch); - txch->teardown_pending = 0; - emac_write(EMAC_TXINTMASKCLEAR, BIT(ch)); - } + if (txch) { + txch->teardown_pending = 1; + emac_write(EMAC_TXTEARDOWN, 0); + emac_txch_teardown(priv, ch); + txch->teardown_pending = 0; + emac_write(EMAC_TXINTMASKCLEAR, BIT(ch)); + } } @@ -474,65 +460,65 @@ static void emac_stop_txch(struct emac_priv *priv, rt_uint32_t ch) */ static int emac_tx_bdproc(struct emac_priv *priv, rt_uint32_t ch, rt_uint32_t budget) { - unsigned long flags; - rt_uint32_t frame_status; - rt_uint32_t pkts_processed = 0; - rt_uint32_t tx_complete_cnt = 0; - struct emac_tx_bd __iomem *curr_bd; - struct emac_txch *txch = priv->txch[ch]; - rt_uint32_t *tx_complete_ptr = txch->tx_complete; + unsigned long flags; + rt_uint32_t frame_status; + rt_uint32_t pkts_processed = 0; + rt_uint32_t tx_complete_cnt = 0; + struct emac_tx_bd __iomem *curr_bd; + struct emac_txch *txch = priv->txch[ch]; + rt_uint32_t *tx_complete_ptr = txch->tx_complete; - if (1 == txch->teardown_pending) { - rt_kprintf("DaVinci EMAC:emac_tx_bdproc: "\ - "teardown pending\n"); - return 0; /* dont handle any pkt completions */ - } + if (1 == txch->teardown_pending) { + rt_kprintf("DaVinci EMAC:emac_tx_bdproc: "\ + "teardown pending\n"); + return 0; /* dont handle any pkt completions */ + } - ++txch->proc_count; - rt_sem_take(&priv->tx_lock, RT_WAITING_FOREVER); - curr_bd = txch->active_queue_head; - if (RT_NULL == curr_bd) { - emac_write(EMAC_TXCP(ch), - emac_virt_to_phys(txch->last_hw_bdprocessed)); - txch->no_active_pkts++; - rt_sem_release(&priv->tx_lock); - return 0; - } - BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); - frame_status = curr_bd->mode; - while ((curr_bd) && - ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) && - (pkts_processed < budget)) { - emac_write(EMAC_TXCP(ch), emac_virt_to_phys(curr_bd)); - txch->active_queue_head = curr_bd->next; - if (frame_status & EMAC_CPPI_EOQ_BIT) { - if (curr_bd->next) { /* misqueued packet */ - emac_write(EMAC_TXHDP(ch), curr_bd->h_next); - ++txch->mis_queued_packets; - } else { - txch->queue_active = 0; /* end of queue */ - } - } - *tx_complete_ptr = (rt_uint32_t) curr_bd->buf_token; - ++tx_complete_ptr; - ++tx_complete_cnt; - curr_bd->next = txch->bd_pool_head; - txch->bd_pool_head = curr_bd; - --txch->active_queue_count; - pkts_processed++; - txch->last_hw_bdprocessed = curr_bd; - curr_bd = txch->active_queue_head; - if (curr_bd) { - BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); - frame_status = curr_bd->mode; - } - } /* end of pkt processing loop */ + ++txch->proc_count; + rt_sem_take(&priv->tx_lock, RT_WAITING_FOREVER); + curr_bd = txch->active_queue_head; + if (RT_NULL == curr_bd) { + emac_write(EMAC_TXCP(ch), + emac_virt_to_phys(txch->last_hw_bdprocessed)); + txch->no_active_pkts++; + rt_sem_release(&priv->tx_lock); + return 0; + } + BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); + frame_status = curr_bd->mode; + while ((curr_bd) && + ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) && + (pkts_processed < budget)) { + emac_write(EMAC_TXCP(ch), emac_virt_to_phys(curr_bd)); + txch->active_queue_head = curr_bd->next; + if (frame_status & EMAC_CPPI_EOQ_BIT) { + if (curr_bd->next) { /* misqueued packet */ + emac_write(EMAC_TXHDP(ch), curr_bd->h_next); + ++txch->mis_queued_packets; + } else { + txch->queue_active = 0; /* end of queue */ + } + } + *tx_complete_ptr = (rt_uint32_t) curr_bd->buf_token; + ++tx_complete_ptr; + ++tx_complete_cnt; + curr_bd->next = txch->bd_pool_head; + txch->bd_pool_head = curr_bd; + --txch->active_queue_count; + pkts_processed++; + txch->last_hw_bdprocessed = curr_bd; + curr_bd = txch->active_queue_head; + if (curr_bd) { + BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); + frame_status = curr_bd->mode; + } + } /* end of pkt processing loop */ - emac_net_tx_complete(priv, - (void *)&txch->tx_complete[0], - tx_complete_cnt, ch); - rt_sem_release(&priv->tx_lock); - return pkts_processed; + emac_net_tx_complete(priv, + (void *)&txch->tx_complete[0], + tx_complete_cnt, ch); + rt_sem_release(&priv->tx_lock); + return pkts_processed; } @@ -550,81 +536,81 @@ static int emac_tx_bdproc(struct emac_priv *priv, rt_uint32_t ch, rt_uint32_t bu */ static int emac_send(struct emac_priv *priv, struct emac_netpktobj *pkt, rt_uint32_t ch) { - unsigned long flags; - struct emac_tx_bd __iomem *curr_bd; - struct emac_txch *txch; - struct emac_netbufobj *buf_list; - rt_uint32_t num_pkts = 0; - int retry = 0; + unsigned long flags; + struct emac_tx_bd __iomem *curr_bd; + struct emac_txch *txch; + struct emac_netbufobj *buf_list; + rt_uint32_t num_pkts = 0; + int retry = 0; - txch = priv->txch[ch]; - buf_list = pkt->buf_list; /* get handle to the buffer array */ + txch = priv->txch[ch]; + buf_list = pkt->buf_list; /* get handle to the buffer array */ - /* check packet size and pad if short */ - if (pkt->pkt_length < EMAC_DEF_MIN_ETHPKTSIZE) { - buf_list->length += (EMAC_DEF_MIN_ETHPKTSIZE - pkt->pkt_length); - pkt->pkt_length = EMAC_DEF_MIN_ETHPKTSIZE; - } + /* check packet size and pad if short */ + if (pkt->pkt_length < EMAC_DEF_MIN_ETHPKTSIZE) { + buf_list->length += (EMAC_DEF_MIN_ETHPKTSIZE - pkt->pkt_length); + pkt->pkt_length = EMAC_DEF_MIN_ETHPKTSIZE; + } try: - rt_sem_take(&priv->tx_lock, RT_WAITING_FOREVER); - curr_bd = txch->bd_pool_head; - if (curr_bd == RT_NULL) { - txch->out_of_tx_bd++; - rt_sem_release(&priv->tx_lock); - num_pkts = emac_tx_bdproc(priv, EMAC_DEF_TX_CH, - EMAC_DEF_TX_MAX_SERVICE); - if (!num_pkts) { - retry++; - if (retry > 5) - return EMAC_ERR_TX_OUT_OF_BD; - rt_thread_delay(1); - } - goto try; - } + rt_sem_take(&priv->tx_lock, RT_WAITING_FOREVER); + curr_bd = txch->bd_pool_head; + if (curr_bd == RT_NULL) { + txch->out_of_tx_bd++; + rt_sem_release(&priv->tx_lock); + num_pkts = emac_tx_bdproc(priv, EMAC_DEF_TX_CH, + EMAC_DEF_TX_MAX_SERVICE); + if (!num_pkts) { + retry++; + if (retry > 5) + return EMAC_ERR_TX_OUT_OF_BD; + rt_thread_delay(1); + } + goto try; + } - txch->bd_pool_head = curr_bd->next; - curr_bd->buf_token = buf_list->buf_token; - curr_bd->buff_ptr = virt_to_phys(buf_list->data_ptr); - curr_bd->off_b_len = buf_list->length; - curr_bd->h_next = 0; - curr_bd->next = RT_NULL; - curr_bd->mode = (EMAC_CPPI_SOP_BIT | EMAC_CPPI_OWNERSHIP_BIT | - EMAC_CPPI_EOP_BIT | pkt->pkt_length); + txch->bd_pool_head = curr_bd->next; + curr_bd->buf_token = buf_list->buf_token; + curr_bd->buff_ptr = virt_to_phys(buf_list->data_ptr); + curr_bd->off_b_len = buf_list->length; + curr_bd->h_next = 0; + curr_bd->next = RT_NULL; + curr_bd->mode = (EMAC_CPPI_SOP_BIT | EMAC_CPPI_OWNERSHIP_BIT | + EMAC_CPPI_EOP_BIT | pkt->pkt_length); - /* flush the packet from cache if write back cache is present */ - BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); + /* flush the packet from cache if write back cache is present */ + BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); - /* send the packet */ - if (txch->active_queue_head == RT_NULL) { - txch->active_queue_head = curr_bd; - txch->active_queue_tail = curr_bd; - if (1 != txch->queue_active) { - emac_write(EMAC_TXHDP(ch), - emac_virt_to_phys(curr_bd)); - txch->queue_active = 1; - } - ++txch->queue_reinit; - } else { - register struct emac_tx_bd __iomem *tail_bd; - register rt_uint32_t frame_status; + /* send the packet */ + if (txch->active_queue_head == RT_NULL) { + txch->active_queue_head = curr_bd; + txch->active_queue_tail = curr_bd; + if (1 != txch->queue_active) { + emac_write(EMAC_TXHDP(ch), + emac_virt_to_phys(curr_bd)); + txch->queue_active = 1; + } + ++txch->queue_reinit; + } else { + register struct emac_tx_bd __iomem *tail_bd; + register rt_uint32_t frame_status; - tail_bd = txch->active_queue_tail; - tail_bd->next = curr_bd; - txch->active_queue_tail = curr_bd; - tail_bd = EMAC_VIRT_NOCACHE(tail_bd); - tail_bd->h_next = (int)emac_virt_to_phys(curr_bd); - frame_status = tail_bd->mode; - if (frame_status & EMAC_CPPI_EOQ_BIT) { - emac_write(EMAC_TXHDP(ch), emac_virt_to_phys(curr_bd)); - frame_status &= ~(EMAC_CPPI_EOQ_BIT); - tail_bd->mode = frame_status; - ++txch->end_of_queue_add; - } - } - txch->active_queue_count++; - rt_sem_release(&priv->tx_lock); - return 0; + tail_bd = txch->active_queue_tail; + tail_bd->next = curr_bd; + txch->active_queue_tail = curr_bd; + tail_bd = EMAC_VIRT_NOCACHE(tail_bd); + tail_bd->h_next = (int)emac_virt_to_phys(curr_bd); + frame_status = tail_bd->mode; + if (frame_status & EMAC_CPPI_EOQ_BIT) { + emac_write(EMAC_TXHDP(ch), emac_virt_to_phys(curr_bd)); + frame_status &= ~(EMAC_CPPI_EOQ_BIT); + tail_bd->mode = frame_status; + ++txch->end_of_queue_add; + } + } + txch->active_queue_count++; + rt_sem_release(&priv->tx_lock); + return 0; } /** @@ -639,40 +625,40 @@ try: */ static int emac_dev_xmit(struct pbuf *p, struct emac_priv *priv) { - int ret_code; - struct emac_netbufobj tx_buf; /* buffer obj-only single frame support */ - struct emac_netpktobj tx_packet; /* packet object */ + int ret_code; + struct emac_netbufobj tx_buf; /* buffer obj-only single frame support */ + struct emac_netpktobj tx_packet; /* packet object */ - /* If no link, return */ - if (!priv->link) { - rt_kprintf("DaVinci EMAC: No link to transmit\n"); - return -RT_EBUSY; - } + /* If no link, return */ + if (!priv->link) { + rt_kprintf("DaVinci EMAC: No link to transmit\n"); + return -RT_EBUSY; + } - /* Build the buffer and packet objects - Since only single fragment is - * supported, need not set length and token in both packet & object. - * Doing so for completeness sake & to show that this needs to be done - * in multifragment case - */ - tx_packet.buf_list = &tx_buf; - tx_packet.num_bufs = 1; /* only single fragment supported */ - tx_packet.pkt_length = p->len; - tx_packet.pkt_token = (void *)p; - tx_buf.length = p->len; - tx_buf.buf_token = (void *)p; - tx_buf.data_ptr = p->payload; - EMAC_CACHE_WRITEBACK((unsigned long)p->payload, p->len); - ret_code = emac_send(priv, &tx_packet, EMAC_DEF_TX_CH); - if (ret_code != 0) { - if (ret_code == EMAC_ERR_TX_OUT_OF_BD) { - rt_kprintf("DaVinci EMAC: xmit() fatal"\ - " err. Out of TX BD's\n"); - } - priv->net_dev_stats.tx_dropped++; - return -RT_EBUSY; - } + /* Build the buffer and packet objects - Since only single fragment is + * supported, need not set length and token in both packet & object. + * Doing so for completeness sake & to show that this needs to be done + * in multifragment case + */ + tx_packet.buf_list = &tx_buf; + tx_packet.num_bufs = 1; /* only single fragment supported */ + tx_packet.pkt_length = p->len; + tx_packet.pkt_token = (void *)p; + tx_buf.length = p->len; + tx_buf.buf_token = (void *)p; + tx_buf.data_ptr = p->payload; + EMAC_CACHE_WRITEBACK((unsigned long)p->payload, p->len); + ret_code = emac_send(priv, &tx_packet, EMAC_DEF_TX_CH); + if (ret_code != 0) { + if (ret_code == EMAC_ERR_TX_OUT_OF_BD) { + rt_kprintf("DaVinci EMAC: xmit() fatal"\ + " err. Out of TX BD's\n"); + } + priv->net_dev_stats.tx_dropped++; + return -RT_EBUSY; + } - return RT_EOK; + return RT_EOK; } /** @@ -685,15 +671,15 @@ static int emac_dev_xmit(struct pbuf *p, struct emac_priv *priv) */ static void emac_cleanup_txch(struct emac_priv *priv, rt_uint32_t ch) { - struct emac_txch *txch = priv->txch[ch]; + struct emac_txch *txch = priv->txch[ch]; - if (txch) { - if (txch->bd_mem) - txch->bd_mem = NULL; - rt_free(txch->tx_complete); - rt_free(txch); - priv->txch[ch] = NULL; - } + if (txch) { + if (txch->bd_mem) + txch->bd_mem = NULL; + rt_free(txch->tx_complete); + rt_free(txch); + priv->txch[ch] = NULL; + } } @@ -709,15 +695,15 @@ static void emac_cleanup_txch(struct emac_priv *priv, rt_uint32_t ch) */ static void emac_dev_tx_timeout(struct emac_priv *priv) { - rt_kprintf("emac tx timeout.\n"); - priv->net_dev_stats.tx_errors++; - emac_int_disable(priv); - emac_stop_txch(priv, EMAC_DEF_TX_CH); - emac_cleanup_txch(priv, EMAC_DEF_TX_CH); - emac_init_txch(priv, EMAC_DEF_TX_CH); - emac_write(EMAC_TXHDP(0), 0); - emac_write(EMAC_TXINTMASKSET, BIT(EMAC_DEF_TX_CH)); - emac_int_enable(priv); + rt_kprintf("emac tx timeout.\n"); + priv->net_dev_stats.tx_errors++; + emac_int_disable(priv); + emac_stop_txch(priv, EMAC_DEF_TX_CH); + emac_cleanup_txch(priv, EMAC_DEF_TX_CH); + emac_init_txch(priv, EMAC_DEF_TX_CH); + emac_write(EMAC_TXHDP(0), 0); + emac_write(EMAC_TXINTMASKSET, BIT(EMAC_DEF_TX_CH)); + emac_int_enable(priv); } @@ -725,16 +711,16 @@ static void emac_dev_tx_timeout(struct emac_priv *priv) /* transmit packet. */ rt_err_t rt_davinci_emac_tx( rt_device_t dev, struct pbuf* p) { - rt_err_t err; - struct emac_priv *priv = dev->user_data; + rt_err_t err; + struct emac_priv *priv = dev->user_data; - err = emac_dev_xmit(p, priv); - if (err != RT_EOK) - { - emac_dev_tx_timeout(priv); - } + err = emac_dev_xmit(p, priv); + if (err != RT_EOK) + { + emac_dev_tx_timeout(priv); + } - return RT_EOK; + return RT_EOK; } /** @@ -751,49 +737,49 @@ rt_err_t rt_davinci_emac_tx( rt_device_t dev, struct pbuf* p) * */ static void emac_addbd_to_rx_queue(struct emac_priv *priv, rt_uint32_t ch, - struct emac_rx_bd __iomem *curr_bd, - char *buffer, void *buf_token) + struct emac_rx_bd __iomem *curr_bd, + char *buffer, void *buf_token) { - struct emac_rxch *rxch = priv->rxch[ch]; + struct emac_rxch *rxch = priv->rxch[ch]; - /* populate the hardware descriptor */ - curr_bd->h_next = 0; - curr_bd->buff_ptr = virt_to_phys(buffer); - curr_bd->off_b_len = rxch->buf_size; - curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT; - curr_bd->next = RT_NULL; - curr_bd->data_ptr = buffer; - curr_bd->buf_token = buf_token; + /* populate the hardware descriptor */ + curr_bd->h_next = 0; + curr_bd->buff_ptr = virt_to_phys(buffer); + curr_bd->off_b_len = rxch->buf_size; + curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT; + curr_bd->next = RT_NULL; + curr_bd->data_ptr = buffer; + curr_bd->buf_token = buf_token; - /* write back */ - BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); - if (rxch->active_queue_head == RT_NULL) { - rxch->active_queue_head = curr_bd; - rxch->active_queue_tail = curr_bd; - if (0 != rxch->queue_active) { - emac_write(EMAC_RXHDP(ch), - emac_virt_to_phys(rxch->active_queue_head)); - rxch->queue_active = 1; - } - } else { - struct emac_rx_bd __iomem *tail_bd; - rt_uint32_t frame_status; + /* write back */ + BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); + if (rxch->active_queue_head == RT_NULL) { + rxch->active_queue_head = curr_bd; + rxch->active_queue_tail = curr_bd; + if (0 != rxch->queue_active) { + emac_write(EMAC_RXHDP(ch), + emac_virt_to_phys(rxch->active_queue_head)); + rxch->queue_active = 1; + } + } else { + struct emac_rx_bd __iomem *tail_bd; + rt_uint32_t frame_status; - tail_bd = rxch->active_queue_tail; - rxch->active_queue_tail = curr_bd; - tail_bd->next = curr_bd; - tail_bd = EMAC_VIRT_NOCACHE(tail_bd); - tail_bd->h_next = emac_virt_to_phys(curr_bd); - frame_status = tail_bd->mode; - if (frame_status & EMAC_CPPI_EOQ_BIT) { - emac_write(EMAC_RXHDP(ch), - emac_virt_to_phys(curr_bd)); - frame_status &= ~(EMAC_CPPI_EOQ_BIT); - tail_bd->mode = frame_status; - ++rxch->end_of_queue_add; - } - } - ++rxch->recycled_bd; + tail_bd = rxch->active_queue_tail; + rxch->active_queue_tail = curr_bd; + tail_bd->next = curr_bd; + tail_bd = EMAC_VIRT_NOCACHE(tail_bd); + tail_bd->h_next = emac_virt_to_phys(curr_bd); + frame_status = tail_bd->mode; + if (frame_status & EMAC_CPPI_EOQ_BIT) { + emac_write(EMAC_RXHDP(ch), + emac_virt_to_phys(curr_bd)); + frame_status &= ~(EMAC_CPPI_EOQ_BIT); + tail_bd->mode = frame_status; + ++rxch->end_of_queue_add; + } + } + ++rxch->recycled_bd; } /** @@ -807,22 +793,22 @@ static void emac_addbd_to_rx_queue(struct emac_priv *priv, rt_uint32_t ch, * Returns success or appropriate error code (none as of now) */ static int emac_net_rx_cb(struct emac_priv *priv, - struct emac_netpktobj *net_pkt_list) + struct emac_netpktobj *net_pkt_list) { - struct eth_device *device = &priv->parent; - struct pbuf *p; - p = (struct pbuf *)net_pkt_list->pkt_token; - /* set length of packet */ - p->tot_len = net_pkt_list->pkt_length; - p->len = net_pkt_list->pkt_length; - EMAC_CACHE_INVALIDATE((unsigned long)p->payload, p->len); - if (device->netif->input(p, device->netif) != RT_EOK) - { - pbuf_free(p); - } - priv->net_dev_stats.rx_bytes += net_pkt_list->pkt_length; - priv->net_dev_stats.rx_packets++; - return 0; + struct eth_device *device = &priv->parent; + struct pbuf *p; + p = (struct pbuf *)net_pkt_list->pkt_token; + /* set length of packet */ + p->tot_len = net_pkt_list->pkt_length; + p->len = net_pkt_list->pkt_length; + EMAC_CACHE_INVALIDATE((unsigned long)p->payload, p->len); + if (device->netif->input(p, device->netif) != RT_EOK) + { + pbuf_free(p); + } + priv->net_dev_stats.rx_bytes += net_pkt_list->pkt_length; + priv->net_dev_stats.rx_packets++; + return 0; } /** @@ -838,20 +824,20 @@ static int emac_net_rx_cb(struct emac_priv *priv, * Returns pbuf data pointer or 0 on failure to alloc pbuf */ static void *emac_net_alloc_rx_buf(struct emac_priv *priv, int buf_size, - void **data_token, rt_uint32_t ch) + void **data_token, rt_uint32_t ch) { - struct pbuf* p; + struct pbuf* p; - p = pbuf_alloc(PBUF_LINK, buf_size, PBUF_RAM); - if (RT_NULL == p) { - rt_kprintf("DaVinci EMAC: failed to alloc pbuf\n"); - return RT_NULL; - } + p = pbuf_alloc(PBUF_LINK, buf_size, PBUF_RAM); + if (RT_NULL == p) { + rt_kprintf("DaVinci EMAC: failed to alloc pbuf\n"); + return RT_NULL; + } - /* set device pointer in p and reserve space for extra bytes */ - *data_token = (void *) p; - EMAC_CACHE_WRITEBACK_INVALIDATE((unsigned long)p->payload, buf_size); - return p->payload; + /* set device pointer in p and reserve space for extra bytes */ + *data_token = (void *) p; + EMAC_CACHE_WRITEBACK_INVALIDATE((unsigned long)p->payload, buf_size); + return p->payload; } @@ -871,160 +857,160 @@ static void *emac_net_alloc_rx_buf(struct emac_priv *priv, int buf_size, */ static int emac_rx_bdproc(struct emac_priv *priv, rt_uint32_t ch, rt_uint32_t budget) { - unsigned long flags; - rt_uint32_t frame_status; - rt_uint32_t pkts_processed = 0; - char *new_buffer; - struct emac_rx_bd __iomem *curr_bd; - struct emac_rx_bd __iomem *last_bd; - struct emac_netpktobj *curr_pkt, pkt_obj; - struct emac_netbufobj buf_obj; - struct emac_netbufobj *rx_buf_obj; - void *new_buf_token; - struct emac_rxch *rxch = priv->rxch[ch]; + unsigned long flags; + rt_uint32_t frame_status; + rt_uint32_t pkts_processed = 0; + char *new_buffer; + struct emac_rx_bd __iomem *curr_bd; + struct emac_rx_bd __iomem *last_bd; + struct emac_netpktobj *curr_pkt, pkt_obj; + struct emac_netbufobj buf_obj; + struct emac_netbufobj *rx_buf_obj; + void *new_buf_token; + struct emac_rxch *rxch = priv->rxch[ch]; - if (1 == rxch->teardown_pending) - return 0; - ++rxch->proc_count; - rt_sem_take(&priv->rx_lock, RT_WAITING_FOREVER); - pkt_obj.buf_list = &buf_obj; - curr_pkt = &pkt_obj; - curr_bd = rxch->active_queue_head; - BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); - frame_status = curr_bd->mode; + if (1 == rxch->teardown_pending) + return 0; + ++rxch->proc_count; + rt_sem_take(&priv->rx_lock, RT_WAITING_FOREVER); + pkt_obj.buf_list = &buf_obj; + curr_pkt = &pkt_obj; + curr_bd = rxch->active_queue_head; + BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); + frame_status = curr_bd->mode; - while ((curr_bd) && - ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) && - (pkts_processed < budget)) { + while ((curr_bd) && + ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) && + (pkts_processed < budget)) { - new_buffer = emac_net_alloc_rx_buf(priv, rxch->buf_size, - &new_buf_token, EMAC_DEF_RX_CH); - if (RT_NULL == new_buffer) { - ++rxch->out_of_rx_buffers; - goto end_emac_rx_bdproc; - } + new_buffer = emac_net_alloc_rx_buf(priv, rxch->buf_size, + &new_buf_token, EMAC_DEF_RX_CH); + if (RT_NULL == new_buffer) { + ++rxch->out_of_rx_buffers; + goto end_emac_rx_bdproc; + } - /* populate received packet data structure */ - rx_buf_obj = &curr_pkt->buf_list[0]; - rx_buf_obj->data_ptr = (char *)curr_bd->data_ptr; - rx_buf_obj->length = curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE; - rx_buf_obj->buf_token = curr_bd->buf_token; - curr_pkt->pkt_token = curr_pkt->buf_list->buf_token; - curr_pkt->num_bufs = 1; - curr_pkt->pkt_length = - (frame_status & EMAC_RX_BD_PKT_LENGTH_MASK); - emac_write(EMAC_RXCP(ch), emac_virt_to_phys(curr_bd)); - ++rxch->processed_bd; - last_bd = curr_bd; - curr_bd = last_bd->next; - rxch->active_queue_head = curr_bd; + /* populate received packet data structure */ + rx_buf_obj = &curr_pkt->buf_list[0]; + rx_buf_obj->data_ptr = (char *)curr_bd->data_ptr; + rx_buf_obj->length = curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE; + rx_buf_obj->buf_token = curr_bd->buf_token; + curr_pkt->pkt_token = curr_pkt->buf_list->buf_token; + curr_pkt->num_bufs = 1; + curr_pkt->pkt_length = + (frame_status & EMAC_RX_BD_PKT_LENGTH_MASK); + emac_write(EMAC_RXCP(ch), emac_virt_to_phys(curr_bd)); + ++rxch->processed_bd; + last_bd = curr_bd; + curr_bd = last_bd->next; + rxch->active_queue_head = curr_bd; - /* check if end of RX queue ? */ - if (frame_status & EMAC_CPPI_EOQ_BIT) { - if (curr_bd) { - ++rxch->mis_queued_packets; - emac_write(EMAC_RXHDP(ch), - emac_virt_to_phys(curr_bd)); - } else { - ++rxch->end_of_queue; - rxch->queue_active = 0; - } - } + /* check if end of RX queue ? */ + if (frame_status & EMAC_CPPI_EOQ_BIT) { + if (curr_bd) { + ++rxch->mis_queued_packets; + emac_write(EMAC_RXHDP(ch), + emac_virt_to_phys(curr_bd)); + } else { + ++rxch->end_of_queue; + rxch->queue_active = 0; + } + } - /* recycle BD */ - emac_addbd_to_rx_queue(priv, ch, last_bd, new_buffer, - new_buf_token); + /* recycle BD */ + emac_addbd_to_rx_queue(priv, ch, last_bd, new_buffer, + new_buf_token); - /* return the packet to the user - BD ptr passed in - * last parameter for potential *future* use */ - rt_sem_release(&priv->rx_lock); - emac_net_rx_cb(priv, curr_pkt);//??? - rt_sem_take(&priv->rx_lock, RT_WAITING_FOREVER); - curr_bd = rxch->active_queue_head; - if (curr_bd) { - BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); - frame_status = curr_bd->mode; - } - ++pkts_processed; - } + /* return the packet to the user - BD ptr passed in + * last parameter for potential *future* use */ + rt_sem_release(&priv->rx_lock); + emac_net_rx_cb(priv, curr_pkt);//??? + rt_sem_take(&priv->rx_lock, RT_WAITING_FOREVER); + curr_bd = rxch->active_queue_head; + if (curr_bd) { + BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); + frame_status = curr_bd->mode; + } + ++pkts_processed; + } end_emac_rx_bdproc: - rt_sem_release(&priv->rx_lock); - return pkts_processed; + rt_sem_release(&priv->rx_lock); + return pkts_processed; } /* reception packet. */ struct pbuf *rt_davinci_emac_rx(rt_device_t dev) { - struct emac_priv *priv = dev->user_data; - struct pbuf* p = RT_NULL; - rt_uint32_t len; - void *buffer; + struct emac_priv *priv = dev->user_data; + struct pbuf* p = RT_NULL; + rt_uint32_t len; + void *buffer; - struct pbuf* q; - rt_uint8_t *buf = RT_NULL; - unsigned int mask; - rt_uint32_t status = 0; - rt_uint32_t num_pkts = 0; + struct pbuf* q; + rt_uint8_t *buf = RT_NULL; + unsigned int mask; + rt_uint32_t status = 0; + rt_uint32_t num_pkts = 0; - /* Check interrupt vectors and call packet processing */ - status = emac_read(EMAC_MACINVECTOR); + /* Check interrupt vectors and call packet processing */ + status = emac_read(EMAC_MACINVECTOR); - mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC; + mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC; - if (priv->version == EMAC_VERSION_2) - mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC; + if (priv->version == EMAC_VERSION_2) + mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC; - if (status & mask) { - num_pkts = emac_tx_bdproc(priv, EMAC_DEF_TX_CH, - EMAC_DEF_TX_MAX_SERVICE); - } /* TX processing */ + if (status & mask) { + num_pkts = emac_tx_bdproc(priv, EMAC_DEF_TX_CH, + EMAC_DEF_TX_MAX_SERVICE); + } /* TX processing */ - /*if (num_pkts) - //return budget; - return RT_NULL;*/ + /*if (num_pkts) + //return budget; + return RT_NULL;*/ - mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC; + mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC; - if (priv->version == EMAC_VERSION_2) - mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC; + if (priv->version == EMAC_VERSION_2) + mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC; - if (status & mask) { - num_pkts = emac_rx_bdproc(priv, EMAC_DEF_RX_CH, EMAC_DEF_RX_MAX_SERVICE); - } /* RX processing */ + if (status & mask) { + num_pkts = emac_rx_bdproc(priv, EMAC_DEF_RX_CH, EMAC_DEF_RX_MAX_SERVICE); + } /* RX processing */ - /*if (num_pkts < EMAC_DEF_RX_MAX_SERVICE) { - emac_int_enable(priv); - }*/ + /*if (num_pkts < EMAC_DEF_RX_MAX_SERVICE) { + emac_int_enable(priv); + }*/ - mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT; - if (priv->version == EMAC_VERSION_2) - mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT; + mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT; + if (priv->version == EMAC_VERSION_2) + mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT; - if (status & mask) { - rt_uint32_t ch, cause; - rt_kprintf("DaVinci EMAC: Fatal Hardware Error\n"); + if (status & mask) { + rt_uint32_t ch, cause; + rt_kprintf("DaVinci EMAC: Fatal Hardware Error\n"); - status = emac_read(EMAC_MACSTATUS); - cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >> - EMAC_MACSTATUS_TXERRCODE_SHIFT); - if (cause) { - ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >> - EMAC_MACSTATUS_TXERRCH_SHIFT); - } - cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >> - EMAC_MACSTATUS_RXERRCODE_SHIFT); - if (cause) { - ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >> - EMAC_MACSTATUS_RXERRCH_SHIFT); - } - } /* Host error processing */ + status = emac_read(EMAC_MACSTATUS); + cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >> + EMAC_MACSTATUS_TXERRCODE_SHIFT); + if (cause) { + ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >> + EMAC_MACSTATUS_TXERRCH_SHIFT); + } + cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >> + EMAC_MACSTATUS_RXERRCODE_SHIFT); + if (cause) { + ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >> + EMAC_MACSTATUS_RXERRCH_SHIFT); + } + } /* Host error processing */ - //return num_pkts; - //return p; - emac_int_enable(priv); - return RT_NULL; + //return num_pkts; + //return p; + emac_int_enable(priv); + return RT_NULL; } @@ -1040,19 +1026,19 @@ struct pbuf *rt_davinci_emac_rx(rt_device_t dev) */ static void emac_set_type0addr(struct emac_priv *priv, rt_uint32_t ch, char *mac_addr) { - rt_uint32_t val; - val = ((mac_addr[5] << 8) | (mac_addr[4])); - emac_write(EMAC_MACSRCADDRLO, val); + rt_uint32_t val; + val = ((mac_addr[5] << 8) | (mac_addr[4])); + emac_write(EMAC_MACSRCADDRLO, val); - val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ - (mac_addr[1] << 8) | (mac_addr[0])); - emac_write(EMAC_MACSRCADDRHI, val); - val = emac_read(EMAC_RXUNICASTSET); - val |= BIT(ch); - emac_write(EMAC_RXUNICASTSET, val); - val = emac_read(EMAC_RXUNICASTCLEAR); - val &= ~BIT(ch); - emac_write(EMAC_RXUNICASTCLEAR, val); + val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ + (mac_addr[1] << 8) | (mac_addr[0])); + emac_write(EMAC_MACSRCADDRHI, val); + val = emac_read(EMAC_RXUNICASTSET); + val |= BIT(ch); + emac_write(EMAC_RXUNICASTSET, val); + val = emac_read(EMAC_RXUNICASTCLEAR); + val &= ~BIT(ch); + emac_write(EMAC_RXUNICASTCLEAR, val); } /** @@ -1067,14 +1053,14 @@ static void emac_set_type0addr(struct emac_priv *priv, rt_uint32_t ch, char *mac */ static void emac_set_type1addr(struct emac_priv *priv, rt_uint32_t ch, char *mac_addr) { - rt_uint32_t val; - emac_write(EMAC_MACINDEX, ch); - val = ((mac_addr[5] << 8) | mac_addr[4]); - emac_write(EMAC_MACADDRLO, val); - val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ - (mac_addr[1] << 8) | (mac_addr[0])); - emac_write(EMAC_MACADDRHI, val); - emac_set_type0addr(priv, ch, mac_addr); + rt_uint32_t val; + emac_write(EMAC_MACINDEX, ch); + val = ((mac_addr[5] << 8) | mac_addr[4]); + emac_write(EMAC_MACADDRLO, val); + val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ + (mac_addr[1] << 8) | (mac_addr[0])); + emac_write(EMAC_MACADDRHI, val); + emac_set_type0addr(priv, ch, mac_addr); } /** @@ -1090,17 +1076,17 @@ static void emac_set_type1addr(struct emac_priv *priv, rt_uint32_t ch, char *mac * Returns success (0) or appropriate error code (none as of now) */ static void emac_set_type2addr(struct emac_priv *priv, rt_uint32_t ch, - char *mac_addr, int index, int match) + char *mac_addr, int index, int match) { - rt_uint32_t val; - emac_write(EMAC_MACINDEX, index); - val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ - (mac_addr[1] << 8) | (mac_addr[0])); - emac_write(EMAC_MACADDRHI, val); - val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \ - (match << 19) | BIT(20)); - emac_write(EMAC_MACADDRLO, val); - emac_set_type0addr(priv, ch, mac_addr); + rt_uint32_t val; + emac_write(EMAC_MACINDEX, index); + val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ + (mac_addr[1] << 8) | (mac_addr[0])); + emac_write(EMAC_MACADDRHI, val); + val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \ + (match << 19) | BIT(20)); + emac_write(EMAC_MACADDRLO, val); + emac_set_type0addr(priv, ch, mac_addr); } /** @@ -1115,18 +1101,18 @@ static void emac_set_type2addr(struct emac_priv *priv, rt_uint32_t ch, */ static void emac_setmac(struct emac_priv *priv, rt_uint32_t ch, char *mac_addr) { - if (priv->rx_addr_type == 0) { - emac_set_type0addr(priv, ch, mac_addr); - } else if (priv->rx_addr_type == 1) { - rt_uint32_t cnt; - for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++) - emac_set_type1addr(priv, ch, mac_addr); - } else if (priv->rx_addr_type == 2) { - emac_set_type2addr(priv, ch, mac_addr, ch, 1); - emac_set_type0addr(priv, ch, mac_addr); - } else { - rt_kprintf("DaVinci EMAC: Wrong addressing\n"); - } + if (priv->rx_addr_type == 0) { + emac_set_type0addr(priv, ch, mac_addr); + } else if (priv->rx_addr_type == 1) { + rt_uint32_t cnt; + for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++) + emac_set_type1addr(priv, ch, mac_addr); + } else if (priv->rx_addr_type == 2) { + emac_set_type2addr(priv, ch, mac_addr, ch, 1); + emac_set_type0addr(priv, ch, mac_addr); + } else { + rt_kprintf("DaVinci EMAC: Wrong addressing\n"); + } } @@ -1139,9 +1125,9 @@ static void emac_setmac(struct emac_priv *priv, rt_uint32_t ch, char *mac_addr) * pointer to the memory * */ -#define EMAC_TX_BD_MEM(priv) ((priv)->emac_ctrl_ram) -#define EMAC_RX_BD_MEM(priv) ((priv)->emac_ctrl_ram + \ - (((priv)->ctrl_ram_size) >> 1)) +#define EMAC_TX_BD_MEM(priv) ((priv)->emac_ctrl_ram) +#define EMAC_RX_BD_MEM(priv) ((priv)->emac_ctrl_ram + \ + (((priv)->ctrl_ram_size) >> 1)) /** * emac_init_txch: TX channel initialization @@ -1155,59 +1141,59 @@ static void emac_setmac(struct emac_priv *priv, rt_uint32_t ch, char *mac_addr) */ static int emac_init_txch(struct emac_priv *priv, rt_uint32_t ch) { - rt_uint32_t cnt, bd_size; - void __iomem *mem; - struct emac_tx_bd __iomem *curr_bd; - struct emac_txch *txch = RT_NULL; + rt_uint32_t cnt, bd_size; + void __iomem *mem; + struct emac_tx_bd __iomem *curr_bd; + struct emac_txch *txch = RT_NULL; - txch = rt_malloc(sizeof(struct emac_txch)); - if (RT_NULL == txch) { - rt_kprintf("DaVinci EMAC: TX Ch mem alloc failed"); - return -RT_ENOMEM; - } - rt_memset(txch, 0, sizeof(struct emac_txch)); - priv->txch[ch] = txch; - txch->service_max = EMAC_DEF_TX_MAX_SERVICE; - txch->active_queue_head = RT_NULL; - txch->active_queue_tail = RT_NULL; - txch->queue_active = 0; - txch->teardown_pending = 0; + txch = rt_malloc(sizeof(struct emac_txch)); + if (RT_NULL == txch) { + rt_kprintf("DaVinci EMAC: TX Ch mem alloc failed"); + return -RT_ENOMEM; + } + rt_memset(txch, 0, sizeof(struct emac_txch)); + priv->txch[ch] = txch; + txch->service_max = EMAC_DEF_TX_MAX_SERVICE; + txch->active_queue_head = RT_NULL; + txch->active_queue_tail = RT_NULL; + txch->queue_active = 0; + txch->teardown_pending = 0; - /* allocate memory for TX CPPI channel on a 4 byte boundry */ - txch->tx_complete = rt_malloc(txch->service_max * sizeof(rt_uint32_t)); - if (RT_NULL == txch->tx_complete) { - rt_kprintf("DaVinci EMAC: Tx service mem alloc failed"); - rt_free(txch); - return -RT_ENOMEM; - } - memset(txch->tx_complete, 0, txch->service_max * sizeof(rt_uint32_t)); + /* allocate memory for TX CPPI channel on a 4 byte boundry */ + txch->tx_complete = rt_malloc(txch->service_max * sizeof(rt_uint32_t)); + if (RT_NULL == txch->tx_complete) { + rt_kprintf("DaVinci EMAC: Tx service mem alloc failed"); + rt_free(txch); + return -RT_ENOMEM; + } + memset(txch->tx_complete, 0, txch->service_max * sizeof(rt_uint32_t)); - /* allocate buffer descriptor pool align every BD on four word - * boundry for future requirements */ - bd_size = (sizeof(struct emac_tx_bd) + 0xF) & ~0xF; - txch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size; - txch->alloc_size = (((bd_size * txch->num_bd) + 0xF) & ~0xF); + /* allocate buffer descriptor pool align every BD on four word + * boundry for future requirements */ + bd_size = (sizeof(struct emac_tx_bd) + 0xF) & ~0xF; + txch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size; + txch->alloc_size = (((bd_size * txch->num_bd) + 0xF) & ~0xF); - /* alloc TX BD memory */ - txch->bd_mem = EMAC_TX_BD_MEM(priv); - rt_memset((void *)txch->bd_mem, 0, txch->alloc_size); + /* alloc TX BD memory */ + txch->bd_mem = EMAC_TX_BD_MEM(priv); + rt_memset((void *)txch->bd_mem, 0, txch->alloc_size); - /* initialize the BD linked list */ - mem = (void __iomem *) - (((rt_uint32_t) txch->bd_mem + 0xF) & ~0xF); - txch->bd_pool_head = RT_NULL; - for (cnt = 0; cnt < txch->num_bd; cnt++) { - curr_bd = mem + (cnt * bd_size); - curr_bd->next = txch->bd_pool_head; - txch->bd_pool_head = curr_bd; - } + /* initialize the BD linked list */ + mem = (void __iomem *) + (((rt_uint32_t) txch->bd_mem + 0xF) & ~0xF); + txch->bd_pool_head = RT_NULL; + for (cnt = 0; cnt < txch->num_bd; cnt++) { + curr_bd = mem + (cnt * bd_size); + curr_bd->next = txch->bd_pool_head; + txch->bd_pool_head = curr_bd; + } - /* reset statistics counters */ - txch->out_of_tx_bd = 0; - txch->no_active_pkts = 0; - txch->active_queue_count = 0; + /* reset statistics counters */ + txch->out_of_tx_bd = 0; + txch->no_active_pkts = 0; + txch->active_queue_count = 0; - return 0; + return 0; } /** @@ -1223,74 +1209,74 @@ static int emac_init_txch(struct emac_priv *priv, rt_uint32_t ch) */ static int emac_init_rxch(struct emac_priv *priv, rt_uint32_t ch, char *param) { - rt_uint32_t cnt, bd_size; - void __iomem *mem; - struct emac_rx_bd __iomem *curr_bd; - struct emac_rxch *rxch = RT_NULL; + rt_uint32_t cnt, bd_size; + void __iomem *mem; + struct emac_rx_bd __iomem *curr_bd; + struct emac_rxch *rxch = RT_NULL; - rxch = rt_malloc(sizeof(struct emac_rxch)); - if (RT_NULL == rxch) { - rt_kprintf("DaVinci EMAC: RX Ch mem alloc failed"); - return -ENOMEM; - } - rt_memset(rxch, 0, sizeof(struct emac_rxch)); - priv->rxch[ch] = rxch; - rxch->buf_size = priv->rx_buf_size; - rxch->service_max = EMAC_DEF_RX_MAX_SERVICE; - rxch->queue_active = 0; - rxch->teardown_pending = 0; + rxch = rt_malloc(sizeof(struct emac_rxch)); + if (RT_NULL == rxch) { + rt_kprintf("DaVinci EMAC: RX Ch mem alloc failed"); + return -ENOMEM; + } + rt_memset(rxch, 0, sizeof(struct emac_rxch)); + priv->rxch[ch] = rxch; + rxch->buf_size = priv->rx_buf_size; + rxch->service_max = EMAC_DEF_RX_MAX_SERVICE; + rxch->queue_active = 0; + rxch->teardown_pending = 0; - /* save mac address */ - for (cnt = 0; cnt < 6; cnt++) - rxch->mac_addr[cnt] = param[cnt]; + /* save mac address */ + for (cnt = 0; cnt < 6; cnt++) + rxch->mac_addr[cnt] = param[cnt]; - /* allocate buffer descriptor pool align every BD on four word - * boundry for future requirements */ - bd_size = (sizeof(struct emac_rx_bd) + 0xF) & ~0xF; - rxch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size; - rxch->alloc_size = (((bd_size * rxch->num_bd) + 0xF) & ~0xF); - rxch->bd_mem = EMAC_RX_BD_MEM(priv); + /* allocate buffer descriptor pool align every BD on four word + * boundry for future requirements */ + bd_size = (sizeof(struct emac_rx_bd) + 0xF) & ~0xF; + rxch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size; + rxch->alloc_size = (((bd_size * rxch->num_bd) + 0xF) & ~0xF); + rxch->bd_mem = EMAC_RX_BD_MEM(priv); - rt_memset((void *)rxch->bd_mem, 0, rxch->alloc_size); - rxch->pkt_queue.buf_list = &rxch->buf_queue; + rt_memset((void *)rxch->bd_mem, 0, rxch->alloc_size); + rxch->pkt_queue.buf_list = &rxch->buf_queue; - /* allocate RX buffer and initialize the BD linked list */ - mem = (void __iomem *) - (((rt_uint32_t) rxch->bd_mem + 0xF) & ~0xF); - rxch->active_queue_head = RT_NULL; - rxch->active_queue_tail = mem; - for (cnt = 0; cnt < rxch->num_bd; cnt++) { - curr_bd = mem + (cnt * bd_size); - /* for future use the last parameter contains the BD ptr */ - curr_bd->data_ptr = emac_net_alloc_rx_buf(priv, - rxch->buf_size, - (void **)&curr_bd->buf_token, - EMAC_DEF_RX_CH); - if (curr_bd->data_ptr == RT_NULL) { - rt_kprintf("DaVinci EMAC: RX buf mem alloc " \ - "failed for ch %d\n", ch); - rt_free(rxch); - return -RT_ENOMEM; - } + /* allocate RX buffer and initialize the BD linked list */ + mem = (void __iomem *) + (((rt_uint32_t) rxch->bd_mem + 0xF) & ~0xF); + rxch->active_queue_head = RT_NULL; + rxch->active_queue_tail = mem; + for (cnt = 0; cnt < rxch->num_bd; cnt++) { + curr_bd = mem + (cnt * bd_size); + /* for future use the last parameter contains the BD ptr */ + curr_bd->data_ptr = emac_net_alloc_rx_buf(priv, + rxch->buf_size, + (void **)&curr_bd->buf_token, + EMAC_DEF_RX_CH); + if (curr_bd->data_ptr == RT_NULL) { + rt_kprintf("DaVinci EMAC: RX buf mem alloc " \ + "failed for ch %d\n", ch); + rt_free(rxch); + return -RT_ENOMEM; + } - /* populate the hardware descriptor */ - curr_bd->h_next = emac_virt_to_phys(rxch->active_queue_head); - curr_bd->buff_ptr = virt_to_phys(curr_bd->data_ptr); - curr_bd->off_b_len = rxch->buf_size; - curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT; + /* populate the hardware descriptor */ + curr_bd->h_next = emac_virt_to_phys(rxch->active_queue_head); + curr_bd->buff_ptr = virt_to_phys(curr_bd->data_ptr); + curr_bd->off_b_len = rxch->buf_size; + curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT; - /* write back to hardware memory */ - BD_CACHE_WRITEBACK_INVALIDATE((rt_uint32_t) curr_bd, - EMAC_BD_LENGTH_FOR_CACHE); - curr_bd->next = rxch->active_queue_head; - rxch->active_queue_head = curr_bd; - } + /* write back to hardware memory */ + BD_CACHE_WRITEBACK_INVALIDATE((rt_uint32_t) curr_bd, + EMAC_BD_LENGTH_FOR_CACHE); + curr_bd->next = rxch->active_queue_head; + rxch->active_queue_head = curr_bd; + } - /* At this point rxCppi->activeQueueHead points to the first - RX BD ready to be given to RX HDP and rxch->active_queue_tail - points to the last RX BD - */ - return 0; + /* At this point rxCppi->activeQueueHead points to the first + RX BD ready to be given to RX HDP and rxch->active_queue_tail + points to the last RX BD + */ + return 0; } @@ -1303,23 +1289,23 @@ static int emac_init_rxch(struct emac_priv *priv, rt_uint32_t ch, char *param) */ static void emac_int_disable(struct emac_priv *priv) { - if (priv->version == EMAC_VERSION_2) { - unsigned long flags; + if (priv->version == EMAC_VERSION_2) { + unsigned long flags; - rt_interrupt_enter(); + rt_interrupt_enter(); - /* Program C0_Int_En to zero to turn off - * interrupts to the CPU */ - emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0); - emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0); - /* NOTE: Rx Threshold and Misc interrupts are not disabled */ + /* Program C0_Int_En to zero to turn off + * interrupts to the CPU */ + emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0); + emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0); + /* NOTE: Rx Threshold and Misc interrupts are not disabled */ - rt_interrupt_leave(); + rt_interrupt_leave(); - } else { - /* Set DM644x control registers for interrupt control */ - emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0); - } + } else { + /* Set DM644x control registers for interrupt control */ + emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0); + } } @@ -1332,31 +1318,31 @@ static void emac_int_disable(struct emac_priv *priv) */ static void emac_int_enable(struct emac_priv *priv) { - if (priv->version == EMAC_VERSION_2) { - /*if (priv->int_enable) - priv->int_enable();*/ + if (priv->version == EMAC_VERSION_2) { + /*if (priv->int_enable) + priv->int_enable();*/ - emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff); - emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff); + emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff); + emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff); - /* In addition to turning on interrupt Enable, we need - * ack by writing appropriate values to the EOI - * register */ + /* In addition to turning on interrupt Enable, we need + * ack by writing appropriate values to the EOI + * register */ - /* NOTE: Rx Threshold and Misc interrupts are not enabled */ + /* NOTE: Rx Threshold and Misc interrupts are not enabled */ - /* ack rxen only then a new pulse will be generated */ - emac_write(EMAC_DM646X_MACEOIVECTOR, - EMAC_DM646X_MAC_EOI_C0_RXEN); + /* ack rxen only then a new pulse will be generated */ + emac_write(EMAC_DM646X_MACEOIVECTOR, + EMAC_DM646X_MAC_EOI_C0_RXEN); - /* ack txen- only then a new pulse will be generated */ - emac_write(EMAC_DM646X_MACEOIVECTOR, - EMAC_DM646X_MAC_EOI_C0_TXEN); + /* ack txen- only then a new pulse will be generated */ + emac_write(EMAC_DM646X_MACEOIVECTOR, + EMAC_DM646X_MAC_EOI_C0_TXEN); - } else { - /* Set DM644x control registers for interrupt control */ - emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1); - } + } else { + /* Set DM644x control registers for interrupt control */ + emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1); + } } @@ -1368,11 +1354,11 @@ static void emac_int_enable(struct emac_priv *priv) */ static void emac_irq(int irq, void *param) { - struct emac_priv *priv = param; + struct emac_priv *priv = param; - ++priv->isr_count; - emac_int_disable(priv); - eth_device_ready(&priv->parent); + ++priv->isr_count; + emac_int_disable(priv); + eth_device_ready(&priv->parent); } @@ -1388,77 +1374,77 @@ static void emac_irq(int irq, void *param) */ static int emac_hw_enable(struct emac_priv *priv) { - rt_uint32_t ch, val, mbp_enable, mac_control; + rt_uint32_t ch, val, mbp_enable, mac_control; - /* Soft reset */ - emac_write(EMAC_SOFTRESET, 1); - while (emac_read(EMAC_SOFTRESET)); + /* Soft reset */ + emac_write(EMAC_SOFTRESET, 1); + while (emac_read(EMAC_SOFTRESET)); - /* Disable interrupt & Set pacing for more interrupts initially */ - emac_int_disable(priv); + /* Disable interrupt & Set pacing for more interrupts initially */ + emac_int_disable(priv); - /* Full duplex enable bit set when auto negotiation happens */ - mac_control = - (((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) | - ((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) | - ((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) | - ((priv->duplex == DUPLEX_FULL) ? 0x1 : 0)); - emac_write(EMAC_MACCONTROL, mac_control); + /* Full duplex enable bit set when auto negotiation happens */ + mac_control = + (((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) | + ((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) | + ((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) | + ((priv->duplex == DUPLEX_FULL) ? 0x1 : 0)); + emac_write(EMAC_MACCONTROL, mac_control); - mbp_enable = - (((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) | - ((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) | - ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) | - ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) | - ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) | - ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) | - ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) | - ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \ - EMAC_RXMBP_PROMCH_SHIFT) | - ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) | - ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \ - EMAC_RXMBP_BROADCH_SHIFT) | - ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) | - ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \ - EMAC_RXMBP_MULTICH_SHIFT)); - emac_write(EMAC_RXMBPENABLE, mbp_enable); - emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE & - EMAC_RX_MAX_LEN_MASK)); - emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET & - EMAC_RX_BUFFER_OFFSET_MASK)); - emac_write(EMAC_RXFILTERLOWTHRESH, 0); - emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL); - priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF; + mbp_enable = + (((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) | + ((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) | + ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) | + ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) | + ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) | + ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) | + ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) | + ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \ + EMAC_RXMBP_PROMCH_SHIFT) | + ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) | + ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \ + EMAC_RXMBP_BROADCH_SHIFT) | + ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) | + ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \ + EMAC_RXMBP_MULTICH_SHIFT)); + emac_write(EMAC_RXMBPENABLE, mbp_enable); + emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE & + EMAC_RX_MAX_LEN_MASK)); + emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET & + EMAC_RX_BUFFER_OFFSET_MASK)); + emac_write(EMAC_RXFILTERLOWTHRESH, 0); + emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL); + priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF; - val = emac_read(EMAC_TXCONTROL); - val |= EMAC_TX_CONTROL_TX_ENABLE_VAL; - emac_write(EMAC_TXCONTROL, val); - val = emac_read(EMAC_RXCONTROL); - val |= EMAC_RX_CONTROL_RX_ENABLE_VAL; - emac_write(EMAC_RXCONTROL, val); - emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL); + val = emac_read(EMAC_TXCONTROL); + val |= EMAC_TX_CONTROL_TX_ENABLE_VAL; + emac_write(EMAC_TXCONTROL, val); + val = emac_read(EMAC_RXCONTROL); + val |= EMAC_RX_CONTROL_RX_ENABLE_VAL; + emac_write(EMAC_RXCONTROL, val); + emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL); - for (ch = 0; ch < EMAC_DEF_MAX_TX_CH; ch++) { - emac_write(EMAC_TXHDP(ch), 0); - emac_write(EMAC_TXINTMASKSET, BIT(ch)); - } - for (ch = 0; ch < EMAC_DEF_MAX_RX_CH; ch++) { - struct emac_rxch *rxch = priv->rxch[ch]; - emac_setmac(priv, ch, rxch->mac_addr); - emac_write(EMAC_RXINTMASKSET, BIT(ch)); - rxch->queue_active = 1; - emac_write(EMAC_RXHDP(ch), - (unsigned int)(rxch->active_queue_head)); /* physcal addr */ - } + for (ch = 0; ch < EMAC_DEF_MAX_TX_CH; ch++) { + emac_write(EMAC_TXHDP(ch), 0); + emac_write(EMAC_TXINTMASKSET, BIT(ch)); + } + for (ch = 0; ch < EMAC_DEF_MAX_RX_CH; ch++) { + struct emac_rxch *rxch = priv->rxch[ch]; + emac_setmac(priv, ch, rxch->mac_addr); + emac_write(EMAC_RXINTMASKSET, BIT(ch)); + rxch->queue_active = 1; + emac_write(EMAC_RXHDP(ch), + (unsigned int)(rxch->active_queue_head)); /* physcal addr */ + } - /* Enable MII */ - val = emac_read(EMAC_MACCONTROL); - val |= (EMAC_MACCONTROL_GMIIEN); - emac_write(EMAC_MACCONTROL, val); + /* Enable MII */ + val = emac_read(EMAC_MACCONTROL); + val |= (EMAC_MACCONTROL_GMIIEN); + emac_write(EMAC_MACCONTROL, val); - /* Enable interrupts */ - emac_int_enable(priv); - return 0; + /* Enable interrupts */ + emac_int_enable(priv); + return 0; } @@ -1472,51 +1458,51 @@ static int emac_hw_enable(struct emac_priv *priv) */ static struct net_device_stats *emac_dev_getnetstats(struct emac_priv *priv) { - rt_uint32_t mac_control; - rt_uint32_t stats_clear_mask; + rt_uint32_t mac_control; + rt_uint32_t stats_clear_mask; - /* update emac hardware stats and reset the registers*/ + /* update emac hardware stats and reset the registers*/ - mac_control = emac_read(EMAC_MACCONTROL); + mac_control = emac_read(EMAC_MACCONTROL); - if (mac_control & EMAC_MACCONTROL_GMIIEN) - stats_clear_mask = EMAC_STATS_CLR_MASK; - else - stats_clear_mask = 0; + if (mac_control & EMAC_MACCONTROL_GMIIEN) + stats_clear_mask = EMAC_STATS_CLR_MASK; + else + stats_clear_mask = 0; - priv->net_dev_stats.multicast += emac_read(EMAC_RXMCASTFRAMES); - emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask); + priv->net_dev_stats.multicast += emac_read(EMAC_RXMCASTFRAMES); + emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask); - priv->net_dev_stats.collisions += (emac_read(EMAC_TXCOLLISION) + - emac_read(EMAC_TXSINGLECOLL) + - emac_read(EMAC_TXMULTICOLL)); - emac_write(EMAC_TXCOLLISION, stats_clear_mask); - emac_write(EMAC_TXSINGLECOLL, stats_clear_mask); - emac_write(EMAC_TXMULTICOLL, stats_clear_mask); + priv->net_dev_stats.collisions += (emac_read(EMAC_TXCOLLISION) + + emac_read(EMAC_TXSINGLECOLL) + + emac_read(EMAC_TXMULTICOLL)); + emac_write(EMAC_TXCOLLISION, stats_clear_mask); + emac_write(EMAC_TXSINGLECOLL, stats_clear_mask); + emac_write(EMAC_TXMULTICOLL, stats_clear_mask); - priv->net_dev_stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) + - emac_read(EMAC_RXJABBER) + - emac_read(EMAC_RXUNDERSIZED)); - emac_write(EMAC_RXOVERSIZED, stats_clear_mask); - emac_write(EMAC_RXJABBER, stats_clear_mask); - emac_write(EMAC_RXUNDERSIZED, stats_clear_mask); + priv->net_dev_stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) + + emac_read(EMAC_RXJABBER) + + emac_read(EMAC_RXUNDERSIZED)); + emac_write(EMAC_RXOVERSIZED, stats_clear_mask); + emac_write(EMAC_RXJABBER, stats_clear_mask); + emac_write(EMAC_RXUNDERSIZED, stats_clear_mask); - priv->net_dev_stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) + - emac_read(EMAC_RXMOFOVERRUNS)); - emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask); - emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask); + priv->net_dev_stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) + + emac_read(EMAC_RXMOFOVERRUNS)); + emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask); + emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask); - priv->net_dev_stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS); - emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask); + priv->net_dev_stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS); + emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask); - priv->net_dev_stats.tx_carrier_errors += - emac_read(EMAC_TXCARRIERSENSE); - emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask); + priv->net_dev_stats.tx_carrier_errors += + emac_read(EMAC_TXCARRIERSENSE); + emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask); - priv->net_dev_stats.tx_fifo_errors = emac_read(EMAC_TXUNDERRUN); - emac_write(EMAC_TXUNDERRUN, stats_clear_mask); + priv->net_dev_stats.tx_fifo_errors = emac_read(EMAC_TXUNDERRUN); + emac_write(EMAC_TXUNDERRUN, stats_clear_mask); - return &priv->net_dev_stats; + return &priv->net_dev_stats; } @@ -1525,164 +1511,164 @@ static struct net_device_stats *emac_dev_getnetstats(struct emac_priv *priv) static rt_err_t rt_davinci_emac_init(rt_device_t dev) { - struct emac_priv *priv = dev->user_data; - unsigned long paddr; - rt_uint32_t ch, rc; - int i; + struct emac_priv *priv = dev->user_data; + unsigned long paddr; + rt_uint32_t ch, rc; + int i; - /* Configuration items */ - priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN; + /* Configuration items */ + priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN; - /* Clear basic hardware */ - for (ch = 0; ch < EMAC_MAX_TXRX_CHANNELS; ch++) { - emac_write(EMAC_TXHDP(ch), 0); - emac_write(EMAC_RXHDP(ch), 0); - emac_write(EMAC_RXHDP(ch), 0); - emac_write(EMAC_RXINTMASKCLEAR, EMAC_INT_MASK_CLEAR); - emac_write(EMAC_TXINTMASKCLEAR, EMAC_INT_MASK_CLEAR); - } - priv->mac_hash1 = 0; - priv->mac_hash2 = 0; - emac_write(EMAC_MACHASH1, 0); - emac_write(EMAC_MACHASH2, 0); + /* Clear basic hardware */ + for (ch = 0; ch < EMAC_MAX_TXRX_CHANNELS; ch++) { + emac_write(EMAC_TXHDP(ch), 0); + emac_write(EMAC_RXHDP(ch), 0); + emac_write(EMAC_RXHDP(ch), 0); + emac_write(EMAC_RXINTMASKCLEAR, EMAC_INT_MASK_CLEAR); + emac_write(EMAC_TXINTMASKCLEAR, EMAC_INT_MASK_CLEAR); + } + priv->mac_hash1 = 0; + priv->mac_hash2 = 0; + emac_write(EMAC_MACHASH1, 0); + emac_write(EMAC_MACHASH2, 0); - /* multi ch not supported - open 1 TX, 1RX ch by default */ - rc = emac_init_txch(priv, EMAC_DEF_TX_CH); - if (0 != rc) { - rt_kprintf("DaVinci EMAC: emac_init_txch() failed"); - return rc; - } - rc = emac_init_rxch(priv, EMAC_DEF_RX_CH, priv->mac_addr); - if (0 != rc) { - rt_kprintf("DaVinci EMAC: emac_init_rxch() failed"); - return rc; - } + /* multi ch not supported - open 1 TX, 1RX ch by default */ + rc = emac_init_txch(priv, EMAC_DEF_TX_CH); + if (0 != rc) { + rt_kprintf("DaVinci EMAC: emac_init_txch() failed"); + return rc; + } + rc = emac_init_rxch(priv, EMAC_DEF_RX_CH, priv->mac_addr); + if (0 != rc) { + rt_kprintf("DaVinci EMAC: emac_init_rxch() failed"); + return rc; + } - rt_hw_interrupt_install(IRQ_DM365_EMAC_RXPULSE, emac_irq, - (void *)priv, "EMAC_RXPULSE"); - rt_hw_interrupt_umask(IRQ_DM365_EMAC_RXPULSE); - rt_hw_interrupt_install(IRQ_DM365_EMAC_TXPULSE, emac_irq, - (void *)priv, "EMAC_TXPULSE"); - rt_hw_interrupt_umask(IRQ_DM365_EMAC_TXPULSE); - rt_hw_interrupt_install(IRQ_DM365_EMAC_RXTHRESH, emac_irq, - (void *)priv, "EMAC_RXTHRESH"); - rt_hw_interrupt_umask(IRQ_DM365_EMAC_RXTHRESH); - rt_hw_interrupt_install(IRQ_DM365_EMAC_MISCPULSE, emac_irq, - (void *)priv, "EMAC_MISCPULSE"); - rt_hw_interrupt_umask(IRQ_DM365_EMAC_MISCPULSE); + rt_hw_interrupt_install(IRQ_DM365_EMAC_RXPULSE, emac_irq, + (void *)priv, "EMAC_RXPULSE"); + rt_hw_interrupt_umask(IRQ_DM365_EMAC_RXPULSE); + rt_hw_interrupt_install(IRQ_DM365_EMAC_TXPULSE, emac_irq, + (void *)priv, "EMAC_TXPULSE"); + rt_hw_interrupt_umask(IRQ_DM365_EMAC_TXPULSE); + rt_hw_interrupt_install(IRQ_DM365_EMAC_RXTHRESH, emac_irq, + (void *)priv, "EMAC_RXTHRESH"); + rt_hw_interrupt_umask(IRQ_DM365_EMAC_RXTHRESH); + rt_hw_interrupt_install(IRQ_DM365_EMAC_MISCPULSE, emac_irq, + (void *)priv, "EMAC_MISCPULSE"); + rt_hw_interrupt_umask(IRQ_DM365_EMAC_MISCPULSE); - emac_mii_reset(priv); - davinci_emac_phy_init(dev); + emac_mii_reset(priv); + davinci_emac_phy_init(dev); - /* Start/Enable EMAC hardware */ - emac_hw_enable(priv); + /* Start/Enable EMAC hardware */ + emac_hw_enable(priv); - rt_timer_init(&priv->timer, "link_timer", - davinci_emac_update_link, - (void *)priv, - RT_TICK_PER_SECOND, - RT_TIMER_FLAG_PERIODIC); + rt_timer_init(&priv->timer, "link_timer", + davinci_emac_update_link, + (void *)priv, + RT_TICK_PER_SECOND, + RT_TIMER_FLAG_PERIODIC); - rt_timer_start(&priv->timer); - rt_kprintf("davinci emac initialized\n"); - - return RT_EOK; + rt_timer_start(&priv->timer); + rt_kprintf("davinci emac initialized\n"); + + return RT_EOK; } static rt_err_t rt_davinci_emac_open(rt_device_t dev, rt_uint16_t oflag) { - return RT_EOK; + return RT_EOK; } static rt_err_t rt_davinci_emac_close(rt_device_t dev) { - return RT_EOK; + return RT_EOK; } static rt_size_t rt_davinci_emac_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_size_t rt_davinci_emac_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_err_t rt_davinci_emac_control(rt_device_t dev, int cmd, void *args) { - struct emac_priv *priv = dev->user_data; - switch(cmd) - { - case NIOCTL_GADDR: - /* get mac address */ - if(args) rt_memcpy(args, priv->mac_addr, 6); - else return -RT_ERROR; - break; + struct emac_priv *priv = dev->user_data; + switch(cmd) + { + case NIOCTL_GADDR: + /* get mac address */ + if(args) rt_memcpy(args, priv->mac_addr, 6); + else return -RT_ERROR; + break; - default : - break; - } + default : + break; + } - return RT_EOK; + return RT_EOK; } void dm365_emac_gpio_init(void) { - rt_uint32_t arm_intmux; + rt_uint32_t arm_intmux; - /* - * EMAC interrupts are multiplexed with GPIO interrupts - * Details are available at the DM365 ARM - * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134 - */ - arm_intmux = davinci_readl(DM365_ARM_INTMUX); - arm_intmux |= (1 << 14)|(1 << 15)|(1 << 16)|(1 << 17); - davinci_writel(arm_intmux, DM365_ARM_INTMUX); + /* + * EMAC interrupts are multiplexed with GPIO interrupts + * Details are available at the DM365 ARM + * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134 + */ + arm_intmux = davinci_readl(DM365_ARM_INTMUX); + arm_intmux |= (1 << 14)|(1 << 15)|(1 << 16)|(1 << 17); + davinci_writel(arm_intmux, DM365_ARM_INTMUX); } int rt_hw_davinci_emac_init() { - struct emac_priv *priv = &davinci_emac_device; - struct clk *emac_clk; - emac_clk = clk_get("EMACCLK"); - emac_bus_frequency = clk_get_rate(emac_clk); - psc_change_state(DAVINCI_DM365_LPSC_CPGMAC, PSC_ENABLE); - dm365_emac_gpio_init(); - rt_memset(&davinci_emac_device, 0, sizeof(davinci_emac_device)); - davinci_emac_device.emac_base = (void __iomem *)DM365_EMAC_CNTRL_BASE; - davinci_emac_device.ctrl_base = (void __iomem *)DM365_EMAC_WRAP_CNTRL_BASE; - davinci_emac_device.ctrl_ram_size = DM365_EMAC_CNTRL_RAM_SIZE; - davinci_emac_device.emac_ctrl_ram = (void __iomem *)DM365_EMAC_WRAP_RAM_BASE; - davinci_emac_device.mdio_base = (void __iomem *)DM365_EMAC_MDIO_BASE; - davinci_emac_device.version = EMAC_VERSION_2; - davinci_emac_device.rmii_en = 0; - davinci_emac_device.phy_addr = 0x09; - rt_sem_init(&priv->tx_lock, "tx_lock", 1, RT_IPC_FLAG_FIFO); - rt_sem_init(&priv->rx_lock, "rx_lock", 1, RT_IPC_FLAG_FIFO); + struct emac_priv *priv = &davinci_emac_device; + struct clk *emac_clk; + emac_clk = clk_get("EMACCLK"); + emac_bus_frequency = clk_get_rate(emac_clk); + psc_change_state(DAVINCI_DM365_LPSC_CPGMAC, PSC_ENABLE); + dm365_emac_gpio_init(); + rt_memset(&davinci_emac_device, 0, sizeof(davinci_emac_device)); + davinci_emac_device.emac_base = (void __iomem *)DM365_EMAC_CNTRL_BASE; + davinci_emac_device.ctrl_base = (void __iomem *)DM365_EMAC_WRAP_CNTRL_BASE; + davinci_emac_device.ctrl_ram_size = DM365_EMAC_CNTRL_RAM_SIZE; + davinci_emac_device.emac_ctrl_ram = (void __iomem *)DM365_EMAC_WRAP_RAM_BASE; + davinci_emac_device.mdio_base = (void __iomem *)DM365_EMAC_MDIO_BASE; + davinci_emac_device.version = EMAC_VERSION_2; + davinci_emac_device.rmii_en = 0; + davinci_emac_device.phy_addr = 0x09; + rt_sem_init(&priv->tx_lock, "tx_lock", 1, RT_IPC_FLAG_FIFO); + rt_sem_init(&priv->rx_lock, "rx_lock", 1, RT_IPC_FLAG_FIFO); - davinci_emac_device.mac_addr[0] = 0x00; - davinci_emac_device.mac_addr[1] = 0x60; - davinci_emac_device.mac_addr[2] = 0x6E; - davinci_emac_device.mac_addr[3] = 0x11; - davinci_emac_device.mac_addr[4] = 0x22; - davinci_emac_device.mac_addr[5] = 0x33; - - davinci_emac_device.parent.parent.init = rt_davinci_emac_init; - davinci_emac_device.parent.parent.open = rt_davinci_emac_open; - davinci_emac_device.parent.parent.close = rt_davinci_emac_close; - davinci_emac_device.parent.parent.read = rt_davinci_emac_read; - davinci_emac_device.parent.parent.write = rt_davinci_emac_write; - davinci_emac_device.parent.parent.control = rt_davinci_emac_control; - davinci_emac_device.parent.parent.user_data = &davinci_emac_device; + davinci_emac_device.mac_addr[0] = 0x00; + davinci_emac_device.mac_addr[1] = 0x60; + davinci_emac_device.mac_addr[2] = 0x6E; + davinci_emac_device.mac_addr[3] = 0x11; + davinci_emac_device.mac_addr[4] = 0x22; + davinci_emac_device.mac_addr[5] = 0x33; - davinci_emac_device.parent.eth_rx = rt_davinci_emac_rx; - davinci_emac_device.parent.eth_tx = rt_davinci_emac_tx; + davinci_emac_device.parent.parent.init = rt_davinci_emac_init; + davinci_emac_device.parent.parent.open = rt_davinci_emac_open; + davinci_emac_device.parent.parent.close = rt_davinci_emac_close; + davinci_emac_device.parent.parent.read = rt_davinci_emac_read; + davinci_emac_device.parent.parent.write = rt_davinci_emac_write; + davinci_emac_device.parent.parent.control = rt_davinci_emac_control; + davinci_emac_device.parent.parent.user_data = &davinci_emac_device; + + davinci_emac_device.parent.eth_rx = rt_davinci_emac_rx; + davinci_emac_device.parent.eth_tx = rt_davinci_emac_tx; + + eth_device_init(&(davinci_emac_device.parent), "e0"); - eth_device_init(&(davinci_emac_device.parent), "e0"); - } INIT_DEVICE_EXPORT(rt_hw_davinci_emac_init); @@ -1693,68 +1679,68 @@ INIT_DEVICE_EXPORT(rt_hw_davinci_emac_init); void dump_emac_stats(void) { - int i; - struct emac_priv *emac; - struct net_device_stats *stats; - rt_device_t dev = rt_device_find("e0"); + int i; + struct emac_priv *emac; + struct net_device_stats *stats; + rt_device_t dev = rt_device_find("e0"); - if(dev == RT_NULL) - return; + if(dev == RT_NULL) + return; - emac = (struct emac_priv *)dev->user_data; + emac = (struct emac_priv *)dev->user_data; - stats = emac_dev_getnetstats(emac); - rt_kprintf("rx_packets = %d\n" - "tx_packets = %d\n" - "rx_bytes = %d\n" - "tx_bytes = %d\n" - "rx_errors = %d\n" - "tx_errors = %d\n" - "rx_dropped = %d\n" - "tx_dropped = %d\n" - "multicast = %d\n" - "collisions = %d\n", - stats->rx_packets, - stats->tx_packets, - stats->rx_bytes, - stats->tx_bytes, - stats->rx_errors, - stats->tx_errors, - stats->rx_dropped, - stats->tx_dropped, - stats->multicast, - stats->collisions); + stats = emac_dev_getnetstats(emac); + rt_kprintf("rx_packets = %d\n" + "tx_packets = %d\n" + "rx_bytes = %d\n" + "tx_bytes = %d\n" + "rx_errors = %d\n" + "tx_errors = %d\n" + "rx_dropped = %d\n" + "tx_dropped = %d\n" + "multicast = %d\n" + "collisions = %d\n", + stats->rx_packets, + stats->tx_packets, + stats->rx_bytes, + stats->tx_bytes, + stats->rx_errors, + stats->tx_errors, + stats->rx_dropped, + stats->tx_dropped, + stats->multicast, + stats->collisions); - rt_kprintf("rx_length_errors = %d\n" - "rx_over_errors = %d\n" - "rx_crc_errors = %d\n" - "rx_frame_errors = %d\n" - "rx_fifo_errors = %d\n" - "rx_missed_errors = %d\n", - stats->rx_length_errors, - stats->rx_over_errors, - stats->rx_crc_errors, - stats->rx_frame_errors, - stats->rx_fifo_errors, - stats->rx_missed_errors); + rt_kprintf("rx_length_errors = %d\n" + "rx_over_errors = %d\n" + "rx_crc_errors = %d\n" + "rx_frame_errors = %d\n" + "rx_fifo_errors = %d\n" + "rx_missed_errors = %d\n", + stats->rx_length_errors, + stats->rx_over_errors, + stats->rx_crc_errors, + stats->rx_frame_errors, + stats->rx_fifo_errors, + stats->rx_missed_errors); - rt_kprintf("tx_aborted_errors = %d\n" - "tx_carrier_errors = %d\n" - "tx_fifo_errors = %d\n" - "tx_heartbeat_errors = %d\n" - "tx_window_errors = %d\n", - stats->tx_aborted_errors, - stats->tx_carrier_errors, - stats->tx_fifo_errors, - stats->tx_heartbeat_errors, - stats->tx_window_errors); + rt_kprintf("tx_aborted_errors = %d\n" + "tx_carrier_errors = %d\n" + "tx_fifo_errors = %d\n" + "tx_heartbeat_errors = %d\n" + "tx_window_errors = %d\n", + stats->tx_aborted_errors, + stats->tx_carrier_errors, + stats->tx_fifo_errors, + stats->tx_heartbeat_errors, + stats->tx_window_errors); - rt_kprintf("rx_compressed = %d\n" - "tx_compressed = %d\n", - stats->rx_compressed, - stats->tx_compressed); + rt_kprintf("rx_compressed = %d\n" + "tx_compressed = %d\n", + stats->rx_compressed, + stats->tx_compressed); - rt_kprintf("\n"); + rt_kprintf("\n"); } FINSH_FUNCTION_EXPORT(dump_emac_stats, dump emac statistics); @@ -1762,8 +1748,8 @@ FINSH_FUNCTION_EXPORT(dump_emac_stats, dump emac statistics); #ifdef FINSH_USING_MSH int cmd_dump_emac_stats(int argc, char** argv) { - dump_emac_stats(); - return 0; + dump_emac_stats(); + return 0; } FINSH_FUNCTION_EXPORT_ALIAS(cmd_dump_emac_stats, __cmd_dump_emac_stats, dump emac statistics.); #endif diff --git a/bsp/dm365/drivers/davinci_emac.h b/bsp/dm365/drivers/davinci_emac.h index 026323c286..1d80c754c9 100644 --- a/bsp/dm365/drivers/davinci_emac.h +++ b/bsp/dm365/drivers/davinci_emac.h @@ -1,25 +1,11 @@ /* - * File : davinci_emac.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2013-01-30 weety first version + * Date Author Notes + * 2013-01-30 weety first version */ #ifndef _DAVINCI_EMAC_H @@ -31,249 +17,249 @@ #endif enum { - EMAC_VERSION_1, /* DM644x */ - EMAC_VERSION_2, /* DM646x */ + EMAC_VERSION_1, /* DM644x */ + EMAC_VERSION_2, /* DM646x */ }; #define __iomem -#define BIT(nr) (1UL << (nr)) +#define BIT(nr) (1UL << (nr)) /* Configuration items */ -#define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC upto frames */ -#define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */ -#define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */ -#define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */ -#define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */ -#define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */ -#define EMAC_DEF_PROM_EN (0) /* Promiscous disabled */ -#define EMAC_DEF_PROM_CH (0) /* Promiscous channel is 0 */ -#define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */ -#define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */ -#define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */ -#define EMAC_DEF_MCAST_CH (0) /* Multicast channel is 0 */ +#define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC upto frames */ +#define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */ +#define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */ +#define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */ +#define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */ +#define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */ +#define EMAC_DEF_PROM_EN (0) /* Promiscous disabled */ +#define EMAC_DEF_PROM_CH (0) /* Promiscous channel is 0 */ +#define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */ +#define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */ +#define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */ +#define EMAC_DEF_MCAST_CH (0) /* Multicast channel is 0 */ -#define EMAC_DEF_TXPRIO_FIXED (1) /* TX Priority is fixed */ -#define EMAC_DEF_TXPACING_EN (0) /* TX pacing NOT supported*/ +#define EMAC_DEF_TXPRIO_FIXED (1) /* TX Priority is fixed */ +#define EMAC_DEF_TXPACING_EN (0) /* TX pacing NOT supported*/ -#define EMAC_DEF_BUFFER_OFFSET (0) /* Buffer offset to DMA (future) */ -#define EMAC_DEF_MIN_ETHPKTSIZE (60) /* Minimum ethernet pkt size */ -#define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4) -#define EMAC_DEF_TX_CH (0) /* Default 0th channel */ -#define EMAC_DEF_RX_CH (0) /* Default 0th channel */ -#define EMAC_DEF_MDIO_TICK_MS (10) /* typically 1 tick=1 ms) */ -#define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */ -#define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */ -#define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */ +#define EMAC_DEF_BUFFER_OFFSET (0) /* Buffer offset to DMA (future) */ +#define EMAC_DEF_MIN_ETHPKTSIZE (60) /* Minimum ethernet pkt size */ +#define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4) +#define EMAC_DEF_TX_CH (0) /* Default 0th channel */ +#define EMAC_DEF_RX_CH (0) /* Default 0th channel */ +#define EMAC_DEF_MDIO_TICK_MS (10) /* typically 1 tick=1 ms) */ +#define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */ +#define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */ +#define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */ /* Buffer descriptor parameters */ -#define EMAC_DEF_TX_MAX_SERVICE (32) /* TX max service BD's */ -#define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */ +#define EMAC_DEF_TX_MAX_SERVICE (32) /* TX max service BD's */ +#define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */ /* EMAC register related defines */ -#define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF) -#define EMAC_NUM_MULTICAST_BITS (64) -#define EMAC_TEARDOWN_VALUE (0xFFFFFFFC) -#define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1) -#define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1) -#define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2) -#define EMAC_RX_UNICAST_CLEAR_ALL (0xFF) -#define EMAC_INT_MASK_CLEAR (0xFF) +#define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF) +#define EMAC_NUM_MULTICAST_BITS (64) +#define EMAC_TEARDOWN_VALUE (0xFFFFFFFC) +#define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1) +#define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1) +#define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2) +#define EMAC_RX_UNICAST_CLEAR_ALL (0xFF) +#define EMAC_INT_MASK_CLEAR (0xFF) /* RX MBP register bit positions */ -#define EMAC_RXMBP_PASSCRC_MASK BIT(30) -#define EMAC_RXMBP_QOSEN_MASK BIT(29) -#define EMAC_RXMBP_NOCHAIN_MASK BIT(28) -#define EMAC_RXMBP_CMFEN_MASK BIT(24) -#define EMAC_RXMBP_CSFEN_MASK BIT(23) -#define EMAC_RXMBP_CEFEN_MASK BIT(22) -#define EMAC_RXMBP_CAFEN_MASK BIT(21) -#define EMAC_RXMBP_PROMCH_SHIFT (16) -#define EMAC_RXMBP_PROMCH_MASK (0x7 << 16) -#define EMAC_RXMBP_BROADEN_MASK BIT(13) -#define EMAC_RXMBP_BROADCH_SHIFT (8) -#define EMAC_RXMBP_BROADCH_MASK (0x7 << 8) -#define EMAC_RXMBP_MULTIEN_MASK BIT(5) -#define EMAC_RXMBP_MULTICH_SHIFT (0) -#define EMAC_RXMBP_MULTICH_MASK (0x7) -#define EMAC_RXMBP_CHMASK (0x7) +#define EMAC_RXMBP_PASSCRC_MASK BIT(30) +#define EMAC_RXMBP_QOSEN_MASK BIT(29) +#define EMAC_RXMBP_NOCHAIN_MASK BIT(28) +#define EMAC_RXMBP_CMFEN_MASK BIT(24) +#define EMAC_RXMBP_CSFEN_MASK BIT(23) +#define EMAC_RXMBP_CEFEN_MASK BIT(22) +#define EMAC_RXMBP_CAFEN_MASK BIT(21) +#define EMAC_RXMBP_PROMCH_SHIFT (16) +#define EMAC_RXMBP_PROMCH_MASK (0x7 << 16) +#define EMAC_RXMBP_BROADEN_MASK BIT(13) +#define EMAC_RXMBP_BROADCH_SHIFT (8) +#define EMAC_RXMBP_BROADCH_MASK (0x7 << 8) +#define EMAC_RXMBP_MULTIEN_MASK BIT(5) +#define EMAC_RXMBP_MULTICH_SHIFT (0) +#define EMAC_RXMBP_MULTICH_MASK (0x7) +#define EMAC_RXMBP_CHMASK (0x7) /* EMAC register definitions/bit maps used */ -# define EMAC_MBP_RXPROMISC (0x00200000) -# define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16) -# define EMAC_MBP_RXBCAST (0x00002000) -# define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8) -# define EMAC_MBP_RXMCAST (0x00000020) -# define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7) +# define EMAC_MBP_RXPROMISC (0x00200000) +# define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16) +# define EMAC_MBP_RXBCAST (0x00002000) +# define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8) +# define EMAC_MBP_RXMCAST (0x00000020) +# define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7) /* EMAC mac_control register */ -#define EMAC_MACCONTROL_TXPTYPE BIT(9) -#define EMAC_MACCONTROL_TXPACEEN BIT(6) -#define EMAC_MACCONTROL_GMIIEN BIT(5) -#define EMAC_MACCONTROL_GIGABITEN BIT(7) -#define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0) -#define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15) +#define EMAC_MACCONTROL_TXPTYPE BIT(9) +#define EMAC_MACCONTROL_TXPACEEN BIT(6) +#define EMAC_MACCONTROL_GMIIEN BIT(5) +#define EMAC_MACCONTROL_GIGABITEN BIT(7) +#define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0) +#define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15) /* GIGABIT MODE related bits */ -#define EMAC_DM646X_MACCONTORL_GIG BIT(7) -#define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17) +#define EMAC_DM646X_MACCONTORL_GIG BIT(7) +#define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17) /* EMAC mac_status register */ -#define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000) -#define EMAC_MACSTATUS_TXERRCODE_SHIFT (20) -#define EMAC_MACSTATUS_TXERRCH_MASK (0x7) -#define EMAC_MACSTATUS_TXERRCH_SHIFT (16) -#define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000) -#define EMAC_MACSTATUS_RXERRCODE_SHIFT (12) -#define EMAC_MACSTATUS_RXERRCH_MASK (0x7) -#define EMAC_MACSTATUS_RXERRCH_SHIFT (8) +#define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000) +#define EMAC_MACSTATUS_TXERRCODE_SHIFT (20) +#define EMAC_MACSTATUS_TXERRCH_MASK (0x7) +#define EMAC_MACSTATUS_TXERRCH_SHIFT (16) +#define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000) +#define EMAC_MACSTATUS_RXERRCODE_SHIFT (12) +#define EMAC_MACSTATUS_RXERRCH_MASK (0x7) +#define EMAC_MACSTATUS_RXERRCH_SHIFT (8) /* EMAC RX register masks */ -#define EMAC_RX_MAX_LEN_MASK (0xFFFF) -#define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF) +#define EMAC_RX_MAX_LEN_MASK (0xFFFF) +#define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF) /* MAC_IN_VECTOR (0x180) register bit fields */ -#define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17) -#define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16) -#define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8) -#define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0) +#define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17) +#define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16) +#define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8) +#define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0) /** NOTE:: For DM646x the IN_VECTOR has changed */ -#define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH) -#define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH) -#define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26) -#define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27) +#define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH) +#define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH) +#define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26) +#define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27) /* CPPI bit positions */ -#define EMAC_CPPI_SOP_BIT BIT(31) -#define EMAC_CPPI_EOP_BIT BIT(30) -#define EMAC_CPPI_OWNERSHIP_BIT BIT(29) -#define EMAC_CPPI_EOQ_BIT BIT(28) +#define EMAC_CPPI_SOP_BIT BIT(31) +#define EMAC_CPPI_EOP_BIT BIT(30) +#define EMAC_CPPI_OWNERSHIP_BIT BIT(29) +#define EMAC_CPPI_EOQ_BIT BIT(28) #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27) -#define EMAC_CPPI_PASS_CRC_BIT BIT(26) -#define EMAC_RX_BD_BUF_SIZE (0xFFFF) -#define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */ -#define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF) +#define EMAC_CPPI_PASS_CRC_BIT BIT(26) +#define EMAC_RX_BD_BUF_SIZE (0xFFFF) +#define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */ +#define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF) /* Max hardware defines */ -#define EMAC_MAX_TXRX_CHANNELS (8) /* Max hardware channels */ +#define EMAC_MAX_TXRX_CHANNELS (8) /* Max hardware channels */ #define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */ /* EMAC Peripheral Device Register Memory Layout structure */ -#define EMAC_TXIDVER 0x0 -#define EMAC_TXCONTROL 0x4 -#define EMAC_TXTEARDOWN 0x8 -#define EMAC_RXIDVER 0x10 -#define EMAC_RXCONTROL 0x14 -#define EMAC_RXTEARDOWN 0x18 -#define EMAC_TXINTSTATRAW 0x80 -#define EMAC_TXINTSTATMASKED 0x84 -#define EMAC_TXINTMASKSET 0x88 -#define EMAC_TXINTMASKCLEAR 0x8C -#define EMAC_MACINVECTOR 0x90 +#define EMAC_TXIDVER 0x0 +#define EMAC_TXCONTROL 0x4 +#define EMAC_TXTEARDOWN 0x8 +#define EMAC_RXIDVER 0x10 +#define EMAC_RXCONTROL 0x14 +#define EMAC_RXTEARDOWN 0x18 +#define EMAC_TXINTSTATRAW 0x80 +#define EMAC_TXINTSTATMASKED 0x84 +#define EMAC_TXINTMASKSET 0x88 +#define EMAC_TXINTMASKCLEAR 0x8C +#define EMAC_MACINVECTOR 0x90 -#define EMAC_DM646X_MACEOIVECTOR 0x94 +#define EMAC_DM646X_MACEOIVECTOR 0x94 -#define EMAC_RXINTSTATRAW 0xA0 -#define EMAC_RXINTSTATMASKED 0xA4 -#define EMAC_RXINTMASKSET 0xA8 -#define EMAC_RXINTMASKCLEAR 0xAC -#define EMAC_MACINTSTATRAW 0xB0 -#define EMAC_MACINTSTATMASKED 0xB4 -#define EMAC_MACINTMASKSET 0xB8 -#define EMAC_MACINTMASKCLEAR 0xBC +#define EMAC_RXINTSTATRAW 0xA0 +#define EMAC_RXINTSTATMASKED 0xA4 +#define EMAC_RXINTMASKSET 0xA8 +#define EMAC_RXINTMASKCLEAR 0xAC +#define EMAC_MACINTSTATRAW 0xB0 +#define EMAC_MACINTSTATMASKED 0xB4 +#define EMAC_MACINTMASKSET 0xB8 +#define EMAC_MACINTMASKCLEAR 0xBC -#define EMAC_RXMBPENABLE 0x100 -#define EMAC_RXUNICASTSET 0x104 -#define EMAC_RXUNICASTCLEAR 0x108 -#define EMAC_RXMAXLEN 0x10C -#define EMAC_RXBUFFEROFFSET 0x110 -#define EMAC_RXFILTERLOWTHRESH 0x114 +#define EMAC_RXMBPENABLE 0x100 +#define EMAC_RXUNICASTSET 0x104 +#define EMAC_RXUNICASTCLEAR 0x108 +#define EMAC_RXMAXLEN 0x10C +#define EMAC_RXBUFFEROFFSET 0x110 +#define EMAC_RXFILTERLOWTHRESH 0x114 -#define EMAC_MACCONTROL 0x160 -#define EMAC_MACSTATUS 0x164 -#define EMAC_EMCONTROL 0x168 -#define EMAC_FIFOCONTROL 0x16C -#define EMAC_MACCONFIG 0x170 -#define EMAC_SOFTRESET 0x174 -#define EMAC_MACSRCADDRLO 0x1D0 -#define EMAC_MACSRCADDRHI 0x1D4 -#define EMAC_MACHASH1 0x1D8 -#define EMAC_MACHASH2 0x1DC -#define EMAC_MACADDRLO 0x500 -#define EMAC_MACADDRHI 0x504 -#define EMAC_MACINDEX 0x508 +#define EMAC_MACCONTROL 0x160 +#define EMAC_MACSTATUS 0x164 +#define EMAC_EMCONTROL 0x168 +#define EMAC_FIFOCONTROL 0x16C +#define EMAC_MACCONFIG 0x170 +#define EMAC_SOFTRESET 0x174 +#define EMAC_MACSRCADDRLO 0x1D0 +#define EMAC_MACSRCADDRHI 0x1D4 +#define EMAC_MACHASH1 0x1D8 +#define EMAC_MACHASH2 0x1DC +#define EMAC_MACADDRLO 0x500 +#define EMAC_MACADDRHI 0x504 +#define EMAC_MACINDEX 0x508 /* EMAC HDP and Completion registors */ -#define EMAC_TXHDP(ch) (0x600 + (ch * 4)) -#define EMAC_RXHDP(ch) (0x620 + (ch * 4)) -#define EMAC_TXCP(ch) (0x640 + (ch * 4)) -#define EMAC_RXCP(ch) (0x660 + (ch * 4)) +#define EMAC_TXHDP(ch) (0x600 + (ch * 4)) +#define EMAC_RXHDP(ch) (0x620 + (ch * 4)) +#define EMAC_TXCP(ch) (0x640 + (ch * 4)) +#define EMAC_RXCP(ch) (0x660 + (ch * 4)) /* EMAC statistics registers */ -#define EMAC_RXGOODFRAMES 0x200 -#define EMAC_RXBCASTFRAMES 0x204 -#define EMAC_RXMCASTFRAMES 0x208 -#define EMAC_RXPAUSEFRAMES 0x20C -#define EMAC_RXCRCERRORS 0x210 -#define EMAC_RXALIGNCODEERRORS 0x214 -#define EMAC_RXOVERSIZED 0x218 -#define EMAC_RXJABBER 0x21C -#define EMAC_RXUNDERSIZED 0x220 -#define EMAC_RXFRAGMENTS 0x224 -#define EMAC_RXFILTERED 0x228 -#define EMAC_RXQOSFILTERED 0x22C -#define EMAC_RXOCTETS 0x230 -#define EMAC_TXGOODFRAMES 0x234 -#define EMAC_TXBCASTFRAMES 0x238 -#define EMAC_TXMCASTFRAMES 0x23C -#define EMAC_TXPAUSEFRAMES 0x240 -#define EMAC_TXDEFERRED 0x244 -#define EMAC_TXCOLLISION 0x248 -#define EMAC_TXSINGLECOLL 0x24C -#define EMAC_TXMULTICOLL 0x250 -#define EMAC_TXEXCESSIVECOLL 0x254 -#define EMAC_TXLATECOLL 0x258 -#define EMAC_TXUNDERRUN 0x25C -#define EMAC_TXCARRIERSENSE 0x260 -#define EMAC_TXOCTETS 0x264 -#define EMAC_NETOCTETS 0x280 -#define EMAC_RXSOFOVERRUNS 0x284 -#define EMAC_RXMOFOVERRUNS 0x288 -#define EMAC_RXDMAOVERRUNS 0x28C +#define EMAC_RXGOODFRAMES 0x200 +#define EMAC_RXBCASTFRAMES 0x204 +#define EMAC_RXMCASTFRAMES 0x208 +#define EMAC_RXPAUSEFRAMES 0x20C +#define EMAC_RXCRCERRORS 0x210 +#define EMAC_RXALIGNCODEERRORS 0x214 +#define EMAC_RXOVERSIZED 0x218 +#define EMAC_RXJABBER 0x21C +#define EMAC_RXUNDERSIZED 0x220 +#define EMAC_RXFRAGMENTS 0x224 +#define EMAC_RXFILTERED 0x228 +#define EMAC_RXQOSFILTERED 0x22C +#define EMAC_RXOCTETS 0x230 +#define EMAC_TXGOODFRAMES 0x234 +#define EMAC_TXBCASTFRAMES 0x238 +#define EMAC_TXMCASTFRAMES 0x23C +#define EMAC_TXPAUSEFRAMES 0x240 +#define EMAC_TXDEFERRED 0x244 +#define EMAC_TXCOLLISION 0x248 +#define EMAC_TXSINGLECOLL 0x24C +#define EMAC_TXMULTICOLL 0x250 +#define EMAC_TXEXCESSIVECOLL 0x254 +#define EMAC_TXLATECOLL 0x258 +#define EMAC_TXUNDERRUN 0x25C +#define EMAC_TXCARRIERSENSE 0x260 +#define EMAC_TXOCTETS 0x264 +#define EMAC_NETOCTETS 0x280 +#define EMAC_RXSOFOVERRUNS 0x284 +#define EMAC_RXMOFOVERRUNS 0x288 +#define EMAC_RXDMAOVERRUNS 0x28C /* EMAC DM644x control registers */ -#define EMAC_CTRL_EWCTL (0x4) -#define EMAC_CTRL_EWINTTCNT (0x8) +#define EMAC_CTRL_EWCTL (0x4) +#define EMAC_CTRL_EWINTTCNT (0x8) /* EMAC MDIO related */ /* Mask & Control defines */ -#define MDIO_CONTROL_CLKDIV (0xFF) -#define MDIO_CONTROL_ENABLE BIT(30) -#define MDIO_USERACCESS_GO BIT(31) -#define MDIO_USERACCESS_WRITE BIT(30) -#define MDIO_USERACCESS_READ (0) -#define MDIO_USERACCESS_REGADR (0x1F << 21) -#define MDIO_USERACCESS_PHYADR (0x1F << 16) -#define MDIO_USERACCESS_DATA (0xFFFF) -#define MDIO_USERPHYSEL_LINKSEL BIT(7) -#define MDIO_VER_MODID (0xFFFF << 16) -#define MDIO_VER_REVMAJ (0xFF << 8) -#define MDIO_VER_REVMIN (0xFF) +#define MDIO_CONTROL_CLKDIV (0xFF) +#define MDIO_CONTROL_ENABLE BIT(30) +#define MDIO_USERACCESS_GO BIT(31) +#define MDIO_USERACCESS_WRITE BIT(30) +#define MDIO_USERACCESS_READ (0) +#define MDIO_USERACCESS_REGADR (0x1F << 21) +#define MDIO_USERACCESS_PHYADR (0x1F << 16) +#define MDIO_USERACCESS_DATA (0xFFFF) +#define MDIO_USERPHYSEL_LINKSEL BIT(7) +#define MDIO_VER_MODID (0xFFFF << 16) +#define MDIO_VER_REVMAJ (0xFF << 8) +#define MDIO_VER_REVMIN (0xFF) -#define MDIO_USERACCESS(inst) (0x80 + (inst * 8)) -#define MDIO_USERPHYSEL(inst) (0x84 + (inst * 8)) -#define MDIO_CONTROL (0x04) +#define MDIO_USERACCESS(inst) (0x80 + (inst * 8)) +#define MDIO_USERPHYSEL(inst) (0x84 + (inst * 8)) +#define MDIO_CONTROL (0x04) /* EMAC DM646X control module registers */ -#define EMAC_DM646X_CMRXINTEN (0x14) -#define EMAC_DM646X_CMTXINTEN (0x18) +#define EMAC_DM646X_CMRXINTEN (0x14) +#define EMAC_DM646X_CMTXINTEN (0x18) /* EMAC EOI codes for C0 */ -#define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01) -#define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02) +#define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01) +#define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02) /* EMAC Stats Clear Mask */ #define EMAC_STATS_CLR_MASK (0xFFFFFFFF) @@ -283,9 +269,9 @@ enum { * EMAC network buffer data structure */ struct emac_netbufobj { - void *buf_token; - char *data_ptr; - int length; + void *buf_token; + char *data_ptr; + int length; }; /** net_pkt_obj: EMAC network packet data structure @@ -293,10 +279,10 @@ struct emac_netbufobj { * EMAC network packet data structure - supports buffer list (for future) */ struct emac_netpktobj { - void *pkt_token; /* data token may hold tx/rx chan id */ - struct emac_netbufobj *buf_list; /* array of network buffer objects */ - int num_bufs; - int pkt_length; + void *pkt_token; /* data token may hold tx/rx chan id */ + struct emac_netbufobj *buf_list; /* array of network buffer objects */ + int num_bufs; + int pkt_length; }; /** emac_tx_bd: EMAC TX Buffer descriptor data structure @@ -304,12 +290,12 @@ struct emac_netpktobj { * EMAC TX Buffer descriptor data structure */ struct emac_tx_bd { - int h_next; - int buff_ptr; - int off_b_len; - int mode; /* SOP, EOP, ownership, EOQ, teardown,Qstarv, length */ - struct emac_tx_bd __iomem *next; - void *buf_token; + int h_next; + int buff_ptr; + int off_b_len; + int mode; /* SOP, EOP, ownership, EOQ, teardown,Qstarv, length */ + struct emac_tx_bd __iomem *next; + void *buf_token; }; /** emac_txch: EMAC TX Channel data structure @@ -317,29 +303,29 @@ struct emac_tx_bd { * EMAC TX Channel data structure */ struct emac_txch { - /* Config related */ - rt_uint32_t num_bd; - rt_uint32_t service_max; + /* Config related */ + rt_uint32_t num_bd; + rt_uint32_t service_max; - /* CPPI specific */ - rt_uint32_t alloc_size; - void __iomem *bd_mem; - struct emac_tx_bd __iomem *bd_pool_head; - struct emac_tx_bd __iomem *active_queue_head; - struct emac_tx_bd __iomem *active_queue_tail; - struct emac_tx_bd __iomem *last_hw_bdprocessed; - rt_uint32_t queue_active; - rt_uint32_t teardown_pending; - rt_uint32_t *tx_complete; + /* CPPI specific */ + rt_uint32_t alloc_size; + void __iomem *bd_mem; + struct emac_tx_bd __iomem *bd_pool_head; + struct emac_tx_bd __iomem *active_queue_head; + struct emac_tx_bd __iomem *active_queue_tail; + struct emac_tx_bd __iomem *last_hw_bdprocessed; + rt_uint32_t queue_active; + rt_uint32_t teardown_pending; + rt_uint32_t *tx_complete; - /** statistics */ - rt_uint32_t proc_count; /* TX: # of times emac_tx_bdproc is called */ - rt_uint32_t mis_queued_packets; - rt_uint32_t queue_reinit; - rt_uint32_t end_of_queue_add; - rt_uint32_t out_of_tx_bd; - rt_uint32_t no_active_pkts; /* IRQ when there were no packets to process */ - rt_uint32_t active_queue_count; + /** statistics */ + rt_uint32_t proc_count; /* TX: # of times emac_tx_bdproc is called */ + rt_uint32_t mis_queued_packets; + rt_uint32_t queue_reinit; + rt_uint32_t end_of_queue_add; + rt_uint32_t out_of_tx_bd; + rt_uint32_t no_active_pkts; /* IRQ when there were no packets to process */ + rt_uint32_t active_queue_count; }; /** emac_rx_bd: EMAC RX Buffer descriptor data structure @@ -347,13 +333,13 @@ struct emac_txch { * EMAC RX Buffer descriptor data structure */ struct emac_rx_bd { - int h_next; - int buff_ptr; - int off_b_len; - int mode; - struct emac_rx_bd __iomem *next; - void *data_ptr; - void *buf_token; + int h_next; + int buff_ptr; + int off_b_len; + int mode; + struct emac_rx_bd __iomem *next; + void *data_ptr; + void *buf_token; }; /** emac_rxch: EMAC RX Channel data structure @@ -361,68 +347,68 @@ struct emac_rx_bd { * EMAC RX Channel data structure */ struct emac_rxch { - /* configuration info */ - rt_uint32_t num_bd; - rt_uint32_t service_max; - rt_uint32_t buf_size; - char mac_addr[6]; + /* configuration info */ + rt_uint32_t num_bd; + rt_uint32_t service_max; + rt_uint32_t buf_size; + char mac_addr[6]; - /** CPPI specific */ - rt_uint32_t alloc_size; - void __iomem *bd_mem; - struct emac_rx_bd __iomem *bd_pool_head; - struct emac_rx_bd __iomem *active_queue_head; - struct emac_rx_bd __iomem *active_queue_tail; - rt_uint32_t queue_active; - rt_uint32_t teardown_pending; + /** CPPI specific */ + rt_uint32_t alloc_size; + void __iomem *bd_mem; + struct emac_rx_bd __iomem *bd_pool_head; + struct emac_rx_bd __iomem *active_queue_head; + struct emac_rx_bd __iomem *active_queue_tail; + rt_uint32_t queue_active; + rt_uint32_t teardown_pending; - /* packet and buffer objects */ - struct emac_netpktobj pkt_queue; - struct emac_netbufobj buf_queue; + /* packet and buffer objects */ + struct emac_netpktobj pkt_queue; + struct emac_netbufobj buf_queue; - /** statistics */ - rt_uint32_t proc_count; /* number of times emac_rx_bdproc is called */ - rt_uint32_t processed_bd; - rt_uint32_t recycled_bd; - rt_uint32_t out_of_rx_bd; - rt_uint32_t out_of_rx_buffers; - rt_uint32_t queue_reinit; - rt_uint32_t end_of_queue_add; - rt_uint32_t end_of_queue; - rt_uint32_t mis_queued_packets; + /** statistics */ + rt_uint32_t proc_count; /* number of times emac_rx_bdproc is called */ + rt_uint32_t processed_bd; + rt_uint32_t recycled_bd; + rt_uint32_t out_of_rx_bd; + rt_uint32_t out_of_rx_buffers; + rt_uint32_t queue_reinit; + rt_uint32_t end_of_queue_add; + rt_uint32_t end_of_queue; + rt_uint32_t mis_queued_packets; }; struct net_device_stats { - unsigned long rx_packets; /* total packets received */ - unsigned long tx_packets; /* total packets transmitted */ - unsigned long rx_bytes; /* total bytes received */ - unsigned long tx_bytes; /* total bytes transmitted */ - unsigned long rx_errors; /* bad packets received */ - unsigned long tx_errors; /* packet transmit problems */ - unsigned long rx_dropped; /* no space in linux buffers */ - unsigned long tx_dropped; /* no space available in linux */ - unsigned long multicast; /* multicast packets received */ - unsigned long collisions; + unsigned long rx_packets; /* total packets received */ + unsigned long tx_packets; /* total packets transmitted */ + unsigned long rx_bytes; /* total bytes received */ + unsigned long tx_bytes; /* total bytes transmitted */ + unsigned long rx_errors; /* bad packets received */ + unsigned long tx_errors; /* packet transmit problems */ + unsigned long rx_dropped; /* no space in linux buffers */ + unsigned long tx_dropped; /* no space available in linux */ + unsigned long multicast; /* multicast packets received */ + unsigned long collisions; - /* detailed rx_errors: */ - unsigned long rx_length_errors; - unsigned long rx_over_errors; /* receiver ring buff overflow */ - unsigned long rx_crc_errors; /* recved pkt with crc error */ - unsigned long rx_frame_errors; /* recv'd frame alignment error */ - unsigned long rx_fifo_errors; /* recv'r fifo overrun */ - unsigned long rx_missed_errors; /* receiver missed packet */ + /* detailed rx_errors: */ + unsigned long rx_length_errors; + unsigned long rx_over_errors; /* receiver ring buff overflow */ + unsigned long rx_crc_errors; /* recved pkt with crc error */ + unsigned long rx_frame_errors; /* recv'd frame alignment error */ + unsigned long rx_fifo_errors; /* recv'r fifo overrun */ + unsigned long rx_missed_errors; /* receiver missed packet */ - /* detailed tx_errors */ - unsigned long tx_aborted_errors; - unsigned long tx_carrier_errors; - unsigned long tx_fifo_errors; - unsigned long tx_heartbeat_errors; - unsigned long tx_window_errors; - - /* for cslip etc */ - unsigned long rx_compressed; - unsigned long tx_compressed; + /* detailed tx_errors */ + unsigned long tx_aborted_errors; + unsigned long tx_carrier_errors; + unsigned long tx_fifo_errors; + unsigned long tx_heartbeat_errors; + unsigned long tx_window_errors; + + /* for cslip etc */ + unsigned long rx_compressed; + unsigned long tx_compressed; }; @@ -433,44 +419,44 @@ struct net_device_stats #define MAX_ADDR_LEN 6 struct emac_priv { - /* inherit from ethernet device */ - struct eth_device parent; + /* inherit from ethernet device */ + struct eth_device parent; - /* interface address info. */ - rt_uint8_t mac_addr[MAX_ADDR_LEN]; /* hw address */ - unsigned short phy_addr; - - struct rt_semaphore tx_lock; - struct rt_semaphore rx_lock; - void __iomem *remap_addr; - rt_uint32_t emac_base_phys; - void __iomem *emac_base; - void __iomem *ctrl_base; - void __iomem *emac_ctrl_ram; - void __iomem *mdio_base; - rt_uint32_t ctrl_ram_size; - rt_uint32_t hw_ram_addr; - struct emac_txch *txch[EMAC_DEF_MAX_TX_CH]; - struct emac_rxch *rxch[EMAC_DEF_MAX_RX_CH]; - rt_uint32_t link; /* 1=link on, 0=link off */ - rt_uint32_t speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */ - rt_uint32_t duplex; /* Link duplex: 0=Half, 1=Full */ - rt_uint32_t rx_buf_size; - rt_uint32_t isr_count; - rt_uint8_t rmii_en; - rt_uint8_t version; - struct net_device_stats net_dev_stats; - rt_uint32_t mac_hash1; - rt_uint32_t mac_hash2; - rt_uint32_t multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS]; - rt_uint32_t rx_addr_type; - /* periodic timer required for MDIO polling */ - struct rt_timer timer; - rt_uint32_t periodic_ticks; - rt_uint32_t timer_active; - rt_uint32_t phy_mask; - /* mii_bus,phy members */ - struct rt_semaphore lock; + /* interface address info. */ + rt_uint8_t mac_addr[MAX_ADDR_LEN]; /* hw address */ + unsigned short phy_addr; + + struct rt_semaphore tx_lock; + struct rt_semaphore rx_lock; + void __iomem *remap_addr; + rt_uint32_t emac_base_phys; + void __iomem *emac_base; + void __iomem *ctrl_base; + void __iomem *emac_ctrl_ram; + void __iomem *mdio_base; + rt_uint32_t ctrl_ram_size; + rt_uint32_t hw_ram_addr; + struct emac_txch *txch[EMAC_DEF_MAX_TX_CH]; + struct emac_rxch *rxch[EMAC_DEF_MAX_RX_CH]; + rt_uint32_t link; /* 1=link on, 0=link off */ + rt_uint32_t speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */ + rt_uint32_t duplex; /* Link duplex: 0=Half, 1=Full */ + rt_uint32_t rx_buf_size; + rt_uint32_t isr_count; + rt_uint8_t rmii_en; + rt_uint8_t version; + struct net_device_stats net_dev_stats; + rt_uint32_t mac_hash1; + rt_uint32_t mac_hash2; + rt_uint32_t multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS]; + rt_uint32_t rx_addr_type; + /* periodic timer required for MDIO polling */ + struct rt_timer timer; + rt_uint32_t periodic_ticks; + rt_uint32_t timer_active; + rt_uint32_t phy_mask; + /* mii_bus,phy members */ + struct rt_semaphore lock; }; diff --git a/bsp/dm365/drivers/davinci_serial.c b/bsp/dm365/drivers/davinci_serial.c index 0671cb4e49..96118ac347 100644 --- a/bsp/dm365/drivers/davinci_serial.c +++ b/bsp/dm365/drivers/davinci_serial.c @@ -1,25 +1,11 @@ /* - * File : davinci_serial.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version + * Date Author Notes + * 2011-01-13 weety first version */ #include @@ -32,35 +18,35 @@ static struct rt_serial_device davinci_serial_dev0; static struct rt_serial_device davinci_serial_dev1; -#define LSR_DR 0x01 /* Data ready */ -#define LSR_THRE 0x20 /* Xmit holding register empty */ -//#define USTAT_TXB_EMPTY 0x02 /* tx buffer empty */ -#define BPS 115200 /* serial baudrate */ +#define LSR_DR 0x01 /* Data ready */ +#define LSR_THRE 0x20 /* Xmit holding register empty */ +//#define USTAT_TXB_EMPTY 0x02 /* tx buffer empty */ +#define BPS 115200 /* serial baudrate */ typedef struct uartport { - volatile rt_uint32_t rbr; - volatile rt_uint32_t ier; - volatile rt_uint32_t fcr; - volatile rt_uint32_t lcr; - volatile rt_uint32_t mcr; - volatile rt_uint32_t lsr; - volatile rt_uint32_t msr; - volatile rt_uint32_t scr; - volatile rt_uint32_t dll; - volatile rt_uint32_t dlh; - - volatile rt_uint32_t res[2]; - volatile rt_uint32_t pwremu_mgmt; - volatile rt_uint32_t mdr; + volatile rt_uint32_t rbr; + volatile rt_uint32_t ier; + volatile rt_uint32_t fcr; + volatile rt_uint32_t lcr; + volatile rt_uint32_t mcr; + volatile rt_uint32_t lsr; + volatile rt_uint32_t msr; + volatile rt_uint32_t scr; + volatile rt_uint32_t dll; + volatile rt_uint32_t dlh; + + volatile rt_uint32_t res[2]; + volatile rt_uint32_t pwremu_mgmt; + volatile rt_uint32_t mdr; }uartport; #define thr rbr #define iir fcr -#define UART0 ((struct uartport *)DAVINCI_UART0_BASE) +#define UART0 ((struct uartport *)DAVINCI_UART0_BASE) -#define UART1 ((struct uartport *)DM365_UART1_BASE) +#define UART1 ((struct uartport *)DM365_UART1_BASE) /** @@ -68,8 +54,8 @@ typedef struct uartport */ void rt_davinci_serial_handler(int vector, void *param) { - struct rt_serial_device *dev = (struct rt_serial_device *)param; - rt_hw_serial_isr(dev, RT_SERIAL_EVENT_RX_IND); + struct rt_serial_device *dev = (struct rt_serial_device *)param; + rt_hw_serial_isr(dev, RT_SERIAL_EVENT_RX_IND); } /** @@ -84,23 +70,23 @@ static rt_err_t davinci_uart_configure(struct rt_serial_device *serial, static rt_err_t davinci_uart_control(struct rt_serial_device *serial, int cmd, void *arg) { - uartport *uart = serial->parent.user_data; + uartport *uart = serial->parent.user_data; switch (cmd) { case RT_DEVICE_CTRL_CLR_INT: /* disable rx irq */ - if (uart == UART0) - rt_hw_interrupt_mask(IRQ_UARTINT0); - else if (uart == UART1) - rt_hw_interrupt_mask(IRQ_UARTINT1); + if (uart == UART0) + rt_hw_interrupt_mask(IRQ_UARTINT0); + else if (uart == UART1) + rt_hw_interrupt_mask(IRQ_UARTINT1); break; case RT_DEVICE_CTRL_SET_INT: /* enable rx irq */ - if (uart == UART0) - rt_hw_interrupt_umask(IRQ_UARTINT0); - else if (uart == UART1) - rt_hw_interrupt_umask(IRQ_UARTINT1); + if (uart == UART0) + rt_hw_interrupt_umask(IRQ_UARTINT0); + else if (uart == UART1) + rt_hw_interrupt_umask(IRQ_UARTINT1); break; } @@ -110,10 +96,10 @@ static rt_err_t davinci_uart_control(struct rt_serial_device *serial, static int davinci_uart_putc(struct rt_serial_device *serial, char c) { rt_uint32_t level; - uartport *uart = serial->parent.user_data; + uartport *uart = serial->parent.user_data; while (!(uart->lsr & LSR_THRE)); - uart->thr = c; + uart->thr = c; return 1; } @@ -121,16 +107,16 @@ static int davinci_uart_putc(struct rt_serial_device *serial, char c) static int davinci_uart_getc(struct rt_serial_device *serial) { int result; - uartport *uart = serial->parent.user_data; + uartport *uart = serial->parent.user_data; if (uart->lsr & LSR_DR) - { - result = uart->rbr & 0xff; - } - else - { - result = -1; - } + { + result = uart->rbr & 0xff; + } + else + { + result = -1; + } return result; } @@ -145,78 +131,78 @@ static const struct rt_uart_ops davinci_uart_ops = void davinci_uart0_init(void) { - rt_uint32_t divisor; + rt_uint32_t divisor; - divisor = (24000000 + (115200 * (16 / 2))) / (16 * 115200); - UART0->ier = 0; - UART0->lcr = 0x83; //8N1 - UART0->dll = 0; - UART0->dlh = 0; - UART0->lcr = 0x03; - UART0->mcr = 0x03; //RTS,CTS - UART0->fcr = 0x07; //FIFO - UART0->lcr = 0x83; - UART0->dll = divisor & 0xff; - UART0->dlh = (divisor >> 8) & 0xff; - UART0->lcr = 0x03; - UART0->mdr = 0; //16x over-sampling - UART0->pwremu_mgmt = 0x6000; - rt_hw_interrupt_install(IRQ_UARTINT0, rt_davinci_serial_handler, - (void *)&davinci_serial_dev0, "UART0"); - rt_hw_interrupt_mask(IRQ_UARTINT0); - UART0->ier = 0x05; + divisor = (24000000 + (115200 * (16 / 2))) / (16 * 115200); + UART0->ier = 0; + UART0->lcr = 0x83; //8N1 + UART0->dll = 0; + UART0->dlh = 0; + UART0->lcr = 0x03; + UART0->mcr = 0x03; //RTS,CTS + UART0->fcr = 0x07; //FIFO + UART0->lcr = 0x83; + UART0->dll = divisor & 0xff; + UART0->dlh = (divisor >> 8) & 0xff; + UART0->lcr = 0x03; + UART0->mdr = 0; //16x over-sampling + UART0->pwremu_mgmt = 0x6000; + rt_hw_interrupt_install(IRQ_UARTINT0, rt_davinci_serial_handler, + (void *)&davinci_serial_dev0, "UART0"); + rt_hw_interrupt_mask(IRQ_UARTINT0); + UART0->ier = 0x05; } void davinci_uart_gpio_init() { - rt_uint32_t val; + rt_uint32_t val; - val = davinci_readl(PINMUX3); - val &= 0xf3ffffff; /* gio23 RS485_CTRL */ - val |= 0x60000000; /*UART1_TXD (gio25)*/ - davinci_writel(val, PINMUX3); - val = davinci_readl(PINMUX4); - val |= 0x0000c000; /* UART1_RXD (gio34) */ - davinci_writel(val, PINMUX4); + val = davinci_readl(PINMUX3); + val &= 0xf3ffffff; /* gio23 RS485_CTRL */ + val |= 0x60000000; /*UART1_TXD (gio25)*/ + davinci_writel(val, PINMUX3); + val = davinci_readl(PINMUX4); + val |= 0x0000c000; /* UART1_RXD (gio34) */ + davinci_writel(val, PINMUX4); - val = davinci_readl(DAVINCI_GPIO_BASE + 0x10); - val &= ~(1 << 23); - davinci_writel(val, DAVINCI_GPIO_BASE + 0x10); - davinci_writel((1<<23), DAVINCI_GPIO_BASE + 0x1C); + val = davinci_readl(DAVINCI_GPIO_BASE + 0x10); + val &= ~(1 << 23); + davinci_writel(val, DAVINCI_GPIO_BASE + 0x10); + davinci_writel((1<<23), DAVINCI_GPIO_BASE + 0x1C); } void davinci_uart1_init(void) { - rt_uint32_t divisor; - rt_uint32_t freq; - rt_uint32_t baudrate; - struct clk *clk; + rt_uint32_t divisor; + rt_uint32_t freq; + rt_uint32_t baudrate; + struct clk *clk; - davinci_uart_gpio_init(); - psc_change_state(DAVINCI_DM365_LPSC_UART1, PSC_ENABLE); - clk = clk_get("UART1"); - freq = clk_get_rate(clk); + davinci_uart_gpio_init(); + psc_change_state(DAVINCI_DM365_LPSC_UART1, PSC_ENABLE); + clk = clk_get("UART1"); + freq = clk_get_rate(clk); - baudrate = 9600; - divisor = (freq + (baudrate * (16 / 2))) / (16 * baudrate); - UART1->ier = 0; - UART1->lcr = 0x87; //8N2, 0x83 8N1 - UART1->dll = 0; - UART1->dlh = 0; - UART1->lcr = 0x07; - UART1->mcr = 0x03; //RTS,CTS - UART1->fcr = 0x07; //FIFO - UART1->lcr = 0x87; - UART1->dll = divisor & 0xff; - UART1->dlh = (divisor >> 8) & 0xff; - UART1->lcr = 0x07; - UART1->mdr = 0; //16x over-sampling - UART1->pwremu_mgmt = 0x6000; - - rt_hw_interrupt_install(IRQ_UARTINT1, rt_davinci_serial_handler, - (void *)&davinci_serial_dev1, "UART1"); - rt_hw_interrupt_mask(IRQ_UARTINT1); - UART1->ier = 0x05; + baudrate = 9600; + divisor = (freq + (baudrate * (16 / 2))) / (16 * baudrate); + UART1->ier = 0; + UART1->lcr = 0x87; //8N2, 0x83 8N1 + UART1->dll = 0; + UART1->dlh = 0; + UART1->lcr = 0x07; + UART1->mcr = 0x03; //RTS,CTS + UART1->fcr = 0x07; //FIFO + UART1->lcr = 0x87; + UART1->dll = divisor & 0xff; + UART1->dlh = (divisor >> 8) & 0xff; + UART1->lcr = 0x07; + UART1->mdr = 0; //16x over-sampling + UART1->pwremu_mgmt = 0x6000; + + rt_hw_interrupt_install(IRQ_UARTINT1, rt_davinci_serial_handler, + (void *)&davinci_serial_dev1, "UART1"); + rt_hw_interrupt_mask(IRQ_UARTINT1); + UART1->ier = 0x05; } @@ -225,39 +211,39 @@ void davinci_uart1_init(void) */ int rt_hw_uart_init(void) { - davinci_serial_dev0.ops = &davinci_uart_ops; + davinci_serial_dev0.ops = &davinci_uart_ops; //davinci_serial_dev0.config = RT_SERIAL_CONFIG_DEFAULT; - davinci_serial_dev0.config.baud_rate = BAUD_RATE_115200; + davinci_serial_dev0.config.baud_rate = BAUD_RATE_115200; davinci_serial_dev0.config.bit_order = BIT_ORDER_LSB; davinci_serial_dev0.config.data_bits = DATA_BITS_8; davinci_serial_dev0.config.parity = PARITY_NONE; davinci_serial_dev0.config.stop_bits = STOP_BITS_1; davinci_serial_dev0.config.invert = NRZ_NORMAL; - davinci_serial_dev0.config.bufsz = RT_SERIAL_RB_BUFSZ; + davinci_serial_dev0.config.bufsz = RT_SERIAL_RB_BUFSZ; /* register vcom device */ rt_hw_serial_register(&davinci_serial_dev0, "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, UART0); - davinci_uart0_init(); + davinci_uart0_init(); - davinci_serial_dev1.ops = &davinci_uart_ops; + davinci_serial_dev1.ops = &davinci_uart_ops; //davinci_serial_dev1.config = RT_SERIAL_CONFIG_DEFAULT; - davinci_serial_dev1.config.baud_rate = BAUD_RATE_115200; + davinci_serial_dev1.config.baud_rate = BAUD_RATE_115200; davinci_serial_dev1.config.bit_order = BIT_ORDER_LSB; davinci_serial_dev1.config.data_bits = DATA_BITS_8; davinci_serial_dev1.config.parity = PARITY_NONE; davinci_serial_dev1.config.stop_bits = STOP_BITS_1; davinci_serial_dev1.config.invert = NRZ_NORMAL; - davinci_serial_dev1.config.bufsz = RT_SERIAL_RB_BUFSZ; + davinci_serial_dev1.config.bufsz = RT_SERIAL_RB_BUFSZ; /* register vcom device */ rt_hw_serial_register(&davinci_serial_dev1, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, UART1); - davinci_uart1_init(); + davinci_uart1_init(); - return 0; + return 0; } INIT_BOARD_EXPORT(rt_hw_uart_init); diff --git a/bsp/dm365/drivers/gpio.c b/bsp/dm365/drivers/gpio.c index 6c1f6b05e1..b226c736c8 100644 --- a/bsp/dm365/drivers/gpio.c +++ b/bsp/dm365/drivers/gpio.c @@ -1,176 +1,162 @@ /* - * File : gpio.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version + * Date Author Notes + * 2011-01-13 weety first version */ #include #include "gpio.h" -#define GPIO0_BASE (DAVINCI_GPIO_BASE + 0x10) -#define GPIO1_BASE (DAVINCI_GPIO_BASE + 0x38) -#define GPIO2_BASE (DAVINCI_GPIO_BASE + 0x60) -#define GPIO3_BASE (DAVINCI_GPIO_BASE + 0x88) +#define GPIO0_BASE (DAVINCI_GPIO_BASE + 0x10) +#define GPIO1_BASE (DAVINCI_GPIO_BASE + 0x38) +#define GPIO2_BASE (DAVINCI_GPIO_BASE + 0x60) +#define GPIO3_BASE (DAVINCI_GPIO_BASE + 0x88) static unsigned int dm365_gpio_base = (unsigned int)GPIO0_BASE; -#define GPIO_OE (dm365_gpio_base + 0x00) -#define GPIO_DATAIN (dm365_gpio_base + 0x10) -#define GPIO_DATAOUT (dm365_gpio_base + 0x04) -#define GPIO_CLROUT (dm365_gpio_base + 0x0C) -#define GPIO_SETOUT (dm365_gpio_base + 0x08) +#define GPIO_OE (dm365_gpio_base + 0x00) +#define GPIO_DATAIN (dm365_gpio_base + 0x10) +#define GPIO_DATAOUT (dm365_gpio_base + 0x04) +#define GPIO_CLROUT (dm365_gpio_base + 0x0C) +#define GPIO_SETOUT (dm365_gpio_base + 0x08) -#define gpio_dirin(n) *(volatile unsigned int *)((GPIO_OE)) |= 1<<(n) -#define gpio_dirout(n) *(volatile unsigned int *)((GPIO_OE)) &= ~(1u<<(n)) -#define gpio_set(n) *(volatile unsigned int *)((GPIO_SETOUT)) = 1<<(n) -#define gpio_clr(n) *(volatile unsigned int *)((GPIO_CLROUT)) = 1<<(n) -#define gpio_get(n) ( ( *(volatile unsigned int *)((GPIO_DATAIN)) & (1<<(n)) ) ? 1 : 0 ) +#define gpio_dirin(n) *(volatile unsigned int *)((GPIO_OE)) |= 1<<(n) +#define gpio_dirout(n) *(volatile unsigned int *)((GPIO_OE)) &= ~(1u<<(n)) +#define gpio_set(n) *(volatile unsigned int *)((GPIO_SETOUT)) = 1<<(n) +#define gpio_clr(n) *(volatile unsigned int *)((GPIO_CLROUT)) = 1<<(n) +#define gpio_get(n) ( ( *(volatile unsigned int *)((GPIO_DATAIN)) & (1<<(n)) ) ? 1 : 0 ) #define GPIO_GRP_MASK (5) - + static int gpio_to_base(unsigned int gpio) { - unsigned int grp_idx; - int ret; + unsigned int grp_idx; + int ret; - grp_idx = gpio >> GPIO_GRP_MASK; + grp_idx = gpio >> GPIO_GRP_MASK; - switch (grp_idx) { - case 0: - dm365_gpio_base = (unsigned int)GPIO0_BASE; - ret = 0; - break; - case 1: - dm365_gpio_base = (unsigned int)GPIO1_BASE; - ret = 0; - break; - case 2: - dm365_gpio_base = (unsigned int)GPIO2_BASE; - ret = 0; - break; - case 3: - dm365_gpio_base = (unsigned int)GPIO3_BASE; - ret = 0; - break; - default: - ret =-RT_EIO; - break; - } - return ret; + switch (grp_idx) { + case 0: + dm365_gpio_base = (unsigned int)GPIO0_BASE; + ret = 0; + break; + case 1: + dm365_gpio_base = (unsigned int)GPIO1_BASE; + ret = 0; + break; + case 2: + dm365_gpio_base = (unsigned int)GPIO2_BASE; + ret = 0; + break; + case 3: + dm365_gpio_base = (unsigned int)GPIO3_BASE; + ret = 0; + break; + default: + ret =-RT_EIO; + break; + } + return ret; } int gpio_direction_input(unsigned int gpio) { - unsigned int offset; - int ret=0; + unsigned int offset; + int ret=0; - rt_ubase_t temp = rt_hw_interrupt_disable(); - ret = gpio_to_base(gpio); - if (ret < 0) { - goto gpio_free; - } - offset = gpio & ((1 << GPIO_GRP_MASK) -1); + rt_ubase_t temp = rt_hw_interrupt_disable(); + ret = gpio_to_base(gpio); + if (ret < 0) { + goto gpio_free; + } + offset = gpio & ((1 << GPIO_GRP_MASK) -1); - gpio_dirin(offset); + gpio_dirin(offset); gpio_free: - rt_hw_interrupt_enable(temp); + rt_hw_interrupt_enable(temp); - return ret; + return ret; } int gpio_direction_output(unsigned int gpio, int value) { - unsigned int offset; - int ret=0; + unsigned int offset; + int ret=0; - rt_ubase_t temp = rt_hw_interrupt_disable(); - ret = gpio_to_base(gpio); - if (ret < 0) { - goto gpio_free; - } + rt_ubase_t temp = rt_hw_interrupt_disable(); + ret = gpio_to_base(gpio); + if (ret < 0) { + goto gpio_free; + } - offset = gpio & ((1 << GPIO_GRP_MASK) -1); + offset = gpio & ((1 << GPIO_GRP_MASK) -1); - if (value) { - gpio_set(offset); - } - else { - gpio_clr(offset); - } + if (value) { + gpio_set(offset); + } + else { + gpio_clr(offset); + } - gpio_dirout(offset); + gpio_dirout(offset); gpio_free: - rt_hw_interrupt_enable(temp); + rt_hw_interrupt_enable(temp); - return ret; + return ret; } int gpio_set_value(unsigned int gpio, int value) { - unsigned int offset; - int ret=0; + unsigned int offset; + int ret=0; - rt_ubase_t temp = rt_hw_interrupt_disable(); - ret = gpio_to_base(gpio); - if (ret < 0) { - goto gpio_free; - } + rt_ubase_t temp = rt_hw_interrupt_disable(); + ret = gpio_to_base(gpio); + if (ret < 0) { + goto gpio_free; + } - offset = gpio & ((1 << GPIO_GRP_MASK) -1); + offset = gpio & ((1 << GPIO_GRP_MASK) -1); - if (value) { - gpio_set(offset); - } - else { - gpio_clr(offset); - } + if (value) { + gpio_set(offset); + } + else { + gpio_clr(offset); + } gpio_free: - rt_hw_interrupt_enable(temp); + rt_hw_interrupt_enable(temp); - return ret; + return ret; } int gpio_get_value(unsigned int gpio) { - unsigned int offset; - int ret=0; + unsigned int offset; + int ret=0; - rt_ubase_t temp = rt_hw_interrupt_disable(); - ret = gpio_to_base(gpio); - if (ret < 0) { - goto gpio_free; - } + rt_ubase_t temp = rt_hw_interrupt_disable(); + ret = gpio_to_base(gpio); + if (ret < 0) { + goto gpio_free; + } - offset = gpio & ((1 << GPIO_GRP_MASK) -1); - ret = gpio_get(offset); + offset = gpio & ((1 << GPIO_GRP_MASK) -1); + ret = gpio_get(offset); gpio_free: - rt_hw_interrupt_enable(temp); + rt_hw_interrupt_enable(temp); - return ret; + return ret; } diff --git a/bsp/dm365/drivers/gpio.h b/bsp/dm365/drivers/gpio.h index c40798ed22..a6c8265648 100644 --- a/bsp/dm365/drivers/gpio.h +++ b/bsp/dm365/drivers/gpio.h @@ -1,51 +1,37 @@ /* - * File : gpio.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version + * Date Author Notes + * 2011-01-13 weety first version */ -#ifndef __DM365_GPIO_H -#define __DM365_GPIO_H +#ifndef __DM365_GPIO_H +#define __DM365_GPIO_H #include -#define GPIO(X) (X) +#define GPIO(X) (X) -#define get_io(r) *((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r))) -#define set_io(r,v) *((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r))) = (v) -#define and_io(r,v) *((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r))) &= (v) -#define or_io(r,v) *((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r))) |= (v) +#define get_io(r) *((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r))) +#define set_io(r,v) *((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r))) = (v) +#define and_io(r,v) *((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r))) &= (v) +#define or_io(r,v) *((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r))) |= (v) -#define v_get_io(r) *((volatile u_int *)(r)) -#define v_set_io(r,v) *((volatile u_int *)(r)) = (v) -#define v_and_io(r,v) *((volatile u_int *)(r)) &= (v) -#define v_or_io(r,v) *((volatile u_int *)(r)) |= (v) +#define v_get_io(r) *((volatile u_int *)(r)) +#define v_set_io(r,v) *((volatile u_int *)(r)) = (v) +#define v_and_io(r,v) *((volatile u_int *)(r)) &= (v) +#define v_or_io(r,v) *((volatile u_int *)(r)) |= (v) enum gpio_intr_mode { LEVELDETECT_LOW = 0, LEVELDETECT_HIGH, - RISINGDETECT, + RISINGDETECT, FALLINGDETECT, - EDGEDETECT //both rising-edge and falling-edge detect + EDGEDETECT //both rising-edge and falling-edge detect }; enum gpio_intr_req @@ -56,10 +42,10 @@ enum gpio_intr_req enum gpio_intr_num { - GPIOINT0A = 96, - GPIOINT0B, - GPIOINT1A, - GPIOINT1B, + GPIOINT0A = 96, + GPIOINT0B, + GPIOINT1A, + GPIOINT1B, }; enum pin_func_mod @@ -70,4 +56,4 @@ enum pin_func_mod IIC_MOD=0x20 }; -#endif /* __TI814X_GPIO_H */ +#endif /* __TI814X_GPIO_H */ diff --git a/bsp/dm365/drivers/i2c-davinci.c b/bsp/dm365/drivers/i2c-davinci.c index c1d8a07ba4..6da4e72d6c 100644 --- a/bsp/dm365/drivers/i2c-davinci.c +++ b/bsp/dm365/drivers/i2c-davinci.c @@ -1,25 +1,11 @@ /* - * File : i2c-davinci.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version + * Date Author Notes + * 2011-01-13 weety first version */ #include @@ -27,61 +13,61 @@ #include /* ----- global defines ----------------------------------------------- */ -#define BIT(nr) (1UL << (nr)) +#define BIT(nr) (1UL << (nr)) -#define DAVINCI_I2C_TIMEOUT (1*RT_TICK_PER_SECOND) -#define DAVINCI_I2C_MAX_TRIES 2 +#define DAVINCI_I2C_TIMEOUT (1*RT_TICK_PER_SECOND) +#define DAVINCI_I2C_MAX_TRIES 2 #define I2C_DAVINCI_INTR_ALL (DAVINCI_I2C_IMR_AAS | \ - DAVINCI_I2C_IMR_SCD | \ - DAVINCI_I2C_IMR_ARDY | \ - DAVINCI_I2C_IMR_NACK | \ - DAVINCI_I2C_IMR_AL) + DAVINCI_I2C_IMR_SCD | \ + DAVINCI_I2C_IMR_ARDY | \ + DAVINCI_I2C_IMR_NACK | \ + DAVINCI_I2C_IMR_AL) -#define DAVINCI_I2C_OAR_REG 0x00 -#define DAVINCI_I2C_IMR_REG 0x04 -#define DAVINCI_I2C_STR_REG 0x08 -#define DAVINCI_I2C_CLKL_REG 0x0c -#define DAVINCI_I2C_CLKH_REG 0x10 -#define DAVINCI_I2C_CNT_REG 0x14 -#define DAVINCI_I2C_DRR_REG 0x18 -#define DAVINCI_I2C_SAR_REG 0x1c -#define DAVINCI_I2C_DXR_REG 0x20 -#define DAVINCI_I2C_MDR_REG 0x24 -#define DAVINCI_I2C_IVR_REG 0x28 -#define DAVINCI_I2C_EMDR_REG 0x2c -#define DAVINCI_I2C_PSC_REG 0x30 +#define DAVINCI_I2C_OAR_REG 0x00 +#define DAVINCI_I2C_IMR_REG 0x04 +#define DAVINCI_I2C_STR_REG 0x08 +#define DAVINCI_I2C_CLKL_REG 0x0c +#define DAVINCI_I2C_CLKH_REG 0x10 +#define DAVINCI_I2C_CNT_REG 0x14 +#define DAVINCI_I2C_DRR_REG 0x18 +#define DAVINCI_I2C_SAR_REG 0x1c +#define DAVINCI_I2C_DXR_REG 0x20 +#define DAVINCI_I2C_MDR_REG 0x24 +#define DAVINCI_I2C_IVR_REG 0x28 +#define DAVINCI_I2C_EMDR_REG 0x2c +#define DAVINCI_I2C_PSC_REG 0x30 -#define DAVINCI_I2C_IVR_AAS 0x07 -#define DAVINCI_I2C_IVR_SCD 0x06 -#define DAVINCI_I2C_IVR_XRDY 0x05 -#define DAVINCI_I2C_IVR_RDR 0x04 -#define DAVINCI_I2C_IVR_ARDY 0x03 -#define DAVINCI_I2C_IVR_NACK 0x02 -#define DAVINCI_I2C_IVR_AL 0x01 +#define DAVINCI_I2C_IVR_AAS 0x07 +#define DAVINCI_I2C_IVR_SCD 0x06 +#define DAVINCI_I2C_IVR_XRDY 0x05 +#define DAVINCI_I2C_IVR_RDR 0x04 +#define DAVINCI_I2C_IVR_ARDY 0x03 +#define DAVINCI_I2C_IVR_NACK 0x02 +#define DAVINCI_I2C_IVR_AL 0x01 -#define DAVINCI_I2C_STR_BB BIT(12) -#define DAVINCI_I2C_STR_RSFULL BIT(11) -#define DAVINCI_I2C_STR_SCD BIT(5) -#define DAVINCI_I2C_STR_ARDY BIT(2) -#define DAVINCI_I2C_STR_NACK BIT(1) -#define DAVINCI_I2C_STR_AL BIT(0) +#define DAVINCI_I2C_STR_BB BIT(12) +#define DAVINCI_I2C_STR_RSFULL BIT(11) +#define DAVINCI_I2C_STR_SCD BIT(5) +#define DAVINCI_I2C_STR_ARDY BIT(2) +#define DAVINCI_I2C_STR_NACK BIT(1) +#define DAVINCI_I2C_STR_AL BIT(0) -#define DAVINCI_I2C_MDR_NACK BIT(15) -#define DAVINCI_I2C_MDR_STT BIT(13) -#define DAVINCI_I2C_MDR_STP BIT(11) -#define DAVINCI_I2C_MDR_MST BIT(10) -#define DAVINCI_I2C_MDR_TRX BIT(9) -#define DAVINCI_I2C_MDR_XA BIT(8) -#define DAVINCI_I2C_MDR_RM BIT(7) -#define DAVINCI_I2C_MDR_IRS BIT(5) +#define DAVINCI_I2C_MDR_NACK BIT(15) +#define DAVINCI_I2C_MDR_STT BIT(13) +#define DAVINCI_I2C_MDR_STP BIT(11) +#define DAVINCI_I2C_MDR_MST BIT(10) +#define DAVINCI_I2C_MDR_TRX BIT(9) +#define DAVINCI_I2C_MDR_XA BIT(8) +#define DAVINCI_I2C_MDR_RM BIT(7) +#define DAVINCI_I2C_MDR_IRS BIT(5) -#define DAVINCI_I2C_IMR_AAS BIT(6) -#define DAVINCI_I2C_IMR_SCD BIT(5) -#define DAVINCI_I2C_IMR_XRDY BIT(4) -#define DAVINCI_I2C_IMR_RRDY BIT(3) -#define DAVINCI_I2C_IMR_ARDY BIT(2) -#define DAVINCI_I2C_IMR_NACK BIT(1) -#define DAVINCI_I2C_IMR_AL BIT(0) +#define DAVINCI_I2C_IMR_AAS BIT(6) +#define DAVINCI_I2C_IMR_SCD BIT(5) +#define DAVINCI_I2C_IMR_XRDY BIT(4) +#define DAVINCI_I2C_IMR_RRDY BIT(3) +#define DAVINCI_I2C_IMR_ARDY BIT(2) +#define DAVINCI_I2C_IMR_NACK BIT(1) +#define DAVINCI_I2C_IMR_AL BIT(0) #ifdef RT_EDMA_DEBUG #define i2c_dbg(fmt, ...) rt_kprintf(fmt, ##__VA_ARGS__) @@ -91,42 +77,42 @@ struct davinci_i2c_dev { - void *base; - struct rt_semaphore completion; - struct clk *clk; - int cmd_err; - rt_uint8_t *buf; - rt_uint32_t buf_len; - int irq; - int stop; - rt_uint8_t terminate; - rt_uint32_t bus_freq; - rt_uint32_t bus_delay; - struct rt_i2c_bus_device *bus; + void *base; + struct rt_semaphore completion; + struct clk *clk; + int cmd_err; + rt_uint8_t *buf; + rt_uint32_t buf_len; + int irq; + int stop; + rt_uint8_t terminate; + rt_uint32_t bus_freq; + rt_uint32_t bus_delay; + struct rt_i2c_bus_device *bus; }; static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev, - int reg, rt_uint16_t val) + int reg, rt_uint16_t val) { - davinci_writew(val, i2c_dev->base + reg); + davinci_writew(val, i2c_dev->base + reg); } static inline rt_uint16_t davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg) { - return davinci_readw(i2c_dev->base + reg); + return davinci_readw(i2c_dev->base + reg); } static void udelay (rt_uint32_t us) { - rt_int32_t i; - for (; us > 0; us--) - { - i = 50000; - while(i > 0) - { - i--; - } - } + rt_int32_t i; + for (; us > 0; us--) + { + i = 50000; + while(i > 0) + { + i--; + } + } } @@ -134,17 +120,17 @@ static void udelay (rt_uint32_t us) /* Generate a pulse on the i2c clock pin. */ static void generic_i2c_clock_pulse(unsigned int scl_pin) { - rt_uint16_t i; + rt_uint16_t i; - if (scl_pin) { - /* Send high and low on the SCL line */ - for (i = 0; i < 9; i++) { - gpio_set_value(scl_pin, 0); - udelay(20); - gpio_set_value(scl_pin, 1); - udelay(20); - } - } + if (scl_pin) { + /* Send high and low on the SCL line */ + for (i = 0; i < 9; i++) { + gpio_set_value(scl_pin, 0); + udelay(20); + gpio_set_value(scl_pin, 1); + udelay(20); + } + } } #endif @@ -153,78 +139,78 @@ static void generic_i2c_clock_pulse(unsigned int scl_pin) */ static void i2c_recover_bus(struct davinci_i2c_dev *dev) { - rt_uint32_t flag = 0; + rt_uint32_t flag = 0; - i2c_dbg("initiating i2c bus recovery\n"); - /* Send NACK to the slave */ - flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); - flag |= DAVINCI_I2C_MDR_NACK; - /* write the data into mode register */ - davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); + i2c_dbg("initiating i2c bus recovery\n"); + /* Send NACK to the slave */ + flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); + flag |= DAVINCI_I2C_MDR_NACK; + /* write the data into mode register */ + davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); #if 0 - if (pdata) - generic_i2c_clock_pulse(pdata->scl_pin); + if (pdata) + generic_i2c_clock_pulse(pdata->scl_pin); #endif - /* Send STOP */ - flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); - flag |= DAVINCI_I2C_MDR_STP; - davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); + /* Send STOP */ + flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); + flag |= DAVINCI_I2C_MDR_STP; + davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); } static inline void davinci_i2c_reset_ctrl(struct davinci_i2c_dev *i2c_dev, - int val) + int val) { - rt_uint16_t w; + rt_uint16_t w; - w = davinci_i2c_read_reg(i2c_dev, DAVINCI_I2C_MDR_REG); - if (!val) /* put I2C into reset */ - w &= ~DAVINCI_I2C_MDR_IRS; - else /* take I2C out of reset */ - w |= DAVINCI_I2C_MDR_IRS; + w = davinci_i2c_read_reg(i2c_dev, DAVINCI_I2C_MDR_REG); + if (!val) /* put I2C into reset */ + w &= ~DAVINCI_I2C_MDR_IRS; + else /* take I2C out of reset */ + w |= DAVINCI_I2C_MDR_IRS; - davinci_i2c_write_reg(i2c_dev, DAVINCI_I2C_MDR_REG, w); + davinci_i2c_write_reg(i2c_dev, DAVINCI_I2C_MDR_REG, w); } static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev) { - rt_uint16_t psc; - rt_uint32_t clk; - rt_uint32_t d; - rt_uint32_t clkh; - rt_uint32_t clkl; - rt_uint32_t input_clock = clk_get_rate(dev->clk); + rt_uint16_t psc; + rt_uint32_t clk; + rt_uint32_t d; + rt_uint32_t clkh; + rt_uint32_t clkl; + rt_uint32_t input_clock = clk_get_rate(dev->clk); - /* NOTE: I2C Clock divider programming info - * As per I2C specs the following formulas provide prescaler - * and low/high divider values - * input clk --> PSC Div -----------> ICCL/H Div --> output clock - * module clk - * - * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ] - * - * Thus, - * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d; - * - * where if PSC == 0, d = 7, - * if PSC == 1, d = 6 - * if PSC > 1 , d = 5 - */ + /* NOTE: I2C Clock divider programming info + * As per I2C specs the following formulas provide prescaler + * and low/high divider values + * input clk --> PSC Div -----------> ICCL/H Div --> output clock + * module clk + * + * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ] + * + * Thus, + * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d; + * + * where if PSC == 0, d = 7, + * if PSC == 1, d = 6 + * if PSC > 1 , d = 5 + */ - /* get minimum of 7 MHz clock, but max of 12 MHz */ - psc = (input_clock / 7000000) - 1; - if ((input_clock / (psc + 1)) > 12000000) - psc++; /* better to run under spec than over */ - d = (psc >= 2) ? 5 : 7 - psc; + /* get minimum of 7 MHz clock, but max of 12 MHz */ + psc = (input_clock / 7000000) - 1; + if ((input_clock / (psc + 1)) > 12000000) + psc++; /* better to run under spec than over */ + d = (psc >= 2) ? 5 : 7 - psc; - clk = ((input_clock / (psc + 1)) / (dev->bus_freq * 1000)) - (d << 1); - clkh = clk >> 1; - clkl = clk - clkh; + clk = ((input_clock / (psc + 1)) / (dev->bus_freq * 1000)) - (d << 1); + clkh = clk >> 1; + clkl = clk - clkh; - davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc); - davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh); - davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl); + davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc); + davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh); + davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl); - i2c_dbg("input_clock = %d, CLK = %d\n", input_clock, clk); + i2c_dbg("input_clock = %d, CLK = %d\n", input_clock, clk); } /* @@ -234,65 +220,65 @@ static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev) */ static int i2c_davinci_init(struct davinci_i2c_dev *dev) { - /* put I2C into reset */ - davinci_i2c_reset_ctrl(dev, 0); + /* put I2C into reset */ + davinci_i2c_reset_ctrl(dev, 0); - /* compute clock dividers */ - i2c_davinci_calc_clk_dividers(dev); + /* compute clock dividers */ + i2c_davinci_calc_clk_dividers(dev); - /* Respond at reserved "SMBus Host" slave address" (and zero); - * we seem to have no option to not respond... - */ - davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, 0x08); + /* Respond at reserved "SMBus Host" slave address" (and zero); + * we seem to have no option to not respond... + */ + davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, 0x08); - i2c_dbg("PSC = %d\n", - davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG)); - i2c_dbg("CLKL = %d\n", - davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG)); - i2c_dbg("CLKH = %d\n", - davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG)); - i2c_dbg("bus_freq = %dkHz, bus_delay = %d\n", - dev->bus_freq, dev->bus_delay); + i2c_dbg("PSC = %d\n", + davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG)); + i2c_dbg("CLKL = %d\n", + davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG)); + i2c_dbg("CLKH = %d\n", + davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG)); + i2c_dbg("bus_freq = %dkHz, bus_delay = %d\n", + dev->bus_freq, dev->bus_delay); - /* Take the I2C module out of reset: */ - davinci_i2c_reset_ctrl(dev, 1); + /* Take the I2C module out of reset: */ + davinci_i2c_reset_ctrl(dev, 1); - /* Enable interrupts */ - davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL); + /* Enable interrupts */ + davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL); - return 0; + return 0; } /* * Waiting for bus not busy */ static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev, - char allow_sleep) + char allow_sleep) { - unsigned long timeout; - static rt_uint16_t to_cnt; - RT_ASSERT(dev != RT_NULL); - RT_ASSERT(dev->bus != RT_NULL); + unsigned long timeout; + static rt_uint16_t to_cnt; + RT_ASSERT(dev != RT_NULL); + RT_ASSERT(dev->bus != RT_NULL); - timeout = rt_tick_get() + dev->bus->timeout; - while (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) - & DAVINCI_I2C_STR_BB) { - if (to_cnt <= DAVINCI_I2C_MAX_TRIES) { - if (rt_tick_get() >= timeout) { - rt_kprintf("timeout waiting for bus ready\n"); - to_cnt++; - return -RT_ETIMEOUT; - } else { - to_cnt = 0; - i2c_recover_bus(dev); - i2c_davinci_init(dev); - } - } - if (allow_sleep) - rt_thread_delay(2); - } + timeout = rt_tick_get() + dev->bus->timeout; + while (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) + & DAVINCI_I2C_STR_BB) { + if (to_cnt <= DAVINCI_I2C_MAX_TRIES) { + if (rt_tick_get() >= timeout) { + rt_kprintf("timeout waiting for bus ready\n"); + to_cnt++; + return -RT_ETIMEOUT; + } else { + to_cnt = 0; + i2c_recover_bus(dev); + i2c_davinci_init(dev); + } + } + if (allow_sleep) + rt_thread_delay(2); + } - return 0; + return 0; } /* @@ -302,125 +288,125 @@ static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev, static int i2c_davinci_xfer_msg(struct rt_i2c_bus_device *bus, struct rt_i2c_msg *msg, int stop) { - struct davinci_i2c_dev *dev = bus->priv; - rt_uint32_t flag; - rt_uint16_t w; - int r; + struct davinci_i2c_dev *dev = bus->priv; + rt_uint32_t flag; + rt_uint16_t w; + int r; - /* Introduce a delay, required for some boards (e.g Davinci EVM) */ - if (dev->bus_delay) - udelay(dev->bus_delay); + /* Introduce a delay, required for some boards (e.g Davinci EVM) */ + if (dev->bus_delay) + udelay(dev->bus_delay); - /* set the slave address */ - davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr); + /* set the slave address */ + davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr); - dev->buf = msg->buf; - dev->buf_len = msg->len; - dev->stop = stop; + dev->buf = msg->buf; + dev->buf_len = msg->len; + dev->stop = stop; - davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len); + davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len); - //INIT_COMPLETION(dev->cmd_complete); - dev->cmd_err = 0; + //INIT_COMPLETION(dev->cmd_complete); + dev->cmd_err = 0; - /* Take I2C out of reset and configure it as master */ - flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST; + /* Take I2C out of reset and configure it as master */ + flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST; - /* if the slave address is ten bit address, enable XA bit */ - if (msg->flags & RT_I2C_ADDR_10BIT) - flag |= DAVINCI_I2C_MDR_XA; - if (!(msg->flags & RT_I2C_RD)) - flag |= DAVINCI_I2C_MDR_TRX; - if (msg->len == 0) - flag |= DAVINCI_I2C_MDR_RM; + /* if the slave address is ten bit address, enable XA bit */ + if (msg->flags & RT_I2C_ADDR_10BIT) + flag |= DAVINCI_I2C_MDR_XA; + if (!(msg->flags & RT_I2C_RD)) + flag |= DAVINCI_I2C_MDR_TRX; + if (msg->len == 0) + flag |= DAVINCI_I2C_MDR_RM; - /* Enable receive or transmit interrupts */ - w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG); - if (msg->flags & RT_I2C_RD) - w |= DAVINCI_I2C_IMR_RRDY; - else - w |= DAVINCI_I2C_IMR_XRDY; - davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w); + /* Enable receive or transmit interrupts */ + w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG); + if (msg->flags & RT_I2C_RD) + w |= DAVINCI_I2C_IMR_RRDY; + else + w |= DAVINCI_I2C_IMR_XRDY; + davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w); - dev->terminate = 0; + dev->terminate = 0; - /* - * Write mode register first as needed for correct behaviour - * on OMAP-L138, but don't set STT yet to avoid a race with XRDY - * occurring before we have loaded DXR - */ - davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); + /* + * Write mode register first as needed for correct behaviour + * on OMAP-L138, but don't set STT yet to avoid a race with XRDY + * occurring before we have loaded DXR + */ + davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); - /* - * First byte should be set here, not after interrupt, - * because transmit-data-ready interrupt can come before - * NACK-interrupt during sending of previous message and - * ICDXR may have wrong data - * It also saves us one interrupt, slightly faster - */ - if ((!(msg->flags & RT_I2C_RD)) && dev->buf_len) - { - davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++); - dev->buf_len--; - } + /* + * First byte should be set here, not after interrupt, + * because transmit-data-ready interrupt can come before + * NACK-interrupt during sending of previous message and + * ICDXR may have wrong data + * It also saves us one interrupt, slightly faster + */ + if ((!(msg->flags & RT_I2C_RD)) && dev->buf_len) + { + davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++); + dev->buf_len--; + } - /* Set STT to begin transmit now DXR is loaded */ - flag |= DAVINCI_I2C_MDR_STT; - if (stop && msg->len != 0) - flag |= DAVINCI_I2C_MDR_STP; - davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); + /* Set STT to begin transmit now DXR is loaded */ + flag |= DAVINCI_I2C_MDR_STT; + if (stop && msg->len != 0) + flag |= DAVINCI_I2C_MDR_STP; + davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); - r = rt_sem_take(&dev->completion, dev->bus->timeout); - if (r == -RT_ETIMEOUT) - { - rt_kprintf("controller timed out\n"); - i2c_recover_bus(dev); - i2c_davinci_init(dev); - dev->buf_len = 0; - return -RT_ETIMEOUT; - } - if (dev->buf_len) - { - /* This should be 0 if all bytes were transferred - * or dev->cmd_err denotes an error. - * A signal may have aborted the transfer. - */ - if (r == RT_EOK) - { - rt_kprintf("abnormal termination buf_len=%i\n", - dev->buf_len); - r = -RT_EIO; - } - dev->terminate = 1; - dev->buf_len = 0; - } - if (r < 0) - return r; + r = rt_sem_take(&dev->completion, dev->bus->timeout); + if (r == -RT_ETIMEOUT) + { + rt_kprintf("controller timed out\n"); + i2c_recover_bus(dev); + i2c_davinci_init(dev); + dev->buf_len = 0; + return -RT_ETIMEOUT; + } + if (dev->buf_len) + { + /* This should be 0 if all bytes were transferred + * or dev->cmd_err denotes an error. + * A signal may have aborted the transfer. + */ + if (r == RT_EOK) + { + rt_kprintf("abnormal termination buf_len=%i\n", + dev->buf_len); + r = -RT_EIO; + } + dev->terminate = 1; + dev->buf_len = 0; + } + if (r < 0) + return r; - /* no error */ - if (!dev->cmd_err) - return msg->len; + /* no error */ + if (!dev->cmd_err) + return msg->len; - /* We have an error */ - if (dev->cmd_err & DAVINCI_I2C_STR_AL) - { - i2c_davinci_init(dev); - return -RT_EIO; - } + /* We have an error */ + if (dev->cmd_err & DAVINCI_I2C_STR_AL) + { + i2c_davinci_init(dev); + return -RT_EIO; + } - if (dev->cmd_err & DAVINCI_I2C_STR_NACK) - { - if (msg->flags & RT_I2C_IGNORE_NACK) - return msg->len; - if (stop) - { - w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); - w |= DAVINCI_I2C_MDR_STP; - davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); - } - return -RT_EIO; - } - return -RT_EIO; + if (dev->cmd_err & DAVINCI_I2C_STR_NACK) + { + if (msg->flags & RT_I2C_IGNORE_NACK) + return msg->len; + if (stop) + { + w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); + w |= DAVINCI_I2C_MDR_STP; + davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); + } + return -RT_EIO; + } + return -RT_EIO; } /* @@ -429,52 +415,52 @@ i2c_davinci_xfer_msg(struct rt_i2c_bus_device *bus, struct rt_i2c_msg *msg, int static int i2c_davinci_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], int num) { - struct davinci_i2c_dev *dev = bus->priv; - int i; - int ret; + struct davinci_i2c_dev *dev = bus->priv; + int i; + int ret; - i2c_dbg("%s: msgs: %d\n", __func__, num); + i2c_dbg("%s: msgs: %d\n", __func__, num); - ret = i2c_davinci_wait_bus_not_busy(dev, 1); - if (ret < 0) - { - i2c_dbg("timeout waiting for bus ready\n"); - return ret; - } + ret = i2c_davinci_wait_bus_not_busy(dev, 1); + if (ret < 0) + { + i2c_dbg("timeout waiting for bus ready\n"); + return ret; + } - for (i = 0; i < num; i++) - { - ret = i2c_davinci_xfer_msg(bus, &msgs[i], (i == (num - 1))); - i2c_dbg("%s [%d/%d] ret: %d\n", __func__, i + 1, num, - ret); - if (ret < 0) - return ret; - } + for (i = 0; i < num; i++) + { + ret = i2c_davinci_xfer_msg(bus, &msgs[i], (i == (num - 1))); + i2c_dbg("%s [%d/%d] ret: %d\n", __func__, i + 1, num, + ret); + if (ret < 0) + return ret; + } - return num; + return num; } static void terminate_read(struct davinci_i2c_dev *dev) { - rt_uint16_t w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); - w |= DAVINCI_I2C_MDR_NACK; - davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); + rt_uint16_t w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); + w |= DAVINCI_I2C_MDR_NACK; + davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); - /* Throw away data */ - davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG); - if (!dev->terminate) - rt_kprintf("RDR IRQ while no data requested\n"); + /* Throw away data */ + davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG); + if (!dev->terminate) + rt_kprintf("RDR IRQ while no data requested\n"); } static void terminate_write(struct davinci_i2c_dev *dev) { - rt_uint16_t w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); - w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP; - davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); + rt_uint16_t w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); + w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP; + davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); - if (!dev->terminate) - i2c_dbg("TDR IRQ while no data to send\n"); + if (!dev->terminate) + i2c_dbg("TDR IRQ while no data to send\n"); } /* @@ -483,173 +469,173 @@ static void terminate_write(struct davinci_i2c_dev *dev) */ static void i2c_davinci_isr(int irq, void *param) { - struct davinci_i2c_dev *dev = (struct davinci_i2c_dev *)param; - rt_uint32_t stat; - int count = 0; - rt_uint16_t w; + struct davinci_i2c_dev *dev = (struct davinci_i2c_dev *)param; + rt_uint32_t stat; + int count = 0; + rt_uint16_t w; - while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) { - i2c_dbg("%s: stat=0x%x\n", __func__, stat); - if (count++ == 100) { - rt_kprintf("Too much work in one IRQ\n"); - break; - } + while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) { + i2c_dbg("%s: stat=0x%x\n", __func__, stat); + if (count++ == 100) { + rt_kprintf("Too much work in one IRQ\n"); + break; + } - switch (stat) { - case DAVINCI_I2C_IVR_AL: - /* Arbitration lost, must retry */ - dev->cmd_err |= DAVINCI_I2C_STR_AL; - dev->buf_len = 0; - rt_sem_release(&dev->completion); - break; + switch (stat) { + case DAVINCI_I2C_IVR_AL: + /* Arbitration lost, must retry */ + dev->cmd_err |= DAVINCI_I2C_STR_AL; + dev->buf_len = 0; + rt_sem_release(&dev->completion); + break; - case DAVINCI_I2C_IVR_NACK: - dev->cmd_err |= DAVINCI_I2C_STR_NACK; - dev->buf_len = 0; - rt_sem_release(&dev->completion); - break; + case DAVINCI_I2C_IVR_NACK: + dev->cmd_err |= DAVINCI_I2C_STR_NACK; + dev->buf_len = 0; + rt_sem_release(&dev->completion); + break; - case DAVINCI_I2C_IVR_ARDY: - davinci_i2c_write_reg(dev, - DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY); - if (((dev->buf_len == 0) && (dev->stop != 0)) || - (dev->cmd_err & DAVINCI_I2C_STR_NACK)) { - w = davinci_i2c_read_reg(dev, - DAVINCI_I2C_MDR_REG); - w |= DAVINCI_I2C_MDR_STP; - davinci_i2c_write_reg(dev, - DAVINCI_I2C_MDR_REG, w); - } - rt_sem_release(&dev->completion); - break; + case DAVINCI_I2C_IVR_ARDY: + davinci_i2c_write_reg(dev, + DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY); + if (((dev->buf_len == 0) && (dev->stop != 0)) || + (dev->cmd_err & DAVINCI_I2C_STR_NACK)) { + w = davinci_i2c_read_reg(dev, + DAVINCI_I2C_MDR_REG); + w |= DAVINCI_I2C_MDR_STP; + davinci_i2c_write_reg(dev, + DAVINCI_I2C_MDR_REG, w); + } + rt_sem_release(&dev->completion); + break; - case DAVINCI_I2C_IVR_RDR: - if (dev->buf_len) { - *dev->buf++ = - davinci_i2c_read_reg(dev, - DAVINCI_I2C_DRR_REG); - dev->buf_len--; - if (dev->buf_len) - continue; + case DAVINCI_I2C_IVR_RDR: + if (dev->buf_len) { + *dev->buf++ = + davinci_i2c_read_reg(dev, + DAVINCI_I2C_DRR_REG); + dev->buf_len--; + if (dev->buf_len) + continue; - davinci_i2c_write_reg(dev, - DAVINCI_I2C_STR_REG, - DAVINCI_I2C_IMR_RRDY); - } else { - /* signal can terminate transfer */ - terminate_read(dev); - } - break; + davinci_i2c_write_reg(dev, + DAVINCI_I2C_STR_REG, + DAVINCI_I2C_IMR_RRDY); + } else { + /* signal can terminate transfer */ + terminate_read(dev); + } + break; - case DAVINCI_I2C_IVR_XRDY: - if (dev->buf_len) { - davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, - *dev->buf++); - dev->buf_len--; - if (dev->buf_len) - continue; + case DAVINCI_I2C_IVR_XRDY: + if (dev->buf_len) { + davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, + *dev->buf++); + dev->buf_len--; + if (dev->buf_len) + continue; - w = davinci_i2c_read_reg(dev, - DAVINCI_I2C_IMR_REG); - w &= ~DAVINCI_I2C_IMR_XRDY; - davinci_i2c_write_reg(dev, - DAVINCI_I2C_IMR_REG, - w); - } else { - /* signal can terminate transfer */ - terminate_write(dev); - } - break; + w = davinci_i2c_read_reg(dev, + DAVINCI_I2C_IMR_REG); + w &= ~DAVINCI_I2C_IMR_XRDY; + davinci_i2c_write_reg(dev, + DAVINCI_I2C_IMR_REG, + w); + } else { + /* signal can terminate transfer */ + terminate_write(dev); + } + break; - case DAVINCI_I2C_IVR_SCD: - davinci_i2c_write_reg(dev, - DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD); - rt_sem_release(&dev->completion); - break; + case DAVINCI_I2C_IVR_SCD: + davinci_i2c_write_reg(dev, + DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD); + rt_sem_release(&dev->completion); + break; - case DAVINCI_I2C_IVR_AAS: - i2c_dbg("Address as slave interrupt\n"); - break; + case DAVINCI_I2C_IVR_AAS: + i2c_dbg("Address as slave interrupt\n"); + break; - default: - i2c_dbg("Unrecognized irq stat %d\n", stat); - break; - } - } + default: + i2c_dbg("Unrecognized irq stat %d\n", stat); + break; + } + } } static struct rt_i2c_bus_device_ops bus_ops = { - .master_xfer = i2c_davinci_xfer, + .master_xfer = i2c_davinci_xfer, }; int davinci_i2c_init(char *bus_name) { - struct rt_i2c_bus_device *bus; - struct davinci_i2c_dev *dev; - int r; + struct rt_i2c_bus_device *bus; + struct davinci_i2c_dev *dev; + int r; - bus = rt_malloc(sizeof(struct rt_i2c_bus_device)); - if (bus == RT_NULL) - { - rt_kprintf("rt_malloc failed\n"); - return -RT_ENOMEM; - } - - rt_memset((void *)bus, 0, sizeof(struct rt_i2c_bus_device)); + bus = rt_malloc(sizeof(struct rt_i2c_bus_device)); + if (bus == RT_NULL) + { + rt_kprintf("rt_malloc failed\n"); + return -RT_ENOMEM; + } - bus->ops = &bus_ops; - bus->timeout = DAVINCI_I2C_TIMEOUT; + rt_memset((void *)bus, 0, sizeof(struct rt_i2c_bus_device)); - dev = rt_malloc(sizeof(struct davinci_i2c_dev)); - if (!dev) - { - r = -RT_ENOMEM; - goto err; - } + bus->ops = &bus_ops; + bus->timeout = DAVINCI_I2C_TIMEOUT; - rt_memset((void *)dev, 0, sizeof(struct davinci_i2c_dev)); + dev = rt_malloc(sizeof(struct davinci_i2c_dev)); + if (!dev) + { + r = -RT_ENOMEM; + goto err; + } - rt_sem_init(&dev->completion, "i2c_ack", 0, RT_IPC_FLAG_FIFO); + rt_memset((void *)dev, 0, sizeof(struct davinci_i2c_dev)); - dev->irq = IRQ_I2C; + rt_sem_init(&dev->completion, "i2c_ack", 0, RT_IPC_FLAG_FIFO); - dev->clk = clk_get("I2CCLK"); - if (dev->clk == RT_NULL) { - r = -RT_ERROR; - goto err1; - } + dev->irq = IRQ_I2C; - psc_change_state(DAVINCI_DM365_LPSC_I2C, 3); + dev->clk = clk_get("I2CCLK"); + if (dev->clk == RT_NULL) { + r = -RT_ERROR; + goto err1; + } - dev->base = DAVINCI_I2C_BASE; - dev->bus_freq = 100; - dev->bus_delay = 0; - dev->bus = bus; + psc_change_state(DAVINCI_DM365_LPSC_I2C, 3); - bus->priv = dev; + dev->base = DAVINCI_I2C_BASE; + dev->bus_freq = 100; + dev->bus_delay = 0; + dev->bus = bus; - i2c_davinci_init(dev); + bus->priv = dev; - rt_hw_interrupt_install(dev->irq, i2c_davinci_isr, (void *)dev, "I2C"); - rt_hw_interrupt_umask(dev->irq); + i2c_davinci_init(dev); - return rt_i2c_bus_device_register(bus, bus_name); + rt_hw_interrupt_install(dev->irq, i2c_davinci_isr, (void *)dev, "I2C"); + rt_hw_interrupt_umask(dev->irq); + + return rt_i2c_bus_device_register(bus, bus_name); err1: - rt_free(dev); + rt_free(dev); err: - rt_free(bus); + rt_free(bus); - return r; + return r; } int rt_hw_iic_init(void) { - davinci_i2c_init("I2C1"); + davinci_i2c_init("I2C1"); } INIT_DEVICE_EXPORT(rt_hw_iic_init); diff --git a/bsp/dm365/drivers/mii.h b/bsp/dm365/drivers/mii.h index de799bccce..8b42352bf4 100644 --- a/bsp/dm365/drivers/mii.h +++ b/bsp/dm365/drivers/mii.h @@ -1,25 +1,11 @@ /* - * File : mii.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-03-18 weety first version + * Date Author Notes + * 2011-03-18 weety first version */ @@ -37,7 +23,7 @@ #define MII_EXPANSION 0x06 /* Expansion register */ #define MII_CTRL1000 0x09 /* 1000BASE-T control */ #define MII_STAT1000 0x0a /* 1000BASE-T status */ -#define MII_ESTATUS 0x0f /* Extended Status */ +#define MII_ESTATUS 0x0f /* Extended Status */ #define MII_DCOUNTER 0x12 /* Disconnect counter */ #define MII_FCSCOUNTER 0x13 /* False carrier counter */ #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ @@ -52,7 +38,7 @@ /* Basic mode control register. */ #define BMCR_RESV 0x003f /* Unused... */ -#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ +#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ #define BMCR_CTST 0x0080 /* Collision test */ #define BMCR_FULLDPLX 0x0100 /* Full duplex */ #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ @@ -71,7 +57,7 @@ #define BMSR_RFAULT 0x0010 /* Remote fault detected */ #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ #define BMSR_RESV 0x00c0 /* Unused... */ -#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ +#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */ #define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */ #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ @@ -100,7 +86,7 @@ #define ADVERTISE_NPAGE 0x8000 /* Next page bit */ #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ - ADVERTISE_CSMA) + ADVERTISE_CSMA) #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ ADVERTISE_100HALF | ADVERTISE_100FULL) @@ -122,8 +108,8 @@ #define LPA_LPACK 0x4000 /* Link partner acked us */ #define LPA_NPAGE 0x8000 /* Next page bit */ -#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) -#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) +#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) +#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) /* Expansion register for auto-negotiation. */ #define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */ @@ -133,8 +119,8 @@ #define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */ #define EXPANSION_RESV 0xffe0 /* Unused... */ -#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ -#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ +#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ +#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ /* N-way test register. */ #define NWAYTEST_RESV1 0x00ff /* Unused... */ @@ -152,8 +138,8 @@ #define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */ /* Flow control flags */ -#define FLOW_CTRL_TX 0x01 -#define FLOW_CTRL_RX 0x02 +#define FLOW_CTRL_TX 0x01 +#define FLOW_CTRL_RX 0x02 /** * mii_nway_result @@ -188,11 +174,11 @@ rt_inline unsigned int mii_nway_result (unsigned int negotiated) } /* The forced speed, 10Mb, 100Mb, gigabit, 2.5Gb, 10GbE. */ -#define SPEED_10 10 -#define SPEED_100 100 -#define SPEED_1000 1000 -#define SPEED_2500 2500 -#define SPEED_10000 10000 +#define SPEED_10 10 +#define SPEED_100 100 +#define SPEED_1000 1000 +#define SPEED_2500 2500 +#define SPEED_10000 10000 #endif /* __MII_H__ */ diff --git a/bsp/dm365/drivers/mmcsd.c b/bsp/dm365/drivers/mmcsd.c index 00a1c045ea..8e12236256 100644 --- a/bsp/dm365/drivers/mmcsd.c +++ b/bsp/dm365/drivers/mmcsd.c @@ -1,25 +1,11 @@ /* - * File : mmcsd.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version + * Date Author Notes + * 2011-01-13 weety first version */ #include @@ -32,66 +18,66 @@ #define RT_USING_MMCSD0 -#define MMCSD_DEBUG 0 +#define MMCSD_DEBUG 0 #if MMCSD_DEBUG -#define mmc_dbg(fmt, ...) rt_kprintf(fmt, ##__VA_ARGS__) +#define mmc_dbg(fmt, ...) rt_kprintf(fmt, ##__VA_ARGS__) #else #define mmc_dbg(fmt, ...) #endif -#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<29)) -#define CACHE_LINE_SIZE 32 +#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<29)) +#define CACHE_LINE_SIZE 32 extern void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size); extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size); -#define EVT_QUEUE_NUM 0 /* EDMA3 Event queue number. */ +#define EVT_QUEUE_NUM 0 /* EDMA3 Event queue number. */ static unsigned rw_threshold = 32; static rt_bool_t use_dma = RT_TRUE; enum DATA_DIR_TYPE { - DM365_MMC_DATADIR_NONE = 0, - DM365_MMC_DATADIR_READ, - DM365_MMC_DATADIR_WRITE, + DM365_MMC_DATADIR_NONE = 0, + DM365_MMC_DATADIR_READ, + DM365_MMC_DATADIR_WRITE, }; -struct mmc_dm365_host +struct mmc_dm365_host { - struct rt_mmcsd_host *mmc; - struct rt_mmcsd_req *req; - struct rt_mmcsd_data *data; - struct rt_mmcsd_cmd *cmd; - struct edmacc_param tx_template; - struct edmacc_param rx_template; + struct rt_mmcsd_host *mmc; + struct rt_mmcsd_req *req; + struct rt_mmcsd_data *data; + struct rt_mmcsd_cmd *cmd; + struct edmacc_param tx_template; + struct edmacc_param rx_template; - rt_uint32_t mmc_input_clk; - rt_uint32_t ns_in_one_cycle; /* for ns in one cycle calculation */ + rt_uint32_t mmc_input_clk; + rt_uint32_t ns_in_one_cycle; /* for ns in one cycle calculation */ - mmcsd_regs_t *mmcsd_regs; - rt_uint8_t bus_mode; + mmcsd_regs_t *mmcsd_regs; + rt_uint8_t bus_mode; - enum DATA_DIR_TYPE data_dir; + enum DATA_DIR_TYPE data_dir; - rt_uint32_t rxdma; - rt_uint32_t txdma; - rt_bool_t use_dma; - rt_bool_t do_dma; + rt_uint32_t rxdma; + rt_uint32_t txdma; + rt_bool_t use_dma; + rt_bool_t do_dma; - rt_uint8_t *buffer; - rt_uint32_t buffer_bytes_left; - rt_uint32_t bytes_left; + rt_uint8_t *buffer; + rt_uint32_t buffer_bytes_left; + rt_uint32_t bytes_left; - rt_uint8_t *dma_buffer; - rt_bool_t use_dma_buffer; - rt_bool_t sdio_int; + rt_uint8_t *dma_buffer; + rt_bool_t use_dma_buffer; + rt_bool_t sdio_int; }; void *mmc_priv(struct rt_mmcsd_host *host) { - return (void *)host->private_data; + return (void *)host->private_data; } static void delay_us(rt_uint32_t us) @@ -102,1380 +88,1380 @@ static void delay_us(rt_uint32_t us) } /******************************************************************************************************* -** : calculate_freq_for_card() -** : ˺ڼSDƵķƵ -** -** 䡡: host -> DM365 MMC host -** mmc_req_freq -> MMCƵ +** 函数名称: calculate_freq_for_card() +** 功能描述: 此函数用于计算设置SD卡频率所需的分频数 ** -** 䡡: Ƶֵ -** -** ȫֱ: -** ģ: +** 输　入: host -> DM365 MMC host句柄 +** mmc_req_freq -> MMC工作频率 +** +** 输　出: 分频值 +** +** 全局变量: +** 调用模块: 无 ** ********************************************************************************************************/ static rt_uint32_t calculate_freq_for_card(struct mmc_dm365_host *host, rt_uint32_t mmc_req_freq) { - rt_uint32_t mmc_freq = 0; - rt_uint32_t mmc_pclk = 0; - rt_uint32_t mmc_push_pull_divisor = 0; + rt_uint32_t mmc_freq = 0; + rt_uint32_t mmc_pclk = 0; + rt_uint32_t mmc_push_pull_divisor = 0; - mmc_pclk = host->mmc_input_clk; - - if (mmc_req_freq && mmc_pclk > (2 * mmc_req_freq)) - mmc_push_pull_divisor = ((rt_uint32_t)mmc_pclk / (2 * mmc_req_freq)) - 1; - else - mmc_push_pull_divisor = 0; + mmc_pclk = host->mmc_input_clk; - mmc_freq = (rt_uint32_t)mmc_pclk / (2 * (mmc_push_pull_divisor + 1)); + if (mmc_req_freq && mmc_pclk > (2 * mmc_req_freq)) + mmc_push_pull_divisor = ((rt_uint32_t)mmc_pclk / (2 * mmc_req_freq)) - 1; + else + mmc_push_pull_divisor = 0; - if (mmc_freq > mmc_req_freq) - mmc_push_pull_divisor = mmc_push_pull_divisor + 1; - - /* Convert ns to clock cycles */ - if (mmc_req_freq <= 400000) - host->ns_in_one_cycle = (1000000)/(((mmc_pclk/(2*(mmc_push_pull_divisor+1)))/1000)); - else - host->ns_in_one_cycle = (1000000)/(((mmc_pclk/(2*(mmc_push_pull_divisor+1)))/1000000)); + mmc_freq = (rt_uint32_t)mmc_pclk / (2 * (mmc_push_pull_divisor + 1)); - return mmc_push_pull_divisor; + if (mmc_freq > mmc_req_freq) + mmc_push_pull_divisor = mmc_push_pull_divisor + 1; + + /* Convert ns to clock cycles */ + if (mmc_req_freq <= 400000) + host->ns_in_one_cycle = (1000000)/(((mmc_pclk/(2*(mmc_push_pull_divisor+1)))/1000)); + else + host->ns_in_one_cycle = (1000000)/(((mmc_pclk/(2*(mmc_push_pull_divisor+1)))/1000000)); + + return mmc_push_pull_divisor; } /******************************************************************************************************* -** : calculate_freq_for_card() -** : ˺ڼMMC clockƵ -** -** 䡡: host -> DM365 MMC host -** ios -> MMC +** 函数名称: calculate_freq_for_card() +** 功能描述: 此函数用于计算MMC clock分频数 ** -** 䡡: ȡPHYĴֵ -** -** ȫֱ: -** ģ: +** 输　入: host -> DM365 MMC host句柄 +** ios -> MMC 操作句柄 +** +** 输　出: 读取到的PHY寄存器值 +** +** 全局变量: +** 调用模块: 无 ** ********************************************************************************************************/ static void calculate_clk_divider(struct rt_mmcsd_host *mmc, struct rt_mmcsd_io_cfg *ios) { - rt_uint32_t temp = 0; - rt_uint32_t mmc_pclk = 0; - rt_uint32_t open_drain_freq = 0; - rt_uint32_t mmc_push_pull_freq = 0; - struct mmc_dm365_host *host = mmc_priv(mmc); + rt_uint32_t temp = 0; + rt_uint32_t mmc_pclk = 0; + rt_uint32_t open_drain_freq = 0; + rt_uint32_t mmc_push_pull_freq = 0; + struct mmc_dm365_host *host = mmc_priv(mmc); - mmc_pclk = host->mmc_input_clk; + mmc_pclk = host->mmc_input_clk; - if (ios->bus_mode == MMCSD_BUSMODE_OPENDRAIN) - { - /* Ignoring the init clock value passed for fixing the inter - * operability with different cards. - */ - open_drain_freq = ((rt_uint32_t)mmc_pclk / (2 * MMCSD_INIT_CLOCK)) - 1; + if (ios->bus_mode == MMCSD_BUSMODE_OPENDRAIN) + { + /* Ignoring the init clock value passed for fixing the inter + * operability with different cards. + */ + open_drain_freq = ((rt_uint32_t)mmc_pclk / (2 * MMCSD_INIT_CLOCK)) - 1; - if (open_drain_freq > 0xFF) - open_drain_freq = 0xFF; + if (open_drain_freq > 0xFF) + open_drain_freq = 0xFF; - temp = host->mmcsd_regs->MMCCLK & ~MMCCLK_CLKRT_MASK; - temp |= open_drain_freq; - host->mmcsd_regs->MMCCLK = temp; + temp = host->mmcsd_regs->MMCCLK & ~MMCCLK_CLKRT_MASK; + temp |= open_drain_freq; + host->mmcsd_regs->MMCCLK = temp; - - /* Convert ns to clock cycles */ - host->ns_in_one_cycle = (1000000) / (MMCSD_INIT_CLOCK / 1000); - } - else - { - mmc_push_pull_freq = calculate_freq_for_card(host, ios->clock); - if (mmc_push_pull_freq > 0xFF) - mmc_push_pull_freq = 0xFF; + /* Convert ns to clock cycles */ + host->ns_in_one_cycle = (1000000) / (MMCSD_INIT_CLOCK / 1000); + } + else + { + mmc_push_pull_freq = calculate_freq_for_card(host, ios->clock); - temp = host->mmcsd_regs->MMCCLK & ~MMCCLK_CLKEN; - host->mmcsd_regs->MMCCLK = temp; - - delay_us(10); + if (mmc_push_pull_freq > 0xFF) + mmc_push_pull_freq = 0xFF; - temp = host->mmcsd_regs->MMCCLK & ~MMCCLK_CLKRT_MASK; - temp |= mmc_push_pull_freq; - host->mmcsd_regs->MMCCLK = temp; - - host->mmcsd_regs->MMCCLK = temp | MMCCLK_CLKEN; + temp = host->mmcsd_regs->MMCCLK & ~MMCCLK_CLKEN; + host->mmcsd_regs->MMCCLK = temp; - delay_us(10); - } + delay_us(10); + + temp = host->mmcsd_regs->MMCCLK & ~MMCCLK_CLKRT_MASK; + temp |= mmc_push_pull_freq; + host->mmcsd_regs->MMCCLK = temp; + + host->mmcsd_regs->MMCCLK = temp | MMCCLK_CLKEN; + + delay_us(10); + } } /******************************************************************************************************* -** : mmc_dm365_set_ios() -** : ˺mmc -** -** 䡡: mmc -> mmc host -** ios -> mmc +** 函数名称: mmc_dm365_set_ios() +** 功能描述: 此函数是mmc设置设置 ** -** 䡡: -** -** ȫֱ: -** ģ: +** 输　入: mmc -> mmc host 句柄 +** ios -> mmc 操作句柄 +** +** 输　出: 无 +** +** 全局变量: +** 调用模块: 无 ** ********************************************************************************************************/ static void mmc_dm365_set_ios(struct rt_mmcsd_host *mmc, struct rt_mmcsd_io_cfg *ios) { - struct mmc_dm365_host *host = mmc_priv(mmc); + struct mmc_dm365_host *host = mmc_priv(mmc); - mmc_dbg("clock %dHz busmode %d powermode %d Vdd %04x\n", ios->clock, ios->bus_mode, ios->power_mode, ios->vdd); + mmc_dbg("clock %dHz busmode %d powermode %d Vdd %04x\n", ios->clock, ios->bus_mode, ios->power_mode, ios->vdd); - switch (ios->bus_width) + switch (ios->bus_width) { - case MMCSD_BUS_WIDTH_8: + case MMCSD_BUS_WIDTH_8: mmc_dbg("Enabling 8 bit mode\n"); - host->mmcsd_regs->MMCCTL = (host->mmcsd_regs->MMCCTL & ~MMCCTL_WIDTH_4_BIT) | MMCCTL_WIDTH_8_BIT; - break; - case MMCSD_BUS_WIDTH_4: + host->mmcsd_regs->MMCCTL = (host->mmcsd_regs->MMCCTL & ~MMCCTL_WIDTH_4_BIT) | MMCCTL_WIDTH_8_BIT; + break; + case MMCSD_BUS_WIDTH_4: mmc_dbg("Enabling 4 bit mode\n"); - host->mmcsd_regs->MMCCTL = (host->mmcsd_regs->MMCCTL & ~MMCCTL_WIDTH_8_BIT) | MMCCTL_WIDTH_4_BIT; - break; - case MMCSD_BUS_WIDTH_1: + host->mmcsd_regs->MMCCTL = (host->mmcsd_regs->MMCCTL & ~MMCCTL_WIDTH_8_BIT) | MMCCTL_WIDTH_4_BIT; + break; + case MMCSD_BUS_WIDTH_1: mmc_dbg("Enabling 1 bit mode\n"); - host->mmcsd_regs->MMCCTL = host->mmcsd_regs->MMCCTL & ~(MMCCTL_WIDTH_8_BIT | MMCCTL_WIDTH_4_BIT); - break; - } + host->mmcsd_regs->MMCCTL = host->mmcsd_regs->MMCCTL & ~(MMCCTL_WIDTH_8_BIT | MMCCTL_WIDTH_4_BIT); + break; + } - calculate_clk_divider(mmc, ios); + calculate_clk_divider(mmc, ios); - host->bus_mode = ios->bus_mode; - if (ios->power_mode == MMCSD_POWER_UP) + host->bus_mode = ios->bus_mode; + if (ios->power_mode == MMCSD_POWER_UP) { - unsigned long timeout = rt_tick_get() + 500; - rt_bool_t lose = 1; + unsigned long timeout = rt_tick_get() + 500; + rt_bool_t lose = 1; - host->mmcsd_regs->MMCARGHL = 0; - host->mmcsd_regs->MMCCMD = MMCCMD_INITCK; - - while (rt_tick_get() < timeout) - { - rt_uint32_t tmp = host->mmcsd_regs->MMCST0; + host->mmcsd_regs->MMCARGHL = 0; + host->mmcsd_regs->MMCCMD = MMCCMD_INITCK; - if (tmp & MMCST0_RSPDNE) - { - lose = 0; - break; - } - } - if (lose) - mmc_dbg("powerup timeout\n"); - } + while (rt_tick_get() < timeout) + { + rt_uint32_t tmp = host->mmcsd_regs->MMCST0; + + if (tmp & MMCST0_RSPDNE) + { + lose = 0; + break; + } + } + if (lose) + mmc_dbg("powerup timeout\n"); + } } /******************************************************************************************************* -** : dm365_fifo_data_trans() -** : ˺fifoģʽ -** -** 䡡: host -> DM365 mmc host -** n -> ֽ +** 函数名称: dm365_fifo_data_trans() +** 功能描述: 此函数是fifo模式传输 ** -** 䡡: -** -** ȫֱ: -** ģ: +** 输　入: host -> DM365 mmc host 句柄 +** n -> 传输字节数 +** +** 输　出: 无 +** +** 全局变量: +** 调用模块: 无 ** ********************************************************************************************************/ static void dm365_fifo_data_trans(struct mmc_dm365_host *host, rt_uint32_t n) { - rt_uint8_t *p; - rt_uint32_t i; + rt_uint8_t *p; + rt_uint32_t i; - p = host->buffer; + p = host->buffer; - if (host->bytes_left < n) - n = host->bytes_left; - - host->bytes_left -= n; + if (host->bytes_left < n) + n = host->bytes_left; - /* NOTE: we never transfer more than rw_threshold bytes - * to/from the fifo here; there's no I/O overlap. - * This also assumes that access width( i.e. ACCWD) is 4 bytes - */ - if (host->data_dir == DM365_MMC_DATADIR_WRITE) - { - for (i = 0; i < (n >> 2); i++) - { - host->mmcsd_regs->MMCDXR = *((rt_uint32_t *)p); - p = p + 4; - } - if (n & 3) - { - rt_kprintf("to do ... \n"); -// iowrite8_rep(host->base + MMCSD_MMCDXR, p, (n & 3)); - p = p + (n & 3); - } - } - else - { - for (i = 0; i < (n >> 2); i++) - { - *((rt_uint32_t *)p) = host->mmcsd_regs->MMCDRR; - p = p + 4; - } - if (n & 3) - { + host->bytes_left -= n; + + /* NOTE: we never transfer more than rw_threshold bytes + * to/from the fifo here; there's no I/O overlap. + * This also assumes that access width( i.e. ACCWD) is 4 bytes + */ + if (host->data_dir == DM365_MMC_DATADIR_WRITE) + { + for (i = 0; i < (n >> 2); i++) + { + host->mmcsd_regs->MMCDXR = *((rt_uint32_t *)p); + p = p + 4; + } + if (n & 3) + { rt_kprintf("to do ... \n"); -// ioread8_rep(host->base + MMCSD_MMCDRR, p, (n & 3)); - p = p + (n & 3); - } - } - host->buffer = p; +// iowrite8_rep(host->base + MMCSD_MMCDXR, p, (n & 3)); + p = p + (n & 3); + } + } + else + { + for (i = 0; i < (n >> 2); i++) + { + *((rt_uint32_t *)p) = host->mmcsd_regs->MMCDRR; + p = p + 4; + } + if (n & 3) + { + rt_kprintf("to do ... \n"); +// ioread8_rep(host->base + MMCSD_MMCDRR, p, (n & 3)); + p = p + (n & 3); + } + } + host->buffer = p; } /******************************************************************************************************* -** : mmc_dm365_start_command() -** : ˺ǿʼSD -** -** 䡡: host -> DM365 mmc host -** cmd -> SD +** 函数名称: mmc_dm365_start_command() +** 功能描述: 此函数是开始发送SD命令 ** -** 䡡: -** -** ȫֱ: -** ģ: +** 输　入: host -> DM365 mmc host 句柄 +** cmd -> SD命令句柄 +** +** 输　出: 无 +** +** 全局变量: +** 调用模块: 无 ** ********************************************************************************************************/ static void mmc_dm365_start_command(struct mmc_dm365_host *host, struct rt_mmcsd_cmd *cmd) { - rt_uint32_t cmd_reg = 0; - rt_uint32_t im_val; - - host->cmd = cmd; + rt_uint32_t cmd_reg = 0; + rt_uint32_t im_val; - switch (resp_type(cmd)) - { - case RESP_R1B: - /* There's some spec confusion about when R1B is - * allowed, but if the card doesn't issue a BUSY - * then it's harmless for us to allow it. - */ - cmd_reg |= MMCCMD_BSYEXP; - /* FALLTHROUGH */ - case RESP_R1: /* 48 bits, CRC */ + host->cmd = cmd; + + switch (resp_type(cmd)) + { + case RESP_R1B: + /* There's some spec confusion about when R1B is + * allowed, but if the card doesn't issue a BUSY + * then it's harmless for us to allow it. + */ + cmd_reg |= MMCCMD_BSYEXP; + /* FALLTHROUGH */ + case RESP_R1: /* 48 bits, CRC */ case RESP_R4: - case RESP_R5: + case RESP_R5: case RESP_R6: - case RESP_R7: - cmd_reg |= MMCCMD_RSPFMT_R1456; - break; - case RESP_R2: /* 136 bits, CRC */ - cmd_reg |= MMCCMD_RSPFMT_R2; - break; - case RESP_R3: /* 48 bits, no CRC */ - cmd_reg |= MMCCMD_RSPFMT_R3; - break; - default: - cmd_reg |= MMCCMD_RSPFMT_NONE; - mmc_dbg("unknown resp_type %04x\n", resp_type(cmd)); - break; - } + case RESP_R7: + cmd_reg |= MMCCMD_RSPFMT_R1456; + break; + case RESP_R2: /* 136 bits, CRC */ + cmd_reg |= MMCCMD_RSPFMT_R2; + break; + case RESP_R3: /* 48 bits, no CRC */ + cmd_reg |= MMCCMD_RSPFMT_R3; + break; + default: + cmd_reg |= MMCCMD_RSPFMT_NONE; + mmc_dbg("unknown resp_type %04x\n", resp_type(cmd)); + break; + } - /* Set command index */ - cmd_reg |= cmd->cmd_code; + /* Set command index */ + cmd_reg |= cmd->cmd_code; - /* Enable EDMA transfer triggers */ - if (host->do_dma == RT_TRUE) - cmd_reg |= MMCCMD_DMATRIG; + /* Enable EDMA transfer triggers */ + if (host->do_dma == RT_TRUE) + cmd_reg |= MMCCMD_DMATRIG; - if (host->data != RT_NULL && host->data_dir == DM365_MMC_DATADIR_READ) - cmd_reg |= MMCCMD_DMATRIG; + if (host->data != RT_NULL && host->data_dir == DM365_MMC_DATADIR_READ) + cmd_reg |= MMCCMD_DMATRIG; - /* Setting whether command involves data transfer or not */ - if (cmd->data) - cmd_reg |= MMCCMD_WDATX; + /* Setting whether command involves data transfer or not */ + if (cmd->data) + cmd_reg |= MMCCMD_WDATX; - /* Setting whether stream or block transfer */ - if (cmd->flags & MMC_DATA_STREAM) - { - mmc_dbg("to do\n"); - cmd_reg |= MMCCMD_STRMTP; - } + /* Setting whether stream or block transfer */ + if (cmd->flags & MMC_DATA_STREAM) + { + mmc_dbg("to do\n"); + cmd_reg |= MMCCMD_STRMTP; + } - /* Setting whether data read or write */ - if (host->data_dir == DM365_MMC_DATADIR_WRITE) - cmd_reg |= MMCCMD_DTRW; + /* Setting whether data read or write */ + if (host->data_dir == DM365_MMC_DATADIR_WRITE) + cmd_reg |= MMCCMD_DTRW; - if (host->bus_mode == MMCSD_BUSMODE_PUSHPULL) - { - cmd_reg |= MMCCMD_PPLEN; - } - - /* set Command timeout */ - host->mmcsd_regs->MMCTOR = 0x1FFF; - - /* Enable interrupt (calculate here, defer until FIFO is stuffed). */ - im_val = MMCST0_RSPDNE | MMCST0_CRCRS | MMCST0_TOUTRS; - if (host->data_dir == DM365_MMC_DATADIR_WRITE) - { - im_val |= MMCST0_DATDNE | MMCST0_CRCWR; + if (host->bus_mode == MMCSD_BUSMODE_PUSHPULL) + { + cmd_reg |= MMCCMD_PPLEN; + } - if (host->do_dma == RT_FALSE) - im_val |= MMCST0_DXRDY; - } - else if (host->data_dir == DM365_MMC_DATADIR_READ) - { - im_val |= MMCST0_DATDNE | MMCST0_CRCRD | MMCST0_TOUTRD; + /* set Command timeout */ + host->mmcsd_regs->MMCTOR = 0x1FFF; - if (host->do_dma == RT_FALSE) - im_val |= MMCST0_DRRDY; - } + /* Enable interrupt (calculate here, defer until FIFO is stuffed). */ + im_val = MMCST0_RSPDNE | MMCST0_CRCRS | MMCST0_TOUTRS; + if (host->data_dir == DM365_MMC_DATADIR_WRITE) + { + im_val |= MMCST0_DATDNE | MMCST0_CRCWR; - /* - * Before non-DMA WRITE commands the controller needs priming: - * FIFO should be populated with 32 bytes i.e. whatever is the FIFO size - */ - if ((host->do_dma == RT_FALSE) && (host->data_dir == DM365_MMC_DATADIR_WRITE)) - dm365_fifo_data_trans(host, rw_threshold); + if (host->do_dma == RT_FALSE) + im_val |= MMCST0_DXRDY; + } + else if (host->data_dir == DM365_MMC_DATADIR_READ) + { + im_val |= MMCST0_DATDNE | MMCST0_CRCRD | MMCST0_TOUTRD; - host->mmcsd_regs->MMCARGHL = cmd->arg; - host->mmcsd_regs->MMCCMD = cmd_reg; - host->mmcsd_regs->MMCIM = im_val; + if (host->do_dma == RT_FALSE) + im_val |= MMCST0_DRRDY; + } + + /* + * Before non-DMA WRITE commands the controller needs priming: + * FIFO should be populated with 32 bytes i.e. whatever is the FIFO size + */ + if ((host->do_dma == RT_FALSE) && (host->data_dir == DM365_MMC_DATADIR_WRITE)) + dm365_fifo_data_trans(host, rw_threshold); + + host->mmcsd_regs->MMCARGHL = cmd->arg; + host->mmcsd_regs->MMCCMD = cmd_reg; + host->mmcsd_regs->MMCIM = im_val; } /******************************************************************************************************* -** : dm365_abort_dma() -** : ˺ֹDMA -** -** 䡡: host -> DM365 mmc host +** 函数名称: dm365_abort_dma() +** 功能描述: 此函数终止DMA传输 ** -** 䡡: -** -** ȫֱ: -** ģ: +** 输　入: host -> DM365 mmc host 句柄 +** +** 输　出: 无 +** +** 全局变量: +** 调用模块: 无 ** ********************************************************************************************************/ static void dm365_abort_dma(struct mmc_dm365_host *host) { - int sync_dev; + int sync_dev; - if (host->data_dir == DM365_MMC_DATADIR_READ) - sync_dev = host->rxdma; - else - sync_dev = host->txdma; + if (host->data_dir == DM365_MMC_DATADIR_READ) + sync_dev = host->rxdma; + else + sync_dev = host->txdma; - //EDMA3DisableTransfer(EDMA0CC0_REG_BASE, sync_dev, EDMA3_TRIG_MODE_EVENT); - edma_stop(sync_dev); - edma_clean_channel(sync_dev); + //EDMA3DisableTransfer(EDMA0CC0_REG_BASE, sync_dev, EDMA3_TRIG_MODE_EVENT); + edma_stop(sync_dev); + edma_clean_channel(sync_dev); } /******************************************************************************************************* -** : mmc_request_done() -** : ˺ڽһMMC -** -** 䡡: host -> DM365 mmc host -** mrq -> request +** 函数名称: mmc_request_done() +** 功能描述: 此函数用于结束处理一个MMC请求 ** -** 䡡: -** -** ȫֱ: -** ģ: +** 输　入: host -> DM365 mmc host 句柄 +** mrq -> request 句柄 +** +** 输　出: 无 +** +** 全局变量: +** 调用模块: 无 ** ********************************************************************************************************/ void mmc_request_done(struct rt_mmcsd_host *host, struct rt_mmcsd_req *mrq) { - struct rt_mmcsd_cmd *cmd = mrq->cmd; - int err = cmd->err; + struct rt_mmcsd_cmd *cmd = mrq->cmd; + int err = cmd->err; - if (err && cmd->retries) - { - mmc_dbg("req failed (CMD%u): %d, retrying...\n", cmd->cmd_code, err); + if (err && cmd->retries) + { + mmc_dbg("req failed (CMD%u): %d, retrying...\n", cmd->cmd_code, err); - cmd->retries--; - cmd->err = 0; - host->ops->request(host, mrq); - } - else - { - mmc_dbg("%s: req done (CMD%u): %d: %08x %08x %08x %08x\n", - "dm365 host", cmd->cmd_code, err, - cmd->resp[0], cmd->resp[1], - cmd->resp[2], cmd->resp[3]); + cmd->retries--; + cmd->err = 0; + host->ops->request(host, mrq); + } + else + { + mmc_dbg("%s: req done (CMD%u): %d: %08x %08x %08x %08x\n", + "dm365 host", cmd->cmd_code, err, + cmd->resp[0], cmd->resp[1], + cmd->resp[2], cmd->resp[3]); - if (mrq->data) - { - mmc_dbg("%s: %d bytes transferred: %d\n", - "dm365 host", - mrq->data->bytes_xfered, mrq->data->err); - } + if (mrq->data) + { + mmc_dbg("%s: %d bytes transferred: %d\n", + "dm365 host", + mrq->data->bytes_xfered, mrq->data->err); + } - if (mrq->stop) - { - mmc_dbg("%s: (CMD%u): %d: %08x %08x %08x %08x\n", - "dm365 host", mrq->stop->cmd_code, - mrq->stop->err, - mrq->stop->resp[0], mrq->stop->resp[1], - mrq->stop->resp[2], mrq->stop->resp[3]); - } + if (mrq->stop) + { + mmc_dbg("%s: (CMD%u): %d: %08x %08x %08x %08x\n", + "dm365 host", mrq->stop->cmd_code, + mrq->stop->err, + mrq->stop->resp[0], mrq->stop->resp[1], + mrq->stop->resp[2], mrq->stop->resp[3]); + } - mmcsd_req_complete(host); - } + mmcsd_req_complete(host); + } } /******************************************************************************************************* -** : mmc_dm365_xfer_done() -** : ݴͽô˺ -** -** 䡡: host -> DM365 mmc host -** data -> data +** 函数名称: mmc_dm365_xfer_done() +** 功能描述: 数据传送结束调用此函数 ** -** 䡡: -** -** ȫֱ: -** ģ: +** 输　入: host -> DM365 mmc host 句柄 +** data -> data 句柄 +** +** 输　出: 无 +** +** 全局变量: +** 调用模块: 无 ** ********************************************************************************************************/ static void mmc_dm365_xfer_done(struct mmc_dm365_host *host, struct rt_mmcsd_data *data) { - host->data = RT_NULL; + host->data = RT_NULL; - if (host->mmc->flags & MMCSD_SUP_SDIO_IRQ) { - /* - * SDIO Interrupt Detection work-around as suggested by - * Davinci Errata (TMS320DM355 Silicon Revision 1.1 Errata - * 2.1.6): Signal SDIO interrupt only if it is enabled by core - */ - if (host->sdio_int && !(host->mmcsd_regs->SDIOST0 & - SDIOST0_DAT1_HI)) { - host->mmcsd_regs->SDIOIST = SDIOIST_IOINT; - sdio_irq_wakeup(host->mmc); - } - } + if (host->mmc->flags & MMCSD_SUP_SDIO_IRQ) { + /* + * SDIO Interrupt Detection work-around as suggested by + * Davinci Errata (TMS320DM355 Silicon Revision 1.1 Errata + * 2.1.6): Signal SDIO interrupt only if it is enabled by core + */ + if (host->sdio_int && !(host->mmcsd_regs->SDIOST0 & + SDIOST0_DAT1_HI)) { + host->mmcsd_regs->SDIOIST = SDIOIST_IOINT; + sdio_irq_wakeup(host->mmc); + } + } - if (host->do_dma == RT_TRUE) - { - dm365_abort_dma(host); + if (host->do_dma == RT_TRUE) + { + dm365_abort_dma(host); - if (data->flags & DATA_DIR_READ) - { - /* read operation */ - if (host->use_dma_buffer == RT_TRUE) - { - /* copy DMA buffer to read buffer */ - memcpy(data->buf, (void*)MMU_NOCACHE_ADDR(host->dma_buffer), data->blks * data->blksize); - } - /*else - { - mmu_invalidate_dcache((rt_uint32_t)data->buf, data->blks * data->blksize); - }*/ - } + if (data->flags & DATA_DIR_READ) + { + /* read operation */ + if (host->use_dma_buffer == RT_TRUE) + { + /* copy DMA buffer to read buffer */ + memcpy(data->buf, (void*)MMU_NOCACHE_ADDR(host->dma_buffer), data->blks * data->blksize); + } + /*else + { + mmu_invalidate_dcache((rt_uint32_t)data->buf, data->blks * data->blksize); + }*/ + } - host->do_dma = RT_FALSE; - } - - host->data_dir = DM365_MMC_DATADIR_NONE; + host->do_dma = RT_FALSE; + } - if (!data->stop || (host->cmd && host->cmd->err)) - { - mmc_request_done(host->mmc, data->mrq); - host->mmcsd_regs->MMCIM = 0; - } - else - mmc_dm365_start_command(host, data->stop); + host->data_dir = DM365_MMC_DATADIR_NONE; + + if (!data->stop || (host->cmd && host->cmd->err)) + { + mmc_request_done(host->mmc, data->mrq); + host->mmcsd_regs->MMCIM = 0; + } + else + mmc_dm365_start_command(host, data->stop); } static void mmc_dm365_dma_cb(unsigned channel, rt_uint16_t ch_status, void *data) { - if (DMA_COMPLETE != ch_status) { - struct mmc_dm365_host *host = data; + if (DMA_COMPLETE != ch_status) { + struct mmc_dm365_host *host = data; - /* Currently means: DMA Event Missed, or "null" transfer - * request was seen. In the future, TC errors (like bad - * addresses) might be presented too. - */ - mmc_dbg("DMA %s error\n", - (host->data->flags & MMC_DATA_WRITE) - ? "write" : "read"); - host->data->err = -RT_EIO; - mmc_dm365_xfer_done(host, host->data); - } + /* Currently means: DMA Event Missed, or "null" transfer + * request was seen. In the future, TC errors (like bad + * addresses) might be presented too. + */ + mmc_dbg("DMA %s error\n", + (host->data->flags & MMC_DATA_WRITE) + ? "write" : "read"); + host->data->err = -RT_EIO; + mmc_dm365_xfer_done(host, host->data); + } } /******************************************************************************************************* -** : mmc_dm365_dma_setup() -** : DMA ú -** -** 䡡: host -> DM365 mmc host -** tx -> жTxRx -** template -> ڱEDMA3CCPaRAMEntry +** 函数名称: mmc_dm365_dma_setup() +** 功能描述: DMA 设置函数 ** -** 䡡: -** -** ȫֱ: -** ģ: +** 输　入: host -> DM365 mmc host 句柄 +** tx -> 布尔变量，用于判断Tx或者是Rx +** template -> 用于保存EDMA3CCPaRAMEntry机构数据 +** +** 输　出: 无 +** +** 全局变量: +** 调用模块: 无 ** ********************************************************************************************************/ static void mmc_dm365_dma_setup(struct mmc_dm365_host *host, rt_bool_t tx, struct edmacc_param *template) { - rt_uint32_t sync_dev; - const rt_uint16_t acnt = 4; - const rt_uint16_t bcnt = rw_threshold >> 2; - const rt_uint16_t ccnt = 0; - rt_uint32_t src_port = 0; - rt_uint32_t dst_port = 0; - rt_int16_t src_bidx, dst_bidx; - rt_int16_t src_cidx, dst_cidx; + rt_uint32_t sync_dev; + const rt_uint16_t acnt = 4; + const rt_uint16_t bcnt = rw_threshold >> 2; + const rt_uint16_t ccnt = 0; + rt_uint32_t src_port = 0; + rt_uint32_t dst_port = 0; + rt_int16_t src_bidx, dst_bidx; + rt_int16_t src_cidx, dst_cidx; //edmacc_param paramSet; - /* - * A-B Sync transfer: each DMA request is for one "frame" of - * rw_threshold bytes, broken into "acnt"-size chunks repeated - * "bcnt" times. Each segment needs "ccnt" such frames; since - * we tell the block layer our mmc->max_seg_size limit, we can - * trust (later) that it's within bounds. - * - * The FIFOs are read/written in 4-byte chunks (acnt == 4) and - * EDMA will optimize memory operations to use larger bursts. - */ - if (tx) - { - sync_dev = host->txdma; + /* + * A-B Sync transfer: each DMA request is for one "frame" of + * rw_threshold bytes, broken into "acnt"-size chunks repeated + * "bcnt" times. Each segment needs "ccnt" such frames; since + * we tell the block layer our mmc->max_seg_size limit, we can + * trust (later) that it's within bounds. + * + * The FIFOs are read/written in 4-byte chunks (acnt == 4) and + * EDMA will optimize memory operations to use larger bursts. + */ + if (tx) + { + sync_dev = host->txdma; - /* src_prt, ccnt, and link to be set up later */ - /*paramSet.srcBIdx = acnt; - paramSet.srcCIdx = acnt * bcnt; + /* src_prt, ccnt, and link to be set up later */ + /*paramSet.srcBIdx = acnt; + paramSet.srcCIdx = acnt * bcnt; - paramSet.destAddr = (rt_uint32_t)&(host->mmcsd_regs->MMCDXR); - paramSet.destBIdx = 0; - paramSet.destCIdx = 0;*/ - /* src_prt, ccnt, and link to be set up later */ - src_bidx = acnt; - src_cidx = acnt * bcnt; + paramSet.destAddr = (rt_uint32_t)&(host->mmcsd_regs->MMCDXR); + paramSet.destBIdx = 0; + paramSet.destCIdx = 0;*/ + /* src_prt, ccnt, and link to be set up later */ + src_bidx = acnt; + src_cidx = acnt * bcnt; - dst_port = (rt_uint32_t)&(host->mmcsd_regs->MMCDXR); - dst_bidx = 0; - dst_cidx = 0; - } - else - { - sync_dev = host->rxdma; + dst_port = (rt_uint32_t)&(host->mmcsd_regs->MMCDXR); + dst_bidx = 0; + dst_cidx = 0; + } + else + { + sync_dev = host->rxdma; - /* dst_prt, ccnt, and link to be set up later */ - /*paramSet.srcAddr = (rt_uint32_t)&(host->mmcsd_regs->MMCDRR); - paramSet.srcBIdx = 0; - paramSet.srcCIdx = 0; + /* dst_prt, ccnt, and link to be set up later */ + /*paramSet.srcAddr = (rt_uint32_t)&(host->mmcsd_regs->MMCDRR); + paramSet.srcBIdx = 0; + paramSet.srcCIdx = 0; - paramSet.destBIdx = acnt; - paramSet.destCIdx = acnt * bcnt;*/ - src_port = (rt_uint32_t)&(host->mmcsd_regs->MMCDRR); - src_bidx = 0; - src_cidx = 0; + paramSet.destBIdx = acnt; + paramSet.destCIdx = acnt * bcnt;*/ + src_port = (rt_uint32_t)&(host->mmcsd_regs->MMCDRR); + src_bidx = 0; + src_cidx = 0; - /* dst_prt, ccnt, and link to be set up later */ - dst_bidx = acnt; - dst_cidx = acnt * bcnt; - } - /* - * We can't use FIFO mode for the FIFOs because MMC FIFO addresses - * are not 256-bit (32-byte) aligned. So we use INCR, and the W8BIT - * parameter is ignored. - */ - edma_set_src(sync_dev, src_port, INCR, W8BIT); - edma_set_dest(sync_dev, dst_port, INCR, W8BIT); + /* dst_prt, ccnt, and link to be set up later */ + dst_bidx = acnt; + dst_cidx = acnt * bcnt; + } + /* + * We can't use FIFO mode for the FIFOs because MMC FIFO addresses + * are not 256-bit (32-byte) aligned. So we use INCR, and the W8BIT + * parameter is ignored. + */ + edma_set_src(sync_dev, src_port, INCR, W8BIT); + edma_set_dest(sync_dev, dst_port, INCR, W8BIT); - edma_set_src_index(sync_dev, src_bidx, src_cidx); - edma_set_dest_index(sync_dev, dst_bidx, dst_cidx); + edma_set_src_index(sync_dev, src_bidx, src_cidx); + edma_set_dest_index(sync_dev, dst_bidx, dst_cidx); - edma_set_transfer_params(sync_dev, acnt, bcnt, ccnt, 8, ABSYNC); + edma_set_transfer_params(sync_dev, acnt, bcnt, ccnt, 8, ABSYNC); - edma_read_slot(sync_dev, template); + edma_read_slot(sync_dev, template); + + /* don't bother with irqs or chaining */ + template->opt |= EDMA_CHAN_SLOT(sync_dev) << 12; - /* don't bother with irqs or chaining */ - template->opt |= EDMA_CHAN_SLOT(sync_dev) << 12; - #if 0 - paramSet.opt = 0u; - /* Src & Dest are in INCR modes */ - paramSet.opt &= 0xFFFFFFFCu; - /* Program the TCC */ - paramSet.opt |= ((sync_dev << EDMA3CC_OPT_TCC_SHIFT) & EDMA3CC_OPT_TCC); - - paramSet.aCnt = acnt; - paramSet.bCnt = bcnt; - - /* AB Sync Transfer Mode */ - paramSet.opt |= (1 << EDMA3CC_OPT_SYNCDIM_SHIFT); - - /* Now, write the PaRAM Set. */ - EDMA3SetPaRAM(EDMA0CC0_REG_BASE, sync_dev, ¶mSet); + paramSet.opt = 0u; + /* Src & Dest are in INCR modes */ + paramSet.opt &= 0xFFFFFFFCu; + /* Program the TCC */ + paramSet.opt |= ((sync_dev << EDMA3CC_OPT_TCC_SHIFT) & EDMA3CC_OPT_TCC); - EDMA3GetPaRAM(EDMA0CC0_REG_BASE, sync_dev, template); + paramSet.aCnt = acnt; + paramSet.bCnt = bcnt; + + /* AB Sync Transfer Mode */ + paramSet.opt |= (1 << EDMA3CC_OPT_SYNCDIM_SHIFT); + + /* Now, write the PaRAM Set. */ + EDMA3SetPaRAM(EDMA0CC0_REG_BASE, sync_dev, ¶mSet); + + EDMA3GetPaRAM(EDMA0CC0_REG_BASE, sync_dev, template); #endif } /******************************************************************************************************* -** : mmc_dm365_send_dma_request() -** : DMA -** -** 䡡: host -> DM365 mmc host -** data -> DMAݽṹ +** 函数名称: mmc_dm365_send_dma_request() +** 功能描述: 发送DMA请求 ** -** 䡡: -** -** ȫֱ: -** ģ: +** 输　入: host -> DM365 mmc host 句柄 +** data -> DMA传送数据结构句柄 +** +** 输　出: 无 +** +** 全局变量: +** 调用模块: 无 ** ********************************************************************************************************/ static void mmc_dm365_send_dma_request(struct mmc_dm365_host *host, struct rt_mmcsd_data *data) { - //struct EDMA3CCPaRAMEntry *template; - struct edmacc_param *template; - rt_uint32_t buf_ptr; - rt_uint32_t channel; - rt_uint32_t bytes_left = host->bytes_left; - rt_uint32_t count = host->bytes_left; - const rt_uint32_t shift = ffs(rw_threshold) - 1; + //struct EDMA3CCPaRAMEntry *template; + struct edmacc_param *template; + rt_uint32_t buf_ptr; + rt_uint32_t channel; + rt_uint32_t bytes_left = host->bytes_left; + rt_uint32_t count = host->bytes_left; + const rt_uint32_t shift = ffs(rw_threshold) - 1; - if (host->use_dma_buffer == RT_TRUE) - buf_ptr = host->dma_buffer;//MMU_NOCACHE_ADDR(host->dma_buffer); - else - buf_ptr = (rt_uint32_t)data->buf; + if (host->use_dma_buffer == RT_TRUE) + buf_ptr = host->dma_buffer;//MMU_NOCACHE_ADDR(host->dma_buffer); + else + buf_ptr = (rt_uint32_t)data->buf; - if (host->data_dir == DM365_MMC_DATADIR_WRITE) - { - template = &host->tx_template; - channel = host->txdma; - } - else - { - template = &host->rx_template; - channel = host->rxdma; - } + if (host->data_dir == DM365_MMC_DATADIR_WRITE) + { + template = &host->tx_template; + channel = host->txdma; + } + else + { + template = &host->rx_template; + channel = host->rxdma; + } - template->link_bcntrld = 0xffff; - //template->bCntReload = 0x0; + template->link_bcntrld = 0xffff; + //template->bCntReload = 0x0; - if (count > bytes_left) - count = bytes_left; - bytes_left -= count; + if (count > bytes_left) + count = bytes_left; + bytes_left -= count; - if (host->data_dir == DM365_MMC_DATADIR_WRITE) - template->src = buf_ptr; - else - template->dst = buf_ptr; - template->ccnt = count >> shift; + if (host->data_dir == DM365_MMC_DATADIR_WRITE) + template->src = buf_ptr; + else + template->dst = buf_ptr; + template->ccnt = count >> shift; - edma_write_slot(channel, template); + edma_write_slot(channel, template); - edma_clear_event(channel); + edma_clear_event(channel); - /*EDMA3SetPaRAM(EDMA0CC0_REG_BASE, channel, template); - EDMA3ClrEvt(EDMA0CC0_REG_BASE, channel); - EDMA3EnableTransfer(EDMA0CC0_REG_BASE, channel, EDMA3_TRIG_MODE_EVENT);*/ - edma_start(channel); + /*EDMA3SetPaRAM(EDMA0CC0_REG_BASE, channel, template); + EDMA3ClrEvt(EDMA0CC0_REG_BASE, channel); + EDMA3EnableTransfer(EDMA0CC0_REG_BASE, channel, EDMA3_TRIG_MODE_EVENT);*/ + edma_start(channel); } /******************************************************************************************************* -** : mmc_dm365_start_dma_transfer() -** : ʼDMA -** -** 䡡: host -> DM365 mmc host -** data -> DMAݽṹ +** 函数名称: mmc_dm365_start_dma_transfer() +** 功能描述: 开始DMA传输 ** -** 䡡: DMAֽ -** -** ȫֱ: -** ģ: +** 输　入: host -> DM365 mmc host 句柄 +** data -> DMA传送数据结构句柄 +** +** 输　出: DMA传输字节数 +** +** 全局变量: +** 调用模块: 无 ** ********************************************************************************************************/ static int mmc_dm365_start_dma_transfer(struct mmc_dm365_host *host, struct rt_mmcsd_data *data) { - /* set initial value */ - host->use_dma_buffer = RT_FALSE; + /* set initial value */ + host->use_dma_buffer = RT_FALSE; - if (!(data->flags & DATA_DIR_READ)) - { - if ((rt_uint32_t)data->buf & (RT_ALIGN_SIZE - 1)) - { - /* not align to basic size, use DMA buffer */ - host->use_dma_buffer = RT_TRUE; - memcpy((void*)MMU_NOCACHE_ADDR(host->dma_buffer), data->buf, data->blks * data->blksize); - } - else - { - rt_uint32_t addr; - addr = ((rt_uint32_t)data->buf & ~(CACHE_LINE_SIZE - 1)); - /* write data case, always clean DCache */ - mmu_clean_dcache(addr, (data->blks + 1)* data->blksize); - } - } - else - { - /* whether align to cache line in read operation */ - if (((rt_uint32_t)data->buf) & (CACHE_LINE_SIZE - 1)) - host->use_dma_buffer = RT_TRUE; - else - mmu_invalidate_dcache((rt_uint32_t)data->buf, data->blks * data->blksize); - } + if (!(data->flags & DATA_DIR_READ)) + { + if ((rt_uint32_t)data->buf & (RT_ALIGN_SIZE - 1)) + { + /* not align to basic size, use DMA buffer */ + host->use_dma_buffer = RT_TRUE; + memcpy((void*)MMU_NOCACHE_ADDR(host->dma_buffer), data->buf, data->blks * data->blksize); + } + else + { + rt_uint32_t addr; + addr = ((rt_uint32_t)data->buf & ~(CACHE_LINE_SIZE - 1)); + /* write data case, always clean DCache */ + mmu_clean_dcache(addr, (data->blks + 1)* data->blksize); + } + } + else + { + /* whether align to cache line in read operation */ + if (((rt_uint32_t)data->buf) & (CACHE_LINE_SIZE - 1)) + host->use_dma_buffer = RT_TRUE; + else + mmu_invalidate_dcache((rt_uint32_t)data->buf, data->blks * data->blksize); + } - host->do_dma = RT_TRUE; - mmc_dm365_send_dma_request(host, data); + host->do_dma = RT_TRUE; + mmc_dm365_send_dma_request(host, data); - return 0; + return 0; } #if 0 /******************************************************************************************************* -** : acquire_dma_channels() -** : ȡDMA channel -** -** 䡡: host -> DM365 mmc host +** 函数名称: acquire_dma_channels() +** 功能描述: 获取DMA channel ** -** 䡡: DMA ͨ -** -** ȫֱ: -** ģ: +** 输　入: host -> DM365 mmc host 句柄 +** +** 输　出: DMA 通道号 +** +** 全局变量: +** 调用模块: 无 ** ********************************************************************************************************/ static int acquire_dma_channels(struct mmc_dm365_host *host) { - int r; + int r; - /* Acquire master DMA write channel */ - r = EDMA3RequestChannel(EDMA0CC0_REG_BASE, EDMA3_CHANNEL_TYPE_DMA, host->txdma, host->txdma, EVT_QUEUE_NUM); - if (r < 0) - { - rt_kprintf("alloc %s channel err %d\n", "tx", r); - return r; - } - mmc_dm365_dma_setup(host, RT_TRUE, &host->tx_template); + /* Acquire master DMA write channel */ + r = EDMA3RequestChannel(EDMA0CC0_REG_BASE, EDMA3_CHANNEL_TYPE_DMA, host->txdma, host->txdma, EVT_QUEUE_NUM); + if (r < 0) + { + rt_kprintf("alloc %s channel err %d\n", "tx", r); + return r; + } + mmc_dm365_dma_setup(host, RT_TRUE, &host->tx_template); - /* Acquire master DMA read channel */ - r = EDMA3RequestChannel(EDMA0CC0_REG_BASE, EDMA3_CHANNEL_TYPE_DMA, host->rxdma, host->rxdma, EVT_QUEUE_NUM); - if (r < 0) - { - rt_kprintf("alloc %s channel err %d\n", "rx", r); - goto free_master_write; - } - mmc_dm365_dma_setup(host, RT_FALSE, &host->rx_template); + /* Acquire master DMA read channel */ + r = EDMA3RequestChannel(EDMA0CC0_REG_BASE, EDMA3_CHANNEL_TYPE_DMA, host->rxdma, host->rxdma, EVT_QUEUE_NUM); + if (r < 0) + { + rt_kprintf("alloc %s channel err %d\n", "rx", r); + goto free_master_write; + } + mmc_dm365_dma_setup(host, RT_FALSE, &host->rx_template); - return 0; + return 0; free_master_write: - EDMA3FreeChannel(EDMA0CC0_REG_BASE, EDMA3_CHANNEL_TYPE_DMA, host->txdma, EDMA3_TRIG_MODE_EVENT, host->txdma, EVT_QUEUE_NUM); + EDMA3FreeChannel(EDMA0CC0_REG_BASE, EDMA3_CHANNEL_TYPE_DMA, host->txdma, EDMA3_TRIG_MODE_EVENT, host->txdma, EVT_QUEUE_NUM); - return r; + return r; } #endif static int acquire_dma_channels(struct mmc_dm365_host *host) { - //u32 link_size; - int r, i; + //u32 link_size; + int r, i; - /* Acquire master DMA write channel */ - r = edma_alloc_channel(host->txdma, mmc_dm365_dma_cb, host, - EVENTQ_DEFAULT); - if (r < 0) { - mmc_dbg("alloc %s channel err %d\n", - "tx", r); - return r; - } - mmc_dm365_dma_setup(host, RT_TRUE, &host->tx_template); + /* Acquire master DMA write channel */ + r = edma_alloc_channel(host->txdma, mmc_dm365_dma_cb, host, + EVENTQ_DEFAULT); + if (r < 0) { + mmc_dbg("alloc %s channel err %d\n", + "tx", r); + return r; + } + mmc_dm365_dma_setup(host, RT_TRUE, &host->tx_template); - /* Acquire master DMA read channel */ - r = edma_alloc_channel(host->rxdma, mmc_dm365_dma_cb, host, - EVENTQ_DEFAULT); - if (r < 0) { - mmc_dbg("alloc %s channel err %d\n", - "rx", r); - goto free_master_write; - } - mmc_dm365_dma_setup(host, RT_FALSE, &host->rx_template); + /* Acquire master DMA read channel */ + r = edma_alloc_channel(host->rxdma, mmc_dm365_dma_cb, host, + EVENTQ_DEFAULT); + if (r < 0) { + mmc_dbg("alloc %s channel err %d\n", + "rx", r); + goto free_master_write; + } + mmc_dm365_dma_setup(host, RT_FALSE, &host->rx_template); - /* Allocate parameter RAM slots, which will later be bound to a - * channel as needed to handle a scatterlist. - */ + /* Allocate parameter RAM slots, which will later be bound to a + * channel as needed to handle a scatterlist. + */ #if 0 - link_size = min_t(unsigned, host->nr_sg, ARRAY_SIZE(host->links)); - for (i = 0; i < link_size; i++) { - r = edma_alloc_slot(EDMA_CTLR(host->txdma), EDMA_SLOT_ANY); - if (r < 0) { - mmc_dbg("dma PaRAM alloc --> %d\n", - r); - break; - } - host->links[i] = r; - } - host->n_link = i; + link_size = min_t(unsigned, host->nr_sg, ARRAY_SIZE(host->links)); + for (i = 0; i < link_size; i++) { + r = edma_alloc_slot(EDMA_CTLR(host->txdma), EDMA_SLOT_ANY); + if (r < 0) { + mmc_dbg("dma PaRAM alloc --> %d\n", + r); + break; + } + host->links[i] = r; + } + host->n_link = i; #endif - return 0; + return 0; free_master_write: - edma_free_channel(host->txdma); + edma_free_channel(host->txdma); - return r; + return r; } /******************************************************************************************************* -** : mmc_dm365_prepare_data() -** : ׼ DMA -** -** 䡡: host -> DM365 mmc host -** req -> SD request ṹ +** 函数名称: mmc_dm365_prepare_data() +** 功能描述: 准备 DMA 数据 ** -** 䡡: -** -** ȫֱ: -** ģ: +** 输　入: host -> DM365 mmc host 句柄 +** req -> SD request 结构句柄 +** +** 输　出: 无 +** +** 全局变量: +** 调用模块: 无 ** ********************************************************************************************************/ static void mmc_dm365_prepare_data(struct mmc_dm365_host *host, struct rt_mmcsd_req *req) { - int timeout; - int fifo_lev; - struct rt_mmcsd_data *data = req->data; + int timeout; + int fifo_lev; + struct rt_mmcsd_data *data = req->data; - fifo_lev = (rw_threshold == 64) ? MMCFIFOCTL_FIFOLEV : 0; + fifo_lev = (rw_threshold == 64) ? MMCFIFOCTL_FIFOLEV : 0; - host->data = data; - if (data == RT_NULL) - { - host->data_dir = DM365_MMC_DATADIR_NONE; - host->mmcsd_regs->MMCBLEN = 0; - host->mmcsd_regs->MMCNBLK = 0; - return; - } + host->data = data; + if (data == RT_NULL) + { + host->data_dir = DM365_MMC_DATADIR_NONE; + host->mmcsd_regs->MMCBLEN = 0; + host->mmcsd_regs->MMCNBLK = 0; + return; + } - mmc_dbg("%s %s, %d blocks of %d bytes\n", - (data->flags & DATA_STREAM) ? "stream" : "block", - (data->flags & DATA_DIR_WRITE) ? "write" : "read", - data->blks, data->blksize); - mmc_dbg(" DTO %d cycles + %d ns\n", - data->timeout_clks, data->timeout_ns); - timeout = data->timeout_clks + (data->timeout_ns / host->ns_in_one_cycle); - if (timeout > 0xffff) - timeout = 0xffff; + mmc_dbg("%s %s, %d blocks of %d bytes\n", + (data->flags & DATA_STREAM) ? "stream" : "block", + (data->flags & DATA_DIR_WRITE) ? "write" : "read", + data->blks, data->blksize); + mmc_dbg(" DTO %d cycles + %d ns\n", + data->timeout_clks, data->timeout_ns); + timeout = data->timeout_clks + (data->timeout_ns / host->ns_in_one_cycle); + if (timeout > 0xffff) + timeout = 0xffff; - host->mmcsd_regs->MMCTOD = timeout; - host->mmcsd_regs->MMCNBLK = data->blks; - host->mmcsd_regs->MMCBLEN = data->blksize; - - /* Configure the FIFO */ - switch (data->flags & DATA_DIR_WRITE) - { - case DATA_DIR_WRITE: - host->data_dir = DM365_MMC_DATADIR_WRITE; - host->mmcsd_regs->MMCFIFOCTL = fifo_lev | MMCFIFOCTL_FIFODIR_WR | MMCFIFOCTL_FIFORST; - host->mmcsd_regs->MMCFIFOCTL = fifo_lev | MMCFIFOCTL_FIFODIR_WR; - break; + host->mmcsd_regs->MMCTOD = timeout; + host->mmcsd_regs->MMCNBLK = data->blks; + host->mmcsd_regs->MMCBLEN = data->blksize; - default: - host->data_dir = DM365_MMC_DATADIR_READ; - host->mmcsd_regs->MMCFIFOCTL = fifo_lev | MMCFIFOCTL_FIFODIR_RD | MMCFIFOCTL_FIFORST; - host->mmcsd_regs->MMCFIFOCTL = fifo_lev | MMCFIFOCTL_FIFODIR_RD; - break; - } + /* Configure the FIFO */ + switch (data->flags & DATA_DIR_WRITE) + { + case DATA_DIR_WRITE: + host->data_dir = DM365_MMC_DATADIR_WRITE; + host->mmcsd_regs->MMCFIFOCTL = fifo_lev | MMCFIFOCTL_FIFODIR_WR | MMCFIFOCTL_FIFORST; + host->mmcsd_regs->MMCFIFOCTL = fifo_lev | MMCFIFOCTL_FIFODIR_WR; + break; - host->buffer = RT_NULL; - host->bytes_left = data->blks * data->blksize; + default: + host->data_dir = DM365_MMC_DATADIR_READ; + host->mmcsd_regs->MMCFIFOCTL = fifo_lev | MMCFIFOCTL_FIFODIR_RD | MMCFIFOCTL_FIFORST; + host->mmcsd_regs->MMCFIFOCTL = fifo_lev | MMCFIFOCTL_FIFODIR_RD; + break; + } - /* For now we try to use DMA whenever we won't need partial FIFO - * reads or writes, either for the whole transfer (as tested here) - * or for any individual scatterlist segment (tested when we call - * start_dma_transfer). - * - * While we *could* change that, unusual block sizes are rarely - * used. The occasional fallback to PIO should't hurt. - */ - if ((host->use_dma == RT_TRUE) && (host->bytes_left & (rw_threshold - 1)) == 0 && - mmc_dm365_start_dma_transfer(host, data) == 0) - { - /* zero this to ensure we take no PIO paths */ - host->bytes_left = 0; - } - else - { - /* Revert to CPU Copy */ - host->buffer = (rt_uint8_t*)req->data->buf; - } + host->buffer = RT_NULL; + host->bytes_left = data->blks * data->blksize; + + /* For now we try to use DMA whenever we won't need partial FIFO + * reads or writes, either for the whole transfer (as tested here) + * or for any individual scatterlist segment (tested when we call + * start_dma_transfer). + * + * While we *could* change that, unusual block sizes are rarely + * used. The occasional fallback to PIO should't hurt. + */ + if ((host->use_dma == RT_TRUE) && (host->bytes_left & (rw_threshold - 1)) == 0 && + mmc_dm365_start_dma_transfer(host, data) == 0) + { + /* zero this to ensure we take no PIO paths */ + host->bytes_left = 0; + } + else + { + /* Revert to CPU Copy */ + host->buffer = (rt_uint8_t*)req->data->buf; + } } /******************************************************************************************************* -** : mmc_dm365_request() -** : ˺ʵSD request -** -** 䡡: host -> DM365 mmc host -** req -> SD request ṹ +** 函数名称: mmc_dm365_request() +** 功能描述: 此函数实现SD request操作 ** -** 䡡: -** -** ȫֱ: -** ģ: +** 输　入: host -> DM365 mmc host 句柄 +** req -> SD request 结构句柄 +** +** 输　出: 无 +** +** 全局变量: +** 调用模块: 无 ** ********************************************************************************************************/ static void mmc_dm365_request(struct rt_mmcsd_host *mmc, struct rt_mmcsd_req *req) { - struct mmc_dm365_host *host = mmc_priv(mmc); - unsigned long timeout = rt_tick_get() + 900; - rt_uint32_t mmcst1 = 0; + struct mmc_dm365_host *host = mmc_priv(mmc); + unsigned long timeout = rt_tick_get() + 900; + rt_uint32_t mmcst1 = 0; - /* Card may still be sending BUSY after a previous operation, - * typically some kind of write. If so, we can't proceed yet. - */ - while (rt_tick_get() < timeout) + /* Card may still be sending BUSY after a previous operation, + * typically some kind of write. If so, we can't proceed yet. + */ + while (rt_tick_get() < timeout) { - mmcst1 = host->mmcsd_regs->MMCST1; - if (!(mmcst1 & MMCST1_BUSY)) - break; - } - if (mmcst1 & MMCST1_BUSY) + mmcst1 = host->mmcsd_regs->MMCST1; + if (!(mmcst1 & MMCST1_BUSY)) + break; + } + if (mmcst1 & MMCST1_BUSY) { - mmc_dbg("still BUSY? bad ... \n"); - req->cmd->err = -RT_ETIMEOUT; - mmc_request_done(mmc, req); - return; - } + mmc_dbg("still BUSY? bad ... \n"); + req->cmd->err = -RT_ETIMEOUT; + mmc_request_done(mmc, req); + return; + } - host->do_dma = RT_FALSE; - mmc_dm365_prepare_data(host, req); - mmc_dm365_start_command(host, req->cmd); + host->do_dma = RT_FALSE; + mmc_dm365_prepare_data(host, req); + mmc_dm365_start_command(host, req->cmd); } static void mmc_dm365_enable_sdio_irq(struct rt_mmcsd_host *mmc, rt_int32_t enable) { - struct mmc_dm365_host *host = mmc_priv(mmc); + struct mmc_dm365_host *host = mmc_priv(mmc); - if (enable) - { - if (!(host->mmcsd_regs->SDIOST0 & SDIOST0_DAT1_HI)) - { - host->mmcsd_regs->SDIOIST = SDIOIST_IOINT; - sdio_irq_wakeup(host->mmc); - } - else - { - host->sdio_int = RT_TRUE; - host->mmcsd_regs->SDIOIEN |= SDIOIEN_IOINTEN; - } - } - else - { - host->sdio_int = RT_FALSE; - host->mmcsd_regs->SDIOIEN &= ~SDIOIEN_IOINTEN; - } + if (enable) + { + if (!(host->mmcsd_regs->SDIOST0 & SDIOST0_DAT1_HI)) + { + host->mmcsd_regs->SDIOIST = SDIOIST_IOINT; + sdio_irq_wakeup(host->mmc); + } + else + { + host->sdio_int = RT_TRUE; + host->mmcsd_regs->SDIOIEN |= SDIOIEN_IOINTEN; + } + } + else + { + host->sdio_int = RT_FALSE; + host->mmcsd_regs->SDIOIEN &= ~SDIOIEN_IOINTEN; + } } -static const struct rt_mmcsd_host_ops mmc_dm365_ops = +static const struct rt_mmcsd_host_ops mmc_dm365_ops = { - mmc_dm365_request, - mmc_dm365_set_ios, + mmc_dm365_request, + mmc_dm365_set_ios, RT_NULL, mmc_dm365_enable_sdio_irq }; /******************************************************************************************************* -** : mmc_dm365_reset_ctrl() -** : ˺reset mmc -** -** 䡡: host -> DM365 mmc host -** val -> жresetenable +** 函数名称: mmc_dm365_reset_ctrl() +** 功能描述: 此函数用于reset mmc控制器 ** -** 䡡: -** -** ȫֱ: -** ģ: +** 输　入: host -> DM365 mmc host 句柄 +** val -> 判断做reset还是enable +** +** 输　出: 无 +** +** 全局变量: +** 调用模块: 无 ** ********************************************************************************************************/ static void mmc_dm365_reset_ctrl(struct mmc_dm365_host *host, int val) { - rt_uint32_t temp; + rt_uint32_t temp; - temp = host->mmcsd_regs->MMCCTL; - - if (val) /* reset */ - temp |= MMCCTL_CMDRST | MMCCTL_DATRST; - else /* enable */ - temp &= ~(MMCCTL_CMDRST | MMCCTL_DATRST); + temp = host->mmcsd_regs->MMCCTL; - host->mmcsd_regs->MMCCTL = temp; + if (val) /* reset */ + temp |= MMCCTL_CMDRST | MMCCTL_DATRST; + else /* enable */ + temp &= ~(MMCCTL_CMDRST | MMCCTL_DATRST); - delay_us(10); + host->mmcsd_regs->MMCCTL = temp; + + delay_us(10); } /******************************************************************************************************* -** : init_mmcsd_host() -** : ˺ڳʼDM365 MMCSD -** -** 䡡: host -> DM365 mmc host +** 函数名称: init_mmcsd_host() +** 功能描述: 此函数用于初始化DM365 MMCSD控制器 ** -** 䡡: -** -** ȫֱ: -** ģ: +** 输　入: host -> DM365 mmc host 句柄 +** +** 输　出: 无 +** +** 全局变量: +** 调用模块: 无 ** ********************************************************************************************************/ static void init_mmcsd_host(struct mmc_dm365_host *host) { - mmc_dm365_reset_ctrl(host, 1); + mmc_dm365_reset_ctrl(host, 1); - host->mmcsd_regs->MMCCLK = 0; - host->mmcsd_regs->MMCCLK = MMCCLK_CLKEN; + host->mmcsd_regs->MMCCLK = 0; + host->mmcsd_regs->MMCCLK = MMCCLK_CLKEN; - host->mmcsd_regs->MMCTOR = 0x1FFF; - host->mmcsd_regs->MMCTOD = 0xFFFF; - - mmc_dm365_reset_ctrl(host, 0); + host->mmcsd_regs->MMCTOR = 0x1FFF; + host->mmcsd_regs->MMCTOD = 0xFFFF; + + mmc_dm365_reset_ctrl(host, 0); } /******************************************************************************************************* -** : mmc_dm365_cmd_done() -** : SD ô˺ -** -** 䡡: host -> DM365 mmc host -** cmd -> SD ṹ +** 函数名称: mmc_dm365_cmd_done() +** 功能描述: 结束SD 命令后调用此函数 ** -** 䡡: -** -** ȫֱ: -** ģ: +** 输　入: host -> DM365 mmc host 句柄 +** cmd -> SD 命令结构句柄 +** +** 输　出: 无 +** +** 全局变量: +** 调用模块: 无 ** ********************************************************************************************************/ static void mmc_dm365_cmd_done(struct mmc_dm365_host *host, struct rt_mmcsd_cmd *cmd) { - host->cmd = RT_NULL; + host->cmd = RT_NULL; - if (resp_type(cmd) != RESP_NONE) - { - if (resp_type(cmd) == RESP_R2) - { - /* response type 2 */ - cmd->resp[3] = host->mmcsd_regs->MMCRSP01; - cmd->resp[2] = host->mmcsd_regs->MMCRSP23; - cmd->resp[1] = host->mmcsd_regs->MMCRSP45; - cmd->resp[0] = host->mmcsd_regs->MMCRSP67; - } - else - { - /* response types 1, 1b, 3, 4, 5, 6 */ - cmd->resp[0] = host->mmcsd_regs->MMCRSP67; - } - } + if (resp_type(cmd) != RESP_NONE) + { + if (resp_type(cmd) == RESP_R2) + { + /* response type 2 */ + cmd->resp[3] = host->mmcsd_regs->MMCRSP01; + cmd->resp[2] = host->mmcsd_regs->MMCRSP23; + cmd->resp[1] = host->mmcsd_regs->MMCRSP45; + cmd->resp[0] = host->mmcsd_regs->MMCRSP67; + } + else + { + /* response types 1, 1b, 3, 4, 5, 6 */ + cmd->resp[0] = host->mmcsd_regs->MMCRSP67; + } + } - if (host->data == RT_NULL || cmd->err) - { - if (cmd->err == -RT_ETIMEOUT) - cmd->mrq->cmd->retries = 0; - mmc_request_done(host->mmc, cmd->mrq); - host->mmcsd_regs->MMCIM = 0; - } + if (host->data == RT_NULL || cmd->err) + { + if (cmd->err == -RT_ETIMEOUT) + cmd->mrq->cmd->retries = 0; + mmc_request_done(host->mmc, cmd->mrq); + host->mmcsd_regs->MMCIM = 0; + } } /******************************************************************************************************* -** : dm365_abort_data() -** : ˺ֹݴ -** -** 䡡: host -> DM365 mmc host -** data -> data ṹ +** 函数名称: dm365_abort_data() +** 功能描述: 此函数用于终止数据传输 ** -** 䡡: -** -** ȫֱ: -** ģ: +** 输　入: host -> DM365 mmc host 句柄 +** data -> data 结构句柄 +** +** 输　出: 无 +** +** 全局变量: +** 调用模块: 无 ** ********************************************************************************************************/ static void dm365_abort_data(struct mmc_dm365_host *host, struct rt_mmcsd_data *data) { - mmc_dm365_reset_ctrl(host, 1); - mmc_dm365_reset_ctrl(host, 0); + mmc_dm365_reset_ctrl(host, 1); + mmc_dm365_reset_ctrl(host, 0); } static void mmc_dm365_sdio_irq(int irq, void *param) { - struct mmc_dm365_host *host = (struct mmc_dm365_host *)param; - rt_uint32_t status; + struct mmc_dm365_host *host = (struct mmc_dm365_host *)param; + rt_uint32_t status; - status = host->mmcsd_regs->SDIOIST;//readl(host->base + DAVINCI_SDIOIST); - if (status & SDIOIST_IOINT) { - mmc_dbg("SDIO interrupt status %x\n", status); - //writel(status | SDIOIST_IOINT, host->base + DAVINCI_SDIOIST); - host->mmcsd_regs->SDIOIST = status | SDIOIST_IOINT; - sdio_irq_wakeup(host->mmc); - } + status = host->mmcsd_regs->SDIOIST;//readl(host->base + DAVINCI_SDIOIST); + if (status & SDIOIST_IOINT) { + mmc_dbg("SDIO interrupt status %x\n", status); + //writel(status | SDIOIST_IOINT, host->base + DAVINCI_SDIOIST); + host->mmcsd_regs->SDIOIST = status | SDIOIST_IOINT; + sdio_irq_wakeup(host->mmc); + } } /******************************************************************************************************* -** : mmc_dm365_irq() -** : MMCSDжϴ -** -** 䡡: irq ->ж +** 函数名称: mmc_dm365_irq() +** 功能描述: MMCSD的中断处理程序 ** -** 䡡: -** -** ȫֱ: -** ģ: +** 输　入: irq ->中断向量号 +** +** 输　出: 无 +** +** 全局变量: +** 调用模块: 无 ** ********************************************************************************************************/ static void mmc_dm365_irq(int irq, void *param) { - struct mmc_dm365_host *host = (struct mmc_dm365_host *)param; - rt_uint32_t status, qstatus; - int end_command = 0; - int end_transfer = 0; - struct rt_mmcsd_data *data = host->data; + struct mmc_dm365_host *host = (struct mmc_dm365_host *)param; + rt_uint32_t status, qstatus; + int end_command = 0; + int end_transfer = 0; + struct rt_mmcsd_data *data = host->data; - if (host->cmd == RT_NULL && host->data == RT_NULL) - { - status = host->mmcsd_regs->MMCST0; - mmc_dbg("Spurious interrupt 0x%04x\n", status); - /* Disable the interrupt from mmcsd */ - host->mmcsd_regs->MMCIM = 0; - return; - } + if (host->cmd == RT_NULL && host->data == RT_NULL) + { + status = host->mmcsd_regs->MMCST0; + mmc_dbg("Spurious interrupt 0x%04x\n", status); + /* Disable the interrupt from mmcsd */ + host->mmcsd_regs->MMCIM = 0; + return; + } - status = host->mmcsd_regs->MMCST0; - qstatus = status; - - /* handle FIFO first when using PIO for data. - * bytes_left will decrease to zero as I/O progress and status will - * read zero over iteration because this controller status - * register(MMCST0) reports any status only once and it is cleared - * by read. So, it is not unbouned loop even in the case of - * non-dma. - */ - while (host->bytes_left && (status & (MMCST0_DXRDY | MMCST0_DRRDY))) - { - dm365_fifo_data_trans(host, rw_threshold); - status = host->mmcsd_regs->MMCST0; - if (!status) - break; - qstatus |= status; - } + status = host->mmcsd_regs->MMCST0; + qstatus = status; - if (qstatus & MMCST0_DATDNE) - { - /* All blocks sent/received, and CRC checks passed */ - if (data != RT_NULL) - { - if ((host->do_dma == RT_FALSE) && (host->bytes_left > 0)) - { - /* if datasize < rw_threshold - * no RX ints are generated - */ - rt_kprintf("to do! host->bytes_left=0x%x\n", host->bytes_left); - dm365_fifo_data_trans(host, host->bytes_left); - } - end_transfer = 1; - data->bytes_xfered = data->blks* data->blksize; - } - else - { - mmc_dbg("DATDNE with no host->data\n"); - } - } + /* handle FIFO first when using PIO for data. + * bytes_left will decrease to zero as I/O progress and status will + * read zero over iteration because this controller status + * register(MMCST0) reports any status only once and it is cleared + * by read. So, it is not unbouned loop even in the case of + * non-dma. + */ + while (host->bytes_left && (status & (MMCST0_DXRDY | MMCST0_DRRDY))) + { + dm365_fifo_data_trans(host, rw_threshold); + status = host->mmcsd_regs->MMCST0; + if (!status) + break; + qstatus |= status; + } - if (qstatus & MMCST0_TOUTRD) - { - /* Read data timeout */ - data->err = -RT_ETIMEOUT; - end_transfer = 1; + if (qstatus & MMCST0_DATDNE) + { + /* All blocks sent/received, and CRC checks passed */ + if (data != RT_NULL) + { + if ((host->do_dma == RT_FALSE) && (host->bytes_left > 0)) + { + /* if datasize < rw_threshold + * no RX ints are generated + */ + rt_kprintf("to do! host->bytes_left=0x%x\n", host->bytes_left); + dm365_fifo_data_trans(host, host->bytes_left); + } + end_transfer = 1; + data->bytes_xfered = data->blks* data->blksize; + } + else + { + mmc_dbg("DATDNE with no host->data\n"); + } + } - mmc_dbg("read data timeout, status %x\n", qstatus); - rt_kprintf("read data timeout, status %x\n", qstatus); + if (qstatus & MMCST0_TOUTRD) + { + /* Read data timeout */ + data->err = -RT_ETIMEOUT; + end_transfer = 1; - dm365_abort_data(host, data); - } + mmc_dbg("read data timeout, status %x\n", qstatus); + rt_kprintf("read data timeout, status %x\n", qstatus); - if (qstatus & (MMCST0_CRCWR | MMCST0_CRCRD)) - { - /* Data CRC error */ - data->err = -RT_ERROR; - end_transfer = 1; + dm365_abort_data(host, data); + } - /* NOTE: this controller uses CRCWR to report both CRC - * errors and timeouts (on writes). MMCDRSP values are - * only weakly documented, but 0x9f was clearly a timeout - * case and the two three-bit patterns in various SD specs - * (101, 010) aren't part of it ... - */ - if (qstatus & MMCST0_CRCWR) - { - rt_uint32_t temp = host->mmcsd_regs->MMCDRSP; + if (qstatus & (MMCST0_CRCWR | MMCST0_CRCRD)) + { + /* Data CRC error */ + data->err = -RT_ERROR; + end_transfer = 1; - if (temp == 0x9f) - data->err = -RT_ETIMEOUT; - } - mmc_dbg("data %s %s error\n", (qstatus & MMCST0_CRCWR) ? "write" : "read", (data->err == -110) ? "timeout" : "CRC"); + /* NOTE: this controller uses CRCWR to report both CRC + * errors and timeouts (on writes). MMCDRSP values are + * only weakly documented, but 0x9f was clearly a timeout + * case and the two three-bit patterns in various SD specs + * (101, 010) aren't part of it ... + */ + if (qstatus & MMCST0_CRCWR) + { + rt_uint32_t temp = host->mmcsd_regs->MMCDRSP; - rt_kprintf("data %s %s error\n", (qstatus & MMCST0_CRCWR) ? "write" : "read", (data->err == -110) ? "timeout" : "CRC"); + if (temp == 0x9f) + data->err = -RT_ETIMEOUT; + } + mmc_dbg("data %s %s error\n", (qstatus & MMCST0_CRCWR) ? "write" : "read", (data->err == -110) ? "timeout" : "CRC"); - dm365_abort_data(host, data); - } + rt_kprintf("data %s %s error\n", (qstatus & MMCST0_CRCWR) ? "write" : "read", (data->err == -110) ? "timeout" : "CRC"); - if (qstatus & MMCST0_TOUTRS) - { - /* Command timeout */ - if (host->cmd) - { - mmc_dbg("CMD%d timeout, status %x\n", host->cmd->cmd_code, qstatus); - host->cmd->err = -RT_ETIMEOUT; - if (data) - { - end_transfer = 1; - dm365_abort_data(host, data); - } - else - end_command = 1; - } - } + dm365_abort_data(host, data); + } - if (qstatus & MMCST0_CRCRS) - { - /* Command CRC error */ - mmc_dbg("Command CRC error\n"); - if (host->cmd) - { - host->cmd->err = -RT_ERROR; - end_command = 1; - } - } + if (qstatus & MMCST0_TOUTRS) + { + /* Command timeout */ + if (host->cmd) + { + mmc_dbg("CMD%d timeout, status %x\n", host->cmd->cmd_code, qstatus); + host->cmd->err = -RT_ETIMEOUT; + if (data) + { + end_transfer = 1; + dm365_abort_data(host, data); + } + else + end_command = 1; + } + } - if (qstatus & MMCST0_RSPDNE) - { - /* End of command phase */ - end_command = (int) host->cmd; - } + if (qstatus & MMCST0_CRCRS) + { + /* Command CRC error */ + mmc_dbg("Command CRC error\n"); + if (host->cmd) + { + host->cmd->err = -RT_ERROR; + end_command = 1; + } + } - if (end_command) - mmc_dm365_cmd_done(host, host->cmd); - if (end_transfer) - mmc_dm365_xfer_done(host, data); + if (qstatus & MMCST0_RSPDNE) + { + /* End of command phase */ + end_command = (int) host->cmd; + } - return; + if (end_command) + mmc_dm365_cmd_done(host, host->cmd); + if (end_transfer) + mmc_dm365_xfer_done(host, data); + + return; } #if 0 /******************************************************************************************************* -** : rt_hw_edma_init() -** : ˺ڳʼEDMA3 -** -** 䡡: +** 函数名称: rt_hw_edma_init() +** 功能描述: 此函数用于初始化EDMA3 ** -** 䡡: -** -** ȫֱ: -** ģ: +** 输　入: 无 +** +** 输　出: 无 +** +** 全局变量: +** 调用模块: 无 ** ********************************************************************************************************/ static void rt_hw_edma_init(void) { - psc_transition(PSC0, DOMAIN0, LPSC_TPCC, PSC_ENABLE); - psc_transition(PSC0, DOMAIN0, LPSC_TPTC0, PSC_ENABLE); + psc_transition(PSC0, DOMAIN0, LPSC_TPCC, PSC_ENABLE); + psc_transition(PSC0, DOMAIN0, LPSC_TPTC0, PSC_ENABLE); - /* Initialization of EDMA3 */ + /* Initialization of EDMA3 */ edma3_init(EDMA0CC0_REG_BASE, EVT_QUEUE_NUM); - + /* Register EDMA3 Interrupts */ -// ConfigureAINTCIntEDMA3(); +// ConfigureAINTCIntEDMA3(); } #endif /******************************************************************************************************* -** : rt_hw_mmcsd_init() -** : ˺ڳʼMMCģ -** -** 䡡: +** 函数名称: rt_hw_mmcsd_init() +** 功能描述: 此函数用于初始化MMC驱动模块 ** -** 䡡: ʼɹ0ʼʧܣ-RT_ENOMEM -** -** ȫֱ: -** ģ: +** 输　入: 无 +** +** 输　出: 如果初始化成功，返回0；如果初始化失败，返回-RT_ENOMEM +** +** 全局变量: +** 调用模块: 无 ** ********************************************************************************************************/ int rt_hw_mmcsd_init(void) { - struct clk *clk; - struct mmc_dm365_host *dm365_host; - struct rt_mmcsd_host *mmc = RT_NULL; + struct clk *clk; + struct mmc_dm365_host *dm365_host; + struct rt_mmcsd_host *mmc = RT_NULL; - mmc = mmcsd_alloc_host(); - if (!mmc) - { - mmc_dbg("alloc mmc failed\n"); - return -RT_ERROR; - } + mmc = mmcsd_alloc_host(); + if (!mmc) + { + mmc_dbg("alloc mmc failed\n"); + return -RT_ERROR; + } - dm365_host = rt_malloc(sizeof(struct mmc_dm365_host)); - if (!dm365_host) - { - mmc_dbg("alloc mci failed\n"); - goto err; - } + dm365_host = rt_malloc(sizeof(struct mmc_dm365_host)); + if (!dm365_host) + { + mmc_dbg("alloc mci failed\n"); + goto err; + } - rt_memset(dm365_host, 0, sizeof(struct mmc_dm365_host)); + rt_memset(dm365_host, 0, sizeof(struct mmc_dm365_host)); #ifdef RT_USING_MMCSD0 - //psc_transition(PSC0, DOMAIN0, LPSC_MMCSD0, PSC_ENABLE); - //pinmux_config(PINMUX_MMCSD0_REG, PINMUX_MMCSD0_MASK, PINMUX_MMCSD0_VAL); - psc_change_state(DAVINCI_DM365_LPSC_MMC_SD0, PSC_ENABLE); - dm365_host->mmcsd_regs = (mmcsd_regs_t *)DM365_MMC_SD0_BASE; + //psc_transition(PSC0, DOMAIN0, LPSC_MMCSD0, PSC_ENABLE); + //pinmux_config(PINMUX_MMCSD0_REG, PINMUX_MMCSD0_MASK, PINMUX_MMCSD0_VAL); + psc_change_state(DAVINCI_DM365_LPSC_MMC_SD0, PSC_ENABLE); + dm365_host->mmcsd_regs = (mmcsd_regs_t *)DM365_MMC_SD0_BASE; #else #ifdef RT_USING_MMCSD1 - psc_transition(PSC1, DOMAIN0, LPSC_MMCSD1, PSC_ENABLE); - pinmux_config(PINMUX_MMCSD1_REG, PINMUX_MMCSD1_MASK, PINMUX_MMCSD1_VAL); - dm365_host->mmcsd_regs = MMCSD1; + psc_transition(PSC1, DOMAIN0, LPSC_MMCSD1, PSC_ENABLE); + pinmux_config(PINMUX_MMCSD1_REG, PINMUX_MMCSD1_MASK, PINMUX_MMCSD1_VAL); + dm365_host->mmcsd_regs = MMCSD1; #endif #endif - //rt_hw_edma_init(); + //rt_hw_edma_init(); - clk = clk_get("MMCSDCLK0"); - dm365_host->mmc_input_clk = clk_get_rate(clk); - dm365_host->rxdma = DM365_DMA_MMC0RXEVT; - dm365_host->txdma = DM365_DMA_MMC0TXEVT; - dm365_host->use_dma = use_dma; - if ((dm365_host->use_dma == RT_TRUE)&& acquire_dma_channels(dm365_host) != 0) - { - dm365_host->use_dma = RT_FALSE; - } - else - { - dm365_host->dma_buffer = (rt_uint8_t*)rt_malloc_align(64*1024, 32); - if (dm365_host->dma_buffer == RT_NULL) - dm365_host->use_dma = RT_FALSE; - } + clk = clk_get("MMCSDCLK0"); + dm365_host->mmc_input_clk = clk_get_rate(clk); + dm365_host->rxdma = DM365_DMA_MMC0RXEVT; + dm365_host->txdma = DM365_DMA_MMC0TXEVT; + dm365_host->use_dma = use_dma; + if ((dm365_host->use_dma == RT_TRUE)&& acquire_dma_channels(dm365_host) != 0) + { + dm365_host->use_dma = RT_FALSE; + } + else + { + dm365_host->dma_buffer = (rt_uint8_t*)rt_malloc_align(64*1024, 32); + if (dm365_host->dma_buffer == RT_NULL) + dm365_host->use_dma = RT_FALSE; + } - mmc->ops = &mmc_dm365_ops; - mmc->freq_min = 312500; - mmc->freq_max = 25000000; - mmc->valid_ocr = VDD_32_33 | VDD_33_34; - mmc->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE; - mmc->flags |= MMCSD_SUP_SDIO_IRQ; + mmc->ops = &mmc_dm365_ops; + mmc->freq_min = 312500; + mmc->freq_max = 25000000; + mmc->valid_ocr = VDD_32_33 | VDD_33_34; + mmc->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE; + mmc->flags |= MMCSD_SUP_SDIO_IRQ; - dm365_host->mmc = mmc; - mmc->private_data = dm365_host; + dm365_host->mmc = mmc; + mmc->private_data = dm365_host; - /* install interrupt */ + /* install interrupt */ #ifdef RT_USING_MMCSD0 - rt_hw_interrupt_install(IRQ_DM3XX_MMCINT0, mmc_dm365_irq, - (void *)dm365_host, "MMC0"); - rt_hw_interrupt_umask(IRQ_DM3XX_MMCINT0); - rt_hw_interrupt_install(IRQ_DM3XX_SDIOINT0, mmc_dm365_sdio_irq, - (void *)dm365_host, "SDIO0"); - rt_hw_interrupt_umask(IRQ_DM3XX_SDIOINT0); + rt_hw_interrupt_install(IRQ_DM3XX_MMCINT0, mmc_dm365_irq, + (void *)dm365_host, "MMC0"); + rt_hw_interrupt_umask(IRQ_DM3XX_MMCINT0); + rt_hw_interrupt_install(IRQ_DM3XX_SDIOINT0, mmc_dm365_sdio_irq, + (void *)dm365_host, "SDIO0"); + rt_hw_interrupt_umask(IRQ_DM3XX_SDIOINT0); #endif #ifdef RT_USING_MMCSD1 - rt_hw_interrupt_install(MMCSD_INT1, mmc_dm365_irq, - (void *)dm365_host, "MMC1"); - rt_hw_interrupt_umask(MMCSD_INT1); + rt_hw_interrupt_install(MMCSD_INT1, mmc_dm365_irq, + (void *)dm365_host, "MMC1"); + rt_hw_interrupt_umask(MMCSD_INT1); #endif - init_mmcsd_host(dm365_host); + init_mmcsd_host(dm365_host); - mmcsd_change(mmc); + mmcsd_change(mmc); - return 0; + return 0; err: - mmcsd_free_host(mmc); + mmcsd_free_host(mmc); - return -RT_ENOMEM; + return -RT_ENOMEM; } INIT_DEVICE_EXPORT(rt_hw_mmcsd_init); diff --git a/bsp/dm365/drivers/mmcsd.h b/bsp/dm365/drivers/mmcsd.h index 71fb93649d..812b44a72e 100644 --- a/bsp/dm365/drivers/mmcsd.h +++ b/bsp/dm365/drivers/mmcsd.h @@ -1,25 +1,11 @@ /* - * File : mmcsd.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version + * Date Author Notes + * 2011-01-13 weety first version */ #ifndef __DAVINCI_MMC_H__ @@ -44,18 +30,18 @@ #define MMCCLK_CLKRT_MASK (0xFF << 0) /* IRQ bit definitions, for DAVINCI_MMCST0 and DAVINCI_MMCIM */ -#define MMCST0_DATDNE (1 << 0) /* data done */ -#define MMCST0_BSYDNE (1 << 1) /* busy done */ -#define MMCST0_RSPDNE (1 << 2) /* command done */ -#define MMCST0_TOUTRD (1 << 3) /* data read timeout */ -#define MMCST0_TOUTRS (1 << 4) /* command response timeout */ -#define MMCST0_CRCWR (1 << 5) /* data write CRC error */ -#define MMCST0_CRCRD (1 << 6) /* data read CRC error */ -#define MMCST0_CRCRS (1 << 7) /* command response CRC error */ -#define MMCST0_DXRDY (1 << 9) /* data transmit ready (fifo empty) */ -#define MMCST0_DRRDY (1 << 10) /* data receive ready (data in fifo)*/ -#define MMCST0_DATED (1 << 11) /* DAT3 edge detect */ -#define MMCST0_TRNDNE (1 << 12) /* transfer done */ +#define MMCST0_DATDNE (1 << 0) /* data done */ +#define MMCST0_BSYDNE (1 << 1) /* busy done */ +#define MMCST0_RSPDNE (1 << 2) /* command done */ +#define MMCST0_TOUTRD (1 << 3) /* data read timeout */ +#define MMCST0_TOUTRS (1 << 4) /* command response timeout */ +#define MMCST0_CRCWR (1 << 5) /* data write CRC error */ +#define MMCST0_CRCRD (1 << 6) /* data read CRC error */ +#define MMCST0_CRCRS (1 << 7) /* command response CRC error */ +#define MMCST0_DXRDY (1 << 9) /* data transmit ready (fifo empty) */ +#define MMCST0_DRRDY (1 << 10) /* data receive ready (data in fifo)*/ +#define MMCST0_DATED (1 << 11) /* DAT3 edge detect */ +#define MMCST0_TRNDNE (1 << 12) /* transfer done */ /* DAVINCI_MMCST1 definitions */ #define MMCST1_BUSY (1 << 0) @@ -100,44 +86,44 @@ #define SDIOIST_RWS (1 << 1) /* MMCSD Init clock in Hz in opendrain mode */ -#define MMCSD_INIT_CLOCK 200000 +#define MMCSD_INIT_CLOCK 200000 -#define MAX_CCNT ((1 << 16) - 1) +#define MAX_CCNT ((1 << 16) - 1) -#define MAX_NR_SG 16 +#define MAX_NR_SG 16 -#define MMC_DATA_WRITE (1 << 8) -#define MMC_DATA_READ (1 << 9) -#define MMC_DATA_STREAM (1 << 10) +#define MMC_DATA_WRITE (1 << 8) +#define MMC_DATA_READ (1 << 9) +#define MMC_DATA_STREAM (1 << 10) typedef struct { - volatile rt_uint32_t MMCCTL; - volatile rt_uint32_t MMCCLK; - volatile rt_uint32_t MMCST0; - volatile rt_uint32_t MMCST1; - volatile rt_uint32_t MMCIM; - volatile rt_uint32_t MMCTOR; - volatile rt_uint32_t MMCTOD; - volatile rt_uint32_t MMCBLEN; - volatile rt_uint32_t MMCNBLK; - volatile rt_uint32_t MMCNBLC; - volatile rt_uint32_t MMCDRR; - volatile rt_uint32_t MMCDXR; - volatile rt_uint32_t MMCCMD; - volatile rt_uint32_t MMCARGHL; - volatile rt_uint32_t MMCRSP01; - volatile rt_uint32_t MMCRSP23; - volatile rt_uint32_t MMCRSP45; - volatile rt_uint32_t MMCRSP67; - volatile rt_uint32_t MMCDRSP; - volatile rt_uint32_t reserved0; - volatile rt_uint32_t MMCCIDX; - volatile rt_uint32_t reserved1[4]; - volatile rt_uint32_t SDIOCTL; - volatile rt_uint32_t SDIOST0; - volatile rt_uint32_t SDIOIEN; - volatile rt_uint32_t SDIOIST; - volatile rt_uint32_t MMCFIFOCTL; + volatile rt_uint32_t MMCCTL; + volatile rt_uint32_t MMCCLK; + volatile rt_uint32_t MMCST0; + volatile rt_uint32_t MMCST1; + volatile rt_uint32_t MMCIM; + volatile rt_uint32_t MMCTOR; + volatile rt_uint32_t MMCTOD; + volatile rt_uint32_t MMCBLEN; + volatile rt_uint32_t MMCNBLK; + volatile rt_uint32_t MMCNBLC; + volatile rt_uint32_t MMCDRR; + volatile rt_uint32_t MMCDXR; + volatile rt_uint32_t MMCCMD; + volatile rt_uint32_t MMCARGHL; + volatile rt_uint32_t MMCRSP01; + volatile rt_uint32_t MMCRSP23; + volatile rt_uint32_t MMCRSP45; + volatile rt_uint32_t MMCRSP67; + volatile rt_uint32_t MMCDRSP; + volatile rt_uint32_t reserved0; + volatile rt_uint32_t MMCCIDX; + volatile rt_uint32_t reserved1[4]; + volatile rt_uint32_t SDIOCTL; + volatile rt_uint32_t SDIOST0; + volatile rt_uint32_t SDIOIEN; + volatile rt_uint32_t SDIOIST; + volatile rt_uint32_t MMCFIFOCTL; }mmcsd_regs_t; extern int rt_hw_mmcsd_init(void); diff --git a/bsp/dm365/drivers/spi-davinci.c b/bsp/dm365/drivers/spi-davinci.c index fb5d9729d4..35de558e14 100644 --- a/bsp/dm365/drivers/spi-davinci.c +++ b/bsp/dm365/drivers/spi-davinci.c @@ -1,25 +1,11 @@ /* - * File : spi-davinci.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version + * Date Author Notes + * 2011-01-13 weety first version */ #include @@ -34,13 +20,13 @@ #define barrier() __asm__ __volatile__("": : :"memory") #define cpu_relax() barrier() -#define SPI_DEBUG 0 +#define SPI_DEBUG 0 #if SPI_DEBUG #define spi_dbg(dev, fmt, ...) \ - do { \ - rt_kprintf("%s:", dev->parent.name); \ - rt_kprintf(fmt, ##__VA_ARGS__); \ - } while(0) + do { \ + rt_kprintf("%s:", dev->parent.name); \ + rt_kprintf(fmt, ##__VA_ARGS__); \ + } while(0) #else #define spi_dbg(dev, fmt, ...) #endif @@ -48,50 +34,50 @@ #define SZ_64K 0x10000 #define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) -#define SPI_NO_RESOURCE ((resource_size_t)-1) +#define SPI_NO_RESOURCE ((resource_size_t)-1) -#define SPI_MAX_CHIPSELECT 2 +#define SPI_MAX_CHIPSELECT 2 -#define CS_DEFAULT 0xFF +#define CS_DEFAULT 0xFF #define __iomem -#define BIT(nr) (1UL << (nr)) +#define BIT(nr) (1UL << (nr)) -#define SPIFMT_PHASE_MASK BIT(16) -#define SPIFMT_POLARITY_MASK BIT(17) -#define SPIFMT_DISTIMER_MASK BIT(18) -#define SPIFMT_SHIFTDIR_MASK BIT(20) -#define SPIFMT_WAITENA_MASK BIT(21) -#define SPIFMT_PARITYENA_MASK BIT(22) -#define SPIFMT_ODD_PARITY_MASK BIT(23) -#define SPIFMT_WDELAY_MASK 0x3f000000u -#define SPIFMT_WDELAY_SHIFT 24 -#define SPIFMT_PRESCALE_SHIFT 8 +#define SPIFMT_PHASE_MASK BIT(16) +#define SPIFMT_POLARITY_MASK BIT(17) +#define SPIFMT_DISTIMER_MASK BIT(18) +#define SPIFMT_SHIFTDIR_MASK BIT(20) +#define SPIFMT_WAITENA_MASK BIT(21) +#define SPIFMT_PARITYENA_MASK BIT(22) +#define SPIFMT_ODD_PARITY_MASK BIT(23) +#define SPIFMT_WDELAY_MASK 0x3f000000u +#define SPIFMT_WDELAY_SHIFT 24 +#define SPIFMT_PRESCALE_SHIFT 8 /* SPIPC0 */ -#define SPIPC0_DIFUN_MASK BIT(11) /* MISO */ -#define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */ -#define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */ -#define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */ +#define SPIPC0_DIFUN_MASK BIT(11) /* MISO */ +#define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */ +#define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */ +#define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */ -#define SPIINT_MASKALL 0x0101035F -#define SPIINT_MASKINT 0x0000015F -#define SPI_INTLVL_1 0x000001FF -#define SPI_INTLVL_0 0x00000000 +#define SPIINT_MASKALL 0x0101035F +#define SPIINT_MASKINT 0x0000015F +#define SPI_INTLVL_1 0x000001FF +#define SPI_INTLVL_0 0x00000000 /* SPIDAT1 (upper 16 bit defines) */ -#define SPIDAT1_CSHOLD_MASK BIT(12) +#define SPIDAT1_CSHOLD_MASK BIT(12) /* SPIGCR1 */ -#define SPIGCR1_CLKMOD_MASK BIT(1) +#define SPIGCR1_CLKMOD_MASK BIT(1) #define SPIGCR1_MASTER_MASK BIT(0) -#define SPIGCR1_POWERDOWN_MASK BIT(8) -#define SPIGCR1_LOOPBACK_MASK BIT(16) -#define SPIGCR1_SPIENA_MASK BIT(24) +#define SPIGCR1_POWERDOWN_MASK BIT(8) +#define SPIGCR1_LOOPBACK_MASK BIT(16) +#define SPIGCR1_SPIENA_MASK BIT(24) /* SPIBUF */ -#define SPIBUF_TXFULL_MASK BIT(29) -#define SPIBUF_RXEMPTY_MASK BIT(31) +#define SPIBUF_TXFULL_MASK BIT(29) +#define SPIBUF_RXEMPTY_MASK BIT(31) /* SPIDELAY */ #define SPIDELAY_C2TDELAY_SHIFT 24 @@ -104,67 +90,67 @@ #define SPIDELAY_C2EDELAY_MASK 0xFF /* Error Masks */ -#define SPIFLG_DLEN_ERR_MASK BIT(0) -#define SPIFLG_TIMEOUT_MASK BIT(1) -#define SPIFLG_PARERR_MASK BIT(2) -#define SPIFLG_DESYNC_MASK BIT(3) -#define SPIFLG_BITERR_MASK BIT(4) -#define SPIFLG_OVRRUN_MASK BIT(6) -#define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24) -#define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \ - | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \ - | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \ - | SPIFLG_OVRRUN_MASK) +#define SPIFLG_DLEN_ERR_MASK BIT(0) +#define SPIFLG_TIMEOUT_MASK BIT(1) +#define SPIFLG_PARERR_MASK BIT(2) +#define SPIFLG_DESYNC_MASK BIT(3) +#define SPIFLG_BITERR_MASK BIT(4) +#define SPIFLG_OVRRUN_MASK BIT(6) +#define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24) +#define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \ + | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \ + | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \ + | SPIFLG_OVRRUN_MASK) -#define SPIINT_DMA_REQ_EN BIT(16) +#define SPIINT_DMA_REQ_EN BIT(16) /* SPI Controller registers */ -#define SPIGCR0 0x00 -#define SPIGCR1 0x04 -#define SPIINT 0x08 -#define SPILVL 0x0c -#define SPIFLG 0x10 -#define SPIPC0 0x14 -#define SPIDAT1 0x3c -#define SPIBUF 0x40 -#define SPIDELAY 0x48 -#define SPIDEF 0x4c -#define SPIFMT0 0x50 +#define SPIGCR0 0x00 +#define SPIGCR1 0x04 +#define SPIINT 0x08 +#define SPILVL 0x0c +#define SPIFLG 0x10 +#define SPIPC0 0x14 +#define SPIDAT1 0x3c +#define SPIBUF 0x40 +#define SPIDELAY 0x48 +#define SPIDEF 0x4c +#define SPIFMT0 0x50 /* We have 2 DMA channels per CS, one for RX and one for TX */ struct davinci_spi_dma { - int tx_channel; - int rx_channel; - int dummy_param_slot; - enum dma_event_q eventq; + int tx_channel; + int rx_channel; + int dummy_param_slot; + enum dma_event_q eventq; }; /* SPI Controller driver's private data. */ struct davinci_spi { - struct rt_spi_bus parent; - struct clk *clk; + struct rt_spi_bus parent; + struct clk *clk; - u8 version; - void __iomem *base; - u32 irq; - struct rt_completion done; + u8 version; + void __iomem *base; + u32 irq; + struct rt_completion done; - const void *tx; - void *rx; + const void *tx; + void *rx; #define SMP_CACHE_BYTES 32 -#define SPI_TMP_BUFSZ (SMP_CACHE_BYTES + 1) - u8 rx_tmp_buf[SPI_TMP_BUFSZ]; - int rcount; - int wcount; - struct davinci_spi_dma dma; +#define SPI_TMP_BUFSZ (SMP_CACHE_BYTES + 1) + u8 rx_tmp_buf[SPI_TMP_BUFSZ]; + int rcount; + int wcount; + struct davinci_spi_dma dma; - void (*get_rx)(u32 rx_data, struct davinci_spi *); - u32 (*get_tx)(struct davinci_spi *); + void (*get_rx)(u32 rx_data, struct davinci_spi *); + u32 (*get_tx)(struct davinci_spi *); - u8 bytes_per_word[SPI_MAX_CHIPSELECT]; - u8 chip_sel[SPI_MAX_CHIPSELECT]; - struct davinci_spi_config *controller_data; - int cshold_bug; + u8 bytes_per_word[SPI_MAX_CHIPSELECT]; + u8 chip_sel[SPI_MAX_CHIPSELECT]; + struct davinci_spi_config *controller_data; + int cshold_bug; }; static struct davinci_spi_config davinci_spi_default_cfg; @@ -174,58 +160,58 @@ extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size); static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *dspi) { - if (dspi->rx) { - u8 *rx = dspi->rx; - *rx++ = (u8)data; - dspi->rx = rx; - } + if (dspi->rx) { + u8 *rx = dspi->rx; + *rx++ = (u8)data; + dspi->rx = rx; + } } static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi) { - if (dspi->rx) { - u16 *rx = dspi->rx; - *rx++ = (u16)data; - dspi->rx = rx; - } + if (dspi->rx) { + u16 *rx = dspi->rx; + *rx++ = (u16)data; + dspi->rx = rx; + } } static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi) { - u32 data = 0; - if (dspi->tx) { - const u8 *tx = dspi->tx; - data = *tx++; - dspi->tx = tx; - } - return data; + u32 data = 0; + if (dspi->tx) { + const u8 *tx = dspi->tx; + data = *tx++; + dspi->tx = tx; + } + return data; } static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi) { - u32 data = 0; - if (dspi->tx) { - const u16 *tx = dspi->tx; - data = *tx++; - dspi->tx = tx; - } - return data; + u32 data = 0; + if (dspi->tx) { + const u16 *tx = dspi->tx; + data = *tx++; + dspi->tx = tx; + } + return data; } static inline void set_io_bits(void __iomem *addr, u32 bits) { - u32 v = readl(addr); + u32 v = readl(addr); - v |= bits; - writel(v, addr); + v |= bits; + writel(v, addr); } static inline void clear_io_bits(void __iomem *addr, u32 bits) { - u32 v = readl(addr); + u32 v = readl(addr); - v &= ~bits; - writel(v, addr); + v &= ~bits; + writel(v, addr); } /* @@ -233,39 +219,39 @@ static inline void clear_io_bits(void __iomem *addr, u32 bits) */ static void davinci_spi_chipselect(struct rt_spi_device *spi, int value) { - struct davinci_spi *dspi; - u8 chip_sel = (u8)spi->parent.user_data; - u16 spidat1 = CS_DEFAULT; - bool gpio_chipsel = RT_FALSE; + struct davinci_spi *dspi; + u8 chip_sel = (u8)spi->parent.user_data; + u16 spidat1 = CS_DEFAULT; + bool gpio_chipsel = RT_FALSE; - dspi = spi->bus->parent.user_data; + dspi = spi->bus->parent.user_data; - if (chip_sel < SPI_MAX_CHIPSELECT && - dspi->chip_sel[chip_sel] != SPI_INTERN_CS) - gpio_chipsel = RT_TRUE; + if (chip_sel < SPI_MAX_CHIPSELECT && + dspi->chip_sel[chip_sel] != SPI_INTERN_CS) + gpio_chipsel = RT_TRUE; - /* - * Board specific chip select logic decides the polarity and cs - * line for the controller - */ - if (gpio_chipsel) { - if (value == 0) - gpio_set_value(dspi->chip_sel[chip_sel], 0); - else - gpio_set_value(dspi->chip_sel[chip_sel], 1); - } else { - spidat1 = readw(dspi->base + SPIDAT1 + 2); - if (value == 0) { - spidat1 |= SPIDAT1_CSHOLD_MASK; - spidat1 &= ~(0x1 << chip_sel); - } else { - spidat1 &= ~SPIDAT1_CSHOLD_MASK; - spidat1 |= 0x03; - } - rt_kprintf("0x%04x\n", spidat1); + /* + * Board specific chip select logic decides the polarity and cs + * line for the controller + */ + if (gpio_chipsel) { + if (value == 0) + gpio_set_value(dspi->chip_sel[chip_sel], 0); + else + gpio_set_value(dspi->chip_sel[chip_sel], 1); + } else { + spidat1 = readw(dspi->base + SPIDAT1 + 2); + if (value == 0) { + spidat1 |= SPIDAT1_CSHOLD_MASK; + spidat1 &= ~(0x1 << chip_sel); + } else { + spidat1 &= ~SPIDAT1_CSHOLD_MASK; + spidat1 |= 0x03; + } + rt_kprintf("0x%04x\n", spidat1); - writew(spidat1, dspi->base + SPIDAT1 + 2); - } + writew(spidat1, dspi->base + SPIDAT1 + 2); + } } /** @@ -279,25 +265,25 @@ static void davinci_spi_chipselect(struct rt_spi_device *spi, int value) * or negative error number if valid prescalar cannot be updated. */ static inline int davinci_spi_get_prescale(struct davinci_spi *dspi, - u32 max_speed_hz) + u32 max_speed_hz) { - int ret; + int ret; - ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz); + ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz); - if (ret < 3) { - rt_kprintf("spi clock freq too high\n"); - ret = 3; - } - if (ret > 256) { - rt_kprintf("spi clock freq too litter\n"); - ret = 256; - } + if (ret < 3) { + rt_kprintf("spi clock freq too high\n"); + ret = 3; + } + if (ret > 256) { + rt_kprintf("spi clock freq too litter\n"); + ret = 256; + } - /*if (ret < 3 || ret > 256) - return -RT_ERROR;*/ + /*if (ret < 3 || ret > 256) + return -RT_ERROR;*/ - return ret - 1; + return ret - 1; } /** @@ -310,104 +296,104 @@ static inline int davinci_spi_get_prescale(struct davinci_spi *dspi, * SPI slave device freq. */ static int davinci_spi_setup_transfer(struct rt_spi_device *spi, - struct rt_spi_configuration *cfg) + struct rt_spi_configuration *cfg) { - struct davinci_spi *dspi; - struct davinci_spi_config *spicfg; - u8 bits_per_word = 0; - u32 hz = 0, spifmt = 0, prescale = 0; - u8 chip_select = (u8)spi->parent.user_data; + struct davinci_spi *dspi; + struct davinci_spi_config *spicfg; + u8 bits_per_word = 0; + u32 hz = 0, spifmt = 0, prescale = 0; + u8 chip_select = (u8)spi->parent.user_data; - dspi = spi->bus->parent.user_data; - spicfg = (struct davinci_spi_config *)dspi->controller_data; - if (!spicfg) - spicfg = &davinci_spi_default_cfg; + dspi = spi->bus->parent.user_data; + spicfg = (struct davinci_spi_config *)dspi->controller_data; + if (!spicfg) + spicfg = &davinci_spi_default_cfg; - bits_per_word = cfg->data_width; - hz = cfg->max_hz; + bits_per_word = cfg->data_width; + hz = cfg->max_hz; - /* - * Assign function pointer to appropriate transfer method - * 8bit, 16bit or 32bit transfer - */ - if (bits_per_word <= 8 && bits_per_word >= 2) { - dspi->get_rx = davinci_spi_rx_buf_u8; - dspi->get_tx = davinci_spi_tx_buf_u8; - dspi->bytes_per_word[chip_select] = 1; - } else if (bits_per_word <= 16 && bits_per_word >= 2) { - dspi->get_rx = davinci_spi_rx_buf_u16; - dspi->get_tx = davinci_spi_tx_buf_u16; - dspi->bytes_per_word[chip_select] = 2; - } else - return -RT_ERROR; + /* + * Assign function pointer to appropriate transfer method + * 8bit, 16bit or 32bit transfer + */ + if (bits_per_word <= 8 && bits_per_word >= 2) { + dspi->get_rx = davinci_spi_rx_buf_u8; + dspi->get_tx = davinci_spi_tx_buf_u8; + dspi->bytes_per_word[chip_select] = 1; + } else if (bits_per_word <= 16 && bits_per_word >= 2) { + dspi->get_rx = davinci_spi_rx_buf_u16; + dspi->get_tx = davinci_spi_tx_buf_u16; + dspi->bytes_per_word[chip_select] = 2; + } else + return -RT_ERROR; - /* Set up SPIFMTn register, unique to this chipselect. */ + /* Set up SPIFMTn register, unique to this chipselect. */ - prescale = davinci_spi_get_prescale(dspi, hz); - if (prescale < 0) - return prescale; + prescale = davinci_spi_get_prescale(dspi, hz); + if (prescale < 0) + return prescale; - spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f); + spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f); - if (!(cfg->mode & RT_SPI_MSB)) - spifmt |= SPIFMT_SHIFTDIR_MASK; + if (!(cfg->mode & RT_SPI_MSB)) + spifmt |= SPIFMT_SHIFTDIR_MASK; - if (cfg->mode & RT_SPI_CPOL) - spifmt |= SPIFMT_POLARITY_MASK; + if (cfg->mode & RT_SPI_CPOL) + spifmt |= SPIFMT_POLARITY_MASK; - if (!(cfg->mode & RT_SPI_CPHA)) - spifmt |= SPIFMT_PHASE_MASK; + if (!(cfg->mode & RT_SPI_CPHA)) + spifmt |= SPIFMT_PHASE_MASK; - /* - * Version 1 hardware supports two basic SPI modes: - * - Standard SPI mode uses 4 pins, with chipselect - * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS) - * (distinct from SPI_3WIRE, with just one data wire; - * or similar variants without MOSI or without MISO) - * - * Version 2 hardware supports an optional handshaking signal, - * so it can support two more modes: - * - 5 pin SPI variant is standard SPI plus SPI_READY - * - 4 pin with enable is (SPI_READY | SPI_NO_CS) - */ + /* + * Version 1 hardware supports two basic SPI modes: + * - Standard SPI mode uses 4 pins, with chipselect + * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS) + * (distinct from SPI_3WIRE, with just one data wire; + * or similar variants without MOSI or without MISO) + * + * Version 2 hardware supports an optional handshaking signal, + * so it can support two more modes: + * - 5 pin SPI variant is standard SPI plus SPI_READY + * - 4 pin with enable is (SPI_READY | SPI_NO_CS) + */ - if (dspi->version == SPI_VERSION_2) { + if (dspi->version == SPI_VERSION_2) { - u32 delay = 0; + u32 delay = 0; - spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT) - & SPIFMT_WDELAY_MASK); + spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT) + & SPIFMT_WDELAY_MASK); - if (spicfg->odd_parity) - spifmt |= SPIFMT_ODD_PARITY_MASK; + if (spicfg->odd_parity) + spifmt |= SPIFMT_ODD_PARITY_MASK; - if (spicfg->parity_enable) - spifmt |= SPIFMT_PARITYENA_MASK; + if (spicfg->parity_enable) + spifmt |= SPIFMT_PARITYENA_MASK; - if (spicfg->timer_disable) { - spifmt |= SPIFMT_DISTIMER_MASK; - } else { - delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT) - & SPIDELAY_C2TDELAY_MASK; - delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT) - & SPIDELAY_T2CDELAY_MASK; - } + if (spicfg->timer_disable) { + spifmt |= SPIFMT_DISTIMER_MASK; + } else { + delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT) + & SPIDELAY_C2TDELAY_MASK; + delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT) + & SPIDELAY_T2CDELAY_MASK; + } - if (cfg->mode & RT_SPI_READY) { - spifmt |= SPIFMT_WAITENA_MASK; - delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT) - & SPIDELAY_T2EDELAY_MASK; - delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT) - & SPIDELAY_C2EDELAY_MASK; - } + if (cfg->mode & RT_SPI_READY) { + spifmt |= SPIFMT_WAITENA_MASK; + delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT) + & SPIDELAY_T2EDELAY_MASK; + delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT) + & SPIDELAY_C2EDELAY_MASK; + } - writel(delay, dspi->base + SPIDELAY); - } + writel(delay, dspi->base + SPIDELAY); + } - writel(spifmt, dspi->base + SPIFMT0); + writel(spifmt, dspi->base + SPIFMT0); - return 0; + return 0; } #if 0 @@ -419,73 +405,73 @@ static int davinci_spi_setup_transfer(struct rt_spi_device *spi, */ static int davinci_spi_setup(struct spi_device *spi) { - int retval = 0; - struct davinci_spi *dspi; - struct davinci_spi_platform_data *pdata; + int retval = 0; + struct davinci_spi *dspi; + struct davinci_spi_platform_data *pdata; - dspi = spi_master_get_devdata(spi->master); - pdata = dspi->pdata; + dspi = spi_master_get_devdata(spi->master); + pdata = dspi->pdata; - /* if bits per word length is zero then set it default 8 */ - if (!spi->bits_per_word) - spi->bits_per_word = 8; + /* if bits per word length is zero then set it default 8 */ + if (!spi->bits_per_word) + spi->bits_per_word = 8; - if (!(spi->mode & SPI_NO_CS)) { - if ((pdata->chip_sel == NULL) || - (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS)) - set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select); + if (!(spi->mode & SPI_NO_CS)) { + if ((pdata->chip_sel == NULL) || + (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS)) + set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select); - } + } - if (spi->mode & SPI_READY) - set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK); + if (spi->mode & SPI_READY) + set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK); - if (spi->mode & SPI_LOOP) - set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK); - else - clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK); + if (spi->mode & SPI_LOOP) + set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK); + else + clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK); - return retval; + return retval; } #endif static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status) { - struct rt_device *sdev = &dspi->parent.parent; + struct rt_device *sdev = &dspi->parent.parent; - if (int_status & SPIFLG_TIMEOUT_MASK) { - spi_dbg(sdev, "SPI Time-out Error\n"); - return -RT_ETIMEOUT; - } - if (int_status & SPIFLG_DESYNC_MASK) { - spi_dbg(sdev, "SPI Desynchronization Error\n"); - return -RT_EIO; - } - if (int_status & SPIFLG_BITERR_MASK) { - spi_dbg(sdev, "SPI Bit error\n"); - return -RT_EIO; - } + if (int_status & SPIFLG_TIMEOUT_MASK) { + spi_dbg(sdev, "SPI Time-out Error\n"); + return -RT_ETIMEOUT; + } + if (int_status & SPIFLG_DESYNC_MASK) { + spi_dbg(sdev, "SPI Desynchronization Error\n"); + return -RT_EIO; + } + if (int_status & SPIFLG_BITERR_MASK) { + spi_dbg(sdev, "SPI Bit error\n"); + return -RT_EIO; + } - if (dspi->version == SPI_VERSION_2) { - if (int_status & SPIFLG_DLEN_ERR_MASK) { - spi_dbg(sdev, "SPI Data Length Error\n"); - return -RT_EIO; - } - if (int_status & SPIFLG_PARERR_MASK) { - spi_dbg(sdev, "SPI Parity Error\n"); - return -RT_EIO; - } - if (int_status & SPIFLG_OVRRUN_MASK) { - spi_dbg(sdev, "SPI Data Overrun error\n"); - return -RT_EIO; - } - if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) { - spi_dbg(sdev, "SPI Buffer Init Active\n"); - return -RT_EBUSY; - } - } + if (dspi->version == SPI_VERSION_2) { + if (int_status & SPIFLG_DLEN_ERR_MASK) { + spi_dbg(sdev, "SPI Data Length Error\n"); + return -RT_EIO; + } + if (int_status & SPIFLG_PARERR_MASK) { + spi_dbg(sdev, "SPI Parity Error\n"); + return -RT_EIO; + } + if (int_status & SPIFLG_OVRRUN_MASK) { + spi_dbg(sdev, "SPI Data Overrun error\n"); + return -RT_EIO; + } + if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) { + spi_dbg(sdev, "SPI Buffer Init Active\n"); + return -RT_EBUSY; + } + } - return 0; + return 0; } /** @@ -497,50 +483,50 @@ static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status) */ static int davinci_spi_process_events(struct davinci_spi *dspi) { - u32 buf, status, errors = 0, spidat1; + u32 buf, status, errors = 0, spidat1; - buf = readl(dspi->base + SPIBUF); + buf = readl(dspi->base + SPIBUF); - if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) { - dspi->get_rx(buf & 0xFFFF, dspi); - dspi->rcount--; - } + if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) { + dspi->get_rx(buf & 0xFFFF, dspi); + dspi->rcount--; + } - status = readl(dspi->base + SPIFLG); + status = readl(dspi->base + SPIFLG); - if (unlikely(status & SPIFLG_ERROR_MASK)) { - errors = status & SPIFLG_ERROR_MASK; - goto out; - } + if (unlikely(status & SPIFLG_ERROR_MASK)) { + errors = status & SPIFLG_ERROR_MASK; + goto out; + } - if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) { - spidat1 = readl(dspi->base + SPIDAT1); - dspi->wcount--; - spidat1 &= ~0xFFFF; - spidat1 |= 0xFFFF & dspi->get_tx(dspi); - writel(spidat1, dspi->base + SPIDAT1); - } + if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) { + spidat1 = readl(dspi->base + SPIDAT1); + dspi->wcount--; + spidat1 &= ~0xFFFF; + spidat1 |= 0xFFFF & dspi->get_tx(dspi); + writel(spidat1, dspi->base + SPIDAT1); + } out: - return errors; + return errors; } static void davinci_spi_dma_callback(unsigned lch, u16 status, void *data) { - struct davinci_spi *dspi = data; - struct davinci_spi_dma *dma = &dspi->dma; + struct davinci_spi *dspi = data; + struct davinci_spi_dma *dma = &dspi->dma; - edma_stop(lch); + edma_stop(lch); - if (status == DMA_COMPLETE) { - if (lch == dma->rx_channel) - dspi->rcount = 0; - if (lch == dma->tx_channel) - dspi->wcount = 0; - } + if (status == DMA_COMPLETE) { + if (lch == dma->rx_channel) + dspi->rcount = 0; + if (lch == dma->tx_channel) + dspi->wcount = 0; + } - if ((!dspi->wcount && !dspi->rcount) || (status != DMA_COMPLETE)) - rt_completion_done(&dspi->done); + if ((!dspi->wcount && !dspi->rcount) || (status != DMA_COMPLETE)) + rt_completion_done(&dspi->done); } /** @@ -554,186 +540,186 @@ static void davinci_spi_dma_callback(unsigned lch, u16 status, void *data) */ static int davinci_spi_bufs(struct rt_spi_device *spi, struct rt_spi_message *msg) { - struct davinci_spi *dspi; - int data_type, ret; - u32 tx_data, spidat1; - u32 errors = 0; - struct davinci_spi_config *spicfg; - unsigned rx_buf_count; - struct rt_device *sdev; - u8 chip_select = (u8)spi->parent.user_data; + struct davinci_spi *dspi; + int data_type, ret; + u32 tx_data, spidat1; + u32 errors = 0; + struct davinci_spi_config *spicfg; + unsigned rx_buf_count; + struct rt_device *sdev; + u8 chip_select = (u8)spi->parent.user_data; - dspi = spi->bus->parent.user_data; - spicfg = (struct davinci_spi_config *)dspi->controller_data; - if (!spicfg) - spicfg = &davinci_spi_default_cfg; - sdev = &dspi->parent.parent; + dspi = spi->bus->parent.user_data; + spicfg = (struct davinci_spi_config *)dspi->controller_data; + if (!spicfg) + spicfg = &davinci_spi_default_cfg; + sdev = &dspi->parent.parent; - /* convert len to words based on bits_per_word */ - data_type = dspi->bytes_per_word[chip_select]; + /* convert len to words based on bits_per_word */ + data_type = dspi->bytes_per_word[chip_select]; - dspi->tx = msg->send_buf; - dspi->rx = msg->recv_buf; - dspi->wcount = msg->length / data_type; - dspi->rcount = dspi->wcount; + dspi->tx = msg->send_buf; + dspi->rx = msg->recv_buf; + dspi->wcount = msg->length / data_type; + dspi->rcount = dspi->wcount; - spidat1 = readl(dspi->base + SPIDAT1); + spidat1 = readl(dspi->base + SPIDAT1); - clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); - set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); + clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); + set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); - rt_completion_init(&(dspi->done)); + rt_completion_init(&(dspi->done)); - if (msg->cs_take) - davinci_spi_chipselect(spi, 0); + if (msg->cs_take) + davinci_spi_chipselect(spi, 0); - if (spicfg->io_type == SPI_IO_TYPE_INTR) - set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); + if (spicfg->io_type == SPI_IO_TYPE_INTR) + set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); - if (msg->length > 0) { - if (spicfg->io_type != SPI_IO_TYPE_DMA) { - /* start the transfer */ - dspi->wcount--; - tx_data = dspi->get_tx(dspi); - spidat1 &= 0xFFFF0000; - spidat1 |= tx_data & 0xFFFF; - writel(spidat1, dspi->base + SPIDAT1); - } else { - struct davinci_spi_dma *dma; - unsigned long tx_reg, rx_reg; - struct edmacc_param param; - void *rx_buf; - int b, c; + if (msg->length > 0) { + if (spicfg->io_type != SPI_IO_TYPE_DMA) { + /* start the transfer */ + dspi->wcount--; + tx_data = dspi->get_tx(dspi); + spidat1 &= 0xFFFF0000; + spidat1 |= tx_data & 0xFFFF; + writel(spidat1, dspi->base + SPIDAT1); + } else { + struct davinci_spi_dma *dma; + unsigned long tx_reg, rx_reg; + struct edmacc_param param; + void *rx_buf; + int b, c; - dma = &dspi->dma; + dma = &dspi->dma; - tx_reg = (unsigned long)dspi->base + SPIDAT1; - rx_reg = (unsigned long)dspi->base + SPIBUF; + tx_reg = (unsigned long)dspi->base + SPIDAT1; + rx_reg = (unsigned long)dspi->base + SPIBUF; - /* - * Transmit DMA setup - * - * If there is transmit data, map the transmit buffer, set it - * as the source of data and set the source B index to data - * size. If there is no transmit data, set the transmit register - * as the source of data, and set the source B index to zero. - * - * The destination is always the transmit register itself. And - * the destination never increments. - */ + /* + * Transmit DMA setup + * + * If there is transmit data, map the transmit buffer, set it + * as the source of data and set the source B index to data + * size. If there is no transmit data, set the transmit register + * as the source of data, and set the source B index to zero. + * + * The destination is always the transmit register itself. And + * the destination never increments. + */ - if (msg->send_buf) { - mmu_clean_dcache((rt_uint32_t)msg->send_buf, (rt_uint32_t)msg->length); - } + if (msg->send_buf) { + mmu_clean_dcache((rt_uint32_t)msg->send_buf, (rt_uint32_t)msg->length); + } - /* - * If number of words is greater than 65535, then we need - * to configure a 3 dimension transfer. Use the BCNTRLD - * feature to allow for transfers that aren't even multiples - * of 65535 (or any other possible b size) by first transferring - * the remainder amount then grabbing the next N blocks of - * 65535 words. - */ + /* + * If number of words is greater than 65535, then we need + * to configure a 3 dimension transfer. Use the BCNTRLD + * feature to allow for transfers that aren't even multiples + * of 65535 (or any other possible b size) by first transferring + * the remainder amount then grabbing the next N blocks of + * 65535 words. + */ - c = dspi->wcount / (SZ_64K - 1); /* N 65535 Blocks */ - b = dspi->wcount - c * (SZ_64K - 1); /* Remainder */ - if (b) - c++; - else - b = SZ_64K - 1; + c = dspi->wcount / (SZ_64K - 1); /* N 65535 Blocks */ + b = dspi->wcount - c * (SZ_64K - 1); /* Remainder */ + if (b) + c++; + else + b = SZ_64K - 1; - param.opt = TCINTEN | EDMA_TCC(dma->tx_channel); - param.src = msg->send_buf ? msg->send_buf : tx_reg; - param.a_b_cnt = b << 16 | data_type; - param.dst = tx_reg; - param.src_dst_bidx = msg->send_buf ? data_type : 0; - param.link_bcntrld = 0xffffffff; - param.src_dst_cidx = msg->send_buf ? data_type : 0; - param.ccnt = c; - edma_write_slot(dma->tx_channel, ¶m); - edma_link(dma->tx_channel, dma->dummy_param_slot); + param.opt = TCINTEN | EDMA_TCC(dma->tx_channel); + param.src = msg->send_buf ? msg->send_buf : tx_reg; + param.a_b_cnt = b << 16 | data_type; + param.dst = tx_reg; + param.src_dst_bidx = msg->send_buf ? data_type : 0; + param.link_bcntrld = 0xffffffff; + param.src_dst_cidx = msg->send_buf ? data_type : 0; + param.ccnt = c; + edma_write_slot(dma->tx_channel, ¶m); + edma_link(dma->tx_channel, dma->dummy_param_slot); - /* - * Receive DMA setup - * - * If there is receive buffer, use it to receive data. If there - * is none provided, use a temporary receive buffer. Set the - * destination B index to 0 so effectively only one byte is used - * in the temporary buffer (address does not increment). - * - * The source of receive data is the receive data register. The - * source address never increments. - */ + /* + * Receive DMA setup + * + * If there is receive buffer, use it to receive data. If there + * is none provided, use a temporary receive buffer. Set the + * destination B index to 0 so effectively only one byte is used + * in the temporary buffer (address does not increment). + * + * The source of receive data is the receive data register. The + * source address never increments. + */ - if (msg->recv_buf) { - rx_buf = msg->recv_buf; - rx_buf_count = msg->length; - } else { - rx_buf = dspi->rx_tmp_buf; - rx_buf_count = sizeof(dspi->rx_tmp_buf); - } + if (msg->recv_buf) { + rx_buf = msg->recv_buf; + rx_buf_count = msg->length; + } else { + rx_buf = dspi->rx_tmp_buf; + rx_buf_count = sizeof(dspi->rx_tmp_buf); + } - mmu_invalidate_dcache((rt_uint32_t)rx_buf, (rt_uint32_t)rx_buf_count); + mmu_invalidate_dcache((rt_uint32_t)rx_buf, (rt_uint32_t)rx_buf_count); - param.opt = TCINTEN | EDMA_TCC(dma->rx_channel); - param.src = rx_reg; - param.a_b_cnt = b << 16 | data_type; - param.dst = rx_buf; - param.src_dst_bidx = (msg->recv_buf ? data_type : 0) << 16; - param.link_bcntrld = 0xffffffff; - param.src_dst_cidx = (msg->recv_buf ? data_type : 0) << 16; - param.ccnt = c; - edma_write_slot(dma->rx_channel, ¶m); + param.opt = TCINTEN | EDMA_TCC(dma->rx_channel); + param.src = rx_reg; + param.a_b_cnt = b << 16 | data_type; + param.dst = rx_buf; + param.src_dst_bidx = (msg->recv_buf ? data_type : 0) << 16; + param.link_bcntrld = 0xffffffff; + param.src_dst_cidx = (msg->recv_buf ? data_type : 0) << 16; + param.ccnt = c; + edma_write_slot(dma->rx_channel, ¶m); - if (dspi->cshold_bug) - writew(spidat1 >> 16, dspi->base + SPIDAT1 + 2); + if (dspi->cshold_bug) + writew(spidat1 >> 16, dspi->base + SPIDAT1 + 2); - edma_start(dma->rx_channel); - edma_start(dma->tx_channel); - set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); - } + edma_start(dma->rx_channel); + edma_start(dma->tx_channel); + set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); + } - /* Wait for the transfer to complete */ - if (spicfg->io_type != SPI_IO_TYPE_POLL) { - rt_completion_wait(&(dspi->done), RT_WAITING_FOREVER); - } else { - while (dspi->rcount > 0 || dspi->wcount > 0) { - errors = davinci_spi_process_events(dspi); - if (errors) - break; - cpu_relax(); - } - } - } + /* Wait for the transfer to complete */ + if (spicfg->io_type != SPI_IO_TYPE_POLL) { + rt_completion_wait(&(dspi->done), RT_WAITING_FOREVER); + } else { + while (dspi->rcount > 0 || dspi->wcount > 0) { + errors = davinci_spi_process_events(dspi); + if (errors) + break; + cpu_relax(); + } + } + } - if (msg->cs_release) - davinci_spi_chipselect(spi, 1); + if (msg->cs_release) + davinci_spi_chipselect(spi, 1); - clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL); - if (spicfg->io_type == SPI_IO_TYPE_DMA) { - clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); - } + clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL); + if (spicfg->io_type == SPI_IO_TYPE_DMA) { + clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); + } - clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); - set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); + clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); + set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); - /* - * Check for bit error, desync error,parity error,timeout error and - * receive overflow errors - */ - if (errors) { - ret = davinci_spi_check_error(dspi, errors); - rt_kprintf("%s: error reported but no error found!\n", - spi->bus->parent.parent.name); - return ret; - } + /* + * Check for bit error, desync error,parity error,timeout error and + * receive overflow errors + */ + if (errors) { + ret = davinci_spi_check_error(dspi, errors); + rt_kprintf("%s: error reported but no error found!\n", + spi->bus->parent.parent.name); + return ret; + } - if (dspi->rcount != 0 || dspi->wcount != 0) { - spi_dbg(sdev, "SPI data transfer error\n"); - return -RT_EIO; - } + if (dspi->rcount != 0 || dspi->wcount != 0) { + spi_dbg(sdev, "SPI data transfer error\n"); + return -RT_EIO; + } - return msg->length; + return msg->length; } /** @@ -749,65 +735,65 @@ static int davinci_spi_bufs(struct rt_spi_device *spi, struct rt_spi_message *ms */ static void davinci_spi_irq(int irq, void *data) { - struct davinci_spi *dspi = data; - int status; + struct davinci_spi *dspi = data; + int status; - status = davinci_spi_process_events(dspi); - if (unlikely(status != 0)) - clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); + status = davinci_spi_process_events(dspi); + if (unlikely(status != 0)) + clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); - if ((!dspi->rcount && !dspi->wcount) || status) - rt_completion_done(&dspi->done); + if ((!dspi->rcount && !dspi->wcount) || status) + rt_completion_done(&dspi->done); } static int davinci_spi_request_dma(struct davinci_spi *dspi) { - int r; - struct davinci_spi_dma *dma = &dspi->dma; + int r; + struct davinci_spi_dma *dma = &dspi->dma; - r = edma_alloc_channel(dma->rx_channel, davinci_spi_dma_callback, dspi, - dma->eventq); - if (r < 0) { - rt_kprintf("Unable to request DMA channel for SPI RX\n"); - r = -RT_EFULL; - goto rx_dma_failed; - } + r = edma_alloc_channel(dma->rx_channel, davinci_spi_dma_callback, dspi, + dma->eventq); + if (r < 0) { + rt_kprintf("Unable to request DMA channel for SPI RX\n"); + r = -RT_EFULL; + goto rx_dma_failed; + } - r = edma_alloc_channel(dma->tx_channel, davinci_spi_dma_callback, dspi, - dma->eventq); - if (r < 0) { - rt_kprintf("Unable to request DMA channel for SPI TX\n"); - r = -RT_EFULL; - goto tx_dma_failed; - } + r = edma_alloc_channel(dma->tx_channel, davinci_spi_dma_callback, dspi, + dma->eventq); + if (r < 0) { + rt_kprintf("Unable to request DMA channel for SPI TX\n"); + r = -RT_EFULL; + goto tx_dma_failed; + } - r = edma_alloc_slot(EDMA_CTLR(dma->tx_channel), EDMA_SLOT_ANY); - if (r < 0) { - rt_kprintf("Unable to request SPI TX DMA param slot\n"); - r = -RT_EFULL; - goto param_failed; - } - dma->dummy_param_slot = r; - edma_link(dma->dummy_param_slot, dma->dummy_param_slot); + r = edma_alloc_slot(EDMA_CTLR(dma->tx_channel), EDMA_SLOT_ANY); + if (r < 0) { + rt_kprintf("Unable to request SPI TX DMA param slot\n"); + r = -RT_EFULL; + goto param_failed; + } + dma->dummy_param_slot = r; + edma_link(dma->dummy_param_slot, dma->dummy_param_slot); - return 0; + return 0; param_failed: - edma_free_channel(dma->tx_channel); + edma_free_channel(dma->tx_channel); tx_dma_failed: - edma_free_channel(dma->rx_channel); + edma_free_channel(dma->rx_channel); rx_dma_failed: - return r; + return r; } static rt_err_t configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration) { - return davinci_spi_setup_transfer(device, configuration); + return davinci_spi_setup_transfer(device, configuration); } static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message *message) { - return davinci_spi_bufs(device, message); + return davinci_spi_bufs(device, message); }; @@ -820,29 +806,29 @@ static struct rt_spi_ops davinci_spi_ops = static void udelay (volatile rt_uint32_t us) { - volatile rt_int32_t i; - for (; us > 0; us--) - { - i = 5000; - while(i > 0) - { - i--; - } - } + volatile rt_int32_t i; + for (; us > 0; us--) + { + i = 5000; + while(i > 0) + { + i--; + } + } } void spi_pin_cfg(void) { - rt_uint32_t val; + rt_uint32_t val; - val = davinci_readl(PINMUX3); - val |= 0x80000000; /* SPI1 */ - davinci_writel(val, PINMUX3); + val = davinci_readl(PINMUX3); + val |= 0x80000000; /* SPI1 */ + davinci_writel(val, PINMUX3); - val = davinci_readl(PINMUX4); - val &= 0xffffffc0; /* SPI1 */ - val |= 0x05;//0x00000015; /* SPI1 */ - davinci_writel(val, PINMUX4); + val = davinci_readl(PINMUX4); + val &= 0xffffffc0; /* SPI1 */ + val |= 0x05;//0x00000015; /* SPI1 */ + davinci_writel(val, PINMUX4); } /** @@ -858,87 +844,87 @@ void spi_pin_cfg(void) */ static int davinci_spi_probe(struct davinci_spi *dspi, char *spi_bus_name) { - int i = 0, ret = 0; - u32 spipc0; + int i = 0, ret = 0; + u32 spipc0; - spi_pin_cfg(); - psc_change_state(DAVINCI_DM365_LPSC_SPI1, PSC_ENABLE); + spi_pin_cfg(); + psc_change_state(DAVINCI_DM365_LPSC_SPI1, PSC_ENABLE); - dspi->base = DM3XX_SPI1_BASE;//spi; + dspi->base = DM3XX_SPI1_BASE;//spi; - dspi->irq = IRQ_DM3XX_SPINT1_0; + dspi->irq = IRQ_DM3XX_SPINT1_0; - rt_hw_interrupt_install(dspi->irq, davinci_spi_irq, dspi, spi_bus_name); - rt_hw_interrupt_umask(dspi->irq); + rt_hw_interrupt_install(dspi->irq, davinci_spi_irq, dspi, spi_bus_name); + rt_hw_interrupt_umask(dspi->irq); - dspi->clk = clk_get("SPICLK"); + dspi->clk = clk_get("SPICLK"); - dspi->version = SPI_VERSION_1; - dspi->chip_sel[0] = 29;//SPI_INTERN_CS; - dspi->chip_sel[1] = 0;//GPIO0 + dspi->version = SPI_VERSION_1; + dspi->chip_sel[0] = 29;//SPI_INTERN_CS; + dspi->chip_sel[1] = 0;//GPIO0 - dspi->dma.rx_channel = 15; - dspi->dma.tx_channel = 14; - dspi->dma.eventq = EVENTQ_3; + dspi->dma.rx_channel = 15; + dspi->dma.tx_channel = 14; + dspi->dma.eventq = EVENTQ_3; - ret = davinci_spi_request_dma(dspi); - if (ret) - goto err; + ret = davinci_spi_request_dma(dspi); + if (ret) + goto err; - rt_kprintf("%s: DMA: supported\n", spi_bus_name); - rt_kprintf("%s: DMA: RX channel: %d, TX channel: %d, " - "event queue: %d\n", spi_bus_name, dspi->dma.rx_channel, - dspi->dma.tx_channel, dspi->dma.eventq); + rt_kprintf("%s: DMA: supported\n", spi_bus_name); + rt_kprintf("%s: DMA: RX channel: %d, TX channel: %d, " + "event queue: %d\n", spi_bus_name, dspi->dma.rx_channel, + dspi->dma.tx_channel, dspi->dma.eventq); - dspi->get_rx = davinci_spi_rx_buf_u8; - dspi->get_tx = davinci_spi_tx_buf_u8; + dspi->get_rx = davinci_spi_rx_buf_u8; + dspi->get_tx = davinci_spi_tx_buf_u8; - rt_completion_init(&dspi->done); + rt_completion_init(&dspi->done); - /* Reset In/OUT SPI module */ - writel(0, dspi->base + SPIGCR0); - udelay(100); - writel(1, dspi->base + SPIGCR0); + /* Reset In/OUT SPI module */ + writel(0, dspi->base + SPIGCR0); + udelay(100); + writel(1, dspi->base + SPIGCR0); - /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */ - spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK; - writel(spipc0, dspi->base + SPIPC0); + /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */ + spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK; + writel(spipc0, dspi->base + SPIPC0); - /* initialize chip selects */ - for (i = 0; i < SPI_MAX_CHIPSELECT; i++) { - if (dspi->chip_sel[i] != SPI_INTERN_CS) - gpio_direction_output(dspi->chip_sel[i], 1); - } + /* initialize chip selects */ + for (i = 0; i < SPI_MAX_CHIPSELECT; i++) { + if (dspi->chip_sel[i] != SPI_INTERN_CS) + gpio_direction_output(dspi->chip_sel[i], 1); + } - if (0) - writel(SPI_INTLVL_1, dspi->base + SPILVL); - else - writel(SPI_INTLVL_0, dspi->base + SPILVL); + if (0) + writel(SPI_INTLVL_1, dspi->base + SPILVL); + else + writel(SPI_INTLVL_0, dspi->base + SPILVL); - writel(CS_DEFAULT, dspi->base + SPIDEF); + writel(CS_DEFAULT, dspi->base + SPIDEF); - /* master mode default */ - set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK); - set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK); - set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); + /* master mode default */ + set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK); + set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK); + set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); - //set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);//LOOP BACK mode + //set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);//LOOP BACK mode - rt_kprintf("%s: Controller at 0x%p\n", spi_bus_name, dspi->base); + rt_kprintf("%s: Controller at 0x%p\n", spi_bus_name, dspi->base); - dspi->parent.parent.user_data = dspi; + dspi->parent.parent.user_data = dspi; - return rt_spi_bus_register(&dspi->parent, spi_bus_name, &davinci_spi_ops); + return rt_spi_bus_register(&dspi->parent, spi_bus_name, &davinci_spi_ops); - return ret; + return ret; free_dma: - edma_free_channel(dspi->dma.tx_channel); - edma_free_channel(dspi->dma.rx_channel); - edma_free_slot(dspi->dma.dummy_param_slot); + edma_free_channel(dspi->dma.tx_channel); + edma_free_channel(dspi->dma.rx_channel); + edma_free_slot(dspi->dma.dummy_param_slot); err: - return ret; + return ret; } @@ -947,15 +933,15 @@ int rt_hw_spi_init(void) /* register spi bus */ { static struct davinci_spi dspi; - rt_memset(&dspi, 0, sizeof(dspi)); - davinci_spi_probe(&dspi, "spi1"); + rt_memset(&dspi, 0, sizeof(dspi)); + davinci_spi_probe(&dspi, "spi1"); } /* attach cs */ { static struct rt_spi_device spi_device; rt_spi_bus_attach_device(&spi_device, "spi10", "spi1", (void *)0); } - { + { static struct rt_spi_device spi_device; rt_spi_bus_attach_device(&spi_device, "spi11", "spi1", (void *)1); } diff --git a/bsp/dm365/drivers/spi-davinci.h b/bsp/dm365/drivers/spi-davinci.h index 07e8bef4df..d1761e03f3 100644 --- a/bsp/dm365/drivers/spi-davinci.h +++ b/bsp/dm365/drivers/spi-davinci.h @@ -1,25 +1,11 @@ /* - * File : spi-davinci.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version + * Date Author Notes + * 2011-01-13 weety first version */ #ifndef __DAVINCI_SPI_H @@ -30,46 +16,46 @@ typedef unsigned short u16; typedef unsigned char u8; typedef unsigned int bool; -#define SPI_INTERN_CS 0xFF +#define SPI_INTERN_CS 0xFF enum { - SPI_VERSION_1, /* For DM355/DM365/DM6467 */ - SPI_VERSION_2, /* For DA8xx */ + SPI_VERSION_1, /* For DM355/DM365/DM6467 */ + SPI_VERSION_2, /* For DA8xx */ }; /** * davinci_spi_config - Per-chip-select configuration for SPI slave devices * - * @wdelay: amount of delay between transmissions. Measured in number of - * SPI module clocks. - * @odd_parity: polarity of parity flag at the end of transmit data stream. - * 0 - odd parity, 1 - even parity. + * @wdelay: amount of delay between transmissions. Measured in number of + * SPI module clocks. + * @odd_parity: polarity of parity flag at the end of transmit data stream. + * 0 - odd parity, 1 - even parity. * @parity_enable: enable transmission of parity at end of each transmit - * data stream. - * @io_type: type of IO transfer. Choose between polled, interrupt and DMA. + * data stream. + * @io_type: type of IO transfer. Choose between polled, interrupt and DMA. * @timer_disable: disable chip-select timers (setup and hold) - * @c2tdelay: chip-select setup time. Measured in number of SPI module clocks. - * @t2cdelay: chip-select hold time. Measured in number of SPI module clocks. - * @t2edelay: transmit data finished to SPI ENAn pin inactive time. Measured - * in number of SPI clocks. - * @c2edelay: chip-select active to SPI ENAn signal active time. Measured in - * number of SPI clocks. + * @c2tdelay: chip-select setup time. Measured in number of SPI module clocks. + * @t2cdelay: chip-select hold time. Measured in number of SPI module clocks. + * @t2edelay: transmit data finished to SPI ENAn pin inactive time. Measured + * in number of SPI clocks. + * @c2edelay: chip-select active to SPI ENAn signal active time. Measured in + * number of SPI clocks. */ struct davinci_spi_config { - u8 wdelay; - u8 odd_parity; - u8 parity_enable; -#define SPI_IO_TYPE_INTR 0 -#define SPI_IO_TYPE_POLL 1 -#define SPI_IO_TYPE_DMA 2 - u8 io_type; - u8 timer_disable; - u8 c2tdelay; - u8 t2cdelay; - u8 t2edelay; - u8 c2edelay; + u8 wdelay; + u8 odd_parity; + u8 parity_enable; +#define SPI_IO_TYPE_INTR 0 +#define SPI_IO_TYPE_POLL 1 +#define SPI_IO_TYPE_DMA 2 + u8 io_type; + u8 timer_disable; + u8 c2tdelay; + u8 t2cdelay; + u8 t2edelay; + u8 c2edelay; }; extern int rt_hw_spi_init(void); -#endif /* __DAVINCI_SPI_H */ +#endif /* __DAVINCI_SPI_H */ diff --git a/bsp/dm365/platform/dm365.c b/bsp/dm365/platform/dm365.c index 010e2a030e..0fe2d0a94a 100644 --- a/bsp/dm365/platform/dm365.c +++ b/bsp/dm365/platform/dm365.c @@ -1,25 +1,11 @@ /* - * File : dm365.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2010-11-13 weety first version + * Date Author Notes + * 2010-11-13 weety first version */ #include @@ -40,285 +26,285 @@ static rt_uint32_t vpssrate, vencrate_sd, vencrate_hd; /* Four Transfer Controllers on DM365 */ static const rt_int8_t dm365_queue_tc_mapping[][2] = { - /* {event queue no, TC no} */ - {0, 0}, - {1, 1}, - {2, 2}, - {3, 3}, - {-1, -1}, + /* {event queue no, TC no} */ + {0, 0}, + {1, 1}, + {2, 2}, + {3, 3}, + {-1, -1}, }; static const rt_int8_t dm365_queue_priority_mapping[][2] = { - /* {event queue no, Priority} */ - {0, 7}, - {1, 7}, - {2, 7}, - {3, 0}, - {-1, -1}, + /* {event queue no, Priority} */ + {0, 7}, + {1, 7}, + {2, 7}, + {3, 0}, + {-1, -1}, }; static struct edma_soc_info edma_cc0_info = { - .n_channel = 64, - .n_region = 4, - .n_slot = 256, - .n_tc = 4, - .n_cc = 1, - .queue_tc_mapping = dm365_queue_tc_mapping, - .queue_priority_mapping = dm365_queue_priority_mapping, - .default_queue = EVENTQ_3, + .n_channel = 64, + .n_region = 4, + .n_slot = 256, + .n_tc = 4, + .n_cc = 1, + .queue_tc_mapping = dm365_queue_tc_mapping, + .queue_priority_mapping = dm365_queue_priority_mapping, + .default_queue = EVENTQ_3, }; static struct edma_soc_info *dm365_edma_info[EDMA_MAX_CC] = { - &edma_cc0_info, + &edma_cc0_info, }; static rt_list_t clocks; struct clk { - char name[32]; - rt_uint32_t *rate_hz; - struct clk *parent; - rt_list_t node; + char name[32]; + rt_uint32_t *rate_hz; + struct clk *parent; + rt_list_t node; }; static struct clk davinci_dm365_clks[] = { - { - .name = "ARMCLK", - .rate_hz = &armrate, - }, - { - .name = "UART0", - .rate_hz = &fixedrate, - }, - { - .name = "UART1", - .rate_hz = &commonrate, - }, - { - .name = "HPI", - .rate_hz = &commonrate, - }, - { - .name = "EMACCLK", - .rate_hz = &commonrate, - }, - { - .name = "I2CCLK", - .rate_hz = &fixedrate, - }, - { - .name = "McBSPCLK", - .rate_hz = &commonrate, - }, - { - .name = "MMCSDCLK0", - .rate_hz = &mmcsdrate, - }, - { - .name = "MMCSDCLK1", - .rate_hz = &mmcsdrate, - }, - { - .name = "SPICLK", - .rate_hz = &commonrate, - }, - { - .name = "gpio", - .rate_hz = &commonrate, - }, - { - .name = "AEMIFCLK", - .rate_hz = &commonrate, - }, - { - .name = "PWM0_CLK", - .rate_hz = &fixedrate, - }, - { - .name = "PWM1_CLK", - .rate_hz = &fixedrate, - }, - { - .name = "PWM2_CLK", - .rate_hz = &fixedrate, - }, - { - .name = "PWM3_CLK", - .rate_hz = &fixedrate, - }, - { - .name = "USBCLK", - .rate_hz = &fixedrate, - }, - { - .name = "VOICECODEC_CLK", - .rate_hz = &voicerate, - }, - { - .name = "RTC_CLK", - .rate_hz = &fixedrate, - }, - { - .name = "KEYSCAN_CLK", - .rate_hz = &fixedrate, - }, - { - .name = "ADCIF_CLK", - .rate_hz = &fixedrate, - }, + { + .name = "ARMCLK", + .rate_hz = &armrate, + }, + { + .name = "UART0", + .rate_hz = &fixedrate, + }, + { + .name = "UART1", + .rate_hz = &commonrate, + }, + { + .name = "HPI", + .rate_hz = &commonrate, + }, + { + .name = "EMACCLK", + .rate_hz = &commonrate, + }, + { + .name = "I2CCLK", + .rate_hz = &fixedrate, + }, + { + .name = "McBSPCLK", + .rate_hz = &commonrate, + }, + { + .name = "MMCSDCLK0", + .rate_hz = &mmcsdrate, + }, + { + .name = "MMCSDCLK1", + .rate_hz = &mmcsdrate, + }, + { + .name = "SPICLK", + .rate_hz = &commonrate, + }, + { + .name = "gpio", + .rate_hz = &commonrate, + }, + { + .name = "AEMIFCLK", + .rate_hz = &commonrate, + }, + { + .name = "PWM0_CLK", + .rate_hz = &fixedrate, + }, + { + .name = "PWM1_CLK", + .rate_hz = &fixedrate, + }, + { + .name = "PWM2_CLK", + .rate_hz = &fixedrate, + }, + { + .name = "PWM3_CLK", + .rate_hz = &fixedrate, + }, + { + .name = "USBCLK", + .rate_hz = &fixedrate, + }, + { + .name = "VOICECODEC_CLK", + .rate_hz = &voicerate, + }, + { + .name = "RTC_CLK", + .rate_hz = &fixedrate, + }, + { + .name = "KEYSCAN_CLK", + .rate_hz = &fixedrate, + }, + { + .name = "ADCIF_CLK", + .rate_hz = &fixedrate, + }, }; /* clocks cannot be de-registered no refcounting necessary */ struct clk *clk_get(const char *id) { - struct clk *clk; - rt_list_t *list; - - for (list = (&clocks)->next; list != &clocks; list = list->next) - { - clk = (struct clk *)rt_list_entry(list, struct clk, node); - if (rt_strcmp(id, clk->name) == 0) - return clk; - } + struct clk *clk; + rt_list_t *list; - return RT_NULL; + for (list = (&clocks)->next; list != &clocks; list = list->next) + { + clk = (struct clk *)rt_list_entry(list, struct clk, node); + if (rt_strcmp(id, clk->name) == 0) + return clk; + } + + return RT_NULL; } rt_uint32_t clk_get_rate(struct clk *clk) { - rt_uint32_t flags; - rt_uint32_t *rate; + rt_uint32_t flags; + rt_uint32_t *rate; - for (;;) { - rate = clk->rate_hz; - if (rate || !clk->parent) - break; - clk = clk->parent; - } - return *rate; + for (;;) { + rate = clk->rate_hz; + if (rate || !clk->parent) + break; + clk = clk->parent; + } + return *rate; } void clk_register(struct clk *clk) { - rt_list_insert_after(&clocks, &clk->node); + rt_list_insert_after(&clocks, &clk->node); } int davinci_register_clks(struct clk *clk_list, int num_clks) { - struct clk *clkp; - int i; + struct clk *clkp; + int i; - for (i = 0, clkp = clk_list; i < num_clks; i++, clkp++) - { - //rt_kprintf("1:%s\n", clkp->name); - clk_register(clkp); - //rt_kprintf("2:%s\n", clkp->name); - } + for (i = 0, clkp = clk_list; i < num_clks; i++, clkp++) + { + //rt_kprintf("1:%s\n", clkp->name); + clk_register(clkp); + //rt_kprintf("2:%s\n", clkp->name); + } - return 0; + return 0; } /* PLL/Reset register offsets */ -#define PLLM 0x110 -#define PREDIV 0x114 -#define PLLDIV2 0x11C -#define POSTDIV 0x128 -#define PLLDIV4 0x160 -#define PLLDIV5 0x164 -#define PLLDIV6 0x168 -#define PLLDIV7 0x16C -#define PLLDIV8 0x170 +#define PLLM 0x110 +#define PREDIV 0x114 +#define PLLDIV2 0x11C +#define POSTDIV 0x128 +#define PLLDIV4 0x160 +#define PLLDIV5 0x164 +#define PLLDIV6 0x168 +#define PLLDIV7 0x16C +#define PLLDIV8 0x170 int davinci_clk_init(void) { - struct clk *clk_list; - int num_clks; - rt_uint32_t pll0_mult, pll1_mult; + struct clk *clk_list; + int num_clks; + rt_uint32_t pll0_mult, pll1_mult; - unsigned long prediv, postdiv; - unsigned long pll_rate; - unsigned long pll_div2, pll_div4, pll_div5, - pll_div6, pll_div7, pll_div8; + unsigned long prediv, postdiv; + unsigned long pll_rate; + unsigned long pll_div2, pll_div4, pll_div5, + pll_div6, pll_div7, pll_div8; - rt_list_init(&clocks); + rt_list_init(&clocks); - //davinci_psc_register(davinci_psc_base, 1); + //davinci_psc_register(davinci_psc_base, 1); - pll0_mult = davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLM); - pll1_mult = davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLM); + pll0_mult = davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLM); + pll1_mult = davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLM); - commonrate = ((pll0_mult + 1) * 27000000) / 6; - armrate = ((pll0_mult + 1) * 27000000) / 2; + commonrate = ((pll0_mult + 1) * 27000000) / 6; + armrate = ((pll0_mult + 1) * 27000000) / 2; - fixedrate = 24000000; + fixedrate = 24000000; - /* Read PLL0 configuration */ - prediv = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PREDIV) & - 0x1f) + 1; - postdiv = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + POSTDIV) & - 0x1f) + 1; + /* Read PLL0 configuration */ + prediv = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PREDIV) & + 0x1f) + 1; + postdiv = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + POSTDIV) & + 0x1f) + 1; - /* PLL0 dividers */ - pll_div4 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV4) & - 0x1f) + 1; /* EDMA, EMAC, config, common */ - pll_div5 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV5) & - 0x1f) + 1; /* VPSS */ - pll_div6 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV6) & - 0x1f) + 1; /* VENC */ - pll_div7 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV7) & - 0x1f) + 1; /* DDR */ - pll_div8 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV8) & - 0x1f) + 1; /* MMC/SD */ + /* PLL0 dividers */ + pll_div4 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV4) & + 0x1f) + 1; /* EDMA, EMAC, config, common */ + pll_div5 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV5) & + 0x1f) + 1; /* VPSS */ + pll_div6 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV6) & + 0x1f) + 1; /* VENC */ + pll_div7 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV7) & + 0x1f) + 1; /* DDR */ + pll_div8 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV8) & + 0x1f) + 1; /* MMC/SD */ - pll_rate = ((fixedrate / prediv) * (2 * pll0_mult)) / postdiv; + pll_rate = ((fixedrate / prediv) * (2 * pll0_mult)) / postdiv; - commonrate = pll_rate / pll_div4; /* 486/4 = 121.5MHz */ - vpssrate = pll_rate / pll_div5; /* 486/2 = 243MHz */ - vencrate_sd = pll_rate / pll_div6; /* 486/18 = 27MHz */ - ddrrate = pll_rate / pll_div7; /* 486/2 = 243MHz */ - mmcsdrate = pll_rate / pll_div8; /* 486/4 = 121.5MHz */ + commonrate = pll_rate / pll_div4; /* 486/4 = 121.5MHz */ + vpssrate = pll_rate / pll_div5; /* 486/2 = 243MHz */ + vencrate_sd = pll_rate / pll_div6; /* 486/18 = 27MHz */ + ddrrate = pll_rate / pll_div7; /* 486/2 = 243MHz */ + mmcsdrate = pll_rate / pll_div8; /* 486/4 = 121.5MHz */ - rt_kprintf( - "PLL0: fixedrate: %d, commonrate: %d, vpssrate: %d\n", - fixedrate, commonrate, vpssrate); - rt_kprintf( - "PLL0: vencrate_sd: %d, ddrrate: %d mmcsdrate: %d\n", - vencrate_sd, (ddrrate/2), mmcsdrate); + rt_kprintf( + "PLL0: fixedrate: %d, commonrate: %d, vpssrate: %d\n", + fixedrate, commonrate, vpssrate); + rt_kprintf( + "PLL0: vencrate_sd: %d, ddrrate: %d mmcsdrate: %d\n", + vencrate_sd, (ddrrate/2), mmcsdrate); - /* Read PLL1 configuration */ - prediv = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PREDIV) & - 0x1f) + 1; - postdiv = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + POSTDIV) & - 0x1f) + 1; - pll_rate = ((fixedrate / prediv) * (2 * pll1_mult)) / postdiv; + /* Read PLL1 configuration */ + prediv = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PREDIV) & + 0x1f) + 1; + postdiv = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + POSTDIV) & + 0x1f) + 1; + pll_rate = ((fixedrate / prediv) * (2 * pll1_mult)) / postdiv; - /* PLL1 dividers */ - pll_div2 = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLDIV2) & - 0x1f) + 1; /* ARM */ - pll_div4 = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLDIV4) & - 0x1f) + 1; /* VOICE */ - pll_div5 = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLDIV5) & - 0x1f) + 1; /* VENC */ + /* PLL1 dividers */ + pll_div2 = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLDIV2) & + 0x1f) + 1; /* ARM */ + pll_div4 = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLDIV4) & + 0x1f) + 1; /* VOICE */ + pll_div5 = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLDIV5) & + 0x1f) + 1; /* VENC */ - armrate = pll_rate / pll_div2; /* 594/2 = 297MHz */ - voicerate = pll_rate / pll_div4; /* 594/6 = 99MHz */ - vencrate_hd = pll_rate / pll_div5; /* 594/8 = 74.25MHz */ + armrate = pll_rate / pll_div2; /* 594/2 = 297MHz */ + voicerate = pll_rate / pll_div4; /* 594/6 = 99MHz */ + vencrate_hd = pll_rate / pll_div5; /* 594/8 = 74.25MHz */ - rt_kprintf( - "PLL1: armrate: %d, voicerate: %d, vencrate_hd: %d\n", - armrate, voicerate, vencrate_hd); + rt_kprintf( + "PLL1: armrate: %d, voicerate: %d, vencrate_hd: %d\n", + armrate, voicerate, vencrate_hd); - clk_list = davinci_dm365_clks; - num_clks = ARRAY_SIZE(davinci_dm365_clks); + clk_list = davinci_dm365_clks; + num_clks = ARRAY_SIZE(davinci_dm365_clks); - return davinci_register_clks(clk_list, num_clks); + return davinci_register_clks(clk_list, num_clks); } int platform_init(void) { - edma_init(dm365_edma_info); + edma_init(dm365_edma_info); } INIT_BOARD_EXPORT(platform_init); @@ -326,44 +312,44 @@ INIT_BOARD_EXPORT(platform_init); /* Reset board using the watchdog timer */ void reset_system(void) { - rt_uint32_t tgcr, wdtcr; - rt_uint32_t base = DAVINCI_WDOG_BASE; + rt_uint32_t tgcr, wdtcr; + rt_uint32_t base = DAVINCI_WDOG_BASE; - /* Disable, internal clock source */ - davinci_writel(0, base + TCR); + /* Disable, internal clock source */ + davinci_writel(0, base + TCR); - /* Reset timer, set mode to 64-bit watchdog, and unreset */ - davinci_writel(0, base + TGCR); - tgcr = (TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT) | - (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) | - (TGCR_UNRESET << TGCR_TIM34RS_SHIFT); - davinci_writel(tgcr, base + TGCR); + /* Reset timer, set mode to 64-bit watchdog, and unreset */ + davinci_writel(0, base + TGCR); + tgcr = (TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT) | + (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) | + (TGCR_UNRESET << TGCR_TIM34RS_SHIFT); + davinci_writel(tgcr, base + TGCR); - /* Clear counter and period regs */ - davinci_writel(0, base + TIM12); - davinci_writel(0, base + TIM34); - davinci_writel(0, base + PRD12); - davinci_writel(0, base + PRD34); + /* Clear counter and period regs */ + davinci_writel(0, base + TIM12); + davinci_writel(0, base + TIM34); + davinci_writel(0, base + PRD12); + davinci_writel(0, base + PRD34); - /* Enable periodic mode */ - davinci_writel(TCR_ENAMODE_PERIODIC << ENAMODE12_SHIFT, base + TCR); + /* Enable periodic mode */ + davinci_writel(TCR_ENAMODE_PERIODIC << ENAMODE12_SHIFT, base + TCR); - /* Put watchdog in pre-active state */ - wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) | - (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT); - davinci_writel(wdtcr, base + WDTCR); + /* Put watchdog in pre-active state */ + wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) | + (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT); + davinci_writel(wdtcr, base + WDTCR); - /* Put watchdog in active state */ - wdtcr = (WDTCR_WDKEY_SEQ1 << WDTCR_WDKEY_SHIFT) | - (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT); - davinci_writel(wdtcr, base + WDTCR); + /* Put watchdog in active state */ + wdtcr = (WDTCR_WDKEY_SEQ1 << WDTCR_WDKEY_SHIFT) | + (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT); + davinci_writel(wdtcr, base + WDTCR); - /* - * Write an invalid value to the WDKEY field to trigger - * a watchdog reset. - */ - wdtcr = 0xDEADBEEF; - davinci_writel(wdtcr, base + WDTCR); + /* + * Write an invalid value to the WDKEY field to trigger + * a watchdog reset. + */ + wdtcr = 0xDEADBEEF; + davinci_writel(wdtcr, base + WDTCR); } diff --git a/bsp/dm365/platform/dm365_timer.h b/bsp/dm365/platform/dm365_timer.h index 2dd6114c02..93a0e3ef6b 100644 --- a/bsp/dm365/platform/dm365_timer.h +++ b/bsp/dm365/platform/dm365_timer.h @@ -1,74 +1,60 @@ /* - * File : dm365_timer.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2010-11-13 weety first version + * Date Author Notes + * 2010-11-13 weety first version */ #ifndef __ASM_ARCH_TIME_H #define __ASM_ARCH_TIME_H /* Timer register offsets */ -#define PID12 0x0 -#define TIM12 0x10 -#define TIM34 0x14 -#define PRD12 0x18 -#define PRD34 0x1c -#define TCR 0x20 -#define TGCR 0x24 -#define WDTCR 0x28 -#define CMP12(n) (0x60 + ((n) << 2)) +#define PID12 0x0 +#define TIM12 0x10 +#define TIM34 0x14 +#define PRD12 0x18 +#define PRD34 0x1c +#define TCR 0x20 +#define TGCR 0x24 +#define WDTCR 0x28 +#define CMP12(n) (0x60 + ((n) << 2)) /* Timer register bitfields */ -#define ENAMODE12_SHIFT 6 -#define ENAMODE34_SHIFT 22 -#define TCR_ENAMODE_DISABLE 0x0 -#define TCR_ENAMODE_ONESHOT 0x1 -#define TCR_ENAMODE_PERIODIC 0x2 -#define TCR_ENAMODE_MASK 0x3 +#define ENAMODE12_SHIFT 6 +#define ENAMODE34_SHIFT 22 +#define TCR_ENAMODE_DISABLE 0x0 +#define TCR_ENAMODE_ONESHOT 0x1 +#define TCR_ENAMODE_PERIODIC 0x2 +#define TCR_ENAMODE_MASK 0x3 -#define TGCR_TIMMODE_SHIFT 2 -#define TGCR_TIMMODE_64BIT_GP 0x0 -#define TGCR_TIMMODE_32BIT_UNCHAINED 0x1 -#define TGCR_TIMMODE_64BIT_WDOG 0x2 -#define TGCR_TIMMODE_32BIT_CHAINED 0x3 +#define TGCR_TIMMODE_SHIFT 2 +#define TGCR_TIMMODE_64BIT_GP 0x0 +#define TGCR_TIMMODE_32BIT_UNCHAINED 0x1 +#define TGCR_TIMMODE_64BIT_WDOG 0x2 +#define TGCR_TIMMODE_32BIT_CHAINED 0x3 -#define TGCR_TIM12RS_SHIFT 0 -#define TGCR_TIM34RS_SHIFT 1 -#define TGCR_RESET 0x0 -#define TGCR_UNRESET 0x1 -#define TGCR_RESET_MASK 0x3 +#define TGCR_TIM12RS_SHIFT 0 +#define TGCR_TIM34RS_SHIFT 1 +#define TGCR_RESET 0x0 +#define TGCR_UNRESET 0x1 +#define TGCR_RESET_MASK 0x3 -#define WDTCR_WDEN_SHIFT 14 -#define WDTCR_WDEN_DISABLE 0x0 -#define WDTCR_WDEN_ENABLE 0x1 -#define WDTCR_WDKEY_SHIFT 16 -#define WDTCR_WDKEY_SEQ0 0xA5C6 -#define WDTCR_WDKEY_SEQ1 0xDA7E +#define WDTCR_WDEN_SHIFT 14 +#define WDTCR_WDEN_DISABLE 0x0 +#define WDTCR_WDEN_ENABLE 0x1 +#define WDTCR_WDKEY_SHIFT 16 +#define WDTCR_WDKEY_SEQ0 0xA5C6 +#define WDTCR_WDKEY_SEQ1 0xDA7E enum { - T0_BOT, - T0_TOP, - T1_BOT, - T1_TOP, - NUM_TIMERS + T0_BOT, + T0_TOP, + T1_BOT, + T1_TOP, + NUM_TIMERS }; #endif /* __ASM_ARCH_TIME_H__ */ diff --git a/bsp/dm365/platform/dm36x.h b/bsp/dm365/platform/dm36x.h index 85be007c24..2aa72a23ce 100644 --- a/bsp/dm365/platform/dm36x.h +++ b/bsp/dm365/platform/dm36x.h @@ -1,25 +1,11 @@ /* - * File : dm36x.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2010-11-13 weety first version + * Date Author Notes + * 2010-11-13 weety first version */ #ifndef __DM36X_H__ @@ -43,43 +29,43 @@ extern "C" { /* * Base register addresses */ -#define DAVINCI_DMA_3PCC_BASE (0x01C00000) -#define DAVINCI_DMA_3PTC0_BASE (0x01C10000) -#define DAVINCI_DMA_3PTC1_BASE (0x01C10400) -#define DAVINCI_I2C_BASE (0x01C21000) -#define DAVINCI_TIMER0_BASE (0x01C21400) -#define DAVINCI_TIMER1_BASE (0x01C21800) -#define DAVINCI_WDOG_BASE (0x01C21C00) -#define DAVINCI_PWM0_BASE (0x01C22000) -#define DAVINCI_PWM1_BASE (0x01C22400) -#define DAVINCI_PWM2_BASE (0x01C22800) -#define DAVINCI_SYSTEM_MODULE_BASE (0x01C40000) -#define DAVINCI_PLL_CNTRL0_BASE (0x01C40800) -#define DAVINCI_PLL_CNTRL1_BASE (0x01C40C00) -#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01C41000) -#define DAVINCI_SYSTEM_DFT_BASE (0x01C42000) -#define DAVINCI_IEEE1394_BASE (0x01C60000) -#define DAVINCI_USB_OTG_BASE (0x01C64000) -#define DAVINCI_CFC_ATA_BASE (0x01C66000) -#define DAVINCI_SPI_BASE (0x01C66800) -#define DAVINCI_GPIO_BASE (0x01C67000) -#define DAVINCI_UHPI_BASE (0x01C67800) -#define DAVINCI_VPSS_REGS_BASE (0x01C70000) -#define DAVINCI_EMAC_CNTRL_REGS_BASE (0x01C80000) -#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE (0x01C81000) -#define DAVINCI_EMAC_WRAPPER_RAM_BASE (0x01C82000) -#define DAVINCI_MDIO_CNTRL_REGS_BASE (0x01C84000) -#define DAVINCI_IMCOP_BASE (0x01CC0000) -#define DAVINCI_ASYNC_EMIF_CNTRL_BASE (0x01E00000) -#define DAVINCI_VLYNQ_BASE (0x01E01000) -#define DAVINCI_MCBSP_BASE (0x01E02000) -#define DAVINCI_MMC_SD_BASE (0x01E10000) -#define DAVINCI_MS_BASE (0x01E20000) -#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000) -#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000) -#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000) -#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000) -#define DAVINCI_VLYNQ_REMOTE_BASE (0x0C000000) +#define DAVINCI_DMA_3PCC_BASE (0x01C00000) +#define DAVINCI_DMA_3PTC0_BASE (0x01C10000) +#define DAVINCI_DMA_3PTC1_BASE (0x01C10400) +#define DAVINCI_I2C_BASE (0x01C21000) +#define DAVINCI_TIMER0_BASE (0x01C21400) +#define DAVINCI_TIMER1_BASE (0x01C21800) +#define DAVINCI_WDOG_BASE (0x01C21C00) +#define DAVINCI_PWM0_BASE (0x01C22000) +#define DAVINCI_PWM1_BASE (0x01C22400) +#define DAVINCI_PWM2_BASE (0x01C22800) +#define DAVINCI_SYSTEM_MODULE_BASE (0x01C40000) +#define DAVINCI_PLL_CNTRL0_BASE (0x01C40800) +#define DAVINCI_PLL_CNTRL1_BASE (0x01C40C00) +#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01C41000) +#define DAVINCI_SYSTEM_DFT_BASE (0x01C42000) +#define DAVINCI_IEEE1394_BASE (0x01C60000) +#define DAVINCI_USB_OTG_BASE (0x01C64000) +#define DAVINCI_CFC_ATA_BASE (0x01C66000) +#define DAVINCI_SPI_BASE (0x01C66800) +#define DAVINCI_GPIO_BASE (0x01C67000) +#define DAVINCI_UHPI_BASE (0x01C67800) +#define DAVINCI_VPSS_REGS_BASE (0x01C70000) +#define DAVINCI_EMAC_CNTRL_REGS_BASE (0x01C80000) +#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE (0x01C81000) +#define DAVINCI_EMAC_WRAPPER_RAM_BASE (0x01C82000) +#define DAVINCI_MDIO_CNTRL_REGS_BASE (0x01C84000) +#define DAVINCI_IMCOP_BASE (0x01CC0000) +#define DAVINCI_ASYNC_EMIF_CNTRL_BASE (0x01E00000) +#define DAVINCI_VLYNQ_BASE (0x01E01000) +#define DAVINCI_MCBSP_BASE (0x01E02000) +#define DAVINCI_MMC_SD_BASE (0x01E10000) +#define DAVINCI_MS_BASE (0x01E20000) +#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000) +#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000) +#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000) +#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000) +#define DAVINCI_VLYNQ_REMOTE_BASE (0x0C000000) /* @@ -91,14 +77,14 @@ extern "C" { * In case of only one VLYNQ IP, define only the * 'LOW_VLYNQ_CONTROL_BASE'. */ -#define LOW_VLYNQ_CONTROL_BASE DAVINCI_VLYNQ_BASE +#define LOW_VLYNQ_CONTROL_BASE DAVINCI_VLYNQ_BASE -#define DM365_EMAC_BASE (0x01D07000) -#define DM365_EMAC_CNTRL_OFFSET (0x0000) -#define DM365_EMAC_CNTRL_MOD_OFFSET (0x3000) -#define DM365_EMAC_CNTRL_RAM_OFFSET (0x1000) -#define DM365_EMAC_MDIO_OFFSET (0x4000) -#define DM365_EMAC_CNTRL_RAM_SIZE (0x2000) +#define DM365_EMAC_BASE (0x01D07000) +#define DM365_EMAC_CNTRL_OFFSET (0x0000) +#define DM365_EMAC_CNTRL_MOD_OFFSET (0x3000) +#define DM365_EMAC_CNTRL_RAM_OFFSET (0x1000) +#define DM365_EMAC_MDIO_OFFSET (0x4000) +#define DM365_EMAC_CNTRL_RAM_SIZE (0x2000) /* @@ -110,117 +96,117 @@ extern "C" { /* * System module registers */ -#define PINMUX0 (DAVINCI_SYSTEM_MODULE_BASE + 0x00) -#define PINMUX1 (DAVINCI_SYSTEM_MODULE_BASE + 0x04) -#define PINMUX2 (DAVINCI_SYSTEM_MODULE_BASE + 0x08) -#define PINMUX3 (DAVINCI_SYSTEM_MODULE_BASE + 0x0c) -#define PINMUX4 (DAVINCI_SYSTEM_MODULE_BASE + 0x10) +#define PINMUX0 (DAVINCI_SYSTEM_MODULE_BASE + 0x00) +#define PINMUX1 (DAVINCI_SYSTEM_MODULE_BASE + 0x04) +#define PINMUX2 (DAVINCI_SYSTEM_MODULE_BASE + 0x08) +#define PINMUX3 (DAVINCI_SYSTEM_MODULE_BASE + 0x0c) +#define PINMUX4 (DAVINCI_SYSTEM_MODULE_BASE + 0x10) -#define DM365_ARM_INTMUX (DAVINCI_SYSTEM_MODULE_BASE + 0x18) -#define DM365_EDMA_EVTMUX (DAVINCI_SYSTEM_MODULE_BASE + 0x1C) -#define DAVINCI_PUPDCTL1 (DAVINCI_SYSTEM_MODULE_BASE + 0x7C) +#define DM365_ARM_INTMUX (DAVINCI_SYSTEM_MODULE_BASE + 0x18) +#define DM365_EDMA_EVTMUX (DAVINCI_SYSTEM_MODULE_BASE + 0x1C) +#define DAVINCI_PUPDCTL1 (DAVINCI_SYSTEM_MODULE_BASE + 0x7C) -#define ASYNC_EMIF_REVID 0x00 -#define ASYNC_EMIF_AWCCR 0x04 -#define ASYNC_EMIF_A1CR 0x10 -#define ASYNC_EMIF_A2CR 0x14 -#define ASYNC_EMIF_A3CR 0x18 +#define ASYNC_EMIF_REVID 0x00 +#define ASYNC_EMIF_AWCCR 0x04 +#define ASYNC_EMIF_A1CR 0x10 +#define ASYNC_EMIF_A2CR 0x14 +#define ASYNC_EMIF_A3CR 0x18 /* * Base register addresses common across DM355 and DM365 */ -#define DM3XX_TIMER2_BASE (0x01C20800) -#define DM3XX_REALTIME_BASE (0x01C20C00) -#define DM3XX_PWM3_BASE (0x01C22C00) -#define DM3XX_SPI_BASE (0x01C66000) -#define DM3XX_SPI0_BASE DM3XX_SPI_BASE -#define DM3XX_SPI1_BASE (0x01C66800) -#define DM3XX_SPI2_BASE (0x01C67800) +#define DM3XX_TIMER2_BASE (0x01C20800) +#define DM3XX_REALTIME_BASE (0x01C20C00) +#define DM3XX_PWM3_BASE (0x01C22C00) +#define DM3XX_SPI_BASE (0x01C66000) +#define DM3XX_SPI0_BASE DM3XX_SPI_BASE +#define DM3XX_SPI1_BASE (0x01C66800) +#define DM3XX_SPI2_BASE (0x01C67800) /* * DM365 base register address */ -#define DM365_DMA_3PTC2_BASE (0x01C10800) -#define DM365_DMA_3PTC3_BASE (0x01C10C00) -#define DM365_TIMER3_BASE (0x01C23800) -#define DM365_ADCIF_BASE (0x01C23C00) -#define DM365_SPI3_BASE (0x01C68000) -#define DM365_SPI4_BASE (0x01C23000) -#define DM365_RTC_BASE (0x01C69000) -#define DM365_KEYSCAN_BASE (0x01C69400) -#define DM365_UHPI_BASE (0x01C69800) -#define DM365_IMCOP_BASE (0x01CA0000) -#define DM365_MMC_SD1_BASE (0x01D00000) -#define DM365_MCBSP_BASE (0x01D02000) -#define DM365_UART1_BASE (0x01D06000) -#define DM365_EMAC_CNTRL_BASE (0x01D07000) -#define DM365_EMAC_WRAP_RAM_BASE (0x01D08000) -#define DM365_EMAC_WRAP_CNTRL_BASE (0x01D0A000) -#define DM365_EMAC_MDIO_BASE (0x01D0B000) -#define DM365_VOICE_CODEC_BASE (0x01D0C000) -#define DM365_ASYNC_EMIF_CNTRL_BASE (0x01D10000) -#define DM365_MMC_SD0_BASE (0x01D11000) -#define DM365_MS_BASE (0x01D20000) -#define DM365_KALEIDO_BASE (0x01E00000) +#define DM365_DMA_3PTC2_BASE (0x01C10800) +#define DM365_DMA_3PTC3_BASE (0x01C10C00) +#define DM365_TIMER3_BASE (0x01C23800) +#define DM365_ADCIF_BASE (0x01C23C00) +#define DM365_SPI3_BASE (0x01C68000) +#define DM365_SPI4_BASE (0x01C23000) +#define DM365_RTC_BASE (0x01C69000) +#define DM365_KEYSCAN_BASE (0x01C69400) +#define DM365_UHPI_BASE (0x01C69800) +#define DM365_IMCOP_BASE (0x01CA0000) +#define DM365_MMC_SD1_BASE (0x01D00000) +#define DM365_MCBSP_BASE (0x01D02000) +#define DM365_UART1_BASE (0x01D06000) +#define DM365_EMAC_CNTRL_BASE (0x01D07000) +#define DM365_EMAC_WRAP_RAM_BASE (0x01D08000) +#define DM365_EMAC_WRAP_CNTRL_BASE (0x01D0A000) +#define DM365_EMAC_MDIO_BASE (0x01D0B000) +#define DM365_VOICE_CODEC_BASE (0x01D0C000) +#define DM365_ASYNC_EMIF_CNTRL_BASE (0x01D10000) +#define DM365_MMC_SD0_BASE (0x01D11000) +#define DM365_MS_BASE (0x01D20000) +#define DM365_KALEIDO_BASE (0x01E00000) -#define DAVINCI_UART0_BASE (0x01C20000) +#define DAVINCI_UART0_BASE (0x01C20000) -#define PSC_MDCTL_BASE (0x01c41a00) -#define PSC_MDSTAT_BASE (0x01c41800) -#define PSC_PTCMD (0x01c41120) -#define PSC_PTSTAT (0x01c41128) +#define PSC_MDCTL_BASE (0x01c41a00) +#define PSC_MDSTAT_BASE (0x01c41800) +#define PSC_PTCMD (0x01c41120) +#define PSC_PTSTAT (0x01c41128) -#define DM365_EINT_ENABLE0 0x01c48018 -#define DM365_EINT_ENABLE1 0x01c4801c +#define DM365_EINT_ENABLE0 0x01c48018 +#define DM365_EINT_ENABLE1 0x01c4801c -#define davinci_readb(a) (*(volatile unsigned char *)(a)) -#define davinci_readw(a) (*(volatile unsigned short *)(a)) -#define davinci_readl(a) (*(volatile unsigned int *)(a)) +#define davinci_readb(a) (*(volatile unsigned char *)(a)) +#define davinci_readw(a) (*(volatile unsigned short *)(a)) +#define davinci_readl(a) (*(volatile unsigned int *)(a)) -#define davinci_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define davinci_writew(v,a) (*(volatile unsigned short *)(a) = (v)) -#define davinci_writel(v,a) (*(volatile unsigned int *)(a) = (v)) +#define davinci_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) +#define davinci_writew(v,a) (*(volatile unsigned short *)(a) = (v)) +#define davinci_writel(v,a) (*(volatile unsigned int *)(a) = (v)) -#define readb(a) davinci_readb(a) -#define readw(a) davinci_readw(a) -#define readl(a) davinci_readl(a) +#define readb(a) davinci_readb(a) +#define readw(a) davinci_readw(a) +#define readl(a) davinci_readl(a) -#define write(v,a) davinci_writeb(v,a) -#define writew(v,a) davinci_writew(v,a) -#define writel(v,a) davinci_writel(v,a) +#define write(v,a) davinci_writeb(v,a) +#define writew(v,a) davinci_writew(v,a) +#define writel(v,a) davinci_writel(v,a) /* define timer register struct*/ typedef struct timer_regs_s { - rt_uint32_t pid12; /* 0x0 */ - rt_uint32_t emumgt_clksped; /* 0x4 */ - rt_uint32_t gpint_en; /* 0x8 */ - rt_uint32_t gpdir_dat; /* 0xC */ - rt_uint32_t tim12; /* 0x10 */ - rt_uint32_t tim34; /* 0x14 */ - rt_uint32_t prd12; /* 0x18 */ - rt_uint32_t prd34; /* 0x1C */ - rt_uint32_t tcr; /* 0x20 */ - rt_uint32_t tgcr; /* 0x24 */ - rt_uint32_t wdtcr; /* 0x28 */ - rt_uint32_t tlgc; /* 0x2C */ - rt_uint32_t tlmr; /* 0x30 */ + rt_uint32_t pid12; /* 0x0 */ + rt_uint32_t emumgt_clksped; /* 0x4 */ + rt_uint32_t gpint_en; /* 0x8 */ + rt_uint32_t gpdir_dat; /* 0xC */ + rt_uint32_t tim12; /* 0x10 */ + rt_uint32_t tim34; /* 0x14 */ + rt_uint32_t prd12; /* 0x18 */ + rt_uint32_t prd34; /* 0x1C */ + rt_uint32_t tcr; /* 0x20 */ + rt_uint32_t tgcr; /* 0x24 */ + rt_uint32_t wdtcr; /* 0x28 */ + rt_uint32_t tlgc; /* 0x2C */ + rt_uint32_t tlmr; /* 0x30 */ } timer_regs_t; /*****************************/ /* CPU Mode */ /*****************************/ -#define USERMODE 0x10 -#define FIQMODE 0x11 -#define IRQMODE 0x12 -#define SVCMODE 0x13 -#define ABORTMODE 0x17 -#define UNDEFMODE 0x1b -#define MODEMASK 0x1f -#define NOINT 0xc0 +#define USERMODE 0x10 +#define FIQMODE 0x11 +#define IRQMODE 0x12 +#define SVCMODE 0x13 +#define ABORTMODE 0x17 +#define UNDEFMODE 0x1b +#define MODEMASK 0x1f +#define NOINT 0xc0 struct rt_hw_register { diff --git a/bsp/dm365/platform/dma.c b/bsp/dm365/platform/dma.c index 2acf572f49..baaedf650a 100644 --- a/bsp/dm365/platform/dma.c +++ b/bsp/dm365/platform/dma.c @@ -1,113 +1,99 @@ /* - * File : dma.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2010-11-13 weety first version + * Date Author Notes + * 2010-11-13 weety first version */ #include /* Offsets matching "struct edmacc_param" */ -#define PARM_OPT 0x00 -#define PARM_SRC 0x04 -#define PARM_A_B_CNT 0x08 -#define PARM_DST 0x0c -#define PARM_SRC_DST_BIDX 0x10 -#define PARM_LINK_BCNTRLD 0x14 -#define PARM_SRC_DST_CIDX 0x18 -#define PARM_CCNT 0x1c +#define PARM_OPT 0x00 +#define PARM_SRC 0x04 +#define PARM_A_B_CNT 0x08 +#define PARM_DST 0x0c +#define PARM_SRC_DST_BIDX 0x10 +#define PARM_LINK_BCNTRLD 0x14 +#define PARM_SRC_DST_CIDX 0x18 +#define PARM_CCNT 0x1c -#define PARM_SIZE 0x20 +#define PARM_SIZE 0x20 /* Offsets for EDMA CC global channel registers and their shadows */ -#define SH_ER 0x00 /* 64 bits */ -#define SH_ECR 0x08 /* 64 bits */ -#define SH_ESR 0x10 /* 64 bits */ -#define SH_CER 0x18 /* 64 bits */ -#define SH_EER 0x20 /* 64 bits */ -#define SH_EECR 0x28 /* 64 bits */ -#define SH_EESR 0x30 /* 64 bits */ -#define SH_SER 0x38 /* 64 bits */ -#define SH_SECR 0x40 /* 64 bits */ -#define SH_IER 0x50 /* 64 bits */ -#define SH_IECR 0x58 /* 64 bits */ -#define SH_IESR 0x60 /* 64 bits */ -#define SH_IPR 0x68 /* 64 bits */ -#define SH_ICR 0x70 /* 64 bits */ -#define SH_IEVAL 0x78 -#define SH_QER 0x80 -#define SH_QEER 0x84 -#define SH_QEECR 0x88 -#define SH_QEESR 0x8c -#define SH_QSER 0x90 -#define SH_QSECR 0x94 -#define SH_SIZE 0x200 +#define SH_ER 0x00 /* 64 bits */ +#define SH_ECR 0x08 /* 64 bits */ +#define SH_ESR 0x10 /* 64 bits */ +#define SH_CER 0x18 /* 64 bits */ +#define SH_EER 0x20 /* 64 bits */ +#define SH_EECR 0x28 /* 64 bits */ +#define SH_EESR 0x30 /* 64 bits */ +#define SH_SER 0x38 /* 64 bits */ +#define SH_SECR 0x40 /* 64 bits */ +#define SH_IER 0x50 /* 64 bits */ +#define SH_IECR 0x58 /* 64 bits */ +#define SH_IESR 0x60 /* 64 bits */ +#define SH_IPR 0x68 /* 64 bits */ +#define SH_ICR 0x70 /* 64 bits */ +#define SH_IEVAL 0x78 +#define SH_QER 0x80 +#define SH_QEER 0x84 +#define SH_QEECR 0x88 +#define SH_QEESR 0x8c +#define SH_QSER 0x90 +#define SH_QSECR 0x94 +#define SH_SIZE 0x200 /* Offsets for EDMA CC global registers */ -#define EDMA_REV 0x0000 -#define EDMA_CCCFG 0x0004 -#define EDMA_QCHMAP 0x0200 /* 8 registers */ -#define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */ -#define EDMA_QDMAQNUM 0x0260 -#define EDMA_QUETCMAP 0x0280 -#define EDMA_QUEPRI 0x0284 -#define EDMA_EMR 0x0300 /* 64 bits */ -#define EDMA_EMCR 0x0308 /* 64 bits */ -#define EDMA_QEMR 0x0310 -#define EDMA_QEMCR 0x0314 -#define EDMA_CCERR 0x0318 -#define EDMA_CCERRCLR 0x031c -#define EDMA_EEVAL 0x0320 -#define EDMA_DRAE 0x0340 /* 4 x 64 bits*/ -#define EDMA_QRAE 0x0380 /* 4 registers */ -#define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */ -#define EDMA_QSTAT 0x0600 /* 2 registers */ -#define EDMA_QWMTHRA 0x0620 -#define EDMA_QWMTHRB 0x0624 -#define EDMA_CCSTAT 0x0640 +#define EDMA_REV 0x0000 +#define EDMA_CCCFG 0x0004 +#define EDMA_QCHMAP 0x0200 /* 8 registers */ +#define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */ +#define EDMA_QDMAQNUM 0x0260 +#define EDMA_QUETCMAP 0x0280 +#define EDMA_QUEPRI 0x0284 +#define EDMA_EMR 0x0300 /* 64 bits */ +#define EDMA_EMCR 0x0308 /* 64 bits */ +#define EDMA_QEMR 0x0310 +#define EDMA_QEMCR 0x0314 +#define EDMA_CCERR 0x0318 +#define EDMA_CCERRCLR 0x031c +#define EDMA_EEVAL 0x0320 +#define EDMA_DRAE 0x0340 /* 4 x 64 bits*/ +#define EDMA_QRAE 0x0380 /* 4 registers */ +#define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */ +#define EDMA_QSTAT 0x0600 /* 2 registers */ +#define EDMA_QWMTHRA 0x0620 +#define EDMA_QWMTHRB 0x0624 +#define EDMA_CCSTAT 0x0640 -#define EDMA_M 0x1000 /* global channel registers */ -#define EDMA_ECR 0x1008 -#define EDMA_ECRH 0x100C -#define EDMA_SHADOW0 0x2000 /* 4 regions shadowing global channels */ -#define EDMA_PARM 0x4000 /* 128 param entries */ +#define EDMA_M 0x1000 /* global channel registers */ +#define EDMA_ECR 0x1008 +#define EDMA_ECRH 0x100C +#define EDMA_SHADOW0 0x2000 /* 4 regions shadowing global channels */ +#define EDMA_PARM 0x4000 /* 128 param entries */ -#define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5)) +#define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5)) -#define EDMA_DCHMAP 0x0100 /* 64 registers */ -#define CHMAP_EXIST BIT(24) +#define EDMA_DCHMAP 0x0100 /* 64 registers */ +#define CHMAP_EXIST BIT(24) #define EDMA_MAX_DMACH 64 #define EDMA_MAX_PARAMENTRY 512 -#define EDMA_CC0_BASE_REG 0x01c00000 -#define EDMA_TC0_BASE_REG 0x01c10000 -#define EDMA_TC1_BASE_REG 0x01c10400 -#define EDMA_TC2_BASE_REG 0x01c10800 -#define EDMA_TC3_BASE_REG 0x01c10c00 +#define EDMA_CC0_BASE_REG 0x01c00000 +#define EDMA_TC0_BASE_REG 0x01c10000 +#define EDMA_TC1_BASE_REG 0x01c10400 +#define EDMA_TC2_BASE_REG 0x01c10800 +#define EDMA_TC3_BASE_REG 0x01c10c00 -#define min_t(type, x, y) ({ \ - type __min1 = (x); \ - type __min2 = (y); \ - __min1 < __min2 ? __min1: __min2; }) +#define min_t(type, x, y) ({ \ + type __min1 = (x); \ + type __min2 = (y); \ + __min1 < __min2 ? __min1: __min2; }) @@ -117,130 +103,130 @@ static void volatile *edmacc_regs_base[EDMA_MAX_CC]; static inline unsigned int edma_read(unsigned ctlr, int offset) { - return (unsigned int)davinci_readl(edmacc_regs_base[ctlr] + offset); + return (unsigned int)davinci_readl(edmacc_regs_base[ctlr] + offset); } static inline void edma_write(unsigned ctlr, int offset, int val) { - davinci_writel(val, edmacc_regs_base[ctlr] + offset); + davinci_writel(val, edmacc_regs_base[ctlr] + offset); } static inline void edma_modify(unsigned ctlr, int offset, unsigned and, - unsigned or) + unsigned or) { - unsigned val = edma_read(ctlr, offset); - val &= and; - val |= or; - edma_write(ctlr, offset, val); + unsigned val = edma_read(ctlr, offset); + val &= and; + val |= or; + edma_write(ctlr, offset, val); } static inline void edma_and(unsigned ctlr, int offset, unsigned and) { - unsigned val = edma_read(ctlr, offset); - val &= and; - edma_write(ctlr, offset, val); + unsigned val = edma_read(ctlr, offset); + val &= and; + edma_write(ctlr, offset, val); } static inline void edma_or(unsigned ctlr, int offset, unsigned or) { - unsigned val = edma_read(ctlr, offset); - val |= or; - edma_write(ctlr, offset, val); + unsigned val = edma_read(ctlr, offset); + val |= or; + edma_write(ctlr, offset, val); } static inline unsigned int edma_read_array(unsigned ctlr, int offset, int i) { - return edma_read(ctlr, offset + (i << 2)); + return edma_read(ctlr, offset + (i << 2)); } static inline void edma_write_array(unsigned ctlr, int offset, int i, - unsigned val) + unsigned val) { - edma_write(ctlr, offset + (i << 2), val); + edma_write(ctlr, offset + (i << 2), val); } static inline void edma_modify_array(unsigned ctlr, int offset, int i, - unsigned and, unsigned or) + unsigned and, unsigned or) { - edma_modify(ctlr, offset + (i << 2), and, or); + edma_modify(ctlr, offset + (i << 2), and, or); } static inline void edma_or_array(unsigned ctlr, int offset, int i, unsigned or) { - edma_or(ctlr, offset + (i << 2), or); + edma_or(ctlr, offset + (i << 2), or); } static inline void edma_or_array2(unsigned ctlr, int offset, int i, int j, - unsigned or) + unsigned or) { - edma_or(ctlr, offset + ((i*2 + j) << 2), or); + edma_or(ctlr, offset + ((i*2 + j) << 2), or); } static inline void edma_write_array2(unsigned ctlr, int offset, int i, int j, - unsigned val) + unsigned val) { - edma_write(ctlr, offset + ((i*2 + j) << 2), val); + edma_write(ctlr, offset + ((i*2 + j) << 2), val); } static inline unsigned int edma_shadow0_read(unsigned ctlr, int offset) { - return edma_read(ctlr, EDMA_SHADOW0 + offset); + return edma_read(ctlr, EDMA_SHADOW0 + offset); } static inline unsigned int edma_shadow0_read_array(unsigned ctlr, int offset, - int i) + int i) { - return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2)); + return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2)); } static inline void edma_shadow0_write(unsigned ctlr, int offset, unsigned val) { - edma_write(ctlr, EDMA_SHADOW0 + offset, val); + edma_write(ctlr, EDMA_SHADOW0 + offset, val); } static inline void edma_shadow0_write_array(unsigned ctlr, int offset, int i, - unsigned val) + unsigned val) { - edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val); + edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val); } static inline unsigned int edma_parm_read(unsigned ctlr, int offset, - int param_no) + int param_no) { - return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5)); + return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5)); } static inline void edma_parm_write(unsigned ctlr, int offset, int param_no, - unsigned val) + unsigned val) { - edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val); + edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val); } static inline void edma_parm_modify(unsigned ctlr, int offset, int param_no, - unsigned and, unsigned or) + unsigned and, unsigned or) { - edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or); + edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or); } static inline void edma_parm_and(unsigned ctlr, int offset, int param_no, - unsigned and) + unsigned and) { - edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and); + edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and); } static inline void edma_parm_or(unsigned ctlr, int offset, int param_no, - unsigned or) + unsigned or) { - edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or); + edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or); } #if 0 static inline void set_bits(int offset, int len, unsigned long *p) { - for (; len > 0; len--) - set_bit(offset + (len - 1), p); + for (; len > 0; len--) + set_bit(offset + (len - 1), p); } static inline void clear_bits(int offset, int len, unsigned long *p) { - for (; len > 0; len--) - clear_bit(offset + (len - 1), p); + for (; len > 0; len--) + clear_bit(offset + (len - 1), p); } #endif /*****************************************************************************/ -#define BIT(nr) (1UL << (nr)) +#define BIT(nr) (1UL << (nr)) #define BITS_PER_LONG 32 -#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) -#define BIT_WORD(nr) ((nr) / BITS_PER_LONG) -#define BITS_PER_BYTE 8 +#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) +#define BIT_WORD(nr) ((nr) / BITS_PER_LONG) +#define BITS_PER_BYTE 8 #define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) -#define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long)) +#define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long)) #define DECLARE_BITMAP(name,bits) \ - unsigned long name[BITS_TO_LONGS(bits)] + unsigned long name[BITS_TO_LONGS(bits)] /** * test_bit - Determine whether a bit is set @@ -249,44 +235,44 @@ static inline void clear_bits(int offset, int len, unsigned long *p) */ static inline int test_bit(int nr, const volatile unsigned long *addr) { - return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1))); + return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1))); } static inline void clear_bit(int nr, volatile unsigned long *addr) { - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - rt_base_t level; + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + rt_base_t level; - level = rt_hw_interrupt_disable(); - *p &= ~mask; - rt_hw_interrupt_enable(level); + level = rt_hw_interrupt_disable(); + *p &= ~mask; + rt_hw_interrupt_enable(level); } static inline int test_and_set_bit(int nr, volatile unsigned long *addr) { - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - unsigned long old; - rt_base_t level; + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old; + rt_base_t level; - level = rt_hw_interrupt_disable(); - old = *p; - *p = old | mask; - rt_hw_interrupt_enable(level); + level = rt_hw_interrupt_disable(); + old = *p; + *p = old | mask; + rt_hw_interrupt_enable(level); - return (old & mask) != 0; + return (old & mask) != 0; } static inline void set_bit(int nr, volatile unsigned long *addr) { - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - rt_base_t level; + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + rt_base_t level; - level = rt_hw_interrupt_disable(); - *p |= mask; - rt_hw_interrupt_enable(level); + level = rt_hw_interrupt_disable(); + *p |= mask; + rt_hw_interrupt_enable(level); } /* @@ -300,45 +286,45 @@ extern int _find_next_bit_le(const unsigned long *p, int size, int offset); /* * These are the little endian, atomic definitions. */ -#define find_first_zero_bit(p,sz) _find_first_zero_bit_le(p,sz) -#define find_next_zero_bit(p,sz,off) _find_next_zero_bit_le(p,sz,off) -#define find_first_bit(p,sz) _find_first_bit_le(p,sz) -#define find_next_bit(p,sz,off) _find_next_bit_le(p,sz,off) +#define find_first_zero_bit(p,sz) _find_first_zero_bit_le(p,sz) +#define find_next_zero_bit(p,sz,off) _find_next_zero_bit_le(p,sz,off) +#define find_first_bit(p,sz) _find_first_bit_le(p,sz) +#define find_next_bit(p,sz,off) _find_next_bit_le(p,sz,off) /* actual number of DMA channels and slots on this silicon */ struct edma { - /* how many dma resources of each type */ - unsigned num_channels; - unsigned num_region; - unsigned num_slots; - unsigned num_tc; - unsigned num_cc; - enum dma_event_q default_queue; + /* how many dma resources of each type */ + unsigned num_channels; + unsigned num_region; + unsigned num_slots; + unsigned num_tc; + unsigned num_cc; + enum dma_event_q default_queue; - /* list of channels with no even trigger; terminated by "-1" */ - const rt_int8_t *noevent; + /* list of channels with no even trigger; terminated by "-1" */ + const rt_int8_t *noevent; - /* The edma_inuse bit for each PaRAM slot is clear unless the - * channel is in use ... by ARM or DSP, for QDMA, or whatever. - */ - DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY); + /* The edma_inuse bit for each PaRAM slot is clear unless the + * channel is in use ... by ARM or DSP, for QDMA, or whatever. + */ + DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY); - /* The edma_unused bit for each channel is clear unless - * it is not being used on this platform. It uses a bit - * of SOC-specific initialization code. - */ - DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH); + /* The edma_unused bit for each channel is clear unless + * it is not being used on this platform. It uses a bit + * of SOC-specific initialization code. + */ + DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH); - unsigned irq_res_start; - unsigned irq_res_end; + unsigned irq_res_start; + unsigned irq_res_end; - struct dma_interrupt_data { - void (*callback)(unsigned channel, unsigned short ch_status, - void *data); - void *data; - } intr_data[EDMA_MAX_DMACH]; + struct dma_interrupt_data { + void (*callback)(unsigned channel, unsigned short ch_status, + void *data); + void *data; + } intr_data[EDMA_MAX_DMACH]; }; static struct edma *edma_cc[EDMA_MAX_CC]; @@ -346,38 +332,38 @@ static int arch_num_cc; /* dummy param set used to (re)initialize parameter RAM slots */ static const struct edmacc_param dummy_paramset = { - .link_bcntrld = 0xffff, - .ccnt = 1, + .link_bcntrld = 0xffff, + .ccnt = 1, }; /*****************************************************************************/ static void map_dmach_queue(unsigned ctlr, unsigned ch_no, - enum dma_event_q queue_no) + enum dma_event_q queue_no) { - int bit = (ch_no & 0x7) * 4; + int bit = (ch_no & 0x7) * 4; - /* default to low priority queue */ - if (queue_no == EVENTQ_DEFAULT) - queue_no = edma_cc[ctlr]->default_queue; + /* default to low priority queue */ + if (queue_no == EVENTQ_DEFAULT) + queue_no = edma_cc[ctlr]->default_queue; - queue_no &= 7; - edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3), - ~(0x7 << bit), queue_no << bit); + queue_no &= 7; + edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3), + ~(0x7 << bit), queue_no << bit); } static void map_queue_tc(unsigned ctlr, int queue_no, int tc_no) { - int bit = queue_no * 4; - edma_modify(ctlr, EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit)); + int bit = queue_no * 4; + edma_modify(ctlr, EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit)); } static void assign_priority_to_queue(unsigned ctlr, int queue_no, - int priority) + int priority) { - int bit = queue_no * 4; - edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit), - ((priority & 0x7) << bit)); + int bit = queue_no * 4; + edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit), + ((priority & 0x7) << bit)); } /** @@ -393,45 +379,45 @@ static void assign_priority_to_queue(unsigned ctlr, int queue_no, */ static void map_dmach_param(unsigned ctlr) { - int i; - for (i = 0; i < EDMA_MAX_DMACH; i++) - edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5)); + int i; + for (i = 0; i < EDMA_MAX_DMACH; i++) + edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5)); } static inline void setup_dma_interrupt(unsigned lch, - void (*callback)(unsigned channel, rt_uint16_t ch_status, void *data), - void *data) + void (*callback)(unsigned channel, rt_uint16_t ch_status, void *data), + void *data) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(lch); - lch = EDMA_CHAN_SLOT(lch); + ctlr = EDMA_CTLR(lch); + lch = EDMA_CHAN_SLOT(lch); - if (!callback) - edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5, - BIT(lch & 0x1f)); + if (!callback) + edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5, + BIT(lch & 0x1f)); - edma_cc[ctlr]->intr_data[lch].callback = callback; - edma_cc[ctlr]->intr_data[lch].data = data; + edma_cc[ctlr]->intr_data[lch].callback = callback; + edma_cc[ctlr]->intr_data[lch].data = data; - if (callback) { - edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5, - BIT(lch & 0x1f)); - edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5, - BIT(lch & 0x1f)); - } + if (callback) { + edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5, + BIT(lch & 0x1f)); + edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5, + BIT(lch & 0x1f)); + } } static int irq2ctlr(int irq) { - if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end) - return 0; - else if (irq >= edma_cc[1]->irq_res_start && - irq <= edma_cc[1]->irq_res_end) - return 1; + if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end) + return 0; + else if (irq >= edma_cc[1]->irq_res_start && + irq <= edma_cc[1]->irq_res_end) + return 1; - return -1; + return -1; } /****************************************************************************** @@ -441,53 +427,53 @@ static int irq2ctlr(int irq) *****************************************************************************/ static void dma_irq_handler(int irq, void *data) { - int i; - int ctlr; - unsigned int cnt = 0; + int i; + int ctlr; + unsigned int cnt = 0; - ctlr = irq2ctlr(irq); - if (ctlr < 0) - return ; + ctlr = irq2ctlr(irq); + if (ctlr < 0) + return ; - edma_dbg("dma_irq_handler\n"); + edma_dbg("dma_irq_handler\n"); - if ((edma_shadow0_read_array(ctlr, SH_IPR, 0) == 0) && - (edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0)) - return ; + if ((edma_shadow0_read_array(ctlr, SH_IPR, 0) == 0) && + (edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0)) + return ; - while (1) { - int j; - if (edma_shadow0_read_array(ctlr, SH_IPR, 0) & - edma_shadow0_read_array(ctlr, SH_IER, 0)) - j = 0; - else if (edma_shadow0_read_array(ctlr, SH_IPR, 1) & - edma_shadow0_read_array(ctlr, SH_IER, 1)) - j = 1; - else - break; - edma_dbg("IPR%d %08x\n", j, - edma_shadow0_read_array(ctlr, SH_IPR, j)); - for (i = 0; i < 32; i++) { - int k = (j << 5) + i; - if ((edma_shadow0_read_array(ctlr, SH_IPR, j) & BIT(i)) - && (edma_shadow0_read_array(ctlr, - SH_IER, j) & BIT(i))) { - /* Clear the corresponding IPR bits */ - edma_shadow0_write_array(ctlr, SH_ICR, j, - BIT(i)); - if (edma_cc[ctlr]->intr_data[k].callback) - edma_cc[ctlr]->intr_data[k].callback( - k, DMA_COMPLETE, - edma_cc[ctlr]->intr_data[k]. - data); - } - } - cnt++; - if (cnt > 10) - break; - } - edma_shadow0_write(ctlr, SH_IEVAL, 1); - return ; + while (1) { + int j; + if (edma_shadow0_read_array(ctlr, SH_IPR, 0) & + edma_shadow0_read_array(ctlr, SH_IER, 0)) + j = 0; + else if (edma_shadow0_read_array(ctlr, SH_IPR, 1) & + edma_shadow0_read_array(ctlr, SH_IER, 1)) + j = 1; + else + break; + edma_dbg("IPR%d %08x\n", j, + edma_shadow0_read_array(ctlr, SH_IPR, j)); + for (i = 0; i < 32; i++) { + int k = (j << 5) + i; + if ((edma_shadow0_read_array(ctlr, SH_IPR, j) & BIT(i)) + && (edma_shadow0_read_array(ctlr, + SH_IER, j) & BIT(i))) { + /* Clear the corresponding IPR bits */ + edma_shadow0_write_array(ctlr, SH_ICR, j, + BIT(i)); + if (edma_cc[ctlr]->intr_data[k].callback) + edma_cc[ctlr]->intr_data[k].callback( + k, DMA_COMPLETE, + edma_cc[ctlr]->intr_data[k]. + data); + } + } + cnt++; + if (cnt > 10) + break; + } + edma_shadow0_write(ctlr, SH_IEVAL, 1); + return ; } /****************************************************************************** @@ -497,90 +483,90 @@ static void dma_irq_handler(int irq, void *data) *****************************************************************************/ static void dma_ccerr_handler(int irq, void *data) { - int i; - int ctlr; - unsigned int cnt = 0; + int i; + int ctlr; + unsigned int cnt = 0; - ctlr = irq2ctlr(irq); - if (ctlr < 0) - return ; + ctlr = irq2ctlr(irq); + if (ctlr < 0) + return ; - edma_dbg("dma_ccerr_handler\n"); + edma_dbg("dma_ccerr_handler\n"); - if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) && - (edma_read_array(ctlr, EDMA_EMR, 1) == 0) && - (edma_read(ctlr, EDMA_QEMR) == 0) && - (edma_read(ctlr, EDMA_CCERR) == 0)) - return ; + if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) && + (edma_read_array(ctlr, EDMA_EMR, 1) == 0) && + (edma_read(ctlr, EDMA_QEMR) == 0) && + (edma_read(ctlr, EDMA_CCERR) == 0)) + return ; - while (1) { - int j = -1; - if (edma_read_array(ctlr, EDMA_EMR, 0)) - j = 0; - else if (edma_read_array(ctlr, EDMA_EMR, 1)) - j = 1; - if (j >= 0) { - edma_dbg("EMR%d %08x\n", j, - edma_read_array(ctlr, EDMA_EMR, j)); - for (i = 0; i < 32; i++) { - int k = (j << 5) + i; - if (edma_read_array(ctlr, EDMA_EMR, j) & - BIT(i)) { - /* Clear the corresponding EMR bits */ - edma_write_array(ctlr, EDMA_EMCR, j, - BIT(i)); - /* Clear any SER */ - edma_shadow0_write_array(ctlr, SH_SECR, - j, BIT(i)); - if (edma_cc[ctlr]->intr_data[k]. - callback) { - edma_cc[ctlr]->intr_data[k]. - callback(k, - DMA_CC_ERROR, - edma_cc[ctlr]->intr_data - [k].data); - } - } - } - } else if (edma_read(ctlr, EDMA_QEMR)) { - edma_dbg("QEMR %02x\n", - edma_read(ctlr, EDMA_QEMR)); - for (i = 0; i < 8; i++) { - if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) { - /* Clear the corresponding IPR bits */ - edma_write(ctlr, EDMA_QEMCR, BIT(i)); - edma_shadow0_write(ctlr, SH_QSECR, - BIT(i)); + while (1) { + int j = -1; + if (edma_read_array(ctlr, EDMA_EMR, 0)) + j = 0; + else if (edma_read_array(ctlr, EDMA_EMR, 1)) + j = 1; + if (j >= 0) { + edma_dbg("EMR%d %08x\n", j, + edma_read_array(ctlr, EDMA_EMR, j)); + for (i = 0; i < 32; i++) { + int k = (j << 5) + i; + if (edma_read_array(ctlr, EDMA_EMR, j) & + BIT(i)) { + /* Clear the corresponding EMR bits */ + edma_write_array(ctlr, EDMA_EMCR, j, + BIT(i)); + /* Clear any SER */ + edma_shadow0_write_array(ctlr, SH_SECR, + j, BIT(i)); + if (edma_cc[ctlr]->intr_data[k]. + callback) { + edma_cc[ctlr]->intr_data[k]. + callback(k, + DMA_CC_ERROR, + edma_cc[ctlr]->intr_data + [k].data); + } + } + } + } else if (edma_read(ctlr, EDMA_QEMR)) { + edma_dbg("QEMR %02x\n", + edma_read(ctlr, EDMA_QEMR)); + for (i = 0; i < 8; i++) { + if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) { + /* Clear the corresponding IPR bits */ + edma_write(ctlr, EDMA_QEMCR, BIT(i)); + edma_shadow0_write(ctlr, SH_QSECR, + BIT(i)); - /* NOTE: not reported!! */ - } - } - } else if (edma_read(ctlr, EDMA_CCERR)) { - edma_dbg("CCERR %08x\n", - edma_read(ctlr, EDMA_CCERR)); - /* FIXME: CCERR.BIT(16) ignored! much better - * to just write CCERRCLR with CCERR value... - */ - for (i = 0; i < 8; i++) { - if (edma_read(ctlr, EDMA_CCERR) & BIT(i)) { - /* Clear the corresponding IPR bits */ - edma_write(ctlr, EDMA_CCERRCLR, BIT(i)); + /* NOTE: not reported!! */ + } + } + } else if (edma_read(ctlr, EDMA_CCERR)) { + edma_dbg("CCERR %08x\n", + edma_read(ctlr, EDMA_CCERR)); + /* FIXME: CCERR.BIT(16) ignored! much better + * to just write CCERRCLR with CCERR value... + */ + for (i = 0; i < 8; i++) { + if (edma_read(ctlr, EDMA_CCERR) & BIT(i)) { + /* Clear the corresponding IPR bits */ + edma_write(ctlr, EDMA_CCERRCLR, BIT(i)); - /* NOTE: not reported!! */ - } - } - } - if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) && - (edma_read_array(ctlr, EDMA_EMR, 1) == 0) && - (edma_read(ctlr, EDMA_QEMR) == 0) && - (edma_read(ctlr, EDMA_CCERR) == 0)) - break; - cnt++; - if (cnt > 10) - break; - } - edma_write(ctlr, EDMA_EEVAL, 1); - return ; + /* NOTE: not reported!! */ + } + } + } + if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) && + (edma_read_array(ctlr, EDMA_EMR, 1) == 0) && + (edma_read(ctlr, EDMA_QEMR) == 0) && + (edma_read(ctlr, EDMA_CCERR) == 0)) + break; + cnt++; + if (cnt > 10) + break; + } + edma_write(ctlr, EDMA_EEVAL, 1); + return ; } /****************************************************************************** @@ -589,92 +575,92 @@ static void dma_ccerr_handler(int irq, void *data) * *****************************************************************************/ -#define tc_errs_handled RT_FALSE/* disabled as long as they're NOPs */ +#define tc_errs_handled RT_FALSE/* disabled as long as they're NOPs */ static void dma_tc0err_handler(int irq, void *data) { - edma_dbg("dma_tc0err_handler\n"); - return ; + edma_dbg("dma_tc0err_handler\n"); + return ; } static void dma_tc1err_handler(int irq, void *data) { - edma_dbg("dma_tc1err_handler\n"); - return ; + edma_dbg("dma_tc1err_handler\n"); + return ; } static int reserve_contiguous_slots(int ctlr, unsigned int id, - unsigned int num_slots, - unsigned int start_slot) + unsigned int num_slots, + unsigned int start_slot) { - int i, j; - unsigned int count = num_slots; - int stop_slot = start_slot; - DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY); + int i, j; + unsigned int count = num_slots; + int stop_slot = start_slot; + DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY); - for (i = start_slot; i < edma_cc[ctlr]->num_slots; ++i) { - j = EDMA_CHAN_SLOT(i); - if (!test_and_set_bit(j, edma_cc[ctlr]->edma_inuse)) { - /* Record our current beginning slot */ - if (count == num_slots) - stop_slot = i; + for (i = start_slot; i < edma_cc[ctlr]->num_slots; ++i) { + j = EDMA_CHAN_SLOT(i); + if (!test_and_set_bit(j, edma_cc[ctlr]->edma_inuse)) { + /* Record our current beginning slot */ + if (count == num_slots) + stop_slot = i; - count--; - set_bit(j, tmp_inuse); + count--; + set_bit(j, tmp_inuse); - if (count == 0) - break; - } else { - clear_bit(j, tmp_inuse); + if (count == 0) + break; + } else { + clear_bit(j, tmp_inuse); - if (id == EDMA_CONT_PARAMS_FIXED_EXACT) { - stop_slot = i; - break; - } else { - count = num_slots; - } - } - } + if (id == EDMA_CONT_PARAMS_FIXED_EXACT) { + stop_slot = i; + break; + } else { + count = num_slots; + } + } + } - /* - * We have to clear any bits that we set - * if we run out parameter RAM slots, i.e we do find a set - * of contiguous parameter RAM slots but do not find the exact number - * requested as we may reach the total number of parameter RAM slots - */ - if (i == edma_cc[ctlr]->num_slots) - stop_slot = i; + /* + * We have to clear any bits that we set + * if we run out parameter RAM slots, i.e we do find a set + * of contiguous parameter RAM slots but do not find the exact number + * requested as we may reach the total number of parameter RAM slots + */ + if (i == edma_cc[ctlr]->num_slots) + stop_slot = i; - for (j = start_slot; j < stop_slot; j++) - if (test_bit(j, tmp_inuse)) - clear_bit(j, edma_cc[ctlr]->edma_inuse); + for (j = start_slot; j < stop_slot; j++) + if (test_bit(j, tmp_inuse)) + clear_bit(j, edma_cc[ctlr]->edma_inuse); - if (count) - return -RT_EBUSY; + if (count) + return -RT_EBUSY; - for (j = i - num_slots + 1; j <= i; ++j) - rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(j)), - &dummy_paramset, PARM_SIZE); + for (j = i - num_slots + 1; j <= i; ++j) + rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(j)), + &dummy_paramset, PARM_SIZE); - return EDMA_CTLR_CHAN(ctlr, i - num_slots + 1); + return EDMA_CTLR_CHAN(ctlr, i - num_slots + 1); } #if 0 static int prepare_unused_channel_list(struct device *dev, void *data) { - struct platform_device *pdev = to_platform_device(dev); - int i, ctlr; + struct platform_device *pdev = to_platform_device(dev); + int i, ctlr; - for (i = 0; i < pdev->num_resources; i++) { - if ((pdev->resource[i].flags & IORESOURCE_DMA) && - (int)pdev->resource[i].start >= 0) { - ctlr = EDMA_CTLR(pdev->resource[i].start); - clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start), - edma_cc[ctlr]->edma_unused); - } - } + for (i = 0; i < pdev->num_resources; i++) { + if ((pdev->resource[i].flags & IORESOURCE_DMA) && + (int)pdev->resource[i].start >= 0) { + ctlr = EDMA_CTLR(pdev->resource[i].start); + clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start), + edma_cc[ctlr]->edma_unused); + } + } - return 0; + return 0; } #endif @@ -690,8 +676,8 @@ static rt_bool_t unused_chan_list_done; * @callback: optional; to be issued on DMA completion or errors * @data: passed to callback * @eventq_no: an EVENTQ_* constant, used to choose which Transfer - * Controller (TC) executes requests using this channel. Use - * EVENTQ_DEFAULT unless you really need a high priority queue. + * Controller (TC) executes requests using this channel. Use + * EVENTQ_DEFAULT unless you really need a high priority queue. * * This allocates a DMA channel and its associated parameter RAM slot. * The parameter RAM is initialized to hold a dummy transfer. @@ -715,77 +701,77 @@ static rt_bool_t unused_chan_list_done; * Returns the number of the channel, else negative errno. */ int edma_alloc_channel(int channel, - void (*callback)(unsigned channel, rt_uint16_t ch_status, void *data), - void *data, - enum dma_event_q eventq_no) + void (*callback)(unsigned channel, rt_uint16_t ch_status, void *data), + void *data, + enum dma_event_q eventq_no) { - unsigned i, done = 0, ctlr = 0; - int ret = 0; + unsigned i, done = 0, ctlr = 0; + int ret = 0; #if 0 - if (!unused_chan_list_done) { - /* - * Scan all the platform devices to find out the EDMA channels - * used and clear them in the unused list, making the rest - * available for ARM usage. - */ - ret = bus_for_each_dev(&platform_bus_type, NULL, NULL, - prepare_unused_channel_list); - if (ret < 0) - return ret; + if (!unused_chan_list_done) { + /* + * Scan all the platform devices to find out the EDMA channels + * used and clear them in the unused list, making the rest + * available for ARM usage. + */ + ret = bus_for_each_dev(&platform_bus_type, NULL, NULL, + prepare_unused_channel_list); + if (ret < 0) + return ret; - unused_chan_list_done = true; - } + unused_chan_list_done = true; + } #endif - if (channel >= 0) { - ctlr = EDMA_CTLR(channel); - channel = EDMA_CHAN_SLOT(channel); - clear_bit(channel, edma_cc[ctlr]->edma_unused); - } + if (channel >= 0) { + ctlr = EDMA_CTLR(channel); + channel = EDMA_CHAN_SLOT(channel); + clear_bit(channel, edma_cc[ctlr]->edma_unused); + } - if (channel < 0) { - for (i = 0; i < arch_num_cc; i++) { - channel = 0; - for (;;) { - channel = find_next_bit(edma_cc[i]->edma_unused, - edma_cc[i]->num_channels, - channel); - if (channel == edma_cc[i]->num_channels) - break; - if (!test_and_set_bit(channel, - edma_cc[i]->edma_inuse)) { - done = 1; - ctlr = i; - break; - } - channel++; - } - if (done) - break; - } - if (!done) - return -RT_ENOMEM; - } else if (channel >= edma_cc[ctlr]->num_channels) { - return -RT_ERROR; - } else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) { - return -RT_EBUSY; - } + if (channel < 0) { + for (i = 0; i < arch_num_cc; i++) { + channel = 0; + for (;;) { + channel = find_next_bit(edma_cc[i]->edma_unused, + edma_cc[i]->num_channels, + channel); + if (channel == edma_cc[i]->num_channels) + break; + if (!test_and_set_bit(channel, + edma_cc[i]->edma_inuse)) { + done = 1; + ctlr = i; + break; + } + channel++; + } + if (done) + break; + } + if (!done) + return -RT_ENOMEM; + } else if (channel >= edma_cc[ctlr]->num_channels) { + return -RT_ERROR; + } else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) { + return -RT_EBUSY; + } - /* ensure access through shadow region 0 */ - edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f)); + /* ensure access through shadow region 0 */ + edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f)); - /* ensure no events are pending */ - edma_stop(EDMA_CTLR_CHAN(ctlr, channel)); - rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(channel)), - &dummy_paramset, PARM_SIZE); + /* ensure no events are pending */ + edma_stop(EDMA_CTLR_CHAN(ctlr, channel)); + rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(channel)), + &dummy_paramset, PARM_SIZE); - if (callback) - setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel), - callback, data); + if (callback) + setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel), + callback, data); - map_dmach_queue(ctlr, channel, eventq_no); + map_dmach_queue(ctlr, channel, eventq_no); - return EDMA_CTLR_CHAN(ctlr, channel); + return EDMA_CTLR_CHAN(ctlr, channel); } @@ -802,20 +788,20 @@ int edma_alloc_channel(int channel, */ void edma_free_channel(unsigned channel) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(channel); - channel = EDMA_CHAN_SLOT(channel); + ctlr = EDMA_CTLR(channel); + channel = EDMA_CHAN_SLOT(channel); - if (channel >= edma_cc[ctlr]->num_channels) - return; + if (channel >= edma_cc[ctlr]->num_channels) + return; - setup_dma_interrupt(channel, RT_NULL, RT_NULL); - /* REVISIT should probably take out of shadow region 0 */ + setup_dma_interrupt(channel, RT_NULL, RT_NULL); + /* REVISIT should probably take out of shadow region 0 */ - rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(channel)), - &dummy_paramset, PARM_SIZE); - clear_bit(channel, edma_cc[ctlr]->edma_inuse); + rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(channel)), + &dummy_paramset, PARM_SIZE); + clear_bit(channel, edma_cc[ctlr]->edma_inuse); } @@ -835,30 +821,30 @@ void edma_free_channel(unsigned channel) */ int edma_alloc_slot(unsigned ctlr, int slot) { - if (slot >= 0) - slot = EDMA_CHAN_SLOT(slot); + if (slot >= 0) + slot = EDMA_CHAN_SLOT(slot); - if (slot < 0) { - slot = edma_cc[ctlr]->num_channels; - for (;;) { - slot = find_next_zero_bit(edma_cc[ctlr]->edma_inuse, - edma_cc[ctlr]->num_slots, slot); - if (slot == edma_cc[ctlr]->num_slots) - return -RT_ENOMEM; - if (!test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) - break; - } - } else if (slot < edma_cc[ctlr]->num_channels || - slot >= edma_cc[ctlr]->num_slots) { - return -RT_ERROR; - } else if (test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) { - return -RT_EBUSY; - } + if (slot < 0) { + slot = edma_cc[ctlr]->num_channels; + for (;;) { + slot = find_next_zero_bit(edma_cc[ctlr]->edma_inuse, + edma_cc[ctlr]->num_slots, slot); + if (slot == edma_cc[ctlr]->num_slots) + return -RT_ENOMEM; + if (!test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) + break; + } + } else if (slot < edma_cc[ctlr]->num_channels || + slot >= edma_cc[ctlr]->num_slots) { + return -RT_ERROR; + } else if (test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) { + return -RT_EBUSY; + } - rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(slot)), - &dummy_paramset, PARM_SIZE); + rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(slot)), + &dummy_paramset, PARM_SIZE); - return EDMA_CTLR_CHAN(ctlr, slot); + return EDMA_CTLR_CHAN(ctlr, slot); } @@ -872,18 +858,18 @@ int edma_alloc_slot(unsigned ctlr, int slot) */ void edma_free_slot(unsigned slot) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(slot); - slot = EDMA_CHAN_SLOT(slot); + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); - if (slot < edma_cc[ctlr]->num_channels || - slot >= edma_cc[ctlr]->num_slots) - return; + if (slot < edma_cc[ctlr]->num_channels || + slot >= edma_cc[ctlr]->num_slots) + return; - rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(slot)), - &dummy_paramset, PARM_SIZE); - clear_bit(slot, edma_cc[ctlr]->edma_inuse); + rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(slot)), + &dummy_paramset, PARM_SIZE); + clear_bit(slot, edma_cc[ctlr]->edma_inuse); } @@ -915,35 +901,35 @@ void edma_free_slot(unsigned slot) */ int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count) { - /* - * The start slot requested should be greater than - * the number of channels and lesser than the total number - * of slots - */ - if ((id != EDMA_CONT_PARAMS_ANY) && - (slot < edma_cc[ctlr]->num_channels || - slot >= edma_cc[ctlr]->num_slots)) - return -RT_ERROR; + /* + * The start slot requested should be greater than + * the number of channels and lesser than the total number + * of slots + */ + if ((id != EDMA_CONT_PARAMS_ANY) && + (slot < edma_cc[ctlr]->num_channels || + slot >= edma_cc[ctlr]->num_slots)) + return -RT_ERROR; - /* - * The number of parameter RAM slots requested cannot be less than 1 - * and cannot be more than the number of slots minus the number of - * channels - */ - if (count < 1 || count > - (edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels)) - return -RT_ERROR; + /* + * The number of parameter RAM slots requested cannot be less than 1 + * and cannot be more than the number of slots minus the number of + * channels + */ + if (count < 1 || count > + (edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels)) + return -RT_ERROR; - switch (id) { - case EDMA_CONT_PARAMS_ANY: - return reserve_contiguous_slots(ctlr, id, count, - edma_cc[ctlr]->num_channels); - case EDMA_CONT_PARAMS_FIXED_EXACT: - case EDMA_CONT_PARAMS_FIXED_NOT_EXACT: - return reserve_contiguous_slots(ctlr, id, count, slot); - default: - return -RT_ERROR; - } + switch (id) { + case EDMA_CONT_PARAMS_ANY: + return reserve_contiguous_slots(ctlr, id, count, + edma_cc[ctlr]->num_channels); + case EDMA_CONT_PARAMS_FIXED_EXACT: + case EDMA_CONT_PARAMS_FIXED_NOT_EXACT: + return reserve_contiguous_slots(ctlr, id, count, slot); + default: + return -RT_ERROR; + } } @@ -963,27 +949,27 @@ int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count) */ int edma_free_cont_slots(unsigned slot, int count) { - unsigned ctlr, slot_to_free; - int i; + unsigned ctlr, slot_to_free; + int i; - ctlr = EDMA_CTLR(slot); - slot = EDMA_CHAN_SLOT(slot); + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); - if (slot < edma_cc[ctlr]->num_channels || - slot >= edma_cc[ctlr]->num_slots || - count < 1) - return -RT_ERROR; + if (slot < edma_cc[ctlr]->num_channels || + slot >= edma_cc[ctlr]->num_slots || + count < 1) + return -RT_ERROR; - for (i = slot; i < slot + count; ++i) { - ctlr = EDMA_CTLR(i); - slot_to_free = EDMA_CHAN_SLOT(i); + for (i = slot; i < slot + count; ++i) { + ctlr = EDMA_CTLR(i); + slot_to_free = EDMA_CHAN_SLOT(i); - rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free)), - &dummy_paramset, PARM_SIZE); - clear_bit(slot_to_free, edma_cc[ctlr]->edma_inuse); - } + rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free)), + &dummy_paramset, PARM_SIZE); + clear_bit(slot_to_free, edma_cc[ctlr]->edma_inuse); + } - return 0; + return 0; } @@ -997,35 +983,35 @@ int edma_free_cont_slots(unsigned slot, int count) * @src_port: physical address of source (memory, controller FIFO, etc) * @addressMode: INCR, except in very rare cases * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the - * width to use when addressing the fifo (e.g. W8BIT, W32BIT) + * width to use when addressing the fifo (e.g. W8BIT, W32BIT) * * Note that the source address is modified during the DMA transfer * according to edma_set_src_index(). */ void edma_set_src(unsigned slot, rt_uint32_t src_port, - enum address_mode mode, enum fifo_width width) + enum address_mode mode, enum fifo_width width) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(slot); - slot = EDMA_CHAN_SLOT(slot); + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); - if (slot < edma_cc[ctlr]->num_slots) { - unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); + if (slot < edma_cc[ctlr]->num_slots) { + unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); - if (mode) { - /* set SAM and program FWID */ - i = (i & ~(EDMA_FWID)) | (SAM | ((width & 0x7) << 8)); - } else { - /* clear SAM */ - i &= ~SAM; - } - edma_parm_write(ctlr, PARM_OPT, slot, i); + if (mode) { + /* set SAM and program FWID */ + i = (i & ~(EDMA_FWID)) | (SAM | ((width & 0x7) << 8)); + } else { + /* clear SAM */ + i &= ~SAM; + } + edma_parm_write(ctlr, PARM_OPT, slot, i); - /* set the source port address - in source register of param structure */ - edma_parm_write(ctlr, PARM_SRC, slot, src_port); - } + /* set the source port address + in source register of param structure */ + edma_parm_write(ctlr, PARM_SRC, slot, src_port); + } } @@ -1035,34 +1021,34 @@ void edma_set_src(unsigned slot, rt_uint32_t src_port, * @dest_port: physical address of destination (memory, controller FIFO, etc) * @addressMode: INCR, except in very rare cases * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the - * width to use when addressing the fifo (e.g. W8BIT, W32BIT) + * width to use when addressing the fifo (e.g. W8BIT, W32BIT) * * Note that the destination address is modified during the DMA transfer * according to edma_set_dest_index(). */ void edma_set_dest(unsigned slot, rt_uint32_t dest_port, - enum address_mode mode, enum fifo_width width) + enum address_mode mode, enum fifo_width width) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(slot); - slot = EDMA_CHAN_SLOT(slot); + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); - if (slot < edma_cc[ctlr]->num_slots) { - unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); + if (slot < edma_cc[ctlr]->num_slots) { + unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); - if (mode) { - /* set DAM and program FWID */ - i = (i & ~(EDMA_FWID)) | (DAM | ((width & 0x7) << 8)); - } else { - /* clear DAM */ - i &= ~DAM; - } - edma_parm_write(ctlr, PARM_OPT, slot, i); - /* set the destination port address - in dest register of param structure */ - edma_parm_write(ctlr, PARM_DST, slot, dest_port); - } + if (mode) { + /* set DAM and program FWID */ + i = (i & ~(EDMA_FWID)) | (DAM | ((width & 0x7) << 8)); + } else { + /* clear DAM */ + i &= ~DAM; + } + edma_parm_write(ctlr, PARM_OPT, slot, i); + /* set the destination port address + in dest register of param structure */ + edma_parm_write(ctlr, PARM_DST, slot, dest_port); + } } @@ -1077,17 +1063,17 @@ void edma_set_dest(unsigned slot, rt_uint32_t dest_port, */ void edma_get_position(unsigned slot, rt_uint32_t *src, rt_uint32_t *dst) { - struct edmacc_param temp; - unsigned ctlr; + struct edmacc_param temp; + unsigned ctlr; - ctlr = EDMA_CTLR(slot); - slot = EDMA_CHAN_SLOT(slot); + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); - edma_read_slot(EDMA_CTLR_CHAN(ctlr, slot), &temp); - if (src != RT_NULL) - *src = temp.src; - if (dst != RT_NULL) - *dst = temp.dst; + edma_read_slot(EDMA_CTLR_CHAN(ctlr, slot), &temp); + if (src != RT_NULL) + *src = temp.src; + if (dst != RT_NULL) + *dst = temp.dst; } @@ -1103,17 +1089,17 @@ void edma_get_position(unsigned slot, rt_uint32_t *src, rt_uint32_t *dst) */ void edma_set_src_index(unsigned slot, rt_int16_t src_bidx, rt_int16_t src_cidx) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(slot); - slot = EDMA_CHAN_SLOT(slot); + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); - if (slot < edma_cc[ctlr]->num_slots) { - edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, - 0xffff0000, src_bidx); - edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, - 0xffff0000, src_cidx); - } + if (slot < edma_cc[ctlr]->num_slots) { + edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, + 0xffff0000, src_bidx); + edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, + 0xffff0000, src_cidx); + } } @@ -1129,17 +1115,17 @@ void edma_set_src_index(unsigned slot, rt_int16_t src_bidx, rt_int16_t src_cidx) */ void edma_set_dest_index(unsigned slot, rt_int16_t dest_bidx, rt_int16_t dest_cidx) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(slot); - slot = EDMA_CHAN_SLOT(slot); + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); - if (slot < edma_cc[ctlr]->num_slots) { - edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, - 0x0000ffff, dest_bidx << 16); - edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, - 0x0000ffff, dest_cidx << 16); - } + if (slot < edma_cc[ctlr]->num_slots) { + edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, + 0x0000ffff, dest_bidx << 16); + edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, + 0x0000ffff, dest_cidx << 16); + } } @@ -1150,7 +1136,7 @@ void edma_set_dest_index(unsigned slot, rt_int16_t dest_bidx, rt_int16_t dest_ci * @bcnt: how many arrays per frame (at least one) * @ccnt: how many frames per block (at least one) * @bcnt_rld: used only for A-Synchronized transfers; this specifies - * the value to reload into bcnt when it decrements to zero + * the value to reload into bcnt when it decrements to zero * @sync_mode: ASYNC or ABSYNC * * See the EDMA3 documentation to understand how to configure and link @@ -1173,25 +1159,25 @@ void edma_set_dest_index(unsigned slot, rt_int16_t dest_bidx, rt_int16_t dest_ci * efficient burst modes to access memory. */ void edma_set_transfer_params(unsigned slot, - rt_uint16_t acnt, rt_uint16_t bcnt, rt_uint16_t ccnt, - rt_uint16_t bcnt_rld, enum sync_dimension sync_mode) + rt_uint16_t acnt, rt_uint16_t bcnt, rt_uint16_t ccnt, + rt_uint16_t bcnt_rld, enum sync_dimension sync_mode) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(slot); - slot = EDMA_CHAN_SLOT(slot); + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); - if (slot < edma_cc[ctlr]->num_slots) { - edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot, - 0x0000ffff, bcnt_rld << 16); - if (sync_mode == ASYNC) - edma_parm_and(ctlr, PARM_OPT, slot, ~SYNCDIM); - else - edma_parm_or(ctlr, PARM_OPT, slot, SYNCDIM); - /* Set the acount, bcount, ccount registers */ - edma_parm_write(ctlr, PARM_A_B_CNT, slot, (bcnt << 16) | acnt); - edma_parm_write(ctlr, PARM_CCNT, slot, ccnt); - } + if (slot < edma_cc[ctlr]->num_slots) { + edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot, + 0x0000ffff, bcnt_rld << 16); + if (sync_mode == ASYNC) + edma_parm_and(ctlr, PARM_OPT, slot, ~SYNCDIM); + else + edma_parm_or(ctlr, PARM_OPT, slot, SYNCDIM); + /* Set the acount, bcount, ccount registers */ + edma_parm_write(ctlr, PARM_A_B_CNT, slot, (bcnt << 16) | acnt); + edma_parm_write(ctlr, PARM_CCNT, slot, ccnt); + } } @@ -1204,19 +1190,19 @@ void edma_set_transfer_params(unsigned slot, */ void edma_link(unsigned from, unsigned to) { - unsigned ctlr_from, ctlr_to; + unsigned ctlr_from, ctlr_to; - ctlr_from = EDMA_CTLR(from); - from = EDMA_CHAN_SLOT(from); - ctlr_to = EDMA_CTLR(to); - to = EDMA_CHAN_SLOT(to); + ctlr_from = EDMA_CTLR(from); + from = EDMA_CHAN_SLOT(from); + ctlr_to = EDMA_CTLR(to); + to = EDMA_CHAN_SLOT(to); - if (from >= edma_cc[ctlr_from]->num_slots) - return; - if (to >= edma_cc[ctlr_to]->num_slots) - return; - edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000, - PARM_OFFSET(to)); + if (from >= edma_cc[ctlr_from]->num_slots) + return; + if (to >= edma_cc[ctlr_to]->num_slots) + return; + edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000, + PARM_OFFSET(to)); } @@ -1229,14 +1215,14 @@ void edma_link(unsigned from, unsigned to) */ void edma_unlink(unsigned from) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(from); - from = EDMA_CHAN_SLOT(from); + ctlr = EDMA_CTLR(from); + from = EDMA_CHAN_SLOT(from); - if (from >= edma_cc[ctlr]->num_slots) - return; - edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff); + if (from >= edma_cc[ctlr]->num_slots) + return; + edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff); } @@ -1256,15 +1242,15 @@ void edma_unlink(unsigned from) */ void edma_write_slot(unsigned slot, const struct edmacc_param *param) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(slot); - slot = EDMA_CHAN_SLOT(slot); + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); - if (slot >= edma_cc[ctlr]->num_slots) - return; - rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(slot)), param, - PARM_SIZE); + if (slot >= edma_cc[ctlr]->num_slots) + return; + rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(slot)), param, + PARM_SIZE); } @@ -1278,15 +1264,15 @@ void edma_write_slot(unsigned slot, const struct edmacc_param *param) */ void edma_read_slot(unsigned slot, struct edmacc_param *param) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(slot); - slot = EDMA_CHAN_SLOT(slot); + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); - if (slot >= edma_cc[ctlr]->num_slots) - return; - rt_memcpy(param, (void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(slot)), - PARM_SIZE); + if (slot >= edma_cc[ctlr]->num_slots) + return; + rt_memcpy(param, (void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(slot)), + PARM_SIZE); } @@ -1303,16 +1289,16 @@ void edma_read_slot(unsigned slot, struct edmacc_param *param) */ void edma_pause(unsigned channel) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(channel); - channel = EDMA_CHAN_SLOT(channel); + ctlr = EDMA_CTLR(channel); + channel = EDMA_CHAN_SLOT(channel); - if (channel < edma_cc[ctlr]->num_channels) { - unsigned int mask = BIT(channel & 0x1f); + if (channel < edma_cc[ctlr]->num_channels) { + unsigned int mask = BIT(channel & 0x1f); - edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask); - } + edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask); + } } @@ -1324,16 +1310,16 @@ void edma_pause(unsigned channel) */ void edma_resume(unsigned channel) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(channel); - channel = EDMA_CHAN_SLOT(channel); + ctlr = EDMA_CTLR(channel); + channel = EDMA_CHAN_SLOT(channel); - if (channel < edma_cc[ctlr]->num_channels) { - unsigned int mask = BIT(channel & 0x1f); + if (channel < edma_cc[ctlr]->num_channels) { + unsigned int mask = BIT(channel & 0x1f); - edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask); - } + edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask); + } } @@ -1350,38 +1336,38 @@ void edma_resume(unsigned channel) */ int edma_start(unsigned channel) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(channel); - channel = EDMA_CHAN_SLOT(channel); + ctlr = EDMA_CTLR(channel); + channel = EDMA_CHAN_SLOT(channel); - if (channel < edma_cc[ctlr]->num_channels) { - int j = channel >> 5; - unsigned int mask = BIT(channel & 0x1f); + if (channel < edma_cc[ctlr]->num_channels) { + int j = channel >> 5; + unsigned int mask = BIT(channel & 0x1f); - /* EDMA channels without event association */ - if (test_bit(channel, edma_cc[ctlr]->edma_unused)) { - edma_dbg("EDMA: ESR%d %08x\n", j, - edma_shadow0_read_array(ctlr, SH_ESR, j)); - edma_shadow0_write_array(ctlr, SH_ESR, j, mask); - return 0; - } + /* EDMA channels without event association */ + if (test_bit(channel, edma_cc[ctlr]->edma_unused)) { + edma_dbg("EDMA: ESR%d %08x\n", j, + edma_shadow0_read_array(ctlr, SH_ESR, j)); + edma_shadow0_write_array(ctlr, SH_ESR, j, mask); + return 0; + } - /* EDMA channel with event association */ - edma_dbg("EDMA: ER%d %08x\n", j, - edma_shadow0_read_array(ctlr, SH_ER, j)); - /* Clear any pending event or error */ - edma_write_array(ctlr, EDMA_ECR, j, mask); - edma_write_array(ctlr, EDMA_EMCR, j, mask); - /* Clear any SER */ - edma_shadow0_write_array(ctlr, SH_SECR, j, mask); - edma_shadow0_write_array(ctlr, SH_EESR, j, mask); - edma_dbg("EDMA: EER%d %08x\n", j, - edma_shadow0_read_array(ctlr, SH_EER, j)); - return 0; - } + /* EDMA channel with event association */ + edma_dbg("EDMA: ER%d %08x\n", j, + edma_shadow0_read_array(ctlr, SH_ER, j)); + /* Clear any pending event or error */ + edma_write_array(ctlr, EDMA_ECR, j, mask); + edma_write_array(ctlr, EDMA_EMCR, j, mask); + /* Clear any SER */ + edma_shadow0_write_array(ctlr, SH_SECR, j, mask); + edma_shadow0_write_array(ctlr, SH_EESR, j, mask); + edma_dbg("EDMA: EER%d %08x\n", j, + edma_shadow0_read_array(ctlr, SH_EER, j)); + return 0; + } - return -RT_ERROR; + return -RT_ERROR; } @@ -1396,27 +1382,27 @@ int edma_start(unsigned channel) */ void edma_stop(unsigned channel) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(channel); - channel = EDMA_CHAN_SLOT(channel); + ctlr = EDMA_CTLR(channel); + channel = EDMA_CHAN_SLOT(channel); - if (channel < edma_cc[ctlr]->num_channels) { - int j = channel >> 5; - unsigned int mask = BIT(channel & 0x1f); + if (channel < edma_cc[ctlr]->num_channels) { + int j = channel >> 5; + unsigned int mask = BIT(channel & 0x1f); - edma_shadow0_write_array(ctlr, SH_EECR, j, mask); - edma_shadow0_write_array(ctlr, SH_ECR, j, mask); - edma_shadow0_write_array(ctlr, SH_SECR, j, mask); - edma_write_array(ctlr, EDMA_EMCR, j, mask); + edma_shadow0_write_array(ctlr, SH_EECR, j, mask); + edma_shadow0_write_array(ctlr, SH_ECR, j, mask); + edma_shadow0_write_array(ctlr, SH_SECR, j, mask); + edma_write_array(ctlr, EDMA_EMCR, j, mask); - edma_dbg("EDMA: EER%d %08x\n", j, - edma_shadow0_read_array(ctlr, SH_EER, j)); + edma_dbg("EDMA: EER%d %08x\n", j, + edma_shadow0_read_array(ctlr, SH_EER, j)); - /* REVISIT: consider guarding against inappropriate event - * chaining by overwriting with dummy_paramset. - */ - } + /* REVISIT: consider guarding against inappropriate event + * chaining by overwriting with dummy_paramset. + */ + } } @@ -1435,45 +1421,45 @@ void edma_stop(unsigned channel) void edma_clean_channel(unsigned channel) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(channel); - channel = EDMA_CHAN_SLOT(channel); + ctlr = EDMA_CTLR(channel); + channel = EDMA_CHAN_SLOT(channel); - if (channel < edma_cc[ctlr]->num_channels) { - int j = (channel >> 5); - unsigned int mask = BIT(channel & 0x1f); + if (channel < edma_cc[ctlr]->num_channels) { + int j = (channel >> 5); + unsigned int mask = BIT(channel & 0x1f); - edma_dbg("EDMA: EMR%d %08x\n", j, - edma_read_array(ctlr, EDMA_EMR, j)); - edma_shadow0_write_array(ctlr, SH_ECR, j, mask); - /* Clear the corresponding EMR bits */ - edma_write_array(ctlr, EDMA_EMCR, j, mask); - /* Clear any SER */ - edma_shadow0_write_array(ctlr, SH_SECR, j, mask); - edma_write(ctlr, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0)); - } + edma_dbg("EDMA: EMR%d %08x\n", j, + edma_read_array(ctlr, EDMA_EMR, j)); + edma_shadow0_write_array(ctlr, SH_ECR, j, mask); + /* Clear the corresponding EMR bits */ + edma_write_array(ctlr, EDMA_EMCR, j, mask); + /* Clear any SER */ + edma_shadow0_write_array(ctlr, SH_SECR, j, mask); + edma_write(ctlr, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0)); + } } /* * edma_clear_event - clear an outstanding event on the DMA channel * Arguments: - * channel - channel number + * channel - channel number */ void edma_clear_event(unsigned channel) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(channel); - channel = EDMA_CHAN_SLOT(channel); + ctlr = EDMA_CTLR(channel); + channel = EDMA_CHAN_SLOT(channel); - if (channel >= edma_cc[ctlr]->num_channels) - return; - if (channel < 32) - edma_write(ctlr, EDMA_ECR, BIT(channel)); - else - edma_write(ctlr, EDMA_ECRH, BIT(channel - 32)); + if (channel >= edma_cc[ctlr]->num_channels) + return; + if (channel < 32) + edma_write(ctlr, EDMA_ECR, BIT(channel)); + else + edma_write(ctlr, EDMA_ECRH, BIT(channel - 32)); } @@ -1481,112 +1467,112 @@ void edma_clear_event(unsigned channel) int edma_init(struct edma_soc_info **info) { - //struct edma_soc_info **info = pdev->dev.platform_data; - const rt_int8_t (*queue_priority_mapping)[2]; - const rt_int8_t (*queue_tc_mapping)[2]; - int i, j, off, ln, found = 0; - int status = -1; - const rt_int16_t (*rsv_chans)[2]; - const rt_int16_t (*rsv_slots)[2]; - int irq[EDMA_MAX_CC] = {0, 0}; - int err_irq[EDMA_MAX_CC] = {0, 0}; + //struct edma_soc_info **info = pdev->dev.platform_data; + const rt_int8_t (*queue_priority_mapping)[2]; + const rt_int8_t (*queue_tc_mapping)[2]; + int i, j, off, ln, found = 0; + int status = -1; + const rt_int16_t (*rsv_chans)[2]; + const rt_int16_t (*rsv_slots)[2]; + int irq[EDMA_MAX_CC] = {0, 0}; + int err_irq[EDMA_MAX_CC] = {0, 0}; - RT_ASSERT(info != RT_NULL); + RT_ASSERT(info != RT_NULL); - psc_change_state(DAVINCI_DM365_LPSC_TPCC, PSC_ENABLE); - psc_change_state(DAVINCI_DM365_LPSC_TPTC0, PSC_ENABLE); - psc_change_state(DAVINCI_DM365_LPSC_TPTC1, PSC_ENABLE); - psc_change_state(DAVINCI_DM365_LPSC_TPTC2, PSC_ENABLE); - psc_change_state(DAVINCI_DM365_LPSC_TPTC3, PSC_ENABLE); + psc_change_state(DAVINCI_DM365_LPSC_TPCC, PSC_ENABLE); + psc_change_state(DAVINCI_DM365_LPSC_TPTC0, PSC_ENABLE); + psc_change_state(DAVINCI_DM365_LPSC_TPTC1, PSC_ENABLE); + psc_change_state(DAVINCI_DM365_LPSC_TPTC2, PSC_ENABLE); + psc_change_state(DAVINCI_DM365_LPSC_TPTC3, PSC_ENABLE); - edmacc_regs_base[0] = (void *)EDMA_CC0_BASE_REG; + edmacc_regs_base[0] = (void *)EDMA_CC0_BASE_REG; - edma_cc[0] = rt_malloc(sizeof(struct edma)); - if (!edma_cc[0]) { - status = -RT_ENOMEM; - goto fail1; - } - rt_memset(edma_cc[0], 0, sizeof(struct edma)); + edma_cc[0] = rt_malloc(sizeof(struct edma)); + if (!edma_cc[0]) { + status = -RT_ENOMEM; + goto fail1; + } + rt_memset(edma_cc[0], 0, sizeof(struct edma)); - edma_cc[0]->num_channels = min_t(unsigned, info[0]->n_channel, - EDMA_MAX_DMACH); - edma_cc[0]->num_slots = min_t(unsigned, info[0]->n_slot, - EDMA_MAX_PARAMENTRY); - edma_cc[0]->num_cc = min_t(unsigned, info[0]->n_cc, - EDMA_MAX_CC); + edma_cc[0]->num_channels = min_t(unsigned, info[0]->n_channel, + EDMA_MAX_DMACH); + edma_cc[0]->num_slots = min_t(unsigned, info[0]->n_slot, + EDMA_MAX_PARAMENTRY); + edma_cc[0]->num_cc = min_t(unsigned, info[0]->n_cc, + EDMA_MAX_CC); - edma_cc[0]->default_queue = info[0]->default_queue; - if (!edma_cc[0]->default_queue) - edma_cc[0]->default_queue = EVENTQ_1; + edma_cc[0]->default_queue = info[0]->default_queue; + if (!edma_cc[0]->default_queue) + edma_cc[0]->default_queue = EVENTQ_1; - edma_dbg("DMA REG BASE ADDR=%p\n", - edmacc_regs_base[j]); + edma_dbg("DMA REG BASE ADDR=%p\n", + edmacc_regs_base[j]); - for (i = 0; i < edma_cc[0]->num_slots; i++) - rt_memcpy((void *)(edmacc_regs_base[0] + PARM_OFFSET(i)), - &dummy_paramset, PARM_SIZE); + for (i = 0; i < edma_cc[0]->num_slots; i++) + rt_memcpy((void *)(edmacc_regs_base[0] + PARM_OFFSET(i)), + &dummy_paramset, PARM_SIZE); - /* Mark all channels as unused */ - rt_memset(edma_cc[0]->edma_unused, 0xff, - sizeof(edma_cc[0]->edma_unused)); + /* Mark all channels as unused */ + rt_memset(edma_cc[0]->edma_unused, 0xff, + sizeof(edma_cc[0]->edma_unused)); - edma_cc[0]->irq_res_start = IRQ_CCINT0; - rt_hw_interrupt_install(IRQ_CCINT0, dma_irq_handler, RT_NULL, "edma"); - rt_hw_interrupt_umask(IRQ_CCINT0); + edma_cc[0]->irq_res_start = IRQ_CCINT0; + rt_hw_interrupt_install(IRQ_CCINT0, dma_irq_handler, RT_NULL, "edma"); + rt_hw_interrupt_umask(IRQ_CCINT0); - edma_cc[0]->irq_res_end = IRQ_CCERRINT; - rt_hw_interrupt_install(IRQ_CCERRINT, dma_ccerr_handler, RT_NULL, "edma_error"); - rt_hw_interrupt_umask(IRQ_CCERRINT); + edma_cc[0]->irq_res_end = IRQ_CCERRINT; + rt_hw_interrupt_install(IRQ_CCERRINT, dma_ccerr_handler, RT_NULL, "edma_error"); + rt_hw_interrupt_umask(IRQ_CCERRINT); - /* Everything lives on transfer controller 1 until otherwise - * specified. This way, long transfers on the low priority queue - * started by the codec engine will not cause audio defects. - */ - for (i = 0; i < edma_cc[0]->num_channels; i++) - map_dmach_queue(0, i, EVENTQ_1); + /* Everything lives on transfer controller 1 until otherwise + * specified. This way, long transfers on the low priority queue + * started by the codec engine will not cause audio defects. + */ + for (i = 0; i < edma_cc[0]->num_channels; i++) + map_dmach_queue(0, i, EVENTQ_1); - queue_tc_mapping = info[0]->queue_tc_mapping; - queue_priority_mapping = info[0]->queue_priority_mapping; + queue_tc_mapping = info[0]->queue_tc_mapping; + queue_priority_mapping = info[0]->queue_priority_mapping; - /* Event queue to TC mapping */ - for (i = 0; queue_tc_mapping[i][0] != -1; i++) - map_queue_tc(0, queue_tc_mapping[i][0], - queue_tc_mapping[i][1]); + /* Event queue to TC mapping */ + for (i = 0; queue_tc_mapping[i][0] != -1; i++) + map_queue_tc(0, queue_tc_mapping[i][0], + queue_tc_mapping[i][1]); - /* Event queue priority mapping */ - for (i = 0; queue_priority_mapping[i][0] != -1; i++) - assign_priority_to_queue(0, - queue_priority_mapping[i][0], - queue_priority_mapping[i][1]); + /* Event queue priority mapping */ + for (i = 0; queue_priority_mapping[i][0] != -1; i++) + assign_priority_to_queue(0, + queue_priority_mapping[i][0], + queue_priority_mapping[i][1]); - /* Map the channel to param entry if channel mapping logic - * exist - */ - if (edma_read(0, EDMA_CCCFG) & CHMAP_EXIST) - map_dmach_param(0); + /* Map the channel to param entry if channel mapping logic + * exist + */ + if (edma_read(0, EDMA_CCCFG) & CHMAP_EXIST) + map_dmach_param(0); - for (i = 0; i < info[0]->n_region; i++) { - edma_write_array2(0, EDMA_DRAE, i, 0, 0x0); - edma_write_array2(0, EDMA_DRAE, i, 1, 0x0); - edma_write_array(0, EDMA_QRAE, i, 0x0); - } - arch_num_cc++; + for (i = 0; i < info[0]->n_region; i++) { + edma_write_array2(0, EDMA_DRAE, i, 0, 0x0); + edma_write_array2(0, EDMA_DRAE, i, 1, 0x0); + edma_write_array(0, EDMA_QRAE, i, 0x0); + } + arch_num_cc++; - if (tc_errs_handled) { - rt_hw_interrupt_install(IRQ_TCERRINT0, dma_tc0err_handler, "edma_tc0"); - rt_hw_interrupt_umask(IRQ_TCERRINT0); - rt_hw_interrupt_install(IRQ_TCERRINT, dma_tc1err_handler, "edma_tc1"); - rt_hw_interrupt_umask(IRQ_TCERRINT); - } + if (tc_errs_handled) { + rt_hw_interrupt_install(IRQ_TCERRINT0, dma_tc0err_handler, "edma_tc0"); + rt_hw_interrupt_umask(IRQ_TCERRINT0); + rt_hw_interrupt_install(IRQ_TCERRINT, dma_tc1err_handler, "edma_tc1"); + rt_hw_interrupt_umask(IRQ_TCERRINT); + } - return 0; + return 0; fail: fail1: - rt_free(edma_cc[0]); + rt_free(edma_cc[0]); - return status; + return status; } diff --git a/bsp/dm365/platform/edma.h b/bsp/dm365/platform/edma.h index 34d5bb1ef7..57007f5bbb 100644 --- a/bsp/dm365/platform/edma.h +++ b/bsp/dm365/platform/edma.h @@ -1,39 +1,25 @@ /* - * File : edma.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2010-11-13 weety first version + * Date Author Notes + * 2010-11-13 weety first version */ /* * This EDMA3 programming framework exposes two basic kinds of resource: * - * Channel Triggers transfers, usually from a hardware event but - * also manually or by "chaining" from DMA completions. - * Each channel is coupled to a Parameter RAM (PaRAM) slot. + * Channel Triggers transfers, usually from a hardware event but + * also manually or by "chaining" from DMA completions. + * Each channel is coupled to a Parameter RAM (PaRAM) slot. * - * Slot Each PaRAM slot holds a DMA transfer descriptor (PaRAM - * "set"), source and destination addresses, a link to a - * next PaRAM slot (if any), options for the transfer, and - * instructions for updating those addresses. There are - * more than twice as many slots as event channels. + * Slot Each PaRAM slot holds a DMA transfer descriptor (PaRAM + * "set"), source and destination addresses, a link to a + * next PaRAM slot (if any), options for the transfer, and + * instructions for updating those addresses. There are + * more than twice as many slots as event channels. * * Each PaRAM set describes a sequence of transfers, either for one large * buffer or for several discontiguous smaller buffers. An EDMA transfer @@ -66,14 +52,14 @@ /* PaRAM slots are laid out like this */ struct edmacc_param { - unsigned int opt; - unsigned int src; - unsigned int a_b_cnt; - unsigned int dst; - unsigned int src_dst_bidx; - unsigned int link_bcntrld; - unsigned int src_dst_cidx; - unsigned int ccnt; + unsigned int opt; + unsigned int src; + unsigned int a_b_cnt; + unsigned int dst; + unsigned int src_dst_bidx; + unsigned int link_bcntrld; + unsigned int src_dst_cidx; + unsigned int ccnt; }; #define CCINT0_INTERRUPT 16 @@ -82,110 +68,110 @@ struct edmacc_param { #define TCERRINT1_INTERRUPT 19 /* fields in edmacc_param.opt */ -#define SAM BIT(0) -#define DAM BIT(1) -#define SYNCDIM BIT(2) -#define STATIC BIT(3) -#define EDMA_FWID (0x07 << 8) -#define TCCMODE BIT(11) -#define EDMA_TCC(t) ((t) << 12) -#define TCINTEN BIT(20) -#define ITCINTEN BIT(21) -#define TCCHEN BIT(22) -#define ITCCHEN BIT(23) +#define SAM BIT(0) +#define DAM BIT(1) +#define SYNCDIM BIT(2) +#define STATIC BIT(3) +#define EDMA_FWID (0x07 << 8) +#define TCCMODE BIT(11) +#define EDMA_TCC(t) ((t) << 12) +#define TCINTEN BIT(20) +#define ITCINTEN BIT(21) +#define TCCHEN BIT(22) +#define ITCCHEN BIT(23) #define TRWORD (0x7<<2) #define PAENTRY (0x1ff<<5) /* DM365 specific EDMA3 Events Information */ enum dm365_edma_ch { - DM365_DMA_TIMER3_TINT6, - DM365_DMA_TIMER3_TINT7, - DM365_DMA_MCBSP_TX = 2, - DM365_DMA_VCIF_TX = 2, - DM365_DMA_MCBSP_RX = 3, - DM365_DMA_VCIF_RX = 3, - DM365_DMA_VPSS_EVT1, - DM365_DMA_VPSS_EVT2, - DM365_DMA_VPSS_EVT3, - DM365_DMA_VPSS_EVT4, - DM365_DMA_TIMER2_TINT4, - DM365_DMA_TIMER2_TINT5, - DM365_DMA_SPI2XEVT, - DM365_DMA_SPI2REVT, - DM365_DMA_IMCOP_IMX0INT = 12, - DM365_DMA_KALEIDO_ARMINT = 12, - DM365_DMA_IMCOP_SEQINT, - DM365_DMA_SPI1XEVT, - DM365_DMA_SPI1REVT, - DM365_DMA_SPI0XEVT, - DM365_DMA_SPI0REVT, - DM365_DMA_URXEVT0 = 18, - DM365_DMA_SPI3XEVT = 18, - DM365_DMA_UTXEVT0 = 19, - DM365_DMA_SPI3REVT = 19, - DM365_DMA_URXEVT1, - DM365_DMA_UTXEVT1, - DM365_DMA_TIMER4_TINT8, - DM365_DMA_TIMER4_TINT9, - DM365_DMA_RTOINT, - DM365_DMA_GPIONT9, - DM365_DMA_MMC0RXEVT = 26, - DM365_DMA_MEMSTK_MSEVT = 26, - DM365_DMA_MMC0TXEVT, - DM365_DMA_I2C_ICREVT, - DM365_DMA_I2C_ICXEVT, - DM365_DMA_MMC1RXEVT, - DM365_DMA_MMC1TXEVT, - DM365_DMA_GPIOINT0, - DM365_DMA_GPIOINT1, - DM365_DMA_GPIOINT2, - DM365_DMA_GPIOINT3, - DM365_DMA_GPIOINT4, - DM365_DMA_GPIOINT5, - DM365_DMA_GPIOINT6, - DM365_DMA_GPIOINT7, - DM365_DMA_GPIOINT10 = 40, - DM365_DMA_EMAC_RXTHREESH = 40, - DM365_DMA_GPIOINT11 = 41, - DM365_DMA_EMAC_RXPULSE = 41, - DM365_DMA_GPIOINT12 = 42, - DM365_DMA_EMAC_TXPULSE = 42, - DM365_DMA_GPIOINT13 = 43, - DM365_DMA_EMAC_MISCPULSE = 43, - DM365_DMA_GPIOINT14 = 44, - DM365_DMA_SPI4XEVT = 44, - DM365_DMA_GPIOINT15 = 45, - DM365_DMA_SPI4REVT = 45, - DM365_DMA_ADC_ADINT, - DM365_DMA_GPIOINT8, - DM365_DMA_TIMER0_TINT0, - DM365_DMA_TIMER0_TINT1, - DM365_DMA_TIMER1_TINT2, - DM365_DMA_TIMER1_TINT3, - DM365_DMA_PWM0, - DM365_DMA_PWM1 = 53, - DM365_DMA_IMCOP_IMX1INT = 53, - DM365_DMA_PWM2 = 54, - DM365_DMA_IMCOP_NSFINT = 54, - DM365_DMA_PWM3 = 55, - DM365_DMA_KALEIDO6_CP_UNDEF = 55, - DM365_DMA_IMCOP_VLCDINT = 56, - DM365_DMA_KALEIDO5_CP_ECDCMP = 56, - DM365_DMA_IMCOP_BIMINT = 57, - DM365_DMA_KALEIDO8_CP_ME = 57, - DM365_DMA_IMCOP_DCTINT = 58, - DM365_DMA_KALEIDO1_CP_CALC = 58, - DM365_DMA_IMCOP_QIQINT = 59, - DM365_DMA_KALEIDO7_CP_IPE = 59, - DM365_DMA_IMCOP_BPSINT = 60, - DM365_DMA_KALEIDO2_CP_BS = 60, - DM365_DMA_IMCOP_VLCDERRINT = 61, - DM365_DMA_KALEIDO0_CP_LPF = 61, - DM365_DMA_IMCOP_RCNTINT = 62, - DM365_DMA_KALEIDO3_CP_MC = 62, - DM365_DMA_IMCOP_COPCINT = 63, - DM365_DMA_KALEIDO4_CP_ECDEND = 63, + DM365_DMA_TIMER3_TINT6, + DM365_DMA_TIMER3_TINT7, + DM365_DMA_MCBSP_TX = 2, + DM365_DMA_VCIF_TX = 2, + DM365_DMA_MCBSP_RX = 3, + DM365_DMA_VCIF_RX = 3, + DM365_DMA_VPSS_EVT1, + DM365_DMA_VPSS_EVT2, + DM365_DMA_VPSS_EVT3, + DM365_DMA_VPSS_EVT4, + DM365_DMA_TIMER2_TINT4, + DM365_DMA_TIMER2_TINT5, + DM365_DMA_SPI2XEVT, + DM365_DMA_SPI2REVT, + DM365_DMA_IMCOP_IMX0INT = 12, + DM365_DMA_KALEIDO_ARMINT = 12, + DM365_DMA_IMCOP_SEQINT, + DM365_DMA_SPI1XEVT, + DM365_DMA_SPI1REVT, + DM365_DMA_SPI0XEVT, + DM365_DMA_SPI0REVT, + DM365_DMA_URXEVT0 = 18, + DM365_DMA_SPI3XEVT = 18, + DM365_DMA_UTXEVT0 = 19, + DM365_DMA_SPI3REVT = 19, + DM365_DMA_URXEVT1, + DM365_DMA_UTXEVT1, + DM365_DMA_TIMER4_TINT8, + DM365_DMA_TIMER4_TINT9, + DM365_DMA_RTOINT, + DM365_DMA_GPIONT9, + DM365_DMA_MMC0RXEVT = 26, + DM365_DMA_MEMSTK_MSEVT = 26, + DM365_DMA_MMC0TXEVT, + DM365_DMA_I2C_ICREVT, + DM365_DMA_I2C_ICXEVT, + DM365_DMA_MMC1RXEVT, + DM365_DMA_MMC1TXEVT, + DM365_DMA_GPIOINT0, + DM365_DMA_GPIOINT1, + DM365_DMA_GPIOINT2, + DM365_DMA_GPIOINT3, + DM365_DMA_GPIOINT4, + DM365_DMA_GPIOINT5, + DM365_DMA_GPIOINT6, + DM365_DMA_GPIOINT7, + DM365_DMA_GPIOINT10 = 40, + DM365_DMA_EMAC_RXTHREESH = 40, + DM365_DMA_GPIOINT11 = 41, + DM365_DMA_EMAC_RXPULSE = 41, + DM365_DMA_GPIOINT12 = 42, + DM365_DMA_EMAC_TXPULSE = 42, + DM365_DMA_GPIOINT13 = 43, + DM365_DMA_EMAC_MISCPULSE = 43, + DM365_DMA_GPIOINT14 = 44, + DM365_DMA_SPI4XEVT = 44, + DM365_DMA_GPIOINT15 = 45, + DM365_DMA_SPI4REVT = 45, + DM365_DMA_ADC_ADINT, + DM365_DMA_GPIOINT8, + DM365_DMA_TIMER0_TINT0, + DM365_DMA_TIMER0_TINT1, + DM365_DMA_TIMER1_TINT2, + DM365_DMA_TIMER1_TINT3, + DM365_DMA_PWM0, + DM365_DMA_PWM1 = 53, + DM365_DMA_IMCOP_IMX1INT = 53, + DM365_DMA_PWM2 = 54, + DM365_DMA_IMCOP_NSFINT = 54, + DM365_DMA_PWM3 = 55, + DM365_DMA_KALEIDO6_CP_UNDEF = 55, + DM365_DMA_IMCOP_VLCDINT = 56, + DM365_DMA_KALEIDO5_CP_ECDCMP = 56, + DM365_DMA_IMCOP_BIMINT = 57, + DM365_DMA_KALEIDO8_CP_ME = 57, + DM365_DMA_IMCOP_DCTINT = 58, + DM365_DMA_KALEIDO1_CP_CALC = 58, + DM365_DMA_IMCOP_QIQINT = 59, + DM365_DMA_KALEIDO7_CP_IPE = 59, + DM365_DMA_IMCOP_BPSINT = 60, + DM365_DMA_KALEIDO2_CP_BS = 60, + DM365_DMA_IMCOP_VLCDERRINT = 61, + DM365_DMA_KALEIDO0_CP_LPF = 61, + DM365_DMA_IMCOP_RCNTINT = 62, + DM365_DMA_KALEIDO3_CP_MC = 62, + DM365_DMA_IMCOP_COPCINT = 63, + DM365_DMA_KALEIDO4_CP_ECDEND = 63, }; /* end DM365 specific info */ @@ -197,48 +183,48 @@ enum dm365_edma_ch { #define DMA_TC2_ERROR 4 enum address_mode { - INCR = 0, - FIFO = 1 + INCR = 0, + FIFO = 1 }; enum fifo_width { - W8BIT = 0, - W16BIT = 1, - W32BIT = 2, - W64BIT = 3, - W128BIT = 4, - W256BIT = 5 + W8BIT = 0, + W16BIT = 1, + W32BIT = 2, + W64BIT = 3, + W128BIT = 4, + W256BIT = 5 }; enum dma_event_q { - EVENTQ_0 = 0, - EVENTQ_1 = 1, - EVENTQ_2 = 2, - EVENTQ_3 = 3, - EVENTQ_DEFAULT = -1 + EVENTQ_0 = 0, + EVENTQ_1 = 1, + EVENTQ_2 = 2, + EVENTQ_3 = 3, + EVENTQ_DEFAULT = -1 }; enum sync_dimension { - ASYNC = 0, - ABSYNC = 1 + ASYNC = 0, + ABSYNC = 1 }; -#define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan)) -#define EDMA_CTLR(i) ((i) >> 16) -#define EDMA_CHAN_SLOT(i) ((i) & 0xffff) +#define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan)) +#define EDMA_CTLR(i) ((i) >> 16) +#define EDMA_CHAN_SLOT(i) ((i) & 0xffff) -#define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */ -#define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */ -#define EDMA_CONT_PARAMS_ANY 1001 -#define EDMA_CONT_PARAMS_FIXED_EXACT 1002 +#define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */ +#define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */ +#define EDMA_CONT_PARAMS_ANY 1001 +#define EDMA_CONT_PARAMS_FIXED_EXACT 1002 #define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003 #define EDMA_MAX_CC 2 /* alloc/free DMA channels and their dedicated parameter RAM slots */ int edma_alloc_channel(int channel, - void (*callback)(unsigned channel, rt_uint16_t ch_status, void *data), - void *data, enum dma_event_q); + void (*callback)(unsigned channel, rt_uint16_t ch_status, void *data), + void *data, enum dma_event_q); void edma_free_channel(unsigned channel); /* alloc/free parameter RAM slots */ @@ -251,14 +237,14 @@ int edma_free_cont_slots(unsigned slot, int count); /* calls that operate on part of a parameter RAM slot */ void edma_set_src(unsigned slot, rt_uint32_t src_port, - enum address_mode mode, enum fifo_width); + enum address_mode mode, enum fifo_width); void edma_set_dest(unsigned slot, rt_uint32_t dest_port, - enum address_mode mode, enum fifo_width); + enum address_mode mode, enum fifo_width); void edma_get_position(unsigned slot, rt_uint32_t *src, rt_uint32_t *dst); void edma_set_src_index(unsigned slot, rt_int16_t src_bidx, rt_int16_t src_cidx); void edma_set_dest_index(unsigned slot, rt_int16_t dest_bidx, rt_int16_t dest_cidx); void edma_set_transfer_params(unsigned slot, rt_uint16_t acnt, rt_uint16_t bcnt, rt_uint16_t ccnt, - rt_uint16_t bcnt_rld, enum sync_dimension sync_mode); + rt_uint16_t bcnt_rld, enum sync_dimension sync_mode); void edma_link(unsigned from, unsigned to); void edma_unlink(unsigned from); @@ -277,26 +263,26 @@ void edma_resume(unsigned channel); struct edma_rsv_info { - const rt_int16_t (*rsv_chans)[2]; - const rt_int16_t (*rsv_slots)[2]; + const rt_int16_t (*rsv_chans)[2]; + const rt_int16_t (*rsv_slots)[2]; }; /* platform_data for EDMA driver */ struct edma_soc_info { - /* how many dma resources of each type */ - unsigned n_channel; - unsigned n_region; - unsigned n_slot; - unsigned n_tc; - unsigned n_cc; - enum dma_event_q default_queue; + /* how many dma resources of each type */ + unsigned n_channel; + unsigned n_region; + unsigned n_slot; + unsigned n_tc; + unsigned n_cc; + enum dma_event_q default_queue; - /* Resource reservation for other cores */ - struct edma_rsv_info *rsv; + /* Resource reservation for other cores */ + struct edma_rsv_info *rsv; - const rt_int8_t (*queue_tc_mapping)[2]; - const rt_int8_t (*queue_priority_mapping)[2]; + const rt_int8_t (*queue_tc_mapping)[2]; + const rt_int8_t (*queue_priority_mapping)[2]; }; int edma_init(struct edma_soc_info **info); diff --git a/bsp/dm365/platform/findbit.S b/bsp/dm365/platform/findbit.S index 0c18563c96..229d9502cd 100644 --- a/bsp/dm365/platform/findbit.S +++ b/bsp/dm365/platform/findbit.S @@ -1,25 +1,11 @@ /* - * File : findbit.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2010-11-13 weety first version + * Date Author Notes + * 2010-11-13 weety first version */ //#include //.text @@ -30,20 +16,20 @@ */ .globl _find_first_zero_bit_le _find_first_zero_bit_le: - teq r1, #0 - beq 3f - mov r2, #0 + teq r1, #0 + beq 3f + mov r2, #0 1: - ldrb r3, [r0, r2, lsr #3] - lsr r3, r2, #3 - ldrb r3, [r0, r3] - eors r3, r3, #0xff @ invert bits - bne .L_found @ any now set - found zero bit - add r2, r2, #8 @ next bit pointer -2: cmp r2, r1 @ any more? - blo 1b -3: mov r0, r1 @ no free bits - mov pc, lr + ldrb r3, [r0, r2, lsr #3] + lsr r3, r2, #3 + ldrb r3, [r0, r3] + eors r3, r3, #0xff @ invert bits + bne .L_found @ any now set - found zero bit + add r2, r2, #8 @ next bit pointer +2: cmp r2, r1 @ any more? + blo 1b +3: mov r0, r1 @ no free bits + mov pc, lr //ENDPROC(_find_first_zero_bit_le) /* @@ -52,19 +38,19 @@ _find_first_zero_bit_le: */ .globl _find_next_zero_bit_le _find_next_zero_bit_le: - teq r1, #0 - beq 3b - ands ip, r2, #7 - beq 1b @ If new byte, goto old routine - ldrb r3, [r0, r2, lsr #3] - lsr r3, r2, #3 - ldrb r3, [r0, r3] - eor r3, r3, #0xff @ now looking for a 1 bit - movs r3, r3, lsr ip @ shift off unused bits - bne .L_found - orr r2, r2, #7 @ if zero, then no bits here - add r2, r2, #1 @ align bit pointer - b 2b @ loop for next bit + teq r1, #0 + beq 3b + ands ip, r2, #7 + beq 1b @ If new byte, goto old routine + ldrb r3, [r0, r2, lsr #3] + lsr r3, r2, #3 + ldrb r3, [r0, r3] + eor r3, r3, #0xff @ now looking for a 1 bit + movs r3, r3, lsr ip @ shift off unused bits + bne .L_found + orr r2, r2, #7 @ if zero, then no bits here + add r2, r2, #1 @ align bit pointer + b 2b @ loop for next bit //ENDPROC(_find_next_zero_bit_le) /* @@ -73,20 +59,20 @@ _find_next_zero_bit_le: */ .globl _find_first_bit_le _find_first_bit_le: - teq r1, #0 - beq 3f - mov r2, #0 + teq r1, #0 + beq 3f + mov r2, #0 1: - ldrb r3, [r0, r2, lsr #3] - lsr r3, r2, #3 - ldrb r3, [r0, r3] - movs r3, r3 - bne .L_found @ any now set - found zero bit - add r2, r2, #8 @ next bit pointer -2: cmp r2, r1 @ any more? - blo 1b -3: mov r0, r1 @ no free bits - mov pc, lr + ldrb r3, [r0, r2, lsr #3] + lsr r3, r2, #3 + ldrb r3, [r0, r3] + movs r3, r3 + bne .L_found @ any now set - found zero bit + add r2, r2, #8 @ next bit pointer +2: cmp r2, r1 @ any more? + blo 1b +3: mov r0, r1 @ no free bits + mov pc, lr //ENDPROC(_find_first_bit_le) /* @@ -95,87 +81,87 @@ _find_first_bit_le: */ .globl _find_next_bit_le _find_next_bit_le: - teq r1, #0 - beq 3b - ands ip, r2, #7 - beq 1b @ If new byte, goto old routine - ldrb r3, [r0, r2, lsr #3] - lsr r3, r2, #3 - ldrb r3, [r0, r3] - movs r3, r3, lsr ip @ shift off unused bits - bne .L_found - orr r2, r2, #7 @ if zero, then no bits here - add r2, r2, #1 @ align bit pointer - b 2b @ loop for next bit + teq r1, #0 + beq 3b + ands ip, r2, #7 + beq 1b @ If new byte, goto old routine + ldrb r3, [r0, r2, lsr #3] + lsr r3, r2, #3 + ldrb r3, [r0, r3] + movs r3, r3, lsr ip @ shift off unused bits + bne .L_found + orr r2, r2, #7 @ if zero, then no bits here + add r2, r2, #1 @ align bit pointer + b 2b @ loop for next bit //ENDPROC(_find_next_bit_le) #ifdef __ARMEB__ ENTRY(_find_first_zero_bit_be) - teq r1, #0 - beq 3f - mov r2, #0 -1: eor r3, r2, #0x18 @ big endian byte ordering - ARM( ldrb r3, [r0, r3, lsr #3] ) - THUMB( lsr r3, #3 ) - THUMB( ldrb r3, [r0, r3] ) - eors r3, r3, #0xff @ invert bits - bne .L_found @ any now set - found zero bit - add r2, r2, #8 @ next bit pointer -2: cmp r2, r1 @ any more? - blo 1b -3: mov r0, r1 @ no free bits - mov pc, lr + teq r1, #0 + beq 3f + mov r2, #0 +1: eor r3, r2, #0x18 @ big endian byte ordering + ARM( ldrb r3, [r0, r3, lsr #3] ) + THUMB( lsr r3, #3 ) + THUMB( ldrb r3, [r0, r3] ) + eors r3, r3, #0xff @ invert bits + bne .L_found @ any now set - found zero bit + add r2, r2, #8 @ next bit pointer +2: cmp r2, r1 @ any more? + blo 1b +3: mov r0, r1 @ no free bits + mov pc, lr ENDPROC(_find_first_zero_bit_be) ENTRY(_find_next_zero_bit_be) - teq r1, #0 - beq 3b - ands ip, r2, #7 - beq 1b @ If new byte, goto old routine - eor r3, r2, #0x18 @ big endian byte ordering - ARM( ldrb r3, [r0, r3, lsr #3] ) - THUMB( lsr r3, #3 ) - THUMB( ldrb r3, [r0, r3] ) - eor r3, r3, #0xff @ now looking for a 1 bit - movs r3, r3, lsr ip @ shift off unused bits - bne .L_found - orr r2, r2, #7 @ if zero, then no bits here - add r2, r2, #1 @ align bit pointer - b 2b @ loop for next bit + teq r1, #0 + beq 3b + ands ip, r2, #7 + beq 1b @ If new byte, goto old routine + eor r3, r2, #0x18 @ big endian byte ordering + ARM( ldrb r3, [r0, r3, lsr #3] ) + THUMB( lsr r3, #3 ) + THUMB( ldrb r3, [r0, r3] ) + eor r3, r3, #0xff @ now looking for a 1 bit + movs r3, r3, lsr ip @ shift off unused bits + bne .L_found + orr r2, r2, #7 @ if zero, then no bits here + add r2, r2, #1 @ align bit pointer + b 2b @ loop for next bit ENDPROC(_find_next_zero_bit_be) ENTRY(_find_first_bit_be) - teq r1, #0 - beq 3f - mov r2, #0 -1: eor r3, r2, #0x18 @ big endian byte ordering - ARM( ldrb r3, [r0, r3, lsr #3] ) - THUMB( lsr r3, #3 ) - THUMB( ldrb r3, [r0, r3] ) - movs r3, r3 - bne .L_found @ any now set - found zero bit - add r2, r2, #8 @ next bit pointer -2: cmp r2, r1 @ any more? - blo 1b -3: mov r0, r1 @ no free bits - mov pc, lr + teq r1, #0 + beq 3f + mov r2, #0 +1: eor r3, r2, #0x18 @ big endian byte ordering + ARM( ldrb r3, [r0, r3, lsr #3] ) + THUMB( lsr r3, #3 ) + THUMB( ldrb r3, [r0, r3] ) + movs r3, r3 + bne .L_found @ any now set - found zero bit + add r2, r2, #8 @ next bit pointer +2: cmp r2, r1 @ any more? + blo 1b +3: mov r0, r1 @ no free bits + mov pc, lr ENDPROC(_find_first_bit_be) ENTRY(_find_next_bit_be) - teq r1, #0 - beq 3b - ands ip, r2, #7 - beq 1b @ If new byte, goto old routine - eor r3, r2, #0x18 @ big endian byte ordering - ARM( ldrb r3, [r0, r3, lsr #3] ) - THUMB( lsr r3, #3 ) - THUMB( ldrb r3, [r0, r3] ) - movs r3, r3, lsr ip @ shift off unused bits - bne .L_found - orr r2, r2, #7 @ if zero, then no bits here - add r2, r2, #1 @ align bit pointer - b 2b @ loop for next bit + teq r1, #0 + beq 3b + ands ip, r2, #7 + beq 1b @ If new byte, goto old routine + eor r3, r2, #0x18 @ big endian byte ordering + ARM( ldrb r3, [r0, r3, lsr #3] ) + THUMB( lsr r3, #3 ) + THUMB( ldrb r3, [r0, r3] ) + movs r3, r3, lsr ip @ shift off unused bits + bne .L_found + orr r2, r2, #7 @ if zero, then no bits here + add r2, r2, #1 @ align bit pointer + b 2b @ loop for next bit ENDPROC(_find_next_bit_be) #endif @@ -185,23 +171,23 @@ ENDPROC(_find_next_bit_be) */ .L_found: #if 1 //__LINUX_ARM_ARCH__ >= 5 - rsb r0, r3, #0 - and r3, r3, r0 - clz r3, r3 - rsb r3, r3, #31 - add r0, r2, r3 + rsb r0, r3, #0 + and r3, r3, r0 + clz r3, r3 + rsb r3, r3, #31 + add r0, r2, r3 #else - tst r3, #0x0f - addeq r2, r2, #4 - movne r3, r3, lsl #4 - tst r3, #0x30 - addeq r2, r2, #2 - movne r3, r3, lsl #2 - tst r3, #0x40 - addeq r2, r2, #1 - mov r0, r2 + tst r3, #0x0f + addeq r2, r2, #4 + movne r3, r3, lsl #4 + tst r3, #0x30 + addeq r2, r2, #2 + movne r3, r3, lsl #2 + tst r3, #0x40 + addeq r2, r2, #1 + mov r0, r2 #endif - cmp r1, r0 @ Clamp to maxbit - movlo r0, r1 - mov pc, lr + cmp r1, r0 @ Clamp to maxbit + movlo r0, r1 + mov pc, lr diff --git a/bsp/dm365/platform/interrupt.c b/bsp/dm365/platform/interrupt.c index eee5709da0..6334072bcd 100644 --- a/bsp/dm365/platform/interrupt.c +++ b/bsp/dm365/platform/interrupt.c @@ -1,25 +1,11 @@ /* - * File : interrupt.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2010-11-13 weety first version + * Date Author Notes + * 2010-11-13 weety first version */ @@ -27,7 +13,7 @@ #include #include "dm36x.h" -#define MAX_HANDLERS 64 +#define MAX_HANDLERS 64 extern rt_uint32_t rt_interrupt_nest; @@ -37,95 +23,95 @@ struct rt_irq_desc irq_desc[MAX_HANDLERS]; rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; rt_uint32_t rt_thread_switch_interrupt_flag; -#define IRQ_BIT(irq) ((irq) & 0x1f) +#define IRQ_BIT(irq) ((irq) & 0x1f) -#define FIQ_REG0_OFFSET 0x0000 -#define FIQ_REG1_OFFSET 0x0004 -#define IRQ_REG0_OFFSET 0x0008 -#define IRQ_REG1_OFFSET 0x000C -#define IRQ_ENT_REG0_OFFSET 0x0018 -#define IRQ_ENT_REG1_OFFSET 0x001C -#define IRQ_INCTL_REG_OFFSET 0x0020 -#define IRQ_EABASE_REG_OFFSET 0x0024 -#define IRQ_INTPRI0_REG_OFFSET 0x0030 -#define IRQ_INTPRI7_REG_OFFSET 0x004C +#define FIQ_REG0_OFFSET 0x0000 +#define FIQ_REG1_OFFSET 0x0004 +#define IRQ_REG0_OFFSET 0x0008 +#define IRQ_REG1_OFFSET 0x000C +#define IRQ_ENT_REG0_OFFSET 0x0018 +#define IRQ_ENT_REG1_OFFSET 0x001C +#define IRQ_INCTL_REG_OFFSET 0x0020 +#define IRQ_EABASE_REG_OFFSET 0x0024 +#define IRQ_INTPRI0_REG_OFFSET 0x0030 +#define IRQ_INTPRI7_REG_OFFSET 0x004C /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ static const rt_uint8_t dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = { - [IRQ_DM3XX_VPSSINT0] = 2, - [IRQ_DM3XX_VPSSINT1] = 6, - [IRQ_DM3XX_VPSSINT2] = 6, - [IRQ_DM3XX_VPSSINT3] = 6, - [IRQ_DM3XX_VPSSINT4] = 6, - [IRQ_DM3XX_VPSSINT5] = 6, - [IRQ_DM3XX_VPSSINT6] = 6, - [IRQ_DM3XX_VPSSINT7] = 7, - [IRQ_DM3XX_VPSSINT8] = 6, - [IRQ_ASQINT] = 6, - [IRQ_DM365_IMXINT0] = 6, - [IRQ_DM3XX_IMCOPINT] = 6, - [IRQ_USBINT] = 4, - [IRQ_DM3XX_RTOINT] = 4, - [IRQ_DM3XX_TINT5] = 7, - [IRQ_DM3XX_TINT6] = 7, - [IRQ_CCINT0] = 5, /* dma */ - [IRQ_DM3XX_SPINT1_0] = 5, /* dma */ - [IRQ_DM3XX_SPINT1_1] = 5, /* dma */ - [IRQ_DM3XX_SPINT2_0] = 5, /* dma */ - [IRQ_DM365_PSCINT] = 7, - [IRQ_DM3XX_SPINT2_1] = 7, - [IRQ_DM3XX_TINT7] = 4, - [IRQ_DM3XX_SDIOINT0] = 7, - [IRQ_DM365_MBXINT] = 7, - [IRQ_DM365_MBRINT] = 7, - [IRQ_DM3XX_MMCINT0] = 7, - [IRQ_DM3XX_MMCINT1] = 7, - [IRQ_DM3XX_PWMINT3] = 7, - [IRQ_DM365_DDRINT] = 7, - [IRQ_DM365_AEMIFINT] = 7, - [IRQ_DM3XX_SDIOINT1] = 4, - [IRQ_DM365_TINT0] = 2, /* clockevent */ - [IRQ_DM365_TINT1] = 2, /* clocksource */ - [IRQ_DM365_TINT2] = 7, /* DSP timer */ - [IRQ_DM365_TINT3] = 7, /* system tick */ - [IRQ_PWMINT0] = 7, - [IRQ_PWMINT1] = 7, - [IRQ_DM365_PWMINT2] = 7, - [IRQ_DM365_IICINT] = 3, - [IRQ_UARTINT0] = 3, - [IRQ_UARTINT1] = 3, - [IRQ_DM3XX_SPINT0_0] = 3, - [IRQ_DM3XX_SPINT0_1] = 3, - [IRQ_DM3XX_GPIO0] = 3, - [IRQ_DM3XX_GPIO1] = 7, - [IRQ_DM3XX_GPIO2] = 4, - [IRQ_DM3XX_GPIO3] = 4, - [IRQ_DM3XX_GPIO4] = 7, - [IRQ_DM3XX_GPIO5] = 7, - [IRQ_DM3XX_GPIO6] = 7, - [IRQ_DM3XX_GPIO7] = 7, - [IRQ_DM3XX_GPIO8] = 7, - [IRQ_DM3XX_GPIO9] = 7, - [IRQ_DM365_GPIO10] = 7, - [IRQ_DM365_GPIO11] = 7, - [IRQ_DM365_GPIO12] = 7, - [IRQ_DM365_GPIO13] = 7, - [IRQ_DM365_GPIO14] = 7, - [IRQ_DM365_GPIO15] = 7, - [IRQ_DM365_KEYINT] = 7, - [IRQ_DM365_COMMTX] = 7, - [IRQ_DM365_COMMRX] = 7, - [IRQ_EMUINT] = 7, + [IRQ_DM3XX_VPSSINT0] = 2, + [IRQ_DM3XX_VPSSINT1] = 6, + [IRQ_DM3XX_VPSSINT2] = 6, + [IRQ_DM3XX_VPSSINT3] = 6, + [IRQ_DM3XX_VPSSINT4] = 6, + [IRQ_DM3XX_VPSSINT5] = 6, + [IRQ_DM3XX_VPSSINT6] = 6, + [IRQ_DM3XX_VPSSINT7] = 7, + [IRQ_DM3XX_VPSSINT8] = 6, + [IRQ_ASQINT] = 6, + [IRQ_DM365_IMXINT0] = 6, + [IRQ_DM3XX_IMCOPINT] = 6, + [IRQ_USBINT] = 4, + [IRQ_DM3XX_RTOINT] = 4, + [IRQ_DM3XX_TINT5] = 7, + [IRQ_DM3XX_TINT6] = 7, + [IRQ_CCINT0] = 5, /* dma */ + [IRQ_DM3XX_SPINT1_0] = 5, /* dma */ + [IRQ_DM3XX_SPINT1_1] = 5, /* dma */ + [IRQ_DM3XX_SPINT2_0] = 5, /* dma */ + [IRQ_DM365_PSCINT] = 7, + [IRQ_DM3XX_SPINT2_1] = 7, + [IRQ_DM3XX_TINT7] = 4, + [IRQ_DM3XX_SDIOINT0] = 7, + [IRQ_DM365_MBXINT] = 7, + [IRQ_DM365_MBRINT] = 7, + [IRQ_DM3XX_MMCINT0] = 7, + [IRQ_DM3XX_MMCINT1] = 7, + [IRQ_DM3XX_PWMINT3] = 7, + [IRQ_DM365_DDRINT] = 7, + [IRQ_DM365_AEMIFINT] = 7, + [IRQ_DM3XX_SDIOINT1] = 4, + [IRQ_DM365_TINT0] = 2, /* clockevent */ + [IRQ_DM365_TINT1] = 2, /* clocksource */ + [IRQ_DM365_TINT2] = 7, /* DSP timer */ + [IRQ_DM365_TINT3] = 7, /* system tick */ + [IRQ_PWMINT0] = 7, + [IRQ_PWMINT1] = 7, + [IRQ_DM365_PWMINT2] = 7, + [IRQ_DM365_IICINT] = 3, + [IRQ_UARTINT0] = 3, + [IRQ_UARTINT1] = 3, + [IRQ_DM3XX_SPINT0_0] = 3, + [IRQ_DM3XX_SPINT0_1] = 3, + [IRQ_DM3XX_GPIO0] = 3, + [IRQ_DM3XX_GPIO1] = 7, + [IRQ_DM3XX_GPIO2] = 4, + [IRQ_DM3XX_GPIO3] = 4, + [IRQ_DM3XX_GPIO4] = 7, + [IRQ_DM3XX_GPIO5] = 7, + [IRQ_DM3XX_GPIO6] = 7, + [IRQ_DM3XX_GPIO7] = 7, + [IRQ_DM3XX_GPIO8] = 7, + [IRQ_DM3XX_GPIO9] = 7, + [IRQ_DM365_GPIO10] = 7, + [IRQ_DM365_GPIO11] = 7, + [IRQ_DM365_GPIO12] = 7, + [IRQ_DM365_GPIO13] = 7, + [IRQ_DM365_GPIO14] = 7, + [IRQ_DM365_GPIO15] = 7, + [IRQ_DM365_KEYINT] = 7, + [IRQ_DM365_COMMTX] = 7, + [IRQ_DM365_COMMRX] = 7, + [IRQ_EMUINT] = 7, }; static inline unsigned int davinci_irq_readl(int offset) { - return davinci_readl(DAVINCI_ARM_INTC_BASE + offset); + return davinci_readl(DAVINCI_ARM_INTC_BASE + offset); } static inline void davinci_irq_writel(unsigned long value, int offset) { - davinci_writel(value, DAVINCI_ARM_INTC_BASE + offset); + davinci_writel(value, DAVINCI_ARM_INTC_BASE + offset); } /** @@ -135,8 +121,8 @@ static inline void davinci_irq_writel(unsigned long value, int offset) rt_isr_handler_t rt_hw_interrupt_handle(int vector, void *param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); - return RT_NULL; + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + return RT_NULL; } /** @@ -144,59 +130,59 @@ rt_isr_handler_t rt_hw_interrupt_handle(int vector, void *param) */ void rt_hw_interrupt_init(void) { - int i; - register rt_uint32_t idx; - const rt_uint8_t *priority; - priority = dm365_default_priorities; + int i; + register rt_uint32_t idx; + const rt_uint8_t *priority; + priority = dm365_default_priorities; - /* Clear all interrupt requests */ - davinci_irq_writel(~0x0, FIQ_REG0_OFFSET); - davinci_irq_writel(~0x0, FIQ_REG1_OFFSET); - davinci_irq_writel(~0x0, IRQ_REG0_OFFSET); - davinci_irq_writel(~0x0, IRQ_REG1_OFFSET); + /* Clear all interrupt requests */ + davinci_irq_writel(~0x0, FIQ_REG0_OFFSET); + davinci_irq_writel(~0x0, FIQ_REG1_OFFSET); + davinci_irq_writel(~0x0, IRQ_REG0_OFFSET); + davinci_irq_writel(~0x0, IRQ_REG1_OFFSET); - /* Disable all interrupts */ - davinci_irq_writel(0x0, IRQ_ENT_REG0_OFFSET); - davinci_irq_writel(0x0, IRQ_ENT_REG1_OFFSET); + /* Disable all interrupts */ + davinci_irq_writel(0x0, IRQ_ENT_REG0_OFFSET); + davinci_irq_writel(0x0, IRQ_ENT_REG1_OFFSET); - /* Interrupts disabled immediately, IRQ entry reflects all */ - davinci_irq_writel(0x0, IRQ_INCTL_REG_OFFSET); + /* Interrupts disabled immediately, IRQ entry reflects all */ + davinci_irq_writel(0x0, IRQ_INCTL_REG_OFFSET); - /* we don't use the hardware vector table, just its entry addresses */ - davinci_irq_writel(0, IRQ_EABASE_REG_OFFSET); + /* we don't use the hardware vector table, just its entry addresses */ + davinci_irq_writel(0, IRQ_EABASE_REG_OFFSET); - /* Clear all interrupt requests */ - davinci_irq_writel(~0x0, FIQ_REG0_OFFSET); - davinci_irq_writel(~0x0, FIQ_REG1_OFFSET); - davinci_irq_writel(~0x0, IRQ_REG0_OFFSET); - davinci_irq_writel(~0x0, IRQ_REG1_OFFSET); + /* Clear all interrupt requests */ + davinci_irq_writel(~0x0, FIQ_REG0_OFFSET); + davinci_irq_writel(~0x0, FIQ_REG1_OFFSET); + davinci_irq_writel(~0x0, IRQ_REG0_OFFSET); + davinci_irq_writel(~0x0, IRQ_REG1_OFFSET); - for (i = IRQ_INTPRI0_REG_OFFSET; i <= IRQ_INTPRI7_REG_OFFSET; i += 4) { - unsigned j; - rt_uint32_t pri; + for (i = IRQ_INTPRI0_REG_OFFSET; i <= IRQ_INTPRI7_REG_OFFSET; i += 4) { + unsigned j; + rt_uint32_t pri; - for (j = 0, pri = 0; j < 32; j += 4, priority++) - pri |= (*priority & 0x07) << j; - davinci_irq_writel(pri, i); - } + for (j = 0, pri = 0; j < 32; j += 4, priority++) + pri |= (*priority & 0x07) << j; + davinci_irq_writel(pri, i); + } - /* init exceptions table */ - for(idx=0; idx < MAX_HANDLERS; idx++) - { - - irq_desc[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle; - irq_desc[idx].param = RT_NULL; - #ifdef RT_USING_INTERRUPT_INFO - rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, "default"); - irq_desc[idx].counter = 0; - #endif - } + /* init exceptions table */ + for(idx=0; idx < MAX_HANDLERS; idx++) + { - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; + irq_desc[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle; + irq_desc[idx].param = RT_NULL; + #ifdef RT_USING_INTERRUPT_INFO + rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, "default"); + irq_desc[idx].counter = 0; + #endif + } + + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; } /** @@ -205,20 +191,20 @@ void rt_hw_interrupt_init(void) */ void rt_hw_interrupt_mask(int irq) { - unsigned int mask; - rt_uint32_t l; + unsigned int mask; + rt_uint32_t l; - mask = 1 << IRQ_BIT(irq); + mask = 1 << IRQ_BIT(irq); - if (irq > 31) { - l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET); - l &= ~mask; - davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET); - } else { - l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET); - l &= ~mask; - davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET); - } + if (irq > 31) { + l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET); + l &= ~mask; + davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET); + } else { + l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET); + l &= ~mask; + davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET); + } } /** @@ -227,20 +213,20 @@ void rt_hw_interrupt_mask(int irq) */ void rt_hw_interrupt_umask(int irq) { - unsigned int mask; - rt_uint32_t l; + unsigned int mask; + rt_uint32_t l; - mask = 1 << IRQ_BIT(irq); + mask = 1 << IRQ_BIT(irq); - if (irq > 31) { - l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET); - l |= mask; - davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET); - } else { - l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET); - l |= mask; - davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET); - } + if (irq > 31) { + l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET); + l |= mask; + davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET); + } else { + l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET); + l |= mask; + davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET); + } } /** @@ -253,25 +239,25 @@ void rt_hw_interrupt_umask(int irq) */ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name) + void *param, const char *name) { - rt_isr_handler_t old_handler = RT_NULL; + rt_isr_handler_t old_handler = RT_NULL; - if(vector < MAX_HANDLERS) - { - old_handler = irq_desc[vector].handler; - if (handler != RT_NULL) - { - irq_desc[vector].handler = (rt_isr_handler_t)handler; - irq_desc[vector].param = param; - #ifdef RT_USING_INTERRUPT_INFO - rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name); - irq_desc[vector].counter = 0; - #endif - } - } + if(vector < MAX_HANDLERS) + { + old_handler = irq_desc[vector].handler; + if (handler != RT_NULL) + { + irq_desc[vector].handler = (rt_isr_handler_t)handler; + irq_desc[vector].param = param; + #ifdef RT_USING_INTERRUPT_INFO + rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name); + irq_desc[vector].counter = 0; + #endif + } + } - return old_handler; + return old_handler; } @@ -279,16 +265,16 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, #ifdef RT_USING_INTERRUPT_INFO void list_irq(void) { - int irq; - - rt_kprintf("number\tcount\tname\n"); - for (irq = 0; irq < MAX_HANDLERS; irq++) - { - if (rt_strncmp(irq_desc[irq].name, "default", sizeof("default"))) - { - rt_kprintf("%02ld: %10ld %s\n", irq, irq_desc[irq].counter, irq_desc[irq].name); - } - } + int irq; + + rt_kprintf("number\tcount\tname\n"); + for (irq = 0; irq < MAX_HANDLERS; irq++) + { + if (rt_strncmp(irq_desc[irq].name, "default", sizeof("default"))) + { + rt_kprintf("%02ld: %10ld %s\n", irq, irq_desc[irq].counter, irq_desc[irq].name); + } + } } #include diff --git a/bsp/dm365/platform/irqs.h b/bsp/dm365/platform/irqs.h index b0e345f923..b8c4ecc9e4 100644 --- a/bsp/dm365/platform/irqs.h +++ b/bsp/dm365/platform/irqs.h @@ -1,25 +1,11 @@ /* - * File : irqs.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2010-11-13 weety first version + * Date Author Notes + * 2010-11-13 weety first version */ #ifndef __DM36X_IRQS_H__ @@ -32,7 +18,7 @@ extern "C" { /* Base address */ #define DAVINCI_ARM_INTC_BASE 0x01C48000 -#define DAVINCI_N_AINTC_IRQ 64 +#define DAVINCI_N_AINTC_IRQ 64 /* Interrupt lines */ #define IRQ_VDINT0 0 @@ -102,100 +88,100 @@ extern "C" { /* * Base Interrupts common across DM355 and DM365 */ -#define IRQ_DM3XX_VPSSINT0 0 -#define IRQ_DM3XX_VPSSINT1 1 -#define IRQ_DM3XX_VPSSINT2 2 -#define IRQ_DM3XX_VPSSINT3 3 -#define IRQ_DM3XX_VPSSINT4 4 -#define IRQ_DM3XX_VPSSINT5 5 -#define IRQ_DM3XX_VPSSINT6 6 -#define IRQ_DM3XX_VPSSINT7 7 -#define IRQ_DM3XX_VPSSINT8 8 -#define IRQ_DM3XX_IMCOPINT 11 -#define IRQ_DM3XX_RTOINT 13 -#define IRQ_DM3XX_TINT4 13 -#define IRQ_DM3XX_TINT2_TINT12 13 -#define IRQ_DM3XX_TINT5 14 -#define IRQ_DM3XX_TINT2_TINT34 14 -#define IRQ_DM3XX_TINT6 15 -#define IRQ_DM3XX_TINT3_TINT12 15 -#define IRQ_DM3XX_SPINT1_0 17 -#define IRQ_DM3XX_SPINT1_1 18 -#define IRQ_DM3XX_SPINT2_0 19 -#define IRQ_DM3XX_SPINT2_1 21 -#define IRQ_DM3XX_TINT7 22 -#define IRQ_DM3XX_TINT3_TINT34 22 -#define IRQ_DM3XX_SDIOINT0 23 -#define IRQ_DM3XX_MMCINT0 26 -#define IRQ_DM3XX_MSINT 26 -#define IRQ_DM3XX_MMCINT1 27 -#define IRQ_DM3XX_PWMINT3 28 -#define IRQ_DM3XX_SDIOINT1 31 -#define IRQ_DM3XX_SPINT0_0 42 -#define IRQ_DM3XX_SPINT0_1 43 -#define IRQ_DM3XX_GPIO0 44 -#define IRQ_DM3XX_GPIO1 45 -#define IRQ_DM3XX_GPIO2 46 -#define IRQ_DM3XX_GPIO3 47 -#define IRQ_DM3XX_GPIO4 48 -#define IRQ_DM3XX_GPIO5 49 -#define IRQ_DM3XX_GPIO6 50 -#define IRQ_DM3XX_GPIO7 51 -#define IRQ_DM3XX_GPIO8 52 -#define IRQ_DM3XX_GPIO9 53 +#define IRQ_DM3XX_VPSSINT0 0 +#define IRQ_DM3XX_VPSSINT1 1 +#define IRQ_DM3XX_VPSSINT2 2 +#define IRQ_DM3XX_VPSSINT3 3 +#define IRQ_DM3XX_VPSSINT4 4 +#define IRQ_DM3XX_VPSSINT5 5 +#define IRQ_DM3XX_VPSSINT6 6 +#define IRQ_DM3XX_VPSSINT7 7 +#define IRQ_DM3XX_VPSSINT8 8 +#define IRQ_DM3XX_IMCOPINT 11 +#define IRQ_DM3XX_RTOINT 13 +#define IRQ_DM3XX_TINT4 13 +#define IRQ_DM3XX_TINT2_TINT12 13 +#define IRQ_DM3XX_TINT5 14 +#define IRQ_DM3XX_TINT2_TINT34 14 +#define IRQ_DM3XX_TINT6 15 +#define IRQ_DM3XX_TINT3_TINT12 15 +#define IRQ_DM3XX_SPINT1_0 17 +#define IRQ_DM3XX_SPINT1_1 18 +#define IRQ_DM3XX_SPINT2_0 19 +#define IRQ_DM3XX_SPINT2_1 21 +#define IRQ_DM3XX_TINT7 22 +#define IRQ_DM3XX_TINT3_TINT34 22 +#define IRQ_DM3XX_SDIOINT0 23 +#define IRQ_DM3XX_MMCINT0 26 +#define IRQ_DM3XX_MSINT 26 +#define IRQ_DM3XX_MMCINT1 27 +#define IRQ_DM3XX_PWMINT3 28 +#define IRQ_DM3XX_SDIOINT1 31 +#define IRQ_DM3XX_SPINT0_0 42 +#define IRQ_DM3XX_SPINT0_1 43 +#define IRQ_DM3XX_GPIO0 44 +#define IRQ_DM3XX_GPIO1 45 +#define IRQ_DM3XX_GPIO2 46 +#define IRQ_DM3XX_GPIO3 47 +#define IRQ_DM3XX_GPIO4 48 +#define IRQ_DM3XX_GPIO5 49 +#define IRQ_DM3XX_GPIO6 50 +#define IRQ_DM3XX_GPIO7 51 +#define IRQ_DM3XX_GPIO8 52 +#define IRQ_DM3XX_GPIO9 53 /* DaVinci DM365-specific Interrupts */ -#define IRQ_DM365_INSFINT 7 -#define IRQ_DM365_IMXINT1 8 -#define IRQ_DM365_IMXINT0 10 -#define IRQ_DM365_KLD_ARMINT 10 -#define IRQ_DM365_CCERRINT 17 -#define IRQ_DM365_TCERRINT0 18 -#define IRQ_DM365_SPINT2_0 19 -#define IRQ_DM365_PSCINT 20 -#define IRQ_DM365_TVINT 20 -#define IRQ_DM365_SPINT4_0 21 -#define IRQ_DM365_MBXINT 24 -#define IRQ_DM365_VCINT 24 -#define IRQ_DM365_MBRINT 25 -#define IRQ_DM365_TINT9 28 -#define IRQ_DM365_TINT4_TINT34 28 -#define IRQ_DM365_DDRINT 29 -#define IRQ_DM365_RTCINT 29 -#define IRQ_DM365_AEMIFINT 30 -#define IRQ_DM365_HPIINT 30 -#define IRQ_DM365_TINT0 32 -#define IRQ_DM365_TINT0_TINT12 32 -#define IRQ_DM365_TINT1 33 -#define IRQ_DM365_TINT0_TINT34 33 -#define IRQ_DM365_TINT2 34 -#define IRQ_DM365_TINT1_TINT12 34 -#define IRQ_DM365_TINT3 35 -#define IRQ_DM365_TINT1_TINT34 35 -#define IRQ_DM365_PWMINT2 38 -#define IRQ_DM365_TINT8 38 -#define IRQ_DM365_TINT4_TINT12 38 -#define IRQ_DM365_IICINT 39 -#define IRQ_DM365_SPINT3_0 43 -#define IRQ_DM365_EMAC_RXTHRESH 52 -#define IRQ_DM365_EMAC_RXPULSE 53 -#define IRQ_DM365_GPIO10 54 -#define IRQ_DM365_EMAC_TXPULSE 54 -#define IRQ_DM365_GPIO11 55 +#define IRQ_DM365_INSFINT 7 +#define IRQ_DM365_IMXINT1 8 +#define IRQ_DM365_IMXINT0 10 +#define IRQ_DM365_KLD_ARMINT 10 +#define IRQ_DM365_CCERRINT 17 +#define IRQ_DM365_TCERRINT0 18 +#define IRQ_DM365_SPINT2_0 19 +#define IRQ_DM365_PSCINT 20 +#define IRQ_DM365_TVINT 20 +#define IRQ_DM365_SPINT4_0 21 +#define IRQ_DM365_MBXINT 24 +#define IRQ_DM365_VCINT 24 +#define IRQ_DM365_MBRINT 25 +#define IRQ_DM365_TINT9 28 +#define IRQ_DM365_TINT4_TINT34 28 +#define IRQ_DM365_DDRINT 29 +#define IRQ_DM365_RTCINT 29 +#define IRQ_DM365_AEMIFINT 30 +#define IRQ_DM365_HPIINT 30 +#define IRQ_DM365_TINT0 32 +#define IRQ_DM365_TINT0_TINT12 32 +#define IRQ_DM365_TINT1 33 +#define IRQ_DM365_TINT0_TINT34 33 +#define IRQ_DM365_TINT2 34 +#define IRQ_DM365_TINT1_TINT12 34 +#define IRQ_DM365_TINT3 35 +#define IRQ_DM365_TINT1_TINT34 35 +#define IRQ_DM365_PWMINT2 38 +#define IRQ_DM365_TINT8 38 +#define IRQ_DM365_TINT4_TINT12 38 +#define IRQ_DM365_IICINT 39 +#define IRQ_DM365_SPINT3_0 43 +#define IRQ_DM365_EMAC_RXTHRESH 52 +#define IRQ_DM365_EMAC_RXPULSE 53 +#define IRQ_DM365_GPIO10 54 +#define IRQ_DM365_EMAC_TXPULSE 54 +#define IRQ_DM365_GPIO11 55 #define IRQ_DM365_EMAC_MISCPULSE 55 -#define IRQ_DM365_GPIO12 56 -#define IRQ_DM365_PWRGIO0 56 -#define IRQ_DM365_GPIO13 57 -#define IRQ_DM365_PWRGIO1 57 -#define IRQ_DM365_GPIO14 58 -#define IRQ_DM365_PWRGIO2 58 -#define IRQ_DM365_GPIO15 59 -#define IRQ_DM365_ADCINT 59 -#define IRQ_DM365_KEYINT 60 -#define IRQ_DM365_COMMTX 61 -#define IRQ_DM365_TCERRINT2 61 -#define IRQ_DM365_COMMRX 62 -#define IRQ_DM365_TCERRINT3 62 +#define IRQ_DM365_GPIO12 56 +#define IRQ_DM365_PWRGIO0 56 +#define IRQ_DM365_GPIO13 57 +#define IRQ_DM365_PWRGIO1 57 +#define IRQ_DM365_GPIO14 58 +#define IRQ_DM365_PWRGIO2 58 +#define IRQ_DM365_GPIO15 59 +#define IRQ_DM365_ADCINT 59 +#define IRQ_DM365_KEYINT 60 +#define IRQ_DM365_COMMTX 61 +#define IRQ_DM365_TCERRINT2 61 +#define IRQ_DM365_COMMRX 62 +#define IRQ_DM365_TCERRINT3 62 #ifdef __cplusplus diff --git a/bsp/dm365/platform/psc.c b/bsp/dm365/platform/psc.c index 0fbed347f6..b2e0a90197 100644 --- a/bsp/dm365/platform/psc.c +++ b/bsp/dm365/platform/psc.c @@ -1,25 +1,11 @@ /* - * File : psc.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2010-11-13 weety first version + * Date Author Notes + * 2010-11-13 weety first version */ #include "dm36x.h" @@ -33,13 +19,13 @@ * ------------------------------------------------------------------------ */ void psc_change_state(int id, int state) { - rt_uint32_t mdstat, mdctl; + rt_uint32_t mdstat, mdctl; - if (id > DAVINCI_DM365_LPSC_KALEIDO) - return; + if (id > DAVINCI_DM365_LPSC_KALEIDO) + return; - mdstat = PSC_MDSTAT_BASE + (id * 4); - mdctl = PSC_MDCTL_BASE + (id * 4); + mdstat = PSC_MDSTAT_BASE + (id * 4); + mdctl = PSC_MDCTL_BASE + (id * 4); /* * Step 0 - Ignore request if the state is already set as is diff --git a/bsp/dm365/platform/psc.h b/bsp/dm365/platform/psc.h index 10068a9553..116b7b2dd7 100644 --- a/bsp/dm365/platform/psc.h +++ b/bsp/dm365/platform/psc.h @@ -1,25 +1,11 @@ /* - * File : psc.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2010-11-13 weety first version + * Date Author Notes + * 2010-11-13 weety first version */ #ifndef __DM36X_PSC_H @@ -31,69 +17,69 @@ extern "C" { /* PSC register offsets */ -#define EPCPR 0x070 -#define PTCMD 0x120 -#define PTSTAT 0x128 -#define PDSTAT 0x200 -#define PDCTL1 0x304 -#define MDSTAT(n) (0x800 + (n) * 4) -#define MDCTL(n) (0xA00 + (n) * 4) +#define EPCPR 0x070 +#define PTCMD 0x120 +#define PTSTAT 0x128 +#define PDSTAT 0x200 +#define PDCTL1 0x304 +#define MDSTAT(n) (0x800 + (n) * 4) +#define MDCTL(n) (0xA00 + (n) * 4) /* Power and Sleep Controller (PSC) Domains */ -#define DAVINCI_GPSC_ARMDOMAIN 0 -#define DAVINCI_GPSC_DSPDOMAIN 1 +#define DAVINCI_GPSC_ARMDOMAIN 0 +#define DAVINCI_GPSC_DSPDOMAIN 1 -#define DAVINCI_DM365_LPSC_TPCC 0 -#define DAVINCI_DM365_LPSC_TPTC0 1 -#define DAVINCI_DM365_LPSC_TPTC1 2 -#define DAVINCI_DM365_LPSC_TPTC2 3 -#define DAVINCI_DM365_LPSC_TPTC3 4 -#define DAVINCI_DM365_LPSC_TIMER3 5 -#define DAVINCI_DM365_LPSC_SPI1 6 -#define DAVINCI_DM365_LPSC_MMC_SD1 7 -#define DAVINCI_DM365_LPSC_McBSP 8 -#define DAVINCI_DM365_LPSC_USB 9 -#define DAVINCI_DM365_LPSC_PWM3 10 -#define DAVINCI_DM365_LPSC_SPI2 11 -#define DAVINCI_DM365_LPSC_RTO 12 -#define DAVINCI_DM365_LPSC_DDR_EMIF 13 -#define DAVINCI_DM365_LPSC_AEMIF 14 -#define DAVINCI_DM365_LPSC_MMC_SD 15 -#define DAVINCI_DM365_LPSC_MMC_SD0 15 -#define DAVINCI_DM365_LPSC_MEMSTICK 16 -#define DAVINCI_DM365_LPSC_TIMER4 17 -#define DAVINCI_DM365_LPSC_I2C 18 -#define DAVINCI_DM365_LPSC_UART0 19 -#define DAVINCI_DM365_LPSC_UART1 20 -#define DAVINCI_DM365_LPSC_UHPI 21 -#define DAVINCI_DM365_LPSC_SPI0 22 -#define DAVINCI_DM365_LPSC_PWM0 23 -#define DAVINCI_DM365_LPSC_PWM1 24 -#define DAVINCI_DM365_LPSC_PWM2 25 -#define DAVINCI_DM365_LPSC_GPIO 26 -#define DAVINCI_DM365_LPSC_TIMER0 27 -#define DAVINCI_DM365_LPSC_TIMER1 28 -#define DAVINCI_DM365_LPSC_TIMER2 29 +#define DAVINCI_DM365_LPSC_TPCC 0 +#define DAVINCI_DM365_LPSC_TPTC0 1 +#define DAVINCI_DM365_LPSC_TPTC1 2 +#define DAVINCI_DM365_LPSC_TPTC2 3 +#define DAVINCI_DM365_LPSC_TPTC3 4 +#define DAVINCI_DM365_LPSC_TIMER3 5 +#define DAVINCI_DM365_LPSC_SPI1 6 +#define DAVINCI_DM365_LPSC_MMC_SD1 7 +#define DAVINCI_DM365_LPSC_McBSP 8 +#define DAVINCI_DM365_LPSC_USB 9 +#define DAVINCI_DM365_LPSC_PWM3 10 +#define DAVINCI_DM365_LPSC_SPI2 11 +#define DAVINCI_DM365_LPSC_RTO 12 +#define DAVINCI_DM365_LPSC_DDR_EMIF 13 +#define DAVINCI_DM365_LPSC_AEMIF 14 +#define DAVINCI_DM365_LPSC_MMC_SD 15 +#define DAVINCI_DM365_LPSC_MMC_SD0 15 +#define DAVINCI_DM365_LPSC_MEMSTICK 16 +#define DAVINCI_DM365_LPSC_TIMER4 17 +#define DAVINCI_DM365_LPSC_I2C 18 +#define DAVINCI_DM365_LPSC_UART0 19 +#define DAVINCI_DM365_LPSC_UART1 20 +#define DAVINCI_DM365_LPSC_UHPI 21 +#define DAVINCI_DM365_LPSC_SPI0 22 +#define DAVINCI_DM365_LPSC_PWM0 23 +#define DAVINCI_DM365_LPSC_PWM1 24 +#define DAVINCI_DM365_LPSC_PWM2 25 +#define DAVINCI_DM365_LPSC_GPIO 26 +#define DAVINCI_DM365_LPSC_TIMER0 27 +#define DAVINCI_DM365_LPSC_TIMER1 28 +#define DAVINCI_DM365_LPSC_TIMER2 29 #define DAVINCI_DM365_LPSC_SYSTEM_SUBSYS 30 -#define DAVINCI_DM365_LPSC_ARM 31 -#define DAVINCI_DM365_LPSC_SCR0 33 -#define DAVINCI_DM365_LPSC_SCR1 34 -#define DAVINCI_DM365_LPSC_EMU 35 -#define DAVINCI_DM365_LPSC_CHIPDFT 36 -#define DAVINCI_DM365_LPSC_PBIST 37 -#define DAVINCI_DM365_LPSC_SPI3 38 -#define DAVINCI_DM365_LPSC_SPI4 39 -#define DAVINCI_DM365_LPSC_CPGMAC 40 -#define DAVINCI_DM365_LPSC_RTC 41 -#define DAVINCI_DM365_LPSC_KEYSCAN 42 -#define DAVINCI_DM365_LPSC_ADCIF 43 -#define DAVINCI_DM365_LPSC_VOICE_CODEC 44 -#define DAVINCI_DM365_LPSC_DAC_CLKRES 45 -#define DAVINCI_DM365_LPSC_DAC_CLK 46 -#define DAVINCI_DM365_LPSC_VPSSMSTR 47 -#define DAVINCI_DM365_LPSC_IMCOP 50 -#define DAVINCI_DM365_LPSC_KALEIDO 51 +#define DAVINCI_DM365_LPSC_ARM 31 +#define DAVINCI_DM365_LPSC_SCR0 33 +#define DAVINCI_DM365_LPSC_SCR1 34 +#define DAVINCI_DM365_LPSC_EMU 35 +#define DAVINCI_DM365_LPSC_CHIPDFT 36 +#define DAVINCI_DM365_LPSC_PBIST 37 +#define DAVINCI_DM365_LPSC_SPI3 38 +#define DAVINCI_DM365_LPSC_SPI4 39 +#define DAVINCI_DM365_LPSC_CPGMAC 40 +#define DAVINCI_DM365_LPSC_RTC 41 +#define DAVINCI_DM365_LPSC_KEYSCAN 42 +#define DAVINCI_DM365_LPSC_ADCIF 43 +#define DAVINCI_DM365_LPSC_VOICE_CODEC 44 +#define DAVINCI_DM365_LPSC_DAC_CLKRES 45 +#define DAVINCI_DM365_LPSC_DAC_CLK 46 +#define DAVINCI_DM365_LPSC_VPSSMSTR 47 +#define DAVINCI_DM365_LPSC_IMCOP 50 +#define DAVINCI_DM365_LPSC_KALEIDO 51 #define PSC_ENABLE 3 #define PSC_DISABLE 2 diff --git a/bsp/dm365/platform/reset.c b/bsp/dm365/platform/reset.c index 9d7d549dbf..dc80fac76e 100644 --- a/bsp/dm365/platform/reset.c +++ b/bsp/dm365/platform/reset.c @@ -1,25 +1,11 @@ /* - * File : reset.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2010-11-13 weety first version + * Date Author Notes + * 2010-11-13 weety first version */ @@ -38,7 +24,7 @@ */ void machine_reset() { - reset_system(); + reset_system(); } /** @@ -58,14 +44,14 @@ FINSH_FUNCTION_EXPORT_ALIAS(rt_hw_cpu_reset, reset, restart the system); #ifdef FINSH_USING_MSH int cmd_reset(int argc, char** argv) { - rt_hw_cpu_reset(); - return 0; + rt_hw_cpu_reset(); + return 0; } int cmd_shutdown(int argc, char** argv) { - rt_hw_cpu_shutdown(); - return 0; + rt_hw_cpu_shutdown(); + return 0; } FINSH_FUNCTION_EXPORT_ALIAS(cmd_reset, __cmd_reset, restart the system.); diff --git a/bsp/dm365/platform/start_gcc.S b/bsp/dm365/platform/start_gcc.S index ff926e5a0d..836fb4b28f 100644 --- a/bsp/dm365/platform/start_gcc.S +++ b/bsp/dm365/platform/start_gcc.S @@ -1,21 +1,7 @@ /* - * File : start.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -46,21 +32,21 @@ .equ I_BIT, 0x80 @ when I bit is set, IRQ is disabled .equ F_BIT, 0x40 @ when F bit is set, FIQ is disabled -.equ USERMODE, 0x10 -.equ FIQMODE, 0x11 -.equ IRQMODE, 0x12 -.equ SVCMODE, 0x13 -.equ ABORTMODE, 0x17 -.equ UNDEFMODE, 0x1b -.equ MODEMASK, 0x1f -.equ NOINT, 0xc0 +.equ USERMODE, 0x10 +.equ FIQMODE, 0x11 +.equ IRQMODE, 0x12 +.equ SVCMODE, 0x13 +.equ ABORTMODE, 0x17 +.equ UNDEFMODE, 0x1b +.equ MODEMASK, 0x1f +.equ NOINT, 0xc0 -.equ RAM_BASE, 0x00000000 /*Start address of RAM */ -.equ ROM_BASE, 0x80000000 /*Start address of Flash */ +.equ RAM_BASE, 0x00000000 /*Start address of RAM */ +.equ ROM_BASE, 0x80000000 /*Start address of Flash */ -.equ EINT_ENABLE0, 0x01c48018 -.equ EINT_ENABLE1, 0x01c4801c +.equ EINT_ENABLE0, 0x01c48018 +.equ EINT_ENABLE1, 0x01c4801c /* ************************************************************************* @@ -124,7 +110,7 @@ _rtthread_end: * rtthread bss start and end which are defined in linker script */ .globl _bss_start -_bss_start: +_bss_start: .word __bss_start .globl _bss_end @@ -147,7 +133,7 @@ UNDEFINED_STACK_START: .globl ABORT_STACK_START ABORT_STACK_START: .word _abort_stack_start + CONFIG_STACKSIZE - + .globl _STACK_START _STACK_START: .word _svc_stack_start + 1024 @@ -162,16 +148,16 @@ reset: msr cpsr,r0 /* mask all IRQs by clearing all bits in the INTMRs */ - mov r1, $0 - ldr r0, =EINT_ENABLE0 - str r1, [r0] - ldr r0, =EINT_ENABLE1 - str r1, [r0] + mov r1, $0 + ldr r0, =EINT_ENABLE0 + str r1, [r0] + ldr r0, =EINT_ENABLE1 + str r1, [r0] #if 0 /* set interrupt vector */ ldr r0, _TEXT_BASE - mov r1, #0x00 - add r2, r0, #0x40 /* size, 32bytes */ + mov r1, #0x00 + add r2, r0, #0x40 /* size, 32bytes */ copy_loop: ldmia r0!, {r3-r10} /* copy from source address [r0] */ @@ -212,13 +198,13 @@ ctor_end: /* start RT-Thread Kernel */ ldr pc, _rtthread_startup -_rtthread_startup: +_rtthread_startup: .word rtthread_startup #if defined (__FLASH_BUILD__) -_load_address: +_load_address: .word ROM_BASE + _TEXT_BASE #else -_load_address: +_load_address: .word RAM_BASE + _TEXT_BASE #endif diff --git a/bsp/dm365/platform/system_clock.c b/bsp/dm365/platform/system_clock.c index b4e81e98a2..7d4c58874f 100644 --- a/bsp/dm365/platform/system_clock.c +++ b/bsp/dm365/platform/system_clock.c @@ -1,25 +1,11 @@ /* - * File : system_clock.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2010-11-13 weety first version + * Date Author Notes + * 2010-11-13 weety first version */ @@ -33,6 +19,6 @@ extern int davinci_clk_init(void); */ void rt_hw_clock_init(void) { - davinci_clk_init(); + davinci_clk_init(); } diff --git a/bsp/dm365/platform/trap.c b/bsp/dm365/platform/trap.c index 169e4da40b..5c5f0272b3 100644 --- a/bsp/dm365/platform/trap.c +++ b/bsp/dm365/platform/trap.c @@ -1,25 +1,11 @@ /* - * File : trap.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2010-11-13 weety first version + * Date Author Notes + * 2010-11-13 weety first version */ @@ -46,13 +32,13 @@ extern long list_thread(void); void rt_hw_show_register (struct rt_hw_register *regs) { - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); - rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("cpsr:0x%08x\n", regs->cpsr); + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); + rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); + rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); + rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); + rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); + rt_kprintf("cpsr:0x%08x\n", regs->cpsr); } /** @@ -65,15 +51,15 @@ void rt_hw_show_register (struct rt_hw_register *regs) */ void rt_hw_trap_udef(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("undefined instruction\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_kprintf("undefined instruction\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -87,10 +73,10 @@ void rt_hw_trap_udef(struct rt_hw_register *regs) */ void rt_hw_trap_swi(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("software interrupt\n"); - rt_hw_cpu_shutdown(); + rt_kprintf("software interrupt\n"); + rt_hw_cpu_shutdown(); } /** @@ -103,15 +89,15 @@ void rt_hw_trap_swi(struct rt_hw_register *regs) */ void rt_hw_trap_pabt(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("prefetch abort\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_kprintf("prefetch abort\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -124,30 +110,30 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs) */ void rt_hw_trap_dabt(struct rt_hw_register *regs) { - rt_uint32_t fault_addr; - rt_uint32_t fault_status; - asm volatile ("mrc p15, 0, %0, c6, c0, 0" - : - :"r"(fault_addr) - :"cc"); - rt_kprintf("unhandler access to 0x%08x\n", fault_addr); + rt_uint32_t fault_addr; + rt_uint32_t fault_status; + asm volatile ("mrc p15, 0, %0, c6, c0, 0" + : + :"r"(fault_addr) + :"cc"); + rt_kprintf("unhandler access to 0x%08x\n", fault_addr); - /* read DFSR */ - asm volatile ("MRC p15, 0, %0, c5, c0, 0" - : - :"r"(fault_status) - :"cc"); - rt_kprintf("fault status 0x%08x\n", fault_status); + /* read DFSR */ + asm volatile ("MRC p15, 0, %0, c5, c0, 0" + : + :"r"(fault_status) + :"cc"); + rt_kprintf("fault status 0x%08x\n", fault_status); - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("data abort\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_kprintf("data abort\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -159,9 +145,9 @@ void rt_hw_trap_dabt(struct rt_hw_register *regs) */ void rt_hw_trap_resv(struct rt_hw_register *regs) { - rt_kprintf("not used\n"); - rt_hw_show_register(regs); - rt_hw_cpu_shutdown(); + rt_kprintf("not used\n"); + rt_hw_show_register(regs); + rt_hw_cpu_shutdown(); } extern struct rt_irq_desc irq_desc[]; @@ -169,32 +155,32 @@ extern struct rt_irq_desc irq_desc[]; void rt_hw_trap_irq() { - rt_isr_handler_t isr_func; - rt_uint32_t val, irq, mask; - void *param; + rt_isr_handler_t isr_func; + rt_uint32_t val, irq, mask; + void *param; - /* get irq number */ - val = readl(DAVINCI_ARM_INTC_BASE+0x14) - readl(DAVINCI_ARM_INTC_BASE+0x24); - irq = (val >> 2) - 1; - /* clear pending register */ - mask = 1 << (irq & 0x1f); - if (irq > 31) - writel(mask, DAVINCI_ARM_INTC_BASE+0x0c); //IRQ1 - else - writel(mask, DAVINCI_ARM_INTC_BASE+0x08); //IRQ0 - - /* get interrupt service routine */ - isr_func = irq_desc[irq].handler; - param = irq_desc[irq].param; + /* get irq number */ + val = readl(DAVINCI_ARM_INTC_BASE+0x14) - readl(DAVINCI_ARM_INTC_BASE+0x24); + irq = (val >> 2) - 1; + /* clear pending register */ + mask = 1 << (irq & 0x1f); + if (irq > 31) + writel(mask, DAVINCI_ARM_INTC_BASE+0x0c); //IRQ1 + else + writel(mask, DAVINCI_ARM_INTC_BASE+0x08); //IRQ0 - /* turn to interrupt service routine */ - isr_func(irq, param); - irq_desc[irq].counter++; + /* get interrupt service routine */ + isr_func = irq_desc[irq].handler; + param = irq_desc[irq].param; + + /* turn to interrupt service routine */ + isr_func(irq, param); + irq_desc[irq].counter++; } void rt_hw_trap_fiq() { - rt_kprintf("fast interrupt request\n"); + rt_kprintf("fast interrupt request\n"); } /*@}*/ diff --git a/bsp/efm32/enc28j60.h b/bsp/efm32/enc28j60.h index 1c97d9e10c..5955c603e7 100644 --- a/bsp/efm32/enc28j60.h +++ b/bsp/efm32/enc28j60.h @@ -1,11 +1,7 @@ /* - * File : enc28j60.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/frdm-k64f/board/drv_emac.c b/bsp/frdm-k64f/board/drv_emac.c index 606c141545..6770b0d281 100644 --- a/bsp/frdm-k64f/board/drv_emac.c +++ b/bsp/frdm-k64f/board/drv_emac.c @@ -1,7 +1,8 @@ /* * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd - * + * * SPDX-License-Identifier: Apache-2.0 + * * Change Logs: * Date Author Notes * 2015-07-15 Bernard The first version @@ -33,7 +34,7 @@ #define DEBUG_PRINTF(...) #endif -#define MAX_ADDR_LEN 6 +#define MAX_ADDR_LEN 6 #define ENET_RX_RING_LEN (16) #define ENET_TX_RING_LEN (8) @@ -45,17 +46,17 @@ #define ENET_RXBUFF_SIZE (ENET_FRAME_MAX_FRAMELEN) #define ENET_TXBUFF_SIZE (ENET_FRAME_MAX_FRAMELEN) #define ENET_ETH_MAX_FLEN (1522) // recommended size for a VLAN frame - + struct emac_device { /* inherit from Ethernet device */ struct eth_device parent; - - ALIGN(64) enet_rx_bd_struct_t RxBuffDescrip[ENET_RX_RING_LEN]; - ALIGN(64) enet_tx_bd_struct_t TxBuffDescrip[ENET_TX_RING_LEN]; - ALIGN(64) uint8_t RxDataBuff[ENET_RX_RING_LEN * ENET_ALIGN(ENET_RXBUFF_SIZE)]; - ALIGN(64) uint8_t TxDataBuff[ENET_TX_RING_LEN * ENET_ALIGN(ENET_TXBUFF_SIZE)]; - + + ALIGN(64) enet_rx_bd_struct_t RxBuffDescrip[ENET_RX_RING_LEN]; + ALIGN(64) enet_tx_bd_struct_t TxBuffDescrip[ENET_TX_RING_LEN]; + ALIGN(64) uint8_t RxDataBuff[ENET_RX_RING_LEN * ENET_ALIGN(ENET_RXBUFF_SIZE)]; + ALIGN(64) uint8_t TxDataBuff[ENET_TX_RING_LEN * ENET_ALIGN(ENET_TXBUFF_SIZE)]; + enet_handle_t enet_handle; rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* MAC address */ struct rt_semaphore tx_wait; @@ -112,7 +113,7 @@ static void setup_enet_clock_init(void) { CLOCK_EnableClock(kCLOCK_PortC); CLOCK_EnableClock(kCLOCK_PortB); - + /* Select the Ethernet timestamp clock source */ CLOCK_SetEnetTime0Clock(0x2); } @@ -120,7 +121,7 @@ static void setup_enet_clock_init(void) static void enet_mac_rx_isr(struct emac_device* emac) { rt_err_t result; - + result = eth_device_ready(&(_emac.parent)); if( result != RT_EOK ) { @@ -136,7 +137,7 @@ static void enet_mac_tx_isr(struct emac_device* emac) static void ethernet_callback(ENET_Type *base, enet_handle_t *handle, enet_event_t event, void *param) { struct emac_device* emac = param; - + switch (event) { case kENET_RxEvent: @@ -154,7 +155,7 @@ static rt_err_t k64_emac_init(rt_device_t dev) { struct emac_device* emac = K64_EMAC_DEVICE(dev); enet_handle_t * enet_handle = &emac->enet_handle; - + bool link = false; uint32_t phyAddr = 0; phy_speed_t phy_speed; @@ -167,7 +168,7 @@ static rt_err_t k64_emac_init(rt_device_t dev) setup_enet_clock_init(); /* enable iomux and clock */ setup_k64_io_enet(); - + /* prepare the buffer configuration. */ buffCfg.rxBdNumber = ENET_RX_RING_LEN; /* Receive buffer descriptor number. */ buffCfg.txBdNumber = ENET_TX_RING_LEN; /* Transmit buffer descriptor number. */ @@ -177,12 +178,12 @@ static rt_err_t k64_emac_init(rt_device_t dev) buffCfg.txBdStartAddrAlign = emac->TxBuffDescrip; /* Aligned transmit buffer descriptor start address. */ buffCfg.rxBufferAlign = emac->RxDataBuff; /* Receive data buffer start address. */ buffCfg.txBufferAlign = emac->TxDataBuff; /* Transmit data buffer start address. */ - + sysClock = CLOCK_GetFreq(kCLOCK_CoreSysClk); DEBUG_PRINTF("sysClock: %d\n", sysClock); - + ENET_GetDefaultConfig(&config); - + PHY_Init(ENET, 0, CLOCK_GetFreq(kCLOCK_CoreSysClk)); if (PHY_GetLinkStatus(ENET, phyAddr, &link) == kStatus_Success) { @@ -191,7 +192,7 @@ static rt_err_t k64_emac_init(rt_device_t dev) DEBUG_PRINTF("phy link up\n"); /* Get link information from PHY */ PHY_GetLinkSpeedDuplex(ENET, phyAddr, &phy_speed, &phy_duplex); - + /* Change the MII speed and duplex for actual link status. */ config.miiSpeed = (enet_mii_speed_t)phy_speed; config.miiDuplex = (enet_mii_duplex_t)phy_duplex; @@ -205,7 +206,7 @@ static rt_err_t k64_emac_init(rt_device_t dev) config.macSpecialConfig = kENET_ControlFlowControlEnable; config.txAccelerConfig = 0; config.rxAccelerConfig = kENET_RxAccelMacCheckEnabled; - + ENET_Init(ENET, enet_handle, &config, &buffCfg, emac->dev_addr, sysClock); ENET_SetCallback(enet_handle, ethernet_callback, emac); ENET_ActiveRead(ENET); @@ -214,7 +215,7 @@ static rt_err_t k64_emac_init(rt_device_t dev) { DEBUG_PRINTF("read phy failed\n"); } - + return RT_EOK; } @@ -244,7 +245,7 @@ static rt_err_t k64_emac_control(rt_device_t dev, int cmd, void *args) { struct emac_device *emac; - DEBUG_PRINTF("k64_emac_control\n"); + DEBUG_PRINTF("k64_emac_control\n"); emac = K64_EMAC_DEVICE(dev); RT_ASSERT(emac != RT_NULL); @@ -270,14 +271,14 @@ static rt_err_t k64_emac_tx(rt_device_t dev, struct pbuf* p) struct emac_device *emac = K64_EMAC_DEVICE(dev); enet_handle_t * enet_handle = &emac->enet_handle; - + RT_ASSERT(p != NULL); - DEBUG_PRINTF("k64_emac_tx: %d\n", p->len); + DEBUG_PRINTF("k64_emac_tx: %d\n", p->len); emac = K64_EMAC_DEVICE(dev); RT_ASSERT(emac != RT_NULL); - + #ifdef DRV_EMAC_RX_DUMP { int i; @@ -290,10 +291,10 @@ static rt_err_t k64_emac_tx(rt_device_t dev, struct pbuf* p) DEBUG_PRINTF("\n"); } DEBUG_PRINTF("\n"); - } + } #endif - + do { result = ENET_SendFrame(ENET, enet_handle, p->payload, p->len); @@ -313,17 +314,17 @@ struct pbuf *k64_emac_rx(rt_device_t dev) uint32_t length = 0; status_t status; enet_data_error_stats_t eErrStatic; - + struct pbuf* p = RT_NULL; struct emac_device *emac = K64_EMAC_DEVICE(dev); enet_handle_t * enet_handle = &emac->enet_handle; RT_ASSERT(emac != RT_NULL); DEBUG_PRINTF("k64_emac_rx\n"); - + /* Get the Frame size */ status = ENET_GetRxFrameSize(enet_handle, &length); - + if (status == kStatus_ENET_RxFrameError) { /* Update the received buffer when error happened. */ @@ -331,19 +332,19 @@ struct pbuf *k64_emac_rx(rt_device_t dev) ENET_GetRxErrBeforeReadFrame(enet_handle, &eErrStatic); /* update the receive buffer. */ ENET_ReadFrame(ENET, enet_handle, NULL, 0); - + DEBUG_PRINTF("receive frame faild\n"); - + return p; } - + /* Call ENET_ReadFrame when there is a received frame. */ if (length != 0) { /* Received valid frame. Deliver the rx buffer with the size equal to length. */ p = pbuf_alloc(PBUF_RAW, length, PBUF_POOL); } - + if (p != NULL) { status = ENET_ReadFrame(ENET, enet_handle, p->payload, length); @@ -370,7 +371,7 @@ struct pbuf *k64_emac_rx(rt_device_t dev) pbuf_free(p); } } - + return p; } @@ -397,7 +398,7 @@ int drv_emac_hw_init(void) /* init tx semaphore */ rt_sem_init(&_emac.tx_wait, "tx_wait", ENET_TX_RING_LEN - 1, RT_IPC_FLAG_FIFO); - + /* register ETH device */ eth_device_init(&(_emac.parent), "e0"); @@ -409,15 +410,15 @@ INIT_DEVICE_EXPORT(drv_emac_hw_init); long k64_dump_tx_bd(void) { - int i; + int i; - enet_tx_bd_struct_t *txbd = _emac.TxBuffDescrip; + enet_tx_bd_struct_t *txbd = _emac.TxBuffDescrip; + + for (i = 0; i < ENET_RX_RING_LEN; i++) + { + DEBUG_PRINTF("status: %04X, length: %04X, data: %08X\n", txbd[i].control, txbd[i].length, (uint32_t)txbd[i].buffer); + } - for (i = 0; i < ENET_RX_RING_LEN; i++) - { - DEBUG_PRINTF("status: %04X, length: %04X, data: %08X\n", txbd[i].control, txbd[i].length, (uint32_t)txbd[i].buffer); - } - return 0; } FINSH_FUNCTION_EXPORT(k64_dump_tx_bd, dump all receive buffer descriptor); @@ -425,21 +426,21 @@ MSH_CMD_EXPORT(k64_dump_tx_bd, dump all receive buffer descriptor); long k64_dump_rx_bd(void) { - int i; - enet_rx_bd_struct_t *rxbd = _emac.RxBuffDescrip; + int i; + enet_rx_bd_struct_t *rxbd = _emac.RxBuffDescrip; - for (i = 0; i < ENET_RX_RING_LEN; i++) - { - DEBUG_PRINTF("bd:%08X, ", (void *)&rxbd[i]); - //rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, (void *)&rxbd[i], sizeof(enet_rx_bd_struct_t)); - DEBUG_PRINTF("status:%04X, length:%04X, data:%08X ", rxbd[i].control, rxbd[i].length, (uint32_t)rxbd[i].buffer); + for (i = 0; i < ENET_RX_RING_LEN; i++) + { + DEBUG_PRINTF("bd:%08X, ", (void *)&rxbd[i]); + //rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, (void *)&rxbd[i], sizeof(enet_rx_bd_struct_t)); + DEBUG_PRINTF("status:%04X, length:%04X, data:%08X ", rxbd[i].control, rxbd[i].length, (uint32_t)rxbd[i].buffer); #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE - DEBUG_PRINTF("ce:%04X/%04X/%04X ", rxbd[i].controlExtend0, rxbd[i].controlExtend1, rxbd[i].controlExtend2); - DEBUG_PRINTF("crc:%04X, len:%04X, type:%04X, ts:%04X", rxbd[i].payloadCheckSum, rxbd[i].headerLength, rxbd[i].protocolTyte, rxbd[i].timestamp); + DEBUG_PRINTF("ce:%04X/%04X/%04X ", rxbd[i].controlExtend0, rxbd[i].controlExtend1, rxbd[i].controlExtend2); + DEBUG_PRINTF("crc:%04X, len:%04X, type:%04X, ts:%04X", rxbd[i].payloadCheckSum, rxbd[i].headerLength, rxbd[i].protocolTyte, rxbd[i].timestamp); #endif - DEBUG_PRINTF("\n"); - } - + DEBUG_PRINTF("\n"); + } + return 0; } FINSH_FUNCTION_EXPORT(k64_dump_rx_bd, dump all receive buffer descriptor); diff --git a/bsp/frdm-k64f/board/drv_emac.h b/bsp/frdm-k64f/board/drv_emac.h index e2d0ec8c8c..7cc0a3f09a 100644 --- a/bsp/frdm-k64f/board/drv_emac.h +++ b/bsp/frdm-k64f/board/drv_emac.h @@ -1,7 +1,8 @@ /* * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd - * + * * SPDX-License-Identifier: Apache-2.0 + * * Change Logs: * Date Author Notes * 2015-07-15 Bernard The first version diff --git a/bsp/gd32303e-eval/Libraries/CMSIS/GD/GD32F30x/Source/GCC/startup_gd32f30x_hd.S b/bsp/gd32303e-eval/Libraries/CMSIS/GD/GD32F30x/Source/GCC/startup_gd32f30x_hd.S index 123c92182c..9d88020123 100644 --- a/bsp/gd32303e-eval/Libraries/CMSIS/GD/GD32F30x/Source/GCC/startup_gd32f30x_hd.S +++ b/bsp/gd32303e-eval/Libraries/CMSIS/GD/GD32F30x/Source/GCC/startup_gd32f30x_hd.S @@ -1,21 +1,7 @@ ;/* -; * File : startup_gd32f30x_hd.s -; * This file is part of RT-Thread RTOS -; * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team +; * Copyright (c) 2006-2021, RT-Thread Development Team ; * -; * This program is free software; you can redistribute it and/or modify -; * it under the terms of the GNU General Public License as published by -; * the Free Software Foundation; either version 2 of the License, or -; * (at your option) any later version. -; * -; * This program is distributed in the hope that it will be useful, -; * but WITHOUT ANY WARRANTY; without even the implied warranty of -; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; * GNU General Public License for more details. -; * -; * You should have received a copy of the GNU General Public License along -; * with this program; if not, write to the Free Software Foundation, Inc., -; * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +; * SPDX-License-Identifier: Apache-2.0 ; * ; * Change Logs: ; * Date Author Notes @@ -34,7 +20,7 @@ .type g_pfnVectors, %object g_pfnVectors: - .word _estack // Top of Stack + .word _estack // Top of Stack .word Reset_Handler // Reset Handler .word NMI_Handler // NMI Handler .word HardFault_Handler // Hard Fault Handler @@ -78,7 +64,7 @@ g_pfnVectors: .word EXTI5_9_IRQHandler // 39:EXTI5 to EXTI9 .word TIMER0_BRK_IRQHandler // 40:TIMER0 Break .word TIMER0_UP_IRQHandler // 41:TIMER0 Update - .word TIMER0_TRG_CMT_IRQHandler // 42:TIMER0 Trigger and Commutation + .word TIMER0_TRG_CMT_IRQHandler // 42:TIMER0 Trigger and Commutation .word TIMER0_Channel_IRQHandler // 43:TIMER0 Channel Capture Compare .word TIMER1_IRQHandler // 44:TIMER1 .word TIMER2_IRQHandler // 45:TIMER2 @@ -95,8 +81,8 @@ g_pfnVectors: .word EXTI10_15_IRQHandler // 56:EXTI10 to EXTI15 .word RTC_Alarm_IRQHandler // 57:RTC Alarm .word USBD_WKUP_IRQHandler // 58:USBD Wakeup - .word TIMER7_BRK_IRQHandler // 59:TIMER7 Break - .word TIMER7_UP_IRQHandler // 60:TIMER7 Update + .word TIMER7_BRK_IRQHandler // 59:TIMER7 Break + .word TIMER7_UP_IRQHandler // 60:TIMER7 Update .word TIMER7_TRG_CMT_IRQHandler // 61:TIMER7 Trigger and Commutation .word TIMER7_Channel_IRQHandler // 62:TIMER7 Channel Capture Compare .word ADC2_IRQHandler // 63:ADC2 @@ -106,7 +92,7 @@ g_pfnVectors: .word SPI2_IRQHandler // 67:SPI2 .word UART3_IRQHandler // 68:UART3 .word UART4_IRQHandler // 69:UART4 - .word TIMER5_IRQHandler // 70:TIMER5 + .word TIMER5_IRQHandler // 70:TIMER5 .word TIMER6_IRQHandler // 71:TIMER6 .word DMA1_Channel0_IRQHandler // 72:DMA1 Channel0 .word DMA1_Channel1_IRQHandler // 73:DMA1 Channel1 @@ -166,13 +152,13 @@ MemManage_Handler: BusFault_Handler: b . .size BusFault_Handler, . - BusFault_Handler - + .weak UsageFault_Handler .type UsageFault_Handler, %function UsageFault_Handler: b . .size UsageFault_Handler, . - UsageFault_Handler - + .weak SVC_Handler .type SVC_Handler, %function SVC_Handler: @@ -190,13 +176,13 @@ DebugMon_Handler: PendSV_Handler: b . .size PendSV_Handler, . - PendSV_Handler - + .weak SysTick_Handler .type SysTick_Handler, %function SysTick_Handler: b . .size SysTick_Handler, . - SysTick_Handler - + /* IQR Handler */ .section .text.Default_Handler,"ax",%progbits .type Default_Handler, %function diff --git a/bsp/gd32303e-eval/applications/main.c b/bsp/gd32303e-eval/applications/main.c index 6e190ae3cc..e9947e89d3 100644 --- a/bsp/gd32303e-eval/applications/main.c +++ b/bsp/gd32303e-eval/applications/main.c @@ -1,11 +1,7 @@ /* - * File : main.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/gd32303e-eval/drivers/board.c b/bsp/gd32303e-eval/drivers/board.c index d4091d32dc..5910ec4124 100644 --- a/bsp/gd32303e-eval/drivers/board.c +++ b/bsp/gd32303e-eval/drivers/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/gd32303e-eval/drivers/board.h b/bsp/gd32303e-eval/drivers/board.h index 4e97fce727..208f3f4c6a 100644 --- a/bsp/gd32303e-eval/drivers/board.h +++ b/bsp/gd32303e-eval/drivers/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/gd32303e-eval/drivers/drv_gpio.c b/bsp/gd32303e-eval/drivers/drv_gpio.c index 700a11d3df..a96cecc13e 100644 --- a/bsp/gd32303e-eval/drivers/drv_gpio.c +++ b/bsp/gd32303e-eval/drivers/drv_gpio.c @@ -1,11 +1,7 @@ /* - * File : drv_gpio.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/gd32303e-eval/drivers/drv_gpio.h b/bsp/gd32303e-eval/drivers/drv_gpio.h index bca532ff2d..ae9bda7dce 100644 --- a/bsp/gd32303e-eval/drivers/drv_gpio.h +++ b/bsp/gd32303e-eval/drivers/drv_gpio.h @@ -1,11 +1,7 @@ /* - * File : drv_gpio.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/gd32303e-eval/drivers/drv_i2c.c b/bsp/gd32303e-eval/drivers/drv_i2c.c index 0cca20e1d0..e7587618fe 100644 --- a/bsp/gd32303e-eval/drivers/drv_i2c.c +++ b/bsp/gd32303e-eval/drivers/drv_i2c.c @@ -1,21 +1,7 @@ /* - * File : drv_i2c.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/gd32303e-eval/drivers/drv_i2c.h b/bsp/gd32303e-eval/drivers/drv_i2c.h index 2cc86ace3c..c4b321594c 100644 --- a/bsp/gd32303e-eval/drivers/drv_i2c.h +++ b/bsp/gd32303e-eval/drivers/drv_i2c.h @@ -1,21 +1,7 @@ /* - * File : drv_i2c.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/gd32303e-eval/drivers/drv_spi.c b/bsp/gd32303e-eval/drivers/drv_spi.c index 78ff99d423..96f53b5019 100644 --- a/bsp/gd32303e-eval/drivers/drv_spi.c +++ b/bsp/gd32303e-eval/drivers/drv_spi.c @@ -1,11 +1,7 @@ /* - * File : drv_spi.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017 RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/gd32303e-eval/drivers/drv_spi.h b/bsp/gd32303e-eval/drivers/drv_spi.h index 69b07b70af..ba8e55916a 100644 --- a/bsp/gd32303e-eval/drivers/drv_spi.h +++ b/bsp/gd32303e-eval/drivers/drv_spi.h @@ -1,11 +1,7 @@ /* - * File : gd32f30x_spi.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/gd32303e-eval/drivers/drv_spi_flash.c b/bsp/gd32303e-eval/drivers/drv_spi_flash.c index d4a3dafc1b..64d4b32be3 100644 --- a/bsp/gd32303e-eval/drivers/drv_spi_flash.c +++ b/bsp/gd32303e-eval/drivers/drv_spi_flash.c @@ -1,11 +1,7 @@ /* - * File : stm32f20x_40x_spi.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/gd32303e-eval/drivers/drv_usart.c b/bsp/gd32303e-eval/drivers/drv_usart.c index 33430a5a31..07077f5cba 100644 --- a/bsp/gd32303e-eval/drivers/drv_usart.c +++ b/bsp/gd32303e-eval/drivers/drv_usart.c @@ -1,11 +1,7 @@ /* - * File : drv_usart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/gd32303e-eval/drivers/drv_usart.h b/bsp/gd32303e-eval/drivers/drv_usart.h index 2158016272..4059092706 100644 --- a/bsp/gd32303e-eval/drivers/drv_usart.h +++ b/bsp/gd32303e-eval/drivers/drv_usart.h @@ -1,11 +1,7 @@ /* - * File : drv_usart.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Source/GCC/startup_gd32f4xx.S b/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Source/GCC/startup_gd32f4xx.S index d3b0023b0a..149472da00 100644 --- a/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Source/GCC/startup_gd32f4xx.S +++ b/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Source/GCC/startup_gd32f4xx.S @@ -1,21 +1,7 @@ ;/* -; * File : startup_gd32f4xx.c -; * This file is part of RT-Thread RTOS -; * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team +; * Copyright (c) 2006-2021, RT-Thread Development Team ; * -; * This program is free software; you can redistribute it and/or modify -; * it under the terms of the GNU General Public License as published by -; * the Free Software Foundation; either version 2 of the License, or -; * (at your option) any later version. -; * -; * This program is distributed in the hope that it will be useful, -; * but WITHOUT ANY WARRANTY; without even the implied warranty of -; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; * GNU General Public License for more details. -; * -; * You should have received a copy of the GNU General Public License along -; * with this program; if not, write to the Free Software Foundation, Inc., -; * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +; * SPDX-License-Identifier: Apache-2.0 ; * ; * Change Logs: ; * Date Author Notes @@ -34,7 +20,7 @@ .type g_pfnVectors, %object g_pfnVectors: - .word _estack // Top of Stack + .word _estack // Top of Stack .word Reset_Handler // Reset Handler .word NMI_Handler // NMI Handler .word HardFault_Handler // Hard Fault Handler @@ -195,13 +181,13 @@ MemManage_Handler: BusFault_Handler: b . .size BusFault_Handler, . - BusFault_Handler - + .weak UsageFault_Handler .type UsageFault_Handler, %function UsageFault_Handler: b . .size UsageFault_Handler, . - UsageFault_Handler - + .weak SVC_Handler .type SVC_Handler, %function SVC_Handler: @@ -219,13 +205,13 @@ DebugMon_Handler: PendSV_Handler: b . .size PendSV_Handler, . - PendSV_Handler - + .weak SysTick_Handler .type SysTick_Handler, %function SysTick_Handler: b . .size SysTick_Handler, . - SysTick_Handler - + /* IQR Handler */ .section .text.Default_Handler,"ax",%progbits .type Default_Handler, %function diff --git a/bsp/gd32450z-eval/applications/main.c b/bsp/gd32450z-eval/applications/main.c index 9b0ba13a45..5c74d95c06 100644 --- a/bsp/gd32450z-eval/applications/main.c +++ b/bsp/gd32450z-eval/applications/main.c @@ -1,21 +1,7 @@ /* - * File : main.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/gd32450z-eval/applications/rtgui_demo.h b/bsp/gd32450z-eval/applications/rtgui_demo.h index e27f7b5609..d2d073b75d 100644 --- a/bsp/gd32450z-eval/applications/rtgui_demo.h +++ b/bsp/gd32450z-eval/applications/rtgui_demo.h @@ -1,11 +1,7 @@ /* - * File : dc.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2009, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/gd32450z-eval/drivers/board.c b/bsp/gd32450z-eval/drivers/board.c index f7628dae9b..fb17c159eb 100644 --- a/bsp/gd32450z-eval/drivers/board.c +++ b/bsp/gd32450z-eval/drivers/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/gd32450z-eval/drivers/board.h b/bsp/gd32450z-eval/drivers/board.h index 49e9bf56c4..ea7dd83acd 100644 --- a/bsp/gd32450z-eval/drivers/board.h +++ b/bsp/gd32450z-eval/drivers/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/gd32450z-eval/drivers/drv_enet.c b/bsp/gd32450z-eval/drivers/drv_enet.c index 66a6f9d516..f461b50fba 100644 --- a/bsp/gd32450z-eval/drivers/drv_enet.c +++ b/bsp/gd32450z-eval/drivers/drv_enet.c @@ -1,11 +1,7 @@ /* - * File : eth_driver.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/gd32450z-eval/drivers/drv_lcd.c b/bsp/gd32450z-eval/drivers/drv_lcd.c index 8f9e65c266..3cbae2ac84 100644 --- a/bsp/gd32450z-eval/drivers/drv_lcd.c +++ b/bsp/gd32450z-eval/drivers/drv_lcd.c @@ -1,11 +1,7 @@ /* - * File : usart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/gd32450z-eval/drivers/drv_spi.c b/bsp/gd32450z-eval/drivers/drv_spi.c index a1fc143cf2..acd4f7198f 100644 --- a/bsp/gd32450z-eval/drivers/drv_spi.c +++ b/bsp/gd32450z-eval/drivers/drv_spi.c @@ -1,11 +1,7 @@ /* - * File : drv_spi.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017 RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/gd32450z-eval/drivers/drv_spi.h b/bsp/gd32450z-eval/drivers/drv_spi.h index 692da41cbe..51bae441ca 100644 --- a/bsp/gd32450z-eval/drivers/drv_spi.h +++ b/bsp/gd32450z-eval/drivers/drv_spi.h @@ -1,11 +1,7 @@ /* - * File : gd32f20x_40x_spi.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/gd32450z-eval/drivers/drv_spi_flash.c b/bsp/gd32450z-eval/drivers/drv_spi_flash.c index 1731d1499b..7f95d59314 100644 --- a/bsp/gd32450z-eval/drivers/drv_spi_flash.c +++ b/bsp/gd32450z-eval/drivers/drv_spi_flash.c @@ -1,11 +1,7 @@ /* - * File : gd32f20x_40x_spi.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/gd32450z-eval/drivers/drv_usart.c b/bsp/gd32450z-eval/drivers/drv_usart.c index 226c6fd121..fa691a42b9 100644 --- a/bsp/gd32450z-eval/drivers/drv_usart.c +++ b/bsp/gd32450z-eval/drivers/drv_usart.c @@ -1,11 +1,7 @@ /* - * File : usart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/gd32450z-eval/drivers/drv_usart.h b/bsp/gd32450z-eval/drivers/drv_usart.h index 79c7ed6d90..547384efec 100644 --- a/bsp/gd32450z-eval/drivers/drv_usart.h +++ b/bsp/gd32450z-eval/drivers/drv_usart.h @@ -1,11 +1,7 @@ /* - * File : usart.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/gd32450z-eval/drivers/synopsys_emac.c b/bsp/gd32450z-eval/drivers/synopsys_emac.c index dfe1dd39b6..1894792d82 100644 --- a/bsp/gd32450z-eval/drivers/synopsys_emac.c +++ b/bsp/gd32450z-eval/drivers/synopsys_emac.c @@ -1,21 +1,7 @@ /* - * File : rthw.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 */ #include "synopsys_emac.h" #include "gd32f4xx_enet.h" diff --git a/bsp/gd32450z-eval/drivers/synopsys_emac.h b/bsp/gd32450z-eval/drivers/synopsys_emac.h index 1610f19540..f6c303ce7f 100644 --- a/bsp/gd32450z-eval/drivers/synopsys_emac.h +++ b/bsp/gd32450z-eval/drivers/synopsys_emac.h @@ -1,21 +1,7 @@ /* - * File : rtdef.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 */ #ifndef __SYNOPSYS_EMAC_H__ diff --git a/bsp/gkipc/applications/main.c b/bsp/gkipc/applications/main.c index 0d9fd0ebcf..971e404459 100644 --- a/bsp/gkipc/applications/main.c +++ b/bsp/gkipc/applications/main.c @@ -1,21 +1,7 @@ /* - * File : main.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/gkipc/armv6/context_gcc.s b/bsp/gkipc/armv6/context_gcc.s index 2980654f3f..69813d521b 100644 --- a/bsp/gkipc/armv6/context_gcc.s +++ b/bsp/gkipc/armv6/context_gcc.s @@ -1,50 +1,36 @@ /* - * File : context.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2011-01-13 weety copy from mini2440 */ -#define NOINT 0xc0 +#define NOINT 0xc0 .globl __delay __delay: - subs r0, r0, #1 + subs r0, r0, #1 #if 1 - movls pc, lr - subs r0, r0, #1 - movls pc, lr - subs r0, r0, #1 - movls pc, lr - subs r0, r0, #1 - movls pc, lr - subs r0, r0, #1 - movls pc, lr - subs r0, r0, #1 - movls pc, lr - subs r0, r0, #1 - movls pc, lr - subs r0, r0, #1 + movls pc, lr + subs r0, r0, #1 + movls pc, lr + subs r0, r0, #1 + movls pc, lr + subs r0, r0, #1 + movls pc, lr + subs r0, r0, #1 + movls pc, lr + subs r0, r0, #1 + movls pc, lr + subs r0, r0, #1 + movls pc, lr + subs r0, r0, #1 #endif - bhi __delay - mov pc, lr + bhi __delay + mov pc, lr /* @@ -52,52 +38,52 @@ __delay: */ .globl rt_hw_interrupt_disable rt_hw_interrupt_disable: - mrs r0, cpsr - orr r1, r0, #NOINT - msr cpsr_c, r1 - mov pc, lr + mrs r0, cpsr + orr r1, r0, #NOINT + msr cpsr_c, r1 + mov pc, lr /* * void rt_hw_interrupt_enable(rt_base_t level); */ .globl rt_hw_interrupt_enable rt_hw_interrupt_enable: - msr cpsr, r0 - mov pc, lr + msr cpsr, r0 + mov pc, lr .globl restore_context @.func restore_context - + .globl save_context @.func save_context save_context: - stmfd sp!, {lr} @ push pc (lr should be pushed in place of PC) - stmfd sp!, {r0-r12, lr} @ push lr & register file + stmfd sp!, {lr} @ push pc (lr should be pushed in place of PC) + stmfd sp!, {r0-r12, lr} @ push lr & register file - mrs r4, cpsr - stmfd sp!, {r4} @ push cpsr - mrs r4, spsr - stmfd sp!, {r4} @ push spsr + mrs r4, cpsr + stmfd sp!, {r4} @ push cpsr + mrs r4, spsr + stmfd sp!, {r4} @ push spsr - str sp, [r0] @ store sp in preempted tasks TCB - mov pc, lr + str sp, [r0] @ store sp in preempted tasks TCB + mov pc, lr bx lr @ branch back to caller restore_context: - ldr sp, [r0] @ get new task stack pointer + ldr sp, [r0] @ get new task stack pointer + + ldmfd sp!, {r4} @ pop new task spsr + msr spsr_cxsf, r4 + ldmfd sp!, {r4} @ pop new task cpsr + msr spsr_cxsf, r4 + + ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc - ldmfd sp!, {r4} @ pop new task spsr - msr spsr_cxsf, r4 - ldmfd sp!, {r4} @ pop new task cpsr - msr spsr_cxsf, r4 - ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc - - /* * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); * r0 --> from @@ -105,23 +91,23 @@ restore_context: */ .globl rt_hw_context_switch rt_hw_context_switch: - stmfd sp!, {lr} @ push pc (lr should be pushed in place of PC) - stmfd sp!, {r0-r12, lr} @ push lr & register file + stmfd sp!, {lr} @ push pc (lr should be pushed in place of PC) + stmfd sp!, {r0-r12, lr} @ push lr & register file - mrs r4, cpsr - stmfd sp!, {r4} @ push cpsr - mrs r4, spsr - stmfd sp!, {r4} @ push spsr + mrs r4, cpsr + stmfd sp!, {r4} @ push cpsr + mrs r4, spsr + stmfd sp!, {r4} @ push spsr - str sp, [r0] @ store sp in preempted tasks TCB - ldr sp, [r1] @ get new task stack pointer + str sp, [r0] @ store sp in preempted tasks TCB + ldr sp, [r1] @ get new task stack pointer - ldmfd sp!, {r4} @ pop new task spsr - msr spsr_cxsf, r4 - ldmfd sp!, {r4} @ pop new task cpsr - msr spsr_cxsf, r4 + ldmfd sp!, {r4} @ pop new task spsr + msr spsr_cxsf, r4 + ldmfd sp!, {r4} @ pop new task cpsr + msr spsr_cxsf, r4 - ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc + ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc /* * void rt_hw_context_switch_to(rt_uint32 to); @@ -129,14 +115,14 @@ rt_hw_context_switch: */ .globl rt_hw_context_switch_to rt_hw_context_switch_to: - ldr sp, [r0] @ get new task stack pointer + ldr sp, [r0] @ get new task stack pointer - ldmfd sp!, {r4} @ pop new task spsr - msr spsr_cxsf, r4 - ldmfd sp!, {r4} @ pop new task cpsr - msr cpsr_cxsf, r4 + ldmfd sp!, {r4} @ pop new task spsr + msr spsr_cxsf, r4 + ldmfd sp!, {r4} @ pop new task cpsr + msr cpsr_cxsf, r4 - ldmfd sp!, {r0-r12, lr, pc} @ pop new task r0-r12, lr & pc + ldmfd sp!, {r0-r12, lr, pc} @ pop new task r0-r12, lr & pc /* * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); @@ -146,15 +132,15 @@ rt_hw_context_switch_to: .globl rt_interrupt_to_thread .globl rt_hw_context_switch_interrupt rt_hw_context_switch_interrupt: - ldr r2, =rt_thread_switch_interrupt_flag - ldr r3, [r2] - cmp r3, #1 - beq _reswitch - mov r3, #1 @ set rt_thread_switch_interrupt_flag to 1 - str r3, [r2] - ldr r2, =rt_interrupt_from_thread @ set rt_interrupt_from_thread - str r0, [r2] + ldr r2, =rt_thread_switch_interrupt_flag + ldr r3, [r2] + cmp r3, #1 + beq _reswitch + mov r3, #1 @ set rt_thread_switch_interrupt_flag to 1 + str r3, [r2] + ldr r2, =rt_interrupt_from_thread @ set rt_interrupt_from_thread + str r0, [r2] _reswitch: - ldr r2, =rt_interrupt_to_thread @ set rt_interrupt_to_thread - str r1, [r2] - mov pc, lr + ldr r2, =rt_interrupt_to_thread @ set rt_interrupt_to_thread + str r1, [r2] + mov pc, lr diff --git a/bsp/gkipc/armv6/cpuport.c b/bsp/gkipc/armv6/cpuport.c index 08e7f9315b..21235e825b 100644 --- a/bsp/gkipc/armv6/cpuport.c +++ b/bsp/gkipc/armv6/cpuport.c @@ -1,21 +1,7 @@ /* - * File : cpu.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/gkipc/armv6/gk7101.h b/bsp/gkipc/armv6/gk7101.h index 8614dab4da..bcf7f110f1 100644 --- a/bsp/gkipc/armv6/gk7101.h +++ b/bsp/gkipc/armv6/gk7101.h @@ -1,21 +1,7 @@ /* - * File : at91sam926x.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -36,35 +22,35 @@ extern "C" { /*****************************/ /* CPU Mode */ /*****************************/ -#define USERMODE 0x10 -#define FIQMODE 0x11 -#define IRQMODE 0x12 -#define SVCMODE 0x13 -#define ABORTMODE 0x17 -#define UNDEFMODE 0x1b -#define MODEMASK 0x1f -#define NOINT 0xc0 +#define USERMODE 0x10 +#define FIQMODE 0x11 +#define IRQMODE 0x12 +#define SVCMODE 0x13 +#define ABORTMODE 0x17 +#define UNDEFMODE 0x1b +#define MODEMASK 0x1f +#define NOINT 0xc0 struct rt_hw_register { - rt_uint32_t r0; - rt_uint32_t r1; - rt_uint32_t r2; - rt_uint32_t r3; - rt_uint32_t r4; - rt_uint32_t r5; - rt_uint32_t r6; - rt_uint32_t r7; - rt_uint32_t r8; - rt_uint32_t r9; - rt_uint32_t r10; - rt_uint32_t fp; - rt_uint32_t ip; - rt_uint32_t sp; - rt_uint32_t lr; - rt_uint32_t pc; - rt_uint32_t cpsr; - rt_uint32_t ORIG_r0; + rt_uint32_t r0; + rt_uint32_t r1; + rt_uint32_t r2; + rt_uint32_t r3; + rt_uint32_t r4; + rt_uint32_t r5; + rt_uint32_t r6; + rt_uint32_t r7; + rt_uint32_t r8; + rt_uint32_t r9; + rt_uint32_t r10; + rt_uint32_t fp; + rt_uint32_t ip; + rt_uint32_t sp; + rt_uint32_t lr; + rt_uint32_t pc; + rt_uint32_t cpsr; + rt_uint32_t ORIG_r0; }; #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) diff --git a/bsp/gkipc/armv6/interrupt.c b/bsp/gkipc/armv6/interrupt.c index 0eb03c9b2c..f276f3ee3c 100644 --- a/bsp/gkipc/armv6/interrupt.c +++ b/bsp/gkipc/armv6/interrupt.c @@ -1,21 +1,7 @@ /* - * File : interrupt.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/gkipc/armv6/mmu.c b/bsp/gkipc/armv6/mmu.c index 9f331c7147..0085113f3d 100644 --- a/bsp/gkipc/armv6/mmu.c +++ b/bsp/gkipc/armv6/mmu.c @@ -1,21 +1,7 @@ /* - * File : mmu.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -27,22 +13,22 @@ #ifdef __CC_ARM void mmu_setttbase(rt_uint32_t i) { - register rt_uint32_t value; + register rt_uint32_t value; /* Invalidates all TLBs.Domain access is selected as * client by configuring domain access register, * in that case access controlled by permission value * set by page table entry */ - value = 0; + value = 0; __asm { mcr p15, 0, value, c8, c7, 0 - } + } - value = 0x55555555; - __asm - { + value = 0x55555555; + __asm + { mcr p15, 0, value, c3, c0, 0 mcr p15, 0, i, c2, c0, 0 } @@ -168,44 +154,44 @@ void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size) while(ptr < buffer + size) { - __asm - { - MCR p15, 0, ptr, c7, c14, 1 - } + __asm + { + MCR p15, 0, ptr, c7, c14, 1 + } ptr += CACHE_LINE_SIZE; } } void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while (ptr < buffer + size) - { - __asm - { - MCR p15, 0, ptr, c7, c10, 1 - } - ptr += CACHE_LINE_SIZE; - } + while (ptr < buffer + size) + { + __asm + { + MCR p15, 0, ptr, c7, c10, 1 + } + ptr += CACHE_LINE_SIZE; + } } void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while (ptr < buffer + size) - { - __asm - { - MCR p15, 0, ptr, c7, c6, 1 - } - ptr += CACHE_LINE_SIZE; - } + while (ptr < buffer + size) + { + __asm + { + MCR p15, 0, ptr, c7, c6, 1 + } + ptr += CACHE_LINE_SIZE; + } } void mmu_invalidate_tlb() @@ -246,7 +232,7 @@ void mmu_invalidate_dcache_all() #elif defined(__GNUC__) void mmu_setttbase(register rt_uint32_t i) { - //register rt_uint32_t value; + //register rt_uint32_t value; /* Invalidates all TLBs.Domain access is selected as * client by configuring domain access register, @@ -254,18 +240,18 @@ void mmu_setttbase(register rt_uint32_t i) * set by page table entry */ #if 0 - value = 0; - asm ("mcr p15, 0, %0, c8,c7, 0"::"r"(value)); + value = 0; + asm ("mcr p15, 0, %0, c8,c7, 0"::"r"(value)); - value = 0x55555555; - asm ("mcr p15, 0, %0, c3,c0, 0"::"r"(value)); - asm ("mcr p15, 0, %0, c2,c0, 0"::"r"(i)); + value = 0x55555555; + asm ("mcr p15, 0, %0, c3,c0, 0"::"r"(value)); + asm ("mcr p15, 0, %0, c2,c0, 0"::"r"(i)); #endif - asm ( - "mrc p15,0,r0,c1,c0,0 \r\n" + asm ( + "mrc p15,0,r0,c1,c0,0 \r\n" "mov r1,#0x800000 \r\n" - "orr r0,r0,r1 @ disable Subpage AP bits \r\n" + "orr r0,r0,r1 @ disable Subpage AP bits \r\n" "mcr p15,0,r0,c1,c0,0 @ write value back \r\n" "mov r0,#0x0 \r\n" "mcr p15,0,r0,c2,c0,2 @ W \r\n" @@ -275,116 +261,116 @@ void mmu_setttbase(register rt_uint32_t i) void mmu_set_domain(register rt_uint32_t i) { - asm ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); + asm ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); } void mmu_enable() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= 0x1; + i |= 0x1; - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~0x1; + i &= ~0x1; - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_enable_icache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= (1 << 12); + i |= (1 << 12); - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_enable_dcache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= (1 << 2); + i |= (1 << 2); - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable_icache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(1 << 12); + i &= ~(1 << 12); - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable_dcache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(1 << 2); + i &= ~(1 << 2); - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_enable_alignfault() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= (1 << 1); + i |= (1 << 1); - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable_alignfault() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(1 << 1); + i &= ~(1 << 1); - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_clean_invalidated_cache_index(int index) { - asm ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); + asm ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); } void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size) @@ -395,7 +381,7 @@ void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size) while(ptr < buffer + size) { - asm ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr)); + asm ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr)); ptr += CACHE_LINE_SIZE; } } @@ -403,38 +389,38 @@ void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size) void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while (ptr < buffer + size) - { - asm ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr)); - ptr += CACHE_LINE_SIZE; - } + while (ptr < buffer + size) + { + asm ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr)); + ptr += CACHE_LINE_SIZE; + } } void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while (ptr < buffer + size) - { - asm ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr)); - ptr += CACHE_LINE_SIZE; - } + while (ptr < buffer + size) + { + asm ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr)); + ptr += CACHE_LINE_SIZE; + } } void mmu_invalidate_tlb() { - asm ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); + asm ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); } void mmu_invalidate_icache() { - asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); + asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); } void mmu_invalidate_dcache_all() @@ -458,8 +444,8 @@ void mmu_setmtt(rt_uint32_t vaddrStart, rt_uint32_t vaddrEnd, rt_uint32_t paddrS nSec=(vaddrEnd>>20)-(vaddrStart>>20); for(i=0;i<=nSec;i++) { - *pTT = attr |(((paddrStart>>20)+i)<<20); - pTT++; + *pTT = attr |(((paddrStart>>20)+i)<<20); + pTT++; } } @@ -528,22 +514,22 @@ void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb) void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size) { - /* disable I/D cache */ - mmu_disable_dcache(); - mmu_disable_icache(); - mmu_disable(); - mmu_invalidate_tlb(); + /* disable I/D cache */ + mmu_disable_dcache(); + mmu_disable_icache(); + mmu_disable(); + mmu_invalidate_tlb(); - /* set page table */ - for (; size > 0; size--) - { - mmu_setmtt(mdesc->vaddr_start, mdesc->vaddr_end, - mdesc->paddr_start, mdesc->attr); - mdesc++; - } + /* set page table */ + for (; size > 0; size--) + { + mmu_setmtt(mdesc->vaddr_start, mdesc->vaddr_end, + mdesc->paddr_start, mdesc->attr); + mdesc++; + } - /* set MMU table address */ - mmu_setttbase((rt_uint32_t)_page_table); + /* set MMU table address */ + mmu_setttbase((rt_uint32_t)_page_table); /* enables MMU */ mmu_enable(); diff --git a/bsp/gkipc/armv6/mmu.h b/bsp/gkipc/armv6/mmu.h index 2ca3d03817..7476dc42ab 100644 --- a/bsp/gkipc/armv6/mmu.h +++ b/bsp/gkipc/armv6/mmu.h @@ -1,21 +1,7 @@ /* - * File : mmu.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -26,29 +12,29 @@ #include -#define CACHE_LINE_SIZE 32 +#define CACHE_LINE_SIZE 32 -#define DESC_SEC (0x2|(1<<4)) -#define CB (3<<2) //cache_on, write_back -#define CNB (2<<2) //cache_on, write_through -#define NCB (1<<2) //cache_off,WR_BUF on -#define NCNB (0<<2) //cache_off,WR_BUF off -#define AP_RW (3<<10) //supervisor=RW, user=RW -#define AP_RO (2<<10) //supervisor=RW, user=RO +#define DESC_SEC (0x2|(1<<4)) +#define CB (3<<2) //cache_on, write_back +#define CNB (2<<2) //cache_on, write_through +#define NCB (1<<2) //cache_off,WR_BUF on +#define NCNB (0<<2) //cache_off,WR_BUF off +#define AP_RW (3<<10) //supervisor=RW, user=RW +#define AP_RO (2<<10) //supervisor=RW, user=RO -#define DOMAIN_FAULT (0x0) -#define DOMAIN_CHK (0x1) -#define DOMAIN_NOTCHK (0x3) -#define DOMAIN0 (0x0<<5) -#define DOMAIN1 (0x1<<5) +#define DOMAIN_FAULT (0x0) +#define DOMAIN_CHK (0x1) +#define DOMAIN_NOTCHK (0x3) +#define DOMAIN0 (0x0<<5) +#define DOMAIN1 (0x1<<5) -#define DOMAIN0_ATTR (DOMAIN_CHK<<0) -#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) +#define DOMAIN0_ATTR (DOMAIN_CHK<<0) +#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) -#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) /* Read/Write, cache, write back */ -#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) /* Read/Write, cache, write through */ -#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ -#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ +#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) /* Read/Write, cache, write back */ +#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) /* Read/Write, cache, write through */ +#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ +#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ #define ARM1176_1MB_NOCACHE_BUFFER 0x00000DE6 // non-cachable/bufferable #define ARM1176_1MB_CACHE_NOBUFFER 0x00000DEA // cachable/non-bufferable @@ -60,10 +46,10 @@ struct mem_desc { - rt_uint32_t vaddr_start; - rt_uint32_t vaddr_end; - rt_uint32_t paddr_start; - rt_uint32_t attr; + rt_uint32_t vaddr_start; + rt_uint32_t vaddr_end; + rt_uint32_t paddr_start; + rt_uint32_t attr; }; void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size); diff --git a/bsp/gkipc/armv6/reset.c b/bsp/gkipc/armv6/reset.c index b7bc58f664..a2adc17499 100644 --- a/bsp/gkipc/armv6/reset.c +++ b/bsp/gkipc/armv6/reset.c @@ -1,21 +1,7 @@ /* - * File : reset.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/gkipc/armv6/stack.c b/bsp/gkipc/armv6/stack.c index 8167923856..bfaf18ba70 100644 --- a/bsp/gkipc/armv6/stack.c +++ b/bsp/gkipc/armv6/stack.c @@ -1,21 +1,7 @@ /* - * File : stack.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -25,29 +11,29 @@ /*****************************/ /* CPU Mode */ /*****************************/ -#define USERMODE 0x10 -#define FIQMODE 0x11 -#define IRQMODE 0x12 -#define SVCMODE 0x13 -#define ABORTMODE 0x17 -#define UNDEFMODE 0x1b -#define MODEMASK 0x1f -#define NOINT 0xc0 +#define USERMODE 0x10 +#define FIQMODE 0x11 +#define IRQMODE 0x12 +#define SVCMODE 0x13 +#define ABORTMODE 0x17 +#define UNDEFMODE 0x1b +#define MODEMASK 0x1f +#define NOINT 0xc0 /** * This function will initialize thread stack * * @param tentry the entry of thread - * @param parameter the parameter of entry + * @param parameter the parameter of entry * @param stack_addr the beginning stack address * @param texit the function will be called when thread exit * * @return stack address */ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) + rt_uint8_t *stack_addr, void *texit) { - rt_uint32_t *stk; + rt_uint32_t *stk; stack_addr += sizeof(rt_uint32_t); stack_addr = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8); @@ -68,10 +54,10 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, *(--stk) = 0xdeadbeef; /* r2 */ *(--stk) = 0xdeadbeef; /* r1 */ *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */ - *(--stk) = SVCMODE; /* cpsr */ - *(--stk) = SVCMODE; /* spsr */ + *(--stk) = SVCMODE; /* cpsr */ + *(--stk) = SVCMODE; /* spsr */ - /* return task's current stack address */ - return (rt_uint8_t *)stk; + /* return task's current stack address */ + return (rt_uint8_t *)stk; } diff --git a/bsp/gkipc/armv6/start_gcc.s b/bsp/gkipc/armv6/start_gcc.s index 6f9da355e3..684ff81eab 100644 --- a/bsp/gkipc/armv6/start_gcc.s +++ b/bsp/gkipc/armv6/start_gcc.s @@ -1,21 +1,7 @@ /* - * File : start.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -183,7 +169,7 @@ reset: mrc p15, 0, r1, c0, c0, 1 @/* Read cache type {0x1d152152}*/ mrc p15, 0, r2, c0, c0, 2 @/* Read TCM status {0x10001}*/ -#ifdef GK7102C +#ifdef GK7102C @mrc p15, 0, r0, c15,c14,0 @ read CP15 register c15 into r0 @orr r0, r0,#0x80000000 @ system bit enabled @bic r0, r0,#0x00000077 @ @@ -194,7 +180,7 @@ reset: orr r0, r0,#0x00000040 @CZ bit enabled mcr p15, 0, r0, c1, c0, 1 @read CP15 register c1 into r0 #endif - + @/* Turn on instrucion cache and disable MMU */ mrc p15, 0, r0, c1, c0, 0 @/* Read control register {0x5327d}*/ @bic r0, r0, #0x1000 @ Turn off bit 12 - I-cache diff --git a/bsp/gkipc/armv6/system_clock.c b/bsp/gkipc/armv6/system_clock.c index 17c072fdfe..ad11201c93 100644 --- a/bsp/gkipc/armv6/system_clock.c +++ b/bsp/gkipc/armv6/system_clock.c @@ -1,21 +1,7 @@ /* - * File : clock.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/gkipc/armv6/trap.c b/bsp/gkipc/armv6/trap.c index 602badff39..1c239f1d8c 100644 --- a/bsp/gkipc/armv6/trap.c +++ b/bsp/gkipc/armv6/trap.c @@ -1,21 +1,7 @@ /* - * File : trap.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -112,16 +98,16 @@ int g_wifi_input = 0; int g_wifi_output = 0; void rt_hw_show_register (struct rt_hw_register *regs) { - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); - rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("cpsr:0x%08x\n", regs->cpsr); - rt_kprintf("eth info : in = %d out = %d\n", g_eth_input, g_eth_output); - rt_kprintf("wifi info: in = %d out = %d\n", g_wifi_input, g_wifi_output); - _rtt_statistics(); + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); + rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); + rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); + rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); + rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); + rt_kprintf("cpsr:0x%08x\n", regs->cpsr); + rt_kprintf("eth info : in = %d out = %d\n", g_eth_input, g_eth_output); + rt_kprintf("wifi info: in = %d out = %d\n", g_wifi_input, g_wifi_output); + _rtt_statistics(); } /** @@ -134,15 +120,15 @@ void rt_hw_show_register (struct rt_hw_register *regs) */ void rt_hw_trap_udef(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("undefined instruction\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_kprintf("undefined instruction\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -156,10 +142,10 @@ void rt_hw_trap_udef(struct rt_hw_register *regs) */ void rt_hw_trap_swi(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("software interrupt\n"); - rt_hw_cpu_shutdown(); + rt_kprintf("software interrupt\n"); + rt_hw_cpu_shutdown(); } /** @@ -172,15 +158,15 @@ void rt_hw_trap_swi(struct rt_hw_register *regs) */ void rt_hw_trap_pabt(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("prefetch abort\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_kprintf("prefetch abort\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -194,16 +180,16 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs) void rt_hw_trap_dabt(struct rt_hw_register *regs) { - rt_kprintf(">>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); - rt_kprintf("data abort\n"); - rt_kprintf("thread - [%s] stack:\n", rt_current_thread->name); + rt_kprintf(">>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); + rt_kprintf("data abort\n"); + rt_kprintf("thread - [%s] stack:\n", rt_current_thread->name); - rt_hw_show_register(regs); + rt_hw_show_register(regs); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -215,9 +201,9 @@ void rt_hw_trap_dabt(struct rt_hw_register *regs) */ void rt_hw_trap_resv(struct rt_hw_register *regs) { - rt_kprintf("not used\n"); - rt_hw_show_register(regs); - rt_hw_cpu_shutdown(); + rt_kprintf("not used\n"); + rt_hw_show_register(regs); + rt_hw_cpu_shutdown(); } extern struct rt_irq_desc irq_desc[]; @@ -225,26 +211,26 @@ extern struct rt_irq_desc irq_desc[]; void rt_hw_trap_irq() { int index; - //rt_kprintf("irq interrupt request\n"); + //rt_kprintf("irq interrupt request\n"); GD_IRQ_ISR(); - if(gkosHookData) - { - for( index=0; index < gkosHookData->timerFunctionCount; index++ ) - { - if( gkosHookData->timerFunctionArray[index] ) - { - (*gkosHookData->timerFunctionArray[index])(NULL); - } - } - } + if(gkosHookData) + { + for( index=0; index < gkosHookData->timerFunctionCount; index++ ) + { + if( gkosHookData->timerFunctionArray[index] ) + { + (*gkosHookData->timerFunctionArray[index])(NULL); + } + } + } } void rt_hw_trap_fiq() { - //rt_kprintf("fast interrupt request\n"); - GD_FIQ_ISR(); - //rt_tick_increase(); + //rt_kprintf("fast interrupt request\n"); + GD_FIQ_ISR(); + //rt_tick_increase(); } /*@}*/ diff --git a/bsp/gkipc/drivers/board.h b/bsp/gkipc/drivers/board.h index 9e7659e77b..815a1f981d 100644 --- a/bsp/gkipc/drivers/board.h +++ b/bsp/gkipc/drivers/board.h @@ -1,21 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/hifive1/applications/main.c b/bsp/hifive1/applications/main.c index 9fdfde2334..e3cd69f303 100644 --- a/bsp/hifive1/applications/main.c +++ b/bsp/hifive1/applications/main.c @@ -1,21 +1,7 @@ /* - * File : main.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -28,5 +14,5 @@ int main(void) { - return 0; + return 0; } diff --git a/bsp/hifive1/drivers/board.c b/bsp/hifive1/drivers/board.c index 80a425309b..273901b93e 100644 --- a/bsp/hifive1/drivers/board.c +++ b/bsp/hifive1/drivers/board.c @@ -1,21 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/hifive1/drivers/board.h b/bsp/hifive1/drivers/board.h index 698f316267..a708115374 100644 --- a/bsp/hifive1/drivers/board.h +++ b/bsp/hifive1/drivers/board.h @@ -1,21 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/hifive1/drivers/drv_usart.c b/bsp/hifive1/drivers/drv_usart.c index 6588892ae9..935d39105f 100644 --- a/bsp/hifive1/drivers/drv_usart.c +++ b/bsp/hifive1/drivers/drv_usart.c @@ -1,21 +1,7 @@ /* - * File : drv_usart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -37,7 +23,7 @@ static rt_err_t usart_configure(struct rt_serial_device *serial, { RT_ASSERT(serial != RT_NULL); RT_ASSERT(cfg != RT_NULL); - + GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK; GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK; diff --git a/bsp/hifive1/drivers/interrupt.c b/bsp/hifive1/drivers/interrupt.c index 506e80f451..75e8e8ac59 100644 --- a/bsp/hifive1/drivers/interrupt.c +++ b/bsp/hifive1/drivers/interrupt.c @@ -1,21 +1,7 @@ /* - * File : interrupt.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -62,13 +48,13 @@ rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector, void *param) void rt_hw_interrupt_init(void) { int idx; - + /* config interrupt vector*/ asm volatile( "la t0, trap_entry\n" "csrw mtvec, t0" ); - + /* enable global interrupt*/ PLIC_init(&g_plic, PLIC_CTRL_ADDR, @@ -86,8 +72,8 @@ void rt_hw_interrupt_init(void) irq_desc[idx].counter = 0; #endif } - - // enable machine external interrupt + + // enable machine external interrupt set_csr(mie, MIP_MEIP); } @@ -132,7 +118,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, } /** - * This function will be call when external machine-level + * This function will be call when external machine-level * interrupt from PLIC occurred. */ void handle_m_ext_interrupt(void) diff --git a/bsp/hifive1/drivers/interrupt.h b/bsp/hifive1/drivers/interrupt.h index 506634e667..52d378233a 100644 --- a/bsp/hifive1/drivers/interrupt.h +++ b/bsp/hifive1/drivers/interrupt.h @@ -1,21 +1,7 @@ /* - * File : interrupt.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -33,5 +19,5 @@ rt_uint32_t rt_hw_interrupt_get_active(rt_uint32_t fiq_irq); void rt_hw_interrupt_ack(rt_uint32_t fiq_irq, rt_uint32_t id); rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, void *param, const char *name); - + #endif diff --git a/bsp/imx6sx/cortex-a9/drivers/emac_drv.c b/bsp/imx6sx/cortex-a9/drivers/emac_drv.c index af5ca009cf..ff8a579435 100644 --- a/bsp/imx6sx/cortex-a9/drivers/emac_drv.c +++ b/bsp/imx6sx/cortex-a9/drivers/emac_drv.c @@ -1,7 +1,8 @@ /* * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd - * + * * SPDX-License-Identifier: Apache-2.0 + * * Change Logs: * Date Author Notes * 2015-07-15 Bernard The first version @@ -16,17 +17,17 @@ #include #include "emac_drv.h" -#define MAX_ADDR_LEN 6 -#define IMX_EMAC_DEVICE(eth) (struct emac_device*)(eth) +#define MAX_ADDR_LEN 6 +#define IMX_EMAC_DEVICE(eth) (struct emac_device*)(eth) struct emac_device { - /* inherit from Ethernet device */ - struct eth_device parent; + /* inherit from Ethernet device */ + struct eth_device parent; - imx_enet_priv_t enet_priv; - /* interface address info. */ - rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* MAC address */ + imx_enet_priv_t enet_priv; + /* interface address info. */ + rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* MAC address */ }; static struct emac_device _emac; @@ -54,7 +55,7 @@ void init_enet(struct emac_device* emac) // Check PHY link status. if (!(emac->enet_priv.status & ENET_STATUS_LINK_ON)) { - rt_kprintf("ENET link status check fail\n"); + rt_kprintf("ENET link status check fail\n"); } imx_enet_start(&emac->enet_priv, emac->dev_addr); @@ -62,69 +63,69 @@ void init_enet(struct emac_device* emac) void imx_enet_isr(int vector, void *param) { - unsigned int value = 0; - imx_enet_priv_t * dev = &(_emac.enet_priv); - volatile hw_enet_t *enet_reg = dev->enet_reg; + unsigned int value = 0; + imx_enet_priv_t * dev = &(_emac.enet_priv); + volatile hw_enet_t *enet_reg = dev->enet_reg; value = enet_reg->EIR.U; enet_reg->EIR.U = value & (~ENET_EVENT_MII); if (value & ENET_EVENT_TX_ERR) - { + { dev->tx_busy = 0; } - else if (value & ENET_EVENT_TX) - { + else if (value & ENET_EVENT_TX) + { dev->tx_busy = 0; } if (value & ENET_EVENT_RX) - { - eth_device_ready(&(_emac.parent)); + { + eth_device_ready(&(_emac.parent)); } if (value & ENET_EVENT_HBERR) - { + { // printf("WARNGING[POLL]: Hearbeat error!\n"); } if (value & ENET_EVENT_EBERR) - { + { // printf("WARNING[POLL]: Ethernet Bus Error!\n"); } } static rt_err_t imx_emac_init(rt_device_t dev) { - struct emac_device *emac; + struct emac_device *emac; - emac = IMX_EMAC_DEVICE(dev); + emac = IMX_EMAC_DEVICE(dev); - /* initialize enet */ - init_enet(emac); - return RT_EOK; + /* initialize enet */ + init_enet(emac); + return RT_EOK; } static rt_err_t imx_emac_open(rt_device_t dev, rt_uint16_t oflag) { - return RT_EOK; + return RT_EOK; } static rt_err_t imx_emac_close(rt_device_t dev) { - return RT_EOK; + return RT_EOK; } static rt_size_t imx_emac_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_size_t imx_emac_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_err_t imx_emac_control(rt_device_t dev, int cmd, void *args) @@ -134,19 +135,19 @@ static rt_err_t imx_emac_control(rt_device_t dev, int cmd, void *args) emac = IMX_EMAC_DEVICE(dev); RT_ASSERT(emac != RT_NULL); - switch(cmd) - { - case NIOCTL_GADDR: - /* get MAC address */ - if(args) rt_memcpy(args, emac->dev_addr, 6); - else return -RT_ERROR; - break; + switch(cmd) + { + case NIOCTL_GADDR: + /* get MAC address */ + if(args) rt_memcpy(args, emac->dev_addr, 6); + else return -RT_ERROR; + break; - default : - break; - } + default : + break; + } - return RT_EOK; + return RT_EOK; } /* Ethernet device interface */ @@ -161,8 +162,8 @@ rt_err_t imx_emac_tx(rt_device_t dev, struct pbuf* p) /* copy pbuf to a whole ETH frame */ pbuf_copy_partial(p, s_pkt_send, p->tot_len, 0); - /* send to the enet */ - imx_enet_send(&emac->enet_priv, s_pkt_send, p->tot_len, 1); + /* send to the enet */ + imx_enet_send(&emac->enet_priv, s_pkt_send, p->tot_len, 1); return result; } @@ -170,23 +171,23 @@ rt_err_t imx_emac_tx(rt_device_t dev, struct pbuf* p) /* reception packet. */ struct pbuf *imx_emac_rx(rt_device_t dev) { - int len; + int len; struct pbuf* p = RT_NULL; struct emac_device *emac; emac = IMX_EMAC_DEVICE(dev); RT_ASSERT(emac != RT_NULL); - imx_enet_recv(&emac->enet_priv, s_pkt_recv, &len); - if (len > 0) - { - /* We allocate a pbuf chain of pbufs from the pool. */ - p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL); - if (p != RT_NULL) - { - pbuf_take(p, s_pkt_recv, len); - } - } + imx_enet_recv(&emac->enet_priv, s_pkt_recv, &len); + if (len > 0) + { + /* We allocate a pbuf chain of pbufs from the pool. */ + p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL); + if (p != RT_NULL) + { + pbuf_take(p, s_pkt_recv, len); + } + } return p; } @@ -194,27 +195,27 @@ struct pbuf *imx_emac_rx(rt_device_t dev) int imx_emac_hw_init(void) { /* test MAC address */ - _emac.dev_addr[0] = 0x00; - _emac.dev_addr[1] = 0x11; - _emac.dev_addr[2] = 0x22; - _emac.dev_addr[3] = 0x33; - _emac.dev_addr[4] = 0x44; - _emac.dev_addr[5] = 0x55; + _emac.dev_addr[0] = 0x00; + _emac.dev_addr[1] = 0x11; + _emac.dev_addr[2] = 0x22; + _emac.dev_addr[3] = 0x33; + _emac.dev_addr[4] = 0x44; + _emac.dev_addr[5] = 0x55; - _emac.parent.parent.init = imx_emac_init; - _emac.parent.parent.open = imx_emac_open; - _emac.parent.parent.close = imx_emac_close; - _emac.parent.parent.read = imx_emac_read; - _emac.parent.parent.write = imx_emac_write; - _emac.parent.parent.control = imx_emac_control; - _emac.parent.parent.user_data = RT_NULL; + _emac.parent.parent.init = imx_emac_init; + _emac.parent.parent.open = imx_emac_open; + _emac.parent.parent.close = imx_emac_close; + _emac.parent.parent.read = imx_emac_read; + _emac.parent.parent.write = imx_emac_write; + _emac.parent.parent.control = imx_emac_control; + _emac.parent.parent.user_data = RT_NULL; - _emac.parent.eth_rx = imx_emac_rx; - _emac.parent.eth_tx = imx_emac_tx; + _emac.parent.eth_rx = imx_emac_rx; + _emac.parent.eth_tx = imx_emac_tx; /* register ETH device */ eth_device_init(&(_emac.parent), "e0"); - return 0; + return 0; } INIT_DEVICE_EXPORT(imx_emac_hw_init); diff --git a/bsp/imx6sx/cortex-a9/drivers/emac_drv.h b/bsp/imx6sx/cortex-a9/drivers/emac_drv.h index face875283..455fa496e7 100644 --- a/bsp/imx6sx/cortex-a9/drivers/emac_drv.h +++ b/bsp/imx6sx/cortex-a9/drivers/emac_drv.h @@ -1,7 +1,8 @@ /* * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd - * + * * SPDX-License-Identifier: Apache-2.0 + * * Change Logs: * Date Author Notes * 2015-07-15 Bernard The first version diff --git a/bsp/imx6sx/cortex-a9/drivers/serial.c b/bsp/imx6sx/cortex-a9/drivers/serial.c index a2d4e2338a..5a9e8121e1 100644 --- a/bsp/imx6sx/cortex-a9/drivers/serial.c +++ b/bsp/imx6sx/cortex-a9/drivers/serial.c @@ -1,7 +1,8 @@ /* * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd - * + * * SPDX-License-Identifier: Apache-2.0 + * * Change Logs: * Date Author Notes * 2013-03-30 Bernard the first verion diff --git a/bsp/imx6sx/cortex-a9/drivers/serial.h b/bsp/imx6sx/cortex-a9/drivers/serial.h index 00d464bde0..862ba65ef7 100644 --- a/bsp/imx6sx/cortex-a9/drivers/serial.h +++ b/bsp/imx6sx/cortex-a9/drivers/serial.h @@ -1,7 +1,8 @@ /* * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd - * + * * SPDX-License-Identifier: Apache-2.0 + * * Change Logs: * Date Author Notes * 2013-03-30 Bernard the first verion diff --git a/bsp/imx6ul/drivers/serial.c b/bsp/imx6ul/drivers/serial.c index 0f6943cfbd..ce46050c92 100644 --- a/bsp/imx6ul/drivers/serial.c +++ b/bsp/imx6ul/drivers/serial.c @@ -1,7 +1,8 @@ /* * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd - * + * * SPDX-License-Identifier: Apache-2.0 + * * Change Logs: * Date Author Notes * 2013-03-30 Bernard the first verion diff --git a/bsp/imx6ul/drivers/serial.h b/bsp/imx6ul/drivers/serial.h index 00d464bde0..862ba65ef7 100644 --- a/bsp/imx6ul/drivers/serial.h +++ b/bsp/imx6ul/drivers/serial.h @@ -1,7 +1,8 @@ /* * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd - * + * * SPDX-License-Identifier: Apache-2.0 + * * Change Logs: * Date Author Notes * 2013-03-30 Bernard the first verion diff --git a/bsp/imxrt/libraries/drivers/drv_lcd.c b/bsp/imxrt/libraries/drivers/drv_lcd.c index 3d2ca8a055..f386e082cc 100644 --- a/bsp/imxrt/libraries/drivers/drv_lcd.c +++ b/bsp/imxrt/libraries/drivers/drv_lcd.c @@ -1,18 +1,14 @@ /* - * File : drv_lcd.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2013, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2017-10-30 Tanek the first version * 2018-04-05 Liu2guang export LCD config parameters. */ - + #include #ifdef BSP_USING_LCD diff --git a/bsp/imxrt/libraries/drivers/drv_lcd.h b/bsp/imxrt/libraries/drivers/drv_lcd.h index 8dd6ab9031..a67c8c3250 100644 --- a/bsp/imxrt/libraries/drivers/drv_lcd.h +++ b/bsp/imxrt/libraries/drivers/drv_lcd.h @@ -1,11 +1,7 @@ /* - * File : drv_lcd2.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2013, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc43xx/M0/applications/vbus_drv.c b/bsp/lpc43xx/M0/applications/vbus_drv.c index 8d90d72bfb..43b4b22aee 100644 --- a/bsp/lpc43xx/M0/applications/vbus_drv.c +++ b/bsp/lpc43xx/M0/applications/vbus_drv.c @@ -2,6 +2,7 @@ * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 + * * Change Logs: * Date Author Notes * 2015-01-07 Grissiom add comment diff --git a/bsp/lpc43xx/M0/applications/vbus_hw.h b/bsp/lpc43xx/M0/applications/vbus_hw.h index d269a7c907..0466d2339c 100644 --- a/bsp/lpc43xx/M0/applications/vbus_hw.h +++ b/bsp/lpc43xx/M0/applications/vbus_hw.h @@ -2,6 +2,7 @@ * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 + * * Change Logs: * Date Author Notes * 2015-01-07 Grissiom init commit diff --git a/bsp/lpc43xx/M4/applications/vbus_drv.c b/bsp/lpc43xx/M4/applications/vbus_drv.c index 4a3ee9dda6..c2f41881a9 100644 --- a/bsp/lpc43xx/M4/applications/vbus_drv.c +++ b/bsp/lpc43xx/M4/applications/vbus_drv.c @@ -2,6 +2,7 @@ * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 + * * Change Logs: * Date Author Notes * 2015-01-07 Grissiom add comment diff --git a/bsp/lpc43xx/M4/applications/vbus_hw.h b/bsp/lpc43xx/M4/applications/vbus_hw.h index d269a7c907..0466d2339c 100644 --- a/bsp/lpc43xx/M4/applications/vbus_hw.h +++ b/bsp/lpc43xx/M4/applications/vbus_hw.h @@ -2,6 +2,7 @@ * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 + * * Change Logs: * Date Author Notes * 2015-01-07 Grissiom init commit diff --git a/bsp/ls1bdev/drivers/board.c b/bsp/ls1bdev/drivers/board.c index 8a42f8e3a0..0933568526 100644 --- a/bsp/ls1bdev/drivers/board.c +++ b/bsp/ls1bdev/drivers/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2012, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -33,7 +29,7 @@ extern unsigned char __bss_end; /** * @addtogroup Loongson LS1B */ - + /*@{*/ /** @@ -43,10 +39,10 @@ void rt_hw_board_init(void) { /* init hardware interrupt */ rt_hw_exception_init(); - + /* init hardware interrupt */ rt_hw_interrupt_init(); - + #ifdef RT_USING_HEAP rt_system_heap_init((void*)&__bss_end, (void*)RT_HW_HEAP_END); #endif diff --git a/bsp/ls1bdev/drivers/board.h b/bsp/ls1bdev/drivers/board.h index fbe2ed8f9c..7d7002892c 100644 --- a/bsp/ls1bdev/drivers/board.h +++ b/bsp/ls1bdev/drivers/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2012, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -19,7 +15,7 @@ void rt_hw_board_init(void); /* 64M SDRAM */ -#define RT_HW_HEAP_END (0x80000000 + RT_MEM_SIZE * 1024 * 1024) -#define CPU_HZ (125 * 1000000) +#define RT_HW_HEAP_END (0x80000000 + RT_MEM_SIZE * 1024 * 1024) +#define CPU_HZ (125 * 1000000) #endif diff --git a/bsp/ls1bdev/drivers/display_controller.c b/bsp/ls1bdev/drivers/display_controller.c index 060bd0a041..5dba114b69 100644 --- a/bsp/ls1bdev/drivers/display_controller.c +++ b/bsp/ls1bdev/drivers/display_controller.c @@ -1,11 +1,7 @@ /* - * File : display_controller.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2012, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -17,24 +13,24 @@ struct vga_struct vga_mode[] = { - {/*"640x480_70.00"*/ 28560, 640, 664, 728, 816, 480, 481, 484, 500, }, - {/*"640x640_60.00"*/ 33100, 640, 672, 736, 832, 640, 641, 644, 663, }, - {/*"640x768_60.00"*/ 39690, 640, 672, 736, 832, 768, 769, 772, 795, }, - {/*"640x800_60.00"*/ 42130, 640, 680, 744, 848, 800, 801, 804, 828, }, - {/*"800x480_70.00"*/ 35840, 800, 832, 912, 1024, 480, 481, 484, 500, }, - {/*"800x600_60.00"*/ 38220, 800, 832, 912, 1024, 600, 601, 604, 622, }, - {/*"800x640_60.00"*/ 40730, 800, 832, 912, 1024, 640, 641, 644, 663, }, - {/*"832x600_60.00"*/ 40010, 832, 864, 952, 1072, 600, 601, 604, 622, }, - {/*"832x608_60.00"*/ 40520, 832, 864, 952, 1072, 608, 609, 612, 630, }, - {/*"1024x480_60.00"*/ 38170, 1024, 1048, 1152, 1280, 480, 481, 484, 497, }, - {/*"1024x600_60.00"*/ 48960, 1024, 1064, 1168, 1312, 600, 601, 604, 622, }, - {/*"1024x640_60.00"*/ 52830, 1024, 1072, 1176, 1328, 640, 641, 644, 663, }, - {/*"1024x768_60.00"*/ 64110, 1024, 1080, 1184, 1344, 768, 769, 772, 795, }, - {/*"1152x764_60.00"*/ 71380, 1152, 1208, 1328, 1504, 764, 765, 768, 791, }, - {/*"1280x800_60.00"*/ 83460, 1280, 1344, 1480, 1680, 800, 801, 804, 828, }, - {/*"1280x1024_55.00"*/ 98600, 1280, 1352, 1488, 1696, 1024, 1025, 1028, 1057, }, - {/*"1440x800_60.00"*/ 93800, 1440, 1512, 1664, 1888, 800, 801, 804, 828, }, - {/*"1440x900_67.00"*/ 120280, 1440, 1528, 1680, 1920, 900, 901, 904, 935, }, + {/*"640x480_70.00"*/ 28560, 640, 664, 728, 816, 480, 481, 484, 500, }, + {/*"640x640_60.00"*/ 33100, 640, 672, 736, 832, 640, 641, 644, 663, }, + {/*"640x768_60.00"*/ 39690, 640, 672, 736, 832, 768, 769, 772, 795, }, + {/*"640x800_60.00"*/ 42130, 640, 680, 744, 848, 800, 801, 804, 828, }, + {/*"800x480_70.00"*/ 35840, 800, 832, 912, 1024, 480, 481, 484, 500, }, + {/*"800x600_60.00"*/ 38220, 800, 832, 912, 1024, 600, 601, 604, 622, }, + {/*"800x640_60.00"*/ 40730, 800, 832, 912, 1024, 640, 641, 644, 663, }, + {/*"832x600_60.00"*/ 40010, 832, 864, 952, 1072, 600, 601, 604, 622, }, + {/*"832x608_60.00"*/ 40520, 832, 864, 952, 1072, 608, 609, 612, 630, }, + {/*"1024x480_60.00"*/ 38170, 1024, 1048, 1152, 1280, 480, 481, 484, 497, }, + {/*"1024x600_60.00"*/ 48960, 1024, 1064, 1168, 1312, 600, 601, 604, 622, }, + {/*"1024x640_60.00"*/ 52830, 1024, 1072, 1176, 1328, 640, 641, 644, 663, }, + {/*"1024x768_60.00"*/ 64110, 1024, 1080, 1184, 1344, 768, 769, 772, 795, }, + {/*"1152x764_60.00"*/ 71380, 1152, 1208, 1328, 1504, 764, 765, 768, 791, }, + {/*"1280x800_60.00"*/ 83460, 1280, 1344, 1480, 1680, 800, 801, 804, 828, }, + {/*"1280x1024_55.00"*/ 98600, 1280, 1352, 1488, 1696, 1024, 1025, 1028, 1057, }, + {/*"1440x800_60.00"*/ 93800, 1440, 1512, 1664, 1888, 800, 801, 804, 828, }, + {/*"1440x900_67.00"*/ 120280, 1440, 1528, 1680, 1920, 900, 901, 904, 935, }, }; ALIGN(16) @@ -46,189 +42,189 @@ static struct rt_device_graphic_info _dc_info; int caclulate_freq(long long XIN, long long PCLK) { - int i; - long long clk, clk1; - int start, end; - int mi; - int pll,ctrl,div,div1,frac; + int i; + long long clk, clk1; + int start, end; + int mi; + int pll,ctrl,div,div1,frac; - pll = PLL_FREQ; - ctrl = PLL_DIV_PARAM; - rt_kprintf("pll=0x%x, ctrl=0x%x\n", pll, ctrl); -// rt_kprintf("cpu freq is %d\n", tgt_pipefreq()); - start = -1; - end = 1; + pll = PLL_FREQ; + ctrl = PLL_DIV_PARAM; + rt_kprintf("pll=0x%x, ctrl=0x%x\n", pll, ctrl); +// rt_kprintf("cpu freq is %d\n", tgt_pipefreq()); + start = -1; + end = 1; - for (i=start; i<=end; i++) - { - clk = (12+i+(pll&0x3f))*33333333/2; - div = clk/(long)PCLK/1000; - clk1 = (12+i+1+(pll&0x3f))*33333333/2; - div1 = clk1/(long)PCLK/1000; - if (div!=div1) - break; - } + for (i=start; i<=end; i++) + { + clk = (12+i+(pll&0x3f))*33333333/2; + div = clk/(long)PCLK/1000; + clk1 = (12+i+1+(pll&0x3f))*33333333/2; + div1 = clk1/(long)PCLK/1000; + if (div!=div1) + break; + } - if (div!=div1) - { - frac = ((PCLK*1000*div1)*2*1024/33333333 - (12+i+(pll&0x3f))*1024)&0x3ff; - pll = (pll & ~0x3ff3f)|(frac<<8)|((pll&0x3f)+i); - ctrl = ctrl&~(0x1f<<26)|(div1<<26)|(1<<31); - } - else - { - clk = (12+start+(pll&0x3f))*33333333/2; - clk1 = (12+end+(pll&0x3f))*33333333/2; - if (abs((long)clk/div/1000-PCLK)type = RT_Device_Class_Graphic; - dc->init = rt_dc_init; - dc->open = RT_NULL; - dc->close = RT_NULL; - dc->control = rt_dc_control; - dc->user_data = (void*)&_dc_info; - - /* register Display Controller device to RT-Thread */ - rt_device_register(dc, "dc", RT_DEVICE_FLAG_RDWR); + /* init device structure */ + dc->type = RT_Device_Class_Graphic; + dc->init = rt_dc_init; + dc->open = RT_NULL; + dc->close = RT_NULL; + dc->control = rt_dc_control; + dc->user_data = (void*)&_dc_info; + + /* register Display Controller device to RT-Thread */ + rt_device_register(dc, "dc", RT_DEVICE_FLAG_RDWR); } diff --git a/bsp/ls1bdev/drivers/display_controller.h b/bsp/ls1bdev/drivers/display_controller.h index 5554eb1c2e..1fa6243a72 100644 --- a/bsp/ls1bdev/drivers/display_controller.h +++ b/bsp/ls1bdev/drivers/display_controller.h @@ -1,58 +1,54 @@ /* - * File : display_controller.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2012, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2011-08-08 lgnq first version for LS1B */ - + #ifndef __DISPLAY_CONTROLLER_H__ #define __DISPLAY_CONTROLLER_H__ #include #include "ls1b.h" -#define DC_BASE 0xBC301240 //Display Controller +#define DC_BASE 0xBC301240 //Display Controller /* Frame Buffer registers */ -#define DC_FB_CONFIG __REG32(DC_BASE + 0x000) -#define DC_FB_BUFFER_ADDR0 __REG32(DC_BASE + 0x020) -#define DC_FB_BUFFER_STRIDE __REG32(DC_BASE + 0x040) -#define DC_FB_BUFFER_ORIGIN __REG32(DC_BASE + 0x060) -#define DC_DITHER_CONFIG __REG32(DC_BASE + 0x120) -#define DC_DITHER_TABLE_LOW __REG32(DC_BASE + 0x140) -#define DC_DITHER_TABLE_HIGH __REG32(DC_BASE + 0x160) -#define DC_PANEL_CONFIG __REG32(DC_BASE + 0x180) -#define DC_PANEL_TIMING __REG32(DC_BASE + 0x1A0) -#define DC_HDISPLAY __REG32(DC_BASE + 0x1C0) -#define DC_HSYNC __REG32(DC_BASE + 0x1E0) -#define DC_VDISPLAY __REG32(DC_BASE + 0x240) -#define DC_VSYNC __REG32(DC_BASE + 0x260) -#define DC_FB_BUFFER_ADDR1 __REG32(DC_BASE + 0x340) +#define DC_FB_CONFIG __REG32(DC_BASE + 0x000) +#define DC_FB_BUFFER_ADDR0 __REG32(DC_BASE + 0x020) +#define DC_FB_BUFFER_STRIDE __REG32(DC_BASE + 0x040) +#define DC_FB_BUFFER_ORIGIN __REG32(DC_BASE + 0x060) +#define DC_DITHER_CONFIG __REG32(DC_BASE + 0x120) +#define DC_DITHER_TABLE_LOW __REG32(DC_BASE + 0x140) +#define DC_DITHER_TABLE_HIGH __REG32(DC_BASE + 0x160) +#define DC_PANEL_CONFIG __REG32(DC_BASE + 0x180) +#define DC_PANEL_TIMING __REG32(DC_BASE + 0x1A0) +#define DC_HDISPLAY __REG32(DC_BASE + 0x1C0) +#define DC_HSYNC __REG32(DC_BASE + 0x1E0) +#define DC_VDISPLAY __REG32(DC_BASE + 0x240) +#define DC_VSYNC __REG32(DC_BASE + 0x260) +#define DC_FB_BUFFER_ADDR1 __REG32(DC_BASE + 0x340) /* Display Controller driver for 1024x768 16bit */ -#define FB_XSIZE 1024 -#define FB_YSIZE 768 +#define FB_XSIZE 1024 +#define FB_YSIZE 768 #define CONFIG_VIDEO_16BPP #define APB_CLK 33333333 -#define K1BASE 0xA0000000 -#define KSEG1(addr) ((void *)(K1BASE | (rt_uint32_t)(addr))) -#define HW_FB_ADDR KSEG1(_rt_framebuffer) -#define HW_FB_PIXEL(x, y) *(volatile rt_uint16_t*)((rt_uint8_t*)HW_FB_ADDR + (y * FB_XSIZE * 2) + x * 2) +#define K1BASE 0xA0000000 +#define KSEG1(addr) ((void *)(K1BASE | (rt_uint32_t)(addr))) +#define HW_FB_ADDR KSEG1(_rt_framebuffer) +#define HW_FB_PIXEL(x, y) *(volatile rt_uint16_t*)((rt_uint8_t*)HW_FB_ADDR + (y * FB_XSIZE * 2) + x * 2) struct vga_struct { - long pclk; - int hr,hss,hse,hfl; - int vr,vss,vse,vfl; + long pclk; + int hr,hss,hse,hfl; + int vr,vss,vse,vfl; }; #endif diff --git a/bsp/ls1bdev/ls1b_ram.lds b/bsp/ls1bdev/ls1b_ram.lds index 872df8ad76..a3419501c0 100644 --- a/bsp/ls1bdev/ls1b_ram.lds +++ b/bsp/ls1bdev/ls1b_ram.lds @@ -1,11 +1,7 @@ /* - * File : ls1b_ram.lds - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -21,25 +17,25 @@ ENTRY(_start) SECTIONS { . = 0x80200000; - .text : + .text : { - start = ABSOLUTE(.); - *(.selfboot); - *(.selfboot_data); - . = ALIGN(4); - __selfboot_end = .; - . = ALIGN(0x1000); - __ebase_entry = .; - KEEP(*(.exc_vectors)) - __ebase_end = .; - *(.start); + start = ABSOLUTE(.); + *(.selfboot); + *(.selfboot_data); + . = ALIGN(4); + __selfboot_end = .; + . = ALIGN(0x1000); + __ebase_entry = .; + KEEP(*(.exc_vectors)) + __ebase_end = .; + *(.start); *(.text) *(.text.*) *(.rodata) *(.rodata.*) *(.rodata1) *(.rodata1.*) - + /* section information for finsh shell */ . = ALIGN(4); __fsymtab_start = .; @@ -57,26 +53,26 @@ SECTIONS __rt_init_end = .; . = ALIGN(4); } - - .eh_frame_hdr : - { - *(.eh_frame_hdr) + + .eh_frame_hdr : + { + *(.eh_frame_hdr) *(.eh_frame_entry) } .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } . = ALIGN(4); - .data : + .data : { *(.data) *(.data.*) - + *(.data1) *(.data1.*) - + . = ALIGN(8); _gp = ABSOLUTE(.); /* Base of small data */ - + *(.sdata) *(.sdata.*) } @@ -90,7 +86,7 @@ SECTIONS _system_stack = .; } - .sbss : + .sbss : { __bss_start = .; *(.sbss) diff --git a/bsp/ls1cdev/drivers/drv_spi.c b/bsp/ls1cdev/drivers/drv_spi.c index 3cc2212850..25b30e07ca 100644 --- a/bsp/ls1cdev/drivers/drv_spi.c +++ b/bsp/ls1cdev/drivers/drv_spi.c @@ -1,21 +1,7 @@ /* - * File : drv_spi.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/ls1cdev/ls1c_ram.lds b/bsp/ls1cdev/ls1c_ram.lds index 38aabfe012..aced32b90b 100644 --- a/bsp/ls1cdev/ls1c_ram.lds +++ b/bsp/ls1cdev/ls1c_ram.lds @@ -1,11 +1,7 @@ /* - * File : ls1c_ram.lds - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -22,25 +18,25 @@ ENTRY(_start) SECTIONS { . = ALIGN(4); - .text : + .text : { - start = ABSOLUTE(.); - *(.selfboot); - *(.selfboot_data); - . = ALIGN(4); - __selfboot_end = .; - . = ALIGN(0x1000); - __ebase_entry = .; - KEEP(*(.exc_vectors)) - __ebase_end = .; - *(.start); + start = ABSOLUTE(.); + *(.selfboot); + *(.selfboot_data); + . = ALIGN(4); + __selfboot_end = .; + . = ALIGN(0x1000); + __ebase_entry = .; + KEEP(*(.exc_vectors)) + __ebase_end = .; + *(.start); *(.text) *(.text.*) *(.rodata) *(.rodata.*) *(.rodata1) *(.rodata1.*) - + /* section information for finsh shell */ . = ALIGN(4); __fsymtab_start = .; @@ -58,26 +54,26 @@ SECTIONS __rt_init_end = .; . = ALIGN(4); } - - .eh_frame_hdr : - { - *(.eh_frame_hdr) + + .eh_frame_hdr : + { + *(.eh_frame_hdr) *(.eh_frame_entry) } .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } . = ALIGN(4); - .data : + .data : { *(.data) *(.data.*) - + *(.data1) *(.data1.*) - + . = ALIGN(8); _gp = ABSOLUTE(.); /* Base of small data */ - + *(.sdata) *(.sdata.*) } @@ -91,7 +87,7 @@ SECTIONS _system_stack = .; } - .sbss : + .sbss : { __bss_start = .; *(.sbss) diff --git a/bsp/m16c62p/applications/application.c b/bsp/m16c62p/applications/application.c index d345cfc425..35eb423193 100644 --- a/bsp/m16c62p/applications/application.c +++ b/bsp/m16c62p/applications/application.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -48,7 +44,7 @@ int rt_application_init(void) sizeof(led_stack), RT_THREAD_PRIORITY_MAX / 2, 32); - + if (result == RT_EOK) rt_thread_startup(&led); diff --git a/bsp/m16c62p/applications/startup.c b/bsp/m16c62p/applications/startup.c index 1802ecadee..149e530892 100644 --- a/bsp/m16c62p/applications/startup.c +++ b/bsp/m16c62p/applications/startup.c @@ -1,11 +1,7 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -40,61 +36,61 @@ extern unsigned char user_ram_end; */ void rtthread_startup(void) { - /* init hardware interrupt */ - rt_hw_interrupt_init(); - - /* init board */ - rt_hw_board_init(); + /* init hardware interrupt */ + rt_hw_interrupt_init(); + + /* init board */ + rt_hw_board_init(); + + /* show version */ + rt_show_version(); + + /* init timer system */ + rt_system_timer_init(); - /* show version */ - rt_show_version(); - - /* init timer system */ - rt_system_timer_init(); - #ifdef RT_USING_HEAP #ifdef __ICCM16C__ - rt_system_heap_init(__segment_begin("DATA16_HEAP"), __segment_end("DATA16_HEAP")); + rt_system_heap_init(__segment_begin("DATA16_HEAP"), __segment_end("DATA16_HEAP")); #elif (defined (__GNUC__)) - rt_system_heap_init((void*)&user_ram_end, (void*)M16C62P_SRAM_END); + rt_system_heap_init((void*)&user_ram_end, (void*)M16C62P_SRAM_END); #endif #endif - /* init scheduler system */ - rt_system_scheduler_init(); + /* init scheduler system */ + rt_system_scheduler_init(); - /* init application */ - rt_application_init(); + /* init application */ + rt_application_init(); #ifdef RT_USING_FINSH - /* init finsh */ - finsh_system_init(); - finsh_set_device("uart0"); + /* init finsh */ + finsh_system_init(); + finsh_set_device("uart0"); #endif - /* init timer thread */ - rt_system_timer_thread_init(); + /* init timer thread */ + rt_system_timer_thread_init(); - /* init idle thread */ - rt_thread_idle_init(); - - /* start scheduler */ - rt_system_scheduler_start(); - - /* never reach here */ - return ; + /* init idle thread */ + rt_thread_idle_init(); + + /* start scheduler */ + rt_system_scheduler_start(); + + /* never reach here */ + return ; } int main(void) { - /* disable interrupt first */ - rt_hw_interrupt_disable(); + /* disable interrupt first */ + rt_hw_interrupt_disable(); - /* init system setting */ - system_init(); - - /* startup RT-Thread RTOS */ - rtthread_startup(); + /* init system setting */ + system_init(); - return 0; + /* startup RT-Thread RTOS */ + rtthread_startup(); + + return 0; } diff --git a/bsp/m16c62p/drivers/board.c b/bsp/m16c62p/drivers/board.c index 69c581ffa7..9771e97fed 100644 --- a/bsp/m16c62p/drivers/board.c +++ b/bsp/m16c62p/drivers/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -27,8 +23,8 @@ void rt_hw_board_init(void) { #ifdef RT_USING_UART0 - rt_hw_uart_init(); - rt_console_set_device("uart0"); + rt_hw_uart_init(); + rt_console_set_device("uart0"); #endif rt_kprintf("\r\n\r\nSystemInit......\r\n"); diff --git a/bsp/m16c62p/drivers/board.h b/bsp/m16c62p/drivers/board.h index e3a4a604fe..05aa63832b 100644 --- a/bsp/m16c62p/drivers/board.h +++ b/bsp/m16c62p/drivers/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/m16c62p/drivers/bsp.c b/bsp/m16c62p/drivers/bsp.c index e03fa499e0..29732cb636 100644 --- a/bsp/m16c62p/drivers/bsp.c +++ b/bsp/m16c62p/drivers/bsp.c @@ -1,11 +1,7 @@ /* - * File : bsp.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -39,31 +35,31 @@ void led_off(void) static void mcu_init(void) { - volatile rt_uint32_t count; - /* Configure clock for divide by 1 mode */ - PRCR.BYTE |= 0x01; /* Enable access to clock registers PRCR.PRC0 = 1 */ - CM1.BYTE = 0x20; /* Set CM16, CM17 divide ratio to 1: */ - /* ... main clock on in high drive no PLL */ - CM0.BYTE &= ~0x40; /* Set divide ratio to 1 CM0.CM06 = 0 */ + volatile rt_uint32_t count; + /* Configure clock for divide by 1 mode */ + PRCR.BYTE |= 0x01; /* Enable access to clock registers PRCR.PRC0 = 1 */ + CM1.BYTE = 0x20; /* Set CM16, CM17 divide ratio to 1: */ + /* ... main clock on in high drive no PLL */ + CM0.BYTE &= ~0x40; /* Set divide ratio to 1 CM0.CM06 = 0 */ /* Configure main PLL */ - PRCR.BYTE |= 0x02; /* Allow writing to processor mode register PRCR.PRC0 = 1 */ - PM2.BYTE |= 0x01; /* Set SFR access to 2 wait, which is required for */ - /* ... operation greater than 16 MHz PM2.PM20 = 1 */ - PRCR.BYTE &= ~0x02; /* Protect processor mode register PRCR.PRC0 = 0 */ - PLC0.BYTE = 0x91; /* Enable and turn on PLL */ + PRCR.BYTE |= 0x02; /* Allow writing to processor mode register PRCR.PRC0 = 1 */ + PM2.BYTE |= 0x01; /* Set SFR access to 2 wait, which is required for */ + /* ... operation greater than 16 MHz PM2.PM20 = 1 */ + PRCR.BYTE &= ~0x02; /* Protect processor mode register PRCR.PRC0 = 0 */ + PLC0.BYTE = 0x91; /* Enable and turn on PLL */ count = 20000; /* Delay while PLL stabilizes */ - while (count > 0) { + while (count > 0) { count--; } CM1.BYTE |= 0x02; /* Switch to PLL CM1.CM11 = 1 */ PRCR.BYTE &= ~0x01; /* Protect clock control register PRCR.PRC0 = 0 */ - - PRCR.BYTE |= 0x02; /* Allow writing to processor mode register PRCR.PRC0 = 1 */ - PM1.BYTE |= 0x01; /* Enable data flash area PM1.PM10 = 1 */ - PRCR.BYTE &= ~0x02; /* Protect processor mode register PRCR.PRC0 = 0 */ + + PRCR.BYTE |= 0x02; /* Allow writing to processor mode register PRCR.PRC0 = 1 */ + PM1.BYTE |= 0x01; /* Enable data flash area PM1.PM10 = 1 */ + PRCR.BYTE &= ~0x02; /* Protect processor mode register PRCR.PRC0 = 0 */ } /* @@ -89,15 +85,15 @@ static void mcu_init(void) static void timer_tick_init(void) { - /* Set timer to timer mode */ + /* Set timer to timer mode */ /* Set count source as PLL clock / 8 (f8) */ - TB0MR.BYTE = 0x40; + TB0MR.BYTE = 0x40; /* Assign timer value and reload value */ - TB0 = (CPU_CLK_FREQ / 8) / RT_TICK_PER_SECOND; - /* Set timer B channel 0 interrupt level = 7 */ - /* Clear interrupt request */ + TB0 = (CPU_CLK_FREQ / 8) / RT_TICK_PER_SECOND; + /* Set timer B channel 0 interrupt level = 7 */ + /* Clear interrupt request */ TB0IC.BYTE = 0x07; - TABSR.BYTE |= 0x20; /* Start timer */ + TABSR.BYTE |= 0x20; /* Start timer */ } void system_init(void) diff --git a/bsp/m16c62p/drivers/bsp.h b/bsp/m16c62p/drivers/bsp.h index 9e353d6ecb..e77e0dc7fe 100644 --- a/bsp/m16c62p/drivers/bsp.h +++ b/bsp/m16c62p/drivers/bsp.h @@ -1,11 +1,7 @@ /* - * File : bsp.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/m16c62p/drivers/interrupts_gcc.S b/bsp/m16c62p/drivers/interrupts_gcc.S index 5c1f4cb1a8..03ff885b51 100644 --- a/bsp/m16c62p/drivers/interrupts_gcc.S +++ b/bsp/m16c62p/drivers/interrupts_gcc.S @@ -1,11 +1,7 @@ /* - * File : interrupt.s34 - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -15,23 +11,23 @@ * Toolchain : IAR's EW for M16C v3.401 */ - .text + .text - .globl _rt_hw_context_switch_interrupt_do - .type _rt_hw_context_switch_interrupt_do, #function + .globl _rt_hw_context_switch_interrupt_do + .type _rt_hw_context_switch_interrupt_do, #function _rt_hw_context_switch_interrupt_do: MOV.B #0, _rt_thread_switch_interrupt_flag MOV.W _rt_interrupt_from_thread, A0 STC ISP, [A0] - + MOV.W _rt_interrupt_to_thread, A0 LDC [A0], ISP POPM R0,R1,R2,R3,A0,A1,SB,FB ; Restore all processor registers from the new task's stack REIT - - .text - .globl _rt_hw_timer_handler - .type _rt_hw_timer_handler, #function + + .text + .globl _rt_hw_timer_handler + .type _rt_hw_timer_handler, #function _rt_hw_timer_handler: PUSHM R0,R1,R2,R3,A0,A1,SB,FB ; Save current task's registers jsr.a _rt_interrupt_enter @@ -40,22 +36,22 @@ _rt_hw_timer_handler: CMP.B #1, _rt_thread_switch_interrupt_flag JEQ _rt_hw_context_switch_interrupt_do - + POPM R0,R1,R2,R3,A0,A1,SB,FB ; Restore current task's registers REIT ; Return from interrup - .text - .globl _rt_hw_uart0_receive_handler - .type _rt_hw_uart0_receive_handler, #function + .text + .globl _rt_hw_uart0_receive_handler + .type _rt_hw_uart0_receive_handler, #function _rt_hw_uart0_receive_handler: PUSHM R0,R1,R2,R3,A0,A1,SB,FB ; Save current task's registers - jsr.a _rt_interrupt_enter + jsr.a _rt_interrupt_enter jsr.a _u0rec_handler jsr.a _rt_interrupt_leave CMP.B #1, _rt_thread_switch_interrupt_flag JEQ _rt_hw_context_switch_interrupt_do - + POPM R0,R1,R2,R3,A0,A1,SB,FB ; Restore current task's registers REIT ; Return from interrup diff --git a/bsp/m16c62p/drivers/interrupts_iar.asm b/bsp/m16c62p/drivers/interrupts_iar.asm index afaaae487f..5f2688e068 100644 --- a/bsp/m16c62p/drivers/interrupts_iar.asm +++ b/bsp/m16c62p/drivers/interrupts_iar.asm @@ -1,11 +1,7 @@ /* - * File : interrupt.s34 - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -17,7 +13,7 @@ PUBLIC rt_hw_timer_handler PUBLIC rt_hw_uart0_receive_handler - + EXTERN rt_thread_switch_interrupt_flag EXTERN rt_interrupt_from_thread EXTERN rt_interrupt_to_thread @@ -25,7 +21,7 @@ EXTERN rt_interrupt_leave EXTERN rt_tick_increase EXTERN u0rec_handler - + RSEG CSTACK RSEG ISTACK RSEG CODE:CODE:NOROOT(2) @@ -34,12 +30,12 @@ rt_hw_context_switch_interrupt_do MOV.B #0, rt_thread_switch_interrupt_flag MOV.W rt_interrupt_from_thread, A0 STC ISP, [A0] - + MOV.W rt_interrupt_to_thread, A0 LDC [A0], ISP POPM R0,R1,R2,R3,A0,A1,SB,FB ; Restore all processor registers from the new task's stack REIT - + .EVEN rt_hw_timer_handler: PUSHM R0,R1,R2,R3,A0,A1,SB,FB ; Save current task's registers @@ -49,20 +45,20 @@ rt_hw_timer_handler: CMP.B #1, rt_thread_switch_interrupt_flag JEQ rt_hw_context_switch_interrupt_do - + POPM R0,R1,R2,R3,A0,A1,SB,FB ; Restore current task's registers REIT ; Return from interrup .EVEN rt_hw_uart0_receive_handler: PUSHM R0,R1,R2,R3,A0,A1,SB,FB ; Save current task's registers - JSR rt_interrupt_enter + JSR rt_interrupt_enter JSR u0rec_handler JSR rt_interrupt_leave CMP.B #1, rt_thread_switch_interrupt_flag JEQ rt_hw_context_switch_interrupt_do - + POPM R0,R1,R2,R3,A0,A1,SB,FB ; Restore current task's registers REIT ; Return from interrup diff --git a/bsp/m16c62p/drivers/uart.c b/bsp/m16c62p/drivers/uart.c index 76cf038347..67f56b98a3 100644 --- a/bsp/m16c62p/drivers/uart.c +++ b/bsp/m16c62p/drivers/uart.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -23,44 +19,44 @@ struct rt_uart_m16c { - struct rt_device parent; + struct rt_device parent; - /* buffer for reception */ - rt_uint8_t read_index, save_index; - rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; + /* buffer for reception */ + rt_uint8_t read_index, save_index; + rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; }uart_device; void u0rec_handler(void) { - rt_ubase_t level; - rt_uint8_t c; + rt_ubase_t level; + rt_uint8_t c; - struct rt_uart_m16c *uart = &uart_device; + struct rt_uart_m16c *uart = &uart_device; - while (U0C1.BIT.RI == 0) - ; - c = U0RB.BYTE.U0RBL; + while (U0C1.BIT.RI == 0) + ; + c = U0RB.BYTE.U0RBL; - /* Receive Data Available */ + /* Receive Data Available */ uart->rx_buffer[uart->save_index] = c; level = rt_hw_interrupt_disable(); - uart->save_index ++; + uart->save_index ++; if (uart->save_index >= RT_UART_RX_BUFFER_SIZE) uart->save_index = 0; rt_hw_interrupt_enable(level); - /* invoke callback */ - if (uart->parent.rx_indicate != RT_NULL) - { - rt_size_t length; - if (uart->read_index > uart->save_index) + /* invoke callback */ + if (uart->parent.rx_indicate != RT_NULL) + { + rt_size_t length; + if (uart->read_index > uart->save_index) length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index; else length = uart->save_index - uart->read_index; uart->parent.rx_indicate(&uart->parent, length); - } + } } static rt_err_t rt_uart_init (rt_device_t dev) @@ -69,7 +65,7 @@ static rt_err_t rt_uart_init (rt_device_t dev) /* set UART0 bit rate generator bit rate can be calculated by: bit rate = ((BRG count source / 16)/baud rate) - 1 Baud rate is based on main crystal or PLL not CPU core clock */ - //pclk1 = 1; /// seleck F1SIO + //pclk1 = 1; /// seleck F1SIO U0BRG = (unsigned char)(((CPU_CLK_FREQ/16)/BAUD_RATE)-1); //(N+1) /* UART Transmit/Receive Control Register 2 */ @@ -143,144 +139,144 @@ static rt_err_t rt_uart_init (rt_device_t dev) b6 UOLCH Data logic select bit b7 UOERE Error signal output enable bit */ - return RT_EOK; + return RT_EOK; } static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag) { - RT_ASSERT(dev != RT_NULL); - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* Enable the UART Interrupt */ - } + RT_ASSERT(dev != RT_NULL); + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* Enable the UART Interrupt */ + } - return RT_EOK; + return RT_EOK; } static rt_err_t rt_uart_close(rt_device_t dev) { - RT_ASSERT(dev != RT_NULL); - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* Disable the UART Interrupt */ - } + RT_ASSERT(dev != RT_NULL); + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* Disable the UART Interrupt */ + } - return RT_EOK; + return RT_EOK; } static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_uint8_t *ptr; - struct rt_uart_m16c *uart = (struct rt_uart_m16c *)dev; - RT_ASSERT(uart != RT_NULL); + rt_uint8_t *ptr; + struct rt_uart_m16c *uart = (struct rt_uart_m16c *)dev; + RT_ASSERT(uart != RT_NULL); - /* point to buffer */ - ptr = (rt_uint8_t *)buffer; - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - while (size) - { - /* interrupt receive */ - rt_base_t level; + /* point to buffer */ + ptr = (rt_uint8_t *)buffer; + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + while (size) + { + /* interrupt receive */ + rt_base_t level; - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - if (uart->read_index != uart->save_index) - { - *ptr = uart->rx_buffer[uart->read_index]; + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + if (uart->read_index != uart->save_index) + { + *ptr = uart->rx_buffer[uart->read_index]; - uart->read_index ++; - if (uart->read_index >= RT_UART_RX_BUFFER_SIZE) - uart->read_index = 0; - } - else - { - /* no data in rx buffer */ + uart->read_index ++; + if (uart->read_index >= RT_UART_RX_BUFFER_SIZE) + uart->read_index = 0; + } + else + { + /* no data in rx buffer */ - /* enable interrupt */ - rt_hw_interrupt_enable(level); - break; - } + /* enable interrupt */ + rt_hw_interrupt_enable(level); + break; + } - /* enable interrupt */ - rt_hw_interrupt_enable(level); + /* enable interrupt */ + rt_hw_interrupt_enable(level); - ptr ++; - size --; - } + ptr ++; + size --; + } - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; - } + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + } - return 0; + return 0; } static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) { - char *ptr; - ptr = (char *)buffer; + char *ptr; + ptr = (char *)buffer; - if (dev->flag & RT_DEVICE_FLAG_STREAM) - { - /* stream mode */ - while (size) - { - if (*ptr == '\n') - { - while (U0C1.BIT.TI == 0) - ; - U0TB.BYTE.U0TBL = '\r'; - } + if (dev->flag & RT_DEVICE_FLAG_STREAM) + { + /* stream mode */ + while (size) + { + if (*ptr == '\n') + { + while (U0C1.BIT.TI == 0) + ; + U0TB.BYTE.U0TBL = '\r'; + } - /* THRE status, contain valid data */ - while (U0C1.BIT.TI == 0) - ; - U0TB.BYTE.U0TBL = *ptr; - - ptr ++; - size --; - } - } - else - { - while (size != 0) - { - /* THRE status, contain valid data */ - while (U0C1.BIT.TI == 0) - ; - U0TB.BYTE.U0TBL = *ptr; - - ptr ++; - size --; - } - } + /* THRE status, contain valid data */ + while (U0C1.BIT.TI == 0) + ; + U0TB.BYTE.U0TBL = *ptr; - return (rt_size_t)ptr - (rt_size_t)buffer; + ptr ++; + size --; + } + } + else + { + while (size != 0) + { + /* THRE status, contain valid data */ + while (U0C1.BIT.TI == 0) + ; + U0TB.BYTE.U0TBL = *ptr; + + ptr ++; + size --; + } + } + + return (rt_size_t)ptr - (rt_size_t)buffer; } void rt_hw_uart_init(void) { - struct rt_uart_m16c *uart; + struct rt_uart_m16c *uart; - /* get uart device */ - uart = &uart_device; + /* get uart device */ + uart = &uart_device; - /* device initialization */ - uart->parent.type = RT_Device_Class_Char; - rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer)); - uart->read_index = uart->save_index = 0; + /* device initialization */ + uart->parent.type = RT_Device_Class_Char; + rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer)); + uart->read_index = uart->save_index = 0; - /* device interface */ - uart->parent.init = rt_uart_init; - uart->parent.open = rt_uart_open; - uart->parent.close = rt_uart_close; - uart->parent.read = rt_uart_read; - uart->parent.write = rt_uart_write; - uart->parent.control = RT_NULL; - uart->parent.user_data = RT_NULL; + /* device interface */ + uart->parent.init = rt_uart_init; + uart->parent.open = rt_uart_open; + uart->parent.close = rt_uart_close; + uart->parent.read = rt_uart_read; + uart->parent.write = rt_uart_write; + uart->parent.control = RT_NULL; + uart->parent.user_data = RT_NULL; - rt_device_register(&uart->parent, - "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX); + rt_device_register(&uart->parent, + "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX); } #endif /* end of UART */ diff --git a/bsp/m16c62p/drivers/vectors_iar.asm b/bsp/m16c62p/drivers/vectors_iar.asm index a6ec8d5b7d..8a5ce3fb54 100644 --- a/bsp/m16c62p/drivers/vectors_iar.asm +++ b/bsp/m16c62p/drivers/vectors_iar.asm @@ -1,11 +1,7 @@ /* - * File : vectors.s34 - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -24,7 +20,7 @@ EXTERN rt_hw_timer_handler EXTERN rt_hw_uart0_receive_handler EXTERN os_context_switch - + PUBLIC RelocatableVectTbl RSEG INTVEC:NOROOT diff --git a/bsp/m16c62p/readme.txt b/bsp/m16c62p/readme.txt index 70059fd48b..95939c7bd9 100644 --- a/bsp/m16c62p/readme.txt +++ b/bsp/m16c62p/readme.txt @@ -1,17 +1,13 @@ /* - * File : readme.txt - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2011-02-17 lgnq the first version */ - + Summary: ======== This directory contains the source code for M16C porting to rt-thread @@ -23,7 +19,7 @@ finsh - a user shell, comes with rt-thread Where to get help: ================== In case you have questions about, problems with or contributions for -Renesas M16C prot to rt-thread, you can send a mail to dzzxzz@gmail.com. +Renesas M16C prot to rt-thread, you can send a mail to dzzxzz@gmail.com. or you can post a message to the rt-thread forum there are two forums: @@ -48,10 +44,10 @@ Directory Hierarchy: /startup.c - rt-thread start, include main() /drivers /board.c - hardware init, init uart0 - /board.h + /board.h /bsp.c - include led_init(), mcu_init(), timer0_init() /bsp.h - /uart.c - implement uart0 device + /uart.c - implement uart0 device /uart.h /start_iar.asm - assembly start of iar /interrupts_iar.asm - include time0 interrupt handler, uart0 interrupt handler @@ -75,7 +71,7 @@ Directory Hierarchy: /context_gcc.S - rt-thread context switch, used by SCONS + gcc /interrupt.c /stack.c - rt-thread stack initlization - + Build Project: ============== there are two ways to build the renesase M16C project: @@ -84,7 +80,7 @@ there are two ways to build the renesase M16C project: rebuild all the target file(rtt2m16c.mot) will be produced in /rt-thread/bsp/m16c62p/Debug/Exe you can download the rtt2m16c.mot to m16c board with E8A - + 2, install python, scons and IAR for m16c(recommend python2.7, scons1.3.1 and EWM16C-EV-3501.exe) open a windows cmd, and change directory to m16c project, like /rt-thread/bsp/m16c62p/ #set PATH=C:\Python27\Scripts;%PATH% diff --git a/bsp/mb9bf500r/CMSIS/start_gcc.S b/bsp/mb9bf500r/CMSIS/start_gcc.S index b1a93e52be..8789adb8f6 100644 --- a/bsp/mb9bf500r/CMSIS/start_gcc.S +++ b/bsp/mb9bf500r/CMSIS/start_gcc.S @@ -1,17 +1,13 @@ /* - * File : start_gcc.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2011-07-01 lgnq first version */ - + .syntax unified .cpu cortex-m3 .fpu softvfp @@ -20,10 +16,10 @@ .global g_pfnVectors .global Default_Handler -/* start address for the initialization values of the .data section. +/* start address for the initialization values of the .data section. defined in linker script */ .word _sidata -/* start address for the .data section. defined in linker script */ +/* start address for the .data section. defined in linker script */ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata @@ -38,7 +34,7 @@ defined in linker script */ * @brief This is the code that gets called when the processor first * starts execution following a reset event. Only the absolutely * necessary set is performed, after which the application - * supplied main() routine is called. + * supplied main() routine is called. * @param None * @retval : None */ @@ -46,11 +42,11 @@ defined in linker script */ .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function -Reset_Handler: -/* restore original stack pointer */ +Reset_Handler: +/* restore original stack pointer */ ldr sp, =_estack /* set stack pointer */ -/* Copy the data segment initializers from flash to SRAM */ +/* Copy the data segment initializers from flash to SRAM */ movs r1, #0 b LoopCopyDataInit @@ -59,7 +55,7 @@ CopyDataInit: ldr r3, [r3, r1] str r3, [r0, r1] adds r1, r1, #4 - + LoopCopyDataInit: ldr r0, =_sdata ldr r3, =_edata @@ -68,27 +64,27 @@ LoopCopyDataInit: bcc CopyDataInit ldr r2, =_sbss b LoopFillZerobss -/* Zero fill the bss segment. */ +/* Zero fill the bss segment. */ FillZerobss: movs r3, #0 str r3, [r2], #4 - + LoopFillZerobss: ldr r3, = _ebss cmp r2, r3 bcc FillZerobss /* Call the application's entry point.*/ bl main - bx lr + bx lr .size Reset_Handler, .-Reset_Handler /** - * @brief This is the code that gets called when the processor receives an + * @brief This is the code that gets called when the processor receives an * unexpected interrupt. This simply enters an infinite loop, preserving * the system state for examination by a debugger. * - * @param None - * @retval : None + * @param None + * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: @@ -101,7 +97,7 @@ Infinite_Loop: * must be placed on this to ensure that it ends up at physical address * 0x0000.0000. * -******************************************************************************/ +******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object .size g_pfnVectors, .-g_pfnVectors @@ -123,7 +119,7 @@ g_pfnVectors: .word 0 .word PendSV_Handler .word SysTick_Handler - + .word CSV_IRQHandler .word SWDT_IRQHandler .word LVD_IRQHandler @@ -171,25 +167,25 @@ g_pfnVectors: .word DMAC6_IRQHandler .word DMAC7_IRQHandler .word RESERVED_3_IRQHandler - .word RESERVED_4_IRQHandler - + .word RESERVED_4_IRQHandler + /******************************************************************************* * -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override * this definition. * *******************************************************************************/ - + .weak NMI_Handler .thumb_set NMI_Handler,Default_Handler .weak HardFault_Handler .thumb_set HardFault_Handler,Default_Handler - + .weak MemManage_Handler .thumb_set MemManage_Handler,Default_Handler - + .weak BusFault_Handler .thumb_set BusFault_Handler,Default_Handler @@ -204,10 +200,10 @@ g_pfnVectors: .weak PendSV_Handler .thumb_set PendSV_Handler,Default_Handler - + .weak SysTick_Handler .thumb_set SysTick_Handler,Default_Handler - + .weak CSV_IRQHandler .thumb_set CSV_IRQHandler,Default_Handler @@ -351,4 +347,4 @@ g_pfnVectors: .weak RESERVED_4_IRQHandler .thumb_set RESERVED_4_IRQHandler,Default_Handler - + diff --git a/bsp/mb9bf500r/CMSIS/start_iar.S b/bsp/mb9bf500r/CMSIS/start_iar.S index 1daaffc49a..e60f066822 100644 --- a/bsp/mb9bf500r/CMSIS/start_iar.S +++ b/bsp/mb9bf500r/CMSIS/start_iar.S @@ -1,11 +1,7 @@ ;/* -; * File : context_iar.S -; * This file is part of RT-Thread RTOS -; * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team +; * Copyright (c) 2006-2021, RT-Thread Development Team ; * -; * The license and distribution terms for this file may be -; * found in the file LICENSE in this distribution or at -; * http://www.rt-thread.org/license/LICENSE +; * SPDX-License-Identifier: Apache-2.0 ; * ; * Change Logs: ; * Date Author Notes @@ -15,349 +11,349 @@ #include "rtconfig.h" - MODULE ?cstartup + MODULE ?cstartup ;; ICODE is the same segment as cstartup. By placing __low_level_init ;; in the same segment, we make sure it can be reached with BL. */ - SECTION CSTACK:DATA:NOROOT(3) - SECTION .icode:CODE:NOROOT(2) + SECTION CSTACK:DATA:NOROOT(3) + SECTION .icode:CODE:NOROOT(2) -#ifdef RT_USING_UART2 - IMPORT MFS2RX_IRQHandler +#ifdef RT_USING_UART2 + IMPORT MFS2RX_IRQHandler #endif - PUBLIC __low_level_init + PUBLIC __low_level_init - PUBWEAK SystemInit_ExtMemCtl - SECTION .text:CODE:REORDER(2) - THUMB + PUBWEAK SystemInit_ExtMemCtl + SECTION .text:CODE:REORDER(2) + THUMB SystemInit_ExtMemCtl - BX LR + BX LR __low_level_init: - ;; Initialize hardware. - LDR R0, = SystemInit_ExtMemCtl ; initialize external memory controller - MOV R11, LR - BLX R0 - LDR R1, =sfe(CSTACK) ; restore original stack pointer - MSR MSP, R1 - MOV R0,#1 - ;; Return with BX to be independent of mode of caller - BX R11 + ;; Initialize hardware. + LDR R0, = SystemInit_ExtMemCtl ; initialize external memory controller + MOV R11, LR + BLX R0 + LDR R1, =sfe(CSTACK) ; restore original stack pointer + MSR MSP, R1 + MOV R0,#1 + ;; Return with BX to be independent of mode of caller + BX R11 - ;; Forward declaration of sections. - SECTION .intvec:CODE:NOROOT(2) + ;; Forward declaration of sections. + SECTION .intvec:CODE:NOROOT(2) - EXTERN __iar_program_start - PUBLIC __vector_table + EXTERN __iar_program_start + PUBLIC __vector_table - DATA + DATA __vector_table - DCD sfe(CSTACK) - DCD __iar_program_start - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD CSV_IRQHandler ; Clock Super Visor - DCD SWDT_IRQHandler ; Software Watchdog Timer - DCD LVD_IRQHandler ; Low Voltage Detector - DCD WFG_IRQHandler ; Wave Form Generator - DCD EXINT0_7_IRQHandler ; External Interrupt Request ch.0 to ch.7 - DCD EXINT8_15_IRQHandler ; External Interrupt Request ch.8 to ch.15 - DCD DTIM_QDU_IRQHandler ; Dual Timer / Quad Decoder - DCD MFS0RX_IRQHandler ; MultiFunction Serial ch.0 - DCD MFS0TX_IRQHandler ; MultiFunction Serial ch.0 - DCD MFS1RX_IRQHandler ; MultiFunction Serial ch.1 - DCD MFS1TX_IRQHandler ; MultiFunction Serial ch.1 -#ifdef RT_USING_UART2 - DCD MFS2RX_IRQHandler ; MultiFunction Serial ch.2 + DCD sfe(CSTACK) + DCD __iar_program_start + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD CSV_IRQHandler ; Clock Super Visor + DCD SWDT_IRQHandler ; Software Watchdog Timer + DCD LVD_IRQHandler ; Low Voltage Detector + DCD WFG_IRQHandler ; Wave Form Generator + DCD EXINT0_7_IRQHandler ; External Interrupt Request ch.0 to ch.7 + DCD EXINT8_15_IRQHandler ; External Interrupt Request ch.8 to ch.15 + DCD DTIM_QDU_IRQHandler ; Dual Timer / Quad Decoder + DCD MFS0RX_IRQHandler ; MultiFunction Serial ch.0 + DCD MFS0TX_IRQHandler ; MultiFunction Serial ch.0 + DCD MFS1RX_IRQHandler ; MultiFunction Serial ch.1 + DCD MFS1TX_IRQHandler ; MultiFunction Serial ch.1 +#ifdef RT_USING_UART2 + DCD MFS2RX_IRQHandler ; MultiFunction Serial ch.2 #else - DCD NULL_IRQHandler ; MultiFunction Serial ch.2 + DCD NULL_IRQHandler ; MultiFunction Serial ch.2 #endif - DCD MFS2TX_IRQHandler ; MultiFunction Serial ch.2 - DCD MFS3RX_IRQHandler ; MultiFunction Serial ch.3 - DCD MFS3TX_IRQHandler ; MultiFunction Serial ch.3 - DCD MFS4RX_IRQHandler ; MultiFunction Serial ch.4 - DCD MFS4TX_IRQHandler ; MultiFunction Serial ch.4 - DCD MFS5RX_IRQHandler ; MultiFunction Serial ch.5 - DCD MFS5TX_IRQHandler ; MultiFunction Serial ch.5 - DCD MFS6RX_IRQHandler ; MultiFunction Serial ch.6 - DCD MFS6TX_IRQHandler ; MultiFunction Serial ch.6 - DCD MFS7RX_IRQHandler ; MultiFunction Serial ch.7 - DCD MFS7TX_IRQHandler ; MultiFunction Serial ch.7 - DCD PPG_IRQHandler ; PPG - DCD OSC_PLL_WC_IRQHandler ; OSC / PLL / Watch Counter - DCD ADC0_IRQHandler ; ADC0 - DCD ADC1_IRQHandler ; ADC1 - DCD ADC2_IRQHandler ; ADC2 - DCD FRTIM_IRQHandler ; Free-run Timer - DCD INCAP_IRQHandler ; Input Capture - DCD OUTCOMP_IRQHandler ; Output Compare - DCD BTIM_IRQHandler ; Base Timer ch.0 to ch.7 - DCD CAN0_IRQHandler ; CAN ch.0 - DCD CAN1_IRQHandler ; CAN ch.1 - DCD USBF_IRQHandler ; USB Function - DCD USBF_USBH_IRQHandler ; USB Function / USB HOST - DCD RESERVED_1_IRQHandler ; Reserved_1 - DCD RESERVED_2_IRQHandler ; Reserved_2 - DCD DMAC0_IRQHandler ; DMAC ch.0 - DCD DMAC1_IRQHandler ; DMAC ch.1 - DCD DMAC2_IRQHandler ; DMAC ch.2 - DCD DMAC3_IRQHandler ; DMAC ch.3 - DCD DMAC4_IRQHandler ; DMAC ch.4 - DCD DMAC5_IRQHandler ; DMAC ch.5 - DCD DMAC6_IRQHandler ; DMAC ch.6 - DCD DMAC7_IRQHandler ; DMAC ch.7 - DCD RESERVED_3_IRQHandler ; Reserved_3 - DCD RESERVED_4_IRQHandler ; Reserved_4 + DCD MFS2TX_IRQHandler ; MultiFunction Serial ch.2 + DCD MFS3RX_IRQHandler ; MultiFunction Serial ch.3 + DCD MFS3TX_IRQHandler ; MultiFunction Serial ch.3 + DCD MFS4RX_IRQHandler ; MultiFunction Serial ch.4 + DCD MFS4TX_IRQHandler ; MultiFunction Serial ch.4 + DCD MFS5RX_IRQHandler ; MultiFunction Serial ch.5 + DCD MFS5TX_IRQHandler ; MultiFunction Serial ch.5 + DCD MFS6RX_IRQHandler ; MultiFunction Serial ch.6 + DCD MFS6TX_IRQHandler ; MultiFunction Serial ch.6 + DCD MFS7RX_IRQHandler ; MultiFunction Serial ch.7 + DCD MFS7TX_IRQHandler ; MultiFunction Serial ch.7 + DCD PPG_IRQHandler ; PPG + DCD OSC_PLL_WC_IRQHandler ; OSC / PLL / Watch Counter + DCD ADC0_IRQHandler ; ADC0 + DCD ADC1_IRQHandler ; ADC1 + DCD ADC2_IRQHandler ; ADC2 + DCD FRTIM_IRQHandler ; Free-run Timer + DCD INCAP_IRQHandler ; Input Capture + DCD OUTCOMP_IRQHandler ; Output Compare + DCD BTIM_IRQHandler ; Base Timer ch.0 to ch.7 + DCD CAN0_IRQHandler ; CAN ch.0 + DCD CAN1_IRQHandler ; CAN ch.1 + DCD USBF_IRQHandler ; USB Function + DCD USBF_USBH_IRQHandler ; USB Function / USB HOST + DCD RESERVED_1_IRQHandler ; Reserved_1 + DCD RESERVED_2_IRQHandler ; Reserved_2 + DCD DMAC0_IRQHandler ; DMAC ch.0 + DCD DMAC1_IRQHandler ; DMAC ch.1 + DCD DMAC2_IRQHandler ; DMAC ch.2 + DCD DMAC3_IRQHandler ; DMAC ch.3 + DCD DMAC4_IRQHandler ; DMAC ch.4 + DCD DMAC5_IRQHandler ; DMAC ch.5 + DCD DMAC6_IRQHandler ; DMAC ch.6 + DCD DMAC7_IRQHandler ; DMAC ch.7 + DCD RESERVED_3_IRQHandler ; Reserved_3 + DCD RESERVED_4_IRQHandler ; Reserved_4 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Default interrupt handlers. ;; - THUMB + THUMB - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER(1) + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) NMI_Handler - B NMI_Handler - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER(1) + B NMI_Handler + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) HardFault_Handler - B HardFault_Handler - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER(1) + B HardFault_Handler + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) MemManage_Handler - B MemManage_Handler - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER(1) + B MemManage_Handler + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) BusFault_Handler - B BusFault_Handler - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER(1) + B BusFault_Handler + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) UsageFault_Handler - B UsageFault_Handler - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER(1) + B UsageFault_Handler + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) SVC_Handler - B SVC_Handler - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER(1) + B SVC_Handler + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) DebugMon_Handler - B DebugMon_Handler - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER(1) + B DebugMon_Handler + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) PendSV_Handler - B PendSV_Handler - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER(1) + B PendSV_Handler + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) SysTick_Handler - B SysTick_Handler - PUBWEAK CSV_IRQHandler - SECTION .text:CODE:REORDER(1) + B SysTick_Handler + PUBWEAK CSV_IRQHandler + SECTION .text:CODE:REORDER(1) CSV_IRQHandler - B CSV_IRQHandler - PUBWEAK SWDT_IRQHandler - SECTION .text:CODE:REORDER(1) + B CSV_IRQHandler + PUBWEAK SWDT_IRQHandler + SECTION .text:CODE:REORDER(1) SWDT_IRQHandler - B SWDT_IRQHandler - PUBWEAK LVD_IRQHandler - SECTION .text:CODE:REORDER(1) + B SWDT_IRQHandler + PUBWEAK LVD_IRQHandler + SECTION .text:CODE:REORDER(1) LVD_IRQHandler - B LVD_IRQHandler - PUBWEAK WFG_IRQHandler - SECTION .text:CODE:REORDER(1) + B LVD_IRQHandler + PUBWEAK WFG_IRQHandler + SECTION .text:CODE:REORDER(1) WFG_IRQHandler - B WFG_IRQHandler - PUBWEAK EXINT0_7_IRQHandler - SECTION .text:CODE:REORDER(1) + B WFG_IRQHandler + PUBWEAK EXINT0_7_IRQHandler + SECTION .text:CODE:REORDER(1) EXINT0_7_IRQHandler - B EXINT0_7_IRQHandler - PUBWEAK EXINT8_15_IRQHandler - SECTION .text:CODE:REORDER(1) + B EXINT0_7_IRQHandler + PUBWEAK EXINT8_15_IRQHandler + SECTION .text:CODE:REORDER(1) EXINT8_15_IRQHandler - B EXINT8_15_IRQHandler - PUBWEAK DTIM_QDU_IRQHandler - SECTION .text:CODE:REORDER(1) + B EXINT8_15_IRQHandler + PUBWEAK DTIM_QDU_IRQHandler + SECTION .text:CODE:REORDER(1) DTIM_QDU_IRQHandler - B DTIM_QDU_IRQHandler - PUBWEAK MFS0RX_IRQHandler - SECTION .text:CODE:REORDER(1) + B DTIM_QDU_IRQHandler + PUBWEAK MFS0RX_IRQHandler + SECTION .text:CODE:REORDER(1) MFS0RX_IRQHandler - B MFS0RX_IRQHandler - PUBWEAK MFS0TX_IRQHandler - SECTION .text:CODE:REORDER(1) + B MFS0RX_IRQHandler + PUBWEAK MFS0TX_IRQHandler + SECTION .text:CODE:REORDER(1) MFS0TX_IRQHandler - B MFS0TX_IRQHandler - PUBWEAK MFS1RX_IRQHandler - SECTION .text:CODE:REORDER(1) + B MFS0TX_IRQHandler + PUBWEAK MFS1RX_IRQHandler + SECTION .text:CODE:REORDER(1) MFS1RX_IRQHandler - B MFS1RX_IRQHandler - PUBWEAK MFS1TX_IRQHandler - SECTION .text:CODE:REORDER(1) + B MFS1RX_IRQHandler + PUBWEAK MFS1TX_IRQHandler + SECTION .text:CODE:REORDER(1) MFS1TX_IRQHandler - B MFS1TX_IRQHandler - PUBWEAK NULL_IRQHandler - SECTION .text:CODE:REORDER(1) + B MFS1TX_IRQHandler + PUBWEAK NULL_IRQHandler + SECTION .text:CODE:REORDER(1) NULL_IRQHandler - B NULL_IRQHandler - PUBWEAK MFS2TX_IRQHandler - SECTION .text:CODE:REORDER(1) + B NULL_IRQHandler + PUBWEAK MFS2TX_IRQHandler + SECTION .text:CODE:REORDER(1) MFS2TX_IRQHandler - B MFS2TX_IRQHandler - PUBWEAK MFS3RX_IRQHandler - SECTION .text:CODE:REORDER(1) + B MFS2TX_IRQHandler + PUBWEAK MFS3RX_IRQHandler + SECTION .text:CODE:REORDER(1) MFS3RX_IRQHandler - B MFS3RX_IRQHandler - PUBWEAK MFS3TX_IRQHandler - SECTION .text:CODE:REORDER(1) + B MFS3RX_IRQHandler + PUBWEAK MFS3TX_IRQHandler + SECTION .text:CODE:REORDER(1) MFS3TX_IRQHandler - B MFS3TX_IRQHandler - PUBWEAK MFS4RX_IRQHandler - SECTION .text:CODE:REORDER(1) + B MFS3TX_IRQHandler + PUBWEAK MFS4RX_IRQHandler + SECTION .text:CODE:REORDER(1) MFS4RX_IRQHandler - B MFS4RX_IRQHandler - PUBWEAK MFS4TX_IRQHandler - SECTION .text:CODE:REORDER(1) + B MFS4RX_IRQHandler + PUBWEAK MFS4TX_IRQHandler + SECTION .text:CODE:REORDER(1) MFS4TX_IRQHandler - B MFS4TX_IRQHandler - PUBWEAK MFS5RX_IRQHandler - SECTION .text:CODE:REORDER(1) + B MFS4TX_IRQHandler + PUBWEAK MFS5RX_IRQHandler + SECTION .text:CODE:REORDER(1) MFS5RX_IRQHandler - B MFS5RX_IRQHandler - PUBWEAK MFS5TX_IRQHandler - SECTION .text:CODE:REORDER(1) + B MFS5RX_IRQHandler + PUBWEAK MFS5TX_IRQHandler + SECTION .text:CODE:REORDER(1) MFS5TX_IRQHandler - B MFS5TX_IRQHandler - PUBWEAK MFS6RX_IRQHandler - SECTION .text:CODE:REORDER(1) + B MFS5TX_IRQHandler + PUBWEAK MFS6RX_IRQHandler + SECTION .text:CODE:REORDER(1) MFS6RX_IRQHandler - B MFS6RX_IRQHandler - PUBWEAK MFS6TX_IRQHandler - SECTION .text:CODE:REORDER(1) + B MFS6RX_IRQHandler + PUBWEAK MFS6TX_IRQHandler + SECTION .text:CODE:REORDER(1) MFS6TX_IRQHandler - B MFS6TX_IRQHandler - PUBWEAK MFS7RX_IRQHandler - SECTION .text:CODE:REORDER(1) + B MFS6TX_IRQHandler + PUBWEAK MFS7RX_IRQHandler + SECTION .text:CODE:REORDER(1) MFS7RX_IRQHandler - B MFS7RX_IRQHandler - PUBWEAK MFS7TX_IRQHandler - SECTION .text:CODE:REORDER(1) + B MFS7RX_IRQHandler + PUBWEAK MFS7TX_IRQHandler + SECTION .text:CODE:REORDER(1) MFS7TX_IRQHandler - B MFS7TX_IRQHandler - PUBWEAK PPG_IRQHandler - SECTION .text:CODE:REORDER(1) + B MFS7TX_IRQHandler + PUBWEAK PPG_IRQHandler + SECTION .text:CODE:REORDER(1) PPG_IRQHandler - B PPG_IRQHandler - PUBWEAK OSC_PLL_WC_IRQHandler - SECTION .text:CODE:REORDER(1) + B PPG_IRQHandler + PUBWEAK OSC_PLL_WC_IRQHandler + SECTION .text:CODE:REORDER(1) OSC_PLL_WC_IRQHandler - B OSC_PLL_WC_IRQHandler - PUBWEAK ADC0_IRQHandler - SECTION .text:CODE:REORDER(1) + B OSC_PLL_WC_IRQHandler + PUBWEAK ADC0_IRQHandler + SECTION .text:CODE:REORDER(1) ADC0_IRQHandler - B ADC0_IRQHandler - PUBWEAK ADC1_IRQHandler - SECTION .text:CODE:REORDER(1) + B ADC0_IRQHandler + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:REORDER(1) ADC1_IRQHandler - B ADC1_IRQHandler - PUBWEAK ADC2_IRQHandler - SECTION .text:CODE:REORDER(1) + B ADC1_IRQHandler + PUBWEAK ADC2_IRQHandler + SECTION .text:CODE:REORDER(1) ADC2_IRQHandler - B ADC2_IRQHandler - PUBWEAK FRTIM_IRQHandler - SECTION .text:CODE:REORDER(1) + B ADC2_IRQHandler + PUBWEAK FRTIM_IRQHandler + SECTION .text:CODE:REORDER(1) FRTIM_IRQHandler - B FRTIM_IRQHandler - PUBWEAK INCAP_IRQHandler - SECTION .text:CODE:REORDER(1) + B FRTIM_IRQHandler + PUBWEAK INCAP_IRQHandler + SECTION .text:CODE:REORDER(1) INCAP_IRQHandler - B INCAP_IRQHandler - PUBWEAK OUTCOMP_IRQHandler - SECTION .text:CODE:REORDER(1) + B INCAP_IRQHandler + PUBWEAK OUTCOMP_IRQHandler + SECTION .text:CODE:REORDER(1) OUTCOMP_IRQHandler - B OUTCOMP_IRQHandler - PUBWEAK BTIM_IRQHandler - SECTION .text:CODE:REORDER(1) + B OUTCOMP_IRQHandler + PUBWEAK BTIM_IRQHandler + SECTION .text:CODE:REORDER(1) BTIM_IRQHandler - B BTIM_IRQHandler - PUBWEAK CAN0_IRQHandler - SECTION .text:CODE:REORDER(1) + B BTIM_IRQHandler + PUBWEAK CAN0_IRQHandler + SECTION .text:CODE:REORDER(1) CAN0_IRQHandler - B CAN0_IRQHandler - PUBWEAK CAN1_IRQHandler - SECTION .text:CODE:REORDER(1) + B CAN0_IRQHandler + PUBWEAK CAN1_IRQHandler + SECTION .text:CODE:REORDER(1) CAN1_IRQHandler - B CAN1_IRQHandler - PUBWEAK USBF_IRQHandler - SECTION .text:CODE:REORDER(1) + B CAN1_IRQHandler + PUBWEAK USBF_IRQHandler + SECTION .text:CODE:REORDER(1) USBF_IRQHandler - B USBF_IRQHandler - PUBWEAK USBF_USBH_IRQHandler - SECTION .text:CODE:REORDER(1) + B USBF_IRQHandler + PUBWEAK USBF_USBH_IRQHandler + SECTION .text:CODE:REORDER(1) USBF_USBH_IRQHandler - B USBF_USBH_IRQHandler - PUBWEAK RESERVED_1_IRQHandler - SECTION .text:CODE:REORDER(1) + B USBF_USBH_IRQHandler + PUBWEAK RESERVED_1_IRQHandler + SECTION .text:CODE:REORDER(1) RESERVED_1_IRQHandler - B RESERVED_1_IRQHandler - PUBWEAK RESERVED_2_IRQHandler - SECTION .text:CODE:REORDER(1) + B RESERVED_1_IRQHandler + PUBWEAK RESERVED_2_IRQHandler + SECTION .text:CODE:REORDER(1) RESERVED_2_IRQHandler - B RESERVED_2_IRQHandler - PUBWEAK DMAC0_IRQHandler - SECTION .text:CODE:REORDER(1) + B RESERVED_2_IRQHandler + PUBWEAK DMAC0_IRQHandler + SECTION .text:CODE:REORDER(1) DMAC0_IRQHandler - B DMAC0_IRQHandler - PUBWEAK DMAC1_IRQHandler - SECTION .text:CODE:REORDER(1) + B DMAC0_IRQHandler + PUBWEAK DMAC1_IRQHandler + SECTION .text:CODE:REORDER(1) DMAC1_IRQHandler - B DMAC1_IRQHandler - PUBWEAK DMAC2_IRQHandler - SECTION .text:CODE:REORDER(1) + B DMAC1_IRQHandler + PUBWEAK DMAC2_IRQHandler + SECTION .text:CODE:REORDER(1) DMAC2_IRQHandler - B DMAC2_IRQHandler - PUBWEAK DMAC3_IRQHandler - SECTION .text:CODE:REORDER(1) + B DMAC2_IRQHandler + PUBWEAK DMAC3_IRQHandler + SECTION .text:CODE:REORDER(1) DMAC3_IRQHandler - B DMAC3_IRQHandler - PUBWEAK DMAC4_IRQHandler - SECTION .text:CODE:REORDER(1) + B DMAC3_IRQHandler + PUBWEAK DMAC4_IRQHandler + SECTION .text:CODE:REORDER(1) DMAC4_IRQHandler - B DMAC4_IRQHandler - PUBWEAK DMAC5_IRQHandler - SECTION .text:CODE:REORDER(1) + B DMAC4_IRQHandler + PUBWEAK DMAC5_IRQHandler + SECTION .text:CODE:REORDER(1) DMAC5_IRQHandler - B DMAC5_IRQHandler - PUBWEAK DMAC6_IRQHandler - SECTION .text:CODE:REORDER(1) + B DMAC5_IRQHandler + PUBWEAK DMAC6_IRQHandler + SECTION .text:CODE:REORDER(1) DMAC6_IRQHandler - B DMAC6_IRQHandler - PUBWEAK DMAC7_IRQHandler - SECTION .text:CODE:REORDER(1) + B DMAC6_IRQHandler + PUBWEAK DMAC7_IRQHandler + SECTION .text:CODE:REORDER(1) DMAC7_IRQHandler - B DMAC7_IRQHandler - PUBWEAK RESERVED_3_IRQHandler - SECTION .text:CODE:REORDER(1) + B DMAC7_IRQHandler + PUBWEAK RESERVED_3_IRQHandler + SECTION .text:CODE:REORDER(1) RESERVED_3_IRQHandler - B RESERVED_3_IRQHandler - PUBWEAK RESERVED_4_IRQHandler - SECTION .text:CODE:REORDER(1) + B RESERVED_3_IRQHandler + PUBWEAK RESERVED_4_IRQHandler + SECTION .text:CODE:REORDER(1) RESERVED_4_IRQHandler - B RESERVED_4_IRQHandler + B RESERVED_4_IRQHandler - END + END diff --git a/bsp/mb9bf500r/CMSIS/start_rvds.S b/bsp/mb9bf500r/CMSIS/start_rvds.S index f74f0473f2..451f17aa0d 100644 --- a/bsp/mb9bf500r/CMSIS/start_rvds.S +++ b/bsp/mb9bf500r/CMSIS/start_rvds.S @@ -1,11 +1,7 @@ ; /* -; * File : start_rvds.s -; * This file is part of RT-Thread RTOS -; * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team +; * Copyright (c) 2006-2021, RT-Thread Development Team ; * -; * The license and distribution terms for this file may be -; * found in the file LICENSE in this distribution or at -; * http://www.rt-thread.org/license/LICENSE +; * SPDX-License-Identifier: Apache-2.0 ; * ; * Change Logs: ; * Date Author Notes diff --git a/bsp/microblaze/application.c b/bsp/microblaze/application.c index 4a09f8b951..d2ec464861 100755 --- a/bsp/microblaze/application.c +++ b/bsp/microblaze/application.c @@ -1,11 +1,7 @@ /* - * File : app.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -20,7 +16,7 @@ int rt_application_init() { - return 0; + return 0; } /*@}*/ diff --git a/bsp/microblaze/startup.c b/bsp/microblaze/startup.c index c900973bb7..e1104a4cd5 100755 --- a/bsp/microblaze/startup.c +++ b/bsp/microblaze/startup.c @@ -1,16 +1,12 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2006-08-31 Bernard first implementation - * 2011-12-17 nl1031 for MicroBlaze + * 2011-12-17 nl1031 for MicroBlaze */ #include @@ -47,66 +43,66 @@ extern rt_err_t rt_hw_serial_init(void); */ void rtthread_startup(void) { - /* init hardware interrupt */ - rt_hw_interrupt_init(); + /* init hardware interrupt */ + rt_hw_interrupt_init(); - /* init board */ - rt_hw_board_init(); - - rt_show_version(); + /* init board */ + rt_hw_board_init(); - /* init timer system */ - rt_system_timer_init(); + rt_show_version(); + + /* init timer system */ + rt_system_timer_init(); #ifdef RT_USING_HEAP #ifdef __CC_ARM - rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x204000); + rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x204000); #elif __ICCARM__ rt_system_heap_init(__segment_end("HEAP"), (void*)0x204000); #else - rt_system_heap_init((void*)&__bss_end, (void*)(&__bss_end+0x4000)); + rt_system_heap_init((void*)&__bss_end, (void*)(&__bss_end+0x4000)); #endif #endif - /* init scheduler system */ - rt_system_scheduler_init(); + /* init scheduler system */ + rt_system_scheduler_init(); #ifdef RT_USING_HOOK /* if the hook is used */ - /* set idle thread hook */ - rt_thread_idle_sethook(rt_hw_led_flash); + /* set idle thread hook */ + rt_thread_idle_sethook(rt_hw_led_flash); #endif #ifdef RT_USING_DEVICE - /* init hardware serial device */ - rt_hw_serial_init(); + /* init hardware serial device */ + rt_hw_serial_init(); #endif - /* init application */ - rt_application_init(); + /* init application */ + rt_application_init(); #ifdef RT_USING_FINSH - /* init finsh */ - finsh_system_init(); - finsh_set_device("uart1"); + /* init finsh */ + finsh_system_init(); + finsh_set_device("uart1"); #endif - /* init idle thread */ - rt_thread_idle_init(); + /* init idle thread */ + rt_thread_idle_init(); - /* start scheduler */ - rt_system_scheduler_start(); + /* start scheduler */ + rt_system_scheduler_start(); - /* never reach here */ - return ; + /* never reach here */ + return ; } int main (void) { - /* invoke rtthread_startup */ - rtthread_startup(); - - return 0; + /* invoke rtthread_startup */ + rtthread_startup(); + + return 0; } /*@}*/ diff --git a/bsp/mini2440/drivers/board.c b/bsp/mini2440/drivers/board.c index d79daaa59c..4cc2dad409 100644 --- a/bsp/mini2440/drivers/board.c +++ b/bsp/mini2440/drivers/board.c @@ -1,18 +1,14 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2009 RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2006-03-24 Bernard first implementation * 2006-05-05 Bernard add DATA_COUNT definition * 2006-10-05 Alsor.Z for s3c2410x porting - * 2007-11-20 Yi.Qiu add lcd,touch,console + * 2007-11-20 Yi.Qiu add lcd,touch,console */ #include @@ -63,7 +59,7 @@ extern void rt_hw_set_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv); */ static void rt_timer_handler(int vector, void *param) { - rt_tick_increase(); + rt_tick_increase(); } /** @@ -71,22 +67,22 @@ static void rt_timer_handler(int vector, void *param) */ static void rt_hw_timer_init(void) { - /* timer4, pre = 15+1 */ - TCFG0 &= 0xffff00ff; - TCFG0 |= 15 << 8; - /* all are interrupt mode,set Timer 4 MUX 1/4 */ - TCFG1 &= 0xfff0ffff; - TCFG1 |= 0x00010000; + /* timer4, pre = 15+1 */ + TCFG0 &= 0xffff00ff; + TCFG0 |= 15 << 8; + /* all are interrupt mode,set Timer 4 MUX 1/4 */ + TCFG1 &= 0xfff0ffff; + TCFG1 |= 0x00010000; - TCNTB4 = (rt_int32_t)(PCLK / (4 *16* RT_TICK_PER_SECOND)) - 1; - /* manual update */ - TCON = TCON & (~(0x0f<<20)) | (0x02<<20); - /* install interrupt handler */ - rt_hw_interrupt_install(INTTIMER4, rt_timer_handler, RT_NULL, "tick"); - rt_hw_interrupt_umask(INTTIMER4); + TCNTB4 = (rt_int32_t)(PCLK / (4 *16* RT_TICK_PER_SECOND)) - 1; + /* manual update */ + TCON = TCON & (~(0x0f<<20)) | (0x02<<20); + /* install interrupt handler */ + rt_hw_interrupt_install(INTTIMER4, rt_timer_handler, RT_NULL, "tick"); + rt_hw_interrupt_umask(INTTIMER4); /* start timer4, reload */ - TCON = TCON & (~(0x0f<<20)) | (0x05<<20); + TCON = TCON & (~(0x0f<<20)) | (0x05<<20); } /** @@ -94,34 +90,34 @@ static void rt_hw_timer_init(void) */ void rt_hw_board_init(void) { - rt_hw_cpu_icache_enable(); - rt_hw_cpu_dcache_enable(); + rt_hw_cpu_icache_enable(); + rt_hw_cpu_dcache_enable(); - /* init hardware interrupt */ - rt_hw_interrupt_init(); + /* init hardware interrupt */ + rt_hw_interrupt_init(); - /* initialize the system clock */ - rt_hw_clock_init(); + /* initialize the system clock */ + rt_hw_clock_init(); - /* Get the clock */ - rt_hw_get_clock(); + /* Get the clock */ + rt_hw_get_clock(); - /* initialize led port */ - rt_hw_led_init(); + /* initialize led port */ + rt_hw_led_init(); - /* initialize mmu */ - rt_hw_mmu_init(); + /* initialize mmu */ + rt_hw_mmu_init(); - /* initialize timer4 */ - rt_hw_timer_init(); + /* initialize timer4 */ + rt_hw_timer_init(); - /* initialize system heap */ - rt_system_heap_init(HEAP_BEGIN, HEAP_END); + /* initialize system heap */ + rt_system_heap_init(HEAP_BEGIN, HEAP_END); - rt_components_board_init(); + rt_components_board_init(); #ifdef RT_USING_CONSOLE - rt_console_set_device("uart0"); + rt_console_set_device("uart0"); #endif } diff --git a/bsp/mini2440/drivers/board.h b/bsp/mini2440/drivers/board.h index 434f725216..33be5cf558 100644 --- a/bsp/mini2440/drivers/board.h +++ b/bsp/mini2440/drivers/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/mini2440/drivers/key.c b/bsp/mini2440/drivers/key.c index d75ffd6d26..459ebf2b07 100644 --- a/bsp/mini2440/drivers/key.c +++ b/bsp/mini2440/drivers/key.c @@ -1,79 +1,75 @@ /* - * File : touch.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2010, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2010-10-01 Yi.Qiu first version */ - /* - * Warning, this keypad driver can only work on QEMU emulator + /* + * Warning, this keypad driver can only work on QEMU emulator */ - + #include #include #include -#define KEY_RX_BUFFER_SIZE 32 +#define KEY_RX_BUFFER_SIZE 32 struct rt_key_device { - struct rt_device parent; + struct rt_device parent; - rt_uint32_t rx_buffer[KEY_RX_BUFFER_SIZE]; - rt_uint32_t read_index, save_index; -}; + rt_uint32_t rx_buffer[KEY_RX_BUFFER_SIZE]; + rt_uint32_t read_index, save_index; +}; static struct rt_key_device *key_device = RT_NULL; /* save a char to serial buffer */ static void rt_key_savechar(char ch) { - rt_base_t level; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); + rt_base_t level; - key_device->rx_buffer[key_device->save_index] = ch; - key_device->save_index ++; - if (key_device->save_index >= KEY_RX_BUFFER_SIZE) - key_device->save_index = 0; - - /* if the next position is read index, discard this 'read char' */ - if (key_device->save_index == key_device->read_index) - { - key_device->read_index ++; - if (key_device->read_index >= KEY_RX_BUFFER_SIZE) - key_device->read_index = 0; - } + /* disable interrupt */ + level = rt_hw_interrupt_disable(); - /* enable interrupt */ - rt_hw_interrupt_enable(level); + key_device->rx_buffer[key_device->save_index] = ch; + key_device->save_index ++; + if (key_device->save_index >= KEY_RX_BUFFER_SIZE) + key_device->save_index = 0; + + /* if the next position is read index, discard this 'read char' */ + if (key_device->save_index == key_device->read_index) + { + key_device->read_index ++; + if (key_device->read_index >= KEY_RX_BUFFER_SIZE) + key_device->read_index = 0; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); } /* ISR for serial interrupt */ static void rt_hw_key_isr(void) { - /* save on rx buffer */ - rt_key_savechar(URXH1 & 0xff); + /* save on rx buffer */ + rt_key_savechar(URXH1 & 0xff); - /* invoke callback */ - if (key_device->parent.rx_indicate != RT_NULL) - { - rt_size_t rx_length; - - /* get rx length */ - rx_length = key_device->read_index > key_device->save_index ? - KEY_RX_BUFFER_SIZE - key_device->read_index + key_device->save_index : - key_device->save_index - key_device->read_index; + /* invoke callback */ + if (key_device->parent.rx_indicate != RT_NULL) + { + rt_size_t rx_length; - key_device->parent.rx_indicate(&key_device->parent, rx_length); - } + /* get rx length */ + rx_length = key_device->read_index > key_device->save_index ? + KEY_RX_BUFFER_SIZE - key_device->read_index + key_device->save_index : + key_device->save_index - key_device->read_index; + + key_device->parent.rx_indicate(&key_device->parent, rx_length); + } } /** @@ -81,14 +77,14 @@ static void rt_hw_key_isr(void) */ static void rt_key_handler(int vector, void *param) { - INTSUBMSK |= (BIT_SUB_RXD1); + INTSUBMSK |= (BIT_SUB_RXD1); - rt_hw_key_isr(); - - SUBSRCPND |= BIT_SUB_RXD1; - - /*Unmask sub interrupt (RXD0)*/ - INTSUBMSK &=~(BIT_SUB_RXD1); + rt_hw_key_isr(); + + SUBSRCPND |= BIT_SUB_RXD1; + + /*Unmask sub interrupt (RXD0)*/ + INTSUBMSK &=~(BIT_SUB_RXD1); } /** @@ -96,114 +92,114 @@ static void rt_key_handler(int vector, void *param) */ static void key_init(void) { - int i = 0; + int i = 0; - GPHCON |= 0xa0; - /*PULLUP is enable */ - GPHUP |= 0x0c; - - /* FIFO enable, Tx/Rx FIFO clear */ - UFCON1 = 0x0; - /* disable the flow control */ - UMCON1= 0x0; - /* Normal,No parity,1 stop,8 bit */ - ULCON1 = 0x3; - /* - * tx=level,rx=edge,disable timeout int.,enable rx error int., - * normal,interrupt or polling - */ - UCON1 = 0x245; + GPHCON |= 0xa0; + /*PULLUP is enable */ + GPHUP |= 0x0c; - //UBRD0 = div; - // UBRD0 = 0x500; /* baudrate = 19200bps */ - UBRD1 = 0x1a; + /* FIFO enable, Tx/Rx FIFO clear */ + UFCON1 = 0x0; + /* disable the flow control */ + UMCON1= 0x0; + /* Normal,No parity,1 stop,8 bit */ + ULCON1 = 0x3; + /* + * tx=level,rx=edge,disable timeout int.,enable rx error int., + * normal,interrupt or polling + */ + UCON1 = 0x245; - UTXH1 = 0x2; - URXH1 = 0x1; + //UBRD0 = div; + // UBRD0 = 0x500; /* baudrate = 19200bps */ + UBRD1 = 0x1a; - /* output PCLK to UART0/1, PWMTIMER */ - CLKCON |= 0x0D00; + UTXH1 = 0x2; + URXH1 = 0x1; - for (i = 0; i < 100; i++); + /* output PCLK to UART0/1, PWMTIMER */ + CLKCON |= 0x0D00; - /* install key isr */ - INTSUBMSK &= ~(BIT_SUB_RXD1); + for (i = 0; i < 100; i++); - rt_hw_interrupt_install(INTUART1, rt_key_handler, RT_NULL , "INTUART1"); - rt_hw_interrupt_umask(INTUART1); + /* install key isr */ + INTSUBMSK &= ~(BIT_SUB_RXD1); + + rt_hw_interrupt_install(INTUART1, rt_key_handler, RT_NULL , "INTUART1"); + rt_hw_interrupt_umask(INTUART1); } static rt_err_t rt_key_init(rt_device_t dev) -{ - if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) - { +{ + if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) + { - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - rt_memset(key_device->rx_buffer, 0, - sizeof(key_device->rx_buffer)); - key_device->read_index = key_device->save_index = 0; - } + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + rt_memset(key_device->rx_buffer, 0, + sizeof(key_device->rx_buffer)); + key_device->read_index = key_device->save_index = 0; + } - dev->flag |= RT_DEVICE_FLAG_ACTIVATED; - } + dev->flag |= RT_DEVICE_FLAG_ACTIVATED; + } - return RT_EOK; + return RT_EOK; } static rt_err_t rt_key_open(rt_device_t dev, rt_uint16_t oflag) -{ - return RT_EOK; +{ + return RT_EOK; } static rt_err_t rt_key_close(rt_device_t dev) -{ - return RT_EOK; +{ + return RT_EOK; } static rt_size_t rt_key_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - rt_err_t err_code; - rt_base_t level; - - ptr = buffer; - err_code = RT_EOK; + rt_uint8_t* ptr; + rt_err_t err_code; + rt_base_t level; - /* interrupt mode Rx */ - while (size) - { - if (key_device->read_index != key_device->save_index) - { - *ptr++ = key_device->rx_buffer[key_device->read_index]; - size --; + ptr = buffer; + err_code = RT_EOK; - /* disable interrupt */ - level = rt_hw_interrupt_disable(); + /* interrupt mode Rx */ + while (size) + { + if (key_device->read_index != key_device->save_index) + { + *ptr++ = key_device->rx_buffer[key_device->read_index]; + size --; - key_device->read_index ++; - if (key_device->read_index >= KEY_RX_BUFFER_SIZE) - key_device->read_index = 0; + /* disable interrupt */ + level = rt_hw_interrupt_disable(); - /* enable interrupt */ - rt_hw_interrupt_enable(level); - } - else - { - /* set error code */ - err_code = -RT_EEMPTY; - break; - } - } + key_device->read_index ++; + if (key_device->read_index >= KEY_RX_BUFFER_SIZE) + key_device->read_index = 0; - /* set error code */ - rt_set_errno(err_code); - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } + else + { + /* set error code */ + err_code = -RT_EEMPTY; + break; + } + } + + /* set error code */ + rt_set_errno(err_code); + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; } static rt_err_t rt_key_control(rt_device_t dev, int cmd, void *args) { - return RT_EOK; + return RT_EOK; } #ifdef RT_USING_RTGUI @@ -215,96 +211,96 @@ static int s_key_map[0xff] = {0}; static void rt_keymap_init(void) { - s_key_map[0x1] = RTGUIK_ESCAPE; - s_key_map[0xc] = RTGUIK_MINUS; - s_key_map[0x39] = RTGUIK_SPACE; - s_key_map[0xd] = RTGUIK_KP_EQUALS; - s_key_map[0xe] = RTGUIK_BACKSPACE; - s_key_map[0xf] = RTGUIK_TAB; - s_key_map[0x1c] = RTGUIK_KP_ENTER; - s_key_map[0xb] = RTGUIK_0; - s_key_map[0x2] = RTGUIK_1; - s_key_map[0x3] = RTGUIK_2; - s_key_map[0x4] = RTGUIK_3; - s_key_map[0x5] = RTGUIK_4; - s_key_map[0x6] = RTGUIK_5; - s_key_map[0x7] = RTGUIK_6; - s_key_map[0x8] = RTGUIK_7; - s_key_map[0x9] = RTGUIK_8; - s_key_map[0xa] = RTGUIK_9; - s_key_map[0x3b] = RTGUIK_F1; - s_key_map[0x3c] = RTGUIK_F2; - s_key_map[0x3d] = RTGUIK_F3; - s_key_map[0x3e] = RTGUIK_F4; - s_key_map[0xef] = RTGUIK_F5; - s_key_map[0x40] = RTGUIK_F6; - s_key_map[0x41] = RTGUIK_F7; - s_key_map[0x42] = RTGUIK_F8; - s_key_map[0x43] = RTGUIK_F9; - s_key_map[0x1e] = RTGUIK_a; - s_key_map[0x30] = RTGUIK_b; - s_key_map[0x2c] = RTGUIK_c; - s_key_map[0x20] = RTGUIK_d; - s_key_map[0x12] = RTGUIK_e; - s_key_map[0x21] = RTGUIK_f; - s_key_map[0x22] = RTGUIK_g; - s_key_map[0x23] = RTGUIK_h; - s_key_map[0x17] = RTGUIK_i; - s_key_map[0x24] = RTGUIK_j; - s_key_map[0x25] = RTGUIK_k; - s_key_map[0x26] = RTGUIK_l; - s_key_map[0x32] = RTGUIK_m; - s_key_map[0x31] = RTGUIK_n; - s_key_map[0x18] = RTGUIK_o; - s_key_map[0x19] = RTGUIK_p; - s_key_map[0x10] = RTGUIK_q; - s_key_map[0x13] = RTGUIK_r; - s_key_map[0x1f] = RTGUIK_s; - s_key_map[0x14] = RTGUIK_t; - s_key_map[0x16] = RTGUIK_u; - s_key_map[0x2f] = RTGUIK_v; - s_key_map[0x11] = RTGUIK_w; - s_key_map[0x2d] = RTGUIK_x; - s_key_map[0x15] = RTGUIK_y; - s_key_map[0x2c] = RTGUIK_z; - s_key_map[0x4b] = RTGUIK_LEFT; - s_key_map[0x4d] = RTGUIK_RIGHT; - s_key_map[0x50] = RTGUIK_DOWN; - s_key_map[0x2e] = RTGUIK_DELETE; - s_key_map[0x48] = RTGUIK_UP; -} + s_key_map[0x1] = RTGUIK_ESCAPE; + s_key_map[0xc] = RTGUIK_MINUS; + s_key_map[0x39] = RTGUIK_SPACE; + s_key_map[0xd] = RTGUIK_KP_EQUALS; + s_key_map[0xe] = RTGUIK_BACKSPACE; + s_key_map[0xf] = RTGUIK_TAB; + s_key_map[0x1c] = RTGUIK_KP_ENTER; + s_key_map[0xb] = RTGUIK_0; + s_key_map[0x2] = RTGUIK_1; + s_key_map[0x3] = RTGUIK_2; + s_key_map[0x4] = RTGUIK_3; + s_key_map[0x5] = RTGUIK_4; + s_key_map[0x6] = RTGUIK_5; + s_key_map[0x7] = RTGUIK_6; + s_key_map[0x8] = RTGUIK_7; + s_key_map[0x9] = RTGUIK_8; + s_key_map[0xa] = RTGUIK_9; + s_key_map[0x3b] = RTGUIK_F1; + s_key_map[0x3c] = RTGUIK_F2; + s_key_map[0x3d] = RTGUIK_F3; + s_key_map[0x3e] = RTGUIK_F4; + s_key_map[0xef] = RTGUIK_F5; + s_key_map[0x40] = RTGUIK_F6; + s_key_map[0x41] = RTGUIK_F7; + s_key_map[0x42] = RTGUIK_F8; + s_key_map[0x43] = RTGUIK_F9; + s_key_map[0x1e] = RTGUIK_a; + s_key_map[0x30] = RTGUIK_b; + s_key_map[0x2c] = RTGUIK_c; + s_key_map[0x20] = RTGUIK_d; + s_key_map[0x12] = RTGUIK_e; + s_key_map[0x21] = RTGUIK_f; + s_key_map[0x22] = RTGUIK_g; + s_key_map[0x23] = RTGUIK_h; + s_key_map[0x17] = RTGUIK_i; + s_key_map[0x24] = RTGUIK_j; + s_key_map[0x25] = RTGUIK_k; + s_key_map[0x26] = RTGUIK_l; + s_key_map[0x32] = RTGUIK_m; + s_key_map[0x31] = RTGUIK_n; + s_key_map[0x18] = RTGUIK_o; + s_key_map[0x19] = RTGUIK_p; + s_key_map[0x10] = RTGUIK_q; + s_key_map[0x13] = RTGUIK_r; + s_key_map[0x1f] = RTGUIK_s; + s_key_map[0x14] = RTGUIK_t; + s_key_map[0x16] = RTGUIK_u; + s_key_map[0x2f] = RTGUIK_v; + s_key_map[0x11] = RTGUIK_w; + s_key_map[0x2d] = RTGUIK_x; + s_key_map[0x15] = RTGUIK_y; + s_key_map[0x2c] = RTGUIK_z; + s_key_map[0x4b] = RTGUIK_LEFT; + s_key_map[0x4d] = RTGUIK_RIGHT; + s_key_map[0x50] = RTGUIK_DOWN; + s_key_map[0x2e] = RTGUIK_DELETE; + s_key_map[0x48] = RTGUIK_UP; +} static rt_err_t rtgui_key_rx(rt_device_t dev, rt_size_t size) { - struct rtgui_event_kbd kbd_event; - char key_value; + struct rtgui_event_kbd kbd_event; + char key_value; - while(rt_device_read(dev, 0, &key_value, 1) == 1) - { - /* init keyboard event */ - RTGUI_EVENT_KBD_INIT(&kbd_event); - kbd_event.mod = RTGUI_KMOD_NONE; - kbd_event.unicode = 0; - kbd_event.key = RTGUIK_UNKNOWN; + while(rt_device_read(dev, 0, &key_value, 1) == 1) + { + /* init keyboard event */ + RTGUI_EVENT_KBD_INIT(&kbd_event); + kbd_event.mod = RTGUI_KMOD_NONE; + kbd_event.unicode = 0; + kbd_event.key = RTGUIK_UNKNOWN; - if(key_value & 0x80) - { - kbd_event.type = RTGUI_KEYUP; - } - else - { - kbd_event.type = RTGUI_KEYDOWN; - } + if(key_value & 0x80) + { + kbd_event.type = RTGUI_KEYUP; + } + else + { + kbd_event.type = RTGUI_KEYDOWN; + } - kbd_event.key = s_key_map[key_value & 0x7F]; - } - if (kbd_event.key != RTGUIK_UNKNOWN) - { - /* post down event */ - rtgui_server_post_event(&(kbd_event.parent), sizeof(kbd_event)); - } - - return RT_EOK; + kbd_event.key = s_key_map[key_value & 0x7F]; + } + if (kbd_event.key != RTGUIK_UNKNOWN) + { + /* post down event */ + rtgui_server_post_event(&(kbd_event.parent), sizeof(kbd_event)); + } + + return RT_EOK; } #endif @@ -314,33 +310,33 @@ static rt_err_t rtgui_key_rx(rt_device_t dev, rt_size_t size) */ void rt_hw_key_init(void) { - /* hardware init */ - key_init(); + /* hardware init */ + key_init(); - key_device = (struct rt_key_device*)rt_malloc (sizeof(struct rt_key_device)); - if (key_device == RT_NULL) return; /* no memory yet */ + key_device = (struct rt_key_device*)rt_malloc (sizeof(struct rt_key_device)); + if (key_device == RT_NULL) return; /* no memory yet */ - /* clear device structure */ - rt_memset(&(key_device->parent), 0, sizeof(struct rt_device)); - - key_device->parent.type = RT_Device_Class_Char; - key_device->parent.tx_complete = RT_NULL; - key_device->parent.init = rt_key_init; - key_device->parent.open = rt_key_open; - key_device->parent.close = rt_key_close; - key_device->parent.read = rt_key_read; - key_device->parent.write = RT_NULL; - key_device->parent.control = rt_key_control; - key_device->parent.user_data = RT_NULL; + /* clear device structure */ + rt_memset(&(key_device->parent), 0, sizeof(struct rt_device)); + + key_device->parent.type = RT_Device_Class_Char; + key_device->parent.tx_complete = RT_NULL; + key_device->parent.init = rt_key_init; + key_device->parent.open = rt_key_open; + key_device->parent.close = rt_key_close; + key_device->parent.read = rt_key_read; + key_device->parent.write = RT_NULL; + key_device->parent.control = rt_key_control; + key_device->parent.user_data = RT_NULL; #ifdef RT_USING_RTGUI - key_device->parent.rx_indicate = rtgui_key_rx; + key_device->parent.rx_indicate = rtgui_key_rx; - /* init keymap */ - rt_keymap_init(); + /* init keymap */ + rt_keymap_init(); #endif - /* register key device to RT-Thread */ - rt_device_register(&(key_device->parent), "key", RT_DEVICE_FLAG_RDONLY | RT_DEVICE_FLAG_INT_RX); + /* register key device to RT-Thread */ + rt_device_register(&(key_device->parent), "key", RT_DEVICE_FLAG_RDONLY | RT_DEVICE_FLAG_INT_RX); } diff --git a/bsp/mini2440/drivers/lcd_a70.c b/bsp/mini2440/drivers/lcd_a70.c index 5020012b2f..9d7da3f8c6 100644 --- a/bsp/mini2440/drivers/lcd_a70.c +++ b/bsp/mini2440/drivers/lcd_a70.c @@ -1,11 +1,7 @@ /* - * File : lcd_t35.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2010, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -141,7 +137,7 @@ static void LcdBkLtSet(rt_uint32_t HiRatio) #define FREQ_PWM1 1000 if(!HiRatio) { - GPBCON = GPBCON & (~(3<<2)) | (1<<2) ; + GPBCON = GPBCON & (~(3<<2)) | (1<<2) ; GPBDAT &= ~(1<<1); return; } @@ -212,7 +208,7 @@ static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args) break; case RTGRAPHIC_CTRL_POWEROFF: break; - case RTGRAPHIC_CTRL_GET_INFO: + case RTGRAPHIC_CTRL_GET_INFO: rt_memcpy(args, &_lcd_info, sizeof(_lcd_info)); break; case RTGRAPHIC_CTRL_SET_MODE: @@ -225,7 +221,7 @@ static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args) int rt_hw_lcd_init(void) { rt_device_t lcd = rt_malloc(sizeof(struct rt_device)); - if (lcd == RT_NULL) + if (lcd == RT_NULL) return -RT_ERROR; /* no memory yet */ _lcd_info.bits_per_pixel = 16; @@ -241,7 +237,7 @@ int rt_hw_lcd_init(void) lcd->close = RT_NULL; lcd->control = rt_lcd_control; lcd->user_data = (void*)&_lcd_info; - + /* register lcd device to RT-Thread */ rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR); } diff --git a/bsp/mini2440/drivers/lcd_n35.c b/bsp/mini2440/drivers/lcd_n35.c index 1a3af23c09..f536dd5d7d 100644 --- a/bsp/mini2440/drivers/lcd_n35.c +++ b/bsp/mini2440/drivers/lcd_n35.c @@ -1,11 +1,7 @@ /* - * File : lcd_t35.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2010, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -142,7 +138,7 @@ static void LcdBkLtSet(rt_uint32_t HiRatio) #define FREQ_PWM1 1000 if(!HiRatio) { - GPBCON = GPBCON & (~(3<<2)) | (1<<2) ; + GPBCON = GPBCON & (~(3<<2)) | (1<<2) ; GPBDAT &= ~(1<<1); return; } @@ -167,7 +163,7 @@ static void LcdBkLtSet(rt_uint32_t HiRatio) /* RT-Thread Device Interface */ static rt_err_t rt_lcd_init (rt_device_t dev) -{ +{ GPB1_TO_OUT(); GPB1_TO_1(); @@ -213,7 +209,7 @@ static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args) break; case RTGRAPHIC_CTRL_POWEROFF: break; - case RTGRAPHIC_CTRL_GET_INFO: + case RTGRAPHIC_CTRL_GET_INFO: rt_memcpy(args, &_lcd_info, sizeof(_lcd_info)); break; case RTGRAPHIC_CTRL_SET_MODE: @@ -226,7 +222,7 @@ static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args) int rt_hw_lcd_init(void) { rt_device_t lcd = rt_malloc(sizeof(struct rt_device)); - if (lcd == RT_NULL) + if (lcd == RT_NULL) return -RT_ERROR; /* no memory yet */ _lcd_info.bits_per_pixel = 16; @@ -242,7 +238,7 @@ int rt_hw_lcd_init(void) lcd->close = RT_NULL; lcd->control = rt_lcd_control; lcd->user_data = (void*)&_lcd_info; - + /* register lcd device to RT-Thread */ rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR); } diff --git a/bsp/mini2440/drivers/lcd_t35.c b/bsp/mini2440/drivers/lcd_t35.c index c13a3c030f..edf8db17f9 100644 --- a/bsp/mini2440/drivers/lcd_t35.c +++ b/bsp/mini2440/drivers/lcd_t35.c @@ -1,11 +1,7 @@ /* - * File : lcd_t35.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2010, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -142,7 +138,7 @@ static void LcdBkLtSet(rt_uint32_t HiRatio) #define FREQ_PWM1 1000 if(!HiRatio) { - GPBCON = GPBCON & (~(3<<2)) | (1<<2) ; + GPBCON = GPBCON & (~(3<<2)) | (1<<2) ; GPBDAT &= ~(1<<1); return; } @@ -167,7 +163,7 @@ static void LcdBkLtSet(rt_uint32_t HiRatio) /* RT-Thread Device Interface */ static rt_err_t rt_lcd_init (rt_device_t dev) -{ +{ GPB1_TO_OUT(); GPB1_TO_1(); @@ -214,7 +210,7 @@ static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args) break; case RTGRAPHIC_CTRL_POWEROFF: break; - case RTGRAPHIC_CTRL_GET_INFO: + case RTGRAPHIC_CTRL_GET_INFO: rt_memcpy(args, &_lcd_info, sizeof(_lcd_info)); break; case RTGRAPHIC_CTRL_SET_MODE: @@ -227,7 +223,7 @@ static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args) int rt_hw_lcd_init(void) { rt_device_t lcd = rt_malloc(sizeof(struct rt_device)); - if (lcd == RT_NULL) + if (lcd == RT_NULL) return -RT_ERROR; /* no memory yet */ _lcd_info.bits_per_pixel = 16; @@ -243,7 +239,7 @@ int rt_hw_lcd_init(void) lcd->close = RT_NULL; lcd->control = rt_lcd_control; lcd->user_data = (void*)&_lcd_info; - + /* register lcd device to RT-Thread */ rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR); } diff --git a/bsp/mini2440/drivers/lcd_x35.c b/bsp/mini2440/drivers/lcd_x35.c index b4a8fda23c..a198aac05e 100644 --- a/bsp/mini2440/drivers/lcd_x35.c +++ b/bsp/mini2440/drivers/lcd_x35.c @@ -1,16 +1,12 @@ /* - * File : lcd_x35.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2010, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2010-01-01 bernard first version from QiuYi's driver - * 2011-07-13 Manoel Modifications on lcd_n35.c to support X35 LCD + * 2011-07-13 Manoel Modifications on lcd_n35.c to support X35 LCD * ACX502BMU - 7522J16D SONY */ @@ -28,7 +24,7 @@ #define LCD_HSYNC_LEN 5 // hsync #define LCD_UPPER_MARGIN 1 // margin_top -#define LCD_LOWER_MARGIN 3 // margin_botton +#define LCD_LOWER_MARGIN 3 // margin_botton #define LCD_VSYNC_LEN 9 // vsync #define LCD_XSIZE LCD_WIDTH @@ -144,7 +140,7 @@ static void LcdBkLtSet(rt_uint32_t HiRatio) #define FREQ_PWM1 1000 if(!HiRatio) { - GPBCON = GPBCON & (~(3<<2)) | (1<<2) ; + GPBCON = GPBCON & (~(3<<2)) | (1<<2) ; GPBDAT &= ~(1<<1); return; } @@ -169,7 +165,7 @@ static void LcdBkLtSet(rt_uint32_t HiRatio) /* RT-Thread Device Interface */ static rt_err_t rt_lcd_init (rt_device_t dev) -{ +{ GPB1_TO_OUT(); GPB1_TO_1(); @@ -219,7 +215,7 @@ static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args) break; case RTGRAPHIC_CTRL_POWEROFF: break; - case RTGRAPHIC_CTRL_GET_INFO: + case RTGRAPHIC_CTRL_GET_INFO: rt_memcpy(args, &_lcd_info, sizeof(_lcd_info)); break; case RTGRAPHIC_CTRL_SET_MODE: @@ -232,7 +228,7 @@ static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args) int rt_hw_lcd_init(void) { rt_device_t lcd = rt_malloc(sizeof(struct rt_device)); - if (lcd == RT_NULL) + if (lcd == RT_NULL) return -RT_ERROR; /* no memory yet */ _lcd_info.bits_per_pixel = 16; @@ -248,7 +244,7 @@ int rt_hw_lcd_init(void) lcd->close = RT_NULL; lcd->control = rt_lcd_control; lcd->user_data = (void*)&_lcd_info; - + /* register lcd device to RT-Thread */ rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR); } diff --git a/bsp/mini2440/drivers/led.c b/bsp/mini2440/drivers/led.c index 4155a6bab7..88e83d33ef 100644 --- a/bsp/mini2440/drivers/led.c +++ b/bsp/mini2440/drivers/led.c @@ -1,11 +1,7 @@ /* - * File : led.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -22,19 +18,19 @@ void rt_hw_led_init(void) { - /* GPB5,GPB6,GPB7,GPB8 for LED */ - GPBCON = GPBCON & (~(0xff << 10)) | (0x55 << 10); - GPBUP |= (0x0f << 5); + /* GPB5,GPB6,GPB7,GPB8 for LED */ + GPBCON = GPBCON & (~(0xff << 10)) | (0x55 << 10); + GPBUP |= (0x0f << 5); } void rt_hw_led_on(unsigned char value) { - GPBDAT &= ~ ((value & 0x0f) << 5); + GPBDAT &= ~ ((value & 0x0f) << 5); } void rt_hw_led_off(unsigned char value) { - GPBDAT |= (value & 0x0f) << 5; + GPBDAT |= (value & 0x0f) << 5; } /*@}*/ diff --git a/bsp/mini2440/drivers/led.h b/bsp/mini2440/drivers/led.h index bc719f182e..67deceb230 100644 --- a/bsp/mini2440/drivers/led.h +++ b/bsp/mini2440/drivers/led.h @@ -1,11 +1,7 @@ /* - * File : led.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/mini2440/drivers/touch.c b/bsp/mini2440/drivers/touch.c index 404169a43f..122488daff 100644 --- a/bsp/mini2440/drivers/touch.c +++ b/bsp/mini2440/drivers/touch.c @@ -1,17 +1,13 @@ /* - * File : touch.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2010 - 2012, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2010-01-01 Yi.Qiu first version */ - + #include #include #include @@ -104,7 +100,7 @@ struct rtgui_touch_device rt_uint16_t width; rt_uint16_t height; - + rt_bool_t first_down_report; }; static struct rtgui_touch_device *touch = RT_NULL; @@ -120,7 +116,7 @@ static void report_touch_input(int updown) /* set emouse button */ emouse.button = RTGUI_MOUSE_BUTTON_LEFT; emouse.parent.sender = RT_NULL; - + if (updown) { ts.xp = ts.xp / ts.count; @@ -166,7 +162,7 @@ static void report_touch_input(int updown) emouse.button |= RTGUI_MOUSE_BUTTON_DOWN; } else - { + { emouse.parent.type = RTGUI_EVENT_MOUSE_MOTION; emouse.button = 0; } @@ -174,7 +170,7 @@ static void report_touch_input(int updown) else { emouse.x = touch->x; - emouse.y = touch->y; + emouse.y = touch->y; emouse.parent.type = RTGUI_EVENT_MOUSE_BUTTON; emouse.button |= RTGUI_MOUSE_BUTTON_UP; if ((touch->calibrating == RT_TRUE) && (touch->calibration_func != RT_NULL)) @@ -185,11 +181,11 @@ static void report_touch_input(int updown) } /* rt_kprintf("touch %s: ts.x: %d, ts.y: %d\n", updown? "down" : "up", - touch->x, touch->y); */ - + touch->x, touch->y); */ + /* send event to server */ if (touch->calibrating != RT_TRUE) - { + { rtgui_server_post_event((&emouse.parent), sizeof(emouse)); } } @@ -237,7 +233,7 @@ static void report_touch_input(int updown) { if (touch->calibrating != RT_TRUE && touch->eventpost_func) { - touch->eventpost_func(touch->eventpost_param, &touch_event); + touch->eventpost_func(touch->eventpost_param, &touch_event); } } } @@ -246,7 +242,7 @@ static void report_touch_input(int updown) touch_event.x = touch->x; touch_event.y = touch->y; touch_event.pressed = 0; - + if ((touch->calibrating == RT_TRUE) && (touch->calibration_func != RT_NULL)) { /* callback function */ @@ -254,8 +250,8 @@ static void report_touch_input(int updown) } if (touch->calibrating != RT_TRUE && touch->eventpost_func) - { - touch->eventpost_func(touch->eventpost_param, &touch_event); + { + touch->eventpost_func(touch->eventpost_param, &touch_event); } } } @@ -295,7 +291,7 @@ static void s3c2410_adc_stylus_action(void) data0 = ADCDAT0; data1 = ADCDAT1; - + ts.xp += data0 & S3C2410_ADCDAT0_XPDATA_MASK; ts.yp += data1 & S3C2410_ADCDAT1_YPDATA_MASK; ts.count ++; @@ -336,10 +332,10 @@ static void s3c2410_intc_stylus_updown(void) /* rt_kprintf("stylus: %s\n", updown? "down" : "up"); */ - if (updown) + if (updown) { touch_timer_fire(0); - } + } else { /* stop timer */ @@ -437,7 +433,7 @@ static rt_err_t rtgui_touch_control(rt_device_t dev, int cmd, void *args) /* rt_kprintf("min_x = %d, max_x = %d, min_y = %d, max_y = %d\n", touch->min_x, touch->max_x, touch->min_y, touch->max_y); - */ + */ } break; @@ -480,10 +476,10 @@ int rtgui_touch_hw_init(void) touch->parent.user_data = RT_NULL; device = rt_device_find("lcd"); - if (device == RT_NULL) + if (device == RT_NULL) { rt_kprintf("No lcd found\n"); - return -RT_ERROR; /* no this device */ + return -RT_ERROR; /* no this device */ } /* get graphic device info */ @@ -497,7 +493,7 @@ int rtgui_touch_hw_init(void) touch->width = info.width; touch->height = info.height; - + /* create 1/8 second timer */ touch->poll_timer = rt_timer_create("touch", touch_timer_fire, RT_NULL, RT_TICK_PER_SECOND/8, RT_TIMER_FLAG_PERIODIC); diff --git a/bsp/mini4020/applications/application.c b/bsp/mini4020/applications/application.c index 6281b8385d..f5a77d8c60 100644 --- a/bsp/mini4020/applications/application.c +++ b/bsp/mini4020/applications/application.c @@ -1,22 +1,18 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2007-11-20 Yi.Qiu add rtgui application - * 2008-6-28 Bernard no rtgui init + * Date Author Notes + * 2007-11-20 Yi.Qiu add rtgui application + * 2008-6-28 Bernard no rtgui init */ /** * @addtogroup mini4020 */ - + /*@{*/ #include @@ -38,54 +34,54 @@ extern void radio_rtgui_init(void); void rt_init_thread_entry(void *parameter) { - int fd; - rt_uint32_t sz; - char buffer[20]; + int fd; + rt_uint32_t sz; + char buffer[20]; #ifdef RT_USING_DFS - dfs_init(); + dfs_init(); #ifdef RT_USING_DFS_ELMFAT - elm_init(); - /* mount sd card fat partition 1 as root directory */ - if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) - { - rt_kprintf("File System initialized!\n"); + elm_init(); + /* mount sd card fat partition 1 as root directory */ + if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) + { + rt_kprintf("File System initialized!\n"); - /*Open a file*/ - fd = open("/fattest.txt", O_RDWR|O_CREAT, 0); - if (fd < 0) - { - rt_kprintf("open file for write failed\n"); - return; - } + /*Open a file*/ + fd = open("/fattest.txt", O_RDWR|O_CREAT, 0); + if (fd < 0) + { + rt_kprintf("open file for write failed\n"); + return; + } - sz = write(fd,"Hello RT-Thread!",sizeof("Hello RT-Thread!")); + sz = write(fd,"Hello RT-Thread!",sizeof("Hello RT-Thread!")); - if (sz != 0) - { - rt_kprintf("written %d\n",sz); - } - else - rt_kprintf("haven't written\n"); + if (sz != 0) + { + rt_kprintf("written %d\n",sz); + } + else + rt_kprintf("haven't written\n"); - lseek(fd, 0, SEEK_SET); - - sz = read(fd, buffer, sizeof(buffer)); + lseek(fd, 0, SEEK_SET); - if (sz != 0) - { - rt_kprintf("READ %d:",sz); - while (sz--) - rt_kprintf("%c",buffer[sz]);//opposite - rt_kprintf("\n"); - } - else - rt_kprintf("haven't read\n"); + sz = read(fd, buffer, sizeof(buffer)); - close(fd); - } - else - rt_kprintf("File System initialzation failed!\n"); -#endif + if (sz != 0) + { + rt_kprintf("READ %d:",sz); + while (sz--) + rt_kprintf("%c",buffer[sz]);//opposite + rt_kprintf("\n"); + } + else + rt_kprintf("haven't read\n"); + + close(fd); + } + else + rt_kprintf("File System initialzation failed!\n"); +#endif #endif } @@ -108,23 +104,23 @@ void rt_led_thread_entry(void *parameter) int rt_application_init(void) { - rt_thread_t init_thread; - rt_thread_t led_thread; + rt_thread_t init_thread; + rt_thread_t led_thread; - init_thread = rt_thread_create("init", - rt_init_thread_entry, RT_NULL, - RT_INIT_THREAD_STACK_SIZE, 8, 20); - led_thread = rt_thread_create("led", - rt_led_thread_entry, RT_NULL, - 512, 200, 20); + init_thread = rt_thread_create("init", + rt_init_thread_entry, RT_NULL, + RT_INIT_THREAD_STACK_SIZE, 8, 20); + led_thread = rt_thread_create("led", + rt_led_thread_entry, RT_NULL, + 512, 200, 20); - if (init_thread != RT_NULL) - rt_thread_startup(init_thread); + if (init_thread != RT_NULL) + rt_thread_startup(init_thread); - if (led_thread != RT_NULL) - rt_thread_startup(led_thread); - - return 0; + if (led_thread != RT_NULL) + rt_thread_startup(led_thread); + + return 0; } /*@}*/ diff --git a/bsp/mini4020/applications/startup.c b/bsp/mini4020/applications/startup.c index ae84f8b461..4d07a8edd7 100644 --- a/bsp/mini4020/applications/startup.c +++ b/bsp/mini4020/applications/startup.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -26,12 +22,12 @@ #include #endif -#define SDRAM_BASE 0x30000000 +#define SDRAM_BASE 0x30000000 #ifdef __CC_ARM extern int Image$$RW_RAM1$$ZI$$Limit; #elif (defined (__GNUC__)) - extern unsigned char __bss_end; + extern unsigned char __bss_end; #endif extern void rt_application_init(void); @@ -40,72 +36,72 @@ extern void sd_init(void); void rtthread_startup() { - /* init hardware interrupt */ - rt_hw_interrupt_init(); + /* init hardware interrupt */ + rt_hw_interrupt_init(); - /* init board */ - rt_hw_board_init(); + /* init board */ + rt_hw_board_init(); - /* show version */ - rt_show_version(); - - /* init timer system */ - rt_system_timer_init(); + /* show version */ + rt_show_version(); - /* init heap memory system */ + /* init timer system */ + rt_system_timer_init(); + + /* init heap memory system */ #ifdef __CC_ARM - rt_system_heap_init((void*)&Image$$RW_RAM1$$ZI$$Limit, (void*)(SDRAM_BASE + 0x200000)); + rt_system_heap_init((void*)&Image$$RW_RAM1$$ZI$$Limit, (void*)(SDRAM_BASE + 0x200000)); #else - rt_system_heap_init(&__bss_end, (void*)0x34000000); + rt_system_heap_init(&__bss_end, (void*)0x34000000); #endif - /* init scheduler system */ - rt_system_scheduler_init(); + /* init scheduler system */ + rt_system_scheduler_init(); #ifdef RT_USING_DEVICE #ifdef RT_USING_DFS - rt_hw_sdcard_init(); + rt_hw_sdcard_init(); #endif #ifdef RT_USING_LWIP - eth_system_device_init(); - rt_hw_dm9161_init(); + eth_system_device_init(); + rt_hw_dm9161_init(); #endif #endif - /* init application */ - rt_application_init(); + /* init application */ + rt_application_init(); #ifdef RT_USING_FINSH - /* init finsh */ - finsh_system_init(); + /* init finsh */ + finsh_system_init(); #ifdef RT_USING_DEVICE - finsh_set_device("uart0"); + finsh_set_device("uart0"); #endif #endif - /* init idle thread */ - rt_thread_idle_init(); + /* init idle thread */ + rt_thread_idle_init(); - /* start scheduler */ - rt_system_scheduler_start(); + /* start scheduler */ + rt_system_scheduler_start(); + + /* never reach here */ + return ; - /* never reach here */ - return ; - } int main() { - /* disable interrupt first */ - rt_hw_interrupt_disable(); + /* disable interrupt first */ + rt_hw_interrupt_disable(); - /* startup RT-Thread RTOS */ - rtthread_startup(); + /* startup RT-Thread RTOS */ + rtthread_startup(); - return 0; + return 0; } diff --git a/bsp/mini4020/drivers/board.h b/bsp/mini4020/drivers/board.h index fd794a8a7c..baabfae361 100644 --- a/bsp/mini4020/drivers/board.h +++ b/bsp/mini4020/drivers/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/mini4020/drivers/dm9161.c b/bsp/mini4020/drivers/dm9161.c index cae98435e2..a5100f501b 100644 --- a/bsp/mini4020/drivers/dm9161.c +++ b/bsp/mini4020/drivers/dm9161.c @@ -1,11 +1,7 @@ /* - * File : dm9161.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -22,8 +18,8 @@ #define SPEED_100 100 #define SPEED_1000 1000 /* Duplex, half or full. */ -#define DUPLEX_HALF 0x00 -#define DUPLEX_FULL 0x01 +#define DUPLEX_HALF 0x00 +#define DUPLEX_FULL 0x01 /* * Davicom dm9161EP driver @@ -32,9 +28,9 @@ * nLAN_CS connects to nGCS4 */ -/* #define dm9161_DEBUG 1 */ +/* #define dm9161_DEBUG 1 */ #if DM9161_DEBUG -#define DM9161_TRACE rt_kprintf +#define DM9161_TRACE rt_kprintf #else #define DM9161_TRACE(...) #endif @@ -65,18 +61,18 @@ struct rt_dm9161_eth struct eth_device parent; enum DM9161_TYPE type; - enum DM9161_PHY_mode mode; + enum DM9161_PHY_mode mode; rt_uint8_t imr_all; - rt_uint8_t phy_addr; + rt_uint8_t phy_addr; - rt_uint32_t tx_index; + rt_uint32_t tx_index; rt_uint8_t packet_cnt; /* packet I or II */ rt_uint16_t queue_packet_len; /* queued packet (packet II) */ /* interface address info. */ - rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ + rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ }; static struct rt_dm9161_eth dm9161_device; static struct rt_semaphore sem_ack, sem_lock; @@ -85,33 +81,33 @@ void rt_dm9161_isr(int irqno, void *param); static void udelay(unsigned long ns) { - unsigned long i; + unsigned long i; - while (ns--) - { - i = 100; - while (i--); - } + while (ns--) + { + i = 100; + while (i--); + } } static __inline unsigned long sep_emac_read(unsigned int reg) { - void __iomem *emac_base = (void __iomem *)reg; + void __iomem *emac_base = (void __iomem *)reg; - return read_reg(emac_base); + return read_reg(emac_base); } - + /* * Write to a EMAC register. */ static __inline void sep_emac_write(unsigned int reg, unsigned long value) { - void __iomem *emac_base = (void __iomem *)reg; - - write_reg(emac_base,value); + void __iomem *emac_base = (void __iomem *)reg; + + write_reg(emac_base,value); } - + /* ........................... PHY INTERFACE ........................... */ /* CAN DO MAC CONFIGRATION * Enable the MDIO bit in MAC control register @@ -120,12 +116,12 @@ static __inline void sep_emac_write(unsigned int reg, unsigned long value) */ static void enable_mdi(void) //need think more { - unsigned long ctl; + unsigned long ctl; - ctl = sep_emac_read(MAC_CTRL); - sep_emac_write(MAC_CTRL, ctl&(~0x3)); /* enable management port */ + ctl = sep_emac_read(MAC_CTRL); + sep_emac_write(MAC_CTRL, ctl&(~0x3)); /* enable management port */ - return; + return; } /* CANNOT DO MAC CONFIGRATION @@ -133,216 +129,216 @@ static void enable_mdi(void) //need think more */ static void disable_mdi(void) { - unsigned long ctl; - - ctl = sep_emac_read(MAC_CTRL); - sep_emac_write(MAC_CTRL, ctl|(0x3)); /* disable management port */ + unsigned long ctl; - return; + ctl = sep_emac_read(MAC_CTRL); + sep_emac_write(MAC_CTRL, ctl|(0x3)); /* disable management port */ + + return; } /* * Wait until the PHY operation is complete. */ -static __inline void sep_phy_wait(void) +static __inline void sep_phy_wait(void) { - unsigned long timeout = 2; + unsigned long timeout = 2; - while ((sep_emac_read(MAC_MII_STATUS) & 0x2)) - { - timeout--; - if (!timeout) - { - EOUT("sep_ether: MDIO timeout\n"); - break; - } - } + while ((sep_emac_read(MAC_MII_STATUS) & 0x2)) + { + timeout--; + if (!timeout) + { + EOUT("sep_ether: MDIO timeout\n"); + break; + } + } - return; + return; } - + /* * Write value to the a PHY register * Note: MDI interface is assumed to already have been enabled. */ static void write_phy(unsigned char phy_addr, unsigned char address, unsigned int value) { - unsigned short mii_txdata; - - mii_txdata = value; - sep_emac_write(MAC_MII_ADDRESS,(unsigned long)(address<<8) | phy_addr); - sep_emac_write(MAC_MII_TXDATA ,mii_txdata); - sep_emac_write(MAC_MII_CMD ,0x4); - udelay(40); + unsigned short mii_txdata; - sep_phy_wait(); + mii_txdata = value; + sep_emac_write(MAC_MII_ADDRESS,(unsigned long)(address<<8) | phy_addr); + sep_emac_write(MAC_MII_TXDATA ,mii_txdata); + sep_emac_write(MAC_MII_CMD ,0x4); + udelay(40); - return; + sep_phy_wait(); + + return; } - + /* * Read value stored in a PHY register. * Note: MDI interface is assumed to already have been enabled. */ static void read_phy(unsigned char phy_addr, unsigned char address, unsigned int *value) { - unsigned short mii_rxdata; -// unsigned long mii_status; - - sep_emac_write(MAC_MII_ADDRESS,(unsigned long)(address<<8) | phy_addr); - sep_emac_write(MAC_MII_CMD ,0x2); - udelay(40); - sep_phy_wait(); - - mii_rxdata = sep_emac_read(MAC_MII_RXDATA); - *value = mii_rxdata; + unsigned short mii_rxdata; +// unsigned long mii_status; - return; + sep_emac_write(MAC_MII_ADDRESS,(unsigned long)(address<<8) | phy_addr); + sep_emac_write(MAC_MII_CMD ,0x2); + udelay(40); + sep_phy_wait(); + + mii_rxdata = sep_emac_read(MAC_MII_RXDATA); + *value = mii_rxdata; + + return; } /* interrupt service routine */ void rt_dm9161_isr(int irqno, void *param) { - unsigned long intstatus; - rt_uint32_t address; + unsigned long intstatus; + rt_uint32_t address; - mask_irq(INTSRC_MAC); - intstatus = sep_emac_read(MAC_INTSRC); + mask_irq(INTSRC_MAC); + intstatus = sep_emac_read(MAC_INTSRC); - sep_emac_write(MAC_INTSRC,intstatus); - - /*Receive complete*/ - if(intstatus & 0x04) - { - eth_device_ready(&(dm9161_device.parent)); - } - /*Receive error*/ - else if(intstatus & 0x08) - { - rt_kprintf("Receive error\n"); - } - /*Transmit complete*/ - else if(intstatus & 0x03) - { - if(dm9161_device.tx_index == 0) - address = (MAC_TX_BD +(MAX_TX_DESCR-2)*8); - else if(dm9161_device.tx_index == 1) - address = (MAC_TX_BD +(MAX_TX_DESCR-1)*8); - else - address = (MAC_TX_BD + dm9161_device.tx_index*8-16); - //printk("free tx skb 0x%x in inter!!\n",lp->txBuffIndex); - sep_emac_write(address,0x0); - } - else if (intstatus & 0x10) - { - rt_kprintf("ROVER ERROR\n"); - } + sep_emac_write(MAC_INTSRC,intstatus); - while(intstatus) - { - sep_emac_write(MAC_INTSRC,intstatus); - intstatus = sep_emac_read(MAC_INTSRC); - } + /*Receive complete*/ + if(intstatus & 0x04) + { + eth_device_ready(&(dm9161_device.parent)); + } + /*Receive error*/ + else if(intstatus & 0x08) + { + rt_kprintf("Receive error\n"); + } + /*Transmit complete*/ + else if(intstatus & 0x03) + { + if(dm9161_device.tx_index == 0) + address = (MAC_TX_BD +(MAX_TX_DESCR-2)*8); + else if(dm9161_device.tx_index == 1) + address = (MAC_TX_BD +(MAX_TX_DESCR-1)*8); + else + address = (MAC_TX_BD + dm9161_device.tx_index*8-16); + //printk("free tx skb 0x%x in inter!!\n",lp->txBuffIndex); + sep_emac_write(address,0x0); + } + else if (intstatus & 0x10) + { + rt_kprintf("ROVER ERROR\n"); + } - unmask_irq(INTSRC_MAC); + while(intstatus) + { + sep_emac_write(MAC_INTSRC,intstatus); + intstatus = sep_emac_read(MAC_INTSRC); + } + + unmask_irq(INTSRC_MAC); } static rt_err_t update_mac_address() { - rt_uint32_t lo,hi; - hi = sep_emac_read(MAC_ADDR1); - lo = sep_emac_read(MAC_ADDR0); - DBOUT("Before MAC: hi=%x lo=%x\n",hi,lo); + rt_uint32_t lo,hi; + hi = sep_emac_read(MAC_ADDR1); + lo = sep_emac_read(MAC_ADDR0); + DBOUT("Before MAC: hi=%x lo=%x\n",hi,lo); - sep_emac_write(MAC_ADDR0,(dm9161_device.dev_addr[2] << 24) | (dm9161_device.dev_addr[3] << 16) | (dm9161_device.dev_addr[4] << 8) | (dm9161_device.dev_addr[5])); - sep_emac_write(MAC_ADDR1,dm9161_device.dev_addr[1]|(dm9161_device.dev_addr[0]<<8)); + sep_emac_write(MAC_ADDR0,(dm9161_device.dev_addr[2] << 24) | (dm9161_device.dev_addr[3] << 16) | (dm9161_device.dev_addr[4] << 8) | (dm9161_device.dev_addr[5])); + sep_emac_write(MAC_ADDR1,dm9161_device.dev_addr[1]|(dm9161_device.dev_addr[0]<<8)); - hi = sep_emac_read(MAC_ADDR1); - lo = sep_emac_read(MAC_ADDR0); - DBOUT("After MAC: hi=%x lo=%x\n",hi,lo); + hi = sep_emac_read(MAC_ADDR1); + lo = sep_emac_read(MAC_ADDR0); + DBOUT("After MAC: hi=%x lo=%x\n",hi,lo); - return RT_EOK; + return RT_EOK; } static int mii_link_ok(unsigned long phy_id) { - /* first, a dummy read, needed to latch some MII phys */ - unsigned int value; + /* first, a dummy read, needed to latch some MII phys */ + unsigned int value; - read_phy(phy_id, MII_BMSR,&value); - if (value & BMSR_LSTATUS) - return 1; + read_phy(phy_id, MII_BMSR,&value); + if (value & BMSR_LSTATUS) + return 1; - return 0; + return 0; } static void update_link_speed(unsigned short phy_addr) { - unsigned int bmsr, bmcr, lpa, mac_cfg; - unsigned int speed, duplex; + unsigned int bmsr, bmcr, lpa, mac_cfg; + unsigned int speed, duplex; - if (!mii_link_ok(phy_addr)) - { - EOUT("Link Down\n"); - //goto result; - } + if (!mii_link_ok(phy_addr)) + { + EOUT("Link Down\n"); + //goto result; + } - read_phy(phy_addr,MII_BMSR,&bmsr); - read_phy(phy_addr,MII_BMCR,&bmcr); + read_phy(phy_addr,MII_BMSR,&bmsr); + read_phy(phy_addr,MII_BMCR,&bmcr); - if (bmcr & BMCR_ANENABLE) /* AutoNegotiation is enabled */ - { - if (!(bmsr & BMSR_ANEGCOMPLETE)) /* Do nothing - another interrupt generated when negotiation complete */ - goto result; + if (bmcr & BMCR_ANENABLE) /* AutoNegotiation is enabled */ + { + if (!(bmsr & BMSR_ANEGCOMPLETE)) /* Do nothing - another interrupt generated when negotiation complete */ + goto result; + + read_phy(phy_addr, MII_LPA, &lpa); + + if ((lpa & LPA_100FULL) || (lpa & LPA_100HALF)) + speed = SPEED_100; + else + speed = SPEED_10; + + if ((lpa & LPA_100FULL) || (lpa & LPA_10FULL)) + duplex = DUPLEX_FULL; + else + duplex = DUPLEX_HALF; + } + else + { + speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10; + duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF; + } + + /* Update the MAC */ + mac_cfg = sep_emac_read(MAC_CTRL); + if (speed == SPEED_100) + { + mac_cfg |= 0x800; /* set speed 100 M */ + //bmcr &=(~0x2000); + //write_phy(lp->phy_address, MII_BMCR, bmcr); //将dm9161的速度设为10M + if (duplex == DUPLEX_FULL) /* 100 Full Duplex */ + mac_cfg |= 0x400; + else /* 100 Half Duplex */ + mac_cfg &= (~0x400); + } + else + { + mac_cfg &= (~0x800); /* set speed 10 M */ + + if (duplex == DUPLEX_FULL) /* 10 Full Duplex */ + mac_cfg |= 0x400; + else /* 10 Half Duplex */ + mac_cfg &= (~0x400); + } + + sep_emac_write(MAC_CTRL, mac_cfg); + rt_kprintf("Link now %i M-%s\n", speed, (duplex == DUPLEX_FULL) ? "FullDuplex" : "HalfDuplex"); - read_phy(phy_addr, MII_LPA, &lpa); - - if ((lpa & LPA_100FULL) || (lpa & LPA_100HALF)) - speed = SPEED_100; - else - speed = SPEED_10; - - if ((lpa & LPA_100FULL) || (lpa & LPA_10FULL)) - duplex = DUPLEX_FULL; - else - duplex = DUPLEX_HALF; - } - else - { - speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10; - duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF; - } - - /* Update the MAC */ - mac_cfg = sep_emac_read(MAC_CTRL); - if (speed == SPEED_100) - { - mac_cfg |= 0x800; /* set speed 100 M */ - //bmcr &=(~0x2000); - //write_phy(lp->phy_address, MII_BMCR, bmcr); //dm9161ٶΪ10M - if (duplex == DUPLEX_FULL) /* 100 Full Duplex */ - mac_cfg |= 0x400; - else /* 100 Half Duplex */ - mac_cfg &= (~0x400); - } - else - { - mac_cfg &= (~0x800); /* set speed 10 M */ - - if (duplex == DUPLEX_FULL) /* 10 Full Duplex */ - mac_cfg |= 0x400; - else /* 10 Half Duplex */ - mac_cfg &= (~0x400); - } - - sep_emac_write(MAC_CTRL, mac_cfg); - rt_kprintf("Link now %i M-%s\n", speed, (duplex == DUPLEX_FULL) ? "FullDuplex" : "HalfDuplex"); - result: - mac_cfg = sep_emac_read(MAC_CTRL); - DBOUT("After mac_cfg=%d\n",mac_cfg); - - return; + mac_cfg = sep_emac_read(MAC_CTRL); + DBOUT("After mac_cfg=%d\n",mac_cfg); + + return; } static rt_err_t rt_dm9161_open(rt_device_t dev, rt_uint16_t oflag); @@ -350,53 +346,53 @@ static rt_err_t rt_dm9161_open(rt_device_t dev, rt_uint16_t oflag); /* initialize the interface */ static rt_err_t rt_dm9161_init(rt_device_t dev) { - unsigned int phyid1, phyid2; - int detected = -1; - unsigned long phy_id; - unsigned short phy_address = 0; + unsigned int phyid1, phyid2; + int detected = -1; + unsigned long phy_id; + unsigned short phy_address = 0; - while ((detected != 0) && (phy_address < 32)) - { - /* Read the PHY ID registers */ - enable_mdi(); - read_phy(phy_address, MII_PHYSID1, &phyid1); - read_phy(phy_address, MII_PHYSID2, &phyid2); - - disable_mdi(); + while ((detected != 0) && (phy_address < 32)) + { + /* Read the PHY ID registers */ + enable_mdi(); + read_phy(phy_address, MII_PHYSID1, &phyid1); + read_phy(phy_address, MII_PHYSID2, &phyid2); - phy_id = (phyid1 << 16) | (phyid2 & 0xfff0); - switch (phy_id) - { - case MII_DM9161_ID: /* Davicom 9161: PHY_ID1 = 0x181, PHY_ID2 = B881 */ - case MII_DM9161A_ID: /* Davicom 9161A: PHY_ID1 = 0x181, PHY_ID2 = B8A0 */ - case MII_RTL8201_ID: /* Realtek RTL8201: PHY_ID1 = 0, PHY_ID2 = 0x8201 */ - case MII_BCM5221_ID: /* Broadcom BCM5221: PHY_ID1 = 0x40, PHY_ID2 = 0x61e0 */ - case MII_DP83847_ID: /* National Semiconductor DP83847: */ - case MII_AC101L_ID: /* Altima AC101L: PHY_ID1 = 0x22, PHY_ID2 = 0x5520 */ - case MII_KS8721_ID: /* Micrel KS8721: PHY_ID1 = 0x22, PHY_ID2 = 0x1610 */ - { - enable_mdi(); - #warning SHOULD SET MAC ADDR - //get_mac_address(dev); /* Get ethernet address and store it in dev->dev_addr */ - update_mac_address(); /* Program ethernet address into MAC */ - - //ùϣĴȽϵǰȺַȫ˫CRCУ飬֡ - sep_emac_write(MAC_CTRL, 0xa413); - #warning SHOULD DETERMIN LINK SPEED - update_link_speed(phy_address); - dm9161_device.phy_addr = phy_address; - disable_mdi(); - break; - } - - } + disable_mdi(); - phy_address++; - } + phy_id = (phyid1 << 16) | (phyid2 & 0xfff0); + switch (phy_id) + { + case MII_DM9161_ID: /* Davicom 9161: PHY_ID1 = 0x181, PHY_ID2 = B881 */ + case MII_DM9161A_ID: /* Davicom 9161A: PHY_ID1 = 0x181, PHY_ID2 = B8A0 */ + case MII_RTL8201_ID: /* Realtek RTL8201: PHY_ID1 = 0, PHY_ID2 = 0x8201 */ + case MII_BCM5221_ID: /* Broadcom BCM5221: PHY_ID1 = 0x40, PHY_ID2 = 0x61e0 */ + case MII_DP83847_ID: /* National Semiconductor DP83847: */ + case MII_AC101L_ID: /* Altima AC101L: PHY_ID1 = 0x22, PHY_ID2 = 0x5520 */ + case MII_KS8721_ID: /* Micrel KS8721: PHY_ID1 = 0x22, PHY_ID2 = 0x1610 */ + { + enable_mdi(); + #warning SHOULD SET MAC ADDR + //get_mac_address(dev); /* Get ethernet address and store it in dev->dev_addr */ + update_mac_address(); /* Program ethernet address into MAC */ - rt_dm9161_open(dev,0); + //用哈希寄存器比较当前群播地址，全双工，添加CRC校验，短数据帧进行填充 + sep_emac_write(MAC_CTRL, 0xa413); + #warning SHOULD DETERMIN LINK SPEED + update_link_speed(phy_address); + dm9161_device.phy_addr = phy_address; + disable_mdi(); + break; + } - return RT_EOK; + } + + phy_address++; + } + + rt_dm9161_open(dev,0); + + return RT_EOK; } /* ................................ MAC ................................ */ @@ -406,300 +402,300 @@ static rt_err_t rt_dm9161_init(rt_device_t dev) */ static void sepether_start(void) { - int i; - unsigned int tempaddr; - - sep_emac_write(MAC_TXBD_NUM,MAX_TX_DESCR); + int i; + unsigned int tempaddr; - //ʼͺͽ - for (i = 0; i < MAX_TX_DESCR; i++) - { - tempaddr=(MAC_TX_BD+i*8); - sep_emac_write(tempaddr,0); - tempaddr=(MAC_TX_BD+i*8+4); - sep_emac_write(tempaddr,0); - } - for (i = 0; i < MAX_RX_DESCR; i++) - { - tempaddr=(MAC_TX_BD + MAX_TX_DESCR*8+i*8); - sep_emac_write(tempaddr,0); - tempaddr=(MAC_TX_BD + MAX_TX_DESCR*8+i*8+4); - sep_emac_write(tempaddr,0); - } + sep_emac_write(MAC_TXBD_NUM,MAX_TX_DESCR); - for (i = 0; i < MAX_RX_DESCR; i++) - { - tempaddr=(MAC_TX_BD + MAX_TX_DESCR*8+i*8); - sep_emac_write(tempaddr,0xc000); - tempaddr=(MAC_TX_BD + MAX_TX_DESCR*8+i*8+4); - sep_emac_write(tempaddr,ESRAM_BASE+ MAX_TX_DESCR*0x600+i*0x600); - } + //初始化发送和接收描述符 + for (i = 0; i < MAX_TX_DESCR; i++) + { + tempaddr=(MAC_TX_BD+i*8); + sep_emac_write(tempaddr,0); + tempaddr=(MAC_TX_BD+i*8+4); + sep_emac_write(tempaddr,0); + } + for (i = 0; i < MAX_RX_DESCR; i++) + { + tempaddr=(MAC_TX_BD + MAX_TX_DESCR*8+i*8); + sep_emac_write(tempaddr,0); + tempaddr=(MAC_TX_BD + MAX_TX_DESCR*8+i*8+4); + sep_emac_write(tempaddr,0); + } - /* Set the Wrap bit on the last descriptor */ - tempaddr=(MAC_TX_BD + MAX_TX_DESCR*8+i*8-8); - sep_emac_write(tempaddr,0xe000); + for (i = 0; i < MAX_RX_DESCR; i++) + { + tempaddr=(MAC_TX_BD + MAX_TX_DESCR*8+i*8); + sep_emac_write(tempaddr,0xc000); + tempaddr=(MAC_TX_BD + MAX_TX_DESCR*8+i*8+4); + sep_emac_write(tempaddr,ESRAM_BASE+ MAX_TX_DESCR*0x600+i*0x600); + } - for (i = 0; i < MAX_TX_DESCR; i++) - { - tempaddr=(MAC_TX_BD+i*8); - sep_emac_write(tempaddr,0x0); - tempaddr=(MAC_TX_BD+i*8+4); - sep_emac_write(tempaddr,ESRAM_BASE+i*0x600); - } - - return; + /* Set the Wrap bit on the last descriptor */ + tempaddr=(MAC_TX_BD + MAX_TX_DESCR*8+i*8-8); + sep_emac_write(tempaddr,0xe000); + + for (i = 0; i < MAX_TX_DESCR; i++) + { + tempaddr=(MAC_TX_BD+i*8); + sep_emac_write(tempaddr,0x0); + tempaddr=(MAC_TX_BD+i*8+4); + sep_emac_write(tempaddr,ESRAM_BASE+i*0x600); + } + + return; } static rt_err_t rt_dm9161_open(rt_device_t dev, rt_uint16_t oflag) { - unsigned int dsintr; + unsigned int dsintr; - enable_mdi(); - mask_irq(28); + enable_mdi(); + mask_irq(28); - sep_emac_write(MAC_INTMASK,0x0); //ж + sep_emac_write(MAC_INTMASK,0x0); //首先屏蔽中断 - sepether_start(); + sepether_start(); - /* Enable PHY interrupt */ - *(volatile unsigned long*)GPIO_PORTA_DIR |= 0x0080 ; //1 stands for in - *(volatile unsigned long*)GPIO_PORTA_SEL |= 0x0080 ; //for common use - *(volatile unsigned long*)GPIO_PORTA_INCTL |= 0x0080; //ж뷽ʽ - *(volatile unsigned long*)GPIO_PORTA_INTRCTL |= (0x3UL<<14); //жΪ͵ƽⷢ - *(volatile unsigned long*)GPIO_PORTA_INTRCLR |= 0x0080; //ж - *(volatile unsigned long*)GPIO_PORTA_INTRCLR = 0x0000; //ж + /* Enable PHY interrupt */ + *(volatile unsigned long*)GPIO_PORTA_DIR |= 0x0080 ; //1 stands for in + *(volatile unsigned long*)GPIO_PORTA_SEL |= 0x0080 ; //for common use + *(volatile unsigned long*)GPIO_PORTA_INCTL |= 0x0080; //中断输入方式 + *(volatile unsigned long*)GPIO_PORTA_INTRCTL |= (0x3UL<<14); //中断类型为低电平解发 + *(volatile unsigned long*)GPIO_PORTA_INTRCLR |= 0x0080; //清除中断 + *(volatile unsigned long*)GPIO_PORTA_INTRCLR = 0x0000; //清除中断 - rt_hw_interrupt_install(INTSRC_MAC, rt_dm9161_isr, RT_NULL, "EMAC"); - enable_irq(INTSRC_EXINT7); + rt_hw_interrupt_install(INTSRC_MAC, rt_dm9161_isr, RT_NULL, "EMAC"); + enable_irq(INTSRC_EXINT7); - read_phy(dm9161_device.phy_addr, MII_DSINTR_REG, &dsintr); - dsintr = dsintr & ~0xf00; /* clear bits 8..11 */ - write_phy(dm9161_device.phy_addr, MII_DSINTR_REG, dsintr); + read_phy(dm9161_device.phy_addr, MII_DSINTR_REG, &dsintr); + dsintr = dsintr & ~0xf00; /* clear bits 8..11 */ + write_phy(dm9161_device.phy_addr, MII_DSINTR_REG, dsintr); - update_link_speed(dm9161_device.phy_addr); - - - /************************************************************************************/ - /* Enable MAC interrupts */ - sep_emac_write(MAC_INTMASK,0xff); //openж - sep_emac_write(MAC_INTSRC,0xff); //clear all mac irq - unmask_irq(28); - disable_mdi(); - - rt_kprintf("SEP4020 ethernet interface open!\n\r"); + update_link_speed(dm9161_device.phy_addr); - return RT_EOK; + + /************************************************************************************/ + /* Enable MAC interrupts */ + sep_emac_write(MAC_INTMASK,0xff); //open中断 + sep_emac_write(MAC_INTSRC,0xff); //clear all mac irq + unmask_irq(28); + disable_mdi(); + + rt_kprintf("SEP4020 ethernet interface open!\n\r"); + + return RT_EOK; } static rt_err_t rt_dm9161_close(rt_device_t dev) { - rt_kprintf("SEP4020 ethernet interface close!\n\r"); - - /* Disable Receiver and Transmitter */ - disable_mdi(); - #warning disable ether; - -// INT_ENABLE(28); - /* Disable PHY interrupt */ -// disable_phyirq(dev); - - /* Disable MAC interrupts */ - sep_emac_write(MAC_INTMASK,0); //ж + rt_kprintf("SEP4020 ethernet interface close!\n\r"); -// INT_DISABLE(28); - - return RT_EOK; + /* Disable Receiver and Transmitter */ + disable_mdi(); + #warning disable ether; + +// INT_ENABLE(28); + /* Disable PHY interrupt */ +// disable_phyirq(dev); + + /* Disable MAC interrupts */ + sep_emac_write(MAC_INTMASK,0); //屏蔽中断 + +// INT_DISABLE(28); + + return RT_EOK; } static rt_size_t rt_dm9161_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); + rt_set_errno(-RT_ENOSYS); - return 0; + return 0; } static rt_size_t rt_dm9161_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); + rt_set_errno(-RT_ENOSYS); - return 0; + return 0; } static rt_err_t rt_dm9161_control(rt_device_t dev, int cmd, void *args) { - return RT_EOK; + return RT_EOK; } /* ethernet device interface */ /* transmit packet. */ rt_err_t rt_dm9161_tx( rt_device_t dev, struct pbuf* p) { - rt_uint8_t i; - rt_uint32_t length = 0; - struct pbuf *q; - unsigned long address; - unsigned long tmp_tx_bd; + rt_uint8_t i; + rt_uint32_t length = 0; + struct pbuf *q; + unsigned long address; + unsigned long tmp_tx_bd; - /* lock DM9000 device */ -// rt_sem_take(&sem_lock, RT_WAITING_FOREVER); + /* lock DM9000 device */ +// rt_sem_take(&sem_lock, RT_WAITING_FOREVER); - /* disable dm9000a interrupt */ - #warning SHOULD DISABLE INTEERUPT? + /* disable dm9000a interrupt */ + #warning SHOULD DISABLE INTEERUPT? - /*Search for available BD*/ - for (i = 0;ipayload,q->len); - length += q->len; - q = q->next; - } + /*Search for available BD*/ + for (i = 0;ipayload,q->len); + length += q->len; + q = q->next; + } - length = length << 16; + #warning SHOULD NOTICE IT'S LENGTH - if (i == MAX_TX_DESCR - 1) - length |= 0xb800; - else - length |= 0x9800; + length = length << 16; - address = (MAC_TX_BD + i*8); - dm9161_device.tx_index = i; - sep_emac_write(address,length); + if (i == MAX_TX_DESCR - 1) + length |= 0xb800; + else + length |= 0x9800; - //wait for tranfer complete - while(!(sep_emac_read(address)&0x8000)); + address = (MAC_TX_BD + i*8); + dm9161_device.tx_index = i; + sep_emac_write(address,length); - /* unlock DM9000 device */ + //wait for tranfer complete + while(!(sep_emac_read(address)&0x8000)); + + /* unlock DM9000 device */ // rt_sem_release(&sem_lock); - /* wait ack */ + /* wait ack */ // rt_sem_take(&sem_ack, RT_WAITING_FOREVER); - return RT_EOK; + return RT_EOK; } /* reception packet. */ struct pbuf *rt_dm9161_rx(rt_device_t dev) { - unsigned int temp_rx_bd,address; - rt_uint32_t i = 0; - rt_uint32_t length; - unsigned char *p_recv; - struct pbuf* p = RT_NULL; + unsigned int temp_rx_bd,address; + rt_uint32_t i = 0; + rt_uint32_t length; + unsigned char *p_recv; + struct pbuf* p = RT_NULL; - /* lock DM9000 device */ - rt_sem_take(&sem_lock, RT_WAITING_FOREVER); + /* lock DM9000 device */ + rt_sem_take(&sem_lock, RT_WAITING_FOREVER); - while (1) - { - - address = MAC_TX_BD + (MAX_TX_DESCR + i) * 8; - temp_rx_bd = sep_emac_read(address); - - if (!(temp_rx_bd & 0x8000)) - { - length = temp_rx_bd; - length = length >> 16; + while (1) + { - p_recv = (unsigned char *)(ESRAM_BASE + (MAX_TX_DESCR + i) * 0x600); - p = pbuf_alloc(PBUF_LINK,length,PBUF_RAM); - if (p != RT_NULL) - { - struct pbuf *q; - rt_int32_t len; + address = MAC_TX_BD + (MAX_TX_DESCR + i) * 8; + temp_rx_bd = sep_emac_read(address); - for (q = p; q != RT_NULL; q = q->next) - { - rt_memcpy((rt_uint8_t *)(q->payload),p_recv,q->len); - } - } - else - { - rt_kprintf("Droping %d packet \n",length); - } + if (!(temp_rx_bd & 0x8000)) + { + length = temp_rx_bd; + length = length >> 16; - if(i == (MAX_RX_DESCR-1)) - { - sep_emac_write(address,0xe000); - i = 0; - } - else - { - sep_emac_write(address,0xc000); - i++; - } - } - else - break; - } + p_recv = (unsigned char *)(ESRAM_BASE + (MAX_TX_DESCR + i) * 0x600); + p = pbuf_alloc(PBUF_LINK,length,PBUF_RAM); + if (p != RT_NULL) + { + struct pbuf *q; + rt_int32_t len; - rt_sem_release(&sem_lock); + for (q = p; q != RT_NULL; q = q->next) + { + rt_memcpy((rt_uint8_t *)(q->payload),p_recv,q->len); + } + } + else + { + rt_kprintf("Droping %d packet \n",length); + } - return p; + if(i == (MAX_RX_DESCR-1)) + { + sep_emac_write(address,0xe000); + i = 0; + } + else + { + sep_emac_write(address,0xc000); + i++; + } + } + else + break; + } + + rt_sem_release(&sem_lock); + + return p; } void rt_hw_dm9161_init() { - rt_sem_init(&sem_ack, "tx_ack", 1, RT_IPC_FLAG_FIFO); - rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO); + rt_sem_init(&sem_ack, "tx_ack", 1, RT_IPC_FLAG_FIFO); + rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO); - dm9161_device.type = TYPE_DM9161; - dm9161_device.mode = DM9161_AUTO; - dm9161_device.packet_cnt = 0; - dm9161_device.queue_packet_len = 0; + dm9161_device.type = TYPE_DM9161; + dm9161_device.mode = DM9161_AUTO; + dm9161_device.packet_cnt = 0; + dm9161_device.queue_packet_len = 0; - /* - * SRAM Tx/Rx pointer automatically return to start address, - * Packet Transmitted, Packet Received - */ - #warning NOTICE: - //dm9161_device.imr_all = IMR_PAR | IMR_PTM | IMR_PRM; + /* + * SRAM Tx/Rx pointer automatically return to start address, + * Packet Transmitted, Packet Received + */ + #warning NOTICE: + //dm9161_device.imr_all = IMR_PAR | IMR_PTM | IMR_PRM; - dm9161_device.dev_addr[0] = 0x01; - dm9161_device.dev_addr[1] = 0x60; - dm9161_device.dev_addr[2] = 0x6E; - dm9161_device.dev_addr[3] = 0x11; - dm9161_device.dev_addr[4] = 0x02; - dm9161_device.dev_addr[5] = 0x0F; + dm9161_device.dev_addr[0] = 0x01; + dm9161_device.dev_addr[1] = 0x60; + dm9161_device.dev_addr[2] = 0x6E; + dm9161_device.dev_addr[3] = 0x11; + dm9161_device.dev_addr[4] = 0x02; + dm9161_device.dev_addr[5] = 0x0F; - dm9161_device.parent.parent.init = rt_dm9161_init; - dm9161_device.parent.parent.open = rt_dm9161_open; - dm9161_device.parent.parent.close = rt_dm9161_close; - dm9161_device.parent.parent.read = rt_dm9161_read; - dm9161_device.parent.parent.write = rt_dm9161_write; - dm9161_device.parent.parent.control = rt_dm9161_control; - dm9161_device.parent.parent.user_data = RT_NULL; + dm9161_device.parent.parent.init = rt_dm9161_init; + dm9161_device.parent.parent.open = rt_dm9161_open; + dm9161_device.parent.parent.close = rt_dm9161_close; + dm9161_device.parent.parent.read = rt_dm9161_read; + dm9161_device.parent.parent.write = rt_dm9161_write; + dm9161_device.parent.parent.control = rt_dm9161_control; + dm9161_device.parent.parent.user_data = RT_NULL; - dm9161_device.parent.eth_rx = rt_dm9161_rx; - dm9161_device.parent.eth_tx = rt_dm9161_tx; + dm9161_device.parent.eth_rx = rt_dm9161_rx; + dm9161_device.parent.eth_tx = rt_dm9161_tx; - eth_device_init(&(dm9161_device.parent), "e0"); + eth_device_init(&(dm9161_device.parent), "e0"); - /* instal interrupt */ - #warning TODO - //rt_hw_interrupt_install(INTEINT4_7, rt_dm9161_isr, RT_NULL); - //rt_hw_interrupt_umask(INTEINT4_7); + /* instal interrupt */ + #warning TODO + //rt_hw_interrupt_install(INTEINT4_7, rt_dm9161_isr, RT_NULL); + //rt_hw_interrupt_umask(INTEINT4_7); } void dm9161a(void) diff --git a/bsp/mini4020/drivers/dm9161.h b/bsp/mini4020/drivers/dm9161.h index 620f8653bc..5b63508aaa 100644 --- a/bsp/mini4020/drivers/dm9161.h +++ b/bsp/mini4020/drivers/dm9161.h @@ -1,11 +1,7 @@ /* - * File : dm9161.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -21,15 +17,15 @@ /* Davicom 9161 PHY */ #define MII_DM9161_ID 0x0181b880 #define MII_DM9161A_ID 0x0181b8a0 - + /* Davicom specific registers */ #define MII_DSCR_REG 16 #define MII_DSCSR_REG 17 #define MII_DSINTR_REG 21 - + /* Intel LXT971A PHY */ #define MII_LXT971A_ID 0x001378E0 - + /* Intel specific registers */ #define MII_ISINTE_REG 18 #define MII_ISINTS_REG 19 @@ -37,41 +33,41 @@ /* Realtek RTL8201 PHY */ #define MII_RTL8201_ID 0x00008200 - + /* Broadcom BCM5221 PHY */ #define MII_BCM5221_ID 0x004061e0 - + /* Broadcom specific registers */ #define MII_BCMINTR_REG 26 - + /* National Semiconductor DP83847 */ #define MII_DP83847_ID 0x20005c30 - + /* Altima AC101L PHY */ #define MII_AC101L_ID 0x00225520 - + /* Micrel KS8721 PHY */ #define MII_KS8721_ID 0x00221610 - + /* ........................................................................ */ - + #define MAX_RBUFF_SZ 0x600 /* 1518 rounded up */ #define MAX_RX_DESCR 20 /* max number of receive buffers */ - + #define MAX_TBUFF_SZ 0x600 /* 1518 rounded up */ #define MAX_TX_DESCR 20 /* max number of receive buffers */ - + #define EMAC_DESC_DONE 0x00000001 /* bit for if DMA is done */ #define EMAC_DESC_WRAP 0x00000002 /* bit for wrap */ - + #define EMAC_BROADCAST 0x80000000 /* broadcast address */ #define EMAC_MULTICAST 0x40000000 /* multicast address */ #define EMAC_UNICAST 0x20000000 /* unicast address */ - -#define DM9161_inb(r) (*(volatile rt_uint8_t *)r) -#define DM9161_outb(r, d) (*(volatile rt_uint8_t *)r = d) -#define DM9161_inw(r) (*(volatile rt_uint16_t *)r) -#define DM9161_outw(r, d) (*(volatile rt_uint16_t *)r = d) + +#define DM9161_inb(r) (*(volatile rt_uint8_t *)r) +#define DM9161_outb(r, d) (*(volatile rt_uint8_t *)r = d) +#define DM9161_inw(r) (*(volatile rt_uint16_t *)r) +#define DM9161_outw(r, d) (*(volatile rt_uint16_t *)r = d) void rt_hw_dm9616_init(void); diff --git a/bsp/mini4020/drivers/lcd.c b/bsp/mini4020/drivers/lcd.c index f9799d9ef7..c325764953 100644 --- a/bsp/mini4020/drivers/lcd.c +++ b/bsp/mini4020/drivers/lcd.c @@ -1,11 +1,7 @@ /* - * File : lcd.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -56,7 +52,7 @@ void radio_rtgui_init(void) _rtgui_lcd_driver.bits_per_pixel = 16; _rtgui_lcd_driver.width = 320; _rtgui_lcd_driver.height = 240; - + _rtgui_lcd_driver.ops = &_rtgui_graphic_driver_ops; //_rtgui_lcd_driver.screen_update = lcd_update; @@ -67,7 +63,7 @@ void radio_rtgui_init(void) rt_memset((char*)pVideoBuffer,0xff,320*240*2); //rt_memcpy((char*)pVideoBuffer,pic,320*240*2); //TESTING IMAGE - //˴ + //此处待修正 /* add lcd driver into graphic driver */ // rtgui_graphic_driver_add(&_rtgui_lcd_driver); } diff --git a/bsp/mini4020/drivers/lcdc.c b/bsp/mini4020/drivers/lcdc.c index d468eebd91..4be34518ba 100644 --- a/bsp/mini4020/drivers/lcdc.c +++ b/bsp/mini4020/drivers/lcdc.c @@ -1,11 +1,7 @@ /* - * File : lcdc.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -23,20 +19,20 @@ rt_err_t sep4020_lcd_init(void) { pVideoBuffer =(unsigned long)rt_malloc(LCDWIDTH * LCDHEIGHT * 2); - *(RP)GPIO_PORTC_SEL |= 0X0008; //Portc8Ϊͨÿ - *(RP)GPIO_PORTC_DIR &= (~0X0008); //Portc8Ϊ - *(RP)GPIO_PORTC_DATA |= 0X0008; //Portc8ߵƽ + *(RP)GPIO_PORTC_SEL |= 0X0008; //Portc8设置为通用口 + *(RP)GPIO_PORTC_DIR &= (~0X0008); //Portc8设置为输出 + *(RP)GPIO_PORTC_DATA |= 0X0008; //Portc8输出高电平 - writel(0x00000000,LCDC_LECR); //LCDC - writel(pVideoBuffer,LCDC_SSA); //lcd֡ʼַ + writel(0x00000000,LCDC_LECR); //禁用LCDC + writel(pVideoBuffer,LCDC_SSA); //lcd数据帧的起始地址 writel(YMAX | XMAX,LCDC_SIZE); writel(TFT|COLOR|PBSIZE|BPIX|PIXPOL|FLMPOL|LPPOL|CLKPOL|OEPOL|END_SEL|ACD_SEL|ACD|PCD,LCDC_PCR); writel(H_WIDTH|H_WAIT_1|H_WAIT_2,LCDC_HCR); writel(V_WIDTH|PASS_FRAME_WAIT|V_WAIT_1|V_WAIT_2,LCDC_VCR); writel(SCR|CC_EN|PW,LCDC_PWMR); writel(BL|HM|TM,LCDC_DMACR); - writel(0x00000001,LCDC_LECR); //ʹLCDC - writel(0x00000000,LCDC_LCDISREN); //жڼ֡һһʱãLCD֮һʱ + writel(0x00000001,LCDC_LECR); //使能LCDC + writel(0x00000000,LCDC_LCDISREN); //中断在加载帧的最后一个或第一个数据时设置，到LCD之间会有一个延时 return RT_EOK; } diff --git a/bsp/mini4020/drivers/lcdc.h b/bsp/mini4020/drivers/lcdc.h index 4b361e502c..39a88e82e0 100644 --- a/bsp/mini4020/drivers/lcdc.h +++ b/bsp/mini4020/drivers/lcdc.h @@ -1,11 +1,7 @@ /* - * File : lcdc.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -29,40 +25,40 @@ //Macro for PCR register setting #define TFT ((U32)1 << 31) -#define COLOR (1 << 30) //1Ϊɫ. +#define COLOR (1 << 30) //1为色彩. #define PBSIZE (0 << 28) -#define BPIX (4 << 25) //洢һضӦ16bit -#define PIXPOL (0 << 24) //ؼԡصļ,Ч //0<<24 -#define FLMPOL (1 << 23) //б־ԡб־ļ,Ч. -#define LPPOL (1 << 22) //弫ԡźŵļ,Ч. -#define CLKPOL (0 << 21) //LCD λʱӼԡLCD λʱӵЧصļ,½Ч. -#define OEPOL (1 << 20) //ʹܼԡʹźŵļ,Ч. -#define END_SEL (0 << 18) //ӡڰʽѡ,Сӡڰ. -#define ACD_SEL (0 << 15) //ACDʱԴѡѡ任ʱ,ʹFLM ΪACD ʱ -#define ACD (0 << 8 ) //ģʽ. +#define BPIX (4 << 25) //存储器中一个像素对应16bit +#define PIXPOL (0 << 24) //像素极性—设置像素的极性,高有效 //0<<24 +#define FLMPOL (1 << 23) //首行标志极性—设置首行标志的极性,低有效. +#define LPPOL (1 << 22) //行脉冲极性—设置行脉冲信号的极性,低有效. +#define CLKPOL (0 << 21) //LCD 移位时钟极性—设置LCD 移位时钟的有效沿的极性,下降延有效. +#define OEPOL (1 << 20) //输出使能极性—设置输出使能信号的极性,高有效. +#define END_SEL (0 << 18) //印第安格式选择,小印第安. +#define ACD_SEL (0 << 15) //ACD时钟源选择—选择晶向变换计数器的时钟,使用FLM 作为ACD 计数时钟 +#define ACD (0 << 8 ) //被动模式. #define PCD (10) -//Macro for HCR regiter setting //ˮƽüĴ. +//Macro for HCR regiter setting //水平配置寄存器. #define H_WIDTH ((U32)46 << 26) #define H_WAIT_1 (20 << 8) #define H_WAIT_2 (20) -//Macro for VCR register setting //ֱüĴ. +//Macro for VCR register setting //垂直配置寄存器. #define V_WIDTH ((U32)10 << 26) #define PASS_FRAME_WAIT (0 <<16) #define V_WAIT_1 (3 << 8) #define V_WAIT_2 (3) //Macro for LGPR register setting -#define GRAY (4) //Ҷȵȼ. +#define GRAY (4) //灰度等级. //Macro for PWMR register setting -#define SCR (0 << 9) //ʱԴѡ.. -#define CC_EN (0 << 8) //Աȶȿʹ,. -#define PW (64) //Ŀ, +#define SCR (0 << 9) //时钟源选择.行脉冲. +#define CC_EN (0 << 8) //对比度控制使能,关. +#define PW (64) //输出脉冲数目, //Macro for DMACR register setting -#define BL ((U32)1 << 31) //̶. +#define BL ((U32)1 << 31) //固定长度. #define HM (7 << 16) #define TM (3) diff --git a/bsp/mini4020/drivers/mii.h b/bsp/mini4020/drivers/mii.h index 617550bfd9..b58d8bf56f 100644 --- a/bsp/mini4020/drivers/mii.h +++ b/bsp/mini4020/drivers/mii.h @@ -1,11 +1,7 @@ /* - * File : mii.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -25,7 +21,7 @@ #define MII_EXPANSION 0x06 /* Expansion register */ #define MII_CTRL1000 0x09 /* 1000BASE-T control */ #define MII_STAT1000 0x0a /* 1000BASE-T status */ -#define MII_ESTATUS 0x0f /* Extended Status */ +#define MII_ESTATUS 0x0f /* Extended Status */ #define MII_DCOUNTER 0x12 /* Disconnect counter */ #define MII_FCSCOUNTER 0x13 /* False carrier counter */ #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ @@ -40,7 +36,7 @@ /* Basic mode control register. */ #define BMCR_RESV 0x003f /* Unused... */ -#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ +#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ #define BMCR_CTST 0x0080 /* Collision test */ #define BMCR_FULLDPLX 0x0100 /* Full duplex */ #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ @@ -59,9 +55,9 @@ #define BMSR_RFAULT 0x0010 /* Remote fault detected */ #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ #define BMSR_RESV 0x00c0 /* Unused... */ -#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ -#define BMSR_100FULL2 0x0200 /* Can do 100BASE-T2 HDX */ -#define BMSR_100HALF2 0x0400 /* Can do 100BASE-T2 FDX */ +#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ +#define BMSR_100FULL2 0x0200 /* Can do 100BASE-T2 HDX */ +#define BMSR_100HALF2 0x0400 /* Can do 100BASE-T2 FDX */ #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ #define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ #define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ @@ -88,7 +84,7 @@ #define ADVERTISE_NPAGE 0x8000 /* Next page bit */ #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ - ADVERTISE_CSMA) + ADVERTISE_CSMA) #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ ADVERTISE_100HALF | ADVERTISE_100FULL) @@ -110,8 +106,8 @@ #define LPA_LPACK 0x4000 /* Link partner acked us */ #define LPA_NPAGE 0x8000 /* Next page bit */ -#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) -#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) +#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) +#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) /* Expansion register for auto-negotiation. */ #define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */ @@ -121,8 +117,8 @@ #define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */ #define EXPANSION_RESV 0xffe0 /* Unused... */ -#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ -#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ +#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ +#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ /* N-way test register. */ #define NWAYTEST_RESV1 0x00ff /* Unused... */ diff --git a/bsp/mini4020/drivers/sdcard.c b/bsp/mini4020/drivers/sdcard.c index 78c1306a0d..52c3b5cd82 100644 --- a/bsp/mini4020/drivers/sdcard.c +++ b/bsp/mini4020/drivers/sdcard.c @@ -1,11 +1,7 @@ /* - * File : sdcard.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2007 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -62,7 +58,7 @@ static void delay(U32 j) for (i = 0; i < j; i++) { - /* nothing */ + /* nothing */ } } diff --git a/bsp/mini4020/drivers/sdcard.h b/bsp/mini4020/drivers/sdcard.h index c8a4acf1a1..6f2db415d0 100644 --- a/bsp/mini4020/drivers/sdcard.h +++ b/bsp/mini4020/drivers/sdcard.h @@ -1,11 +1,7 @@ /* - * File : sdcard.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/nios_ii/application.c b/bsp/nios_ii/application.c index eedd990a18..a8422dcc46 100644 --- a/bsp/nios_ii/application.c +++ b/bsp/nios_ii/application.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/nios_ii/board.c b/bsp/nios_ii/board.c index d9609c1cec..dfe0abc38e 100644 --- a/bsp/nios_ii/board.c +++ b/bsp/nios_ii/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/nios_ii/board.h b/bsp/nios_ii/board.h index 218dfd372a..4953258665 100644 --- a/bsp/nios_ii/board.h +++ b/bsp/nios_ii/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/nios_ii/startup.c b/bsp/nios_ii/startup.c index 76983e346d..fd2f909aa2 100644 --- a/bsp/nios_ii/startup.c +++ b/bsp/nios_ii/startup.c @@ -1,11 +1,7 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/nrf51822/Libraries/nrf51822/Include/compiler_abstraction.h b/bsp/nrf51822/Libraries/nrf51822/Include/compiler_abstraction.h new file mode 100644 index 0000000000..c239fd11cd --- /dev/null +++ b/bsp/nrf51822/Libraries/nrf51822/Include/compiler_abstraction.h @@ -0,0 +1,255 @@ +/* + +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef _COMPILER_ABSTRACTION_H +#define _COMPILER_ABSTRACTION_H + +/*lint ++flb "Enter library region" */ + +#ifndef NRF_STRING_CONCATENATE_IMPL + #define NRF_STRING_CONCATENATE_IMPL(lhs, rhs) lhs ## rhs +#endif +#ifndef NRF_STRING_CONCATENATE + #define NRF_STRING_CONCATENATE(lhs, rhs) NRF_STRING_CONCATENATE_IMPL(lhs, rhs) +#endif + +#if defined ( __CC_ARM ) + + #ifndef __ASM + #define __ASM __asm + #endif + + #ifndef __INLINE + #define __INLINE __inline + #endif + + #ifndef __WEAK + #define __WEAK __weak + #endif + + #ifndef __ALIGN + #define __ALIGN(n) __align(n) + #endif + + #ifndef __PACKED + #define __PACKED __packed + #endif + + #ifndef __UNUSED + #define __UNUSED __attribute__((unused)) + #endif + + #define GET_SP() __current_sp() + + #ifndef NRF_STATIC_ASSERT + #define NRF_STATIC_ASSERT(cond, msg) \ + ;enum { NRF_STRING_CONCATENATE(static_assert_on_line_, __LINE__) = 1 / (!!(cond)) } + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + + #ifndef __ASM + #define __ASM __asm + #endif + + #ifndef __INLINE + #define __INLINE __inline + #endif + + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + + #ifndef __ALIGN + #define __ALIGN(n) __attribute__((aligned(n))) + #endif + + #ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) + #endif + + #ifndef __UNUSED + #define __UNUSED __attribute__((unused)) + #endif + + #define GET_SP() __current_sp() + + #ifndef NRF_STATIC_ASSERT + #ifdef __cplusplus + #ifndef _Static_assert + #define _Static_assert static_assert + #endif + #endif + #define NRF_STATIC_ASSERT(cond, msg) _Static_assert(cond, msg) + #endif + +#elif defined ( __ICCARM__ ) + + #ifndef __ASM + #define __ASM __asm + #endif + + #ifndef __INLINE + #define __INLINE inline + #endif + + #ifndef __WEAK + #define __WEAK __weak + #endif + + #if (__VER__ >= 8000000) + #ifndef __ALIGN + #define __ALIGN(n) __attribute__((aligned(x))) + #endif + + #ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) + #endif + #else + #ifndef __ALIGN + #define STRING_PRAGMA(x) _Pragma(#x) + #define __ALIGN(n) STRING_PRAGMA(data_alignment = n) + #endif + + #ifndef __PACKED + #define __PACKED __packed + #endif + #endif + + #ifndef __UNUSED + #define __UNUSED + #endif + + #define GET_SP() __get_SP() + + #ifndef NRF_STATIC_ASSERT + #define NRF_STATIC_ASSERT(cond, msg) static_assert(cond, msg) + #endif + +#elif defined ( __GNUC__ ) || defined ( __clang__ ) + + #ifndef __ASM + #define __ASM __asm + #endif + + #ifndef __INLINE + #define __INLINE inline + #endif + + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + + #ifndef __ALIGN + #define __ALIGN(n) __attribute__((aligned(n))) + #endif + + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + + #ifndef __UNUSED + #define __UNUSED __attribute__((unused)) + #endif + + #define GET_SP() gcc_current_sp() + + static inline unsigned int gcc_current_sp(void) + { + unsigned int stack_pointer = 0; + __asm__ __volatile__ ("mov %0, sp" : "=r"(stack_pointer)); + return stack_pointer; + } + + #ifndef NRF_STATIC_ASSERT + #ifdef __cplusplus + #ifndef _Static_assert + #define _Static_assert static_assert + #endif + #endif + #define NRF_STATIC_ASSERT(cond, msg) _Static_assert(cond, msg) + #endif + +#elif defined ( __TASKING__ ) + + #ifndef __ASM + #define __ASM __asm + #endif + + #ifndef __INLINE + #define __INLINE inline + #endif + + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + + #ifndef __ALIGN + #define __ALIGN(n) __align(n) + #endif + + /* Not defined for TASKING. */ + #ifndef __PACKED + #define __PACKED + #endif + + #ifndef __UNUSED + #define __UNUSED __attribute__((unused)) + #endif + + #define GET_SP() __get_MSP() + + #ifndef NRF_STATIC_ASSERT + #define NRF_STATIC_ASSERT(cond, msg) static_assert(cond, msg) + #endif + +#endif + +#define NRF_MDK_VERSION_ASSERT_AT_LEAST(major, minor, micro) \ + NRF_STATIC_ASSERT( \ + ( \ + (major < MDK_MAJOR_VERSION) || \ + (major == MDK_MAJOR_VERSION && minor < MDK_MINOR_VERSION) || \ + (major == MDK_MAJOR_VERSION && minor == MDK_MINOR_VERSION && micro < MDK_MICRO_VERSION) \ + ), "MDK version mismatch.") + +#define NRF_MDK_VERSION_ASSERT_EXACT(major, minor, micro) \ + NRF_STATIC_ASSERT( \ + ( \ + (major != MDK_MAJOR_VERSION) || \ + (major != MDK_MAJOR_VERSION) || \ + (major != MDK_MAJOR_VERSION) \ + ), "MDK version mismatch.") + +/*lint --flb "Leave library region" */ + +#endif diff --git a/bsp/nrf51822/Libraries/nrf51822/Include/nrf.h b/bsp/nrf51822/Libraries/nrf51822/Include/nrf.h new file mode 100644 index 0000000000..6f47bd4211 --- /dev/null +++ b/bsp/nrf51822/Libraries/nrf51822/Include/nrf.h @@ -0,0 +1,189 @@ +/* + +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF_H +#define NRF_H + +/* MDK version */ +#define MDK_MAJOR_VERSION 8 +#define MDK_MINOR_VERSION 38 +#define MDK_MICRO_VERSION 0 + + +/* Define coprocessor domains */ +#if defined (NRF5340_XXAA_APPLICATION) || defined (NRF5340_XXAA_NETWORK) + #ifndef NRF5340_XXAA + #define NRF5340_XXAA + #endif +#endif +#if defined (NRF5340_XXAA_APPLICATION) + #ifndef NRF_APPLICATION + #define NRF_APPLICATION + #endif +#endif +#if defined (NRF5340_XXAA_NETWORK) + #ifndef NRF_NETWORK + #define NRF_NETWORK + #endif +#endif + +/* Apply compatibility macros for old nRF5340 macros */ +#if defined(NRF5340_XXAA) + #if defined (NRF_APPLICATION) + #ifndef NRF5340_XXAA_APPLICATION + #define NRF5340_XXAA_APPLICATION + #endif + #endif + #if defined (NRF_NETWORK) + #ifndef NRF5340_XXAA_NETWORK + #define NRF5340_XXAA_NETWORK + #endif + #endif +#endif + +/* Define NRF51_SERIES for common use in nRF51 series devices. Only if not previously defined. */ +#if defined (NRF51) ||\ + defined (NRF51422_XXAA) ||\ + defined (NRF51422_XXAB) ||\ + defined (NRF51422_XXAC) ||\ + defined (NRF51801_XXAB) ||\ + defined (NRF51802_XXAA) ||\ + defined (NRF51822_XXAA) ||\ + defined (NRF51822_XXAB) ||\ + defined (NRF51822_XXAC) ||\ + defined (NRF51824_XXAA) + #ifndef NRF51_SERIES + #define NRF51_SERIES + #endif + #ifndef NRF51 + #define NRF51 + #endif +#endif + +/* Redefine "old" too-generic name NRF52 to NRF52832_XXAA to keep backwards compatibility. */ +#if defined (NRF52) + #ifndef NRF52832_XXAA + #define NRF52832_XXAA + #endif +#endif + +/* Define NRF52_SERIES for common use in nRF52 series devices. Only if not previously defined. */ +#if defined (NRF52805_XXAA) || defined (NRF52810_XXAA) || defined (NRF52811_XXAA) || defined (NRF52820_XXAA) || defined (NRF52832_XXAA) || defined (NRF52832_XXAB) || defined (NRF52833_XXAA) || defined (NRF52840_XXAA) + #ifndef NRF52_SERIES + #define NRF52_SERIES + #endif +#endif + +/* Define NRF53_SERIES for common use in nRF53 series devices. */ +#if defined (NRF5340_XXAA) + #ifndef NRF53_SERIES + #define NRF53_SERIES + #endif +#endif + +/* Define NRF91_SERIES for common use in nRF91 series devices. */ +#if defined (NRF9160_XXAA) + #ifndef NRF91_SERIES + #define NRF91_SERIES + #endif +#endif + +/* Device selection for device includes. */ +#if defined (NRF51) + #include "nrf51.h" + #include "nrf51_bitfields.h" + #include "nrf51_deprecated.h" + +#elif defined (NRF52805_XXAA) + #include "nrf52805.h" + #include "nrf52805_bitfields.h" + #include "nrf51_to_nrf52810.h" + #include "nrf52_to_nrf52810.h" + #include "nrf52810_to_nrf52811.h" +#elif defined (NRF52810_XXAA) + #include "nrf52810.h" + #include "nrf52810_bitfields.h" + #include "nrf51_to_nrf52810.h" + #include "nrf52_to_nrf52810.h" + #include "nrf52810_name_change.h" +#elif defined (NRF52811_XXAA) + #include "nrf52811.h" + #include "nrf52811_bitfields.h" + #include "nrf51_to_nrf52810.h" + #include "nrf52_to_nrf52810.h" + #include "nrf52810_to_nrf52811.h" +#elif defined (NRF52820_XXAA) + #include "nrf52820.h" + #include "nrf52820_bitfields.h" + #include "nrf51_to_nrf52.h" + #include "nrf52_to_nrf52833.h" + #include "nrf52833_to_nrf52820.h" +#elif defined (NRF52832_XXAA) || defined (NRF52832_XXAB) + #include "nrf52.h" + #include "nrf52_bitfields.h" + #include "nrf51_to_nrf52.h" + #include "nrf52_name_change.h" +#elif defined (NRF52833_XXAA) + #include "nrf52833.h" + #include "nrf52833_bitfields.h" + #include "nrf52_to_nrf52833.h" + #include "nrf51_to_nrf52.h" +#elif defined (NRF52840_XXAA) + #include "nrf52840.h" + #include "nrf52840_bitfields.h" + #include "nrf51_to_nrf52840.h" + #include "nrf52_to_nrf52840.h" + +#elif defined (NRF5340_XXAA) + #if defined(NRF_APPLICATION) + #include "nrf5340_application.h" + #include "nrf5340_application_bitfields.h" + #include "nrf5340_application_name_change.h" + #elif defined (NRF_NETWORK) + #include "nrf5340_network.h" + #include "nrf5340_network_bitfields.h" + #include "nrf5340_network_name_change.h" + #endif + +#elif defined (NRF9160_XXAA) + #include "nrf9160.h" + #include "nrf9160_bitfields.h" + #include "nrf9160_name_change.h" + +#else + #error "Device must be defined. See nrf.h." +#endif /* NRF51, NRF52805_XXAA, NRF52810_XXAA, NRF52811_XXAA, NRF52820_XXAA, NRF52832_XXAA, NRF52832_XXAB, NRF52833_XXAA, NRF52840_XXAA, NRF5340_XXAA_APPLICATION, NRF5340_XXAA_NETWORK, NRF9160_XXAA */ + +#include "compiler_abstraction.h" + +#endif /* NRF_H */ + diff --git a/bsp/nrf51822/Libraries/nrf51822/Include/nrf51_deprecated.h b/bsp/nrf51822/Libraries/nrf51822/Include/nrf51_deprecated.h new file mode 100644 index 0000000000..a59e9d479b --- /dev/null +++ b/bsp/nrf51822/Libraries/nrf51822/Include/nrf51_deprecated.h @@ -0,0 +1,446 @@ +/* + +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF51_DEPRECATED_H +#define NRF51_DEPRECATED_H + +/*lint ++flb "Enter library region */ + +/* This file is given to prevent your SW from not compiling with the updates made to nrf51.h and + * nrf51_bitfields.h. The macros defined in this file were available previously. Do not use these + * macros on purpose. Use the ones defined in nrf51.h and nrf51_bitfields.h instead. + */ + +/* NVMC */ +/* The register ERASEPROTECTEDPAGE is called ERASEPCR0 in the documentation. */ +#define ERASEPROTECTEDPAGE ERASEPCR0 + + +/* LPCOMP */ +/* The interrupt ISR was renamed. Adding old name to the macros. */ +#define LPCOMP_COMP_IRQHandler LPCOMP_IRQHandler +#define LPCOMP_COMP_IRQn LPCOMP_IRQn +/* Corrected typo in RESULT register. */ +#define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below + + +/* MPU */ +/* The field MPU.PERR0.LPCOMP_COMP was renamed. Added into deprecated in case somebody was using the macros defined for it. */ +#define MPU_PERR0_LPCOMP_COMP_Pos MPU_PERR0_LPCOMP_Pos +#define MPU_PERR0_LPCOMP_COMP_Msk MPU_PERR0_LPCOMP_Msk +#define MPU_PERR0_LPCOMP_COMP_InRegion1 MPU_PERR0_LPCOMP_InRegion1 +#define MPU_PERR0_LPCOMP_COMP_InRegion0 MPU_PERR0_LPCOMP_InRegion0 + + +/* POWER */ +/* The field POWER.RAMON.OFFRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */ +#define POWER_RAMON_OFFRAM3_Pos (19UL) +#define POWER_RAMON_OFFRAM3_Msk (0x1UL << POWER_RAMON_OFFRAM3_Pos) +#define POWER_RAMON_OFFRAM3_RAM3Off (0UL) +#define POWER_RAMON_OFFRAM3_RAM3On (1UL) +/* The field POWER.RAMON.OFFRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */ +#define POWER_RAMON_OFFRAM2_Pos (18UL) +#define POWER_RAMON_OFFRAM2_Msk (0x1UL << POWER_RAMON_OFFRAM2_Pos) +#define POWER_RAMON_OFFRAM2_RAM2Off (0UL) +#define POWER_RAMON_OFFRAM2_RAM2On (1UL) +/* The field POWER.RAMON.ONRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */ +#define POWER_RAMON_ONRAM3_Pos (3UL) +#define POWER_RAMON_ONRAM3_Msk (0x1UL << POWER_RAMON_ONRAM3_Pos) +#define POWER_RAMON_ONRAM3_RAM3Off (0UL) +#define POWER_RAMON_ONRAM3_RAM3On (1UL) +/* The field POWER.RAMON.ONRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */ +#define POWER_RAMON_ONRAM2_Pos (2UL) +#define POWER_RAMON_ONRAM2_Msk (0x1UL << POWER_RAMON_ONRAM2_Pos) +#define POWER_RAMON_ONRAM2_RAM2Off (0UL) +#define POWER_RAMON_ONRAM2_RAM2On (1UL) + + +/* RADIO */ +/* The enumerated value RADIO.TXPOWER.TXPOWER.Neg40dBm was renamed. Added into deprecated with the new macro name. */ +#define RADIO_TXPOWER_TXPOWER_Neg40dBm RADIO_TXPOWER_TXPOWER_Neg30dBm +/* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */ +#define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos +#define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk +#define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include +#define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip +/* The name of the field PLLLOCK was corrected. Old macros added for compatibility. */ +#define RADIO_TEST_PLL_LOCK_Pos RADIO_TEST_PLLLOCK_Pos +#define RADIO_TEST_PLL_LOCK_Msk RADIO_TEST_PLLLOCK_Msk +#define RADIO_TEST_PLL_LOCK_Disabled RADIO_TEST_PLLLOCK_Disabled +#define RADIO_TEST_PLL_LOCK_Enabled RADIO_TEST_PLLLOCK_Enabled +/* The name of the field CONSTCARRIER was corrected. Old macros added for compatibility. */ +#define RADIO_TEST_CONST_CARRIER_Pos RADIO_TEST_CONSTCARRIER_Pos +#define RADIO_TEST_CONST_CARRIER_Msk RADIO_TEST_CONSTCARRIER_Msk +#define RADIO_TEST_CONST_CARRIER_Disabled RADIO_TEST_CONSTCARRIER_Disabled +#define RADIO_TEST_CONST_CARRIER_Enabled RADIO_TEST_CONSTCARRIER_Enabled + + +/* FICR */ +/* The registers FICR.SIZERAMBLOCK0, FICR.SIZERAMBLOCK1, FICR.SIZERAMBLOCK2 and FICR.SIZERAMBLOCK3 were renamed into an array. */ +#define SIZERAMBLOCK0 SIZERAMBLOCKS +#define SIZERAMBLOCK1 SIZERAMBLOCKS +#define SIZERAMBLOCK2 SIZERAMBLOCK[2] /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */ +#define SIZERAMBLOCK3 SIZERAMBLOCK[3] /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */ +/* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */ +#define DEVICEID0 DEVICEID[0] +#define DEVICEID1 DEVICEID[1] +/* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */ +#define ER0 ER[0] +#define ER1 ER[1] +#define ER2 ER[2] +#define ER3 ER[3] +/* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */ +#define IR0 IR[0] +#define IR1 IR[1] +#define IR2 IR[2] +#define IR3 IR[3] +/* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */ +#define DEVICEADDR0 DEVICEADDR[0] +#define DEVICEADDR1 DEVICEADDR[1] + + +/* PPI */ +/* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */ +#define TASKS_CHG0EN TASKS_CHG[0].EN +#define TASKS_CHG0DIS TASKS_CHG[0].DIS +#define TASKS_CHG1EN TASKS_CHG[1].EN +#define TASKS_CHG1DIS TASKS_CHG[1].DIS +#define TASKS_CHG2EN TASKS_CHG[2].EN +#define TASKS_CHG2DIS TASKS_CHG[2].DIS +#define TASKS_CHG3EN TASKS_CHG[3].EN +#define TASKS_CHG3DIS TASKS_CHG[3].DIS +/* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */ +#define CH0_EEP CH[0].EEP +#define CH0_TEP CH[0].TEP +#define CH1_EEP CH[1].EEP +#define CH1_TEP CH[1].TEP +#define CH2_EEP CH[2].EEP +#define CH2_TEP CH[2].TEP +#define CH3_EEP CH[3].EEP +#define CH3_TEP CH[3].TEP +#define CH4_EEP CH[4].EEP +#define CH4_TEP CH[4].TEP +#define CH5_EEP CH[5].EEP +#define CH5_TEP CH[5].TEP +#define CH6_EEP CH[6].EEP +#define CH6_TEP CH[6].TEP +#define CH7_EEP CH[7].EEP +#define CH7_TEP CH[7].TEP +#define CH8_EEP CH[8].EEP +#define CH8_TEP CH[8].TEP +#define CH9_EEP CH[9].EEP +#define CH9_TEP CH[9].TEP +#define CH10_EEP CH[10].EEP +#define CH10_TEP CH[10].TEP +#define CH11_EEP CH[11].EEP +#define CH11_TEP CH[11].TEP +#define CH12_EEP CH[12].EEP +#define CH12_TEP CH[12].TEP +#define CH13_EEP CH[13].EEP +#define CH13_TEP CH[13].TEP +#define CH14_EEP CH[14].EEP +#define CH14_TEP CH[14].TEP +#define CH15_EEP CH[15].EEP +#define CH15_TEP CH[15].TEP +/* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */ +#define CHG0 CHG[0] +#define CHG1 CHG[1] +#define CHG2 CHG[2] +#define CHG3 CHG[3] +/* All bitfield macros for the CHGx registers therefore changed name. */ +#define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included +#define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included +#define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included +#define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included +#define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included +#define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included +#define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included +#define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included +#define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included +#define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included +#define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included +#define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included +#define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included +#define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included +#define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included +#define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included +#define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included +#define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included +#define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included +#define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included +#define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included +#define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included +#define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included +#define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included +#define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included +#define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included +#define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included +#define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included +#define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included +#define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included +#define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included +#define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included +#define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included +#define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included +#define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included +#define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included +#define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included +#define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included +#define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included +#define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included +#define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included +#define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included +#define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included +#define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included +#define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included +#define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included +#define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included +#define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included +#define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included +#define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included +#define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included +#define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included +#define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included +#define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included +#define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included +#define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included +#define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included +#define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included +#define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included +#define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included +#define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included +#define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included +#define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included +#define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included + +/* SPIS */ +/* nRF51 devices do not have an SPIS0, only SPIS1. SPIS0_EASYDMA_MAXCNT_SIZE was therefore renamed. */ +#define SPIS0_EASYDMA_MAXCNT_SIZE SPIS1_EASYDMA_MAXCNT_SIZE + + + +/*lint --flb "Leave library region" */ + +#endif /* NRF51_DEPRECATED_H */ + diff --git a/bsp/nrf51822/Libraries/nrf51822/Include/system_nrf51.h b/bsp/nrf51822/Libraries/nrf51822/Include/system_nrf51.h index ae613609dd..9db78f961c 100644 --- a/bsp/nrf51822/Libraries/nrf51822/Include/system_nrf51.h +++ b/bsp/nrf51822/Libraries/nrf51822/Include/system_nrf51.h @@ -1,32 +1,25 @@ -/* Copyright (c) 2013, Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * * Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ +/* + +Copyright (c) 2009-2021 ARM Limited. All rights reserved. + + SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the License); you may +not use this file except in compliance with the License. +You may obtain a copy of the License at + + www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an AS IS BASIS, WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +NOTICE: This file has been modified by Nordic Semiconductor ASA. + +*/ + #ifndef SYSTEM_NRF51_H #define SYSTEM_NRF51_H @@ -56,7 +49,7 @@ extern void SystemInit (void); * @param none * @return none * - * @brief Updates the SystemCoreClock with current core Clock + * @brief Updates the SystemCoreClock with current core Clock * retrieved from cpu registers. */ extern void SystemCoreClockUpdate (void); diff --git a/bsp/nrf51822/Libraries/nrf51822/Source/templates/arm/arm_startup_nrf51.s b/bsp/nrf51822/Libraries/nrf51822/Source/templates/arm/arm_startup_nrf51.s index e06b1423b2..cad23a6595 100644 --- a/bsp/nrf51822/Libraries/nrf51822/Source/templates/arm/arm_startup_nrf51.s +++ b/bsp/nrf51822/Libraries/nrf51822/Source/templates/arm/arm_startup_nrf51.s @@ -1,42 +1,55 @@ -; Copyright (c) 2013, Nordic Semiconductor ASA -; All rights reserved. +; Copyright (c) 2009-2021 ARM Limited. All rights reserved. ; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: +; SPDX-License-Identifier: Apache-2.0 ; -; * Redistributions of source code must retain the above copyright notice, this -; list of conditions and the following disclaimer. +; Licensed under the Apache License, Version 2.0 (the License); you may +; not use this file except in compliance with the License. +; You may obtain a copy of the License at ; -; * Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. +; www.apache.org/licenses/LICENSE-2.0 ; -; * Neither the name of Nordic Semiconductor ASA nor the names of its -; contributors may be used to endorse or promote products derived from -; this software without specific prior written permission. +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an AS IS BASIS, WITHOUT +; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. ; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -; NOTE: Template files (including this one) are application specific and therefore -; expected to be copied into the application project folder prior to its use! +; NOTICE: This file has been modified by Nordic Semiconductor ASA. -; Description message + IF :DEF: __STARTUP_CONFIG +#ifdef __STARTUP_CONFIG +#include "startup_config.h" +#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT +#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3 +#endif +#endif + ENDIF -Stack_Size EQU 0x00000400 - AREA STACK, NOINIT, READWRITE, ALIGN=3 + IF :DEF: __STARTUP_CONFIG +Stack_Size EQU __STARTUP_CONFIG_STACK_SIZE + ELIF :DEF: __STACK_SIZE +Stack_Size EQU __STACK_SIZE + ELSE +Stack_Size EQU 2048 + ENDIF + + IF :DEF: __STARTUP_CONFIG +Stack_Align EQU __STARTUP_CONFIG_STACK_ALIGNEMENT + ELSE +Stack_Align EQU 3 + ENDIF + + AREA STACK, NOINIT, READWRITE, ALIGN=Stack_Align Stack_Mem SPACE Stack_Size __initial_sp -Heap_Size EQU 0x00000000 + IF :DEF: __STARTUP_CONFIG +Heap_Size EQU __STARTUP_CONFIG_HEAP_SIZE + ELIF :DEF: __HEAP_SIZE +Heap_Size EQU __HEAP_SIZE + ELSE +Heap_Size EQU 2048 + ENDIF AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base @@ -54,9 +67,9 @@ __heap_limit EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler + DCD Reset_Handler + DCD NMI_Handler + DCD HardFault_Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved @@ -64,46 +77,45 @@ __Vectors DCD __initial_sp ; Top of Stack DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler + DCD SVC_Handler DCD 0 ; Reserved DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler + DCD PendSV_Handler + DCD SysTick_Handler ; External Interrupts - DCD POWER_CLOCK_IRQHandler ;POWER_CLOCK - DCD RADIO_IRQHandler ;RADIO - DCD UART0_IRQHandler ;UART0 - DCD SPI0_TWI0_IRQHandler ;SPI0_TWI0 - DCD SPI1_TWI1_IRQHandler ;SPI1_TWI1 - DCD 0 ;Reserved - DCD GPIOTE_IRQHandler ;GPIOTE - DCD ADC_IRQHandler ;ADC - DCD TIMER0_IRQHandler ;TIMER0 - DCD TIMER1_IRQHandler ;TIMER1 - DCD TIMER2_IRQHandler ;TIMER2 - DCD RTC0_IRQHandler ;RTC0 - DCD TEMP_IRQHandler ;TEMP - DCD RNG_IRQHandler ;RNG - DCD ECB_IRQHandler ;ECB - DCD CCM_AAR_IRQHandler ;CCM_AAR - DCD WDT_IRQHandler ;WDT - DCD RTC1_IRQHandler ;RTC1 - DCD QDEC_IRQHandler ;QDEC - DCD LPCOMP_IRQHandler ;LPCOMP - DCD SWI0_IRQHandler ;SWI0 - DCD SWI1_IRQHandler ;SWI1 - DCD SWI2_IRQHandler ;SWI2 - DCD SWI3_IRQHandler ;SWI3 - DCD SWI4_IRQHandler ;SWI4 - DCD SWI5_IRQHandler ;SWI5 - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - + DCD POWER_CLOCK_IRQHandler + DCD RADIO_IRQHandler + DCD UART0_IRQHandler + DCD SPI0_TWI0_IRQHandler + DCD SPI1_TWI1_IRQHandler + DCD 0 ; Reserved + DCD GPIOTE_IRQHandler + DCD ADC_IRQHandler + DCD TIMER0_IRQHandler + DCD TIMER1_IRQHandler + DCD TIMER2_IRQHandler + DCD RTC0_IRQHandler + DCD TEMP_IRQHandler + DCD RNG_IRQHandler + DCD ECB_IRQHandler + DCD CCM_AAR_IRQHandler + DCD WDT_IRQHandler + DCD RTC1_IRQHandler + DCD QDEC_IRQHandler + DCD LPCOMP_IRQHandler + DCD SWI0_IRQHandler + DCD SWI1_IRQHandler + DCD SWI2_IRQHandler + DCD SWI3_IRQHandler + DCD SWI4_IRQHandler + DCD SWI5_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved __Vectors_End @@ -113,16 +125,16 @@ __Vectors_Size EQU __Vectors_End - __Vectors ; Reset Handler -NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address -NRF_POWER_RAMONB_ADDRESS EQU 0x40000554 ; NRF_POWER->RAMONB address -NRF_POWER_RAMONx_RAMxON_ONMODE_Msk EQU 0x3 ; All RAM blocks on in onmode bit mask +NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address +NRF_POWER_RAMONB_ADDRESS EQU 0x40000554 ; NRF_POWER->RAMONB address +NRF_POWER_RAMONx_RAMxON_ONMODE_Msk EQU 0x3 ; All RAM blocks on in onmode bit mask Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main - - MOVS R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk + + MOVS R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk LDR R0, =NRF_POWER_RAMON_ADDRESS LDR R2, [R0] @@ -133,7 +145,7 @@ Reset_Handler PROC LDR R2, [R0] ORRS R2, R2, R1 STR R2, [R0] - + LDR R0, =SystemInit BLX R0 LDR R0, =__main @@ -216,7 +228,6 @@ SWI2_IRQHandler SWI3_IRQHandler SWI4_IRQHandler SWI5_IRQHandler - B . ENDP ALIGN @@ -224,7 +235,7 @@ SWI5_IRQHandler ; User Initial Stack & Heap IF :DEF:__MICROLIB - + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -233,17 +244,18 @@ SWI5_IRQHandler IMPORT __use_two_region_memory EXPORT __user_initial_stackheap -__user_initial_stackheap + +__user_initial_stackheap PROC LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDP ALIGN ENDIF END - diff --git a/bsp/nrf51822/Libraries/nrf51822/Source/templates/system_nrf51.c b/bsp/nrf51822/Libraries/nrf51822/Source/templates/system_nrf51.c index 712114e6c1..3c036c8cbd 100644 --- a/bsp/nrf51822/Libraries/nrf51822/Source/templates/system_nrf51.c +++ b/bsp/nrf51822/Libraries/nrf51822/Source/templates/system_nrf51.c @@ -1,39 +1,32 @@ -/* Copyright (c) 2013, Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * * Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ +/* -/* NOTE: Template files (including this one) are application specific and therefore expected to +Copyright (c) 2009-2021 ARM Limited. All rights reserved. + + SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the License); you may +not use this file except in compliance with the License. +You may obtain a copy of the License at + + www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an AS IS BASIS, WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +NOTICE: This file has been modified by Nordic Semiconductor ASA. + +*/ + +/* NOTE: Template files (including this one) are application specific and therefore expected to be copied into the application project folder prior to its use! */ #include #include #include "nrf.h" +#include "nrf_erratas.h" #include "system_nrf51.h" /*lint ++flb "Enter library region" */ @@ -41,12 +34,8 @@ #define __SYSTEM_CLOCK (16000000UL) /*!< nRF51 devices use a fixed System Clock Frequency of 16MHz */ -static bool is_manual_peripheral_setup_needed(void); -static bool is_disabled_in_debug_needed(void); - - #if defined ( __CC_ARM ) - uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK; + uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK; #elif defined ( __ICCARM__ ) __root uint32_t SystemCoreClock = __SYSTEM_CLOCK; #elif defined ( __GNUC__ ) @@ -65,57 +54,36 @@ void SystemInit(void) /* Prepare the peripherals for use as indicated by the PAN 26 "System: Manual setup is required to enable the use of peripherals" found at Product Anomaly document for your device found at - https://www.nordicsemi.com/. The side effect of executing these instructions in the devices + https://infocenter.nordicsemi.com/index.jsp The side effect of executing these instructions in the devices that do not need it is that the new peripherals in the second generation devices (LPCOMP for example) will not be available. */ - if (is_manual_peripheral_setup_needed()) + if (nrf51_errata_26()) { *(uint32_t volatile *)0x40000504 = 0xC007FFDF; *(uint32_t volatile *)0x40006C18 = 0x00008000; } - + /* Disable PROTENSET registers under debug, as indicated by PAN 59 "MPU: Reset value of DISABLEINDEBUG - register is incorrect" found at Product Anomaly document four your device found at - https://www.nordicsemi.com/. There is no side effect of using these instruction if not needed. */ - if (is_disabled_in_debug_needed()) + register is incorrect" found at Product Anomaly document for your device found at + https://infocenter.nordicsemi.com/index.jsp There is no side effect of using these instruction if not needed. */ + if (nrf51_errata_59()) { NRF_MPU->DISABLEINDEBUG = MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos; } -} - -static bool is_manual_peripheral_setup_needed(void) -{ - if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) - { - if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x00) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) - { - return true; - } - if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x10) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) - { - return true; - } - if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) - { - return true; + /* Execute the following code to eliminate excessive current in sleep mode with RAM retention in nRF51802 devices, + as indicated by PAN 76 "System: Excessive current in sleep mode with retention" found at Product Anomaly document + for your device found at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf51_errata_76()){ + if (*(uint32_t volatile *)0x4006EC00 != 1){ + *(uint32_t volatile *)0x4006EC00 = 0x9375; + while (*(uint32_t volatile *)0x4006EC00 != 1){ + } } + *(uint32_t volatile *)0x4006EC14 = 0xC0; } - - return false; -} -static bool is_disabled_in_debug_needed(void) -{ - if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) - { - if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) - { - return true; - } - } - - return false; + SystemCoreClockUpdate(); } /*lint --flb "Leave library region" */ diff --git a/bsp/nrf51822/applications/application.c b/bsp/nrf51822/applications/application.c index 355c843156..4ff4507306 100644 --- a/bsp/nrf51822/applications/application.c +++ b/bsp/nrf51822/applications/application.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/nrf51822/drivers/SConscript b/bsp/nrf51822/drivers/SConscript index 638846d656..cba5bbfffc 100644 --- a/bsp/nrf51822/drivers/SConscript +++ b/bsp/nrf51822/drivers/SConscript @@ -3,7 +3,7 @@ Import('rtconfig') from building import * # get current directory -cwd = GetCurrentDir() +cwd = GetCurrentDir() src = Glob('*.c') CPPPATH = [cwd] diff --git a/bsp/nrf51822/drivers/board.c b/bsp/nrf51822/drivers/board.c index 933e2237cc..978a9aa675 100644 --- a/bsp/nrf51822/drivers/board.c +++ b/bsp/nrf51822/drivers/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * */ @@ -80,7 +76,7 @@ void RTC0_IRQHandler(void) */ void rt_hw_board_init() { - lfclk_config(); + //lfclk_config(); rtc_config(); NRF_RTC0->TASKS_START = 1; /* Initial usart deriver, and set console device */ diff --git a/bsp/nrf51822/drivers/board.h b/bsp/nrf51822/drivers/board.h index 83cd5f9eb6..59f0c03898 100644 --- a/bsp/nrf51822/drivers/board.h +++ b/bsp/nrf51822/drivers/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * */ diff --git a/bsp/nrf51822/drivers/uart.c b/bsp/nrf51822/drivers/uart.c index a959bf50c2..a7b017a949 100644 --- a/bsp/nrf51822/drivers/uart.c +++ b/bsp/nrf51822/drivers/uart.c @@ -1,11 +1,7 @@ /* - * File : uart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015 RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * */ @@ -72,7 +68,7 @@ static rt_err_t rt_uart_init (rt_device_t dev) NRF_UART0->CONFIG = (UART_CONFIG_HWFC_Enabled << UART_CONFIG_HWFC_Pos); } - NRF_UART0->BAUDRATE = (UART_BAUDRATE_BAUDRATE_Baud38400 << UART_BAUDRATE_BAUDRATE_Pos); + NRF_UART0->BAUDRATE = (UART_BAUDRATE_BAUDRATE_Baud115200 << UART_BAUDRATE_BAUDRATE_Pos); NRF_UART0->ENABLE = (UART_ENABLE_ENABLE_Enabled << UART_ENABLE_ENABLE_Pos); NRF_UART0->TASKS_STARTTX = 1; NRF_UART0->TASKS_STARTRX = 1; diff --git a/bsp/nrf51822/drivers/uart.h b/bsp/nrf51822/drivers/uart.h index 5ad910d3aa..48d950365c 100644 --- a/bsp/nrf51822/drivers/uart.h +++ b/bsp/nrf51822/drivers/uart.h @@ -1,11 +1,7 @@ /* - * File : uart.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * */ @@ -14,10 +10,10 @@ -#define RX_PIN_NUMBER 23 +#define RX_PIN_NUMBER 25 #define TX_PIN_NUMBER 24 -#define CTS_PIN_NUMBER 25 -#define RTS_PIN_NUMBER 22 +#define CTS_PIN_NUMBER 26 +#define RTS_PIN_NUMBER 27 #define HWFC false diff --git a/bsp/nrf51822/project.uvoptx b/bsp/nrf51822/project.uvoptx new file mode 100644 index 0000000000..2557e6d7b4 --- /dev/null +++ b/bsp/nrf51822/project.uvoptx @@ -0,0 +1,640 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 5 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U480200710 -O78 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0nrf51xxx.flm -FS00 -FL0200000 -FP0($$Device:nRF51822_xxAA$Flash\nrf51xxx.flm) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0nrf51xxx -FS00 -FL0200000 -FP0($$Device:nRF51822_xxAA$Flash\nrf51xxx.flm)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 10000000 + + + + + + Applications + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + applications\startup.c + startup.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + applications\application.c + application.c + 0 + 0 + + + + + CPU + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\..\libcpu\arm\common\div0.c + div0.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\..\libcpu\arm\common\showmem.c + showmem.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ..\..\libcpu\arm\common\backtrace.c + backtrace.c + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\libcpu\arm\cortex-m0\cpuport.c + cpuport.c + 0 + 0 + + + 2 + 7 + 2 + 0 + 0 + 0 + ..\..\libcpu\arm\cortex-m0\context_rvds.S + context_rvds.S + 0 + 0 + + + + + DeviceDrivers + 1 + 0 + 0 + 0 + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\dataqueue.c + dataqueue.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\workqueue.c + workqueue.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\ringblk_buf.c + ringblk_buf.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\completion.c + completion.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\pipe.c + pipe.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\ringbuffer.c + ringbuffer.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\waitqueue.c + waitqueue.c + 0 + 0 + + + + + Drivers + 1 + 0 + 0 + 0 + + 4 + 15 + 1 + 0 + 0 + 0 + drivers\board.c + board.c + 0 + 0 + + + 4 + 16 + 1 + 0 + 0 + 0 + drivers\uart.c + uart.c + 0 + 0 + + + 4 + 17 + 1 + 0 + 0 + 0 + Libraries\nrf51822\Source\templates\system_nrf51.c + system_nrf51.c + 0 + 0 + + + 4 + 18 + 2 + 0 + 0 + 0 + Libraries\nrf51822\Source\templates\arm\arm_startup_nrf51.s + arm_startup_nrf51.s + 0 + 0 + + + + + finsh + 1 + 0 + 0 + 0 + + 5 + 19 + 1 + 0 + 0 + 0 + ..\..\components\finsh\shell.c + shell.c + 0 + 0 + + + 5 + 20 + 1 + 0 + 0 + 0 + ..\..\components\finsh\msh.c + msh.c + 0 + 0 + + + 5 + 21 + 1 + 0 + 0 + 0 + ..\..\components\finsh\cmd.c + cmd.c + 0 + 0 + + + + + Kernel + 1 + 0 + 0 + 0 + + 6 + 22 + 1 + 0 + 0 + 0 + ..\..\src\kservice.c + kservice.c + 0 + 0 + + + 6 + 23 + 1 + 0 + 0 + 0 + ..\..\src\device.c + device.c + 0 + 0 + + + 6 + 24 + 1 + 0 + 0 + 0 + ..\..\src\components.c + components.c + 0 + 0 + + + 6 + 25 + 1 + 0 + 0 + 0 + ..\..\src\thread.c + thread.c + 0 + 0 + + + 6 + 26 + 1 + 0 + 0 + 0 + ..\..\src\object.c + object.c + 0 + 0 + + + 6 + 27 + 1 + 0 + 0 + 0 + ..\..\src\idle.c + idle.c + 0 + 0 + + + 6 + 28 + 1 + 0 + 0 + 0 + ..\..\src\mem.c + mem.c + 0 + 0 + + + 6 + 29 + 1 + 0 + 0 + 0 + ..\..\src\ipc.c + ipc.c + 0 + 0 + + + 6 + 30 + 1 + 0 + 0 + 0 + ..\..\src\irq.c + irq.c + 0 + 0 + + + 6 + 31 + 1 + 0 + 0 + 0 + ..\..\src\timer.c + timer.c + 0 + 0 + + + 6 + 32 + 1 + 0 + 0 + 0 + ..\..\src\clock.c + clock.c + 0 + 0 + + + 6 + 33 + 1 + 0 + 0 + 0 + ..\..\src\scheduler.c + scheduler.c + 0 + 0 + + + 6 + 34 + 1 + 0 + 0 + 0 + ..\..\src\mempool.c + mempool.c + 0 + 0 + + + + diff --git a/bsp/nrf51822/project.uvproj b/bsp/nrf51822/project.uvprojx similarity index 78% rename from bsp/nrf51822/project.uvproj rename to bsp/nrf51822/project.uvprojx index de8e9fc084..c4d044488b 100644 --- a/bsp/nrf51822/project.uvproj +++ b/bsp/nrf51822/project.uvprojx @@ -1,41 +1,46 @@ + 2.1 +
### uVision Project, (C) Keil Software
+ rt-thread 0x4 ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 nRF51822_xxAA Nordic Semiconductor - NordicSemiconductor.nRF_DeviceFamilyPack.1.1.4 - http://developer.nordicsemi.com/nRF51_SDK/pieces/nRF_DeviceFamilyPack/ + NordicSemiconductor.nRF_DeviceFamilyPack.8.38.0 + http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/ IROM(0x00000000,0x40000) IRAM(0x20000000,0x4000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE - - + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0nrf51xxx -FS00 -FL0200000 -FP0($$Device:nRF51822_xxAA$Flash\nrf51xxx.flm)) 0 $$Device:nRF51822_xxAA$Device\Include\nrf.h - - - - - - - - - + + + + + + + + + $$Device:nRF51822_xxAA$SVD\nrf51.xml 0 0 - - - - - + + + + + 0 0 @@ -57,8 +62,8 @@ 0 0 - - + + 0 0 0 @@ -67,8 +72,8 @@ 0 0 - - + + 0 0 0 @@ -77,13 +82,15 @@ 0 0 - - + + 0 0 + 0 + 0 0 - + 0 @@ -97,8 +104,8 @@ 0 0 3 - - + + 1 @@ -119,47 +126,6 @@ 0 16 - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 0 - 1 - - 0 - 6 - - - - - - - - - - - - - - Segger\JL2CM3.dll - @@ -173,10 +139,10 @@ 1 BIN\UL2CM3.DLL "" () - - - - + + + + 0 @@ -209,7 +175,7 @@ 0 0 "Cortex-M0" - + 0 0 0 @@ -218,12 +184,14 @@ 0 0 0 + 0 0 0 8 0 0 0 + 0 3 3 0 @@ -340,7 +308,7 @@ 0x0 - + 1 @@ -357,12 +325,20 @@ 0 0 0 + 0 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 --c99 - NRF51, USE_STDPERIPH_DRIVER - - .;..\..\include;applications;.;drivers;Libraries\CMSIS\Include;Libraries\nrf51822\Include;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m0;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\common + NRF51, __RTTHREAD__, USE_STDPERIPH_DRIVER + + applications;.;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m0;..\..\components\drivers\include;drivers;Libraries\CMSIS\Include;Libraries\nrf51822\Include;..\..\components\finsh;.;..\..\include @@ -375,11 +351,12 @@ 0 0 0 + 0 - - - - + + + + @@ -391,207 +368,55 @@ 0 0x08000000 0x20000000 - - - - - - - + + + + + + + - - Kernel - - - clock.c - 1 - ..\..\src\clock.c - - - - - components.c - 1 - ..\..\src\components.c - - - - - cpu.c - 1 - ..\..\src\cpu.c - - - - - device.c - 1 - ..\..\src\device.c - - - - - idle.c - 1 - ..\..\src\idle.c - - - - - ipc.c - 1 - ..\..\src\ipc.c - - - - - irq.c - 1 - ..\..\src\irq.c - - - - - kservice.c - 1 - ..\..\src\kservice.c - - - - - mem.c - 1 - ..\..\src\mem.c - - - - - mempool.c - 1 - ..\..\src\mempool.c - - - - - object.c - 1 - ..\..\src\object.c - - - - - scheduler.c - 1 - ..\..\src\scheduler.c - - - - - signal.c - 1 - ..\..\src\signal.c - - - - - thread.c - 1 - ..\..\src\thread.c - - - - - timer.c - 1 - ..\..\src\timer.c - - - Applications - - - application.c - 1 - applications\application.c - - startup.c 1 applications\startup.c - - - - Drivers - - board.c + application.c 1 - drivers\board.c - - - - - uart.c - 1 - drivers\uart.c + applications\application.c - Startup Code - - - system_nrf51.c - 1 - Libraries\nrf51822\Source\templates\system_nrf51.c - - - - - arm_startup_nrf51.s - 2 - Libraries\nrf51822\Source\templates\arm\arm_startup_nrf51.s - - - - - cpu - - - backtrace.c - 1 - ..\..\libcpu\arm\common\backtrace.c - - + CPU div0.c 1 ..\..\libcpu\arm\common\div0.c - - showmem.c 1 ..\..\libcpu\arm\common\showmem.c - - + + backtrace.c + 1 + ..\..\libcpu\arm\common\backtrace.c + cpuport.c 1 ..\..\libcpu\arm\cortex-m0\cpuport.c - - context_rvds.S 2 @@ -601,53 +426,66 @@ DeviceDrivers - - - completion.c - 1 - ..\..\components\drivers\src\completion.c - - dataqueue.c 1 ..\..\components\drivers\src\dataqueue.c - - - pipe.c + workqueue.c 1 - ..\..\components\drivers\src\pipe.c + ..\..\components\drivers\src\workqueue.c - - ringblk_buf.c 1 ..\..\components\drivers\src\ringblk_buf.c - - + + completion.c + 1 + ..\..\components\drivers\src\completion.c + + + pipe.c + 1 + ..\..\components\drivers\src\pipe.c + ringbuffer.c 1 ..\..\components\drivers\src\ringbuffer.c - - waitqueue.c 1 ..\..\components\drivers\src\waitqueue.c + + + Drivers - workqueue.c + board.c 1 - ..\..\components\drivers\src\workqueue.c + drivers\board.c + + + uart.c + 1 + drivers\uart.c + + + system_nrf51.c + 1 + Libraries\nrf51822\Source\templates\system_nrf51.c + + + arm_startup_nrf51.s + 2 + Libraries\nrf51822\Source\templates\arm\arm_startup_nrf51.s @@ -659,23 +497,96 @@ 1 ..\..\components\finsh\shell.c - - + + msh.c + 1 + ..\..\components\finsh\msh.c + cmd.c 1 ..\..\components\finsh\cmd.c + + + Kernel - msh.c + kservice.c 1 - ..\..\components\finsh\msh.c + ..\..\src\kservice.c + + + device.c + 1 + ..\..\src\device.c + + + components.c + 1 + ..\..\src\components.c + + + thread.c + 1 + ..\..\src\thread.c + + + object.c + 1 + ..\..\src\object.c + + + idle.c + 1 + ..\..\src\idle.c + + + mem.c + 1 + ..\..\src\mem.c + + + ipc.c + 1 + ..\..\src\ipc.c + + + irq.c + 1 + ..\..\src\irq.c + + + timer.c + 1 + ..\..\src\timer.c + + + clock.c + 1 + ..\..\src\clock.c + + + scheduler.c + 1 + ..\..\src\scheduler.c + + + mempool.c + 1 + ..\..\src\mempool.c + + + + + + + diff --git a/bsp/nrf51822/rtconfig.h b/bsp/nrf51822/rtconfig.h index 66a727c898..306c8e8b2c 100644 --- a/bsp/nrf51822/rtconfig.h +++ b/bsp/nrf51822/rtconfig.h @@ -37,7 +37,7 @@ #define RT_USING_SEMAPHORE /* Using Mutex */ -/* #define RT_USING_MUTEX */ +#define RT_USING_MUTEX /* Using Event */ /* #define RT_USING_EVENT */ diff --git a/bsp/nrf51822/rtconfig.py b/bsp/nrf51822/rtconfig.py index bad289d12d..85b4f3154b 100644 --- a/bsp/nrf51822/rtconfig.py +++ b/bsp/nrf51822/rtconfig.py @@ -69,7 +69,7 @@ elif PLATFORM == 'armcc': AFLAGS = DEVICE LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-stm32.map --scatter nrf51822_rom.sct' - CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' EXEC_PATH += '/arm/bin40/' diff --git a/bsp/nrf51822/template.uvoptx b/bsp/nrf51822/template.uvoptx new file mode 100644 index 0000000000..0b46ec95af --- /dev/null +++ b/bsp/nrf51822/template.uvoptx @@ -0,0 +1,177 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 5 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U480200710 -O78 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0nrf51xxx.flm -FS00 -FL0200000 -FP0($$Device:nRF51822_xxAA$Flash\nrf51xxx.flm) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0nrf51xxx -FS00 -FL0200000 -FP0($$Device:nRF51822_xxAA$Flash\nrf51xxx.flm)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + diff --git a/bsp/nrf51822/template.uvproj b/bsp/nrf51822/template.uvprojx similarity index 95% rename from bsp/nrf51822/template.uvproj rename to bsp/nrf51822/template.uvprojx index 39cd92f59a..328e8f0c3f 100644 --- a/bsp/nrf51822/template.uvproj +++ b/bsp/nrf51822/template.uvprojx @@ -10,12 +10,13 @@ rt-thread 0x4 ARM-ADS + 0 nRF51822_xxAA Nordic Semiconductor - NordicSemiconductor.nRF_DeviceFamilyPack.1.1.4 - http://developer.nordicsemi.com/nRF51_SDK/pieces/nRF_DeviceFamilyPack/ + NordicSemiconductor.nRF_DeviceFamilyPack.8.38.0 + http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/ IROM(0x00000000,0x40000) IRAM(0x20000000,0x4000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE @@ -84,6 +85,8 @@ 0 0 + 0 + 0 0 @@ -147,7 +150,7 @@ 1 0 - 6 + 4 @@ -221,12 +224,14 @@ 0 0 0 + 0 0 0 8 0 0 0 + 0 3 3 0 @@ -360,7 +365,15 @@ 0 0 0 + 0 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 --c99 @@ -378,6 +391,7 @@ 0 0 0 + 0 diff --git a/bsp/nrf5x/libraries/templates/nrf52x/applications/application.c b/bsp/nrf5x/libraries/templates/nrf52x/applications/application.c index 1135d82e16..38a5dd245e 100644 --- a/bsp/nrf5x/libraries/templates/nrf52x/applications/application.c +++ b/bsp/nrf5x/libraries/templates/nrf52x/applications/application.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/nv32f100x/app/src/ledapp.c b/bsp/nv32f100x/app/src/ledapp.c index 2464f0e34b..129b906a96 100644 --- a/bsp/nv32f100x/app/src/ledapp.c +++ b/bsp/nv32f100x/app/src/ledapp.c @@ -1,17 +1,13 @@ /* - * File : ledapp.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2017-09-19 Quintin.Z the first version */ - + #include #include #include @@ -25,11 +21,11 @@ void led_thread_entry(void* parameter) { GPIO_Init (GPIOA, GPIO_PTB5_MASK, GPIO_PinOutput); - - while(1) - { + + while(1) + { GPIO_Toggle (GPIOA, GPIO_PTB5_MASK); rt_thread_delay(RT_TICK_PER_SECOND / 10); - } + } } diff --git a/bsp/nv32f100x/app/src/main.c b/bsp/nv32f100x/app/src/main.c index b63fa2f4dc..813878bc9f 100644 --- a/bsp/nv32f100x/app/src/main.c +++ b/bsp/nv32f100x/app/src/main.c @@ -1,21 +1,7 @@ /* - * File : _main.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/nv32f100x/board/inc/board.h b/bsp/nv32f100x/board/inc/board.h index 3639fa0b03..08acc7a77b 100644 --- a/bsp/nv32f100x/board/inc/board.h +++ b/bsp/nv32f100x/board/inc/board.h @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/nv32f100x/board/inc/drv_uart.h b/bsp/nv32f100x/board/inc/drv_uart.h index d1e0c6c109..4a98e3ee14 100644 --- a/bsp/nv32f100x/board/inc/drv_uart.h +++ b/bsp/nv32f100x/board/inc/drv_uart.h @@ -1,11 +1,7 @@ /* - * File : drv_uart.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/nv32f100x/board/src/board.c b/bsp/nv32f100x/board/src/board.c index 43c7910384..372099a6ba 100644 --- a/bsp/nv32f100x/board/src/board.c +++ b/bsp/nv32f100x/board/src/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -54,11 +50,11 @@ extern int __bss_end; *******************************************************************************/ void assert_failed(uint8_t* file, uint32_t line) { - rt_kprintf("\n\r Wrong parameter value detected on\r\n"); - rt_kprintf(" file %s\r\n", file); - rt_kprintf(" line %d\r\n", line); + rt_kprintf("\n\r Wrong parameter value detected on\r\n"); + rt_kprintf(" file %s\r\n", file); + rt_kprintf(" line %d\r\n", line); - while (1) ; + while (1) ; } /** @@ -98,7 +94,7 @@ void rt_hw_board_init() rt_console_set_device(RT_CONSOLE_DEVICE_NAME); #endif - + #ifdef RT_USING_HEAP rt_system_heap_init((void*)NV32_SRAM_BEGIN, (void*)NV32_SRAM_END); #endif diff --git a/bsp/nv32f100x/board/src/drv_uart.c b/bsp/nv32f100x/board/src/drv_uart.c index d8629d804d..89bac6eb76 100644 --- a/bsp/nv32f100x/board/src/drv_uart.c +++ b/bsp/nv32f100x/board/src/drv_uart.c @@ -1,11 +1,7 @@ /* - * File : drv_uart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/pic32ethernet/application.c b/bsp/pic32ethernet/application.c index 234a5acc50..ae2238f60b 100644 --- a/bsp/pic32ethernet/application.c +++ b/bsp/pic32ethernet/application.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -33,7 +29,7 @@ void thread_led1_entry(void* parameter) static void thread_led2_entry(void* parameter) { - // configure PORTD.RD2 = output + // configure PORTD.RD2 = output mPORTDSetPinsDigitalOut(BIT_2); while (1) diff --git a/bsp/pic32ethernet/board.c b/bsp/pic32ethernet/board.c index 8daa9b7123..5a738af8b1 100644 --- a/bsp/pic32ethernet/board.c +++ b/bsp/pic32ethernet/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2011, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -36,12 +32,12 @@ #pragma config DEBUG = OFF // Debugger Disabled for Starter Kit // The following is used by the main application -#define SYS_FREQ (80000000UL) +#define SYS_FREQ (80000000UL) -#define PB_DIV (1 << ((OSCCON&_OSCCON_PBDIV0_MASK)>>_OSCCON_PBDIV0_POSITION) ) -#define PRESCALE 256 -#define TOGGLES_PER_SEC RT_TICK_PER_SECOND -#define T1_TICK (SYS_FREQ/PB_DIV/PRESCALE/TOGGLES_PER_SEC) +#define PB_DIV (1 << ((OSCCON&_OSCCON_PBDIV0_MASK)>>_OSCCON_PBDIV0_POSITION) ) +#define PRESCALE 256 +#define TOGGLES_PER_SEC RT_TICK_PER_SECOND +#define T1_TICK (SYS_FREQ/PB_DIV/PRESCALE/TOGGLES_PER_SEC) static void rt_hw_show_info(void) { @@ -68,18 +64,18 @@ static void rt_hw_timer_handler(void) void rt_hw_board_init() { // Configure the device for maximum performance, but do not change the PBDIV clock divisor. - // Given the options, this function will change the program Flash wait states, - // RAM wait state and enable prefetch cache, but will not change the PBDIV. + // Given the options, this function will change the program Flash wait states, + // RAM wait state and enable prefetch cache, but will not change the PBDIV. // The PBDIV value is already set via the pragma FPBDIV option above. - SYSTEMConfig(SYS_FREQ, SYS_CFG_WAIT_STATES | SYS_CFG_PCACHE); + SYSTEMConfig(SYS_FREQ, SYS_CFG_WAIT_STATES | SYS_CFG_PCACHE); - /* use DBPRINTF */ - /* rt_hw_console_init(); */ + /* use DBPRINTF */ + /* rt_hw_console_init(); */ - rt_hw_usart_init(); - rt_console_set_device("uart1"); + rt_hw_usart_init(); + rt_console_set_device("uart1"); - rt_hw_show_info(); + rt_hw_show_info(); // enable multi-vector interrupts INTEnableSystemMultiVectoredInt(); @@ -97,7 +93,7 @@ void rt_hw_board_init() ConfigIntTimer1(T1_INT_ON | T1_INT_PRIOR_2); /* Setup the software interrupt. */ - mConfigIntCoreSW0( CSW_INT_ON | CSW_INT_PRIOR_1 | CSW_INT_SUB_PRIOR_0 ); + mConfigIntCoreSW0( CSW_INT_ON | CSW_INT_PRIOR_1 | CSW_INT_SUB_PRIOR_0 ); } void __ISR(_TIMER_1_VECTOR, ipl2) Timer1Handler(void) diff --git a/bsp/pic32ethernet/console.c b/bsp/pic32ethernet/console.c index fe8566203b..35c6725cf2 100644 --- a/bsp/pic32ethernet/console.c +++ b/bsp/pic32ethernet/console.c @@ -1,11 +1,7 @@ /* - * File : console.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2011, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -23,8 +19,8 @@ void rt_hw_console_init(void) { - //Initialize the DB_UTILS IO channel -// DBINIT(); + //Initialize the DB_UTILS IO channel +// DBINIT(); } /** diff --git a/bsp/pic32ethernet/startup.c b/bsp/pic32ethernet/startup.c index e139dfefca..372440d711 100644 --- a/bsp/pic32ethernet/startup.c +++ b/bsp/pic32ethernet/startup.c @@ -1,11 +1,7 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -29,55 +25,55 @@ extern void finsh_set_device(const char* device); */ void rtthread_startup(void) { - /* init board */ - rt_hw_board_init(); + /* init board */ + rt_hw_board_init(); - /* show version */ - rt_show_version(); + /* show version */ + rt_show_version(); - /* init timer system */ - rt_system_timer_init(); + /* init timer system */ + rt_system_timer_init(); #ifdef RT_USING_HEAP /* init memory system */ rt_system_heap_init((void*)&_ramfunc_end, (void*)PIC32_SRAM_END); #endif - /* init scheduler system */ - rt_system_scheduler_init(); + /* init scheduler system */ + rt_system_scheduler_init(); - /* init application */ - rt_application_init(); + /* init application */ + rt_application_init(); #ifdef RT_USING_FINSH - /* init finsh */ - finsh_system_init(); + /* init finsh */ + finsh_system_init(); #ifdef RT_USING_DEVICE - finsh_set_device("uart1"); + finsh_set_device("uart1"); #endif #endif /* init timer thread */ rt_system_timer_thread_init(); - /* init idle thread */ - rt_thread_idle_init(); + /* init idle thread */ + rt_thread_idle_init(); - /* start scheduler */ - rt_system_scheduler_start(); + /* start scheduler */ + rt_system_scheduler_start(); - /* never reach here */ - return ; + /* never reach here */ + return ; } int main(void) { - /* disable interrupt first */ - rt_hw_interrupt_disable(); + /* disable interrupt first */ + rt_hw_interrupt_disable(); - /* startup RT-Thread RTOS */ - rtthread_startup(); + /* startup RT-Thread RTOS */ + rtthread_startup(); - return 0; + return 0; } diff --git a/bsp/qemu-vexpress-gemini/applications/application.c b/bsp/qemu-vexpress-gemini/applications/application.c index c0160df189..b65c758208 100644 --- a/bsp/qemu-vexpress-gemini/applications/application.c +++ b/bsp/qemu-vexpress-gemini/applications/application.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -23,7 +19,7 @@ int rt_application_init() { rt_thread_t tid; - tid = rt_thread_create("init", init_thread, RT_NULL, + tid = rt_thread_create("init", init_thread, RT_NULL, 1024, RT_THREAD_PRIORITY_MAX/3, 10); if (tid != RT_NULL) rt_thread_startup(tid); diff --git a/bsp/qemu-vexpress-gemini/applications/startup.c b/bsp/qemu-vexpress-gemini/applications/startup.c index fa17c0571b..2c37bb4726 100644 --- a/bsp/qemu-vexpress-gemini/applications/startup.c +++ b/bsp/qemu-vexpress-gemini/applications/startup.c @@ -1,11 +1,7 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/qemu-vexpress-gemini/cpu/context_gcc.S b/bsp/qemu-vexpress-gemini/cpu/context_gcc.S index 01593a7c0a..2b8206b01b 100644 --- a/bsp/qemu-vexpress-gemini/cpu/context_gcc.S +++ b/bsp/qemu-vexpress-gemini/cpu/context_gcc.S @@ -1,21 +1,7 @@ /* - * File : context.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2013, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/qemu-vexpress-gemini/cpu/cp15_gcc.S b/bsp/qemu-vexpress-gemini/cpu/cp15_gcc.S index f1ed6492aa..f299cc4acb 100644 --- a/bsp/qemu-vexpress-gemini/cpu/cp15_gcc.S +++ b/bsp/qemu-vexpress-gemini/cpu/cp15_gcc.S @@ -1,22 +1,7 @@ /* - * File : cp15_gcc.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2013, RT-Thread Development Team - * http://www.rt-thread.org + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/qemu-vexpress-gemini/cpu/cpu.c b/bsp/qemu-vexpress-gemini/cpu/cpu.c index 7dd426e4dd..5f82671c1b 100644 --- a/bsp/qemu-vexpress-gemini/cpu/cpu.c +++ b/bsp/qemu-vexpress-gemini/cpu/cpu.c @@ -1,11 +1,7 @@ /* - * File : cpu.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -24,14 +20,14 @@ /** shutdown CPU */ void rt_hw_cpu_shutdown() { - rt_uint32_t level; - rt_kprintf("shutdown...\n"); + rt_uint32_t level; + rt_kprintf("shutdown...\n"); - level = rt_hw_interrupt_disable(); - while (level) - { - RT_ASSERT(0); - } + level = rt_hw_interrupt_disable(); + while (level) + { + RT_ASSERT(0); + } } /*@}*/ diff --git a/bsp/qemu-vexpress-gemini/cpu/gic.c b/bsp/qemu-vexpress-gemini/cpu/gic.c index 4cff1bad3e..962317821a 100644 --- a/bsp/qemu-vexpress-gemini/cpu/gic.c +++ b/bsp/qemu-vexpress-gemini/cpu/gic.c @@ -1,11 +1,7 @@ /* - * File : gic.c, ARM Generic Interrupt Controller - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2013-2014, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/qemu-vexpress-gemini/cpu/gic.h b/bsp/qemu-vexpress-gemini/cpu/gic.h index 41a7727da2..7c781ad4d9 100644 --- a/bsp/qemu-vexpress-gemini/cpu/gic.h +++ b/bsp/qemu-vexpress-gemini/cpu/gic.h @@ -1,11 +1,7 @@ /* - * File : gic.h, ARM Generic Interrupt Controller - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2013, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/qemu-vexpress-gemini/cpu/interrupt.c b/bsp/qemu-vexpress-gemini/cpu/interrupt.c index 889f74b5ca..70f745a120 100644 --- a/bsp/qemu-vexpress-gemini/cpu/interrupt.c +++ b/bsp/qemu-vexpress-gemini/cpu/interrupt.c @@ -1,11 +1,7 @@ /* - * File : interrupt.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2013-2014, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/qemu-vexpress-gemini/cpu/interrupt.h b/bsp/qemu-vexpress-gemini/cpu/interrupt.h index d81f1c81ae..90f392f407 100644 --- a/bsp/qemu-vexpress-gemini/cpu/interrupt.h +++ b/bsp/qemu-vexpress-gemini/cpu/interrupt.h @@ -1,11 +1,7 @@ /* - * File : interrupt.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -18,28 +14,28 @@ #define INT_IRQ 0x00 #define INT_FIQ 0x01 -#define INTC_REVISION(hw_base) REG32((hw_base) + 0x0) -#define INTC_SYSCONFIG(hw_base) REG32((hw_base) + 0x10) -#define INTC_SYSSTATUS(hw_base) REG32((hw_base) + 0x14) -#define INTC_SIR_IRQ(hw_base) REG32((hw_base) + 0x40) -#define INTC_SIR_FIQ(hw_base) REG32((hw_base) + 0x44) -#define INTC_CONTROL(hw_base) REG32((hw_base) + 0x48) -#define INTC_PROTECTION(hw_base) REG32((hw_base) + 0x4c) -#define INTC_IDLE(hw_base) REG32((hw_base) + 0x50) -#define INTC_IRQ_PRIORITY(hw_base) REG32((hw_base) + 0x60) -#define INTC_FIQ_PRIORITY(hw_base) REG32((hw_base) + 0x64) -#define INTC_THRESHOLD(hw_base) REG32((hw_base) + 0x68) -#define INTC_SICR(hw_base) REG32((hw_base) + 0x6c) -#define INTC_SCR(hw_base, n) REG32((hw_base) + 0x70 + ((n) * 0x04)) -#define INTC_ITR(hw_base, n) REG32((hw_base) + 0x80 + ((n) * 0x20)) -#define INTC_MIR(hw_base, n) REG32((hw_base) + 0x84 + ((n) * 0x20)) -#define INTC_MIR_CLEAR(hw_base, n) REG32((hw_base) + 0x88 + ((n) * 0x20)) -#define INTC_MIR_SET(hw_base, n) REG32((hw_base) + 0x8c + ((n) * 0x20)) -#define INTC_ISR_SET(hw_base, n) REG32((hw_base) + 0x90 + ((n) * 0x20)) -#define INTC_ISR_CLEAR(hw_base, n) REG32((hw_base) + 0x94 + ((n) * 0x20)) +#define INTC_REVISION(hw_base) REG32((hw_base) + 0x0) +#define INTC_SYSCONFIG(hw_base) REG32((hw_base) + 0x10) +#define INTC_SYSSTATUS(hw_base) REG32((hw_base) + 0x14) +#define INTC_SIR_IRQ(hw_base) REG32((hw_base) + 0x40) +#define INTC_SIR_FIQ(hw_base) REG32((hw_base) + 0x44) +#define INTC_CONTROL(hw_base) REG32((hw_base) + 0x48) +#define INTC_PROTECTION(hw_base) REG32((hw_base) + 0x4c) +#define INTC_IDLE(hw_base) REG32((hw_base) + 0x50) +#define INTC_IRQ_PRIORITY(hw_base) REG32((hw_base) + 0x60) +#define INTC_FIQ_PRIORITY(hw_base) REG32((hw_base) + 0x64) +#define INTC_THRESHOLD(hw_base) REG32((hw_base) + 0x68) +#define INTC_SICR(hw_base) REG32((hw_base) + 0x6c) +#define INTC_SCR(hw_base, n) REG32((hw_base) + 0x70 + ((n) * 0x04)) +#define INTC_ITR(hw_base, n) REG32((hw_base) + 0x80 + ((n) * 0x20)) +#define INTC_MIR(hw_base, n) REG32((hw_base) + 0x84 + ((n) * 0x20)) +#define INTC_MIR_CLEAR(hw_base, n) REG32((hw_base) + 0x88 + ((n) * 0x20)) +#define INTC_MIR_SET(hw_base, n) REG32((hw_base) + 0x8c + ((n) * 0x20)) +#define INTC_ISR_SET(hw_base, n) REG32((hw_base) + 0x90 + ((n) * 0x20)) +#define INTC_ISR_CLEAR(hw_base, n) REG32((hw_base) + 0x94 + ((n) * 0x20)) #define INTC_PENDING_IRQ(hw_base, n) REG32((hw_base) + 0x98 + ((n) * 0x20)) #define INTC_PENDING_FIQ(hw_base, n) REG32((hw_base) + 0x9c + ((n) * 0x20)) -#define INTC_ILR(hw_base, n) REG32((hw_base) + 0x100 + ((n) * 0x04)) +#define INTC_ILR(hw_base, n) REG32((hw_base) + 0x100 + ((n) * 0x04)) void rt_hw_interrupt_control(int vector, int priority, int route); int rt_hw_interrupt_get_active(int fiq_irq); diff --git a/bsp/qemu-vexpress-gemini/cpu/mmu.c b/bsp/qemu-vexpress-gemini/cpu/mmu.c index b2503e4260..f4d6068099 100644 --- a/bsp/qemu-vexpress-gemini/cpu/mmu.c +++ b/bsp/qemu-vexpress-gemini/cpu/mmu.c @@ -1,11 +1,7 @@ /* - * File : mmu.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/qemu-vexpress-gemini/cpu/stack.c b/bsp/qemu-vexpress-gemini/cpu/stack.c index 4ae1536a20..c1d9262d4b 100644 --- a/bsp/qemu-vexpress-gemini/cpu/stack.c +++ b/bsp/qemu-vexpress-gemini/cpu/stack.c @@ -1,11 +1,7 @@ /* - * File : stack.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -24,42 +20,42 @@ * This function will initialize thread stack * * @param tentry the entry of thread - * @param parameter the parameter of entry + * @param parameter the parameter of entry * @param stack_addr the beginning stack address * @param texit the function will be called when thread exit * * @return stack address */ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) + rt_uint8_t *stack_addr, void *texit) { - rt_uint32_t *stk; + rt_uint32_t *stk; - stk = (rt_uint32_t*)stack_addr; - *(stk) = (rt_uint32_t)tentry; /* entry point */ - *(--stk) = (rt_uint32_t)texit; /* lr */ - *(--stk) = 0; /* r12 */ - *(--stk) = 0; /* r11 */ - *(--stk) = 0; /* r10 */ - *(--stk) = 0; /* r9 */ - *(--stk) = 0; /* r8 */ - *(--stk) = 0; /* r7 */ - *(--stk) = 0; /* r6 */ - *(--stk) = 0; /* r5 */ - *(--stk) = 0; /* r4 */ - *(--stk) = 0; /* r3 */ - *(--stk) = 0; /* r2 */ - *(--stk) = 0; /* r1 */ - *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */ + stk = (rt_uint32_t*)stack_addr; + *(stk) = (rt_uint32_t)tentry; /* entry point */ + *(--stk) = (rt_uint32_t)texit; /* lr */ + *(--stk) = 0; /* r12 */ + *(--stk) = 0; /* r11 */ + *(--stk) = 0; /* r10 */ + *(--stk) = 0; /* r9 */ + *(--stk) = 0; /* r8 */ + *(--stk) = 0; /* r7 */ + *(--stk) = 0; /* r6 */ + *(--stk) = 0; /* r5 */ + *(--stk) = 0; /* r4 */ + *(--stk) = 0; /* r3 */ + *(--stk) = 0; /* r2 */ + *(--stk) = 0; /* r1 */ + *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */ - /* cpsr */ - if ((rt_uint32_t)tentry & 0x01) - *(--stk) = SVCMODE | 0x20; /* thumb mode */ - else - *(--stk) = SVCMODE; /* arm mode */ + /* cpsr */ + if ((rt_uint32_t)tentry & 0x01) + *(--stk) = SVCMODE | 0x20; /* thumb mode */ + else + *(--stk) = SVCMODE; /* arm mode */ - /* return task's current stack address */ - return (rt_uint8_t *)stk; + /* return task's current stack address */ + return (rt_uint8_t *)stk; } /*@}*/ diff --git a/bsp/qemu-vexpress-gemini/cpu/start_gcc.S b/bsp/qemu-vexpress-gemini/cpu/start_gcc.S index 0c64d9fecf..404e1df9c3 100644 --- a/bsp/qemu-vexpress-gemini/cpu/start_gcc.S +++ b/bsp/qemu-vexpress-gemini/cpu/start_gcc.S @@ -1,21 +1,7 @@ /* - * File : start_gcc.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2013-2014, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -215,35 +201,35 @@ rt_hw_context_switch_interrupt_do: .endm .align 5 - .globl vector_swi + .globl vector_swi vector_swi: push_svc_reg bl rt_hw_trap_swi b . .align 5 - .globl vector_undef + .globl vector_undef vector_undef: push_svc_reg bl rt_hw_trap_undef b . .align 5 - .globl vector_pabt + .globl vector_pabt vector_pabt: push_svc_reg bl rt_hw_trap_pabt b . .align 5 - .globl vector_dabt + .globl vector_dabt vector_dabt: push_svc_reg bl rt_hw_trap_dabt b . .align 5 - .globl vector_resv + .globl vector_resv vector_resv: push_svc_reg bl rt_hw_trap_resv diff --git a/bsp/qemu-vexpress-gemini/cpu/trap.c b/bsp/qemu-vexpress-gemini/cpu/trap.c index a6397d20d2..c6ca45aee7 100644 --- a/bsp/qemu-vexpress-gemini/cpu/trap.c +++ b/bsp/qemu-vexpress-gemini/cpu/trap.c @@ -1,11 +1,7 @@ /* - * File : trap.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2013, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -135,7 +131,7 @@ void rt_hw_trap_resv(struct rt_hw_exp_stack *regs) rt_hw_cpu_shutdown(); } -#define GIC_ACK_INTID_MASK 0x000003ff +#define GIC_ACK_INTID_MASK 0x000003ff void rt_hw_trap_irq(void) { diff --git a/bsp/qemu-vexpress-gemini/cpu/vector_gcc.S b/bsp/qemu-vexpress-gemini/cpu/vector_gcc.S index 4a44a7395c..b5ab2042d9 100644 --- a/bsp/qemu-vexpress-gemini/cpu/vector_gcc.S +++ b/bsp/qemu-vexpress-gemini/cpu/vector_gcc.S @@ -1,21 +1,7 @@ /* - * File : vector_gcc.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2013, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -62,4 +48,4 @@ _vector_irq: _vector_fiq: .word vector_fiq -.balignl 16,0xdeadbeef +.balignl 16,0xdeadbeef diff --git a/bsp/qemu-vexpress-gemini/drivers/board.c b/bsp/qemu-vexpress-gemini/drivers/board.c index 3de322c52e..990ec3779a 100644 --- a/bsp/qemu-vexpress-gemini/drivers/board.c +++ b/bsp/qemu-vexpress-gemini/drivers/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/qemu-vexpress-gemini/drivers/board.h b/bsp/qemu-vexpress-gemini/drivers/board.h index 0a9bb3670c..23ccc52233 100644 --- a/bsp/qemu-vexpress-gemini/drivers/board.h +++ b/bsp/qemu-vexpress-gemini/drivers/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2013, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/qemu-vexpress-gemini/drivers/serial.c b/bsp/qemu-vexpress-gemini/drivers/serial.c index 92e8b949fa..eff3205a2d 100644 --- a/bsp/qemu-vexpress-gemini/drivers/serial.c +++ b/bsp/qemu-vexpress-gemini/drivers/serial.c @@ -1,26 +1,7 @@ /* - * serial.c UART driver + * Copyright (c) 2006-2021, RT-Thread Development Team * - * COPYRIGHT (C) 2013, Shanghai Real-Thread Technology Co., Ltd - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * Maintainer: bernard.xiong - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/qemu-vexpress-gemini/drivers/serial.h b/bsp/qemu-vexpress-gemini/drivers/serial.h index 52e6f07ea3..dceea68d1f 100644 --- a/bsp/qemu-vexpress-gemini/drivers/serial.h +++ b/bsp/qemu-vexpress-gemini/drivers/serial.h @@ -1,26 +1,7 @@ /* - * UART driver + * Copyright (c) 2006-2021, RT-Thread Development Team * - * COPYRIGHT (C) 2013, Shanghai Real-Thread Technology Co., Ltd - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * Maintainer: bernard.xiong - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/qemu-vexpress-gemini/drivers/vbus_drv.c b/bsp/qemu-vexpress-gemini/drivers/vbus_drv.c index 0f522a271d..939838b67c 100644 --- a/bsp/qemu-vexpress-gemini/drivers/vbus_drv.c +++ b/bsp/qemu-vexpress-gemini/drivers/vbus_drv.c @@ -1,26 +1,7 @@ /* - * VMM Bus Driver + * Copyright (c) 2006-2021, RT-Thread Development Team * - * COPYRIGHT (C) 2015, Shanghai Real-Thread Technology Co., Ltd - * http://www.rt-thread.com - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/qemu-vexpress-gemini/drivers/vbus_hw.h b/bsp/qemu-vexpress-gemini/drivers/vbus_hw.h index 19c6fcc902..6ad9c4d561 100644 --- a/bsp/qemu-vexpress-gemini/drivers/vbus_hw.h +++ b/bsp/qemu-vexpress-gemini/drivers/vbus_hw.h @@ -1,25 +1,7 @@ /* - * VMM Bus + * Copyright (c) 2006-2021, RT-Thread Development Team * - * COPYRIGHT (C) 2015, Shanghai Real-Thread Technology Co., Ltd - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/raspberry-pi/raspi2/applications/main.c b/bsp/raspberry-pi/raspi2/applications/main.c index 101386fdfd..548881ae4b 100644 --- a/bsp/raspberry-pi/raspi2/applications/main.c +++ b/bsp/raspberry-pi/raspi2/applications/main.c @@ -1,21 +1,7 @@ /* - * File : main.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/raspberry-pi/raspi2/applications/mnt.c b/bsp/raspberry-pi/raspi2/applications/mnt.c index 8da1dc1ece..db45518cfb 100644 --- a/bsp/raspberry-pi/raspi2/applications/mnt.c +++ b/bsp/raspberry-pi/raspi2/applications/mnt.c @@ -1,21 +1,7 @@ /* - * File : mnt.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/raspberry-pi/raspi2/cpu/context_gcc.S b/bsp/raspberry-pi/raspi2/cpu/context_gcc.S index 48402739f9..9d95d833c0 100644 --- a/bsp/raspberry-pi/raspi2/cpu/context_gcc.S +++ b/bsp/raspberry-pi/raspi2/cpu/context_gcc.S @@ -1,21 +1,7 @@ /* - * File : context.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2013, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/raspberry-pi/raspi2/cpu/cp15_gcc.S b/bsp/raspberry-pi/raspi2/cpu/cp15_gcc.S index f1ed6492aa..f299cc4acb 100644 --- a/bsp/raspberry-pi/raspi2/cpu/cp15_gcc.S +++ b/bsp/raspberry-pi/raspi2/cpu/cp15_gcc.S @@ -1,22 +1,7 @@ /* - * File : cp15_gcc.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2013, RT-Thread Development Team - * http://www.rt-thread.org + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/raspberry-pi/raspi2/cpu/cpu.c b/bsp/raspberry-pi/raspi2/cpu/cpu.c index 8bf16d19e8..5f82671c1b 100644 --- a/bsp/raspberry-pi/raspi2/cpu/cpu.c +++ b/bsp/raspberry-pi/raspi2/cpu/cpu.c @@ -1,11 +1,7 @@ /* - * File : cpu.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/raspberry-pi/raspi2/cpu/interrupt.c b/bsp/raspberry-pi/raspi2/cpu/interrupt.c index 93513f3da3..7a48eaa9fd 100644 --- a/bsp/raspberry-pi/raspi2/cpu/interrupt.c +++ b/bsp/raspberry-pi/raspi2/cpu/interrupt.c @@ -1,11 +1,7 @@ /* - * File : interrupt.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2013-2014, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/raspberry-pi/raspi2/cpu/mmu.c b/bsp/raspberry-pi/raspi2/cpu/mmu.c index b2503e4260..f4d6068099 100644 --- a/bsp/raspberry-pi/raspi2/cpu/mmu.c +++ b/bsp/raspberry-pi/raspi2/cpu/mmu.c @@ -1,11 +1,7 @@ /* - * File : mmu.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/raspberry-pi/raspi2/cpu/stack.c b/bsp/raspberry-pi/raspi2/cpu/stack.c index e60e8c7170..3fe42b5db9 100644 --- a/bsp/raspberry-pi/raspi2/cpu/stack.c +++ b/bsp/raspberry-pi/raspi2/cpu/stack.c @@ -1,11 +1,7 @@ /* - * File : stack.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/raspberry-pi/raspi2/cpu/start_gcc.S b/bsp/raspberry-pi/raspi2/cpu/start_gcc.S index b60ad6a38f..cde901515d 100644 --- a/bsp/raspberry-pi/raspi2/cpu/start_gcc.S +++ b/bsp/raspberry-pi/raspi2/cpu/start_gcc.S @@ -1,21 +1,7 @@ /* - * File : start_gcc.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2013-2014, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -59,25 +45,25 @@ stack_top: /* reset entry */ .globl _reset _reset: - /* Disable IRQ & FIQ */ - cpsid if + /* Disable IRQ & FIQ */ + cpsid if - /* Check for HYP mode */ - mrs r0, cpsr_all - and r0, r0, #0x1F - mov r8, #0x1A - cmp r0, r8 - beq overHyped - b continue + /* Check for HYP mode */ + mrs r0, cpsr_all + and r0, r0, #0x1F + mov r8, #0x1A + cmp r0, r8 + beq overHyped + b continue overHyped: /* Get out of HYP mode */ - ldr r1, =continue - msr ELR_hyp, r1 - mrs r1, cpsr_all - and r1, r1, #0x1f ;@ CPSR_MODE_MASK - orr r1, r1, #0x13 ;@ CPSR_MODE_SUPERVISOR - msr SPSR_hyp, r1 - eret + ldr r1, =continue + msr ELR_hyp, r1 + mrs r1, cpsr_all + and r1, r1, #0x1f ;@ CPSR_MODE_MASK + orr r1, r1, #0x13 ;@ CPSR_MODE_SUPERVISOR + msr SPSR_hyp, r1 + eret continue: @@ -115,7 +101,7 @@ stack_setup: @ Set the startup stack for svc mov sp, r0 - sub r0, r0, #SVC_Stack_Size + sub r0, r0, #SVC_Stack_Size @ Enter Undefined Instruction Mode and set its Stack Pointer msr cpsr_c, #Mode_UND|I_Bit|F_Bit diff --git a/bsp/raspberry-pi/raspi2/cpu/trap.c b/bsp/raspberry-pi/raspi2/cpu/trap.c index 3012c26e2c..8a1eb33c65 100644 --- a/bsp/raspberry-pi/raspi2/cpu/trap.c +++ b/bsp/raspberry-pi/raspi2/cpu/trap.c @@ -1,11 +1,7 @@ /* - * File : trap.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2013, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/raspberry-pi/raspi2/cpu/vector_gcc.S b/bsp/raspberry-pi/raspi2/cpu/vector_gcc.S index 17c2d69c30..b5ab2042d9 100644 --- a/bsp/raspberry-pi/raspi2/cpu/vector_gcc.S +++ b/bsp/raspberry-pi/raspi2/cpu/vector_gcc.S @@ -1,21 +1,7 @@ /* - * File : vector_gcc.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2013, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/raspberry-pi/raspi2/driver/board.c b/bsp/raspberry-pi/raspi2/driver/board.c index 78cac6ba4d..a5e822f168 100644 --- a/bsp/raspberry-pi/raspi2/driver/board.c +++ b/bsp/raspberry-pi/raspi2/driver/board.c @@ -1,21 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/raspberry-pi/raspi2/driver/board.h b/bsp/raspberry-pi/raspi2/driver/board.h index 92ef5de76c..1c71cd7744 100644 --- a/bsp/raspberry-pi/raspi2/driver/board.h +++ b/bsp/raspberry-pi/raspi2/driver/board.h @@ -1,21 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/raspberry-pi/raspi2/driver/drv_uart.c b/bsp/raspberry-pi/raspi2/driver/drv_uart.c index de7b987c2a..b25a3a5c8b 100644 --- a/bsp/raspberry-pi/raspi2/driver/drv_uart.c +++ b/bsp/raspberry-pi/raspi2/driver/drv_uart.c @@ -1,21 +1,7 @@ /* - * File : drv_uart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/raspberry-pi/raspi2/driver/drv_uart.h b/bsp/raspberry-pi/raspi2/driver/drv_uart.h index e489eaae65..76072f938e 100644 --- a/bsp/raspberry-pi/raspi2/driver/drv_uart.h +++ b/bsp/raspberry-pi/raspi2/driver/drv_uart.h @@ -1,21 +1,7 @@ /* - * File : drv_uart.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/raspberry-pi/raspi2/link.lds b/bsp/raspberry-pi/raspi2/link.lds index 75e0845943..2624a5a95d 100644 --- a/bsp/raspberry-pi/raspi2/link.lds +++ b/bsp/raspberry-pi/raspi2/link.lds @@ -1,20 +1,7 @@ /* - * File : link.lds - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * 2017-5-30 bernard first version diff --git a/bsp/raspberry-pi/raspi3-32/link.lds b/bsp/raspberry-pi/raspi3-32/link.lds index 75e0845943..2624a5a95d 100644 --- a/bsp/raspberry-pi/raspi3-32/link.lds +++ b/bsp/raspberry-pi/raspi3-32/link.lds @@ -1,20 +1,7 @@ /* - * File : link.lds - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * 2017-5-30 bernard first version diff --git a/bsp/raspberry-pi/raspi3-64/link.lds b/bsp/raspberry-pi/raspi3-64/link.lds index b7b2dcc32c..a624a973b4 100644 --- a/bsp/raspberry-pi/raspi3-64/link.lds +++ b/bsp/raspberry-pi/raspi3-64/link.lds @@ -1,20 +1,7 @@ /* - * File : link.lds - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * 2017-5-30 bernard first version @@ -40,7 +27,7 @@ SECTIONS *(.gnu.linkonce.t*) *(COMMON) - + /* section information for finsh shell */ . = ALIGN(16); __fsymtab_start = .; @@ -110,7 +97,7 @@ SECTIONS *(.bss) *(.bss.*) *(.dynbss) - + PROVIDE(__bss_end = .); } _end = .; diff --git a/bsp/raspberry-pi/raspi4-32/link.lds b/bsp/raspberry-pi/raspi4-32/link.lds index 92ec03c8f4..df4ecb5ad3 100644 --- a/bsp/raspberry-pi/raspi4-32/link.lds +++ b/bsp/raspberry-pi/raspi4-32/link.lds @@ -1,20 +1,7 @@ /* - * File : link.lds - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * 2017-5-30 bernard first version @@ -40,7 +27,7 @@ SECTIONS *(.gnu.linkonce.t*) *(COMMON) - + /* section information for finsh shell */ . = ALIGN(16); __fsymtab_start = .; @@ -118,7 +105,7 @@ SECTIONS *(.bss) *(.bss.*) *(.dynbss) - + PROVIDE(__bss_end = .); } _end = .; diff --git a/bsp/raspberry-pi/raspi4-64/link.lds b/bsp/raspberry-pi/raspi4-64/link.lds index b7b2dcc32c..a624a973b4 100644 --- a/bsp/raspberry-pi/raspi4-64/link.lds +++ b/bsp/raspberry-pi/raspi4-64/link.lds @@ -1,20 +1,7 @@ /* - * File : link.lds - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * 2017-5-30 bernard first version @@ -40,7 +27,7 @@ SECTIONS *(.gnu.linkonce.t*) *(COMMON) - + /* section information for finsh shell */ . = ALIGN(16); __fsymtab_start = .; @@ -110,7 +97,7 @@ SECTIONS *(.bss) *(.bss.*) *(.dynbss) - + PROVIDE(__bss_end = .); } _end = .; diff --git a/bsp/realview-a8/applications/application.c b/bsp/realview-a8/applications/application.c index 072cd6d98f..0b8f14b1db 100644 --- a/bsp/realview-a8/applications/application.c +++ b/bsp/realview-a8/applications/application.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -23,7 +19,7 @@ int rt_application_init() { rt_thread_t tid; - tid = rt_thread_create("init", init_thread, RT_NULL, + tid = rt_thread_create("init", init_thread, RT_NULL, 1024, RT_THREAD_PRIORITY_MAX/3, 10); if (tid != RT_NULL) rt_thread_startup(tid); diff --git a/bsp/realview-a8/applications/startup.c b/bsp/realview-a8/applications/startup.c index fa17c0571b..2c37bb4726 100644 --- a/bsp/realview-a8/applications/startup.c +++ b/bsp/realview-a8/applications/startup.c @@ -1,11 +1,7 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/realview-a8/drivers/board.c b/bsp/realview-a8/drivers/board.c index 7a5f80e454..013603b684 100644 --- a/bsp/realview-a8/drivers/board.c +++ b/bsp/realview-a8/drivers/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/realview-a8/drivers/board.h b/bsp/realview-a8/drivers/board.h index 89ba3cbe03..f1d30314ba 100644 --- a/bsp/realview-a8/drivers/board.h +++ b/bsp/realview-a8/drivers/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2013, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/realview-a8/drivers/serial.c b/bsp/realview-a8/drivers/serial.c index 7df953a282..75fca59401 100644 --- a/bsp/realview-a8/drivers/serial.c +++ b/bsp/realview-a8/drivers/serial.c @@ -1,26 +1,7 @@ /* - * serial.c UART driver + * Copyright (c) 2006-2021, RT-Thread Development Team * - * COPYRIGHT (C) 2013, Shanghai Real-Thread Technology Co., Ltd - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * Maintainer: bernard.xiong - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/realview-a8/drivers/serial.h b/bsp/realview-a8/drivers/serial.h index 52e6f07ea3..dceea68d1f 100644 --- a/bsp/realview-a8/drivers/serial.h +++ b/bsp/realview-a8/drivers/serial.h @@ -1,26 +1,7 @@ /* - * UART driver + * Copyright (c) 2006-2021, RT-Thread Development Team * - * COPYRIGHT (C) 2013, Shanghai Real-Thread Technology Co., Ltd - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * Maintainer: bernard.xiong - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/realview-a8/rtt_api.h b/bsp/realview-a8/rtt_api.h index 365e756351..cf8e8ddb1a 100644 --- a/bsp/realview-a8/rtt_api.h +++ b/bsp/realview-a8/rtt_api.h @@ -1,25 +1,7 @@ /* - * serial.c UART driver + * Copyright (c) 2006-2021, RT-Thread Development Team * - * COPYRIGHT (C) 2014, Shanghai Real-Thread Technology Co., Ltd - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -149,11 +131,11 @@ struct vmm_domain struct vmm_iomap { - const char name[16]; /* iomap name */ + const char name[16]; /* iomap name */ - unsigned long pa; /* physical address */ - volatile void __iomem * va; /* virtual address */ - size_t size; /* memory size */ + unsigned long pa; /* physical address */ + volatile void __iomem * va; /* virtual address */ + size_t size; /* memory size */ }; struct vmm_entry_param diff --git a/bsp/rm48x50/application/startup.c b/bsp/rm48x50/application/startup.c index 40b69e2c95..a49c9f1810 100644 --- a/bsp/rm48x50/application/startup.c +++ b/bsp/rm48x50/application/startup.c @@ -1,11 +1,7 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2013, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -75,21 +71,21 @@ void rtthread_startup(void) *rt_hw_cpu_dcache_enable(); */ - /* init hardware interrupt */ - rt_hw_interrupt_init(); + /* init hardware interrupt */ + rt_hw_interrupt_init(); - /* init board */ - rt_hw_board_init(); + /* init board */ + rt_hw_board_init(); - rt_show_version(); + rt_show_version(); - /* init timer system */ - rt_system_timer_init(); + /* init timer system */ + rt_system_timer_init(); - /* init memory system */ + /* init memory system */ #ifdef RT_USING_HEAP #ifdef __CC_ARM - rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)MEMEND); + rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)MEMEND); #elif defined(__GNUC__) rt_system_heap_init((void*)&__bss_end, (void*)MEMEND); #elif defined(__TI_COMPILER_VERSION__) @@ -99,40 +95,40 @@ void rtthread_startup(void) #endif #endif - /* init scheduler system */ - rt_system_scheduler_init(); + /* init scheduler system */ + rt_system_scheduler_init(); - /* init application */ - rt_application_init(); + /* init application */ + rt_application_init(); #ifdef RT_USING_FINSH - /* init finsh */ - finsh_system_init(); - finsh_set_device("sci2"); + /* init finsh */ + finsh_system_init(); + finsh_set_device("sci2"); #endif - /* init soft timer thread */ - rt_system_timer_thread_init(); + /* init soft timer thread */ + rt_system_timer_thread_init(); - /* init idle thread */ - rt_thread_idle_init(); + /* init idle thread */ + rt_thread_idle_init(); - /* start scheduler */ - rt_system_scheduler_start(); + /* start scheduler */ + rt_system_scheduler_start(); - /* never reach here */ - return ; + /* never reach here */ + return ; } int main(void) { - /* disable interrupt first */ - rt_hw_interrupt_disable(); + /* disable interrupt first */ + rt_hw_interrupt_disable(); - /* invoke rtthread_startup */ - rtthread_startup(); + /* invoke rtthread_startup */ + rtthread_startup(); - return 0; + return 0; } /*@}*/ diff --git a/bsp/sam7x/applications/application.c b/bsp/sam7x/applications/application.c index 2b52802115..6500ddfa10 100644 --- a/bsp/sam7x/applications/application.c +++ b/bsp/sam7x/applications/application.c @@ -1,11 +1,7 @@ /* - * File : app.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -44,49 +40,49 @@ void rt_init_thread_entry(void *parameter) { /* Filesystem Initialization */ #ifdef RT_USING_DFS - { - /* init the device filesystem */ - dfs_init(); - /* init the efsl filesystam*/ - efsl_init(); + { + /* init the device filesystem */ + dfs_init(); + /* init the efsl filesystam*/ + efsl_init(); - /* mount sd card fat partition 1 as root directory */ - if (dfs_mount("sd0", "/", "efs", 0, 0) == 0) - rt_kprintf("File System initialized!\n"); - else - rt_kprintf("File System init failed!\n"); - } + /* mount sd card fat partition 1 as root directory */ + if (dfs_mount("sd0", "/", "efs", 0, 0) == 0) + rt_kprintf("File System initialized!\n"); + else + rt_kprintf("File System init failed!\n"); + } #endif /* LwIP Initialization */ #ifdef RT_USING_LWIP - { - extern void lwip_sys_init(void); + { + extern void lwip_sys_init(void); - eth_system_device_init(); + eth_system_device_init(); - /* register AT91 EMAC device */ - sam7xether_register("E0"); + /* register AT91 EMAC device */ + sam7xether_register("E0"); - /* init lwip system */ - lwip_sys_init(); - rt_kprintf("TCP/IP initialized!\n"); - } + /* init lwip system */ + lwip_sys_init(); + rt_kprintf("TCP/IP initialized!\n"); + } #endif } int rt_application_init() { - rt_thread_t init_thread; + rt_thread_t init_thread; - init_thread = rt_thread_create("init", - rt_init_thread_entry, RT_NULL, - 1024, 8, 5); - rt_thread_startup(init_thread); + init_thread = rt_thread_create("init", + rt_init_thread_entry, RT_NULL, + 1024, 8, 5); + rt_thread_startup(init_thread); - rt_kprintf("enter list() to get function list!\n"); + rt_kprintf("enter list() to get function list!\n"); - return 0; + return 0; } /*@}*/ diff --git a/bsp/sam7x/applications/startup.c b/bsp/sam7x/applications/startup.c index d167d9ebcb..528d6127f3 100644 --- a/bsp/sam7x/applications/startup.c +++ b/bsp/sam7x/applications/startup.c @@ -1,11 +1,7 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -56,17 +52,17 @@ extern int finsh_system_init(void); void led_flash() { - int i; - static int j = 0; + int i; + static int j = 0; - rt_hw_board_led_off(j); - for (i = 0; i < 2000000; i ++); + rt_hw_board_led_off(j); + for (i = 0; i < 2000000; i ++); - j ++; - if (j >= 4) j = 0; + j ++; + if (j >= 4) j = 0; - rt_hw_board_led_on(j); - for (i = 0; i < 2000000; i ++); + rt_hw_board_led_on(j); + for (i = 0; i < 2000000; i ++); } /** @@ -74,70 +70,70 @@ void led_flash() */ void rtthread_startup(void) { - /* init hardware interrupt */ - rt_hw_interrupt_init(); + /* init hardware interrupt */ + rt_hw_interrupt_init(); - /* init board */ - rt_hw_board_init(); + /* init board */ + rt_hw_board_init(); - rt_show_version(); + rt_show_version(); - /* init timer system */ - rt_system_timer_init(); + /* init timer system */ + rt_system_timer_init(); #ifdef RT_USING_HEAP #ifdef __CC_ARM - rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x00210000); + rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x00210000); #elif __ICCARM__ rt_system_heap_init(__segment_end("HEAP"), (void*)0x00210000); #else - rt_system_heap_init(&__bss_end, (void*)0x00210000); + rt_system_heap_init(&__bss_end, (void*)0x00210000); #endif #endif - /* init scheduler system */ - rt_system_scheduler_init(); + /* init scheduler system */ + rt_system_scheduler_init(); #ifdef RT_USING_HOOK /* if the hook is used */ - /* set idle thread hook */ - rt_thread_idle_sethook(led_flash); + /* set idle thread hook */ + rt_thread_idle_sethook(led_flash); #endif #ifdef RT_USING_DEVICE - /* init hardware serial device */ - rt_hw_serial_init(); + /* init hardware serial device */ + rt_hw_serial_init(); #ifdef RT_USING_DFS - rt_hw_sdcard_init(); + rt_hw_sdcard_init(); #endif #endif - /* init application */ - rt_application_init(); + /* init application */ + rt_application_init(); #ifdef RT_USING_FINSH - /* init finsh */ - finsh_system_init(); - finsh_set_device("uart1"); + /* init finsh */ + finsh_system_init(); + finsh_set_device("uart1"); #endif - /* init idle thread */ - rt_thread_idle_init(); + /* init idle thread */ + rt_thread_idle_init(); - /* start scheduler */ - rt_system_scheduler_start(); + /* start scheduler */ + rt_system_scheduler_start(); - /* never reach here */ - return ; + /* never reach here */ + return ; } #ifdef __CC_ARM int main (void) { - /* invoke rtthread_startup */ - rtthread_startup(); + /* invoke rtthread_startup */ + rtthread_startup(); - return 0; + return 0; } #endif diff --git a/bsp/sep6200/application/application.c b/bsp/sep6200/application/application.c index cbc4cd4d47..5a032933b4 100644 --- a/bsp/sep6200/application/application.c +++ b/bsp/sep6200/application/application.c @@ -1,24 +1,10 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes + * Date Author Notes * 2013-7-14 Peng Fan Simple application */ @@ -59,31 +45,31 @@ void rt_test2_thread_entry(void *parameter) int rt_application_init(void) { - rt_thread_t init_thread; - rt_thread_t test1_thread; - rt_thread_t test2_thread; + rt_thread_t init_thread; + rt_thread_t test1_thread; + rt_thread_t test2_thread; - init_thread = rt_thread_create("init", - rt_init_thread_entry, RT_NULL, - RT_INIT_THREAD_STACK_SIZE, 8, 20); + init_thread = rt_thread_create("init", + rt_init_thread_entry, RT_NULL, + RT_INIT_THREAD_STACK_SIZE, 8, 20); - test1_thread = rt_thread_create("test1", - rt_test1_thread_entry, RT_NULL, - 512, 200, 20); - test2_thread = rt_thread_create("test2", - rt_test2_thread_entry, RT_NULL, - 512, 200, 20); + test1_thread = rt_thread_create("test1", + rt_test1_thread_entry, RT_NULL, + 512, 200, 20); + test2_thread = rt_thread_create("test2", + rt_test2_thread_entry, RT_NULL, + 512, 200, 20); - if (init_thread != RT_NULL) - rt_thread_startup(init_thread); + if (init_thread != RT_NULL) + rt_thread_startup(init_thread); - if (test1_thread != RT_NULL) - rt_thread_startup(test1_thread); + if (test1_thread != RT_NULL) + rt_thread_startup(test1_thread); - if (test2_thread != RT_NULL) - rt_thread_startup(test2_thread); + if (test2_thread != RT_NULL) + rt_thread_startup(test2_thread); - return 0; + return 0; } /*@}*/ diff --git a/bsp/sep6200/application/startup.c b/bsp/sep6200/application/startup.c index 78b9c30c5f..0d67f08256 100644 --- a/bsp/sep6200/application/startup.c +++ b/bsp/sep6200/application/startup.c @@ -1,21 +1,7 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -54,44 +40,44 @@ extern void sd_init(void); void rtthread_startup() { - /* init hardware interrupt */ - rt_hw_interrupt_init(); + /* init hardware interrupt */ + rt_hw_interrupt_init(); - /* init board */ - rt_hw_board_init(); + /* init board */ + rt_hw_board_init(); - /* show version */ - rt_show_version(); + /* show version */ + rt_show_version(); - /* init timer system */ - rt_system_timer_init(); + /* init timer system */ + rt_system_timer_init(); - /* init heap memory system */ - rt_system_heap_init(&__bss_end, (void*)0x45000000); + /* init heap memory system */ + rt_system_heap_init(&__bss_end, (void*)0x45000000); - /* init scheduler system */ - rt_system_scheduler_init(); + /* init scheduler system */ + rt_system_scheduler_init(); - /* init application */ - rt_application_init(); + /* init application */ + rt_application_init(); #ifdef RT_USING_FINSH - /* init finsh */ - finsh_system_init(); + /* init finsh */ + finsh_system_init(); #ifdef RT_USING_DEVICE - finsh_set_device("uart0"); + finsh_set_device("uart0"); #endif #endif rt_system_timer_thread_init(); - /* init idle thread */ - rt_thread_idle_init(); + /* init idle thread */ + rt_thread_idle_init(); - /* start scheduler */ - rt_system_scheduler_start(); + /* start scheduler */ + rt_system_scheduler_start(); - /* never reach here */ - return ; + /* never reach here */ + return ; } diff --git a/bsp/sep6200/board.h b/bsp/sep6200/board.h index 91b745b516..51079875dc 100644 --- a/bsp/sep6200/board.h +++ b/bsp/sep6200/board.h @@ -1,21 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/sep6200/drivers/board.c b/bsp/sep6200/drivers/board.c index bc8756c9a1..3a1ade2752 100644 --- a/bsp/sep6200/drivers/board.c +++ b/bsp/sep6200/drivers/board.c @@ -1,21 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -36,14 +22,14 @@ void rt_hw_serial_putc(const char c); -#define UART0 ((struct uartport *)SEP6200_UART0_BASE) +#define UART0 ((struct uartport *)SEP6200_UART0_BASE) struct rt_device uart0_device; struct serial_int_rx uart0_int_rx; struct serial_device uart0 = { - UART0, - &uart0_int_rx, + UART0, + &uart0_int_rx, RT_NULL }; @@ -52,13 +38,13 @@ struct serial_device uart0 = */ void rt_timer_handler(int vector, void *param) { - rt_uint32_t clear_int; + rt_uint32_t clear_int; - /* clear timer interrupt */ - if (read_reg(SEP6200_TIMER_T2IMSR) & 0x1) - clear_int = read_reg(SEP6200_TIMER_T2ISCR); + /* clear timer interrupt */ + if (read_reg(SEP6200_TIMER_T2IMSR) & 0x1) + clear_int = read_reg(SEP6200_TIMER_T2ISCR); - rt_tick_increase(); + rt_tick_increase(); } /* @@ -66,47 +52,47 @@ void rt_timer_handler(int vector, void *param) */ void rt_serial_handler(int vector, void *param) { - rt_uint32_t num; - switch (vector) { - case INTSRC_UART0: + rt_uint32_t num; + switch (vector) { + case INTSRC_UART0: /*No interrupt*/ - if ((*(RP)SEP6200_UART0_IIR & 0x1)) - return; + if ((*(RP)SEP6200_UART0_IIR & 0x1)) + return; /*Get the serial interrupt num*/ - num = (*(RP)SEP6200_UART0_IIR >> 1) & 0x7; + num = (*(RP)SEP6200_UART0_IIR >> 1) & 0x7; /*Receive or timeout*/ if ((num == 6) || (num == 2)) - rt_hw_serial_isr(&uart0_device); - break; - /*1,2,3 not implemented now, do in future*/ - case INTSRC_UART1: - break; - case INTSRC_UART2: - break; - case INTSRC_UART3: - break; - } + rt_hw_serial_isr(&uart0_device); + break; + /*1,2,3 not implemented now, do in future*/ + case INTSRC_UART1: + break; + case INTSRC_UART2: + break; + case INTSRC_UART3: + break; + } } /* * This function will init timer2 for system ticks */ -#define BUS4_FREQ 320000000UL -#define TIMER_CLK BUS4_FREQ +#define BUS4_FREQ 320000000UL +#define TIMER_CLK BUS4_FREQ #define HZ 100 void rt_hw_timer_init(void) { - *(RP)SEP6200_TIMER_T2LCR = (TIMER_CLK + HZ / 2) / HZ; - *(RP)SEP6200_TIMER_T2CR = 0x6; + *(RP)SEP6200_TIMER_T2LCR = (TIMER_CLK + HZ / 2) / HZ; + *(RP)SEP6200_TIMER_T2CR = 0x6; - rt_hw_interrupt_install(INTSRC_TIMER1, rt_timer_handler, RT_NULL, "timer"); - rt_hw_interrupt_umask(INTSRC_TIMER1); + rt_hw_interrupt_install(INTSRC_TIMER1, rt_timer_handler, RT_NULL, "timer"); + rt_hw_interrupt_umask(INTSRC_TIMER1); - /* start the timer */ - *(RP)SEP6200_TIMER_T2CR |= 0x1; + /* start the timer */ + *(RP)SEP6200_TIMER_T2CR |= 0x1; } /* @@ -115,35 +101,35 @@ void rt_hw_timer_init(void) #define UART_CLK 60000000UL void rt_hw_uart_init(void) { - const rt_uint32_t uartclk = UART_CLK; + const rt_uint32_t uartclk = UART_CLK; - *(RP)(SEP6200_UART0_LCR) = 0x83; - *(RP)(SEP6200_UART0_DLBH) = (uartclk/16/115200) >> 8; - *(RP)(SEP6200_UART0_DLBL) = (uartclk/16/115200) & 0xff; - *(RP)(SEP6200_UART0_LCR) = 0x83 & (~(0x1 << 7)); + *(RP)(SEP6200_UART0_LCR) = 0x83; + *(RP)(SEP6200_UART0_DLBH) = (uartclk/16/115200) >> 8; + *(RP)(SEP6200_UART0_DLBL) = (uartclk/16/115200) & 0xff; + *(RP)(SEP6200_UART0_LCR) = 0x83 & (~(0x1 << 7)); - *(RP)(SEP6200_UART0_FCR) = 0x0; - *(RP)(SEP6200_UART0_MCR) = 0x0; + *(RP)(SEP6200_UART0_FCR) = 0x0; + *(RP)(SEP6200_UART0_MCR) = 0x0; - *(RP)(SEP6200_UART0_IER) = 0x0; - /* Enable rx interrupt*/ - *(RP)(SEP6200_UART0_IER) |= 0x1; - /* Disable tx interrupt*/ - *(RP)(SEP6200_UART0_IER) &= ~(0x1 << 1); + *(RP)(SEP6200_UART0_IER) = 0x0; + /* Enable rx interrupt*/ + *(RP)(SEP6200_UART0_IER) |= 0x1; + /* Disable tx interrupt*/ + *(RP)(SEP6200_UART0_IER) &= ~(0x1 << 1); - rt_hw_interrupt_install(INTSRC_UART0, rt_serial_handler, RT_NULL, "uart0"); - rt_hw_interrupt_umask(INTSRC_UART0); + rt_hw_interrupt_install(INTSRC_UART0, rt_serial_handler, RT_NULL, "uart0"); + rt_hw_interrupt_umask(INTSRC_UART0); - rt_hw_serial_register(&uart0_device, "uart0", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart0); + rt_hw_serial_register(&uart0_device, "uart0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart0); } void rt_hw_board_init(void) { int i = 0; - rt_hw_uart_init(); - rt_hw_timer_init(); + rt_hw_uart_init(); + rt_hw_timer_init(); } /* @@ -151,12 +137,12 @@ void rt_hw_board_init(void) */ void rt_hw_serial_putc(const char c) { - if (c == '\n') - rt_hw_serial_putc('\r'); + if (c == '\n') + rt_hw_serial_putc('\r'); - while (!((*(RP)SEP6200_UART0_LSR) & 0x40)); + while (!((*(RP)SEP6200_UART0_LSR) & 0x40)); - *(RP)(SEP6200_UART0_TXFIFO) = c; + *(RP)(SEP6200_UART0_TXFIFO) = c; } /** diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_can.c b/bsp/stm32/libraries/HAL_Drivers/drv_can.c index 83d58ec800..4fe801187a 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_can.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_can.c @@ -11,6 +11,7 @@ * fix bug.port to BSP [stm32] * 2019-03-27 YLZ support double can channels, support stm32F4xx (only Legacy mode). * 2019-06-17 YLZ port to new STM32F1xx HAL V1.1.3. + * 2021-02-02 YuZhe XU fix bug in filter config */ #include "drv_can.h" @@ -292,6 +293,13 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg) } break; case RT_CAN_CMD_SET_FILTER: + { + rt_uint32_t id_h = 0; + rt_uint32_t id_l = 0; + rt_uint32_t mask_h = 0; + rt_uint32_t mask_l = 0; + rt_uint32_t mask_l_tail = 0; //CAN_FxR2 bit [2:0] + if (RT_NULL == arg) { /* default filter config */ @@ -303,19 +311,69 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg) /* get default filter */ for (int i = 0; i < filter_cfg->count; i++) { - drv_can->FilterConfig.FilterBank = filter_cfg->items[i].hdr; - drv_can->FilterConfig.FilterIdHigh = (filter_cfg->items[i].id >> 13) & 0xFFFF; - drv_can->FilterConfig.FilterIdLow = ((filter_cfg->items[i].id << 3) | - (filter_cfg->items[i].ide << 2) | - (filter_cfg->items[i].rtr << 1)) & 0xFFFF; - drv_can->FilterConfig.FilterMaskIdHigh = (filter_cfg->items[i].mask >> 16) & 0xFFFF; - drv_can->FilterConfig.FilterMaskIdLow = filter_cfg->items[i].mask & 0xFFFF; + if (filter_cfg->items[i].hdr == -1) + { + drv_can->FilterConfig.FilterBank = i; + } + else + { + drv_can->FilterConfig.FilterBank = filter_cfg->items[i].hdr; + } + /** + * ID | CAN_FxR1[31:24] | CAN_FxR1[23:16] | CAN_FxR1[15:8] | CAN_FxR1[7:0] | + * MASK | CAN_FxR2[31:24] | CAN_FxR1[23:16] | CAN_FxR1[15:8] | CAN_FxR1[7:0] | + * STD ID | STID[10:3] | STDID[2:0] |<- 21bit ->| + * EXT ID | EXTID[28:21] | EXTID[20:13] | EXTID[12:5] | EXTID[4:0] IDE RTR 0| + * @note the 32bit STD ID must << 21 to fill CAN_FxR1[31:21] and EXT ID must << 3, + * -> but the id bit of struct rt_can_filter_item is 29, + * -> so STD id << 18 and EXT id Don't need << 3, when get the high 16bit. + * -> FilterIdHigh : (((STDid << 18) or (EXT id)) >> 13) & 0xFFFF, + * -> FilterIdLow: ((STDid << 18) or (EXT id << 3)) & 0xFFFF. + * @note the mask bit of struct rt_can_filter_item is 32, + * -> FilterMaskIdHigh: (((STD mask << 21) or (EXT mask <<3)) >> 16) & 0xFFFF + * -> FilterMaskIdLow: ((STD mask << 21) or (EXT mask <<3)) & 0xFFFF + */ + if (filter_cfg->items[i].mode == CAN_FILTERMODE_IDMASK) + { + /* make sure the CAN_FxR1[2:0](IDE RTR) work */ + mask_l_tail = 0x06; + } + else if (filter_cfg->items[i].mode == CAN_FILTERMODE_IDLIST) + { + /* same as CAN_FxR1 */ + mask_l_tail = (filter_cfg->items[i].ide << 2) | + (filter_cfg->items[i].rtr << 1); + } + if (filter_cfg->items[i].ide == RT_CAN_STDID) + { + id_h = ((filter_cfg->items[i].id << 18) >> 13) & 0xFFFF; + id_l = ((filter_cfg->items[i].id << 18) | + (filter_cfg->items[i].ide << 2) | + (filter_cfg->items[i].rtr << 1)) & 0xFFFF; + mask_h = ((filter_cfg->items[i].mask << 21) >> 16) & 0xFFFF; + mask_l = ((filter_cfg->items[i].mask << 21) | mask_l_tail) & 0xFFFF; + } + else if (filter_cfg->items[i].ide == RT_CAN_EXTID) + { + id_h = (filter_cfg->items[i].id >> 13) & 0xFFFF; + id_l = ((filter_cfg->items[i].id << 3) | + (filter_cfg->items[i].ide << 2) | + (filter_cfg->items[i].rtr << 1)) & 0xFFFF; + mask_h = ((filter_cfg->items[i].mask << 3) >> 16) & 0xFFFF; + mask_l = ((filter_cfg->items[i].mask << 3) | mask_l_tail) & 0xFFFF; + } + drv_can->FilterConfig.FilterIdHigh = id_h; + drv_can->FilterConfig.FilterIdLow = id_l; + drv_can->FilterConfig.FilterMaskIdHigh = mask_h; + drv_can->FilterConfig.FilterMaskIdLow = mask_l; + drv_can->FilterConfig.FilterMode = filter_cfg->items[i].mode; /* Filter conf */ HAL_CAN_ConfigFilter(&drv_can->CanHandle, &drv_can->FilterConfig); } } break; + } case RT_CAN_CMD_SET_MODE: argval = (rt_uint32_t) arg; if (argval != RT_CAN_MODE_NORMAL && diff --git a/bsp/stm32/stm32f429-st-disco/board/ports/ili9341.c b/bsp/stm32/stm32f429-st-disco/board/ports/ili9341.c index eaab59c78d..f8e9eda216 100644 --- a/bsp/stm32/stm32f429-st-disco/board/ports/ili9341.c +++ b/bsp/stm32/stm32f429-st-disco/board/ports/ili9341.c @@ -1,21 +1,7 @@ /* - * File : ili9341.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32/stm32f429-st-disco/board/ports/ili9341.h b/bsp/stm32/stm32f429-st-disco/board/ports/ili9341.h index 895683be5c..d2403452ef 100644 --- a/bsp/stm32/stm32f429-st-disco/board/ports/ili9341.h +++ b/bsp/stm32/stm32f429-st-disco/board/ports/ili9341.h @@ -1,21 +1,7 @@ /* - * File : ili9341.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32/stm32l475-atk-pandora/board/board.c b/bsp/stm32/stm32l475-atk-pandora/board/board.c index d711d2c3d6..6e2be4bf42 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/board.c +++ b/bsp/stm32/stm32l475-atk-pandora/board/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32/stm32l476-st-nucleo/project.uvprojx b/bsp/stm32/stm32l476-st-nucleo/project.uvprojx index bdbb353d3c..6b5c2aedb7 100644 --- a/bsp/stm32/stm32l476-st-nucleo/project.uvprojx +++ b/bsp/stm32/stm32l476-st-nucleo/project.uvprojx @@ -333,7 +333,7 @@ 0 - RT_USING_ARM_LIBC, USE_HAL_DRIVER, STM32L476xx, __RTTHREAD__ + RT_USING_ARM_LIBC, USE_HAL_DRIVER, STM32L476xx, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND applications;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;board\CubeMX_Config\Inc;board\ports;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\components\finsh;.;..\..\..\include;..\..\..\components\libc\compilers\armlibc;..\..\..\components\libc\compilers\common;..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Inc;..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Include;..\libraries\STM32L4xx_HAL\CMSIS\Include @@ -397,16 +397,16 @@ - div0.c + showmem.c 1 - ..\..\..\libcpu\arm\common\div0.c + ..\..\..\libcpu\arm\common\showmem.c - showmem.c + div0.c 1 - ..\..\..\libcpu\arm\common\showmem.c + ..\..\..\libcpu\arm\common\div0.c @@ -461,34 +461,6 @@ ..\..\..\components\drivers\src\completion.c - - - dataqueue.c - 1 - ..\..\..\components\drivers\src\dataqueue.c - - - - - pipe.c - 1 - ..\..\..\components\drivers\src\pipe.c - - - - - ringblk_buf.c - 1 - ..\..\..\components\drivers\src\ringblk_buf.c - - - - - ringbuffer.c - 1 - ..\..\..\components\drivers\src\ringbuffer.c - - waitqueue.c @@ -503,14 +475,42 @@ ..\..\..\components\drivers\src\workqueue.c + + + ringbuffer.c + 1 + ..\..\..\components\drivers\src\ringbuffer.c + + + + + dataqueue.c + 1 + ..\..\..\components\drivers\src\dataqueue.c + + + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\src\ringblk_buf.c + + + + + pipe.c + 1 + ..\..\..\components\drivers\src\pipe.c + + Drivers - board.c - 1 - board\board.c + startup_stm32l476xx.s + 2 + ..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Source\Templates\arm\startup_stm32l476xx.s @@ -522,9 +522,9 @@ - startup_stm32l476xx.s - 2 - ..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Source\Templates\arm\startup_stm32l476xx.s + board.c + 1 + board\board.c @@ -536,16 +536,16 @@ - drv_usart.c + drv_common.c 1 - ..\libraries\HAL_Drivers\drv_usart.c + ..\libraries\HAL_Drivers\drv_common.c - drv_pm.c + drv_usart.c 1 - ..\libraries\HAL_Drivers\drv_pm.c + ..\libraries\HAL_Drivers\drv_usart.c @@ -557,9 +557,9 @@ - drv_common.c + drv_pm.c 1 - ..\libraries\HAL_Drivers\drv_common.c + ..\libraries\HAL_Drivers\drv_pm.c @@ -572,13 +572,6 @@ ..\..\..\components\finsh\shell.c - - - cmd.c - 1 - ..\..\..\components\finsh\cmd.c - - msh.c @@ -586,9 +579,23 @@ ..\..\..\components\finsh\msh.c + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + Kernel + + + timer.c + 1 + ..\..\..\src\timer.c + + clock.c @@ -598,30 +605,9 @@ - components.c + object.c 1 - ..\..\..\src\components.c - - - - - device.c - 1 - ..\..\..\src\device.c - - - - - idle.c - 1 - ..\..\..\src\idle.c - - - - - ipc.c - 1 - ..\..\..\src\ipc.c + ..\..\..\src\object.c @@ -640,23 +626,9 @@ - mem.c + ipc.c 1 - ..\..\..\src\mem.c - - - - - mempool.c - 1 - ..\..\..\src\mempool.c - - - - - object.c - 1 - ..\..\..\src\object.c + ..\..\..\src\ipc.c @@ -666,13 +638,6 @@ ..\..\..\src\scheduler.c - - - signal.c - 1 - ..\..\..\src\signal.c - - thread.c @@ -682,21 +647,42 @@ - timer.c + idle.c 1 - ..\..\..\src\timer.c + ..\..\..\src\idle.c + + + + + components.c + 1 + ..\..\..\src\components.c + + + + + device.c + 1 + ..\..\..\src\device.c + + + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + + + mem.c + 1 + ..\..\..\src\mem.c libc - - - libc.c - 1 - ..\..\..\components\libc\compilers\armlibc\libc.c - - mem_std.c @@ -706,9 +692,23 @@ - stubs.c + syscalls.c 1 - ..\..\..\components\libc\compilers\armlibc\stubs.c + ..\..\..\components\libc\compilers\armlibc\syscalls.c + + + + + libc.c + 1 + ..\..\..\components\libc\compilers\armlibc\libc.c + + + + + stdlib.c + 1 + ..\..\..\components\libc\compilers\common\stdlib.c @@ -723,23 +723,9 @@ Libraries - system_stm32l4xx.c + stm32l4xx_hal_cryp.c 1 - ..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Source\Templates\system_stm32l4xx.c - - - - - stm32l4xx_hal.c - 1 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal.c - - - - - stm32l4xx_hal_comp.c - 1 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_comp.c + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cryp.c @@ -749,69 +735,6 @@ ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cortex.c - - - stm32l4xx_hal_crc.c - 1 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc.c - - - - - stm32l4xx_hal_crc_ex.c - 1 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc_ex.c - - - - - stm32l4xx_hal_cryp.c - 1 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cryp.c - - - - - stm32l4xx_hal_cryp_ex.c - 1 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cryp_ex.c - - - - - stm32l4xx_hal_dma.c - 1 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c - - - - - stm32l4xx_hal_dma_ex.c - 1 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma_ex.c - - - - - stm32l4xx_hal_exti.c - 1 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_exti.c - - - - - stm32l4xx_hal_pwr.c - 1 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c - - - - - stm32l4xx_hal_pwr_ex.c - 1 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c - - stm32l4xx_hal_rcc.c @@ -819,55 +742,6 @@ ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc.c - - - stm32l4xx_hal_rcc_ex.c - 1 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c - - - - - stm32l4xx_hal_rng.c - 1 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rng.c - - - - - stm32l4xx_hal_gpio.c - 1 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c - - - - - stm32l4xx_hal_uart.c - 1 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart.c - - - - - stm32l4xx_hal_uart_ex.c - 1 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart_ex.c - - - - - stm32l4xx_hal_usart.c - 1 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_usart.c - - - - - stm32l4xx_hal_usart_ex.c - 1 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_usart_ex.c - - stm32l4xx_hal_rtc.c @@ -877,9 +751,58 @@ - stm32l4xx_hal_rtc_ex.c + stm32l4xx_hal_pwr.c 1 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rtc_ex.c + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c + + + + + stm32l4xx_hal_usart_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_usart_ex.c + + + + + system_stm32l4xx.c + 1 + ..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Source\Templates\system_stm32l4xx.c + + + + + stm32l4xx_hal_pwr_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c + + + + + stm32l4xx_hal_usart.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_usart.c + + + + + stm32l4xx_hal_cryp_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cryp_ex.c + + + + + stm32l4xx_hal_rcc_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c + + + + + stm32l4xx_hal_uart.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart.c @@ -889,6 +812,83 @@ ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_lptim.c + + + stm32l4xx_hal_dma_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma_ex.c + + + + + stm32l4xx_hal_gpio.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c + + + + + stm32l4xx_hal_crc_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc_ex.c + + + + + stm32l4xx_hal_dma.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c + + + + + stm32l4xx_hal.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal.c + + + + + stm32l4xx_hal_rtc_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rtc_ex.c + + + + + stm32l4xx_hal_comp.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_comp.c + + + + + stm32l4xx_hal_exti.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_exti.c + + + + + stm32l4xx_hal_rng.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rng.c + + + + + stm32l4xx_hal_crc.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc.c + + + + + stm32l4xx_hal_uart_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart_ex.c + + diff --git a/bsp/stm32/stm32l496-ali-developer/board/board.c b/bsp/stm32/stm32l496-ali-developer/board/board.c index a0886582d4..9622e73038 100644 --- a/bsp/stm32/stm32l496-ali-developer/board/board.c +++ b/bsp/stm32/stm32l496-ali-developer/board/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32/stm32l496-st-nucleo/board/board.c b/bsp/stm32/stm32l496-st-nucleo/board/board.c index 29f27a354f..05887f6152 100644 --- a/bsp/stm32/stm32l496-st-nucleo/board/board.c +++ b/bsp/stm32/stm32l496-st-nucleo/board/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_sdio.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_sdio.c index df1ca92691..458a62097a 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_sdio.c +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_sdio.c @@ -54,7 +54,7 @@ struct rthw_sdio }; /* SYSRAM SDMMC1/2 accesses */ -#define SDCARD_ADDR 0x2FFC0000 +#define SDCARD_ADDR 0x2FFFF000 #if defined(__CC_ARM) || defined(__CLANG_ARM) __attribute__((at(SDCARD_ADDR))) static rt_uint8_t cache_buf[SDIO_BUFF_SIZE]; #elif defined ( __GNUC__ ) @@ -579,7 +579,11 @@ int rt_hw_sdio_init(void) #endif #ifdef BSP_USING_SDIO2 - MX_RTC_Init(); + + if (IS_ENGINEERING_BOOT_MODE()) + { + MX_RTC_Init(); + } LBEE5KL1DX_init(); struct stm32_sdio_des sdio_des2; diff --git a/bsp/upd70f3454/applications/application.c b/bsp/upd70f3454/applications/application.c index ace92c365f..65f203a96c 100644 --- a/bsp/upd70f3454/applications/application.c +++ b/bsp/upd70f3454/applications/application.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/upd70f3454/applications/startup.c b/bsp/upd70f3454/applications/startup.c index 409b3cc615..9a9ed22cde 100644 --- a/bsp/upd70f3454/applications/startup.c +++ b/bsp/upd70f3454/applications/startup.c @@ -1,11 +1,7 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -49,7 +45,7 @@ void rtthread_startup(void) /* show version */ rt_show_version(); - + /* init timer system */ rt_system_timer_init(); @@ -91,7 +87,7 @@ int main(void) /* init system setting */ TAB0_Start(); - + /* startup RT-Thread RTOS */ rtthread_startup(); diff --git a/bsp/upd70f3454/drivers/board.c b/bsp/upd70f3454/drivers/board.c index 8af3f72d77..d8ebdfc558 100644 --- a/bsp/upd70f3454/drivers/board.c +++ b/bsp/upd70f3454/drivers/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/upd70f3454/drivers/board.h b/bsp/upd70f3454/drivers/board.h index 66ec065d5b..51fbf2feee 100644 --- a/bsp/upd70f3454/drivers/board.h +++ b/bsp/upd70f3454/drivers/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -30,7 +26,7 @@ #define UP_KEY 0x1b #define DOWN_KEY 0x17 #define LEFT_KEY 0x0f -#define RIGHT_KEY 0x1e +#define RIGHT_KEY 0x1e void rt_hw_board_init(void); rt_uint8_t get_key(void); diff --git a/bsp/upd70f3454/drivers/uart.c b/bsp/upd70f3454/drivers/uart.c index f41f4eceeb..d452092497 100644 --- a/bsp/upd70f3454/drivers/uart.c +++ b/bsp/upd70f3454/drivers/uart.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2012 RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -196,7 +192,7 @@ static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer while (UA1TSF == 1U) ; UA1TX = *ptr; - + ptr ++; size --; } diff --git a/bsp/xplorer4330/applications/application.c b/bsp/xplorer4330/applications/application.c index e40ad02e48..707be03de8 100644 --- a/bsp/xplorer4330/applications/application.c +++ b/bsp/xplorer4330/applications/application.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2014, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/xplorer4330/applications/startup.c b/bsp/xplorer4330/applications/startup.c index f6cf534b03..65d430d64a 100644 --- a/bsp/xplorer4330/applications/startup.c +++ b/bsp/xplorer4330/applications/startup.c @@ -1,11 +1,7 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/xplorer4330/drivers/board.c b/bsp/xplorer4330/drivers/board.c index b0621b8238..4b7f19935d 100644 --- a/bsp/xplorer4330/drivers/board.c +++ b/bsp/xplorer4330/drivers/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2014 RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/xplorer4330/drivers/board.h b/bsp/xplorer4330/drivers/board.h index 22515a125e..606802d4cd 100644 --- a/bsp/xplorer4330/drivers/board.h +++ b/bsp/xplorer4330/drivers/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/xplorer4330/drivers/drv_uart.c b/bsp/xplorer4330/drivers/drv_uart.c index 48b80ba555..ed928426a9 100644 --- a/bsp/xplorer4330/drivers/drv_uart.c +++ b/bsp/xplorer4330/drivers/drv_uart.c @@ -1,11 +1,7 @@ /* - * File : drv_uart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009-2013 RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -212,8 +208,8 @@ void rt_hw_uart_init(void) config.parity = PARITY_NONE; config.stop_bits = STOP_BITS_1; config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; - + config.bufsz = RT_SERIAL_RB_BUFSZ; + serial0.ops = &lpc_uart_ops; serial0.config = config; @@ -244,7 +240,7 @@ void rt_hw_uart_init(void) LPC_USART0->DLM = 0x00; LPC_USART0->FDR = 0xC1; LPC_USART0->LCR = 0x03; /* DLAB = 0 */ - + /* preemption = 1, sub-priority = 1 */ NVIC_SetPriority(uart->USART_IRQn, ((0x01 << 3) | 0x01)); @@ -264,7 +260,7 @@ void rt_hw_uart_init(void) config.parity = PARITY_NONE; config.stop_bits = STOP_BITS_1; config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; + config.bufsz = RT_SERIAL_RB_BUFSZ; serial2.ops = &lpc_uart_ops; serial2.config = config; diff --git a/components/drivers/include/drivers/sensor.h b/components/drivers/include/drivers/sensor.h index e05006f9f6..ede8d11c99 100644 --- a/components/drivers/include/drivers/sensor.h +++ b/components/drivers/include/drivers/sensor.h @@ -90,8 +90,6 @@ extern "C" { #define RT_SENSOR_UNIT_PPB (15) /* Concentration unit: ppb */ #define RT_SENSOR_UNIT_DMS (16) /* Coordinates unit: DMS */ #define RT_SENSOR_UNIT_DD (17) /* Coordinates unit: DD */ -#define RT_SENSOR_UNIT_PERCENT (18) /* Percentage unit: % */ - /* Sensor communication interface types */ #define RT_SENSOR_INTF_I2C (1 << 0) @@ -219,7 +217,7 @@ struct rt_sensor_data rt_int32_t force; /* Force sensor. unit: mN */ rt_uint32_t dust; /* Dust sensor. unit: ug/m3 */ rt_uint32_t eco2; /* eCO2 sensor. unit: ppm */ - rt_uint32_t spo2; /* SpO2 sensor. unit: % */ + rt_uint32_t spo2; /* SpO2 sensor. unit: permillage */ } data; }; diff --git a/documentation/coding_style_cn.md b/documentation/coding_style_cn.md index 9c4019d647..7a0493f3ac 100644 --- a/documentation/coding_style_cn.md +++ b/documentation/coding_style_cn.md @@ -1,25 +1,18 @@ # RT-Thread 编程风格 -这是一份 RT-Thread 开发人员的开发指引。RT-Thread 做为一份开源软件，它需要由不同 -的人采用合作的方式完成，这份文档是开发人员的一个指引。RT-Thread 的开发人员请遵 -守这样的编程风格。同时对于使用 RT-Thread 的用户，也可通过这份文档了解 RT-Thread -代码内部一些约定从而比较容易的把握到 RT-Thread 的实现方式。 +这是一份 RT-Thread 开发人员的开发指引。RT-Thread 做为一份开源软件，它需要由不同的人采用合作的方式完成，这份文档是开发人员的一个指引。RT-Thread 的开发人员请遵守这样的编程风格。同时对于使用 RT-Thread 的用户，也可通过这份文档了解 RT-Thread代码内部一些约定从而比较容易的把握到 RT-Thread 的实现方式。 ## 1.目录名称 -目录名称如果无特殊的需求，请使用全小写的形式；目录名称应能够反映部分的意思，例 -如各芯片移植由其芯片名称构成或芯片类别构成；components 目录下能够反映组件的意义。 +目录名称如果无特殊的需求，请使用全小写的形式；目录名称应能够反映部分的意思，例如各芯片移植由其芯片名称构成或芯片类别构成；components 目录下能够反映组件的意义。 ## 2.文件名称 -文件名称如果无特殊的需求(如果是引用其他地方，可以保留相应的名称)，请使用全小写 -的形式。另外为了避免文件名重名的问题，一些地方请尽量不要使用通用化、使用频率高 -的名称。 +文件名称如果无特殊的需求(如果是引用其他地方，可以保留相应的名称)，请使用全小写的形式。另外为了避免文件名重名的问题，一些地方请尽量不要使用通用化、使用频率高的名称。 ## 3.头文件定义 -C语言头文件为了避免多次重复包含，需要定义一个符号。这个符号的定义形式请采用如下 -的风格： +C语言头文件为了避免多次重复包含，需要定义一个符号。这个符号的定义形式请采用如下的风格： ```c #ifndef __FILE_H__ @@ -28,8 +21,7 @@ C语言头文件为了避免多次重复包含，需要定义一个符号。这 #endif ``` -即定义的符号两侧采用 "__" 以避免重名，另外也可以根据文件名中是否包含多个词语而 -采用 "_" 连接起来。 +即定义的符号两侧采用 "__" 以避免重名，另外也可以根据文件名中是否包含多个词语而采用 "_" 连接起来。 ## 4.文件头注释 @@ -62,7 +54,7 @@ C语言头文件为了避免多次重复包含，需要定义一个符号。这 }; ``` -其中，"{"，"}" 独立占用一行，后面的成员定义使用缩进的方式定义。 +其中，**"{"，"}" 独立占用一行**，后面的成员定义使用缩进的方式定义。 结构体等的类型定义请以结构体名称加上 "_t" 的形式作为名称，例如： @@ -86,9 +78,7 @@ C语言头文件为了避免多次重复包含，需要定义一个符号。这 ## 7.函数名称、声明 -函数名称请使用小写英文的形式，单词之间使用 "_" 连接。提供给上层应用使用的 API -接口，必须在相应的头文件中声明；如果函数入口参数是空，必须使用 void 作为入口参 -数，例如： +函数名称请使用小写英文的形式，单词之间使用 "_" 连接。提供给上层应用使用的 API接口，必须在相应的头文件中声明；如果函数入口参数是空，必须使用 void 作为入口参数，例如： ```c rt_thread_t rt_thread_self(void); @@ -96,18 +86,13 @@ C语言头文件为了避免多次重复包含，需要定义一个符号。这 ## 8.注释编写 -请使用英文做为注释，使用中文注释将意味着在编写代码时需要来回不停的切换中英文输 -入法从而打断编写代码的思路。并且使用英文注释也能够比较好的与中国以外的技术者进 -行交流。 +请使用英文做为注释，使用中文注释将意味着在编写代码时需要来回不停的切换中英文输入法从而打断编写代码的思路。并且使用英文注释也能够比较好的与中国以外的技术者进行交流。 -源代码的注释不应该过多，更多的说明应该是代码做了什么，仅当个别关键点才需要一些 -相应提示性的注释以解释一段复杂的算法它是如何工作的。对语句的注释只能写在它的上 -方或右方，其他位置都是非法的。 +源代码的注释不应该过多，更多的说明应该是代码做了什么，仅当个别关键点才需要一些相应提示性的注释以解释一段复杂的算法它是如何工作的。对语句的注释只能写在它的上方或右方，其他位置都是非法的。 ## 9.缩进及分行 -缩进请采用 4 个空格的方式。如果没有什么特殊意义，请在 "{" 后进行分行，并在下一 -行都采用缩进的方式，例如： +缩进请采用 4 个空格的方式。如果没有什么特殊意义，请在 "{" 后进行分行，并在下一行都采用缩进的方式，例如： ```c if (condition) @@ -127,9 +112,7 @@ C语言头文件为了避免多次重复包含，需要定义一个符号。这 } ``` -case 语句与前面的 switch 语句对齐，后续的语句则采用缩进的方式。 - -分行上，如果没有什么特殊考虑，请**不要在代码中连续使用两个以上的空行**。 +case 语句与前面的 switch 语句对齐，后续的语句则采用缩进的方式。分行上，如果没有什么特殊考虑，请**不要在代码中连续使用两个以上的空行**。 ## 10.大括号与空格 @@ -142,9 +125,7 @@ case 语句与前面的 switch 语句对齐，后续的语句则采用缩进的 } ``` -匹配的大括号单独占用一行，代码阅读起来就会有相应的层次而不会容易出现混淆的情况。 - -空格建议在非函数方式的括号调用前留一个空格以和前面的进行区分，例如： +匹配的大括号单独占用一行，代码阅读起来就会有相应的层次而不会容易出现混淆的情况。空格建议在非函数方式的括号调用前留一个空格以和前面的进行区分，例如： ```c if (x <= y) @@ -158,8 +139,7 @@ case 语句与前面的 switch 语句对齐，后续的语句则采用缩进的 } ``` -建议在括号前留出一个空格(涉及的包括 if、for、while、switch 语句)，而运算表达式 -中，运算符与字符串间留一个空格。另外，不要在括号的表达式两侧留空格，例如： +建议在括号前留出一个空格(涉及的包括 if、for、while、switch 语句)，而运算表达式中，运算符与字符串间留一个空格。另外，不要在括号的表达式两侧留空格，例如： ```c if ( x <= y ) @@ -172,26 +152,19 @@ case 语句与前面的 switch 语句对齐，后续的语句则采用缩进的 ## 11.trace、log信息 -在 RT-Thread 中，普遍使用的 log 方式是 rt_kprintf。rt_kprintf 在 RT-Thread 被实 -现成一个采用轮询、非中断方式的字串输出，能够适合于在中断这类"即时"显示日志的场 -合。因为这种轮询方式的存在，也必然会影响到日志输出的时序关系。 +在 RT-Thread 中，普遍使用的 log 方式是 rt_kprintf。rt_kprintf 在 RT-Thread 被实现成一个采用轮询、非中断方式的字串输出，能够适合于在中断这类"即时"显示日志的场合。因为这种轮询方式的存在，也必然会影响到日志输出的时序关系。 -建议在代码中不要频繁的使用 rt_kprintf 作为日志输出，除非你真正的明白，你的代码 -运行占用的时间多一些也没什么关系。 +建议在代码中不要频繁的使用 rt_kprintf 作为日志输出，除非你真正的明白，你的代码运行占用的时间多一些也没什么关系。 -日志输出应该被设计成正常情况下是关闭状态(例如通过一个变量或宏就能够开启)，并且 -当真正输出日志时，日志是易懂易定位问题的方式。"天书式"的日志系统是糟糕的，不合 -理的。 +日志输出应该被设计成正常情况下是关闭状态(例如通过一个变量或宏就能够开启)，并且当真正输出日志时，日志是易懂易定位问题的方式。"天书式"的日志系统是糟糕的，不合理的。 ## 12.函数 -在内核编程中，函数应该尽量精简，仅完成相对独立的简单功能。函数的实现不应该太长 -，函数实现太长，应该反思能够如何修改(或拆分)使得函数更为精简、易懂。 +在内核编程中，函数应该尽量精简，仅完成相对独立的简单功能。函数的实现不应该太长，函数实现太长，应该反思能够如何修改(或拆分)使得函数更为精简、易懂。 ## 13.对象 -RT-Thread 内核采用了 C 语言对象化技术，命名表现形式是：对象名结构体表示类定义、 -对象名 + 动词短语形式表示类方法，例如： +RT-Thread 内核采用了 C 语言对象化技术，命名表现形式是：对象名结构体表示类定义、对象名 + 动词短语形式表示类方法，例如： ```c struct rt_timer @@ -215,8 +188,7 @@ RT-Thread 内核采用了 C 语言对象化技术，命名表现形式是：对 rt_timer + 动词短语的形式表示能够应用于 timer 对象的方法。 -在创建一个新的对象时，应该思考好，对象的内存操作处理：是否允许一个静态对象存在 -，或仅仅支持从堆中动态分配的对象。 +在创建一个新的对象时，应该思考好，对象的内存操作处理：是否允许一个静态对象存在，或仅仅支持从堆中动态分配的对象。 ## 14. 用 astyle 自动格式化代码 diff --git a/libcpu/arm/cortex-a/cp15.h b/libcpu/arm/cortex-a/cp15.h index 687199e573..6896fd9f71 100644 --- a/libcpu/arm/cortex-a/cp15.h +++ b/libcpu/arm/cortex-a/cp15.h @@ -10,6 +10,11 @@ #ifndef __CP15_H__ #define __CP15_H__ +#define __get_cp(cp, op1, Rt, CRn, CRm, op2) __asm__ volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) +#define __set_cp(cp, op1, Rt, CRn, CRm, op2) __asm__ volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) +#define __get_cp64(cp, op1, Rt, CRm) __asm__ volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) +#define __set_cp64(cp, op1, Rt, CRm) __asm__ volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + unsigned long rt_cpu_get_smp_id(void); void rt_cpu_mmu_disable(void); diff --git a/libcpu/arm/cortex-a/gic.c b/libcpu/arm/cortex-a/gic.c index faad418b2d..60e924d405 100644 --- a/libcpu/arm/cortex-a/gic.c +++ b/libcpu/arm/cortex-a/gic.c @@ -28,29 +28,35 @@ struct arm_gic /* 'ARM_GIC_MAX_NR' is the number of cores */ static struct arm_gic _gic_table[ARM_GIC_MAX_NR]; -#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00) -#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04) -#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08) -#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0c) -#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10) -#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14) -#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18) +/** Macro to access the Generic Interrupt Controller Interface (GICC) +*/ +#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00U) +#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04U) +#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08U) +#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0cU) +#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10U) +#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14U) +#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18U) +#define GIC_CPU_IIDR(hw_base) __REG32((hw_base) + 0xFCU) -#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000) -#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004) -#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080 + ((n)/32) * 4) -#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100 + ((n)/32) * 4) -#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180 + ((n)/32) * 4) -#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200 + ((n)/32) * 4) -#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280 + ((n)/32) * 4) -#define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300 + ((n)/32) * 4) -#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380 + ((n)/32) * 4) -#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400 + ((n)/4) * 4) -#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800 + ((n)/4) * 4) -#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00 + ((n)/16) * 4) -#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00) -#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10 + ((n)/4) * 4) -#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8) +/** Macro to access the Generic Interrupt Controller Distributor (GICD) +*/ +#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000U) +#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004U) +#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080U + ((n)/32U) * 4U) +#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100U + ((n)/32U) * 4U) +#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180U + ((n)/32U) * 4U) +#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200U + ((n)/32U) * 4U) +#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280U + ((n)/32U) * 4U) +#define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300U + ((n)/32U) * 4U) +#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380U + ((n)/32U) * 4U) +#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400U + ((n)/4U) * 4U) +#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800U + ((n)/4U) * 4U) +#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00U + ((n)/16U) * 4U) +#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00U) +#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10U + ((n)/4U) * 4U) +#define GIC_DIST_SPENDSGI(hw_base, n) __REG32((hw_base) + 0xf20U + ((n)/4U) * 4U) +#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8U) static unsigned int _gic_max_irq; @@ -67,12 +73,12 @@ int arm_gic_get_active_irq(rt_uint32_t index) void arm_gic_ack(rt_uint32_t index, int irq) { - rt_uint32_t mask = 1 << (irq % 32); + rt_uint32_t mask = 1U << (irq % 32U); RT_ASSERT(index < ARM_GIC_MAX_NR); irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0); + RT_ASSERT(irq >= 0U); GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq; @@ -80,36 +86,136 @@ void arm_gic_ack(rt_uint32_t index, int irq) void arm_gic_mask(rt_uint32_t index, int irq) { - rt_uint32_t mask = 1 << (irq % 32); + rt_uint32_t mask = 1U << (irq % 32U); RT_ASSERT(index < ARM_GIC_MAX_NR); irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0); + RT_ASSERT(irq >= 0U); GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; } -void arm_gic_clear_pending(rt_uint32_t index, int irq) +void arm_gic_umask(rt_uint32_t index, int irq) { - rt_uint32_t mask = 1 << (irq % 32); + rt_uint32_t mask = 1U << (irq % 32U); RT_ASSERT(index < ARM_GIC_MAX_NR); irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0); + RT_ASSERT(irq >= 0U); - GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; + GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; +} + +rt_uint32_t arm_gic_get_pending_irq(rt_uint32_t index, int irq) +{ + rt_uint32_t pend; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + if (irq >= 16U) + { + pend = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; + } + else + { + /* INTID 0-15 Software Generated Interrupt */ + pend = (GIC_DIST_SPENDSGI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; + /* No CPU identification offered */ + if (pend != 0U) + { + pend = 1U; + } + else + { + pend = 0U; + } + } + + return (pend); +} + +void arm_gic_set_pending_irq(rt_uint32_t index, int irq) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + if (irq >= 16U) + { + GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) = 1U << (irq % 32U); + } + else + { + /* INTID 0-15 Software Generated Interrupt */ + /* Forward the interrupt to the CPU interface that requested it */ + GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = (irq | 0x02000000U); + } +} + +void arm_gic_clear_pending_irq(rt_uint32_t index, int irq) +{ + rt_uint32_t mask; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + if (irq >= 16U) + { + mask = 1U << (irq % 32U); + GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; + } + else + { + mask = 1U << ((irq % 4U) * 8U); + GIC_DIST_CPENDSGI(_gic_table[index].dist_hw_base, irq) = mask; + } +} + +void arm_gic_set_configuration(rt_uint32_t index, int irq, uint32_t config) +{ + rt_uint32_t icfgr; + rt_uint32_t shift; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + icfgr = GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq); + shift = (irq % 16U) << 1U; + + icfgr &= (~(3U << shift)); + icfgr |= (config << shift); + + GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) = icfgr; +} + +rt_uint32_t arm_gic_get_configuration(rt_uint32_t index, int irq) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + return (GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) >> ((irq % 16U) >> 1U)); } void arm_gic_clear_active(rt_uint32_t index, int irq) { - rt_uint32_t mask = 1 << (irq % 32); + rt_uint32_t mask = 1U << (irq % 32U); RT_ASSERT(index < ARM_GIC_MAX_NR); irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0); + RT_ASSERT(irq >= 0U); GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; } @@ -122,79 +228,149 @@ void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask) RT_ASSERT(index < ARM_GIC_MAX_NR); irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0); + RT_ASSERT(irq >= 0U); old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq); - old_tgt &= ~(0x0FFUL << ((irq % 4)*8)); - old_tgt |= cpumask << ((irq % 4)*8); + old_tgt &= ~(0x0FFUL << ((irq % 4U)*8U)); + old_tgt |= cpumask << ((irq % 4U)*8U); GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt; } -void arm_gic_umask(rt_uint32_t index, int irq) +rt_uint32_t arm_gic_get_target_cpu(rt_uint32_t index, int irq) { - rt_uint32_t mask = 1 << (irq % 32); + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + return (GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; +} + +void arm_gic_set_priority(rt_uint32_t index, int irq, rt_uint32_t priority) +{ + rt_uint32_t mask; RT_ASSERT(index < ARM_GIC_MAX_NR); irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0); + RT_ASSERT(irq >= 0U); - GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; + mask = GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq); + mask &= ~(0xFFUL << ((irq % 4U) * 8U)); + mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U)); + GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) = mask; } -void arm_gic_dump_type(rt_uint32_t index) +rt_uint32_t arm_gic_get_priority(rt_uint32_t index, int irq) { - unsigned int gic_type; + RT_ASSERT(index < ARM_GIC_MAX_NR); - gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base); - rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n", - (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4) & 0xf, - _gic_table[index].dist_hw_base, - _gic_max_irq, - gic_type & (1 << 10) ? "has" : "no", - gic_type); + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + return (GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; } -void arm_gic_dump(rt_uint32_t index) +void arm_gic_set_interface_prior_mask(rt_uint32_t index, rt_uint32_t priority) { - unsigned int i, k; + RT_ASSERT(index < ARM_GIC_MAX_NR); - k = GIC_CPU_HIGHPRI(_gic_table[index].cpu_hw_base); - rt_kprintf("--- high pending priority: %d(%08x)\n", k, k); - rt_kprintf("--- hw mask ---\n"); - for (i = 0; i < _gic_max_irq / 32; i++) - { - rt_kprintf("0x%08x, ", - GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, - i * 32)); - } - rt_kprintf("\n--- hw pending ---\n"); - for (i = 0; i < _gic_max_irq / 32; i++) - { - rt_kprintf("0x%08x, ", - GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, - i * 32)); - } - rt_kprintf("\n--- hw active ---\n"); - for (i = 0; i < _gic_max_irq / 32; i++) - { - rt_kprintf("0x%08x, ", - GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, - i * 32)); - } - rt_kprintf("\n"); + /* set priority mask */ + GIC_CPU_PRIMASK(_gic_table[index].cpu_hw_base) = priority & 0xFFUL; +} + +rt_uint32_t arm_gic_get_interface_prior_mask(rt_uint32_t index) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + return GIC_CPU_PRIMASK(_gic_table[index].cpu_hw_base); +} + +void arm_gic_set_binary_point(rt_uint32_t index, rt_uint32_t binary_point) +{ + GIC_CPU_BINPOINT(_gic_table[index].cpu_hw_base) = binary_point & 0x7U; +} + +rt_uint32_t arm_gic_get_binary_point(rt_uint32_t index) +{ + return GIC_CPU_BINPOINT(_gic_table[index].cpu_hw_base); +} + +rt_uint32_t arm_gic_get_irq_status(rt_uint32_t index, int irq) +{ + rt_uint32_t pending; + rt_uint32_t active; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + active = (GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; + pending = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; + + return ((active << 1U) | pending); +} + +void arm_gic_send_sgi(rt_uint32_t index, int irq, rt_uint32_t target_list, rt_uint32_t filter_list) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = ((filter_list & 0x3U) << 24U) | ((target_list & 0xFFUL) << 16U) | (irq & 0x0FUL); +} + +rt_uint32_t arm_gic_get_high_pending_irq(rt_uint32_t index) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + return GIC_CPU_HIGHPRI(_gic_table[index].cpu_hw_base); +} + +rt_uint32_t arm_gic_get_interface_id(rt_uint32_t index) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + return GIC_CPU_IIDR(_gic_table[index].cpu_hw_base); +} + +void arm_gic_set_group(rt_uint32_t index, int irq, rt_uint32_t group) +{ + uint32_t igroupr; + uint32_t shift; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + RT_ASSERT(group <= 1U); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + igroupr = GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq); + shift = (irq % 32U); + igroupr &= (~(1U << shift)); + igroupr |= ( (group & 0x1U) << shift); + + GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) = igroupr; +} + +rt_uint32_t arm_gic_get_group(rt_uint32_t index, int irq) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + return (GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; } -#ifdef RT_USING_FINSH -#include -FINSH_FUNCTION_EXPORT_ALIAS(arm_gic_dump, gic, show gic status); -#endif int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start) { unsigned int gic_type, i; - rt_uint32_t cpumask = 1 << 0; + rt_uint32_t cpumask = 1U << 0U; RT_ASSERT(index < ARM_GIC_MAX_NR); @@ -203,50 +379,50 @@ int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start) /* Find out how many interrupts are supported. */ gic_type = GIC_DIST_TYPE(dist_base); - _gic_max_irq = ((gic_type & 0x1f) + 1) * 32; + _gic_max_irq = ((gic_type & 0x1fU) + 1U) * 32U; /* * The GIC only supports up to 1020 interrupt sources. * Limit this to either the architected maximum, or the * platform maximum. */ - if (_gic_max_irq > 1020) - _gic_max_irq = 1020; + if (_gic_max_irq > 1020U) + _gic_max_irq = 1020U; if (_gic_max_irq > ARM_GIC_NR_IRQS) /* the platform maximum interrupts */ _gic_max_irq = ARM_GIC_NR_IRQS; - cpumask |= cpumask << 8; - cpumask |= cpumask << 16; - cpumask |= cpumask << 24; + cpumask |= cpumask << 8U; + cpumask |= cpumask << 16U; + cpumask |= cpumask << 24U; - GIC_DIST_CTRL(dist_base) = 0x0; + GIC_DIST_CTRL(dist_base) = 0x0U; /* Set all global interrupts to be level triggered, active low. */ - for (i = 32; i < _gic_max_irq; i += 16) - GIC_DIST_CONFIG(dist_base, i) = 0x0; + for (i = 32U; i < _gic_max_irq; i += 16U) + GIC_DIST_CONFIG(dist_base, i) = 0x0U; /* Set all global interrupts to this CPU only. */ - for (i = 32; i < _gic_max_irq; i += 4) + for (i = 32U; i < _gic_max_irq; i += 4U) GIC_DIST_TARGET(dist_base, i) = cpumask; /* Set priority on all interrupts. */ - for (i = 0; i < _gic_max_irq; i += 4) - GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0; + for (i = 0U; i < _gic_max_irq; i += 4U) + GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0U; /* Disable all interrupts. */ - for (i = 0; i < _gic_max_irq; i += 32) - GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffff; + for (i = 0U; i < _gic_max_irq; i += 32U) + GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffffU; #if 0 /* All interrupts defaults to IGROUP1(IRQ). */ for (i = 0; i < _gic_max_irq; i += 32) GIC_DIST_IGROUP(dist_base, i) = 0xffffffff; #endif - for (i = 0; i < _gic_max_irq; i += 32) - GIC_DIST_IGROUP(dist_base, i) = 0; + for (i = 0U; i < _gic_max_irq; i += 32U) + GIC_DIST_IGROUP(dist_base, i) = 0U; /* Enable group0 and group1 interrupt forwarding. */ - GIC_DIST_CTRL(dist_base) = 0x01; + GIC_DIST_CTRL(dist_base) = 0x01U; return 0; } @@ -257,44 +433,63 @@ int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base) _gic_table[index].cpu_hw_base = cpu_base; - GIC_CPU_PRIMASK(cpu_base) = 0xf0; - GIC_CPU_BINPOINT(cpu_base) = 0x7; + GIC_CPU_PRIMASK(cpu_base) = 0xf0U; + GIC_CPU_BINPOINT(cpu_base) = 0x7U; /* Enable CPU interrupt */ - GIC_CPU_CTRL(cpu_base) = 0x01; + GIC_CPU_CTRL(cpu_base) = 0x01U; return 0; } -void arm_gic_set_group(rt_uint32_t index, int vector, int group) +void arm_gic_dump_type(rt_uint32_t index) { - /* As for GICv2, there are only group0 and group1. */ - RT_ASSERT(group <= 1); - RT_ASSERT(vector < _gic_max_irq); + unsigned int gic_type; - if (group == 0) - { - GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, - vector) &= ~(1 << (vector % 32)); - } - else if (group == 1) - { - GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, - vector) |= (1 << (vector % 32)); - } + gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base); + rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n", + (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4U) & 0xfUL, + _gic_table[index].dist_hw_base, + _gic_max_irq, + gic_type & (1U << 10U) ? "has" : "no", + gic_type); } -#ifdef RT_USING_SMP -void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask) - { - /* note: ipi_vector maybe different with irq_vector */ - GIC_DIST_SOFTINT(_gic_table[0].dist_hw_base) = (cpu_mask << 16) | ipi_vector; -} -#endif - -#ifdef RT_USING_SMP -void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler) +void arm_gic_dump(rt_uint32_t index) { - /* note: ipi_vector maybe different with irq_vector */ - rt_hw_interrupt_install(ipi_vector, ipi_isr_handler, 0, "IPI_HANDLER"); + unsigned int i, k; + + k = GIC_CPU_HIGHPRI(_gic_table[index].cpu_hw_base); + rt_kprintf("--- high pending priority: %d(%08x)\n", k, k); + rt_kprintf("--- hw mask ---\n"); + for (i = 0U; i < _gic_max_irq / 32U; i++) + { + rt_kprintf("0x%08x, ", + GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, + i * 32U)); + } + rt_kprintf("\n--- hw pending ---\n"); + for (i = 0U; i < _gic_max_irq / 32U; i++) + { + rt_kprintf("0x%08x, ", + GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, + i * 32U)); + } + rt_kprintf("\n--- hw active ---\n"); + for (i = 0U; i < _gic_max_irq / 32U; i++) + { + rt_kprintf("0x%08x, ", + GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, + i * 32U)); + } + rt_kprintf("\n"); } -#endif + +long gic_dump(void) +{ + arm_gic_dump_type(0); + arm_gic_dump(0); + + return 0; +} +MSH_CMD_EXPORT(gic_dump, show gic status); + diff --git a/libcpu/arm/cortex-a/gic.h b/libcpu/arm/cortex-a/gic.h index e48f9f854d..e74b760f45 100644 --- a/libcpu/arm/cortex-a/gic.h +++ b/libcpu/arm/cortex-a/gic.h @@ -14,19 +14,46 @@ #include #include -int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start); -int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base); - -void arm_gic_mask(rt_uint32_t index, int irq); -void arm_gic_umask(rt_uint32_t index, int irq); -void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask); -void arm_gic_set_group(rt_uint32_t index, int vector, int group); - int arm_gic_get_active_irq(rt_uint32_t index); void arm_gic_ack(rt_uint32_t index, int irq); +void arm_gic_mask(rt_uint32_t index, int irq); +void arm_gic_umask(rt_uint32_t index, int irq); + +rt_uint32_t arm_gic_get_pending_irq(rt_uint32_t index, int irq); +void arm_gic_set_pending_irq(rt_uint32_t index, int irq); +void arm_gic_clear_pending_irq(rt_uint32_t index, int irq); + +void arm_gic_set_configuration(rt_uint32_t index, int irq, uint32_t config); +rt_uint32_t arm_gic_get_configuration(rt_uint32_t index, int irq); + void arm_gic_clear_active(rt_uint32_t index, int irq); -void arm_gic_clear_pending(rt_uint32_t index, int irq); + +void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask); +rt_uint32_t arm_gic_get_target_cpu(rt_uint32_t index, int irq); + +void arm_gic_set_priority(rt_uint32_t index, int irq, rt_uint32_t priority); +rt_uint32_t arm_gic_get_priority(rt_uint32_t index, int irq); + +void arm_gic_set_interface_prior_mask(rt_uint32_t index, rt_uint32_t priority); +rt_uint32_t arm_gic_get_interface_prior_mask(rt_uint32_t index); + +void arm_gic_set_binary_point(rt_uint32_t index, rt_uint32_t binary_point); +rt_uint32_t arm_gic_get_binary_point(rt_uint32_t index); + +rt_uint32_t arm_gic_get_irq_status(rt_uint32_t index, int irq); + +void arm_gic_send_sgi(rt_uint32_t index, int irq, rt_uint32_t target_list, rt_uint32_t filter_list); + +rt_uint32_t arm_gic_get_high_pending_irq(rt_uint32_t index); + +rt_uint32_t arm_gic_get_interface_id(rt_uint32_t index); + +void arm_gic_set_group(rt_uint32_t index, int irq, rt_uint32_t group); +rt_uint32_t arm_gic_get_group(rt_uint32_t index, int irq); + +int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start); +int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base); void arm_gic_dump_type(rt_uint32_t index); void arm_gic_dump(rt_uint32_t index); diff --git a/libcpu/arm/cortex-a/gtimer.c b/libcpu/arm/cortex-a/gtimer.c new file mode 100644 index 0000000000..b193a1593d --- /dev/null +++ b/libcpu/arm/cortex-a/gtimer.c @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-03-30 huijie.feng first version + */ + +#include "cp15.h" +#include + +/** Set CNTFRQ + * This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ). + * @param value: CNTFRQ Register value to set + */ +static inline void __set_cntfrq(rt_uint32_t value) +{ + __set_cp(15, 0, value, 14, 0, 0); +} + +/** Get CNTFRQ + * This function returns the value of the PL1 Physical Timer Counter Frequency Register (CNTFRQ). + * return CNTFRQ Register value + */ +static inline rt_uint32_t __get_cntfrq(void) +{ + rt_uint32_t result; + __get_cp(15, 0, result, 14, 0 , 0); + return result; +} + +/** Set CNTP_TVAL + * This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL). + * param value: CNTP_TVAL Register value to set + */ +static inline void __set_cntp_tval(rt_uint32_t value) +{ + __set_cp(15, 0, value, 14, 2, 0); +} + +/** Get CNTP_TVAL + * This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL). + * return CNTP_TVAL Register value + */ +static inline rt_uint32_t __get_cntp_tval(void) +{ + rt_uint32_t result; + __get_cp(15, 0, result, 14, 2, 0); + return result; +} + +/** Get CNTPCT + * This function returns the value of the 64 bits PL1 Physical Count Register (CNTPCT). + * return CNTPCT Register value + */ +static inline rt_uint64_t __get_cntpct(void) +{ + rt_uint64_t result; + __get_cp64(15, 0, result, 14); + return result; +} + +/** Set CNTP_CVAL + * This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL). + * param value: CNTP_CVAL Register value to set +*/ +static inline void __set_cntp_cval(rt_uint64_t value) +{ + __set_cp64(15, 2, value, 14); +} + +/** Get CNTP_CVAL + * This function returns the value of the 64 bits PL1 Physical Timer CompareValue Register (CNTP_CVAL). + * return CNTP_CVAL Register value + */ +static inline rt_uint64_t __get_cntp_cval(void) +{ + rt_uint64_t result; + __get_cp64(15, 2, result, 14); + return result; +} + +/** Set CNTP_CTL + * This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL). + * param value: CNTP_CTL Register value to set + */ +static inline void __set_cntp_ctl(uint32_t value) +{ + __set_cp(15, 0, value, 14, 2, 1); +} + +/** Get CNTP_CTL register + * return CNTP_CTL Register value + */ +static inline rt_uint32_t __get_cntp_ctl(void) +{ + rt_uint32_t result; + __get_cp(15, 0, result, 14, 2, 1); + return result; +} + +/** Configures the frequency the timer shall run at. + * param value The timer frequency in Hz. + */ +void gtimer_set_counter_frequency(rt_uint32_t value) +{ + __set_cntfrq(value); + __asm__ volatile ("isb 0xF":::"memory"); +} + +/** Sets the reset value of the timer. + * param value: The value the timer is loaded with. + */ +void gtimer_set_load_value(rt_uint32_t value) +{ + __set_cntp_tval(value); + __asm__ volatile ("isb 0xF":::"memory"); +} + +/** Get the current counter value. + * return Current counter value. + */ +rt_uint32_t gtimer_get_current_value(void) +{ + return(__get_cntp_tval()); +} + +/** Get the current physical counter value. + * return Current physical counter value. + */ +rt_uint64_t gtimer_get_current_physical_value(void) +{ + return(__get_cntpct()); +} + +/** Set the physical compare value. + * param value: New physical timer compare value. + */ +void gtimer_set_physical_compare_value(rt_uint64_t value) +{ + __set_cntp_cval(value); + __asm__ volatile ("isb 0xF":::"memory"); +} + +/** Get the physical compare value. + * return Physical compare value. + */ +rt_uint64_t gtimer_get_physical_compare_value(void) +{ + return(__get_cntp_cval()); +} + +/** Configure the timer by setting the control value. + * param value: New timer control value. + */ +void gtimer_set_control(rt_uint32_t value) +{ + __set_cntp_ctl(value); + __asm__ volatile ("isb 0xF":::"memory"); +} + +/** Get the control value. + * return Control value. + */ +rt_uint32_t gtimer_get_control(void) +{ + return(__get_cntp_ctl()); +} + diff --git a/libcpu/arm/cortex-a/gtimer.h b/libcpu/arm/cortex-a/gtimer.h new file mode 100644 index 0000000000..160d0cefde --- /dev/null +++ b/libcpu/arm/cortex-a/gtimer.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-03-30 huijie.feng first version + */ + +#ifndef __GTIMER_H__ +#define __GTIMER_H__ + +#include + +void gtimer_set_counter_frequency(rt_uint32_t value); +void gtimer_set_load_value(rt_uint32_t value); +rt_uint32_t gtimer_get_current_value(void); +rt_uint64_t gtimer_get_current_physical_value(void); +void gtimer_set_physical_compare_value(rt_uint64_t value); +rt_uint64_t gtimer_get_physical_compare_value(void); +void gtimer_set_control(rt_uint32_t value); +rt_uint32_t gtimer_get_control(void); + +#endif + diff --git a/libcpu/arm/cortex-a/interrupt.c b/libcpu/arm/cortex-a/interrupt.c index 0d440d1d0e..65e51fa3ae 100644 --- a/libcpu/arm/cortex-a/interrupt.c +++ b/libcpu/arm/cortex-a/interrupt.c @@ -83,7 +83,7 @@ void rt_hw_interrupt_umask(int vector) */ int rt_hw_interrupt_get_irq(void) { - return arm_gic_get_active_irq(0) & GIC_ACK_INTID_MASK; + return arm_gic_get_active_irq(0); } /** @@ -94,6 +94,150 @@ void rt_hw_interrupt_ack(int vector) { arm_gic_ack(0, vector); } + +/** + * This function set interrupt CPU targets. + * @param vector: the interrupt number + * cpu_mask: target cpus mask, one bit for one core + */ +void rt_hw_interrupt_set_target_cpus(int vector, unsigned int cpu_mask) +{ + arm_gic_set_cpu(0, vector, cpu_mask); +} + +/** + * This function get interrupt CPU targets. + * @param vector: the interrupt number + * @return target cpus mask, one bit for one core + */ +unsigned int rt_hw_interrupt_get_target_cpus(int vector) +{ + return arm_gic_get_target_cpu(0, vector); +} + +/** + * This function set interrupt triger mode. + * @param vector: the interrupt number + * mode: interrupt triger mode; 0: level triger, 1: edge triger + */ +void rt_hw_interrupt_set_triger_mode(int vector, unsigned int mode) +{ + arm_gic_set_configuration(0, vector, mode); +} + +/** + * This function get interrupt triger mode. + * @param vector: the interrupt number + * @return interrupt triger mode; 0: level triger, 1: edge triger + */ +unsigned int rt_hw_interrupt_get_triger_mode(int vector) +{ + return arm_gic_get_configuration(0, vector); +} + +/** + * This function set interrupt pending flag. + * @param vector: the interrupt number + */ +void rt_hw_interrupt_set_pending(int vector) +{ + arm_gic_set_pending_irq(0, vector); +} + +/** + * This function get interrupt pending flag. + * @param vector: the interrupt number + * @return interrupt pending flag, 0: not pending; 1: pending + */ +unsigned int rt_hw_interrupt_get_pending(int vector) +{ + return arm_gic_get_pending_irq(0, vector); +} + +/** + * This function clear interrupt pending flag. + * @param vector: the interrupt number + */ +void rt_hw_interrupt_clear_pending(int vector) +{ + arm_gic_clear_pending_irq(0, vector); +} + +/** + * This function set interrupt priority value. + * @param vector: the interrupt number + * priority: the priority of interrupt to set + */ +void rt_hw_interrupt_set_priority(int vector, unsigned int priority) +{ + arm_gic_set_priority(0, vector, priority); +} + +/** + * This function get interrupt priority. + * @param vector: the interrupt number + * @return interrupt priority value + */ +unsigned int rt_hw_interrupt_get_priority(int vector) +{ + return arm_gic_get_priority(0, vector); +} + +/** + * This function set priority masking threshold. + * @param priority: priority masking threshold + */ +void rt_hw_interrupt_set_priority_mask(unsigned int priority) +{ + arm_gic_set_interface_prior_mask(0, priority); +} + +/** + * This function get priority masking threshold. + * @param none + * @return priority masking threshold + */ +unsigned int rt_hw_interrupt_get_priority_mask(void) +{ + return arm_gic_get_interface_prior_mask(0); +} + +/** + * This function set priority grouping field split point. + * @param bits: priority grouping field split point + * @return 0: success; -1: failed + */ +int rt_hw_interrupt_set_prior_group_bits(unsigned int bits) +{ + int status; + + if (bits < 8) + { + arm_gic_set_binary_point(0, (7 - bits)); + status = 0; + } + else + { + status = -1; + } + + return (status); +} + +/** + * This function get priority grouping field split point. + * @param none + * @return priority grouping field split point + */ +unsigned int rt_hw_interrupt_get_prior_group_bits(void) +{ + unsigned int bp; + + bp = arm_gic_get_binary_point(0) & 0x07; + + return (7 - bp); +} + /** * This function will install a interrupt service routine to a interrupt. * @param vector the interrupt number @@ -121,3 +265,17 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, return old_handler; } + +#ifdef RT_USING_SMP +void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask) +{ + arm_gic_send_sgi(0, ipi_vector, cpu_mask, 0); +} + +void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler) +{ + /* note: ipi_vector maybe different with irq_vector */ + rt_hw_interrupt_install(ipi_vector, ipi_isr_handler, 0, "IPI_HANDLER"); +} +#endif + diff --git a/libcpu/arm/cortex-a/interrupt.h b/libcpu/arm/cortex-a/interrupt.h index a8a9afb95c..dda6c5534a 100644 --- a/libcpu/arm/cortex-a/interrupt.h +++ b/libcpu/arm/cortex-a/interrupt.h @@ -17,9 +17,10 @@ #define INT_IRQ 0x00 #define INT_FIQ 0x01 -void rt_hw_vector_init(void); +#define IRQ_MODE_TRIG_LEVEL (0x00) /* Trigger: level triggered interrupt */ +#define IRQ_MODE_TRIG_EDGE (0x01) /* Trigger: edge triggered interrupt */ -void rt_hw_interrupt_control(int vector, int priority, int route); +void rt_hw_vector_init(void); void rt_hw_interrupt_init(void); void rt_hw_interrupt_mask(int vector); @@ -28,7 +29,32 @@ void rt_hw_interrupt_umask(int vector); int rt_hw_interrupt_get_irq(void); void rt_hw_interrupt_ack(int vector); +void rt_hw_interrupt_set_target_cpus(int vector, unsigned int cpu_mask); +unsigned int rt_hw_interrupt_get_target_cpus(int vector); + +void rt_hw_interrupt_set_triger_mode(int vector, unsigned int mode); +unsigned int rt_hw_interrupt_get_triger_mode(int vector); + +void rt_hw_interrupt_set_pending(int vector); +unsigned int rt_hw_interrupt_get_pending(int vector); +void rt_hw_interrupt_clear_pending(int vector); + +void rt_hw_interrupt_set_priority(int vector, unsigned int priority); +unsigned int rt_hw_interrupt_get_priority(int vector); + +void rt_hw_interrupt_set_priority_mask(unsigned int priority); +unsigned int rt_hw_interrupt_get_priority_mask(void); + +int rt_hw_interrupt_set_prior_group_bits(unsigned int bits); +unsigned int rt_hw_interrupt_get_prior_group_bits(void); + rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, void *param, const char *name); +#ifdef RT_USING_SMP +void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask); +void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler); #endif + +#endif + diff --git a/libcpu/arm/cortex-a/trap.c b/libcpu/arm/cortex-a/trap.c index a213e776c7..3faa136677 100644 --- a/libcpu/arm/cortex-a/trap.c +++ b/libcpu/arm/cortex-a/trap.c @@ -47,30 +47,24 @@ void rt_hw_trap_undef(struct rt_hw_exp_stack *regs) { #ifdef RT_USING_FPU { - uint32_t ins; + uint32_t val; uint32_t addr; if (regs->cpsr & (1 << 5)) { /* thumb mode */ addr = regs->pc - 2; - ins = (uint32_t)*(uint16_t*)addr; - if ((ins & (3 << 11)) != 0) - { - /* 32 bit ins */ - ins <<= 16; - ins += *(uint16_t*)(addr + 2); - } } else { addr = regs->pc - 4; - ins = *(uint32_t*)addr; } - if ((ins & 0xe00) == 0xa00) + asm volatile ("vmrs %0, fpexc" : "=r"(val)::"memory"); + + if (!(val & 0x40000000)) { /* float ins */ - uint32_t val = (1U << 30); + val = (1U << 30); asm volatile ("vmsr fpexc, %0"::"r"(val):"memory"); regs->pc = addr; diff --git a/src/Kconfig b/src/Kconfig index 0b1735e004..6afb719395 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -116,10 +116,18 @@ config RT_TIMER_THREAD_STACK_SIZE endif +menu "kservice optimization" + config RT_KSERVICE_USING_STDLIB bool "Enable kservice to use standard C library" default n +config RT_KSERVICE_USING_TINY_SIZE + bool "Enable kservice to use tiny size" + default n + +endmenu + menuconfig RT_DEBUG bool "Enable debugging features" default y diff --git a/src/kservice.c b/src/kservice.c index bd0650ac37..e9972dba97 100644 --- a/src/kservice.c +++ b/src/kservice.c @@ -126,7 +126,7 @@ RTM_EXPORT(_rt_errno); */ RT_WEAK void *rt_memset(void *s, int c, rt_ubase_t count) { -#ifdef RT_USING_TINY_SIZE +#ifdef RT_KSERVICE_USING_TINY_SIZE char *xs = (char *)s; while (count--) @@ -210,7 +210,7 @@ RTM_EXPORT(rt_memset); */ RT_WEAK void *rt_memcpy(void *dst, const void *src, rt_ubase_t count) { -#ifdef RT_USING_TINY_SIZE +#ifdef RT_KSERVICE_USING_TINY_SIZE char *tmp = (char *)dst, *s = (char *)src; rt_ubase_t len; diff --git a/tools/auto-ci.py b/tools/auto-ci.py index 67834544d8..bbb384cec2 100644 --- a/tools/auto-ci.py +++ b/tools/auto-ci.py @@ -52,7 +52,7 @@ fail = False BSP_ROOT = '../bsp' -for bsp,cpu in bsp_to_cpu.iteritems(): +for bsp,cpu in bsp_to_cpu.items(): project_dir = os.path.join(BSP_ROOT, bsp) if os.getenv('RTT_CPU') == cpu and os.path.isfile(os.path.join(project_dir, 'SConstruct')): if os.system('scons --directory=' + project_dir) != 0: @@ -63,10 +63,10 @@ for bsp,cpu in bsp_to_cpu.iteritems(): else: results['ignore'].append(bsp) -for result,bsp_list in results.iteritems(): - print "## {0}: {1}\n".format(result, len(bsp_list)) +for result,bsp_list in results.items(): + print("## {0}: {1}\n".format(result, len(bsp_list))) for bsp in bsp_list: - print "* " + bsp + print("* " + bsp) if fail: sys.exit(1) diff --git a/tools/buildbot.py b/tools/buildbot.py index ecc0031195..bcce3449ec 100644 --- a/tools/buildbot.py +++ b/tools/buildbot.py @@ -2,9 +2,9 @@ import os import sys def usage(): - print '%s all -- build all bsp' % os.path.basename(sys.argv[0]) - print '%s clean -- clean all bsp' % os.path.basename(sys.argv[0]) - print '%s project -- update all prject files' % os.path.basename(sys.argv[0]) + print('%s all -- build all bsp' % os.path.basename(sys.argv[0])) + print('%s clean -- clean all bsp' % os.path.basename(sys.argv[0])) + print('%s project -- update all prject files' % os.path.basename(sys.argv[0])) BSP_ROOT = os.path.join("..", "bsp") @@ -25,25 +25,25 @@ elif sys.argv[1] == 'project': project_dir = os.path.join(BSP_ROOT, item) if os.path.isfile(os.path.join(project_dir, 'template.Uv2')): - print ('prepare MDK3 project file on ' + project_dir) + print('prepare MDK3 project file on ' + project_dir) command = ' --target=mdk -s' os.system('scons --directory=' + project_dir + command) if os.path.isfile(os.path.join(project_dir, 'template.uvproj')): - print ('prepare MDK4 project file on ' + project_dir) + print('prepare MDK4 project file on ' + project_dir) command = ' --target=mdk4 -s' os.system('scons --directory=' + project_dir + command) if os.path.isfile(os.path.join(project_dir, 'template.uvprojx')): - print ('prepare MDK5 project file on ' + project_dir) + print('prepare MDK5 project file on ' + project_dir) command = ' --target=mdk5 -s' os.system('scons --directory=' + project_dir + command) if os.path.isfile(os.path.join(project_dir, 'template.ewp')): - print ('prepare IAR project file on ' + project_dir) + print('prepare IAR project file on ' + project_dir) command = ' --target=iar -s' os.system('scons --directory=' + project_dir + command) @@ -58,5 +58,5 @@ for item in projects: project_dir = os.path.join(BSP_ROOT, item) if os.path.isfile(os.path.join(project_dir, 'SConstruct')): if os.system('scons --directory=' + project_dir + command) != 0: - print 'build failed!!' + print('build failed!!') break diff --git a/tools/building.py b/tools/building.py index 00a9f04107..2498aa2304 100644 --- a/tools/building.py +++ b/tools/building.py @@ -85,7 +85,7 @@ class Win32Spawn: try: os.remove(f) except Exception as e: - print ('Error removing file: ' + e) + print('Error removing file: ' + e) return -1 return 0 @@ -106,8 +106,8 @@ class Win32Spawn: try: proc = subprocess.Popen(cmdline, env=_e, shell=False) except Exception as e: - print ('Error in calling command:' + cmdline.split(' ')[0]) - print ('Exception: ' + os.strerror(e.errno)) + print('Error in calling command:' + cmdline.split(' ')[0]) + print('Exception: ' + os.strerror(e.errno)) if (os.strerror(e.errno) == "No such file or directory"): print ("\nPlease check Toolchains PATH setting.\n") @@ -274,7 +274,7 @@ def PrepareBuilding(env, root_directory, has_libcpu=False, remove_components = [ os.environ['RTT_CC'] = rtconfig.CROSS_TOOL utils.ReloadModule(rtconfig) except KeyError: - print ('Unknow target: '+ tgt_name+'. Avaible targets: ' +', '.join(tgt_dict.keys())) + print('Unknow target: '+ tgt_name+'. Avaible targets: ' +', '.join(tgt_dict.keys())) sys.exit(1) # auto change the 'RTT_EXEC_PATH' when 'rtconfig.EXEC_PATH' get failed @@ -662,7 +662,7 @@ def DefineGroup(name, src, depend, **parameters): # check whether to clean up library if GetOption('cleanlib') and os.path.exists(os.path.join(group['path'], GroupLibFullName(name, Env))): if group['src'] != []: - print ('Remove library:'+ GroupLibFullName(name, Env)) + print('Remove library:'+ GroupLibFullName(name, Env)) fn = os.path.join(group['path'], GroupLibFullName(name, Env)) if os.path.exists(fn): os.unlink(fn) @@ -735,7 +735,7 @@ def BuildLibInstallAction(target, source, env): if Group['name'] == lib_name: lib_name = GroupLibFullName(Group['name'], env) dst_name = os.path.join(Group['path'], lib_name) - print ('Copy '+lib_name+' => ' +dst_name) + print('Copy '+lib_name+' => ' + dst_name) do_copy_file(lib_name, dst_name) break @@ -996,11 +996,11 @@ def GetVersion(): prepcessor.process_contents(contents) def_ns = prepcessor.cpp_namespace - version = int(filter(lambda ch: ch in '0123456789.', def_ns['RT_VERSION'])) - subversion = int(filter(lambda ch: ch in '0123456789.', def_ns['RT_SUBVERSION'])) + version = int([ch for ch in def_ns['RT_VERSION'] if ch in '0123456789.']) + subversion = int([ch for ch in def_ns['RT_SUBVERSION'] if ch in '0123456789.']) if 'RT_REVISION' in def_ns: - revision = int(filter(lambda ch: ch in '0123456789.', def_ns['RT_REVISION'])) + revision = int([ch for ch in def_ns['RT_REVISION'] if ch in '0123456789.']) return '%d.%d.%d' % (version, subversion, revision) return '0.%d.%d' % (version, subversion) diff --git a/tools/clang-analyze.py b/tools/clang-analyze.py index e73f30ca31..7004ba610b 100644 --- a/tools/clang-analyze.py +++ b/tools/clang-analyze.py @@ -53,9 +53,9 @@ def generate(env): if rtconfig.EXEC_PATH: if not os.path.exists(rtconfig.EXEC_PATH): - print - print 'warning: rtconfig.EXEC_PATH(%s) does not exists.' % rtconfig.EXEC_PATH - print + print() + print('warning: rtconfig.EXEC_PATH(%s) does not exists.' % rtconfig.EXEC_PATH) + print() return env.AppendENVPath('PATH', rtconfig.EXEC_PATH) diff --git a/tools/eclipse.py b/tools/eclipse.py index 4d5e28e02e..6498c1c9f6 100644 --- a/tools/eclipse.py +++ b/tools/eclipse.py @@ -212,7 +212,7 @@ def HandleToolOption(tools, env, project, reset): linker_nostart_option = option elif option.get('id').find('linker.libs') != -1: linker_libs_option = option - elif option.get('id').find('linker.paths') != -1 and env.has_key('LIBPATH'): + elif option.get('id').find('linker.paths') != -1 and 'LIBPATH' in env: linker_paths_option = option elif option.get('id').find('linker.usenewlibnano') != -1: linker_newlib_nano_option = option @@ -317,7 +317,7 @@ def HandleToolOption(tools, env, project, reset): option.remove(item) # add new libs - if env.has_key('LIBS'): + if 'LIBS' in env: for lib in env['LIBS']: formatedLib = ConverToRttEclipseLibFormat(lib) SubElement(option, 'listOptionValue', { diff --git a/tools/file_check.py b/tools/file_check.py index 10d9060a37..3e7ac6fc1c 100644 --- a/tools/file_check.py +++ b/tools/file_check.py @@ -12,6 +12,7 @@ import os import re import sys import click +import yaml import chardet import logging import datetime @@ -25,12 +26,57 @@ def init_logger(): datefmt=date_format, ) + class CheckOut: def __init__(self, rtt_repo, rtt_branch): self.root = os.getcwd() self.rtt_repo = rtt_repo self.rtt_branch = rtt_branch + def __exclude_file(self, file_path): + dir_number = file_path.split('/') + ignore_path = file_path + + # gets the file path depth. + for i in dir_number: + # current directory. + dir_name = os.path.dirname(ignore_path) + ignore_path = dir_name + # judge the ignore file exists in the current directory. + ignore_file_path = os.path.join(dir_name, ".ignore_format.yml") + if not os.path.exists(ignore_file_path): + continue + try: + with open(ignore_file_path) as f: + ignore_config = yaml.safe_load(f.read()) + file_ignore = ignore_config.get("file_path", []) + dir_ignore = ignore_config.get("dir_path", []) + except Exception as e: + logging.error(e) + continue + + try: + # judge file_path in the ignore file. + for file in file_ignore: + if file is not None: + file_real_path = os.path.join(dir_name, file) + if file_real_path == file_path: + logging.info("ignore file path: {}".format(file_real_path)) + return 0 + + file_dir_path = os.path.dirname(file_path) + for _dir in dir_ignore: + if _dir is not None: + dir_real_path = os.path.join(dir_name, _dir) + if dir_real_path == file_dir_path: + logging.info("ignore dir path: {}".format(dir_real_path)) + return 0 + except Exception as e: + logging.error(e) + continue + + return 1 + def get_new_file(self): file_list = list() try: @@ -60,7 +106,9 @@ class CheckOut: else: continue - file_list.append(file_path) + result = self.__exclude_file(file_path) + if result != 0: + file_list.append(file_path) return file_list @@ -69,20 +117,20 @@ class FormatCheck: def __init__(self, file_list): self.file_list = file_list - def __check_file(self, file_lines): + def __check_file(self, file_lines, file_path): line_num = 1 - check_result = False + check_result = True for line in file_lines: # check line start line_start = line.replace(' ', '') # find tab if line_start.startswith('\t'): - logging.error("line[{}]: please use space replace tab at the start of this line.".format(line_num)) + logging.error("{} line[{}]: please use space replace tab at the start of this line.".format(file_path, line_num)) check_result = False # check line end lin_end = line.split('\n')[0] if lin_end.endswith(' ') or lin_end.endswith('\t'): - logging.error("line[{}]: please delete extra space at the end of this line.".format(line_num)) + logging.error("{} line[{}]: please delete extra space at the end of this line.".format(file_path, line_num)) check_result = False line_num += 1 @@ -92,17 +140,15 @@ class FormatCheck: logging.info("Start to check files format.") if len(self.file_list) == 0: logging.warning("There are no files to check license.") - return 0 + return True encoding_check_result = True format_check_result = True for file_path in self.file_list: - file_lines = '' code = '' if file_path.endswith(".c") or file_path.endswith(".h"): try: - with open(file_path, 'r') as f: + with open(file_path, 'rb') as f: file = f.read() - file_lines = f.readlines() # get file encoding code = chardet.detect(file)['encoding'] except Exception as e: @@ -110,13 +156,15 @@ class FormatCheck: else: continue - if code != 'utf-8': + if code != 'utf-8' and code != 'ascii': logging.error("[{0}]: encoding not utf-8, please format it.".format(file_path)) encoding_check_result = False else: logging.info('[{0}]: encoding check success.'.format(file_path)) - format_check_result = self.__check_file(file_lines) + with open(file_path, 'r', encoding = "utf-8") as f: + file_lines = f.readlines() + format_check_result = self.__check_file(file_lines, file_path) if not encoding_check_result or not format_check_result: logging.error("files format check fail.") @@ -155,8 +203,8 @@ class LicenseCheck: true_year = '2006-{}'.format(current_year) if license_year != true_year: logging.warning("[{0}]: license year: {} is not true: {}, please update.".format(file_path, - license_year, - true_year)) + license_year, + true_year)) else: logging.info("[{0}]: license check success.".format(file_path)) diff --git a/tools/keil.py b/tools/keil.py index ce6f690085..b3643fbe74 100644 --- a/tools/keil.py +++ b/tools/keil.py @@ -122,12 +122,18 @@ def MDK4AddLibToGroup(ProjectFiles, group, name, filename, project_path): if ProjectFiles.count(obj_name): name = basename + '_' + name ProjectFiles.append(obj_name) - file_name.text = name.decode(fs_encoding) + try: + file_name.text = name.decode(fs_encoding) + except: + file_name.text = name file_type = SubElement(file, 'FileType') file_type.text = '%d' % _get_filetype(name) file_path = SubElement(file, 'FilePath') - file_path.text = path.decode(fs_encoding) + try: + file_path.text = path.decode(fs_encoding) + except: + file_path.text = path return group diff --git a/tools/mkromfs.py b/tools/mkromfs.py index 120053be40..9f4f24d0d6 100644 --- a/tools/mkromfs.py +++ b/tools/mkromfs.py @@ -5,7 +5,7 @@ import os import struct from collections import namedtuple -import StringIO +import io import argparse parser = argparse.ArgumentParser() @@ -43,8 +43,10 @@ class File(object): if self.entry_size == 0: return '' - - return head + ','.join(('0x%02x' % ord(i) for i in self._data)) + tail + if len(self._data) > 0 and type(self._data[0]) == int: + return head + ','.join(('0x%02x' % i for i in self._data)) + tail + else: + return head + ','.join(('0x%02x' % ord(i) for i in self._data)) + tail @property def entry_size(self): @@ -104,7 +106,8 @@ class Folder(object): return 1 else: return -1 - self._children.sort(cmp=_sort) + from functools import cmp_to_key + self._children.sort(key=cmp_to_key(_sort)) # sort recursively for c in self._children: @@ -255,7 +258,7 @@ if __name__ == '__main__': if args.binary: data = get_bin_data(tree, int(args.addr, 16)) else: - data = get_c_data(tree) + data = get_c_data(tree).encode() output = args.output if not output: diff --git a/tools/ses.py b/tools/ses.py index dcd9d34442..cc513f0baa 100644 --- a/tools/ses.py +++ b/tools/ses.py @@ -59,14 +59,14 @@ def SESProject(env) : group_tree = SDKAddGroup(project_node, group['name'], group['src'], project_path) # get each group's cc flags - if group.has_key('CCFLAGS') and group['CCFLAGS']: + if 'CCFLAGS' in group and group['CCFLAGS']: if CCFLAGS: CCFLAGS += ' ' + group['CCFLAGS'] else: CCFLAGS += group['CCFLAGS'] # get each group's link flags - if group.has_key('LINKFLAGS') and group['LINKFLAGS']: + if 'LINKFLAGS' in group and group['LINKFLAGS']: if LINKFLAGS: LINKFLAGS += ' ' + group['LINKFLAGS'] else: diff --git a/tools/ua.py b/tools/ua.py index 0505f3596c..08b0ef8fad 100644 --- a/tools/ua.py +++ b/tools/ua.py @@ -45,7 +45,7 @@ def PrepareUA(project, RTT_ROOT, BSP_ROOT): # ua.write('import sys\n') ua.write('\n') - print RTT_ROOT + print(RTT_ROOT) CPPPATH = [] CPPDEFINES = [] diff --git a/tools/vs.py b/tools/vs.py index f51862b9d9..8025828b64 100644 --- a/tools/vs.py +++ b/tools/vs.py @@ -45,9 +45,12 @@ def VS_AddGroup(ProjectFiles, parent, name, files, libs, project_path): path = _make_path_relative(project_path, path) path = os.path.join(path, name) - + try: + path = path.decode(fs_encoding) + except: + path = path File = SubElement(Filter, 'File') - File.set('RelativePath', path.decode(fs_encoding)) + File.set('RelativePath', path) for lib in libs: name = os.path.basename(lib) @@ -57,7 +60,11 @@ def VS_AddGroup(ProjectFiles, parent, name, files, libs, project_path): path = os.path.join(path, name) File = SubElement(Filter, 'File') - File.set('RelativePath', path.decode(fs_encoding)) + try: + path = path.decode(fs_encoding) + except: + path = path + File.set('RelativePath', path) def VS_AddHeadFilesGroup(program, elem, project_path): utils.source_ext = [] @@ -70,7 +77,11 @@ def VS_AddHeadFilesGroup(program, elem, project_path): for f in utils.source_list: path = _make_path_relative(project_path, f) File = SubElement(elem, 'File') - File.set('RelativePath', path.decode(fs_encoding)) + try: + path = path.decode(fs_encoding) + except: + path = path + File.set('RelativePath', path) def VSProject(target, script, program): project_path = os.path.dirname(os.path.abspath(target)) @@ -158,12 +169,17 @@ def VSProject(target, script, program): for path in lib_path: inc = _make_path_relative(project_path, os.path.normpath(path)) paths.add(inc) #.replace('\\', '/') - + paths = [i for i in paths] paths.sort() lib_paths = ';'.join(paths) elem.set('AdditionalLibraryDirectories', lib_paths) xml_indent(root) - out.write(etree.tostring(root, encoding='utf-8')) + text = etree.tostring(root, encoding='utf-8') + try: + text = text.decode(encoding="utf-8") + except: + text = text + out.write(text) out.close() diff --git a/tools/vs2012.py b/tools/vs2012.py index 0c6b9d83d0..c9b0c76dc7 100644 --- a/tools/vs2012.py +++ b/tools/vs2012.py @@ -44,7 +44,12 @@ fs_encoding = sys.getfilesystemencoding() filter_project = etree.Element('Project', attrib={'ToolsVersion':'4.0'}) def get_uuid(): id = uuid.uuid1() # UUID('3e5526c0-2841-11e3-a376-20cf3048bcb3') - idstr = id.get_urn()[9:] #'urn:uuid:3e5526c0-2841-11e3-a376-20cf3048bcb3'[9:] + if sys.version > '3': + idstr = id.urn[9:] #'urn:uuid:3e5526c0-2841-11e3-a376-20cf3048bcb3'[9:] + else: + # python3 is no decode function + idstr = id.get_urn()[9:] #'urn:uuid:3e5526c0-2841-11e3-a376-20cf3048bcb3'[9:] + return '{'+idstr+'}' def VS2012_AddGroup(parent, group_name, files, project_path): @@ -57,7 +62,12 @@ def VS2012_AddGroup(parent, group_name, files, project_path): path = os.path.join(path, name) ClCompile = SubElement(parent, 'ClCompile') - ClCompile.set('Include', path.decode(fs_encoding)) + + if sys.version > '3': + ClCompile.set('Include', path) + else: + # python3 is no decode function + ClCompile.set('Include', path.decode(fs_encoding)) Filter = SubElement(ClCompile, 'Filter') Filter.text='Source Files\\'+group_name @@ -119,7 +129,13 @@ def VS_add_ItemGroup(parent, file_type, files, project_path): path = os.path.join(path, name) File = SubElement(ItemGroup, item_tag) - File.set('Include', path.decode(fs_encoding)) + + if sys.version > '3': + File.set('Include', path) + else: + # python3 is no decode function + File.set('Include', path.decode(fs_encoding)) + if file_type == 'C' : ObjName = SubElement(File, 'ObjectFileName') ObjName.text = ''.join('$(IntDir)'+objpath+'\\') @@ -137,11 +153,22 @@ def VS_add_HeadFiles(program, elem, project_path): for f in utils.source_list: path = _make_path_relative(project_path, f) File = SubElement(ItemGroup, 'ClInclude') - File.set('Include', path.decode(fs_encoding)) + + if sys.version > '3': + File.set('Include', path) + else: + # python3 is no decode function + File.set('Include', path.decode(fs_encoding)) # add project.vcxproj.filter ClInclude = SubElement(filter_h_ItemGroup, 'ClInclude') - ClInclude.set('Include', path.decode(fs_encoding)) + + if sys.version > '3': + ClInclude.set('Include', path) + else: + # python3 is no decode function + ClInclude.set('Include', path.decode(fs_encoding)) + Filter = SubElement(ClInclude, 'Filter') Filter.text='Header Files' @@ -151,12 +178,12 @@ def VS2012Project(target, script, program): tree = etree.parse('template_vs2012.vcxproj') root = tree.getroot() elem = root - - out = file(target, 'wb') + + out = open(target, 'w') out.write('\r\n') - + ProjectFiles = [] - + # add "*.c or *.h" files VS2012_CreateFilter(script, project_path) @@ -187,7 +214,16 @@ def VS2012Project(target, script, program): # write cppdefinitons flags if 'CPPDEFINES' in building.Env: for elem in tree.iter(tag='PreprocessorDefinitions'): - definitions = ';'.join(building.Env['CPPDEFINES']) + ';%(PreprocessorDefinitions)' + CPPDEFINES = building.Env['CPPDEFINES'] + definitions = [] + if type(CPPDEFINES[0]) == type(()): + for item in CPPDEFINES: + definitions += [i for i in item] + definitions = ';'.join(definitions) + else: + definitions = ';'.join(building.Env['CPPDEFINES']) + + definitions = definitions + ';%(PreprocessorDefinitions)' elem.text = definitions break # write link flags @@ -216,15 +252,27 @@ def VS2012Project(target, script, program): break xml_indent(root) - vcxproj_string = etree.tostring(root, encoding='utf-8') + + if sys.version > '3': + vcxproj_string = etree.tostring(root, encoding='unicode') + else: + # python3 is no decode function + vcxproj_string = etree.tostring(root, encoding='utf-8') + root_node=r'' out.write(r'') out.write(vcxproj_string[len(root_node):]) out.close() xml_indent(filter_project) - filter_string = etree.tostring(filter_project, encoding='utf-8') - out = file('project.vcxproj.filters', 'wb') + + if sys.version > '3': + filter_string = etree.tostring(filter_project, encoding='unicode') + else: + # python3 is no decode function + filter_string = etree.tostring(filter_project, encoding='utf-8') + + out = open('project.vcxproj.filters', 'w') out.write('\r\n') root_node=r'' out.write(r'') diff --git a/tools/win32spawn.py b/tools/win32spawn.py index 9b878bf69f..1c2cfcf83b 100644 --- a/tools/win32spawn.py +++ b/tools/win32spawn.py @@ -24,7 +24,13 @@ import os import threading -import Queue +import sys + +_PY2 = sys.version_info[0] < 3 +if _PY2: + import Queue +else: + import queue as Queue # Windows import import win32file