From 3a602808c9fe748b3a721bd83dc0abf7829b16a6 Mon Sep 17 00:00:00 2001 From: jacycle <515892376@qq.com> Date: Sat, 21 Aug 2021 14:10:33 +0800 Subject: [PATCH 01/29] =?UTF-8?q?1.=E5=A2=9E=E5=8A=A0hc32l136=20bsp?= =?UTF-8?q?=E5=B7=A5=E7=A8=8B=E6=96=87=E4=BB=B6?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/hc32l136/.config | 574 + bsp/hc32l136/Kconfig | 23 + .../Device/HDSC/HC32L136/Include/base_types.h | 155 + .../HDSC/HC32L136/Include/board_stkhc32l13x.h | 120 + .../Device/HDSC/HC32L136/Include/ddl_device.h | 76 + .../Device/HDSC/HC32L136/Include/hc32l136.h | 9620 +++++++++++++++++ .../HDSC/HC32L136/Include/system_hc32l136.h | 107 + .../HDSC/HC32L136/Include/system_hc32l13x.h | 111 + .../HC32L136/Source/ARM/startup_hc32l136.s | 294 + .../HC32L136/Source/IAR/startup_hc32l136.s | 353 + .../HC32L136/Source/interrupts_hc32l136.c | 477 + .../HDSC/HC32L136/Source/system_hc32l136.h | 107 + .../HDSC/HC32L136/Source/system_hc32l13x.c | 91 + .../Libraries/CMSIS/Include/cmsis_armcc.h | 894 ++ .../Libraries/CMSIS/Include/cmsis_armclang.h | 1444 +++ .../CMSIS/Include/cmsis_armclang_ltm.h | 1891 ++++ .../Libraries/CMSIS/Include/cmsis_compiler.h | 283 + .../Libraries/CMSIS/Include/cmsis_gcc.h | 2168 ++++ .../Libraries/CMSIS/Include/cmsis_iccarm.h | 964 ++ .../Libraries/CMSIS/Include/cmsis_version.h | 39 + .../Libraries/CMSIS/Include/core_armv81mml.h | 2968 +++++ .../Libraries/CMSIS/Include/core_armv8mbl.h | 1921 ++++ .../Libraries/CMSIS/Include/core_armv8mml.h | 2835 +++++ .../Libraries/CMSIS/Include/core_cm0.h | 952 ++ .../Libraries/CMSIS/Include/core_cm0plus.h | 1085 ++ .../Libraries/CMSIS/Include/core_cm1.h | 979 ++ .../Libraries/CMSIS/Include/core_cm23.h | 1996 ++++ .../Libraries/CMSIS/Include/core_cm3.h | 1937 ++++ .../Libraries/CMSIS/Include/core_cm33.h | 2910 +++++ .../Libraries/CMSIS/Include/core_cm35p.h | 2910 +++++ .../Libraries/CMSIS/Include/core_cm4.h | 2124 ++++ .../Libraries/CMSIS/Include/core_cm7.h | 2725 +++++ .../Libraries/CMSIS/Include/core_sc000.h | 1025 ++ .../Libraries/CMSIS/Include/core_sc300.h | 1912 ++++ .../Libraries/CMSIS/Include/mpu_armv7.h | 272 + .../Libraries/CMSIS/Include/mpu_armv8.h | 346 + .../Libraries/CMSIS/Include/tz_context.h | 70 + .../HC32L136_StdPeriph_Driver/inc/adc.h | 486 + .../HC32L136_StdPeriph_Driver/inc/adt.h | 819 ++ .../HC32L136_StdPeriph_Driver/inc/aes.h | 108 + .../HC32L136_StdPeriph_Driver/inc/bgr.h | 109 + .../HC32L136_StdPeriph_Driver/inc/bt.h | 770 ++ .../HC32L136_StdPeriph_Driver/inc/crc.h | 120 + .../HC32L136_StdPeriph_Driver/inc/ddl.h | 208 + .../HC32L136_StdPeriph_Driver/inc/debug.h | 129 + .../HC32L136_StdPeriph_Driver/inc/dmac.h | 327 + .../HC32L136_StdPeriph_Driver/inc/flash.h | 196 + .../HC32L136_StdPeriph_Driver/inc/gpio.h | 506 + .../HC32L136_StdPeriph_Driver/inc/hdiv.h | 119 + .../HC32L136_StdPeriph_Driver/inc/i2c.h | 167 + .../inc/interrupts_hc32l136.h | 103 + .../HC32L136_StdPeriph_Driver/inc/lcd.h | 270 + .../HC32L136_StdPeriph_Driver/inc/lpm.h | 147 + .../HC32L136_StdPeriph_Driver/inc/lpt.h | 211 + .../HC32L136_StdPeriph_Driver/inc/lpuart.h | 325 + .../HC32L136_StdPeriph_Driver/inc/lvd.h | 208 + .../HC32L136_StdPeriph_Driver/inc/opa.h | 205 + .../HC32L136_StdPeriph_Driver/inc/pca.h | 301 + .../HC32L136_StdPeriph_Driver/inc/pcnt.h | 214 + .../HC32L136_StdPeriph_Driver/inc/reset.h | 166 + .../HC32L136_StdPeriph_Driver/inc/rng.h | 108 + .../HC32L136_StdPeriph_Driver/inc/rtc.h | 298 + .../HC32L136_StdPeriph_Driver/inc/spi.h | 212 + .../HC32L136_StdPeriph_Driver/inc/sysctrl.h | 457 + .../HC32L136_StdPeriph_Driver/inc/timer0.h | 788 ++ .../HC32L136_StdPeriph_Driver/inc/timer3.h | 788 ++ .../HC32L136_StdPeriph_Driver/inc/trim.h | 186 + .../HC32L136_StdPeriph_Driver/inc/uart.h | 297 + .../HC32L136_StdPeriph_Driver/inc/vc.h | 311 + .../HC32L136_StdPeriph_Driver/inc/wdt.h | 127 + .../HC32L136_StdPeriph_Driver/src/adc.c | 1022 ++ .../HC32L136_StdPeriph_Driver/src/adt.c | 1952 ++++ .../HC32L136_StdPeriph_Driver/src/aes.c | 176 + .../HC32L136_StdPeriph_Driver/src/bgr.c | 155 + .../HC32L136_StdPeriph_Driver/src/bt.c | 1608 +++ .../HC32L136_StdPeriph_Driver/src/crc.c | 438 + .../HC32L136_StdPeriph_Driver/src/ddl.c | 345 + .../HC32L136_StdPeriph_Driver/src/debug.c | 119 + .../HC32L136_StdPeriph_Driver/src/dmac.c | 1538 +++ .../HC32L136_StdPeriph_Driver/src/flash.c | 688 ++ .../HC32L136_StdPeriph_Driver/src/gpio.c | 613 ++ .../HC32L136_StdPeriph_Driver/src/hdiv.c | 176 + .../HC32L136_StdPeriph_Driver/src/i2c.c | 666 ++ .../src/interrupts_hc32l136.c | 477 + .../HC32L136_StdPeriph_Driver/src/lcd.c | 579 + .../HC32L136_StdPeriph_Driver/src/lpm.c | 134 + .../HC32L136_StdPeriph_Driver/src/lpt.c | 289 + .../HC32L136_StdPeriph_Driver/src/lpuart.c | 966 ++ .../HC32L136_StdPeriph_Driver/src/lvd.c | 327 + .../HC32L136_StdPeriph_Driver/src/opa.c | 438 + .../HC32L136_StdPeriph_Driver/src/pca.c | 834 ++ .../HC32L136_StdPeriph_Driver/src/pcnt.c | 417 + .../HC32L136_StdPeriph_Driver/src/reset.c | 163 + .../HC32L136_StdPeriph_Driver/src/rng.c | 191 + .../HC32L136_StdPeriph_Driver/src/rtc.c | 875 ++ .../HC32L136_StdPeriph_Driver/src/spi.c | 526 + .../HC32L136_StdPeriph_Driver/src/sysctrl.c | 776 ++ .../HC32L136_StdPeriph_Driver/src/timer0.c | 1390 +++ .../HC32L136_StdPeriph_Driver/src/timer3.c | 1399 +++ .../HC32L136_StdPeriph_Driver/src/trim.c | 348 + .../HC32L136_StdPeriph_Driver/src/uart.c | 910 ++ .../HC32L136_StdPeriph_Driver/src/vc.c | 674 ++ .../HC32L136_StdPeriph_Driver/src/wdt.c | 184 + bsp/hc32l136/Libraries/LICENSE | 29 + bsp/hc32l136/Libraries/SConscript | 48 + bsp/hc32l136/README.md | 100 + bsp/hc32l136/SConscript | 15 + bsp/hc32l136/SConstruct | 45 + bsp/hc32l136/applications/SConscript | 12 + bsp/hc32l136/applications/main.c | 90 + bsp/hc32l136/board/Kconfig | 57 + bsp/hc32l136/board/SConscript | 14 + bsp/hc32l136/board/board.c | 101 + bsp/hc32l136/board/board.h | 49 + bsp/hc32l136/board/linker_scripts/link.icf | 28 + bsp/hc32l136/board/linker_scripts/link.lds | 203 + bsp/hc32l136/board/linker_scripts/link.sct | 15 + bsp/hc32l136/drivers/SConscript | 22 + bsp/hc32l136/drivers/drv_dma.h | 39 + bsp/hc32l136/drivers/drv_gpio.c | 449 + bsp/hc32l136/drivers/drv_gpio.h | 151 + bsp/hc32l136/drivers/drv_soft_i2c.c | 207 + bsp/hc32l136/drivers/drv_soft_i2c.h | 128 + bsp/hc32l136/drivers/drv_usart.c | 627 ++ bsp/hc32l136/drivers/drv_usart.h | 74 + bsp/hc32l136/figures/board.png | Bin 0 -> 322618 bytes bsp/hc32l136/project.ewp | 2157 ++++ bsp/hc32l136/project.eww | 10 + bsp/hc32l136/project.uvoptx | 924 ++ bsp/hc32l136/project.uvprojx | 713 ++ bsp/hc32l136/rtconfig.h | 180 + bsp/hc32l136/rtconfig.py | 132 + bsp/hc32l136/template.ewp | 1933 ++++ bsp/hc32l136/template.eww | 10 + bsp/hc32l136/template.uvoptx | 184 + bsp/hc32l136/template.uvprojx | 391 + 136 files changed, 89074 insertions(+) create mode 100644 bsp/hc32l136/.config create mode 100644 bsp/hc32l136/Kconfig create mode 100644 bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Include/base_types.h create mode 100644 bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Include/board_stkhc32l13x.h create mode 100644 bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Include/ddl_device.h create mode 100644 bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Include/hc32l136.h create mode 100644 bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Include/system_hc32l136.h create mode 100644 bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Include/system_hc32l13x.h create mode 100644 bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Source/ARM/startup_hc32l136.s create mode 100644 bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Source/IAR/startup_hc32l136.s create mode 100644 bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Source/interrupts_hc32l136.c create mode 100644 bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Source/system_hc32l136.h create mode 100644 bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Source/system_hc32l13x.c create mode 100644 bsp/hc32l136/Libraries/CMSIS/Include/cmsis_armcc.h create mode 100644 bsp/hc32l136/Libraries/CMSIS/Include/cmsis_armclang.h create mode 100644 bsp/hc32l136/Libraries/CMSIS/Include/cmsis_armclang_ltm.h create mode 100644 bsp/hc32l136/Libraries/CMSIS/Include/cmsis_compiler.h create mode 100644 bsp/hc32l136/Libraries/CMSIS/Include/cmsis_gcc.h create mode 100644 bsp/hc32l136/Libraries/CMSIS/Include/cmsis_iccarm.h create mode 100644 bsp/hc32l136/Libraries/CMSIS/Include/cmsis_version.h create mode 100644 bsp/hc32l136/Libraries/CMSIS/Include/core_armv81mml.h create mode 100644 bsp/hc32l136/Libraries/CMSIS/Include/core_armv8mbl.h create mode 100644 bsp/hc32l136/Libraries/CMSIS/Include/core_armv8mml.h create mode 100644 bsp/hc32l136/Libraries/CMSIS/Include/core_cm0.h create mode 100644 bsp/hc32l136/Libraries/CMSIS/Include/core_cm0plus.h create mode 100644 bsp/hc32l136/Libraries/CMSIS/Include/core_cm1.h create mode 100644 bsp/hc32l136/Libraries/CMSIS/Include/core_cm23.h create mode 100644 bsp/hc32l136/Libraries/CMSIS/Include/core_cm3.h create mode 100644 bsp/hc32l136/Libraries/CMSIS/Include/core_cm33.h create mode 100644 bsp/hc32l136/Libraries/CMSIS/Include/core_cm35p.h create mode 100644 bsp/hc32l136/Libraries/CMSIS/Include/core_cm4.h create mode 100644 bsp/hc32l136/Libraries/CMSIS/Include/core_cm7.h create mode 100644 bsp/hc32l136/Libraries/CMSIS/Include/core_sc000.h create mode 100644 bsp/hc32l136/Libraries/CMSIS/Include/core_sc300.h create mode 100644 bsp/hc32l136/Libraries/CMSIS/Include/mpu_armv7.h create mode 100644 bsp/hc32l136/Libraries/CMSIS/Include/mpu_armv8.h create mode 100644 bsp/hc32l136/Libraries/CMSIS/Include/tz_context.h create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/adc.h create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/adt.h create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/aes.h create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/bgr.h create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/bt.h create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/crc.h create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/ddl.h create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/debug.h create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/dmac.h create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/flash.h create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/gpio.h create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/hdiv.h create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/i2c.h create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/interrupts_hc32l136.h create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/lcd.h create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/lpm.h create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/lpt.h create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/lpuart.h create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/lvd.h create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/opa.h create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/pca.h create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/pcnt.h create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/reset.h create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/rng.h create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/rtc.h create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/spi.h create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/sysctrl.h create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/timer0.h create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/timer3.h create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/trim.h create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/uart.h create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/vc.h create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/wdt.h create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/adc.c create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/adt.c create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/aes.c create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/bgr.c create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/bt.c create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/crc.c create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/ddl.c create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/debug.c create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/dmac.c create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/flash.c create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/gpio.c create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/hdiv.c create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/i2c.c create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/interrupts_hc32l136.c create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/lcd.c create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/lpm.c create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/lpt.c create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/lpuart.c create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/lvd.c create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/opa.c create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/pca.c create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/pcnt.c create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/reset.c create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/rng.c create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/rtc.c create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/spi.c create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/sysctrl.c create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/timer0.c create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/timer3.c create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/trim.c create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/uart.c create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/vc.c create mode 100644 bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/wdt.c create mode 100644 bsp/hc32l136/Libraries/LICENSE create mode 100644 bsp/hc32l136/Libraries/SConscript create mode 100644 bsp/hc32l136/README.md create mode 100644 bsp/hc32l136/SConscript create mode 100644 bsp/hc32l136/SConstruct create mode 100644 bsp/hc32l136/applications/SConscript create mode 100644 bsp/hc32l136/applications/main.c create mode 100644 bsp/hc32l136/board/Kconfig create mode 100644 bsp/hc32l136/board/SConscript create mode 100644 bsp/hc32l136/board/board.c create mode 100644 bsp/hc32l136/board/board.h create mode 100644 bsp/hc32l136/board/linker_scripts/link.icf create mode 100644 bsp/hc32l136/board/linker_scripts/link.lds create mode 100644 bsp/hc32l136/board/linker_scripts/link.sct create mode 100644 bsp/hc32l136/drivers/SConscript create mode 100644 bsp/hc32l136/drivers/drv_dma.h create mode 100644 bsp/hc32l136/drivers/drv_gpio.c create mode 100644 bsp/hc32l136/drivers/drv_gpio.h create mode 100644 bsp/hc32l136/drivers/drv_soft_i2c.c create mode 100644 bsp/hc32l136/drivers/drv_soft_i2c.h create mode 100644 bsp/hc32l136/drivers/drv_usart.c create mode 100644 bsp/hc32l136/drivers/drv_usart.h create mode 100644 bsp/hc32l136/figures/board.png create mode 100644 bsp/hc32l136/project.ewp create mode 100644 bsp/hc32l136/project.eww create mode 100644 bsp/hc32l136/project.uvoptx create mode 100644 bsp/hc32l136/project.uvprojx create mode 100644 bsp/hc32l136/rtconfig.h create mode 100644 bsp/hc32l136/rtconfig.py create mode 100644 bsp/hc32l136/template.ewp create mode 100644 bsp/hc32l136/template.eww create mode 100644 bsp/hc32l136/template.uvoptx create mode 100644 bsp/hc32l136/template.uvprojx diff --git a/bsp/hc32l136/.config b/bsp/hc32l136/.config new file mode 100644 index 0000000000..732d1347cc --- /dev/null +++ b/bsp/hc32l136/.config @@ -0,0 +1,574 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Project Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_COLOR is not set +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +# CONFIG_RT_PRINTF_LONGLONG is not set +CONFIG_RT_VER_NUM=0x40003 +CONFIG_ARCH_ARM=y +# CONFIG_RT_USING_CPU_FFS is not set +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M0=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=512 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=512 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +# CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +# CONFIG_RT_USING_DFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +# CONFIG_RT_USING_LIBC is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_LIBC_USING_TIME is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_LWP is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set + +# +# system packages +# + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set + +# +# Hardware Drivers Config +# +CONFIG_MCU_HC32L136=y + +# +# Onboard Peripheral Drivers +# + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +# CONFIG_BSP_USING_UART0 is not set +CONFIG_BSP_USING_UART1=y +# CONFIG_BSP_USING_I2C1 is not set + +# +# Board extended module Drivers +# diff --git a/bsp/hc32l136/Kconfig b/bsp/hc32l136/Kconfig new file mode 100644 index 0000000000..f4ed99b3fa --- /dev/null +++ b/bsp/hc32l136/Kconfig @@ -0,0 +1,23 @@ +mainmenu "RT-Thread Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "board/Kconfig" + + + diff --git a/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Include/base_types.h b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Include/base_types.h new file mode 100644 index 0000000000..d3feeaff73 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Include/base_types.h @@ -0,0 +1,155 @@ +/****************************************************************************** +* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file base_types.h + ** + ** base type common define. + ** @link SampleGroup Some description @endlink + ** + ** - 2018-03-09 1.0 Lux First version. + ** + ******************************************************************************/ + +#ifndef __BASE_TYPES_H__ +#define __BASE_TYPES_H__ + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include +#include +#include +#include +#include + + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ +#ifndef TRUE + /** Value is true (boolean_t type) */ + #define TRUE ((boolean_t) 1u) +#endif + +#ifndef FALSE + /** Value is false (boolean_t type) */ + #define FALSE ((boolean_t) 0u) +#endif + +#if defined (__ICCARM__) +#define __WEAKDEF __WEAK __ATTRIBUTES +#elif defined (__CC_ARM) +#define __WEAKDEF __weak +#else +#error "unsupported compiler!!" +#endif + +/** Returns the minimum value out of two values */ +#define MINIMUM( X, Y ) ((X) < (Y) ? (X) : (Y)) + +/** Returns the maximum value out of two values */ +#define MAXIMUM( X, Y ) ((X) > (Y) ? (X) : (Y)) + +/** Returns the dimension of an array */ +#define ARRAY_SZ( X ) (sizeof(X) / sizeof((X)[0])) + +#ifdef __DEBUG_ASSERT + #define ASSERT(x) do{ assert((x)> 0u) ; }while(0); +#else + #define ASSERT(x) {} +#endif +/****************************************************************************** + * Global type definitions + ******************************************************************************/ + +/** logical datatype (only values are TRUE and FALSE) */ +typedef uint8_t boolean_t; + +/** single precision floating point number (4 byte) */ +typedef float float32_t; + +/** double precision floating point number (8 byte) */ +typedef double float64_t; + +/** ASCII character for string generation (8 bit) */ +typedef char char_t; + +/** function pointer type to void/void function */ +typedef void (*func_ptr_t)(void); + +/** function pointer type to void/uint8_t function */ +typedef void (*func_ptr_arg1_t)(uint8_t u8Param); + +/** generic error codes */ +typedef enum en_result +{ + Ok = 0u, ///< No error + Error = 1u, ///< Non-specific error code + ErrorAddressAlignment = 2u, ///< Address alignment does not match + ErrorAccessRights = 3u, ///< Wrong mode (e.g. user/system) mode is set + ErrorInvalidParameter = 4u, ///< Provided parameter is not valid + ErrorOperationInProgress = 5u, ///< A conflicting or requested operation is still in progress + ErrorInvalidMode = 6u, ///< Operation not allowed in current mode + ErrorUninitialized = 7u, ///< Module (or part of it) was not initialized properly + ErrorBufferFull = 8u, ///< Circular buffer can not be written because the buffer is full + ErrorTimeout = 9u, ///< Time Out error occurred (e.g. I2C arbitration lost, Flash time-out, etc.) + ErrorNotReady = 10u, ///< A requested final state is not reached + OperationInProgress = 11u ///< Indicator for operation in progress +} en_result_t; + + +/*****************************************************************************/ +/* Global variable declarations ('extern', definition in C source) */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/*****************************************************************************/ + +#endif /* __BASE_TYPES_H__ */ + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ + + + diff --git a/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Include/board_stkhc32l13x.h b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Include/board_stkhc32l13x.h new file mode 100644 index 0000000000..e5c194c7c2 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Include/board_stkhc32l13x.h @@ -0,0 +1,120 @@ +/****************************************************************************** +* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file stkhc32l13x.h + ** + ** stk board common define. + ** @link SampleGroup Some description @endlink + ** + ** - 2018-03-09 1.0 Lux First version. + ** + ******************************************************************************/ +#ifndef __BOARD_STKHC32L13X_H__ +#define __BOARD_STKHC32L13X_H__ + +///< STK GPIO DEFINE +///< USER KEY +#define STK_USER_PORT GpioPortD +#define STK_USER_PIN GpioPin4 + +///< LED +#define STK_LED_PORT GpioPortD +#define STK_LED_PIN GpioPin5 + +///< XTH +#define SYSTEM_XTH (32*1000*1000u) ///< 32MHz + +#define STK_XTHI_PORT GpioPortD +#define STK_XTHI_PIN GpioPin0 +#define STK_XTHO_PORT GpioPortD +#define STK_XTHO_PIN GpioPin1 + +///< XTL +#define SYSTEM_XTL (32768u) ///< 32768Hz +#define STK_XTLI_PORT GpioPortC +#define STK_XTLI_PIN GpioPin14 +#define STK_XTLO_PORT GpioPortC +#define STK_XTLO_PIN GpioPin15 + +///< LCD +#define STK_LCD_COM0_PORT GpioPortA +#define STK_LCD_COM0_PIN GpioPin9 +#define STK_LCD_COM1_PORT GpioPortA +#define STK_LCD_COM1_PIN GpioPin10 +#define STK_LCD_COM2_PORT GpioPortA +#define STK_LCD_COM2_PIN GpioPin11 +#define STK_LCD_COM3_PORT GpioPortA +#define STK_LCD_COM3_PIN GpioPin12 +#define STK_LCD_SEG0_PORT GpioPortA +#define STK_LCD_SEG0_PIN GpioPin8 +#define STK_LCD_SEG1_PORT GpioPortC +#define STK_LCD_SEG1_PIN GpioPin9 +#define STK_LCD_SEG2_PORT GpioPortC +#define STK_LCD_SEG2_PIN GpioPin8 +#define STK_LCD_SEG3_PORT GpioPortC +#define STK_LCD_SEG3_PIN GpioPin7 +#define STK_LCD_SEG4_PORT GpioPortC +#define STK_LCD_SEG4_PIN GpioPin6 +#define STK_LCD_SEG5_PORT GpioPortB +#define STK_LCD_SEG5_PIN GpioPin15 +#define STK_LCD_SEG6_PORT GpioPortB +#define STK_LCD_SEG6_PIN GpioPin14 +#define STK_LCD_SEG7_PORT GpioPortB +#define STK_LCD_SEG7_PIN GpioPin13 + +///< I2C EEPROM +#define EVB_I2C0_EEPROM_SCL_PORT GpioPortB +#define EVB_I2C0_EEPROM_SCL_PIN GpioPin6 +#define EVB_I2C0_EEPROM_SDA_PORT GpioPortB +#define EVB_I2C0_EEPROM_SDA_PIN GpioPin7 + +///< SPI0 +#define EVB_SPI0_FLASH_CS_PORT GpioPortE +#define EVB_SPI0_FLASH_CS_PIN GpioPin12 +#define EVB_SPI0_FLASH_SCK_PORT GpioPortE +#define EVB_SPI0_FLASH_SCK_PIN GpioPin13 +#define EVB_SPI0_FLASH_MISO_PORT GpioPortE +#define EVB_SPI0_FLASH_MISO_PIN GpioPin14 +#define EVB_SPI0_FLASH_MOSI_PORT GpioPortE +#define EVB_SPI0_FLASH_MOSI_PIN GpioPin15 + +#endif diff --git a/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Include/ddl_device.h b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Include/ddl_device.h new file mode 100644 index 0000000000..6ee91e5f2e --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Include/ddl_device.h @@ -0,0 +1,76 @@ +/******************************************************************************* +* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file ddl_device.h + ** + ** Device define + ** @link SampleGroup Some description @endlink + ** + ** - 2018-04-15 + ** + *****************************************************************************/ + +#ifndef __DDL_DEVICE_H__ +#define __DDL_DEVICE_H__ + +/** + ******************************************************************************* + ** \brief Global device series definition + ** + ** \note + ******************************************************************************/ +#define DDL_MCU_SERIES DDL_DEVICE_SERIES_HC32L13X + + +/** + ******************************************************************************* + ** \brief Global package definition + ** + ** \note This definition is used for device package settings + ******************************************************************************/ +#define DDL_MCU_PACKAGE DDL_DEVICE_PACKAGE_HC_K + +#endif /* __DDL_DEVICE_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Include/hc32l136.h b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Include/hc32l136.h new file mode 100644 index 0000000000..a162e9e5a2 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Include/hc32l136.h @@ -0,0 +1,9620 @@ +/******************************************************************************* +* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \\file HC32L136.h +** +** Auto generate. +** Headerfile for HC32L136 series MCU +** +** History: +** +** - 2018-09-14 0.1 Lux First version. +** +******************************************************************************/ + +#ifndef __HC32L136_H__ +#define __HC32L136_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/****************************************************************************** +* Configuration of the Cortex-M0P Processor and Core Peripherals +******************************************************************************/ +#define __MPU_PRESENT 0 /* No MPU */ +#define __NVIC_PRIO_BITS 2 /* M0P uses 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ + +/****************************************************************************** +* Interrupt Number Definition +******************************************************************************/ +typedef enum IRQn +{ + NMI_IRQn = -14, /* 2 Non Maskable */ + HardFault_IRQn = -13, /* 3 Hard Fault */ + SVC_IRQn = -5, /* 11 SV Call */ + PendSV_IRQn = -2, /* 14 Pend SV */ + SysTick_IRQn = -1, /* 15 System Tick */ + + PORTA_IRQn = 0 , + PORTB_IRQn = 1 , + PORTC_IRQn = 2 , + PORTD_IRQn = 3 , + DMAC_IRQn = 4 , + TIM3_IRQn = 5 , + UART0_IRQn = 6 , + UART1_IRQn = 7 , + LPUART0_IRQn = 8 , + LPUART1_IRQn = 9 , + SPI0_IRQn = 10, + SPI1_IRQn = 11, + I2C0_IRQn = 12, + I2C1_IRQn = 13, + TIM0_IRQn = 14, + TIM1_IRQn = 15, + TIM2_IRQn = 16, + LPTIM_IRQn = 17, + TIM4_IRQn = 18, + TIM5_IRQn = 19, + TIM6_IRQn = 20, + PCA_IRQn = 21, + WDT_IRQn = 22, + RTC_IRQn = 23, + ADC_IRQn = 24, + PCNT_IRQn = 25, + VC0_IRQn = 26, + VC1_IRQn = 27, + LVD_IRQn = 28, + LCD_IRQn = 29, + FLASH_RAM_IRQn = 30, + CLK_TRIM_IRQn = 31, + + +} IRQn_Type; + + +#include +#include + +#define SUCCESS (0) +#define ERROR (-1) + +#ifndef NULL +#define NULL (0) +#endif + + +/******************************************************************************/ +/* Device Specific Peripheral Registers structures */ +/******************************************************************************/ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +typedef struct +{ + __IO uint32_t EN : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CLKDIV : 2; + __IO uint32_t SGLMUX : 5; + __IO uint32_t REF : 2; + __IO uint32_t BUF : 1; + __IO uint32_t SAM : 2; + __IO uint32_t INREFEN : 1; + __IO uint32_t IE : 1; +} stc_adc_cr0_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 2; + __IO uint32_t ALIGN : 1; + __IO uint32_t THCH : 5; + __IO uint32_t DMASQR : 1; + __IO uint32_t DMAJQR : 1; + __IO uint32_t MODE : 1; + __IO uint32_t RACCEN : 1; + __IO uint32_t LTCMP : 1; + __IO uint32_t HTCMP : 1; + __IO uint32_t REGCMP : 1; + __IO uint32_t RACCCLR : 1; +} stc_adc_cr1_field_t; + +typedef struct +{ + __IO uint32_t CH0MUX : 5; + __IO uint32_t CH1MUX : 5; + __IO uint32_t CH2MUX : 5; + __IO uint32_t CH3MUX : 5; + __IO uint32_t CH4MUX : 5; + __IO uint32_t CH5MUX : 5; +} stc_adc_sqr0_field_t; + +typedef struct +{ + __IO uint32_t CH6MUX : 5; + __IO uint32_t CH7MUX : 5; + __IO uint32_t CH8MUX : 5; + __IO uint32_t CH9MUX : 5; + __IO uint32_t CH10MUX : 5; + __IO uint32_t CH11MUX : 5; +} stc_adc_sqr1_field_t; + +typedef struct +{ + __IO uint32_t CH12MUX : 5; + __IO uint32_t CH13MUX : 5; + __IO uint32_t CH14MUX : 5; + __IO uint32_t CH15MUX : 5; + __IO uint32_t CNT : 4; +} stc_adc_sqr2_field_t; + +typedef struct +{ + __IO uint32_t CH0MUX : 5; + __IO uint32_t CH1MUX : 5; + __IO uint32_t CH2MUX : 5; + __IO uint32_t CH3MUX : 5; + __IO uint32_t CNT : 2; +} stc_adc_jqr_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; +} stc_adc_sqrresult0_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; +} stc_adc_sqrresult1_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; +} stc_adc_sqrresult2_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; +} stc_adc_sqrresult3_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; +} stc_adc_sqrresult4_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; +} stc_adc_sqrresult5_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; +} stc_adc_sqrresult6_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; +} stc_adc_sqrresult7_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; +} stc_adc_sqrresult8_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; +} stc_adc_sqrresult9_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; +} stc_adc_sqrresult10_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; +} stc_adc_sqrresult11_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; +} stc_adc_sqrresult12_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; +} stc_adc_sqr_result13_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; +} stc_adc_sqrresult14_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; +} stc_adc_sqrresult15_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; +} stc_adc_jqrresult0_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; +} stc_adc_jqrresult1_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; +} stc_adc_jqrresult2_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; +} stc_adc_jqrresult3_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; +} stc_adc_result_field_t; + +typedef struct +{ + __IO uint32_t RESULTACC :20; +} stc_adc_resultacc_field_t; + +typedef struct +{ + __IO uint32_t HT :12; +} stc_adc_ht_field_t; + +typedef struct +{ + __IO uint32_t LT :12; +} stc_adc_lt_field_t; + +typedef struct +{ + __IO uint32_t SGLIF : 1; + __IO uint32_t LTIF : 1; + __IO uint32_t HTIF : 1; + __IO uint32_t REGIF : 1; + __IO uint32_t SQRIF : 1; + __IO uint32_t JQRIF : 1; +} stc_adc_ifr_field_t; + +typedef struct +{ + __IO uint32_t SGLIC : 1; + __IO uint32_t LTIC : 1; + __IO uint32_t HTIC : 1; + __IO uint32_t REGIC : 1; + __IO uint32_t SQRIC : 1; + __IO uint32_t JQRIC : 1; +} stc_adc_icr_field_t; + +typedef struct +{ + __IO uint32_t TIM0 : 1; + __IO uint32_t TIM1 : 1; + __IO uint32_t TIM2 : 1; + __IO uint32_t TIM3 : 1; + __IO uint32_t TIM4 : 1; + __IO uint32_t TIM5 : 1; + __IO uint32_t TIM6 : 1; + __IO uint32_t UART0 : 1; + __IO uint32_t UART1 : 1; + __IO uint32_t LPUART0 : 1; + __IO uint32_t LPUART1 : 1; + __IO uint32_t VC0 : 1; + __IO uint32_t VC1 : 1; + __IO uint32_t RTC : 1; + __IO uint32_t PCA : 1; + __IO uint32_t SPI0 : 1; + __IO uint32_t SPI1 : 1; + __IO uint32_t DMA : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PD07 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PA15 : 1; + __IO uint32_t PB15 : 1; + __IO uint32_t PC15 : 1; +} stc_adc_exttrigger0_field_t; + +typedef struct +{ + __IO uint32_t TIM0 : 1; + __IO uint32_t TIM1 : 1; + __IO uint32_t TIM2 : 1; + __IO uint32_t TIM3 : 1; + __IO uint32_t TIM4 : 1; + __IO uint32_t TIM5 : 1; + __IO uint32_t TIM6 : 1; + __IO uint32_t UART0 : 1; + __IO uint32_t UART1 : 1; + __IO uint32_t LPUART0 : 1; + __IO uint32_t LPUART1 : 1; + __IO uint32_t VC0 : 1; + __IO uint32_t VC1 : 1; + __IO uint32_t RTC : 1; + __IO uint32_t PCA : 1; + __IO uint32_t SPI0 : 1; + __IO uint32_t SPI1 : 1; + __IO uint32_t DMA : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PD07 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PA15 : 1; + __IO uint32_t PB15 : 1; + __IO uint32_t PC15 : 1; +} stc_adc_exttrigger1_field_t; + +typedef struct +{ + __IO uint32_t START : 1; +} stc_adc_sglstart_field_t; + +typedef struct +{ + __IO uint32_t START : 1; +} stc_adc_sqrstart_field_t; + +typedef struct +{ + __IO uint32_t START : 1; +} stc_adc_jqrstart_field_t; + +typedef struct +{ + __IO uint32_t START : 1; + __IO uint32_t MODE : 1; +} stc_aes_cr_field_t; + +typedef struct +{ + __IO uint32_t DATA0 :32; +} stc_aes_data0_field_t; + +typedef struct +{ + __IO uint32_t DATA0 :32; +} stc_aes_data1_field_t; + +typedef struct +{ + __IO uint32_t DATA0 :32; +} stc_aes_data2_field_t; + +typedef struct +{ + __IO uint32_t DATA0 :32; +} stc_aes_data3_field_t; + +typedef struct +{ + __IO uint32_t KEY0 :32; +} stc_aes_key0_field_t; + +typedef struct +{ + __IO uint32_t KEY0 :32; +} stc_aes_key1_field_t; + +typedef struct +{ + __IO uint32_t KEY0 :32; +} stc_aes_key2_field_t; + +typedef struct +{ + __IO uint32_t KEY0 :32; +} stc_aes_key3_field_t; + +typedef struct +{ + __IO uint32_t BGR_EN : 1; + __IO uint32_t TS_EN : 1; +} stc_bgr_cr_field_t; + +typedef struct +{ + __IO uint32_t TRIM_START : 1; + __IO uint32_t REFCLK_SEL : 3; + __IO uint32_t CALCLK_SEL : 2; + __IO uint32_t MON_EN : 1; + __IO uint32_t IE : 1; + __IO uint32_t CALCLK_SEL2 : 1; +} stc_clk_trim_cr_field_t; + +typedef struct +{ + __IO uint32_t RCNTVAL :32; +} stc_clk_trim_refcon_field_t; + +typedef struct +{ + __IO uint32_t REFCNT :32; +} stc_clk_trim_refcnt_field_t; + +typedef struct +{ + __IO uint32_t CALCNT :32; +} stc_clk_trim_calcnt_field_t; + +typedef struct +{ + __IO uint32_t STOP : 1; + __IO uint32_t CALCNT_OF : 1; + __IO uint32_t XTL_FAULT : 1; + __IO uint32_t XTH_FAULT : 1; + __IO uint32_t PLL_FAULT : 1; +} stc_clk_trim_ifr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 2; + __IO uint32_t XTL_FAULT_CLR : 1; + __IO uint32_t XTH_FAULT_CLR : 1; + __IO uint32_t PLL_FAULT_CLR : 1; +} stc_clk_trim_iclr_field_t; + +typedef struct +{ + __IO uint32_t CCNTVAL :32; +} stc_clk_trim_calcon_field_t; + +typedef struct +{ + __IO uint32_t CR : 1; + __IO uint32_t FLAG : 1; +} stc_crc_cr_field_t; + +typedef struct +{ + __IO uint32_t RESULT :32; +} stc_crc_result_field_t; + +typedef struct +{ + __IO uint32_t DATA :32; +} stc_crc_data_field_t; + +typedef struct +{ + __IO uint32_t TIM0 : 1; + __IO uint32_t TIM1 : 1; + __IO uint32_t TIM2 : 1; + __IO uint32_t LPTIM : 1; + __IO uint32_t TIM4 : 1; + __IO uint32_t TIM5 : 1; + __IO uint32_t TIM6 : 1; + __IO uint32_t PCA : 1; + __IO uint32_t WDT : 1; + __IO uint32_t RTC : 1; + uint32_t RESERVED10 : 1; + __IO uint32_t TIM3 : 1; +} stc_debug_active_field_t; + +typedef struct +{ + uint32_t RESERVED0 :24; + __IO uint32_t HALT : 4; + __IO uint32_t PRIO : 1; + uint32_t RESERVED29 : 1; + __IO uint32_t ST : 1; + __IO uint32_t EN : 1; +} stc_dmac_conf_field_t; + +typedef struct +{ + __IO uint32_t TC :16; + __IO uint32_t BC : 4; + uint32_t RESERVED20 : 3; + __IO uint32_t TRI_SEL : 6; + __IO uint32_t ST : 1; + __IO uint32_t PAS : 1; + __IO uint32_t ENS : 1; +} stc_dmac_confa0_field_t; + +typedef struct +{ + __IO uint32_t MSK : 1; + uint32_t RESERVED1 :15; + __IO uint32_t STAT : 3; + __IO uint32_t FIS_IE : 1; + __IO uint32_t ERR_IE : 1; + __IO uint32_t RD : 1; + __IO uint32_t RS : 1; + __IO uint32_t RC : 1; + __IO uint32_t FD : 1; + __IO uint32_t FS : 1; + __IO uint32_t WIDTH : 2; + __IO uint32_t MODE : 2; +} stc_dmac_confb0_field_t; + +typedef struct +{ + __IO uint32_t SRCADR :32; +} stc_dmac_srcadr0_field_t; + +typedef struct +{ + __IO uint32_t DSTADR :32; +} stc_dmac_dstadr0_field_t; + +typedef struct +{ + __IO uint32_t TC :16; + __IO uint32_t BC : 4; + uint32_t RESERVED20 : 3; + __IO uint32_t TRI_SEL : 6; + __IO uint32_t ST : 1; + __IO uint32_t PAS : 1; + __IO uint32_t ENS : 1; +} stc_dmac_confa1_field_t; + +typedef struct +{ + __IO uint32_t MSK : 1; + uint32_t RESERVED1 :15; + __IO uint32_t STAT : 3; + __IO uint32_t FIS_IE : 1; + __IO uint32_t ERR_IE : 1; + __IO uint32_t RD : 1; + __IO uint32_t RS : 1; + __IO uint32_t RC : 1; + __IO uint32_t FD : 1; + __IO uint32_t FS : 1; + __IO uint32_t WIDTH : 2; + __IO uint32_t MODE : 2; +} stc_dmac_confb1_field_t; + +typedef struct +{ + __IO uint32_t SRCADR :32; +} stc_dmac_srcadr1_field_t; + +typedef struct +{ + __IO uint32_t DSTADR :32; +} stc_dmac_dstadr1_field_t; + +typedef struct +{ + __IO uint32_t TNVS : 9; +} stc_flash_tnvs_field_t; + +typedef struct +{ + __IO uint32_t TPGS : 8; +} stc_flash_tpgs_field_t; + +typedef struct +{ + __IO uint32_t TPROG : 9; +} stc_flash_tprog_field_t; + +typedef struct +{ + __IO uint32_t TSERASE :18; +} stc_flash_tserase_field_t; + +typedef struct +{ + __IO uint32_t TMERASE :21; +} stc_flash_tmerase_field_t; + +typedef struct +{ + __IO uint32_t TPRCV :12; +} stc_flash_tprcv_field_t; + +typedef struct +{ + __IO uint32_t TSRCV :12; +} stc_flash_tsrcv_field_t; + +typedef struct +{ + __IO uint32_t TMRCV :13; +} stc_flash_tmrcv_field_t; + +typedef struct +{ + __IO uint32_t OP : 2; + __IO uint32_t WAIT : 2; + __IO uint32_t BUSY : 1; + __IO uint32_t IE : 2; + uint32_t RESERVED7 : 2; + __IO uint32_t DPSTB_EN : 1; +} stc_flash_cr_field_t; + +typedef struct +{ + __IO uint32_t IF0 : 1; + __IO uint32_t IF1 : 1; +} stc_flash_ifr_field_t; + +typedef struct +{ + __IO uint32_t ICLR0 : 1; + __IO uint32_t ICLR1 : 1; +} stc_flash_iclr_field_t; + +typedef struct +{ + __IO uint32_t BYSEQ :16; +} stc_flash_bypass_field_t; + +typedef struct +{ + __IO uint32_t SLOCK :32; +} stc_flash_slock_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pa00_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pa01_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pa02_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pa03_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pa04_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pa05_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pa06_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pa07_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pa08_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pa09_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pa10_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pa11_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pa12_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pa13_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pa14_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pa15_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pb00_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pb01_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pb02_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pb03_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pb04_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pb05_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pb06_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pb07_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pb08_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pb09_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pb10_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pb11_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pb12_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pb13_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pb14_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pb15_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pc00_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pc01_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pc02_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pc03_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pc04_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pc05_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pc06_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pc07_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pc08_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pc09_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pc10_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pc11_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pc12_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pc13_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pc14_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pc15_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pd00_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pd01_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pd02_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pd03_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pd04_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pd05_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pd06_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pd07_sel_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; +} stc_gpio_padir_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; +} stc_gpio_pain_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; +} stc_gpio_paout_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; +} stc_gpio_paads_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; +} stc_gpio_pabset_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; +} stc_gpio_pabclr_field_t; + +typedef struct +{ + __IO uint32_t PABCLR :16; + __IO uint32_t PABSET :16; +} stc_gpio_pabsetclr_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; +} stc_gpio_padr_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; +} stc_gpio_papu_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; +} stc_gpio_papd_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; +} stc_gpio_paod_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; +} stc_gpio_pahie_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; +} stc_gpio_palie_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; +} stc_gpio_parie_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; +} stc_gpio_pafie_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; +} stc_gpio_pbdir_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; +} stc_gpio_pbin_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; +} stc_gpio_pbout_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; +} stc_gpio_pbads_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; +} stc_gpio_pbbset_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; +} stc_gpio_pbbclr_field_t; + +typedef struct +{ + __IO uint32_t PBBCLR :16; + __IO uint32_t PBBSET :16; +} stc_gpio_pbbsetclr_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; +} stc_gpio_pbdr_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; +} stc_gpio_pbpu_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; +} stc_gpio_pbpd_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; +} stc_gpio_pbod_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; +} stc_gpio_pbhie_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; +} stc_gpio_pblie_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; +} stc_gpio_pbrie_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; +} stc_gpio_pbfie_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; +} stc_gpio_pcdir_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; +} stc_gpio_pcin_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; +} stc_gpio_pcout_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; +} stc_gpio_pcads_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; +} stc_gpio_pcbset_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; +} stc_gpio_pcbclr_field_t; + +typedef struct +{ + __IO uint32_t PCBCLR :16; + __IO uint32_t PCBSET :16; +} stc_gpio_pcbsetclr_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; +} stc_gpio_pcdr_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; +} stc_gpio_pcpu_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; +} stc_gpio_pcpd_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; +} stc_gpio_pcod_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; +} stc_gpio_pchie_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; +} stc_gpio_pclie_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; +} stc_gpio_pcrie_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; +} stc_gpio_pcfie_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; +} stc_gpio_pddir_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; +} stc_gpio_pdin_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; +} stc_gpio_pdout_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; +} stc_gpio_pdads_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; +} stc_gpio_pdbset_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; +} stc_gpio_pdbclr_field_t; + +typedef struct +{ + __IO uint32_t PDBCLR : 8; + uint32_t RESERVED8 : 8; + __IO uint32_t PDBSET : 8; +} stc_gpio_pdbsetclr_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; +} stc_gpio_pddr_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; +} stc_gpio_pdpu_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; +} stc_gpio_pdpd_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; +} stc_gpio_pdod_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; +} stc_gpio_pdhie_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; +} stc_gpio_pdlie_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; +} stc_gpio_pdrie_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; +} stc_gpio_pdfie_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; +} stc_gpio_pa_stat_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; +} stc_gpio_pa_iclr_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; +} stc_gpio_pb_stat_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; +} stc_gpio_pb_iclr_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; +} stc_gpio_pc_stat_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; +} stc_gpio_pc_iclr_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; +} stc_gpio_pd_stat_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; +} stc_gpio_pd_iclr_field_t; + +typedef struct +{ + __IO uint32_t IESEL : 1; +} stc_gpio_ctrl0_field_t; + +typedef struct +{ + __IO uint32_t EXT_CLK_SEL : 4; + __IO uint32_t SSN0_SEL : 4; + __IO uint32_t PCLK_SEL : 2; + __IO uint32_t HCLK_SEL : 2; + __IO uint32_t PCLK_EN : 1; + __IO uint32_t HCLK_EN : 1; + __IO uint32_t IR_POL : 1; +} stc_gpio_ctrl1_field_t; + +typedef struct +{ + __IO uint32_t SSN1_SEL : 4; + uint32_t RESERVED4 :11; + __IO uint32_t AHB_SEL : 1; +} stc_gpio_ctrl2_field_t; + +typedef struct +{ + __IO uint32_t TIM0_G : 3; + __IO uint32_t TIM1_G : 3; + __IO uint32_t TIM2_G : 3; + __IO uint32_t TIM3_G : 3; + __IO uint32_t LPTIM_G : 3; +} stc_gpio_timgs_field_t; + +typedef struct +{ + __IO uint32_t TIM0_E : 3; + __IO uint32_t TIM1_E : 3; + __IO uint32_t TIM2_E : 3; + __IO uint32_t TIM3_E : 3; + __IO uint32_t LPTIM_E : 3; +} stc_gpio_times_field_t; + +typedef struct +{ + __IO uint32_t TIM0_CA : 3; + __IO uint32_t TIM1_CA : 3; + __IO uint32_t TIM2_CA : 3; + __IO uint32_t TIM3_CA : 3; + __IO uint32_t TIM3_CB : 3; +} stc_gpio_timcps_field_t; + +typedef struct +{ + __IO uint32_t PCA_CH0 : 3; + __IO uint32_t PCA_ECI : 3; +} stc_gpio_pcas_field_t; + +typedef struct +{ + __IO uint32_t DIVIDEND :32; +} stc_hdiv_dividend_field_t; + +typedef struct +{ + __IO uint32_t DIVISOR :16; +} stc_hdiv_divisor_field_t; + +typedef struct +{ + __IO uint32_t QUOTIENT :32; +} stc_hdiv_quotient_field_t; + +typedef struct +{ + __IO uint32_t REMAINDER :32; +} stc_hdiv_remainder_field_t; + +typedef struct +{ + __IO uint32_t SIGN : 1; +} stc_hdiv_sign_field_t; + +typedef struct +{ + __IO uint32_t END : 1; + __IO uint32_t ZERO : 1; +} stc_hdiv_stat_field_t; + +typedef struct +{ + __IO uint32_t TME : 1; +} stc_i2c_tmrun_field_t; + +typedef struct +{ + __IO uint32_t TM : 8; +} stc_i2c_tm_field_t; + +typedef struct +{ + __IO uint32_t H1M : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t AA : 1; + __IO uint32_t SI : 1; + __IO uint32_t STO : 1; + __IO uint32_t STA : 1; + __IO uint32_t ENS : 1; +} stc_i2c_cr_field_t; + +typedef struct +{ + __IO uint32_t DAT : 8; +} stc_i2c_data_field_t; + +typedef struct +{ + __IO uint32_t GC : 1; + __IO uint32_t ADR : 7; +} stc_i2c_addr_field_t; + +typedef struct +{ + __IO uint32_t STA : 8; +} stc_i2c_stat_field_t; + +typedef struct +{ + __IO uint32_t EN : 1; + __IO uint32_t LCDCLK : 2; + __IO uint32_t CPCLK : 2; + __IO uint32_t BIAS : 1; + __IO uint32_t DUTY : 3; + __IO uint32_t BSEL : 3; + __IO uint32_t CONTRAST : 4; +} stc_lcd_cr0_field_t; + +typedef struct +{ + __IO uint32_t BLINKCNT : 6; + __IO uint32_t BLINKEN : 1; + __IO uint32_t CLKSRC : 1; + __IO uint32_t MODE : 1; + __IO uint32_t IE : 1; + __IO uint32_t DMAEN : 1; + __IO uint32_t INTF : 1; +} stc_lcd_cr1_field_t; + +typedef struct +{ + uint32_t RESERVED0 :10; + __IO uint32_t INTF : 1; +} stc_lcd_intclr_field_t; + +typedef struct +{ + __IO uint32_t S0 : 1; + __IO uint32_t S1 : 1; + __IO uint32_t S2 : 1; + __IO uint32_t S3 : 1; + __IO uint32_t S4 : 1; + __IO uint32_t S5 : 1; + __IO uint32_t S6 : 1; + __IO uint32_t S7 : 1; + __IO uint32_t S8 : 1; + __IO uint32_t S9 : 1; + __IO uint32_t S10 : 1; + __IO uint32_t S11 : 1; + __IO uint32_t S12 : 1; + __IO uint32_t S13 : 1; + __IO uint32_t S14 : 1; + __IO uint32_t S15 : 1; + __IO uint32_t S16 : 1; + __IO uint32_t S17 : 1; + __IO uint32_t S18 : 1; + __IO uint32_t S19 : 1; + __IO uint32_t S20 : 1; + __IO uint32_t S21 : 1; + __IO uint32_t S22 : 1; + __IO uint32_t S23 : 1; + __IO uint32_t S24 : 1; + __IO uint32_t S25 : 1; + __IO uint32_t S26 : 1; + __IO uint32_t S27 : 1; + __IO uint32_t S28 : 1; + __IO uint32_t S29 : 1; + __IO uint32_t S30 : 1; + __IO uint32_t S31 : 1; +} stc_lcd_poen0_field_t; + +typedef struct +{ + __IO uint32_t S32 : 1; + __IO uint32_t S33 : 1; + __IO uint32_t S34 : 1; + __IO uint32_t S35 : 1; + __IO uint32_t S36C7 : 1; + __IO uint32_t S37C6 : 1; + __IO uint32_t S38C5 : 1; + __IO uint32_t S39C4 : 1; + __IO uint32_t C0 : 1; + __IO uint32_t C1 : 1; + __IO uint32_t C2 : 1; + __IO uint32_t C3 : 1; + __IO uint32_t MUX : 1; +} stc_lcd_poen1_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t D24 : 1; + __IO uint32_t D25 : 1; + __IO uint32_t D26 : 1; + __IO uint32_t D27 : 1; + __IO uint32_t D28 : 1; + __IO uint32_t D29 : 1; + __IO uint32_t D30 : 1; + __IO uint32_t D31 : 1; +} stc_lcd_ram0_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t D24 : 1; + __IO uint32_t D25 : 1; + __IO uint32_t D26 : 1; + __IO uint32_t D27 : 1; + __IO uint32_t D28 : 1; + __IO uint32_t D29 : 1; + __IO uint32_t D30 : 1; + __IO uint32_t D31 : 1; +} stc_lcd_ram1_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t D24 : 1; + __IO uint32_t D25 : 1; + __IO uint32_t D26 : 1; + __IO uint32_t D27 : 1; + __IO uint32_t D28 : 1; + __IO uint32_t D29 : 1; + __IO uint32_t D30 : 1; + __IO uint32_t D31 : 1; +} stc_lcd_ram2_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t D24 : 1; + __IO uint32_t D25 : 1; + __IO uint32_t D26 : 1; + __IO uint32_t D27 : 1; + __IO uint32_t D28 : 1; + __IO uint32_t D29 : 1; + __IO uint32_t D30 : 1; + __IO uint32_t D31 : 1; +} stc_lcd_ram3_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t D24 : 1; + __IO uint32_t D25 : 1; + __IO uint32_t D26 : 1; + __IO uint32_t D27 : 1; + __IO uint32_t D28 : 1; + __IO uint32_t D29 : 1; + __IO uint32_t D30 : 1; + __IO uint32_t D31 : 1; +} stc_lcd_ram4_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t D24 : 1; + __IO uint32_t D25 : 1; + __IO uint32_t D26 : 1; + __IO uint32_t D27 : 1; + __IO uint32_t D28 : 1; + __IO uint32_t D29 : 1; + __IO uint32_t D30 : 1; + __IO uint32_t D31 : 1; +} stc_lcd_ram5_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t D24 : 1; + __IO uint32_t D25 : 1; + __IO uint32_t D26 : 1; + __IO uint32_t D27 : 1; + __IO uint32_t D28 : 1; + __IO uint32_t D29 : 1; + __IO uint32_t D30 : 1; + __IO uint32_t D31 : 1; +} stc_lcd_ram6_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t D24 : 1; + __IO uint32_t D25 : 1; + __IO uint32_t D26 : 1; + __IO uint32_t D27 : 1; + __IO uint32_t D28 : 1; + __IO uint32_t D29 : 1; + __IO uint32_t D30 : 1; + __IO uint32_t D31 : 1; +} stc_lcd_ram7_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; +} stc_lcd_ram8_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; +} stc_lcd_ram9_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; +} stc_lcd_rama_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; +} stc_lcd_ramb_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; +} stc_lcd_ramc_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; +} stc_lcd_ramd_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; +} stc_lcd_rame_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; +} stc_lcd_ramf_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; +} stc_lptimer_cnt_field_t; + +typedef struct +{ + __IO uint32_t ARR :16; +} stc_lptimer_arr_field_t; + +typedef struct +{ + __IO uint32_t TR : 1; + __IO uint32_t MD : 1; + __IO uint32_t CT : 1; + __IO uint32_t TOG_EN : 1; + __IO uint32_t TCK_SEL : 2; + uint32_t RESERVED6 : 1; + __IO uint32_t WT_FLAG : 1; + __IO uint32_t GATE : 1; + __IO uint32_t GATE_P : 1; + __IO uint32_t IE : 1; +} stc_lptimer_cr_field_t; + +typedef struct +{ + __IO uint32_t TF : 1; +} stc_lptimer_ifr_field_t; + +typedef struct +{ + __IO uint32_t TFC : 1; +} stc_lptimer_iclr_field_t; + +typedef struct +{ + __IO uint32_t DATA : 8; + __IO uint32_t DATA8 : 1; +} stc_lpuart_sbuf_field_t; + +typedef struct +{ + __IO uint32_t RCIE : 1; + __IO uint32_t TCIE : 1; + __IO uint32_t B8CONT : 2; + __IO uint32_t REN : 1; + __IO uint32_t ADRDET : 1; + __IO uint32_t SM : 2; + __IO uint32_t TXEIE : 1; + __IO uint32_t OVER : 2; + __IO uint32_t SCLKSEL : 2; + __IO uint32_t PEIE : 1; + __IO uint32_t STOPBIT : 2; + __IO uint32_t DMARXEN : 1; + __IO uint32_t DMATXEN : 1; + __IO uint32_t RTSEN : 1; + __IO uint32_t CTSEN : 1; + __IO uint32_t CTSIE : 1; + __IO uint32_t FEIE : 1; +} stc_lpuart_scon_field_t; + +typedef struct +{ + __IO uint32_t SADDR : 8; +} stc_lpuart_saddr_field_t; + +typedef struct +{ + __IO uint32_t SADEN : 8; +} stc_lpuart_saden_field_t; + +typedef struct +{ + __IO uint32_t RC : 1; + __IO uint32_t TC : 1; + __IO uint32_t FE : 1; + __IO uint32_t TXE : 1; + __IO uint32_t PE : 1; + __IO uint32_t CTSIF : 1; + __IO uint32_t CTS : 1; +} stc_lpuart_isr_field_t; + +typedef struct +{ + __IO uint32_t RCCF : 1; + __IO uint32_t TCCF : 1; + __IO uint32_t FECF : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t PECF : 1; + __IO uint32_t CTSIFCF : 1; +} stc_lpuart_icr_field_t; + +typedef struct +{ + __IO uint32_t SCNT :16; +} stc_lpuart_scnt_field_t; + +typedef struct +{ + __IO uint32_t LVDEN : 1; + __IO uint32_t ACT : 1; + __IO uint32_t SOURCE_SEL : 2; + __IO uint32_t VTDS : 4; + __IO uint32_t FLTEN : 1; + __IO uint32_t DEBOUNCE_TIME : 3; + __IO uint32_t FTEN : 1; + __IO uint32_t RTEN : 1; + __IO uint32_t HTEN : 1; + __IO uint32_t IE : 1; +} stc_lvd_cr_field_t; + +typedef struct +{ + __IO uint32_t INTF : 1; + __IO uint32_t FILTER : 1; +} stc_lvd_ifr_field_t; + +typedef struct +{ + __IO uint32_t EN : 1; + __IO uint32_t AZEN : 1; + __IO uint32_t MODE : 1; + __IO uint32_t UBUFSEL : 1; + __IO uint32_t RESSEL : 1; + __IO uint32_t BIASSEL : 3; + __IO uint32_t NEGSEL : 2; + __IO uint32_t POSSEL : 2; + __IO uint32_t PGAGAIN : 3; + __IO uint32_t POEN : 1; + __IO uint32_t RESINMUX : 2; +} stc_opa_cr0_field_t; + +typedef struct +{ + __IO uint32_t EN : 1; + __IO uint32_t AZEN : 1; + __IO uint32_t MODE : 1; + __IO uint32_t UBUFSEL : 1; + __IO uint32_t RESSEL : 1; + __IO uint32_t BIASSEL : 3; + __IO uint32_t NEGSEL : 2; + __IO uint32_t POSSEL : 2; + __IO uint32_t PGAGAIN : 3; + __IO uint32_t POEN : 1; + __IO uint32_t RESINMUX : 2; +} stc_opa_cr1_field_t; + +typedef struct +{ + __IO uint32_t EN : 1; + __IO uint32_t AZEN : 1; + __IO uint32_t MODE : 1; + __IO uint32_t UBUFSEL : 1; + __IO uint32_t RESSEL : 1; + __IO uint32_t BIASSEL : 3; + __IO uint32_t NEGSEL : 2; + __IO uint32_t POSSEL : 2; + __IO uint32_t PGAGAIN : 3; + __IO uint32_t POEN : 1; + __IO uint32_t RESINMUX : 2; +} stc_opa_cr2_field_t; + +typedef struct +{ + __IO uint8_t ADCTR_EN : 1; + __IO uint8_t TRIGGER : 1; + __IO uint8_t AZ_PULSE : 1; + __IO uint8_t CLK_SW_SET : 1; + __IO uint8_t CLK_SEL : 4; +} stc_opa_cr_field_t; + +typedef struct +{ + __IO uint32_t CCF0 : 1; + __IO uint32_t CCF1 : 1; + __IO uint32_t CCF2 : 1; + __IO uint32_t CCF3 : 1; + __IO uint32_t CCF4 : 1; + uint32_t RESERVED5 : 1; + __IO uint32_t CR : 1; + __IO uint32_t CF : 1; +} stc_pca_ccon_field_t; + +typedef struct +{ + __IO uint32_t CFIE : 1; + __IO uint32_t CPS : 3; + uint32_t RESERVED4 : 2; + __IO uint32_t WDTE : 1; + __IO uint32_t CIDL : 1; +} stc_pca_cmod_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; +} stc_pca_cnt_field_t; + +typedef struct +{ + __IO uint32_t CCF0 : 1; + __IO uint32_t CCF1 : 1; + __IO uint32_t CCF2 : 1; + __IO uint32_t CCF3 : 1; + __IO uint32_t CCF4 : 1; + uint32_t RESERVED5 : 2; + __IO uint32_t CF : 1; +} stc_pca_iclr_field_t; + +typedef struct +{ + __IO uint32_t CCIE : 1; + __IO uint32_t PWM : 1; + __IO uint32_t TOG : 1; + __IO uint32_t MAT : 1; + __IO uint32_t CAPN : 1; + __IO uint32_t CAPP : 1; + __IO uint32_t ECOM : 1; +} stc_pca_ccapm0_field_t; + +typedef struct +{ + __IO uint32_t CCIE : 1; + __IO uint32_t PWM : 1; + __IO uint32_t TOG : 1; + __IO uint32_t MAT : 1; + __IO uint32_t CAPN : 1; + __IO uint32_t CAPP : 1; + __IO uint32_t ECOM : 1; +} stc_pca_ccapm1_field_t; + +typedef struct +{ + __IO uint32_t CCIE : 1; + __IO uint32_t PWM : 1; + __IO uint32_t TOG : 1; + __IO uint32_t MAT : 1; + __IO uint32_t CAPN : 1; + __IO uint32_t CAPP : 1; + __IO uint32_t ECOM : 1; +} stc_pca_ccapm2_field_t; + +typedef struct +{ + __IO uint32_t CCIE : 1; + __IO uint32_t PWM : 1; + __IO uint32_t TOG : 1; + __IO uint32_t MAT : 1; + __IO uint32_t CAPN : 1; + __IO uint32_t CAPP : 1; + __IO uint32_t ECOM : 1; +} stc_pca_ccapm3_field_t; + +typedef struct +{ + __IO uint32_t CCIE : 1; + __IO uint32_t PWM : 1; + __IO uint32_t TOG : 1; + __IO uint32_t MAT : 1; + __IO uint32_t CAPN : 1; + __IO uint32_t CAPP : 1; + __IO uint32_t ECOM : 1; +} stc_pca_ccapm4_field_t; + +typedef struct +{ + __IO uint32_t CCAP0 : 8; +} stc_pca_ccap0h_field_t; + +typedef struct +{ + __IO uint32_t CCAP0 : 8; +} stc_pca_ccap0l_field_t; + +typedef struct +{ + __IO uint32_t CCAP1 : 8; +} stc_pca_ccap1h_field_t; + +typedef struct +{ + __IO uint32_t CCAP1 : 8; +} stc_pca_ccap1l_field_t; + +typedef struct +{ + __IO uint32_t CCAP2 : 8; +} stc_pca_ccap2h_field_t; + +typedef struct +{ + __IO uint32_t CCAP2 : 8; +} stc_pca_ccap2l_field_t; + +typedef struct +{ + __IO uint32_t CCAP3 : 8; +} stc_pca_ccap3h_field_t; + +typedef struct +{ + __IO uint32_t CCAP3 : 8; +} stc_pca_ccap3l_field_t; + +typedef struct +{ + __IO uint32_t CCAP4 : 8; +} stc_pca_ccap4h_field_t; + +typedef struct +{ + __IO uint32_t CCAP4 : 8; +} stc_pca_ccap4l_field_t; + +typedef struct +{ + __IO uint32_t CCAPO0 : 1; + __IO uint32_t CCAPO1 : 1; + __IO uint32_t CCAPO2 : 1; + __IO uint32_t CCAPO3 : 1; + __IO uint32_t CCAPO4 : 1; +} stc_pca_ccapo_field_t; + +typedef struct +{ + __IO uint32_t CCAP0 :16; +} stc_pca_ccap0_field_t; + +typedef struct +{ + __IO uint32_t CCAP1 :16; +} stc_pca_ccap1_field_t; + +typedef struct +{ + __IO uint32_t CCAP2 :16; +} stc_pca_ccap2_field_t; + +typedef struct +{ + __IO uint32_t CCAP3 :16; +} stc_pca_ccap3_field_t; + +typedef struct +{ + __IO uint32_t CCAP4 :16; +} stc_pca_ccap4_field_t; + +typedef struct +{ + __IO uint32_t CARR :16; +} stc_pca_carr_field_t; + +typedef struct +{ + __IO uint32_t EPWM : 1; +} stc_pca_epwm_field_t; + +typedef struct +{ + __IO uint8_t RUN : 1; +} stc_pcnt_run_field_t; + +typedef struct +{ + __IO uint8_t MODE : 2; + __IO uint8_t CLKSEL : 2; + __IO uint8_t DIR : 1; + __IO uint8_t S0P : 1; + __IO uint8_t S1P : 1; +} stc_pcnt_cr_field_t; + +typedef struct +{ + __IO uint32_t CLKDIV :13; + __IO uint32_t DEBTOP : 3; + __IO uint32_t EN : 1; +} stc_pcnt_flt_field_t; + +typedef struct +{ + __IO uint32_t TH :12; + uint32_t RESERVED12 : 4; + __IO uint32_t EN : 1; +} stc_pcnt_tocr_field_t; + +typedef struct +{ + __IO uint8_t T2C : 1; + __IO uint8_t B2T : 1; + __IO uint8_t B2C : 1; +} stc_pcnt_cmd_field_t; + +typedef struct +{ + __IO uint8_t DIR : 1; +} stc_pcnt_sr1_field_t; + +typedef struct +{ + __IO uint16_t CNT :16; +} stc_pcnt_cnt_field_t; + +typedef struct +{ + __IO uint16_t TOP :16; +} stc_pcnt_top_field_t; + +typedef struct +{ + __IO uint16_t BUF :16; +} stc_pcnt_buf_field_t; + +typedef struct +{ + __IO uint8_t UF : 1; + __IO uint8_t OV : 1; + __IO uint8_t TO : 1; + __IO uint8_t DIR : 1; + __IO uint8_t FE : 1; + __IO uint8_t BB : 1; + __IO uint8_t S0E : 1; + __IO uint8_t S1E : 1; +} stc_pcnt_ifr_field_t; + +typedef struct +{ + __IO uint8_t UF : 1; + __IO uint8_t OV : 1; + __IO uint8_t TO : 1; + __IO uint8_t DIR : 1; + __IO uint8_t FE : 1; + __IO uint8_t BB : 1; + __IO uint8_t S0E : 1; + __IO uint8_t S1E : 1; +} stc_pcnt_icr_field_t; + +typedef struct +{ + __IO uint8_t UF : 1; + __IO uint8_t OV : 1; + __IO uint8_t TO : 1; + __IO uint8_t DIR : 1; + __IO uint8_t FE : 1; + __IO uint8_t BB : 1; + __IO uint8_t S0E : 1; + __IO uint8_t S1E : 1; +} stc_pcnt_ien_field_t; + +typedef struct +{ + __IO uint8_t T2C : 1; + __IO uint8_t B2T : 1; + __IO uint8_t B2C : 1; +} stc_pcnt_sr2_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 1; + __IO uint32_t IE : 1; +} stc_ram_cr_field_t; + +typedef struct +{ + __IO uint32_t ERRADDR :13; +} stc_ram_erraddr_field_t; + +typedef struct +{ + __IO uint32_t ERR : 1; +} stc_ram_ifr_field_t; + +typedef struct +{ + __IO uint32_t ERRCLR : 1; +} stc_ram_iclr_field_t; + +typedef struct +{ + __IO uint32_t POR5V : 1; + __IO uint32_t POR15V : 1; + __IO uint32_t LVD : 1; + __IO uint32_t WDT : 1; + __IO uint32_t PCA : 1; + __IO uint32_t LOCKUP : 1; + __IO uint32_t SYSREQ : 1; + __IO uint32_t RSTB : 1; +} stc_reset_flag_field_t; + +typedef struct +{ + __IO uint32_t UART0 : 1; + __IO uint32_t UART1 : 1; + __IO uint32_t LPUART0 : 1; + __IO uint32_t LPUART1 : 1; + __IO uint32_t I2C0 : 1; + __IO uint32_t I2C1 : 1; + __IO uint32_t SPI0 : 1; + __IO uint32_t SPI1 : 1; + __IO uint32_t BASETIM : 1; + __IO uint32_t LPTIM : 1; + __IO uint32_t ADVTIM : 1; + __IO uint32_t TIM3 : 1; + uint32_t RESERVED12 : 1; + __IO uint32_t OPA : 1; + __IO uint32_t PCA : 1; + uint32_t RESERVED15 : 1; + __IO uint32_t ADC : 1; + __IO uint32_t VC : 1; + __IO uint32_t RNG : 1; + __IO uint32_t PCNT : 1; + __IO uint32_t RTC : 1; + __IO uint32_t TRIM : 1; + __IO uint32_t LCD : 1; + uint32_t RESERVED23 : 1; + __IO uint32_t TICK : 1; + __IO uint32_t SWD : 1; + __IO uint32_t CRC : 1; + __IO uint32_t AES : 1; + __IO uint32_t GPIO : 1; + __IO uint32_t DMA : 1; + __IO uint32_t DIV : 1; +} stc_reset_prei_field_t; + +typedef struct +{ + __IO uint32_t RNGCIR_EN : 1; + __IO uint32_t RNG_RUN : 1; +} stc_rng_cr_field_t; + +typedef struct +{ + __IO uint32_t LOAD : 1; + __IO uint32_t FDBK : 1; + __IO uint32_t CNT : 3; +} stc_rng_mode_field_t; + +typedef struct +{ + __IO uint32_t DATA0 :32; +} stc_rng_data0_field_t; + +typedef struct +{ + __IO uint32_t DATA1 :32; +} stc_rng_data1_field_t; + +typedef struct +{ + __IO uint32_t PRDS : 3; + __IO uint32_t AMPM : 1; + uint32_t RESERVED4 : 1; + __IO uint32_t HZ1OE : 1; + __IO uint32_t HZ1SEL : 1; + __IO uint32_t START : 1; + __IO uint32_t PRDX : 6; + __IO uint32_t PRDSEL : 1; +} stc_rtc_cr0_field_t; + +typedef struct +{ + __IO uint32_t WAIT : 1; + __IO uint32_t WAITF : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t PRDF : 1; + __IO uint32_t ALMF : 1; + uint32_t RESERVED5 : 1; + __IO uint32_t ALMIE : 1; + __IO uint32_t ALMEN : 1; + __IO uint32_t CKSEL : 3; +} stc_rtc_cr1_field_t; + +typedef struct +{ + __IO uint32_t SECL : 4; + __IO uint32_t SECH : 3; +} stc_rtc_sec_field_t; + +typedef struct +{ + __IO uint32_t MINL : 4; + __IO uint32_t MINH : 3; +} stc_rtc_min_field_t; + +typedef struct +{ + __IO uint32_t HOURL : 4; + __IO uint32_t HOURH : 2; +} stc_rtc_hour_field_t; + +typedef struct +{ + __IO uint32_t WEEK : 3; +} stc_rtc_week_field_t; + +typedef struct +{ + __IO uint32_t DAYL : 4; + __IO uint32_t DAYH : 2; +} stc_rtc_day_field_t; + +typedef struct +{ + __IO uint32_t MON : 5; +} stc_rtc_mon_field_t; + +typedef struct +{ + __IO uint32_t YEARL : 4; + __IO uint32_t YEARH : 4; +} stc_rtc_year_field_t; + +typedef struct +{ + __IO uint32_t ALMMINL : 4; + __IO uint32_t ALMMINH : 3; +} stc_rtc_almmin_field_t; + +typedef struct +{ + __IO uint32_t ALMHOURL : 4; + __IO uint32_t ALMHOURH : 2; +} stc_rtc_almhour_field_t; + +typedef struct +{ + __IO uint32_t ALMWEEK : 7; +} stc_rtc_almweek_field_t; + +typedef struct +{ + __IO uint32_t CR : 9; + uint32_t RESERVED9 : 6; + __IO uint32_t EN : 1; +} stc_rtc_compen_field_t; + +typedef struct +{ + __IO uint32_t SPR0 : 1; + __IO uint32_t SPR1 : 1; + __IO uint32_t CPHA : 1; + __IO uint32_t CPOL : 1; + __IO uint32_t MSTR : 1; + uint32_t RESERVED5 : 1; + __IO uint32_t SPEN : 1; + __IO uint32_t SPR2 : 1; +} stc_spi_cr_field_t; + +typedef struct +{ + __IO uint32_t SSN : 1; +} stc_spi_ssn_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 1; + __IO uint32_t RXNE : 1; + __IO uint32_t TXE : 1; + __IO uint32_t BUSY : 1; + __IO uint32_t MDF : 1; + __IO uint32_t SSERR : 1; + uint32_t RESERVED6 : 1; + __IO uint32_t SPIF : 1; +} stc_spi_stat_field_t; + +typedef struct +{ + __IO uint32_t DAT : 8; +} stc_spi_data_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 2; + __IO uint32_t INT_EN : 1; + __IO uint32_t HDMA_RX : 1; + __IO uint32_t HDMA_TX : 1; + __IO uint32_t TXEIE : 1; + __IO uint32_t RXNEIE : 1; +} stc_spi_cr2_field_t; + +typedef struct +{ + __IO uint32_t INT_CLR : 1; +} stc_spi_iclr_field_t; + +typedef struct +{ + __IO uint32_t RCH_EN : 1; + __IO uint32_t XTH_EN : 1; + __IO uint32_t RCL_EN : 1; + __IO uint32_t XTL_EN : 1; + __IO uint32_t PLL_EN : 1; + __IO uint32_t CLK_SW5_SEL : 3; + __IO uint32_t HCLK_PRS : 3; + __IO uint32_t PCLK_PRS : 2; + uint32_t RESERVED13 : 2; + __IO uint32_t WAKEUP_BYRCH : 1; +} stc_sysctrl_sysctrl0_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 1; + __IO uint32_t EXTH_EN : 1; + __IO uint32_t EXTL_EN : 1; + __IO uint32_t XTL_ALWAYS_ON : 1; + uint32_t RESERVED4 : 1; + __IO uint32_t RTC_LPW : 1; + __IO uint32_t LOCKUP_EN : 1; + uint32_t RESERVED7 : 1; + __IO uint32_t SWD_USE_IO : 1; + __IO uint32_t RTC_FREQ_ADJUST : 3; +} stc_sysctrl_sysctrl1_field_t; + +typedef struct +{ + __IO uint32_t SYSCTRL2 :16; +} stc_sysctrl_sysctrl2_field_t; + +typedef struct +{ + __IO uint32_t TRIM :11; + __IO uint32_t STABLE : 1; +} stc_sysctrl_rch_cr_field_t; + +typedef struct +{ + __IO uint32_t DRIVER : 2; + __IO uint32_t XTH_FSEL : 2; + __IO uint32_t STARTUP : 2; + __IO uint32_t STABLE : 1; +} stc_sysctrl_xth_cr_field_t; + +typedef struct +{ + __IO uint32_t TRIM :10; + __IO uint32_t STARTUP : 2; + __IO uint32_t STABLE : 1; +} stc_sysctrl_rcl_cr_field_t; + +typedef struct +{ + __IO uint32_t DRIVER : 2; + __IO uint32_t AMP_SEL : 2; + __IO uint32_t STARTUP : 2; + __IO uint32_t STABLE : 1; +} stc_sysctrl_xtl_cr_field_t; + +typedef struct +{ + __IO uint32_t UART0 : 1; + __IO uint32_t UART1 : 1; + __IO uint32_t LPUART0 : 1; + __IO uint32_t LPUART1 : 1; + __IO uint32_t I2C0 : 1; + __IO uint32_t I2C1 : 1; + __IO uint32_t SPI0 : 1; + __IO uint32_t SPI1 : 1; + __IO uint32_t BASETIM : 1; + __IO uint32_t LPTIM : 1; + __IO uint32_t ADVTIM : 1; + __IO uint32_t TIM3 : 1; + uint32_t RESERVED12 : 1; + __IO uint32_t OPA : 1; + __IO uint32_t PCA : 1; + __IO uint32_t WDT : 1; + __IO uint32_t ADC : 1; + __IO uint32_t VC : 1; + __IO uint32_t RNG : 1; + __IO uint32_t PCNT : 1; + __IO uint32_t RTC : 1; + __IO uint32_t TRIM : 1; + __IO uint32_t LCD : 1; + uint32_t RESERVED23 : 1; + __IO uint32_t TICK : 1; + __IO uint32_t SWD : 1; + __IO uint32_t CRC : 1; + __IO uint32_t AES : 1; + __IO uint32_t GPIO : 1; + __IO uint32_t DMA : 1; + __IO uint32_t DIV : 1; + __IO uint32_t FLASH : 1; +} stc_sysctrl_peri_clken_field_t; + +typedef struct +{ + __IO uint32_t REFSEL : 2; + __IO uint32_t FOSC : 3; + __IO uint32_t DIVN : 4; + __IO uint32_t IBSEL : 2; + __IO uint32_t LFSEL : 2; + __IO uint32_t FRSEL : 2; + __IO uint32_t STARTUP : 3; + __IO uint32_t STABLE : 1; +} stc_sysctrl_pll_cr_field_t; + +typedef struct +{ + __IO uint32_t ARR :16; +} stc_tim0_mode0_arr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; +} stc_tim0_mode0_cnt_field_t; + +typedef struct +{ + __IO uint32_t CNT32 :32; +} stc_tim0_mode0_cnt32_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + __IO uint32_t MD : 1; + __IO uint32_t CT : 1; + __IO uint32_t TOGEN : 1; + __IO uint32_t PRS : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t GATE : 1; + __IO uint32_t GATEP : 1; + __IO uint32_t UIE : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t MODE : 2; +} stc_tim0_mode0_m0cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; +} stc_tim0_mode0_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; +} stc_tim0_mode0_iclr_field_t; + +typedef struct +{ + uint32_t RESERVED0 :12; + __IO uint32_t MOE : 1; +} stc_tim0_mode0_dtr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; +} stc_tim0_mode1_cnt_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CT : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t PRS : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t EDG1ST : 1; + __IO uint32_t EDG2ND : 1; + __IO uint32_t UIE : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t MODE : 2; + __IO uint32_t ONESHOT : 1; +} stc_tim0_mode1_m1cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; +} stc_tim0_mode1_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; +} stc_tim0_mode1_iclr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 5; + __IO uint32_t TS : 3; + uint32_t RESERVED8 : 3; + __IO uint32_t IA0S : 1; + __IO uint32_t IB0S : 1; +} stc_tim0_mode1_mscr_field_t; + +typedef struct +{ + __IO uint32_t FLTA0 : 3; + uint32_t RESERVED3 : 1; + __IO uint32_t FLTB0 : 3; + uint32_t RESERVED7 :21; + __IO uint32_t FLTET : 3; + __IO uint32_t ETP : 1; +} stc_tim0_mode1_fltr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 8; + __IO uint32_t CIEA : 1; +} stc_tim0_mode1_cr0_field_t; + +typedef struct +{ + __IO uint32_t CCR0A :16; +} stc_tim0_mode1_ccr0a_field_t; + +typedef struct +{ + __IO uint32_t ARR :16; +} stc_tim0_mode23_arr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; +} stc_tim0_mode23_cnt_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + __IO uint32_t COMP : 1; + __IO uint32_t CT : 1; + __IO uint32_t PWM2S : 1; + __IO uint32_t PRS : 3; + __IO uint32_t BUFPEN : 1; + __IO uint32_t CRG : 1; + __IO uint32_t CFG : 1; + __IO uint32_t UIE : 1; + __IO uint32_t UDE : 1; + __IO uint32_t MODE : 2; + __IO uint32_t ONESHOT : 1; + __IO uint32_t CSG : 1; + __IO uint32_t OCCS : 1; + __IO uint32_t URS : 1; + __IO uint32_t TDE : 1; + __IO uint32_t TIE : 1; + __IO uint32_t BIE : 1; + __IO uint32_t CIS : 2; + __IO uint32_t OCCE : 1; + __IO uint32_t TG : 1; + __IO uint32_t UG : 1; + __IO uint32_t BG : 1; + __IO uint32_t DIR : 1; +} stc_tim0_mode23_m23cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + uint32_t RESERVED3 : 2; + __IO uint32_t CB0F : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t CA0E : 1; + uint32_t RESERVED9 : 2; + __IO uint32_t CB0E : 1; + uint32_t RESERVED12 : 2; + __IO uint32_t BIF : 1; + __IO uint32_t TIF : 1; +} stc_tim0_mode23_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + uint32_t RESERVED3 : 2; + __IO uint32_t CB0F : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t CA0E : 1; + uint32_t RESERVED9 : 2; + __IO uint32_t CB0E : 1; + uint32_t RESERVED12 : 2; + __IO uint32_t BIF : 1; + __IO uint32_t TIF : 1; +} stc_tim0_mode23_iclr_field_t; + +typedef struct +{ + __IO uint32_t MMS : 3; + __IO uint32_t CCDS : 1; + __IO uint32_t MSM : 1; + __IO uint32_t TS : 3; + __IO uint32_t SMS : 3; + __IO uint32_t IA0S : 1; + __IO uint32_t IB0S : 1; +} stc_tim0_mode23_mscr_field_t; + +typedef struct +{ + __IO uint32_t OCMA0_FLTA0 : 3; + __IO uint32_t CCPA0 : 1; + __IO uint32_t OCMB0_FLTB0 : 3; + __IO uint32_t CCPB0 : 1; + uint32_t RESERVED8 :16; + __IO uint32_t FLTBK : 3; + __IO uint32_t BKP : 1; + __IO uint32_t FLTET : 3; + __IO uint32_t ETP : 1; +} stc_tim0_mode23_fltr_field_t; + +typedef struct +{ + __IO uint32_t UEVE : 1; + __IO uint32_t CMA0E : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t CMB0E : 1; + uint32_t RESERVED5 : 2; + __IO uint32_t ADTE : 1; +} stc_tim0_mode23_adtr_field_t; + +typedef struct +{ + __IO uint32_t CFA_CRA_BKSA : 2; + __IO uint32_t CFB_CRB_BKSB : 2; + __IO uint32_t CSA : 1; + __IO uint32_t CSB : 1; + __IO uint32_t BUFEA : 1; + __IO uint32_t BUFEB : 1; + __IO uint32_t CIEA : 1; + __IO uint32_t CIEB : 1; + __IO uint32_t CDEA : 1; + __IO uint32_t CDEB : 1; + __IO uint32_t CISB : 2; + __IO uint32_t CCGA : 1; + __IO uint32_t CCGB : 1; +} stc_tim0_mode23_crch0_field_t; + +typedef struct +{ + __IO uint32_t DTR : 8; + __IO uint32_t BKSEL : 1; + __IO uint32_t DTEN : 1; + __IO uint32_t BKE : 1; + __IO uint32_t AOE : 1; + __IO uint32_t MOE : 1; + __IO uint32_t SAFEEN : 1; + __IO uint32_t VC0E : 1; + __IO uint32_t VC1E : 1; +} stc_tim0_mode23_dtr_field_t; + +typedef struct +{ + __IO uint32_t RCR : 8; +} stc_tim0_mode23_rcr_field_t; + +typedef struct +{ + __IO uint32_t ARRDM :16; +} stc_tim0_mode23_arrdm_field_t; + +typedef struct +{ + __IO uint32_t CCR0A :16; +} stc_tim0_mode23_ccr0a_field_t; + +typedef struct +{ + __IO uint32_t CCR0B :16; +} stc_tim0_mode23_ccr0b_field_t; + +typedef struct +{ + __IO uint32_t ARR :16; +} stc_tim1_mode0_arr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; +} stc_tim1_mode0_cnt_field_t; + +typedef struct +{ + __IO uint32_t CNT32 :32; +} stc_tim1_mode0_cnt32_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + __IO uint32_t MD : 1; + __IO uint32_t CT : 1; + __IO uint32_t TOGEN : 1; + __IO uint32_t PRS : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t GATE : 1; + __IO uint32_t GATEP : 1; + __IO uint32_t UIE : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t MODE : 2; +} stc_tim1_mode0_m0cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; +} stc_tim1_mode0_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; +} stc_tim1_mode0_iclr_field_t; + +typedef struct +{ + uint32_t RESERVED0 :12; + __IO uint32_t MOE : 1; +} stc_tim1_mode0_dtr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; +} stc_tim1_mode1_cnt_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CT : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t PRS : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t EDG1ST : 1; + __IO uint32_t EDG2ND : 1; + __IO uint32_t UIE : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t MODE : 2; + __IO uint32_t ONESHOT : 1; +} stc_tim1_mode1_m1cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; +} stc_tim1_mode1_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; +} stc_tim1_mode1_iclr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 5; + __IO uint32_t TS : 3; + uint32_t RESERVED8 : 3; + __IO uint32_t IA0S : 1; + __IO uint32_t IB0S : 1; +} stc_tim1_mode1_mscr_field_t; + +typedef struct +{ + __IO uint32_t FLTA0 : 3; + uint32_t RESERVED3 : 1; + __IO uint32_t FLTB0 : 3; + uint32_t RESERVED7 :21; + __IO uint32_t FLTET : 3; + __IO uint32_t ETP : 1; +} stc_tim1_mode1_fltr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 8; + __IO uint32_t CIEA : 1; +} stc_tim1_mode1_cr0_field_t; + +typedef struct +{ + __IO uint32_t CCR0A :16; +} stc_tim1_mode1_ccr0a_field_t; + +typedef struct +{ + __IO uint32_t ARR :16; +} stc_tim1_mode23_arr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; +} stc_tim1_mode23_cnt_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + __IO uint32_t COMP : 1; + __IO uint32_t CT : 1; + __IO uint32_t PWM2S : 1; + __IO uint32_t PRS : 3; + __IO uint32_t BUFPEN : 1; + __IO uint32_t CRG : 1; + __IO uint32_t CFG : 1; + __IO uint32_t UIE : 1; + __IO uint32_t UDE : 1; + __IO uint32_t MODE : 2; + __IO uint32_t ONESHOT : 1; + __IO uint32_t CSG : 1; + __IO uint32_t OCCS : 1; + __IO uint32_t URS : 1; + __IO uint32_t TDE : 1; + __IO uint32_t TIE : 1; + __IO uint32_t BIE : 1; + __IO uint32_t CIS : 2; + __IO uint32_t OCCE : 1; + __IO uint32_t TG : 1; + __IO uint32_t UG : 1; + __IO uint32_t BG : 1; + __IO uint32_t DIR : 1; +} stc_tim1_mode23_m23cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + uint32_t RESERVED3 : 2; + __IO uint32_t CB0F : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t CA0E : 1; + uint32_t RESERVED9 : 2; + __IO uint32_t CB0E : 1; + uint32_t RESERVED12 : 2; + __IO uint32_t BIF : 1; + __IO uint32_t TIF : 1; +} stc_tim1_mode23_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + uint32_t RESERVED3 : 2; + __IO uint32_t CB0F : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t CA0E : 1; + uint32_t RESERVED9 : 2; + __IO uint32_t CB0E : 1; + uint32_t RESERVED12 : 2; + __IO uint32_t BIF : 1; + __IO uint32_t TIF : 1; +} stc_tim1_mode23_iclr_field_t; + +typedef struct +{ + __IO uint32_t MMS : 3; + __IO uint32_t CCDS : 1; + __IO uint32_t MSM : 1; + __IO uint32_t TS : 3; + __IO uint32_t SMS : 3; + __IO uint32_t IA0S : 1; + __IO uint32_t IB0S : 1; +} stc_tim1_mode23_mscr_field_t; + +typedef struct +{ + __IO uint32_t OCMA0_FLTA0 : 3; + __IO uint32_t CCPA0 : 1; + __IO uint32_t OCMB0_FLTB0 : 3; + __IO uint32_t CCPB0 : 1; + uint32_t RESERVED8 :16; + __IO uint32_t FLTBK : 3; + __IO uint32_t BKP : 1; + __IO uint32_t FLTET : 3; + __IO uint32_t ETP : 1; +} stc_tim1_mode23_fltr_field_t; + +typedef struct +{ + __IO uint32_t UEVE : 1; + __IO uint32_t CMA0E : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t CMB0E : 1; + uint32_t RESERVED5 : 2; + __IO uint32_t ADTE : 1; +} stc_tim1_mode23_adtr_field_t; + +typedef struct +{ + __IO uint32_t CFA_CRA_BKSA : 2; + __IO uint32_t CFB_CRB_BKSB : 2; + __IO uint32_t CSA : 1; + __IO uint32_t CSB : 1; + __IO uint32_t BUFEA : 1; + __IO uint32_t BUFEB : 1; + __IO uint32_t CIEA : 1; + __IO uint32_t CIEB : 1; + __IO uint32_t CDEA : 1; + __IO uint32_t CDEB : 1; + __IO uint32_t CISB : 2; + __IO uint32_t CCGA : 1; + __IO uint32_t CCGB : 1; +} stc_tim1_mode23_crch0_field_t; + +typedef struct +{ + __IO uint32_t DTR : 8; + __IO uint32_t BKSEL : 1; + __IO uint32_t DTEN : 1; + __IO uint32_t BKE : 1; + __IO uint32_t AOE : 1; + __IO uint32_t MOE : 1; + __IO uint32_t SAFEEN : 1; + __IO uint32_t VC0E : 1; + __IO uint32_t VC1E : 1; +} stc_tim1_mode23_dtr_field_t; + +typedef struct +{ + __IO uint32_t RCR : 8; +} stc_tim1_mode23_rcr_field_t; + +typedef struct +{ + __IO uint32_t ARRDM :16; +} stc_tim1_mode23_arrdm_field_t; + +typedef struct +{ + __IO uint32_t CCR0A :16; +} stc_tim1_mode23_ccr0a_field_t; + +typedef struct +{ + __IO uint32_t CCR0B :16; +} stc_tim1_mode23_ccr0b_field_t; + +typedef struct +{ + __IO uint32_t ARR :16; +} stc_tim2_mode0_arr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; +} stc_tim2_mode0_cnt_field_t; + +typedef struct +{ + __IO uint32_t CNT32 :32; +} stc_tim2_mode0_cnt32_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + __IO uint32_t MD : 1; + __IO uint32_t CT : 1; + __IO uint32_t TOGEN : 1; + __IO uint32_t PRS : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t GATE : 1; + __IO uint32_t GATEP : 1; + __IO uint32_t UIE : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t MODE : 2; +} stc_tim2_mode0_m0cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; +} stc_tim2_mode0_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; +} stc_tim2_mode0_iclr_field_t; + +typedef struct +{ + uint32_t RESERVED0 :12; + __IO uint32_t MOE : 1; +} stc_tim2_mode0_dtr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; +} stc_tim2_mode1_cnt_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CT : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t PRS : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t EDG1ST : 1; + __IO uint32_t EDG2ND : 1; + __IO uint32_t UIE : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t MODE : 2; + __IO uint32_t ONESHOT : 1; +} stc_tim2_mode1_m1cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; +} stc_tim2_mode1_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; +} stc_tim2_mode1_iclr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 5; + __IO uint32_t TS : 3; + uint32_t RESERVED8 : 3; + __IO uint32_t IA0S : 1; + __IO uint32_t IB0S : 1; +} stc_tim2_mode1_mscr_field_t; + +typedef struct +{ + __IO uint32_t FLTA0 : 3; + uint32_t RESERVED3 : 1; + __IO uint32_t FLTB0 : 3; + uint32_t RESERVED7 :21; + __IO uint32_t FLTET : 3; + __IO uint32_t ETP : 1; +} stc_tim2_mode1_fltr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 8; + __IO uint32_t CIEA : 1; +} stc_tim2_mode1_cr0_field_t; + +typedef struct +{ + __IO uint32_t CCR0A :16; +} stc_tim2_mode1_ccr0a_field_t; + +typedef struct +{ + __IO uint32_t ARR :16; +} stc_tim2_mode23_arr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; +} stc_tim2_mode23_cnt_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + __IO uint32_t COMP : 1; + __IO uint32_t CT : 1; + __IO uint32_t PWM2S : 1; + __IO uint32_t PRS : 3; + __IO uint32_t BUFPEN : 1; + __IO uint32_t CRG : 1; + __IO uint32_t CFG : 1; + __IO uint32_t UIE : 1; + __IO uint32_t UDE : 1; + __IO uint32_t MODE : 2; + __IO uint32_t ONESHOT : 1; + __IO uint32_t CSG : 1; + __IO uint32_t OCCS : 1; + __IO uint32_t URS : 1; + __IO uint32_t TDE : 1; + __IO uint32_t TIE : 1; + __IO uint32_t BIE : 1; + __IO uint32_t CIS : 2; + __IO uint32_t OCCE : 1; + __IO uint32_t TG : 1; + __IO uint32_t UG : 1; + __IO uint32_t BG : 1; + __IO uint32_t DIR : 1; +} stc_tim2_mode23_m23cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + uint32_t RESERVED3 : 2; + __IO uint32_t CB0F : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t CA0E : 1; + uint32_t RESERVED9 : 2; + __IO uint32_t CB0E : 1; + uint32_t RESERVED12 : 2; + __IO uint32_t BIF : 1; + __IO uint32_t TIF : 1; +} stc_tim2_mode23_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + uint32_t RESERVED3 : 2; + __IO uint32_t CB0F : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t CA0E : 1; + uint32_t RESERVED9 : 2; + __IO uint32_t CB0E : 1; + uint32_t RESERVED12 : 2; + __IO uint32_t BIF : 1; + __IO uint32_t TIF : 1; +} stc_tim2_mode23_iclr_field_t; + +typedef struct +{ + __IO uint32_t MMS : 3; + __IO uint32_t CCDS : 1; + __IO uint32_t MSM : 1; + __IO uint32_t TS : 3; + __IO uint32_t SMS : 3; + __IO uint32_t IA0S : 1; + __IO uint32_t IB0S : 1; +} stc_tim2_mode23_mscr_field_t; + +typedef struct +{ + __IO uint32_t OCMA0_FLTA0 : 3; + __IO uint32_t CCPA0 : 1; + __IO uint32_t OCMB0_FLTB0 : 3; + __IO uint32_t CCPB0 : 1; + uint32_t RESERVED8 :16; + __IO uint32_t FLTBK : 3; + __IO uint32_t BKP : 1; + __IO uint32_t FLTET : 3; + __IO uint32_t ETP : 1; +} stc_tim2_mode23_fltr_field_t; + +typedef struct +{ + __IO uint32_t UEVE : 1; + __IO uint32_t CMA0E : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t CMB0E : 1; + uint32_t RESERVED5 : 2; + __IO uint32_t ADTE : 1; +} stc_tim2_mode23_adtr_field_t; + +typedef struct +{ + __IO uint32_t CFA_CRA_BKSA : 2; + __IO uint32_t CFB_CRB_BKSB : 2; + __IO uint32_t CSA : 1; + __IO uint32_t CSB : 1; + __IO uint32_t BUFEA : 1; + __IO uint32_t BUFEB : 1; + __IO uint32_t CIEA : 1; + __IO uint32_t CIEB : 1; + __IO uint32_t CDEA : 1; + __IO uint32_t CDEB : 1; + __IO uint32_t CISB : 2; + __IO uint32_t CCGA : 1; + __IO uint32_t CCGB : 1; +} stc_tim2_mode23_crch0_field_t; + +typedef struct +{ + __IO uint32_t DTR : 8; + __IO uint32_t BKSEL : 1; + __IO uint32_t DTEN : 1; + __IO uint32_t BKE : 1; + __IO uint32_t AOE : 1; + __IO uint32_t MOE : 1; + __IO uint32_t SAFEEN : 1; + __IO uint32_t VC0E : 1; + __IO uint32_t VC1E : 1; +} stc_tim2_mode23_dtr_field_t; + +typedef struct +{ + __IO uint32_t RCR : 8; +} stc_tim2_mode23_rcr_field_t; + +typedef struct +{ + __IO uint32_t ARRDM :16; +} stc_tim2_mode23_arrdm_field_t; + +typedef struct +{ + __IO uint32_t CCR0A :16; +} stc_tim2_mode23_ccr0a_field_t; + +typedef struct +{ + __IO uint32_t CCR0B :16; +} stc_tim2_mode23_ccr0b_field_t; + +typedef struct +{ + __IO uint32_t ARR :16; +} stc_tim3_mode0_arr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; +} stc_tim3_mode0_cnt_field_t; + +typedef struct +{ + __IO uint32_t CNT32 :32; +} stc_tim3_mode0_cnt32_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + __IO uint32_t MD : 1; + __IO uint32_t CT : 1; + __IO uint32_t TOGEN : 1; + __IO uint32_t PRS : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t GATE : 1; + __IO uint32_t GATEP : 1; + __IO uint32_t UIE : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t MODE : 2; +} stc_tim3_mode0_m0cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; +} stc_tim3_mode0_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; +} stc_tim3_mode0_iclr_field_t; + +typedef struct +{ + uint32_t RESERVED0 :12; + __IO uint32_t MOE : 1; +} stc_tim3_mode0_dtr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; +} stc_tim3_mode1_cnt_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CT : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t PRS : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t EDG1ST : 1; + __IO uint32_t EDG2ND : 1; + __IO uint32_t UIE : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t MODE : 2; + __IO uint32_t ONESHOT : 1; +} stc_tim3_mode1_m1cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; +} stc_tim3_mode1_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; +} stc_tim3_mode1_iclr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 5; + __IO uint32_t TS : 3; + uint32_t RESERVED8 : 3; + __IO uint32_t IA0S : 1; + __IO uint32_t IB0S : 1; +} stc_tim3_mode1_mscr_field_t; + +typedef struct +{ + __IO uint32_t FLTA0 : 3; + uint32_t RESERVED3 : 1; + __IO uint32_t FLTB0 : 3; + uint32_t RESERVED7 :21; + __IO uint32_t FLTET : 3; + __IO uint32_t ETP : 1; +} stc_tim3_mode1_fltr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 8; + __IO uint32_t CIEA : 1; +} stc_tim3_mode1_cr0_field_t; + +typedef struct +{ + __IO uint32_t CCR0A :16; +} stc_tim3_mode1_ccr0a_field_t; + +typedef struct +{ + __IO uint32_t ARR :16; +} stc_tim3_mode23_arr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; +} stc_tim3_mode23_cnt_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + __IO uint32_t COMP : 1; + __IO uint32_t CT : 1; + __IO uint32_t PWM2S : 1; + __IO uint32_t PRS : 3; + __IO uint32_t BUFPEN : 1; + __IO uint32_t CRG : 1; + __IO uint32_t CFG : 1; + __IO uint32_t UIE : 1; + __IO uint32_t UDE : 1; + __IO uint32_t MODE : 2; + __IO uint32_t ONESHOT : 1; + __IO uint32_t CSG : 1; + __IO uint32_t OCCS : 1; + __IO uint32_t URS : 1; + __IO uint32_t TDE : 1; + __IO uint32_t TIE : 1; + __IO uint32_t BIE : 1; + __IO uint32_t CIS : 2; + __IO uint32_t OCCE : 1; + __IO uint32_t TG : 1; + __IO uint32_t UG : 1; + __IO uint32_t BG : 1; + __IO uint32_t DIR : 1; +} stc_tim3_mode23_m23cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + __IO uint32_t CA1F : 1; + __IO uint32_t CA2F : 1; + __IO uint32_t CB0F : 1; + __IO uint32_t CB1F : 1; + __IO uint32_t CB2F : 1; + __IO uint32_t CA0E : 1; + __IO uint32_t CA1E : 1; + __IO uint32_t CA2E : 1; + __IO uint32_t CB0E : 1; + __IO uint32_t CB1E : 1; + __IO uint32_t CB2E : 1; + __IO uint32_t BIF : 1; + __IO uint32_t TIF : 1; +} stc_tim3_mode23_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + __IO uint32_t CA1F : 1; + __IO uint32_t CA2F : 1; + __IO uint32_t CB0F : 1; + __IO uint32_t CB1F : 1; + __IO uint32_t CB2F : 1; + __IO uint32_t CA0E : 1; + __IO uint32_t CA1E : 1; + __IO uint32_t CA2E : 1; + __IO uint32_t CB0E : 1; + __IO uint32_t CB1E : 1; + __IO uint32_t CB2E : 1; + __IO uint32_t BIF : 1; + __IO uint32_t TIF : 1; +} stc_tim3_mode23_iclr_field_t; + +typedef struct +{ + __IO uint32_t MMS : 3; + __IO uint32_t CCDS : 1; + __IO uint32_t MSM : 1; + __IO uint32_t TS : 3; + __IO uint32_t SMS : 3; + __IO uint32_t IA0S : 1; + __IO uint32_t IB0S : 1; +} stc_tim3_mode23_mscr_field_t; + +typedef struct +{ + __IO uint32_t OCMA0_FLTA0 : 3; + __IO uint32_t CCPA0 : 1; + __IO uint32_t OCMB0_FLTB0 : 3; + __IO uint32_t CCPB0 : 1; + __IO uint32_t OCMA1_FLTA1 : 3; + __IO uint32_t CCPA1 : 1; + __IO uint32_t OCMB1_FLTB1 : 3; + __IO uint32_t CCPB1 : 1; + __IO uint32_t OCMA2_FLTA2 : 3; + __IO uint32_t CCPA2 : 1; + __IO uint32_t OCMB2_FLTB2 : 3; + __IO uint32_t CCPB2 : 1; + __IO uint32_t FLTBK : 3; + __IO uint32_t BKP : 1; + __IO uint32_t FLTET : 3; + __IO uint32_t ETP : 1; +} stc_tim3_mode23_fltr_field_t; + +typedef struct +{ + __IO uint32_t UEVE : 1; + __IO uint32_t CMA0E : 1; + __IO uint32_t CMA1E : 1; + __IO uint32_t CMA2E : 1; + __IO uint32_t CMB0E : 1; + __IO uint32_t CMB1E : 1; + __IO uint32_t CMB2E : 1; + __IO uint32_t ADTE : 1; +} stc_tim3_mode23_adtr_field_t; + +typedef struct +{ + __IO uint32_t CFA_CRA_BKSA : 2; + __IO uint32_t CFB_CRB_BKSB : 2; + __IO uint32_t CSA : 1; + __IO uint32_t CSB : 1; + __IO uint32_t BUFEA : 1; + __IO uint32_t BUFEB : 1; + __IO uint32_t CIEA : 1; + __IO uint32_t CIEB : 1; + __IO uint32_t CDEA : 1; + __IO uint32_t CDEB : 1; + __IO uint32_t CISB : 2; + __IO uint32_t CCGA : 1; + __IO uint32_t CCGB : 1; +} stc_tim3_mode23_crch0_field_t; + +typedef struct +{ + __IO uint32_t CFA_CRA_BKSA : 2; + __IO uint32_t CFB_CRB_BKSB : 2; + __IO uint32_t CSA : 1; + __IO uint32_t CSB : 1; + __IO uint32_t BUFEA : 1; + __IO uint32_t BUFEB : 1; + __IO uint32_t CIEA : 1; + __IO uint32_t CIEB : 1; + __IO uint32_t CDEA : 1; + __IO uint32_t CDEB : 1; + __IO uint32_t CISB : 2; + __IO uint32_t CCGA : 1; + __IO uint32_t CCGB : 1; +} stc_tim3_mode23_crch1_field_t; + +typedef struct +{ + __IO uint32_t CFA_CRA_BKSA : 2; + __IO uint32_t CFB_CRB_BKSB : 2; + __IO uint32_t CSA : 1; + __IO uint32_t CSB : 1; + __IO uint32_t BUFEA : 1; + __IO uint32_t BUFEB : 1; + __IO uint32_t CIEA : 1; + __IO uint32_t CIEB : 1; + __IO uint32_t CDEA : 1; + __IO uint32_t CDEB : 1; + __IO uint32_t CISB : 2; + __IO uint32_t CCGA : 1; + __IO uint32_t CCGB : 1; +} stc_tim3_mode23_crch2_field_t; + +typedef struct +{ + __IO uint32_t DTR : 8; + __IO uint32_t BKSEL : 1; + __IO uint32_t DTEN : 1; + __IO uint32_t BKE : 1; + __IO uint32_t AOE : 1; + __IO uint32_t MOE : 1; + __IO uint32_t SAFEEN : 1; + __IO uint32_t VC0E : 1; + __IO uint32_t VC1E : 1; +} stc_tim3_mode23_dtr_field_t; + +typedef struct +{ + __IO uint32_t RCR : 8; +} stc_tim3_mode23_rcr_field_t; + +typedef struct +{ + __IO uint32_t ARRDM :16; +} stc_tim3_mode23_arrdm_field_t; + +typedef struct +{ + __IO uint32_t CCR0A :16; +} stc_tim3_mode23_ccr0a_field_t; + +typedef struct +{ + __IO uint32_t CCR0B :16; +} stc_tim3_mode23_ccr0b_field_t; + +typedef struct +{ + __IO uint32_t CCR1A :16; +} stc_tim3_mode23_ccr1a_field_t; + +typedef struct +{ + __IO uint32_t CCR1B :16; +} stc_tim3_mode23_ccr1b_field_t; + +typedef struct +{ + __IO uint32_t CCR2A :16; +} stc_tim3_mode23_ccr2a_field_t; + +typedef struct +{ + __IO uint32_t CCR2B :16; +} stc_tim3_mode23_ccr2b_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; +} stc_tim4_cnter_field_t; + +typedef struct +{ + __IO uint32_t PERA :16; +} stc_tim4_perar_field_t; + +typedef struct +{ + __IO uint32_t PERB :16; +} stc_tim4_perbr_field_t; + +typedef struct +{ + __IO uint32_t GCMA :16; +} stc_tim4_gcmar_field_t; + +typedef struct +{ + __IO uint32_t GCMB :16; +} stc_tim4_gcmbr_field_t; + +typedef struct +{ + __IO uint32_t GCMC :16; +} stc_tim4_gcmcr_field_t; + +typedef struct +{ + __IO uint32_t GCMD :16; +} stc_tim4_gcmdr_field_t; + +typedef struct +{ + __IO uint32_t SCMA :16; +} stc_tim4_scmar_field_t; + +typedef struct +{ + __IO uint32_t SCMB :16; +} stc_tim4_scmbr_field_t; + +typedef struct +{ + __IO uint32_t DTUA :16; +} stc_tim4_dtuar_field_t; + +typedef struct +{ + __IO uint32_t DTDA :16; +} stc_tim4_dtdar_field_t; + +typedef struct +{ + __IO uint32_t START : 1; + __IO uint32_t MODE : 3; + __IO uint32_t CKDIV : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t DIR : 1; + uint32_t RESERVED9 : 7; + __IO uint32_t ZMSKREV : 1; + __IO uint32_t ZMSKPOS : 1; + __IO uint32_t ZMSK : 2; +} stc_tim4_gconr_field_t; + +typedef struct +{ + __IO uint32_t INTENA : 1; + __IO uint32_t INTENB : 1; + __IO uint32_t INTENC : 1; + __IO uint32_t INTEND : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t INTENOVF : 1; + __IO uint32_t INTENUDF : 1; + __IO uint32_t INTENDE : 1; + uint32_t RESERVED9 : 5; + __IO uint32_t INTENSAML : 1; + __IO uint32_t INTENSAMH : 1; + __IO uint32_t INTENSAU : 1; + __IO uint32_t INTENSAD : 1; + __IO uint32_t INTENSBU : 1; + __IO uint32_t INTENSBD : 1; +} stc_tim4_iconr_field_t; + +typedef struct +{ + __IO uint32_t CAPCA : 1; + __IO uint32_t STACA : 1; + __IO uint32_t STPCA : 1; + __IO uint32_t STASTPSA : 1; + __IO uint32_t CMPCA : 2; + __IO uint32_t PERCA : 2; + __IO uint32_t OUTENA : 1; + __IO uint32_t DISSELA : 2; + __IO uint32_t DISVALA : 2; + uint32_t RESERVED13 : 3; + __IO uint32_t CAPCB : 1; + __IO uint32_t STACB : 1; + __IO uint32_t STPCB : 1; + __IO uint32_t STASTPSB : 1; + __IO uint32_t CMPCB : 2; + __IO uint32_t PERCB : 2; + __IO uint32_t OUTENB : 1; + __IO uint32_t DISSELB : 2; + __IO uint32_t DISVALB : 2; +} stc_tim4_pconr_field_t; + +typedef struct +{ + __IO uint32_t BENA : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t BENB : 1; + uint32_t RESERVED3 : 5; + __IO uint32_t BENP : 1; +} stc_tim4_bconr_field_t; + +typedef struct +{ + __IO uint32_t DTCEN : 1; + uint32_t RESERVED1 : 7; + __IO uint32_t SEPA : 1; +} stc_tim4_dconr_field_t; + +typedef struct +{ + __IO uint32_t NOFIENGA : 1; + __IO uint32_t NOFICKGA : 2; + uint32_t RESERVED3 : 1; + __IO uint32_t NOFIENGB : 1; + __IO uint32_t NOFICKGB : 2; + uint32_t RESERVED7 : 9; + __IO uint32_t NOFIENTA : 1; + __IO uint32_t NOFICKTA : 2; + uint32_t RESERVED19 : 1; + __IO uint32_t NOFIENTB : 1; + __IO uint32_t NOFICKTB : 2; + uint32_t RESERVED23 : 1; + __IO uint32_t NOFIENTC : 1; + __IO uint32_t NOFICKTC : 2; + uint32_t RESERVED27 : 1; + __IO uint32_t NOFIENTD : 1; + __IO uint32_t NOFICKTD : 2; +} stc_tim4_fconr_field_t; + +typedef struct +{ + __IO uint32_t GEPERIA : 1; + __IO uint32_t GEPERIB : 1; + __IO uint32_t GEPERIC : 1; + __IO uint32_t GEPERID : 1; + uint32_t RESERVED4 :12; + __IO uint32_t PCNTE : 2; + __IO uint32_t PCNTS : 3; +} stc_tim4_vperr_field_t; + +typedef struct +{ + __IO uint32_t CMAF : 1; + __IO uint32_t CMBF : 1; + __IO uint32_t CMCF : 1; + __IO uint32_t CMDF : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t OVFF : 1; + __IO uint32_t UDFF : 1; + __IO uint32_t DTEF : 1; + __IO uint32_t CMSAUF : 1; + __IO uint32_t CMSADF : 1; + __IO uint32_t CMSBUF : 1; + __IO uint32_t CMSBDF : 1; + uint32_t RESERVED13 : 8; + __IO uint32_t VPERNUM : 3; + uint32_t RESERVED24 : 7; + __IO uint32_t DIRF : 1; +} stc_tim4_stflr_field_t; + +typedef struct +{ + __IO uint32_t HSTA0 : 1; + __IO uint32_t HSTA1 : 1; + __IO uint32_t HSTA2 : 1; + __IO uint32_t HSTA3 : 1; + __IO uint32_t HSTA4 : 1; + __IO uint32_t HSTA5 : 1; + __IO uint32_t HSTA6 : 1; + __IO uint32_t HSTA7 : 1; + __IO uint32_t HSTA8 : 1; + __IO uint32_t HSTA9 : 1; + __IO uint32_t HSTA10 : 1; + __IO uint32_t HSTA11 : 1; + __IO uint32_t HSTA12 : 1; + __IO uint32_t HSTA13 : 1; + __IO uint32_t HSTA14 : 1; + __IO uint32_t HSTA15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t STARTS : 1; +} stc_tim4_hstar_field_t; + +typedef struct +{ + __IO uint32_t HSTP0 : 1; + __IO uint32_t HSTP1 : 1; + __IO uint32_t HSTP2 : 1; + __IO uint32_t HSTP3 : 1; + __IO uint32_t HSTP4 : 1; + __IO uint32_t HSTP5 : 1; + __IO uint32_t HSTP6 : 1; + __IO uint32_t HSTP7 : 1; + __IO uint32_t HSTP8 : 1; + __IO uint32_t HSTP9 : 1; + __IO uint32_t HSTP10 : 1; + __IO uint32_t HSTP11 : 1; + __IO uint32_t HSTP12 : 1; + __IO uint32_t HSTP13 : 1; + __IO uint32_t HSTP14 : 1; + __IO uint32_t HSTP15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t STOPS : 1; +} stc_tim4_hstpr_field_t; + +typedef struct +{ + __IO uint32_t HCEL0 : 1; + __IO uint32_t HCEL1 : 1; + __IO uint32_t HCEL2 : 1; + __IO uint32_t HCEL3 : 1; + __IO uint32_t HCEL4 : 1; + __IO uint32_t HCEL5 : 1; + __IO uint32_t HCEL6 : 1; + __IO uint32_t HCEL7 : 1; + __IO uint32_t HCEL8 : 1; + __IO uint32_t HCEL9 : 1; + __IO uint32_t HCEL10 : 1; + __IO uint32_t HCEL11 : 1; + __IO uint32_t HCEL12 : 1; + __IO uint32_t HCEL13 : 1; + __IO uint32_t HCEL14 : 1; + __IO uint32_t HCEL15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t STARTS : 1; +} stc_tim4_hcelr_field_t; + +typedef struct +{ + __IO uint32_t HCPA0 : 1; + __IO uint32_t HCPA1 : 1; + __IO uint32_t HCPA2 : 1; + __IO uint32_t HCPA3 : 1; + __IO uint32_t HCPA4 : 1; + __IO uint32_t HCPA5 : 1; + __IO uint32_t HCPA6 : 1; + __IO uint32_t HCPA7 : 1; + __IO uint32_t HCPA8 : 1; + __IO uint32_t HCPA9 : 1; + __IO uint32_t HCPA10 : 1; + __IO uint32_t HCPA11 : 1; + __IO uint32_t HCPA12 : 1; + __IO uint32_t HCPA13 : 1; + __IO uint32_t HCPA14 : 1; + __IO uint32_t HCPA15 : 1; +} stc_tim4_hcpar_field_t; + +typedef struct +{ + __IO uint32_t HCPB0 : 1; + __IO uint32_t HCPB1 : 1; + __IO uint32_t HCPB2 : 1; + __IO uint32_t HCPB3 : 1; + __IO uint32_t HCPB4 : 1; + __IO uint32_t HCPB5 : 1; + __IO uint32_t HCPB6 : 1; + __IO uint32_t HCPB7 : 1; + __IO uint32_t HCPB8 : 1; + __IO uint32_t HCPB9 : 1; + __IO uint32_t HCPB10 : 1; + __IO uint32_t HCPB11 : 1; + __IO uint32_t HCPB12 : 1; + __IO uint32_t HCPB13 : 1; + __IO uint32_t HCPB14 : 1; + __IO uint32_t HCPB15 : 1; +} stc_tim4_hcpbr_field_t; + +typedef struct +{ + __IO uint32_t HCUP0 : 1; + __IO uint32_t HCUP1 : 1; + __IO uint32_t HCUP2 : 1; + __IO uint32_t HCUP3 : 1; + __IO uint32_t HCUP4 : 1; + __IO uint32_t HCUP5 : 1; + __IO uint32_t HCUP6 : 1; + __IO uint32_t HCUP7 : 1; + __IO uint32_t HCUP8 : 1; + __IO uint32_t HCUP9 : 1; + __IO uint32_t HCUP10 : 1; + __IO uint32_t HCUP11 : 1; + __IO uint32_t HCUP12 : 1; + __IO uint32_t HCUP13 : 1; + __IO uint32_t HCUP14 : 1; + __IO uint32_t HCUP15 : 1; + __IO uint32_t HCUP16 : 1; + __IO uint32_t HCUP17 : 1; + __IO uint32_t HCUP18 : 1; + __IO uint32_t HCUP19 : 1; +} stc_tim4_hcupr_field_t; + +typedef struct +{ + __IO uint32_t HCDO0 : 1; + __IO uint32_t HCDO1 : 1; + __IO uint32_t HCDO2 : 1; + __IO uint32_t HCDO3 : 1; + __IO uint32_t HCDO4 : 1; + __IO uint32_t HCDO5 : 1; + __IO uint32_t HCDO6 : 1; + __IO uint32_t HCDO7 : 1; + __IO uint32_t HCDO8 : 1; + __IO uint32_t HCDO9 : 1; + __IO uint32_t HCDO10 : 1; + __IO uint32_t HCDO11 : 1; + __IO uint32_t HCDO12 : 1; + __IO uint32_t HCDO13 : 1; + __IO uint32_t HCDO14 : 1; + __IO uint32_t HCDO15 : 1; + __IO uint32_t HCDO16 : 1; + __IO uint32_t HCDO17 : 1; + __IO uint32_t HCDO18 : 1; + __IO uint32_t HCDO19 : 1; +} stc_tim4_hcdor_field_t; + +typedef struct +{ + __IO uint32_t CMAF : 1; + __IO uint32_t CMBF : 1; + __IO uint32_t CMCF : 1; + __IO uint32_t CMDF : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t OVFF : 1; + __IO uint32_t UDFF : 1; + __IO uint32_t DTEF : 1; + uint32_t RESERVED9 : 5; + __IO uint32_t SAMLF : 1; + __IO uint32_t SAMHF : 1; +} stc_tim4_ifr_field_t; + +typedef struct +{ + __IO uint32_t CMAC : 1; + __IO uint32_t CMBC : 1; + __IO uint32_t CMCC : 1; + __IO uint32_t CMDC : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t OVFC : 1; + __IO uint32_t UDFC : 1; + __IO uint32_t DTEC : 1; + uint32_t RESERVED9 : 5; + __IO uint32_t SAMLC : 1; + __IO uint32_t SAMHC : 1; +} stc_tim4_iclr_field_t; + +typedef struct +{ + __IO uint32_t CMAE : 1; + __IO uint32_t CMBE : 1; + __IO uint32_t CMCE : 1; + __IO uint32_t CMDE : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t OVFE : 1; + __IO uint32_t UDFE : 1; + __IO uint32_t DITENA : 1; + __IO uint32_t DITENB : 1; + __IO uint32_t DITENS : 1; + __IO uint32_t CMSAE : 1; + __IO uint32_t CMSBE : 1; + __IO uint32_t DMA_G_CMA : 1; + __IO uint32_t DMA_G_CMB : 1; + __IO uint32_t DMA_G_CMC : 1; + __IO uint32_t DMA_G_CMD : 1; + uint32_t RESERVED17 : 2; + __IO uint32_t DMA_G_OVF : 1; + __IO uint32_t DMA_G_UDF : 1; + __IO uint32_t DMA_S_CMA : 1; + __IO uint32_t DMA_S_CMB : 1; +} stc_tim4_cr_field_t; + +typedef struct +{ + __IO uint32_t FBRAKE : 1; + __IO uint32_t FSAME : 1; + __IO uint32_t BFILTS : 2; + __IO uint32_t BFILTEN : 1; + uint32_t RESERVED5 : 2; + __IO uint32_t SOFTBK : 1; + __IO uint32_t SML0 : 1; + __IO uint32_t SML1 : 1; + __IO uint32_t SML2 : 1; + __IO uint32_t SMH0 : 1; + __IO uint32_t SMH1 : 1; + __IO uint32_t SMH2 : 1; +} stc_tim4_aossr_field_t; + +typedef struct +{ + __IO uint32_t FBRAKE : 1; + __IO uint32_t FSAME : 1; +} stc_tim4_aoscl_field_t; + +typedef struct +{ + __IO uint32_t EN0 : 1; + __IO uint32_t EN1 : 1; + __IO uint32_t EN2 : 1; + __IO uint32_t EN3 : 1; + __IO uint32_t EN4 : 1; + __IO uint32_t EN5 : 1; + __IO uint32_t EN6 : 1; + __IO uint32_t EN7 : 1; + __IO uint32_t EN8 : 1; + __IO uint32_t EN9 : 1; + __IO uint32_t EN10 : 1; + __IO uint32_t EN11 : 1; + __IO uint32_t EN12 : 1; + __IO uint32_t EN13 : 1; + __IO uint32_t EN14 : 1; + __IO uint32_t EN15 : 1; +} stc_tim4_ptbks_field_t; + +typedef struct +{ + __IO uint32_t TRIGAS : 4; + __IO uint32_t TRIGBS : 4; + __IO uint32_t TRIGCS : 4; + __IO uint32_t TRIGDS : 4; +} stc_tim4_ttrig_field_t; + +typedef struct +{ + __IO uint32_t IAOS0S : 4; + __IO uint32_t IAOS1S : 4; + __IO uint32_t IAOS2S : 4; + __IO uint32_t IAOS3S : 4; +} stc_tim4_itrig_field_t; + +typedef struct +{ + __IO uint32_t POL0 : 1; + __IO uint32_t POL1 : 1; + __IO uint32_t POL2 : 1; + __IO uint32_t POL3 : 1; + __IO uint32_t POL4 : 1; + __IO uint32_t POL5 : 1; + __IO uint32_t POL6 : 1; + __IO uint32_t POL7 : 1; + __IO uint32_t POL8 : 1; + __IO uint32_t POL9 : 1; + __IO uint32_t POL10 : 1; + __IO uint32_t POL11 : 1; + __IO uint32_t POL12 : 1; + __IO uint32_t POL13 : 1; + __IO uint32_t POL14 : 1; + __IO uint32_t POL15 : 1; +} stc_tim4_ptbkp_field_t; + +typedef struct +{ + __IO uint32_t SSTA0 : 1; + __IO uint32_t SSTA1 : 1; + __IO uint32_t SSTA2 : 1; +} stc_tim4_sstar_field_t; + +typedef struct +{ + __IO uint32_t SSTP0 : 1; + __IO uint32_t SSTP1 : 1; + __IO uint32_t SSTP2 : 1; +} stc_tim4_sstpr_field_t; + +typedef struct +{ + __IO uint32_t SCLR0 : 1; + __IO uint32_t SCLR1 : 1; + __IO uint32_t SCLR2 : 1; +} stc_tim4_sclrr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; +} stc_tim5_cnter_field_t; + +typedef struct +{ + __IO uint32_t PERA :16; +} stc_tim5_perar_field_t; + +typedef struct +{ + __IO uint32_t PERB :16; +} stc_tim5_perbr_field_t; + +typedef struct +{ + __IO uint32_t GCMA :16; +} stc_tim5_gcmar_field_t; + +typedef struct +{ + __IO uint32_t GCMB :16; +} stc_tim5_gcmbr_field_t; + +typedef struct +{ + __IO uint32_t GCMC :16; +} stc_tim5_gcmcr_field_t; + +typedef struct +{ + __IO uint32_t GCMD :16; +} stc_tim5_gcmdr_field_t; + +typedef struct +{ + __IO uint32_t SCMA :16; +} stc_tim5_scmar_field_t; + +typedef struct +{ + __IO uint32_t SCMB :16; +} stc_tim5_scmbr_field_t; + +typedef struct +{ + __IO uint32_t DTUA :16; +} stc_tim5_dtuar_field_t; + +typedef struct +{ + __IO uint32_t DTDA :16; +} stc_tim5_dtdar_field_t; + +typedef struct +{ + __IO uint32_t START : 1; + __IO uint32_t MODE : 3; + __IO uint32_t CKDIV : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t DIR : 1; + uint32_t RESERVED9 : 7; + __IO uint32_t ZMSKREV : 1; + __IO uint32_t ZMSKPOS : 1; + __IO uint32_t ZMSK : 2; +} stc_tim5_gconr_field_t; + +typedef struct +{ + __IO uint32_t INTENA : 1; + __IO uint32_t INTENB : 1; + __IO uint32_t INTENC : 1; + __IO uint32_t INTEND : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t INTENOVF : 1; + __IO uint32_t INTENUDF : 1; + __IO uint32_t INTENDE : 1; + uint32_t RESERVED9 : 5; + __IO uint32_t INTENSAML : 1; + __IO uint32_t INTENSAMH : 1; + __IO uint32_t INTENSAU : 1; + __IO uint32_t INTENSAD : 1; + __IO uint32_t INTENSBU : 1; + __IO uint32_t INTENSBD : 1; +} stc_tim5_iconr_field_t; + +typedef struct +{ + __IO uint32_t CAPCA : 1; + __IO uint32_t STACA : 1; + __IO uint32_t STPCA : 1; + __IO uint32_t STASTPSA : 1; + __IO uint32_t CMPCA : 2; + __IO uint32_t PERCA : 2; + __IO uint32_t OUTENA : 1; + __IO uint32_t DISSELA : 2; + __IO uint32_t DISVALA : 2; + uint32_t RESERVED13 : 3; + __IO uint32_t CAPCB : 1; + __IO uint32_t STACB : 1; + __IO uint32_t STPCB : 1; + __IO uint32_t STASTPSB : 1; + __IO uint32_t CMPCB : 2; + __IO uint32_t PERCB : 2; + __IO uint32_t OUTENB : 1; + __IO uint32_t DISSELB : 2; + __IO uint32_t DISVALB : 2; +} stc_tim5_pconr_field_t; + +typedef struct +{ + __IO uint32_t BENA : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t BENB : 1; + uint32_t RESERVED3 : 5; + __IO uint32_t BENP : 1; +} stc_tim5_bconr_field_t; + +typedef struct +{ + __IO uint32_t DTCEN : 1; + uint32_t RESERVED1 : 7; + __IO uint32_t SEPA : 1; +} stc_tim5_dconr_field_t; + +typedef struct +{ + __IO uint32_t NOFIENGA : 1; + __IO uint32_t NOFICKGA : 2; + uint32_t RESERVED3 : 1; + __IO uint32_t NOFIENGB : 1; + __IO uint32_t NOFICKGB : 2; + uint32_t RESERVED7 : 9; + __IO uint32_t NOFIENTA : 1; + __IO uint32_t NOFICKTA : 2; + uint32_t RESERVED19 : 1; + __IO uint32_t NOFIENTB : 1; + __IO uint32_t NOFICKTB : 2; + uint32_t RESERVED23 : 1; + __IO uint32_t NOFIENTC : 1; + __IO uint32_t NOFICKTC : 2; + uint32_t RESERVED27 : 1; + __IO uint32_t NOFIENTD : 1; + __IO uint32_t NOFICKTD : 2; +} stc_tim5_fconr_field_t; + +typedef struct +{ + __IO uint32_t GEPERIA : 1; + __IO uint32_t GEPERIB : 1; + __IO uint32_t GEPERIC : 1; + __IO uint32_t GEPERID : 1; + uint32_t RESERVED4 :12; + __IO uint32_t PCNTE : 2; + __IO uint32_t PCNTS : 3; +} stc_tim5_vperr_field_t; + +typedef struct +{ + __IO uint32_t CMAF : 1; + __IO uint32_t CMBF : 1; + __IO uint32_t CMCF : 1; + __IO uint32_t CMDF : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t OVFF : 1; + __IO uint32_t UDFF : 1; + __IO uint32_t DTEF : 1; + __IO uint32_t CMSAUF : 1; + __IO uint32_t CMSADF : 1; + __IO uint32_t CMSBUF : 1; + __IO uint32_t CMSBDF : 1; + uint32_t RESERVED13 : 8; + __IO uint32_t VPERNUM : 3; + uint32_t RESERVED24 : 7; + __IO uint32_t DIRF : 1; +} stc_tim5_stflr_field_t; + +typedef struct +{ + __IO uint32_t HSTA0 : 1; + __IO uint32_t HSTA1 : 1; + __IO uint32_t HSTA2 : 1; + __IO uint32_t HSTA3 : 1; + __IO uint32_t HSTA4 : 1; + __IO uint32_t HSTA5 : 1; + __IO uint32_t HSTA6 : 1; + __IO uint32_t HSTA7 : 1; + __IO uint32_t HSTA8 : 1; + __IO uint32_t HSTA9 : 1; + __IO uint32_t HSTA10 : 1; + __IO uint32_t HSTA11 : 1; + __IO uint32_t HSTA12 : 1; + __IO uint32_t HSTA13 : 1; + __IO uint32_t HSTA14 : 1; + __IO uint32_t HSTA15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t STARTS : 1; +} stc_tim5_hstar_field_t; + +typedef struct +{ + __IO uint32_t HSTP0 : 1; + __IO uint32_t HSTP1 : 1; + __IO uint32_t HSTP2 : 1; + __IO uint32_t HSTP3 : 1; + __IO uint32_t HSTP4 : 1; + __IO uint32_t HSTP5 : 1; + __IO uint32_t HSTP6 : 1; + __IO uint32_t HSTP7 : 1; + __IO uint32_t HSTP8 : 1; + __IO uint32_t HSTP9 : 1; + __IO uint32_t HSTP10 : 1; + __IO uint32_t HSTP11 : 1; + __IO uint32_t HSTP12 : 1; + __IO uint32_t HSTP13 : 1; + __IO uint32_t HSTP14 : 1; + __IO uint32_t HSTP15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t STOPS : 1; +} stc_tim5_hstpr_field_t; + +typedef struct +{ + __IO uint32_t HCEL0 : 1; + __IO uint32_t HCEL1 : 1; + __IO uint32_t HCEL2 : 1; + __IO uint32_t HCEL3 : 1; + __IO uint32_t HCEL4 : 1; + __IO uint32_t HCEL5 : 1; + __IO uint32_t HCEL6 : 1; + __IO uint32_t HCEL7 : 1; + __IO uint32_t HCEL8 : 1; + __IO uint32_t HCEL9 : 1; + __IO uint32_t HCEL10 : 1; + __IO uint32_t HCEL11 : 1; + __IO uint32_t HCEL12 : 1; + __IO uint32_t HCEL13 : 1; + __IO uint32_t HCEL14 : 1; + __IO uint32_t HCEL15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t STARTS : 1; +} stc_tim5_hcelr_field_t; + +typedef struct +{ + __IO uint32_t HCPA0 : 1; + __IO uint32_t HCPA1 : 1; + __IO uint32_t HCPA2 : 1; + __IO uint32_t HCPA3 : 1; + __IO uint32_t HCPA4 : 1; + __IO uint32_t HCPA5 : 1; + __IO uint32_t HCPA6 : 1; + __IO uint32_t HCPA7 : 1; + __IO uint32_t HCPA8 : 1; + __IO uint32_t HCPA9 : 1; + __IO uint32_t HCPA10 : 1; + __IO uint32_t HCPA11 : 1; + __IO uint32_t HCPA12 : 1; + __IO uint32_t HCPA13 : 1; + __IO uint32_t HCPA14 : 1; + __IO uint32_t HCPA15 : 1; +} stc_tim5_hcpar_field_t; + +typedef struct +{ + __IO uint32_t HCPB0 : 1; + __IO uint32_t HCPB1 : 1; + __IO uint32_t HCPB2 : 1; + __IO uint32_t HCPB3 : 1; + __IO uint32_t HCPB4 : 1; + __IO uint32_t HCPB5 : 1; + __IO uint32_t HCPB6 : 1; + __IO uint32_t HCPB7 : 1; + __IO uint32_t HCPB8 : 1; + __IO uint32_t HCPB9 : 1; + __IO uint32_t HCPB10 : 1; + __IO uint32_t HCPB11 : 1; + __IO uint32_t HCPB12 : 1; + __IO uint32_t HCPB13 : 1; + __IO uint32_t HCPB14 : 1; + __IO uint32_t HCPB15 : 1; +} stc_tim5_hcpbr_field_t; + +typedef struct +{ + __IO uint32_t HCUP0 : 1; + __IO uint32_t HCUP1 : 1; + __IO uint32_t HCUP2 : 1; + __IO uint32_t HCUP3 : 1; + __IO uint32_t HCUP4 : 1; + __IO uint32_t HCUP5 : 1; + __IO uint32_t HCUP6 : 1; + __IO uint32_t HCUP7 : 1; + __IO uint32_t HCUP8 : 1; + __IO uint32_t HCUP9 : 1; + __IO uint32_t HCUP10 : 1; + __IO uint32_t HCUP11 : 1; + __IO uint32_t HCUP12 : 1; + __IO uint32_t HCUP13 : 1; + __IO uint32_t HCUP14 : 1; + __IO uint32_t HCUP15 : 1; + __IO uint32_t HCUP16 : 1; + __IO uint32_t HCUP17 : 1; + __IO uint32_t HCUP18 : 1; + __IO uint32_t HCUP19 : 1; +} stc_tim5_hcupr_field_t; + +typedef struct +{ + __IO uint32_t HCDO0 : 1; + __IO uint32_t HCDO1 : 1; + __IO uint32_t HCDO2 : 1; + __IO uint32_t HCDO3 : 1; + __IO uint32_t HCDO4 : 1; + __IO uint32_t HCDO5 : 1; + __IO uint32_t HCDO6 : 1; + __IO uint32_t HCDO7 : 1; + __IO uint32_t HCDO8 : 1; + __IO uint32_t HCDO9 : 1; + __IO uint32_t HCDO10 : 1; + __IO uint32_t HCDO11 : 1; + __IO uint32_t HCDO12 : 1; + __IO uint32_t HCDO13 : 1; + __IO uint32_t HCDO14 : 1; + __IO uint32_t HCDO15 : 1; + __IO uint32_t HCDO16 : 1; + __IO uint32_t HCDO17 : 1; + __IO uint32_t HCDO18 : 1; + __IO uint32_t HCDO19 : 1; +} stc_tim5_hcdor_field_t; + +typedef struct +{ + __IO uint32_t CMAF : 1; + __IO uint32_t CMBF : 1; + __IO uint32_t CMCF : 1; + __IO uint32_t CMDF : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t OVFF : 1; + __IO uint32_t UDFF : 1; + __IO uint32_t DTEF : 1; + uint32_t RESERVED9 : 5; + __IO uint32_t SAMLF : 1; + __IO uint32_t SAMHF : 1; +} stc_tim5_ifr_field_t; + +typedef struct +{ + __IO uint32_t CMAC : 1; + __IO uint32_t CMBC : 1; + __IO uint32_t CMCC : 1; + __IO uint32_t CMDC : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t OVFC : 1; + __IO uint32_t UDFC : 1; + __IO uint32_t DTEC : 1; + uint32_t RESERVED9 : 5; + __IO uint32_t SAMLC : 1; + __IO uint32_t SAMHC : 1; +} stc_tim5_iclr_field_t; + +typedef struct +{ + __IO uint32_t CMAE : 1; + __IO uint32_t CMBE : 1; + __IO uint32_t CMCE : 1; + __IO uint32_t CMDE : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t OVFE : 1; + __IO uint32_t UDFE : 1; + __IO uint32_t DITENA : 1; + __IO uint32_t DITENB : 1; + __IO uint32_t DITENS : 1; + __IO uint32_t CMSAE : 1; + __IO uint32_t CMSBE : 1; + __IO uint32_t DMA_G_CMA : 1; + __IO uint32_t DMA_G_CMB : 1; + __IO uint32_t DMA_G_CMC : 1; + __IO uint32_t DMA_G_CMD : 1; + uint32_t RESERVED17 : 2; + __IO uint32_t DMA_G_OVF : 1; + __IO uint32_t DMA_G_UDF : 1; + __IO uint32_t DMA_S_CMA : 1; + __IO uint32_t DMA_S_CMB : 1; +} stc_tim5_cr_field_t; + +typedef struct +{ + __IO uint32_t FBRAKE : 1; + __IO uint32_t FSAME : 1; + __IO uint32_t BFILTS : 2; + __IO uint32_t BFILTEN : 1; + uint32_t RESERVED5 : 2; + __IO uint32_t SOFTBK : 1; + __IO uint32_t SML0 : 1; + __IO uint32_t SML1 : 1; + __IO uint32_t SML2 : 1; + __IO uint32_t SMH0 : 1; + __IO uint32_t SMH1 : 1; + __IO uint32_t SMH2 : 1; +} stc_tim5_aossr_field_t; + +typedef struct +{ + __IO uint32_t FBRAKE : 1; + __IO uint32_t FSAME : 1; +} stc_tim5_aoscl_field_t; + +typedef struct +{ + __IO uint32_t EN0 : 1; + __IO uint32_t EN1 : 1; + __IO uint32_t EN2 : 1; + __IO uint32_t EN3 : 1; + __IO uint32_t EN4 : 1; + __IO uint32_t EN5 : 1; + __IO uint32_t EN6 : 1; + __IO uint32_t EN7 : 1; + __IO uint32_t EN8 : 1; + __IO uint32_t EN9 : 1; + __IO uint32_t EN10 : 1; + __IO uint32_t EN11 : 1; + __IO uint32_t EN12 : 1; + __IO uint32_t EN13 : 1; + __IO uint32_t EN14 : 1; + __IO uint32_t EN15 : 1; +} stc_tim5_ptbks_field_t; + +typedef struct +{ + __IO uint32_t TRIGAS : 4; + __IO uint32_t TRIGBS : 4; + __IO uint32_t TRIGCS : 4; + __IO uint32_t TRIGDS : 4; +} stc_tim5_ttrig_field_t; + +typedef struct +{ + __IO uint32_t IAOS0S : 4; + __IO uint32_t IAOS1S : 4; + __IO uint32_t IAOS2S : 4; + __IO uint32_t IAOS3S : 4; +} stc_tim5_itrig_field_t; + +typedef struct +{ + __IO uint32_t POL0 : 1; + __IO uint32_t POL1 : 1; + __IO uint32_t POL2 : 1; + __IO uint32_t POL3 : 1; + __IO uint32_t POL4 : 1; + __IO uint32_t POL5 : 1; + __IO uint32_t POL6 : 1; + __IO uint32_t POL7 : 1; + __IO uint32_t POL8 : 1; + __IO uint32_t POL9 : 1; + __IO uint32_t POL10 : 1; + __IO uint32_t POL11 : 1; + __IO uint32_t POL12 : 1; + __IO uint32_t POL13 : 1; + __IO uint32_t POL14 : 1; + __IO uint32_t POL15 : 1; +} stc_tim5_ptbkp_field_t; + +typedef struct +{ + __IO uint32_t SSTA0 : 1; + __IO uint32_t SSTA1 : 1; + __IO uint32_t SSTA2 : 1; +} stc_tim5_sstar_field_t; + +typedef struct +{ + __IO uint32_t SSTP0 : 1; + __IO uint32_t SSTP1 : 1; + __IO uint32_t SSTP2 : 1; +} stc_tim5_sstpr_field_t; + +typedef struct +{ + __IO uint32_t SCLR0 : 1; + __IO uint32_t SCLR1 : 1; + __IO uint32_t SCLR2 : 1; +} stc_tim5_sclrr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; +} stc_tim6_cnter_field_t; + +typedef struct +{ + __IO uint32_t PERA :16; +} stc_tim6_perar_field_t; + +typedef struct +{ + __IO uint32_t PERB :16; +} stc_tim6_perbr_field_t; + +typedef struct +{ + __IO uint32_t GCMA :16; +} stc_tim6_gcmar_field_t; + +typedef struct +{ + __IO uint32_t GCMB :16; +} stc_tim6_gcmbr_field_t; + +typedef struct +{ + __IO uint32_t GCMC :16; +} stc_tim6_gcmcr_field_t; + +typedef struct +{ + __IO uint32_t GCMD :16; +} stc_tim6_gcmdr_field_t; + +typedef struct +{ + __IO uint32_t SCMA :16; +} stc_tim6_scmar_field_t; + +typedef struct +{ + __IO uint32_t SCMB :16; +} stc_tim6_scmbr_field_t; + +typedef struct +{ + __IO uint32_t DTUA :16; +} stc_tim6_dtuar_field_t; + +typedef struct +{ + __IO uint32_t DTDA :16; +} stc_tim6_dtdar_field_t; + +typedef struct +{ + __IO uint32_t START : 1; + __IO uint32_t MODE : 3; + __IO uint32_t CKDIV : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t DIR : 1; + uint32_t RESERVED9 : 7; + __IO uint32_t ZMSKREV : 1; + __IO uint32_t ZMSKPOS : 1; + __IO uint32_t ZMSK : 2; +} stc_tim6_gconr_field_t; + +typedef struct +{ + __IO uint32_t INTENA : 1; + __IO uint32_t INTENB : 1; + __IO uint32_t INTENC : 1; + __IO uint32_t INTEND : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t INTENOVF : 1; + __IO uint32_t INTENUDF : 1; + __IO uint32_t INTENDE : 1; + uint32_t RESERVED9 : 5; + __IO uint32_t INTENSAML : 1; + __IO uint32_t INTENSAMH : 1; + __IO uint32_t INTENSAU : 1; + __IO uint32_t INTENSAD : 1; + __IO uint32_t INTENSBU : 1; + __IO uint32_t INTENSBD : 1; +} stc_tim6_iconr_field_t; + +typedef struct +{ + __IO uint32_t CAPCA : 1; + __IO uint32_t STACA : 1; + __IO uint32_t STPCA : 1; + __IO uint32_t STASTPSA : 1; + __IO uint32_t CMPCA : 2; + __IO uint32_t PERCA : 2; + __IO uint32_t OUTENA : 1; + __IO uint32_t DISSELA : 2; + __IO uint32_t DISVALA : 2; + uint32_t RESERVED13 : 3; + __IO uint32_t CAPCB : 1; + __IO uint32_t STACB : 1; + __IO uint32_t STPCB : 1; + __IO uint32_t STASTPSB : 1; + __IO uint32_t CMPCB : 2; + __IO uint32_t PERCB : 2; + __IO uint32_t OUTENB : 1; + __IO uint32_t DISSELB : 2; + __IO uint32_t DISVALB : 2; +} stc_tim6_pconr_field_t; + +typedef struct +{ + __IO uint32_t BENA : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t BENB : 1; + uint32_t RESERVED3 : 5; + __IO uint32_t BENP : 1; +} stc_tim6_bconr_field_t; + +typedef struct +{ + __IO uint32_t DTCEN : 1; + uint32_t RESERVED1 : 7; + __IO uint32_t SEPA : 1; +} stc_tim6_dconr_field_t; + +typedef struct +{ + __IO uint32_t NOFIENGA : 1; + __IO uint32_t NOFICKGA : 2; + uint32_t RESERVED3 : 1; + __IO uint32_t NOFIENGB : 1; + __IO uint32_t NOFICKGB : 2; + uint32_t RESERVED7 : 9; + __IO uint32_t NOFIENTA : 1; + __IO uint32_t NOFICKTA : 2; + uint32_t RESERVED19 : 1; + __IO uint32_t NOFIENTB : 1; + __IO uint32_t NOFICKTB : 2; + uint32_t RESERVED23 : 1; + __IO uint32_t NOFIENTC : 1; + __IO uint32_t NOFICKTC : 2; + uint32_t RESERVED27 : 1; + __IO uint32_t NOFIENTD : 1; + __IO uint32_t NOFICKTD : 2; +} stc_tim6_fconr_field_t; + +typedef struct +{ + __IO uint32_t GEPERIA : 1; + __IO uint32_t GEPERIB : 1; + __IO uint32_t GEPERIC : 1; + __IO uint32_t GEPERID : 1; + uint32_t RESERVED4 :12; + __IO uint32_t PCNTE : 2; + __IO uint32_t PCNTS : 3; +} stc_tim6_vperr_field_t; + +typedef struct +{ + __IO uint32_t CMAF : 1; + __IO uint32_t CMBF : 1; + __IO uint32_t CMCF : 1; + __IO uint32_t CMDF : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t OVFF : 1; + __IO uint32_t UDFF : 1; + __IO uint32_t DTEF : 1; + __IO uint32_t CMSAUF : 1; + __IO uint32_t CMSADF : 1; + __IO uint32_t CMSBUF : 1; + __IO uint32_t CMSBDF : 1; + uint32_t RESERVED13 : 8; + __IO uint32_t VPERNUM : 3; + uint32_t RESERVED24 : 7; + __IO uint32_t DIRF : 1; +} stc_tim6_stflr_field_t; + +typedef struct +{ + __IO uint32_t HSTA0 : 1; + __IO uint32_t HSTA1 : 1; + __IO uint32_t HSTA2 : 1; + __IO uint32_t HSTA3 : 1; + __IO uint32_t HSTA4 : 1; + __IO uint32_t HSTA5 : 1; + __IO uint32_t HSTA6 : 1; + __IO uint32_t HSTA7 : 1; + __IO uint32_t HSTA8 : 1; + __IO uint32_t HSTA9 : 1; + __IO uint32_t HSTA10 : 1; + __IO uint32_t HSTA11 : 1; + __IO uint32_t HSTA12 : 1; + __IO uint32_t HSTA13 : 1; + __IO uint32_t HSTA14 : 1; + __IO uint32_t HSTA15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t STARTS : 1; +} stc_tim6_hstar_field_t; + +typedef struct +{ + __IO uint32_t HSTP0 : 1; + __IO uint32_t HSTP1 : 1; + __IO uint32_t HSTP2 : 1; + __IO uint32_t HSTP3 : 1; + __IO uint32_t HSTP4 : 1; + __IO uint32_t HSTP5 : 1; + __IO uint32_t HSTP6 : 1; + __IO uint32_t HSTP7 : 1; + __IO uint32_t HSTP8 : 1; + __IO uint32_t HSTP9 : 1; + __IO uint32_t HSTP10 : 1; + __IO uint32_t HSTP11 : 1; + __IO uint32_t HSTP12 : 1; + __IO uint32_t HSTP13 : 1; + __IO uint32_t HSTP14 : 1; + __IO uint32_t HSTP15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t STOPS : 1; +} stc_tim6_hstpr_field_t; + +typedef struct +{ + __IO uint32_t HCEL0 : 1; + __IO uint32_t HCEL1 : 1; + __IO uint32_t HCEL2 : 1; + __IO uint32_t HCEL3 : 1; + __IO uint32_t HCEL4 : 1; + __IO uint32_t HCEL5 : 1; + __IO uint32_t HCEL6 : 1; + __IO uint32_t HCEL7 : 1; + __IO uint32_t HCEL8 : 1; + __IO uint32_t HCEL9 : 1; + __IO uint32_t HCEL10 : 1; + __IO uint32_t HCEL11 : 1; + __IO uint32_t HCEL12 : 1; + __IO uint32_t HCEL13 : 1; + __IO uint32_t HCEL14 : 1; + __IO uint32_t HCEL15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t STARTS : 1; +} stc_tim6_hcelr_field_t; + +typedef struct +{ + __IO uint32_t HCPA0 : 1; + __IO uint32_t HCPA1 : 1; + __IO uint32_t HCPA2 : 1; + __IO uint32_t HCPA3 : 1; + __IO uint32_t HCPA4 : 1; + __IO uint32_t HCPA5 : 1; + __IO uint32_t HCPA6 : 1; + __IO uint32_t HCPA7 : 1; + __IO uint32_t HCPA8 : 1; + __IO uint32_t HCPA9 : 1; + __IO uint32_t HCPA10 : 1; + __IO uint32_t HCPA11 : 1; + __IO uint32_t HCPA12 : 1; + __IO uint32_t HCPA13 : 1; + __IO uint32_t HCPA14 : 1; + __IO uint32_t HCPA15 : 1; +} stc_tim6_hcpar_field_t; + +typedef struct +{ + __IO uint32_t HCPB0 : 1; + __IO uint32_t HCPB1 : 1; + __IO uint32_t HCPB2 : 1; + __IO uint32_t HCPB3 : 1; + __IO uint32_t HCPB4 : 1; + __IO uint32_t HCPB5 : 1; + __IO uint32_t HCPB6 : 1; + __IO uint32_t HCPB7 : 1; + __IO uint32_t HCPB8 : 1; + __IO uint32_t HCPB9 : 1; + __IO uint32_t HCPB10 : 1; + __IO uint32_t HCPB11 : 1; + __IO uint32_t HCPB12 : 1; + __IO uint32_t HCPB13 : 1; + __IO uint32_t HCPB14 : 1; + __IO uint32_t HCPB15 : 1; +} stc_tim6_hcpbr_field_t; + +typedef struct +{ + __IO uint32_t HCUP0 : 1; + __IO uint32_t HCUP1 : 1; + __IO uint32_t HCUP2 : 1; + __IO uint32_t HCUP3 : 1; + __IO uint32_t HCUP4 : 1; + __IO uint32_t HCUP5 : 1; + __IO uint32_t HCUP6 : 1; + __IO uint32_t HCUP7 : 1; + __IO uint32_t HCUP8 : 1; + __IO uint32_t HCUP9 : 1; + __IO uint32_t HCUP10 : 1; + __IO uint32_t HCUP11 : 1; + __IO uint32_t HCUP12 : 1; + __IO uint32_t HCUP13 : 1; + __IO uint32_t HCUP14 : 1; + __IO uint32_t HCUP15 : 1; + __IO uint32_t HCUP16 : 1; + __IO uint32_t HCUP17 : 1; + __IO uint32_t HCUP18 : 1; + __IO uint32_t HCUP19 : 1; +} stc_tim6_hcupr_field_t; + +typedef struct +{ + __IO uint32_t HCDO0 : 1; + __IO uint32_t HCDO1 : 1; + __IO uint32_t HCDO2 : 1; + __IO uint32_t HCDO3 : 1; + __IO uint32_t HCDO4 : 1; + __IO uint32_t HCDO5 : 1; + __IO uint32_t HCDO6 : 1; + __IO uint32_t HCDO7 : 1; + __IO uint32_t HCDO8 : 1; + __IO uint32_t HCDO9 : 1; + __IO uint32_t HCDO10 : 1; + __IO uint32_t HCDO11 : 1; + __IO uint32_t HCDO12 : 1; + __IO uint32_t HCDO13 : 1; + __IO uint32_t HCDO14 : 1; + __IO uint32_t HCDO15 : 1; + __IO uint32_t HCDO16 : 1; + __IO uint32_t HCDO17 : 1; + __IO uint32_t HCDO18 : 1; + __IO uint32_t HCDO19 : 1; +} stc_tim6_hcdor_field_t; + +typedef struct +{ + __IO uint32_t CMAF : 1; + __IO uint32_t CMBF : 1; + __IO uint32_t CMCF : 1; + __IO uint32_t CMDF : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t OVFF : 1; + __IO uint32_t UDFF : 1; + __IO uint32_t DTEF : 1; + uint32_t RESERVED9 : 5; + __IO uint32_t SAMLF : 1; + __IO uint32_t SAMHF : 1; +} stc_tim6_ifr_field_t; + +typedef struct +{ + __IO uint32_t CMAC : 1; + __IO uint32_t CMBC : 1; + __IO uint32_t CMCC : 1; + __IO uint32_t CMDC : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t OVFC : 1; + __IO uint32_t UDFC : 1; + __IO uint32_t DTEC : 1; + uint32_t RESERVED9 : 5; + __IO uint32_t SAMLC : 1; + __IO uint32_t SAMHC : 1; +} stc_tim6_iclr_field_t; + +typedef struct +{ + __IO uint32_t CMAE : 1; + __IO uint32_t CMBE : 1; + __IO uint32_t CMCE : 1; + __IO uint32_t CMDE : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t OVFE : 1; + __IO uint32_t UDFE : 1; + __IO uint32_t DITENA : 1; + __IO uint32_t DITENB : 1; + __IO uint32_t DITENS : 1; + __IO uint32_t CMSAE : 1; + __IO uint32_t CMSBE : 1; + __IO uint32_t DMA_G_CMA : 1; + __IO uint32_t DMA_G_CMB : 1; + __IO uint32_t DMA_G_CMC : 1; + __IO uint32_t DMA_G_CMD : 1; + uint32_t RESERVED17 : 2; + __IO uint32_t DMA_G_OVF : 1; + __IO uint32_t DMA_G_UDF : 1; + __IO uint32_t DMA_S_CMA : 1; + __IO uint32_t DMA_S_CMB : 1; +} stc_tim6_cr_field_t; + +typedef struct +{ + __IO uint32_t FBRAKE : 1; + __IO uint32_t FSAME : 1; + __IO uint32_t BFILTS : 2; + __IO uint32_t BFILTEN : 1; + uint32_t RESERVED5 : 2; + __IO uint32_t SOFTBK : 1; + __IO uint32_t SML0 : 1; + __IO uint32_t SML1 : 1; + __IO uint32_t SML2 : 1; + __IO uint32_t SMH0 : 1; + __IO uint32_t SMH1 : 1; + __IO uint32_t SMH2 : 1; +} stc_tim6_aossr_field_t; + +typedef struct +{ + __IO uint32_t FBRAKE : 1; + __IO uint32_t FSAME : 1; +} stc_tim6_aoscl_field_t; + +typedef struct +{ + __IO uint32_t EN0 : 1; + __IO uint32_t EN1 : 1; + __IO uint32_t EN2 : 1; + __IO uint32_t EN3 : 1; + __IO uint32_t EN4 : 1; + __IO uint32_t EN5 : 1; + __IO uint32_t EN6 : 1; + __IO uint32_t EN7 : 1; + __IO uint32_t EN8 : 1; + __IO uint32_t EN9 : 1; + __IO uint32_t EN10 : 1; + __IO uint32_t EN11 : 1; + __IO uint32_t EN12 : 1; + __IO uint32_t EN13 : 1; + __IO uint32_t EN14 : 1; + __IO uint32_t EN15 : 1; +} stc_tim6_ptbks_field_t; + +typedef struct +{ + __IO uint32_t TRIGAS : 4; + __IO uint32_t TRIGBS : 4; + __IO uint32_t TRIGCS : 4; + __IO uint32_t TRIGDS : 4; +} stc_tim6_ttrig_field_t; + +typedef struct +{ + __IO uint32_t IAOS0S : 4; + __IO uint32_t IAOS1S : 4; + __IO uint32_t IAOS2S : 4; + __IO uint32_t IAOS3S : 4; +} stc_tim6_itrig_field_t; + +typedef struct +{ + __IO uint32_t POL0 : 1; + __IO uint32_t POL1 : 1; + __IO uint32_t POL2 : 1; + __IO uint32_t POL3 : 1; + __IO uint32_t POL4 : 1; + __IO uint32_t POL5 : 1; + __IO uint32_t POL6 : 1; + __IO uint32_t POL7 : 1; + __IO uint32_t POL8 : 1; + __IO uint32_t POL9 : 1; + __IO uint32_t POL10 : 1; + __IO uint32_t POL11 : 1; + __IO uint32_t POL12 : 1; + __IO uint32_t POL13 : 1; + __IO uint32_t POL14 : 1; + __IO uint32_t POL15 : 1; +} stc_tim6_ptbkp_field_t; + +typedef struct +{ + __IO uint32_t SSTA0 : 1; + __IO uint32_t SSTA1 : 1; + __IO uint32_t SSTA2 : 1; +} stc_tim6_sstar_field_t; + +typedef struct +{ + __IO uint32_t SSTP0 : 1; + __IO uint32_t SSTP1 : 1; + __IO uint32_t SSTP2 : 1; +} stc_tim6_sstpr_field_t; + +typedef struct +{ + __IO uint32_t SCLR0 : 1; + __IO uint32_t SCLR1 : 1; + __IO uint32_t SCLR2 : 1; +} stc_tim6_sclrr_field_t; + +typedef struct +{ + __IO uint32_t DATA : 8; + __IO uint32_t DATA8 : 1; +} stc_uart_sbuf_field_t; + +typedef struct +{ + __IO uint32_t RCIE : 1; + __IO uint32_t TCIE : 1; + __IO uint32_t B8CONT : 2; + __IO uint32_t REN : 1; + __IO uint32_t ADRDET : 1; + __IO uint32_t SM : 2; + __IO uint32_t TXEIE : 1; + __IO uint32_t OVER : 1; + uint32_t RESERVED10 : 3; + __IO uint32_t PEIE : 1; + __IO uint32_t STOPBIT : 2; + __IO uint32_t DMARXEN : 1; + __IO uint32_t DMATXEN : 1; + __IO uint32_t RTSEN : 1; + __IO uint32_t CTSEN : 1; + __IO uint32_t CTSIE : 1; + __IO uint32_t FEIE : 1; +} stc_uart_scon_field_t; + +typedef struct +{ + __IO uint32_t SADDR : 8; +} stc_uart_saddr_field_t; + +typedef struct +{ + __IO uint32_t SADEN : 8; +} stc_uart_saden_field_t; + +typedef struct +{ + __IO uint32_t RC : 1; + __IO uint32_t TC : 1; + __IO uint32_t FE : 1; + __IO uint32_t TXE : 1; + __IO uint32_t PE : 1; + __IO uint32_t CTSIF : 1; + __IO uint32_t CTS : 1; +} stc_uart_isr_field_t; + +typedef struct +{ + __IO uint32_t RCCF : 1; + __IO uint32_t TCCF : 1; + __IO uint32_t FECF : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t PECF : 1; + __IO uint32_t CTSIFCF : 1; +} stc_uart_icr_field_t; + +typedef struct +{ + __IO uint32_t SCNT :16; +} stc_uart_scnt_field_t; + +typedef struct +{ + __IO uint32_t DIV : 6; + __IO uint32_t DIV_EN : 1; + __IO uint32_t REF2P5_SEL : 1; + __IO uint32_t VC0_BIAS_SEL : 2; + __IO uint32_t VC0_HYS_SEL : 2; + __IO uint32_t VC1_BIAS_SEL : 2; + __IO uint32_t VC1_HYS_SEL : 2; +} stc_vc_cr_field_t; + +typedef struct +{ + __IO uint32_t P_SEL : 4; + __IO uint32_t N_SEL : 4; + __IO uint32_t FLTEN : 1; + __IO uint32_t DEBOUNCE_TIME : 3; + __IO uint32_t FALLING : 1; + __IO uint32_t RISING : 1; + __IO uint32_t LEVEL : 1; + __IO uint32_t IE : 1; + __IO uint32_t EN : 1; +} stc_vc_vc0_cr_field_t; + +typedef struct +{ + __IO uint32_t P_SEL : 4; + __IO uint32_t N_SEL : 4; + __IO uint32_t FLTEN : 1; + __IO uint32_t DEBOUNCE_TIME : 3; + __IO uint32_t FALLING : 1; + __IO uint32_t RISING : 1; + __IO uint32_t LEVEL : 1; + __IO uint32_t IE : 1; + __IO uint32_t EN : 1; +} stc_vc_vc1_cr_field_t; + +typedef struct +{ + __IO uint32_t INV_TIMER : 1; + __IO uint32_t TIM0RCLR : 1; + __IO uint32_t TIM1RCLR : 1; + __IO uint32_t TIM2RCLR : 1; + __IO uint32_t TIM3RCLR : 1; + __IO uint32_t TIMBK : 1; + uint32_t RESERVED6 : 3; + __IO uint32_t INV_TIM4 : 1; + __IO uint32_t TIM4 : 1; + __IO uint32_t INV_TIM5 : 1; + __IO uint32_t TIM5 : 1; + __IO uint32_t INV_TIM6 : 1; + __IO uint32_t TIM6 : 1; + __IO uint32_t BRAKE : 1; +} stc_vc_vc0_out_cfg_field_t; + +typedef struct +{ + __IO uint32_t INV_TIMER : 1; + __IO uint32_t TIM0RCLR : 1; + __IO uint32_t TIM1RCLR : 1; + __IO uint32_t TIM2RCLR : 1; + __IO uint32_t TIM3RCLR : 1; + __IO uint32_t TIMBK : 1; + uint32_t RESERVED6 : 3; + __IO uint32_t INV_TIM4 : 1; + __IO uint32_t TIM4 : 1; + __IO uint32_t INV_TIM5 : 1; + __IO uint32_t TIM5 : 1; + __IO uint32_t INV_TIM6 : 1; + __IO uint32_t TIM6 : 1; + __IO uint32_t BRAKE : 1; +} stc_vc_vc1_out_cfg_field_t; + +typedef struct +{ + __IO uint32_t VC0_INTF : 1; + __IO uint32_t VC1_INTF : 1; + __IO uint32_t VC0_FILTER : 1; + __IO uint32_t VC1_FILTER : 1; +} stc_vc_ifr_field_t; + +typedef struct +{ + __IO uint32_t RST : 8; +} stc_wdt_rst_field_t; + +typedef struct +{ + __IO uint32_t WOV : 4; + __IO uint32_t WDTR : 1; + __IO uint32_t WINT_EN : 1; + uint32_t RESERVED6 : 1; + __IO uint32_t WDINT : 1; + __IO uint32_t WCNTL : 8; +} stc_wdt_con_field_t; + + +typedef struct +{ + uint8_t RESERVED0[4]; + union + { + __IO uint32_t CR0; + stc_adc_cr0_field_t CR0_f; + }; + union + { + __IO uint32_t CR1; + stc_adc_cr1_field_t CR1_f; + }; + uint8_t RESERVED2[52]; + union + { + __IO uint32_t SQR0; + stc_adc_sqr0_field_t SQR0_f; + }; + union + { + __IO uint32_t SQR1; + stc_adc_sqr1_field_t SQR1_f; + }; + union + { + __IO uint32_t SQR2; + stc_adc_sqr2_field_t SQR2_f; + }; + union + { + __IO uint32_t JQR; + stc_adc_jqr_field_t JQR_f; + }; + union + { + __IO uint32_t SQRRESULT0; + stc_adc_sqrresult0_field_t SQRRESULT0_f; + }; + union + { + __IO uint32_t SQRRESULT1; + stc_adc_sqrresult1_field_t SQRRESULT1_f; + }; + union + { + __IO uint32_t SQRRESULT2; + stc_adc_sqrresult2_field_t SQRRESULT2_f; + }; + union + { + __IO uint32_t SQRRESULT3; + stc_adc_sqrresult3_field_t SQRRESULT3_f; + }; + union + { + __IO uint32_t SQRRESULT4; + stc_adc_sqrresult4_field_t SQRRESULT4_f; + }; + union + { + __IO uint32_t SQRRESULT5; + stc_adc_sqrresult5_field_t SQRRESULT5_f; + }; + union + { + __IO uint32_t SQRRESULT6; + stc_adc_sqrresult6_field_t SQRRESULT6_f; + }; + union + { + __IO uint32_t SQRRESULT7; + stc_adc_sqrresult7_field_t SQRRESULT7_f; + }; + union + { + __IO uint32_t SQRRESULT8; + stc_adc_sqrresult8_field_t SQRRESULT8_f; + }; + union + { + __IO uint32_t SQRRESULT9; + stc_adc_sqrresult9_field_t SQRRESULT9_f; + }; + union + { + __IO uint32_t SQRRESULT10; + stc_adc_sqrresult10_field_t SQRRESULT10_f; + }; + union + { + __IO uint32_t SQRRESULT11; + stc_adc_sqrresult11_field_t SQRRESULT11_f; + }; + union + { + __IO uint32_t SQRRESULT12; + stc_adc_sqrresult12_field_t SQRRESULT12_f; + }; + union + { + __IO uint32_t SQR_RESULT13; + stc_adc_sqr_result13_field_t SQR_RESULT13_f; + }; + union + { + __IO uint32_t SQRRESULT14; + stc_adc_sqrresult14_field_t SQRRESULT14_f; + }; + union + { + __IO uint32_t SQRRESULT15; + stc_adc_sqrresult15_field_t SQRRESULT15_f; + }; + union + { + __IO uint32_t JQRRESULT0; + stc_adc_jqrresult0_field_t JQRRESULT0_f; + }; + union + { + __IO uint32_t JQRRESULT1; + stc_adc_jqrresult1_field_t JQRRESULT1_f; + }; + union + { + __IO uint32_t JQRRESULT2; + stc_adc_jqrresult2_field_t JQRRESULT2_f; + }; + union + { + __IO uint32_t JQRRESULT3; + stc_adc_jqrresult3_field_t JQRRESULT3_f; + }; + union + { + __IO uint32_t RESULT; + stc_adc_result_field_t RESULT_f; + }; + union + { + __IO uint32_t RESULTACC; + stc_adc_resultacc_field_t RESULTACC_f; + }; + union + { + __IO uint32_t HT; + stc_adc_ht_field_t HT_f; + }; + union + { + __IO uint32_t LT; + stc_adc_lt_field_t LT_f; + }; + union + { + __IO uint32_t IFR; + stc_adc_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICR; + stc_adc_icr_field_t ICR_f; + }; + union + { + __IO uint32_t EXTTRIGGER0; + stc_adc_exttrigger0_field_t EXTTRIGGER0_f; + }; + union + { + __IO uint32_t EXTTRIGGER1; + stc_adc_exttrigger1_field_t EXTTRIGGER1_f; + }; + union + { + __IO uint32_t SGLSTART; + stc_adc_sglstart_field_t SGLSTART_f; + }; + union + { + __IO uint32_t SQRSTART; + stc_adc_sqrstart_field_t SQRSTART_f; + }; + union + { + __IO uint32_t JQRSTART; + stc_adc_jqrstart_field_t JQRSTART_f; + }; +}M0P_ADC_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_aes_cr_field_t CR_f; + }; + uint8_t RESERVED1[12]; + union + { + __IO uint32_t DATA0; + stc_aes_data0_field_t DATA0_f; + }; + union + { + __IO uint32_t DATA1; + stc_aes_data1_field_t DATA1_f; + }; + union + { + __IO uint32_t DATA2; + stc_aes_data2_field_t DATA2_f; + }; + union + { + __IO uint32_t DATA3; + stc_aes_data3_field_t DATA3_f; + }; + union + { + __IO uint32_t KEY0; + stc_aes_key0_field_t KEY0_f; + }; + union + { + __IO uint32_t KEY1; + stc_aes_key1_field_t KEY1_f; + }; + union + { + __IO uint32_t KEY2; + stc_aes_key2_field_t KEY2_f; + }; + union + { + __IO uint32_t KEY3; + stc_aes_key3_field_t KEY3_f; + }; +}M0P_AES_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_bgr_cr_field_t CR_f; + }; +}M0P_BGR_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_clk_trim_cr_field_t CR_f; + }; + union + { + __IO uint32_t REFCON; + stc_clk_trim_refcon_field_t REFCON_f; + }; + union + { + __IO uint32_t REFCNT; + stc_clk_trim_refcnt_field_t REFCNT_f; + }; + union + { + __IO uint32_t CALCNT; + stc_clk_trim_calcnt_field_t CALCNT_f; + }; + union + { + __IO uint32_t IFR; + stc_clk_trim_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_clk_trim_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t CALCON; + stc_clk_trim_calcon_field_t CALCON_f; + }; +}M0P_CLK_TRIM_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_crc_cr_field_t CR_f; + }; + union + { + __IO uint32_t RESULT; + stc_crc_result_field_t RESULT_f; + }; + uint8_t RESERVED2[120]; + union + { + __IO uint32_t DATA; + stc_crc_data_field_t DATA_f; + }; +}M0P_CRC_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t DEBUG_ACTIVE; + stc_debug_active_field_t DEBUG_ACTIVE_f; + }; +}M0P_DEBUG_ACTIVE_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CONF; + stc_dmac_conf_field_t CONF_f; + }; + uint8_t RESERVED1[12]; + union + { + __IO uint32_t CONFA0; + stc_dmac_confa0_field_t CONFA0_f; + }; + union + { + __IO uint32_t CONFB0; + stc_dmac_confb0_field_t CONFB0_f; + }; + union + { + __IO uint32_t SRCADR0; + stc_dmac_srcadr0_field_t SRCADR0_f; + }; + union + { + __IO uint32_t DSTADR0; + stc_dmac_dstadr0_field_t DSTADR0_f; + }; + union + { + __IO uint32_t CONFA1; + stc_dmac_confa1_field_t CONFA1_f; + }; + union + { + __IO uint32_t CONFB1; + stc_dmac_confb1_field_t CONFB1_f; + }; + union + { + __IO uint32_t SRCADR1; + stc_dmac_srcadr1_field_t SRCADR1_f; + }; + union + { + __IO uint32_t DSTADR1; + stc_dmac_dstadr1_field_t DSTADR1_f; + }; +}M0P_DMAC_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t TNVS; + stc_flash_tnvs_field_t TNVS_f; + }; + union + { + __IO uint32_t TPGS; + stc_flash_tpgs_field_t TPGS_f; + }; + union + { + __IO uint32_t TPROG; + stc_flash_tprog_field_t TPROG_f; + }; + union + { + __IO uint32_t TSERASE; + stc_flash_tserase_field_t TSERASE_f; + }; + union + { + __IO uint32_t TMERASE; + stc_flash_tmerase_field_t TMERASE_f; + }; + union + { + __IO uint32_t TPRCV; + stc_flash_tprcv_field_t TPRCV_f; + }; + union + { + __IO uint32_t TSRCV; + stc_flash_tsrcv_field_t TSRCV_f; + }; + union + { + __IO uint32_t TMRCV; + stc_flash_tmrcv_field_t TMRCV_f; + }; + union + { + __IO uint32_t CR; + stc_flash_cr_field_t CR_f; + }; + union + { + __IO uint32_t IFR; + stc_flash_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_flash_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t BYPASS; + stc_flash_bypass_field_t BYPASS_f; + }; + union + { + __IO uint32_t SLOCK; + stc_flash_slock_field_t SLOCK_f; + }; +}M0P_FLASH_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t PA00_SEL; + stc_gpio_pa00_sel_field_t PA00_SEL_f; + }; + union + { + __IO uint32_t PA01_SEL; + stc_gpio_pa01_sel_field_t PA01_SEL_f; + }; + union + { + __IO uint32_t PA02_SEL; + stc_gpio_pa02_sel_field_t PA02_SEL_f; + }; + union + { + __IO uint32_t PA03_SEL; + stc_gpio_pa03_sel_field_t PA03_SEL_f; + }; + union + { + __IO uint32_t PA04_SEL; + stc_gpio_pa04_sel_field_t PA04_SEL_f; + }; + union + { + __IO uint32_t PA05_SEL; + stc_gpio_pa05_sel_field_t PA05_SEL_f; + }; + union + { + __IO uint32_t PA06_SEL; + stc_gpio_pa06_sel_field_t PA06_SEL_f; + }; + union + { + __IO uint32_t PA07_SEL; + stc_gpio_pa07_sel_field_t PA07_SEL_f; + }; + union + { + __IO uint32_t PA08_SEL; + stc_gpio_pa08_sel_field_t PA08_SEL_f; + }; + union + { + __IO uint32_t PA09_SEL; + stc_gpio_pa09_sel_field_t PA09_SEL_f; + }; + union + { + __IO uint32_t PA10_SEL; + stc_gpio_pa10_sel_field_t PA10_SEL_f; + }; + union + { + __IO uint32_t PA11_SEL; + stc_gpio_pa11_sel_field_t PA11_SEL_f; + }; + union + { + __IO uint32_t PA12_SEL; + stc_gpio_pa12_sel_field_t PA12_SEL_f; + }; + union + { + __IO uint32_t PA13_SEL; + stc_gpio_pa13_sel_field_t PA13_SEL_f; + }; + union + { + __IO uint32_t PA14_SEL; + stc_gpio_pa14_sel_field_t PA14_SEL_f; + }; + union + { + __IO uint32_t PA15_SEL; + stc_gpio_pa15_sel_field_t PA15_SEL_f; + }; + union + { + __IO uint32_t PB00_SEL; + stc_gpio_pb00_sel_field_t PB00_SEL_f; + }; + union + { + __IO uint32_t PB01_SEL; + stc_gpio_pb01_sel_field_t PB01_SEL_f; + }; + union + { + __IO uint32_t PB02_SEL; + stc_gpio_pb02_sel_field_t PB02_SEL_f; + }; + union + { + __IO uint32_t PB03_SEL; + stc_gpio_pb03_sel_field_t PB03_SEL_f; + }; + union + { + __IO uint32_t PB04_SEL; + stc_gpio_pb04_sel_field_t PB04_SEL_f; + }; + union + { + __IO uint32_t PB05_SEL; + stc_gpio_pb05_sel_field_t PB05_SEL_f; + }; + union + { + __IO uint32_t PB06_SEL; + stc_gpio_pb06_sel_field_t PB06_SEL_f; + }; + union + { + __IO uint32_t PB07_SEL; + stc_gpio_pb07_sel_field_t PB07_SEL_f; + }; + union + { + __IO uint32_t PB08_SEL; + stc_gpio_pb08_sel_field_t PB08_SEL_f; + }; + union + { + __IO uint32_t PB09_SEL; + stc_gpio_pb09_sel_field_t PB09_SEL_f; + }; + union + { + __IO uint32_t PB10_SEL; + stc_gpio_pb10_sel_field_t PB10_SEL_f; + }; + union + { + __IO uint32_t PB11_SEL; + stc_gpio_pb11_sel_field_t PB11_SEL_f; + }; + union + { + __IO uint32_t PB12_SEL; + stc_gpio_pb12_sel_field_t PB12_SEL_f; + }; + union + { + __IO uint32_t PB13_SEL; + stc_gpio_pb13_sel_field_t PB13_SEL_f; + }; + union + { + __IO uint32_t PB14_SEL; + stc_gpio_pb14_sel_field_t PB14_SEL_f; + }; + union + { + __IO uint32_t PB15_SEL; + stc_gpio_pb15_sel_field_t PB15_SEL_f; + }; + union + { + __IO uint32_t PC00_SEL; + stc_gpio_pc00_sel_field_t PC00_SEL_f; + }; + union + { + __IO uint32_t PC01_SEL; + stc_gpio_pc01_sel_field_t PC01_SEL_f; + }; + union + { + __IO uint32_t PC02_SEL; + stc_gpio_pc02_sel_field_t PC02_SEL_f; + }; + union + { + __IO uint32_t PC03_SEL; + stc_gpio_pc03_sel_field_t PC03_SEL_f; + }; + union + { + __IO uint32_t PC04_SEL; + stc_gpio_pc04_sel_field_t PC04_SEL_f; + }; + union + { + __IO uint32_t PC05_SEL; + stc_gpio_pc05_sel_field_t PC05_SEL_f; + }; + union + { + __IO uint32_t PC06_SEL; + stc_gpio_pc06_sel_field_t PC06_SEL_f; + }; + union + { + __IO uint32_t PC07_SEL; + stc_gpio_pc07_sel_field_t PC07_SEL_f; + }; + union + { + __IO uint32_t PC08_SEL; + stc_gpio_pc08_sel_field_t PC08_SEL_f; + }; + union + { + __IO uint32_t PC09_SEL; + stc_gpio_pc09_sel_field_t PC09_SEL_f; + }; + union + { + __IO uint32_t PC10_SEL; + stc_gpio_pc10_sel_field_t PC10_SEL_f; + }; + union + { + __IO uint32_t PC11_SEL; + stc_gpio_pc11_sel_field_t PC11_SEL_f; + }; + union + { + __IO uint32_t PC12_SEL; + stc_gpio_pc12_sel_field_t PC12_SEL_f; + }; + union + { + __IO uint32_t PC13_SEL; + stc_gpio_pc13_sel_field_t PC13_SEL_f; + }; + union + { + __IO uint32_t PC14_SEL; + stc_gpio_pc14_sel_field_t PC14_SEL_f; + }; + union + { + __IO uint32_t PC15_SEL; + stc_gpio_pc15_sel_field_t PC15_SEL_f; + }; + union + { + __IO uint32_t PD00_SEL; + stc_gpio_pd00_sel_field_t PD00_SEL_f; + }; + union + { + __IO uint32_t PD01_SEL; + stc_gpio_pd01_sel_field_t PD01_SEL_f; + }; + union + { + __IO uint32_t PD02_SEL; + stc_gpio_pd02_sel_field_t PD02_SEL_f; + }; + union + { + __IO uint32_t PD03_SEL; + stc_gpio_pd03_sel_field_t PD03_SEL_f; + }; + union + { + __IO uint32_t PD04_SEL; + stc_gpio_pd04_sel_field_t PD04_SEL_f; + }; + union + { + __IO uint32_t PD05_SEL; + stc_gpio_pd05_sel_field_t PD05_SEL_f; + }; + union + { + __IO uint32_t PD06_SEL; + stc_gpio_pd06_sel_field_t PD06_SEL_f; + }; + union + { + __IO uint32_t PD07_SEL; + stc_gpio_pd07_sel_field_t PD07_SEL_f; + }; + uint8_t RESERVED56[32]; + union + { + __IO uint32_t PADIR; + stc_gpio_padir_field_t PADIR_f; + }; + union + { + __IO uint32_t PAIN; + stc_gpio_pain_field_t PAIN_f; + }; + union + { + __IO uint32_t PAOUT; + stc_gpio_paout_field_t PAOUT_f; + }; + union + { + __IO uint32_t PAADS; + stc_gpio_paads_field_t PAADS_f; + }; + union + { + __IO uint32_t PABSET; + stc_gpio_pabset_field_t PABSET_f; + }; + union + { + __IO uint32_t PABCLR; + stc_gpio_pabclr_field_t PABCLR_f; + }; + union + { + __IO uint32_t PABSETCLR; + stc_gpio_pabsetclr_field_t PABSETCLR_f; + }; + union + { + __IO uint32_t PADR; + stc_gpio_padr_field_t PADR_f; + }; + union + { + __IO uint32_t PAPU; + stc_gpio_papu_field_t PAPU_f; + }; + union + { + __IO uint32_t PAPD; + stc_gpio_papd_field_t PAPD_f; + }; + uint8_t RESERVED66[4]; + union + { + __IO uint32_t PAOD; + stc_gpio_paod_field_t PAOD_f; + }; + union + { + __IO uint32_t PAHIE; + stc_gpio_pahie_field_t PAHIE_f; + }; + union + { + __IO uint32_t PALIE; + stc_gpio_palie_field_t PALIE_f; + }; + union + { + __IO uint32_t PARIE; + stc_gpio_parie_field_t PARIE_f; + }; + union + { + __IO uint32_t PAFIE; + stc_gpio_pafie_field_t PAFIE_f; + }; + union + { + __IO uint32_t PBDIR; + stc_gpio_pbdir_field_t PBDIR_f; + }; + union + { + __IO uint32_t PBIN; + stc_gpio_pbin_field_t PBIN_f; + }; + union + { + __IO uint32_t PBOUT; + stc_gpio_pbout_field_t PBOUT_f; + }; + union + { + __IO uint32_t PBADS; + stc_gpio_pbads_field_t PBADS_f; + }; + union + { + __IO uint32_t PBBSET; + stc_gpio_pbbset_field_t PBBSET_f; + }; + union + { + __IO uint32_t PBBCLR; + stc_gpio_pbbclr_field_t PBBCLR_f; + }; + union + { + __IO uint32_t PBBSETCLR; + stc_gpio_pbbsetclr_field_t PBBSETCLR_f; + }; + union + { + __IO uint32_t PBDR; + stc_gpio_pbdr_field_t PBDR_f; + }; + union + { + __IO uint32_t PBPU; + stc_gpio_pbpu_field_t PBPU_f; + }; + union + { + __IO uint32_t PBPD; + stc_gpio_pbpd_field_t PBPD_f; + }; + uint8_t RESERVED81[4]; + union + { + __IO uint32_t PBOD; + stc_gpio_pbod_field_t PBOD_f; + }; + union + { + __IO uint32_t PBHIE; + stc_gpio_pbhie_field_t PBHIE_f; + }; + union + { + __IO uint32_t PBLIE; + stc_gpio_pblie_field_t PBLIE_f; + }; + union + { + __IO uint32_t PBRIE; + stc_gpio_pbrie_field_t PBRIE_f; + }; + union + { + __IO uint32_t PBFIE; + stc_gpio_pbfie_field_t PBFIE_f; + }; + union + { + __IO uint32_t PCDIR; + stc_gpio_pcdir_field_t PCDIR_f; + }; + union + { + __IO uint32_t PCIN; + stc_gpio_pcin_field_t PCIN_f; + }; + union + { + __IO uint32_t PCOUT; + stc_gpio_pcout_field_t PCOUT_f; + }; + union + { + __IO uint32_t PCADS; + stc_gpio_pcads_field_t PCADS_f; + }; + union + { + __IO uint32_t PCBSET; + stc_gpio_pcbset_field_t PCBSET_f; + }; + union + { + __IO uint32_t PCBCLR; + stc_gpio_pcbclr_field_t PCBCLR_f; + }; + union + { + __IO uint32_t PCBSETCLR; + stc_gpio_pcbsetclr_field_t PCBSETCLR_f; + }; + union + { + __IO uint32_t PCDR; + stc_gpio_pcdr_field_t PCDR_f; + }; + union + { + __IO uint32_t PCPU; + stc_gpio_pcpu_field_t PCPU_f; + }; + union + { + __IO uint32_t PCPD; + stc_gpio_pcpd_field_t PCPD_f; + }; + uint8_t RESERVED96[4]; + union + { + __IO uint32_t PCOD; + stc_gpio_pcod_field_t PCOD_f; + }; + union + { + __IO uint32_t PCHIE; + stc_gpio_pchie_field_t PCHIE_f; + }; + union + { + __IO uint32_t PCLIE; + stc_gpio_pclie_field_t PCLIE_f; + }; + union + { + __IO uint32_t PCRIE; + stc_gpio_pcrie_field_t PCRIE_f; + }; + union + { + __IO uint32_t PCFIE; + stc_gpio_pcfie_field_t PCFIE_f; + }; + union + { + __IO uint32_t PDDIR; + stc_gpio_pddir_field_t PDDIR_f; + }; + union + { + __IO uint32_t PDIN; + stc_gpio_pdin_field_t PDIN_f; + }; + union + { + __IO uint32_t PDOUT; + stc_gpio_pdout_field_t PDOUT_f; + }; + union + { + __IO uint32_t PDADS; + stc_gpio_pdads_field_t PDADS_f; + }; + union + { + __IO uint32_t PDBSET; + stc_gpio_pdbset_field_t PDBSET_f; + }; + union + { + __IO uint32_t PDBCLR; + stc_gpio_pdbclr_field_t PDBCLR_f; + }; + union + { + __IO uint32_t PDBSETCLR; + stc_gpio_pdbsetclr_field_t PDBSETCLR_f; + }; + union + { + __IO uint32_t PDDR; + stc_gpio_pddr_field_t PDDR_f; + }; + union + { + __IO uint32_t PDPU; + stc_gpio_pdpu_field_t PDPU_f; + }; + union + { + __IO uint32_t PDPD; + stc_gpio_pdpd_field_t PDPD_f; + }; + uint8_t RESERVED111[4]; + union + { + __IO uint32_t PDOD; + stc_gpio_pdod_field_t PDOD_f; + }; + union + { + __IO uint32_t PDHIE; + stc_gpio_pdhie_field_t PDHIE_f; + }; + union + { + __IO uint32_t PDLIE; + stc_gpio_pdlie_field_t PDLIE_f; + }; + union + { + __IO uint32_t PDRIE; + stc_gpio_pdrie_field_t PDRIE_f; + }; + union + { + __IO uint32_t PDFIE; + stc_gpio_pdfie_field_t PDFIE_f; + }; + union + { + __IO uint32_t PA_STAT; + stc_gpio_pa_stat_field_t PA_STAT_f; + }; + uint8_t RESERVED117[12]; + union + { + __IO uint32_t PA_ICLR; + stc_gpio_pa_iclr_field_t PA_ICLR_f; + }; + uint8_t RESERVED118[44]; + union + { + __IO uint32_t PB_STAT; + stc_gpio_pb_stat_field_t PB_STAT_f; + }; + uint8_t RESERVED119[12]; + union + { + __IO uint32_t PB_ICLR; + stc_gpio_pb_iclr_field_t PB_ICLR_f; + }; + uint8_t RESERVED120[44]; + union + { + __IO uint32_t PC_STAT; + stc_gpio_pc_stat_field_t PC_STAT_f; + }; + uint8_t RESERVED121[12]; + union + { + __IO uint32_t PC_ICLR; + stc_gpio_pc_iclr_field_t PC_ICLR_f; + }; + uint8_t RESERVED122[44]; + union + { + __IO uint32_t PD_STAT; + stc_gpio_pd_stat_field_t PD_STAT_f; + }; + uint8_t RESERVED123[12]; + union + { + __IO uint32_t PD_ICLR; + stc_gpio_pd_iclr_field_t PD_ICLR_f; + }; + uint8_t RESERVED124[44]; + union + { + __IO uint32_t CTRL0; + stc_gpio_ctrl0_field_t CTRL0_f; + }; + union + { + __IO uint32_t CTRL1; + stc_gpio_ctrl1_field_t CTRL1_f; + }; + union + { + __IO uint32_t CTRL2; + stc_gpio_ctrl2_field_t CTRL2_f; + }; + union + { + __IO uint32_t TIMGS; + stc_gpio_timgs_field_t TIMGS_f; + }; + union + { + __IO uint32_t TIMES; + stc_gpio_times_field_t TIMES_f; + }; + union + { + __IO uint32_t TIMCPS; + stc_gpio_timcps_field_t TIMCPS_f; + }; + union + { + __IO uint32_t PCAS; + stc_gpio_pcas_field_t PCAS_f; + }; +}M0P_GPIO_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t DIVIDEND; + stc_hdiv_dividend_field_t DIVIDEND_f; + }; + union + { + __IO uint32_t DIVISOR; + stc_hdiv_divisor_field_t DIVISOR_f; + }; + union + { + __IO uint32_t QUOTIENT; + stc_hdiv_quotient_field_t QUOTIENT_f; + }; + union + { + __IO uint32_t REMAINDER; + stc_hdiv_remainder_field_t REMAINDER_f; + }; + union + { + __IO uint32_t SIGN; + stc_hdiv_sign_field_t SIGN_f; + }; + union + { + __IO uint32_t STAT; + stc_hdiv_stat_field_t STAT_f; + }; +}M0P_HDIV_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t TMRUN; + stc_i2c_tmrun_field_t TMRUN_f; + }; + union + { + __IO uint32_t TM; + stc_i2c_tm_field_t TM_f; + }; + union + { + __IO uint32_t CR; + stc_i2c_cr_field_t CR_f; + }; + union + { + __IO uint32_t DATA; + stc_i2c_data_field_t DATA_f; + }; + union + { + __IO uint32_t ADDR; + stc_i2c_addr_field_t ADDR_f; + }; + union + { + __IO uint32_t STAT; + stc_i2c_stat_field_t STAT_f; + }; +}M0P_I2C_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR0; + stc_lcd_cr0_field_t CR0_f; + }; + union + { + __IO uint32_t CR1; + stc_lcd_cr1_field_t CR1_f; + }; + union + { + __IO uint32_t INTCLR; + stc_lcd_intclr_field_t INTCLR_f; + }; + union + { + __IO uint32_t POEN0; + stc_lcd_poen0_field_t POEN0_f; + }; + union + { + __IO uint32_t POEN1; + stc_lcd_poen1_field_t POEN1_f; + }; + uint8_t RESERVED5[44]; + union + { + __IO uint32_t RAM0; + stc_lcd_ram0_field_t RAM0_f; + }; + union + { + __IO uint32_t RAM1; + stc_lcd_ram1_field_t RAM1_f; + }; + union + { + __IO uint32_t RAM2; + stc_lcd_ram2_field_t RAM2_f; + }; + union + { + __IO uint32_t RAM3; + stc_lcd_ram3_field_t RAM3_f; + }; + union + { + __IO uint32_t RAM4; + stc_lcd_ram4_field_t RAM4_f; + }; + union + { + __IO uint32_t RAM5; + stc_lcd_ram5_field_t RAM5_f; + }; + union + { + __IO uint32_t RAM6; + stc_lcd_ram6_field_t RAM6_f; + }; + union + { + __IO uint32_t RAM7; + stc_lcd_ram7_field_t RAM7_f; + }; + union + { + __IO uint32_t RAM8; + stc_lcd_ram8_field_t RAM8_f; + }; + union + { + __IO uint32_t RAM9; + stc_lcd_ram9_field_t RAM9_f; + }; + union + { + __IO uint32_t RAMA; + stc_lcd_rama_field_t RAMA_f; + }; + union + { + __IO uint32_t RAMB; + stc_lcd_ramb_field_t RAMB_f; + }; + union + { + __IO uint32_t RAMC; + stc_lcd_ramc_field_t RAMC_f; + }; + union + { + __IO uint32_t RAMD; + stc_lcd_ramd_field_t RAMD_f; + }; + union + { + __IO uint32_t RAME; + stc_lcd_rame_field_t RAME_f; + }; + union + { + __IO uint32_t RAMF; + stc_lcd_ramf_field_t RAMF_f; + }; +}M0P_LCD_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CNT; + stc_lptimer_cnt_field_t CNT_f; + }; + union + { + __IO uint32_t ARR; + stc_lptimer_arr_field_t ARR_f; + }; + uint8_t RESERVED2[4]; + union + { + __IO uint32_t CR; + stc_lptimer_cr_field_t CR_f; + }; + union + { + __IO uint32_t IFR; + stc_lptimer_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_lptimer_iclr_field_t ICLR_f; + }; +}M0P_LPTIMER_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t SBUF; + stc_lpuart_sbuf_field_t SBUF_f; + }; + union + { + __IO uint32_t SCON; + stc_lpuart_scon_field_t SCON_f; + }; + union + { + __IO uint32_t SADDR; + stc_lpuart_saddr_field_t SADDR_f; + }; + union + { + __IO uint32_t SADEN; + stc_lpuart_saden_field_t SADEN_f; + }; + union + { + __IO uint32_t ISR; + stc_lpuart_isr_field_t ISR_f; + }; + union + { + __IO uint32_t ICR; + stc_lpuart_icr_field_t ICR_f; + }; + union + { + __IO uint32_t SCNT; + stc_lpuart_scnt_field_t SCNT_f; + }; +}M0P_LPUART_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[40]; + union + { + __IO uint32_t CR; + stc_lvd_cr_field_t CR_f; + }; + union + { + __IO uint32_t IFR; + stc_lvd_ifr_field_t IFR_f; + }; +}M0P_LVD_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[48]; + union + { + __IO uint32_t CR0; + stc_opa_cr0_field_t CR0_f; + }; + union + { + __IO uint32_t CR1; + stc_opa_cr1_field_t CR1_f; + }; + union + { + __IO uint32_t CR2; + stc_opa_cr2_field_t CR2_f; + }; + union + { + __IO uint8_t CR; + stc_opa_cr_field_t CR_f; + }; +}M0P_OPA_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CCON; + stc_pca_ccon_field_t CCON_f; + }; + union + { + __IO uint32_t CMOD; + stc_pca_cmod_field_t CMOD_f; + }; + union + { + __IO uint32_t CNT; + stc_pca_cnt_field_t CNT_f; + }; + union + { + __IO uint32_t ICLR; + stc_pca_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t CCAPM0; + stc_pca_ccapm0_field_t CCAPM0_f; + }; + union + { + __IO uint32_t CCAPM1; + stc_pca_ccapm1_field_t CCAPM1_f; + }; + union + { + __IO uint32_t CCAPM2; + stc_pca_ccapm2_field_t CCAPM2_f; + }; + union + { + __IO uint32_t CCAPM3; + stc_pca_ccapm3_field_t CCAPM3_f; + }; + union + { + __IO uint32_t CCAPM4; + stc_pca_ccapm4_field_t CCAPM4_f; + }; + union + { + __IO uint32_t CCAP0H; + stc_pca_ccap0h_field_t CCAP0H_f; + }; + union + { + __IO uint32_t CCAP0L; + stc_pca_ccap0l_field_t CCAP0L_f; + }; + union + { + __IO uint32_t CCAP1H; + stc_pca_ccap1h_field_t CCAP1H_f; + }; + union + { + __IO uint32_t CCAP1L; + stc_pca_ccap1l_field_t CCAP1L_f; + }; + union + { + __IO uint32_t CCAP2H; + stc_pca_ccap2h_field_t CCAP2H_f; + }; + union + { + __IO uint32_t CCAP2L; + stc_pca_ccap2l_field_t CCAP2L_f; + }; + union + { + __IO uint32_t CCAP3H; + stc_pca_ccap3h_field_t CCAP3H_f; + }; + union + { + __IO uint32_t CCAP3L; + stc_pca_ccap3l_field_t CCAP3L_f; + }; + union + { + __IO uint32_t CCAP4H; + stc_pca_ccap4h_field_t CCAP4H_f; + }; + union + { + __IO uint32_t CCAP4L; + stc_pca_ccap4l_field_t CCAP4L_f; + }; + union + { + __IO uint32_t CCAPO; + stc_pca_ccapo_field_t CCAPO_f; + }; + union + { + __IO uint32_t CCAP0; + stc_pca_ccap0_field_t CCAP0_f; + }; + union + { + __IO uint32_t CCAP1; + stc_pca_ccap1_field_t CCAP1_f; + }; + union + { + __IO uint32_t CCAP2; + stc_pca_ccap2_field_t CCAP2_f; + }; + union + { + __IO uint32_t CCAP3; + stc_pca_ccap3_field_t CCAP3_f; + }; + union + { + __IO uint32_t CCAP4; + stc_pca_ccap4_field_t CCAP4_f; + }; + union + { + __IO uint32_t CARR; + stc_pca_carr_field_t CARR_f; + }; + union + { + __IO uint32_t EPWM; + stc_pca_epwm_field_t EPWM_f; + }; +}M0P_PCA_TypeDef; + +typedef struct +{ + union + { + __IO uint8_t RUN; + stc_pcnt_run_field_t RUN_f; + }; + uint8_t RESERVED1[3]; + union + { + __IO uint8_t CR; + stc_pcnt_cr_field_t CR_f; + }; + uint8_t RESERVED2[3]; + union + { + __IO uint32_t FLT; + stc_pcnt_flt_field_t FLT_f; + }; + union + { + __IO uint32_t TOCR; + stc_pcnt_tocr_field_t TOCR_f; + }; + union + { + __IO uint8_t CMD; + stc_pcnt_cmd_field_t CMD_f; + }; + uint8_t RESERVED5[3]; + union + { + __IO uint8_t SR1; + stc_pcnt_sr1_field_t SR1_f; + }; + uint8_t RESERVED6[3]; + union + { + __IO uint16_t CNT; + stc_pcnt_cnt_field_t CNT_f; + }; + uint8_t RESERVED7[2]; + union + { + __IO uint16_t TOP; + stc_pcnt_top_field_t TOP_f; + }; + uint8_t RESERVED8[2]; + union + { + __IO uint16_t BUF; + stc_pcnt_buf_field_t BUF_f; + }; + uint8_t RESERVED9[2]; + union + { + __IO uint8_t IFR; + stc_pcnt_ifr_field_t IFR_f; + }; + uint8_t RESERVED10[3]; + union + { + __IO uint8_t ICR; + stc_pcnt_icr_field_t ICR_f; + }; + uint8_t RESERVED11[3]; + union + { + __IO uint8_t IEN; + stc_pcnt_ien_field_t IEN_f; + }; + uint8_t RESERVED12[3]; + union + { + __IO uint8_t SR2; + stc_pcnt_sr2_field_t SR2_f; + }; +}M0P_PCNT_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_ram_cr_field_t CR_f; + }; + union + { + __IO uint32_t ERRADDR; + stc_ram_erraddr_field_t ERRADDR_f; + }; + union + { + __IO uint32_t IFR; + stc_ram_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_ram_iclr_field_t ICLR_f; + }; +}M0P_RAM_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t RESET_FLAG; + stc_reset_flag_field_t RESET_FLAG_f; + }; + uint8_t RESERVED1[8]; + union + { + __IO uint32_t PREI_RESET; + stc_reset_prei_field_t PREI_RESET_f; + }; +}M0P_RESET_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_rng_cr_field_t CR_f; + }; + union + { + __IO uint32_t MODE; + stc_rng_mode_field_t MODE_f; + }; + uint8_t RESERVED2[4]; + union + { + __IO uint32_t DATA0; + stc_rng_data0_field_t DATA0_f; + }; + union + { + __IO uint32_t DATA1; + stc_rng_data1_field_t DATA1_f; + }; +}M0P_RNG_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR0; + stc_rtc_cr0_field_t CR0_f; + }; + union + { + __IO uint32_t CR1; + stc_rtc_cr1_field_t CR1_f; + }; + union + { + __IO uint32_t SEC; + stc_rtc_sec_field_t SEC_f; + }; + union + { + __IO uint32_t MIN; + stc_rtc_min_field_t MIN_f; + }; + union + { + __IO uint32_t HOUR; + stc_rtc_hour_field_t HOUR_f; + }; + union + { + __IO uint32_t WEEK; + stc_rtc_week_field_t WEEK_f; + }; + union + { + __IO uint32_t DAY; + stc_rtc_day_field_t DAY_f; + }; + union + { + __IO uint32_t MON; + stc_rtc_mon_field_t MON_f; + }; + union + { + __IO uint32_t YEAR; + stc_rtc_year_field_t YEAR_f; + }; + union + { + __IO uint32_t ALMMIN; + stc_rtc_almmin_field_t ALMMIN_f; + }; + union + { + __IO uint32_t ALMHOUR; + stc_rtc_almhour_field_t ALMHOUR_f; + }; + union + { + __IO uint32_t ALMWEEK; + stc_rtc_almweek_field_t ALMWEEK_f; + }; + union + { + __IO uint32_t COMPEN; + stc_rtc_compen_field_t COMPEN_f; + }; +}M0P_RTC_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_spi_cr_field_t CR_f; + }; + union + { + __IO uint32_t SSN; + stc_spi_ssn_field_t SSN_f; + }; + union + { + __IO uint32_t STAT; + stc_spi_stat_field_t STAT_f; + }; + union + { + __IO uint32_t DATA; + stc_spi_data_field_t DATA_f; + }; + union + { + __IO uint32_t CR2; + stc_spi_cr2_field_t CR2_f; + }; + union + { + __IO uint32_t ICLR; + stc_spi_iclr_field_t ICLR_f; + }; +}M0P_SPI_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t SYSCTRL0; + stc_sysctrl_sysctrl0_field_t SYSCTRL0_f; + }; + union + { + __IO uint32_t SYSCTRL1; + stc_sysctrl_sysctrl1_field_t SYSCTRL1_f; + }; + union + { + __IO uint32_t SYSCTRL2; + stc_sysctrl_sysctrl2_field_t SYSCTRL2_f; + }; + union + { + __IO uint32_t RCH_CR; + stc_sysctrl_rch_cr_field_t RCH_CR_f; + }; + union + { + __IO uint32_t XTH_CR; + stc_sysctrl_xth_cr_field_t XTH_CR_f; + }; + union + { + __IO uint32_t RCL_CR; + stc_sysctrl_rcl_cr_field_t RCL_CR_f; + }; + union + { + __IO uint32_t XTL_CR; + stc_sysctrl_xtl_cr_field_t XTL_CR_f; + }; + uint8_t RESERVED7[4]; + union + { + __IO uint32_t PERI_CLKEN; + stc_sysctrl_peri_clken_field_t PERI_CLKEN_f; + }; + uint8_t RESERVED8[24]; + union + { + __IO uint32_t PLL_CR; + stc_sysctrl_pll_cr_field_t PLL_CR_f; + }; +}M0P_SYSCTRL_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t ARR; + stc_tim0_mode0_arr_field_t ARR_f; + }; + union + { + __IO uint32_t CNT; + stc_tim0_mode0_cnt_field_t CNT_f; + }; + union + { + __IO uint32_t CNT32; + stc_tim0_mode0_cnt32_field_t CNT32_f; + }; + union + { + __IO uint32_t M0CR; + stc_tim0_mode0_m0cr_field_t M0CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim0_mode0_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim0_mode0_iclr_field_t ICLR_f; + }; + uint8_t RESERVED6[24]; + union + { + __IO uint32_t DTR; + stc_tim0_mode0_dtr_field_t DTR_f; + }; +}M0P_TIM0_MODE0_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[4]; + union + { + __IO uint32_t CNT; + stc_tim0_mode1_cnt_field_t CNT_f; + }; + uint8_t RESERVED1[4]; + union + { + __IO uint32_t M1CR; + stc_tim0_mode1_m1cr_field_t M1CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim0_mode1_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim0_mode1_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t MSCR; + stc_tim0_mode1_mscr_field_t MSCR_f; + }; + union + { + __IO uint32_t FLTR; + stc_tim0_mode1_fltr_field_t FLTR_f; + }; + uint8_t RESERVED6[4]; + union + { + __IO uint32_t CR0; + stc_tim0_mode1_cr0_field_t CR0_f; + }; + uint8_t RESERVED7[20]; + union + { + __IO uint32_t CCR0A; + stc_tim0_mode1_ccr0a_field_t CCR0A_f; + }; +}M0P_TIM0_MODE1_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t ARR; + stc_tim0_mode23_arr_field_t ARR_f; + }; + union + { + __IO uint32_t CNT; + stc_tim0_mode23_cnt_field_t CNT_f; + }; + uint8_t RESERVED2[4]; + union + { + __IO uint32_t M23CR; + stc_tim0_mode23_m23cr_field_t M23CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim0_mode23_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim0_mode23_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t MSCR; + stc_tim0_mode23_mscr_field_t MSCR_f; + }; + union + { + __IO uint32_t FLTR; + stc_tim0_mode23_fltr_field_t FLTR_f; + }; + union + { + __IO uint32_t ADTR; + stc_tim0_mode23_adtr_field_t ADTR_f; + }; + union + { + __IO uint32_t CRCH0; + stc_tim0_mode23_crch0_field_t CRCH0_f; + }; + uint8_t RESERVED9[8]; + union + { + __IO uint32_t DTR; + stc_tim0_mode23_dtr_field_t DTR_f; + }; + union + { + __IO uint32_t RCR; + stc_tim0_mode23_rcr_field_t RCR_f; + }; + union + { + __IO uint32_t ARRDM; + stc_tim0_mode23_arrdm_field_t ARRDM_f; + }; + union + { + __IO uint32_t CCR0A; + stc_tim0_mode23_ccr0a_field_t CCR0A_f; + }; + union + { + __IO uint32_t CCR0B; + stc_tim0_mode23_ccr0b_field_t CCR0B_f; + }; +}M0P_TIM0_MODE23_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t ARR; + stc_tim1_mode0_arr_field_t ARR_f; + }; + union + { + __IO uint32_t CNT; + stc_tim1_mode0_cnt_field_t CNT_f; + }; + union + { + __IO uint32_t CNT32; + stc_tim1_mode0_cnt32_field_t CNT32_f; + }; + union + { + __IO uint32_t M0CR; + stc_tim1_mode0_m0cr_field_t M0CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim1_mode0_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim1_mode0_iclr_field_t ICLR_f; + }; + uint8_t RESERVED6[24]; + union + { + __IO uint32_t DTR; + stc_tim1_mode0_dtr_field_t DTR_f; + }; +}M0P_TIM1_MODE0_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[4]; + union + { + __IO uint32_t CNT; + stc_tim1_mode1_cnt_field_t CNT_f; + }; + uint8_t RESERVED1[4]; + union + { + __IO uint32_t M1CR; + stc_tim1_mode1_m1cr_field_t M1CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim1_mode1_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim1_mode1_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t MSCR; + stc_tim1_mode1_mscr_field_t MSCR_f; + }; + union + { + __IO uint32_t FLTR; + stc_tim1_mode1_fltr_field_t FLTR_f; + }; + uint8_t RESERVED6[4]; + union + { + __IO uint32_t CR0; + stc_tim1_mode1_cr0_field_t CR0_f; + }; + uint8_t RESERVED7[20]; + union + { + __IO uint32_t CCR0A; + stc_tim1_mode1_ccr0a_field_t CCR0A_f; + }; +}M0P_TIM1_MODE1_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t ARR; + stc_tim1_mode23_arr_field_t ARR_f; + }; + union + { + __IO uint32_t CNT; + stc_tim1_mode23_cnt_field_t CNT_f; + }; + uint8_t RESERVED2[4]; + union + { + __IO uint32_t M23CR; + stc_tim1_mode23_m23cr_field_t M23CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim1_mode23_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim1_mode23_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t MSCR; + stc_tim1_mode23_mscr_field_t MSCR_f; + }; + union + { + __IO uint32_t FLTR; + stc_tim1_mode23_fltr_field_t FLTR_f; + }; + union + { + __IO uint32_t ADTR; + stc_tim1_mode23_adtr_field_t ADTR_f; + }; + union + { + __IO uint32_t CRCH0; + stc_tim1_mode23_crch0_field_t CRCH0_f; + }; + uint8_t RESERVED9[8]; + union + { + __IO uint32_t DTR; + stc_tim1_mode23_dtr_field_t DTR_f; + }; + union + { + __IO uint32_t RCR; + stc_tim1_mode23_rcr_field_t RCR_f; + }; + union + { + __IO uint32_t ARRDM; + stc_tim1_mode23_arrdm_field_t ARRDM_f; + }; + union + { + __IO uint32_t CCR0A; + stc_tim1_mode23_ccr0a_field_t CCR0A_f; + }; + union + { + __IO uint32_t CCR0B; + stc_tim1_mode23_ccr0b_field_t CCR0B_f; + }; +}M0P_TIM1_MODE23_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t ARR; + stc_tim2_mode0_arr_field_t ARR_f; + }; + union + { + __IO uint32_t CNT; + stc_tim2_mode0_cnt_field_t CNT_f; + }; + union + { + __IO uint32_t CNT32; + stc_tim2_mode0_cnt32_field_t CNT32_f; + }; + union + { + __IO uint32_t M0CR; + stc_tim2_mode0_m0cr_field_t M0CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim2_mode0_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim2_mode0_iclr_field_t ICLR_f; + }; + uint8_t RESERVED6[24]; + union + { + __IO uint32_t DTR; + stc_tim2_mode0_dtr_field_t DTR_f; + }; +}M0P_TIM2_MODE0_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[4]; + union + { + __IO uint32_t CNT; + stc_tim2_mode1_cnt_field_t CNT_f; + }; + uint8_t RESERVED1[4]; + union + { + __IO uint32_t M1CR; + stc_tim2_mode1_m1cr_field_t M1CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim2_mode1_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim2_mode1_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t MSCR; + stc_tim2_mode1_mscr_field_t MSCR_f; + }; + union + { + __IO uint32_t FLTR; + stc_tim2_mode1_fltr_field_t FLTR_f; + }; + uint8_t RESERVED6[4]; + union + { + __IO uint32_t CR0; + stc_tim2_mode1_cr0_field_t CR0_f; + }; + uint8_t RESERVED7[20]; + union + { + __IO uint32_t CCR0A; + stc_tim2_mode1_ccr0a_field_t CCR0A_f; + }; +}M0P_TIM2_MODE1_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t ARR; + stc_tim2_mode23_arr_field_t ARR_f; + }; + union + { + __IO uint32_t CNT; + stc_tim2_mode23_cnt_field_t CNT_f; + }; + uint8_t RESERVED2[4]; + union + { + __IO uint32_t M23CR; + stc_tim2_mode23_m23cr_field_t M23CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim2_mode23_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim2_mode23_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t MSCR; + stc_tim2_mode23_mscr_field_t MSCR_f; + }; + union + { + __IO uint32_t FLTR; + stc_tim2_mode23_fltr_field_t FLTR_f; + }; + union + { + __IO uint32_t ADTR; + stc_tim2_mode23_adtr_field_t ADTR_f; + }; + union + { + __IO uint32_t CRCH0; + stc_tim2_mode23_crch0_field_t CRCH0_f; + }; + uint8_t RESERVED9[8]; + union + { + __IO uint32_t DTR; + stc_tim2_mode23_dtr_field_t DTR_f; + }; + union + { + __IO uint32_t RCR; + stc_tim2_mode23_rcr_field_t RCR_f; + }; + union + { + __IO uint32_t ARRDM; + stc_tim2_mode23_arrdm_field_t ARRDM_f; + }; + union + { + __IO uint32_t CCR0A; + stc_tim2_mode23_ccr0a_field_t CCR0A_f; + }; + union + { + __IO uint32_t CCR0B; + stc_tim2_mode23_ccr0b_field_t CCR0B_f; + }; +}M0P_TIM2_MODE23_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t ARR; + stc_tim3_mode0_arr_field_t ARR_f; + }; + union + { + __IO uint32_t CNT; + stc_tim3_mode0_cnt_field_t CNT_f; + }; + union + { + __IO uint32_t CNT32; + stc_tim3_mode0_cnt32_field_t CNT32_f; + }; + union + { + __IO uint32_t M0CR; + stc_tim3_mode0_m0cr_field_t M0CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim3_mode0_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim3_mode0_iclr_field_t ICLR_f; + }; + uint8_t RESERVED6[24]; + union + { + __IO uint32_t DTR; + stc_tim3_mode0_dtr_field_t DTR_f; + }; +}M0P_TIM3_MODE0_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[4]; + union + { + __IO uint32_t CNT; + stc_tim3_mode1_cnt_field_t CNT_f; + }; + uint8_t RESERVED1[4]; + union + { + __IO uint32_t M1CR; + stc_tim3_mode1_m1cr_field_t M1CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim3_mode1_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim3_mode1_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t MSCR; + stc_tim3_mode1_mscr_field_t MSCR_f; + }; + union + { + __IO uint32_t FLTR; + stc_tim3_mode1_fltr_field_t FLTR_f; + }; + uint8_t RESERVED6[4]; + union + { + __IO uint32_t CR0; + stc_tim3_mode1_cr0_field_t CR0_f; + }; + uint8_t RESERVED7[20]; + union + { + __IO uint32_t CCR0A; + stc_tim3_mode1_ccr0a_field_t CCR0A_f; + }; +}M0P_TIM3_MODE1_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t ARR; + stc_tim3_mode23_arr_field_t ARR_f; + }; + union + { + __IO uint32_t CNT; + stc_tim3_mode23_cnt_field_t CNT_f; + }; + uint8_t RESERVED2[4]; + union + { + __IO uint32_t M23CR; + stc_tim3_mode23_m23cr_field_t M23CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim3_mode23_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim3_mode23_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t MSCR; + stc_tim3_mode23_mscr_field_t MSCR_f; + }; + union + { + __IO uint32_t FLTR; + stc_tim3_mode23_fltr_field_t FLTR_f; + }; + union + { + __IO uint32_t ADTR; + stc_tim3_mode23_adtr_field_t ADTR_f; + }; + union + { + __IO uint32_t CRCH0; + stc_tim3_mode23_crch0_field_t CRCH0_f; + }; + union + { + __IO uint32_t CRCH1; + stc_tim3_mode23_crch1_field_t CRCH1_f; + }; + union + { + __IO uint32_t CRCH2; + stc_tim3_mode23_crch2_field_t CRCH2_f; + }; + union + { + __IO uint32_t DTR; + stc_tim3_mode23_dtr_field_t DTR_f; + }; + union + { + __IO uint32_t RCR; + stc_tim3_mode23_rcr_field_t RCR_f; + }; + union + { + __IO uint32_t ARRDM; + stc_tim3_mode23_arrdm_field_t ARRDM_f; + }; + union + { + __IO uint32_t CCR0A; + stc_tim3_mode23_ccr0a_field_t CCR0A_f; + }; + union + { + __IO uint32_t CCR0B; + stc_tim3_mode23_ccr0b_field_t CCR0B_f; + }; + union + { + __IO uint32_t CCR1A; + stc_tim3_mode23_ccr1a_field_t CCR1A_f; + }; + union + { + __IO uint32_t CCR1B; + stc_tim3_mode23_ccr1b_field_t CCR1B_f; + }; + union + { + __IO uint32_t CCR2A; + stc_tim3_mode23_ccr2a_field_t CCR2A_f; + }; + union + { + __IO uint32_t CCR2B; + stc_tim3_mode23_ccr2b_field_t CCR2B_f; + }; +}M0P_TIM3_MODE23_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CNTER; + stc_tim4_cnter_field_t CNTER_f; + }; + union + { + __IO uint32_t PERAR; + stc_tim4_perar_field_t PERAR_f; + }; + union + { + __IO uint32_t PERBR; + stc_tim4_perbr_field_t PERBR_f; + }; + uint8_t RESERVED3[4]; + union + { + __IO uint32_t GCMAR; + stc_tim4_gcmar_field_t GCMAR_f; + }; + union + { + __IO uint32_t GCMBR; + stc_tim4_gcmbr_field_t GCMBR_f; + }; + union + { + __IO uint32_t GCMCR; + stc_tim4_gcmcr_field_t GCMCR_f; + }; + union + { + __IO uint32_t GCMDR; + stc_tim4_gcmdr_field_t GCMDR_f; + }; + uint8_t RESERVED7[8]; + union + { + __IO uint32_t SCMAR; + stc_tim4_scmar_field_t SCMAR_f; + }; + union + { + __IO uint32_t SCMBR; + stc_tim4_scmbr_field_t SCMBR_f; + }; + uint8_t RESERVED9[16]; + union + { + __IO uint32_t DTUAR; + stc_tim4_dtuar_field_t DTUAR_f; + }; + union + { + __IO uint32_t DTDAR; + stc_tim4_dtdar_field_t DTDAR_f; + }; + uint8_t RESERVED11[8]; + union + { + __IO uint32_t GCONR; + stc_tim4_gconr_field_t GCONR_f; + }; + union + { + __IO uint32_t ICONR; + stc_tim4_iconr_field_t ICONR_f; + }; + union + { + __IO uint32_t PCONR; + stc_tim4_pconr_field_t PCONR_f; + }; + union + { + __IO uint32_t BCONR; + stc_tim4_bconr_field_t BCONR_f; + }; + union + { + __IO uint32_t DCONR; + stc_tim4_dconr_field_t DCONR_f; + }; + uint8_t RESERVED16[4]; + union + { + __IO uint32_t FCONR; + stc_tim4_fconr_field_t FCONR_f; + }; + union + { + __IO uint32_t VPERR; + stc_tim4_vperr_field_t VPERR_f; + }; + union + { + __IO uint32_t STFLR; + stc_tim4_stflr_field_t STFLR_f; + }; + union + { + __IO uint32_t HSTAR; + stc_tim4_hstar_field_t HSTAR_f; + }; + union + { + __IO uint32_t HSTPR; + stc_tim4_hstpr_field_t HSTPR_f; + }; + union + { + __IO uint32_t HCELR; + stc_tim4_hcelr_field_t HCELR_f; + }; + union + { + __IO uint32_t HCPAR; + stc_tim4_hcpar_field_t HCPAR_f; + }; + union + { + __IO uint32_t HCPBR; + stc_tim4_hcpbr_field_t HCPBR_f; + }; + union + { + __IO uint32_t HCUPR; + stc_tim4_hcupr_field_t HCUPR_f; + }; + union + { + __IO uint32_t HCDOR; + stc_tim4_hcdor_field_t HCDOR_f; + }; + uint8_t RESERVED26[112]; + union + { + __IO uint32_t IFR; + stc_tim4_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim4_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t CR; + stc_tim4_cr_field_t CR_f; + }; + uint8_t RESERVED29[4]; + union + { + __IO uint32_t AOSSR; + stc_tim4_aossr_field_t AOSSR_f; + }; + union + { + __IO uint32_t AOSCL; + stc_tim4_aoscl_field_t AOSCL_f; + }; + union + { + __IO uint32_t PTBKS; + stc_tim4_ptbks_field_t PTBKS_f; + }; + union + { + __IO uint32_t TTRIG; + stc_tim4_ttrig_field_t TTRIG_f; + }; + union + { + __IO uint32_t ITRIG; + stc_tim4_itrig_field_t ITRIG_f; + }; + union + { + __IO uint32_t PTBKP; + stc_tim4_ptbkp_field_t PTBKP_f; + }; + uint8_t RESERVED35[716]; + union + { + __IO uint32_t SSTAR; + stc_tim4_sstar_field_t SSTAR_f; + }; + union + { + __IO uint32_t SSTPR; + stc_tim4_sstpr_field_t SSTPR_f; + }; + union + { + __IO uint32_t SCLRR; + stc_tim4_sclrr_field_t SCLRR_f; + }; +}M0P_TIM4_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CNTER; + stc_tim5_cnter_field_t CNTER_f; + }; + union + { + __IO uint32_t PERAR; + stc_tim5_perar_field_t PERAR_f; + }; + union + { + __IO uint32_t PERBR; + stc_tim5_perbr_field_t PERBR_f; + }; + uint8_t RESERVED3[4]; + union + { + __IO uint32_t GCMAR; + stc_tim5_gcmar_field_t GCMAR_f; + }; + union + { + __IO uint32_t GCMBR; + stc_tim5_gcmbr_field_t GCMBR_f; + }; + union + { + __IO uint32_t GCMCR; + stc_tim5_gcmcr_field_t GCMCR_f; + }; + union + { + __IO uint32_t GCMDR; + stc_tim5_gcmdr_field_t GCMDR_f; + }; + uint8_t RESERVED7[8]; + union + { + __IO uint32_t SCMAR; + stc_tim5_scmar_field_t SCMAR_f; + }; + union + { + __IO uint32_t SCMBR; + stc_tim5_scmbr_field_t SCMBR_f; + }; + uint8_t RESERVED9[16]; + union + { + __IO uint32_t DTUAR; + stc_tim5_dtuar_field_t DTUAR_f; + }; + union + { + __IO uint32_t DTDAR; + stc_tim5_dtdar_field_t DTDAR_f; + }; + uint8_t RESERVED11[8]; + union + { + __IO uint32_t GCONR; + stc_tim5_gconr_field_t GCONR_f; + }; + union + { + __IO uint32_t ICONR; + stc_tim5_iconr_field_t ICONR_f; + }; + union + { + __IO uint32_t PCONR; + stc_tim5_pconr_field_t PCONR_f; + }; + union + { + __IO uint32_t BCONR; + stc_tim5_bconr_field_t BCONR_f; + }; + union + { + __IO uint32_t DCONR; + stc_tim5_dconr_field_t DCONR_f; + }; + uint8_t RESERVED16[4]; + union + { + __IO uint32_t FCONR; + stc_tim5_fconr_field_t FCONR_f; + }; + union + { + __IO uint32_t VPERR; + stc_tim5_vperr_field_t VPERR_f; + }; + union + { + __IO uint32_t STFLR; + stc_tim5_stflr_field_t STFLR_f; + }; + union + { + __IO uint32_t HSTAR; + stc_tim5_hstar_field_t HSTAR_f; + }; + union + { + __IO uint32_t HSTPR; + stc_tim5_hstpr_field_t HSTPR_f; + }; + union + { + __IO uint32_t HCELR; + stc_tim5_hcelr_field_t HCELR_f; + }; + union + { + __IO uint32_t HCPAR; + stc_tim5_hcpar_field_t HCPAR_f; + }; + union + { + __IO uint32_t HCPBR; + stc_tim5_hcpbr_field_t HCPBR_f; + }; + union + { + __IO uint32_t HCUPR; + stc_tim5_hcupr_field_t HCUPR_f; + }; + union + { + __IO uint32_t HCDOR; + stc_tim5_hcdor_field_t HCDOR_f; + }; + uint8_t RESERVED26[112]; + union + { + __IO uint32_t IFR; + stc_tim5_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim5_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t CR; + stc_tim5_cr_field_t CR_f; + }; + uint8_t RESERVED29[4]; + union + { + __IO uint32_t AOSSR; + stc_tim5_aossr_field_t AOSSR_f; + }; + union + { + __IO uint32_t AOSCL; + stc_tim5_aoscl_field_t AOSCL_f; + }; + union + { + __IO uint32_t PTBKS; + stc_tim5_ptbks_field_t PTBKS_f; + }; + union + { + __IO uint32_t TTRIG; + stc_tim5_ttrig_field_t TTRIG_f; + }; + union + { + __IO uint32_t ITRIG; + stc_tim5_itrig_field_t ITRIG_f; + }; + union + { + __IO uint32_t PTBKP; + stc_tim5_ptbkp_field_t PTBKP_f; + }; + uint8_t RESERVED35[716]; + union + { + __IO uint32_t SSTAR; + stc_tim5_sstar_field_t SSTAR_f; + }; + union + { + __IO uint32_t SSTPR; + stc_tim5_sstpr_field_t SSTPR_f; + }; + union + { + __IO uint32_t SCLRR; + stc_tim5_sclrr_field_t SCLRR_f; + }; +}M0P_TIM5_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CNTER; + stc_tim6_cnter_field_t CNTER_f; + }; + union + { + __IO uint32_t PERAR; + stc_tim6_perar_field_t PERAR_f; + }; + union + { + __IO uint32_t PERBR; + stc_tim6_perbr_field_t PERBR_f; + }; + uint8_t RESERVED3[4]; + union + { + __IO uint32_t GCMAR; + stc_tim6_gcmar_field_t GCMAR_f; + }; + union + { + __IO uint32_t GCMBR; + stc_tim6_gcmbr_field_t GCMBR_f; + }; + union + { + __IO uint32_t GCMCR; + stc_tim6_gcmcr_field_t GCMCR_f; + }; + union + { + __IO uint32_t GCMDR; + stc_tim6_gcmdr_field_t GCMDR_f; + }; + uint8_t RESERVED7[8]; + union + { + __IO uint32_t SCMAR; + stc_tim6_scmar_field_t SCMAR_f; + }; + union + { + __IO uint32_t SCMBR; + stc_tim6_scmbr_field_t SCMBR_f; + }; + uint8_t RESERVED9[16]; + union + { + __IO uint32_t DTUAR; + stc_tim6_dtuar_field_t DTUAR_f; + }; + union + { + __IO uint32_t DTDAR; + stc_tim6_dtdar_field_t DTDAR_f; + }; + uint8_t RESERVED11[8]; + union + { + __IO uint32_t GCONR; + stc_tim6_gconr_field_t GCONR_f; + }; + union + { + __IO uint32_t ICONR; + stc_tim6_iconr_field_t ICONR_f; + }; + union + { + __IO uint32_t PCONR; + stc_tim6_pconr_field_t PCONR_f; + }; + union + { + __IO uint32_t BCONR; + stc_tim6_bconr_field_t BCONR_f; + }; + union + { + __IO uint32_t DCONR; + stc_tim6_dconr_field_t DCONR_f; + }; + uint8_t RESERVED16[4]; + union + { + __IO uint32_t FCONR; + stc_tim6_fconr_field_t FCONR_f; + }; + union + { + __IO uint32_t VPERR; + stc_tim6_vperr_field_t VPERR_f; + }; + union + { + __IO uint32_t STFLR; + stc_tim6_stflr_field_t STFLR_f; + }; + union + { + __IO uint32_t HSTAR; + stc_tim6_hstar_field_t HSTAR_f; + }; + union + { + __IO uint32_t HSTPR; + stc_tim6_hstpr_field_t HSTPR_f; + }; + union + { + __IO uint32_t HCELR; + stc_tim6_hcelr_field_t HCELR_f; + }; + union + { + __IO uint32_t HCPAR; + stc_tim6_hcpar_field_t HCPAR_f; + }; + union + { + __IO uint32_t HCPBR; + stc_tim6_hcpbr_field_t HCPBR_f; + }; + union + { + __IO uint32_t HCUPR; + stc_tim6_hcupr_field_t HCUPR_f; + }; + union + { + __IO uint32_t HCDOR; + stc_tim6_hcdor_field_t HCDOR_f; + }; + uint8_t RESERVED26[112]; + union + { + __IO uint32_t IFR; + stc_tim6_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim6_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t CR; + stc_tim6_cr_field_t CR_f; + }; + uint8_t RESERVED29[4]; + union + { + __IO uint32_t AOSSR; + stc_tim6_aossr_field_t AOSSR_f; + }; + union + { + __IO uint32_t AOSCL; + stc_tim6_aoscl_field_t AOSCL_f; + }; + union + { + __IO uint32_t PTBKS; + stc_tim6_ptbks_field_t PTBKS_f; + }; + union + { + __IO uint32_t TTRIG; + stc_tim6_ttrig_field_t TTRIG_f; + }; + union + { + __IO uint32_t ITRIG; + stc_tim6_itrig_field_t ITRIG_f; + }; + union + { + __IO uint32_t PTBKP; + stc_tim6_ptbkp_field_t PTBKP_f; + }; + uint8_t RESERVED35[716]; + union + { + __IO uint32_t SSTAR; + stc_tim6_sstar_field_t SSTAR_f; + }; + union + { + __IO uint32_t SSTPR; + stc_tim6_sstpr_field_t SSTPR_f; + }; + union + { + __IO uint32_t SCLRR; + stc_tim6_sclrr_field_t SCLRR_f; + }; +}M0P_TIM6_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t SBUF; + stc_uart_sbuf_field_t SBUF_f; + }; + union + { + __IO uint32_t SCON; + stc_uart_scon_field_t SCON_f; + }; + union + { + __IO uint32_t SADDR; + stc_uart_saddr_field_t SADDR_f; + }; + union + { + __IO uint32_t SADEN; + stc_uart_saden_field_t SADEN_f; + }; + union + { + __IO uint32_t ISR; + stc_uart_isr_field_t ISR_f; + }; + union + { + __IO uint32_t ICR; + stc_uart_icr_field_t ICR_f; + }; + union + { + __IO uint32_t SCNT; + stc_uart_scnt_field_t SCNT_f; + }; +}M0P_UART_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[16]; + union + { + __IO uint32_t CR; + stc_vc_cr_field_t CR_f; + }; + union + { + __IO uint32_t VC0_CR; + stc_vc_vc0_cr_field_t VC0_CR_f; + }; + union + { + __IO uint32_t VC1_CR; + stc_vc_vc1_cr_field_t VC1_CR_f; + }; + union + { + __IO uint32_t VC0_OUT_CFG; + stc_vc_vc0_out_cfg_field_t VC0_OUT_CFG_f; + }; + union + { + __IO uint32_t VC1_OUT_CFG; + stc_vc_vc1_out_cfg_field_t VC1_OUT_CFG_f; + }; + union + { + __IO uint32_t IFR; + stc_vc_ifr_field_t IFR_f; + }; +}M0P_VC_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[128]; + union + { + __IO uint32_t RST; + stc_wdt_rst_field_t RST_f; + }; + union + { + __IO uint32_t CON; + stc_wdt_con_field_t CON_f; + }; +}M0P_WDT_TypeDef; + + + +#define M0P_PERIPH_BASE (0x40000000UL) +#define M0P_ADC_BASE (M0P_PERIPH_BASE + 0x00002400UL) +#define M0P_AES_BASE (M0P_PERIPH_BASE + 0x00021400UL) +#define M0P_BGR_BASE (M0P_PERIPH_BASE + 0x00002400UL) +#define M0P_CLK_TRIM_BASE (M0P_PERIPH_BASE + 0x00001800UL) +#define M0P_CRC_BASE (M0P_PERIPH_BASE + 0x00020900UL) +#define M0P_DEBUG_ACTIVE_BASE (M0P_PERIPH_BASE + 0x00002438UL) +#define M0P_DMAC_BASE (M0P_PERIPH_BASE + 0x00021000UL) +#define M0P_FLASH_BASE (M0P_PERIPH_BASE + 0x00020000UL) +#define M0P_GPIO_BASE (M0P_PERIPH_BASE + 0x00020C00UL) +#define M0P_HDIV_BASE (M0P_PERIPH_BASE + 0x00021800UL) +#define M0P_I2C0_BASE (M0P_PERIPH_BASE + 0x00000400UL) +#define M0P_I2C1_BASE (M0P_PERIPH_BASE + 0x00004400UL) +#define M0P_LCD_BASE (M0P_PERIPH_BASE + 0x00005C00UL) +#define M0P_LPTIMER_BASE (M0P_PERIPH_BASE + 0x00000F00UL) +#define M0P_LPUART0_BASE (M0P_PERIPH_BASE + 0x00000200UL) +#define M0P_LPUART1_BASE (M0P_PERIPH_BASE + 0x00004000UL) +#define M0P_LVD_BASE (M0P_PERIPH_BASE + 0x00002400UL) +#define M0P_OPA_BASE (M0P_PERIPH_BASE + 0x00002400UL) +#define M0P_PCA_BASE (M0P_PERIPH_BASE + 0x00001000UL) +#define M0P_PCNT_BASE (M0P_PERIPH_BASE + 0x00005400UL) +#define M0P_RAM_BASE (M0P_PERIPH_BASE + 0x00020400UL) +#define M0P_RESET_BASE (M0P_PERIPH_BASE + 0x0000201CUL) +#define M0P_RNG_BASE (M0P_PERIPH_BASE + 0x00004C00UL) +#define M0P_RTC_BASE (M0P_PERIPH_BASE + 0x00001400UL) +#define M0P_SPI0_BASE (M0P_PERIPH_BASE + 0x00000800UL) +#define M0P_SPI1_BASE (M0P_PERIPH_BASE + 0x00004800UL) +#define M0P_SYSCTRL_BASE (M0P_PERIPH_BASE + 0x00002000UL) +#define M0P_TIM0_MODE0_BASE (M0P_PERIPH_BASE + 0x00000C00UL) +#define M0P_TIM0_MODE1_BASE (M0P_PERIPH_BASE + 0x00000C00UL) +#define M0P_TIM0_MODE23_BASE (M0P_PERIPH_BASE + 0x00000C00UL) +#define M0P_TIM1_MODE0_BASE (M0P_PERIPH_BASE + 0x00000D00UL) +#define M0P_TIM1_MODE1_BASE (M0P_PERIPH_BASE + 0x00000D00UL) +#define M0P_TIM1_MODE23_BASE (M0P_PERIPH_BASE + 0x00000D00UL) +#define M0P_TIM2_MODE0_BASE (M0P_PERIPH_BASE + 0x00000E00UL) +#define M0P_TIM2_MODE1_BASE (M0P_PERIPH_BASE + 0x00000E00UL) +#define M0P_TIM2_MODE23_BASE (M0P_PERIPH_BASE + 0x00000E00UL) +#define M0P_TIM3_MODE0_BASE (M0P_PERIPH_BASE + 0x00005800UL) +#define M0P_TIM3_MODE1_BASE (M0P_PERIPH_BASE + 0x00005800UL) +#define M0P_TIM3_MODE23_BASE (M0P_PERIPH_BASE + 0x00005800UL) +#define M0P_TIM4_BASE (M0P_PERIPH_BASE + 0x00003000UL) +#define M0P_TIM5_BASE (M0P_PERIPH_BASE + 0x00003400UL) +#define M0P_TIM6_BASE (M0P_PERIPH_BASE + 0x00003800UL) +#define M0P_UART0_BASE (M0P_PERIPH_BASE + 0x00000000UL) +#define M0P_UART1_BASE (M0P_PERIPH_BASE + 0x00000100UL) +#define M0P_VC_BASE (M0P_PERIPH_BASE + 0x00002400UL) +#define M0P_WDT_BASE (M0P_PERIPH_BASE + 0x00000F00UL) + + +#define M0P_ADC ((M0P_ADC_TypeDef *)0x40002400UL) +#define M0P_AES ((M0P_AES_TypeDef *)0x40021400UL) +#define M0P_BGR ((M0P_BGR_TypeDef *)0x40002400UL) +#define M0P_CLK_TRIM ((M0P_CLK_TRIM_TypeDef *)0x40001800UL) +#define M0P_CRC ((M0P_CRC_TypeDef *)0x40020900UL) +#define M0P_DEBUG_ACTIVE ((M0P_DEBUG_ACTIVE_TypeDef *)0x40002438UL) +#define M0P_DMAC ((M0P_DMAC_TypeDef *)0x40021000UL) +#define M0P_FLASH ((M0P_FLASH_TypeDef *)0x40020000UL) +#define M0P_GPIO ((M0P_GPIO_TypeDef *)0x40020C00UL) +#define M0P_HDIV ((M0P_HDIV_TypeDef *)0x40021800UL) +#define M0P_I2C0 ((M0P_I2C_TypeDef *)0x40000400UL) +#define M0P_I2C1 ((M0P_I2C_TypeDef *)0x40004400UL) +#define M0P_LCD ((M0P_LCD_TypeDef *)0x40005C00UL) +#define M0P_LPTIMER ((M0P_LPTIMER_TypeDef *)0x40000F00UL) +#define M0P_LPUART0 ((M0P_LPUART_TypeDef *)0x40000200UL) +#define M0P_LPUART1 ((M0P_LPUART_TypeDef *)0x40004000UL) +#define M0P_LVD ((M0P_LVD_TypeDef *)0x40002400UL) +#define M0P_OPA ((M0P_OPA_TypeDef *)0x40002400UL) +#define M0P_PCA ((M0P_PCA_TypeDef *)0x40001000UL) +#define M0P_PCNT ((M0P_PCNT_TypeDef *)0x40005400UL) +#define M0P_RAM ((M0P_RAM_TypeDef *)0x40020400UL) +#define M0P_RESET ((M0P_RESET_TypeDef *)0x4000201CUL) +#define M0P_RNG ((M0P_RNG_TypeDef *)0x40004C00UL) +#define M0P_RTC ((M0P_RTC_TypeDef *)0x40001400UL) +#define M0P_SPI0 ((M0P_SPI_TypeDef *)0x40000800UL) +#define M0P_SPI1 ((M0P_SPI_TypeDef *)0x40004800UL) +#define M0P_SYSCTRL ((M0P_SYSCTRL_TypeDef *)0x40002000UL) +#define M0P_TIM0_MODE0 ((M0P_TIM0_MODE0_TypeDef *)0x40000C00UL) +#define M0P_TIM0_MODE1 ((M0P_TIM0_MODE1_TypeDef *)0x40000C00UL) +#define M0P_TIM0_MODE23 ((M0P_TIM0_MODE23_TypeDef *)0x40000C00UL) +#define M0P_TIM1_MODE0 ((M0P_TIM1_MODE0_TypeDef *)0x40000D00UL) +#define M0P_TIM1_MODE1 ((M0P_TIM1_MODE1_TypeDef *)0x40000D00UL) +#define M0P_TIM1_MODE23 ((M0P_TIM1_MODE23_TypeDef *)0x40000D00UL) +#define M0P_TIM2_MODE0 ((M0P_TIM2_MODE0_TypeDef *)0x40000E00UL) +#define M0P_TIM2_MODE1 ((M0P_TIM2_MODE1_TypeDef *)0x40000E00UL) +#define M0P_TIM2_MODE23 ((M0P_TIM2_MODE23_TypeDef *)0x40000E00UL) +#define M0P_TIM3_MODE0 ((M0P_TIM3_MODE0_TypeDef *)0x40005800UL) +#define M0P_TIM3_MODE1 ((M0P_TIM3_MODE1_TypeDef *)0x40005800UL) +#define M0P_TIM3_MODE23 ((M0P_TIM3_MODE23_TypeDef *)0x40005800UL) +#define M0P_TIM4 ((M0P_TIM4_TypeDef *)0x40003000UL) +#define M0P_TIM5 ((M0P_TIM5_TypeDef *)0x40003400UL) +#define M0P_TIM6 ((M0P_TIM6_TypeDef *)0x40003800UL) +#define M0P_UART0 ((M0P_UART_TypeDef *)0x40000000UL) +#define M0P_UART1 ((M0P_UART_TypeDef *)0x40000100UL) +#define M0P_VC ((M0P_VC_TypeDef *)0x40002400UL) +#define M0P_WDT ((M0P_WDT_TypeDef *)0x40000F00UL) + + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32L136_H__ */ + diff --git a/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Include/system_hc32l136.h b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Include/system_hc32l136.h new file mode 100644 index 0000000000..708eee7dbd --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Include/system_hc32l136.h @@ -0,0 +1,107 @@ +/******************************************************************************* +* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file system_hc32l136.h + ** + ** A detailed description is available at + ** @link SampleGroup Some description @endlink + ** + ** - 2018-03-09 1.0 Lux First version. + ** + ******************************************************************************/ + +#ifndef __SYSTEM_HC32L136_H__ +#define __SYSTEM_HC32L136_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************/ +/* Global pre-processor symbols/macros ('define') */ +/******************************************************************************/ +#define HWWD_DISABLE (1) + + + +/** + ****************************************************************************** + ** \brief Clock Setup macro definition + ** + ** - 0: CLOCK_SETTING_NONE - User provides own clock setting in application + ** - 1: CLOCK_SETTING_CMSIS - + ******************************************************************************/ +#define CLOCK_SETTING_NONE 0u +#define CLOCK_SETTING_CMSIS 1u + + +/******************************************************************************/ +/* */ +/* START OF USER SETTINGS HERE */ +/* =========================== */ +/* */ +/* All lines with '<<<' can be set by user. */ +/* */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/******************************************************************************/ + + +extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock) +extern void SystemInit (void); // Initialize the system +extern void SystemCoreClockUpdate (void); // Update SystemCoreClock variable + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_HC32L136_H__ */ + + + diff --git a/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Include/system_hc32l13x.h b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Include/system_hc32l13x.h new file mode 100644 index 0000000000..53575aee59 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Include/system_hc32l13x.h @@ -0,0 +1,111 @@ +/******************************************************************************* +* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file system_hc32l13x.h + ** + ** A detailed description is available at + ** @link SampleGroup Some description @endlink + ** + ** - 2019-03-01 1.0 Lux First version. + ** + ******************************************************************************/ + +#ifndef __SYSTEM_HC32L13X_H__ +#define __SYSTEM_HC32L13X_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************/ +/* Global pre-processor symbols/macros ('define') */ +/******************************************************************************/ +#define HWWD_DISABLE (1) + + + +/** + ****************************************************************************** + ** \brief Clock Setup macro definition + ** + ** - 0: CLOCK_SETTING_NONE - User provides own clock setting in application + ** - 1: CLOCK_SETTING_CMSIS - + ******************************************************************************/ +#define CLOCK_SETTING_NONE 0u +#define CLOCK_SETTING_CMSIS 1u + + +/******************************************************************************/ +/* */ +/* START OF USER SETTINGS HERE */ +/* =========================== */ +/* */ +/* All lines with '<<<' can be set by user. */ +/* */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/******************************************************************************/ + + +extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock) +extern void SystemInit (void); // Initialize the system +extern void SystemCoreClockUpdate (void); // Update SystemCoreClock variable + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_HC32L13X_H__ */ + + + + + + + diff --git a/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Source/ARM/startup_hc32l136.s b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Source/ARM/startup_hc32l136.s new file mode 100644 index 0000000000..f066d81363 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Source/ARM/startup_hc32l136.s @@ -0,0 +1,294 @@ +;/****************************************************************************** +;* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +;* +;* This software is owned and published by: +;* Huada Semiconductor Co.,Ltd ("HDSC"). +;* +;* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +;* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +;* +;* This software contains source code for use with HDSC +;* components. This software is licensed by HDSC to be adapted only +;* for use in systems utilizing HDSC components. HDSC shall not be +;* responsible for misuse or illegal use of this software for devices not +;* supported herein. HDSC is providing this software "AS IS" and will +;* not be responsible for issues arising from incorrect user implementation +;* of the software. +;* +;* Disclaimer: +;* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +;* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +;* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +;* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +;* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +;* WARRANTY OF NONINFRINGEMENT. +;* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +;* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +;* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +;* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +;* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +;* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +;* SAVINGS OR PROFITS, +;* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +;* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +;* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +;* FROM, THE SOFTWARE. +;* +;* This software may be replicated in part or whole for the licensed use, +;* with the restriction that this Disclaimer and Copyright notice must be +;* included with each copy of this software, whether used in part or whole, +;* at all times. +;*/ +;/*****************************************************************************/ + +;/*****************************************************************************/ +;/* Startup for ARM */ +;/* Version V1.0 */ +;/* Date 2018-04-15 */ +;/* Target-mcu {HC32L136} */ +;/*****************************************************************************/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + +Stack_Size EQU 0x00000200 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset + DCD NMI_Handler ; NMI + DCD HardFault_Handler ; Hard Fault + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV + DCD SysTick_Handler ; SysTick + + DCD IRQ000_Handler ; + DCD IRQ001_Handler ; + DCD IRQ002_Handler ; + DCD IRQ003_Handler ; + DCD IRQ004_Handler ; + DCD IRQ005_Handler ; + DCD IRQ006_Handler ; + DCD IRQ007_Handler ; + DCD IRQ008_Handler ; + DCD IRQ009_Handler ; + DCD IRQ010_Handler ; + DCD IRQ011_Handler ; + DCD IRQ012_Handler ; + DCD IRQ013_Handler ; + DCD IRQ014_Handler ; + DCD IRQ015_Handler ; + DCD IRQ016_Handler ; + DCD IRQ017_Handler ; + DCD IRQ018_Handler ; + DCD IRQ019_Handler ; + DCD IRQ020_Handler ; + DCD IRQ021_Handler ; + DCD IRQ022_Handler ; + DCD IRQ023_Handler ; + DCD IRQ024_Handler ; + DCD IRQ025_Handler ; + DCD IRQ026_Handler ; + DCD IRQ027_Handler ; + DCD IRQ028_Handler ; + DCD IRQ029_Handler ; + DCD IRQ030_Handler ; + DCD IRQ031_Handler ; + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + ;reset NVIC if in rom debug + LDR R0, =0x20000000 + LDR R2, =0x0 + MOVS R1, #0 ; for warning, + ADD R1, PC,#0 ; for A1609W, + CMP R1, R0 + BLS RAMCODE + + ; ram code base address. + ADD R2, R0,R2 +RAMCODE + ; reset Vector table address. + LDR R0, =0xE000ED08 + STR R2, [R0] + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT IRQ000_Handler [WEAK] + EXPORT IRQ001_Handler [WEAK] + EXPORT IRQ002_Handler [WEAK] + EXPORT IRQ003_Handler [WEAK] + EXPORT IRQ004_Handler [WEAK] + EXPORT IRQ005_Handler [WEAK] + EXPORT IRQ006_Handler [WEAK] + EXPORT IRQ007_Handler [WEAK] + EXPORT IRQ008_Handler [WEAK] + EXPORT IRQ009_Handler [WEAK] + EXPORT IRQ010_Handler [WEAK] + EXPORT IRQ011_Handler [WEAK] + EXPORT IRQ012_Handler [WEAK] + EXPORT IRQ013_Handler [WEAK] + EXPORT IRQ014_Handler [WEAK] + EXPORT IRQ015_Handler [WEAK] + EXPORT IRQ016_Handler [WEAK] + EXPORT IRQ017_Handler [WEAK] + EXPORT IRQ018_Handler [WEAK] + EXPORT IRQ019_Handler [WEAK] + EXPORT IRQ020_Handler [WEAK] + EXPORT IRQ021_Handler [WEAK] + EXPORT IRQ022_Handler [WEAK] + EXPORT IRQ023_Handler [WEAK] + EXPORT IRQ024_Handler [WEAK] + EXPORT IRQ025_Handler [WEAK] + EXPORT IRQ026_Handler [WEAK] + EXPORT IRQ027_Handler [WEAK] + EXPORT IRQ028_Handler [WEAK] + EXPORT IRQ029_Handler [WEAK] + EXPORT IRQ030_Handler [WEAK] + EXPORT IRQ031_Handler [WEAK] + + +IRQ000_Handler +IRQ001_Handler +IRQ002_Handler +IRQ003_Handler +IRQ004_Handler +IRQ005_Handler +IRQ006_Handler +IRQ007_Handler +IRQ008_Handler +IRQ009_Handler +IRQ010_Handler +IRQ011_Handler +IRQ012_Handler +IRQ013_Handler +IRQ014_Handler +IRQ015_Handler +IRQ016_Handler +IRQ017_Handler +IRQ018_Handler +IRQ019_Handler +IRQ020_Handler +IRQ021_Handler +IRQ022_Handler +IRQ023_Handler +IRQ024_Handler +IRQ025_Handler +IRQ026_Handler +IRQ027_Handler +IRQ028_Handler +IRQ029_Handler +IRQ030_Handler +IRQ031_Handler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Source/IAR/startup_hc32l136.s b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Source/IAR/startup_hc32l136.s new file mode 100644 index 0000000000..14bc83d796 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Source/IAR/startup_hc32l136.s @@ -0,0 +1,353 @@ +;******************************************************************************* +; Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +; +; This software is owned and published by: +; Huada Semiconductor Co.,Ltd ("HDSC"). +; +; BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +; BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +; +; This software contains source code for use with HDSC +; components. This software is licensed by HDSC to be adapted only +; for use in systems utilizing HDSC components. HDSC shall not be +; responsible for misuse or illegal use of this software for devices not +; supported herein. HDSC is providing this software "AS IS" and will +; not be responsible for issues arising from incorrect user implementation +; of the software. +; +; Disclaimer: +; HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +; REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +; ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +; WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +; WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +; WARRANTY OF NONINFRINGEMENT. +; HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +; NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +; LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +; LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +; INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +; INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +; SAVINGS OR PROFITS, +; EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +; YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +; INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +; FROM, THE SOFTWARE. +; +; This software may be replicated in part or whole for the licensed use, +; with the restriction that this Disclaimer and Copyright notice must be +; included with each copy of this software, whether used in part or whole, +; at all times. +;/ +;/*****************************************************************************/ +;/* Startup for IAR */ +;/* Version V1.0 */ +;/* Date 2018-04-15 */ +;/* Target-mcu M0+ Device */ +;/*****************************************************************************/ + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + SECTION .intvec:CODE:ROOT(8) + DATA +__vector_table DCD sfe(CSTACK) + DCD Reset_Handler + DCD NMI_Handler ; NMI + DCD HardFault_Handler ; Hard Fault + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall + DCD 0 ; Debug Monitor + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV + DCD SysTick_Handler ; SysTick + +; Numbered IRQ handler vectors + +; Note: renaming to device dependent ISR function names are done in + DCD IRQ000_Handler + DCD IRQ001_Handler + DCD IRQ002_Handler + DCD IRQ003_Handler + DCD IRQ004_Handler + DCD IRQ005_Handler + DCD IRQ006_Handler + DCD IRQ007_Handler + DCD IRQ008_Handler + DCD IRQ009_Handler + DCD IRQ010_Handler + DCD IRQ011_Handler + DCD IRQ012_Handler + DCD IRQ013_Handler + DCD IRQ014_Handler + DCD IRQ015_Handler + DCD IRQ016_Handler + DCD IRQ017_Handler + DCD IRQ018_Handler + DCD IRQ019_Handler + DCD IRQ020_Handler + DCD IRQ021_Handler + DCD IRQ022_Handler + DCD IRQ023_Handler + DCD IRQ024_Handler + DCD IRQ025_Handler + DCD IRQ026_Handler + DCD IRQ027_Handler + DCD IRQ028_Handler + DCD IRQ029_Handler + DCD IRQ030_Handler + DCD IRQ031_Handler + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ;reset NVIC if in rom debug + LDR R0, =0x20000000 + LDR R2, =0x0 ; vector offset + cmp PC, R0 + bls ROMCODE + + ; ram code base address. + ADD R2, R0,R2 +ROMCODE + ; reset Vector table address. + LDR R0, =0xE000ED08 + STR R2, [R0] + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK IRQ000_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ000_Handler + B IRQ000_Handler + + + PUBWEAK IRQ001_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ001_Handler + B IRQ001_Handler + + + PUBWEAK IRQ002_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ002_Handler + B IRQ002_Handler + + + PUBWEAK IRQ003_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ003_Handler + B IRQ003_Handler + + + PUBWEAK IRQ004_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ004_Handler + B IRQ004_Handler + + + PUBWEAK IRQ005_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ005_Handler + B IRQ005_Handler + + + PUBWEAK IRQ006_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ006_Handler + B IRQ006_Handler + + + PUBWEAK IRQ007_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ007_Handler + B IRQ007_Handler + + + PUBWEAK IRQ008_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ008_Handler + B IRQ008_Handler + + + PUBWEAK IRQ009_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ009_Handler + B IRQ009_Handler + + + PUBWEAK IRQ010_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ010_Handler + B IRQ010_Handler + + + PUBWEAK IRQ011_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ011_Handler + B IRQ011_Handler + + + PUBWEAK IRQ012_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ012_Handler + B IRQ012_Handler + + + PUBWEAK IRQ013_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ013_Handler + B IRQ013_Handler + + + PUBWEAK IRQ014_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ014_Handler + B IRQ014_Handler + + + PUBWEAK IRQ015_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ015_Handler + B IRQ015_Handler + + + PUBWEAK IRQ016_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ016_Handler + B IRQ016_Handler + + + PUBWEAK IRQ017_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ017_Handler + B IRQ017_Handler + + + PUBWEAK IRQ018_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ018_Handler + B IRQ018_Handler + + + PUBWEAK IRQ019_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ019_Handler + B IRQ019_Handler + + + PUBWEAK IRQ020_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ020_Handler + B IRQ020_Handler + + + PUBWEAK IRQ021_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ021_Handler + B IRQ021_Handler + + + PUBWEAK IRQ022_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ022_Handler + B IRQ022_Handler + + + PUBWEAK IRQ023_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ023_Handler + B IRQ023_Handler + + + PUBWEAK IRQ024_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ024_Handler + B IRQ024_Handler + + + PUBWEAK IRQ025_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ025_Handler + B IRQ025_Handler + + + PUBWEAK IRQ026_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ026_Handler + B IRQ026_Handler + + + PUBWEAK IRQ027_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ027_Handler + B IRQ027_Handler + + + PUBWEAK IRQ028_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ028_Handler + B IRQ028_Handler + + + PUBWEAK IRQ029_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ029_Handler + B IRQ029_Handler + + + PUBWEAK IRQ030_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ030_Handler + B IRQ030_Handler + + + PUBWEAK IRQ031_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ031_Handler + B IRQ031_Handler + + END diff --git a/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Source/interrupts_hc32l136.c b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Source/interrupts_hc32l136.c new file mode 100644 index 0000000000..4086444a25 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Source/interrupts_hc32l136.c @@ -0,0 +1,477 @@ +/****************************************************************************** +* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file interrupts_hc32l136.c + ** + ** Interrupt management + ** @link Driver Group Some description @endlink + ** + ** - 2018-04-15 1.0 Lux First version. + ** + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "ddl.h" +#include "interrupts_hc32l136.h" +void Gpio_IRQHandler(uint8_t u8Param); +__WEAKDEF void Dma_IRQHandler(uint8_t u8Param); +void Uart_IRQHandler(uint8_t u8Param); +__WEAKDEF void LpUart_IRQHandler(uint8_t u8Param); +__WEAKDEF void Spi_IRQHandler(uint8_t u8Param); +__WEAKDEF void I2c_IRQHandler(uint8_t u8Param); +__WEAKDEF void Tim_IRQHandler(uint8_t u8Param); +__WEAKDEF void Tim3_IRQHandler(uint8_t u8Param); +__WEAKDEF void Adt_IRQHandler(uint8_t u8Param); +__WEAKDEF void LpTim_IRQHandler(uint8_t u8Param); +__WEAKDEF void Pca_IRQHandler(uint8_t u8Param); +__WEAKDEF void Wdt_IRQHandler(uint8_t u8Param); +__WEAKDEF void Vc_IRQHandler(uint8_t u8Param); +__WEAKDEF void Rtc_IRQHandler(uint8_t u8Param); +__WEAKDEF void Adc_IRQHandler(uint8_t u8Param); +__WEAKDEF void Pcnt_IRQHandler(uint8_t u8Param); +__WEAKDEF void Lvd_IRQHandler(uint8_t u8Param); +__WEAKDEF void Lcd_IRQHandler(uint8_t u8Param); +__WEAKDEF void EfRam_IRQHandler(uint8_t u8Param); +__WEAKDEF void ClkTrim_IRQHandler(uint8_t u8Param); + +/** + ******************************************************************************* + ** \brief NVIC 中断使能 + ** + ** \param [in] enIrq 中断å·æžšä¸¾ç±»åž‹ + ** \param [in] enLevel 中断优先级枚举类型 + ** \param [in] bEn 中断开关 + ** \retval Ok 设置æˆåŠŸ + ** 其他值 设置失败 + ******************************************************************************/ +void EnableNvic(IRQn_Type enIrq, en_irq_level_t enLevel, boolean_t bEn) +{ + NVIC_ClearPendingIRQ(enIrq); + NVIC_SetPriority(enIrq, enLevel); + if (TRUE == bEn) + { + NVIC_EnableIRQ(enIrq); + } + else + { + NVIC_DisableIRQ(enIrq); + } +} + +/** + ******************************************************************************* + ** \brief NVIC hardware fault 中断实现 + ** 用于å•æ­¥è°ƒè¯•åŠŸèƒ½ + ** + ** \retval + ******************************************************************************/ +//void HardFault_Handler(void) +//{ +// volatile int a = 0; + +// while( 0 == a) +// { +// ; +// } +//} + +/** + ******************************************************************************* + ** \brief GPIO PortA 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void PORTA_IRQHandler(void) +{ + Gpio_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief GPIO PortB 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void PORTB_IRQHandler(void) +{ + Gpio_IRQHandler(1); +} + +/** + ******************************************************************************* + ** \brief GPIO PortC 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void PORTC_IRQHandler(void) +{ + Gpio_IRQHandler(2); +} + +/** + ******************************************************************************* + ** \brief GPIO PortD 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void PORTD_IRQHandler(void) +{ + Gpio_IRQHandler(3); +} + +/** + ******************************************************************************* + ** \brief DMAC 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void DMAC_IRQHandler(void) +{ + Dma_IRQHandler(0); +} + + +/** + ******************************************************************************* + ** \brief UART0 串å£0 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void UART0_IRQHandler(void) +{ + Uart_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief UART1 串å£1 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void UART1_IRQHandler(void) +{ + Uart_IRQHandler(1); +} + +/** + ******************************************************************************* + ** \brief LPUART0 低功耗串å£0 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void LPUART0_IRQHandler(void) +{ + LpUart_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief LPUART1 低功耗串å£1 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void LPUART1_IRQHandler(void) +{ + LpUart_IRQHandler(1); +} + +/** + ******************************************************************************* + ** \brief SPI0 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void SPI0_IRQHandler(void) +{ + Spi_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief SPI1 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void SPI1_IRQHandler(void) +{ + Spi_IRQHandler(1); +} + +/** + ******************************************************************************* + ** \brief I2C0 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void I2C0_IRQHandler(void) +{ + I2c_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief I2C1 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void I2C1_IRQHandler(void) +{ + I2c_IRQHandler(1); +} + +/** + ******************************************************************************* + ** \brief TIM0 基础时钟0 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void TIM0_IRQHandler(void) +{ + Tim_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief TIM1 基础时钟1 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void TIM1_IRQHandler(void) +{ + Tim_IRQHandler(1); +} + +/** + ******************************************************************************* + ** \brief TIM2 基础时钟2 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void TIM2_IRQHandler(void) +{ + Tim_IRQHandler(2); +} + +/** + ******************************************************************************* + ** \brief TIM3 基础时钟3 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void TIM3_IRQHandler(void) +{ + Tim3_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief LPTIM 低功耗时钟 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void LPTIM_IRQHandler(void) +{ + LpTim_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief TIM4 高级时钟4 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void TIM4_IRQHandler(void) +{ + Adt_IRQHandler(4); +} + +/** + ******************************************************************************* + ** \brief TIM5 高级时钟5 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void TIM5_IRQHandler(void) +{ + Adt_IRQHandler(5); +} + +/** + ******************************************************************************* + ** \brief TIM6 高级时钟6 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void TIM6_IRQHandler(void) +{ + Adt_IRQHandler(6); +} + +/** + ******************************************************************************* + ** \brief PCA 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void PCA_IRQHandler(void) +{ + Pca_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief WDT 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void WDT_IRQHandler(void) +{ + Wdt_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief RTC 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void RTC_IRQHandler(void) +{ + Rtc_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief ADC 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void ADC_IRQHandler(void) +{ + Adc_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief PCNT 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void PCNT_IRQHandler(void) +{ + Pcnt_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief 电压比较0 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void VC0_IRQHandler(void) +{ + Vc_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief 电压比较1 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void VC1_IRQHandler(void) +{ + Vc_IRQHandler(1); +} + +/** + ******************************************************************************* + ** \brief 低电压检测 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void LVD_IRQHandler(void) +{ + Lvd_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief LCD 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void LCD_IRQHandler(void) +{ + Lcd_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief RAM 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void EF_RAM_IRQHandler(void) +{ + EfRam_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief 时钟校准 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void CLKTRIM_IRQHandler(void) +{ + ClkTrim_IRQHandler(0); +} + + + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Source/system_hc32l136.h b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Source/system_hc32l136.h new file mode 100644 index 0000000000..708eee7dbd --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Source/system_hc32l136.h @@ -0,0 +1,107 @@ +/******************************************************************************* +* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file system_hc32l136.h + ** + ** A detailed description is available at + ** @link SampleGroup Some description @endlink + ** + ** - 2018-03-09 1.0 Lux First version. + ** + ******************************************************************************/ + +#ifndef __SYSTEM_HC32L136_H__ +#define __SYSTEM_HC32L136_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************/ +/* Global pre-processor symbols/macros ('define') */ +/******************************************************************************/ +#define HWWD_DISABLE (1) + + + +/** + ****************************************************************************** + ** \brief Clock Setup macro definition + ** + ** - 0: CLOCK_SETTING_NONE - User provides own clock setting in application + ** - 1: CLOCK_SETTING_CMSIS - + ******************************************************************************/ +#define CLOCK_SETTING_NONE 0u +#define CLOCK_SETTING_CMSIS 1u + + +/******************************************************************************/ +/* */ +/* START OF USER SETTINGS HERE */ +/* =========================== */ +/* */ +/* All lines with '<<<' can be set by user. */ +/* */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/******************************************************************************/ + + +extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock) +extern void SystemInit (void); // Initialize the system +extern void SystemCoreClockUpdate (void); // Update SystemCoreClock variable + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_HC32L136_H__ */ + + + diff --git a/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Source/system_hc32l13x.c b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Source/system_hc32l13x.c new file mode 100644 index 0000000000..603861ff37 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Source/system_hc32l13x.c @@ -0,0 +1,91 @@ +/******************************************************************************* +* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file system_hc32l13x.c + ** + ** System clock initialization. + ** @link SampleGroup Some description @endlink + ** + ** - 2019-03-01 1.0 Lux First version. + ** + ******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "base_types.h" +#include "hc32l136.h" +#include "system_hc32l13x.h" +#include "sysctrl.h" + +/** + ****************************************************************************** + ** System Clock Frequency (Core Clock) Variable according CMSIS + ******************************************************************************/ +uint32_t SystemCoreClock = 4000000; + + +//add clock source. +void SystemCoreClockUpdate (void) // Update SystemCoreClock variable +{ + SystemCoreClock = Sysctrl_GetHClkFreq(); +} + +/** + ****************************************************************************** + ** \brief Setup the microcontroller system. Initialize the System and update + ** the SystemCoreClock variable. + ** + ** \param none + ** \return none + ******************************************************************************/ +void SystemInit(void) +{ + SystemCoreClockUpdate(); + +} + + + + + + diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/cmsis_armcc.h b/bsp/hc32l136/Libraries/CMSIS/Include/cmsis_armcc.h new file mode 100644 index 0000000000..59f173ac71 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/cmsis_armcc.h @@ -0,0 +1,894 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.1.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/cmsis_armclang.h b/bsp/hc32l136/Libraries/CMSIS/Include/cmsis_armclang.h new file mode 100644 index 0000000000..e917f357a3 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/cmsis_armclang.h @@ -0,0 +1,1444 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/cmsis_armclang_ltm.h b/bsp/hc32l136/Libraries/CMSIS/Include/cmsis_armclang_ltm.h new file mode 100644 index 0000000000..feec324059 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1891 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/cmsis_compiler.h b/bsp/hc32l136/Libraries/CMSIS/Include/cmsis_compiler.h new file mode 100644 index 0000000000..adbf296f15 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/cmsis_gcc.h b/bsp/hc32l136/Libraries/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 0000000000..3ddcc58b69 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,2168 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/cmsis_iccarm.h b/bsp/hc32l136/Libraries/CMSIS/Include/cmsis_iccarm.h new file mode 100644 index 0000000000..12d68fd9a6 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/cmsis_iccarm.h @@ -0,0 +1,964 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.1.0 + * @date 08. May 2019 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2019 IAR Systems +// Copyright (c) 2017-2019 Arm Limited. All rights reserved. +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/cmsis_version.h b/bsp/hc32l136/Libraries/CMSIS/Include/cmsis_version.h new file mode 100644 index 0000000000..f2e2746626 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.3 + * @date 24. June 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/core_armv81mml.h b/bsp/hc32l136/Libraries/CMSIS/Include/core_armv81mml.h new file mode 100644 index 0000000000..8441e57fb1 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/core_armv81mml.h @@ -0,0 +1,2968 @@ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 15. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +#define __ARM_ARCH_8M_MAIN__ 1 // patching for now +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (0x1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/core_armv8mbl.h b/bsp/hc32l136/Libraries/CMSIS/Include/core_armv8mbl.h new file mode 100644 index 0000000000..344dca5148 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/core_armv8mbl.h @@ -0,0 +1,1921 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/core_armv8mml.h b/bsp/hc32l136/Libraries/CMSIS/Include/core_armv8mml.h new file mode 100644 index 0000000000..5ddb8aeda7 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/core_armv8mml.h @@ -0,0 +1,2835 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. September 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/core_cm0.h b/bsp/hc32l136/Libraries/CMSIS/Include/core_cm0.h new file mode 100644 index 0000000000..cafae5a0a7 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/core_cm0.h @@ -0,0 +1,952 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = 0x0U; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = 0x0U; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/core_cm0plus.h b/bsp/hc32l136/Libraries/CMSIS/Include/core_cm0plus.h new file mode 100644 index 0000000000..d104965db5 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,1085 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/core_cm1.h b/bsp/hc32l136/Libraries/CMSIS/Include/core_cm1.h new file mode 100644 index 0000000000..76b4569743 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/core_cm1.h @@ -0,0 +1,979 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.1 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/core_cm23.h b/bsp/hc32l136/Libraries/CMSIS/Include/core_cm23.h new file mode 100644 index 0000000000..b79c6af0b1 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/core_cm23.h @@ -0,0 +1,1996 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/core_cm3.h b/bsp/hc32l136/Libraries/CMSIS/Include/core_cm3.h new file mode 100644 index 0000000000..8157ca782d --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/core_cm3.h @@ -0,0 +1,1937 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/core_cm33.h b/bsp/hc32l136/Libraries/CMSIS/Include/core_cm33.h new file mode 100644 index 0000000000..7fed59a88e --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/core_cm33.h @@ -0,0 +1,2910 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/core_cm35p.h b/bsp/hc32l136/Libraries/CMSIS/Include/core_cm35p.h new file mode 100644 index 0000000000..5579c82306 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/core_cm35p.h @@ -0,0 +1,2910 @@ +/**************************************************************************//** + * @file core_cm35p.h + * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35P definitions */ +#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ + __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/core_cm4.h b/bsp/hc32l136/Libraries/CMSIS/Include/core_cm4.h new file mode 100644 index 0000000000..12c023b801 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/core_cm4.h @@ -0,0 +1,2124 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/core_cm7.h b/bsp/hc32l136/Libraries/CMSIS/Include/core_cm7.h new file mode 100644 index 0000000000..c4515d8fa3 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/core_cm7.h @@ -0,0 +1,2725 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.1.1 + * @date 28. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/core_sc000.h b/bsp/hc32l136/Libraries/CMSIS/Include/core_sc000.h new file mode 100644 index 0000000000..cf92577b63 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/core_sc000.h @@ -0,0 +1,1025 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/core_sc300.h b/bsp/hc32l136/Libraries/CMSIS/Include/core_sc300.h new file mode 100644 index 0000000000..40f3af81be --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/core_sc300.h @@ -0,0 +1,1912 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 31. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/mpu_armv7.h b/bsp/hc32l136/Libraries/CMSIS/Include/mpu_armv7.h new file mode 100644 index 0000000000..66ef59b4a0 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/mpu_armv7.h @@ -0,0 +1,272 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/mpu_armv8.h b/bsp/hc32l136/Libraries/CMSIS/Include/mpu_armv8.h new file mode 100644 index 0000000000..0041d4dc6f --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/mpu_armv8.h @@ -0,0 +1,346 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Msk) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/tz_context.h b/bsp/hc32l136/Libraries/CMSIS/Include/tz_context.h new file mode 100644 index 0000000000..0d09749f3a --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/adc.h b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/adc.h new file mode 100644 index 0000000000..b0f79183f1 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/adc.h @@ -0,0 +1,486 @@ +/****************************************************************************** +* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file adc.h + ** + ** Header file for AD Converter functions + ** @link ADC Group Some description @endlink + ** + ** - 2017-06-28 Alex First Version + ** + ******************************************************************************/ + +#ifndef __ADC_H__ +#define __ADC_H__ + + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "ddl.h" +#include "interrupts_hc32l136.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ****************************************************************************** + ** \defgroup AdcGroup AD Converter (ADC) + ** + ******************************************************************************/ + +//@{ + +/****************************************************************************** + * Global definitions + ******************************************************************************/ +#define ADC_SCAN_CH0_EN (0x1u) /*!< SCAN模å¼ä½¿ç”¨ADC CH0 */ +#define ADC_SCAN_CH1_EN (0x1u<<1) /*!< SCAN模å¼ä½¿ç”¨ADC CH1 */ +#define ADC_SCAN_CH2_EN (0x1u<<2) /*!< SCAN模å¼ä½¿ç”¨ADC CH2 */ +#define ADC_SCAN_CH3_EN (0x1u<<3) /*!< SCAN模å¼ä½¿ç”¨ADC CH3 */ +#define ADC_SCAN_CH4_EN (0x1u<<4) /*!< SCAN模å¼ä½¿ç”¨ADC CH4 */ +#define ADC_SCAN_CH5_EN (0x1u<<5) /*!< SCAN模å¼ä½¿ç”¨ADC CH5 */ +#define ADC_SCAN_CH6_EN (0x1u<<6) /*!< SCAN模å¼ä½¿ç”¨ADC CH6 */ +#define ADC_SCAN_CH7_EN (0x1u<<7) /*!< SCAN模å¼ä½¿ç”¨ADC CH7 */ + + +/****************************************************************************** + ** Global type definitions + *****************************************************************************/ + + /** + ****************************************************************************** + ** \brief ADCé‡‡æ ·æ¨¡å¼ + *****************************************************************************/ +typedef enum en_adc_op_mode +{ + AdcSglMode = 0u, /*!< å•è¾“入通é“å•æ¬¡é‡‡æ ·æ¨¡å¼ */ + AdcSCanMode = 1u, /*!< 多输入通é“顺åºæ‰«æ采样模å¼,多输入通é“æ’队扫æ采样模å¼*/ +} en_adc_op_mode_t; + +/** + ****************************************************************************** + ** \brief ADC时钟选择 + *****************************************************************************/ +typedef enum en_adc_clk_sel +{ + AdcClkSysTDiv1 = 0u, /*!< PCLK */ + AdcClkSysTDiv2 = 1u, /*!< 1/2 PCLK */ + AdcClkSysTDiv4 = 2u, /*!< 1/4 PCLK */ + AdcClkSysTDiv8 = 3u, /*!< 1/8 PCLK */ + +} en_adc_clk_div_t; + +/** + ****************************************************************************** + ** \brief ADCå‚考电压 + *****************************************************************************/ +typedef enum en_adc_ref_vol_sel +{ + RefVolSelInBgr1p5 = 0u, /*!<内部å‚考电压1.5V(SPS<=200kHz)*/ + RefVolSelInBgr2p5 = 1u, /*!<内部å‚考电压2.5V(avdd>3V,SPS<=200kHz)*/ + RefVolSelExtern1 = 2u, /*!<外部输入(max avdd) PB01*/ + RefVolSelAVDD = 3u, /*!>4)*10) + ((x)&0x0F)) + +#define setBit(addr,offset,flag) { if( (flag) > 0u){\ + *((volatile uint32_t *)(addr)) |= ((1UL)<<(offset));\ + }else{\ + *((volatile uint32_t *)(addr)) &= (~(1UL<<(offset)));\ + }\ + } + +#define getBit(addr,offset) ((((*((volatile uint32_t *)(addr))) >> (offset)) & 1u)>0?1u:0) + +/** + ****************************************************************************** + ** Global Device Series List + ******************************************************************************/ +#define DDL_DEVICE_SERIES_HC32L136 (0u) + +/** + ****************************************************************************** + ** Global Device Package List + ******************************************************************************/ +// package definitions of HC device. +#define DDL_DEVICE_PACKAGE_HC_C (0x00u) +#define DDL_DEVICE_PACKAGE_HC_F (0x10u) +#define DDL_DEVICE_PACKAGE_HC_J (0x20u) +#define DDL_DEVICE_PACKAGE_HC_K (0x30u) + +/******************************************************************************/ +/* User Device Setting Include file */ +/******************************************************************************/ +#include "ddl_device.h" // MUST be included here! + +/** + ****************************************************************************** + ** \brief IRQ name definition for all type MCUs + ******************************************************************************/ + + #define PORTA_IRQHandler(void) IRQ000_Handler(void) + #define PORTB_IRQHandler(void) IRQ001_Handler(void) + #define PORTC_IRQHandler(void) IRQ002_Handler(void) + #define PORTD_IRQHandler(void) IRQ003_Handler(void) + #define DMAC_IRQHandler(void) IRQ004_Handler(void) + #define TIM3_IRQHandler(void) IRQ005_Handler(void) + #define UART0_IRQHandler(void) IRQ006_Handler(void) + #define UART1_IRQHandler(void) IRQ007_Handler(void) + #define LPUART0_IRQHandler(void) IRQ008_Handler(void) + #define LPUART1_IRQHandler(void) IRQ009_Handler(void) + #define SPI0_IRQHandler(void) IRQ010_Handler(void) + #define SPI1_IRQHandler(void) IRQ011_Handler(void) + #define I2C0_IRQHandler(void) IRQ012_Handler(void) + #define I2C1_IRQHandler(void) IRQ013_Handler(void) + #define TIM0_IRQHandler(void) IRQ014_Handler(void) + #define TIM1_IRQHandler(void) IRQ015_Handler(void) + #define TIM2_IRQHandler(void) IRQ016_Handler(void) + #define LPTIM_IRQHandler(void) IRQ017_Handler(void) + #define TIM4_IRQHandler(void) IRQ018_Handler(void) + #define TIM5_IRQHandler(void) IRQ019_Handler(void) + #define TIM6_IRQHandler(void) IRQ020_Handler(void) + #define PCA_IRQHandler(void) IRQ021_Handler(void) + #define WDT_IRQHandler(void) IRQ022_Handler(void) + #define RTC_IRQHandler(void) IRQ023_Handler(void) + #define ADC_IRQHandler(void) IRQ024_Handler(void) + #define PCNT_IRQHandler(void) IRQ025_Handler(void) + #define VC0_IRQHandler(void) IRQ026_Handler(void) + #define VC1_IRQHandler(void) IRQ027_Handler(void) + #define LVD_IRQHandler(void) IRQ028_Handler(void) + #define LCD_IRQHandler(void) IRQ029_Handler(void) + #define EF_RAM_IRQHandler(void) IRQ030_Handler(void) + #define CLKTRIM_IRQHandler(void) IRQ031_Handler(void) + +/******************************************************************************/ +/* Global type definitions ('typedef') */ +/******************************************************************************/ +/** + ****************************************************************************** + ** \brief Level + ** + ** Specifies levels. + ** + ******************************************************************************/ +typedef enum en_level +{ + DdlLow = 0u, ///< Low level '0' + DdlHigh = 1u ///< High level '1' +} en_level_t; + +/** + ****************************************************************************** + ** \brief Generic Flag Code + ** + ** Specifies flags. + ** + ******************************************************************************/ +typedef enum en_flag +{ + DdlClr = 0u, ///< Flag clr '0' + DdlSet = 1u ///< Flag set '1' +} en_stat_flag_t, en_irq_flag_t; +/******************************************************************************/ +/* Global variable declarations ('extern', definition in C source) */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/******************************************************************************/ + +/******************************************************************************* + * Global function prototypes + ******************************************************************************/ +extern void ddl_memclr(void* pu8Address, uint32_t u32Count); +uint32_t Log2(uint32_t u32Val); +/** + ******************************************************************************* + ** This hook is part of wait loops. + ******************************************************************************/ +extern void DDL_WAIT_LOOP_HOOK(void); + +void Debug_UartInit(void); + +void delay1ms(uint32_t u32Cnt); +void delay100us(uint32_t u32Cnt); +void delay10us(uint32_t u32Cnt); +#ifdef __cplusplus +} +#endif + +#endif /* __DDL_H__ */ + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ + diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/debug.h b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/debug.h new file mode 100644 index 0000000000..c29060d2b8 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/debug.h @@ -0,0 +1,129 @@ +/******************************************************************************* +* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file debug.h + ** + ** Headerfile for DEBUG functions + ** @link Debug Group Some description @endlink + ** + ** History: + ** - 2018-04-15 Lux First Version + ** + ******************************************************************************/ + +#ifndef __DEBUG_H__ +#define __DEBUG_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "ddl.h" +#include "interrupts_hc32l136.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ****************************************************************************** + ** \defgroup DebugGroup (DEBUG) + ** + ******************************************************************************/ +//@{ + +/** + ******************************************************************************* + ** function prototypes. + ******************************************************************************/ + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief 调试模å¼ä¸‹å„模å—工作状æ€ç±»åž‹å®šä¹‰ + ** \note + ******************************************************************************/ +typedef enum en_debug_module_active +{ + DebugTim0 = 0x001u, ///< TIM0 + DebugTim1 = 0x002u, ///< TIM1 + DebugTim2 = 0x004u, ///< TIM2 + DebugLpTim = 0x008u, ///< LPTIM + DebugTim4 = 0x010u, ///< TIM4 + DebugTim5 = 0x020u, ///< TIM5 + DebugTim6 = 0x040u, ///< TIM6 + DebugPca = 0x080u, ///< PCA + DebugWdt = 0x100u, ///< WDT + DebugRtc = 0x200u, ///< RTC + DebugTick = 0x400u, ///< TICK + DebugTim3 = 0x800u, ///< TIM3 +}en_debug_module_active_t; + +/******************************************************************************* + * Global definitions + ******************************************************************************/ + +/****************************************************************************** + * Global variable declarations ('extern', definition in C source) + ******************************************************************************/ + +/****************************************************************************** + * Global function prototypes (definition in C source) + ******************************************************************************/ +///< 在SWD调试界é¢ä¸‹ï¼Œä½¿èƒ½æ¨¡å—功能 +en_result_t Debug_ActiveEnable(en_debug_module_active_t enModule); +///< 在SWD调试界é¢ä¸‹ï¼Œæš‚åœæ¨¡å—功能 +en_result_t Debug_ActiveDisable(en_debug_module_active_t enModule); + +//@} // Debug Group + +#ifdef __cplusplus +#endif + +#endif /* __DEBUG_H__ */ +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + + diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/dmac.h b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/dmac.h new file mode 100644 index 0000000000..7e68f2547f --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/dmac.h @@ -0,0 +1,327 @@ +/***************************************************************************** +* Copyright (C) 2016, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file dma.h +** +** A detailed description is available at +** @link DmacGroup Dmac description @endlink +** +** - 2018-03-09 1.0 Hongjh First version for Device Driver Library of Dmac. +** +******************************************************************************/ +#ifndef __DMAC_H__ +#define __DMAC_H__ + +/******************************************************************************* +* Include files +******************************************************************************/ +#include "ddl.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + + /** + ******************************************************************************* + ** \defgroup DmacGroup Direct Memory Access Control(DMAC) + ** + ******************************************************************************/ + //@{ + + /******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + /** + ******************************************************************************* + ** \brief DMA Channel + ** + ******************************************************************************/ + typedef enum en_dma_channel + { + DmaCh0 = 0U, ///< DMA channel 0 + DmaCh1 = 1U, ///< DMA channel 1 + DmaChMax = 2U ///< DMA channel max + } en_dma_channel_t; + /** + ******************************************************************************* + ** \brief DMA priority + ** + ******************************************************************************/ + typedef enum en_dma_priority + { + DmaPriorityFix = 0U, ///< DMA channel priority fix (CH0>CH1) + DmaPriorityLoop = 1U, ///< DMA channel priority loop + } en_dma_priority_t; + + /** + ******************************************************************************* + ** \brief DMA transfer data width + ** + ******************************************************************************/ + typedef enum en_dma_transfer_width + { + Dma8Bit = 0U, ///< 8 bit transfer via DMA + Dma16Bit = 1U, ///< 16 bit transfer via DMA + Dma32Bit = 2U ///< 32 bit transfer via DMA + } en_dma_transfer_width_t; + + /** + ******************************************************************************* + ** \brief DMA transfer mode + ** + ******************************************************************************/ + typedef enum en_dma_transfer_mode + { + DmaBlock = 0U, ///< block transfer via DMA + DmaBurst = 1U, ///< burst transfer via DMA + } en_dma_transfer_mode_t; + + /** + ******************************************************************************* + ** \brief DMA flag + ** + ******************************************************************************/ + typedef enum en_dma_stat + { + DEFAULT = 0U, ///< Reserve + DmaAddOverflow = 1U, ///< DMA address overflow + DmaHALT = 2U, ///< DMA HALT + DmaAccSCRErr = 3U, ///< DMA access source address error + DmaAccDestErr = 4U, ///< DMA access dest address error + DmaTransferComplete = 5U, ///< DMA transfer complete + DmaTransferPause = 7U, ///< DMA transfer pause + } en_dma_stat_t; + + /** + ******************************************************************************* + ** \brief DMA address mode + ** + ******************************************************************************/ + typedef enum en_address_mode + { + AddressIncrease = 0U, ///< Address increased + AddressFix = 1U, ///< Address fixed + } en_address_mode_t; + + /** + ******************************************************************************* + ** \brief DMA repeat tranfer + ** + ******************************************************************************/ + typedef enum en_dma_msk + { + OneTranfer = 0U, ///< One Tranfer + ContinuousTranfer = 1U, ///< Continuous Tranfer + } en_dma_msk_t; + /** + ******************************************************************************* + ** \brief DMA trigger selection + ** + ******************************************************************************/ + typedef enum stc_dma_trig_sel + { + SWTrig = 0U, ///< Select DMA software trig + SPI0RXTrig = 32U, ///< Select DMA hardware trig 0 + SPI0TXTrig = 33U, ///< Select DMA hardware trig 1 + SPI1RXTrig = 34U, ///< Select DMA hardware trig 2 + SPI1TXTrig = 35U, ///< Select DMA hardware trig 3 + ADCJQRTrig = 36U, ///< Select DMA hardware trig 4 + ADCSQRTrig = 37U, ///< Select DMA hardware trig 5 + LCDTxTrig = 38U, ///< Select DMA hardware trig 6 + Uart0RxTrig = 40U, ///< Select DMA hardware trig 8 + Uart0TxTrig = 41U, ///< Select DMA hardware trig 9 + Uart1RxTrig = 42U, ///< Select DMA hardware trig 10 + Uart1TxTrig = 43U, ///< Select DMA hardware trig 11 + LpUart0RxTrig = 44U, ///< Select DMA hardware trig 12 + LpUart0TxTrig = 45U, ///< Select DMA hardware trig 13 + LpUart1RxTrig = 46U, ///< Select DMA hardware trig 14 + LpUart1TxTrig = 47U, ///< Select DMA hardware trig 15 + TIM0ATrig = 50U, ///< Select DMA hardware trig 18 + TIM0BTrig = 51U, ///< Select DMA hardware trig 19 + TIM1ATrig = 52U, ///< Select DMA hardware trig 20 + TIM1BTrig = 53U, ///< Select DMA hardware trig 21 + TIM2ATrig = 54U, ///< Select DMA hardware trig 22 + TIM2BTrig = 55U, ///< Select DMA hardware trig 23 + TIM3ATrig = 56U, ///< Select DMA hardware trig 24 + TIM3BTrig = 57U, ///< Select DMA hardware trig 25 + TIM4ATrig = 58U, ///< Select DMA hardware trig 26 + TIM4BTrig = 59U, ///< Select DMA hardware trig 27 + TIM5ATrig = 60U, ///< Select DMA hardware trig 28 + TIM5BTrig = 61U, ///< Select DMA hardware trig 29 + TIM6ATrig = 62U, ///< Select DMA hardware trig 30 + TIM6BTrig = 63U, ///< Select DMA hardware trig 31 + }en_dma_trig_sel_t; + /** + ******************************************************************************* + ** \brief DMA interrupt selection + ** + ******************************************************************************/ +typedef struct stc_dma_irq + { + boolean_t TrnErrIrq; ///< Select DMA transfer error interrupt + boolean_t TrnCpltIrq; ///< Select DMA transfer completion interrupt + }stc_dma_irq_sel_t; + + + + /** + ******************************************************************************* + ** \brief DMA configuration + ** + ******************************************************************************/ + typedef struct stc_dma_config + { + en_dma_transfer_mode_t enMode; + + uint16_t u16BlockSize; ///< Transfer Block counter + uint16_t u16TransferCnt; ///< Transfer counter + en_dma_transfer_width_t enTransferWidth; ///< DMA transfer width (see #en_dma_transfer_width_t for details) + + en_address_mode_t enSrcAddrMode; ///< Source address mode(see #en_source_address_mode_t for details) + en_address_mode_t enDstAddrMode; ///< Destination address mode(see #en_dest_address_mode_t for details) + + boolean_t bSrcAddrReloadCtl; ///< Source address reload(TRUE: reload;FALSE: reload forbidden) + boolean_t bDestAddrReloadCtl; ///< Dest address reload(TRUE: reload;FALSE: reload forbidden) + boolean_t bSrcBcTcReloadCtl; ///< Bc/Tc address reload(TRUE: reload;FALSE: reload forbidden) + uint32_t u32SrcAddress; ///< Source address> + uint32_t u32DstAddress; ///< Dest address> + boolean_t bMsk; ///0: clear the bit (CONFA:ENS) after tarnfer;1: remain the bit (CONFA:ENS) after tarnfer + + en_dma_trig_sel_t enRequestNum; ///< DMA trigger request number + } stc_dma_config_t; + /** + ****************************************************************************** + ** \brief DMA中断回调函数 + *****************************************************************************/ +typedef struct stc_dma_irq_calbakfn_pt +{ + /*! Dma传输完æˆä¸­æ–­å›žè°ƒå‡½æ•°æŒ‡é’ˆ*/ + func_ptr_t pfnDma0TranferCompleteIrq; + /*! Dma传输完æˆä¸­æ–­å›žè°ƒå‡½æ•°æŒ‡é’ˆ*/ + func_ptr_t pfnDma1TranferCompleteIrq; + /*! Dma传输错误中断回调函数指针*/ + func_ptr_t pfnDma0TranferErrIrq; + /*! Dma传输错误中断回调函数指针*/ + func_ptr_t pfnDma1TranferErrIrq; +}stc_dma_irq_calbakfn_pt_t; + /******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + + /******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + + /******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + en_result_t Dma_InitChannel(en_dma_channel_t enCh, stc_dma_config_t* pstcConfig); + + void Dma_SwTrigger(en_dma_channel_t enCh); + + void Dma_Enable(void); + void Dma_Disable(void); + + void Dma_Start(en_dma_channel_t enCh); + void Dma_Stop(en_dma_channel_t enCh); + + en_result_t Dma_EnableChannel(en_dma_channel_t enCh); + en_result_t Dma_DisableChannel(en_dma_channel_t enCh); + + en_result_t Dma_SetTriggerSel(en_dma_channel_t enCh, en_dma_trig_sel_t enTrgSel); + + en_result_t Dma_SetSourceAddress(en_dma_channel_t enCh, uint32_t u32Address); + en_result_t Dma_SetDestinationAddress(en_dma_channel_t enCh, uint32_t u32Address); + + en_result_t Dma_SetBlockSize(en_dma_channel_t enCh, uint16_t u16BlkSize); + en_result_t Dma_SetTransferCnt(en_dma_channel_t enCh, uint16_t u16TrnCnt); + + + en_result_t Dma_SetSourceIncMode(en_dma_channel_t enCh, en_address_mode_t enMode); + en_result_t Dma_SetDestinationIncMode(en_dma_channel_t enCh, en_address_mode_t enMode); + + en_result_t Dma_EnableSourceRload(en_dma_channel_t enCh); + en_result_t Dma_DisableSourceRload(en_dma_channel_t enCh); + + en_result_t Dma_EnableDestinationRload(en_dma_channel_t enCh); + en_result_t Dma_DisableDestinationRload(en_dma_channel_t enCh); + + en_result_t Dma_EnableContinusTranfer(en_dma_channel_t enCh); + en_result_t Dma_DisableContinusTranfer(en_dma_channel_t enCh); + + en_result_t Dma_EnableBcTcReload(en_dma_channel_t enCh); + en_result_t Dma_DisableBcTcReload(en_dma_channel_t enCh); + + void Dma_HaltTranfer(void); + void Dma_RecoverTranfer(void); + en_result_t Dma_PauseChannelTranfer(en_dma_channel_t enCh); + en_result_t Dma_RecoverChannelTranfer(en_dma_channel_t enCh); + + en_result_t Dma_SetTransferWidth(en_dma_channel_t enCh, en_dma_transfer_width_t enWidth); + + en_result_t Dma_SetChPriority(en_dma_priority_t enPrio); + + en_result_t Dma_EnableChannelIrq(en_dma_channel_t enCh); + en_result_t Dma_DisableChannelIrq(en_dma_channel_t enCh); + + en_result_t Dma_EnableChannelErrIrq(en_dma_channel_t enCh); + en_result_t Dma_DisableChannelErrIrq(en_dma_channel_t enCh); + + en_result_t Dma_ConfigIrq(en_dma_channel_t enCh,stc_dma_irq_sel_t* stcDmaIrqCfg,stc_dma_irq_calbakfn_pt_t* pstcDmaIrqCalbaks); + + + en_dma_stat_t Dma_GetStat(en_dma_channel_t enCh); + + void Dma_ClrStat(en_dma_channel_t enCh); + //@} // DmacGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __DMAC_H__ */ + +/******************************************************************************* +* EOF (not truncated) +******************************************************************************/ diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/flash.h b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/flash.h new file mode 100644 index 0000000000..106e803791 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/flash.h @@ -0,0 +1,196 @@ +/************************************************************************************* +* Copyright (C) 2016, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file flash.h + ** + ** FLASH æ•°æ®ç»“æž„åŠAPI声明. + ** + ** - 2017-05-02 LuX V1.0 + ** + ******************************************************************************/ + +#ifndef __FLASH_H__ +#define __FLASH_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "ddl.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ****************************************************************************** + ** \defgroup FlashGroup Flash Controller (Flash) + ** + ** + ******************************************************************************/ +//@{ + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ +/** + ****************************************************************************** + ** \brief Flash中断类型é‡å®šä¹‰ + *****************************************************************************/ +typedef enum en_flash_int_type +{ + FlashPCInt = 1u, ///<擦写PC地å€æŠ¥è­¦ä¸­æ–­ + FlashSlockInt = 0u, ///<擦写ä¿æŠ¤æŠ¥è­¦ä¸­æ–­ +} en_flash_int_type_t; + + +/** + ****************************************************************************** + ** \brief Flash读等待周期类型é‡å®šä¹‰ + *****************************************************************************/ +typedef enum en_flash_waitcycle +{ + FlashWaitCycle0 = 0u, ///< 读等待周期设置为0（当HCLKå°äºŽç­‰äºŽ24MHz时） + FlashWaitCycle1 = 1u, ///< 读等待周期设置为1（当HCLK大于24MHz时必须至少为1） + FlashWaitCycle2 = 2u, ///< 读等待周期设置为2（当HCK大于48MHz时必须至少为2） +} en_flash_waitcycle_t; + +/** + ****************************************************************************** + ** \brief Flash擦写ä¿æŠ¤èŒƒå›´é‡å®šä¹‰ + *****************************************************************************/ +typedef enum en_flash_sector_lock +{ + FlashSector0_3 = 0x00000001u, ///PCLK=HCLK=SystemClk=RCH4MHz +en_result_t Sysctrl_ClkDeInit(void); + +///< 系统时钟模å—的基本功能设置 +///< 注æ„：使能需è¦ä½¿ç”¨çš„时钟æºä¹‹å‰ï¼Œå¿…须优先设置目标内部时钟æºçš„TRIM值或外部时钟æºçš„频率范围 +en_result_t Sysctrl_ClkSourceEnable(en_sysctrl_clk_source_t enSource, boolean_t bFlag); + +///<外部晶振驱动é…置：系统åˆå§‹åŒ–Sysctrl_ClkInit()之åŽï¼Œå¯æ ¹æ®éœ€è¦é…置外部晶振的驱动能力，时钟åˆå§‹åŒ–Sysctrl_ClkInit()默认为最大值; +en_result_t Sysctrl_XTHDriverConfig(en_sysctrl_xtal_driver_t enDriver); +en_result_t Sysctrl_XTLDriverConfig(en_sysctrl_xtl_amp_t enAmp, en_sysctrl_xtal_driver_t enDriver); + +///<时钟稳定周期设置:系统åˆå§‹åŒ–Sysctrl_ClkInit()之åŽï¼Œå¯æ ¹æ®éœ€è¦é…置时钟开å¯åŽçš„稳定之间，默认为最大值; +en_result_t Sysctrl_SetXTHStableTime(en_sysctrl_xth_cycle_t enCycle); +en_result_t Sysctrl_SetRCLStableTime(en_sysctrl_rcl_cycle_t enCycle); +en_result_t Sysctrl_SetXTLStableTime(en_sysctrl_xtl_cycle_t enCycle); +en_result_t Sysctrl_SetPLLStableTime(en_sysctrl_pll_cycle_t enCycle); + +///<系统时钟æºåˆ‡æ¢å¹¶æ›´æ–°ç³»ç»Ÿæ—¶é’Ÿï¼šå¦‚果需è¦åœ¨ç³»ç»Ÿæ—¶é’Ÿåˆå§‹åŒ–Sysctrl_ClkInit()之åŽåˆ‡æ¢ä¸»é¢‘时钟æºï¼Œåˆ™ä½¿ç”¨è¯¥å‡½æ•°ï¼› +///< 时钟切æ¢å‰åŽï¼Œå¿…须根æ®ç›®æ ‡é¢‘率值设置Flash读等待周期，å¯é…ç½®æ’入周期为0ã€1ã€2， +///< 注æ„!!!：当HCLK大于24MHz时，FLASH等待周期æ’入必须至少为1,å¦åˆ™ç¨‹åºè¿è¡Œå¯èƒ½äº§ç”ŸæœªçŸ¥é”™è¯¯ +en_result_t Sysctrl_SysClkSwitch(en_sysctrl_clk_source_t enSource); + +///< 时钟æºé¢‘率设定：根æ®ç³»ç»Ÿæƒ…况，å•ç‹¬è®¾ç½®ä¸åŒæ—¶é’Ÿæºçš„频率值; +///< 时钟频率设置å‰ï¼Œå¿…须根æ®ç›®æ ‡é¢‘率值设置Flash读等待周期，å¯é…ç½®æ’入周期为0ã€1ã€2， +///< 其中XTL的时钟由外部晶振决定，无需设置。 +en_result_t Sysctrl_SetRCHTrim(en_sysctrl_rch_freq_t enRCHFreq); +en_result_t Sysctrl_SetRCLTrim(en_sysctrl_rcl_freq_t enRCLFreq); +en_result_t Sysctrl_SetXTHFreq(en_sysctrl_xth_freq_t enXTHFreq); +en_result_t Sysctrl_SetPLLFreq(stc_sysctrl_pll_config_t *pstcPLLCfg); + +///< 时钟分频设置:æ ¹æ®ç³»ç»Ÿæƒ…况，å•ç‹¬è®¾ç½®HCLKã€PCLK的分é…值; +en_result_t Sysctrl_SetHCLKDiv(en_sysctrl_hclk_div_t enHCLKDiv); +en_result_t Sysctrl_SetPCLKDiv(en_sysctrl_pclk_div_t enPCLKDiv); + +///< 时钟频率获å–：根æ®ç³»ç»Ÿéœ€è¦ï¼ŒèŽ·å–当å‰HCLKåŠPCLK的频率值 +uint32_t Sysctrl_GetHClkFreq(void); +uint32_t Sysctrl_GetPClkFreq(void); + +///< 外设门控开关/状æ€èŽ·å–：用于控制外设模å—的使能，使用该模å—的功能之å‰ï¼Œå¿…须使能该模å—的门控时钟； +en_result_t Sysctrl_SetPeripheralGate(en_sysctrl_peripheral_gate_t enPeripheral, boolean_t bFlag); +boolean_t Sysctrl_GetPeripheralGate(en_sysctrl_peripheral_gate_t enPeripheral); + +///< 系统功能é…置：用于设置其他系统相关特殊功能； +en_result_t Sysctrl_SetFunc(en_sysctrl_func_t enFunc, boolean_t bFlag); + +///< RTC高速时钟补å¿:用于设置RTCé«˜é€Ÿæ—¶é’Ÿä¸‹çš„é¢‘çŽ‡è¡¥å¿ +en_result_t Sysctrl_SetRTCAdjustClkFreq(en_sysctrl_rtc_adjust_t enRtcAdj); + +//@} // Sysctrl Group + +#ifdef __cplusplus +#endif + +#endif /* __SYSCTRL_H__ */ +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + + diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/timer0.h b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/timer0.h new file mode 100644 index 0000000000..26398b0e6b --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/timer0.h @@ -0,0 +1,788 @@ +/******************************************************************************* +* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file bt.h + ** + ** 基本定时器数æ®ç»“æž„åŠAPI声明 + ** @link BT Timer3 Group Some description @endlink + ** + ** History: + ** - 2018-04-29 Husj First Version + ** + *****************************************************************************/ + +#ifndef __TIMER0_H__ +#define __TIMER0_H__ + +/***************************************************************************** + * Include files + *****************************************************************************/ +#include "ddl.h" +#include "interrupts_hc32l136.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ****************************************************************************** + ** \defgroup Tim0Group Base Timer (BT) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Timer3 通é“定义 + *****************************************************************************/ +typedef enum en_tim0_channel +{ + Tim0CH0 = 0u, ///< Timer3通é“0 + Tim0CH1 = 1u, ///< Timer3通é“1 + Tim0CH2 = 2u, ///< Timer3通é“2 +}en_tim0_channel_t; + +/** + ****************************************************************************** + ** \brief 工作模å¼é€‰æ‹©æ•°æ®ç±»åž‹é‡å®šä¹‰ (MODE)(模å¼0/1/23) + *****************************************************************************/ +typedef enum en_tim0_work_mode +{ + Tim0WorkMode0 = 0u, ///< å®šæ—¶å™¨æ¨¡å¼ + Tim0WorkMode1 = 1u, ///< PWCæ¨¡å¼ + Tim0WorkMode2 = 2u, ///< é”¯é½¿æ³¢æ¨¡å¼ + Tim0WorkMode3 = 3u, ///< ä¸‰è§’æ³¢æ¨¡å¼ +}en_tim0_work_mode_t; + +/** + ****************************************************************************** + ** \brief æžæ€§æŽ§åˆ¶æ•°æ®ç±»åž‹é‡å®šä¹‰ (GATE_P)(模å¼0) + *****************************************************************************/ +typedef enum en_tim0_m0cr_gatep +{ + Tim0GatePositive = 0u, ///< 高电平有效 + Tim0GateOpposite = 1u, ///< 低电平有效 +}en_tim0_m0cr_gatep_t; + +/** + ****************************************************************************** + ** \brief TIM3 预除频选择 (PRS)(模å¼0/1/23) + *****************************************************************************/ +typedef enum en_tim0_cr_timclkdiv +{ + Tim0PCLKDiv1 = 0u, ///< Div 1 + Tim0PCLKDiv2 = 1u, ///< Div 2 + Tim0PCLKDiv4 = 2u, ///< Div 4 + Tim0PCLKDiv8 = 3u, ///< Div 8 + Tim0PCLKDiv16 = 4u, ///< Div 16 + Tim0PCLKDiv32 = 5u, ///< Div 32 + Tim0PCLKDiv64 = 6u, ///< Div 64 + Tim0PCLKDiv256 = 7u, ///< Div 256 +}en_tim0_cr_timclkdiv_t; + +/** + ****************************************************************************** + ** \brief 计数/定时器功能选择数æ®ç±»åž‹é‡å®šä¹‰ (CT)(模å¼0/1/23) + *****************************************************************************/ +typedef enum en_tim0_cr_ct +{ + Tim0Timer = 0u, ///< 定时器功能，计数时钟为内部PCLK + Tim0Counter = 1u, ///< 计数器功能，计数时钟为外部ETR +}en_tim0_cr_ct_t; + + +/** + ****************************************************************************** + ** \brief 定时器工作模å¼æ•°æ®ç±»åž‹é‡å®šä¹‰ (MD)(模å¼0) + *****************************************************************************/ +typedef enum en_tim0_m0cr_md +{ + Tim032bitFreeMode = 0u, ///< 32ä½è®¡æ•°å™¨/定时器 + Tim016bitArrMode = 1u, ///< 自动é‡è£…è½½16ä½è®¡æ•°å™¨/定时器 +}en_tim0_m0cr_md_t; + +/** + ****************************************************************************** +** \brief TIM3中断类型数æ®ç±»åž‹é‡å®šä¹‰(模å¼0/1/23) + *****************************************************************************/ +typedef enum en_tim0_irq_type +{ + Tim0UevIrq = 0u, ///< 溢出/事件更新中断 + Tim0CA0Irq = 2u, ///< CH0Aæ•èŽ·/比较中断(仅模å¼1/23存在) + Tim0CA1Irq = 3u, ///< CH1Aæ•èŽ·/比较中断(仅模å¼23存在) + Tim0CA2Irq = 4u, ///< CH2Aæ•èŽ·/比较中断(仅模å¼23存在) + Tim0CB0Irq = 5u, ///< CH0Bæ•èŽ·/比较中断(仅模å¼23存在) + Tim0CB1Irq = 6u, ///< CH1Bæ•èŽ·/比较中断(仅模å¼23存在) + Tim0CB2Irq = 7u, ///< CH2Bæ•èŽ·/比较中断(仅模å¼23存在) + Tim0CA0E = 8u, ///< CH0Aæ•èŽ·æ•°æ®ä¸¢å¤±æ ‡å¿—(仅模å¼23存在)(ä¸æ˜¯ä¸­æ–­) + Tim0CA1E = 9u, ///< CH1Aæ•èŽ·æ•°æ®ä¸¢å¤±æ ‡å¿—(仅模å¼23存在)(ä¸æ˜¯ä¸­æ–­) + Tim0CA2E = 10u, ///< CH2Aæ•èŽ·æ•°æ®ä¸¢å¤±æ ‡å¿—(仅模å¼23存在)(ä¸æ˜¯ä¸­æ–­) + Tim0CB0E = 11u, ///< CH0Bæ•èŽ·æ•°æ®ä¸¢å¤±æ ‡å¿—(仅模å¼23存在)(ä¸æ˜¯ä¸­æ–­) + Tim0CB1E = 12u, ///< CH1Bæ•èŽ·æ•°æ®ä¸¢å¤±æ ‡å¿—(仅模å¼23存在)(ä¸æ˜¯ä¸­æ–­) + Tim0CB2E = 13u, ///< CH2Bæ•èŽ·æ•°æ®ä¸¢å¤±æ ‡å¿—(仅模å¼23存在)(ä¸æ˜¯ä¸­æ–­) + Tim0BkIrq = 14u, ///< 刹车中断(仅模å¼23存在） + Tim0TrigIrq = 15u, ///< 触å‘中断(仅模å¼23存在） +}en_tim0_irq_type_t; + +/** + ****************************************************************************** + ** \brief 测é‡å¼€å§‹ç»“æŸæ•°æ®ç±»åž‹é‡å®šä¹‰ (Edg1stEdg2nd)(模å¼1) + *****************************************************************************/ +typedef enum en_tim0_m1cr_Edge +{ + Tim0PwcRiseToRise = 0u, ///< 上å‡æ²¿åˆ°ä¸Šå‡æ²¿(周期) + Tim0PwcFallToRise = 1u, ///< 下é™æ²¿åˆ°ä¸Šå‡æ²¿(低电平) + Tim0PwcRiseToFall = 2u, ///< 上å‡æ²¿åˆ°ä¸‹é™æ²¿(高电平) + Tim0PwcFallToFall = 3u, ///< 下é™æ²¿åˆ°ä¸‹é™æ²¿(周期) +}en_tim0_m1cr_Edge_t; + +/** + ****************************************************************************** + ** \brief PWC测é‡æµ‹è¯•æ¨¡å¼é€‰æ‹©æ•°æ®ç±»åž‹é‡å®šä¹‰ (Oneshot)(模å¼1) + *****************************************************************************/ +typedef enum en_tim0_m1cr_oneshot +{ + Tim0PwcCycleDetect = 0u, ///< PWCå¾ªçŽ¯æµ‹é‡ + Tim0PwcOneShotDetect = 1u, ///< PWCå•æ¬¡æµ‹é‡ +}en_tim0_m1cr_oneshot_t; + +/** + ****************************************************************************** + ** \brief PWC IA0选择数æ®ç±»åž‹é‡å®šä¹‰ (IA0S)(模å¼1) + *****************************************************************************/ +typedef enum en_tim0_m1_mscr_ia0s +{ + Tim0IA0Input = 0u, ///< IAO输入 + Tim0XORInput = 1u, ///< IA0 ETR GATE XOR(TIM0/1/2)/IA0 IA1 IA2 XOR(TIM3) +}en_tim0_m1_mscr_ia0s_t; + +/** + ****************************************************************************** + ** \brief PWC IB0选择数æ®ç±»åž‹é‡å®šä¹‰ (IA0S)(模å¼1) + *****************************************************************************/ +typedef enum en_tim0_m1_mscr_ib0s +{ + Tim0IB0Input = 0u, ///< IBO输入 + Tim0TsInput = 1u, ///< 内部触å‘TSé€‰æ‹©ä¿¡å· +}en_tim0_m1_mscr_ib0s_t; + +/** + ****************************************************************************** + ** \brief 输出æžæ€§ã€è¾“å…¥ç›¸ä½ æ•°æ®ç±»åž‹é‡å®šä¹‰ (CCPA0/CCPB0/ETP/BKP)(模å¼1/23) + *****************************************************************************/ +typedef enum en_tim0_port_polarity +{ + Tim0PortPositive = 0u, ///< 正常输入输出 + Tim0PortOpposite = 1u, ///< åå‘输入输出 +}en_tim0_port_polarity_t; + +/** + ****************************************************************************** + ** \brief 滤波选择数æ®ç±»åž‹é‡å®šä¹‰ (FLTET/FLTA0/FLAB0)(模å¼1/23) + *****************************************************************************/ +typedef enum en_tim0_flt +{ + Tim0FltNone = 0u, ///< 无滤波 + Tim0FltPCLKCnt3 = 4u, ///< PCLK 3个连续有效 + Tim0FltPCLKDiv4Cnt3 = 5u, ///< PCLK/4 3个连续有效 + Tim0FltPCLKDiv16Cnt3 = 6u, ///< PCLK/16 3个连续有效 + Tim0FltPCLKDiv64Cnt3 = 7u, ///< PCLK/64 3个连续有效 +}en_tim0_flt_t; + +/** + ****************************************************************************** + ** \brief 通é“比较控制 æ•°æ®ç±»åž‹é‡å®šä¹‰ (OCMA/OCMB)(模å¼23) + *****************************************************************************/ +typedef enum en_tim0_m23_fltr_ocm +{ + Tim0ForceLow = 0u, ///< 强制为0 + Tim0ForceHigh = 1u, ///< 强制为1 + Tim0CMPForceLow = 2u, ///< 比较匹é…时强制为0 + Tim0CMPForceHigh = 3u, ///< 比较匹é…时强制为1 + Tim0CMPInverse = 4u, ///< 比较匹é…时翻转电平 + Tim0CMPOnePrdHigh = 5u, ///< 比较匹é…时输出一个计数周期的高电平 + Tim0PWMMode1 = 6u, ///< 通é“控制为PWM mode 1 + Tim0PWMMode2 = 7u, ///< 通é“控制为PWM mode 2 +}en_tim0_m23_fltr_ocm_t; + +/** + ****************************************************************************** + ** \brief 主从模å¼TSæ•°æ®ç±»åž‹é‡å®šä¹‰ (TS)(模å¼1/23) + *****************************************************************************/ +typedef enum en_tim0_mscr_ts +{ + Tim0Ts0ETR = 0u, ///< ETR外部输入滤波åŽçš„相ä½é€‰æ‹©ä¿¡å· + Tim0Ts1TIM0TRGO = 1u, ///< Timer0çš„TRGOè¾“å‡ºä¿¡å· + Tim0Ts2TIM1TRGO = 2u, ///< Timer1çš„TRGOè¾“å‡ºä¿¡å· + Tim0Ts3TIM2TRGO = 3u, ///< Timer2çš„TRGOè¾“å‡ºä¿¡å· + Tim0Ts4TIM3TRGO = 4u, ///< Timer3çš„TRGOè¾“å‡ºä¿¡å· + //Tim0Ts5IA0ED = 5u, ///< 无效 + Tim0Ts6IAFP = 6u, ///< CH0A 外部输输入滤波åŽçš„相ä½é€‰æ‹©ä¿¡å· + Tim0Ts7IBFP = 7u, ///< CH0B 外部输输入滤波åŽçš„相ä½é€‰æ‹©ä¿¡ +}en_tim0_mscr_ts_t; + +/** + ****************************************************************************** + ** \brief PWM输出模å¼é€‰æ‹©æ•°æ®ç±»åž‹é‡å®šä¹‰ (COMP)(模å¼23) + *****************************************************************************/ +typedef enum en_tim0_m23cr_comp +{ + Tim0IndependentPWM = 0u, ///< 独立PWM输出 + Tim0ComplementaryPWM = 1u, ///< 互补PWM输出 +}en_tim0_m23cr_comp_t; + +/** + ****************************************************************************** + ** \brief 计数方å‘选择数æ®ç±»åž‹é‡å®šä¹‰ (DIR)(模å¼23) + *****************************************************************************/ +typedef enum en_tim0_m23cr_dir +{ + Tim0CntUp = 0u, ///< å‘上计数 + Tim0CntDown = 1u, ///< å‘下计数 +}en_tim0_m23cr_dir_t; + +/** + ****************************************************************************** + ** \brief 计数方å‘选择数æ®ç±»åž‹é‡å®šä¹‰ (PWM2S)(模å¼23) + *****************************************************************************/ +typedef enum en_tim0_m23cr_pwm2s +{ + Tim0DoublePointCmp = 0u, ///< åŒç‚¹æ¯”较使能，使用CCRA,CCRB比较控制OCREFA输出 + Tim0SinglePointCmp = 1u, ///< å•ç‚¹æ¯”较使能，使用CCRA比较控制OCREFA输出 +}en_tim0_m23cr_pwm2s_t; + +/** + ****************************************************************************** + ** \brief GATE在PWM互补模å¼ä¸‹æ•èŽ·æˆ–比较功能 选择数æ®ç±»åž‹é‡å®šä¹‰ (CSG)(模å¼23) + *****************************************************************************/ +typedef enum en_tim0_m23cr_csg +{ + Tim0PWMCompGateCmpOut = 0u, ///< 在PWM互补模å¼ä¸‹ï¼ŒGate作为比较输出 + Tim0PWMCompGateCapIn = 1u, ///< 在PWM互补模å¼ä¸‹ï¼ŒGate作为æ•èŽ·è¾“å…¥ +}en_tim0_m23cr_csg_t; + + +/** + ****************************************************************************** + ** \brief 比较æ•èŽ·å¯„存器 æ•°æ®ç±»åž‹é‡å®šä¹‰ (CCR0A,CCR0B)(模å¼23) + *****************************************************************************/ +typedef enum en_tim0_m23_ccrx +{ + Tim0CCR0A = 0u, ///< CCR0A比较æ•èŽ·å¯„存器 + Tim0CCR0B = 1u, ///< CCR0B比较æ•èŽ·å¯„存器 + Tim0CCR1A = 2u, ///< CCR1A比较æ•èŽ·å¯„存器 + Tim0CCR1B = 3u, ///< CCR1B比较æ•èŽ·å¯„存器 + Tim0CCR2A = 4u, ///< CCR2A比较æ•èŽ·å¯„存器 + Tim0CCR2B = 5u, ///< CCR2B比较æ•èŽ·å¯„存器 +}en_tim0_m23_ccrx_t; + +/** + ****************************************************************************** + ** \brief OCREFæ¸…é™¤æº é€‰æ‹©æ•°æ®ç±»åž‹é‡å®šä¹‰ (OCCS)(模å¼23) + *****************************************************************************/ +typedef enum en_tim0_m23ce_occs +{ + Tim0OC_Ref_Clr = 0u, ///< æ¥è‡ªVCçš„OC_Ref_Clr + Tim0ETRf = 1u, ///< 外部ETRf +}en_tim0_m23ce_occs_t; + +/** + ****************************************************************************** + ** \brief 比较匹é…ä¸­æ–­æ¨¡å¼ é€‰æ‹©æ•°æ®ç±»åž‹é‡å®šä¹‰ (CIS/CISB)(模å¼23) + *****************************************************************************/ +typedef enum en_tim0_m23_cisa_cisb +{ + Tim0CmpIntNone = 0u, ///< 无比较匹é…中断 + Tim0CmpIntRise = 1u, ///< 比较匹é…上å‡æ²¿ä¸­æ–­ + Tim0CmpIntFall = 2u, ///< 比较匹é…下é™æ²¿ä¸­æ–­ + Tim0CmpIntRiseFall = 3u, ///< 比较匹é…上å‡æ²¿ä¸‹é™æ²¿ä¸­æ–­ +}en_tim0_m23_cisa_cisb_t; + +/** + ****************************************************************************** + ** \brief TIM3端å£æŽ§åˆ¶ - 刹车时CHx输出状æ€æŽ§åˆ¶(BKSA/BKSB)(模å¼23) + ** + ** \note + ******************************************************************************/ +typedef enum en_tim0_m23_crchx_bks +{ + Tim0CHxBksHiZ = 0u, ///< 刹车使能时，CHx端å£è¾“å‡ºé«˜é˜»æ€ + Tim0CHxBksNorm = 1u, ///< 刹车使能时，CHx端å£æ­£å¸¸è¾“出 + Tim0CHxBksLow = 2u, ///< 刹车使能时，CHx端å£è¾“出低电平 + Tim0CHxBksHigh = 3u, ///< 刹车使能时，CHx端å£è¾“出高电平 +}en_tim0_m23_crchx_bks_t; + +/** + ****************************************************************************** +** \brief TIM3端å£æŽ§åˆ¶ - CHx上å‡æ²¿ä¸‹é™æ²¿æ•èŽ·(CRx/CFx)(模å¼23) + ** + ** \note + ******************************************************************************/ +typedef enum en_tim0_m23_crch0_cfx_crx +{ + Tim0CHxCapNone = 0u, ///< CHx通é“æ•èŽ·ç¦æ­¢ + Tim0CHxCapRise = 1u, ///< CHx通é“上å‡æ²¿æ•èŽ·ä½¿èƒ½ + Tim0CHxCapFall = 2u, ///< CHx通é“下é™æ²¿æ•èŽ·ä½¿èƒ½ + Tim0CHxCapFallRise = 3u, ///< CHx通é“上å‡æ²¿ä¸‹é™æ²¿æ•èŽ·éƒ½ä½¿èƒ½ +}en_tim0_m23_crch0_cfx_crx_t; + +/** + ****************************************************************************** +** \brief TIM3端å£æŽ§åˆ¶ - CHx比较æ•èŽ·æ¨¡å¼(CSA/CSB)(模å¼23) + ** + ** \note + ******************************************************************************/ +typedef enum en_tim0_m23_crch0_csa_csb +{ + Tim0CHxCmpMode = 0u, ///< CHx通é“è®¾ç½®ä¸ºæ¯”è¾ƒæ¨¡å¼ + Tim0CHxCapMode = 1u, ///< CHx通é“设置为æ•èŽ·æ¨¡å¼ +}en_tim0_m23_crch0_csa_csb_t; + +/** + ****************************************************************************** + ** \brief 比较模å¼ä¸‹ DMA比较触å‘选择 æ•°æ®ç±»åž‹é‡å®šä¹‰ (CCDS)(模å¼23) + *****************************************************************************/ +typedef enum en_tim0_m23_mscr_ccds +{ + Tim0CmpTrigDMA = 0u, ///< 比较匹é…触å‘DMA + Tim0UEVTrigDMA = 1u, ///< 事件更新代替比较匹é…触å‘DMA +}en_tim0_m23_mscr_ccds_t; + +/** + ****************************************************************************** + ** \brief 主从模å¼é€‰æ‹© æ•°æ®ç±»åž‹é‡å®šä¹‰ (MSM)(模å¼23) + *****************************************************************************/ +typedef enum en_tim0_m23_mscr_msm +{ + Tim0SlaveMode = 0u, ///< ä»Žæ¨¡å¼ + Tim0MasterMode = 1u, ///< ä¸»æ¨¡å¼ +}en_tim0_m23_mscr_msm_t; + +/** + ****************************************************************************** + ** \brief 触å‘主模å¼è¾“å‡ºæº æ•°æ®ç±»åž‹é‡å®šä¹‰ (MMS)(模å¼23) + *****************************************************************************/ +typedef enum en_tim0_m23_mscr_mms +{ + Tim0MasterUG = 0u, ///< UG(软件更新)æº + Tim0MasterCTEN = 1u, ///< CTENæº + Tim0MasterUEV = 2u, ///< UEVæ›´æ–°æº + Tim0MasterCMPSO = 3u, ///< 比较匹é…é€‰æ‹©è¾“å‡ºæº + Tim0MasterOCA0Ref = 4u, ///< OCA0_Refæº + Tim0MasterOCB0Ref = 5u, ///< OCB0_Refæº + //Tim0MasterOCB0Ref = 6u, + //Tim0MasterOCB0Ref = 7u, +}en_tim0_m23_mscr_mms_t; + +/** + ****************************************************************************** + ** \brief 触å‘从模å¼é€‰æ‹© æ•°æ®ç±»åž‹é‡å®šä¹‰ (SMS)(模å¼23) + *****************************************************************************/ +typedef enum en_tim0_m23_mscr_sms +{ + Tim0SlaveIClk = 0u, ///< 使用内部时钟 + Tim0SlaveResetTIM = 1u, ///< å¤ä½åŠŸèƒ½ + Tim0SlaveTrigMode = 2u, ///< 触å‘æ¨¡å¼ + Tim0SlaveEClk = 3u, ///< å¤–éƒ¨æ—¶é’Ÿæ¨¡å¼ + Tim0SlaveCodeCnt1 = 4u, ///< 正交编ç è®¡æ•°æ¨¡å¼1 + Tim0SlaveCodeCnt2 = 5u, ///< 正交编ç è®¡æ•°æ¨¡å¼2 + Tim0SlaveCodeCnt3 = 6u, ///< 正交编ç è®¡æ•°æ¨¡å¼3 + Tim0SlaveGateCtrl = 7u, ///< 门控功能 +}en_tim0_m23_mscr_sms_t; + +/** + ****************************************************************************** + ** \brief 定时器è¿è¡ŒæŽ§åˆ¶æ•°æ®ç±»åž‹é‡å®šä¹‰ (CTEN) + *****************************************************************************/ +typedef enum en_tim0_start +{ + Tim0CTENDisable = 0u, ///< åœæ­¢ + Tim0CTENEnable = 1u, ///< è¿è¡Œ +}en_tim0_start_t; + +/** + ****************************************************************************** + ** \brief TIM3 mode0 é…置结构体定义(模å¼0) + *****************************************************************************/ +typedef struct stc_tim0_mode0_config +{ + en_tim0_work_mode_t enWorkMode; ///< 工作模å¼è®¾ç½® + en_tim0_m0cr_gatep_t enGateP; ///< 门控æžæ€§æŽ§åˆ¶ + boolean_t bEnGate; ///< 门控使能 + en_tim0_cr_timclkdiv_t enPRS; ///< 预除频é…ç½® + boolean_t bEnTog; ///< 翻转输出使能 + en_tim0_cr_ct_t enCT; ///< 定时/计数功能选择 + en_tim0_m0cr_md_t enCntMode; ///< 计数模å¼é…ç½® + + func_ptr_t pfnTim0Cb; ///< Timer3中断æœåŠ¡å›žè°ƒå‡½æ•°[void function(void)] +}stc_tim0_mode0_config_t; + +/** + ****************************************************************************** + ** \brief TIM3 mode1 é…置结构体定义(模å¼1) + *****************************************************************************/ +typedef struct stc_tim0_mode1_config +{ + en_tim0_work_mode_t enWorkMode; ///< 工作模å¼è®¾ç½® + en_tim0_cr_timclkdiv_t enPRS; ///< 预除频é…ç½® + en_tim0_cr_ct_t enCT; ///< 定时/计数功能选择 + en_tim0_m1cr_oneshot_t enOneShot; ///< å•æ¬¡æµ‹é‡/循环测é‡é€‰æ‹© + + func_ptr_t pfnTim0Cb; ///< Timer3中断æœåŠ¡å›žè°ƒå‡½æ•°[void function(void)] + +}stc_tim0_mode1_config_t; + +/** + ****************************************************************************** + ** \brief PWC输入é…置结构体定义(模å¼1) + *****************************************************************************/ +typedef struct stc_tim0_pwc_input_config +{ + en_tim0_mscr_ts_t enTsSel; ///< 触å‘输入æºé€‰æ‹© + en_tim0_m1_mscr_ia0s_t enIA0Sel; ///< CHA0输入选择 + en_tim0_m1_mscr_ib0s_t enIB0Sel; ///< CHB0输入选择 + en_tim0_port_polarity_t enETRPhase; ///< ETR相ä½é€‰æ‹© + en_tim0_flt_t enFltETR; ///< ETR滤波设置 + en_tim0_flt_t enFltIA0; ///< CHA0滤波设置 + en_tim0_flt_t enFltIB0; ///< CHB0滤波设置 +}stc_tim0_pwc_input_config_t; + +/** + ****************************************************************************** + ** \brief TIM3 mode23 é…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim0_mode23_config +{ + en_tim0_work_mode_t enWorkMode; ///< 工作模å¼è®¾ç½® + en_tim0_m23cr_dir_t enCntDir; ///< è®¡æ•°æ–¹å‘ + en_tim0_cr_timclkdiv_t enPRS; ///< 时钟预除频é…ç½® + en_tim0_cr_ct_t enCT; ///< 定时/计数功能选择 + en_tim0_m23cr_comp_t enPWMTypeSel; ///< PWM模å¼é€‰æ‹©ï¼ˆç‹¬ç«‹/互补） + en_tim0_m23cr_pwm2s_t enPWM2sSel; ///< OCREFAåŒç‚¹æ¯”较功能选择 + boolean_t bOneShot; ///< å•æ¬¡è§¦å‘模å¼ä½¿èƒ½/ç¦æ­¢ + boolean_t bURSSel; ///< æ›´æ–°æºé€‰æ‹© + + func_ptr_t pfnTim0Cb; ///< Timer3中断æœåŠ¡å›žè°ƒå‡½æ•°[void function(void)] +}stc_tim0_mode23_config_t; + +/** + ****************************************************************************** + ** \brief GATE在PWM互补模å¼ä¸‹æ•èŽ·æˆ–比较功能 é…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim0_m23_gate_config +{ + en_tim0_m23cr_csg_t enGateFuncSel; ///< Gate比较ã€æ•èŽ·åŠŸèƒ½é€‰æ‹© + boolean_t bGateRiseCap; ///< GATE作为æ•èŽ·åŠŸèƒ½æ—¶ï¼Œä¸Šæ²¿æ•èŽ·æœ‰æ•ˆæŽ§åˆ¶ + boolean_t bGateFallCap; ///< GATE作为æ•èŽ·åŠŸèƒ½æ—¶ï¼Œä¸‹æ²¿æ•èŽ·æœ‰æ•ˆæŽ§åˆ¶ +}stc_tim0_m23_gate_config_t; + +/** + ****************************************************************************** + ** \brief CHA/CHB通é“比较控制 é…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim0_m23_compare_config +{ + en_tim0_m23_crch0_csa_csb_t enCHxACmpCap; ///< CH0A比较/æ•èŽ·åŠŸèƒ½é€‰æ‹© + en_tim0_m23_fltr_ocm_t enCHxACmpCtrl; ///< CH0A通é“比较控制 + en_tim0_port_polarity_t enCHxAPolarity; ///< CH0A输出æžæ€§æŽ§åˆ¶ + boolean_t bCHxACmpBufEn; ///< 比较A缓存功能 使能/ç¦æ­¢ + en_tim0_m23_cisa_cisb_t enCHxACmpIntSel; ///< CHA比较匹é…中断选择 + + en_tim0_m23_crch0_csa_csb_t enCHxBCmpCap; ///< CH0B比较/æ•èŽ·åŠŸèƒ½é€‰æ‹© + en_tim0_m23_fltr_ocm_t enCHxBCmpCtrl; ///< CH0B通é“比较控制 + en_tim0_port_polarity_t enCHxBPolarity; ///< CH0B输出æžæ€§æŽ§åˆ¶ + boolean_t bCHxBCmpBufEn; ///< 比较B缓存功能 使能/ç¦æ­¢ + en_tim0_m23_cisa_cisb_t enCHxBCmpIntSel; ///< CHB0比较匹é…中断选择 +}stc_tim0_m23_compare_config_t; + +/** + ****************************************************************************** + ** \brief CHA/CHB通é“æ•èŽ·æŽ§åˆ¶ é…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim0_m23_input_config +{ + en_tim0_m23_crch0_csa_csb_t enCHxACmpCap; ///< CH0A比较/æ•èŽ·åŠŸèƒ½é€‰æ‹© + en_tim0_m23_crch0_cfx_crx_t enCHxACapSel; ///< CH0Aæ•èŽ·è¾¹æ²¿é€‰æ‹© + en_tim0_flt_t enCHxAInFlt; ///< CH0A通é“æ•èŽ·æ»¤æ³¢æŽ§åˆ¶ + en_tim0_port_polarity_t enCHxAPolarity; ///< CH0Aè¾“å…¥ç›¸ä½ + + en_tim0_m23_crch0_csa_csb_t enCHxBCmpCap; ///< CH0A比较/æ•èŽ·åŠŸèƒ½é€‰æ‹© + en_tim0_m23_crch0_cfx_crx_t enCHxBCapSel; ///< CH0Bæ•èŽ·è¾¹æ²¿é€‰æ‹© + en_tim0_flt_t enCHxBInFlt; ///< CH0B通é“æ•èŽ·æ»¤æ³¢æŽ§åˆ¶ + en_tim0_port_polarity_t enCHxBPolarity; ///< CH0Bè¾“å…¥ç›¸ä½ + +}stc_tim0_m23_input_config_t; + +/** + ****************************************************************************** + ** \brief ETR输入相ä½æ»¤æ³¢é…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim0_m23_etr_input_config +{ + en_tim0_port_polarity_t enETRPolarity; ///< ETR输入æžæ€§è®¾ç½® + en_tim0_flt_t enETRFlt; ///< ETR滤波设置 +}stc_tim0_m23_etr_input_config_t; + +/** + ****************************************************************************** + ** \brief 刹车BK输入相ä½æ»¤æ³¢é…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim0_m23_bk_input_config +{ + boolean_t bEnBrake; ///< 刹车使能 + boolean_t bEnVC0Brake; ///< 使能VC0刹车 + boolean_t bEnVC1Brake; ///< 使能VC1刹车 + boolean_t bEnSafetyBk; ///< 使能safety刹车 + boolean_t bEnBKSync; ///< TIM0/TIM1/TIM2刹车åŒæ­¥ä½¿èƒ½ + en_tim0_m23_crchx_bks_t enBkCH0AStat; ///< 刹车时CHA端å£çŠ¶æ€è®¾ç½® + en_tim0_m23_crchx_bks_t enBkCH0BStat; ///< 刹车时CHB端å£çŠ¶æ€è®¾ç½® + en_tim0_m23_crchx_bks_t enBkCH1AStat; ///< 刹车时CHA端å£çŠ¶æ€è®¾ç½® + en_tim0_m23_crchx_bks_t enBkCH1BStat; ///< 刹车时CHB端å£çŠ¶æ€è®¾ç½® + en_tim0_m23_crchx_bks_t enBkCH2AStat; ///< 刹车时CHA端å£çŠ¶æ€è®¾ç½® + en_tim0_m23_crchx_bks_t enBkCH2BStat; ///< 刹车时CHB端å£çŠ¶æ€è®¾ç½® + en_tim0_port_polarity_t enBrakePolarity; ///< 刹车BK输入æžæ€§è®¾ç½® + en_tim0_flt_t enBrakeFlt; ///< 刹车BK滤波设置 +}stc_tim0_m23_bk_input_config_t; + +/** + ****************************************************************************** +** \brief 死区功能é…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim0_m23_dt_config +{ + boolean_t bEnDeadTime; ///< 刹车时CHA端å£çŠ¶æ€è®¾ç½® + uint8_t u8DeadTimeValue; ///< 刹车时CHA端å£çŠ¶æ€è®¾ç½® +}stc_tim0_m23_dt_config_t; + +/** + ****************************************************************************** + ** \brief 触å‘ADCé…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim0_m23_adc_trig_config +{ + boolean_t bEnTrigADC; ///< 触å‘ADC全局控制 + boolean_t bEnUevTrigADC; ///< 事件更新触å‘ADC + boolean_t bEnCH0ACmpTrigADC; ///< CH0A比较匹é…触å‘ADC + boolean_t bEnCH0BCmpTrigADC; ///< CH0B比较匹é…触å‘ADC + boolean_t bEnCH1ACmpTrigADC; ///< CH0A比较匹é…触å‘ADC + boolean_t bEnCH1BCmpTrigADC; ///< CH0B比较匹é…触å‘ADC + boolean_t bEnCH2ACmpTrigADC; ///< CH0A比较匹é…触å‘ADC + boolean_t bEnCH2BCmpTrigADC; ///< CH0B比较匹é…触å‘ADC +}stc_tim0_m23_adc_trig_config_t; + +/** + ****************************************************************************** + ** \brief DMAè§¦å‘ é…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim0_m23_trig_dma_config +{ + boolean_t bUevTrigDMA; ///< æ›´æ–° 触å‘DMA使能 + boolean_t bTITrigDMA; ///< Trig 触å‘DMA功能 + boolean_t bCmpA0TrigDMA; ///< CH0Aæ•èŽ·æ¯”较触å‘DMA使能 + boolean_t bCmpB0TrigDMA; ///< CH0Bæ•èŽ·æ¯”较触å‘DMA使能 + boolean_t bCmpA1TrigDMA; ///< CH1Aæ•èŽ·æ¯”较触å‘DMA使能 + boolean_t bCmpB1TrigDMA; ///< CH1Bæ•èŽ·æ¯”较触å‘DMA使能 + boolean_t bCmpA2TrigDMA; ///< CH2Aæ•èŽ·æ¯”较触å‘DMA使能 + boolean_t bCmpB2TrigDMA; ///< CH2Bæ•èŽ·æ¯”较触å‘DMA使能 + en_tim0_m23_mscr_ccds_t enCmpUevTrigDMA; ///< 比较模å¼ä¸‹DMA比较触å‘选择 +}stc_tim0_m23_trig_dma_config_t; + +/** + ****************************************************************************** + ** \brief ä¸»ä»Žæ¨¡å¼ é…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim0_m23_master_slave_config +{ + en_tim0_m23_mscr_msm_t enMasterSlaveSel; ///< 主从模å¼é€‰æ‹© + en_tim0_m23_mscr_mms_t enMasterSrc; ///< 主模å¼è§¦å‘æºé€‰æ‹© + en_tim0_m23_mscr_sms_t enSlaveModeSel; ///< 从模å¼é€‰æ‹© + en_tim0_mscr_ts_t enTsSel; ///< 触å‘输入æºé€‰æ‹© +}stc_tim0_m23_master_slave_config_t; + +/** + ****************************************************************************** + ** \brief OCREF清除功能 é…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim0_m23_OCREF_Clr_config +{ + en_tim0_m23ce_occs_t enOCRefClrSrcSel; ///< OCREF清除æºé€‰æ‹© + boolean_t bVCClrEn; ///< 是å¦ä½¿èƒ½æ¥è‡ªVCçš„OCREF_Clr +}stc_tim0_m23_OCREF_Clr_config_t; + +/****************************************************************************** + * Global variable declarations ('extern', definition in C source) + *****************************************************************************/ + +/****************************************************************************** + * Global function prototypes (definition in C source) + *****************************************************************************/ +//中断相关函数 + +//ä¸­æ–­æ ‡å¿—èŽ·å– +boolean_t Tim0_GetIntFlag(en_tim0_irq_type_t enTim0Irq); +//中断标志清除 +en_result_t Tim0_ClearIntFlag(en_tim0_irq_type_t enTim0Irq); +//所有中断标志清除 +en_result_t Tim0_ClearAllIntFlag(void); +//模å¼0中断使能 +en_result_t Tim0_Mode0_EnableIrq(void); +//模å¼1中断使能 +en_result_t Tim0_Mode1_EnableIrq (en_tim0_irq_type_t enTim0Irq); +//模å¼2中断使能 +en_result_t Tim0_Mode23_EnableIrq (en_tim0_irq_type_t enTim0Irq); +//模å¼0中断ç¦æ­¢ +en_result_t Tim0_Mode0_DisableIrq(void); +//模å¼1中断ç¦æ­¢ +en_result_t Tim0_Mode1_DisableIrq (en_tim0_irq_type_t enTim0Irq); +//模å¼2中断ç¦æ­¢ +en_result_t Tim0_Mode23_DisableIrq (en_tim0_irq_type_t enTim0Irq); + + +//模å¼0åˆå§‹åŒ–åŠç›¸å…³åŠŸèƒ½æ“作 + +//timeré…ç½®åŠåˆå§‹åŒ– +en_result_t Tim0_Mode0_Init(stc_tim0_mode0_config_t* pstcConfig); +//timer å¯åŠ¨/åœæ­¢ +en_result_t Tim0_M0_Run(void); +en_result_t Tim0_M0_Stop(void); +//é‡è½½å€¼è®¾ç½® +en_result_t Tim0_M0_ARRSet(uint16_t u16Data); +//16ä½è®¡æ•°å€¼è®¾ç½®/èŽ·å– +en_result_t Tim0_M0_Cnt16Set(uint16_t u16Data); +uint16_t Tim0_M0_Cnt16Get(void); +//32ä½è®¡æ•°å€¼è®¾ç½®/èŽ·å– +en_result_t Tim0_M0_Cnt32Set(uint32_t u32Data); +uint32_t Tim0_M0_Cnt32Get(void); +//翻转输出使能/ç¦æ­¢è®¾å®š +en_result_t Tim0_M0_EnTOG_Output(boolean_t bEnOutput); + + +//模å¼1åˆå§‹åŒ–åŠç›¸å…³åŠŸèƒ½æ“作 + +//timeré…ç½®åŠåˆå§‹åŒ– +en_result_t Tim0_Mode1_Init(stc_tim0_mode1_config_t* pstcConfig); +//PWC 输入é…ç½® +en_result_t Tim0_M1_Input_Config(stc_tim0_pwc_input_config_t* pstcConfig); +//PWC测é‡è¾¹æ²¿èµ·å§‹ç»“æŸé€‰æ‹© +en_result_t Tim0_M1_PWC_Edge_Sel(en_tim0_m1cr_Edge_t enEdgeSel); +//timer å¯åŠ¨/åœæ­¢ +en_result_t Tim0_M1_Run(void); +en_result_t Tim0_M1_Stop(void); +//16ä½è®¡æ•°å€¼è®¾ç½®/èŽ·å– +en_result_t Tim0_M1_Cnt16Set(uint16_t u16Data); +uint16_t Tim0_M1_Cnt16Get(void); +//脉冲宽度测é‡ç»“æžœæ•°å€¼èŽ·å– +uint16_t Tim0_M1_PWC_CapValueGet(void); + + +//模å¼1åˆå§‹åŒ–åŠç›¸å…³åŠŸèƒ½æ“作 + +//timeré…ç½®åŠåˆå§‹åŒ– +en_result_t Tim0_Mode23_Init(stc_tim0_mode23_config_t* pstcConfig); +//timer å¯åŠ¨/åœæ­¢ +en_result_t Tim0_M23_Run(void); +en_result_t Tim0_M23_Stop(void); +//PWM输出使能 +en_result_t Tim0_M23_EnPWM_Output(boolean_t bEnOutput, boolean_t bEnAutoOutput); +//é‡è½½å€¼è®¾ç½® +en_result_t Tim0_M23_ARRSet(uint16_t u16Data, boolean_t bArrBufEn); +//16ä½è®¡æ•°å€¼è®¾ç½®/èŽ·å– +en_result_t Tim0_M23_Cnt16Set(uint16_t u16Data); +uint16_t Tim0_M23_Cnt16Get(void); +//比较æ•èŽ·å¯„存器CCR0A/CCR0B设置/è¯»å– +en_result_t Tim0_M23_CCR_Set(en_tim0_m23_ccrx_t enCCRSel, uint16_t u16Data); +uint16_t Tim0_M23_CCR_Get(en_tim0_m23_ccrx_t enCCRSel); +//PWM互补输出模å¼ä¸‹ï¼ŒGATE功能选择 +en_result_t Tim0_M23_GateFuncSel(stc_tim0_m23_gate_config_t* pstcConfig); +//主从模å¼é…ç½® +en_result_t Tim0_M23_MasterSlave_Set(stc_tim0_m23_master_slave_config_t* pstcConfig); +//CH0A/CH0B比较通é“控制 +en_result_t Tim0_M23_PortOutput_Config(en_tim0_channel_t enTim0Chx, stc_tim0_m23_compare_config_t* pstcConfig); +//CH0A/CH0B输入控制 +en_result_t Tim0_M23_PortInput_Config(en_tim0_channel_t enTim0Chx, stc_tim0_m23_input_config_t* pstcConfig); +//ERT输入控制 +en_result_t Tim0_M23_ETRInput_Config(stc_tim0_m23_etr_input_config_t* pstcConfig); +//刹车BK输入控制 +en_result_t Tim0_M23_BrakeInput_Config(stc_tim0_m23_bk_input_config_t* pstcConfig); +//触å‘ADC控制 +en_result_t Tim0_M23_TrigADC_Config(stc_tim0_m23_adc_trig_config_t* pstcConfig); +//死区功能 +en_result_t Tim0_M23_DT_Config(stc_tim0_m23_dt_config_t* pstcConfig); +//é‡å¤å‘¨æœŸè®¾ç½® +en_result_t Tim0_M23_SetValidPeriod(uint8_t u8ValidPeriod); +//OCREF清除功能 +en_result_t Tim0_M23_OCRefClr(stc_tim0_m23_OCREF_Clr_config_t* pstcConfig); +//使能DMA传输 +en_result_t Tim0_M23_EnDMA(stc_tim0_m23_trig_dma_config_t* pstcConfig); +//æ•èŽ·æ¯”较Aè½¯ä»¶è§¦å‘ +en_result_t Tim0_M23_EnSwTrigCapCmpA(en_tim0_channel_t enTim0Chx); +//æ•èŽ·æ¯”较Bè½¯ä»¶è§¦å‘ +en_result_t Tim0_M23_EnSwTrigCapCmpB(en_tim0_channel_t enTim0Chx); +//软件更新使能 +en_result_t Tim0_M23_EnSwUev(void); +//软件触å‘使能 +en_result_t Tim0_M23_EnSwTrig(void); +//软件刹车使能 +en_result_t Tim0_M23_EnSwBk(void); + + +//@} // Tim0Group + +#ifdef __cplusplus +#endif + + +#endif /* __BT_H__ */ +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ + + diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/timer3.h b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/timer3.h new file mode 100644 index 0000000000..1ac153ab94 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/timer3.h @@ -0,0 +1,788 @@ +/******************************************************************************* +* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file bt.h + ** + ** 基本定时器数æ®ç»“æž„åŠAPI声明 + ** @link BT Timer3 Group Some description @endlink + ** + ** History: + ** - 2018-04-29 Husj First Version + ** + *****************************************************************************/ + +#ifndef __TIMER3_H__ +#define __TIMER3_H__ + +/***************************************************************************** + * Include files + *****************************************************************************/ +#include "ddl.h" +#include "interrupts_hc32l136.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ****************************************************************************** + ** \defgroup Tim3Group Base Timer (BT) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Timer3 通é“定义 + *****************************************************************************/ +typedef enum en_tim3_channel +{ + Tim3CH0 = 0u, ///< Timer3通é“0 + Tim3CH1 = 1u, ///< Timer3通é“1 + Tim3CH2 = 2u, ///< Timer3通é“2 +}en_tim3_channel_t; + +/** + ****************************************************************************** + ** \brief 工作模å¼é€‰æ‹©æ•°æ®ç±»åž‹é‡å®šä¹‰ (MODE)(模å¼0/1/23) + *****************************************************************************/ +typedef enum en_tim3_work_mode +{ + Tim3WorkMode0 = 0u, ///< å®šæ—¶å™¨æ¨¡å¼ + Tim3WorkMode1 = 1u, ///< PWCæ¨¡å¼ + Tim3WorkMode2 = 2u, ///< é”¯é½¿æ³¢æ¨¡å¼ + Tim3WorkMode3 = 3u, ///< ä¸‰è§’æ³¢æ¨¡å¼ +}en_tim3_work_mode_t; + +/** + ****************************************************************************** + ** \brief æžæ€§æŽ§åˆ¶æ•°æ®ç±»åž‹é‡å®šä¹‰ (GATE_P)(模å¼0) + *****************************************************************************/ +typedef enum en_tim3_m0cr_gatep +{ + Tim3GatePositive = 0u, ///< 高电平有效 + Tim3GateOpposite = 1u, ///< 低电平有效 +}en_tim3_m0cr_gatep_t; + +/** + ****************************************************************************** + ** \brief TIM3 预除频选择 (PRS)(模å¼0/1/23) + *****************************************************************************/ +typedef enum en_tim3_cr_timclkdiv +{ + Tim3PCLKDiv1 = 0u, ///< Div 1 + Tim3PCLKDiv2 = 1u, ///< Div 2 + Tim3PCLKDiv4 = 2u, ///< Div 4 + Tim3PCLKDiv8 = 3u, ///< Div 8 + Tim3PCLKDiv16 = 4u, ///< Div 16 + Tim3PCLKDiv32 = 5u, ///< Div 32 + Tim3PCLKDiv64 = 6u, ///< Div 64 + Tim3PCLKDiv256 = 7u, ///< Div 256 +}en_tim3_cr_timclkdiv_t; + +/** + ****************************************************************************** + ** \brief 计数/定时器功能选择数æ®ç±»åž‹é‡å®šä¹‰ (CT)(模å¼0/1/23) + *****************************************************************************/ +typedef enum en_tim3_cr_ct +{ + Tim3Timer = 0u, ///< 定时器功能，计数时钟为内部PCLK + Tim3Counter = 1u, ///< 计数器功能，计数时钟为外部ETR +}en_tim3_cr_ct_t; + + +/** + ****************************************************************************** + ** \brief 定时器工作模å¼æ•°æ®ç±»åž‹é‡å®šä¹‰ (MD)(模å¼0) + *****************************************************************************/ +typedef enum en_tim3_m0cr_md +{ + Tim332bitFreeMode = 0u, ///< 32ä½è®¡æ•°å™¨/定时器 + Tim316bitArrMode = 1u, ///< 自动é‡è£…è½½16ä½è®¡æ•°å™¨/定时器 +}en_tim3_m0cr_md_t; + +/** + ****************************************************************************** +** \brief TIM3中断类型数æ®ç±»åž‹é‡å®šä¹‰(模å¼0/1/23) + *****************************************************************************/ +typedef enum en_tim3_irq_type +{ + Tim3UevIrq = 0u, ///< 溢出/事件更新中断 + Tim3CA0Irq = 2u, ///< CH0Aæ•èŽ·/比较中断(仅模å¼1/23存在) + Tim3CA1Irq = 3u, ///< CH1Aæ•èŽ·/比较中断(仅模å¼23存在) + Tim3CA2Irq = 4u, ///< CH2Aæ•èŽ·/比较中断(仅模å¼23存在) + Tim3CB0Irq = 5u, ///< CH0Bæ•èŽ·/比较中断(仅模å¼23存在) + Tim3CB1Irq = 6u, ///< CH1Bæ•èŽ·/比较中断(仅模å¼23存在) + Tim3CB2Irq = 7u, ///< CH2Bæ•èŽ·/比较中断(仅模å¼23存在) + Tim3CA0E = 8u, ///< CH0Aæ•èŽ·æ•°æ®ä¸¢å¤±æ ‡å¿—(仅模å¼23存在)(ä¸æ˜¯ä¸­æ–­) + Tim3CA1E = 9u, ///< CH1Aæ•èŽ·æ•°æ®ä¸¢å¤±æ ‡å¿—(仅模å¼23存在)(ä¸æ˜¯ä¸­æ–­) + Tim3CA2E = 10u, ///< CH2Aæ•èŽ·æ•°æ®ä¸¢å¤±æ ‡å¿—(仅模å¼23存在)(ä¸æ˜¯ä¸­æ–­) + Tim3CB0E = 11u, ///< CH0Bæ•èŽ·æ•°æ®ä¸¢å¤±æ ‡å¿—(仅模å¼23存在)(ä¸æ˜¯ä¸­æ–­) + Tim3CB1E = 12u, ///< CH1Bæ•èŽ·æ•°æ®ä¸¢å¤±æ ‡å¿—(仅模å¼23存在)(ä¸æ˜¯ä¸­æ–­) + Tim3CB2E = 13u, ///< CH2Bæ•èŽ·æ•°æ®ä¸¢å¤±æ ‡å¿—(仅模å¼23存在)(ä¸æ˜¯ä¸­æ–­) + Tim3BkIrq = 14u, ///< 刹车中断(仅模å¼23存在） + Tim3TrigIrq = 15u, ///< 触å‘中断(仅模å¼23存在） +}en_tim3_irq_type_t; + +/** + ****************************************************************************** + ** \brief 测é‡å¼€å§‹ç»“æŸæ•°æ®ç±»åž‹é‡å®šä¹‰ (Edg1stEdg2nd)(模å¼1) + *****************************************************************************/ +typedef enum en_tim3_m1cr_Edge +{ + Tim3PwcRiseToRise = 0u, ///< 上å‡æ²¿åˆ°ä¸Šå‡æ²¿(周期) + Tim3PwcFallToRise = 1u, ///< 下é™æ²¿åˆ°ä¸Šå‡æ²¿(低电平) + Tim3PwcRiseToFall = 2u, ///< 上å‡æ²¿åˆ°ä¸‹é™æ²¿(高电平) + Tim3PwcFallToFall = 3u, ///< 下é™æ²¿åˆ°ä¸‹é™æ²¿(周期) +}en_tim3_m1cr_Edge_t; + +/** + ****************************************************************************** + ** \brief PWC测é‡æµ‹è¯•æ¨¡å¼é€‰æ‹©æ•°æ®ç±»åž‹é‡å®šä¹‰ (Oneshot)(模å¼1) + *****************************************************************************/ +typedef enum en_tim3_m1cr_oneshot +{ + Tim3PwcCycleDetect = 0u, ///< PWCå¾ªçŽ¯æµ‹é‡ + Tim3PwcOneShotDetect = 1u, ///< PWCå•æ¬¡æµ‹é‡ +}en_tim3_m1cr_oneshot_t; + +/** + ****************************************************************************** + ** \brief PWC IA0选择数æ®ç±»åž‹é‡å®šä¹‰ (IA0S)(模å¼1) + *****************************************************************************/ +typedef enum en_tim3_m1_mscr_ia0s +{ + Tim3IA0Input = 0u, ///< IAO输入 + Tim3XORInput = 1u, ///< IA0 ETR GATE XOR(TIM0/1/2)/IA0 IA1 IA2 XOR(TIM3) +}en_tim3_m1_mscr_ia0s_t; + +/** + ****************************************************************************** + ** \brief PWC IB0选择数æ®ç±»åž‹é‡å®šä¹‰ (IA0S)(模å¼1) + *****************************************************************************/ +typedef enum en_tim3_m1_mscr_ib0s +{ + Tim3IB0Input = 0u, ///< IBO输入 + Tim3TsInput = 1u, ///< 内部触å‘TSé€‰æ‹©ä¿¡å· +}en_tim3_m1_mscr_ib0s_t; + +/** + ****************************************************************************** + ** \brief 输出æžæ€§ã€è¾“å…¥ç›¸ä½ æ•°æ®ç±»åž‹é‡å®šä¹‰ (CCPA0/CCPB0/ETP/BKP)(模å¼1/23) + *****************************************************************************/ +typedef enum en_tim3_port_polarity +{ + Tim3PortPositive = 0u, ///< 正常输入输出 + Tim3PortOpposite = 1u, ///< åå‘输入输出 +}en_tim3_port_polarity_t; + +/** + ****************************************************************************** + ** \brief 滤波选择数æ®ç±»åž‹é‡å®šä¹‰ (FLTET/FLTA0/FLAB0)(模å¼1/23) + *****************************************************************************/ +typedef enum en_tim3_flt +{ + Tim3FltNone = 0u, ///< 无滤波 + Tim3FltPCLKCnt3 = 4u, ///< PCLK 3个连续有效 + Tim3FltPCLKDiv4Cnt3 = 5u, ///< PCLK/4 3个连续有效 + Tim3FltPCLKDiv16Cnt3 = 6u, ///< PCLK/16 3个连续有效 + Tim3FltPCLKDiv64Cnt3 = 7u, ///< PCLK/64 3个连续有效 +}en_tim3_flt_t; + +/** + ****************************************************************************** + ** \brief 通é“比较控制 æ•°æ®ç±»åž‹é‡å®šä¹‰ (OCMA/OCMB)(模å¼23) + *****************************************************************************/ +typedef enum en_tim3_m23_fltr_ocm +{ + Tim3ForceLow = 0u, ///< 强制为0 + Tim3ForceHigh = 1u, ///< 强制为1 + Tim3CMPForceLow = 2u, ///< 比较匹é…时强制为0 + Tim3CMPForceHigh = 3u, ///< 比较匹é…时强制为1 + Tim3CMPInverse = 4u, ///< 比较匹é…时翻转电平 + Tim3CMPOnePrdHigh = 5u, ///< 比较匹é…时输出一个计数周期的高电平 + Tim3PWMMode1 = 6u, ///< 通é“控制为PWM mode 1 + Tim3PWMMode2 = 7u, ///< 通é“控制为PWM mode 2 +}en_tim3_m23_fltr_ocm_t; + +/** + ****************************************************************************** + ** \brief 主从模å¼TSæ•°æ®ç±»åž‹é‡å®šä¹‰ (TS)(模å¼1/23) + *****************************************************************************/ +typedef enum en_tim3_mscr_ts +{ + Tim3Ts0ETR = 0u, ///< ETR外部输入滤波åŽçš„相ä½é€‰æ‹©ä¿¡å· + Tim3Ts1TIM0TRGO = 1u, ///< Timer0çš„TRGOè¾“å‡ºä¿¡å· + Tim3Ts2TIM1TRGO = 2u, ///< Timer1çš„TRGOè¾“å‡ºä¿¡å· + Tim3Ts3TIM2TRGO = 3u, ///< Timer2çš„TRGOè¾“å‡ºä¿¡å· + Tim3Ts4TIM3TRGO = 4u, ///< Timer3çš„TRGOè¾“å‡ºä¿¡å· + //Tim3Ts5IA0ED = 5u, ///< 无效 + Tim3Ts6IAFP = 6u, ///< CH0A 外部输输入滤波åŽçš„相ä½é€‰æ‹©ä¿¡å· + Tim3Ts7IBFP = 7u, ///< CH0B 外部输输入滤波åŽçš„相ä½é€‰æ‹©ä¿¡ +}en_tim3_mscr_ts_t; + +/** + ****************************************************************************** + ** \brief PWM输出模å¼é€‰æ‹©æ•°æ®ç±»åž‹é‡å®šä¹‰ (COMP)(模å¼23) + *****************************************************************************/ +typedef enum en_tim3_m23cr_comp +{ + Tim3IndependentPWM = 0u, ///< 独立PWM输出 + Tim3ComplementaryPWM = 1u, ///< 互补PWM输出 +}en_tim3_m23cr_comp_t; + +/** + ****************************************************************************** + ** \brief 计数方å‘选择数æ®ç±»åž‹é‡å®šä¹‰ (DIR)(模å¼23) + *****************************************************************************/ +typedef enum en_tim3_m23cr_dir +{ + Tim3CntUp = 0u, ///< å‘上计数 + Tim3CntDown = 1u, ///< å‘下计数 +}en_tim3_m23cr_dir_t; + +/** + ****************************************************************************** + ** \brief 计数方å‘选择数æ®ç±»åž‹é‡å®šä¹‰ (PWM2S)(模å¼23) + *****************************************************************************/ +typedef enum en_tim3_m23cr_pwm2s +{ + Tim3DoublePointCmp = 0u, ///< åŒç‚¹æ¯”较使能，使用CCRA,CCRB比较控制OCREFA输出 + Tim3SinglePointCmp = 1u, ///< å•ç‚¹æ¯”较使能，使用CCRA比较控制OCREFA输出 +}en_tim3_m23cr_pwm2s_t; + +/** + ****************************************************************************** + ** \brief GATE在PWM互补模å¼ä¸‹æ•èŽ·æˆ–比较功能 选择数æ®ç±»åž‹é‡å®šä¹‰ (CSG)(模å¼23) + *****************************************************************************/ +typedef enum en_tim3_m23cr_csg +{ + Tim3PWMCompGateCmpOut = 0u, ///< 在PWM互补模å¼ä¸‹ï¼ŒGate作为比较输出 + Tim3PWMCompGateCapIn = 1u, ///< 在PWM互补模å¼ä¸‹ï¼ŒGate作为æ•èŽ·è¾“å…¥ +}en_tim3_m23cr_csg_t; + + +/** + ****************************************************************************** + ** \brief 比较æ•èŽ·å¯„存器 æ•°æ®ç±»åž‹é‡å®šä¹‰ (CCR0A,CCR0B)(模å¼23) + *****************************************************************************/ +typedef enum en_tim3_m23_ccrx +{ + Tim3CCR0A = 0u, ///< CCR0A比较æ•èŽ·å¯„存器 + Tim3CCR0B = 1u, ///< CCR0B比较æ•èŽ·å¯„存器 + Tim3CCR1A = 2u, ///< CCR1A比较æ•èŽ·å¯„存器 + Tim3CCR1B = 3u, ///< CCR1B比较æ•èŽ·å¯„存器 + Tim3CCR2A = 4u, ///< CCR2A比较æ•èŽ·å¯„存器 + Tim3CCR2B = 5u, ///< CCR2B比较æ•èŽ·å¯„存器 +}en_tim3_m23_ccrx_t; + +/** + ****************************************************************************** + ** \brief OCREFæ¸…é™¤æº é€‰æ‹©æ•°æ®ç±»åž‹é‡å®šä¹‰ (OCCS)(模å¼23) + *****************************************************************************/ +typedef enum en_tim3_m23ce_occs +{ + Tim3OC_Ref_Clr = 0u, ///< æ¥è‡ªVCçš„OC_Ref_Clr + Tim3ETRf = 1u, ///< 外部ETRf +}en_tim3_m23ce_occs_t; + +/** + ****************************************************************************** + ** \brief 比较匹é…ä¸­æ–­æ¨¡å¼ é€‰æ‹©æ•°æ®ç±»åž‹é‡å®šä¹‰ (CIS/CISB)(模å¼23) + *****************************************************************************/ +typedef enum en_tim3_m23_cisa_cisb +{ + Tim3CmpIntNone = 0u, ///< 无比较匹é…中断 + Tim3CmpIntRise = 1u, ///< 比较匹é…上å‡æ²¿ä¸­æ–­ + Tim3CmpIntFall = 2u, ///< 比较匹é…下é™æ²¿ä¸­æ–­ + Tim3CmpIntRiseFall = 3u, ///< 比较匹é…上å‡æ²¿ä¸‹é™æ²¿ä¸­æ–­ +}en_tim3_m23_cisa_cisb_t; + +/** + ****************************************************************************** + ** \brief TIM3端å£æŽ§åˆ¶ - 刹车时CHx输出状æ€æŽ§åˆ¶(BKSA/BKSB)(模å¼23) + ** + ** \note + ******************************************************************************/ +typedef enum en_tim3_m23_crchx_bks +{ + Tim3CHxBksHiZ = 0u, ///< 刹车使能时，CHx端å£è¾“å‡ºé«˜é˜»æ€ + Tim3CHxBksNorm = 1u, ///< 刹车使能时，CHx端å£æ­£å¸¸è¾“出 + Tim3CHxBksLow = 2u, ///< 刹车使能时，CHx端å£è¾“出低电平 + Tim3CHxBksHigh = 3u, ///< 刹车使能时，CHx端å£è¾“出高电平 +}en_tim3_m23_crchx_bks_t; + +/** + ****************************************************************************** +** \brief TIM3端å£æŽ§åˆ¶ - CHx上å‡æ²¿ä¸‹é™æ²¿æ•èŽ·(CRx/CFx)(模å¼23) + ** + ** \note + ******************************************************************************/ +typedef enum en_tim3_m23_crch0_cfx_crx +{ + Tim3CHxCapNone = 0u, ///< CHx通é“æ•èŽ·ç¦æ­¢ + Tim3CHxCapRise = 1u, ///< CHx通é“上å‡æ²¿æ•èŽ·ä½¿èƒ½ + Tim3CHxCapFall = 2u, ///< CHx通é“下é™æ²¿æ•èŽ·ä½¿èƒ½ + Tim3CHxCapFallRise = 3u, ///< CHx通é“上å‡æ²¿ä¸‹é™æ²¿æ•èŽ·éƒ½ä½¿èƒ½ +}en_tim3_m23_crch0_cfx_crx_t; + +/** + ****************************************************************************** +** \brief TIM3端å£æŽ§åˆ¶ - CHx比较æ•èŽ·æ¨¡å¼(CSA/CSB)(模å¼23) + ** + ** \note + ******************************************************************************/ +typedef enum en_tim3_m23_crch0_csa_csb +{ + Tim3CHxCmpMode = 0u, ///< CHx通é“è®¾ç½®ä¸ºæ¯”è¾ƒæ¨¡å¼ + Tim3CHxCapMode = 1u, ///< CHx通é“设置为æ•èŽ·æ¨¡å¼ +}en_tim3_m23_crch0_csa_csb_t; + +/** + ****************************************************************************** + ** \brief 比较模å¼ä¸‹ DMA比较触å‘选择 æ•°æ®ç±»åž‹é‡å®šä¹‰ (CCDS)(模å¼23) + *****************************************************************************/ +typedef enum en_tim3_m23_mscr_ccds +{ + Tim3CmpTrigDMA = 0u, ///< 比较匹é…触å‘DMA + Tim3UEVTrigDMA = 1u, ///< 事件更新代替比较匹é…触å‘DMA +}en_tim3_m23_mscr_ccds_t; + +/** + ****************************************************************************** + ** \brief 主从模å¼é€‰æ‹© æ•°æ®ç±»åž‹é‡å®šä¹‰ (MSM)(模å¼23) + *****************************************************************************/ +typedef enum en_tim3_m23_mscr_msm +{ + Tim3SlaveMode = 0u, ///< ä»Žæ¨¡å¼ + Tim3MasterMode = 1u, ///< ä¸»æ¨¡å¼ +}en_tim3_m23_mscr_msm_t; + +/** + ****************************************************************************** + ** \brief 触å‘主模å¼è¾“å‡ºæº æ•°æ®ç±»åž‹é‡å®šä¹‰ (MMS)(模å¼23) + *****************************************************************************/ +typedef enum en_tim3_m23_mscr_mms +{ + Tim3MasterUG = 0u, ///< UG(软件更新)æº + Tim3MasterCTEN = 1u, ///< CTENæº + Tim3MasterUEV = 2u, ///< UEVæ›´æ–°æº + Tim3MasterCMPSO = 3u, ///< 比较匹é…é€‰æ‹©è¾“å‡ºæº + Tim3MasterOCA0Ref = 4u, ///< OCA0_Refæº + Tim3MasterOCB0Ref = 5u, ///< OCB0_Refæº + //Tim3MasterOCB0Ref = 6u, + //Tim3MasterOCB0Ref = 7u, +}en_tim3_m23_mscr_mms_t; + +/** + ****************************************************************************** + ** \brief 触å‘从模å¼é€‰æ‹© æ•°æ®ç±»åž‹é‡å®šä¹‰ (SMS)(模å¼23) + *****************************************************************************/ +typedef enum en_tim3_m23_mscr_sms +{ + Tim3SlaveIClk = 0u, ///< 使用内部时钟 + Tim3SlaveResetTIM = 1u, ///< å¤ä½åŠŸèƒ½ + Tim3SlaveTrigMode = 2u, ///< 触å‘æ¨¡å¼ + Tim3SlaveEClk = 3u, ///< å¤–éƒ¨æ—¶é’Ÿæ¨¡å¼ + Tim3SlaveCodeCnt1 = 4u, ///< 正交编ç è®¡æ•°æ¨¡å¼1 + Tim3SlaveCodeCnt2 = 5u, ///< 正交编ç è®¡æ•°æ¨¡å¼2 + Tim3SlaveCodeCnt3 = 6u, ///< 正交编ç è®¡æ•°æ¨¡å¼3 + Tim3SlaveGateCtrl = 7u, ///< 门控功能 +}en_tim3_m23_mscr_sms_t; + +/** + ****************************************************************************** + ** \brief 定时器è¿è¡ŒæŽ§åˆ¶æ•°æ®ç±»åž‹é‡å®šä¹‰ (CTEN) + *****************************************************************************/ +typedef enum en_tim3_start +{ + Tim3CTENDisable = 0u, ///< åœæ­¢ + Tim3CTENEnable = 1u, ///< è¿è¡Œ +}en_tim3_start_t; + +/** + ****************************************************************************** + ** \brief TIM3 mode0 é…置结构体定义(模å¼0) + *****************************************************************************/ +typedef struct stc_tim3_mode0_config +{ + en_tim3_work_mode_t enWorkMode; ///< 工作模å¼è®¾ç½® + en_tim3_m0cr_gatep_t enGateP; ///< 门控æžæ€§æŽ§åˆ¶ + boolean_t bEnGate; ///< 门控使能 + en_tim3_cr_timclkdiv_t enPRS; ///< 预除频é…ç½® + boolean_t bEnTog; ///< 翻转输出使能 + en_tim3_cr_ct_t enCT; ///< 定时/计数功能选择 + en_tim3_m0cr_md_t enCntMode; ///< 计数模å¼é…ç½® + + func_ptr_t pfnTim3Cb; ///< Timer3中断æœåŠ¡å›žè°ƒå‡½æ•°[void function(void)] +}stc_tim3_mode0_config_t; + +/** + ****************************************************************************** + ** \brief TIM3 mode1 é…置结构体定义(模å¼1) + *****************************************************************************/ +typedef struct stc_tim3_mode1_config +{ + en_tim3_work_mode_t enWorkMode; ///< 工作模å¼è®¾ç½® + en_tim3_cr_timclkdiv_t enPRS; ///< 预除频é…ç½® + en_tim3_cr_ct_t enCT; ///< 定时/计数功能选择 + en_tim3_m1cr_oneshot_t enOneShot; ///< å•æ¬¡æµ‹é‡/循环测é‡é€‰æ‹© + + func_ptr_t pfnTim3Cb; ///< Timer3中断æœåŠ¡å›žè°ƒå‡½æ•°[void function(void)] + +}stc_tim3_mode1_config_t; + +/** + ****************************************************************************** + ** \brief PWC输入é…置结构体定义(模å¼1) + *****************************************************************************/ +typedef struct stc_tim3_pwc_input_config +{ + en_tim3_mscr_ts_t enTsSel; ///< 触å‘输入æºé€‰æ‹© + en_tim3_m1_mscr_ia0s_t enIA0Sel; ///< CHA0输入选择 + en_tim3_m1_mscr_ib0s_t enIB0Sel; ///< CHB0输入选择 + en_tim3_port_polarity_t enETRPhase; ///< ETR相ä½é€‰æ‹© + en_tim3_flt_t enFltETR; ///< ETR滤波设置 + en_tim3_flt_t enFltIA0; ///< CHA0滤波设置 + en_tim3_flt_t enFltIB0; ///< CHB0滤波设置 +}stc_tim3_pwc_input_config_t; + +/** + ****************************************************************************** + ** \brief TIM3 mode23 é…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim3_mode23_config +{ + en_tim3_work_mode_t enWorkMode; ///< 工作模å¼è®¾ç½® + en_tim3_m23cr_dir_t enCntDir; ///< è®¡æ•°æ–¹å‘ + en_tim3_cr_timclkdiv_t enPRS; ///< 时钟预除频é…ç½® + en_tim3_cr_ct_t enCT; ///< 定时/计数功能选择 + en_tim3_m23cr_comp_t enPWMTypeSel; ///< PWM模å¼é€‰æ‹©ï¼ˆç‹¬ç«‹/互补） + en_tim3_m23cr_pwm2s_t enPWM2sSel; ///< OCREFAåŒç‚¹æ¯”较功能选择 + boolean_t bOneShot; ///< å•æ¬¡è§¦å‘模å¼ä½¿èƒ½/ç¦æ­¢ + boolean_t bURSSel; ///< æ›´æ–°æºé€‰æ‹© + + func_ptr_t pfnTim3Cb; ///< Timer3中断æœåŠ¡å›žè°ƒå‡½æ•°[void function(void)] +}stc_tim3_mode23_config_t; + +/** + ****************************************************************************** + ** \brief GATE在PWM互补模å¼ä¸‹æ•èŽ·æˆ–比较功能 é…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim3_m23_gate_config +{ + en_tim3_m23cr_csg_t enGateFuncSel; ///< Gate比较ã€æ•èŽ·åŠŸèƒ½é€‰æ‹© + boolean_t bGateRiseCap; ///< GATE作为æ•èŽ·åŠŸèƒ½æ—¶ï¼Œä¸Šæ²¿æ•èŽ·æœ‰æ•ˆæŽ§åˆ¶ + boolean_t bGateFallCap; ///< GATE作为æ•èŽ·åŠŸèƒ½æ—¶ï¼Œä¸‹æ²¿æ•èŽ·æœ‰æ•ˆæŽ§åˆ¶ +}stc_tim3_m23_gate_config_t; + +/** + ****************************************************************************** + ** \brief CHA/CHB通é“比较控制 é…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim3_m23_compare_config +{ + en_tim3_m23_crch0_csa_csb_t enCHxACmpCap; ///< CH0A比较/æ•èŽ·åŠŸèƒ½é€‰æ‹© + en_tim3_m23_fltr_ocm_t enCHxACmpCtrl; ///< CH0A通é“比较控制 + en_tim3_port_polarity_t enCHxAPolarity; ///< CH0A输出æžæ€§æŽ§åˆ¶ + boolean_t bCHxACmpBufEn; ///< 比较A缓存功能 使能/ç¦æ­¢ + en_tim3_m23_cisa_cisb_t enCHxACmpIntSel; ///< CHA比较匹é…中断选择 + + en_tim3_m23_crch0_csa_csb_t enCHxBCmpCap; ///< CH0B比较/æ•èŽ·åŠŸèƒ½é€‰æ‹© + en_tim3_m23_fltr_ocm_t enCHxBCmpCtrl; ///< CH0B通é“比较控制 + en_tim3_port_polarity_t enCHxBPolarity; ///< CH0B输出æžæ€§æŽ§åˆ¶ + boolean_t bCHxBCmpBufEn; ///< 比较B缓存功能 使能/ç¦æ­¢ + en_tim3_m23_cisa_cisb_t enCHxBCmpIntSel; ///< CHB0比较匹é…中断选择 +}stc_tim3_m23_compare_config_t; + +/** + ****************************************************************************** + ** \brief CHA/CHB通é“æ•èŽ·æŽ§åˆ¶ é…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim3_m23_input_config +{ + en_tim3_m23_crch0_csa_csb_t enCHxACmpCap; ///< CH0A比较/æ•èŽ·åŠŸèƒ½é€‰æ‹© + en_tim3_m23_crch0_cfx_crx_t enCHxACapSel; ///< CH0Aæ•èŽ·è¾¹æ²¿é€‰æ‹© + en_tim3_flt_t enCHxAInFlt; ///< CH0A通é“æ•èŽ·æ»¤æ³¢æŽ§åˆ¶ + en_tim3_port_polarity_t enCHxAPolarity; ///< CH0Aè¾“å…¥ç›¸ä½ + + en_tim3_m23_crch0_csa_csb_t enCHxBCmpCap; ///< CH0A比较/æ•èŽ·åŠŸèƒ½é€‰æ‹© + en_tim3_m23_crch0_cfx_crx_t enCHxBCapSel; ///< CH0Bæ•èŽ·è¾¹æ²¿é€‰æ‹© + en_tim3_flt_t enCHxBInFlt; ///< CH0B通é“æ•èŽ·æ»¤æ³¢æŽ§åˆ¶ + en_tim3_port_polarity_t enCHxBPolarity; ///< CH0Bè¾“å…¥ç›¸ä½ + +}stc_tim3_m23_input_config_t; + +/** + ****************************************************************************** + ** \brief ETR输入相ä½æ»¤æ³¢é…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim3_m23_etr_input_config +{ + en_tim3_port_polarity_t enETRPolarity; ///< ETR输入æžæ€§è®¾ç½® + en_tim3_flt_t enETRFlt; ///< ETR滤波设置 +}stc_tim3_m23_etr_input_config_t; + +/** + ****************************************************************************** + ** \brief 刹车BK输入相ä½æ»¤æ³¢é…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim3_m23_bk_input_config +{ + boolean_t bEnBrake; ///< 刹车使能 + boolean_t bEnVC0Brake; ///< 使能VC0刹车 + boolean_t bEnVC1Brake; ///< 使能VC1刹车 + boolean_t bEnSafetyBk; ///< 使能safety刹车 + boolean_t bEnBKSync; ///< TIM0/TIM1/TIM2刹车åŒæ­¥ä½¿èƒ½ + en_tim3_m23_crchx_bks_t enBkCH0AStat; ///< 刹车时CHA端å£çŠ¶æ€è®¾ç½® + en_tim3_m23_crchx_bks_t enBkCH0BStat; ///< 刹车时CHB端å£çŠ¶æ€è®¾ç½® + en_tim3_m23_crchx_bks_t enBkCH1AStat; ///< 刹车时CHA端å£çŠ¶æ€è®¾ç½® + en_tim3_m23_crchx_bks_t enBkCH1BStat; ///< 刹车时CHB端å£çŠ¶æ€è®¾ç½® + en_tim3_m23_crchx_bks_t enBkCH2AStat; ///< 刹车时CHA端å£çŠ¶æ€è®¾ç½® + en_tim3_m23_crchx_bks_t enBkCH2BStat; ///< 刹车时CHB端å£çŠ¶æ€è®¾ç½® + en_tim3_port_polarity_t enBrakePolarity; ///< 刹车BK输入æžæ€§è®¾ç½® + en_tim3_flt_t enBrakeFlt; ///< 刹车BK滤波设置 +}stc_tim3_m23_bk_input_config_t; + +/** + ****************************************************************************** +** \brief 死区功能é…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim3_m23_dt_config +{ + boolean_t bEnDeadTime; ///< 刹车时CHA端å£çŠ¶æ€è®¾ç½® + uint8_t u8DeadTimeValue; ///< 刹车时CHA端å£çŠ¶æ€è®¾ç½® +}stc_tim3_m23_dt_config_t; + +/** + ****************************************************************************** + ** \brief 触å‘ADCé…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim3_m23_adc_trig_config +{ + boolean_t bEnTrigADC; ///< 触å‘ADC全局控制 + boolean_t bEnUevTrigADC; ///< 事件更新触å‘ADC + boolean_t bEnCH0ACmpTrigADC; ///< CH0A比较匹é…触å‘ADC + boolean_t bEnCH0BCmpTrigADC; ///< CH0B比较匹é…触å‘ADC + boolean_t bEnCH1ACmpTrigADC; ///< CH0A比较匹é…触å‘ADC + boolean_t bEnCH1BCmpTrigADC; ///< CH0B比较匹é…触å‘ADC + boolean_t bEnCH2ACmpTrigADC; ///< CH0A比较匹é…触å‘ADC + boolean_t bEnCH2BCmpTrigADC; ///< CH0B比较匹é…触å‘ADC +}stc_tim3_m23_adc_trig_config_t; + +/** + ****************************************************************************** + ** \brief DMAè§¦å‘ é…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim3_m23_trig_dma_config +{ + boolean_t bUevTrigDMA; ///< æ›´æ–° 触å‘DMA使能 + boolean_t bTITrigDMA; ///< Trig 触å‘DMA功能 + boolean_t bCmpA0TrigDMA; ///< CH0Aæ•èŽ·æ¯”较触å‘DMA使能 + boolean_t bCmpB0TrigDMA; ///< CH0Bæ•èŽ·æ¯”较触å‘DMA使能 + boolean_t bCmpA1TrigDMA; ///< CH1Aæ•èŽ·æ¯”较触å‘DMA使能 + boolean_t bCmpB1TrigDMA; ///< CH1Bæ•èŽ·æ¯”较触å‘DMA使能 + boolean_t bCmpA2TrigDMA; ///< CH2Aæ•èŽ·æ¯”较触å‘DMA使能 + boolean_t bCmpB2TrigDMA; ///< CH2Bæ•èŽ·æ¯”较触å‘DMA使能 + en_tim3_m23_mscr_ccds_t enCmpUevTrigDMA; ///< 比较模å¼ä¸‹DMA比较触å‘选择 +}stc_tim3_m23_trig_dma_config_t; + +/** + ****************************************************************************** + ** \brief ä¸»ä»Žæ¨¡å¼ é…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim3_m23_master_slave_config +{ + en_tim3_m23_mscr_msm_t enMasterSlaveSel; ///< 主从模å¼é€‰æ‹© + en_tim3_m23_mscr_mms_t enMasterSrc; ///< 主模å¼è§¦å‘æºé€‰æ‹© + en_tim3_m23_mscr_sms_t enSlaveModeSel; ///< 从模å¼é€‰æ‹© + en_tim3_mscr_ts_t enTsSel; ///< 触å‘输入æºé€‰æ‹© +}stc_tim3_m23_master_slave_config_t; + +/** + ****************************************************************************** + ** \brief OCREF清除功能 é…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim3_m23_OCREF_Clr_config +{ + en_tim3_m23ce_occs_t enOCRefClrSrcSel; ///< OCREF清除æºé€‰æ‹© + boolean_t bVCClrEn; ///< 是å¦ä½¿èƒ½æ¥è‡ªVCçš„OCREF_Clr +}stc_tim3_m23_OCREF_Clr_config_t; + +/****************************************************************************** + * Global variable declarations ('extern', definition in C source) + *****************************************************************************/ + +/****************************************************************************** + * Global function prototypes (definition in C source) + *****************************************************************************/ +//中断相关函数 + +//ä¸­æ–­æ ‡å¿—èŽ·å– +boolean_t Tim3_GetIntFlag(en_tim3_irq_type_t enTim3Irq); +//中断标志清除 +en_result_t Tim3_ClearIntFlag(en_tim3_irq_type_t enTim3Irq); +//所有中断标志清除 +en_result_t Tim3_ClearAllIntFlag(void); +//模å¼0中断使能 +en_result_t Tim3_Mode0_EnableIrq(void); +//模å¼1中断使能 +en_result_t Tim3_Mode1_EnableIrq (en_tim3_irq_type_t enTim3Irq); +//模å¼2中断使能 +en_result_t Tim3_Mode23_EnableIrq (en_tim3_irq_type_t enTim3Irq); +//模å¼0中断ç¦æ­¢ +en_result_t Tim3_Mode0_DisableIrq(void); +//模å¼1中断ç¦æ­¢ +en_result_t Tim3_Mode1_DisableIrq (en_tim3_irq_type_t enTim3Irq); +//模å¼2中断ç¦æ­¢ +en_result_t Tim3_Mode23_DisableIrq (en_tim3_irq_type_t enTim3Irq); + + +//模å¼0åˆå§‹åŒ–åŠç›¸å…³åŠŸèƒ½æ“作 + +//timeré…ç½®åŠåˆå§‹åŒ– +en_result_t Tim3_Mode0_Init(stc_tim3_mode0_config_t* pstcConfig); +//timer å¯åŠ¨/åœæ­¢ +en_result_t Tim3_M0_Run(void); +en_result_t Tim3_M0_Stop(void); +//é‡è½½å€¼è®¾ç½® +en_result_t Tim3_M0_ARRSet(uint16_t u16Data); +//16ä½è®¡æ•°å€¼è®¾ç½®/èŽ·å– +en_result_t Tim3_M0_Cnt16Set(uint16_t u16Data); +uint16_t Tim3_M0_Cnt16Get(void); +//32ä½è®¡æ•°å€¼è®¾ç½®/èŽ·å– +en_result_t Tim3_M0_Cnt32Set(uint32_t u32Data); +uint32_t Tim3_M0_Cnt32Get(void); +//翻转输出使能/ç¦æ­¢è®¾å®š +en_result_t Tim3_M0_EnTOG_Output(boolean_t bEnOutput); + + +//模å¼1åˆå§‹åŒ–åŠç›¸å…³åŠŸèƒ½æ“作 + +//timeré…ç½®åŠåˆå§‹åŒ– +en_result_t Tim3_Mode1_Init(stc_tim3_mode1_config_t* pstcConfig); +//PWC 输入é…ç½® +en_result_t Tim3_M1_Input_Config(stc_tim3_pwc_input_config_t* pstcConfig); +//PWC测é‡è¾¹æ²¿èµ·å§‹ç»“æŸé€‰æ‹© +en_result_t Tim3_M1_PWC_Edge_Sel(en_tim3_m1cr_Edge_t enEdgeSel); +//timer å¯åŠ¨/åœæ­¢ +en_result_t Tim3_M1_Run(void); +en_result_t Tim3_M1_Stop(void); +//16ä½è®¡æ•°å€¼è®¾ç½®/èŽ·å– +en_result_t Tim3_M1_Cnt16Set(uint16_t u16Data); +uint16_t Tim3_M1_Cnt16Get(void); +//脉冲宽度测é‡ç»“æžœæ•°å€¼èŽ·å– +uint16_t Tim3_M1_PWC_CapValueGet(void); + + +//模å¼1åˆå§‹åŒ–åŠç›¸å…³åŠŸèƒ½æ“作 + +//timeré…ç½®åŠåˆå§‹åŒ– +en_result_t Tim3_Mode23_Init(stc_tim3_mode23_config_t* pstcConfig); +//timer å¯åŠ¨/åœæ­¢ +en_result_t Tim3_M23_Run(void); +en_result_t Tim3_M23_Stop(void); +//PWM输出使能 +en_result_t Tim3_M23_EnPWM_Output(boolean_t bEnOutput, boolean_t bEnAutoOutput); +//é‡è½½å€¼è®¾ç½® +en_result_t Tim3_M23_ARRSet(uint16_t u16Data, boolean_t bArrBufEn); +//16ä½è®¡æ•°å€¼è®¾ç½®/èŽ·å– +en_result_t Tim3_M23_Cnt16Set(uint16_t u16Data); +uint16_t Tim3_M23_Cnt16Get(void); +//比较æ•èŽ·å¯„存器CCR0A/CCR0B设置/è¯»å– +en_result_t Tim3_M23_CCR_Set(en_tim3_m23_ccrx_t enCCRSel, uint16_t u16Data); +uint16_t Tim3_M23_CCR_Get(en_tim3_m23_ccrx_t enCCRSel); +//PWM互补输出模å¼ä¸‹ï¼ŒGATE功能选择 +en_result_t Tim3_M23_GateFuncSel(stc_tim3_m23_gate_config_t* pstcConfig); +//主从模å¼é…ç½® +en_result_t Tim3_M23_MasterSlave_Set(stc_tim3_m23_master_slave_config_t* pstcConfig); +//CH0A/CH0B比较通é“控制 +en_result_t Tim3_M23_PortOutput_Config(en_tim3_channel_t enTim3Chx, stc_tim3_m23_compare_config_t* pstcConfig); +//CH0A/CH0B输入控制 +en_result_t Tim3_M23_PortInput_Config(en_tim3_channel_t enTim3Chx, stc_tim3_m23_input_config_t* pstcConfig); +//ERT输入控制 +en_result_t Tim3_M23_ETRInput_Config(stc_tim3_m23_etr_input_config_t* pstcConfig); +//刹车BK输入控制 +en_result_t Tim3_M23_BrakeInput_Config(stc_tim3_m23_bk_input_config_t* pstcConfig); +//触å‘ADC控制 +en_result_t Tim3_M23_TrigADC_Config(stc_tim3_m23_adc_trig_config_t* pstcConfig); +//死区功能 +en_result_t Tim3_M23_DT_Config(stc_tim3_m23_dt_config_t* pstcConfig); +//é‡å¤å‘¨æœŸè®¾ç½® +en_result_t Tim3_M23_SetValidPeriod(uint8_t u8ValidPeriod); +//OCREF清除功能 +en_result_t Tim3_M23_OCRefClr(stc_tim3_m23_OCREF_Clr_config_t* pstcConfig); +//使能DMA传输 +en_result_t Tim3_M23_EnDMA(stc_tim3_m23_trig_dma_config_t* pstcConfig); +//æ•èŽ·æ¯”较Aè½¯ä»¶è§¦å‘ +en_result_t Tim3_M23_EnSwTrigCapCmpA(en_tim3_channel_t enTim3Chx); +//æ•èŽ·æ¯”较Bè½¯ä»¶è§¦å‘ +en_result_t Tim3_M23_EnSwTrigCapCmpB(en_tim3_channel_t enTim3Chx); +//软件更新使能 +en_result_t Tim3_M23_EnSwUev(void); +//软件触å‘使能 +en_result_t Tim3_M23_EnSwTrig(void); +//软件刹车使能 +en_result_t Tim3_M23_EnSwBk(void); + + +//@} // Tim3Group + +#ifdef __cplusplus +#endif + + +#endif /* __BT_H__ */ +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ + + diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/trim.h b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/trim.h new file mode 100644 index 0000000000..7534eb0269 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/trim.h @@ -0,0 +1,186 @@ +/****************************************************************************** +* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/*****************************************************************************/ +/** \file trim.h + ** + ** TRIM æ•°æ®ç»“æž„åŠAPI声明 + ** + ** + ** History: + ** - 2018-04-21 Lux V1.0 + ** + *****************************************************************************/ + +#ifndef __TRIM_H__ +#define __TRIM_H__ + +/***************************************************************************** + * Include files + *****************************************************************************/ +#include "ddl.h" +#include "interrupts_hc32l136.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ****************************************************************************** + ** \defgroup TrimGroup Clock Trimming (TRIM) + ** + ******************************************************************************/ +//@{ + +/****************************************************************************** + ** Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ + + /** + ****************************************************************************** + ** \brief 监测模å¼ä½¿èƒ½æžšä¸¾é‡å®šä¹‰ (MON_EN) + *****************************************************************************/ +typedef enum en_trim_monitor +{ + TrimMonDisable = 0u, ///< ç¦æ­¢ + TrimMonEnable = 1u, ///< 使能 +}en_trim_monitor_t; + + /** + ****************************************************************************** + ** \brief 待校准/监测时钟选择枚举é‡å®šä¹‰ (CALCLK_SEL) + *****************************************************************************/ +typedef enum en_trim_calclksel +{ + TrimCalRCH = 0u, ///< RCH + TrimCalXTH = 1u, ///< XTH + TrimCalRCL = 2u, ///< RCL + TrimCalXTL = 3u, ///< XTL + TrimCalPLL = 4u, ///< PLL +}en_trim_calclksel_t; + +/** + ****************************************************************************** + ** \brief å‚考时钟选择枚举é‡å®šä¹‰ (REFCLK_SEL) + *****************************************************************************/ +typedef enum en_trim_refclksel +{ + TrimRefRCH = 0u, ///< RCH + TrimRefXTH = 1u, ///< XTH + TrimRefRCL = 2u, ///< RCL + TrimRefXTL = 3u, ///< XTL + TrimRefIRC10K = 4u, ///< IRC10K + TrimRefExtClk = 5u, ///< 外部输入时钟 +}en_trim_refclksel_t; + +/** + ****************************************************************************** + ** \brief 中断标志类型枚举é‡å®šä¹‰ + *****************************************************************************/ +typedef enum en_trim_inttype +{ + TrimStop = 0u, ///< å‚考计数器åœæ­¢æ ‡å¿— + TrimCalCntOf = 1u, ///< 校准计数器溢出标志 + TrimXTLFault = 2u, ///< XTL 失效标志 + TrimXTHFault = 3u, ///< XTH 失效标志 + TrimPLLFault = 4u, ///< PLL 失效标志 +}en_trim_inttype_t; + +/** + ****************************************************************************** + ** \brief TRIM é…置结构体定义 + *****************************************************************************/ +typedef struct stc_trim_config +{ + en_trim_monitor_t enMON; ///< 监测模å¼ä½¿èƒ½ + en_trim_calclksel_t enCALCLK; ///< 校准时钟选择 + uint32_t u32CalCon; ///< 校准计数器溢出值é…ç½® + en_trim_refclksel_t enREFCLK; ///< å‚考时钟选择 + uint32_t u32RefCon; ///< å‚考计数器åˆå€¼é…ç½® + + func_ptr_t pfnTrimCb; ///< TRIM 中断æœåŠ¡å›žè°ƒå‡½æ•°[void function(void)] +}stc_trim_config_t; + +/****************************************************************************** + * Global variable declarations ('extern', definition in C source) + *****************************************************************************/ + +/****************************************************************************** + * Global function prototypes (definition in C source) + *****************************************************************************/ +///<<功能é…ç½®åŠæ“作函数 +///IFR_f.REGIF) + { + if (NULL != stcAdcIrqCalbaks.pfnAdcRegIrq) + { + stcAdcIrqCalbaks.pfnAdcRegIrq(); + } + M0P_ADC->ICR_f.REGIC = 0u; + } + + if (TRUE == M0P_ADC->IFR_f.HTIF) + { + if (NULL != stcAdcIrqCalbaks.pfnAdcHhtIrq) + { + stcAdcIrqCalbaks.pfnAdcHhtIrq(); + } + M0P_ADC->ICR_f.HTIC = 0u; + } + + if (TRUE == M0P_ADC->IFR_f.LTIF) + { + if (NULL != stcAdcIrqCalbaks.pfnAdcLltIrq) + { + stcAdcIrqCalbaks.pfnAdcLltIrq(); + } + M0P_ADC->ICR_f.LTIC = 0u; + } + + if (TRUE == M0P_ADC->IFR_f.SGLIF) + { + if (NULL != stcAdcIrqCalbaks.pfnAdcIrq) + { + stcAdcIrqCalbaks.pfnAdcIrq(); + } + M0P_ADC->ICR_f.SGLIC = 0u; + } + if(TRUE == M0P_ADC->IFR_f.SQRIF) + { + if (NULL != stcAdcIrqCalbaks.pfnAdcSQRIrq) + { + stcAdcIrqCalbaks.pfnAdcSQRIrq(); + } + M0P_ADC->ICR_f.SQRIC = 0u; + } + if(TRUE == M0P_ADC->IFR_f.JQRIF) + { + if (NULL != stcAdcIrqCalbaks.pfnAdcJQRIrq) + { + stcAdcIrqCalbaks.pfnAdcJQRIrq(); + } + M0P_ADC->ICR_f.JQRIC = 0u; + } +} + +/** + * \brief + * é…ç½®ADCä¸­æ–­å‡½æ•°å…¥å£ + * + * \param [in] pstcAdcIrqCfg ADC中断é…置指针 + * \param [in] pstcAdcIrqCalbaks ADC中断回调函数指针 + * + * \retval æ—  + */ +void Adc_ConfigIrq(stc_adc_irq_t* pstcAdcIrqCfg, + stc_adc_irq_calbakfn_pt_t* pstcAdcIrqCalbaks) +{ + if (TRUE == pstcAdcIrqCfg->bAdcIrq) + { + if (NULL != pstcAdcIrqCalbaks->pfnAdcIrq) + { + stcAdcIrqCalbaks.pfnAdcIrq = pstcAdcIrqCalbaks->pfnAdcIrq; + } + } + if (TRUE == pstcAdcIrqCfg->bAdcJQRIrq) + { + if (NULL != pstcAdcIrqCalbaks->pfnAdcJQRIrq) + { + stcAdcIrqCalbaks.pfnAdcJQRIrq = pstcAdcIrqCalbaks->pfnAdcJQRIrq; + } + } + if (TRUE == pstcAdcIrqCfg->bAdcSQRIrq) + { + if (NULL != pstcAdcIrqCalbaks->pfnAdcSQRIrq) + { + stcAdcIrqCalbaks.pfnAdcSQRIrq = pstcAdcIrqCalbaks->pfnAdcSQRIrq; + } + } + if (TRUE == pstcAdcIrqCfg->bAdcRegCmp) + { + if (NULL != pstcAdcIrqCalbaks->pfnAdcRegIrq) + { + stcAdcIrqCalbaks.pfnAdcRegIrq = pstcAdcIrqCalbaks->pfnAdcRegIrq; + } + } + + if (TRUE == pstcAdcIrqCfg->bAdcHhtCmp) + { + if (NULL != pstcAdcIrqCalbaks->pfnAdcHhtIrq) + { + stcAdcIrqCalbaks.pfnAdcHhtIrq = pstcAdcIrqCalbaks->pfnAdcHhtIrq; + } + } + + if (TRUE == pstcAdcIrqCfg->bAdcLltCmp) + { + if (NULL != pstcAdcIrqCalbaks->pfnAdcLltIrq) + { + stcAdcIrqCalbaks.pfnAdcLltIrq = pstcAdcIrqCalbaks->pfnAdcLltIrq; + } + } + +} + +/** + * \brief + * 获å–ADCä¸­æ–­çŠ¶æ€ + * + * \param [in] pstcAdcIrqState ADC中断状æ€æŒ‡é’ˆ + * + * \retval æ—  + */ +void Adc_GetIrqState(stc_adc_irq_t* pstcAdcIrqState) +{ + pstcAdcIrqState->bAdcIrq = M0P_ADC->IFR_f.SGLIF; + pstcAdcIrqState->bAdcRegCmp = M0P_ADC->IFR_f.REGIF; + pstcAdcIrqState->bAdcHhtCmp = M0P_ADC->IFR_f.HTIF; + pstcAdcIrqState->bAdcLltCmp = M0P_ADC->IFR_f.LTIF; + pstcAdcIrqState->bAdcJQRIrq = M0P_ADC->IFR_f.JQRIF; + pstcAdcIrqState->bAdcSQRIrq = M0P_ADC->IFR_f.SQRIF; +} +/** + * \brief + * 清除ADC SGLä¸­æ–­çŠ¶æ€ + * + * \param æ—  + * + * \retval æ—  + */ +void Adc_ClrSglIrqState(void) +{ + M0P_ADC->ICR_f.SGLIC = 0; +} +/** + * \brief + * 清除ADC JQRä¸­æ–­çŠ¶æ€ + * + * \param æ—  + * + * \retval æ—  + */ +void Adc_ClrJqrIrqState(void) +{ + M0P_ADC->ICR_f.JQRIC = 0; +} +/** + * \brief + * 清除ADC SQRä¸­æ–­çŠ¶æ€ + * + * \param æ—  + * + * \retval æ—  + */ +void Adc_ClrSqrIrqState(void) +{ + M0P_ADC->ICR_f.SQRIC = 0; +} + +/** + * \brief + * 清除ADC REGä¸­æ–­çŠ¶æ€ + * + * \param æ—  + * + * \retval æ—  + */ +void Adc_ClrRegIrqState(void) +{ + M0P_ADC->ICR_f.REGIC = 0; +} + +/** + * \brief + * 清除ADC HTä¸­æ–­çŠ¶æ€ + * + * \param æ—  + * + * \retval æ—  + */ +void Adc_ClrHtIrqState(void) +{ + M0P_ADC->ICR_f.HTIC = 0; +} + +/** + * \brief + * 清除ADC LTä¸­æ–­çŠ¶æ€ + * + * \param æ—  + * + * \retval æ—  + */ +void Adc_ClrLtIrqState(void) +{ + M0P_ADC->ICR_f.LTIC = 0; +} + + +/** + * \brief + * ADC中断使能 + * + * \param æ—  + * + * \retval æ—  + */ +void Adc_EnableIrq(void) +{ + M0P_ADC->CR0_f.IE = 1u; +} + +/** + * \brief + * ADC比较使能(比较中断) + * + * \param [in] pstcAdcIrqCfg ADC比较é…ç½® + * + * \retval æ—  + */ + +void Adc_ThresholdCfg(stc_adc_threshold_cfg_t* stcAdcThrCfg) +{ + + M0P_ADC->HT_f.HT = stcAdcThrCfg->u32AdcRegHighThd; //使用比较 + M0P_ADC->LT_f.LT = stcAdcThrCfg->u32AdcRegLowThd; //使用比较 + + M0P_ADC->CR1_f.THCH = stcAdcThrCfg->enThCh; //阈值比较通é“选择 + + if (TRUE == stcAdcThrCfg->bAdcRegCmp) + { + M0P_ADC->CR1_f.REGCMP = 1u; + } + else + { + M0P_ADC->CR1_f.REGCMP = 0u; + } + + if (TRUE == stcAdcThrCfg->bAdcHhtCmp) + { + M0P_ADC->CR1_f.HTCMP = 1u; + } + else + { + M0P_ADC->CR1_f.HTCMP = 0u; + } + + if (TRUE == stcAdcThrCfg->bAdcLltCmp) + { + M0P_ADC->CR1_f.LTCMP = 1u; + } + else + { + M0P_ADC->CR1_f.LTCMP = 0u; + } + +} + +/** + * \brief + * ADC中断除能 + * + * \param æ—  + * + * \retval æ—  + */ +void Adc_DisableIrq(void) +{ + uint32_t u32Cr1; + + M0P_ADC->CR0_f.IE = 0u; + + u32Cr1 = M0P_ADC->CR1 | (1<<15); // must write 1 to bit 15 to avoid clear ADC_result_acc + u32Cr1 &= ~((1u<<12)|(1u<<13)|(1u<<14)); + M0P_ADC->CR1 = u32Cr1; +} + +/** + * \brief + * ADCåˆå§‹åŒ– + * + * \param [in] pstcAdcConfig ADCé…置指针 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Adc_Init(stc_adc_cfg_t* pstcAdcConfig) +{ + if (NULL == pstcAdcConfig) + { + return ErrorInvalidParameter; + } + M0P_ADC->CR0_f.CLKDIV = pstcAdcConfig->enAdcClkDiv; + M0P_ADC->CR0_f.SAM = pstcAdcConfig->enAdcSampTimeSel; + M0P_ADC->CR0_f.REF = pstcAdcConfig->enAdcRefVolSel; + M0P_ADC->CR0_f.BUF = pstcAdcConfig->bAdcInBufEn; + M0P_ADC->CR1_f.REGCMP = 0u; + M0P_ADC->CR1_f.HTCMP = 0u; + M0P_ADC->CR1_f.LTCMP = 0u; + + return Ok; +} + +/** + * \brief + * ADC外部中断触å‘æºé…ç½® + * + * \param [in] pstcAdcConfig ADCé…置指针 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Adc_ExtTrigCfg(stc_adc_ext_trig_cfg_t* pstcExtTrigConfig) +{ + if (NULL == pstcExtTrigConfig) + { + return ErrorInvalidParameter; + } + if(pstcExtTrigConfig->enAdcExtTrigRegSel == AdcExtTrig0) + { + M0P_ADC->EXTTRIGGER0 |= 1u << pstcExtTrigConfig->enAdcTrig0Sel; + } + else if(pstcExtTrigConfig->enAdcExtTrigRegSel == AdcExtTrig1) + { + M0P_ADC->EXTTRIGGER1 |= 1u << pstcExtTrigConfig->enAdcTrig1Sel; + } + else + { + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + * \brief + * ADC Deinit + * + * \param æ—  + * + * \retval æ—  + */ +void Adc_DeInit(void) +{ + + M0P_ADC->CR0_f.EN = 0u; + + M0P_ADC->CR0_f.IE = 0u; + M0P_ADC->CR1_f.REGCMP = 0u; + M0P_ADC->CR1_f.HTCMP = 0u; + M0P_ADC->CR1_f.LTCMP = 0u; + + M0P_ADC->ICR_f.SGLIC = 0u; + M0P_ADC->ICR_f.LTIC = 0u; + M0P_ADC->ICR_f.HTIC = 0u; + M0P_ADC->ICR_f.REGIC = 0u; + M0P_ADC->ICR_f.SQRIC = 0u; + M0P_ADC->ICR_f.JQRIC = 0u; + + M0P_ADC->CR0_f.CLKDIV = 0u; + M0P_ADC->CR0_f.SAM = 0x2u; + M0P_ADC->CR0_f.REF = 0x3u; + M0P_ADC->CR0_f.SGLMUX = 0xFu; + M0P_ADC->CR0_f.BUF = 0u; + M0P_ADC->HT_f.HT = 0xFFFu; + M0P_ADC->LT_f.LT = 0u; +} + +/** + * \brief + * ADC å•æ¬¡è½¬æ¢å¼€å§‹ + * + * \param æ—  + * + * \retval æ—  + */ + +void Adc_SGL_Start(void) +{ + M0P_ADC->SGLSTART_f.START = 1u; +} + +/** + * \brief + * ADC å•æ¬¡è½¬æ¢åœæ­¢ + * + * \param æ—  + * + * \retval æ—  + */ +void Adc_SGL_Stop(void) +{ + M0P_ADC->SGLSTART_f.START = 0u; +} +/** + * \brief + * ADC 顺åºè½¬æ¢å¼€å§‹ + * + * \param æ—  + * + * \retval æ—  + */ + +void Adc_SQR_Start(void) +{ + M0P_ADC->SQRSTART_f.START = 1u; +} + +/** + * \brief + * ADC 顺åºè½¬æ¢åœæ­¢ + * + * \param æ—  + * + * \retval æ—  + */ +void Adc_SQR_Stop(void) +{ + M0P_ADC->SQRSTART_f.START = 0u; +} +/** + * \brief + * ADC æ’队转æ¢å¼€å§‹ + * + * \param æ—  + * + * \retval æ—  + */ + +void Adc_JQR_Start(void) +{ + M0P_ADC->JQRSTART_f.START = 1u; +} + +/** + * \brief + * ADC æ’队转æ¢åœæ­¢ + * + * \param æ—  + * + * \retval æ—  + */ +void Adc_JQR_Stop(void) +{ + M0P_ADC->JQRSTART_f.START = 0u; +} +/** + * \brief + * ADC使能 + * + * \param æ—  + * + * \retval æ—  + */ +void Adc_Enable(void) +{ + M0P_ADC->CR0_f.EN = 1u; +} + +/** + * \brief + * ADC除能 + * + * \param æ—  + * + * \retval æ—  + */ +void Adc_Disable(void) +{ + M0P_ADC->CR0_f.EN = 0u; +} + +/** + * \brief + * é…ç½®å•æ¬¡è½¬æ¢æ¨¡å¼ + * + * \param [in] pstcAdcConfig ADCé…置指针 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Adc_ConfigSglMode(stc_adc_cfg_t* pstcAdcConfig) +{ + if (NULL == pstcAdcConfig) + { + return ErrorInvalidParameter; + } + + M0P_ADC->CR1_f.MODE = pstcAdcConfig->enAdcOpMode; + + return Ok; +} + +/** + * \brief + * é…置顺åºæ‰«æ转æ¢æ¨¡å¼ + * + * \param [in] pstcAdcConfig ADCé…置指针 + * \param [in] pstcAdcNormCfg 连续转æ¢æ¨¡å¼é…置指针 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Adc_ConfigSqrMode(stc_adc_cfg_t* pstcAdcConfig, uint8_t u8AdcSampCnt,boolean_t bAdcResultAccEn) +{ + if (NULL == pstcAdcConfig) + { + return ErrorInvalidParameter; + } + + M0P_ADC->CR1_f.MODE = pstcAdcConfig->enAdcOpMode; + M0P_ADC->CR1_f.RACCCLR = 0;//ADC转æ¢ç»“果累加寄存器（ADC_ResultAcc）清零 + M0P_ADC->CR1_f.RACCEN = bAdcResultAccEn; + if (bAdcResultAccEn) + { + M0P_ADC->CR1_f.RACCCLR = 1u; + } + M0P_ADC->SQR2_f.CNT = u8AdcSampCnt - 1; + + return Ok; +} + +/** + * \brief + * é…ç½®æ’队扫æ转æ¢æ¨¡å¼ + * + * \param [in] pstcAdcConfig ADCé…置指针 + * \param [in] pstcAdcNormCfg 扫æ转æ¢æ¨¡å¼é…置指针 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Adc_ConfigJqrMode(stc_adc_cfg_t* pstcAdcConfig, uint8_t u8AdcSampCnt,boolean_t bAdcResultAccEn) +{ + if (NULL == pstcAdcConfig) + { + return ErrorInvalidParameter; + } + + M0P_ADC->CR1_f.MODE = pstcAdcConfig->enAdcOpMode; + M0P_ADC->CR1_f.RACCEN = bAdcResultAccEn; + M0P_ADC->JQR_f.CNT = u8AdcSampCnt - 1; + + return Ok; +} +/** + * \brief + * é…ç½®å•æ¬¡è½¬æ¢é€šé“ + * + * \param [in]enstcAdcSampCh 转æ¢é€šé“ + * + * \retval en_result_t Ok: æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Adc_ConfigSglChannel( en_adc_samp_ch_sel_t enstcAdcSampCh) +{ + M0P_ADC->CR0_f.SGLMUX = enstcAdcSampCh; + return Ok; +} + +/** + * \brief + * é…置顺åºæ‰«æ转æ¢é€šé“ + * + * \param [in]enstcAdcSqrChMux 顺åºæ‰«æ转æ¢é€šé“é¡ºåº + * \param [in]enstcAdcSampCh 转æ¢é€šé“ + * + * \retval en_result_t Ok: æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Adc_ConfigSqrChannel(en_adc_sqr_chmux_t enstcAdcSqrChMux, en_adc_samp_ch_sel_t enstcAdcSampCh) +{ + switch(enstcAdcSqrChMux) + { + case CH0MUX: + M0P_ADC->SQR0_f.CH0MUX = enstcAdcSampCh; + break; + case CH1MUX: + M0P_ADC->SQR0_f.CH1MUX = enstcAdcSampCh; + break; + case CH2MUX: + M0P_ADC->SQR0_f.CH2MUX = enstcAdcSampCh; + break; + case CH3MUX: + M0P_ADC->SQR0_f.CH3MUX = enstcAdcSampCh; + break; + case CH4MUX: + M0P_ADC->SQR0_f.CH4MUX = enstcAdcSampCh; + break; + case CH5MUX: + M0P_ADC->SQR0_f.CH5MUX = enstcAdcSampCh; + break; + case CH6MUX: + M0P_ADC->SQR1_f.CH6MUX = enstcAdcSampCh; + break; + case CH7MUX: + M0P_ADC->SQR1_f.CH7MUX = enstcAdcSampCh; + break; + case CH8MUX: + M0P_ADC->SQR1_f.CH8MUX = enstcAdcSampCh; + break; + case CH9MUX: + M0P_ADC->SQR1_f.CH9MUX = enstcAdcSampCh; + break; + case CH10MUX: + M0P_ADC->SQR1_f.CH10MUX = enstcAdcSampCh; + break; + case CH11MUX: + M0P_ADC->SQR1_f.CH11MUX = enstcAdcSampCh; + break; + case CH12MUX: + M0P_ADC->SQR2_f.CH12MUX = enstcAdcSampCh; + break; + case CH13MUX: + M0P_ADC->SQR2_f.CH13MUX = enstcAdcSampCh; + break; + case CH14MUX: + M0P_ADC->SQR2_f.CH14MUX = enstcAdcSampCh; + break; + case CH15MUX: + M0P_ADC->SQR2_f.CH15MUX = enstcAdcSampCh; + break; + default: + break; + + } + return Ok; +} +/** + * \brief + * é…ç½®æ’队扫æ转æ¢é€šé“ + * + * \param [in]enstcAdcSqrChMux æ’队扫æ转æ¢é€šé“é¡ºåº + * \param [in]enstcAdcSampCh 转æ¢é€šé“ + * + * \retval en_result_t Ok: æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Adc_ConfigJqrChannel(en_adc_jqr_chmux_t enstcAdcJqrChMux, en_adc_samp_ch_sel_t enstcAdcSampCh) +{ + switch(enstcAdcJqrChMux) + { + case CH0MUX: + M0P_ADC->JQR_f.CH0MUX = enstcAdcSampCh; + break; + case CH1MUX: + M0P_ADC->JQR_f.CH1MUX = enstcAdcSampCh; + break; + case CH2MUX: + M0P_ADC->JQR_f.CH2MUX = enstcAdcSampCh; + break; + case CH3MUX: + M0P_ADC->JQR_f.CH3MUX = enstcAdcSampCh; + break; + default: + break; + } + return Ok; +} +/** + * \brief + * é…置触å‘DMA读å–控制 + * + * \param [in]enAdcDmaTrig 触å‘DMA读å–控制 + * + * \retval en_result_t Ok: æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Adc_ConfigDmaTrig(en_adc_dmatrig_t enAdcDmaTrig) +{ + if(enAdcDmaTrig == DmaJqr) + { + M0P_ADC->CR1_f.DMAJQR = 1; + }else + { + M0P_ADC->CR1_f.DMASQR = 1; + } + return Ok; +} + +/** + * \brief + * 查询ADCå•æ¬¡è½¬æ¢çŠ¶æ€ + * + * \param none + * + * \retval boolean_t TRUE: ADC转æ¢å®Œæˆ + * \retval boolean_t FALSE: ADC转æ¢ä¸­ + */ +boolean_t Adc_PollSglBusyState(void) +{ + return M0P_ADC->IFR_f.SGLIF; +} + + +/** + * \brief + * 查询ADC顺åºæ‰«æ转æ¢çŠ¶æ€ + * + * \retval boolean_t TRUE: ADC转æ¢å®Œæˆ + * \retval boolean_t FALSE: ADC转æ¢ä¸­ + * \param none + * + */ +boolean_t Adc_PollSqrBusyState(void) +{ + return M0P_ADC->IFR_f.SQRIF; +} + +/** + * \brief + * 查询ADCæ’队扫æ转æ¢çŠ¶æ€ + * + * \param none + * + * \retval boolean_t TRUE: ADC转æ¢å®Œæˆ + * \retval boolean_t FALSE: ADC转æ¢ä¸­ + */ +boolean_t Adc_PollJqrBusyState(void) +{ + return M0P_ADC->IFR_f.JQRIF; +} + +/** + * \brief + * 获å–采样值 + * + * \param [out] pu16AdcResult 采样值指针 + * + * \retval en_result_t Ok: æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Adc_GetSglResult(uint16_t* pu16AdcResult) +{ + if (NULL == pu16AdcResult) + { + return ErrorInvalidParameter; + } + + *pu16AdcResult = M0P_ADC->RESULT_f.RESULT; + + return Ok; +} + +/** + * \brief + * 查询ADCç»“æžœæ¯”è¾ƒåŒºé—´çŠ¶æ€ + * + * \retval boolean_t TRUE: ADC转æ¢å®Œæˆ + * \retval boolean_t FALSE: ADC转æ¢ä¸­ + * \param none + * + */ +boolean_t Adc_PollRegBusyState(void) +{ + return M0P_ADC->IFR_f.REGIF; +} +/** + * \brief + * 查询ADCç»“æžœæ¯”è¾ƒä¸Šé˜ˆå€¼çŠ¶æ€ + * + * \retval boolean_t TRUE: ADC转æ¢å®Œæˆ + * \retval boolean_t FALSE: ADC转æ¢ä¸­ + * \param none + * + */ +boolean_t Adc_PollHTBusyState(void) +{ + return M0P_ADC->IFR_f.HTIF; +} +/** + * \brief + * 查询ADCç»“æžœæ¯”è¾ƒåŒºé—´çŠ¶æ€ + * + * \retval boolean_t TRUE: ADC转æ¢å®Œæˆ + * \retval boolean_t FALSE: ADC转æ¢ä¸­ + * \param none + * + */ +boolean_t Adc_PollLtBusyState(void) +{ + return M0P_ADC->IFR_f.LTIF; +} +/** + * \brief + * 获å–采样值 + * + * \param [out] pu16AdcResult 采样值指针 + * \param [in] SQRChannelIndex 顺åºæ‰«æ通é“åºå· + * + * \retval en_result_t Ok: æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Adc_GetSqrResult(uint16_t* pu16AdcResult,uint8_t SQRChannelIndex) +{ + volatile uint32_t *BaseSqrResultAddress =(volatile uint32_t *) &(M0P_ADC->SQRRESULT0); + + if (NULL == pu16AdcResult) + { + return ErrorInvalidParameter; + } + + if(SQRChannelIndex > 15) + { + return ErrorInvalidParameter; + } + + *pu16AdcResult = (uint16_t)(*(BaseSqrResultAddress + SQRChannelIndex)); + + return Ok; +} + +/** + * \brief + * 获å–æ’队扫æ采样值 + * + * \param [out] pu16AdcResult 采样值指针 + * \param [in] JQRChannelIndex æ’队扫æ通é“åºå· + * + * \retval en_result_t Ok: æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Adc_GetJqrResult(uint16_t* pu16AdcResult,uint8_t JQRChannelIndex) +{ + volatile uint32_t *BaseJqrResultAddress =(volatile uint32_t *) &(M0P_ADC->JQRRESULT0); + if (NULL == pu16AdcResult) + { + return ErrorInvalidParameter; + } + + if(JQRChannelIndex > 3) + { + return ErrorInvalidParameter; + } + *pu16AdcResult = (uint16_t)(*(BaseJqrResultAddress + JQRChannelIndex)); + return Ok; +} +/** + * \brief + * 获å–累加采样值 + * + * \param [out] pu32AdcAccResult 累加采样值指针 + * + * \retval en_result_t Ok: æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Adc_GetAccResult(uint32_t* pu32AdcAccResult) +{ + if (NULL == pu32AdcAccResult) + { + return ErrorInvalidParameter; + } + + *pu32AdcAccResult = M0P_ADC->RESULTACC_f.RESULTACC; + + return Ok; +} + +/** + * \brief + * 清零累加采样值 + * + * \param æ—  + * + * \retval æ—  + */ +void Adc_ClrAccResult(void) +{ + M0P_ADC->CR1_f.RACCCLR = 0u; +} + + +/** + * \brief + * 设置ADCå‚考电压 + * + * \param [in] enAdcRefVolSel ADCå‚考电压 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Adc_SetVref(en_adc_ref_vol_sel_t enAdcRefVolSel) +{ + if (enAdcRefVolSel > RefVolSelAVDD) + { + return ErrorInvalidParameter; + } + if((RefVolSelInBgr1p5 == enAdcRefVolSel) || (RefVolSelInBgr2p5 == enAdcRefVolSel)) + { + M0P_ADC->CR0_f.INREFEN = 1; + }else + { + M0P_ADC->CR0_f.INREFEN = 0; + } + M0P_ADC->CR0_f.REF = enAdcRefVolSel; + return Ok; +} +/** + * \brief + * 设置ADC结果对é½æ–¹å¼ + * + * \param [in] enAlign ADC结果对é½æ–¹å¼ + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Adc_SetAlign(en_adc_align_t enAlign) +{ + M0P_ADC->CR1_f.ALIGN = enAlign; + return Ok; +} +//@} // AdcGroup + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/adt.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/adt.c new file mode 100644 index 0000000000..471cf96a1d --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/adt.c @@ -0,0 +1,1952 @@ +/****************************************************************************** +* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file adt.c + ** + ** Low Voltage Detect driver API. + ** @link Lvd Group Some description @endlink + ** + ** - 2018-04-18 Husj First Version + ** + ******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "adt.h" + +/** + ****************************************************************************** + ** \addtogroup AdtGroup + ******************************************************************************/ +//@{ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') * + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') + ******************************************************************************/ +static func_ptr_t pfnAdtIrqCbk[3][16] = {NULL}; + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + *****************************************************************************/ + +/************************************************* + * \brief + * 使能NVIC中ADT中断 + * + * \param [in] enIrqn ä¸­æ–­å· + * + * \retval æ—  + **************************************************/ +static void AdtEnableNvic(IRQn_Type enIrqn) +{ + NVIC_ClearPendingIRQ(enIrqn); + NVIC_EnableIRQ(enIrqn); + NVIC_SetPriority(enIrqn, DDL_IRQ_LEVEL_DEFAULT); +} + +/************************************************** + * \brief + * 除能NVIC中ADT中断 + * + * \param [in] enIrqn ä¸­æ–­å· + * + * \retval æ—  + **************************************************/ +static void AdtDisableNvic(IRQn_Type enIrqn) +{ + NVIC_ClearPendingIRQ(enIrqn); + NVIC_DisableIRQ(enIrqn); + NVIC_SetPriority(enIrqn, DDL_IRQ_LEVEL_DEFAULT); +} + +/*************************************************** + * \brief + * ADT中断æœåŠ¡ç¨‹åº + * + * \param [in] u8Param 未使用 + * + * \retval æ—  + ****************************************************/ +void Adt_IRQHandler(uint8_t u8Param) +{ + uint8_t u8Adt = u8Param - 4; + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*u8Adt); + + if (TRUE == pstcM0PAdt->IFR_f.CMAF) + { + if (NULL != pfnAdtIrqCbk[u8Adt][AdtCMAIrq]) + { + pfnAdtIrqCbk[u8Adt][AdtCMAIrq](); + } + pstcM0PAdt->ICLR = ~(1<IFR_f.CMBF) + { + if (NULL != pfnAdtIrqCbk[u8Adt][AdtCMBIrq]) + { + pfnAdtIrqCbk[u8Adt][AdtCMBIrq](); + } + pstcM0PAdt->ICLR = ~(1<IFR_f.CMCF) + { + if (NULL != pfnAdtIrqCbk[u8Adt][AdtCMCIrq]) + { + pfnAdtIrqCbk[u8Adt][AdtCMCIrq](); + } + pstcM0PAdt->ICLR = ~(1<IFR_f.CMDF) + { + if (NULL != pfnAdtIrqCbk[u8Adt][AdtCMDIrq]) + { + pfnAdtIrqCbk[u8Adt][AdtCMDIrq](); + } + pstcM0PAdt->ICLR = ~(1<IFR_f.OVFF) + { + if (NULL != pfnAdtIrqCbk[u8Adt][AdtOVFIrq]) + { + pfnAdtIrqCbk[u8Adt][AdtOVFIrq](); + } + pstcM0PAdt->ICLR = ~(1<IFR_f.UDFF) + { + if (NULL != pfnAdtIrqCbk[u8Adt][AdtUDFIrq]) + { + pfnAdtIrqCbk[u8Adt][AdtUDFIrq](); + } + pstcM0PAdt->ICLR = ~(1<IFR_f.DTEF) + { + if (NULL != pfnAdtIrqCbk[u8Adt][AdtDTEIrq]) + { + pfnAdtIrqCbk[u8Adt][AdtDTEIrq](); + } + pstcM0PAdt->ICLR = ~(1<IFR_f.SAMLF) + { + if (NULL != pfnAdtIrqCbk[u8Adt][AdtSAMLIrq]) + { + pfnAdtIrqCbk[u8Adt][AdtSAMLIrq](); + } + pstcM0PAdt->ICLR = ~(1<IFR_f.SAMHF) + { + if (NULL != pfnAdtIrqCbk[u8Adt][AdtSAMHIrq]) + { + pfnAdtIrqCbk[u8Adt][AdtSAMHIrq](); + } + pstcM0PAdt->ICLR = ~(1<ICONR; + if (bEn) + { + u32Val |= 1u<ICONR = u32Val; + return Ok; +} + +/******************************************************************* + * \brief + * 获å–中断标志 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] enAdtIrq 中断类型 + * \param [in] pbFlag 中断标志指针 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + *****************************************************************/ +en_result_t Adt_GetIrqFlag(en_adt_unit_t enAdtUnit, + en_adt_irq_type_t enAdtIrq, + boolean_t* pbFlag) +{ + uint32_t u32Val; + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + u32Val = pstcM0PAdt->IFR; + *pbFlag = (u32Val>>enAdtIrq) & 0x1; + + return Ok; +} + +/**************************************************************** + * \brief + * 清除中断标志 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] enAdtIrq 中断类型 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ****************************************************************/ +en_result_t Adt_ClearIrqFlag(en_adt_unit_t enAdtUnit, + en_adt_irq_type_t enAdtIrq) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + pstcM0PAdt->ICLR = ~(1u<HCUPR; + pstcM0PAdt->HCUPR = u32Val | (1u<HCUPR = 0; + return Ok; +} + + +/** + * \brief + * é…置硬件递å‡äº‹ä»¶ + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] enAdtHwCntDwn 硬件递å‡äº‹ä»¶ + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Adt_ConfigHwCntDwn(en_adt_unit_t enAdtUnit, en_adt_hw_cnt_t enAdtHwCntDwn) +{ + uint32_t u32Val; + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if ((AdtTIM6 < enAdtUnit) || (AdtHwCntMax <= enAdtHwCntDwn)) + { + return ErrorInvalidParameter; + } + + u32Val = pstcM0PAdt->HCDOR; + pstcM0PAdt->HCDOR = u32Val | (1u<HCDOR = 0; + return Ok; +} + +/****************************************************************** + * \brief + * é…置硬件å¯åŠ¨äº‹ä»¶ + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] enAdtHwStart 硬件å¯åŠ¨äº‹ä»¶ + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + *******************************************************************/ +en_result_t Adt_ConfigHwStart(en_adt_unit_t enAdtUnit, en_adt_hw_trig_t enAdtHwStart) +{ + uint32_t u32Val; + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if ((AdtTIM6 < enAdtUnit) || (AdtHwTrigEnd <= enAdtHwStart)) + { + return ErrorInvalidParameter; + } + u32Val = pstcM0PAdt->HSTAR; + pstcM0PAdt->HSTAR = u32Val | (1u<HSTAR = 0; + return Ok; +} + +/********************************************************************* + * \brief + * 使能硬件å¯åŠ¨ + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + *********************************************************************/ +en_result_t Adt_EnableHwStart(en_adt_unit_t enAdtUnit) +{ + uint32_t u32Val; + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + u32Val = pstcM0PAdt->HSTAR; + pstcM0PAdt->HSTAR = u32Val | (1u<<31); + return Ok; +} + +/************************************************************************* + * \brief + * 除能硬件å¯åŠ¨ + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ************************************************************************/ +en_result_t Adt_DisableHwStart(en_adt_unit_t enAdtUnit) +{ + uint32_t u32Val; + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + u32Val = pstcM0PAdt->HSTAR; + pstcM0PAdt->HSTAR = u32Val & 0x7FFFFFFF; + return Ok; +} + +/**************************************************************** + * \brief + * é…置硬件åœæ­¢äº‹ä»¶ + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] enAdtHwStop 硬件åœæ­¢äº‹ä»¶ + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ***************************************************************/ +en_result_t Adt_ConfigHwStop(en_adt_unit_t enAdtUnit, en_adt_hw_trig_t enAdtHwStop) +{ + uint32_t u32Val; + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if ((AdtTIM6 < enAdtUnit) || (AdtHwTrigEnd <= enAdtHwStop)) + { + return ErrorInvalidParameter; + } + u32Val = pstcM0PAdt->HSTPR; + pstcM0PAdt->HSTPR = u32Val | (1u<HSTPR = 0; + return Ok; +} + +/************************************************************* + * \brief + * 使能硬件åœæ­¢ + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + **********************************************************/ +en_result_t Adt_EnableHwStop(en_adt_unit_t enAdtUnit) +{ + uint32_t u32Val; + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + u32Val = pstcM0PAdt->HSTPR; + pstcM0PAdt->HSTPR = u32Val | (1u<<31); + return Ok; +} + +/***************************************************************************** + * \brief + * 除能硬件åœæ­¢ + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ***************************************************************************/ +en_result_t Adt_DisableHwStop(en_adt_unit_t enAdtUnit) +{ + uint32_t u32Val; + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + u32Val = pstcM0PAdt->HSTPR; + pstcM0PAdt->HSTPR = u32Val & 0x7FFFFFFF; + return Ok; +} + +/************************************************************************** + * \brief + * é…置硬件清零事件 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] enAdtHwClear 硬件清零事件 + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + *************************************************************************/ +en_result_t Adt_ConfigHwClear(en_adt_unit_t enAdtUnit, en_adt_hw_trig_t enAdtHwClear) +{ + uint32_t u32Val; + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if ((AdtTIM6 < enAdtUnit) || (AdtHwTrigEnd <= enAdtHwClear)) + { + return ErrorInvalidParameter; + } + u32Val = pstcM0PAdt->HCELR & (1u<<31); + pstcM0PAdt->HCELR = u32Val | (1u<HCELR = 0; + return Ok; +} + +/*************************************************************************** + * \brief + * 使能硬件清零 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + *************************************************************************/ +en_result_t Adt_EnableHwClear(en_adt_unit_t enAdtUnit) +{ + uint32_t u32Val; + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + u32Val = pstcM0PAdt->HCELR; + pstcM0PAdt->HCELR = u32Val | (1u<<31); + return Ok; +} + +/************************************************************************ + * \brief + * 除能硬件清零 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + **********************************************************************/ +en_result_t Adt_DisableHwClear(en_adt_unit_t enAdtUnit) +{ + uint32_t u32Val; + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + u32Val = pstcM0PAdt->HCELR; + pstcM0PAdt->HCELR = u32Val & 0x7FFFFFFF; + return Ok; +} + +/******************************************************************* + * \brief + * é…置硬件æ•èŽ·A事件 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] enAdtHwCaptureA 硬件æ•èŽ·A事件选择 + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + *******************************************************************/ +en_result_t Adt_ConfigHwCaptureA(en_adt_unit_t enAdtUnit, en_adt_hw_trig_t enAdtHwCaptureA) +{ + uint32_t u32Val; + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if ((AdtTIM6 < enAdtUnit) || (AdtHwTrigEnd <= enAdtHwCaptureA)) + { + return ErrorInvalidParameter; + } + + u32Val = pstcM0PAdt->HCPAR; + pstcM0PAdt->HCPAR = u32Val | (1u<PCONR_f.CAPCA = 1; + return Ok; +} + +/************************************************************************ + * \brief + * 清除硬件æ•èŽ·A事件 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ***********************************************************************/ +en_result_t Adt_ClearHwCaptureA(en_adt_unit_t enAdtUnit) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + pstcM0PAdt->HCPAR = 0; + return Ok; +} + +/********************************************************************* + * \brief + * é…置硬件æ•èŽ·B事件 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] enAdtHwCaptureB 硬件æ•èŽ·B事件选择 + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ********************************************************************/ +en_result_t Adt_ConfigHwCaptureB(en_adt_unit_t enAdtUnit, en_adt_hw_trig_t enAdtHwCaptureB) +{ + uint32_t u32Val; + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if ((AdtTIM6 < enAdtUnit) || (AdtHwTrigEnd <= enAdtHwCaptureB)) + { + return ErrorInvalidParameter; + } + + u32Val = pstcM0PAdt->HCPBR; + pstcM0PAdt->HCPBR = u32Val | (1u<PCONR_f.CAPCB = 1; + return Ok; +} + +/******************************************************************** + * \brief + * 清除硬件æ•èŽ·B事件 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + *******************************************************************/ +en_result_t Adt_ClearHwCaptureB(en_adt_unit_t enAdtUnit) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + pstcM0PAdt->HCPBR = 0; + return Ok; +} + +/***************************************************************** + * \brief + * 软件åŒæ­¥å¼€å§‹ + * + * \param [in] pstcAdtSwSyncStart 软件åŒæ­¥å¼€å§‹æŒ‡é’ˆ + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ***************************************************************/ +en_result_t Adt_SwSyncStart(stc_adt_sw_sync_t* pstcAdtSwSyncStart) +{ + uint32_t u32Val = 0; + + if (NULL == pstcAdtSwSyncStart) + { + return ErrorInvalidParameter; + } + + if (pstcAdtSwSyncStart->bAdTim4) + { + u32Val |= 0x1; + } + if (pstcAdtSwSyncStart->bAdTim5) + { + u32Val |= 0x2; + } + if (pstcAdtSwSyncStart->bAdTim6) + { + u32Val |= 0x4; + } + + M0P_TIM4->SSTAR = u32Val; + return Ok; +} + +/*************************************************************** + * \brief + * 软件åŒæ­¥åœæ­¢ + * + * \param [in] pstcAdtSwSyncStop 软件åŒæ­¥åœæ­¢æŒ‡é’ˆ + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ***************************************************************/ +en_result_t Adt_SwSyncStop(stc_adt_sw_sync_t* pstcAdtSwSyncStop) +{ + uint32_t u32Val = 0; + + if (NULL == pstcAdtSwSyncStop) + { + return ErrorInvalidParameter; + } + + if (pstcAdtSwSyncStop->bAdTim4) + { + u32Val |= 0x1; + } + if (pstcAdtSwSyncStop->bAdTim5) + { + u32Val |= 0x2; + } + if (pstcAdtSwSyncStop->bAdTim6) + { + u32Val |= 0x4; + } + + M0P_TIM4->SSTPR = u32Val; + return Ok; +} + +/***************************************************************** + * \brief + * 软件åŒæ­¥æ¸…零 + * + * \param [in] pstcAdtSwSyncClear 软件åŒæ­¥æ¸…零指针 + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + *******************************************************************/ +en_result_t Adt_SwSyncClear(stc_adt_sw_sync_t* pstcAdtSwSyncClear) +{ + uint32_t u32Val = 0; + + if (NULL == pstcAdtSwSyncClear) + { + return ErrorInvalidParameter; + } + + if (pstcAdtSwSyncClear->bAdTim4) + { + u32Val |= 0x1; + } + if (pstcAdtSwSyncClear->bAdTim5) + { + u32Val |= 0x2; + } + if (pstcAdtSwSyncClear->bAdTim6) + { + u32Val |= 0x4; + } + + M0P_TIM4->SCLRR = u32Val; + return Ok; +} + +/******************************************************************* + * \brief + * 获å–软件åŒæ­¥è¿è¡ŒçŠ¶æ€ + * + * \param [in] pstcAdtSwSyncState ADV Timer软件åŒæ­¥è¿è¡ŒçŠ¶æ€æŒ‡é’ˆ + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + *******************************************************************/ +en_result_t Adt_GetSwSyncState(stc_adt_sw_sync_t* pstcAdtSwSyncState) +{ + if (NULL == pstcAdtSwSyncState) + { + return ErrorInvalidParameter; + } + + if (M0P_TIM4->SSTAR & 0x1) + { + pstcAdtSwSyncState->bAdTim4 = TRUE; + } + else + { + pstcAdtSwSyncState->bAdTim4 = FALSE; + } + if (M0P_TIM4->SSTAR & 0x2) + { + pstcAdtSwSyncState->bAdTim5 = TRUE; + } + else + { + pstcAdtSwSyncState->bAdTim5 = FALSE; + } + if (M0P_TIM4->SSTAR & 0x4) + { + pstcAdtSwSyncState->bAdTim6 = TRUE; + } + else + { + pstcAdtSwSyncState->bAdTim6 = FALSE; + } + return Ok; +} + +/************************************************************************ + * \brief + * AOS触å‘é…ç½® + * + * \param [in] pstcAdtAosTrigCfg 触å‘é…置指针 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ************************************************************************/ +en_result_t Adt_AosTrigConfig(stc_adt_aos_trig_cfg_t* pstcAdtAosTrigCfg) +{ + if (NULL == pstcAdtAosTrigCfg) + { + return ErrorInvalidParameter; + } + + M0P_TIM4->ITRIG_f.IAOS0S = pstcAdtAosTrigCfg->enAos0TrigSrc; + M0P_TIM4->ITRIG_f.IAOS1S = pstcAdtAosTrigCfg->enAos1TrigSrc; + M0P_TIM4->ITRIG_f.IAOS2S = pstcAdtAosTrigCfg->enAos2TrigSrc; + M0P_TIM4->ITRIG_f.IAOS3S = pstcAdtAosTrigCfg->enAos3TrigSrc; + return Ok; +} + +/********************************************************************** + * \brief + * 中断触å‘é…ç½® + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] pstcAdtIrqTrigCfg 触å‘é…置指针 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ***********************************************************************/ +en_result_t Adt_IrqTrigConfig(en_adt_unit_t enAdtUnit, + stc_adt_irq_trig_cfg_t* pstcAdtIrqTrigCfg) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if ((AdtTIM6 < enAdtUnit) || (NULL == pstcAdtIrqTrigCfg)) + { + return ErrorInvalidParameter; + } + + pstcM0PAdt->CR_f.CMAE = pstcAdtIrqTrigCfg->bAdtCntMatchATrigEn; + pstcM0PAdt->CR_f.CMBE = pstcAdtIrqTrigCfg->bAdtCntMatchBTrigEn; + pstcM0PAdt->CR_f.CMCE = pstcAdtIrqTrigCfg->bAdtCntMatchCTrigEn; + pstcM0PAdt->CR_f.CMDE = pstcAdtIrqTrigCfg->bAdtCntMatchDTrigEn; + pstcM0PAdt->CR_f.OVFE = pstcAdtIrqTrigCfg->bAdtOverFlowTrigEn; + pstcM0PAdt->CR_f.UDFE = pstcAdtIrqTrigCfg->bAdtUnderFlowTrigEn; + pstcM0PAdt->CR_f.DMA_G_CMA = pstcAdtIrqTrigCfg->bAdtCntMatchATrigDmaEn; + pstcM0PAdt->CR_f.DMA_G_CMB = pstcAdtIrqTrigCfg->bAdtCntMatchBTrigDmaEn; + pstcM0PAdt->CR_f.DMA_G_CMC = pstcAdtIrqTrigCfg->bAdtCntMatchCTrigDmaEn; + pstcM0PAdt->CR_f.DMA_G_CMD = pstcAdtIrqTrigCfg->bAdtCntMatchDTrigDmaEn; + pstcM0PAdt->CR_f.DMA_G_OVF = pstcAdtIrqTrigCfg->bAdtOverFlowTrigDmaEn; + pstcM0PAdt->CR_f.DMA_G_UDF = pstcAdtIrqTrigCfg->bAdtUnderFlowTrigDmaEn; + pstcM0PAdt->CR_f.DMA_S_CMA = pstcAdtIrqTrigCfg->bAdtSpecilMatchATrigDmaEn; + pstcM0PAdt->CR_f.DMA_S_CMB = pstcAdtIrqTrigCfg->bAdtSpecilMatchBTrigDmaEn; + + return Ok; +} + +/************************************************************************* + * \brief + * 端å£è§¦å‘é…ç½® + * + * \param [in] enAdtTrigPort 触å‘ç«¯å£ + * \param [in] pstcAdtPortTrigCfg 触å‘é…置指针 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + *************************************************************************/ +en_result_t Adt_PortTrigConfig(en_adt_trig_port_t enAdtTrigPort, + stc_adt_port_trig_cfg_t* pstcAdtPortTrigCfg) +{ + if (NULL == pstcAdtPortTrigCfg) + { + return ErrorInvalidParameter; + } + + switch (enAdtTrigPort) + { + case AdtTrigA: + M0P_TIM4->TTRIG_f.TRIGAS = pstcAdtPortTrigCfg->enTrigSrc; + M0P_TIM4->FCONR_f.NOFIENTA = pstcAdtPortTrigCfg->bFltEn; + M0P_TIM4->FCONR_f.NOFICKTA = pstcAdtPortTrigCfg->enFltClk; + break; + + case AdtTrigB: + M0P_TIM4->TTRIG_f.TRIGBS = pstcAdtPortTrigCfg->enTrigSrc; + M0P_TIM4->FCONR_f.NOFIENTB = pstcAdtPortTrigCfg->bFltEn; + M0P_TIM4->FCONR_f.NOFICKTB = pstcAdtPortTrigCfg->enFltClk; + break; + + case AdtTrigC: + M0P_TIM4->TTRIG_f.TRIGCS = pstcAdtPortTrigCfg->enTrigSrc; + M0P_TIM4->FCONR_f.NOFIENTC = pstcAdtPortTrigCfg->bFltEn; + M0P_TIM4->FCONR_f.NOFICKTC = pstcAdtPortTrigCfg->enFltClk; + break; + + case AdtTrigD: + M0P_TIM4->TTRIG_f.TRIGDS = pstcAdtPortTrigCfg->enTrigSrc; + M0P_TIM4->FCONR_f.NOFIENTD = pstcAdtPortTrigCfg->bFltEn; + M0P_TIM4->FCONR_f.NOFICKTD = pstcAdtPortTrigCfg->enFltClk; + break; + + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/*********************************************************************** + * \brief + * CHxX端å£é…ç½® + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] enAdtCHxXPort CHxXç«¯å£ + * \param [in] pstcAdtCHxXCfg CHxX端å£é…置指针 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + *********************************************************************/ +en_result_t Adt_CHxXPortConfig(en_adt_unit_t enAdtUnit, + en_adt_CHxX_port_t enAdtCHxXPort, + stc_adt_CHxX_port_cfg_t* pstcAdtCHxXCfg) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if ((AdtTIM6 < enAdtUnit) || (NULL == pstcAdtCHxXCfg)) + { + return ErrorInvalidParameter; + } + + switch (enAdtCHxXPort) + { + case AdtCHxA: + pstcM0PAdt->PCONR_f.CAPCA = pstcAdtCHxXCfg->enCap; + pstcM0PAdt->PCONR_f.STACA = pstcAdtCHxXCfg->enStaOut; + pstcM0PAdt->PCONR_f.STPCA = pstcAdtCHxXCfg->enStpOut; + pstcM0PAdt->PCONR_f.STASTPSA = pstcAdtCHxXCfg->enStaStp; + pstcM0PAdt->PCONR_f.CMPCA = pstcAdtCHxXCfg->enCmpc; + pstcM0PAdt->PCONR_f.PERCA = pstcAdtCHxXCfg->enPerc; + pstcM0PAdt->PCONR_f.OUTENA = pstcAdtCHxXCfg->bOutEn; + pstcM0PAdt->PCONR_f.DISSELA = pstcAdtCHxXCfg->enDisSel; + pstcM0PAdt->PCONR_f.DISVALA = pstcAdtCHxXCfg->enDisVal; + pstcM0PAdt->FCONR_f.NOFIENGA = pstcAdtCHxXCfg->bFltEn; + pstcM0PAdt->FCONR_f.NOFICKGA = pstcAdtCHxXCfg->enFltClk; + break; + + case AdtCHxB: + pstcM0PAdt->PCONR_f.CAPCB = pstcAdtCHxXCfg->enCap; + pstcM0PAdt->PCONR_f.STACB = pstcAdtCHxXCfg->enStaOut; + pstcM0PAdt->PCONR_f.STPCB = pstcAdtCHxXCfg->enStpOut; + pstcM0PAdt->PCONR_f.STASTPSB = pstcAdtCHxXCfg->enStaStp; + pstcM0PAdt->PCONR_f.CMPCB = pstcAdtCHxXCfg->enCmpc; + pstcM0PAdt->PCONR_f.PERCB = pstcAdtCHxXCfg->enPerc; + pstcM0PAdt->PCONR_f.OUTENB = pstcAdtCHxXCfg->bOutEn; + pstcM0PAdt->PCONR_f.DISSELB = pstcAdtCHxXCfg->enDisSel; + pstcM0PAdt->PCONR_f.DISVALB = pstcAdtCHxXCfg->enDisVal; + pstcM0PAdt->FCONR_f.NOFIENGB = pstcAdtCHxXCfg->bFltEn; + pstcM0PAdt->FCONR_f.NOFICKGB = pstcAdtCHxXCfg->enFltClk; + break; + + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/************************************************************************ + * \brief + * 使能端å£åˆ¹è½¦ + * + * \param [in] port ç«¯å£ + * \param [in] pstcAdtBrkPtCfg 端å£åˆ¹è½¦é…置指针 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ************************************************************************/ +en_result_t Adt_EnableBrakePort(uint8_t port, stc_adt_break_port_cfg_t* pstcAdtBrkPtCfg) +{ + uint32_t u32Val; + + if (NULL == pstcAdtBrkPtCfg) + { + return ErrorInvalidParameter; + } + + u32Val = M0P_TIM4->PTBKP; + u32Val &= ~(1u<PTBKP = u32Val | (pstcAdtBrkPtCfg->enPol<PTBKS; + M0P_TIM4->PTBKS = u32Val | (1u<PTBKS = 0; +} + +/********************************************************************* + * \brief + * 无效æ¡ä»¶3é…ç½® + * + * \param [in] pstcAdtDisable3 无效æ¡ä»¶3é…置指针 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ********************************************************************/ +en_result_t Adt_Disable3Cfg(stc_adt_disable_3_cfg_t* pstcAdtDisable3) +{ + uint8_t i; + + if (NULL == pstcAdtDisable3) + { + return ErrorInvalidParameter; + } + + Adt_ClearBrakePort(); + for (i = 0; i <= 15; i++) + { + if (TRUE == pstcAdtDisable3->stcBrkPtCfg[i].bPortEn) + { + Adt_EnableBrakePort(i, &pstcAdtDisable3->stcBrkPtCfg[i]); + } + } + + M0P_TIM4->AOSSR_f.BFILTEN = pstcAdtDisable3->bFltEn; + M0P_TIM4->AOSSR_f.BFILTS = pstcAdtDisable3->enFltClk; + M0P_TIM4->AOSSR_f.SOFTBK = pstcAdtDisable3->bSwBrk; + + return Ok; +} + +/******************************************************************* + * \brief + * 获å–端å£åˆ¹è½¦æ ‡å¿— + * + * \param none + * + * \retval TRUE or FALSE + ******************************************************************/ +boolean_t Adt_GetPortBrakeFlag(void) +{ + return M0P_TIM4->AOSSR_f.FBRAKE; +} + +/****************************************************************** + * \brief + * 清除端å£åˆ¹è½¦æ ‡å¿— + * + * \param none + * + * \retval none + ******************************************************************/ +void Adt_ClearPortBrakeFlag(void) +{ + M0P_TIM4->AOSCL_f.FBRAKE = 0; +} + +/******************************************************************** + * \brief + * 无效æ¡ä»¶1é…ç½® + * + * \param [in] pstcAdtDisable1 无效æ¡ä»¶1é…置指针 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ********************************************************************/ +en_result_t Adt_Disable1Cfg(stc_adt_disable_1_cfg_t* pstcAdtDisable1) +{ + + if (NULL == pstcAdtDisable1) + { + return ErrorInvalidParameter; + } + + M0P_TIM4->AOSSR_f.SMH2 = pstcAdtDisable1->bTim6OutSH; + M0P_TIM4->AOSSR_f.SMH1 = pstcAdtDisable1->bTim5OutSH; + M0P_TIM4->AOSSR_f.SMH0 = pstcAdtDisable1->bTim4OutSH; + M0P_TIM4->AOSSR_f.SML2 = pstcAdtDisable1->bTim6OutSL; + M0P_TIM4->AOSSR_f.SML1 = pstcAdtDisable1->bTim5OutSL; + M0P_TIM4->AOSSR_f.SML0 = pstcAdtDisable1->bTim4OutSL; + + return Ok; +} + +/******************************************************************** + * \brief + * 获å–åŒé«˜åŒä½Žåˆ¹è½¦æ ‡å¿— + * + * \param none + * + * \retval TRUE or FALSE + ********************************************************************/ +boolean_t Adt_GetSameBrakeFlag(void) +{ + return M0P_TIM4->AOSSR_f.FSAME; +} + +/********************************************************************* + * \brief + * 清除åŒé«˜åŒä½Žåˆ¹è½¦æ ‡å¿— + * + * \param none + * + * \retval none + *********************************************************************/ +void Adt_ClearSameBrakeFlag(void) +{ + M0P_TIM4->AOSCL_f.FSAME = 0; +} + +/******************************************************************** + * \brief + * PWM展频é…ç½® + * + * \param [in] pstcAdtPwmDitherCfg PWM展频é…置指针 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + *********************************************************************/ +en_result_t Adt_PwmDitherConfig(en_adt_unit_t enAdtUnit, stc_adt_pwm_dither_cfg_t* pstcAdtPwmDitherCfg) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (NULL == pstcAdtPwmDitherCfg) + { + return ErrorInvalidParameter; + } + + pstcM0PAdt->CR_f.DITENS = pstcAdtPwmDitherCfg->enAdtPDType; + pstcM0PAdt->CR_f.DITENB = pstcAdtPwmDitherCfg->bTimxBPDEn; + pstcM0PAdt->CR_f.DITENA = pstcAdtPwmDitherCfg->bTimxAPDEn; + + return Ok; +} + +/********************************************************************** + * \brief + * ADTåˆå§‹åŒ– + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] pstcAdtBaseCntCfg 计数é…置指针 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + **********************************************************************/ +en_result_t Adt_Init(en_adt_unit_t enAdtUnit, stc_adt_basecnt_cfg_t* pstcAdtBaseCntCfg) +{ + int32_t i; + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if ((AdtTIM6 < enAdtUnit) || (NULL == pstcAdtBaseCntCfg)) + { + return ErrorInvalidParameter; + } + + if (AdtTriangleModeB < pstcAdtBaseCntCfg->enCntMode) + { + return ErrorInvalidParameter; + } + + pstcM0PAdt->GCONR_f.MODE = pstcAdtBaseCntCfg->enCntMode; + pstcM0PAdt->GCONR_f.DIR = pstcAdtBaseCntCfg->enCntDir; + pstcM0PAdt->GCONR_f.CKDIV = pstcAdtBaseCntCfg->enCntClkDiv; + + for (i = 0; i < 16; i++) + { + pfnAdtIrqCbk[enAdtUnit][i] = NULL; + } + + AdtEnableNvic((IRQn_Type)((int32_t)TIM4_IRQn + (int32_t)enAdtUnit)); + + return Ok; +} + +/************************************************************************ + * \brief + * ADT Deinit + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ***********************************************************************/ +en_result_t Adt_DeInit(en_adt_unit_t enAdtUnit) +{ + int32_t i; + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + pstcM0PAdt->GCONR_f.START = 0; + + AdtDisableNvic((IRQn_Type)((int32_t)TIM4_IRQn + (int32_t)enAdtUnit)); + + for (i = 0; i < 16; i++) + { + pfnAdtIrqCbk[enAdtUnit][i] = NULL; + } + + return Ok; +} + +/*********************************************************************** + * \brief + * 开始计数 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ***********************************************************************/ +en_result_t Adt_StartCount(en_adt_unit_t enAdtUnit) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + pstcM0PAdt->GCONR_f.START = 1; + + return Ok; +} + +/*********************************************************************** + * \brief + * åœæ­¢è®¡æ•° + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + **********************************************************************/ +en_result_t Adt_StopCount(en_adt_unit_t enAdtUnit) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + pstcM0PAdt->GCONR_f.START = 0; + + return Ok; +} + +/******************************************************************** + * \brief + * 设置计数值 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] u16Value 计数值 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * ErrorInvalidParameter: 无效å‚æ•° + *******************************************************************/ +en_result_t Adt_SetCount(en_adt_unit_t enAdtUnit, uint16_t u16Value) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + pstcM0PAdt->CNTER_f.CNT = u16Value; + return Ok; +} + +/******************************************************************** + * \brief + * 获å–计数值 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] u16Value 计数值 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * ErrorInvalidParameter: 无效å‚æ•° + *******************************************************************/ +uint16_t Adt_GetCount(en_adt_unit_t enAdtUnit) +{ + uint16_t u16Value; + + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + u16Value = pstcM0PAdt->CNTER_f.CNT; + + return u16Value; +} + +/************************************************************************** + * \brief + * 清除计数值 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] u16Value 计数值 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + **************************************************************************/ +en_result_t Adt_ClearCount(en_adt_unit_t enAdtUnit) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + pstcM0PAdt->CNTER_f.CNT = 0; + return Ok; +} + +/************************************************************************* + * \brief + * 获å–è®¡æ•°çŠ¶æ€ + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] pstcAdtCntState 计数状æ€æŒ‡é’ˆ + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + *************************************************************************/ +en_result_t Adt_GetCntState(en_adt_unit_t enAdtUnit, stc_adt_cntstate_cfg_t* pstcAdtCntState) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if ((AdtTIM6 < enAdtUnit) || (NULL == pstcAdtCntState)) + { + return ErrorInvalidParameter; + } + + pstcAdtCntState->u16Counter = pstcM0PAdt->CNTER_f.CNT; + pstcAdtCntState->enCntDir = pstcM0PAdt->STFLR_f.DIRF; + pstcAdtCntState->u8ValidPeriod = pstcM0PAdt->STFLR_f.VPERNUM; + pstcAdtCntState->bCMSBDF = pstcM0PAdt->STFLR_f.CMSBDF; + pstcAdtCntState->bCMSBUF = pstcM0PAdt->STFLR_f.CMSBUF; + pstcAdtCntState->bCMSADF = pstcM0PAdt->STFLR_f.CMSADF; + pstcAdtCntState->bCMSAUF = pstcM0PAdt->STFLR_f.CMSAUF; + pstcAdtCntState->bDTEF = pstcM0PAdt->STFLR_f.DTEF; + pstcAdtCntState->bUDFF = pstcM0PAdt->STFLR_f.UDFF; + pstcAdtCntState->bOVFF = pstcM0PAdt->STFLR_f.OVFF; + pstcAdtCntState->bCMDF = pstcM0PAdt->STFLR_f.CMDF; + pstcAdtCntState->bCMCF = pstcM0PAdt->STFLR_f.CMCF; + pstcAdtCntState->bCMBF = pstcM0PAdt->STFLR_f.CMBF; + pstcAdtCntState->bCMAF = pstcM0PAdt->STFLR_f.CMAF; + + return Ok; +} + +/*********************************************************************** + * \brief + * é…置计数周期 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] u16Period 计数周期值 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ***********************************************************************/ +en_result_t Adt_SetPeriod(en_adt_unit_t enAdtUnit, uint16_t u16Period) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + pstcM0PAdt->PERAR = u16Period; + + return Ok; +} + +/*********************************************************************** + * \brief + * é…置计数周期缓冲 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] u16PeriodBuf 计数周期缓冲值 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ***********************************************************************/ +en_result_t Adt_SetPeriodBuf(en_adt_unit_t enAdtUnit, uint16_t u16PeriodBuf) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + pstcM0PAdt->PERBR = u16PeriodBuf; + pstcM0PAdt->BCONR_f.BENP = 1u; + + return Ok; +} + +/********************************************************************** + * \brief + * 清除计数周期缓冲 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + **********************************************************************/ +en_result_t Adt_ClearPeriodBuf(en_adt_unit_t enAdtUnit) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + pstcM0PAdt->BCONR_f.BENP = 0; + pstcM0PAdt->PERBR = 0; + + return Ok; +} + +/*********************************************************************** + * \brief + * é…置有效计数周期 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] pstcAdtValidPerCfg 有效计数周期é…置指针 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ***********************************************************************/ +en_result_t Adt_SetValidPeriod(en_adt_unit_t enAdtUnit, + stc_adt_validper_cfg_t* pstcAdtValidPerCfg) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if ((AdtTIM6 < enAdtUnit) || (NULL == pstcAdtValidPerCfg)) + { + return ErrorInvalidParameter; + } + + pstcM0PAdt->VPERR_f.PCNTS = pstcAdtValidPerCfg->enValidCnt; + pstcM0PAdt->VPERR_f.PCNTE = pstcAdtValidPerCfg->enValidCdt; + pstcM0PAdt->VPERR_f.GEPERID = pstcAdtValidPerCfg->bPeriodD; + pstcM0PAdt->VPERR_f.GEPERIC = pstcAdtValidPerCfg->bPeriodC; + pstcM0PAdt->VPERR_f.GEPERIB = pstcAdtValidPerCfg->bPeriodB; + pstcM0PAdt->VPERR_f.GEPERIA = pstcAdtValidPerCfg->bPeriodA; + + return Ok; +} + +/************************************************************************ + * \brief + * é…置比较输出计数基准值 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] enAdtCompare 比较基准 + * \param [in] u16Compare 比较基准值 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + *************************************************************************/ +en_result_t Adt_SetCompareValue(en_adt_unit_t enAdtUnit, + en_adt_compare_t enAdtCompare, + uint16_t u16Compare) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + if (AdtCompareA == enAdtCompare) + { + pstcM0PAdt->GCMAR = u16Compare; + } + else if (AdtCompareB == enAdtCompare) + { + pstcM0PAdt->GCMBR = u16Compare; + } + else if (AdtCompareC == enAdtCompare) + { + pstcM0PAdt->GCMCR = u16Compare; + } + else if (AdtCompareD == enAdtCompare) + { + pstcM0PAdt->GCMDR = u16Compare; + } + else + { + return ErrorInvalidParameter; + } + + return Ok; +} + +/************************************************************************ + * \brief + * é…置专用比较计数基准值 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] enAdtSpclCmp 专用比较基准值寄存器 + * \param [in] u16SpclCmp 比较基准值 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + *************************************************************************/ +en_result_t Adt_SetSpecilCompareValue(en_adt_unit_t enAdtUnit, + en_adt_special_compare_t enAdtSpclCmp, + uint16_t u16SpclCmp) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + if (AdtSpclCompA == enAdtSpclCmp) + { + pstcM0PAdt->SCMAR_f.SCMA = u16SpclCmp; + } + else if (AdtSpclCompB == enAdtSpclCmp) + { + pstcM0PAdt->SCMBR_f.SCMB = u16SpclCmp; + } + else + { + return ErrorInvalidParameter; + } + + return Ok; +} + +/********************************************************************** + * \brief + * é…置通用比较值/æ•èŽ·å€¼ç¼“å­˜ä¼ é€ + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] enAdtCHxXPort TIMxXç«¯å£ + * \param [in] bCompareBufEn 通用比较值缓存传é€ä½¿èƒ½ + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + **********************************************************************/ +en_result_t Adt_EnableValueBuf(en_adt_unit_t enAdtUnit, + en_adt_CHxX_port_t enAdtCHxXPort, + boolean_t bCompareBufEn) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + if (AdtCHxA == enAdtCHxXPort) + { + pstcM0PAdt->BCONR_f.BENA = bCompareBufEn; + } + else if (AdtCHxB == enAdtCHxXPort) + { + pstcM0PAdt->BCONR_f.BENB = bCompareBufEn; + } + else + { + return ErrorInvalidParameter; + } + + return Ok; +} + +/*********************************************************************** + * \brief + * 清除比较输出计数值/æ•èŽ·å€¼ç¼“å­˜ + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] enAdtCHxXPort TIMxXç«¯å£ + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + **********************************************************************/ +en_result_t Adt_ClearValueBuf(en_adt_unit_t enAdtUnit, + en_adt_CHxX_port_t enAdtCHxXPort) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + if (AdtCHxA == enAdtCHxXPort) + { + pstcM0PAdt->GCMCR = 0; + pstcM0PAdt->BCONR_f.BENA = 0; + } + else if (AdtCHxB == enAdtCHxXPort) + { + pstcM0PAdt->GCMDR = 0; + pstcM0PAdt->BCONR_f.BENB = 0; + } + else + { + return ErrorInvalidParameter; + } + + return Ok; +} + +/*********************************************************************** + * \brief + * 获å–æ•èŽ·å€¼ + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] enAdtCHxXPort TIMxXç«¯å£ + * \param [in] pu16Capture æ•èŽ·å€¼æŒ‡é’ˆ + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ***********************************************************************/ +en_result_t Adt_GetCaptureValue(en_adt_unit_t enAdtUnit, + en_adt_CHxX_port_t enAdtCHxXPort, + uint16_t* pu16Capture) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + if (AdtCHxA == enAdtCHxXPort) + { + *pu16Capture = pstcM0PAdt->GCMAR_f.GCMA; + } + else if (AdtCHxB == enAdtCHxXPort) + { + *pu16Capture = pstcM0PAdt->GCMBR_f.GCMB; + } + else + { + return ErrorInvalidParameter; + } + return Ok; +} + +/********************************************************************** + * \brief + * 获å–æ•èŽ·ç¼“存值 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] enAdtCHxXPort TIMxXç«¯å£ + * \param [in] pu16CaptureBuf æ•èŽ·ç¼“存值指针 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ***********************************************************************/ +en_result_t Adt_GetCaptureBuf(en_adt_unit_t enAdtUnit, + en_adt_CHxX_port_t enAdtCHxXPort, + uint16_t* pu16CaptureBuf) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + if (AdtCHxA == enAdtCHxXPort) + { + *pu16CaptureBuf = pstcM0PAdt->GCMCR_f.GCMC; + } + else if (AdtCHxB == enAdtCHxXPort) + { + *pu16CaptureBuf = pstcM0PAdt->GCMDR_f.GCMD; + } + else + { + return ErrorInvalidParameter; + } + return Ok; +} + +/*********************************************************************** + * \brief + * 设置死区时间上基准值 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] u16Value 死区时间上基准值 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ************************************************************************/ +en_result_t Adt_SetDTUA(en_adt_unit_t enAdtUnit, + uint16_t u16Value) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + pstcM0PAdt->DTUAR = u16Value; + + + return Ok; +} + +/*********************************************************************** + * \brief + * 设置死区时间下基准值 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] u16Value 死区时间下基准值 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ***********************************************************************/ +en_result_t Adt_SetDTDA(en_adt_unit_t enAdtUnit, + uint16_t u16Value) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + pstcM0PAdt->DTDAR = u16Value; + + + return Ok; +} + +/****************************************************************** + * \brief + * é…置死区时间功能 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] bDTEn 死区功能使能 + * \param [in] bEqual DTDAR的值和DTUAR的值自动相等 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + *****************************************************************/ +en_result_t Adt_ConfigDT(en_adt_unit_t enAdtUnit, + boolean_t bDTEn, + boolean_t bEqual) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + pstcM0PAdt->DCONR_f.DTCEN = bDTEn; + pstcM0PAdt->DCONR_f.SEPA = bEqual; + + return Ok; +} + +/************************************************************************* + * \brief + * Z相输入å±è”½è®¾ç½® + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] pstcAdtZMaskCfg Z相输入å±è”½åŠŸèƒ½é…置指针 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + *************************************************************************/ +en_result_t Adt_ConfigZMask(en_adt_unit_t enAdtUnit, stc_adt_zmask_cfg_t* pstcAdtZMaskCfg) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if ((AdtTIM6 < enAdtUnit) || (NULL == pstcAdtZMaskCfg)) + { + return ErrorInvalidParameter; + } + + pstcM0PAdt->GCONR_f.ZMSK = pstcAdtZMaskCfg->enZMaskCycle; + pstcM0PAdt->GCONR_f.ZMSKPOS = pstcAdtZMaskCfg->bFltPosCntMaksEn; + pstcM0PAdt->GCONR_f.ZMSKREV = pstcAdtZMaskCfg->bFltRevCntMaksEn; + + return Ok; +} + +//@} // AdtGroup + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/aes.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/aes.c new file mode 100644 index 0000000000..e28a48275f --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/aes.c @@ -0,0 +1,176 @@ +/****************************************************************************** +*Copyright(C)2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file crc.c + ** + ** Common API of crc. + ** @link crcGroup Some description @endlink + ** + ** - 2017-05-16 + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "aes.h" +/** + ******************************************************************************* + ** \addtogroup CrcGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * \brief + * ADCåˆå§‹åŒ– + * + * \param [in] pu32Data å¾…åŠ å¯†æ•°æ® + * \param [in] pu32Key 加密KEY + * \param [out] pu32Cipher 加密åŽæ•°æ® + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t AES_Encrypt(uint32_t* pu32Data, uint32_t *pu32Key, uint32_t *pu32Cipher) +{ + if ((NULL == pu32Data)||(NULL == pu32Key)||(NULL == pu32Cipher)) + { + return ErrorInvalidParameter; + } + + //Key config + M0P_AES->KEY0 = pu32Key[0]; + M0P_AES->KEY1 = pu32Key[1]; + M0P_AES->KEY2 = pu32Key[2]; + M0P_AES->KEY3 = pu32Key[3]; + + //Data config + M0P_AES->DATA0 = pu32Data[0]; + M0P_AES->DATA1 = pu32Data[1]; + M0P_AES->DATA2 = pu32Data[2]; + M0P_AES->DATA3 = pu32Data[3]; + + M0P_AES->CR_f.MODE = 0;//Encry + M0P_AES->CR_f.START = 1; + while(M0P_AES->CR_f.START == 1) + { + ; + } + pu32Cipher[0] = M0P_AES->DATA0; + pu32Cipher[1] = M0P_AES->DATA1; + pu32Cipher[2] = M0P_AES->DATA2; + pu32Cipher[3] = M0P_AES->DATA3; + return Ok; +} + + +/** + * \brief + * ADCåˆå§‹åŒ– + * + * \param [in] pu32Cipher å¾…è§£å¯†æ•°æ® + * \param [in] pu32Key 加密KEY + * \param [out] pu32Data 解密åŽæ•°æ® + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t AES_Decrypt(uint32_t *pu32Cipher,uint32_t *pu32Key, uint32_t* pu32Plaintext) +{ + if ((NULL == pu32Plaintext)||(NULL == pu32Key)||(NULL == pu32Cipher)) + { + return ErrorInvalidParameter; + } + + //Key config + M0P_AES->KEY0 = pu32Key[0]; + M0P_AES->KEY1 = pu32Key[1]; + M0P_AES->KEY2 = pu32Key[2]; + M0P_AES->KEY3 = pu32Key[3]; + + //Data config + M0P_AES->DATA0 = pu32Cipher[0]; + M0P_AES->DATA1 = pu32Cipher[1]; + M0P_AES->DATA2 = pu32Cipher[2]; + M0P_AES->DATA3 = pu32Cipher[3]; + + M0P_AES->CR_f.MODE = 1;//UnEncry + M0P_AES->CR_f.START = 1; + while(M0P_AES->CR_f.START == 1) + { + ; + } + pu32Plaintext[0] = M0P_AES->DATA0; + pu32Plaintext[1] = M0P_AES->DATA1; + pu32Plaintext[2] = M0P_AES->DATA2; + pu32Plaintext[3] = M0P_AES->DATA3; + return Ok; +} +//@} // CrcGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/bgr.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/bgr.c new file mode 100644 index 0000000000..87bab21ed6 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/bgr.c @@ -0,0 +1,155 @@ +/****************************************************************************** +*Copyright(C)2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file bgr.c + ** + ** Common API of bgr. + ** @link flashGroup Some description @endlink + ** + ** - 2018-05-08 + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "bgr.h" +/** + ******************************************************************************* + ** \addtogroup FlashGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ***************************************************************************** + ** \brief BGR 使能 + ** + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +en_result_t Bgr_BgrEnable(void) +{ + Sysctrl_SetPeripheralGate(SysctrlPeripheralAdcBgr, TRUE); + M0P_BGR->CR_f.BGR_EN = TRUE; + + delay10us(2); + + return Ok; +} + +/** + ***************************************************************************** + ** \brief BGR ç¦æ­¢ + ** + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +en_result_t Bgr_BgrDisable(void) +{ + Sysctrl_SetPeripheralGate(SysctrlPeripheralAdcBgr, TRUE); + M0P_BGR->CR_f.BGR_EN = FALSE; + + return Ok; +} + +/** + ***************************************************************************** + ** \brief BGR 温度传感器使能 + ** + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +en_result_t Bgr_TempSensorEnable(void) +{ + Sysctrl_SetPeripheralGate(SysctrlPeripheralAdcBgr, TRUE); + M0P_BGR->CR_f.TS_EN = TRUE; + + delay10us(2); + + return Ok; +} + +/** + ***************************************************************************** + ** \brief BGR 温度传感器ç¦æ­¢ + ** + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +en_result_t Bgr_TempSensorDisable(void) +{ + Sysctrl_SetPeripheralGate(SysctrlPeripheralAdcBgr, TRUE); + M0P_BGR->CR_f.TS_EN = FALSE; + + return Ok; +} + + +//@} // BgrGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/bt.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/bt.c new file mode 100644 index 0000000000..ea4014e088 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/bt.c @@ -0,0 +1,1608 @@ +/****************************************************************************** +*Copyright(C)2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file bt.c + ** + ** Common API of base timer. + ** @link btGroup Some description @endlink + ** + ** - 2018-04-18 First Version + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "bt.h" +/** + ******************************************************************************* + ** \addtogroup BtGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define IS_VALID_TIM(x) (TIM0 == (x) ||\ + TIM1 == (x) ||\ + TIM2 == (x)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +static func_ptr_t pfnTim0Callback = NULL; +static func_ptr_t pfnTim1Callback = NULL; +static func_ptr_t pfnTim2Callback = NULL; + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ***************************************************************************** + ** \brief Base Timer 中断标志获å–(模å¼0/1/23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] enTim3Irq 中断类型 + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +boolean_t Bt_GetIntFlag(en_bt_unit_t enUnit, en_bt_irq_type_t enBtIrq) +{ + boolean_t bRetVal = FALSE; + uint32_t u32Val; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + + ASSERT(IS_VALID_TIM(enUnit)); + + u32Val = pstcM0PBt->IFR; + bRetVal = (u32Val>>enBtIrq) & 0x1; + + return bRetVal; +} + +/** + ***************************************************************************** + ** \brief Base Timer 中断标志清除(模å¼0/1/23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] enTim3Irq 中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_ClearIntFlag(en_bt_unit_t enUnit, en_bt_irq_type_t enBtIrq) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->ICLR = ~(1u<ICLR_f.UIF = 0; + pstcM0PBt->ICLR_f.CA0F = 0; + pstcM0PBt->ICLR_f.CB0F = 0; + pstcM0PBt->ICLR_f.BIF = 0; + pstcM0PBt->ICLR_f.TIF = 0; + pstcM0PBt->ICLR_f.CA0E = 0; + pstcM0PBt->ICLR_f.CB0E = 0; + + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 中断使能(模å¼0) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_Mode0_EnableIrq(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M0CR_f.UIE = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 中断ç¦æ­¢(模å¼0) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_Mode0_DisableIrq(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M0CR_f.UIE = FALSE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 中断使能(模å¼1) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] enTim3Irq 中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_Mode1_EnableIrq (en_bt_unit_t enUnit, en_bt_irq_type_t enBtIrq) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE1_TypeDef *pstcM0PBt = (M0P_TIM0_MODE1_TypeDef *)((uint32_t)M0P_TIM0_MODE1+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + switch (enBtIrq) + { + case BtUevIrq: + pstcM0PBt->M1CR_f.UIE = TRUE; + break; + case BtCA0Irq: + pstcM0PBt->CR0_f.CIEA = TRUE; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 中断ç¦æ­¢(模å¼1) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] enTim3Irq 中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_Mode1_DisableIrq (en_bt_unit_t enUnit, en_bt_irq_type_t enBtIrq) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE1_TypeDef *pstcM0PBt = (M0P_TIM0_MODE1_TypeDef *)((uint32_t)M0P_TIM0_MODE1+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + + switch (enBtIrq) + { + case BtUevIrq: + pstcM0PBt->M1CR_f.UIE = FALSE; + break; + case BtCA0Irq: + pstcM0PBt->CR0_f.CIEA = FALSE; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 中断使能(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] enTim3Irq 中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_Mode23_EnableIrq (en_bt_unit_t enUnit, en_bt_irq_type_t enBtIrq) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + + switch (enBtIrq) + { + case BtUevIrq: + pstcM0PBt->M23CR_f.UIE = TRUE; + break; + case BtCA0Irq: + pstcM0PBt->CRCH0_f.CIEA = TRUE; + break; + case BtCB0Irq: + pstcM0PBt->CRCH0_f.CIEB = TRUE; + break; + case BtBkIrq: + pstcM0PBt->M23CR_f.BIE = TRUE; + break; + case BtTrigIrq: + pstcM0PBt->M23CR_f.TIE = TRUE; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 中断ç¦æ­¢(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] enTim3Irq 中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_Mode23_DisableIrq (en_bt_unit_t enUnit, en_bt_irq_type_t enBtIrq) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + + switch (enBtIrq) + { + case BtUevIrq: + pstcM0PBt->M23CR_f.UIE = FALSE; + break; + case BtCA0Irq: + pstcM0PBt->CRCH0_f.CIEA = FALSE; + break; + case BtCB0Irq: + pstcM0PBt->CRCH0_f.CIEB = FALSE; + break; + case BtBkIrq: + pstcM0PBt->M23CR_f.BIE = FALSE; + break; + case BtTrigIrq: + pstcM0PBt->M23CR_f.TIE = FALSE; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 中断æœåŠ¡å‡½æ•° + ** + ** + ** \param [in] u8Param Timer通é“选择（0 - TIM0ã€1 - TIM1ã€2 - TIM2） + ** + ** \retval NULL + *****************************************************************************/ +void Tim_IRQHandler(uint8_t u8Param) +{ + switch (u8Param) + { + case 0: + if(NULL != pfnTim0Callback) + { + pfnTim0Callback(); + } + break; + case 1: + if(NULL != pfnTim1Callback) + { + pfnTim1Callback(); + } + break; + case 2: + if(NULL != pfnTim2Callback) + { + pfnTim2Callback(); + } + break; + default: + ; + break; + } +} + + + +/** + ***************************************************************************** + ** \brief Base Timer åˆå§‹åŒ–é…ç½®(模å¼0) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_Mode0_Init(en_bt_unit_t enUnit, stc_bt_mode0_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + ASSERT(IS_VALID_TIM(enUnit)); + + switch (enUnit) + { + case TIM0: + { + M0P_TIM0_MODE0->M0CR_f.MODE = pstcConfig->enWorkMode; + M0P_TIM0_MODE0->M0CR_f.GATEP = pstcConfig->enGateP; + M0P_TIM0_MODE0->M0CR_f.GATE = pstcConfig->bEnGate; + M0P_TIM0_MODE0->M0CR_f.PRS = pstcConfig->enPRS; + M0P_TIM0_MODE0->M0CR_f.TOGEN = pstcConfig->bEnTog; + M0P_TIM0_MODE0->M0CR_f.CT = pstcConfig->enCT; + M0P_TIM0_MODE0->M0CR_f.MD = pstcConfig->enCntMode; + + pfnTim0Callback = pstcConfig->pfnTim0Cb; + } + break; + case TIM1: + { + M0P_TIM1_MODE0->M0CR_f.MODE = pstcConfig->enWorkMode; + M0P_TIM1_MODE0->M0CR_f.GATEP = pstcConfig->enGateP; + M0P_TIM1_MODE0->M0CR_f.GATE = pstcConfig->bEnGate; + M0P_TIM1_MODE0->M0CR_f.PRS = pstcConfig->enPRS; + M0P_TIM1_MODE0->M0CR_f.TOGEN = pstcConfig->bEnTog; + M0P_TIM1_MODE0->M0CR_f.CT = pstcConfig->enCT; + M0P_TIM1_MODE0->M0CR_f.MD = pstcConfig->enCntMode; + + pfnTim1Callback = pstcConfig->pfnTim1Cb; + } + break; + case TIM2: + { + M0P_TIM2_MODE0->M0CR_f.MODE = pstcConfig->enWorkMode; + M0P_TIM2_MODE0->M0CR_f.GATEP = pstcConfig->enGateP; + M0P_TIM2_MODE0->M0CR_f.GATE = pstcConfig->bEnGate; + M0P_TIM2_MODE0->M0CR_f.PRS = pstcConfig->enPRS; + M0P_TIM2_MODE0->M0CR_f.TOGEN = pstcConfig->bEnTog; + M0P_TIM2_MODE0->M0CR_f.CT = pstcConfig->enCT; + M0P_TIM2_MODE0->M0CR_f.MD = pstcConfig->enCntMode; + + pfnTim2Callback = pstcConfig->pfnTim2Cb; + + } + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer å¯åŠ¨è¿è¡Œ(模å¼0) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M0_Run(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M0CR_f.CTEN = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer åœæ­¢è¿è¡Œ(模å¼0) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M0_Stop(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M0CR_f.CTEN = FALSE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 翻转输出使能/ç¦æ­¢è®¾å®š(模å¼0) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] bEnOutput 翻转输出设定 TRUE:使能, FALSE:ç¦æ­¢ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M0_EnTOG_Output(en_bt_unit_t enUnit, boolean_t bEnOutput) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->DTR_f.MOE = bEnOutput; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 16ä½è®¡æ•°å™¨åˆå€¼è®¾ç½®(模å¼0) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] u16Data 16ä½åˆå€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M0_Cnt16Set(en_bt_unit_t enUnit, uint16_t u16Data) +{ + en_result_t enResult = Ok; + + ASSERT(IS_VALID_TIM(enUnit)); + + switch (enUnit) + { + case TIM0: + M0P_TIM0_MODE0->CNT_f.CNT = u16Data; + break; + case TIM1: + M0P_TIM1_MODE0->CNT_f.CNT = u16Data; + break; + case TIM2: + M0P_TIM2_MODE0->CNT_f.CNT = u16Data; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 16ä½è®¡æ•°å€¼èŽ·å–(模å¼0) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** + ** \retval 16bits计数值 + *****************************************************************************/ +uint16_t Bt_M0_Cnt16Get(en_bt_unit_t enUnit) +{ + uint16_t u16CntData = 0; + + ASSERT(IS_VALID_TIM(enUnit)); + + switch (enUnit) + { + case TIM0: + u16CntData = M0P_TIM0_MODE0->CNT_f.CNT; + break; + case TIM1: + u16CntData = M0P_TIM1_MODE0->CNT_f.CNT; + break; + case TIM2: + u16CntData = M0P_TIM2_MODE0->CNT_f.CNT; + break; + default: + u16CntData = 0; + break; + } + + return u16CntData; +} + +/** + ***************************************************************************** + ** \brief Base Timer é‡è½½å€¼è®¾ç½®(模å¼0) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] u16Data 16bitsé‡è½½å€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M0_ARRSet(en_bt_unit_t enUnit, uint16_t u16Data) +{ + en_result_t enResult = Ok; + + ASSERT(IS_VALID_TIM(enUnit)); + + switch (enUnit) + { + case TIM0: + M0P_TIM0_MODE0->ARR_f.ARR = u16Data; + break; + case TIM1: + M0P_TIM1_MODE0->ARR_f.ARR = u16Data; + break; + case TIM2: + M0P_TIM2_MODE0->ARR_f.ARR = u16Data; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 32ä½è®¡æ•°å™¨åˆå€¼è®¾ç½®(模å¼0) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] u32Data 32ä½åˆå€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M0_Cnt32Set(en_bt_unit_t enUnit, uint32_t u32Data) +{ + en_result_t enResult = Ok; + + ASSERT(IS_VALID_TIM(enUnit)); + + switch (enUnit) + { + case TIM0: + M0P_TIM0_MODE0->CNT32_f.CNT32 = u32Data; + break; + case TIM1: + M0P_TIM1_MODE0->CNT32_f.CNT32 = u32Data; + break; + case TIM2: + M0P_TIM2_MODE0->CNT32_f.CNT32 = u32Data; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 32ä½è®¡æ•°å€¼èŽ·å–(模å¼0) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** + ** \retval 32bits计数值 + *****************************************************************************/ +uint32_t Bt_M0_Cnt32Get(en_bt_unit_t enUnit) +{ + uint32_t u32CntData = 0; + + ASSERT(IS_VALID_TIM(enUnit)); + + switch (enUnit) + { + case TIM0: + u32CntData = M0P_TIM0_MODE0->CNT32_f.CNT32; + break; + case TIM1: + u32CntData = M0P_TIM1_MODE0->CNT32_f.CNT32; + break; + case TIM2: + u32CntData = M0P_TIM2_MODE0->CNT32_f.CNT32; + break; + default: + u32CntData = 0; + break; + } + + return u32CntData; +} + +/** + ***************************************************************************** + ** \brief Base Timer åˆå§‹åŒ–é…ç½®(模å¼1) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_Mode1_Init(en_bt_unit_t enUnit, stc_bt_mode1_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + ASSERT(IS_VALID_TIM(enUnit)); + + switch (enUnit) + { + case TIM0: + { + M0P_TIM0_MODE1->M1CR_f.MODE = pstcConfig->enWorkMode; + M0P_TIM0_MODE1->M1CR_f.PRS = pstcConfig->enPRS; + M0P_TIM0_MODE1->M1CR_f.CT = pstcConfig->enCT; + M0P_TIM0_MODE1->M1CR_f.ONESHOT = pstcConfig->enOneShot; + + pfnTim0Callback = pstcConfig->pfnTim0Cb; + } + break; + case TIM1: + { + M0P_TIM1_MODE1->M1CR_f.MODE = pstcConfig->enWorkMode; + M0P_TIM1_MODE1->M1CR_f.PRS = pstcConfig->enPRS; + M0P_TIM1_MODE1->M1CR_f.CT = pstcConfig->enCT; + M0P_TIM1_MODE1->M1CR_f.ONESHOT = pstcConfig->enOneShot; + + pfnTim1Callback = pstcConfig->pfnTim1Cb; + } + break; + case TIM2: + { + M0P_TIM2_MODE1->M1CR_f.MODE = pstcConfig->enWorkMode; + M0P_TIM2_MODE1->M1CR_f.PRS = pstcConfig->enPRS; + M0P_TIM2_MODE1->M1CR_f.CT = pstcConfig->enCT; + M0P_TIM2_MODE1->M1CR_f.ONESHOT = pstcConfig->enOneShot; + + pfnTim2Callback = pstcConfig->pfnTim2Cb; + } + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer PWC 输入é…ç½®(模å¼1) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M1_Input_Config(en_bt_unit_t enUnit, stc_bt_pwc_input_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE1_TypeDef *pstcM0PBt = (M0P_TIM0_MODE1_TypeDef *)((uint32_t)M0P_TIM0_MODE1+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->MSCR_f.TS = pstcConfig->enTsSel; + pstcM0PBt->MSCR_f.IA0S = pstcConfig->enIA0Sel; + pstcM0PBt->MSCR_f.IB0S = pstcConfig->enIB0Sel; + pstcM0PBt->FLTR_f.ETP = pstcConfig->enETRPhase; + pstcM0PBt->FLTR_f.FLTET = pstcConfig->enFltETR; + pstcM0PBt->FLTR_f.FLTA0 = pstcConfig->enFltIA0; + pstcM0PBt->FLTR_f.FLTB0 = pstcConfig->enFltIB0; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer PWC测é‡è¾¹æ²¿èµ·å§‹ç»“æŸé€‰æ‹©(模å¼1) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] enEdgeSel pwc测é‡èµ·å§‹ç»ˆæ­¢ç”µå¹³ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M1_PWC_Edge_Sel(en_bt_unit_t enUnit,en_bt_m1cr_Edge_t enEdgeSel) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE1_TypeDef *pstcM0PBt = (M0P_TIM0_MODE1_TypeDef *)((uint32_t)M0P_TIM0_MODE1+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + switch (enEdgeSel) + { + case 0: ///< 上å‡æ²¿åˆ°ä¸Šå‡æ²¿(周期) + pstcM0PBt->M1CR_f.EDG1ST = 0; //上å‡æ²¿ + pstcM0PBt->M1CR_f.EDG2ND = 0; //上å‡æ²¿ + break; + case 1: ///< 下é™æ²¿åˆ°ä¸Šå‡æ²¿(低电平) + pstcM0PBt->M1CR_f.EDG1ST = 1; //下é™æ²¿ + pstcM0PBt->M1CR_f.EDG2ND = 0; //上å‡æ²¿ + break; + case 2: ///< 上å‡æ²¿åˆ°ä¸‹é™æ²¿(高电平) + pstcM0PBt->M1CR_f.EDG1ST = 0; //上å‡æ²¿ + pstcM0PBt->M1CR_f.EDG2ND = 1; //下é™æ²¿ + break; + case 3: ///< 下é™æ²¿åˆ°ä¸‹é™æ²¿(周期) + pstcM0PBt->M1CR_f.EDG1ST = 1; //下é™æ²¿ + pstcM0PBt->M1CR_f.EDG2ND = 1; //下é™æ²¿ + break; + default: + ; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer å¯åŠ¨è¿è¡Œ(模å¼1) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M1_Run(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE1_TypeDef *pstcM0PBt = (M0P_TIM0_MODE1_TypeDef *)((uint32_t)M0P_TIM0_MODE1+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M1CR_f.CTEN = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer åœæ­¢è¿è¡Œ(模å¼1) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M1_Stop(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE1_TypeDef *pstcM0PBt = (M0P_TIM0_MODE1_TypeDef *)((uint32_t)M0P_TIM0_MODE1+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M1CR_f.CTEN = FALSE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 16ä½è®¡æ•°å™¨åˆå€¼è®¾ç½®(模å¼1) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] u16Data 16ä½åˆå€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M1_Cnt16Set(en_bt_unit_t enUnit, uint16_t u16Data) +{ + en_result_t enResult = Ok; + + ASSERT(IS_VALID_TIM(enUnit)); + + switch (enUnit) + { + case TIM0: + M0P_TIM0_MODE1->CNT_f.CNT = u16Data; + break; + case TIM1: + M0P_TIM1_MODE1->CNT_f.CNT = u16Data; + break; + case TIM2: + M0P_TIM2_MODE1->CNT_f.CNT = u16Data; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 16ä½è®¡æ•°å€¼èŽ·å–(模å¼1) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** + ** \retval 16bits计数值 + *****************************************************************************/ +uint16_t Bt_M1_Cnt16Get(en_bt_unit_t enUnit) +{ + uint16_t u16CntData = 0; + + ASSERT(IS_VALID_TIM(enUnit)); + + switch (enUnit) + { + case TIM0: + u16CntData = M0P_TIM0_MODE1->CNT_f.CNT; + break; + case TIM1: + u16CntData = M0P_TIM1_MODE1->CNT_f.CNT; + break; + case TIM2: + u16CntData = M0P_TIM2_MODE1->CNT_f.CNT; + break; + default: + u16CntData = 0; + break; + } + + return u16CntData; +} + +/** + ***************************************************************************** + ** \brief Base Timer 脉冲宽度测é‡ç»“果数值获å–(模å¼1) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** + ** \retval 16bits脉冲宽度测é‡ç»“æžœ + *****************************************************************************/ +uint16_t Bt_M1_PWC_CapValueGet(en_bt_unit_t enUnit) +{ + uint16_t u16CapData = 0; + + ASSERT(IS_VALID_TIM(enUnit)); + + switch (enUnit) + { + case TIM0: + u16CapData = M0P_TIM0_MODE1->CCR0A_f.CCR0A; + break; + case TIM1: + u16CapData = M0P_TIM1_MODE1->CCR0A_f.CCR0A; + break; + case TIM2: + u16CapData = M0P_TIM2_MODE1->CCR0A_f.CCR0A; + break; + default: + u16CapData = 0; + break; + } + + return u16CapData; +} + +/** + ***************************************************************************** + ** \brief Base Timer åˆå§‹åŒ–é…ç½®(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_Mode23_Init(en_bt_unit_t enUnit, stc_bt_mode23_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + ASSERT(IS_VALID_TIM(enUnit)); + + switch (enUnit) + { + case TIM0: + { + M0P_TIM0_MODE23->M23CR_f.MODE = pstcConfig->enWorkMode; + + M0P_TIM0_MODE23->M23CR_f.PRS = pstcConfig->enPRS; + M0P_TIM0_MODE23->M23CR_f.CT = pstcConfig->enCT; + M0P_TIM0_MODE23->M23CR_f.COMP = pstcConfig->enPWMTypeSel; + M0P_TIM0_MODE23->M23CR_f.PWM2S = pstcConfig->enPWM2sSel; + M0P_TIM0_MODE23->M23CR_f.ONESHOT = pstcConfig->bOneShot; + M0P_TIM0_MODE23->M23CR_f.URS = pstcConfig->bURSSel; + M0P_TIM0_MODE23->M23CR_f.DIR = pstcConfig->enCntDir; + + pfnTim0Callback = pstcConfig->pfnTim0Cb; + } + break; + case TIM1: + { + M0P_TIM1_MODE23->M23CR_f.MODE = pstcConfig->enWorkMode; + + M0P_TIM1_MODE23->M23CR_f.PRS = pstcConfig->enPRS; + M0P_TIM1_MODE23->M23CR_f.CT = pstcConfig->enCT; + M0P_TIM1_MODE23->M23CR_f.COMP = pstcConfig->enPWMTypeSel; + M0P_TIM1_MODE23->M23CR_f.PWM2S = pstcConfig->enPWM2sSel; + M0P_TIM1_MODE23->M23CR_f.ONESHOT = pstcConfig->bOneShot; + M0P_TIM1_MODE23->M23CR_f.URS = pstcConfig->bURSSel; + M0P_TIM1_MODE23->M23CR_f.DIR = pstcConfig->enCntDir; + + pfnTim1Callback = pstcConfig->pfnTim1Cb; + } + break; + case TIM2: + { + M0P_TIM2_MODE23->M23CR_f.MODE = pstcConfig->enWorkMode; + + M0P_TIM2_MODE23->M23CR_f.PRS = pstcConfig->enPRS; + M0P_TIM2_MODE23->M23CR_f.CT = pstcConfig->enCT; + M0P_TIM2_MODE23->M23CR_f.COMP = pstcConfig->enPWMTypeSel; + M0P_TIM2_MODE23->M23CR_f.PWM2S = pstcConfig->enPWM2sSel; + M0P_TIM2_MODE23->M23CR_f.ONESHOT = pstcConfig->bOneShot; + M0P_TIM2_MODE23->M23CR_f.URS = pstcConfig->bURSSel; + M0P_TIM2_MODE23->M23CR_f.DIR = pstcConfig->enCntDir; + + pfnTim2Callback = pstcConfig->pfnTim2Cb; + } + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer PWM输出使能/ç¦æ­¢(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] bEnOutput PWM输出使能/ç¦æ­¢è®¾å®š + ** \param [in] bEnAutoOutput PWM自动输出使能/ç¦æ­¢è®¾å®š + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_EnPWM_Output(en_bt_unit_t enUnit, boolean_t bEnOutput, boolean_t bEnAutoOutput) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->DTR_f.MOE = bEnOutput; + pstcM0PBt->DTR_f.AOE = bEnAutoOutput; + + return enResult; +} + + +/** + ***************************************************************************** + ** \brief Base Timer å¯åŠ¨è¿è¡Œ(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_Run(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M23CR_f.CTEN = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer åœæ­¢è¿è¡Œ(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_Stop(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M23CR_f.CTEN = FALSE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer é‡è½½å€¼è®¾ç½®(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] u16Data 16bitsé‡è½½å€¼ + ** \param [in] bArrBufEn ARRé‡è½½ç¼“存使能TRUE/ç¦æ­¢FALSE + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_ARRSet(en_bt_unit_t enUnit, uint16_t u16Data, boolean_t bArrBufEn) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->ARR_f.ARR = u16Data; + pstcM0PBt->M23CR_f.BUFPEN = bArrBufEn; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 16ä½è®¡æ•°å™¨åˆå€¼è®¾ç½®(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] u16Data 16ä½åˆå€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_Cnt16Set(en_bt_unit_t enUnit, uint16_t u16Data) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->CNT_f.CNT = u16Data; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 16ä½è®¡æ•°å€¼èŽ·å–(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** + ** \retval 16bits计数值 + *****************************************************************************/ +uint16_t Bt_M23_Cnt16Get(en_bt_unit_t enUnit) +{ + uint16_t u16CntData = 0; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + u16CntData = pstcM0PBt->CNT_f.CNT; + + return u16CntData; +} + +/** + ***************************************************************************** + ** \brief Base Timer 比较æ•èŽ·å¯„存器CCR0A/CCR0B设置(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] enCCRSel CCR0A/CCR0B设定 + ** \param [in] u16Data CCR0A/CCR0B 16ä½åˆå§‹å€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_CCR_Set(en_bt_unit_t enUnit, en_bt_m23_ccrx_t enCCRSel, uint16_t u16Data) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + if(BtCCR0A == enCCRSel) + { + pstcM0PBt->CCR0A_f.CCR0A = u16Data; + } + else if(BtCCR0B == enCCRSel) + { + pstcM0PBt->CCR0B_f.CCR0B = u16Data; + } + else + { + enResult = Error; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 比较æ•èŽ·å¯„存器CCR0A/CCR0B读å–(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] enCCRSel CCR0A/CCR0B设定 + ** + ** \retval 16bitsCCR0Aæ•èŽ·å€¼ + *****************************************************************************/ +uint16_t Bt_M23_CCR_Get(en_bt_unit_t enUnit, en_bt_m23_ccrx_t enCCRSel) +{ + uint16_t u16Data = 0; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + if(BtCCR0A == enCCRSel) + { + u16Data = pstcM0PBt->CCR0A_f.CCR0A; + } + else if(BtCCR0B == enCCRSel) + { + u16Data = pstcM0PBt->CCR0B_f.CCR0B; + } + else + { + u16Data = 0; + } + + return u16Data; +} + +/** + ***************************************************************************** + ** \brief Base Timer PWM互补输出模å¼ä¸‹ï¼ŒGATE功能选择(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_GateFuncSel(en_bt_unit_t enUnit,stc_bt_m23_gate_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M23CR_f.CSG = pstcConfig->enGateFuncSel; + pstcM0PBt->M23CR_f.CRG = pstcConfig->bGateRiseCap; + pstcM0PBt->M23CR_f.CFG = pstcConfig->bGateFallCap; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 主从模å¼é…ç½®(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_MasterSlave_Set(en_bt_unit_t enUnit, stc_bt_m23_master_slave_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->MSCR_f.MSM = pstcConfig->enMasterSlaveSel; + pstcM0PBt->MSCR_f.MMS = pstcConfig->enMasterSrc; + pstcM0PBt->MSCR_f.SMS = pstcConfig->enSlaveModeSel; + pstcM0PBt->MSCR_f.TS = pstcConfig->enTsSel; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer CH0A/CH0B比较通é“输出控制(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_PortOutput_Config(en_bt_unit_t enUnit, stc_bt_m23_compare_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->CRCH0_f.CSA = 0; + pstcM0PBt->FLTR_f.OCMA0_FLTA0 = pstcConfig->enCH0ACmpCtrl; + pstcM0PBt->FLTR_f.CCPA0 = pstcConfig->enCH0APolarity; + pstcM0PBt->CRCH0_f.BUFEA = pstcConfig->bCh0ACmpBufEn; + pstcM0PBt->M23CR_f.CIS = pstcConfig->enCh0ACmpIntSel; + + pstcM0PBt->CRCH0_f.CSB = 0; + pstcM0PBt->FLTR_f.OCMB0_FLTB0 = pstcConfig->enCH0BCmpCtrl; + pstcM0PBt->FLTR_f.CCPB0 = pstcConfig->enCH0BPolarity; + pstcM0PBt->CRCH0_f.BUFEB = pstcConfig->bCH0BCmpBufEn; + pstcM0PBt->CRCH0_f.CISB = pstcConfig->enCH0BCmpIntSel; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer CH0A/CH0B输入控制(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_PortInput_Config(en_bt_unit_t enUnit, stc_bt_m23_input_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->CRCH0_f.CSA = 1; + pstcM0PBt->CRCH0_f.CFA_CRA_BKSA = pstcConfig->enCH0ACapSel; + pstcM0PBt->FLTR_f.OCMA0_FLTA0 = pstcConfig->enCH0AInFlt; + pstcM0PBt->FLTR_f.CCPA0 = pstcConfig->enCH0APolarity; + + pstcM0PBt->CRCH0_f.CSB = 1; + pstcM0PBt->CRCH0_f.CFB_CRB_BKSB = pstcConfig->enCH0BCapSel; + pstcM0PBt->FLTR_f.OCMB0_FLTB0 = pstcConfig->enCH0BInFlt; + pstcM0PBt->FLTR_f.CCPB0 = pstcConfig->enCH0BPolarity; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer ERT输入控制(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_ETRInput_Config(en_bt_unit_t enUnit, stc_bt_m23_etr_input_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->FLTR_f.ETP = pstcConfig->enETRPolarity; + pstcM0PBt->FLTR_f.FLTET = pstcConfig->enETRFlt; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 刹车BK输入控制(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_BrakeInput_Config(en_bt_unit_t enUnit, stc_bt_m23_bk_input_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->DTR_f.BKE = pstcConfig->bEnBrake; + pstcM0PBt->DTR_f.VC0E = pstcConfig->bEnVC0Brake; + pstcM0PBt->DTR_f.VC1E = pstcConfig->bEnVC1Brake; + pstcM0PBt->DTR_f.SAFEEN = pstcConfig->bEnSafetyBk; + pstcM0PBt->DTR_f.BKSEL = pstcConfig->bEnBKSync; + pstcM0PBt->CRCH0_f.CFA_CRA_BKSA = pstcConfig->enBkCH0AStat; + pstcM0PBt->CRCH0_f.CFB_CRB_BKSB = pstcConfig->enBkCH0BStat; + pstcM0PBt->FLTR_f.BKP = pstcConfig->enBrakePolarity; + pstcM0PBt->FLTR_f.FLTBK = pstcConfig->enBrakeFlt; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 触å‘ADC控制(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_TrigADC_Config(en_bt_unit_t enUnit, stc_bt_m23_adc_trig_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->ADTR_f.ADTE = pstcConfig->bEnTrigADC; + pstcM0PBt->ADTR_f.UEVE = pstcConfig->bEnUevTrigADC; + pstcM0PBt->ADTR_f.CMA0E = pstcConfig->bEnCH0ACmpTrigADC; + pstcM0PBt->ADTR_f.CMB0E = pstcConfig->bEnCH0BCmpTrigADC; + + return enResult; +} + +/** + ***************************************************************************** +** \brief Base Timer 死区功能(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_DT_Config(en_bt_unit_t enUnit, stc_bt_m23_dt_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->DTR_f.DTEN = pstcConfig->bEnDeadTime; + pstcM0PBt->DTR_f.DTR = pstcConfig->u8DeadTimeValue; + + return enResult; +} + +/** + ***************************************************************************** +** \brief Base Timer é‡å¤å‘¨æœŸè®¾ç½®(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] u8ValidPeriod é‡å¤å‘¨æœŸå€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_SetValidPeriod(en_bt_unit_t enUnit, uint8_t u8ValidPeriod) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->RCR_f.RCR = u8ValidPeriod; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer OCREF清除功能(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_OCRefClr(en_bt_unit_t enUnit, stc_bt_m23_OCREF_Clr_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M23CR_f.OCCS = pstcConfig->enOCRefClrSrcSel; + pstcM0PBt->M23CR_f.OCCE = pstcConfig->bVCClrEn; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 使能DMA传输(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_EnDMA(en_bt_unit_t enUnit, stc_bt_m23_trig_dma_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M23CR_f.UDE = pstcConfig->bUevTrigDMA; + pstcM0PBt->M23CR_f.TDE = pstcConfig->bTITrigDMA; + pstcM0PBt->CRCH0_f.CDEA = pstcConfig->bCmpATrigDMA; + pstcM0PBt->CRCH0_f.CDEB = pstcConfig->bCmpBTrigDMA; + pstcM0PBt->MSCR_f.CCDS = pstcConfig->enCmpUevTrigDMA; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer æ•èŽ·æ¯”较A软件触å‘(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_EnSwTrigCapCmpA(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->CRCH0_f.CCGA = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer æ•èŽ·æ¯”较B软件触å‘(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_EnSwTrigCapCmpB(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->CRCH0_f.CCGB = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 软件更新使能(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_EnSwUev(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M23CR_f.UG = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 软件触å‘使能(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_EnSwTrig(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M23CR_f.TG = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 软件刹车使能(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_EnSwBk(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M23CR_f.BG = TRUE; + + return enResult; +} + +//@} // BtGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/crc.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/crc.c new file mode 100644 index 0000000000..23b6b0bf69 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/crc.c @@ -0,0 +1,438 @@ +/****************************************************************************** +*Copyright(C)2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file crc.c + ** + ** Common API of crc. + ** @link crcGroup Some description @endlink + ** + ** - 2017-05-16 + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "crc.h" +/** + ******************************************************************************* + ** \addtogroup CrcGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ***************************************************************************** + ** \brief CRC16 ç¼–ç (字节填充方å¼) + ** + ** 该函数主è¦ç”¨äºŽç”ŸæˆCRC16ç¼–ç . + ** + ** \param [in] pu8Data å¾…ç¼–ç æ•°æ®æŒ‡é’ˆï¼ˆå­—节方å¼è¾“入） + ** \param [in] u32Len å¾…ç¼–ç æ•°æ®é•¿åº¦ï¼ˆå­—节数） + ** + ** \retval CRC16 CRC16ç¼–ç å€¼. + *****************************************************************************/ +uint16_t CRC16_Get8(uint8_t* pu8Data, uint32_t u32Len) +{ + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 0; + M0P_CRC->RESULT = 0xFFFF; + for(u32Index = 0;u32IndexDATA))) = pu8Data[u32Index]; + } + + return (M0P_CRC->RESULT_f.RESULT); +} + +/** + ***************************************************************************** + ** \brief CRC16 ç¼–ç (åŠå­—å¡«å……æ–¹å¼) + ** + ** 该函数主è¦ç”¨äºŽç”ŸæˆCRC16ç¼–ç . + ** + ** \param [in] pu16Data å¾…ç¼–ç æ•°æ®æŒ‡é’ˆï¼ˆåŠå­—æ–¹å¼è¾“入） + ** \param [in] u32Len å¾…ç¼–ç æ•°æ®é•¿åº¦ï¼ˆåŠå­—数） + ** + ** \retval CRC16 CRC16ç¼–ç å€¼. + *****************************************************************************/ +uint16_t CRC16_Get16(uint16_t* pu16Data, uint32_t u32Len) +{ + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 0; + M0P_CRC->RESULT_f.RESULT = 0xFFFF; + for (u32Index=0; u32IndexDATA))) = pu16Data[u32Index]; + } + + return (M0P_CRC->RESULT_f.RESULT); +} + +/** + ***************************************************************************** + ** \brief CRC16 ç¼–ç (å­—å¡«å……æ–¹å¼) + ** + ** 该函数主è¦ç”¨äºŽç”ŸæˆCRC16ç¼–ç . + ** + ** \param [in] pu32Data å¾…ç¼–ç æ•°æ®æŒ‡é’ˆï¼ˆå­—æ–¹å¼è¾“入） + ** \param [in] u32Len å¾…ç¼–ç æ•°æ®é•¿åº¦ï¼ˆå­—数） + ** + ** \retval CRC16 CRC16ç¼–ç å€¼. + *****************************************************************************/ +uint16_t CRC16_Get32(uint32_t* pu32Data, uint32_t u32Len) +{ + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 0; + M0P_CRC->RESULT_f.RESULT = 0xFFFF; + for (u32Index=0; u32IndexDATA_f.DATA = pu32Data[u32Index]; + } + + return (M0P_CRC->RESULT_f.RESULT); +} + +/** + ***************************************************************************** + ** \brief CRC16 校验(字节填充方å¼) + ** + ** 该函数主è¦ç”¨äºŽå¯¹æ•°æ®åŠCRC16值进行校验. + ** + ** \param [in] pu8Data 待校验数æ®æŒ‡é’ˆï¼ˆå­—节方å¼è¾“入） + ** \param [in] u32Len 待校验数æ®é•¿åº¦ï¼ˆå­—节数） + ** \param [in] u16CRC 待校验CRC16值 + ** + ** \retval Ok CRC校验正确 + ** \retval Error CRC校验错误 + *****************************************************************************/ +en_result_t CRC16_Check8(uint8_t* pu8Data, uint32_t u32Len, uint16_t u16CRC) +{ + en_result_t enResult = Ok; + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 0; + M0P_CRC->RESULT_f.RESULT = 0xFFFF; + for (u32Index=0; u32IndexDATA))) = pu8Data[u32Index]; + } + + *((volatile uint8_t*)(&(M0P_CRC->DATA))) = (uint8_t)((((uint32_t)u16CRC)>>0)&0xFF); + *((volatile uint8_t*)(&(M0P_CRC->DATA))) = (uint8_t)(((uint32_t)u16CRC>>8)&0xFF); + + enResult = M0P_CRC->CR_f.FLAG ? Ok : Error; + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief CRC16 校验(åŠå­—å¡«å……æ–¹å¼) + ** + ** 该函数主è¦ç”¨äºŽå¯¹æ•°æ®åŠCRC16值进行校验. + ** + ** \param [in] pu16Data 待校验数æ®æŒ‡é’ˆï¼ˆåŠå­—æ–¹å¼è¾“入） + ** \param [in] u32Len 待校验数æ®é•¿åº¦ï¼ˆåŠå­—数） + ** \param [in] u16CRC 待校验CRC16值 + ** + ** \retval Ok CRC校验正确 + ** \retval Error CRC校验错误 + *****************************************************************************/ +en_result_t CRC16_Check16(uint16_t* pu16Data, uint32_t u32Len, uint16_t u16CRC) +{ + en_result_t enResult = Ok; + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 0; + M0P_CRC->RESULT_f.RESULT = 0xFFFF; + for (u32Index=0; u32IndexDATA))) = pu16Data[u32Index]; + } + + *((volatile uint16_t*)(&(M0P_CRC->DATA))) = u16CRC; + + enResult = M0P_CRC->CR_f.FLAG ? Ok : Error; + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief CRC16 校验(å­—å¡«å……æ–¹å¼) + ** + ** 该函数主è¦ç”¨äºŽå¯¹æ•°æ®åŠCRC16值进行校验. + ** + ** \param [in] pu32Data 待校验数æ®æŒ‡é’ˆï¼ˆå­—æ–¹å¼è¾“入） + ** \param [in] u32Len 待校验数æ®é•¿åº¦ï¼ˆå­—数） + ** \param [in] u16CRC 待校验CRC16值 + ** + ** \retval Ok CRC校验正确 + ** \retval Error CRC校验错误 + *****************************************************************************/ +en_result_t CRC16_Check32(uint32_t* pu32Data, uint32_t u32Len, uint16_t u16CRC) +{ + en_result_t enResult = Ok; + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 0; + M0P_CRC->RESULT_f.RESULT = 0xFFFFFFFFu; + for (u32Index=0; u32IndexDATA))) = pu32Data[u32Index]; + } + + *((volatile uint16_t*)(&(M0P_CRC->DATA))) = ((uint16_t)u16CRC); + + enResult = M0P_CRC->CR_f.FLAG ? Ok : Error; + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief CRC16 ç¼–ç (字节填充方å¼) + ** + ** 该函数主è¦ç”¨äºŽç”ŸæˆCRC16ç¼–ç . + ** + ** \param [in] pu8Data å¾…ç¼–ç æ•°æ®æŒ‡é’ˆï¼ˆå­—节方å¼è¾“入） + ** \param [in] u32Len å¾…ç¼–ç æ•°æ®é•¿åº¦ï¼ˆå­—节数） + ** + ** \retval CRC16 CRC16ç¼–ç å€¼. + *****************************************************************************/ +uint32_t CRC32_Get8(uint8_t* pu8Data, uint32_t u32Len) +{ + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 1; + M0P_CRC->RESULT = 0xFFFFFFFFu; + for(u32Index = 0;u32IndexDATA))) = pu8Data[u32Index]; + } + + return (M0P_CRC->RESULT_f.RESULT); +} + +/** + ***************************************************************************** + ** \brief CRC16 ç¼–ç (åŠå­—å¡«å……æ–¹å¼) + ** + ** 该函数主è¦ç”¨äºŽç”ŸæˆCRC16ç¼–ç . + ** + ** \param [in] pu16Data å¾…ç¼–ç æ•°æ®æŒ‡é’ˆï¼ˆåŠå­—æ–¹å¼è¾“入） + ** \param [in] u32Len å¾…ç¼–ç æ•°æ®é•¿åº¦ï¼ˆåŠå­—数） + ** + ** \retval CRC16 CRC16ç¼–ç å€¼. + *****************************************************************************/ +uint32_t CRC32_Get16(uint16_t* pu16Data, uint32_t u32Len) +{ + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 1; + M0P_CRC->RESULT_f.RESULT = 0xFFFFFFFFu; + for (u32Index=0; u32IndexDATA))) = pu16Data[u32Index]; + } + + return (M0P_CRC->RESULT_f.RESULT); +} + +/** + ***************************************************************************** + ** \brief CRC16 ç¼–ç (å­—å¡«å……æ–¹å¼) + ** + ** 该函数主è¦ç”¨äºŽç”ŸæˆCRC16ç¼–ç . + ** + ** \param [in] pu32Data å¾…ç¼–ç æ•°æ®æŒ‡é’ˆï¼ˆå­—æ–¹å¼è¾“入） + ** \param [in] u32Len å¾…ç¼–ç æ•°æ®é•¿åº¦ï¼ˆå­—数） + ** + ** \retval CRC16 CRC16ç¼–ç å€¼. + *****************************************************************************/ +uint32_t CRC32_Get32(uint32_t* pu32Data, uint32_t u32Len) +{ + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 1; + M0P_CRC->RESULT_f.RESULT = 0xFFFFFFFFu; + for (u32Index=0; u32IndexDATA_f.DATA = pu32Data[u32Index]; + } + + return (M0P_CRC->RESULT_f.RESULT); +} + +/** + ***************************************************************************** + ** \brief CRC16 校验(字节填充方å¼) + ** + ** 该函数主è¦ç”¨äºŽå¯¹æ•°æ®åŠCRC16值进行校验. + ** + ** \param [in] pu8Data 待校验数æ®æŒ‡é’ˆï¼ˆå­—节方å¼è¾“入） + ** \param [in] u32Len 待校验数æ®é•¿åº¦ï¼ˆå­—节数） + ** \param [in] u16CRC 待校验CRC16值 + ** + ** \retval Ok CRC校验正确 + ** \retval Error CRC校验错误 + *****************************************************************************/ +en_result_t CRC32_Check8(uint8_t* pu8Data, uint32_t u32Len, uint32_t u32CRC) +{ + en_result_t enResult = Ok; + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 1; + M0P_CRC->RESULT_f.RESULT = 0xFFFFFFFFu; + for (u32Index=0; u32IndexDATA))) = pu8Data[u32Index]; + } + + *((volatile uint8_t*)(&(M0P_CRC->DATA))) = (uint8_t)((u32CRC>>0)&0xFF); + *((volatile uint8_t*)(&(M0P_CRC->DATA))) = (uint8_t)((u32CRC>>8)&0xFF); + *((volatile uint8_t*)(&(M0P_CRC->DATA))) = (uint8_t)((u32CRC>>16)&0xFF); + *((volatile uint8_t*)(&(M0P_CRC->DATA))) = (uint8_t)((u32CRC>>24)&0xFF); + + enResult = M0P_CRC->CR_f.FLAG ? Ok : Error; + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief CRC16 校验(åŠå­—å¡«å……æ–¹å¼) + ** + ** 该函数主è¦ç”¨äºŽå¯¹æ•°æ®åŠCRC16值进行校验. + ** + ** \param [in] pu16Data 待校验数æ®æŒ‡é’ˆï¼ˆåŠå­—æ–¹å¼è¾“入） + ** \param [in] u32Len 待校验数æ®é•¿åº¦ï¼ˆåŠå­—数） + ** \param [in] u16CRC 待校验CRC16值 + ** + ** \retval Ok CRC校验正确 + ** \retval Error CRC校验错误 + *****************************************************************************/ +en_result_t CRC32_Check16(uint16_t* pu16Data, uint32_t u32Len, uint32_t u32CRC) +{ + en_result_t enResult = Ok; + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 1; + M0P_CRC->RESULT_f.RESULT = 0xFFFFFFFFu; + for (u32Index=0; u32IndexDATA))) = pu16Data[u32Index]; + } + + *((volatile uint16_t*)(&(M0P_CRC->DATA))) = (uint16_t)((u32CRC>>0)&0xFFFF); + *((volatile uint16_t*)(&(M0P_CRC->DATA))) = (uint16_t)((u32CRC>>16)&0xFFFF); + + + enResult = M0P_CRC->CR_f.FLAG ? Ok : Error; + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief CRC16 校验(å­—å¡«å……æ–¹å¼) + ** + ** 该函数主è¦ç”¨äºŽå¯¹æ•°æ®åŠCRC16值进行校验. + ** + ** \param [in] pu32Data 待校验数æ®æŒ‡é’ˆï¼ˆå­—æ–¹å¼è¾“入） + ** \param [in] u32Len 待校验数æ®é•¿åº¦ï¼ˆå­—数） + ** \param [in] u16CRC 待校验CRC16值 + ** + ** \retval Ok CRC校验正确 + ** \retval Error CRC校验错误 + *****************************************************************************/ +en_result_t CRC32_Check32(uint32_t* pu32Data, uint32_t u32Len, uint32_t u32CRC) +{ + en_result_t enResult = Ok; + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 1; + M0P_CRC->RESULT_f.RESULT = 0xFFFFFFFFu; + for (u32Index=0; u32IndexDATA))) = pu32Data[u32Index]; + } + + *((volatile uint32_t*)(&(M0P_CRC->DATA))) = u32CRC; + + enResult = M0P_CRC->CR_f.FLAG ? Ok : Error; + + return (enResult); +} +//@} // CrcGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/ddl.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/ddl.c new file mode 100644 index 0000000000..dbca2ea4b1 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/ddl.c @@ -0,0 +1,345 @@ +/******************************************************************************* +* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file ddl.c + ** + ** Common API of DDL. + ** @link ddlGroup Some description @endlink + ** + ** - 2018-04-15 + ** + ******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "ddl.h" + +/** + ****************************************************************************** + ** \addtogroup DDL Common Functions + ******************************************************************************/ +//@{ + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/******************************************************************************/ +#ifndef __DEBUG +#define __DEBUG +//#define __CC_ARM +#endif + + + + + + +uint32_t Log2(uint32_t u32Val) +{ + uint32_t u32V1 = 0; + + if(0u == u32Val) + { + return 0; + } + + while(u32Val > 1u) + { + u32V1++; + u32Val /=2; + } + + return u32V1; +} + + +/** + ******************************************************************************* + ** \brief Memory clear function for DDL_ZERO_STRUCT() + ******************************************************************************/ +void ddl_memclr(void *pu8Address, uint32_t u32Count) +{ + uint8_t *pu8Addr = (uint8_t *)pu8Address; + + if(NULL == pu8Addr) + { + return; + } + + while (u32Count--) + { + *pu8Addr++ = 0; + } +} + +/** + ***************************************************************************** + ** \brief Hook function, which is called in polling loops + *****************************************************************************/ +void DDL_WAIT_LOOP_HOOK(void) +{ + // Place code for triggering Watchdog counters here, if needed +} + +/** + ***************************************************************************** + ** \brief debug printf function. + *****************************************************************************/ +void Debug_UartInit(void) +{ +#ifdef __DEBUG + //uint32_t u32Pclk1 = 0; + //volatile uint32_t u32ReloadVal = 0; + // + //// UART0_TXD/P35, 19200bps + //M0P_GPIO->P3ADS_f.P35 = 0; + //M0P_GPIO->P35_SEL_f.SEL = 3; + //M0P_GPIO->P3DIR_f.P35 = 0; + // + //u32Pclk1 = Sysctrl_GetPClkFreq(); + //u32ReloadVal = 65536 - u32Pclk1 * 2 / 19200 / 32; + // + //M0P_BT0->CR_f.CT = 0; + //M0P_BT0->CR_f.MD = 1; + //M0P_BT0->CR_f.TOG_EN = 1; + //M0P_BT0->ARR = u32ReloadVal; + //M0P_BT0->CNT = u32ReloadVal; + //M0P_BT0->CR_f.TR = 1; + // + //M0P_UART0->SCON_f.DBAUD = 1; + //M0P_UART0->SCON_f.SM01 = 1; +#endif +} + +void Debug_Output(uint8_t u8Data) +{ + //M0P_UART0->SCON_f.REN = 0; + //M0P_UART0->SBUF = u8Data; + // + //while (TRUE != M0P_UART0->ISR_f.TI) + //{ + // ; + //} + //M0P_UART0->ICR_f.TICLR = 0; +} + +//#ifdef __DEBUG +///** +// ****************************************************************************** +// ** \brief Re-target putchar function +// ******************************************************************************/ +//int fputc(int ch, FILE *f) +//{ + +// if (((uint8_t)ch) == '\n') +// { +// Debug_Output('\r'); +// } +// Debug_Output(ch); + +// return ch; +//} +//#endif + + + +extern void Debug_UartInit(void); +extern void Debug_Output(uint8_t u8Data); + +#if defined (__CC_ARM) //KEIL +#pragma import(__use_no_semihosting) +void _sys_exit(int x) +{ + x = x; +} +struct __FILE +{ + int handle; + /* Whatever you require here. If the only file you are using is */ + /* standard output using printf() for debugging, no file handling */ +/* is required. */ +}; +/* FILE is typedef?d in stdio.h. */ +FILE __stdout; + +#endif + +#ifdef __DEBUG +/** + ****************************************************************************** + ** \brief Re-target putchar function + ******************************************************************************/ +int fputc(int ch, FILE *f) +{ + + if (((uint8_t)ch) == '\n') + { + Debug_Output('\r'); + } + Debug_Output(ch); + + return ch; +} +#endif + +void _ttywrch(int c) +{ +} + + +int __backspace(void) +{ + return 0; +} + + + +/** + * \brief delay1ms + * delay approximately 1ms. + * \param [in] u32Cnt + * \retval void + */ +void delay1ms(uint32_t u32Cnt) +{ + uint32_t u32end; + + SysTick->LOAD = 0xFFFFFF; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_CLKSOURCE_Msk; + + while(u32Cnt-- > 0) + { + SysTick->VAL = 0; + u32end = 0x1000000 - SystemCoreClock/1000; + while(SysTick->VAL > u32end) + { + ; + } + } + + SysTick->CTRL = (SysTick->CTRL & (~SysTick_CTRL_ENABLE_Msk)); +} + +/** + * \brief delay100us + * delay approximately 100us. + * \param [in] u32Cnt + * \retval void + */ +void delay100us(uint32_t u32Cnt) +{ + uint32_t u32end; + + SysTick->LOAD = 0xFFFFFF; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_CLKSOURCE_Msk; + + while(u32Cnt-- > 0) + { + SysTick->VAL = 0; + + u32end = 0x1000000 - SystemCoreClock/10000; + while(SysTick->VAL > u32end) + { + ; + } + } + + SysTick->CTRL = (SysTick->CTRL & (~SysTick_CTRL_ENABLE_Msk)); +} + +/** + * \brief delay10us + * delay approximately 10us. + * \param [in] u32Cnt + * \retval void + */ +void delay10us(uint32_t u32Cnt) +{ + uint32_t u32end; + + SysTick->LOAD = 0xFFFFFF; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_CLKSOURCE_Msk; + + while(u32Cnt-- > 0) + { + SysTick->VAL = 0; + + u32end = 0x1000000 - SystemCoreClock/100000; + while(SysTick->VAL > u32end) + { + ; + } + } + + SysTick->CTRL = (SysTick->CTRL & (~SysTick_CTRL_ENABLE_Msk)); +} + + +//@} // DDL Functions + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/debug.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/debug.c new file mode 100644 index 0000000000..3084bf3b83 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/debug.c @@ -0,0 +1,119 @@ +/****************************************************************************** +*Copyright(C)2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file debug.c + ** + ** Common API of debug. + ** @link flashGroup Some description @endlink + ** + ** - 2018-05-08 + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "debug.h" +/** + ******************************************************************************* + ** \addtogroup FlashGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ***************************************************************************** + ** \brief 调试模å¼ä¸‹æ¨¡å—功能使能 + ** + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +en_result_t Debug_ActiveEnable(en_debug_module_active_t enModule) +{ + M0P_DEBUG_ACTIVE->DEBUG_ACTIVE &= ~enModule; + + return Ok; +} + +/** + ***************************************************************************** + ** \brief 调试模å¼ä¸‹æ¨¡å—åŠŸèƒ½æš‚åœ + ** + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +en_result_t Debug_ActiveDisable(en_debug_module_active_t enModule) +{ + M0P_DEBUG_ACTIVE->DEBUG_ACTIVE |= enModule; + + return Ok; +} + + +//@} // BgrGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/dmac.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/dmac.c new file mode 100644 index 0000000000..8c95fea752 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/dmac.c @@ -0,0 +1,1538 @@ +/****************************************************************************** +* Copyright (C) 2016, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file dmac.c +** +** A detailed description is available at +** @link DmacGroup Dmac description @endlink +** +** - 2018-03-09 1.0 Hongjh First version for Device Driver Library of Dmac. +** +******************************************************************************/ + +/******************************************************************************* +* Include files +******************************************************************************/ +#include "dmac.h" + +/** +******************************************************************************* +** \addtogroup DmacGroup +******************************************************************************/ +//@{ + +/******************************************************************************* +* Local type definitions ('typedef') +******************************************************************************/ + +/******************************************************************************* +* Local pre-processor symbols/macros ('#define') +******************************************************************************/ + +/******************************************************************************/ +/* DMA */ +/******************************************************************************/ +/***************** Bits definition for DMA_INTSTAT0 register ****************/ +#define DMA_INTSTAT0_TRNERR_Pos (0U) /*!< DMA_INTSTAT0: TRNERR Position */ +#define DMA_INTSTAT0_REQERR_Pos (16U) /*!< DMA_INTSTAT0: REQERR Position */ + +/***************** Bits definition for DMA_INTSTAT1 register ****************/ +#define DMA_INTSTAT1_TC_Pos (0U) /*!< DMA_INTSTAT1: TC Position */ +#define DMA_INTSTAT1_BTC_Pos (16U) /*!< DMA_INTSTAT1: BTC Position */ + +/***************** Bits definition for DMA_INTMASK0 register ****************/ +#define DMA_INTMASK0_MSKTRNERR_Pos (0U) /*!< DMA_INTMASK0: MSKTRNERR Position */ +#define DMA_INTMASK0_MSKREQERR_Pos (16U) /*!< DMA_INTMASK0: MSKREQERR Position */ + +/***************** Bits definition for DMA_INTMASK1 register ****************/ +#define DMA_INTMASK1_MSKTC_Pos (0U) /*!< DMA_INTMASK1: MSKTC Position */ +#define DMA_INTMASK1_MSKBTC_Pos (16U) /*!< DMA_INTMASK1: MSKBTC Position */ + +/***************** Bits definition for DMA_INTCLR0 register *****************/ +#define DMA_INTCLR0_CLRTRNERR_Pos (0U) /*!< DMA_INTCLR0: CLRTRNERR Position */ +#define DMA_INTCLR0_CLRREQERR_Pos (16U) /*!< DMA_INTCLR0: CLRREQERR Position */ + +/***************** Bits definition for DMA_INTCLR1 register *****************/ +#define DMA_INTCLR1_CLRTC_Pos (0U) /*!< DMA_INTCLR1: CLRTC Position */ +#define DMA_INTCLR1_CLRBTC_Pos (16U) /*!< DMA_INTCLR1: CLRBTC Position */ + +/******************* Bits definition for DMA_CHEN register ******************/ +#define DMA_CHEN_CHEN_Pos (0U) /*!< DMA_CHEN: CHEN Position */ + +/************** Bits definition for DMA_TRGSELx(x=0~7) register *************/ +#define DMA_TRGSEL_TRGSEL_Pos (0U) /*!< DMA_TRGSELx: TRGSEL Position */ +#define DMA_TRGSEL_TRGSEL_Msk (0x1FFU << DMA_TRGSEL_TRGSEL_Pos) /*!< DMA_TRGSELx: TRGSEL Mask 0x000001FF */ +#define DMA_TRGSEL_TRGSEL DMA_TRGSEL_TRGSEL_Msk +/************** Bits definition for DMA_DTCTLx(x=0~7) register **************/ +#define DMA_DTCTL_BLKSIZE_Pos (0U) /*!< DMA_DTCTLx: BLKSIZE Position */ +#define DMA_DTCTL_BLKSIZE_Msk (0x3FFU << DMA_DTCTL_BLKSIZE_Pos) /*!< DMA_DTCTLx: BLKSIZE Mask 0x000003FF */ +#define DMA_DTCTL_BLKSIZE DMA_DTCTL_BLKSIZE_Msk + +#define DMA_DTCTL_CNT_Pos (16U) /*!< DMA_DTCTLx: CNT Position */ +#define DMA_DTCTL_CNT_Msk (0xFFFFU << DMA_DTCTL_CNT_Pos) /*!< DMA_DTCTLx: CNT Mask 0xFFFF0000 */ +#define DMA_DTCTL_CNT DMA_DTCTL_CNT_Msk + +/*************** Bits definition for DMA_RPTx(x=0~7) register ***************/ +#define DMA_RPT_SRPT_Pos (0U) /*!< DMA_RPTx: SRPT Position */ +#define DMA_RPT_SRPT_Msk (0x1FFU << DMA_RPT_SRPT_Pos) /*!< DMA_RPTx: SRPT Mask 0x000001FF */ +#define DMA_RPT_SRPT DMA_RPT_SRPT_Msk + +#define DMA_RPT_DRPT_Pos (16U) /*!< DMA_RPTx: DRPT Position */ +#define DMA_RPT_DRPT_Msk (0x1FFU << DMA_RPT_DRPT_Pos) /*!< DMA_RPTx: DRPT Mask 0x01FF0000 */ +#define DMA_RPT_DRPT DMA_RPT_DRPT_Msk + +/************* Bits definition for DMA_SNSEQCTLx(x=0~7) register ************/ +#define DMA_SNSEQCTL_SOFFSET_Pos (0U) /*!< DMA_SNSEQCTLx: SOFFSET Position */ +#define DMA_SNSEQCTL_SOFFSET_Msk (0xFFFFFU << DMA_SNSEQCTL_SOFFSET_Pos) /*!< DMA_SNSEQCTLx: SOFFSET Mask 0x000FFFFF */ +#define DMA_SNSEQCTL_SOFFSET DMA_SNSEQCTL_SOFFSET_Msk + +#define DMA_SNSEQCTL_SNSCNT_Pos (20U) /*!< DMA_SNSEQCTLx: SNSCNT Position */ +#define DMA_SNSEQCTL_SNSCNT_Msk (0xFFFU << DMA_SNSEQCTL_SNSCNT_Pos) /*!< DMA_SNSEQCTLx: SNSCNT Mask 0xFFF00000 */ +#define DMA_SNSEQCTL_SNSCNT DMA_SNSEQCTL_SNSCNT_Msk + +/************* Bits definition for DMA_DNSEQCTLx(x=0~7) register ************/ +#define DMA_DNSEQCTL_DOFFSET_Pos (0U) /*!< DMA_DNSEQCTLx: DOFFSET Position */ +#define DMA_DNSEQCTL_DOFFSET_Msk (0xFFFFFU << DMA_DNSEQCTL_DOFFSET_Pos) /*!< DMA_DNSEQCTLx: DOFFSET Mask 0x000FFFFF */ +#define DMA_DNSEQCTL_DOFFSET DMA_DNSEQCTL_DOFFSET_Msk + +#define DMA_DNSEQCTL_DNSCNT_Pos (20U) /*!< DMA_DNSEQCTLx: DNSCNT Position */ +#define DMA_DNSEQCTL_DNSCNT_Msk (0xFFFU << DMA_DNSEQCTL_DNSCNT_Pos) /*!< DMA_DNSEQCTLx: DNSCNT Mask 0xFFF00000 */ +#define DMA_DNSEQCTL_DNSCNT DMA_DNSEQCTL_DNSCNT_Msk + +/*************** Bits definition for DMA_CHxCTL(x=0~7) register *************/ +#define DMA_CHCTL_SINC_Pos (0U) /*!< DMA_CHxCTL: SINC Position */ +#define DMA_CHCTL_SINC_Msk (0x3u << DMA_CHCTL_SINC_Pos) /*!< DMA_CHxCTL: SINC Mask 0x00000003 */ +#define DMA_CHCTL_SINC DMA_CHCTL_SINC_Msk + +#define DMA_CHCTL_DINC_Pos (2U) /*!< DMA_CHxCTL: DINC Position */ +#define DMA_CHCTL_DINC_Msk (0x3U << DMA_CHCTL_DINC_Pos) /*!< DMA_CHxCTL: DINC Mask 0x0000000C */ +#define DMA_CHCTL_DINC DMA_CHCTL_DINC_Msk + +#define DMA_CHCTL_SRPTEN_Pos (4U) /*!< DMA_CHxCTL: SRPTEN Position */ +#define DMA_CHCTL_DRPTEN_Pos (5U) /*!< DMA_CHxCTL: DRPTEN Position */ +#define DMA_CHCTL_SNSEQEN_Pos (6U) /*!< DMA_CHxCTL: SNSEQEN Position */ +#define DMA_CHCTL_DNSEQEN_Pos (7U) /*!< DMA_CHxCTL: DNSEQEN Position */ + +#define DMA_CHCTL_HSIZE_Pos (8U) /*!< DMA_CHxCTL: HSIZE Position */ +#define DMA_CHCTL_HSIZE_Msk (0x3U << DMA_CHCTL_HSIZE_Pos) /*!< DMA_CHxCTL: HSIZE Mask 0x00000300 */ +#define DMA_CHCTL_HSIZE DMA_CHCTL_HSIZE_Msk + +#define DMA_CHCTL_LLPEN_Pos (10U) /*!< DMA_CHxCTL: LLPEN Position */ +#define DMA_CHCTL_LLPRUN_Pos (11U) /*!< DMA_CHxCTL: LLPRUN Position */ +#define DMA_CHCTL_IE_Pos (12U) /*!< DMA_CHxCTL: IE Position */ +#define DMA_CHCTL_PROT_Pos (13U) /*!< DMA_CHxCTL: PROT Position */ + +/************************ DMA_TRGSELx(x=0~7) register ***********************/ +#define DMA_TRGSEL_BASE (0x40010854U) +#define DMA_TRGSEL(x) (*(volatile uint32_t *)((x) * 0x4U + DMA_TRGSEL_BASE)) + +#define INTC_INTSFTTRG_BASE (0x40010800U) +#define INTC_INTSFTTRG (*(volatile uint32_t *)INTC_INTSFTTRG_BASE) + +/*********************** DMA REGISTERx(x=0~7) register **********************/ +#define _DMA_CH_REG_OFFSET(ch) ((ch) * 0x40U) +#define _DMA_CH_REG(reg_base, ch) (*(volatile uint32_t *)((reg_base) + _DMA_CH_REG_OFFSET(ch))) + +#define WRITE_DMA_CH_REG(reg_base, ch, val) (_DMA_CH_REG((reg_base), (ch)) = (val)) +#define READ_DMA_CH_REG(reg_base, ch) (_DMA_CH_REG((reg_base), (ch))) + +#define SET_DMA_CH_REG_BIT(reg_base, ch, pos) (_DMA_CH_REG((reg_base), (ch)) |= (1U << (pos))) +#define CLR_DMA_CH_REG_BIT(reg_base, ch, pos) (_DMA_CH_REG((reg_base), (ch)) &= (~(1U << (pos)))) + + +/********************** SET DMA_TRGSELx(x=0~7) register *********************/ + +#define SET_DMA_CHCTL_PROT(CH, PROT) SET_DMA_CHCTL_PROT((CH), (PROT)) + +/************************** SET INTSFTTRG register **************************/ +#define SOFTWARE_TRIGGER_DMA() (INTC_INTSFTTRG = 1U) + +/*! Parameter valid check for Dmac Channel. */ +#define IS_VALID_CH(x) \ +( (DmaCh0 == (x)) || \ + (DmaCh1 == (x))) + +/*! Parameter valid check for Dmac transfer data width. */ +#define IS_VALID_TRN_WIDTH(x) \ +( (Dma8Bit == (x)) || \ + (Dma16Bit == (x)) || \ + (Dma32Bit == (x))) + +/*! Parameter valid check for Dmac address mode. */ +#define IS_VALID_ADDR_MODE(x) \ +( (AddressFix == (x)) || \ + (AddressIncrease == (x))) + +#define IS_VALID_PRIO_MODE(x) \ +( (DmaPriorityFix == (x)) || \ + (DmaPriorityLoop == (x))) + +/*! Parameter valid check for Dmac transfer block size. */ +#define IS_VALID_BLKSIZE(x) (!((x) & ~(DMA_DTCTL_BLKSIZE_Msk >> DMA_DTCTL_BLKSIZE_Pos))) + +/*! Parameter valid check for Dmac transfer count. */ +#define IS_VALID_TRNCNT(x) (!((x) & ~(DMA_DTCTL_CNT_Msk >> DMA_DTCTL_CNT_Pos))) + +/*! Parameter valid check for Dmac destination repeat size. */ +#define IS_VALID_DRPT_SIZE(x) (!((x) & ~(DMA_RPT_DRPT_Msk >> DMA_RPT_DRPT_Pos))) + +/*! Parameter valid check for Dmac source no-sequence count. */ +#define IS_VALID_SNSCNT(x) (!((x) & ~(DMA_SNSEQCTL_SNSCNT_Msk >> DMA_SNSEQCTL_SNSCNT_Pos))) + +/*! Parameter valid check for Dmac source no-sequence offset. */ +#define IS_VALID_SNSOFFSET(x) (!((x) & ~(DMA_SNSEQCTL_SOFFSET_Msk >> DMA_SNSEQCTL_SOFFSET_Pos))) + +/*! Parameter valid check for Dmac destination no-sequence count. */ +#define IS_VALID_DNSCNT(x) (!((x) & ~(DMA_DNSEQCTL_DNSCNT_Msk >> DMA_DNSEQCTL_DNSCNT_Pos))) + +/*! Parameter valid check for Dmac destination no-sequence offset. */ +#define IS_VALID_DNSOFFSET(x) (!((x) & ~(DMA_DNSEQCTL_DOFFSET_Msk >> DMA_DNSEQCTL_DOFFSET_Pos))) + +/******************************************************************************* +* Global variable definitions (declared in header file with 'extern') +******************************************************************************/ + +/******************************************************************************* +* Local function prototypes ('static') +******************************************************************************/ + +/******************************************************************************* +* Local variable definitions ('static') +******************************************************************************/ +static stc_dma_irq_calbakfn_pt_t stcDmaIrqCalbaks = {NULL, NULL,NULL, NULL}; +/******************************************************************************* +* Function implementation - global ('extern') and local ('static') +******************************************************************************/ + +/** +******************************************************************************* +** \brief Initializes a DMA channel. +** +** \param [in] enCh The specified dma channel. +** \param [in] pstcConfig The structure pointer of DMA module configuration. +** +** \retval Ok Initializes successfully. +** \retval ErrorInvalidParameter enCh is invalid or the pstcConfig is NULL. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_InitChannel(en_dma_channel_t enCh, stc_dma_config_t* pstcConfig) +{ + ASSERT(IS_VALID_CH(enCh)); + ASSERT(NULL != pstcConfig); + ASSERT(IS_VALID_BLKSIZE(pstcConfig->u16BlockSize)); + ASSERT(IS_VALID_TRNCNT(pstcConfig->u16TransferCnt)); + ASSERT(IS_VALID_TRN_WIDTH(pstcConfig->enTransferWidth)); + ASSERT(IS_VALID_ADDR_MODE(pstcConfig->enSrcAddrMode)); + ASSERT(IS_VALID_ADDR_MODE(pstcConfig->enDstAddrMode)); + + /* Check for channel and NULL pointer */ + if ((!IS_VALID_CH(enCh)) || + (NULL == pstcConfig)) + { + return ErrorInvalidParameter; + } + if(enCh == DmaCh0) + { + M0P_DMAC->CONFB0_f.FIS_IE = 0; + M0P_DMAC->CONFB0_f.ERR_IE = 0; /* Disable DMAC interrupt */ + + /******************* SET DMA MODE ******************/ + M0P_DMAC->CONFB0_f.MODE = pstcConfig->enMode; + /******************* SET DMA_TRGSELx register ******************/ + M0P_DMAC->CONFA0_f.TRI_SEL = pstcConfig->enRequestNum; + /******************* SET DMA_DTCTLx(x=0~7) register ******************/ + /* Block size */ + M0P_DMAC->CONFA0_f.BC = pstcConfig->u16BlockSize - 1; + /* Transfer count */ + M0P_DMAC->CONFA0_f.TC = pstcConfig->u16TransferCnt - 1; + + /******************* SET DMA_CHxCTL(x=0~7) register ******************/ + /* Transfer width */ + M0P_DMAC->CONFB0_f.WIDTH = pstcConfig->enTransferWidth; + + /****************************** source address contrl *******************/ + /* source address mode */ + M0P_DMAC->CONFB0_f.FS = pstcConfig->enSrcAddrMode; + /* Source address */ + M0P_DMAC->SRCADR0_f.SRCADR = pstcConfig->u32SrcAddress; + + /*************************** destination address contrl *******************/ + /* destination address mode */ + M0P_DMAC->CONFB0_f.FD = pstcConfig->enDstAddrMode; + /* Destination address */ + M0P_DMAC->DSTADR0_f.DSTADR = pstcConfig->u32DstAddress; + /********************* Source address reload control ********************/ + M0P_DMAC ->CONFB0_f.RS = pstcConfig->bSrcAddrReloadCtl; + + /******************* Destination address reload control *****************/ + M0P_DMAC ->CONFB0_f.RD = pstcConfig->bDestAddrReloadCtl; + + /******************* Destination bc/tc reload control *****************/ + M0P_DMAC ->CONFB0_f.RC = pstcConfig->bSrcBcTcReloadCtl; + + /******************* MSK control *****************/ + M0P_DMAC->CONFB0_f.MSK = pstcConfig->bMsk; + + } + else{ + M0P_DMAC->CONFB1_f.FIS_IE = 0; + M0P_DMAC->CONFB1_f.ERR_IE = 0; /* Disable DMAC interrupt */ + /******************* SET DMA MODE ******************/ + M0P_DMAC->CONFB1_f.MODE = pstcConfig->enMode; + /******************* SET DMA_TRGSELx register ******************/ + M0P_DMAC->CONFA1_f.TRI_SEL = pstcConfig->enRequestNum; + /******************* SET DMA_DTCTLx(x=0~7) register ******************/ + /* Block size */ + M0P_DMAC->CONFA1_f.BC = pstcConfig->u16BlockSize - 1; + /* Transfer count */ + M0P_DMAC->CONFA1_f.TC = pstcConfig->u16TransferCnt - 1; + + /******************* SET DMA_CHxCTL(x=0~7) register ******************/ + /* Transfer width */ + M0P_DMAC->CONFB1_f.WIDTH = pstcConfig->enTransferWidth; + + /****************************** source address contrl *******************/ + /* source address mode */ + M0P_DMAC->CONFB1_f.FS = pstcConfig->enSrcAddrMode; + /* Source address */ + M0P_DMAC->SRCADR1_f.SRCADR = pstcConfig->u32SrcAddress; + + /*************************** destination address contrl *******************/ + /* destination address mode */ + M0P_DMAC->CONFB1_f.FD = pstcConfig->enDstAddrMode; + /* Destination address */ + M0P_DMAC->DSTADR1_f.DSTADR = pstcConfig->u32DstAddress; + + /********************* Source address reload control ********************/ + M0P_DMAC ->CONFB1_f.RS = pstcConfig->bSrcAddrReloadCtl; + + /******************* Destination address reload control *****************/ + M0P_DMAC ->CONFB1_f.RD = pstcConfig->bDestAddrReloadCtl; + + /******************* Destination bc/tc reload control *****************/ + M0P_DMAC ->CONFB1_f.RC = pstcConfig->bSrcBcTcReloadCtl; + + /******************* MSK control *****************/ + M0P_DMAC->CONFB1_f.MSK = pstcConfig->bMsk; + } + return Ok; +} + +/** +******************************************************************************* +** \brief Trigger dma transfer by software. +** +** \param [in] enCh The specified dma channel. +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_SwTrigger(en_dma_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + if(enCh == DmaCh0) + { + M0P_DMAC->CONFA0_f.TRI_SEL = 0x0000; + } + else{ + M0P_DMAC->CONFA1_f.TRI_SEL = 0x0000; + } +} + +/** +******************************************************************************* +** \brief Enable dma function. +** +** \param None +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_Enable(void) +{ + M0P_DMAC->CONF_f.EN = 1; +} + +/** +******************************************************************************* +** \brief Disable dma function. +** +** \param None +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_Disable(void) +{ + M0P_DMAC->CONF_f.EN = 0; +} +/** +******************************************************************************* +** \brief Start dma function. +** +** \param [in] enCh The specified dma channel. +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_Start(en_dma_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + if(enCh == DmaCh0) + { + M0P_DMAC->CONFA0_f.ST = 1; + } + else{ + M0P_DMAC->CONFA1_f.ST = 1; + } +} + +/** +******************************************************************************* +** \brief Disable dma function. +** +** \param [in] enCh The specified dma channel. +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_Stop(en_dma_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + if(enCh == DmaCh0) + { + M0P_DMAC->CONFA0_f.ST = 0; + } + else{ + M0P_DMAC->CONFA1_f.ST = 0; + } +} +/** +******************************************************************************* +** \brief Enable the specified dma interrupt. +** +** \param [in] enCh The specified dma channel. +** \param [in] enIrqSel The specified dma flag. +** \arg TrnErrIrq The DMA transfer error interrupt. +** \arg TrnReqErrIrq DMA transfer req over error interrupt. +** \arg TrnCpltIrq DMA transfer completion interrupt. +** \arg BlkTrnCpltIrq DMA block completion interrupt. +** +** \retval Ok Interrupt enabled normally. +** \retval ErrorInvalidParameter enCh or enIrqSel is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_EnableIrq(en_dma_channel_t enCh, stc_dma_irq_sel_t stcIrqSel) +{ + en_result_t enRet = Ok; + + ASSERT(IS_VALID_CH(enCh)); + + if(!IS_VALID_CH(enCh)) + { + return ErrorInvalidParameter; + } + + if (TRUE == stcIrqSel.TrnCpltIrq) + { + Dma_EnableChannelIrq(enCh); + } + if(TRUE == stcIrqSel.TrnErrIrq) + { + Dma_EnableChannelErrIrq(enCh); + } + + return enRet; +} + +/** +******************************************************************************* +** \brief Enable the specified dma interrupt. +** +** \param [in] enCh The specified dma channel. +** \param [in] enIrqSel The specified dma flag. +** \arg TrnErrIrq The DMA transfer error interrupt. +** \arg TrnReqErrIrq DMA transfer req over error interrupt. +** \arg TrnCpltIrq DMA transfer completion interrupt. +** \arg BlkTrnCpltIrq DMA block completion interrupt. +** +** \retval Ok Interrupt disabled normally. +** \retval ErrorInvalidParameter enCh or enIrqSel is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_DisableIrq(en_dma_channel_t enCh, stc_dma_irq_sel_t stcIrqSel) +{ + en_result_t enRet = Ok; + + ASSERT(IS_VALID_CH(enCh)); + + if(!IS_VALID_CH(enCh)) + { + return ErrorInvalidParameter; + } + + if (TRUE == stcIrqSel.TrnCpltIrq) + { + Dma_DisableChannelIrq(enCh); + } + if(TRUE == stcIrqSel.TrnErrIrq) + { + Dma_DisableChannelErrIrq(enCh); + } + + return enRet; +} + +/** +******************************************************************************* +** \brief Enable the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** +** \retval Ok Enable channel successfully. +** \retval ErrorInvalidParameter enCh is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_EnableChannel(en_dma_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + + if(!IS_VALID_CH(enCh)) + { + return ErrorInvalidParameter; + } + + if(enCh == DmaCh0) + { + M0P_DMAC->CONFA0_f.ENS = 1; + } + else{ + M0P_DMAC->CONFA1_f.ENS = 1; + } + + return Ok; +} + +/** +******************************************************************************* +** \brief Disable the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** +** \retval Ok Disable channel successfully. +** \retval ErrorInvalidParameter enCh is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_DisableChannel(en_dma_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + + if(!IS_VALID_CH(enCh)) + { + return ErrorInvalidParameter; + } + + if(enCh == DmaCh0) + { + M0P_DMAC->CONFA0_f.ENS = 0;; + } + else { + M0P_DMAC->CONFA1_f.ENS = 0;; + } + + return Ok; +} + +/** +******************************************************************************* +** \brief Set the specified dma trigger. +** +** \param [in] enCh The specified dma channel. +** \param [in] u16TrgSel The trigger selection number. +** +** \retval Ok Set successfully. +** \retval ErrorInvalidParameter enCh or u16TrgSel is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_SetTriggerSel(en_dma_channel_t enCh, en_dma_trig_sel_t enTrgSel) +{ + ASSERT(IS_VALID_CH(enCh)); + + if(!IS_VALID_CH(enCh)) + { + return ErrorInvalidParameter; + } + + if(enCh == DmaCh0) + { + M0P_DMAC->CONFA0_f.TRI_SEL = enTrgSel;; + } + else{ + M0P_DMAC->CONFA1_f.TRI_SEL = enTrgSel;; + } + + return Ok; +} + +/** +******************************************************************************* +** \brief Setthe source address of the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** \param [in] u32Address The source address. +** +** \retval Ok Set successfully. +** \retval ErrorInvalidParameter enCh is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_SetSourceAddress(en_dma_channel_t enCh, uint32_t u32Address) +{ + ASSERT(IS_VALID_CH(enCh)); + + if(!IS_VALID_CH(enCh)) + { + return ErrorInvalidParameter; + } + + if(enCh == DmaCh0) + { + M0P_DMAC->SRCADR0_f.SRCADR = u32Address; + } + else + { + M0P_DMAC->SRCADR1_f.SRCADR = u32Address;; + } + + return Ok; +} + +/** +******************************************************************************* +** \brief Set the destination address of the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** \param [in] u32Address The destination address. +** +** \retval Ok Set successfully. +** \retval ErrorInvalidParameter enCh is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_SetDestinationAddress(en_dma_channel_t enCh, uint32_t u32Address) +{ + ASSERT(IS_VALID_CH(enCh)); + + if(!IS_VALID_CH(enCh)) + { + return ErrorInvalidParameter; + } + + if(enCh == DmaCh0) + { + M0P_DMAC->DSTADR0_f.DSTADR = u32Address; + } + else + { + M0P_DMAC->DSTADR1_f.DSTADR = u32Address; + } + + return Ok; +} + +/** +******************************************************************************* +** \brief Set the block size of the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** \param [in] u32Address The block size. +** +** \retval Ok Set successfully. +** \retval ErrorInvalidParameter enCh or u16BlkSize is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_SetBlockSize(en_dma_channel_t enCh, uint16_t u16BlkSize) +{ + ASSERT(IS_VALID_CH(enCh)); + ASSERT(IS_VALID_BLKSIZE(u16BlkSize)); + + if((!IS_VALID_CH(enCh)) || (!IS_VALID_BLKSIZE(u16BlkSize))) + { + return ErrorInvalidParameter; + } + + if(enCh == DmaCh0) + { + M0P_DMAC->CONFA0_f.BC = u16BlkSize - 1; + } + else + { + M0P_DMAC->CONFA1_f.BC = u16BlkSize - 1; + } + return Ok; +} + +/** +******************************************************************************* +** \brief Set the transfer count of the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** \param [in] u32Address The transfer count. +** +** \retval Ok Set successfully. +** \retval ErrorInvalidParameter enCh or u16TrnCnt is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_SetTransferCnt(en_dma_channel_t enCh, uint16_t u16TrnCnt) +{ + ASSERT(IS_VALID_CH(enCh)); + ASSERT(IS_VALID_TRNCNT(u16TrnCnt)); + + if((!IS_VALID_CH(enCh)) || (!IS_VALID_TRNCNT(u16TrnCnt))) + { + return ErrorInvalidParameter; + } + + if(enCh == DmaCh0) + { + M0P_DMAC->CONFA0_f.TC = u16TrnCnt - 1; + } + else + { + M0P_DMAC->CONFA1_f.TC = u16TrnCnt - 1; + } + + return Ok; +} + +/** +******************************************************************************* +** \brief Set the source repeat size of the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** \param [in] u16Size The source repeat size. +** +** \retval Ok Set successfully. +** \retval ErrorInvalidParameter enCh or u16Size is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_EnableSourceRload(en_dma_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + + if((!IS_VALID_CH(enCh))) + { + return ErrorInvalidParameter; + } + if(enCh == DmaCh0) + { + M0P_DMAC ->CONFB0_f.RS = 1; + } + else + { + M0P_DMAC ->CONFB1_f.RS = 1; + } + + return Ok; +} + +/** +******************************************************************************* +** \brief Set the destination repeat size of the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** \param [in] u16Size The destination repeat size. +** +** \retval Ok Set successfully. +** \retval ErrorInvalidParameter enCh or u16Size is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_DisableSourceRload(en_dma_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + + if(!IS_VALID_CH(enCh)) + { + return ErrorInvalidParameter; + } + + if(enCh == DmaCh0) + { + M0P_DMAC ->CONFB0_f.RS = 0; + } + else{ + M0P_DMAC ->CONFB1_f.RS = 0; + } + + return Ok; +} + +/** +******************************************************************************* +** \brief Set the source repeat size of the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** \param [in] u16Size The source repeat size. +** +** \retval Ok Set successfully. +** \retval ErrorInvalidParameter enCh or u16Size is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_EnableDestinationRload(en_dma_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + + if((!IS_VALID_CH(enCh))) + { + return ErrorInvalidParameter; + } + if(enCh == DmaCh0) + { + M0P_DMAC ->CONFB0_f.RD = 1; + } + else { + M0P_DMAC ->CONFB1_f.RD = 1; + } + + return Ok; +} + +/** +******************************************************************************* +** \brief Set the destination repeat size of the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** \param [in] u16Size The destination repeat size. +** +** \retval Ok Set successfully. +** \retval ErrorInvalidParameter enCh or u16Size is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_DisableDestinationRload(en_dma_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + + if(!IS_VALID_CH(enCh)) + { + return ErrorInvalidParameter; + } + + if(enCh == DmaCh0) + { + M0P_DMAC ->CONFB0_f.RD = 0; + } + else{ + M0P_DMAC ->CONFB1_f.RD = 0; + } + + return Ok; +} +/** +******************************************************************************* +** \brief Set the source repeat size of the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** \param [in] u16Size The source repeat size. +** +** \retval Ok Set successfully. +** \retval ErrorInvalidParameter enCh or u16Size is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_EnableBcTcReload(en_dma_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + + if((!IS_VALID_CH(enCh))) + { + return ErrorInvalidParameter; + } + if(enCh == DmaCh0) + { + M0P_DMAC ->CONFB0_f.RC = 1; + } + else{ + M0P_DMAC ->CONFB1_f.RC = 1; + } + + return Ok; +} + +/** +******************************************************************************* +** \brief Set the destination repeat size of the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** \param [in] u16Size The destination repeat size. +** +** \retval Ok Set successfully. +** \retval ErrorInvalidParameter enCh or u16Size is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_DisableBcTcReload(en_dma_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + + if(!IS_VALID_CH(enCh)) + { + return ErrorInvalidParameter; + } + + if(enCh == DmaCh0) + { + M0P_DMAC ->CONFB0_f.RC = 0; + } + else{ + M0P_DMAC ->CONFB1_f.RC = 0; + } + + return Ok; +} +/** +******************************************************************************* +** \brief Set the source address mode of the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** \param [in] enMode The specified dma address mode. +** \arg AddressFix Address fixed. +** \arg AddressIncrease Address increased. +** \arg AddressDecrease Address decreased. +** +** \retval Ok Set successfully +** \retval ErrorInvalidParameter enCh or enMode is invalid +** +** \note None +** +******************************************************************************/ +en_result_t Dma_SetSourceIncMode(en_dma_channel_t enCh, en_address_mode_t enMode) +{ + ASSERT(IS_VALID_CH(enCh)); + ASSERT(IS_VALID_ADDR_MODE(enMode)); + + if((!IS_VALID_CH(enCh)) || (!IS_VALID_ADDR_MODE(enMode))) + { + return ErrorInvalidParameter; + } + + if(enCh == DmaCh0) + { + M0P_DMAC->CONFB0_f.FS = enMode; + } + else{ + M0P_DMAC->CONFB1_f.FS = enMode; + } + + + return Ok; +} + +/** +******************************************************************************* +** \brief Set the destination address mode of the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** \param [in] enMode The specified dma address mode. +** \arg AddressFix Address fixed. +** \arg AddressIncrease Address increased. +** \arg AddressDecrease Address decreased. +** +** \retval Ok Set successfully +** \retval ErrorInvalidParameter enCh or enMode is invalid +** +** \note None +** +******************************************************************************/ +en_result_t Dma_SetDestinationIncMode(en_dma_channel_t enCh, en_address_mode_t enMode) +{ + ASSERT(IS_VALID_CH(enCh)); + ASSERT(IS_VALID_ADDR_MODE(enMode)); + + if((!IS_VALID_CH(enCh)) || (!IS_VALID_ADDR_MODE(enMode))) + { + return ErrorInvalidParameter; + } + + if(enCh == DmaCh0) + { + M0P_DMAC->CONFB0_f.FD = enMode; + } + else{ + M0P_DMAC->CONFB1_f.FD = enMode; + } + + return Ok; +} + +/** +******************************************************************************* +** \brief Enable source repeat function of the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** +** \retval Ok Enable successfully. +** \retval ErrorInvalidParameter enCh is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_EnableContinusTranfer(en_dma_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + + if(!IS_VALID_CH(enCh)) + { + return ErrorInvalidParameter; + } + if(enCh == DmaCh0) + { + M0P_DMAC->CONFB0_f.MSK = 1; + } + else{ + M0P_DMAC->CONFB1_f.MSK = 1; + } + return Ok; +} + +/** +******************************************************************************* +** \brief Disable source repeat function of the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** +** \retval Ok Disable successfully. +** \retval ErrorInvalidParameter enCh is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_DisableContinusTranfer(en_dma_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + + if(!IS_VALID_CH(enCh)) + { + return ErrorInvalidParameter; + } + + if(enCh == DmaCh0) + { + M0P_DMAC->CONFB0_f.MSK = 0; + } + else{ + M0P_DMAC->CONFB1_f.MSK = 0; + } + + return Ok; +} +/** +******************************************************************************* +** \brief Halt the all dma channel. +** +** \param [in] enCh The specified dma channel. +** +** \retval Ok Disable successfully. +** \retval ErrorInvalidParameter enCh is invalid. +** +** \note None +** +******************************************************************************/ +void Dma_HaltTranfer(void) +{ + M0P_DMAC->CONF_f.HALT = 0x1; +} +/** +******************************************************************************* +** \brief Recover all dma channel from HALT. +** +** \param [in] enCh The specified dma channel. +** +** \retval Ok Disable successfully. +** \retval ErrorInvalidParameter enCh is invalid. +** +** \note None +** +******************************************************************************/ +void Dma_RecoverTranfer(void) +{ + M0P_DMAC->CONF_f.HALT = 0x0; +} +/** +******************************************************************************* +** \brief Pause the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** +** \retval Ok Disable successfully. +** \retval ErrorInvalidParameter enCh is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_PauseChannelTranfer(en_dma_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + + if((!IS_VALID_CH(enCh))) + { + return ErrorInvalidParameter; + } + + if(enCh == DmaCh0) + { + M0P_DMAC->CONFA0_f.PAS = 1; + } + else{ + M0P_DMAC->CONFA1_f.PAS = 1; + } + return Ok; +} +/** +******************************************************************************* +** \brief Recover the specified dma channel from PAUSE. +** +** \param [in] enCh The specified dma channel. +** +** \retval Ok Disable successfully. +** \retval ErrorInvalidParameter enCh is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_RecoverChannelTranfer(en_dma_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + + if((!IS_VALID_CH(enCh))) + { + return ErrorInvalidParameter; + } + + if(enCh == DmaCh0) + { + M0P_DMAC->CONFA0_f.PAS = 0; + } + else{ + M0P_DMAC->CONFA1_f.PAS = 0; + } + return Ok; +} +/** +******************************************************************************* +** \brief Set transfer data width of the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** \param [in] enWidth The specified transfer data width. +** \arg Dma8Bit The 8 bit transfer via DMA. +** \arg Dma16Bit The 16 bit transfer via DMA. +** \arg Dma32Bit The 32 bit transfer via DMA. +** +** \retval Ok Set successfully +** \retval ErrorInvalidParameter enCh or enWidth is invalid +** +** \note None +** +******************************************************************************/ +en_result_t Dma_SetTransferWidth(en_dma_channel_t enCh, en_dma_transfer_width_t enWidth) +{ + ASSERT(IS_VALID_CH(enCh)); + ASSERT(IS_VALID_TRN_WIDTH(enWidth)); + + if((!IS_VALID_CH(enCh)) || (!IS_VALID_TRN_WIDTH(enWidth))) + { + return ErrorInvalidParameter; + } + + if(enCh == DmaCh0) + { + M0P_DMAC->CONFB0_f.WIDTH = enWidth; + } + else{ + M0P_DMAC->CONFB1_f.WIDTH = enWidth; + } + + return Ok; +} +/** +******************************************************************************* +** \brief Set priority of dma channel. +** +** \param [in] enCh The specified dma channel. +** \param [in] enWidth The specified transfer data width. +** \arg Dma8Bit The 8 bit transfer via DMA. +** \arg Dma16Bit The 16 bit transfer via DMA. +** \arg Dma32Bit The 32 bit transfer via DMA. +** +** \retval Ok Set successfully +** \retval ErrorInvalidParameter enCh or enWidth is invalid +** +** \note None +** +******************************************************************************/ +en_result_t Dma_SetChPriority(en_dma_priority_t enPrio) +{ + ASSERT(IS_VALID_PRIO_MODE(enPrio)); + + if(!IS_VALID_PRIO_MODE(enPrio)) + { + return ErrorInvalidParameter; + } + + M0P_DMAC->CONF_f.PRIO = enPrio; + return Ok; +} +/** +******************************************************************************* +** \brief Enable interrupt of the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** +** \retval Ok Enable successfully. +** \retval ErrorInvalidParameter enCh is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_EnableChannelIrq(en_dma_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + + if(!IS_VALID_CH(enCh)) + { + return ErrorInvalidParameter; + } + if(enCh == DmaCh0) + { + M0P_DMAC->CONFB0_f.FIS_IE = 1; + } + else{ + M0P_DMAC->CONFB1_f.FIS_IE = 1; + } + + return Ok; +} + +/** +******************************************************************************* +** \brief Disable interrupt of the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** +** \retval Ok Disable successfully. +** \retval ErrorInvalidParameter enCh is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_DisableChannelIrq(en_dma_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + + if(!IS_VALID_CH(enCh)) + { + return ErrorInvalidParameter; + } + if(enCh == DmaCh0) + { + M0P_DMAC->CONFB0_f.FIS_IE = 0; + } + else{ + M0P_DMAC->CONFB1_f.FIS_IE = 0; + } + + return Ok; +} +/** +******************************************************************************* +** \brief Enable error interrupt of the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** +** \retval Ok Enable successfully. +** \retval ErrorInvalidParameter enCh is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_EnableChannelErrIrq(en_dma_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + + if(!IS_VALID_CH(enCh)) + { + return ErrorInvalidParameter; + } + if(enCh == DmaCh0) + { + M0P_DMAC->CONFB0_f.ERR_IE = 1; + } + else{ + M0P_DMAC->CONFB1_f.ERR_IE = 1; + } + + return Ok; +} + +/** +******************************************************************************* +** \brief Disable error interrupt of the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** +** \retval Ok Disable successfully. +** \retval ErrorInvalidParameter enCh is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_DisableChannelErrIrq(en_dma_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + + if(!IS_VALID_CH(enCh)) + { + return ErrorInvalidParameter; + } + if(enCh == DmaCh0) + { + M0P_DMAC->CONFB0_f.ERR_IE = 0; + } + else{ + M0P_DMAC->CONFB1_f.ERR_IE = 0; + } + + return Ok; +} + +/** + * \brief + * Dma中断æœåŠ¡ç¨‹åº + * + * \param [in] u8Param 未使用 + * + * \retval æ—  + */ + +void Dma_IRQHandler(uint8_t u8Param) +{ + if((DmaAddOverflow == M0P_DMAC->CONFB0_f.STAT)||(DmaHALT == M0P_DMAC->CONFB0_f.STAT)||(DmaAccSCRErr == M0P_DMAC->CONFB0_f.STAT) ||(DmaAccDestErr == M0P_DMAC->CONFB0_f.STAT)) + { + if (NULL != stcDmaIrqCalbaks.pfnDma0TranferErrIrq) + { + stcDmaIrqCalbaks.pfnDma0TranferCompleteIrq(); + } + M0P_DMAC->CONFB0_f.STAT = 0u; + } + if((DmaAddOverflow == M0P_DMAC->CONFB1_f.STAT)||(DmaHALT == M0P_DMAC->CONFB1_f.STAT)||(DmaAccSCRErr == M0P_DMAC->CONFB1_f.STAT) ||(DmaAccDestErr == M0P_DMAC->CONFB1_f.STAT)) + { + if (NULL != stcDmaIrqCalbaks.pfnDma1TranferErrIrq) + { + stcDmaIrqCalbaks.pfnDma1TranferCompleteIrq(); + } + M0P_DMAC->CONFB1_f.STAT = 0u; + } + if(DmaTransferComplete == M0P_DMAC->CONFB0_f.STAT) + { + if (NULL != stcDmaIrqCalbaks.pfnDma0TranferCompleteIrq) + { + stcDmaIrqCalbaks.pfnDma0TranferCompleteIrq(); + } + M0P_DMAC->CONFB0_f.STAT = 0u; + } + if(DmaTransferComplete == M0P_DMAC->CONFB1_f.STAT) + { + if (NULL != stcDmaIrqCalbaks.pfnDma1TranferCompleteIrq) + { + stcDmaIrqCalbaks.pfnDma1TranferCompleteIrq(); + } + M0P_DMAC->CONFB1_f.STAT = 0u; + } + +} +/** + * \brief + * é…ç½®ADCä¸­æ–­å‡½æ•°å…¥å£ + * + * \param [in] pstcAdcIrqCfg ADC中断é…置指针 + * \param [in] pstcAdcIrqCalbaks ADC中断回调函数指针 + * + * \retval æ—  + */ +en_result_t Dma_ConfigIrq(en_dma_channel_t enCh,stc_dma_irq_sel_t* stcDmaIrqCfg,stc_dma_irq_calbakfn_pt_t* pstcDmaIrqCalbaks) +{ + ASSERT(IS_VALID_CH(enCh)); + + if(!IS_VALID_CH(enCh)) + { + return ErrorInvalidParameter; + } + if(DmaCh0 == enCh) + { + if (TRUE == stcDmaIrqCfg->TrnErrIrq) + { + if (NULL != pstcDmaIrqCalbaks->pfnDma0TranferCompleteIrq) + { + stcDmaIrqCalbaks.pfnDma0TranferErrIrq = pstcDmaIrqCalbaks->pfnDma0TranferErrIrq; + } + } + if (TRUE == stcDmaIrqCfg->TrnCpltIrq) + { + if (NULL != pstcDmaIrqCalbaks->pfnDma0TranferCompleteIrq) + { + stcDmaIrqCalbaks.pfnDma0TranferCompleteIrq = pstcDmaIrqCalbaks->pfnDma0TranferCompleteIrq; + } + } + } + else if(DmaCh1 == enCh) + { + if (TRUE == stcDmaIrqCfg->TrnErrIrq) + { + if (NULL != pstcDmaIrqCalbaks->pfnDma1TranferCompleteIrq) + { + stcDmaIrqCalbaks.pfnDma1TranferErrIrq = pstcDmaIrqCalbaks->pfnDma1TranferErrIrq; + } + } + if (TRUE == stcDmaIrqCfg->TrnCpltIrq) + { + if (NULL != pstcDmaIrqCalbaks->pfnDma1TranferCompleteIrq) + { + stcDmaIrqCalbaks.pfnDma1TranferCompleteIrq = pstcDmaIrqCalbaks->pfnDma1TranferCompleteIrq; + } + } + }else + {} + return Ok; +} +/** +** \brief +** 获å–DMAçŠ¶æ€ +** +** \param [in] enCh The specified dma channel. +** +** \retval en_dma_stat_t +** +** +** \retval æ—  +**/ +en_dma_stat_t Dma_GetStat(en_dma_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + + if(!IS_VALID_CH(enCh)) + { + return DEFAULT; + } + if(enCh == DmaCh0) + { + return (en_dma_stat_t)M0P_DMAC->CONFB0_f.STAT ; + } + else{ + return (en_dma_stat_t)M0P_DMAC->CONFB1_f.STAT ; + } +} +/** +** \brief +** 获å–DMAçŠ¶æ€ +** +** \param [in] enCh The specified dma channel. +** +** \retval en_dma_stat_t +** +** +** \retval æ—  +**/ +void Dma_ClrStat(en_dma_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + + if(enCh == DmaCh0) + { + M0P_DMAC->CONFB0_f.STAT = 0x0; + } + else{ + M0P_DMAC->CONFB1_f.STAT = 0x0; + } +} + +//@} // DmacGroup + +/******************************************************************************* +* EOF (not truncated) +******************************************************************************/ diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/flash.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/flash.c new file mode 100644 index 0000000000..33b3f62b8f --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/flash.c @@ -0,0 +1,688 @@ +/****************************************************************************** +*Copyright(C)2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file flash.c + ** + ** Common API of flash. + ** @link flashGroup Some description @endlink + ** + ** - 2018-05-08 + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "flash.h" +/** + ******************************************************************************* + ** \addtogroup FlashGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define FLASH_END_ADDR (0x0000FFFFu) +#define FLASH_BYPASS() M0P_FLASH->BYPASS_f.BYSEQ = 0x5A5A;\ + M0P_FLASH->BYPASS_f.BYSEQ = 0xA5A5; +#define FLASH_IE_TRUE (0x03) +#define FLASH_IE_FALSE (0x00) +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ +/** + ****************************************************************************** + ** \brief FLASH OP + ** + ** Flash æ“作控制数æ®ç±»åž‹é‡å®šä¹‰ + ******************************************************************************/ +typedef enum en_flash_op +{ + Read = 0u, ///<读é…置值 + Program = 1u, ///<编程é…置值 + SectorErase = 2u, ///<扇区擦除é…置值 + ChipErase = 3u, ///<全片擦除é…置值 +} en_flash_op_t; + +/** + ****************************************************************************** + ** \brief FLASH LOCK + ** + ** Flash 加解é”æ•°æ®ç±»åž‹é‡å®šä¹‰ + ******************************************************************************/ +typedef enum en_flash_lock +{ + LockAll = 0x00000000u, ///<å…¨ç‰‡åŠ é” + UnlockAll = (int)0xFFFFFFFFu, ///<å…¨ç‰‡è§£é” +} en_flash_lock_t; + +/** + ****************************************************************************** + ** \brief FLASH 编程时间å‚æ•°é…ç½® + ** + ** FLASH编程时间å‚æ•°é…置数æ®ç±»åž‹é‡å®šä¹‰ (4MHz) + ******************************************************************************/ +typedef enum en_flash_prgtimer +{ + Tnvs = 0x20u, + Tpgs = 0x17u, + Tprog = 0x1Bu, + Tserase = 0x4650u, + Tmerase = 0x222E0u, + Tprcv = 0x18u, + Tsrcv = 0xF0u, + Tmrcv = 0x3E8u, +} en_flash_prgtimer_t; + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static func_ptr_t pfnFlashCallback = NULL; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ***************************************************************************** + ** \brief Flash中断æœåŠ¡å‡½æ•° + ** + ** + ** \param [in] u8Param == 0 + ** + *****************************************************************************/ +void EfRam_IRQHandler(uint8_t u8Param) +{ + if(NULL != pfnFlashCallback) + { + pfnFlashCallback(); + } +} + +/** + ***************************************************************************** + ** \brief Flashä¸­æ–­æ ‡å¿—èŽ·å– + ** + ** + ** \param [in] enFlashIntType Flash中断类型 + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +boolean_t Flash_GetIntFlag(en_flash_int_type_t enFlashIntType) +{ + boolean_t bRetVal = FALSE; + + switch (enFlashIntType) + { + case FlashPCInt: + bRetVal = M0P_FLASH->IFR_f.IF0 ? TRUE : FALSE; + break; + case FlashSlockInt: + bRetVal = M0P_FLASH->IFR_f.IF1 ? TRUE : FALSE; + break; + default: + bRetVal = FALSE; + break; + } + + return bRetVal; +} + +/** + ***************************************************************************** + ** \brief Flash中断标志清除 + ** + ** + ** \param [in] enFlashIntType Flash中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Flash_ClearIntFlag(en_flash_int_type_t enFlashIntType) +{ + en_result_t enResult = Error; + + switch (enFlashIntType) + { + case FlashPCInt: + FLASH_BYPASS(); + M0P_FLASH->ICLR_f.ICLR0 = FALSE; + enResult = Ok; + break; + case FlashSlockInt: + FLASH_BYPASS(); + M0P_FLASH->ICLR_f.ICLR1 = FALSE; + enResult = Ok; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Flash中断使能 + ** + ** + ** \param [in] enFlashIntType Flash中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Flash_EnableIrq (en_flash_int_type_t enFlashIntType) +{ + en_result_t enResult = Error; + + switch (enFlashIntType) + { + case FlashPCInt: + FLASH_BYPASS(); + M0P_FLASH->CR_f.IE |= 0x01; + enResult = Ok; + break; + case FlashSlockInt: + FLASH_BYPASS(); + M0P_FLASH->CR_f.IE |= 0x02; + enResult = Ok; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Flash中断ç¦æ­¢ + ** + ** + ** \param [in] enFlashIntType Flash中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Flash_DisableIrq(en_flash_int_type_t enFlashIntType) +{ + en_result_t enResult = Error; + + switch (enFlashIntType) + { + case FlashSlockInt: + FLASH_BYPASS(); + M0P_FLASH->CR_f.IE &= ~0x02u; + enResult = Ok; + break; + case FlashPCInt: + FLASH_BYPASS(); + M0P_FLASH->CR_f.IE &= ~0x01u; + enResult = Ok; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief FLASH åˆå§‹åŒ–函数——中断æœåŠ¡ç¨‹åºã€ç¼–程时间é…ç½®åŠä½ŽåŠŸè€—æ¨¡å¼ + ** + ** 该函数用于é…置中断æœåŠ¡å‡½æ•°ã€ä½ŽåŠŸè€—模å¼ã€æ ¹æ®ç³»ç»Ÿæ—¶é’Ÿé…ç½®FLASH编程时间相关寄存器. + ** + ** \param [in] pfnFlashCb Flash中断æœåŠ¡å›žè°ƒå‡½æ•°[void function(void)] + ** \param [in] u8FreqCfg FLASH编程时钟频率é…ç½®(æ ¹æ®HCLK的频率选择é…置值)： + ** 1 - (0,4]MHz; + ** 2 - (4,8]MHz; + ** 4 - (8,16]MHz; + ** 6 - (16,24]MHz; + ** 8 - (24,32]MHz（该é…置会设置æ’å…¥1个FLASH等待周期）; + ** 12 - (32,48]MHz（该é…置会设置æ’å…¥1个FLASH等待周期）; + ** other - 无效值 + ** \param [in] bDpstbEn TRUE - 当系统进入DeepSleep模å¼ï¼ŒFLASH进入低功耗模å¼; + ** FALSE - 当系统进入DeepSleep模å¼ï¼ŒFLASHä¸è¿›å…¥ä½ŽåŠŸè€—模å¼; + ** + ** \retval Ok æ“作æˆåŠŸ. + ** \retval ErrorInvalidParameter å‚数无效. + ** + *****************************************************************************/ +en_result_t Flash_Init(func_ptr_t pfnFlashCb, uint8_t u8FreqCfg, boolean_t bDpstbEn) +{ + en_result_t enResult = Ok; + + if ((1 != u8FreqCfg) && + (2 != u8FreqCfg) && + (4 != u8FreqCfg) && + (6 != u8FreqCfg) && + (8 != u8FreqCfg) && + (12 != u8FreqCfg)) + { + enResult = ErrorInvalidParameter; + return (enResult); + } + + //当系统进入DeepSleep模å¼æ—¶ï¼ŒFLASH模å¼é…ç½® + FLASH_BYPASS(); + M0P_FLASH->CR_f.DPSTB_EN = bDpstbEn; + + //flash时间å‚数寄存器é…ç½® + FLASH_BYPASS(); + M0P_FLASH->TNVS_f.TNVS = Tnvs * u8FreqCfg; + FLASH_BYPASS(); + M0P_FLASH->TPGS_f.TPGS = Tpgs * u8FreqCfg; + FLASH_BYPASS(); + M0P_FLASH->TPROG_f.TPROG = Tprog * u8FreqCfg; + FLASH_BYPASS(); + M0P_FLASH->TSERASE_f.TSERASE = Tserase * u8FreqCfg; + FLASH_BYPASS(); + M0P_FLASH->TMERASE_f.TMERASE = Tmerase * u8FreqCfg; + FLASH_BYPASS(); + M0P_FLASH->TPRCV_f.TPRCV = Tprcv * u8FreqCfg; + FLASH_BYPASS(); + M0P_FLASH->TSRCV_f.TSRCV = Tsrcv * u8FreqCfg; + FLASH_BYPASS(); + M0P_FLASH->TMRCV_f.TMRCV = Tmrcv * u8FreqCfg; + + //å¼€å¯è¯»FLASH等待周期 + if (8 == u8FreqCfg) + { + FLASH_BYPASS(); + M0P_FLASH->CR_f.WAIT = 0x01; + } + else if(12 == u8FreqCfg) + { + FLASH_BYPASS(); + M0P_FLASH->CR_f.WAIT = 0x01; + } + else + { + FLASH_BYPASS(); + M0P_FLASH->CR_f.WAIT = 0x00; + } + + pfnFlashCallback = pfnFlashCb; + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief FLASH 字节写 + ** + ** 用于å‘FLASH写入1字节数æ®. + ** + ** \param [in] u32Addr Flashåœ°å€ + ** \param [in] u8Data 1å­—èŠ‚æ•°æ® + ** + ** \retval Ok 写入æˆåŠŸ. + ** \retval ErrorInvalidParameter FLASH地å€æ— æ•ˆ + *****************************************************************************/ +en_result_t Flash_WriteByte(uint32_t u32Addr, uint8_t u8Data) +{ + en_result_t enResult = Ok; + + if (FLASH_END_ADDR < u32Addr) + { + enResult = ErrorInvalidParameter; + return (enResult); + } + + //unlock flash + FLASH_BYPASS(); + M0P_FLASH->SLOCK_f.SLOCK = (uint32_t)UnlockAll; + + //busy? + while (TRUE == M0P_FLASH->CR_f.BUSY) + { + ; + } + + //set OP + FLASH_BYPASS(); + M0P_FLASH->CR_f.OP = Program; + + //write data + *((volatile uint8_t*)u32Addr) = u8Data; + + //busy? + while (TRUE == M0P_FLASH->CR_f.BUSY) + { + ; + } + + //lock flash + FLASH_BYPASS(); + M0P_FLASH->SLOCK_f.SLOCK = (uint32_t)LockAll; + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief FLASH åŠå­—写 + ** + ** 用于å‘FLASH写入åŠå­—（2字节）数æ®. + ** + ** \param [in] u32Addr Flashåœ°å€ + ** \param [in] u16Data åŠå­—（2å­—èŠ‚ï¼‰æ•°æ® + ** + ** \retval Ok 写入æˆåŠŸ. + ** \retval ErrorInvalidParameter FLASH地å€æ— æ•ˆ + *****************************************************************************/ +en_result_t Flash_WriteHalfWord(uint32_t u32Addr, uint16_t u16Data) +{ + en_result_t enResult = Ok; + + if ((FLASH_END_ADDR < u32Addr) || (u32Addr % 2)) + { + enResult = ErrorInvalidParameter; + return (enResult); + } + + //unlock flash + FLASH_BYPASS(); + M0P_FLASH->SLOCK_f.SLOCK = (uint32_t)UnlockAll; + + //busy? + while (TRUE == M0P_FLASH->CR_f.BUSY) + { + ; + } + + //set OP + FLASH_BYPASS(); + M0P_FLASH->CR_f.OP = Program; + + //write data + *((volatile uint16_t*)u32Addr) = u16Data; + + //busy? + while (TRUE == M0P_FLASH->CR_f.BUSY) + { + ; + } + + //lock flash + FLASH_BYPASS(); + M0P_FLASH->SLOCK_f.SLOCK = (uint32_t)LockAll; + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief FLASH 字写 + ** + ** 用于å‘FLASH写入1个字的数æ®. + ** + ** \param [in] u32Addr Flashåœ°å€ + ** \param [in] u32Data 1ä¸ªå­—æ•°æ® + ** + ** \retval Ok 写入æˆåŠŸ. + ** \retval ErrorInvalidParameter FLASH地å€æ— æ•ˆ + *****************************************************************************/ +en_result_t Flash_WriteWord(uint32_t u32Addr, uint32_t u32Data) +{ + en_result_t enResult = Ok; + + if ((FLASH_END_ADDR < u32Addr) || (u32Addr % 4)) + { + enResult = ErrorInvalidParameter; + return (enResult); + } + + //unlock flash + FLASH_BYPASS(); + M0P_FLASH->SLOCK_f.SLOCK = (uint32_t)UnlockAll; + + //busy? + while (TRUE == M0P_FLASH->CR_f.BUSY) + { + ; + } + + //set OP + FLASH_BYPASS(); + M0P_FLASH->CR_f.OP = Program; + + //write data + *((volatile uint32_t*)u32Addr) = u32Data; + + //busy? + while (TRUE == M0P_FLASH->CR_f.BUSY) + { + ; + } + + //lock flash + FLASH_BYPASS(); + M0P_FLASH->SLOCK_f.SLOCK = LockAll; + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief FLASH 扇区擦除 + ** + ** FLASH 扇区擦除. + ** + ** \param [in] u32SectorAddr æ‰€æ“¦é™¤æ‰‡åŒºå†…çš„åœ°å€ + ** + ** \retval Ok 擦除æˆåŠŸ. + ** \retval ErrorInvalidParameter FLASH地å€æ— æ•ˆ + *****************************************************************************/ +en_result_t Flash_SectorErase(uint32_t u32SectorAddr) +{ + + en_result_t enResult = Ok; + + if (FLASH_END_ADDR < u32SectorAddr) + { + enResult = ErrorInvalidParameter; + return (enResult); + } + + //unlock flash + FLASH_BYPASS(); + M0P_FLASH->SLOCK_f.SLOCK = (uint32_t)UnlockAll; + + //busy? + while (TRUE == M0P_FLASH->CR_f.BUSY) + { + ; + } + + //set OP + FLASH_BYPASS(); + M0P_FLASH->CR_f.OP = SectorErase; + + //write data + *((volatile uint8_t*)u32SectorAddr) = 0; + + //busy? + while (TRUE == M0P_FLASH->CR_f.BUSY) + { + ; + } + + //lock flash + FLASH_BYPASS(); + M0P_FLASH->SLOCK_f.SLOCK = LockAll; + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief FLASH 全片擦除 + ** + ** FLASH 全片擦除. + ** + ** + ** \retval Ok 擦除æˆåŠŸ. + ** + *****************************************************************************/ +en_result_t Flash_ChipErase(void) +{ + + en_result_t enResult = Ok; + + //unlock flash + FLASH_BYPASS(); + M0P_FLASH->SLOCK_f.SLOCK = (uint32_t)UnlockAll; + + //busy? + while (TRUE == M0P_FLASH->CR_f.BUSY) + { + ; + } + + //set OP + FLASH_BYPASS(); + M0P_FLASH->CR_f.OP = ChipErase; + + //write data + *((volatile uint8_t*)0) = 0; + + //busy? + while (TRUE == M0P_FLASH->CR_f.BUSY) + { + ; + } + + //lock flash + FLASH_BYPASS(); + M0P_FLASH->SLOCK_f.SLOCK = LockAll; + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief FLASH 编程ä¿æŠ¤åŠ é” + ** + ** \param [in] enFlashSector 加é”范围选择枚举 + ** + ** \retval Ok 加é”æˆåŠŸ + ** \retval ErrorInvalidParameter å‚数错误 + *****************************************************************************/ +en_result_t Flash_Lock(en_flash_sector_lock_t enFlashSector) +{ + en_result_t enResult = Ok; + + FLASH_BYPASS(); + M0P_FLASH->SLOCK_f.SLOCK |= (uint32_t)enFlashSector; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief FLASH 编程ä¿æŠ¤è§£é” + ** + ** \param [in] enFlashSector 解é”范围选择枚举 + ** + ** \retval Ok 解é”æˆåŠŸ + ** \retval ErrorInvalidParameter å‚数错误 + *****************************************************************************/ +en_result_t Flash_Unlock(en_flash_sector_lock_t enFlashSector) +{ + en_result_t enResult = Ok; + + FLASH_BYPASS(); + M0P_FLASH->SLOCK_f.SLOCK &= ~(uint32_t)enFlashSector; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief FLASH 读等待周期设置 + ** + ** \param [in] enWaitCycle æ’å…¥FLASH读等待周期数枚举类型 + ** + ** \retval Ok 解é”æˆåŠŸ + ** \retval ErrorInvalidParameter å‚数错误 + *****************************************************************************/ +en_result_t Flash_WaitCycle(en_flash_waitcycle_t enWaitCycle) +{ + en_result_t enResult = Ok; + + //æ’å…¥FLASH读等待周期 + M0P_SYSCTRL->PERI_CLKEN_f.FLASH = 1; + M0P_FLASH->BYPASS_f.BYSEQ = 0x5A5A; + M0P_FLASH->BYPASS_f.BYSEQ = 0xA5A5; + if (0 == enWaitCycle) + { + M0P_FLASH->CR_f.WAIT = 0; + } + else if(1 == enWaitCycle) + { + M0P_FLASH->CR_f.WAIT = 1; + } + else + { + M0P_FLASH->CR_f.WAIT = 2; + } + + return enResult; +} + + +//@} // FlashGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/gpio.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/gpio.c new file mode 100644 index 0000000000..9e8c3690f9 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/gpio.c @@ -0,0 +1,613 @@ +/****************************************************************************** +* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file Gpio.c + ** + ** GPIO driver API. + ** @link Driver Group Some description @endlink + ** + ** - 2018-04-22 1.0 Lux First version + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "gpio.h" + +/** + ******************************************************************************* + ** \addtogroup GpioGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define IS_VALID_PIN(port,pin) ( ) +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') * + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief GPIO åˆå§‹åŒ– + ** + ** \param [in] enPort IO Portå£ + ** \param [in] enPin IO Pinè„š + ** \param [in] pstcGpioCfg IO é…置结构体指针 + ** + ** \retval Ok 设置æˆåŠŸ + ** 其他值 设置失败 + ******************************************************************************/ +en_result_t Gpio_Init(en_gpio_port_t enPort, en_gpio_pin_t enPin, stc_gpio_config_t *pstcGpioCfg) +{ + //é…置为默认值,GPIO功能 + *((uint32_t*)(((uint32_t)(&(M0P_GPIO->PA00_SEL)) + enPort) + (((uint32_t)enPin)<<2))) = GpioAf0; + + //æ–¹å‘é…ç½® + if(GpioDirIn == pstcGpioCfg->enDir) + { + setBit(((uint32_t)&M0P_GPIO->PADIR + enPort), enPin, TRUE); + } + else + { + setBit(((uint32_t)&M0P_GPIO->PADIR + enPort), enPin, FALSE); + } + + //驱动能力é…ç½® + if(GpioDrvH == pstcGpioCfg->enDrv) + { + setBit(((uint32_t)&M0P_GPIO->PADR + enPort), enPin, FALSE); + } + else + { + setBit(((uint32_t)&M0P_GPIO->PADR + enPort), enPin, TRUE); + } + + //上拉下拉é…ç½® + if(GpioPu == pstcGpioCfg->enPuPd) + { + setBit(((uint32_t)&M0P_GPIO->PAPU + enPort), enPin, TRUE); + setBit(((uint32_t)&M0P_GPIO->PAPD + enPort), enPin, FALSE); + } + else if(GpioPd == pstcGpioCfg->enPuPd) + { + setBit(((uint32_t)&M0P_GPIO->PAPU + enPort), enPin, FALSE); + setBit(((uint32_t)&M0P_GPIO->PAPD + enPort), enPin, TRUE); + } + else + { + setBit(((uint32_t)&M0P_GPIO->PAPU + enPort), enPin, FALSE); + setBit(((uint32_t)&M0P_GPIO->PAPD + enPort), enPin, FALSE); + } + + //å¼€æ¼è¾“出功能 + if(GpioOdDisable == pstcGpioCfg->enOD) + { + setBit(((uint32_t)&M0P_GPIO->PAOD + enPort), enPin, FALSE); + } + else + { + setBit(((uint32_t)&M0P_GPIO->PAOD + enPort), enPin, TRUE); + } + + M0P_GPIO->CTRL2_f.AHB_SEL = pstcGpioCfg->enCtrlMode; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO IOè¾“å…¥å€¼èŽ·å– + ** + ** \param [in] enPort IO Portå£ + ** \param [in] enPin IO Pinè„š + ** + ** \retval boolean_t IO电平高低 + ******************************************************************************/ +boolean_t Gpio_GetInputIO(en_gpio_port_t enPort, en_gpio_pin_t enPin) +{ + return getBit(((uint32_t)&M0P_GPIO->PAIN + enPort), enPin); +} + +/** + ******************************************************************************* + ** \brief GPIO IO Port输入数æ®èŽ·å– + ** + ** \param [in] enPort IO Port + ** + ** \retval boolean_t IO Portæ•°æ® + ******************************************************************************/ +uint16_t Gpio_GetInputData(en_gpio_port_t enPort) +{ + return (uint16_t)(*((uint32_t *)((uint32_t)&M0P_GPIO->PAIN + enPort))); +} + +/** + ******************************************************************************* + ** \brief GPIO IO输出值写入 + ** + ** \param [in] enPort IO Portå£ + ** \param [in] enPin IO Pinè„š + ** \param [out] bVal 输出值 + ** + ** \retval en_result_t Ok 设置æˆåŠŸ + ** 其他值 设置失败 + ******************************************************************************/ +en_result_t Gpio_WriteOutputIO(en_gpio_port_t enPort, en_gpio_pin_t enPin, boolean_t bVal) +{ + setBit(((uint32_t)&M0P_GPIO->PAOUT + enPort), enPin, bVal); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO IOè¾“å‡ºå€¼èŽ·å– + ** + ** \param [in] enPort IO Portå£ + ** \param [in] enPin IO Pinè„š + ** + ** \retval boolean_t IO电平高低 + ******************************************************************************/ +boolean_t Gpio_ReadOutputIO(en_gpio_port_t enPort, en_gpio_pin_t enPin) +{ + return getBit(((uint32_t)&M0P_GPIO->PAOUT + enPort), enPin); +} + +/** + ******************************************************************************* + ** \brief GPIO IO Port设置，å¯åŒæ—¶è®¾ç½®ä¸€ç»„Port中的多个PIN + ** + ** \param [in] enPort IO Port + ** \param [in] u16ValMsk 该Portçš„16个PIN掩ç å€¼,将需è¦è®¾ç½®çš„PIN对应的bit写1有效 + ** + ** \retval boolean_t IO Portæ•°æ® + ******************************************************************************/ +en_result_t Gpio_SetPort(en_gpio_port_t enPort, uint16_t u16ValMsk) +{ + *((uint16_t*)(((uint32_t)&(M0P_GPIO->PABSET)) + enPort)) = u16ValMsk; + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO IO设置 + ** + ** \param [in] enPort IO Portå£ + ** \param [in] enPin IO Pinè„š + ** + ** \retval en_result_t Ok 设置æˆåŠŸ + ** 其他值 设置失败 + ******************************************************************************/ +en_result_t Gpio_SetIO(en_gpio_port_t enPort, en_gpio_pin_t enPin) +{ + setBit(((uint32_t)&M0P_GPIO->PABSET + enPort), enPin, TRUE); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO IO Port清零，å¯åŒæ—¶æ¸…零一组Port中的多个PIN + ** + ** \param [in] enPort IO Port + ** \param [in] u16ValMsk 该Portçš„16个PIN掩ç å€¼,将需è¦æ¸…零的PIN对应的bit写1有效 + ** + ** \retval boolean_t IO Portæ•°æ® + ******************************************************************************/ +en_result_t Gpio_ClrPort(en_gpio_port_t enPort, uint16_t u16ValMsk) +{ + *((uint16_t*)(((uint32_t)&(M0P_GPIO->PABCLR)) + enPort)) = u16ValMsk; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO IO清零 + ** + ** \param [in] enPort IO Portå£ + ** \param [in] enPin IO Pinè„š + ** + ** \retval en_result_t Ok 设置æˆåŠŸ + ** 其他值 设置失败 + ******************************************************************************/ +en_result_t Gpio_ClrIO(en_gpio_port_t enPort, en_gpio_pin_t enPin) +{ + setBit(((uint32_t)&M0P_GPIO->PABCLR + enPort), enPin, TRUE); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO IO Portç½®ä½/清零，å¯åŒæ—¶ç½®ä½/清零一组Port中的多个PIN + ** + ** \param [in] enPort IO Port +** \param [in] u32ValMsk 高16bits表示该Portçš„16个PINç½®ä½æŽ©ç å€¼, + ** 低16bits表示该Portçš„16个PIN清零掩ç å€¼, +** 将需è¦è®¾ç½®çš„PIN对应的bit写1,åŒä¸€ä¸ªPIN的掩ç åŒæ—¶ä¸º1,则该PIN清零。 + ** + ** \retval en_result_t Ok 设置æˆåŠŸ + ** 其他值 设置失败 + ******************************************************************************/ +en_result_t Gpio_SetClrPort(en_gpio_port_t enPort, uint32_t u32ValMsk) +{ + *((uint32_t*)(((uint32_t)&(M0P_GPIO->PABSETCLR)) + enPort)) = u32ValMsk; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO IOé…ç½®ä¸ºæ¨¡æ‹ŸåŠŸèƒ½æ¨¡å¼ + ** + ** \param [in] enPort IO Portå£ + ** \param [in] enPin IO Pinè„š + ** + ** \retval Ok 设置æˆåŠŸ + ** 其他值 设置失败 + ******************************************************************************/ +en_result_t Gpio_SetAnalogMode(en_gpio_port_t enPort, en_gpio_pin_t enPin) +{ + setBit((uint32_t)&M0P_GPIO->PAADS + enPort, enPin, TRUE); + + return Ok; +} + +/** + ******************************************************************************* +** \brief GPIO IOå¤ç”¨åŠŸèƒ½è®¾ç½® + ** + ** \param [in] enPort IO Portå£ + ** \param [in] enPin IO Pinè„š + ** \param [in] enAf å¤ç”¨åŠŸèƒ½æžšä¸¾ç±»åž‹é€‰æ‹© + ** \retval Ok 设置æˆåŠŸ + ** 其他值 设置失败 + ******************************************************************************/ +en_result_t Gpio_SetAfMode(en_gpio_port_t enPort, en_gpio_pin_t enPin, en_gpio_af_t enAf) +{ + *((uint32_t*)(((uint32_t)(&(M0P_GPIO->PA00_SEL)) + enPort) + (((uint32_t)enPin)<<2))) = enAf; + + return Ok; +} + + +static en_result_t _GpioEnableIrq(en_gpio_port_t enPort, + en_gpio_pin_t enPin, + en_gpio_irqtype_t enType, + boolean_t bEnable) +{ + //high level + if (enType & GpioIrqHigh) + { + setBit((uint32_t)&M0P_GPIO->PAHIE + enPort, enPin, bEnable); + } + //low level + if (enType & GpioIrqLow) + { + setBit((uint32_t)&M0P_GPIO->PALIE + enPort, enPin, bEnable); + } + //rising + if (enType & GpioIrqRising) + { + setBit((uint32_t)&M0P_GPIO->PARIE + enPort, enPin, bEnable); + } + //falling + if (enType & GpioIrqFalling) + { + setBit((uint32_t)&M0P_GPIO->PAFIE + enPort, enPin, bEnable); + } + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO IO中断使能 + ** + ** \param [in] enPort IO Portå£ + ** \param [in] enPin IO Pinè„š + ** \param [in] enType 中断使能类型 + ** + ** \retval Ok 设置æˆåŠŸ + ******************************************************************************/ +en_result_t Gpio_EnableIrq(en_gpio_port_t enPort, en_gpio_pin_t enPin, en_gpio_irqtype_t enType) +{ + _GpioEnableIrq(enPort, enPin, enType, TRUE); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO IO中断关闭 + ** + ** \param [in] enPort IO Portå£ + ** \param [in] enPin IO Pinè„š + ** \param [in] enType 中断使能类型 + ** + ** \retval Ok 设置æˆåŠŸ + ******************************************************************************/ +en_result_t Gpio_DisableIrq(en_gpio_port_t enPort, en_gpio_pin_t enPin, en_gpio_irqtype_t enType) +{ + _GpioEnableIrq(enPort, enPin, enType, FALSE); + + return Ok; +} + + +/** + ******************************************************************************* + ** \brief GPIO 获得IOä¸­æ–­çŠ¶æ€ + ** + ** \param [in] u8Port IO Portå£ + ** \param [in] u8Pin IO Pinè„š + ** + ** \retval IO中断状æ€å¼€å…³ + ******************************************************************************/ +boolean_t Gpio_GetIrqStatus(en_gpio_port_t enPort, en_gpio_pin_t enPin) +{ + return getBit((uint32_t)&M0P_GPIO->PA_STAT + enPort, enPin); +} + +/** + ******************************************************************************* + ** \brief GPIO 清除IOä¸­æ–­çŠ¶æ€ + ** + ** \param [in] u8Port IO Portå£ + ** \param [in] u8Pin IO Pinè„š + ** + ** \retval Ok 设置æˆåŠŸ + ******************************************************************************/ +en_result_t Gpio_ClearIrq(en_gpio_port_t enPort, en_gpio_pin_t enPin) +{ + setBit((uint32_t)&M0P_GPIO->PA_ICLR + enPort, enPin, FALSE); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO 端å£è¾…助功能é…置——中断模å¼é…ç½® + ** + ** \param [in] enIrqMode 端å£ä¸­æ–­æ¨¡å¼ï¼ˆæ·±åº¦ä¼‘眠是å¦å“应中断） + ** + ** \retval Ok 设置æˆåŠŸ + ******************************************************************************/ +en_result_t Gpio_SfIrqModeConfig(en_gpio_sf_irqmode_t enIrqMode) +{ + M0P_GPIO->CTRL0_f.IESEL = enIrqMode; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO 端å£è¾…助功能é…置——IR输出æžæ€§é…ç½® + ** + ** \param [in] enIrPolMode IR输出æžæ€§é…置枚举 + ** + ** \retval Ok 设置æˆåŠŸ + ******************************************************************************/ +en_result_t Gpio_SfIrPolConfig(en_gpio_sf_irpol_t enIrPolMode) +{ + M0P_GPIO->CTRL1_f.IR_POL = enIrPolMode; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO 端å£è¾…助功能é…置——HCLK输出é…ç½® + ** + ** \param [in] enGate HCLK输出使能 + ** \param [in] enDiv 输出分频枚举值 + ** + ** \retval Ok 设置æˆåŠŸ + ******************************************************************************/ +en_result_t Gpio_SfHClkOutputConfig(en_gpio_sf_hclkout_g_t enGate, en_gpio_sf_hclkout_div_t enDiv) +{ + M0P_GPIO->CTRL1_f.HCLK_EN = enGate; + M0P_GPIO->CTRL1_f.HCLK_SEL = enDiv; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO 端å£è¾…助功能é…置——PCLK输出é…ç½® + ** + ** \param [in] enGate PCLK输出使能 + ** \param [in] enDiv 输出分频枚举值 + ** + ** \retval Ok 设置æˆåŠŸ + ******************************************************************************/ +en_result_t Gpio_SfPClkOutputConfig(en_gpio_sf_pclkout_g_t enGate, en_gpio_sf_pclkout_div_t enDiv) +{ + M0P_GPIO->CTRL1_f.PCLK_EN = enGate; + M0P_GPIO->CTRL1_f.PCLK_SEL = enDiv; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO 端å£è¾…助功能é…置——外部时钟输入æ¥æºé…ç½® + ** + ** \param [in] enExtClk 外部时钟信å·æ¥æºé€‰æ‹©æžšä¸¾ + ** + ** \retval Ok 设置æˆåŠŸ + ******************************************************************************/ +en_result_t Gpio_SfExtClkConfig(en_gpio_sf_ssn_extclk_t enExtClk) +{ + M0P_GPIO->CTRL1_f.EXT_CLK_SEL = enExtClk; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO 端å£è¾…助功能é…置——SSN 通é“ä¿¡å·æ¥æºé…ç½® + ** + ** \param [in] enSpi SSN SPI通é“选择枚举 + ** \param [in] enSsn SSN ä¿¡å·æ¥æºé€‰æ‹©æžšä¸¾ + ** + ** \retval Ok 设置æˆåŠŸ + ******************************************************************************/ +en_result_t Gpio_SfSsnConfig(en_gpio_sf_ssnspi_t enSpi, en_gpio_sf_ssn_extclk_t enSsn) +{ + //SPI0 + if(enSpi == GpioSpi0) + { + M0P_GPIO->CTRL1_f.SSN0_SEL = enSsn; + } + //SPI1 + if(enSpi == GpioSpi1) + { + M0P_GPIO->CTRL2_f.SSN1_SEL = enSsn; + } + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO 端å£è¾…助功能é…置——Timer 门控输入é…ç½® + ** + ** \param [in] enTimG Timer类型选择枚举 + ** \param [in] enSf Timer互è”功能选择枚举 + ** + ** \retval Ok 设置æˆåŠŸ + ******************************************************************************/ +en_result_t Gpio_SfTimGConfig(en_gpio_sf_tim_g_t enTimG, en_gpio_sf_t enSf) +{ + M0P_GPIO->TIMGS &= (uint32_t)(~(0x07U<TIMGS |= (uint32_t)(enSf<TIMES &= (uint32_t)(~(0x07U<TIMES |= (uint32_t)(enSf<TIMCPS &= (uint32_t)(~(0x07u<TIMCPS |= (uint32_t)(enSf<PCAS_f.PCA_CH0 = enSf; + } + + if(GpioSfPcaECI == enPca) + { + M0P_GPIO->PCAS_f.PCA_ECI = enSf; + } + + return Ok; +} + + +//@} // GpioGroup + + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/hdiv.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/hdiv.c new file mode 100644 index 0000000000..825058189d --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/hdiv.c @@ -0,0 +1,176 @@ +/****************************************************************************** +*Copyright(C)2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file crc.c +** +** Common API of crc. +** @link crcGroup Some description @endlink +** +** - 2017-05-16 +** +******************************************************************************/ + +/******************************************************************************* +* Include files +******************************************************************************/ +#include "ddl.h" +#include "hdiv.h" +/** +******************************************************************************* +** \addtogroup CrcGroup +******************************************************************************/ +//@{ + +/******************************************************************************* +* Local pre-processor symbols/macros ('#define') +******************************************************************************/ + +/******************************************************************************* +* Global variable definitions (declared in header file with 'extern') +******************************************************************************/ + +/******************************************************************************* +* Local type definitions ('typedef') +******************************************************************************/ + +/******************************************************************************* +* Local variable definitions ('static') +******************************************************************************/ + +/******************************************************************************* +* Local function prototypes ('static') +******************************************************************************/ + + +/******************************************************************************* +* Function implementation - global ('extern') and local ('static') +******************************************************************************/ +/** +* \brief +* HDIV 有符å·é™¤æ³• +* +* \param [in] Dividend 被除数 +* \param [in] Dividsor 除数 +* \param [out] stcDivResult 商和余数 +* +* \retval en_result_t Ok: é…ç½®æˆåŠŸ +* \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° +*/ +en_result_t Hdiv_Unsigned(uint32_t Dividend,uint16_t Divisor,stc_div_unsigned_result_t* stcDivResult) +{ + M0P_HDIV->SIGN_f.SIGN = 0; + if(NULL == stcDivResult) + { + return ErrorInvalidParameter; + } + (M0P_HDIV ->DIVIDEND) = Dividend; + (M0P_HDIV ->DIVISOR) = Divisor; + + if(Hdiv_GetZeroState() == TRUE) + { + return ErrorInvalidParameter; + } + + while(Hdiv_GetEndState() != TRUE) + { + ; + } + + stcDivResult->Quotient = M0P_HDIV->QUOTIENT_f.QUOTIENT; + stcDivResult->Remainder = M0P_HDIV ->REMAINDER_f.REMAINDER; + return Ok; +} + + +/** +* \brief +* HDIV 无符å·é™¤æ³• +* +* \param [in] Dividend 被除数 +* \param [in] Dividsor 除数 +* \param [out] stcDivResult 商和余数 +* +* \retval en_result_t Ok: é…ç½®æˆåŠŸ +* \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° +*/ +en_result_t Hdiv_Signed(int32_t Dividend,int16_t Divisor,stc_div_signed_result_t* stcDivResult) +{ + + __IO uint32_t * pDivdend = &(M0P_HDIV ->DIVIDEND); + __IO uint32_t * pDivsor = &(M0P_HDIV ->DIVISOR); + if(NULL == stcDivResult) + { + return ErrorInvalidParameter; + } + M0P_HDIV->SIGN_f.SIGN = 1; + *(__IO int32_t *)pDivdend = Dividend; + *(__IO int16_t *)pDivsor = Divisor; + + if(Hdiv_GetZeroState() == TRUE) + { + return ErrorInvalidParameter; + } + + while(Hdiv_GetEndState() != TRUE) + { + ; + } + + stcDivResult->Quotient = M0P_HDIV->QUOTIENT_f.QUOTIENT; + stcDivResult->Remainder = M0P_HDIV ->REMAINDER_f.REMAINDER; + return Ok; +} + +boolean_t Hdiv_GetEndState(void) +{ + return M0P_HDIV->STAT_f.END; +} + +boolean_t Hdiv_GetZeroState(void) +{ + return M0P_HDIV->STAT_f.ZERO; +} +//@} // CrcGroup + +/******************************************************************************* +* EOF (not truncated) +******************************************************************************/ diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/i2c.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/i2c.c new file mode 100644 index 0000000000..85a13463b6 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/i2c.c @@ -0,0 +1,666 @@ +/************************************************************************************* +* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file I2C.c + ** + ** WDT function driver API. + ** @link SampleGroup Some description @endlink + ** + ** - 2018-03-13 1.0 CJ First version for Device Driver Library of Module. + ** + ******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "i2c.h" + +/** + ******************************************************************************* + ** \addtogroup I2cGroup + ******************************************************************************/ +//@{ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ +static func_ptr_t pfnI2c0tCallback = NULL; +static func_ptr_t pfnI2c1tCallback = NULL; +/** + ****************************************************************************** + ** \brief I2C设置波特率é…置寄存器 + ** + ** \param [in] u8Tm 波特率é…置值 + ** + ** \retval enRet æˆåŠŸæˆ–失败 + ** + ******************************************************************************/ + en_result_t I2C_SetBaud(en_i2c_channel_t enCh,uint8_t u8Tm) + { + en_result_t enRet = Error; + if(I2C0 == enCh) + { + M0P_I2C0->TM = u8Tm; + } + else + { + M0P_I2C1->TM = u8Tm; + } + + enRet = Ok; + return enRet; + } + /** + ****************************************************************************** + ** \brief I2C功能设置相关函数 + ** + ** \param [in] enFunc功能å‚æ•° + ** + ** \retval enRet æˆåŠŸæˆ–失败 + ** + ******************************************************************************/ +en_result_t I2C_SetFunc(en_i2c_channel_t enCh,en_i2c_func_t enFunc) +{ + en_result_t enRet = Error; + if(I2C0 == enCh) + { + switch(enFunc) + { + case I2cMode_En: + M0P_I2C0->CR_f.ENS = 1; + break; + case I2cStart_En: + M0P_I2C0->CR_f.STA = 1; + break; + case I2cStop_En: + M0P_I2C0->CR_f.STO = 1; + break; + case I2cAck_En: + M0P_I2C0->CR_f.AA = 1; + break; + case I2cHlm_En: + M0P_I2C0->CR_f.H1M = 1; + break; + case I2cBaud_En: + M0P_I2C0->TMRUN = 0x01; + break; + default: + return ErrorInvalidParameter; + } + } + else + { + switch(enFunc) + { + case I2cMode_En: + M0P_I2C1->CR_f.ENS = 1; + break; + case I2cStart_En: + M0P_I2C1->CR_f.STA = 1; + break; + case I2cStop_En: + M0P_I2C1->CR_f.STO = 1; + break; + case I2cAck_En: + M0P_I2C1->CR_f.AA = 1; + break; + case I2cHlm_En: + M0P_I2C1->CR_f.H1M = 1; + break; + case I2cBaud_En: + M0P_I2C1->TMRUN = 0x01; + break; + default: + return ErrorInvalidParameter; + } + } + + enRet = Ok; + return enRet; +} + /** + ****************************************************************************** + ** \brief I2C功能清除相关函数 + ** + ** \param [in] enFunc功能å‚æ•° + ** + ** \retval enRet æˆåŠŸæˆ–失败 + ** + ******************************************************************************/ + en_result_t I2C_ClearFunc(en_i2c_channel_t enCh,en_i2c_func_t enFunc) + { + en_result_t enRet = Error; + if(I2C0 == enCh) + { + switch(enFunc) + { + case I2cMode_En: + M0P_I2C0->CR_f.ENS = 0; + break; + case I2cStart_En: + M0P_I2C0->CR_f.STA = 0; + break; + case I2cStop_En: + M0P_I2C0->CR_f.STO = 0; + break; + case I2cAck_En: + M0P_I2C0->CR_f.AA = 0; + break; + case I2cHlm_En: + M0P_I2C0->CR_f.H1M = 0; + break; + case I2cBaud_En: + M0P_I2C0->TMRUN = 0x00; + break; + default: + return ErrorInvalidParameter; + } + } + else + { + switch(enFunc) + { + case I2cMode_En: + M0P_I2C1->CR_f.ENS = 0; + break; + case I2cStart_En: + M0P_I2C1->CR_f.STA = 0; + break; + case I2cStop_En: + M0P_I2C1->CR_f.STO = 0; + break; + case I2cAck_En: + M0P_I2C1->CR_f.AA = 0; + break; + case I2cHlm_En: + M0P_I2C1->CR_f.H1M = 0; + break; + case I2cBaud_En: + M0P_I2C1->TMRUN = 0x00; + break; + default: + return ErrorInvalidParameter; + } + } + enRet = Ok; + return enRet; + } + /** + ****************************************************************************** + ** \brief I2C获å–中断标记函数 + ** + ** \param æ—  + ** + ** \retval bIrq中断标记 + ** + ******************************************************************************/ +boolean_t I2C_GetIrq(en_i2c_channel_t enCh) +{ + boolean_t bIrq = FALSE; + if(I2C0 == enCh) + { + bIrq = M0P_I2C0->CR_f.SI; + } + else + { + bIrq = M0P_I2C1->CR_f.SI; + } + + return bIrq; +} +/** + ****************************************************************************** + ** \brief I2C清除中断标记函数 + ** + ** \param æ—  + ** + ** \retval bIrq中断标记 + ** + ******************************************************************************/ +en_result_t I2C_ClearIrq(en_i2c_channel_t enCh) +{ + en_result_t enRet = Error; + if(I2C0 == enCh) + { + M0P_I2C0->CR_f.SI = 0; + } + else + { + M0P_I2C1->CR_f.SI = 0; + } + enRet = Ok; + return enRet; +} + /** + ****************************************************************************** + ** \brief I2C获å–ç›¸å…³çŠ¶æ€ + ** + ** \param æ—  + ** + ** \retval I2CçŠ¶æ€ + ** + ******************************************************************************/ +uint8_t I2C_GetState(en_i2c_channel_t enCh) +{ + uint8_t u8State = 0; + if(I2C0 == enCh) + { + u8State = M0P_I2C0->STAT; + } + else + { + u8State = M0P_I2C1->STAT; + } + return u8State; +} +/** + ****************************************************************************** + ** \brief I2C写从机地å€å‡½æ•° + ** + ** \param u8SlaveAddrä»Žæœºåœ°å€ + ** + ** \retval I2C写æˆåŠŸä¸Žå¦çŠ¶æ€ + ** + ******************************************************************************/ + en_result_t I2C_WriteSlaveAddr(en_i2c_channel_t enCh,stc_i2c_addr_t *pstcSlaveAddr) +{ + en_result_t enRet = Error; + if(I2C0 == enCh) + { + M0P_I2C0->ADDR_f.ADR = pstcSlaveAddr->Addr; + M0P_I2C0->ADDR_f.GC = pstcSlaveAddr->Gc; + } + else + { + M0P_I2C1->ADDR_f.ADR = pstcSlaveAddr->Addr; + M0P_I2C1->ADDR_f.GC = pstcSlaveAddr->Gc; + } + + enRet = Ok; + return enRet; +} +/** + ****************************************************************************** + ** \brief 字节写从机函数 + ** + ** \param u8Dataå†™æ•°æ® + ** + ** \retval 写数æ®æ˜¯å¦æˆåŠŸ + ** + ******************************************************************************/ +en_result_t I2C_WriteByte(en_i2c_channel_t enCh,uint8_t u8Data) +{ + en_result_t enRet = Error; + if(I2C0 == enCh) + { + M0P_I2C0->DATA = u8Data; + } + else + { + M0P_I2C1->DATA = u8Data; + } + enRet = Ok; + return enRet; +} +/** + ****************************************************************************** + ** \brief 字节读从机函数 + ** + ** \param æ—  + ** + ** \retval 读å–æ•°æ® + ** + ******************************************************************************/ +uint8_t I2C_ReadByte(en_i2c_channel_t enCh) +{ + uint8_t u8Data = 0; + if(I2C0 == enCh) + { + u8Data = M0P_I2C0->DATA; + } + else + { + u8Data = M0P_I2C1->DATA; + } + return u8Data; +} + /** + ****************************************************************************** + ** \brief 主机å‘é€å‡½æ•° + ** + ** \param u8Addr从机内存地å€ï¼Œpu8Data写数æ®ï¼Œu32Len写数æ®é•¿åº¦ + ** + ** \retval 写数æ®æ˜¯å¦æˆåŠŸ + ** + ******************************************************************************/ +en_result_t I2C_MasterWriteData(en_i2c_channel_t enCh,uint8_t u8DevAddr,uint8_t u8Addr,uint8_t *pu8Data,uint32_t u32Len) +{ + en_result_t enRet = Error; + uint8_t u8i=0,u8State; + + I2C_SetFunc(enCh,I2cStart_En); + while(1) + { + while(0 == I2C_GetIrq(enCh)) + {} + u8State = I2C_GetState(enCh); + switch(u8State) + { + case 0x08: + I2C_ClearFunc(enCh,I2cStart_En); + I2C_WriteByte(enCh,u8DevAddr);//从设备地å€å‘é€ + break; + case 0x18: + I2C_WriteByte(enCh,u8Addr);//从设备内存地å€å‘é€ + break; + case 0x28: + I2C_WriteByte(enCh,pu8Data[u8i++]); + break; + case 0x20: + case 0x38: + I2C_SetFunc(enCh,I2cStart_En); + break; + case 0x30: + I2C_SetFunc(enCh,I2cStop_En); + break; + default: + break; + } + if(u8i>u32Len) + { + I2C_SetFunc(enCh,I2cStop_En);//此顺åºä¸èƒ½è°ƒæ¢ï¼Œå‡ºåœæ­¢æ¡ä»¶ + I2C_ClearIrq(enCh); + break; + } + I2C_ClearIrq(enCh); + } + enRet = Ok; + return enRet; +} + /** + ****************************************************************************** + ** \brief 从机å‘é€å‡½æ•° + ** + ** \param pu8Dataå‘é€æ•°æ®ç¼“存，u32Lenå‘é€æ•°æ®é•¿åº¦ + ** + ** \retval å‘é€æ•°æ®æ˜¯å¦æˆåŠŸ + ** + ******************************************************************************/ + en_result_t I2C_SlaveWriteData(en_i2c_channel_t enCh,uint8_t *pu8Data,uint32_t *u32Len) + { + uint8_t u8i=0,u8State; + // + while(1) + { + + while(0 == I2C_GetIrq(enCh)) + {} + u8State = I2C_GetState(enCh); + switch(u8State) + { + case 0xA8: + case 0xB0: + I2C_WriteByte(enCh,pu8Data[u8i++]); + break; + case 0xB8: + case 0xC8: + I2C_WriteByte(enCh,pu8Data[u8i++]); + break; + case 0xF8: + *u32Len = u8i; + break; + default: + + return ErrorInvalidParameter; + } + I2C_ClearIrq(enCh); + } + } + /** + ****************************************************************************** + ** \brief 从机接收函数 + ** + ** \param pu8Data接收数æ®å­˜æ”¾ç¼“存，u32Len接收数æ®æŒ‡é’ˆ + ** + ** \retval 接收数æ®æ˜¯å¦æˆåŠŸ + ** + ******************************************************************************/ +en_result_t I2C_SlaveReadData(en_i2c_channel_t enCh,uint8_t *pu8Data,uint32_t *pu32Len) +{ + uint8_t u8i=0,u8State; + while(0 == I2C_GetIrq(enCh)) + {} + while(1) + { + while(0 == I2C_GetIrq(enCh)) + {} + u8State = I2C_GetState(enCh); + switch(u8State) + { + case 0x60: + case 0x68: + case 0x70: + case 0x78: + break; + case 0x80: + case 0x90: + pu8Data[u8i++] = I2C_ReadByte(enCh); + break; + case 0xA0: + *pu32Len = u8i; + break; + default: + return ErrorInvalidParameter; + } + I2C_ClearIrq(enCh); + if(0xA0 == u8State) + { + return Ok; + } + } +} + +/** + ****************************************************************************** + ** \brief 主机接收函数 + ** + ** \param u8Addr从机内存地å€ï¼Œpu8Data读数æ®å­˜æ”¾ç¼“存，u32Len读数æ®é•¿åº¦ + ** + ** \retval 读数æ®æ˜¯å¦æˆåŠŸ + ** + ******************************************************************************/ + en_result_t I2C_MasterReadData(en_i2c_channel_t enCh,uint8_t u8DevAddr,uint8_t *pu8Data,uint8_t u8Addr,uint32_t u32Len) +{ + en_result_t enRet = Error; + uint8_t u8i=0,u8State; + + I2C_SetFunc(enCh,I2cStart_En); + + while(1) + { + while(0 == I2C_GetIrq(enCh)) + {} + u8State = I2C_GetState(enCh); + switch(u8State) + { + case 0x08: + I2C_ClearFunc(enCh,I2cStart_En); + I2C_WriteByte(enCh,u8DevAddr); + break; + case 0x18: + I2C_WriteByte(enCh,u8Addr); + break; + case 0x28: + I2C_SetFunc(enCh,I2cStart_En); + break; + case 0x10: + I2C_ClearFunc(enCh,I2cStart_En); + I2C_WriteByte(enCh,u8DevAddr|0x01);//从机地å€å‘é€OK + break; + case 0x40: + if(u32Len>1) + { + I2C_SetFunc(enCh,I2cAck_En); + } + break; + case 0x50: + pu8Data[u8i++] = I2C_ReadByte(enCh); + if(u8i==u32Len-1) + { + I2C_ClearFunc(enCh,I2cAck_En); + } + break; + case 0x58: + pu8Data[u8i++] = I2C_ReadByte(enCh); + I2C_SetFunc(enCh,I2cStop_En); + break; + case 0x38: + I2C_SetFunc(enCh,I2cStart_En); + break; + case 0x48: + I2C_SetFunc(enCh,I2cStop_En); + I2C_SetFunc(enCh,I2cStart_En); + break; + default: + I2C_SetFunc(enCh,I2cStart_En);//其他错误状æ€ï¼Œé‡æ–°å‘é€èµ·å§‹æ¡ä»¶ + break; + } + I2C_ClearIrq(enCh); + if(u8i==u32Len) + { + break; + } + } + enRet = Ok; + return enRet; +} +/** + ****************************************************************************** + ** \brief I2C模å—åˆå§‹åŒ– + ** + ** \param pstcI2CCfgåˆå§‹åŒ–é…置结构体 + ** + ** \retval åˆå§‹åŒ–是å¦æˆåŠŸ + ** + ******************************************************************************/ +en_result_t I2C_Init(en_i2c_channel_t enCh,stc_i2c_config_t *pstcI2CCfg) +{ + en_result_t enRet = Error; + enRet = I2C_SetFunc(enCh,pstcI2CCfg->enFunc); + enRet = I2C_SetBaud(enCh,pstcI2CCfg->u8Tm); + enRet = I2C_WriteSlaveAddr(enCh,&pstcI2CCfg->stcSlaveAddr); + if(pstcI2CCfg->u8Tm<9) + { + I2C_SetFunc(enCh,I2cHlm_En); + } + if(NULL!=pstcI2CCfg->pfnI2c0Cb) + { + pfnI2c0tCallback = pstcI2CCfg->pfnI2c0Cb; + } + if(NULL!=pstcI2CCfg->pfnI2c1Cb) + { + pfnI2c1tCallback = pstcI2CCfg->pfnI2c1Cb; + } + if(TRUE == pstcI2CCfg->bTouchNvic) + { + if(I2C0 == enCh) + { + EnableNvic(I2C0_IRQn,IrqLevel3,TRUE); + } + else + { + EnableNvic(I2C1_IRQn,IrqLevel3,TRUE); + } + } + return enRet; +} +/** + ****************************************************************************** + ** \brief I2C模å—关闭åˆå§‹åŒ– + ** + ** \param æ—  + ** + ** \retval 设置是å¦æˆåŠŸ + ** + ******************************************************************************/ + en_result_t I2C_DeInit(en_i2c_channel_t enCh) + { + en_result_t enRet = Error; + if(I2C0 == enCh) + { + M0P_I2C0->CR = 0x00; + } + else + { + M0P_I2C1->CR = 0x00; + } + enRet = Ok; + return enRet; + } + /** + ****************************************************************************** + ** \brief I2C模å—中断处ç†å‡½æ•° + ** + ** \param u8Param æ— æ„义 + ** + ** \retval æ—  + ** + ******************************************************************************/ +void I2c_IRQHandler(uint8_t u8Param) +{ + if(I2C0 == u8Param) + { + if(NULL != pfnI2c0tCallback) + { + pfnI2c0tCallback(); + } + } + else + { + if(NULL != pfnI2c1tCallback) + { + pfnI2c1tCallback(); + } + } +} + +//@} // I2cGroup diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/interrupts_hc32l136.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/interrupts_hc32l136.c new file mode 100644 index 0000000000..eb95c48ee1 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/interrupts_hc32l136.c @@ -0,0 +1,477 @@ +/****************************************************************************** +* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file interrupts_hc32l136.c + ** + ** Interrupt management + ** @link Driver Group Some description @endlink + ** + ** - 2018-04-15 1.0 Lux First version. + ** + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "ddl.h" +#include "interrupts_hc32l136.h" +__WEAKDEF void Gpio_IRQHandler(uint8_t u8Param); +__WEAKDEF void Dma_IRQHandler(uint8_t u8Param); +__WEAKDEF void Uart_IRQHandler(uint8_t u8Param); +__WEAKDEF void LpUart_IRQHandler(uint8_t u8Param); +__WEAKDEF void Spi_IRQHandler(uint8_t u8Param); +__WEAKDEF void I2c_IRQHandler(uint8_t u8Param); +__WEAKDEF void Tim_IRQHandler(uint8_t u8Param); +__WEAKDEF void Tim3_IRQHandler(uint8_t u8Param); +__WEAKDEF void Adt_IRQHandler(uint8_t u8Param); +__WEAKDEF void LpTim_IRQHandler(uint8_t u8Param); +__WEAKDEF void Pca_IRQHandler(uint8_t u8Param); +__WEAKDEF void Wdt_IRQHandler(uint8_t u8Param); +__WEAKDEF void Vc_IRQHandler(uint8_t u8Param); +__WEAKDEF void Rtc_IRQHandler(uint8_t u8Param); +__WEAKDEF void Adc_IRQHandler(uint8_t u8Param); +__WEAKDEF void Pcnt_IRQHandler(uint8_t u8Param); +__WEAKDEF void Lvd_IRQHandler(uint8_t u8Param); +__WEAKDEF void Lcd_IRQHandler(uint8_t u8Param); +__WEAKDEF void EfRam_IRQHandler(uint8_t u8Param); +__WEAKDEF void ClkTrim_IRQHandler(uint8_t u8Param); + +/** + ******************************************************************************* + ** \brief NVIC 中断使能 + ** + ** \param [in] enIrq 中断å·æžšä¸¾ç±»åž‹ + ** \param [in] enLevel 中断优先级枚举类型 + ** \param [in] bEn 中断开关 + ** \retval Ok 设置æˆåŠŸ + ** 其他值 设置失败 + ******************************************************************************/ +void EnableNvic(IRQn_Type enIrq, en_irq_level_t enLevel, boolean_t bEn) +{ + NVIC_ClearPendingIRQ(enIrq); + NVIC_SetPriority(enIrq, enLevel); + if (TRUE == bEn) + { + NVIC_EnableIRQ(enIrq); + } + else + { + NVIC_DisableIRQ(enIrq); + } +} + +/** + ******************************************************************************* + ** \brief NVIC hardware fault 中断实现 + ** 用于å•æ­¥è°ƒè¯•åŠŸèƒ½ + ** + ** \retval + ******************************************************************************/ +void HardFault_Handler(void) +{ + volatile int a = 0; + + while( 0 == a) + { + ; + } +} + +/** + ******************************************************************************* + ** \brief GPIO PortA 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void PORTA_IRQHandler(void) +{ + Gpio_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief GPIO PortB 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void PORTB_IRQHandler(void) +{ + Gpio_IRQHandler(1); +} + +/** + ******************************************************************************* + ** \brief GPIO PortC 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void PORTC_IRQHandler(void) +{ + Gpio_IRQHandler(2); +} + +/** + ******************************************************************************* + ** \brief GPIO PortD 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void PORTD_IRQHandler(void) +{ + Gpio_IRQHandler(3); +} + +/** + ******************************************************************************* + ** \brief DMAC 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void DMAC_IRQHandler(void) +{ + Dma_IRQHandler(0); +} + + +/** + ******************************************************************************* + ** \brief UART0 串å£0 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void UART0_IRQHandler(void) +{ + Uart_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief UART1 串å£1 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void UART1_IRQHandler(void) +{ + Uart_IRQHandler(1); +} + +/** + ******************************************************************************* + ** \brief LPUART0 低功耗串å£0 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void LPUART0_IRQHandler(void) +{ + LpUart_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief LPUART1 低功耗串å£1 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void LPUART1_IRQHandler(void) +{ + LpUart_IRQHandler(1); +} + +/** + ******************************************************************************* + ** \brief SPI0 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void SPI0_IRQHandler(void) +{ + Spi_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief SPI1 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void SPI1_IRQHandler(void) +{ + Spi_IRQHandler(1); +} + +/** + ******************************************************************************* + ** \brief I2C0 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void I2C0_IRQHandler(void) +{ + I2c_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief I2C1 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void I2C1_IRQHandler(void) +{ + I2c_IRQHandler(1); +} + +/** + ******************************************************************************* + ** \brief TIM0 基础时钟0 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void TIM0_IRQHandler(void) +{ + Tim_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief TIM1 基础时钟1 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void TIM1_IRQHandler(void) +{ + Tim_IRQHandler(1); +} + +/** + ******************************************************************************* + ** \brief TIM2 基础时钟2 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void TIM2_IRQHandler(void) +{ + Tim_IRQHandler(2); +} + +/** + ******************************************************************************* + ** \brief TIM3 基础时钟3 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void TIM3_IRQHandler(void) +{ + Tim3_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief LPTIM 低功耗时钟 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void LPTIM_IRQHandler(void) +{ + LpTim_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief TIM4 高级时钟4 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void TIM4_IRQHandler(void) +{ + Adt_IRQHandler(4); +} + +/** + ******************************************************************************* + ** \brief TIM5 高级时钟5 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void TIM5_IRQHandler(void) +{ + Adt_IRQHandler(5); +} + +/** + ******************************************************************************* + ** \brief TIM6 高级时钟6 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void TIM6_IRQHandler(void) +{ + Adt_IRQHandler(6); +} + +/** + ******************************************************************************* + ** \brief PCA 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void PCA_IRQHandler(void) +{ + Pca_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief WDT 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void WDT_IRQHandler(void) +{ + Wdt_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief RTC 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void RTC_IRQHandler(void) +{ + Rtc_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief ADC 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void ADC_IRQHandler(void) +{ + Adc_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief PCNT 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void PCNT_IRQHandler(void) +{ + Pcnt_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief 电压比较0 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void VC0_IRQHandler(void) +{ + Vc_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief 电压比较1 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void VC1_IRQHandler(void) +{ + Vc_IRQHandler(1); +} + +/** + ******************************************************************************* + ** \brief 低电压检测 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void LVD_IRQHandler(void) +{ + Lvd_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief LCD 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void LCD_IRQHandler(void) +{ + Lcd_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief RAM 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void EF_RAM_IRQHandler(void) +{ + EfRam_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief 时钟校准 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void CLKTRIM_IRQHandler(void) +{ + ClkTrim_IRQHandler(0); +} + + + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/lcd.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/lcd.c new file mode 100644 index 0000000000..65206068d2 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/lcd.c @@ -0,0 +1,579 @@ +/************************************************************************************* +* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file lcd.c + ** + ** WDT function driver API. + ** @link SampleGroup Some description @endlink + ** + ** - 2018-5-3 1.0 CJ First version for Device Driver Library of Module. + ** + ******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "lcd.h" + +/** + ******************************************************************************* + ** \addtogroup I2cGroup + ******************************************************************************/ +//@{ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + en_result_t LCD_SetClkSrc(en_lcd_clk_t enLcdClk) + { + en_result_t enRet = Error; + M0P_LCD->CR1_f.CLKSRC = enLcdClk; + enRet = Ok; + return enRet; + } +/** + ****************************************************************************** + ** \brief LCD Biasæºé€‰æ‹©å‡½æ•° + ** + ** \param [in] enBiasSrcåç½®æºé€‰æ‹© + ** + ** \retval enRet æˆåŠŸæˆ–失败 + ** + ******************************************************************************/ + en_result_t LCD_SelBiasSrc(en_lcd_biassrc_t enBiasSrc) + { + en_result_t enRet = Error; + switch(enBiasSrc) + { + case LcdInRes_High: + case LcdInRes_Low: + case LcdInRes_Mid: + case LcdExtCap: + case LcdExtRes: + M0P_LCD->CR0_f.BSEL = enBiasSrc; + break; + default: + return ErrorInvalidParameter; + } + enRet = Ok; + return enRet; + } +/** + ****************************************************************************** + ** \brief LCD å ç©ºæ¯”选择函数 + ** + ** \param [in] enDutyå ç©ºæ¯” + ** + ** \retval enRet æˆåŠŸæˆ–失败 + ** + ******************************************************************************/ +en_result_t LCD_SetDuty(en_lcd_duty_t enDuty) +{ + en_result_t enRet = Error; + switch(enDuty) + { + case LcdStatic: + case LcdDuty2: + case LcdDuty3: + case LcdDuty4: + case LcdDuty6: + case LcdDuty8: + M0P_LCD->CR0_f.DUTY = enDuty; + break; + default: + return ErrorInvalidParameter; + } + enRet = Ok; + return enRet; +} +/** + ****************************************************************************** + ** \brief LCD bias设置函数 + ** + ** \param [in] enBias　åç½® + ** + ** \retval enRet æˆåŠŸæˆ–失败 + ** + ******************************************************************************/ + en_result_t LCD_SetBias(en_lcd_bias_t enBias) + { + en_result_t enRet = Error; + switch(enBias) + { + case LcdBias3: + case LcdBias2: + M0P_LCD->CR0_f.BIAS = enBias; + break; + default: + return ErrorInvalidParameter; + } + enRet = Ok; + return enRet; + } + /** + ****************************************************************************** + ** \brief LCD 电压泵时钟频率选择函数 + ** + ** \param [in] enCpClk 电压泵频率 + ** + ** \retval enRet æˆåŠŸæˆ–失败 + ** + ******************************************************************************/ +en_result_t LCD_SelCpClk(en_lcd_cpclk_t enCpClk) +{ + en_result_t enRet = Error; + switch(enCpClk) + { + case LcdClk2k: + case LcdClk4k: + case LcdClk8k: + case LcdClk16k: + M0P_LCD->CR0_f.CPCLK = enCpClk; + break; + default: + return ErrorInvalidParameter; + } + enRet = Ok; + return enRet; +} + /** + ****************************************************************************** + ** \brief LCD 扫æ时钟频率选择函数 + ** + ** \param [in] enScanClk 扫æ时钟频率 + ** + ** \retval enRet æˆåŠŸæˆ–失败 + ** + ******************************************************************************/ +en_result_t LCD_SelScanClk(en_lcd_scanclk_t enScanClk) +{ + en_result_t enRet = Error; + switch(enScanClk) + { + case LcdClk64hz: + case LcdClk128hz: + case LcdClk256hz: + case LcdClk512hz: + M0P_LCD->CR0_f.LCDCLK = enScanClk; + break; + default: + return ErrorInvalidParameter; + } + enRet = Ok; + return enRet; +} + /** + ****************************************************************************** + ** \brief LCD 模å—使能或闪å±ä½¿èƒ½ç¦æ­¢å‡½æ•° + ** + ** \param [in] enFunc功能，bFlag使能或ç¦æ­¢ + ** + ** \retval enRet æˆåŠŸæˆ–失败 + ** + ******************************************************************************/ + en_result_t LCD_EnFunc(en_lcd_func_t enFunc,boolean_t bFlag) + { + en_result_t enRet = Error; + switch(enFunc) + { + case LcdEn: + M0P_LCD->CR0_f.EN = bFlag; + break; + case LcdBlinkEn: + M0P_LCD->CR1_f.BLINKEN = bFlag; + break; + default: + return ErrorInvalidParameter; + } + enRet = Ok; + return enRet; + } + /** + ****************************************************************************** + ** \brief LCD 显示模å¼0/1设置 + ** + ** \param [in] enDispModeæ¨¡å¼ + ** + ** \retval enRet æˆåŠŸæˆ–失败 + ** + ******************************************************************************/ + en_result_t LCD_SetDispMode(en_lcd_dispmode_t enDispMode) + { + en_result_t enRet = Error; + switch(enDispMode) + { + case LcdMode0: + case LcdMode1: + M0P_LCD->CR1_f.MODE = enDispMode; + break; + default: + return ErrorInvalidParameter; + } + enRet = Ok; + return enRet; + } + /** + ****************************************************************************** + ** \brief LCD 对比度设置 + ** + ** \param [in] u8Contrast对比度 + ** + ** \retval enRet æˆåŠŸæˆ–失败 + ** + ******************************************************************************/ + en_result_t LCD_SetContrast(uint8_t u8Contrast) + { + en_result_t enRet = Error; + M0P_LCD->CR0_f.CONTRAST = u8Contrast; + enRet = Ok; + return enRet; + } + /** + ****************************************************************************** + ** \brief LCD é—ªå±è®¡æ•°å™¨è®¾ç½® + ** + ** \param [in] u8BlinkCnt计数器 + ** + ** \retval enRet æˆåŠŸæˆ–失败 + ** + ******************************************************************************/ + en_result_t LCD_SetBlinkCnt(uint8_t u8BlinkCnt) + { + en_result_t enRet = Error; + M0P_LCD->CR1_f.BLINKCNT = u8BlinkCnt; + enRet = Ok; + return enRet; + } + /** + ****************************************************************************** + ** \brief LCD 中断标记清除 + ** + ** \param [in] æ—  + ** + ** \retval enRet æˆåŠŸæˆ–失败 + ** + ******************************************************************************/ +en_result_t LCD_ClrIntState(void) +{ + en_result_t enRet = Error; + M0P_LCD->INTCLR_f.INTF = 0; + enRet = Ok; + return enRet; +} + /** + ****************************************************************************** + ** \brief æ ¹æ®LCD显示模å¼èŽ·å–端å£é…ç½® + ** + ** \param [in]enLcdRunMode：显示方å¼ï¼Œ stcSegCom获å–端å£å‚æ•° + ** + ** \retval enRet æˆåŠŸæˆ–失败 + ** + ******************************************************************************/ + en_result_t LCD_GetSegCom(stc_lcd_segcompara_t *pstcSegComPara,stc_lcd_segcom_t *pstcSegCom) +{ + en_result_t enRet = Error; + if(pstcSegComPara->u8MaxSeg>40) + { + return ErrorInvalidParameter; + } + switch(pstcSegComPara->enBiasSrc)//seg32_35 + { + case LcdInRes_High: + case LcdInRes_Low: + case LcdInRes_Mid: + pstcSegCom->bMux = 1; + pstcSegCom->Seg32_39VLcdCom7_4_t.SegVLcdCom = 0xff; + break; + case LcdExtCap: + case LcdExtRes: + //VLCD模拟端å£é…ç½® + if(pstcSegComPara->u8MaxSeg>36) + { + return ErrorInvalidParameter; + } + pstcSegCom->bMux = 0; + pstcSegCom->Seg32_39VLcdCom7_4_t.SegVLcdCom = 0x0f;//seg32_35ç½®0 + break; + default: + return ErrorInvalidParameter; + } + switch(pstcSegComPara->enDuty)//COM0_7 + { + case LcdStatic: + pstcSegCom->u8Com0_3 = 0xfe; + pstcSegCom->Seg32_39VLcdCom7_4_t.SegVLcdCom &= 0xff; + break; + case LcdDuty2: + pstcSegCom->u8Com0_3 = 0xfc;//COMå£é…置，默认按顺åºè¿›è¡Œé…ç½®com0/com1 + pstcSegCom->Seg32_39VLcdCom7_4_t.SegVLcdCom &= 0xff; + break; + case LcdDuty3: + pstcSegCom->u8Com0_3 = 0xf8;//åªå–低4bit + pstcSegCom->Seg32_39VLcdCom7_4_t.SegVLcdCom &= 0xff; + break; + case LcdDuty4: + pstcSegCom->u8Com0_3 = 0xf0;//åªå–低4bit + pstcSegCom->Seg32_39VLcdCom7_4_t.SegVLcdCom &= 0xff; + break; + case LcdDuty6: + if(pstcSegComPara->u8MaxSeg>38) + { + return ErrorInvalidParameter; + } + pstcSegCom->u8Com0_3 = 0xf0;//åªå–低4bit + pstcSegCom->Seg32_39VLcdCom7_4_t.SegVLcdCom &= 0xfc; + break; + case LcdDuty8: + if(pstcSegComPara->u8MaxSeg>36) + { + return ErrorInvalidParameter; + } + pstcSegCom->u8Com0_3 = 0xf0;//åªå–低4bit + pstcSegCom->Seg32_39VLcdCom7_4_t.SegVLcdCom &= 0xf0; + break; + default: + return ErrorInvalidParameter; + } + return enRet; +} + /** + ****************************************************************************** + ** \brief LCD COMSEG端å£é…ç½® + ** + ** \param [in] pstcSegCom端å£é…置结构体 + ** + ** \retval enRet æˆåŠŸæˆ–失败 + ** + ******************************************************************************/ + en_result_t LCD_SetSegCom(stc_lcd_segcom_t *pstcSegCom) + { + en_result_t enRet = Error; + M0P_LCD->POEN0 = pstcSegCom->u32Seg0_31; + M0P_LCD->POEN1 = (uint32_t)(pstcSegCom->Seg32_39VLcdCom7_4_t.SegVLcdCom); + M0P_LCD->POEN1_f.MUX = pstcSegCom->bMux; + M0P_LCD->POEN1_f.C0 = pstcSegCom->u8Com0_3&0x01; + M0P_LCD->POEN1_f.C1 = pstcSegCom->u8Com0_3&0x02; + M0P_LCD->POEN1_f.C2 = pstcSegCom->u8Com0_3&0x04; + M0P_LCD->POEN1_f.C3 = pstcSegCom->u8Com0_3&0x08; + enRet = Ok; + return enRet; + } + /** + ****************************************************************************** + ** \brief 液晶全显 + ** + ** \param [in] æ—  + ** + ** \retval enRet æˆåŠŸæˆ–失败 + ** + ******************************************************************************/ + en_result_t LCD_FullDisp(void) + { + en_result_t enRet=Error; + uint8_t i; + uint32_t volatile *p = NULL; + p = &M0P_LCD->RAM0; + for(i=0;i<8;i++) + { + *p = 0xffffffffu; + p++; + } + for(i=0;i<8;i++) + { + *p = 0xffu; + p++; + } + enRet = Ok; + return enRet; + } + /** + ****************************************************************************** + ** \brief 液晶全清 + ** + ** \param [in] æ—  + ** + ** \retval enRet æˆåŠŸæˆ–失败 + ** + ******************************************************************************/ + en_result_t LCD_ClearDisp(void) +{ + en_result_t enRet=Error; + uint8_t i; + uint32_t volatile *p = NULL; + p = &M0P_LCD->RAM0; + for(i=0;i<16;i++) + { + *p = 0x00; + p++; + } + enRet = Ok; + return enRet; +} + /** + ****************************************************************************** + ** \brief LCD RAM bit设置函数 + ** + ** \param [in] u16Row RAM地å€ç´¢å¼•ï¼Œu32List bitä½ç´¢å¼•ï¼ŒbData写入0或1 + ** + ** \retval enRet æˆåŠŸæˆ–失败 + ** + ******************************************************************************/ + en_result_t LCD_WriteRam(uint16_t u16Row, uint32_t u32List, boolean_t bData) + { + en_result_t enRet = Error; + uint8_t RamListSize = 0; + volatile uint32_t *ptemp = NULL; + ptemp = (volatile uint32_t*)&M0P_LCD->RAM0; + if(u16Row>=8) + { + RamListSize = LCDRAM8_FSIZE; + } + else + { + RamListSize = LCDRAM0_7SIZE; + } + if ((u16Row > LCDRAMSIZE) || (u32List > RamListSize)) + { + enRet = ErrorInvalidParameter; + return enRet; + } + + ptemp += u16Row; + + if (bData == TRUE) + { + *ptemp |= (uint32_t)(1 << u32List); + } + else + { + *ptemp &= (uint32_t)(0 << u32List); + } + enRet = Ok; + return enRet; + } +/** + ****************************************************************************** + ** \brief LCD RAM 0-7寄存器设置函数 + ** + ** \param [in] u8Row RAM地å€ç´¢å¼•ï¼Œu32Data写入寄存器数值 + ** + ** \retval enRet æˆåŠŸæˆ–失败 + ** + ******************************************************************************/ +en_result_t LCD_WriteRam0_7Int32(uint8_t u8Row,uint32_t u32Data) +{ + en_result_t enRet = Error; + volatile uint32_t *ptemp = NULL; + ptemp = (volatile uint32_t*)&M0P_LCD->RAM0; + + if (u8Row > LCDRAMSIZE) + { + enRet = ErrorInvalidParameter; + return enRet; + } + + ptemp += u8Row; + *ptemp = u32Data; + enRet = Ok; + return enRet; +} +/** + ****************************************************************************** + ** \brief LCD RAM 8-f寄存器设置函数 + ** + ** \param [in] u8Row RAM地å€ç´¢å¼•ï¼Œu8Data写入寄存器数值 + ** + ** \retval enRet æˆåŠŸæˆ–失败 + ** + ******************************************************************************/ +en_result_t LCD_WriteRam8_FInt8(uint8_t u8Row,uint8_t u8Data) +{ + en_result_t enRet = Error; + volatile uint32_t *ptemp = NULL; + ptemp = (volatile uint32_t*)&M0P_LCD->RAM0; + + if (u8Row > LCDRAMSIZE) + { + enRet = ErrorInvalidParameter; + return enRet; + } + + ptemp += u8Row; + *ptemp = u8Data; + enRet = Ok; + return enRet; +} +/** + ****************************************************************************** + ** \brief LCD模å—åˆå§‹åŒ–函数 + ** + ** \param [in] stcLcdCfgé…置结构体 + ** + ** \retval enRet æˆåŠŸæˆ–失败 + ** + ******************************************************************************/ + en_result_t LCD_Init(stc_lcd_config_t *pstcLcdCfg) + { + en_result_t enRet = Error; + enRet = LCD_SelBiasSrc(pstcLcdCfg->enBiasSrc); + enRet = LCD_SetDuty(pstcLcdCfg->enDuty); + enRet = LCD_SetBias(pstcLcdCfg->enBias); + enRet = LCD_SelCpClk(pstcLcdCfg->enCpClk); + enRet = LCD_SelScanClk(pstcLcdCfg->enScanClk); + enRet = LCD_SetDispMode(pstcLcdCfg->enDispMode); + enRet = LCD_SetClkSrc(pstcLcdCfg->enClk); + if(Ok!=enRet) + { + return ErrorInvalidParameter; + } + if(pstcLcdCfg->bTouchNvic) + { + M0P_LCD->CR1_f.IE = 1; + EnableNvic(LCD_IRQn,IrqLevel3,TRUE); + } + else + { + EnableNvic(LCD_IRQn,IrqLevel3,FALSE); + } + return Ok; + } +//@} // LCDGroup diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/lpm.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/lpm.c new file mode 100644 index 0000000000..dbba75a8e3 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/lpm.c @@ -0,0 +1,134 @@ +/****************************************************************************** +*Copyright(C)2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file lpm.c + ** + ** Common API of lpm. + ** @link LpmGroup Some description @endlink + ** + ** - 2017-06-06 + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "lpm.h" +/** + ******************************************************************************* + ** \addtogroup LpmGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +#define IS_VALID_SEVONPEND(x) (SevPndDisable == (x) ||\ + SevPndEnable == (x)) +#define IS_VALID_SLEEPDEEP(x) (SlpDpDisable == (x) ||\ + SlpDpEnable == (x)) +#define IS_VALID_SLEEPONEXIT(x) (SlpExtDisable == (x) ||\ + SlpExtEnable == (x)) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ***************************************************************************** + ** \brief 低功耗模å¼é…ç½® + ** + ** + ** \param [in] pstcConfig 低功耗模å¼é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Lpm_Config(stc_lpm_config_t* pstcConfig) +{ + en_result_t enResult = Error; + + ASSERT(IS_VALID_SEVONPEND(pstcConfig->enSEVONPEND)); + ASSERT(IS_VALID_SLEEPDEEP(pstcConfig->enSLEEPDEEP)); + ASSERT(IS_VALID_SLEEPONEXIT(pstcConfig->enSLEEPONEXIT)); + + SCB->SCR = pstcConfig->enSEVONPEND ? (SCB->SCR | SCB_SCR_SEVONPEND_Msk) : (SCB->SCR & ~SCB_SCR_SEVONPEND_Msk); + SCB->SCR = pstcConfig->enSLEEPDEEP ? (SCB->SCR | SCB_SCR_SLEEPDEEP_Msk) : (SCB->SCR & ~SCB_SCR_SLEEPDEEP_Msk); + SCB->SCR = pstcConfig->enSLEEPONEXIT ? (SCB->SCR | SCB_SCR_SLEEPONEXIT_Msk) : (SCB->SCR & ~SCB_SCR_SLEEPONEXIT_Msk); + + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief 进入ç¡çœ æ¨¡å¼ + ** + ** + ** + ** \retval NULL + *****************************************************************************/ +void Lpm_GotoLpmMode(void) +{ + __WFI(); +} + +//@} // LpmGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/lpt.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/lpt.c new file mode 100644 index 0000000000..dcefd2e5e3 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/lpt.c @@ -0,0 +1,289 @@ +/****************************************************************************** +*Copyright(C)2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file lpt.c + ** + ** Common API of Low Power timer. + ** @link lptGroup Some description @endlink + ** + ** - 2018-04-16 Husj First version + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "lpt.h" +/** + ******************************************************************************* + ** \addtogroup LptGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static func_ptr_t pfnLpTimCallback = NULL; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ***************************************************************************** + ** \brief Low Power Timer ä¸­æ–­æ ‡å¿—èŽ·å– + ** + ** + ** + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +boolean_t Lpt_GetIntFlag(void) +{ + boolean_t bRetVal = FALSE; + + bRetVal = M0P_LPTIMER->IFR_f.TF ? TRUE : FALSE; + + return bRetVal; +} + +/** + ***************************************************************************** + ** \brief Low Power Timer 中断标志清除 + ** + ** + ** + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Lpt_ClearIntFlag(void) +{ + en_result_t enResult = Error; + + M0P_LPTIMER->ICLR_f.TFC = FALSE; + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Low Power Timer 中断æœåŠ¡å‡½æ•° + ** + ** + ** \param [in] u8Param == 0 + ** + *****************************************************************************/ +void LpTim_IRQHandler(uint8_t u8Param) +{ + if(NULL != pfnLpTimCallback) + { + pfnLpTimCallback(); + } +} + +/** + ***************************************************************************** + ** \brief Low Power Timer 中断使能 + ** + ** + ** + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Lpt_EnableIrq (void) +{ + en_result_t enResult = Error; + + M0P_LPTIMER->CR_f.IE = TRUE; + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Low Power Timer 中断ç¦æ­¢ + ** + ** + ** + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Lpt_DisableIrq(void) +{ + en_result_t enResult = Error; + + M0P_LPTIMER->CR_f.IE = FALSE; + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Low Power Timer åˆå§‹åŒ–é…ç½® + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Lpt_Init(stc_lpt_config_t* pstcConfig) +{ + en_result_t enResult = Error; + + M0P_LPTIMER->CR_f.GATE_P = pstcConfig->enGateP; + M0P_LPTIMER->CR_f.GATE = pstcConfig->enGate; + M0P_LPTIMER->CR_f.TCK_SEL = pstcConfig->enTckSel; + M0P_LPTIMER->CR_f.TOG_EN = pstcConfig->enTog; + M0P_LPTIMER->CR_f.CT = pstcConfig->enCT; + M0P_LPTIMER->CR_f.MD = pstcConfig->enMD; + + pfnLpTimCallback = pstcConfig->pfnLpTimCb; + + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Low Power Timer å¯åŠ¨è¿è¡Œ + ** + ** + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Lpt_Run(void) +{ + en_result_t enResult = Error; + + M0P_LPTIMER->CR_f.TR = TRUE; + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Low Power Timer åœæ­¢è¿è¡Œ + ** + ** + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Lpt_Stop(void) +{ + en_result_t enResult = Error; + + M0P_LPTIMER->CR_f.TR = FALSE; + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Low Power Timer é‡è½½å€¼è®¾ç½® + ** + ** + ** \param [in] u16Data 16bitsé‡è½½å€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Lpt_ARRSet(uint16_t u16Data) +{ + en_result_t enResult = Error; + boolean_t bRetVal = FALSE; + + bRetVal = M0P_LPTIMER->CR_f.WT_FLAG ? TRUE : FALSE; + if(TRUE == bRetVal) + { + M0P_LPTIMER->ARR_f.ARR = u16Data; + enResult = Ok; + } + else + { + enResult = Error; + } + return enResult; +} + +/** + ***************************************************************************** + ** \brief Low Power Timer 16ä½è®¡æ•°å€¼èŽ·å– + ** + ** + ** + ** \retval 16bits计数值 + *****************************************************************************/ +uint16_t Lpt_Cnt16Get(void) +{ + uint16_t u16CntData = 0; + + u16CntData = M0P_LPTIMER->CNT_f.CNT; + + return u16CntData; +} + +//@} // LptGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/lpuart.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/lpuart.c new file mode 100644 index 0000000000..986b7377b4 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/lpuart.c @@ -0,0 +1,966 @@ +/************************************************************************************* +* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file lpuart.c + ** + ** LPUART function driver API. + ** @link SampleGroup Some description @endlink + ** + ** - 2017-05-17 1.0 CJ First version for Device Driver Library of Module. + ** + ******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "lpuart.h" +/** + ****************************************************************************** + ** \addtogroup LPUartGroup + ******************************************************************************/ +//@{ +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +#define IS_VALID_CH(x) ((LPUART0 == (x)) ||\ + (LPUART1 == (x))) + +#define IS_VALID_CLK(x) ((LPUart_Pclk==(x))||\ + (LPUart_Pclk_1==(x))||\ + (LPUart_Xtl==(x))||\ + (LPUart_Rcl==(x))) + +#define IS_VALID_IRQSEL(x) ((LPUartTxIrq == (x)) ||\ + (LPUartRxIrq == (x)) ||\ + (LPUartFEIrq == (x)) ||\ + (LPUartCtsIrq == (x))||\ + (LPUartPEIrq == (x)) ||\ + (LPUartTxEIrq == (x))) + +#define IS_VALID_MODE(x) ((LPUartMode0==(x))||\ + (LPUartMode1==(x))||\ + (LPUartMode2==(x))||\ + (LPUartMode3==(x))) + +#define IS_VALID_STATUS(x) ((LPUartCts == (x))||\ + (LPUartRC == (x))||\ + (LPUartTC == (x))||\ + (LPUartPE == (x))||\ + (LPUartCtsIf == (x))||\ + (LPUartTxe == (x))||\ + (LPUartFE == (x))) +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ +static stc_lpuart_instance_data_t* LPUartGetInternDataPtr(uint8_t u8Idx); +static void LPUartInitNvic(uint8_t u8Idx); +static void LPUartDeInitNvic(uint8_t u8Idx); +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ +static stc_lpuart_instance_data_t m_astcLPUartInstanceDataLut[] = +{ + { + LPUART0, + M0P_LPUART0, /* pstcInstance */ + {NULL,NULL,NULL,NULL,NULL}, + }, + { + LPUART1, + M0P_LPUART1, /* pstcInstance */ + {NULL,NULL,NULL,NULL,NULL}, + }, +}; +/** + ****************************************************************************** + ** \brief LPUART0/1é€šé“ ç›¸å…³åœ°å€èŽ·å– + ** + ** \param [in] u8Idx通é“å· + ** + ** \retval 通é“对应的地å€ç»“æž„ + ** + ******************************************************************************/ +static stc_lpuart_instance_data_t* LPUartGetInternDataPtr(uint8_t u8Idx) +{ + stc_lpuart_instance_data_t* pstcData = NULL; + uint8_t u8i = 0; + for (u8i = 0; u8i < ARRAY_SZ(m_astcLPUartInstanceDataLut); u8i++) + { + if (u8Idx == m_astcLPUartInstanceDataLut[u8i].u32Idx) + { + pstcData = &m_astcLPUartInstanceDataLut[u8i]; + break; + } + } + + return (pstcData); +} +/** + ****************************************************************************** + ** \brief LPUART通信中断使能函数设置 + ** + ** \param [in] u8Idx通é“å·ï¼ŒenIrqSelå‘é€or接收中断使能 + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t LPUart_EnableIrq(uint8_t u8Idx, + en_lpuart_irq_sel_t enIrqSel) +{ + stc_lpuart_instance_data_t* pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + ASSERT(IS_VALID_IRQSEL(enIrqSel)); + pstcData = LPUartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + switch(enIrqSel) + { + case LPUartTxIrq: + pstcData->pstcInstance->SCON_f.TCIE = 1u; + break; + case LPUartRxIrq: + pstcData->pstcInstance->SCON_f.RCIE = 1u; + break; + case LPUartFEIrq: + pstcData->pstcInstance->SCON_f.FEIE = 1u; + break; + case LPUartCtsIrq: + pstcData->pstcInstance->SCON_f.CTSIE = 1u; + break; + case LPUartPEIrq: + pstcData->pstcInstance->SCON_f.PEIE = 1u; + break; + case LPUartTxEIrq: + pstcData->pstcInstance->SCON_f.TXEIE = 1u; + break; + default: + return (ErrorInvalidParameter); + } + return Ok; +} +/** + ****************************************************************************** + ** \brief LPUART通信中断ç¦æ­¢å‡½æ•°è®¾ç½® + ** + ** \param [in] u8Idx通é“å·ï¼ŒenIrqSelå‘é€or接收中断ç¦æ­¢ + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t LPUart_DisableIrq(uint8_t u8Idx, + en_lpuart_irq_sel_t enIrqSel) +{ + stc_lpuart_instance_data_t *pstcData = NULL; + + ASSERT(IS_VALID_CH(u8Idx)); + ASSERT(IS_VALID_IRQSEL(enIrqSel)); + + pstcData = LPUartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + switch(enIrqSel) + { + case LPUartTxIrq: + pstcData->pstcInstance->SCON_f.TCIE = 0u; + break; + case LPUartRxIrq: + pstcData->pstcInstance->SCON_f.RCIE = 0u; + break; + case LPUartFEIrq: + pstcData->pstcInstance->SCON_f.FEIE = 0u; + break; + case LPUartCtsIrq: + pstcData->pstcInstance->SCON_f.CTSIE = 0u; + break; + case LPUartPEIrq: + pstcData->pstcInstance->SCON_f.PEIE = 0u; + break; + case LPUartTxEIrq: + pstcData->pstcInstance->SCON_f.TXEIE = 0u; + break; + default: + return (ErrorInvalidParameter); + } + + return Ok; +} +/** + ****************************************************************************** + ** \brief lpuart通信时钟æºé€‰æ‹© + ** + ** \param [in] u8Idx通é“å·ï¼ŒenClk 时钟æºé€‰é¡¹ + ** + ** \retval Ok 设置æˆåŠŸ + **\retval ErrorInvalidParameter设置失败 + ******************************************************************************/ +en_result_t LPUart_SelSclk(uint8_t u8Idx,en_lpuart_sclksel_t enClk) +{ + stc_lpuart_instance_data_t *pstcData = NULL; + pstcData = LPUartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + ASSERT(IS_VALID_CH(u8Idx)); + ASSERT(IS_VALID_CLK(enClk)); + switch(enClk) + { + case LPUart_Pclk: + case LPUart_Pclk_1: + case LPUart_Xtl: + case LPUart_Rcl: + pstcData->pstcInstance->SCON_f.SCLKSEL = enClk; + break; + default: + return (ErrorInvalidParameter); + } + return Ok; +} +/** + ****************************************************************************** + ** \brief lpuart通信时钟æºé€‰æ‹© + ** + ** \param [in] u8Idx通é“å· + ** + ** \retval Ok 设置æˆåŠŸ + **\retval + ******************************************************************************/ +uint32_t LPUart_GetSclk(uint8_t u8Idx) +{ + stc_lpuart_instance_data_t *pstcData = NULL; + uint8_t u8Sclksrc; + uint32_t u32Sclk; + pstcData = LPUartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + ASSERT(IS_VALID_CH(u8Idx)); + u8Sclksrc = pstcData->pstcInstance->SCON_f.SCLKSEL; + switch(u8Sclksrc) + { + case 0x00: + case 0x01: + u32Sclk = Sysctrl_GetPClkFreq(); + break; + case 0x02: + u32Sclk = 32768; + break; + case 0x03: + u32Sclk = 38400;//此处必须使能内部38.4k + break; + default: + return 0; + } + return u32Sclk; +} +/** + ****************************************************************************** + ** \brief LPUART通é“4ç§æ¨¡å¼é…ç½® + ** + ** \param [in] u8Idx通é“å·ï¼Œmode哪ç§æ¨¡å¼ + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t LPUart_SetMode(uint8_t u8Idx,en_lpuart_mode_t enMode) +{ + stc_lpuart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + ASSERT(IS_VALID_MODE(enMode)); + pstcData = LPUartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + pstcData->pstcInstance->SCON_f.SM = enMode; + return Ok; +} +/** + ****************************************************************************** + ** \brief LPUART通é“多主机模å¼é…ç½® + ** + ** \param [in] u8Idx通é“å·ï¼ŒstcMultiConfig多主机模å¼ç»“æž„ + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t LPUart_SetMultiMode(uint8_t u8Idx,stc_lpuart_multimode_t* pstcMultiConfig) +{ + stc_lpuart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = LPUartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + if(NULL != pstcMultiConfig) + { + pstcData->pstcInstance->SCON_f.ADRDET = pstcMultiConfig->enMulti_mode; + if(pstcMultiConfig->enMulti_mode == LPUartMulti) + { + pstcData->pstcInstance->SADDR = pstcMultiConfig->u8SlaveAddr; + pstcData->pstcInstance->SADEN = pstcMultiConfig->u8SaddEn; + } + } + return Ok; +} +/** + ****************************************************************************** + ** \brief LPUART通é“多主机模å¼å‘é€æ•°æ®/地å€å¸§æˆ–者奇å¶æ ¡éªŒé…ç½®TB8 + ** + ** \param [in] u8Idx通é“å·ï¼Œtb8æ•°æ®or地å€å¸§æˆ–者奇å¶æ ¡éªŒ + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t LPUart_SetMMDOrCk(uint8_t u8Idx,en_lpuart_mmdorck_t enTb8) +{ + stc_lpuart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = LPUartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + pstcData->pstcInstance->SCON_f.B8CONT = enTb8; + return Ok; +} +/** + ****************************************************************************** + ** \brief 获å–RB8数值 + ** + ** \param [in] u8Idx通é“å· + ** + ** \retval RB8 + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +boolean_t LPUart_GetRb8(uint8_t u8Idx) +{ + stc_lpuart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = LPUartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + return ((pstcData->pstcInstance->SBUF>>8)&0x01); +} +/** + ****************************************************************************** + ** \brief LPUART通é“多主机模å¼ä»Žæœºåœ°å€é…置函数 + ** + ** \param [in] u8Idx通é“å·ï¼Œaddråœ°å€ + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t LPUart_SetSaddr(uint8_t u8Idx,uint8_t u8Addr) +{ + stc_lpuart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = LPUartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + pstcData->pstcInstance->SADDR = u8Addr; + return Ok; +} +/** + ****************************************************************************** + ** \brief LPUART通é“多主机模å¼ä»ŽæœºæŽ©ç é…置函数 + ** + ** \param [in] u8Idx通é“å·ï¼Œaddren地å€æŽ©ç  + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t LPUart_SetSaddrEn(uint8_t u8Idx,uint8_t u8Addren) +{ + stc_lpuart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = LPUartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + pstcData->pstcInstance->SADEN = u8Addren; + return Ok; +} +/** + ****************************************************************************** + ** \brief LPUART通é“åœæ­¢ä½é•¿åº¦è®¾ç½® + ** + ** \param [in] u8Idx通é“å·ï¼Œu8Lenåœæ­¢ä½é•¿åº¦ + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t LPUart_SetStopBit(uint8_t u8Idx,uint8_t u8Len) +{ + stc_lpuart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = LPUartGetInternDataPtr(u8Idx); + switch(u8Len) + { + case LPUart1bit: + case LPUart15bit: + case LPUart2bit: + pstcData->pstcInstance->SCON_f.STOPBIT = u8Len; + break; + default: + return ErrorInvalidParameter; + } + return Ok; +} +/** + ****************************************************************************** + ** \brief LPUART采样频率é…ç½® + ** + ** \param [in] u8Idx通é“å·ï¼Œu8Div采样频率 + ** + ** \retval OKé…ç½®æˆåŠŸ + ******************************************************************************/ +en_result_t LPUart_SetClkDiv(uint8_t u8Idx,en_lpuart_clkdiv_t enClkDiv) +{ + stc_lpuart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = LPUartGetInternDataPtr(u8Idx); + pstcData->pstcInstance->SCON_f.OVER = enClkDiv; + return Ok; +} +/** + ****************************************************************************** + ** \brief LPUART波特率计算值 + ** + ** \param [in] u8Idx通é“å·ï¼ŒstcBaud计算波特率值å‚æ•° + ** + ** \retval SCNT计算值 + ******************************************************************************/ +uint16_t LPUart_CalScnt(uint8_t u8Idx,stc_lpuart_baud_t *pstcBaud) +{ + stc_lpuart_instance_data_t *pstcData = NULL; + uint16_t u16Scnt = 0; + uint8_t u8Over = 0; + ASSERT(IS_VALID_CH(u8Idx)); + + pstcData = LPUartGetInternDataPtr(u8Idx); + u8Over = pstcData->pstcInstance->SCON_f.OVER; + if(u8Over == 3) + { + return 0;//test + } + if(LPUartMode0 == pstcBaud->enRunMode) + { + return 0;//test + } + if((LPUartMode1 == pstcBaud->enRunMode)||(LPUartMode3 == pstcBaud->enRunMode)) + { + u8Over = 1<<(4-u8Over); + u16Scnt = pstcBaud->u32Sclk/(pstcBaud->u32Baud*u8Over); + } + else + { + u8Over = 1<<(5-u8Over); + u16Scnt = pstcBaud->u32Sclk/u8Over; + } + return u16Scnt; +} +/** + ****************************************************************************** + ** \brief LPUART通é“波特率é…ç½® + ** + ** \param [in] u8Idx通é“å·ï¼Œu32pclk时钟æºï¼ŒstcBaud波特率é…置结构 + ** + ** \retval 定时器é…置值 + ** \retval 0,获å–值失败 + ******************************************************************************/ +en_result_t LPUart_SetBaud(uint8_t u8Idx,uint16_t u16Scnt) +{ + stc_lpuart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = LPUartGetInternDataPtr(u8Idx); + pstcData->pstcInstance->SCNT = u16Scnt; + return Ok; +} +/** + ****************************************************************************** + ** \brief LPUART通é“æ³¢ç‰¹çŽ‡èŽ·å– + ** + ** \param [in] u8Idx通é“å·,u8Modeå·¥ä½œæ¨¡å¼ + ** + ** \retval 波特率 + ******************************************************************************/ +uint32_t LPUart_GetBaud(uint8_t u8Idx,uint8_t u8Mode,uint32_t u32Pclk) +{ + stc_lpuart_instance_data_t *pstcData = NULL; + uint32_t u32Baud = 0; + uint8_t u8Over = 0; + uint16_t u16Scnt = 0; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = LPUartGetInternDataPtr(u8Idx); + u8Over = pstcData->pstcInstance->SCON_f.OVER; + switch(u8Mode) + { + case LPUartMode0: + u32Baud = u32Pclk/12; + break; + case LPUartMode1: + case LPUartMode3: + u16Scnt = pstcData->pstcInstance->SCNT; + u8Over = 1<<(4-u8Over); + u32Baud = u32Pclk/(u8Over*u16Scnt); + break; + case LPUartMode2: + u8Over = 1<<(5-u8Over); + u32Baud = u32Pclk/u8Over; + break; + default: + return 0;//test + } + return u32Baud; +} +/** + ****************************************************************************** + ** \brief LPUART通é“å‘é€æˆ–接收等功能使能设置 + ** + ** \param [in] u8Idx通é“å·ï¼ŒenFunc功能 + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t LPUart_EnableFunc(uint8_t u8Idx, en_lpuart_func_t enFunc) +{ + stc_lpuart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = LPUartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + switch(enFunc) + { + case LPUartTx: + case LPUartRx: + pstcData->pstcInstance->SCON_f.REN = 1u; + break; + case LPUartDmaTx: + pstcData->pstcInstance->SCON_f.DMATXEN = 1u; + break; + case LPUartDmaRx: + pstcData->pstcInstance->SCON_f.DMARXEN = 1u; + break; + case LPUartCtsRts: + pstcData->pstcInstance->SCON_f.CTSEN = 1u; + pstcData->pstcInstance->SCON_f.RTSEN = 1u; + break; + default: + return ErrorInvalidParameter; + } + return Ok; +} +/** + ****************************************************************************** + ** \brief LPUART通é“å‘é€æˆ–接收等功能ç¦æ­¢è®¾ç½® + ** + ** \param [in] u8Idx通é“å·ï¼ŒenFunc功能 + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t LPUart_DisableFunc(uint8_t u8Idx, en_lpuart_func_t enFunc) +{ + stc_lpuart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = LPUartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + switch(enFunc) + { + case LPUartTx: + case LPUartRx: + pstcData->pstcInstance->SCON_f.REN = 0u; + break; + case LPUartDmaTx: + pstcData->pstcInstance->SCON_f.DMATXEN = 0u; + break; + case LPUartDmaRx: + pstcData->pstcInstance->SCON_f.DMARXEN = 0u; + break; + case LPUartCtsRts: + pstcData->pstcInstance->SCON_f.CTSEN = 0u; + pstcData->pstcInstance->SCON_f.RTSEN = 0u; + break; + default: + return ErrorInvalidParameter; + } + return Ok; +} +/** + ****************************************************************************** + ** \brief LPUART通é“通信状æ€èŽ·å– + ** + ** \param [in] u8Idx通é“å· + ** + ** \retval 状æ€å€¼isr + ******************************************************************************/ +uint8_t LPUart_GetIsr(uint8_t u8Idx) +{ + stc_lpuart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = LPUartGetInternDataPtr(u8Idx); + return(pstcData->pstcInstance->ISR); +} +/** + ****************************************************************************** + ** \brief LPUART通é“通信状æ€å…¨éƒ¨æ¸…除 + ** + ** \param [in] u8Idx通é“å· + ** + **\retval Ok + ******************************************************************************/ +en_result_t LPUart_ClrIsr(uint8_t u8Idx) +{ + en_result_t enRet = Error; + stc_lpuart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = LPUartGetInternDataPtr(u8Idx); + pstcData->pstcInstance->ICR = 0; + enRet = Ok; + return enRet; +} +/** + ****************************************************************************** + ** \brief LPUART通é“通信状æ€èŽ·å– + ** + ** \param [in] u8Idx通é“å·ï¼ŒenStatus获å–å“ªä¸ªçŠ¶æ€ + ** + ** \retval 状æ€å€¼ + **\retval ErrorInvalidParameter获å–失败 + ******************************************************************************/ +boolean_t LPUart_GetStatus(uint8_t u8Idx,en_lpuart_status_t enStatus) +{ + boolean_t bStatus=FALSE; + stc_lpuart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + ASSERT(IS_VALID_STATUS(enStatus)); + pstcData = LPUartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter;//4，用户åªéœ€åˆ¤æ–­0或1 + } + switch(enStatus) + { + case LPUartCts: + bStatus = (pstcData->pstcInstance->ISR_f.CTS == 1) ? TRUE : FALSE; + break; + case LPUartRC: + bStatus = (pstcData->pstcInstance->ISR_f.RC == 1) ? TRUE : FALSE; + break; + case LPUartTC: + bStatus = (pstcData->pstcInstance->ISR_f.TC == 1) ? TRUE : FALSE; + break; + case LPUartPE: + bStatus = (pstcData->pstcInstance->ISR_f.PE == 1) ? TRUE : FALSE; + break; + case LPUartFE: + bStatus = (pstcData->pstcInstance->ISR_f.FE == 1) ? TRUE : FALSE; + break; + case LPUartCtsIf: + bStatus = (pstcData->pstcInstance->ISR_f.CTSIF == 1) ? TRUE : FALSE; + break; + case LPUartTxe: + bStatus = (pstcData->pstcInstance->ISR_f.TXE == 1) ? TRUE : FALSE; + break; + default: + break; + } + return bStatus; +} +/** + ****************************************************************************** + ** \brief LPUART通é“通信状æ€æ¸…除 + ** + ** \param [in] u8Idx通é“å·ï¼ŒenStatusæ¸…é™¤å“ªä¸ªçŠ¶æ€ + ** + ** \retval 状æ€å€¼ + **\retval ErrorInvalidParameter清除失败 + ******************************************************************************/ +en_result_t LPUart_ClrStatus(uint8_t u8Idx,en_lpuart_status_t enStatus) +{ + stc_lpuart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + ASSERT(IS_VALID_STATUS(enStatus)); + pstcData = LPUartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + switch(enStatus) + { + case LPUartCts: + pstcData->pstcInstance->ICR_f.CTSIFCF = 0; + break; + case LPUartRC: + pstcData->pstcInstance->ICR_f.RCCF = 0; + break; + case LPUartTC: + pstcData->pstcInstance->ICR_f.TCCF = 0; + break; + case LPUartPE: + pstcData->pstcInstance->ICR_f.PECF = 0; + break; + case LPUartFE: + pstcData->pstcInstance->ICR_f.FECF = 0; + break; + default: + break; + } + return Ok; +} +/** + ****************************************************************************** + ** \brief LPUART通é“å‘é€æ•°æ®å‡½æ•°,查询方å¼è°ƒç”¨æ­¤å‡½æ•°ï¼Œä¸­æ–­æ–¹å¼å‘é€ä¸é€‚用 + ** + ** \param [in] u8Idx通é“å·ï¼ŒDataå‘é€æ•°æ® + ** + ** \retval Okå‘é€æˆåŠŸ + **\retval ErrorInvalidParameterå‘é€å¤±è´¥ + ******************************************************************************/ +en_result_t LPUart_SendData(uint8_t u8Idx, uint8_t u8Data) +{ + stc_lpuart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = LPUartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + LPUart_ClrStatus(u8Idx,LPUartTC); + pstcData->pstcInstance->SBUF_f.DATA = u8Data; + while(FALSE == LPUart_GetStatus(u8Idx,LPUartTC)) + {} + LPUart_ClrStatus(u8Idx,LPUartTC); + return Ok; +} +/** + ****************************************************************************** + ** \brief LPUART通é“接收数æ®å‡½æ•° + ** + ** \param [in] u8Idx通é“å· + ** + ** \retval æŽ¥æ”¶æ•°æ® + **\retval ErrorInvalidParameter接收失败 + ******************************************************************************/ +uint8_t LPUart_ReceiveData(uint8_t u8Idx) +{ + stc_lpuart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = LPUartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + return (pstcData->pstcInstance->SBUF_f.DATA); +} +/** + ****************************************************************************** + ** \brief LPUART通é“中断处ç†å‡½æ•° + ** + ** \param [in] u8Param通é“å· + ** + ** \retval æ—  + ** + ******************************************************************************/ +void LpUart_IRQHandler(uint8_t u8Param) +{ + stc_lpuart_instance_data_t *pstcData = NULL; + pstcData = LPUartGetInternDataPtr(u8Param); + if (NULL == pstcData) + { + return; + } + if(1 == pstcData->pstcInstance->ISR_f.FE) + { + LPUart_ClrStatus(u8Param,LPUartFE); + if(NULL != pstcData->stcLPUartInternIrqCb.pfnRxFEIrqCb) + { + pstcData->stcLPUartInternIrqCb.pfnRxFEIrqCb(); + } + return;//帧出错则ä¸è¿›è¡ŒåŽç»­æ•°æ®å¤„ç† + } + if(1 == pstcData->pstcInstance->ISR_f.PE) + { + LPUart_ClrStatus(u8Param,LPUartPE); + if(NULL != pstcData->stcLPUartInternIrqCb.pfnPEIrqCb) + { + pstcData->stcLPUartInternIrqCb.pfnPEIrqCb(); + } + return;//若奇å¶æ ¡éªŒå‡ºé”™åˆ™ä¸è¿›è¡ŒåŽç»­æ•°æ®å¤„ç† + } + if(1 == pstcData->pstcInstance->ISR_f.CTSIF) + { + LPUart_ClrStatus(u8Param,LPUartCts); + if(NULL != pstcData->stcLPUartInternIrqCb.pfnCtsIrqCb) + { + pstcData->stcLPUartInternIrqCb.pfnCtsIrqCb(); + } + } + if(1 == pstcData->pstcInstance->ISR_f.RC) + { + LPUart_ClrStatus(u8Param,LPUartRC); + if(NULL != pstcData->stcLPUartInternIrqCb.pfnRxIrqCb) + { + pstcData->stcLPUartInternIrqCb.pfnRxIrqCb(); + } + } + if(1 == pstcData->pstcInstance->ISR_f.TC) + { + LPUart_ClrStatus(u8Param,LPUartTC); + if(NULL != pstcData->stcLPUartInternIrqCb.pfnTxIrqCb) + { + pstcData->stcLPUartInternIrqCb.pfnTxIrqCb(); + } + } +} +/** + ****************************************************************************** + ** \brief LPUART通é“使能内核NVIC中断 + ** + ** \param [in] u8Idx通é“å· + ** + ** \retval æ—  + ** + ******************************************************************************/ +static void LPUartInitNvic(uint8_t u8Idx) +{ + IRQn_Type enIrqIndex; + + ASSERT(IS_VALID_CH(u8Idx));; + enIrqIndex = (IRQn_Type)(LPUART0_IRQn + u8Idx); + NVIC_ClearPendingIRQ(enIrqIndex); + NVIC_SetPriority(enIrqIndex,IrqLevel3); + NVIC_EnableIRQ(enIrqIndex); + +} +/** + ****************************************************************************** + ** \brief LPUART通é“ç¦æ­¢å†…æ ¸NVIC中断 + ** + ** \param [in] u8Idx通é“å· + ** + ** \retval æ—  + ** + ******************************************************************************/ +static void LPUartDeInitNvic(uint8_t u8Idx) +{ + IRQn_Type enIrqIndex; + + ASSERT(IS_VALID_CH(u8Idx)); + enIrqIndex = (IRQn_Type)(LPUART0_IRQn + u8Idx); + NVIC_ClearPendingIRQ(enIrqIndex); + NVIC_SetPriority(enIrqIndex,IrqLevel3); + NVIC_DisableIRQ(enIrqIndex); + +} +/** + ****************************************************************************** + ** \brief LPUART通é“åˆå§‹åŒ–函数 + ** + ** \param [in] u8Idx通é“å·ï¼ŒpstcConfigåˆå§‹åŒ–结构体 + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t LPUart_Init(uint8_t u8Idx,stc_lpuart_config_t* pstcConfig) +{ + en_result_t enRet = Error; + stc_lpuart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = LPUartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + if(NULL == pstcConfig) + { + return ErrorInvalidParameter; + } + if(NULL != pstcConfig->pstcLpuart_clk) + { + LPUart_SelSclk(u8Idx,pstcConfig->pstcLpuart_clk->enSclk_sel); + LPUart_SetClkDiv(u8Idx,pstcConfig->pstcLpuart_clk->enSclk_Prs); + } + enRet = LPUart_SetMode(u8Idx,pstcConfig->enRunMode); + enRet = LPUart_SetStopBit(u8Idx,pstcConfig->enStopBit); + if(NULL != pstcConfig->pstcMultiMode) + { + enRet = LPUart_SetMultiMode(u8Idx,pstcConfig->pstcMultiMode); + } + if(NULL != pstcConfig->pstcIrqCb) + { + pstcData->stcLPUartInternIrqCb.pfnRxFEIrqCb = pstcConfig->pstcIrqCb->pfnRxFEIrqCb; + pstcData->stcLPUartInternIrqCb.pfnRxIrqCb = pstcConfig->pstcIrqCb->pfnRxIrqCb; + pstcData->stcLPUartInternIrqCb.pfnTxIrqCb = pstcConfig->pstcIrqCb->pfnTxIrqCb; + pstcData->stcLPUartInternIrqCb.pfnCtsIrqCb = pstcConfig->pstcIrqCb->pfnCtsIrqCb; + pstcData->stcLPUartInternIrqCb.pfnPEIrqCb = pstcConfig->pstcIrqCb->pfnPEIrqCb; + } + if(pstcConfig->bTouchNvic == TRUE) + { + LPUartInitNvic(u8Idx); + } + else + { + LPUartDeInitNvic(u8Idx); + } + enRet = Ok; + return enRet; +} +//@} // LPUartGroup diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/lvd.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/lvd.c new file mode 100644 index 0000000000..d8e669fbaf --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/lvd.c @@ -0,0 +1,327 @@ +/****************************************************************************** +* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file lvd.c + ** + ** Low Voltage Detect driver API. + ** @link Lvd Group Some description @endlink + ** + ** - 2017-06-28 Alex First Version + ** + ******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "lvd.h" + +/** + ****************************************************************************** + ** \addtogroup LvdGroup + ******************************************************************************/ +//@{ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +#define IS_VALID_INPUT(x) ( (x) <= LvdInputPB07 ) + +#define IS_VALID_THRESHOLD(x) ( (x) <= LvdTH3p3V ) + +#define IS_VALID_FILTER(x) ( (x) <= LvdFilter29ms ) + +#define IS_VALID_IRQTYPE(x) ( (x) <= LvdIrqFall ) + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') * + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +// static void LvdEnableNvic(void); +// static void LvdDisableNvic(void); +// static en_result_t LvdEnable(en_lvd_type_t enType, boolean_t bFlag); + +/****************************************************************************** + * Local variable definitions ('static') + ******************************************************************************/ +static func_ptr_t pfnLvdIrqCbk = NULL; + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + *****************************************************************************/ + + /** + * \brief + * LVD中断æœåŠ¡ç¨‹åº + * + * \param [in] u8Param 未使用 + * + * \retval æ—  + */ +void Lvd_IRQHandler(uint8_t u8Param) +{ + M0P_LVD->IFR_f.INTF = 0u; + if (NULL != pfnLvdIrqCbk) + { + pfnLvdIrqCbk(); + } +} + +/** + * \brief + * 使能NVIC中LVD中断 + * + * \param æ—  + * + * \retval æ—  + */ +static void LvdEnableNvic(void) +{ + NVIC_ClearPendingIRQ(LVD_IRQn); + NVIC_SetPriority(LVD_IRQn, IrqLevel3); + NVIC_EnableIRQ(LVD_IRQn); +} + +/** + * \brief + * 除能NVIC中LVD中断 + * + * \param æ—  + * + * \retval æ—  + */ +static void LvdDisableNvic(void) +{ + NVIC_ClearPendingIRQ(LVD_IRQn); + NVIC_DisableIRQ(LVD_IRQn); + NVIC_SetPriority(LVD_IRQn, IrqLevel3); +} + +/** + * \brief + * 使能LVD中断 + * + * \param [in] enType LVD中断类型 + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效类型 + */ +en_result_t Lvd_EnableIrq(en_lvd_irq_type_t enType) +{ + en_result_t enRet = Ok; + + if (enType > LvdIrqFall) + { + return ErrorInvalidParameter; + } + else + { switch (enType) + { + case LvdIrqHigh: + M0P_LVD->CR_f.HTEN = 1u; + M0P_LVD->CR_f.RTEN = 0u; + M0P_LVD->CR_f.FTEN = 0u; + break; + case LvdIrqRise: + M0P_LVD->CR_f.HTEN = 0u; + M0P_LVD->CR_f.RTEN = 1u; + M0P_LVD->CR_f.FTEN = 0u; + break; + case LvdIrqFall: + M0P_LVD->CR_f.HTEN = 0u; + M0P_LVD->CR_f.RTEN = 0u; + M0P_LVD->CR_f.FTEN = 1u; + break; + default: + break; + } + + M0P_LVD->CR_f.IE = 1u; + LvdEnableNvic(); + } + return enRet; +} + +/** + * \brief + * 除能LVD中断 + * + * \param æ—  + * + * \retval æ—  + */ +void Lvd_DisableIrq(void) +{ + LvdDisableNvic(); + M0P_LVD->CR_f.IE = 0u; + M0P_LVD->CR_f.HTEN = 0u; + M0P_LVD->CR_f.RTEN = 0u; + M0P_LVD->CR_f.FTEN = 0u; +} + +/** + * \brief + * LVDåˆå§‹åŒ– + * + * \param [in] pstcConfig LVDé…置指针 + * + * \retval æ—  + */ +void Lvd_Init(stc_lvd_config_t *pstcConfig) +{ + ASSERT(pstcConfig); + ASSERT(IS_VALID_INPUT(pstcConfig->enInput)); + ASSERT(IS_VALID_THRESHOLD(pstcConfig->enThreshold)); + ASSERT(IS_VALID_FILTER(pstcConfig->enFilterTime)); + ASSERT(IS_VALID_IRQTYPE(pstcConfig->enIrqType)); + + //NEED to DISABLE first. + Lvd_Disable(); + Lvd_DisableIrq(); + LvdDisableNvic(); + + M0P_LVD->CR_f.DEBOUNCE_TIME = pstcConfig->enFilterTime; + M0P_LVD->CR_f.FLTEN = pstcConfig->bFilter; + M0P_LVD->CR_f.VTDS = pstcConfig->enThreshold; + M0P_LVD->CR_f.SOURCE_SEL = pstcConfig->enInput; + M0P_LVD->CR_f.ACT = pstcConfig->bLvdReset; + + pfnLvdIrqCbk = pstcConfig->pfnIrqCbk; +} + +/** + * \brief + * LVD deinit + * + * \param æ—  + * + * \retval æ—  + */ +void Lvd_DeInit(void) +{ + Lvd_DisableIrq(); + LvdDisableNvic(); + + pfnLvdIrqCbk = NULL; + Lvd_Disable(); +} + +/** + * \brief + * 使能LVD + * + * \param æ—  + * + * \retval æ—  + * + */ +void Lvd_Enable(void) +{ + M0P_LVD->CR_f.LVDEN = 1u; +} + +/** + * \brief + * 除能LVD + * + * \param æ—  + * + * \retval æ—  + */ +void Lvd_Disable(void) +{ + M0P_LVD->CR_f.LVDEN = 0u; +} + +/** + * \brief + * 获å–LVD中断标志 + * + * \param æ—  + * + * \retval boolean_t 中断标志 + */ +boolean_t Lvd_GetIrqStat(void) +{ + return M0P_LVD->IFR_f.INTF; + +} + +/** + * \brief + * 清除LVD中断标志 + * + * \param æ—  + * + * \retval æ—  + */ +void Lvd_ClearIrq(void) +{ + M0P_LVD->IFR_f.INTF = 0u; +} + +/** + * \brief + * 获å–Filter结果 + * + * \param æ—  + * + * \retval boolean_t Fliter结果 + */ +boolean_t Lvd_GetFilterResult(void) +{ + return (boolean_t)M0P_LVD->IFR_f.FILTER; +} +//@} // LvdGroup + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/opa.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/opa.c new file mode 100644 index 0000000000..38acfce544 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/opa.c @@ -0,0 +1,438 @@ +/****************************************************************************** +* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file opa.c + ** + ** opa driver API. + ** @link opa Group Some description @endlink + ** + ** - 2018-04-15 Devi First Version + ** + ******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "opa.h" + +/** + ****************************************************************************** + ** \addtogroup OPAGroup + ******************************************************************************/ +//@{ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +#define IS_VALID_pagagain(x) ( (x) <= 7 ) + +#define IS_VALID_channel(x) ( (OPA0 == (x)) ||\ + (OPA1 == (x)) ||\ + (OPA2 == (x)) ) + +#define IS_VALID_Mode(x) ( (OpaUintMode == (x)) ||\ + (OpaForWardMode == (x)) ||\ + (OpaOppositeMode == (x)) ||\ + (OpaThreeOppMode == (x)) ||\ + (OpaThreeForMode == (x)) ||\ + (OpaDiffMode == (x)) ||\ + (OpaMeterMode == (x)) ||\ + (OpaGpMode == (x)) ) + +#define IS_VALID_metergain(x) ( (OpaMeterGain3 == (x)) ||\ + (OpaMeterGain1_3 == (x)) ||\ + (OpaMeterGain1 == (x)) ) + +#define IS_VALID_calsel(x) ( (OpaSoftMode == (x)) ||\ + (OpaSoftTriggerMode == (x)) ||\ + (OpaADCTriggerMode == (x)) ) + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + *****************************************************************************/ + +/** + * \brief + * OPA åˆå§‹åŒ– + * + * \param æ—  + * \param æ—  + * + * \retval æ—  + * \retval æ—  + */ +en_result_t OPA_Init(void) +{ + uint16_t i; + + M0P_SYSCTRL->PERI_CLKEN_f.ADC = 1; + M0P_BGR->CR_f.BGR_EN = 1; + for(i=0;i<2000;i++) + { + ; + } + + M0P_OPA->CR0 = 0x120; + M0P_OPA->CR1 = 0x120; + M0P_OPA->CR2 = 0x120; + M0P_OPA->CR = 0x00; + return Ok; +} + +/** + * \brief + * OPA 去åˆå§‹åŒ– + * + * \param æ—  + * \param æ—  + * + * \retval æ—  + * \retval æ—  + */ +en_result_t OPA_DeInit(void) +{ + + M0P_OPA->CR0 = 0x120; + M0P_OPA->CR1 = 0x120; + M0P_OPA->CR2 = 0x120; + M0P_OPA->CR = 0x00; + M0P_BGR->CR_f.BGR_EN = 0; + M0P_SYSCTRL->PERI_CLKEN_f.ADC = 0; + return Ok; +} + +/** + * \brief + * OPA 基本功能设置 + * + * \param [in] en_opa_channel_t 使用那个通é“çš„OPA + * \param [in] en_opa_modesel_t OPA模å¼é€‰æ‹© + * \param [in] stc_opa_gain_config_t OPA增益选择 + * + * \retval æ—  + */ +en_result_t OPA_Operate(en_opa_channel_t enchannel ,en_opa_modesel_t enMode,stc_opa_gain_config_t *pstrGain) +{ + stc_opa_cr0_field_t *stcOpacr; + + ASSERT( IS_VALID_Mode(enMode) ); + ASSERT( IS_VALID_channel(enchannel) ); + + if (OPA0 == enchannel) + { + stcOpacr = (stc_opa_cr0_field_t*)&M0P_OPA->CR0_f; + } + if (OPA1 == enchannel) + { + stcOpacr = (stc_opa_cr0_field_t*)&M0P_OPA->CR1_f; + } + if (OPA2 == enchannel) + { + stcOpacr = (stc_opa_cr0_field_t*)&M0P_OPA->CR2_f; + } + + if(enMode == OpaUintMode) + { + stcOpacr->NEGSEL = 0; + stcOpacr->POSSEL = 3; + stcOpacr->UBUFSEL = 1; + stcOpacr->POEN = 1; + } + else if(enMode == OpaForWardMode) + { + stcOpacr->NEGSEL = 1; + stcOpacr->POEN = 1; + stcOpacr->PGAGAIN = pstrGain->enNoInGain; + stcOpacr->POSSEL = 3; + stcOpacr->RESINMUX = 0; + stcOpacr->RESSEL = 1; + } + else if(enMode == OpaOppositeMode) + { + stcOpacr->NEGSEL = 1; + stcOpacr->POEN = 1; + stcOpacr->PGAGAIN = pstrGain->enInGain; + stcOpacr->POSSEL = 3; + stcOpacr->RESINMUX = 2; + stcOpacr->RESSEL = 1; + } + else if(enMode == OpaDiffMode) + { + M0P_OPA->CR0_f.POSSEL = 3; + M0P_OPA->CR1_f.POSSEL = 3; + M0P_OPA->CR2_f.POSSEL = 0; + + M0P_OPA->CR0_f.NEGSEL = 0; + M0P_OPA->CR1_f.NEGSEL = 1; + M0P_OPA->CR2_f.NEGSEL = 1; + + M0P_OPA->CR0_f.RESINMUX = 0; + M0P_OPA->CR1_f.RESINMUX = 1; + M0P_OPA->CR2_f.RESINMUX = 0; + + M0P_OPA->CR0_f.UBUFSEL = 1; + M0P_OPA->CR1_f.UBUFSEL = 0; + M0P_OPA->CR2_f.UBUFSEL = 0; + + M0P_OPA->CR0_f.RESSEL = 0; + M0P_OPA->CR1_f.RESSEL = 1; + M0P_OPA->CR2_f.RESSEL = 0; + + M0P_OPA->CR0_f.POEN = 0; + M0P_OPA->CR1_f.POEN = 1; + M0P_OPA->CR2_f.POEN = 0; + + M0P_OPA->CR0_f.PGAGAIN = 0; + M0P_OPA->CR1_f.PGAGAIN = pstrGain->enNoInGain; + M0P_OPA->CR2_f.PGAGAIN = 0; + } + else if(enMode == OpaGpMode) + { + stcOpacr->BIASSEL = 1; + stcOpacr->MODE = 1; + stcOpacr->NEGSEL = 3; + stcOpacr->POEN = 0; + stcOpacr->PGAGAIN = 5; + stcOpacr->POSSEL = 3; + stcOpacr->RESINMUX = 0; + stcOpacr->RESSEL = 0; + stcOpacr->UBUFSEL = 0; + } + else + { + return ErrorInvalidParameter; + } + M0P_OPA->CR0_f.EN = 1; + M0P_OPA->CR1_f.EN = 1; + M0P_OPA->CR2_f.EN = 1; + return Ok; +} + +/** + * \brief + * OPA 基本功能设置 (级è”æ­£å‘å’Œåå‘模å¼ä»¥åŠä»ªè¡¨æ¨¡å¼) + * \param [in] en_opa_modesel_t OPA模å¼é€‰æ‹© + * \param [in] stc_opa_gain_config_t OPA增益选择 + * + * \retval æ—  + */ +en_result_t OPA_ThreeOperate(en_opa_modesel_t enMode,stc_opa_gain_config_t *pstrGain0,stc_opa_gain_config_t *pstrGain1,stc_opa_gain_config_t *pstrGain2) +{ + + ASSERT( IS_VALID_Mode(enMode) ); + + if(enMode == OpaThreeOppMode) + { + M0P_OPA->CR0_f.POSSEL = 3; + M0P_OPA->CR1_f.POSSEL = 3; + M0P_OPA->CR2_f.POSSEL = 3; + + M0P_OPA->CR0_f.NEGSEL = 1; + M0P_OPA->CR1_f.NEGSEL = 1; + M0P_OPA->CR2_f.NEGSEL = 1; + + M0P_OPA->CR0_f.RESINMUX = 2; + M0P_OPA->CR1_f.RESINMUX = 1; + M0P_OPA->CR2_f.RESINMUX = 1; + + M0P_OPA->CR0_f.RESSEL = 1; + M0P_OPA->CR1_f.RESSEL = 1; + M0P_OPA->CR2_f.RESSEL = 1; + + M0P_OPA->CR0_f.POEN = 0; + M0P_OPA->CR1_f.POEN = 0; + M0P_OPA->CR2_f.POEN = 1; + + M0P_OPA->CR0_f.PGAGAIN = pstrGain0->enInGain; + M0P_OPA->CR1_f.PGAGAIN = pstrGain1->enInGain; + M0P_OPA->CR2_f.PGAGAIN = pstrGain2->enInGain; + } + else if(enMode == OpaThreeForMode) + { + M0P_OPA->CR0_f.POSSEL = 3; + M0P_OPA->CR1_f.POSSEL = 2; + M0P_OPA->CR2_f.POSSEL = 2; + + M0P_OPA->CR0_f.NEGSEL = 1; + M0P_OPA->CR1_f.NEGSEL = 1; + M0P_OPA->CR2_f.NEGSEL = 1; + + M0P_OPA->CR0_f.RESINMUX = 0; + M0P_OPA->CR1_f.RESINMUX = 0; + M0P_OPA->CR2_f.RESINMUX = 0; + + M0P_OPA->CR0_f.UBUFSEL = 0; + M0P_OPA->CR1_f.UBUFSEL = 0; + M0P_OPA->CR2_f.UBUFSEL = 0; + + M0P_OPA->CR0_f.RESSEL = 1; + M0P_OPA->CR1_f.RESSEL = 1; + M0P_OPA->CR2_f.RESSEL = 1; + + M0P_OPA->CR0_f.POEN = 0; + M0P_OPA->CR1_f.POEN = 0; + M0P_OPA->CR2_f.POEN = 1; + + M0P_OPA->CR0_f.PGAGAIN = pstrGain0->enNoInGain; + M0P_OPA->CR1_f.PGAGAIN = pstrGain1->enNoInGain; + M0P_OPA->CR2_f.PGAGAIN = pstrGain2->enNoInGain; + } + else + { + return ErrorInvalidParameter; + } + M0P_OPA->CR0_f.EN = 1; + M0P_OPA->CR1_f.EN = 1; + M0P_OPA->CR2_f.EN = 1; + return Ok; +} + +/** + * \brief + * OPA ä»ªè¡¨æ¨¡å¼ + * \param [in] en_opa_metergain_t OPA增益选择 + * + * \retval æ—  + */ +en_result_t OPA_MeterOperate(en_opa_metergain_t enGainMode) +{ + ASSERT( IS_VALID_metergain(enGainMode) ); + + M0P_OPA->CR0_f.POSSEL = 3; + M0P_OPA->CR1_f.POSSEL = 3; + M0P_OPA->CR2_f.POSSEL = 1; + + M0P_OPA->CR0_f.NEGSEL = 0; + M0P_OPA->CR1_f.NEGSEL = 0; + M0P_OPA->CR2_f.NEGSEL = 1; + + M0P_OPA->CR0_f.RESINMUX = 0; + M0P_OPA->CR1_f.RESINMUX = 0; + M0P_OPA->CR2_f.RESINMUX = 1; + + M0P_OPA->CR0_f.UBUFSEL = 1; + M0P_OPA->CR1_f.UBUFSEL = 1; + M0P_OPA->CR2_f.UBUFSEL = 0; + + M0P_OPA->CR0_f.RESSEL = 1; + M0P_OPA->CR1_f.RESSEL = 0; + M0P_OPA->CR2_f.RESSEL = 1; + + M0P_OPA->CR0_f.POEN = 0; + M0P_OPA->CR1_f.POEN = 0; + M0P_OPA->CR2_f.POEN = 1; + + if(enGainMode == OpaMeterGain3) + { + M0P_OPA->CR0_f.PGAGAIN = 6; + M0P_OPA->CR2_f.PGAGAIN = 3; + } + if(enGainMode == OpaMeterGain1_3) + { + M0P_OPA->CR0_f.PGAGAIN = 3; + M0P_OPA->CR2_f.PGAGAIN = 6; + } + if(enGainMode == OpaMeterGain1) + { + M0P_OPA->CR0_f.PGAGAIN = 5; + M0P_OPA->CR2_f.PGAGAIN = 5; + } + + M0P_OPA->CR0_f.EN = 1; + M0P_OPA->CR1_f.EN = 1; + M0P_OPA->CR2_f.EN = 1; + return Ok; +} +/** + * \brief + * OPA æ ¡æ­£æ¨¡å¼ + * \param [in] en_opa_calsel_t OPA校正模å¼é€‰æ‹© + * + * \retval æ—  + */ +en_result_t OPA_Cal(en_opa_calsel_t enCalMode) +{ + ASSERT( IS_VALID_calsel(enCalMode) ); + + if(enCalMode == OpaSoftMode) + { + + } + if(enCalMode == OpaSoftTriggerMode) + { + + } + if (enCalMode == OpaADCTriggerMode) + { + + } + + M0P_OPA->CR0_f.EN = 1; + M0P_OPA->CR1_f.EN = 1; + M0P_OPA->CR2_f.EN = 1; + return Ok; +} +//@} // OPAGroup + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/pca.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/pca.c new file mode 100644 index 0000000000..774e91c265 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/pca.c @@ -0,0 +1,834 @@ +/****************************************************************************** +*Copyright(C)2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file pca.c + ** + ** Common API of PCA. + ** @link pcaGroup Some description @endlink + ** + ** - 2018-04-16 Husj First version + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "pca.h" +/** + ******************************************************************************* + ** \addtogroup PcaGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define IS_VALID_MODULE(x) (Module0 == (x) ||\ + Module1 == (x) ||\ + Module2 == (x) ||\ + Module3 == (x) ||\ + Module4 == (x)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static func_ptr_t pfnPcaCallback = NULL; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ***************************************************************************** + ** \brief PCAä¸­æ–­æ ‡å¿—èŽ·å– + ** + ** + ** \param [in] enModule PCA模å—选择（Module0ã€Module1ã€Module2ã€Module3ã€Module4） + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +boolean_t Pca_GetIntFlag(en_pca_module_t enModule) +{ + boolean_t bRetVal = FALSE; + + ASSERT(IS_VALID_MODULE(enModule)); + + switch (enModule) + { + case Module0: + bRetVal = M0P_PCA->CCON_f.CCF0 ? TRUE : FALSE; + break; + case Module1: + bRetVal = M0P_PCA->CCON_f.CCF1 ? TRUE : FALSE; + break; + case Module2: + bRetVal = M0P_PCA->CCON_f.CCF2 ? TRUE : FALSE; + break; + case Module3: + bRetVal = M0P_PCA->CCON_f.CCF3 ? TRUE : FALSE; + break; + case Module4: + bRetVal = M0P_PCA->CCON_f.CCF4 ? TRUE : FALSE; + break; + default: + bRetVal = FALSE; + break; + } + + return bRetVal; +} + +/** + ***************************************************************************** + ** \brief PCAè®¡æ•°ä¸­æ–­æ ‡å¿—èŽ·å– + ** + ** + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +boolean_t Pca_GetCntIntFlag(void) +{ + boolean_t bRetVal = FALSE; + + bRetVal = M0P_PCA->CCON_f.CF ? TRUE : FALSE; + + return bRetVal; +} + +/** + ***************************************************************************** + ** \brief PCA中断标志清除 + ** + ** + ** \param [in] enModule PCA模å—选择（Module0ã€Module1ã€Module2ã€Module3ã€Module4） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Pca_ClearIntFlag(en_pca_module_t enModule) +{ + en_result_t enResult = Error; + + ASSERT(IS_VALID_MODULE(enModule)); + + switch (enModule) + { + case Module0: + M0P_PCA->ICLR_f.CCF0 = FALSE; + enResult = Ok; + break; + case Module1: + M0P_PCA->ICLR_f.CCF1 = FALSE; + enResult = Ok; + break; + case Module2: + M0P_PCA->ICLR_f.CCF2 = FALSE; + enResult = Ok; + break; + case Module3: + M0P_PCA->ICLR_f.CCF3 = FALSE; + enResult = Ok; + break; + case Module4: + M0P_PCA->ICLR_f.CCF4 = FALSE; + enResult = Ok; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief PCA计数中断标志清除 + ** + ** + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Pca_ClearCntIntFlag(void) +{ + en_result_t enResult = Error; + + M0P_PCA->ICLR_f.CF = FALSE; + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief PCA中断æœåŠ¡ç¨‹åº + ** + ** + ** \param [in] u8Param == 0 + ** + *****************************************************************************/ +void Pca_IRQHandler(uint8_t u8Param) +{ + if(NULL != pfnPcaCallback) + { + pfnPcaCallback(); + } +} + +/** + ***************************************************************************** + ** \brief PCA中断使能 + ** + ** + ** \param [in] enModule PCA模å—选择（Module0ã€Module1ã€Module2ã€Module3ã€Module4） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Pca_EnableIrq(en_pca_module_t enModule) +{ + en_result_t enResult = Error; + + ASSERT(IS_VALID_MODULE(enModule)); + + switch (enModule) + { + case Module0: + M0P_PCA->CCAPM0_f.CCIE = TRUE; + enResult = Ok; + break; + case Module1: + M0P_PCA->CCAPM1_f.CCIE = TRUE; + enResult = Ok; + break; + case Module2: + M0P_PCA->CCAPM2_f.CCIE = TRUE; + enResult = Ok; + break; + case Module3: + M0P_PCA->CCAPM3_f.CCIE = TRUE; + enResult = Ok; + break; + case Module4: + M0P_PCA->CCAPM4_f.CCIE = TRUE; + enResult = Ok; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief PCA计数中断使能 + ** + ** + ** + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Pca_EnableCntIrq (void) +{ + en_result_t enResult = Error; + + M0P_PCA->CMOD_f.CFIE = TRUE; + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief PCA中断ç¦æ­¢ + ** + ** + ** \param [in] enModule PCA模å—选择（Module0ã€Module1ã€Module2ã€Module3ã€Module4） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Pca_DisableIrq(en_pca_module_t enModule) +{ + en_result_t enResult = Error; + + ASSERT(IS_VALID_MODULE(enModule)); + + switch (enModule) + { + case Module0: + M0P_PCA->CCAPM0_f.CCIE = FALSE; + enResult = Ok; + break; + case Module1: + M0P_PCA->CCAPM1_f.CCIE = FALSE; + enResult = Ok; + break; + case Module2: + M0P_PCA->CCAPM2_f.CCIE = FALSE; + enResult = Ok; + break; + case Module3: + M0P_PCA->CCAPM3_f.CCIE = FALSE; + enResult = Ok; + break; + case Module4: + M0P_PCA->CCAPM4_f.CCIE = FALSE; + enResult = Ok; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief PCA计数中断ç¦æ­¢ + ** + ** + ** + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Pca_DisableCntIrq(void) +{ + en_result_t enResult = Error; + + M0P_PCA->CMOD_f.CFIE = FALSE; + enResult = Ok; + + return enResult; +} + + +/** + ***************************************************************************** + ** \brief PCAåˆå§‹åŒ–é…ç½® + ** + ** + ** \param [in] pstcConfig PCA模å—é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Pca_Init(stc_pca_config_t* pstcConfig) +{ + en_result_t enResult = Error; + + M0P_PCA->CMOD_f.CIDL = pstcConfig->enCIDL; + M0P_PCA->CMOD_f.WDTE = pstcConfig->enWDTE; + M0P_PCA->CMOD_f.CPS = pstcConfig->enCPS; + + pfnPcaCallback = pstcConfig->pfnPcaCb; + + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief PCA模å¼é…ç½® + ** + ** + ** \param [in] enModule PCA模å—选择（Module0ã€Module1ã€Module2ã€Module3ã€Module4） + ** \param [in] pstcCapMod PCA模å¼é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Pca_CapModConfig(en_pca_module_t enModule, stc_pca_capmodconfig_t* pstcCapMod) +{ + en_result_t enResult = Error; + + ASSERT(IS_VALID_MODULE(enModule)); + + switch (enModule) + { + case Module0: + { + M0P_PCA->CCAPM0_f.ECOM = pstcCapMod->enECOM; + M0P_PCA->CCAPM0_f.CAPP = pstcCapMod->enCAPP; + M0P_PCA->CCAPM0_f.CAPN = pstcCapMod->enCAPN; + M0P_PCA->CCAPM0_f.MAT = pstcCapMod->enMAT; + M0P_PCA->CCAPM0_f.TOG = pstcCapMod->enTOG; + M0P_PCA->CCAPM0_f.PWM = pstcCapMod->en8bitPWM; + enResult = Ok; + } + break; + case Module1: + { + M0P_PCA->CCAPM1_f.ECOM = pstcCapMod->enECOM; + M0P_PCA->CCAPM1_f.CAPP = pstcCapMod->enCAPP; + M0P_PCA->CCAPM1_f.CAPN = pstcCapMod->enCAPN; + M0P_PCA->CCAPM1_f.MAT = pstcCapMod->enMAT; + M0P_PCA->CCAPM1_f.TOG = pstcCapMod->enTOG; + M0P_PCA->CCAPM1_f.PWM = pstcCapMod->en8bitPWM; + enResult = Ok; + } + break; + case Module2: + { + M0P_PCA->CCAPM2_f.ECOM = pstcCapMod->enECOM; + M0P_PCA->CCAPM2_f.CAPP = pstcCapMod->enCAPP; + M0P_PCA->CCAPM2_f.CAPN = pstcCapMod->enCAPN; + M0P_PCA->CCAPM2_f.MAT = pstcCapMod->enMAT; + M0P_PCA->CCAPM2_f.TOG = pstcCapMod->enTOG; + M0P_PCA->CCAPM2_f.PWM = pstcCapMod->en8bitPWM; + enResult = Ok; + } + break; + case Module3: + { + M0P_PCA->CCAPM3_f.ECOM = pstcCapMod->enECOM; + M0P_PCA->CCAPM3_f.CAPP = pstcCapMod->enCAPP; + M0P_PCA->CCAPM3_f.CAPN = pstcCapMod->enCAPN; + M0P_PCA->CCAPM3_f.MAT = pstcCapMod->enMAT; + M0P_PCA->CCAPM3_f.TOG = pstcCapMod->enTOG; + M0P_PCA->CCAPM3_f.PWM = pstcCapMod->en8bitPWM; + enResult = Ok; + } + break; + case Module4: + { + M0P_PCA->CCAPM4_f.ECOM = pstcCapMod->enECOM; + M0P_PCA->CCAPM4_f.CAPP = pstcCapMod->enCAPP; + M0P_PCA->CCAPM4_f.CAPN = pstcCapMod->enCAPN; + M0P_PCA->CCAPM4_f.MAT = pstcCapMod->enMAT; + M0P_PCA->CCAPM4_f.TOG = pstcCapMod->enTOG; + M0P_PCA->CCAPM4_f.PWM = pstcCapMod->en8bitPWM; + enResult = Ok; + } + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief PCAå¯åŠ¨è¿è¡Œ + ** + ** + ** + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Pca_Run(void) +{ + en_result_t enResult = Error; + + M0P_PCA->CCON_f.CR = TRUE; + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief PCAåœæ­¢è¿è¡Œ + ** + ** + ** + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Pca_Stop(void) +{ + en_result_t enResult = Error; + + M0P_PCA->CCON_f.CR = FALSE; + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief PCA16ä½æ¯”较数æ®è®¾ç½® + ** + ** + ** \param [in] enModule PCA模å—选择（Module0ã€Module1ã€Module2ã€Module3ã€Module4） + ** \param [in] u16Data PCAæ•èŽ·æ•°æ® + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Pca_CmpData16Set(en_pca_module_t enModule, uint16_t u16Data) +{ + en_result_t enResult = Error; + + ASSERT(IS_VALID_MODULE(enModule)); + + switch (enModule) + { + case Module0: + M0P_PCA->CCAP0_f.CCAP0 = u16Data; + enResult = Ok; + break; + case Module1: + M0P_PCA->CCAP1_f.CCAP1 = u16Data; + enResult = Ok; + break; + case Module2: + M0P_PCA->CCAP2_f.CCAP2 = u16Data; + enResult = Ok; + break; + case Module3: + M0P_PCA->CCAP3_f.CCAP3 = u16Data; + enResult = Ok; + break; + case Module4: + M0P_PCA->CCAP4_f.CCAP4 = u16Data; + enResult = Ok; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + + +/** + ***************************************************************************** + ** \brief PCA16ä½æ•èŽ·æ•°æ®èŽ·å– + ** + ** + ** \param [in] enModule PCA模å—选择（Module0ã€Module1ã€Module2ã€Module3ã€Module4） + ** + ** \retval u16Data + *****************************************************************************/ +uint16_t Pca_CapData16Get(en_pca_module_t enModule) +{ + uint16_t u16Data = 0; + + ASSERT(IS_VALID_MODULE(enModule)); + + switch (enModule) + { + case Module0: + u16Data = M0P_PCA->CCAP0_f.CCAP0; + break; + case Module1: + u16Data = M0P_PCA->CCAP1_f.CCAP1; + break; + case Module2: + u16Data = M0P_PCA->CCAP2_f.CCAP2; + break; + case Module3: + u16Data = M0P_PCA->CCAP3_f.CCAP3; + break; + case Module4: + u16Data = M0P_PCA->CCAP4_f.CCAP4; + break; + default: + u16Data = 0; + break; + } + + return u16Data; +} + +/** + ***************************************************************************** + ** \brief PCA高8ä½æ¯”较数æ®è®¾ç½® + ** + ** + ** \param [in] enModule PCA模å—选择（Module0ã€Module1ã€Module2ã€Module3ã€Module4） + ** \param [in] u8Data PCA高8ä½æ•èŽ·æ•°æ® + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Pca_CmpDataHSet(en_pca_module_t enModule, uint8_t u8Data) +{ + en_result_t enResult = Error; + + ASSERT(IS_VALID_MODULE(enModule)); + + switch (enModule) + { + case Module0: + M0P_PCA->CCAP0H_f.CCAP0 = u8Data; + enResult = Ok; + break; + case Module1: + M0P_PCA->CCAP1H_f.CCAP1 = u8Data; + enResult = Ok; + break; + case Module2: + M0P_PCA->CCAP2H_f.CCAP2 = u8Data; + enResult = Ok; + break; + case Module3: + M0P_PCA->CCAP3H_f.CCAP3 = u8Data; + enResult = Ok; + break; + case Module4: + M0P_PCA->CCAP4H_f.CCAP4 = u8Data; + enResult = Ok; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief PCA低8ä½æ¯”较数æ®è®¾ç½® + ** + ** + ** \param [in] enModule PCA模å—选择（Module0ã€Module1ã€Module2ã€Module3ã€Module4） + ** \param [in] u8Data PCA低8ä½æ•èŽ·æ•°æ® + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Pca_CmpDataLSet(en_pca_module_t enModule, uint8_t u8Data) +{ + en_result_t enResult = Error; + + ASSERT(IS_VALID_MODULE(enModule)); + + switch (enModule) + { + case Module0: + M0P_PCA->CCAP0L_f.CCAP0 = u8Data; + enResult = Ok; + break; + case Module1: + M0P_PCA->CCAP1L_f.CCAP1 = u8Data; + enResult = Ok; + break; + case Module2: + M0P_PCA->CCAP2L_f.CCAP2 = u8Data; + enResult = Ok; + break; + case Module3: + M0P_PCA->CCAP3L_f.CCAP3 = u8Data; + enResult = Ok; + break; + case Module4: + M0P_PCA->CCAP4L_f.CCAP4 = u8Data; + enResult = Ok; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief PCA计数器åˆå€¼è®¾ç½® + ** + ** + ** + ** \param [in] u16Data PCA计数器åˆå€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Pca_Cnt16Set(uint16_t u16Data) +{ + en_result_t enResult = Error; + + M0P_PCA->CNT_f.CNT = u16Data; + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief PCA16ä½è®¡æ•°å™¨å€¼èŽ·å– + ** + ** + ** + ** \retval 16ä½è®¡æ•°å™¨å€¼ + *****************************************************************************/ +uint16_t Pca_Cnt16Get(void) +{ + uint16_t u16CntData = 0; + + u16CntData = M0P_PCA->CNT_f.CNT; + + return u16CntData; +} + +/** + ***************************************************************************** + ** \brief PCA周期é‡è½½å€¼è®¾ç½® + ** + ** + ** + ** \param [in] u16Data PCA周期é‡è½½å€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Pca_CARRSet(uint16_t u16Data) +{ + en_result_t enResult = Error; + + M0P_PCA->CARR_f.CARR = u16Data; + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief PCA周期é‡è½½å€¼èŽ·å– + ** + ** + ** + ** \retval PCA周期é‡è½½å€¼ + *****************************************************************************/ +uint16_t Pca_CARRGet(void) +{ + uint16_t u16CntData = 0; + + u16CntData = M0P_PCA->CARR_f.CARR; + + return u16CntData; +} + +/** + ***************************************************************************** + ** \brief PCA增强PWM 使能 + ** + ** + ** + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Pca_Enable16bitPWM(void) +{ + en_result_t enResult = Error; + + M0P_PCA->EPWM_f.EPWM = TRUE; + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief PCA增强PWM ç¦æ­¢ + ** + ** + ** + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Pca_Disable16bitPWM(void) +{ + en_result_t enResult = Error; + + M0P_PCA->EPWM_f.EPWM = FALSE; + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief PCAæ¯”è¾ƒé«˜é€Ÿè¾“å‡ºæ ‡å¿—èŽ·å– + ** + ** + ** \param [in] enModule PCA模å—选择（Module0ã€Module1ã€Module2ã€Module3ã€Module4） + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +boolean_t Pca_GetCmpHighFlag(en_pca_module_t enModule) +{ + boolean_t bRetVal = FALSE; + + ASSERT(IS_VALID_MODULE(enModule)); + + switch (enModule) + { + case Module0: + bRetVal = M0P_PCA->CCAPO_f.CCAPO0 ? TRUE : FALSE; + break; + case Module1: + bRetVal = M0P_PCA->CCAPO_f.CCAPO1 ? TRUE : FALSE; + break; + case Module2: + bRetVal = M0P_PCA->CCAPO_f.CCAPO2 ? TRUE : FALSE; + break; + case Module3: + bRetVal = M0P_PCA->CCAPO_f.CCAPO3 ? TRUE : FALSE; + break; + case Module4: + bRetVal = M0P_PCA->CCAPO_f.CCAPO4 ? TRUE : FALSE; + break; + default: + bRetVal = FALSE; + break; + } + + return bRetVal; +} + +//@} // PcaGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/pcnt.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/pcnt.c new file mode 100644 index 0000000000..bdf0561aeb --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/pcnt.c @@ -0,0 +1,417 @@ +/****************************************************************************** +* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file pcnt.c + ** + ** pcnt driver API. + ** @link pcnt Group Some description @endlink + ** + ** - 2018-04-15 Devi First Version + ** + ******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "pcnt.h" + +/** + ****************************************************************************** + ** \addtogroup PCNTGroup + ******************************************************************************/ +//@{ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +#define IS_VALID_pagagain(x) ( (x) <= 7 ) + +#define IS_VALID_channel(x) ( (OPA0 == (x)) ||\ + (OPA1 == (x)) ||\ + (OPA2 == (x)) ) + +#define IS_VALID_STAT(x) ( (PCNT_S1E == (x)) ||\ + (PCNT_S0E == (x)) ||\ + (PCNT_BB == (x)) ||\ + (PCNT_FE == (x)) ||\ + (PCNT_DIR == (x)) ||\ + (PCNT_TO == (x)) ||\ + (PCNT_OV == (x)) ||\ + (PCNT_UF == (x)) ) + + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +static func_ptr_t pfnPcntCallback = NULL; ///< callback function pointer for PCNT Irq +/****************************************************************************** + * Local variable definitions ('static') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + *****************************************************************************/ + +void Pcnt_IRQHandler(void) +{ + if(NULL != pfnPcntCallback) + { + pfnPcntCallback(); + } +} + +/** + * \brief + * PCNT åˆå§‹åŒ– + * + * \param æ—  + * \param æ—  + * + * \retval æ—  + * \retval æ—  + */ +en_result_t PCNT_Init(stc_pcnt_config_t* pstcPcntConfig) +{ + + + M0P_SYSCTRL->PERI_CLKEN_f.PCNT = 1; + + M0P_PCNT->CR_f.S1P = pstcPcntConfig->bS1Sel; + M0P_PCNT->CR_f.S0P = pstcPcntConfig->bS0Sel; + M0P_PCNT->CR_f.DIR = pstcPcntConfig->u8Direc; //è®¡æ•°æ–¹å¼ + M0P_PCNT->CR_f.CLKSEL = pstcPcntConfig->u8Clk; + M0P_PCNT->CR_f.MODE = pstcPcntConfig->u8Mode; + + M0P_PCNT->FLT_f.CLKDIV = pstcPcntConfig->u8FLTClk; + + if(pstcPcntConfig->bFLTEn) + { + if(pstcPcntConfig->u8FLTDep == 0) + { + M0P_PCNT->FLT_f.DEBTOP = 2; + } + else + { + M0P_PCNT->FLT_f.DEBTOP = pstcPcntConfig->u8FLTDep; + } + } + M0P_PCNT->FLT_f.EN = pstcPcntConfig->bFLTEn; + + M0P_PCNT->TOCR_f.TH = pstcPcntConfig->u16TODep; + M0P_PCNT->TOCR_f.EN = pstcPcntConfig->bTOEn; + + if (TRUE == pstcPcntConfig->bIrqEn) + { + M0P_PCNT->IEN = pstcPcntConfig->u8IrqStatus; + EnableNvic(PCNT_IRQn,IrqLevel3,TRUE); + } + else + { + M0P_PCNT->IEN = 0x00; + EnableNvic(PCNT_IRQn,IrqLevel3,FALSE); + } + if(NULL != pstcPcntConfig->pfnIrqCb) + { + pfnPcntCallback = pstcPcntConfig->pfnIrqCb; + } + return Ok; +} + +/** + * \brief + * PCNT 去åˆå§‹åŒ– + * + * \param æ—  + * \param æ—  + * + * \retval æ—  + * \retval æ—  + */ +void PCNT_DeInit(void) +{ + M0P_PCNT->CR = 0; + M0P_PCNT->RUN = 0; + M0P_SYSCTRL->PERI_CLKEN_f.PCNT = 0; + +} + +/** + * \brief + * PCNT 脉冲计数设置 + * + * \param [in] start 开始计数设置 + * \param [in] end 结æŸè®¡æ•°è®¾ç½® + * + * \retval æ—  + */ +en_result_t PCNT_Parameter(uint8_t start,uint8_t end) +{ + uint32_t u32TimeOut; + + u32TimeOut = 1000; + M0P_PCNT->BUF = end; //加载结æŸæº¢å‡ºå€¼ + M0P_PCNT->CMD_f.B2T = 1; + + while(u32TimeOut--) + { + if(FALSE == M0P_PCNT->SR2_f.B2T) + { + break; + } + } + if(u32TimeOut == 0) + { + return ErrorTimeout; + } + + u32TimeOut = 1000; + M0P_PCNT->BUF = start; //加载åˆå§‹å€¼ + M0P_PCNT->CMD_f.B2C = 1; + + while(u32TimeOut--) + { + if(FALSE == M0P_PCNT->SR2_f.B2C) + { + break; + } + } + if(u32TimeOut == 0) + { + return ErrorTimeout; + } + return Ok; +} + +/** + * \brief + * 获å–PCNTè®¡æ•°æ–¹å‘ + * \param [in] + * + * \retval æ—  + */ +en_pcnt_direcsel_t PCNT_Direction(void) +{ + return (en_pcnt_direcsel_t)M0P_PCNT->SR1_f.DIR; +} + +/** + * \brief + * 获å–PCNT计数值 + * \param [in] + * + * \retval æ—  + */ +uint16_t PCNT_Count(void) +{ + return M0P_PCNT->CNT; +} + +/** + * \brief + * 获å–PCNT溢出值 + * \param [in] + * + * \retval æ—  + */ +uint16_t PCNT_TopCount(void) +{ + return M0P_PCNT->TOP; +} + +/** + * \brief + * PCNT使能 + * \param [in] + * + * \retval æ—  + */ +void PCNT_Run(boolean_t work) +{ + M0P_PCNT->RUN_f.RUN = work; +} + +/** + * \brief + * PCNT 读å–çŠ¶æ€ + * \param [in] en_pcnt_status_t PCNTçŠ¶æ€ + * + * \retval æ—  + */ +boolean_t PCNT_GetStatus(en_pcnt_status_t enStatus) +{ + boolean_t bFlag = FALSE; + + ASSERT(IS_VALID_STAT(enStatus)); + + switch (enStatus) + { + case PCNT_S1E: + bFlag = M0P_PCNT->IFR_f.S1E; + break; + case PCNT_S0E: + bFlag = M0P_PCNT->IFR_f.S0E; + break; + case PCNT_BB: + bFlag = M0P_PCNT->IFR_f.BB; + break; + case PCNT_FE: + bFlag = M0P_PCNT->IFR_f.FE; + break; + case PCNT_DIR: + bFlag = M0P_PCNT->IFR_f.DIR; + break; + case PCNT_TO: + bFlag = M0P_PCNT->IFR_f.TO; + break; + case PCNT_OV: + bFlag = M0P_PCNT->IFR_f.OV; + break; + case PCNT_UF: + bFlag = M0P_PCNT->IFR_f.UF; + break; + default: + break; + } + return bFlag; +} +/** + * \brief + * PCNT æ¸…é™¤çŠ¶æ€ + * \param [in] en_pcnt_status_t PCNTçŠ¶æ€ + * + * \retval æ—  + */ +void PCNT_ClrStatus(en_pcnt_status_t enStatus) +{ + + ASSERT(IS_VALID_STAT(enStatus)); + + switch (enStatus) + { + case PCNT_S1E: + M0P_PCNT->ICR_f.S1E = 0; + break; + case PCNT_S0E: + M0P_PCNT->ICR_f.S0E = 0; + break; + case PCNT_BB: + M0P_PCNT->ICR_f.BB = 0; + break; + case PCNT_FE: + M0P_PCNT->ICR_f.FE = 0; + break; + case PCNT_DIR: + M0P_PCNT->ICR_f.DIR = 0; + break; + case PCNT_TO: + M0P_PCNT->ICR_f.TO = 0; + break; + case PCNT_OV: + M0P_PCNT->ICR_f.OV = 0; + break; + case PCNT_UF: + M0P_PCNT->ICR_f.UF = 0; + break; + default: + break; + } +} +/** + * \brief + * PCNT 中断设置 + * \param [in] en_pcnt_status_t PCNTçŠ¶æ€ + * + * \retval æ—  + */ +void PCNT_SetIrqStatus(en_pcnt_status_t enStatus) +{ + + ASSERT(IS_VALID_STAT(enStatus)); + + switch (enStatus) + { + case PCNT_S1E: + M0P_PCNT->IEN_f.S1E = 1; + break; + case PCNT_S0E: + M0P_PCNT->IEN_f.S0E = 1; + break; + case PCNT_BB: + M0P_PCNT->IEN_f.BB = 1; + break; + case PCNT_FE: + M0P_PCNT->IEN_f.FE = 1; + break; + case PCNT_DIR: + M0P_PCNT->IEN_f.DIR = 1; + break; + case PCNT_TO: + M0P_PCNT->IEN_f.TO = 1; + break; + case PCNT_OV: + M0P_PCNT->IEN_f.OV = 1; + break; + case PCNT_UF: + M0P_PCNT->IEN_f.UF = 1; + break; + default: + break; + } +} +//@} // OPAGroup + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/reset.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/reset.c new file mode 100644 index 0000000000..8dd5ca06d7 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/reset.c @@ -0,0 +1,163 @@ +/****************************************************************************** +*Copyright(C)2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file reset.c + ** + ** Common API of reset. + ** @link resetGroup Some description @endlink + ** + ** - 2017-05-04 + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "reset.h" + +/** + ******************************************************************************* + ** \addtogroup ResetGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief 获å–å¤ä½æºç±»åž‹. + ** + ** \param [out] pstcOut å¤ä½æºç±»åž‹åˆ—表 + ** + ** \retval Ok æ“作æˆåŠŸ + ** 其他 æ“作失败 + ******************************************************************************/ +en_result_t Reset_GetCause(stc_reset_cause_t *pstcOut) +{ + uint8_t u8val = 0; + if (NULL == pstcOut) + { + return ErrorInvalidParameter; + } + + u8val = M0P_RESET->RESET_FLAG; + + *pstcOut = *((stc_reset_cause_t*)&u8val); + return Ok; +} + +/** + ******************************************************************************* + ** \brief 清除å¤ä½æºç±»åž‹. + ** + ** \param [in] stcval å¤ä½æºç±»åž‹åˆ—表,æ¯ç§ç±»åž‹å¯¹åº”的比特ä½å†™â€œ0â€æ¸…除，写“1â€æ— æ•ˆ + ** + ** \retval Ok æ“作æˆåŠŸ + ** 其他 æ“作失败 + ******************************************************************************/ +en_result_t Reset_Clear(stc_reset_cause_t stcval) +{ + uint8_t u8val = *((uint8_t*)&stcval); + + M0P_RESET->RESET_FLAG = u8val; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief 设置外设å¤ä½æºå¼€å…³. + ** + ** \param [in] enPeri å¤ä½æºç±»åž‹åˆ—表 + ** \param [in] bFlag å¤ä½å¼€å…³ + ** + ** \retval Ok æ“作æˆåŠŸ + ** 其他 æ“作失败 + ******************************************************************************/ +en_result_t Reset_SetPeripheralReset(en_reset_peripheral_t enPeri, boolean_t bFlag) +{ + + bFlag = !!bFlag; + + if(TRUE == bFlag) + { + M0P_RESET->PREI_RESET |= (uint32_t)enPeri; + } + else + { + M0P_RESET->PREI_RESET &= ~(uint32_t)enPeri; + } + + return Ok; +} + +//@} // ResetGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + + diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/rng.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/rng.c new file mode 100644 index 0000000000..8ec6c08531 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/rng.c @@ -0,0 +1,191 @@ +/****************************************************************************** +*Copyright(C)2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file rng.c + ** + ** Common API of rng. + ** @link flashGroup Some description @endlink + ** + ** - 2018-05-08 + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "rng.h" +/** + ******************************************************************************* + ** \addtogroup FlashGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ***************************************************************************** + ** \brief éšæœºæ•°åˆå§‹åŒ–(上电第一次生æˆéšæœºæ•°ï¼‰ + ** + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +en_result_t Rng_Init(void) +{ + //==>>生æˆ64bitséšæœºæ•°ï¼ˆä¸Šç”µç¬¬ä¸€æ¬¡ï¼‰ + M0P_RNG->CR_f.RNGCIR_EN = 1; + //模å¼é…ç½®0 + M0P_RNG->MODE_f.LOAD = 1; + M0P_RNG->MODE_f.FDBK = 1; + M0P_RNG->MODE_f.CNT = 6; + //生æˆéšæœºæ•°0 + M0P_RNG->CR_f.RNG_RUN = 1; + while(M0P_RNG->CR_f.RNG_RUN) + { + ; + } + + //模å¼é…ç½®1 + M0P_RNG->MODE_f.LOAD = 0; + M0P_RNG->MODE_f.FDBK = 0; + M0P_RNG->MODE_f.CNT = 4; + //生æˆéšæœºæ•°1 + M0P_RNG->CR_f.RNG_RUN = 1; + while(M0P_RNG->CR_f.RNG_RUN) + { + ; + } + + //关闭éšæœºæºç”µè·¯ï¼ŒèŠ‚çœåŠŸè€— + M0P_RNG->CR_f.RNGCIR_EN = 0; + + return Ok; +} + +/** + ***************************************************************************** + ** \brief 生æˆéšæœºæ•°ï¼ˆéžä¸Šç”µç¬¬ä¸€æ¬¡ç”Ÿæˆéšæœºæ•°ï¼‰ + ** + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +en_result_t Rng_Generate(void) +{ + //==>>生æˆ64bitséšæœºæ•°ï¼ˆéžä¸Šç”µç¬¬ä¸€æ¬¡ç”Ÿæˆï¼‰ + M0P_RNG->CR_f.RNGCIR_EN = 1; + + //模å¼é…ç½®0 + M0P_RNG->MODE_f.LOAD = 0; + M0P_RNG->MODE_f.FDBK = 1; + M0P_RNG->MODE_f.CNT = 6; + //生æˆéšæœºæ•°0 + M0P_RNG->CR_f.RNG_RUN = 1; + while(M0P_RNG->CR_f.RNG_RUN) + { + ; + } + + //模å¼é…ç½®1 + M0P_RNG->MODE_f.FDBK = 0; + M0P_RNG->MODE_f.CNT = 4; + M0P_RNG->MODE_f.CNT = 4; + //生æˆéšæœºæ•°1 + M0P_RNG->CR_f.RNG_RUN = 1; + while(M0P_RNG->CR_f.RNG_RUN) + { + ; + } + + //关闭éšæœºæºç”µè·¯ï¼ŒèŠ‚çœåŠŸè€— + M0P_RNG->CR_f.RNGCIR_EN = 0; + + return Ok; +} + +/** + ***************************************************************************** + ** \brief éšæœºæ•°èŽ·å– + ** + ** \retval data0 + *****************************************************************************/ +uint32_t Rng_GetData0(void) +{ + return M0P_RNG->DATA0; +} + +/** + ***************************************************************************** + ** \brief éšæœºæ•°èŽ·å– + ** + ** \retval data1 + *****************************************************************************/ +uint32_t Rng_GetData1(void) +{ + return M0P_RNG->DATA1; +} + +//@} // RngGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/rtc.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/rtc.c new file mode 100644 index 0000000000..f6e1025edd --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/rtc.c @@ -0,0 +1,875 @@ +/************************************************************************************* +* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file rtc.c + ** + ** RTC function driver API. + ** @link SampleGroup Some description @endlink + ** + ** - 2017-05-17 1.0 CJ First version for Device Driver Library of Module. + ** + ******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "rtc.h" +/** + ****************************************************************************** + ** \addtogroup RtcGroup + ******************************************************************************/ +//@{ + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ +#define IS_VALID_CLK(x) (RtcClk32768 == (x)||\ + RtcClk32768_1== (x)||\ + RtcClk32 == (x)||\ + RtcClk32_1 == (x)||\ + RtcClkHxt128 == (x)||\ + RtcClkHxt256 == (x)||\ + RtcClkHxt512 == (x)||\ + RtcClkHxt1024 == (x)) + +#define IS_VALID_CYCSEL(x) (RtcPrads == (x)||\ + RtcPradx==(x)) + +#define IS_VALID_PRDS(x) (Rtc_None == (x)||\ + Rtc_05S == (x)||\ + Rtc_1S == (x)||\ + Rtc_1Min == (x)||\ + Rtc_1H == (x)||\ + Rtc_1Day == (x)||\ + Rtc_1Mon == (x)||\ + Rtc_1Mon_1 == (x)) + +#define IS_VALID_IRQ_SEL(x) (RtcPrdf == (x) ||\ + RtcAlmf == (x)) + +#define IS_VALID_FUNC(x) ((RtcCount==(x))||\ + (RtcAlarmEn==(x))||\ + (Rtc_ComenEn==(x))||\ + (Rtc1HzOutEn==(x))) +#define CkDateTime 0x7F +#define CkDate 0x78 +#define CkTime 0x07 + +//#define DecToBcd(x) ((((x)/10)<<4) + ((x)%10)) +//#define BcdToDec(x) ((((x)>>4)*10) + ((x)&0x0F)) + +#define RTC_TIMEOUT 1000//test 1s + +/******************************************************************************/ +/* Local function prototypes ('const') */ +/******************************************************************************/ +const uint8_t Leap_Month_Base[] = {3,6,0,3,5,1,3,6,2,4,0,2}; +const uint8_t NonLeap_Month_Base[] = {4,0,0,3,5,1,3,6,2,4,0,2}; +const uint8_t Cnst_Month_Tbl[12]={0x31,0x28,0x31,0x30,0x31,0x30,0x31,0x31,0x30,0x31,0x30,0x31}; +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ +static stc_rtc_intern_cb_t* RtcGetInternDataCb(void); +/******************************************************************************/ +/* Local variable prototypes ('static') */ +/******************************************************************************/ +static stc_rtc_intern_cb_t stcRtcIrqCb = {NULL, NULL}; +/** + ****************************************************************************** + ** \brief RTC计数时钟选择 + ** + ** \param [in] enClkæ—¶é’Ÿæº + ** + ** \retval Ok + ** + ******************************************************************************/ +en_result_t Rtc_SelClk(en_rtc_clk_t enClk) +{ + en_result_t enRet = Error; + ASSERT(IS_VALID_CLK(enClk)); + M0P_RTC->CR1_f.CKSEL = enClk; + enRet = Ok; + return enRet; +} +/** + ****************************************************************************** + ** \brief RTC周期中断方å¼é€‰æ‹© + ** + ** \param [in] pstccCyc周期中断方å¼åŠå‘¨æœŸé—´éš”选择 + ** + ** \retval Ok + ** + ******************************************************************************/ +en_result_t Rtc_SetCyc(stc_rtc_cyc_sel_t* pstcCyc) +{ + en_result_t enRet = Error; + ASSERT(IS_VALID_CYCSEL(pstcCyc->enCyc_sel)); + ASSERT(IS_VALID_PRDS(pstcCyc->enPrds_sel)); + M0P_RTC->CR0_f.PRDSEL = pstcCyc->enCyc_sel; + if(pstcCyc->enCyc_sel) + { + M0P_RTC->CR0_f.PRDX = pstcCyc->u8Prdx; + } + else + { + M0P_RTC->CR0_f.PRDS = pstcCyc->enPrds_sel; + } + enRet = Ok; + return enRet; +} +/** + ****************************************************************************** + ** \brief RTC时制选择 + ** + ** \param [in] bmode是12时制or24时制 + ** + ** \retval Ok 设置正常 + ** \retval ErrorInvalidParameter 设置异常 + ******************************************************************************/ +en_result_t Rtc_SetAmPm(en_rtc_ampm_t enMode) +{ + en_result_t enRet = Error; + switch(enMode) + { + case 0: + case 1: + M0P_RTC->CR0_f.AMPM = enMode; + break; + default: + return ErrorInvalidParameter; + } + enRet = Ok; + return enRet; +} +/** + ****************************************************************************** + ** \brief RTCæ—¶åˆ¶èŽ·å– + ** + ** \param [in] æ—  + ** + ** \retval 时制 + ******************************************************************************/ +boolean_t Rtc_GetHourMode(void) +{ + return(M0P_RTC->CR0_f.AMPM); +} +/** + ****************************************************************************** + ** \brief RTC闹钟中断设置 + ** + ** \param [in] pstcAlarmTime闹钟时间时ã€åˆ†ã€å‘¨ + ** + ** \retval Ok 设置正常 + ** + ******************************************************************************/ +en_result_t Rtc_SetAlarmTime(stc_rtc_alarmset_t* pstcAlarmTime) +{ + en_result_t enRet = Ok; + ASSERT(NULL != pstcAlarmTime); + if(Rtc12h == M0P_RTC->CR0_f.AMPM) + { + enRet = Check_BCD_Format(pstcAlarmTime->u8Hour,0x00,0x12); + } + else + { + enRet = Check_BCD_Format(pstcAlarmTime->u8Hour,0x00,0x24); + } + if(enRet != Ok) + { + return enRet; + } + enRet = Check_BCD_Format(pstcAlarmTime->u8Minute,0x00,0x59); + if(enRet != Ok) + { + return enRet; + } + // enRet = Check_BCD_Format(pstcAlarmTime->u8Week,0x00,0x06); + if(enRet != Ok) + { + return enRet; + } + M0P_RTC->ALMHOUR = pstcAlarmTime->u8Hour; + M0P_RTC->ALMMIN = pstcAlarmTime->u8Minute; + M0P_RTC->ALMWEEK = pstcAlarmTime->u8Week; + enRet = Ok; + return enRet; +} +/** + ****************************************************************************** + ** \brief RTCé—¹é’Ÿä¸­æ–­æ—¶é—´èŽ·å– + ** + ** \param [in] pstcAlarmTime闹钟时间时ã€åˆ†ã€å‘¨ + ** + ** \retval Ok 设置正常 + ** + ******************************************************************************/ +en_result_t Rtc_GetAlarmTime(stc_rtc_alarmset_t* pstcAlarmTime) +{ + en_result_t enRet = Error; + ASSERT(NULL != pstcAlarmTime); + pstcAlarmTime->u8Minute = M0P_RTC->ALMMIN; + pstcAlarmTime->u8Hour = M0P_RTC->ALMHOUR; + pstcAlarmTime->u8Week = M0P_RTC->ALMWEEK; + enRet = Ok; + return enRet; +} +/** + ****************************************************************************** + ** \brief RTC 1hz模å¼é€‰æ‹© + ** + ** \param [in] bmode 高精度和普通精度 + ** + ** \retval Ok 设置正常 + ** + ******************************************************************************/ +en_result_t Rtc_Set1HzMode(boolean_t bMode) +{ + en_result_t enRet = Error; + M0P_RTC->CR0_f.HZ1SEL = bMode; + enRet = Ok; + return enRet; +} +/** + ****************************************************************************** + ** \brief RTC 1hzè¡¥å¿å€¼è®¾ç½® + ** + ** \param [in] u16Cr è¡¥å¿å€¼ + ** + ** \retval Ok 设置正常 + ** + ******************************************************************************/ +en_result_t Rtc_SetCompCr(uint16_t u16Cr) +{ + en_result_t enRet = Error; + M0P_RTC->COMPEN_f.CR = u16Cr; + enRet = Ok; + return enRet; +} +/** + ****************************************************************************** + ** \brief RTC 功能使能设置 + ** + ** \param [in] enFunc 功能选择 + ** + ** \retval Ok 设置正常 + ** \retval ErrorInvalidParameter 设置异常 + ******************************************************************************/ +en_result_t Rtc_EnableFunc(en_rtc_func_t enFunc) +{ + ASSERT(IS_VALID_FUNC(enFunc)); + switch(enFunc) + { + case RtcCount: + M0P_RTC->CR0_f.START = 1u; + break; + case RtcAlarmEn: + M0P_RTC->CR1_f.ALMEN = 1u; + break; + case Rtc_ComenEn: + M0P_RTC->COMPEN_f.EN = 1u; + break; + case Rtc1HzOutEn: + M0P_RTC->CR0_f.HZ1OE = 1u; + break; + default: + return ErrorInvalidParameter; + } + return Ok; +} +/** + ****************************************************************************** + ** \brief RTC 功能ç¦æ­¢è®¾ç½® + ** + ** \param [in] enFunc 功能选择 + ** + ** \retval Ok 设置正常 + ** \retval ErrorInvalidParameter 设置异常 + ******************************************************************************/ +en_result_t Rtc_DisableFunc(en_rtc_func_t enFunc) +{ + ASSERT(IS_VALID_FUNC(enFunc)); + switch(enFunc) + { + case RtcCount: + M0P_RTC->CR0_f.START = 0u; + break; + case RtcAlarmEn: + M0P_RTC->CR1_f.ALMEN = 0u; + break; + case Rtc_ComenEn: + M0P_RTC->COMPEN_f.EN = 0u; + break; + case Rtc1HzOutEn: + M0P_RTC->CR0_f.HZ1OE = 0u; + break; + default: + return ErrorInvalidParameter; + } + return Ok; +} +uint8_t Change_DateTimeFormat(uint8_t u8sr) +{ + uint8_t u8de=0; + while(u8sr>=0x10) + { + u8de +=10; + u8sr -=0x10; + } + u8de += u8sr; + return(u8de); +} +/** + ****************************************************************************** + ** \brief RTC å¹³ã€é—°å¹´æ£€æµ‹ + ** + ** \param [in] u8year å¹´åè¿›åˆ¶ä½Žä¸¤ä½ + ** + ** \retval 1 é—°å¹´ + ** \retval 0 平年 + ******************************************************************************/ +uint8_t Rtc_CheckLeapYear(uint8_t u8year) +{ + uint8_t u8year_shl,u8year_shr; + u8year_shl = u8year>>2; + u8year_shr = u8year_shl<<2; + if(u8year== u8year_shr) + { + return 1; + } + else + { + return 0; + } +} +/** + ****************************************************************************** + ** \brief RTCæ ¹æ®æ—¥æœŸè®¡ç®—周数 + ** + ** \param [in] pu8Date日期 + ** + ** \retval week 周数 + ** + ******************************************************************************/ +uint8_t Rtc_CalWeek(uint8_t* pu8Date) +{ + uint8_t u8week; + if((Rtc_CheckLeapYear(Change_DateTimeFormat(*(pu8Date+2)))==1)) + { + u8week = (Change_DateTimeFormat(*(pu8Date+2))+Change_DateTimeFormat(*(pu8Date+2))/4+Leap_Month_Base[Change_DateTimeFormat(*(pu8Date+1))-1]+Change_DateTimeFormat(*(pu8Date))+2)%7; + } + else + { + u8week = (Change_DateTimeFormat(*(pu8Date+2))+Change_DateTimeFormat(*(pu8Date+2))/4+NonLeap_Month_Base[Change_DateTimeFormat(*(pu8Date+1))-1]+Change_DateTimeFormat(*(pu8Date))+2)%7; + } + return u8week; +} +/** + ****************************************************************************** + ** \brief RTCæ ¹æ®å¹´æœˆèŽ·å–天数 + ** + ** \param [in] u8month月份，u8year年份 + ** + ** \retval u8day天数 + ** + ******************************************************************************/ +uint8_t Get_Month_Max_Day(uint8_t u8month, uint8_t u8year) +{ + uint8_t u8day = 0; + + u8day = Cnst_Month_Tbl[u8month - 1]; + if((u8month == 2) && ((u8year % 4) == 0)) + { + u8day++; + } + return(u8day);//dayçš„æ ¼å¼æ˜¯bcdç ï¼Œä¾‹å¦‚；日为31天，day=0x31 +} +/** + ****************************************************************************** + ** \brief RTCæ ¹æ®æ—¥æœŸè®¡ç®—周数 + ** + ** \param [in] pu8buf日期时间数æ®ï¼Œu8len检查数æ®é•¿åº¦ï¼Œu8limit_min最å°å€¼ï¼Œu8limit_max最大值 + ** + ** \retval Error 错误，Ok校验正确 + ** + ******************************************************************************/ +en_result_t Check_BCD_Format(uint8_t u8data,uint8_t u8limit_min, uint8_t u8limit_max) +{ + + if (((u8data & 0x0F) > 0x09) || ((u8data & 0xF0) > 0x90) + ||(u8data > u8limit_max) || (u8data < u8limit_min)) + { + return Error; + } + return Ok; +} +/** + ****************************************************************************** + ** \brief RTC时间格å¼æ£€æµ‹ + ** + ** \param [in] pu8TimeDate日期时间数æ®ï¼Œu8Modeæ£€æµ‹æ¨¡å¼ + ** + ** \retval enRet校验结果 + ** + ******************************************************************************/ +en_result_t Rtc_CheckDateTimeFormat(uint8_t* pu8TimeDate,uint8_t u8Mode) +{ + uint8_t u8i=0; + uint8_t u8mon_max_day = 0x28; + uint8_t u8date[3]; + uint8_t u8Hour = 0; + en_result_t enRet=Error; + while(u8i<7) + { + if(u8Mode&&(1<CR0_f.AMPM) + { + u8Hour = *pu8TimeDate&0x1f; + enRet = Check_BCD_Format(u8Hour,0x00,0x12);//æ—¶ + } + else + { + enRet = Check_BCD_Format(*pu8TimeDate,0x00,0x24); + } + break; + case 3: + enRet = Check_BCD_Format(*pu8TimeDate,0x00,0x06); + break; + case 4: + enRet = Check_BCD_Format(*pu8TimeDate,0x00,0x31); + u8date[0] = *pu8TimeDate; + break; + case 5: + enRet = Check_BCD_Format(*pu8TimeDate,0x00,0x12); + u8date[1] = *pu8TimeDate; + break; + case 6: + enRet = Check_BCD_Format(*pu8TimeDate,0x00,0x99); + u8date[2] = *pu8TimeDate; + break; + default: + break; + } + pu8TimeDate++; + } + if(enRet!=Ok) + { + return enRet; + } + u8i++; + } + if((u8Mode&0x10)&&(u8Mode&0x20)) + { + if(u8Mode&0x40) + { + u8mon_max_day = Get_Month_Max_Day(Change_DateTimeFormat(u8date[1]), Change_DateTimeFormat(u8date[2])); + } + else + { + u8mon_max_day = Get_Month_Max_Day(Change_DateTimeFormat(u8date[1]), 1); + } + if(u8date[0]>u8mon_max_day) + { + return Error; + } + } + if((u8Mode&0x10)&&(!(u8Mode&0x20))) + { + if(u8date[0]>0x28) + { + return Error; + } + } + enRet = Ok; + return(enRet); +} +/** + ****************************************************************************** + ** \brief RTC设置时间函数 + ** + ** \param [in] pstcTimeDate日期时间数æ®ã€bUpdateTime是å¦æ›´æ”¹æ—¶é—´ã€bUpdateDate是å¦æ›´æ”¹æ—¥æœŸ + ** + ** \retval Ok 设置正常 + ** \retval ErrorTimeout 时间溢出错误 + ******************************************************************************/ +en_result_t Rtc_WriteDateTime(stc_rtc_time_t* pstcTimeDate,boolean_t bUpdateTime, + boolean_t bUpdateDate) +{ + int32_t u32TimeOut; + uint8_t* pu8TimeDate; + en_result_t enRet = Ok; + u32TimeOut = RTC_TIMEOUT; + pu8TimeDate = &pstcTimeDate->u8Second; + ASSERT(NULL != pstcTimeDate); + if(1 == M0P_RTC->CR0_f.START) + { + M0P_RTC->CR1_f.WAIT = 1; + while(--u32TimeOut) + { + if(M0P_RTC->CR1_f.WAITF) + { + break; + } + } + if(u32TimeOut==0) + { + return ErrorTimeout; + } + } + if(TRUE == bUpdateTime) + { + enRet = Rtc_CheckDateTimeFormat(pu8TimeDate,CkTime); + if(enRet != Ok) + { + return enRet; + } + M0P_RTC->SEC = pstcTimeDate->u8Second; + M0P_RTC->MIN = pstcTimeDate->u8Minute; + M0P_RTC->HOUR = pstcTimeDate->u8Hour; + } + if(TRUE == bUpdateDate) + { + enRet = Rtc_CheckDateTimeFormat(pu8TimeDate,CkDate); + if(enRet != Ok) + { + return enRet; + } + M0P_RTC->DAY = pstcTimeDate->u8Day; + M0P_RTC->MON = pstcTimeDate->u8Month; + M0P_RTC->YEAR = pstcTimeDate->u8Year; + M0P_RTC->WEEK = pstcTimeDate->u8DayOfWeek; + } + M0P_RTC->CR1_f.WAIT = 0; + if(1 == M0P_RTC->CR0_f.START) + { + while(M0P_RTC->CR1_f.WAITF) + {} + } + return enRet; +} +/** + ****************************************************************************** +** \brief RTC 12å°æ—¶ä¸Šåˆæˆ–下åˆèŽ·å– + ** + ** \param [in] æ—  + ** +** \retval 上åˆæˆ–ä¸‹åˆ + ******************************************************************************/ +boolean_t Rtc_RDAmPm(void) +{ + boolean_t bRet; + + bRet = M0P_RTC->HOUR&0x20; + bRet>>=5; + return bRet; +} +/** + ****************************************************************************** + ** \brief RTC获å–时间函数 + ** + ** \param [in] pstcTimeDateæ—¥æœŸæ—¶é—´æ•°æ® + ** + ** \retval Ok 获å–正常 + ** \retval ErrorTimeout 时间溢出错误 + ******************************************************************************/ +en_result_t Rtc_ReadDateTime(stc_rtc_time_t* pstcTimeDate) +{ + uint32_t u32TimeOut; + uint8_t u8DayOfWeek, u8BcdSec, u8BcdMin, u8BcdHour, u8Day, u8Month, u8Year; + + ASSERT(NULL != pstcTimeDate); + u32TimeOut = RTC_TIMEOUT; + if(1 == M0P_RTC->CR0_f.START) + { + M0P_RTC->CR1_f.WAIT = 1; + while(u32TimeOut--) + { + if(M0P_RTC->CR1_f.WAITF) + { + break; + } + } + if(u32TimeOut==0) + { + return ErrorTimeout; + } + } + u8BcdSec = M0P_RTC->SEC; + u8BcdMin = M0P_RTC->MIN; + u8BcdHour = M0P_RTC->HOUR; + u8Day = M0P_RTC->DAY; + u8Month = M0P_RTC->MON; + u8Year = M0P_RTC->YEAR; + u8DayOfWeek = M0P_RTC->WEEK; + + pstcTimeDate->u8Second = u8BcdSec; + pstcTimeDate->u8Minute = u8BcdMin; + if(1 == M0P_RTC->CR0_f.AMPM) + { + pstcTimeDate->u8Hour = u8BcdHour; + } + else + { + pstcTimeDate->u8Hour = u8BcdHour&0x1f; + } + pstcTimeDate->u8Day = u8Day; + pstcTimeDate->u8Month = u8Month; + pstcTimeDate->u8Year = u8Year; + pstcTimeDate->u8DayOfWeek = u8DayOfWeek; + + M0P_RTC->CR1_f.WAIT = 0; + if(1 == M0P_RTC->CR0_f.START) + { + while(M0P_RTC->CR1_f.WAITF) + {} + } + + return Ok; +} +/** + ****************************************************************************** + ** \brief RTC计数or读写状æ€èŽ·å– + ** + ** \param [in] æ—  + ** + ** \retval 计数orè¯»å†™çŠ¶æ€ + ** + ******************************************************************************/ +boolean_t Rtc_RDStatus(void) +{ + boolean_t bRet; + bRet = M0P_RTC->CR1_f.WAITF; + return bRet; +} +/** + ****************************************************************************** + ** \brief RTC闹钟中断使能 + ** + ** \param [in] enordis中断使能orç¦æ­¢ + ** + ** \retval Ok设置æˆåŠŸ + ** + ******************************************************************************/ +en_result_t Rtc_EnAlarmIrq(en_rtc_alarmirq_t enIrqEn) +{ + en_result_t enRet = Error; + M0P_RTC->CR1_f.ALMIE = enIrqEn; + Rtc_ClrIrqStatus(RtcAlmf);//使能中断åŽæ¸…除中断请求标记 + enRet = Ok; + return enRet; +} +/** + ****************************************************************************** + ** \brief RTC中断请求状æ€èŽ·å– + ** + ** \param [in] enIrqSel获å–哪ç§ä¸­æ–­è¯·æ±‚ + ** + ** \retval ä¸­æ–­è¯·æ±‚çŠ¶æ€ + ** + ******************************************************************************/ +boolean_t Rtc_GetIrqStatus(en_rtc_status_irq_t enIrqSel) +{ + boolean_t bRet = FALSE; + ASSERT(IS_VALID_IRQ_SEL(enIrqSel)); + switch(enIrqSel) + { + case RtcPrdf: + (M0P_RTC->CR1_f.PRDF == 1)?(bRet = TRUE) : (bRet = FALSE); + break; + case RtcAlmf : + (M0P_RTC->CR1_f.ALMF == 1)?(bRet = TRUE) : (bRet = FALSE); + break; + default: + break; + } + return bRet; +} +/** + ****************************************************************************** + ** \brief RTC中断请求清除 + ** + ** \param [in] enIrqSel清除哪ç§ä¸­æ–­è¯·æ±‚ + ** + ** \retval Ok 清除æˆåŠŸ + ** \retval ErrorInvalidParameter 清除失败 + ******************************************************************************/ +en_result_t Rtc_ClrIrqStatus(en_rtc_status_irq_t enIrqSel) +{ + ASSERT(IS_VALID_IRQ_SEL(enIrqSel)); + switch(enIrqSel) + { + case RtcPrdf: + M0P_RTC->CR1_f.PRDF = 0; + break; + case RtcAlmf: + M0P_RTC->CR1_f.ALMF = 0; + break; + default: + return ErrorInvalidParameter; + } + return Ok; +} + +/** + ****************************************************************************** + ** \brief RTC中断处ç†å‡½æ•°æŽ¥å£èŽ·å– + ** + ** \param [in] æ—  + ** + ** \retval 接å£å‡½æ•°åœ°å€ + ** + ******************************************************************************/ +static stc_rtc_intern_cb_t* RtcGetInternDataCb(void) +{ + return &stcRtcIrqCb; +} +/** + ****************************************************************************** + ** \brief RTC总体åˆå§‹åŒ–函数 + ** + ** \param [in] pstcRtcConfigåˆå§‹åŒ–结构 + ** + ** \retval Okåˆå§‹åŒ–æˆåŠŸ + ** \retval ErrorInvalidParameter åˆå§‹åŒ–错误 + ******************************************************************************/ +en_result_t Rtc_Init(stc_rtc_config_t* pstcRtcConfig) +{ + en_result_t enRet = Error; + stc_rtc_intern_cb_t* pstcRtcInternCb; + if(NULL == pstcRtcConfig) + { + return Error; + } + pstcRtcInternCb = RtcGetInternDataCb(); + enRet = Rtc_SelClk(pstcRtcConfig->enClkSel); + enRet = Rtc_SetAmPm(pstcRtcConfig->enAmpmSel); + if(enRet != Ok) + { + return enRet; + } + if(NULL != pstcRtcConfig->pstcCycSel) + { + if(Ok != Rtc_SetCyc(pstcRtcConfig->pstcCycSel)) + { + return Error; + } + } + if(NULL != pstcRtcConfig->pstcTimeDate) + { + if(Ok != Rtc_WriteDateTime(pstcRtcConfig->pstcTimeDate,TRUE,TRUE)) + { + return Error; + } + } + if(NULL != pstcRtcConfig->pstcIrqCb) + { + pstcRtcInternCb->pfnAlarmIrqCb = pstcRtcConfig->pstcIrqCb->pfnAlarmIrqCb; + pstcRtcInternCb->pfnTimerIrqCb = pstcRtcConfig->pstcIrqCb->pfnTimerIrqCb; + } + if(TRUE == pstcRtcConfig->bTouchNvic) + { + EnableNvic(RTC_IRQn,IrqLevel3,TRUE); + } + else + { + EnableNvic(RTC_IRQn,IrqLevel3,FALSE); + } + return enRet; +} +/** + ****************************************************************************** + ** \brief RTC计数ç¦æ­¢å‡½æ•° + ** + ** \param [in] æ—  + ** + ** \retval Okç¦æ­¢è®¾ç½®æˆåŠŸ + ** + ******************************************************************************/ +en_result_t Rtc_DeInit(void) +{ + EnableNvic(RTC_IRQn,IrqLevel3,FALSE); + Rtc_DisableFunc(RtcCount); + Rtc_DisableFunc(RtcAlarmEn); + Rtc_DisableFunc(Rtc_ComenEn); + Rtc_DisableFunc(Rtc1HzOutEn); + return Ok; +} +/** + ****************************************************************************** + ** \brief RTC中断处ç†å‡½æ•° + ** + ** \param [in] æ—  + ** + ** \retval æ—  + ** + ******************************************************************************/ +void Rtc_IRQHandler(void) +{ + stc_rtc_intern_cb_t* pstcRtcInternCb; + pstcRtcInternCb = RtcGetInternDataCb() ; + if(TRUE == M0P_RTC->CR1_f.ALMF) + { + M0P_RTC->CR1_f.ALMF = 0u; + if(NULL != pstcRtcInternCb->pfnAlarmIrqCb) + { + pstcRtcInternCb->pfnAlarmIrqCb(); + } + } + if(TRUE == M0P_RTC->CR1_f.PRDF) + { + M0P_RTC->CR1_f.PRDF = 0; + if(NULL != pstcRtcInternCb->pfnTimerIrqCb) + { + pstcRtcInternCb->pfnTimerIrqCb(); + } + } +} +//@} // RtcGroup diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/spi.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/spi.c new file mode 100644 index 0000000000..8b9e8e6626 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/spi.c @@ -0,0 +1,526 @@ +/****************************************************************************** +* Copyright (C) 2016, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with eaenCh copy of this software, whether used in part or whole, +* at all times. +*/ +/*****************************************************************************/ +/** \file spi.c + ** + ** SPI driver API. + ** @link Driver Group Some description @endlink + ** + ** - 2018-05-17 1.0 Devi First version for Device Driver Library of + ** Module. + ** + *****************************************************************************/ + +/****************************************************************************** + * Include files + *****************************************************************************/ +#include "spi.h" + +/** + ****************************************************************************** + ** \addtogroup SpiGroup + *****************************************************************************/ +//@{ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + *****************************************************************************/ + +#define IS_VALID_STAT(x) ( SpiIf == (x)||\ + SpiSserr == (x)||\ + SpiBusy == (x)||\ + SpiMdf == (x)||\ + SpiTxe == (x)||\ + SpiRxne == (x)) +#define IS_VALID_CH(x) ( Spi0 == (x)||\ + Spi1 == (x)) + + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local variable prototypes ('static') */ +/******************************************************************************/ +static func_ptr_t pfnSpi0Callback = NULL; ///< callback function pointer for SPI Irq +static func_ptr_t pfnSpi1Callback = NULL; ///< callback function pointer for SPI Irq +/** + ****************************************************************************** + ** \brief SPI 中断处ç†å‡½æ•° + ** + ** \param [in] enChé€šé“ + ** + ** \retval æ—  + ** + ******************************************************************************/ +void Spi_IRQHandler(en_spi_channel_t enCh) +{ + if(Spi0 == enCh) + { + if(NULL != pfnSpi0Callback) + { + pfnSpi0Callback(); + } + } + else + { + if(NULL != pfnSpi1Callback) + { + pfnSpi1Callback(); + } + + } +} +/** + ****************************************************************************** + ** \brief SPI 请求状æ€èŽ·å– + ** + ** \param [in]enCh é€šé“ + ** + ** \retval è¯·æ±‚çŠ¶æ€ + ** + ******************************************************************************/ +uint8_t Spi_GetState(en_spi_channel_t enCh) +{ + uint8_t u8State = 0; + ASSERT(IS_VALID_CH(enCh)); + if(Spi0 == enCh) + { + u8State = M0P_SPI0->STAT; + } + else + { + u8State = M0P_SPI1->STAT; + } + return u8State; +} +/** + ****************************************************************************** + ** \brief SPI 请求状æ€èŽ·å– + ** + ** \param [in]enCh 通é“， enStatus 获å–请求 + ** + ** \retval è¯·æ±‚çŠ¶æ€ + ** + ******************************************************************************/ +boolean_t Spi_GetStatus(en_spi_channel_t enCh,en_spi_status_t enStatus) +{ + boolean_t bFlag = FALSE; + ASSERT(IS_VALID_CH(enCh)); + ASSERT(IS_VALID_STAT(enStatus)); + if(Spi0 == enCh) + { + switch (enStatus) + { + case SpiIf: + bFlag = M0P_SPI0->STAT_f.SPIF; + break; + case SpiSserr: + bFlag = M0P_SPI0->STAT_f.SSERR; + break; + case SpiMdf: + bFlag = M0P_SPI0->STAT_f.MDF; + break; + case SpiBusy: + bFlag = M0P_SPI0->STAT_f.BUSY; + break; + case SpiTxe: + bFlag = M0P_SPI0->STAT_f.TXE; + break; + case SpiRxne: + bFlag = M0P_SPI0->STAT_f.RXNE; + break; + default: + break; + } + } + else + { + switch (enStatus) + { + case SpiIf: + bFlag = M0P_SPI1->STAT_f.SPIF; + break; + case SpiSserr: + bFlag = M0P_SPI1->STAT_f.SSERR; + break; + case SpiMdf: + bFlag = M0P_SPI1->STAT_f.MDF; + break; + case SpiBusy: + bFlag = M0P_SPI1->STAT_f.BUSY; + break; + case SpiTxe: + bFlag = M0P_SPI1->STAT_f.TXE; + break; + case SpiRxne: + bFlag = M0P_SPI1->STAT_f.RXNE; + break; + default: + break; + } + } + return bFlag; +} +/** + ****************************************************************************** + ** \brief SPI中断清除 + ** + ** \param [in]enCh 通é“， enStatus 获å–请求 + ** + ** \retval è¯·æ±‚çŠ¶æ€ + ** + ******************************************************************************/ +en_result_t Spi_ClearStatus(en_spi_channel_t enCh) +{ + en_result_t enRet = Error; + ASSERT(IS_VALID_CH(enCh)); + if(Spi0 == enCh) + { + M0P_SPI0->ICLR_f.INT_CLR = 0; + } + else + { + M0P_SPI1->ICLR_f.INT_CLR = 0; + } + enRet = Ok; + return enRet; +} +/** + ****************************************************************************** + ** \brief SPI 功能使能ç¦æ­¢å‡½æ•° + ** + ** \param [in] enCh通é“，enFunc功能，bFlag 0/1使能或ç¦æ­¢ + ** + ** \retval Okåˆå§‹åŒ–æˆåŠŸ + ** \retval ErrorInvalidParameter åˆå§‹åŒ–错误 + ******************************************************************************/ +en_result_t Spi_FuncEn(en_spi_channel_t enCh,en_spi_func_t enFunc,boolean_t bFlag) +{ + en_result_t enRet = Error; + ASSERT(IS_VALID_CH(enCh)); + if(Spi0 == enCh) + { + switch(enFunc) + { + case SpiRxNeIe: + M0P_SPI0->CR2_f.RXNEIE = bFlag; + break; + case SpiTxEIe: + M0P_SPI0->CR2_f.TXEIE = bFlag; + break; + case SpiDmaTxEn: + M0P_SPI0->CR2_f.HDMA_TX = bFlag; + break; + case SpiDmaRxEn: + M0P_SPI0->CR2_f.HDMA_RX = bFlag; + break; + default: + return ErrorInvalidParameter; + } + } + else + { + switch(enFunc) + { + case SpiRxNeIe: + M0P_SPI1->CR2_f.RXNEIE = bFlag; + break; + case SpiTxEIe: + M0P_SPI1->CR2_f.TXEIE = bFlag; + break; + case SpiDmaTxEn: + M0P_SPI1->CR2_f.HDMA_TX = bFlag; + break; + case SpiDmaRxEn: + M0P_SPI1->CR2_f.HDMA_RX = bFlag; + break; + default: + return ErrorInvalidParameter; + } + } + enRet = Ok; + return enRet; +} +/** + ****************************************************************************** + ** \brief SPI 总体åˆå§‹åŒ–函数 + ** + ** \param [in] + enChé€šé“ + pstcSpiConfigåˆå§‹åŒ–结构 + ** + ** \retval Okåˆå§‹åŒ–æˆåŠŸ + ** \retval ErrorInvalidParameter åˆå§‹åŒ–错误 + ******************************************************************************/ +en_result_t Spi_Init(en_spi_channel_t enCh,stc_spi_config_t *pstcSpiConfig) +{ + ASSERT(NULL != pstcSpiConfig); + ASSERT(IS_VALID_CH(enCh)); + if(Spi0 == enCh) + { + M0P_SPI0->CR = 0x00; + + M0P_SPI0->CR_f.MSTR = pstcSpiConfig->bMasterMode; + M0P_SPI0->CR_f.CPOL = pstcSpiConfig->bCPOL; + M0P_SPI0->CR_f.CPHA = pstcSpiConfig->bCPHA; + if(pstcSpiConfig->u8BaudRate > SpiClkDiv16) + { + M0P_SPI0->CR_f.SPR2 = 1; + } + M0P_SPI0->CR |= (pstcSpiConfig->u8BaudRate&0x03u); + + M0P_SPI0->STAT = 0x00; + + M0P_SPI0->CR_f.SPEN = TRUE; + if (TRUE == pstcSpiConfig->bIrqEn) + { + M0P_SPI0->CR2_f.INT_EN = 1; + EnableNvic(SPI0_IRQn,IrqLevel3,TRUE); + } + else + { + EnableNvic(SPI0_IRQn,IrqLevel3,FALSE); + } + if(NULL != pstcSpiConfig->pfnSpi0IrqCb) + { + pfnSpi0Callback = pstcSpiConfig->pfnSpi0IrqCb; + } + } + else + { + M0P_SPI1->CR = 0x00; + + M0P_SPI1->CR_f.MSTR = pstcSpiConfig->bMasterMode; + M0P_SPI1->CR_f.CPOL = pstcSpiConfig->bCPOL; + M0P_SPI1->CR_f.CPHA = pstcSpiConfig->bCPHA; + if(pstcSpiConfig->u8BaudRate > SpiClkDiv16) + { + M0P_SPI1->CR_f.SPR2 = 1; + } + M0P_SPI1->CR |= (pstcSpiConfig->u8BaudRate&0x03u); + + M0P_SPI1->STAT = 0x00; + + M0P_SPI1->CR_f.SPEN = TRUE; + if (TRUE == pstcSpiConfig->bIrqEn) + { + M0P_SPI1->CR2_f.INT_EN = 1; + EnableNvic(SPI1_IRQn,IrqLevel3,TRUE); + } + else + { + EnableNvic(SPI1_IRQn,IrqLevel3,FALSE); + } + if(NULL != pstcSpiConfig->pfnSpi1IrqCb) + { + pfnSpi1Callback = pstcSpiConfig->pfnSpi1IrqCb; + } + } + return Ok; +} + +/** + ****************************************************************************** + ** \brief SPI ç¦æ­¢å‡½æ•° + ** + ** \param [in] enChé€šé“ + ** + ** \retval Okç¦æ­¢è®¾ç½®æˆåŠŸ + ** + ******************************************************************************/ +en_result_t Spi_DeInit(en_spi_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + if(Spi0 == enCh) + { + M0P_SPI0->DATA = 0x00; + M0P_SPI0->STAT = 0x00; + M0P_SPI0->CR = 0x00; + pfnSpi0Callback = NULL; + EnableNvic(SPI0_IRQn,IrqLevel3,FALSE); + } + else + { + M0P_SPI1->DATA = 0x00; + M0P_SPI1->STAT = 0x00; + M0P_SPI1->CR = 0x00; + pfnSpi1Callback = NULL; + EnableNvic(SPI1_IRQn,IrqLevel3,FALSE); + } + return Ok; +} +/** + ****************************************************************************** + ** \brief SPI é…置主å‘é€çš„电平 + ** + ** \param [in] 高低电平 + ** + ** \retval æ—  + ** + ******************************************************************************/ +void Spi_SetCS(en_spi_channel_t enCh,boolean_t bFlag) +{ + ASSERT(IS_VALID_CH(enCh)); + if(Spi0 == enCh) + { + M0P_SPI0->SSN = bFlag; + } + else + { + M0P_SPI1->SSN = bFlag; + } +} +/** + ****************************************************************************** + ** \brief SPI å‘é€ä¸€å­—节函数 + ** + ** \param [in] enCh通é“，u8Dataå‘é€å­—节 + ** + ** \retval Okå‘é€æˆåŠŸ + ** + ******************************************************************************/ +en_result_t Spi_SendData(en_spi_channel_t enCh,uint8_t u8Data) +{ + uint32_t u32TimeOut; + ASSERT(IS_VALID_CH(enCh)); + u32TimeOut = 1000; + if(Spi0 == enCh) + { + while(--u32TimeOut) + { + if(TRUE == M0P_SPI0->STAT_f.TXE) + { + break; + } + } + if(u32TimeOut == 0) + { + return ErrorTimeout; + } + M0P_SPI0->DATA = u8Data; + u32TimeOut = 1000; + while(--u32TimeOut) + { + if(TRUE == M0P_SPI0->STAT_f.RXNE) + { + break; + } + } + if(u32TimeOut == 0) + { + return ErrorTimeout; + } + u8Data = M0P_SPI0->DATA; + } + else + { + while(--u32TimeOut) + { + if(TRUE == M0P_SPI1->STAT_f.TXE) + + { + break; + } + } + if(u32TimeOut == 0) + { + return ErrorTimeout; + } + M0P_SPI1->DATA = u8Data; + u32TimeOut = 1000; + while(--u32TimeOut) + { + if(TRUE == M0P_SPI1->STAT_f.RXNE) + { + break; + } + } + if(u32TimeOut == 0) + { + return ErrorTimeout; + } + u8Data = M0P_SPI1->DATA; + } + return Ok; +} + +/** + ****************************************************************************** + ** \brief SPI 接收一字节函数 + ** + ** \param [in] enChæŽ¥æ”¶é€šé“ + ** + ** \retval æŽ¥æ”¶ä¸€å­—èŠ‚æ•°æ® + ** + ******************************************************************************/ +uint8_t Spi_ReceiveData(en_spi_channel_t enCh,boolean_t bMasterOrSlave) +{ + uint8_t temp; + ASSERT(IS_VALID_CH(enCh)); + if(Spi0 == enCh) + { + if(1 == bMasterOrSlave) + { + M0P_SPI0->DATA = 0x00; + } + while(0 == M0P_SPI0->STAT_f.RXNE){;} + temp = M0P_SPI0->DATA; + } + else + { + if(1 == bMasterOrSlave) + { + M0P_SPI1->DATA = 0x00; + } + while(0 == M0P_SPI1->STAT_f.RXNE){;} + temp = M0P_SPI1->DATA; + } + return temp; +} + +//@} // SpiGroup +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ + diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/sysctrl.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/sysctrl.c new file mode 100644 index 0000000000..c6f02cce9d --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/sysctrl.c @@ -0,0 +1,776 @@ +/****************************************************************************** +*Copyright(C)2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file sysctrl.c + ** + ** Common API of sysctrl. + ** @link SysctrlGroup Some description @endlink + ** + ** - 2018-04-22 Lux + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "sysctrl.h" + +/** + ******************************************************************************* + ** \addtogroup SysctrlGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define CLK_TIMEOUT (1000000u) + +#define IS_VALID_SRC(x) ( ClkRCH == (x)||\ + ClkXTH == (x)||\ + ClkRCL == (x)||\ + ClkXTL == (x) ) + + +#define IS_VALID_FUNC(x) ( ClkFuncWkupRCH == (x)||\ + ClkFuncXTHEn == (x)||\ + ClkFuncXTLEn == (x)||\ + ClkFuncXTLAWSON == (x)||\ + ClkFuncFaultEn == (x)||\ + ClkFuncRtcLPWEn == (x)||\ + ClkFuncLockUpEn == (x)||\ + ClkFuncRstPinIOEn == (x)||\ + ClkFuncSwdPinIOEn == (x) ) + +#define RCH_CR_TRIM_24M_VAL (*((volatile uint16_t*) (0x00100C00ul))) +#define RCH_CR_TRIM_22_12M_VAL (*((volatile uint16_t*) (0x00100C02ul))) +#define RCH_CR_TRIM_16M_VAL (*((volatile uint16_t*) (0x00100C04ul))) +#define RCH_CR_TRIM_8M_VAL (*((volatile uint16_t*) (0x00100C06ul))) +#define RCH_CR_TRIM_4M_VAL (*((volatile uint16_t*) (0x00100C08ul))) + +#define RCL_CR_TRIM_38400_VAL (*((volatile uint16_t*) (0x00100C20ul))) +#define RCL_CR_TRIM_32768_VAL (*((volatile uint16_t*) (0x00100C22ul))) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +extern uint32_t SystemCoreClock; +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief SYSCTRL0\SYSCTRL1寄存器æ“ä½œè§£é” + ** + ** \retval None + ******************************************************************************/ +static void _SysctrlUnlock(void) +{ + M0P_SYSCTRL->SYSCTRL2 = 0x5A5A; + M0P_SYSCTRL->SYSCTRL2 = 0xA5A5; +} + +/** + ******************************************************************************* + ** \brief 系统时钟æºä½¿èƒ½ + ** \param [in] enSource ç›®æ ‡æ—¶é’Ÿæº + ** \param [in] bFlag 使能1-å¼€/0-å…³ + ** \retval Ok 设定æˆåŠŸ + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_ClkSourceEnable(en_sysctrl_clk_source_t enSource, boolean_t bFlag) +{ + en_result_t enRet = Ok; + + _SysctrlUnlock(); + bFlag = !!bFlag; + + switch (enSource) + { + case SysctrlClkRCH: + M0P_SYSCTRL->SYSCTRL0_f.RCH_EN = bFlag; + while(bFlag && (1 != M0P_SYSCTRL->RCH_CR_f.STABLE)) + { + ; + } + break; + + case SysctrlClkXTH: + M0P_GPIO->PDADS_f.PD00 = 1; + M0P_GPIO->PDADS_f.PD01 = 1; + M0P_SYSCTRL->SYSCTRL0_f.XTH_EN = bFlag; + while(bFlag && (1 != M0P_SYSCTRL->XTH_CR_f.STABLE)) + { + ; + } + break; + + case SysctrlClkRCL: + M0P_SYSCTRL->SYSCTRL0_f.RCL_EN = bFlag; + while(bFlag && (1 != M0P_SYSCTRL->RCL_CR_f.STABLE)) + { + ; + } + break; + + case SysctrlClkXTL: + M0P_GPIO->PCADS_f.PC14 = 1; + M0P_GPIO->PCADS_f.PC15 = 1; + M0P_SYSCTRL->SYSCTRL0_f.XTL_EN = bFlag; + while(bFlag && (1 != M0P_SYSCTRL->XTL_CR_f.STABLE)) + { + ; + } + break; + + case SysctrlClkPLL: + M0P_SYSCTRL->SYSCTRL0_f.PLL_EN = bFlag; + while(bFlag && (1 != M0P_SYSCTRL->PLL_CR_f.STABLE)) + { + ; + } + break; + + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief 外部高速晶振驱动é…ç½® + ** \param [in] enFreq 外部高速晶振频率范围选择 + ** \param [in] enDriver 外部高速晶振驱动能力选择 + ** \retval Ok 设定æˆåŠŸ + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_XTHDriverConfig(en_sysctrl_xtal_driver_t enDriver) +{ + en_result_t enRet = Ok; + + M0P_SYSCTRL->XTH_CR_f.DRIVER = enDriver; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief 外部低速晶振驱动é…ç½® + ** \param [in] enFreq 外部低速晶振频率范围选择 + ** \param [in] enDriver 外部低速晶振驱动能力选择 + ** \retval Ok 设定æˆåŠŸ + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_XTLDriverConfig(en_sysctrl_xtl_amp_t enAmp, en_sysctrl_xtal_driver_t enDriver) +{ + en_result_t enRet = Ok; + + M0P_SYSCTRL->XTL_CR_f.AMP_SEL = enAmp; + M0P_SYSCTRL->XTL_CR_f.DRIVER = enDriver; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief 外部高速时钟稳定周期é…ç½® + ** \param [in] enCycle 外部高速时钟稳定周期设置 + ** \retval Ok 设定æˆåŠŸ + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_SetXTHStableTime(en_sysctrl_xth_cycle_t enCycle) +{ + en_result_t enRet = Ok; + M0P_SYSCTRL->XTH_CR_f.STARTUP = enCycle; + return enRet; +} + +/** + ******************************************************************************* + ** \brief 内部低速时钟稳定周期é…ç½® + ** \param [in] enCycle 内部低速时钟稳定周期设置 + ** \retval Ok 设定æˆåŠŸ + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_SetRCLStableTime(en_sysctrl_rcl_cycle_t enCycle) +{ + en_result_t enRet = Ok; + M0P_SYSCTRL->RCL_CR_f.STARTUP = enCycle; + return enRet; +} + +/** + ******************************************************************************* + ** \brief 外部低速时钟稳定周期é…ç½® + ** \param [in] enCycle 外部低速时钟稳定周期设置 + ** \retval Ok 设定æˆåŠŸ + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_SetXTLStableTime(en_sysctrl_xtl_cycle_t enCycle) +{ + en_result_t enRet = Ok; + M0P_SYSCTRL->XTL_CR_f.STARTUP = enCycle; + return enRet; +} + +/** + ******************************************************************************* + ** \brief PLL稳定周期é…ç½® + ** \param [in] enCycle PLL稳定周期设置 + ** \retval Ok 设定æˆåŠŸ + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_SetPLLStableTime(en_sysctrl_pll_cycle_t enCycle) +{ + en_result_t enRet = Ok; + M0P_SYSCTRL->PLL_CR_f.STARTUP = enCycle; + return enRet; +} + +/** + ******************************************************************************* + ** \brief 时钟æºåˆ‡æ¢ï¼Œè¯¥å‡½æ•°æ‰§è¡ŒåŽä¼šå¼€å¯æ–°æ—¶é’Ÿæº + ** \note 选择时钟æºä¹‹å‰ï¼Œéœ€æ ¹æ®éœ€è¦é…置目标时钟æºçš„频率/驱动å‚æ•°/使能时钟æºç­‰ + ** \param [in] enSource æ–°æ—¶é’Ÿæº + ** + ** \retval Ok 设定æˆåŠŸ + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_SysClkSwitch(en_sysctrl_clk_source_t enSource) +{ + en_result_t enRet = Ok; + + en_sysctrl_clk_source_t ClkNew = enSource; + + _SysctrlUnlock(); + M0P_SYSCTRL->SYSCTRL0_f.CLK_SW5_SEL = ClkNew; + + //æ›´æ–°Core时钟（HCLK） + SystemCoreClockUpdate(); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief 获得系统时钟（HCLK）频率值 + ** \retval uint32_t HCLK频率值 + ** + ******************************************************************************/ +uint32_t Sysctrl_GetHClkFreq(void) +{ + uint32_t u32Val = 0; + const uint32_t u32hcr_tbl[] = { 4000000, 8000000, 16000000, 22120000, 24000000}; + const uint16_t u32lcr_tbl[] = { 32768, 38400}; + en_sysctrl_clk_source_t enSrc; + uint16_t u16Trim[5] = {0}; + u16Trim[4] = RCH_CR_TRIM_24M_VAL; + u16Trim[3] = RCH_CR_TRIM_22_12M_VAL; + u16Trim[2] = RCH_CR_TRIM_16M_VAL; + u16Trim[1] = RCH_CR_TRIM_8M_VAL; + u16Trim[0] = RCL_CR_TRIM_38400_VAL; + + //获å–当å‰ç³»ç»Ÿæ—¶é’Ÿ + enSrc = (en_sysctrl_clk_source_t)(M0P_SYSCTRL->SYSCTRL0_f.CLK_SW5_SEL); + + switch (enSrc) + { + case SysctrlClkRCH: + { + + if((M0P_SYSCTRL->RCH_CR_f.TRIM) == (u16Trim[4])) + { + u32Val = u32hcr_tbl[4]; + } + else if((M0P_SYSCTRL->RCH_CR_f.TRIM) == (u16Trim[3])) + { + u32Val = u32hcr_tbl[3]; + } + else if((M0P_SYSCTRL->RCH_CR_f.TRIM) == (u16Trim[2])) + { + u32Val = u32hcr_tbl[2]; + } + else if((M0P_SYSCTRL->RCH_CR_f.TRIM) == (u16Trim[1])) + { + u32Val = u32hcr_tbl[1]; + } + else + { + u32Val = u32hcr_tbl[0]; + } + } + break; + case SysctrlClkXTH: + u32Val = SYSTEM_XTH; + break; + case SysctrlClkRCL: + { + if(u16Trim[0] == (M0P_SYSCTRL->RCL_CR_f.TRIM)) + { + u32Val = u32lcr_tbl[1]; + } + else + { + u32Val = u32lcr_tbl[0]; + } + } + break; + case SysctrlClkXTL: + u32Val = SYSTEM_XTL; + break; + case SysctrlClkPLL: + { + if (SysctrlPllRch == M0P_SYSCTRL->PLL_CR_f.REFSEL) + { + if(u16Trim[4] == M0P_SYSCTRL->RCH_CR_f.TRIM) + { + u32Val = u32hcr_tbl[4]; + } + else if(u16Trim[3] == M0P_SYSCTRL->RCH_CR_f.TRIM) + { + u32Val = u32hcr_tbl[3]; + } + else if(u16Trim[2] == M0P_SYSCTRL->RCH_CR_f.TRIM) + { + u32Val = u32hcr_tbl[2]; + } + else if(u16Trim[1] == M0P_SYSCTRL->RCH_CR_f.TRIM) + { + u32Val = u32hcr_tbl[1]; + } + else + { + u32Val = u32hcr_tbl[0]; + } + } + else + { + u32Val = SYSTEM_XTH; + } + + u32Val = (u32Val * M0P_SYSCTRL->PLL_CR_f.DIVN); + } + break; + default: + u32Val = 0u; + break; + } + + u32Val = (u32Val >> M0P_SYSCTRL->SYSCTRL0_f.HCLK_PRS); + + return u32Val; +} + +/** + ******************************************************************************* + ** \brief 获得外设时钟（PCLK）频率值 + ** \retval uint32_t PCLK频率值(Hz) + ** + ******************************************************************************/ +uint32_t Sysctrl_GetPClkFreq(void) +{ + uint32_t u32Val = 0; + + u32Val = Sysctrl_GetHClkFreq(); + u32Val = (u32Val >> (M0P_SYSCTRL->SYSCTRL0_f.PCLK_PRS)); + + return u32Val; +} + + +/** + ******************************************************************************* + ** \brief 时钟åˆå§‹åŒ–函数 + ** \param [in] pstcCfg åˆå§‹åŒ–é…ç½®å‚æ•° + ** \retval Ok 设定æˆåŠŸ + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_ClkInit(stc_sysctrl_clk_config_t *pstcCfg) +{ + en_result_t enRet = Ok; + + //系统时钟å‚æ•°é…ç½® + switch(pstcCfg->enClkSrc) + { + case SysctrlClkRCH: + + break; + case SysctrlClkXTH: + Sysctrl_XTHDriverConfig(SysctrlXtalDriver3); + Sysctrl_SetXTHStableTime(SysctrlXthStableCycle16384); + break; + case SysctrlClkRCL: + Sysctrl_SetRCLStableTime(SysctrlRclStableCycle256); + break; + case SysctrlClkXTL: + Sysctrl_XTLDriverConfig(SysctrlXtlAmp3, SysctrlXtalDriver3); + Sysctrl_SetXTLStableTime(SysctrlXtlStableCycle16384); + break; + case SysctrlClkPLL: + Sysctrl_SetPLLStableTime(SysctrlPllStableCycle16384); + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + //时钟æºä½¿èƒ½ + Sysctrl_ClkSourceEnable(pstcCfg->enClkSrc, TRUE); + + //时钟æºåˆ‡æ¢ + Sysctrl_SysClkSwitch(pstcCfg->enClkSrc); + + //时钟分频设置 + Sysctrl_SetHCLKDiv(pstcCfg->enHClkDiv); + Sysctrl_SetPCLKDiv(pstcCfg->enPClkDiv); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief 时钟去åˆå§‹åŒ–函数 + ** \param [in] + ** \retval Ok 设定æˆåŠŸ + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_ClkDeInit(void) +{ + en_result_t enRet = Ok; + + //é…ç½®RCH为内部4Hz + Sysctrl_SetRCHTrim(SysctrlRchFreq4MHz); + + //时钟æºä½¿èƒ½ + Sysctrl_ClkSourceEnable(SysctrlClkRCH, TRUE); + + //时钟æºåˆ‡æ¢ + Sysctrl_SysClkSwitch(SysctrlClkRCH); + + //其它时钟æºä½¿èƒ½å…³é—­ + Sysctrl_ClkSourceEnable(SysctrlClkXTH, FALSE); + Sysctrl_ClkSourceEnable(SysctrlClkRCL, FALSE); + Sysctrl_ClkSourceEnable(SysctrlClkXTL, FALSE); + Sysctrl_ClkSourceEnable(SysctrlClkPLL, FALSE); + + //时钟分频设置 + Sysctrl_SetHCLKDiv(SysctrlHclkDiv1); + Sysctrl_SetPCLKDiv(SysctrlPclkDiv1); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief 内部高速时钟频率TRIM值加载 + ** \param [in] enRCHFreq 设定的RCH目标频率值 + ** \retval Ok 设定æˆåŠŸ + ** 其他 设定失败或时钟未稳定 + ******************************************************************************/ +en_result_t Sysctrl_SetRCHTrim(en_sysctrl_rch_freq_t enRCHFreq) +{ + en_result_t enRet = Ok; + + //加载RCH Trim值 + switch (enRCHFreq) + { + case SysctrlRchFreq4MHz: + M0P_SYSCTRL->RCH_CR_f.TRIM = RCH_CR_TRIM_4M_VAL; + break; + case SysctrlRchFreq8MHz: + M0P_SYSCTRL->RCH_CR_f.TRIM = RCH_CR_TRIM_8M_VAL; + break; + case SysctrlRchFreq16MHz: + M0P_SYSCTRL->RCH_CR_f.TRIM = RCH_CR_TRIM_16M_VAL; + break; + case SysctrlRchFreq22_12MHz: + M0P_SYSCTRL->RCH_CR_f.TRIM = RCH_CR_TRIM_22_12M_VAL; + break; + case SysctrlRchFreq24MHz: + M0P_SYSCTRL->RCH_CR_f.TRIM = RCH_CR_TRIM_24M_VAL; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief 外部高速时钟频率范围设定 + ** \param [in] enXTHFreq 设定的频率值 + ** \retval Ok 设定æˆåŠŸ + ** 其他 设定失败或时钟未稳定 + ******************************************************************************/ +en_result_t Sysctrl_SetXTHFreq(en_sysctrl_xth_freq_t enXTHFreq) +{ + en_result_t enRet = Ok; + + M0P_SYSCTRL->XTH_CR_f.XTH_FSEL = enXTHFreq; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief PLL时钟é…ç½® + ** \param [in] pstcPLLCfg PLLé…置结构体指针 + ** \retval Ok 设定æˆåŠŸ + ** 其他 设定失败或å‚数值ä¸åŒ¹é… + ******************************************************************************/ +en_result_t Sysctrl_SetPLLFreq(stc_sysctrl_pll_config_t *pstcPLLCfg) +{ + en_result_t enRet = Ok; + + uint16_t u16Trim[5] = {0}; + u16Trim[4] = RCH_CR_TRIM_24M_VAL; + u16Trim[3] = RCH_CR_TRIM_22_12M_VAL; + u16Trim[2] = RCH_CR_TRIM_16M_VAL; + u16Trim[1] = RCH_CR_TRIM_8M_VAL; + + ////PLL最高时钟ä¸èƒ½è¶…过48MHz + //RCH作为PLL输入 + if (SysctrlPllRch == pstcPLLCfg->enPllClkSrc) + { + if( ((u16Trim[4] == M0P_SYSCTRL->RCH_CR_f.TRIM) && (pstcPLLCfg->enPllMul > 2)) || + ((u16Trim[3] == M0P_SYSCTRL->RCH_CR_f.TRIM) && (pstcPLLCfg->enPllMul > 2)) || + ((u16Trim[2] == M0P_SYSCTRL->RCH_CR_f.TRIM) && (pstcPLLCfg->enPllMul > 3)) || + ((u16Trim[1] == M0P_SYSCTRL->RCH_CR_f.TRIM) && (pstcPLLCfg->enPllMul > 6))) + { + return ErrorInvalidMode; + } + } + else //XTH作为PLL输入 + { + if ((SYSTEM_XTH * pstcPLLCfg->enPllMul) > 48*1000*1000) + { + return ErrorInvalidMode; + } + } + + M0P_SYSCTRL->PLL_CR_f.FRSEL = pstcPLLCfg->enInFreq; + M0P_SYSCTRL->PLL_CR_f.FOSC = pstcPLLCfg->enOutFreq; + M0P_SYSCTRL->PLL_CR_f.DIVN = pstcPLLCfg->enPllMul; + M0P_SYSCTRL->PLL_CR_f.REFSEL = pstcPLLCfg->enPllClkSrc; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief 内部低速时钟频率TRIM值加载 + ** \param [in] enRCLFreq 设定的RCL目标频率值 + ** \retval Ok 设定æˆåŠŸ + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_SetRCLTrim(en_sysctrl_rcl_freq_t enRCLFreq) +{ + en_result_t enRet = Ok; + + switch (enRCLFreq) + { + case SysctrlRclFreq32768: + M0P_SYSCTRL->RCL_CR_f.TRIM = RCL_CR_TRIM_32768_VAL; + break; + case SysctrlRclFreq38400: + M0P_SYSCTRL->RCL_CR_f.TRIM = RCL_CR_TRIM_38400_VAL; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief 系统时钟（HCLK）分频设定 + ** \param [in] enHCLKDiv 分频设定值 + ** \retval Ok 设定æˆåŠŸ + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_SetHCLKDiv(en_sysctrl_hclk_div_t enHCLKDiv) +{ + en_result_t enRet = Ok; + + _SysctrlUnlock(); + M0P_SYSCTRL->SYSCTRL0_f.HCLK_PRS = enHCLKDiv; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief 外设时钟（PCLK）分频设定 + ** \param [in] enPCLKDiv 分频设定值 + ** \retval Ok 设定æˆåŠŸ + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_SetPCLKDiv(en_sysctrl_pclk_div_t enPCLKDiv) +{ + en_result_t enRet = Ok; + + _SysctrlUnlock(); + M0P_SYSCTRL->SYSCTRL0_f.PCLK_PRS = enPCLKDiv; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief 设置外设时钟门控开关 + ** \param [in] enPeripheral 目标外设 + ** \param [in] bFlag 使能开关 + ** \retval Ok 设定æˆåŠŸ + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_SetPeripheralGate(en_sysctrl_peripheral_gate_t enPeripheral, boolean_t bFlag) +{ + en_result_t enRet = Ok; + + bFlag = !!bFlag; + + setBit(&(M0P_SYSCTRL->PERI_CLKEN), enPeripheral, bFlag); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief èŽ·å¾—å¤–è®¾æ—¶é’Ÿé—¨æŽ§å¼€å…³çŠ¶æ€ + ** \param [in] enPeripheral 目标外设 + ** \retval TRUE å¼€ + ** FALSE å…³ + ******************************************************************************/ +boolean_t Sysctrl_GetPeripheralGate(en_sysctrl_peripheral_gate_t enPeripheral) +{ + return getBit(&(M0P_SYSCTRL->PERI_CLKEN), enPeripheral); +} + +/** + ******************************************************************************* + ** \brief 系统功能设定 + ** \param [in] enFunc 系统功能枚举类型 + ** \param [in] bFlag 1-å¼€/0-å…³ + ** \retval Ok 设定æˆåŠŸ + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_SetFunc(en_sysctrl_func_t enFunc, boolean_t bFlag) +{ + en_result_t enRet = Ok; + + _SysctrlUnlock(); + bFlag = !!bFlag; + + switch (enFunc) + { + case SysctrlWkupByRCHEn: + M0P_SYSCTRL->SYSCTRL0_f.WAKEUP_BYRCH = bFlag; + break; + case SysctrlEXTHEn: + M0P_SYSCTRL->SYSCTRL1_f.EXTH_EN = bFlag; + break; + case SysctrlEXTLEn: + M0P_SYSCTRL->SYSCTRL1_f.EXTL_EN = bFlag; + break; + case SysctrlXTLAlwaysOnEn: + M0P_SYSCTRL->SYSCTRL1_f.XTL_ALWAYS_ON = bFlag; + break; + case SysctrlClkFuncRTCLpmEn: + M0P_SYSCTRL->SYSCTRL1_f.RTC_LPW = bFlag; + break; + case SysctrlCMLockUpEn: + M0P_SYSCTRL->SYSCTRL1_f.LOCKUP_EN = bFlag; + break; + case SysctrlSWDUseIOEn: + M0P_SYSCTRL->SYSCTRL1_f.SWD_USE_IO = bFlag; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief 设定RTC校准时钟频率 + ** \param [in] enRtcAdj 校准频率值 + ** \retval Ok 设定æˆåŠŸ + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_SetRTCAdjustClkFreq(en_sysctrl_rtc_adjust_t enRtcAdj) +{ + en_result_t enRet = Ok; + + _SysctrlUnlock(); + M0P_SYSCTRL->SYSCTRL1_f.RTC_FREQ_ADJUST = enRtcAdj; + + return enRet; +} + +//@} // SysctrlGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/timer0.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/timer0.c new file mode 100644 index 0000000000..7210d18116 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/timer0.c @@ -0,0 +1,1390 @@ +/****************************************************************************** +*Copyright(C)2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file timer3.c + ** + ** Common API of base timer. + ** @link BT Tiemr3 Group Some description @endlink + ** + ** - 2018-04-18 First Version + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "timer0.h" +/** + ******************************************************************************* + ** \addtogroup Tim0Group + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +//#define IS_VALID_TIM(x) (TIM0 == (x) || TIM1 == (x) || TIM2 == (x)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +static func_ptr_t pfnTim0Callback = NULL; + + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ***************************************************************************** + ** \brief Base Timer3 中断标志获å–(模å¼0/1/23) + ** + ** + ** \param [in] enTim0Irq 中断类型 + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +boolean_t Tim0_GetIntFlag(en_tim0_irq_type_t enTim0Irq) +{ + boolean_t bRetVal = FALSE; + uint32_t u32Val; + + u32Val = M0P_TIM0_MODE23->IFR; + bRetVal = (u32Val>>enTim0Irq) & 0x1; + + return bRetVal; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 中断标志清除(模å¼0/1/23) + ** + ** + ** \param [in] enTim0Irq 中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_ClearIntFlag(en_tim0_irq_type_t enTim0Irq) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE23->ICLR = ~(1u<ICLR_f.BIF = 0; + M0P_TIM0_MODE23->ICLR_f.CA0E = 0; + M0P_TIM0_MODE23->ICLR_f.CA0F = 0; + M0P_TIM0_MODE23->ICLR_f.CB0E = 0; + M0P_TIM0_MODE23->ICLR_f.CB0F = 0; + M0P_TIM0_MODE23->ICLR_f.TIF = 0; + M0P_TIM0_MODE23->ICLR_f.UIF = 0; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 中断使能(模å¼0) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_Mode0_EnableIrq(void) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE0->M0CR_f.UIE = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 中断ç¦æ­¢(模å¼0) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_Mode0_DisableIrq(void) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE0->M0CR_f.UIE = FALSE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 中断使能(模å¼1) + ** + ** + ** \param [in] enTim0Irq 中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_Mode1_EnableIrq (en_tim0_irq_type_t enTim0Irq) +{ + en_result_t enResult = Ok; + + + switch (enTim0Irq) + { + case Tim0UevIrq: + M0P_TIM0_MODE1->M1CR_f.UIE = TRUE; + break; + case Tim0CA0Irq: + M0P_TIM0_MODE1->CR0_f.CIEA = TRUE; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 中断ç¦æ­¢(模å¼1) + ** + ** + ** \param [in] enTim0Irq 中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_Mode1_DisableIrq (en_tim0_irq_type_t enTim0Irq) +{ + en_result_t enResult = Ok; + + + switch (enTim0Irq) + { + case Tim0UevIrq: + M0P_TIM0_MODE1->M1CR_f.UIE = FALSE; + break; + case Tim0CA0Irq: + M0P_TIM0_MODE1->CR0_f.CIEA = FALSE; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 中断使能(模å¼23) + ** + ** + ** \param [in] enTim0Irq 中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_Mode23_EnableIrq (en_tim0_irq_type_t enTim0Irq) +{ + en_result_t enResult = Ok; + + + switch (enTim0Irq) + { + case Tim0UevIrq: + M0P_TIM0_MODE23->M23CR_f.UIE = TRUE; + break; + case Tim0CA0Irq: + M0P_TIM0_MODE23->CRCH0_f.CIEA = TRUE; + break; + case Tim0CB0Irq: + M0P_TIM0_MODE23->CRCH0_f.CIEB = TRUE; + break; +// case Tim0CA1Irq: +// M0P_TIM0_MODE23->CRCH1_f.CIEA = TRUE; +// break; +// case Tim0CB1Irq: +// M0P_TIM0_MODE23->CRCH1_f.CIEB = TRUE; +// break; +// case Tim0CA2Irq: +// M0P_TIM0_MODE23->CRCH2_f.CIEA = TRUE; +// break; +// case Tim0CB2Irq: +// M0P_TIM0_MODE23->CRCH2_f.CIEB = TRUE; +// break; + case Tim0BkIrq: + M0P_TIM0_MODE23->M23CR_f.BIE = TRUE; + break; + case Tim0TrigIrq: + M0P_TIM0_MODE23->M23CR_f.TIE = TRUE; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 中断ç¦æ­¢(模å¼23) + ** + ** + ** \param [in] enTim0Irq 中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_Mode23_DisableIrq (en_tim0_irq_type_t enTim0Irq) +{ + en_result_t enResult = Ok; + + + switch (enTim0Irq) + { + case Tim0UevIrq: + M0P_TIM0_MODE23->M23CR_f.UIE = FALSE; + break; + case Tim0CA0Irq: + M0P_TIM0_MODE23->CRCH0_f.CIEA = FALSE; + break; + case Tim0CB0Irq: + M0P_TIM0_MODE23->CRCH0_f.CIEB = FALSE; + break; +// case Tim0CA1Irq: +// M0P_TIM0_MODE23->CRCH1_f.CIEA = FALSE; +// break; +// case Tim0CB1Irq: +// M0P_TIM0_MODE23->CRCH1_f.CIEB = FALSE; +// break; +// case Tim0CA2Irq: +// M0P_TIM0_MODE23->CRCH2_f.CIEA = FALSE; +// break; +// case Tim0CB2Irq: +// M0P_TIM0_MODE23->CRCH2_f.CIEB = FALSE; +// break; + case Tim0BkIrq: + M0P_TIM0_MODE23->M23CR_f.BIE = FALSE; + break; + case Tim0TrigIrq: + M0P_TIM0_MODE23->M23CR_f.TIE = FALSE; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 中断æœåŠ¡å‡½æ•° + ** + ** + ** \param [in] u8Param Timer0通é“选择(0 - TIM0) + ** + ** \retval NULL + *****************************************************************************/ +void Tim0_IRQHandler(uint8_t u8Param) +{ + switch (u8Param) + { + case 0: + if(NULL != pfnTim0Callback) + { + pfnTim0Callback(); + } + break; + default: + ; + break; + } +} + + + +/** + ***************************************************************************** + ** \brief Base Timer3 åˆå§‹åŒ–é…ç½®(模å¼0) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_Mode0_Init(stc_tim0_mode0_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE0->M0CR_f.MODE = pstcConfig->enWorkMode; + M0P_TIM0_MODE0->M0CR_f.GATEP = pstcConfig->enGateP; + M0P_TIM0_MODE0->M0CR_f.GATE = pstcConfig->bEnGate; + M0P_TIM0_MODE0->M0CR_f.PRS = pstcConfig->enPRS; + M0P_TIM0_MODE0->M0CR_f.TOGEN = pstcConfig->bEnTog; + M0P_TIM0_MODE0->M0CR_f.CT = pstcConfig->enCT; + M0P_TIM0_MODE0->M0CR_f.MD = pstcConfig->enCntMode; + + pfnTim0Callback = pstcConfig->pfnTim0Cb; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 å¯åŠ¨è¿è¡Œ(模å¼0) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M0_Run(void) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE0->M0CR_f.CTEN = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 åœæ­¢è¿è¡Œ(模å¼0) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M0_Stop(void) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE0->M0CR_f.CTEN = FALSE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 翻转输出使能/ç¦æ­¢è®¾å®š(模å¼0) + ** + ** + ** \param [in] bEnOutput 翻转输出设定 TRUE:使能, FALSE:ç¦æ­¢ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M0_EnTOG_Output(boolean_t bEnOutput) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE0->DTR_f.MOE = bEnOutput; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 16ä½è®¡æ•°å™¨åˆå€¼è®¾ç½®(模å¼0) + ** + ** + ** \param [in] u16Data CNT 16ä½åˆå€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M0_Cnt16Set(uint16_t u16Data) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE0->CNT_f.CNT = u16Data; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 16ä½è®¡æ•°å€¼èŽ·å–(模å¼0) + ** + ** + ** \param [in] none + ** + ** \retval 16bits计数值 + *****************************************************************************/ +uint16_t Tim0_M0_Cnt16Get(void) +{ + uint16_t u16CntData = 0; + + u16CntData = M0P_TIM0_MODE0->CNT_f.CNT; + + return u16CntData; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 é‡è½½å€¼è®¾ç½®(模å¼0) + ** + ** + ** \param [in] u16Data 16bitsé‡è½½å€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M0_ARRSet(uint16_t u16Data) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE0->ARR_f.ARR = u16Data; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 32ä½è®¡æ•°å™¨åˆå€¼è®¾ç½®(模å¼0) + ** + ** + ** \param [in] u32Data 32ä½åˆå€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M0_Cnt32Set(uint32_t u32Data) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE0->CNT32_f.CNT32 = u32Data; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 32ä½è®¡æ•°å€¼èŽ·å–(模å¼0) + ** + ** + ** \param [in] none + ** + ** \retval 32bits计数值 + *****************************************************************************/ +uint32_t Tim0_M0_Cnt32Get(void) +{ + uint32_t u32CntData = 0; + + u32CntData = M0P_TIM0_MODE0->CNT32_f.CNT32; + + return u32CntData; +} + +/** + ***************************************************************************** + ** \brief Base Timer0 åˆå§‹åŒ–é…ç½®(模å¼1) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_Mode1_Init(stc_tim0_mode1_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + +// M0P_TIM0_MODE0->M1CR_f.MODE = pstcConfig->enWorkMode; +// M0P_TIM0_MODE0->M1CR_f.PRS = pstcConfig->enPRS; +// M0P_TIM0_MODE0->M1CR_f.CT = pstcConfig->enCT; +// M0P_TIM0_MODE0->M1CR_f.ONESHOT = pstcConfig->enOneShot; +// +// pfnTim0Callback = pstcConfig->pfnTim0Cb; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 PWC 输入é…ç½®(模å¼1) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M1_Input_Config(stc_tim0_pwc_input_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + +// M0P_TIM0_MODE0->MSCR_f.TS = pstcConfig->enTsSel; +// M0P_TIM0_MODE0->MSCR_f.IA0S = pstcConfig->enIA0Sel; +// M0P_TIM0_MODE0->MSCR_f.IB0S = pstcConfig->enIB0Sel; +// M0P_TIM0_MODE0->FLTR_f.ETP = pstcConfig->enETRPhase; +// M0P_TIM0_MODE0->FLTR_f.FLTET = pstcConfig->enFltETR; +// M0P_TIM0_MODE0->FLTR_f.FLTA0 = pstcConfig->enFltIA0; +// M0P_TIM0_MODE0->FLTR_f.FLTB0 = pstcConfig->enFltIB0; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 PWC测é‡è¾¹æ²¿èµ·å§‹ç»“æŸé€‰æ‹©(模å¼1) + ** + ** + ** \param [in] enEdgeSel pwc测é‡èµ·å§‹ç»ˆæ­¢ç”µå¹³ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M1_PWC_Edge_Sel(en_tim0_m1cr_Edge_t enEdgeSel) +{ + en_result_t enResult = Ok; + +// switch (enEdgeSel) +// { +// case 0: ///< 上å‡æ²¿åˆ°ä¸Šå‡æ²¿(周期) +// M0P_TIM0_MODE0->M1CR_f.EDG1ST = 0; //上å‡æ²¿ +// M0P_TIM0_MODE0->M1CR_f.EDG2ND = 0; //上å‡æ²¿ +// break; +// case 1: ///< 下é™æ²¿åˆ°ä¸Šå‡æ²¿(低电平) +// M0P_TIM0_MODE0->M1CR_f.EDG1ST = 1; //下é™æ²¿ +// M0P_TIM0_MODE0->M1CR_f.EDG2ND = 0; //上å‡æ²¿ +// break; +// case 2: ///< 上å‡æ²¿åˆ°ä¸‹é™æ²¿(高电平) +// M0P_TIM0_MODE0->M1CR_f.EDG1ST = 0; //上å‡æ²¿ +// M0P_TIM0_MODE0->M1CR_f.EDG2ND = 1; //下é™æ²¿ +// break; +// case 3: ///< 下é™æ²¿åˆ°ä¸‹é™æ²¿(周期) +// M0P_TIM0_MODE0->M1CR_f.EDG1ST = 1; //下é™æ²¿ +// M0P_TIM0_MODE0->M1CR_f.EDG2ND = 1; //下é™æ²¿ +// break; +// default: +// ; +// break; +// } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 å¯åŠ¨è¿è¡Œ(模å¼1) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M1_Run(void) +{ + en_result_t enResult = Ok; + +// M0P_TIM0_MODE0->M1CR_f.CTEN = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 åœæ­¢è¿è¡Œ(模å¼1) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M1_Stop(void) +{ + en_result_t enResult = Ok; + +// M0P_TIM0_MODE0->M1CR_f.CTEN = FALSE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 16ä½è®¡æ•°å™¨åˆå€¼è®¾ç½®(模å¼1) + ** + ** + ** \param [in] u16Data 16ä½åˆå€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M1_Cnt16Set(uint16_t u16Data) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE0->CNT_f.CNT = u16Data; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 16ä½è®¡æ•°å€¼èŽ·å–(模å¼1) + ** + ** + ** \param [in] none + ** + ** \retval 16bits计数值 + *****************************************************************************/ +uint16_t Tim0_M1_Cnt16Get(void) +{ + uint16_t u16CntData = 0; + + u16CntData = M0P_TIM0_MODE0->CNT_f.CNT; + + return u16CntData; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 脉冲宽度测é‡ç»“果数值获å–(模å¼1) + ** + ** + ** \param [in] none + ** + ** \retval 16bits脉冲宽度测é‡ç»“æžœ + *****************************************************************************/ +uint16_t Tim0_M1_PWC_CapValueGet(void) +{ + uint16_t u16CapData = 0; + +// u16CapData = M0P_TIM0_MODE0->CCR0A_f.CCR0A; + + return u16CapData; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 åˆå§‹åŒ–é…ç½®(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_Mode23_Init(stc_tim0_mode23_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE23->M23CR_f.MODE = pstcConfig->enWorkMode; + + M0P_TIM0_MODE23->M23CR_f.PRS = pstcConfig->enPRS; + M0P_TIM0_MODE23->M23CR_f.CT = pstcConfig->enCT; + M0P_TIM0_MODE23->M23CR_f.COMP = pstcConfig->enPWMTypeSel; + M0P_TIM0_MODE23->M23CR_f.PWM2S = pstcConfig->enPWM2sSel; + M0P_TIM0_MODE23->M23CR_f.ONESHOT = pstcConfig->bOneShot; + M0P_TIM0_MODE23->M23CR_f.URS = pstcConfig->bURSSel; + M0P_TIM0_MODE23->M23CR_f.DIR = pstcConfig->enCntDir; + + pfnTim0Callback = pstcConfig->pfnTim0Cb; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 PWM输出使能(模å¼23) + ** + ** + ** \param [in] bEnOutput PWM输出使能/ç¦æ­¢è®¾å®š + ** \param [in] bEnAutoOutput PWM自动输出使能/ç¦æ­¢è®¾å®š + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_EnPWM_Output(boolean_t bEnOutput, boolean_t bEnAutoOutput) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE23->DTR_f.MOE = bEnOutput; + M0P_TIM0_MODE23->DTR_f.AOE = bEnAutoOutput; + + return enResult; +} + + +/** + ***************************************************************************** + ** \brief Base Timer3 å¯åŠ¨è¿è¡Œ(模å¼23) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_Run(void) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE23->M23CR_f.CTEN = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 åœæ­¢è¿è¡Œ(模å¼23) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_Stop(void) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE23->M23CR_f.CTEN = FALSE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 é‡è½½å€¼è®¾ç½®(模å¼23) + ** + ** + ** \param [in] u16Data 16bitsé‡è½½å€¼ + ** \param [in] bArrBufEn ARRé‡è½½ç¼“存使能TRUE/ç¦æ­¢FALSE + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_ARRSet(uint16_t u16Data, boolean_t bArrBufEn) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE23->ARR_f.ARR = u16Data; + M0P_TIM0_MODE23->M23CR_f.BUFPEN = bArrBufEn; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 16ä½è®¡æ•°å™¨åˆå€¼è®¾ç½®(模å¼23) + ** + ** + ** \param [in] u16Data 16ä½åˆå€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_Cnt16Set(uint16_t u16Data) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE23->CNT_f.CNT = u16Data; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 16ä½è®¡æ•°å€¼èŽ·å–(模å¼23) + ** + ** + ** \param [in] none + ** + ** \retval 16bits计数值 + *****************************************************************************/ +uint16_t Tim0_M23_Cnt16Get(void) +{ + uint16_t u16CntData = 0; + + u16CntData = M0P_TIM0_MODE23->CNT_f.CNT; + + return u16CntData; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 比较æ•èŽ·å¯„存器CCRxA/CCRxB设置(模å¼23) + ** + ** + ** \param [in] enCCRSel CCRxA/CCRxB设定 + ** \param [in] u16Data CCRxA/CCRxB 16ä½åˆå§‹å€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_CCR_Set(en_tim0_m23_ccrx_t enCCRSel, uint16_t u16Data) +{ + en_result_t enResult = Ok; + + if(Tim0CCR0A == enCCRSel) + { + M0P_TIM0_MODE23->CCR0A_f.CCR0A = u16Data; + } + else if(Tim0CCR0B == enCCRSel) + { + M0P_TIM0_MODE23->CCR0B_f.CCR0B = u16Data; + } +// else if(Tim0CCR1A == enCCRSel) +// { +// M0P_TIM0_MODE23->CCR1A_f.CCR1A = u16Data; +// } +// else if(Tim0CCR1B == enCCRSel) +// { +// M0P_TIM0_MODE23->CCR1B_f.CCR1B = u16Data; +// } +// else if(Tim0CCR2A == enCCRSel) +// { +// M0P_TIM0_MODE23->CCR2A_f.CCR2A = u16Data; +// } +// else if(Tim0CCR2B == enCCRSel) +// { +// M0P_TIM0_MODE23->CCR2B_f.CCR2B = u16Data; +// } + else + { + enResult = Error; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 比较æ•èŽ·å¯„存器CCRxA/CCRxB读å–(模å¼23) + ** + ** + ** \param [in] enCCRSel CCRxA/CCRxB设定 + ** + ** \retval 16bitsCCRxA/CCRxBæ•èŽ·å€¼ + *****************************************************************************/ +uint16_t Tim0_M23_CCR_Get(en_tim0_m23_ccrx_t enCCRSel) +{ + uint16_t u16Data = 0; + + if(Tim0CCR0A == enCCRSel) + { + u16Data = M0P_TIM0_MODE23->CCR0A_f.CCR0A; + } + else if(Tim0CCR0B == enCCRSel) + { + u16Data = M0P_TIM0_MODE23->CCR0B_f.CCR0B; + } +// else if(Tim0CCR1A == enCCRSel) +// { +// u16Data = M0P_TIM0_MODE23->CCR1A_f.CCR1A; +// } +// else if(Tim0CCR1B == enCCRSel) +// { +// u16Data = M0P_TIM0_MODE23->CCR1B_f.CCR1B; +// } +// else if(Tim0CCR2A == enCCRSel) +// { +// u16Data = M0P_TIM0_MODE23->CCR2A_f.CCR2A; +// } +// else if(Tim0CCR2B == enCCRSel) +// { +// u16Data = M0P_TIM0_MODE23->CCR2B_f.CCR2B; +// } + else + { + u16Data = 0; + } + + return u16Data; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 PWM互补输出模å¼ä¸‹ï¼ŒGATE功能选择(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_GateFuncSel(stc_tim0_m23_gate_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE23->M23CR_f.CSG = pstcConfig->enGateFuncSel; + M0P_TIM0_MODE23->M23CR_f.CRG = pstcConfig->bGateRiseCap; + M0P_TIM0_MODE23->M23CR_f.CFG = pstcConfig->bGateFallCap; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 主从模å¼é…ç½®(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_MasterSlave_Set(stc_tim0_m23_master_slave_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE23->MSCR_f.MSM = pstcConfig->enMasterSlaveSel; + M0P_TIM0_MODE23->MSCR_f.MMS = pstcConfig->enMasterSrc; + M0P_TIM0_MODE23->MSCR_f.SMS = pstcConfig->enSlaveModeSel; + M0P_TIM0_MODE23->MSCR_f.TS = pstcConfig->enTsSel; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 CHxA/CHxB比较通é“控制(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** \param [in] enTim0Chx Timer3通é“(Tim0CH0, Tim0CH1, Tim0CH2) + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_PortOutput_Config(en_tim0_channel_t enTim0Chx, stc_tim0_m23_compare_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + switch (enTim0Chx) + { + case Tim0CH0: + M0P_TIM0_MODE23->CRCH0_f.CSA = 0; + M0P_TIM0_MODE23->FLTR_f.OCMA0_FLTA0 = pstcConfig->enCHxACmpCtrl; + M0P_TIM0_MODE23->FLTR_f.CCPA0 = pstcConfig->enCHxAPolarity; + M0P_TIM0_MODE23->CRCH0_f.BUFEA = pstcConfig->bCHxACmpBufEn; + M0P_TIM0_MODE23->M23CR_f.CIS = pstcConfig->enCHxACmpIntSel; + + M0P_TIM0_MODE23->CRCH0_f.CSB = 0; + M0P_TIM0_MODE23->FLTR_f.OCMB0_FLTB0 = pstcConfig->enCHxBCmpCtrl; + M0P_TIM0_MODE23->FLTR_f.CCPB0 = pstcConfig->enCHxBPolarity; + M0P_TIM0_MODE23->CRCH0_f.BUFEB = pstcConfig->bCHxBCmpBufEn; + M0P_TIM0_MODE23->CRCH0_f.CISB = pstcConfig->enCHxBCmpIntSel; + break; +// case Tim0CH1: +// M0P_TIM0_MODE23->CRCH1_f.CSA = 0; +// M0P_TIM0_MODE23->FLTR_f.OCMA1_FLTA1 = pstcConfig->enCHxACmpCtrl; +// M0P_TIM0_MODE23->FLTR_f.CCPA1 = pstcConfig->enCHxAPolarity; +// M0P_TIM0_MODE23->CRCH1_f.BUFEA = pstcConfig->bCHxACmpBufEn; +// M0P_TIM0_MODE23->M23CR_f.CIS = pstcConfig->enCHxACmpIntSel; +// +// M0P_TIM0_MODE23->CRCH1_f.CSB = 0; +// M0P_TIM0_MODE23->FLTR_f.OCMB1_FLTB1 = pstcConfig->enCHxBCmpCtrl; +// M0P_TIM0_MODE23->FLTR_f.CCPB1 = pstcConfig->enCHxBPolarity; +// M0P_TIM0_MODE23->CRCH1_f.BUFEB = pstcConfig->bCHxBCmpBufEn; +// M0P_TIM0_MODE23->CRCH1_f.CISB = pstcConfig->enCHxBCmpIntSel; +// break; +// case Tim0CH2: +// M0P_TIM0_MODE23->CRCH2_f.CSA = 0; +// M0P_TIM0_MODE23->FLTR_f.OCMA2_FLTA2 = pstcConfig->enCHxACmpCtrl; +// M0P_TIM0_MODE23->FLTR_f.CCPA2 = pstcConfig->enCHxAPolarity; +// M0P_TIM0_MODE23->CRCH2_f.BUFEA = pstcConfig->bCHxACmpBufEn; +// M0P_TIM0_MODE23->M23CR_f.CIS = pstcConfig->enCHxACmpIntSel; +// +// M0P_TIM0_MODE23->CRCH2_f.CSB = 0; +// M0P_TIM0_MODE23->FLTR_f.OCMB2_FLTB2 = pstcConfig->enCHxBCmpCtrl; +// M0P_TIM0_MODE23->FLTR_f.CCPB2 = pstcConfig->enCHxBPolarity; +// M0P_TIM0_MODE23->CRCH2_f.BUFEB = pstcConfig->bCHxBCmpBufEn; +// M0P_TIM0_MODE23->CRCH2_f.CISB = pstcConfig->enCHxBCmpIntSel; +// break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 CHxA/CHxB输入控制(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** \param [in] enTim0Chx Timer3通é“(Tim0CH0, Tim0CH1, Tim0CH2) + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_PortInput_Config(en_tim0_channel_t enTim0Chx, stc_tim0_m23_input_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + switch (enTim0Chx) + { + case Tim0CH0: + M0P_TIM0_MODE23->CRCH0_f.CSA = 1; + M0P_TIM0_MODE23->CRCH0_f.CFA_CRA_BKSA = pstcConfig->enCHxACapSel; + M0P_TIM0_MODE23->FLTR_f.OCMA0_FLTA0 = pstcConfig->enCHxAInFlt; + M0P_TIM0_MODE23->FLTR_f.CCPA0 = pstcConfig->enCHxAPolarity; + + M0P_TIM0_MODE23->CRCH0_f.CSB = 1; + M0P_TIM0_MODE23->CRCH0_f.CFB_CRB_BKSB = pstcConfig->enCHxBCapSel; + M0P_TIM0_MODE23->FLTR_f.OCMB0_FLTB0 = pstcConfig->enCHxBInFlt; + M0P_TIM0_MODE23->FLTR_f.CCPB0 = pstcConfig->enCHxBPolarity; + break; +// case Tim0CH1: +// M0P_TIM0_MODE23->CRCH1_f.CSA = 1; +// M0P_TIM0_MODE23->CRCH1_f.CFA_CRA_BKSA = pstcConfig->enCHxACapSel; +// M0P_TIM0_MODE23->FLTR_f.OCMA1_FLTA1 = pstcConfig->enCHxAInFlt; +// M0P_TIM0_MODE23->FLTR_f.CCPA1 = pstcConfig->enCHxAPolarity; +// +// M0P_TIM0_MODE23->CRCH1_f.CSB = 1; +// M0P_TIM0_MODE23->CRCH1_f.CFB_CRB_BKSB = pstcConfig->enCHxBCapSel; +// M0P_TIM0_MODE23->FLTR_f.OCMB1_FLTB1 = pstcConfig->enCHxBInFlt; +// M0P_TIM0_MODE23->FLTR_f.CCPB1 = pstcConfig->enCHxBPolarity; +// break; +// case Tim0CH2: +// M0P_TIM0_MODE23->CRCH2_f.CSA = 1; +// M0P_TIM0_MODE23->CRCH2_f.CFA_CRA_BKSA = pstcConfig->enCHxACapSel; +// M0P_TIM0_MODE23->FLTR_f.OCMA2_FLTA2 = pstcConfig->enCHxAInFlt; +// M0P_TIM0_MODE23->FLTR_f.CCPA2 = pstcConfig->enCHxAPolarity; +// +// M0P_TIM0_MODE23->CRCH2_f.CSB = 1; +// M0P_TIM0_MODE23->CRCH2_f.CFB_CRB_BKSB = pstcConfig->enCHxBCapSel; +// M0P_TIM0_MODE23->FLTR_f.OCMB2_FLTB2 = pstcConfig->enCHxBInFlt; +// M0P_TIM0_MODE23->FLTR_f.CCPB2 = pstcConfig->enCHxBPolarity; +// break; + default: + enResult = Error; + break; + } + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 ERT输入控制(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_ETRInput_Config(stc_tim0_m23_etr_input_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE23->FLTR_f.ETP = pstcConfig->enETRPolarity; + M0P_TIM0_MODE23->FLTR_f.FLTET = pstcConfig->enETRFlt; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 刹车BK输入控制(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_BrakeInput_Config(stc_tim0_m23_bk_input_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE23->DTR_f.BKE = pstcConfig->bEnBrake; + M0P_TIM0_MODE23->DTR_f.VC0E = pstcConfig->bEnVC0Brake; + M0P_TIM0_MODE23->DTR_f.VC1E = pstcConfig->bEnVC1Brake; + M0P_TIM0_MODE23->DTR_f.SAFEEN = pstcConfig->bEnSafetyBk; + M0P_TIM0_MODE23->DTR_f.BKSEL = pstcConfig->bEnBKSync; + M0P_TIM0_MODE23->CRCH0_f.CFA_CRA_BKSA = pstcConfig->enBkCH0AStat; + M0P_TIM0_MODE23->CRCH0_f.CFB_CRB_BKSB = pstcConfig->enBkCH0BStat; +// M0P_TIM0_MODE23->CRCH1_f.CFA_CRA_BKSA = pstcConfig->enBkCH1AStat; +// M0P_TIM0_MODE23->CRCH1_f.CFB_CRB_BKSB = pstcConfig->enBkCH1BStat; +// M0P_TIM0_MODE23->CRCH2_f.CFA_CRA_BKSA = pstcConfig->enBkCH2AStat; +// M0P_TIM0_MODE23->CRCH2_f.CFB_CRB_BKSB = pstcConfig->enBkCH2BStat; + M0P_TIM0_MODE23->FLTR_f.BKP = pstcConfig->enBrakePolarity; + M0P_TIM0_MODE23->FLTR_f.FLTBK = pstcConfig->enBrakeFlt; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 触å‘ADC控制(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_TrigADC_Config(stc_tim0_m23_adc_trig_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE23->ADTR_f.ADTE = pstcConfig->bEnTrigADC; + M0P_TIM0_MODE23->ADTR_f.UEVE = pstcConfig->bEnUevTrigADC; + M0P_TIM0_MODE23->ADTR_f.CMA0E = pstcConfig->bEnCH0ACmpTrigADC; + M0P_TIM0_MODE23->ADTR_f.CMB0E = pstcConfig->bEnCH0BCmpTrigADC; +// M0P_TIM0_MODE23->ADTR_f.CMA1E = pstcConfig->bEnCH1ACmpTrigADC; +// M0P_TIM0_MODE23->ADTR_f.CMB1E = pstcConfig->bEnCH1BCmpTrigADC; +// M0P_TIM0_MODE23->ADTR_f.CMA2E = pstcConfig->bEnCH2ACmpTrigADC; +// M0P_TIM0_MODE23->ADTR_f.CMB2E = pstcConfig->bEnCH2BCmpTrigADC; + return enResult; +} + +/** + ***************************************************************************** +** \brief Base Timer3 死区功能(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_DT_Config(stc_tim0_m23_dt_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE23->DTR_f.DTEN = pstcConfig->bEnDeadTime; + M0P_TIM0_MODE23->DTR_f.DTR = pstcConfig->u8DeadTimeValue; + + return enResult; +} + +/** + ***************************************************************************** +** \brief Base Timer3 é‡å¤å‘¨æœŸè®¾ç½®(模å¼23) + ** + ** + ** \param [in] u8ValidPeriod é‡å¤å‘¨æœŸå€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_SetValidPeriod(uint8_t u8ValidPeriod) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE23->RCR_f.RCR = u8ValidPeriod; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 OCREF清除功能(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_OCRefClr(stc_tim0_m23_OCREF_Clr_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE23->M23CR_f.OCCS = pstcConfig->enOCRefClrSrcSel; + M0P_TIM0_MODE23->M23CR_f.OCCE = pstcConfig->bVCClrEn; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 使能DMA传输(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_EnDMA(stc_tim0_m23_trig_dma_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE23->M23CR_f.UDE = pstcConfig->bUevTrigDMA; + M0P_TIM0_MODE23->M23CR_f.TDE = pstcConfig->bTITrigDMA; + M0P_TIM0_MODE23->CRCH0_f.CDEA = pstcConfig->bCmpA0TrigDMA; + M0P_TIM0_MODE23->CRCH0_f.CDEB = pstcConfig->bCmpB0TrigDMA; +// M0P_TIM0_MODE23->CRCH1_f.CDEA = pstcConfig->bCmpA1TrigDMA; +// M0P_TIM0_MODE23->CRCH1_f.CDEB = pstcConfig->bCmpB1TrigDMA; +// M0P_TIM0_MODE23->CRCH2_f.CDEA = pstcConfig->bCmpA2TrigDMA; +// M0P_TIM0_MODE23->CRCH2_f.CDEB = pstcConfig->bCmpB2TrigDMA; + M0P_TIM0_MODE23->MSCR_f.CCDS = pstcConfig->enCmpUevTrigDMA; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 æ•èŽ·æ¯”较A软件触å‘(模å¼23) + ** + ** + ** \param [in] enTim0Chx Timer3通é“(Tim0CH0, Tim0CH1, Tim0CH2) + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_EnSwTrigCapCmpA(en_tim0_channel_t enTim0Chx) +{ + en_result_t enResult = Ok; + if(Tim0CH0 == enTim0Chx) + { + M0P_TIM0_MODE23->CRCH0_f.CCGA = TRUE; + } +// else if(Tim0CH1 == enTim0Chx) +// { +// M0P_TIM0_MODE23->CRCH1_f.CCGA = TRUE; +// } +// else if(Tim0CH2 == enTim0Chx) +// { +// M0P_TIM0_MODE23->CRCH2_f.CCGA = TRUE; +// } + else + { + enResult = Error; + } + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 æ•èŽ·æ¯”较B软件触å‘(模å¼23) + ** + ** + ** \param [in] enTim0Chx Timer3通é“(Tim0CH0, Tim0CH1, Tim0CH2) + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_EnSwTrigCapCmpB(en_tim0_channel_t enTim0Chx) +{ + en_result_t enResult = Ok; + if(Tim0CH0 == enTim0Chx) + { + M0P_TIM0_MODE23->CRCH0_f.CCGB = TRUE; + } +// else if(Tim0CH1 == enTim0Chx) +// { +// M0P_TIM0_MODE23->CRCH1_f.CCGB = TRUE; +// } +// else if(Tim0CH2 == enTim0Chx) +// { +// M0P_TIM0_MODE23->CRCH2_f.CCGB = TRUE; +// } + else + { + enResult = Error; + } + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 软件更新使能(模å¼23) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_EnSwUev(void) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE23->M23CR_f.UG = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 软件触å‘使能(模å¼23) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_EnSwTrig(void) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE23->M23CR_f.TG = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 软件刹车使能(模å¼23) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_EnSwBk(void) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE23->M23CR_f.BG = TRUE; + + return enResult; +} + +//@} // Tim0Group + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/timer3.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/timer3.c new file mode 100644 index 0000000000..983062704c --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/timer3.c @@ -0,0 +1,1399 @@ +/****************************************************************************** +*Copyright(C)2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file timer3.c + ** + ** Common API of base timer. + ** @link BT Tiemr3 Group Some description @endlink + ** + ** - 2018-04-18 First Version + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "timer3.h" +/** + ******************************************************************************* + ** \addtogroup Tim3Group + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +//#define IS_VALID_TIM(x) (TIM0 == (x) || TIM1 == (x) || TIM2 == (x)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +static func_ptr_t pfnTim3Callback = NULL; + + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ***************************************************************************** + ** \brief Base Timer3 中断标志获å–(模å¼0/1/23) + ** + ** + ** \param [in] enTim3Irq 中断类型 + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +boolean_t Tim3_GetIntFlag(en_tim3_irq_type_t enTim3Irq) +{ + boolean_t bRetVal = FALSE; + uint32_t u32Val; + + u32Val = M0P_TIM3_MODE23->IFR; + bRetVal = (u32Val>>enTim3Irq) & 0x1; + + return bRetVal; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 中断标志清除(模å¼0/1/23) + ** + ** + ** \param [in] enTim3Irq 中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_ClearIntFlag(en_tim3_irq_type_t enTim3Irq) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->ICLR = ~(1u<ICLR_f.UIF = 0; + M0P_TIM3_MODE23->ICLR_f.CA0F = 0; + M0P_TIM3_MODE23->ICLR_f.CA1F = 0; + M0P_TIM3_MODE23->ICLR_f.CA2F = 0; + M0P_TIM3_MODE23->ICLR_f.CB0F = 0; + M0P_TIM3_MODE23->ICLR_f.CB1F = 0; + M0P_TIM3_MODE23->ICLR_f.CB2F = 0; + M0P_TIM3_MODE23->ICLR_f.BIF = 0; + M0P_TIM3_MODE23->ICLR_f.TIF = 0; + M0P_TIM3_MODE23->ICLR_f.CA0E = 0; + M0P_TIM3_MODE23->ICLR_f.CA1E = 0; + M0P_TIM3_MODE23->ICLR_f.CA2E = 0; + M0P_TIM3_MODE23->ICLR_f.CB0E = 0; + M0P_TIM3_MODE23->ICLR_f.CB1E = 0; + M0P_TIM3_MODE23->ICLR_f.CB2E = 0; + + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 中断使能(模å¼0) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_Mode0_EnableIrq(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE0->M0CR_f.UIE = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 中断ç¦æ­¢(模å¼0) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_Mode0_DisableIrq(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE0->M0CR_f.UIE = FALSE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 中断使能(模å¼1) + ** + ** + ** \param [in] enTim3Irq 中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_Mode1_EnableIrq (en_tim3_irq_type_t enTim3Irq) +{ + en_result_t enResult = Ok; + + + switch (enTim3Irq) + { + case Tim3UevIrq: + M0P_TIM3_MODE1->M1CR_f.UIE = TRUE; + break; + case Tim3CA0Irq: + M0P_TIM3_MODE1->CR0_f.CIEA = TRUE; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 中断ç¦æ­¢(模å¼1) + ** + ** + ** \param [in] enTim3Irq 中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_Mode1_DisableIrq (en_tim3_irq_type_t enTim3Irq) +{ + en_result_t enResult = Ok; + + + switch (enTim3Irq) + { + case Tim3UevIrq: + M0P_TIM3_MODE1->M1CR_f.UIE = FALSE; + break; + case Tim3CA0Irq: + M0P_TIM3_MODE1->CR0_f.CIEA = FALSE; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 中断使能(模å¼23) + ** + ** + ** \param [in] enTim3Irq 中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_Mode23_EnableIrq (en_tim3_irq_type_t enTim3Irq) +{ + en_result_t enResult = Ok; + + + switch (enTim3Irq) + { + case Tim3UevIrq: + M0P_TIM3_MODE23->M23CR_f.UIE = TRUE; + break; + case Tim3CA0Irq: + M0P_TIM3_MODE23->CRCH0_f.CIEA = TRUE; + break; + case Tim3CB0Irq: + M0P_TIM3_MODE23->CRCH0_f.CIEB = TRUE; + break; + case Tim3CA1Irq: + M0P_TIM3_MODE23->CRCH1_f.CIEA = TRUE; + break; + case Tim3CB1Irq: + M0P_TIM3_MODE23->CRCH1_f.CIEB = TRUE; + break; + case Tim3CA2Irq: + M0P_TIM3_MODE23->CRCH2_f.CIEA = TRUE; + break; + case Tim3CB2Irq: + M0P_TIM3_MODE23->CRCH2_f.CIEB = TRUE; + break; + case Tim3BkIrq: + M0P_TIM3_MODE23->M23CR_f.BIE = TRUE; + break; + case Tim3TrigIrq: + M0P_TIM3_MODE23->M23CR_f.TIE = TRUE; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 中断ç¦æ­¢(模å¼23) + ** + ** + ** \param [in] enTim3Irq 中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_Mode23_DisableIrq (en_tim3_irq_type_t enTim3Irq) +{ + en_result_t enResult = Ok; + + + switch (enTim3Irq) + { + case Tim3UevIrq: + M0P_TIM3_MODE23->M23CR_f.UIE = FALSE; + break; + case Tim3CA0Irq: + M0P_TIM3_MODE23->CRCH0_f.CIEA = FALSE; + break; + case Tim3CB0Irq: + M0P_TIM3_MODE23->CRCH0_f.CIEB = FALSE; + break; + case Tim3CA1Irq: + M0P_TIM3_MODE23->CRCH1_f.CIEA = FALSE; + break; + case Tim3CB1Irq: + M0P_TIM3_MODE23->CRCH1_f.CIEB = FALSE; + break; + case Tim3CA2Irq: + M0P_TIM3_MODE23->CRCH2_f.CIEA = FALSE; + break; + case Tim3CB2Irq: + M0P_TIM3_MODE23->CRCH2_f.CIEB = FALSE; + break; + case Tim3BkIrq: + M0P_TIM3_MODE23->M23CR_f.BIE = FALSE; + break; + case Tim3TrigIrq: + M0P_TIM3_MODE23->M23CR_f.TIE = FALSE; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 中断æœåŠ¡å‡½æ•° + ** + ** + ** \param [in] u8Param Timer3通é“选择(3 - TIM3) + ** + ** \retval NULL + *****************************************************************************/ +void Tim3_IRQHandler(uint8_t u8Param) +{ + switch (u8Param) + { + case 0: + if(NULL != pfnTim3Callback) + { + pfnTim3Callback(); + } + break; + default: + ; + break; + } +} + + + +/** + ***************************************************************************** + ** \brief Base Timer3 åˆå§‹åŒ–é…ç½®(模å¼0) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_Mode0_Init(stc_tim3_mode0_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE0->M0CR_f.MODE = pstcConfig->enWorkMode; + M0P_TIM3_MODE0->M0CR_f.GATEP = pstcConfig->enGateP; + M0P_TIM3_MODE0->M0CR_f.GATE = pstcConfig->bEnGate; + M0P_TIM3_MODE0->M0CR_f.PRS = pstcConfig->enPRS; + M0P_TIM3_MODE0->M0CR_f.TOGEN = pstcConfig->bEnTog; + M0P_TIM3_MODE0->M0CR_f.CT = pstcConfig->enCT; + M0P_TIM3_MODE0->M0CR_f.MD = pstcConfig->enCntMode; + + pfnTim3Callback = pstcConfig->pfnTim3Cb; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 å¯åŠ¨è¿è¡Œ(模å¼0) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M0_Run(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE0->M0CR_f.CTEN = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 åœæ­¢è¿è¡Œ(模å¼0) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M0_Stop(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE0->M0CR_f.CTEN = FALSE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 翻转输出使能/ç¦æ­¢è®¾å®š(模å¼0) + ** + ** + ** \param [in] bEnOutput 翻转输出设定 TRUE:使能, FALSE:ç¦æ­¢ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M0_EnTOG_Output(boolean_t bEnOutput) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE0->DTR_f.MOE = bEnOutput; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 16ä½è®¡æ•°å™¨åˆå€¼è®¾ç½®(模å¼0) + ** + ** + ** \param [in] u16Data CNT 16ä½åˆå€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M0_Cnt16Set(uint16_t u16Data) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE0->CNT_f.CNT = u16Data; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 16ä½è®¡æ•°å€¼èŽ·å–(模å¼0) + ** + ** + ** \param [in] none + ** + ** \retval 16bits计数值 + *****************************************************************************/ +uint16_t Tim3_M0_Cnt16Get(void) +{ + uint16_t u16CntData = 0; + + u16CntData = M0P_TIM3_MODE0->CNT_f.CNT; + + return u16CntData; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 é‡è½½å€¼è®¾ç½®(模å¼0) + ** + ** + ** \param [in] u16Data 16bitsé‡è½½å€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M0_ARRSet(uint16_t u16Data) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE0->ARR_f.ARR = u16Data; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 32ä½è®¡æ•°å™¨åˆå€¼è®¾ç½®(模å¼0) + ** + ** + ** \param [in] u32Data 32ä½åˆå€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M0_Cnt32Set(uint32_t u32Data) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE0->CNT32_f.CNT32 = u32Data; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 32ä½è®¡æ•°å€¼èŽ·å–(模å¼0) + ** + ** + ** \param [in] none + ** + ** \retval 32bits计数值 + *****************************************************************************/ +uint32_t Tim3_M0_Cnt32Get(void) +{ + uint32_t u32CntData = 0; + + u32CntData = M0P_TIM3_MODE0->CNT32_f.CNT32; + + return u32CntData; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 åˆå§‹åŒ–é…ç½®(模å¼1) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_Mode1_Init(stc_tim3_mode1_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE1->M1CR_f.MODE = pstcConfig->enWorkMode; + M0P_TIM3_MODE1->M1CR_f.PRS = pstcConfig->enPRS; + M0P_TIM3_MODE1->M1CR_f.CT = pstcConfig->enCT; + M0P_TIM3_MODE1->M1CR_f.ONESHOT = pstcConfig->enOneShot; + + pfnTim3Callback = pstcConfig->pfnTim3Cb; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 PWC 输入é…ç½®(模å¼1) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M1_Input_Config(stc_tim3_pwc_input_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE1->MSCR_f.TS = pstcConfig->enTsSel; + M0P_TIM3_MODE1->MSCR_f.IA0S = pstcConfig->enIA0Sel; + M0P_TIM3_MODE1->MSCR_f.IB0S = pstcConfig->enIB0Sel; + M0P_TIM3_MODE1->FLTR_f.ETP = pstcConfig->enETRPhase; + M0P_TIM3_MODE1->FLTR_f.FLTET = pstcConfig->enFltETR; + M0P_TIM3_MODE1->FLTR_f.FLTA0 = pstcConfig->enFltIA0; + M0P_TIM3_MODE1->FLTR_f.FLTB0 = pstcConfig->enFltIB0; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 PWC测é‡è¾¹æ²¿èµ·å§‹ç»“æŸé€‰æ‹©(模å¼1) + ** + ** + ** \param [in] enEdgeSel pwc测é‡èµ·å§‹ç»ˆæ­¢ç”µå¹³ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M1_PWC_Edge_Sel(en_tim3_m1cr_Edge_t enEdgeSel) +{ + en_result_t enResult = Ok; + + switch (enEdgeSel) + { + case 0: ///< 上å‡æ²¿åˆ°ä¸Šå‡æ²¿(周期) + M0P_TIM3_MODE1->M1CR_f.EDG1ST = 0; //上å‡æ²¿ + M0P_TIM3_MODE1->M1CR_f.EDG2ND = 0; //上å‡æ²¿ + break; + case 1: ///< 下é™æ²¿åˆ°ä¸Šå‡æ²¿(低电平) + M0P_TIM3_MODE1->M1CR_f.EDG1ST = 1; //下é™æ²¿ + M0P_TIM3_MODE1->M1CR_f.EDG2ND = 0; //上å‡æ²¿ + break; + case 2: ///< 上å‡æ²¿åˆ°ä¸‹é™æ²¿(高电平) + M0P_TIM3_MODE1->M1CR_f.EDG1ST = 0; //上å‡æ²¿ + M0P_TIM3_MODE1->M1CR_f.EDG2ND = 1; //下é™æ²¿ + break; + case 3: ///< 下é™æ²¿åˆ°ä¸‹é™æ²¿(周期) + M0P_TIM3_MODE1->M1CR_f.EDG1ST = 1; //下é™æ²¿ + M0P_TIM3_MODE1->M1CR_f.EDG2ND = 1; //下é™æ²¿ + break; + default: + ; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 å¯åŠ¨è¿è¡Œ(模å¼1) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M1_Run(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE1->M1CR_f.CTEN = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 åœæ­¢è¿è¡Œ(模å¼1) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M1_Stop(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE1->M1CR_f.CTEN = FALSE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 16ä½è®¡æ•°å™¨åˆå€¼è®¾ç½®(模å¼1) + ** + ** + ** \param [in] u16Data 16ä½åˆå€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M1_Cnt16Set(uint16_t u16Data) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE1->CNT_f.CNT = u16Data; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 16ä½è®¡æ•°å€¼èŽ·å–(模å¼1) + ** + ** + ** \param [in] none + ** + ** \retval 16bits计数值 + *****************************************************************************/ +uint16_t Tim3_M1_Cnt16Get(void) +{ + uint16_t u16CntData = 0; + + u16CntData = M0P_TIM3_MODE1->CNT_f.CNT; + + return u16CntData; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 脉冲宽度测é‡ç»“果数值获å–(模å¼1) + ** + ** + ** \param [in] none + ** + ** \retval 16bits脉冲宽度测é‡ç»“æžœ + *****************************************************************************/ +uint16_t Tim3_M1_PWC_CapValueGet(void) +{ + uint16_t u16CapData = 0; + + u16CapData = M0P_TIM3_MODE1->CCR0A_f.CCR0A; + + return u16CapData; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 åˆå§‹åŒ–é…ç½®(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_Mode23_Init(stc_tim3_mode23_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->M23CR_f.MODE = pstcConfig->enWorkMode; + + M0P_TIM3_MODE23->M23CR_f.PRS = pstcConfig->enPRS; + M0P_TIM3_MODE23->M23CR_f.CT = pstcConfig->enCT; + M0P_TIM3_MODE23->M23CR_f.COMP = pstcConfig->enPWMTypeSel; + M0P_TIM3_MODE23->M23CR_f.PWM2S = pstcConfig->enPWM2sSel; + M0P_TIM3_MODE23->M23CR_f.ONESHOT = pstcConfig->bOneShot; + M0P_TIM3_MODE23->M23CR_f.URS = pstcConfig->bURSSel; + M0P_TIM3_MODE23->M23CR_f.DIR = pstcConfig->enCntDir; + + pfnTim3Callback = pstcConfig->pfnTim3Cb; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 PWM输出使能(模å¼23) + ** + ** + ** \param [in] bEnOutput PWM输出使能/ç¦æ­¢è®¾å®š + ** \param [in] bEnAutoOutput PWM自动输出使能/ç¦æ­¢è®¾å®š + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_EnPWM_Output(boolean_t bEnOutput, boolean_t bEnAutoOutput) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->DTR_f.MOE = bEnOutput; + M0P_TIM3_MODE23->DTR_f.AOE = bEnAutoOutput; + + return enResult; +} + + +/** + ***************************************************************************** + ** \brief Base Timer3 å¯åŠ¨è¿è¡Œ(模å¼23) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_Run(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->M23CR_f.CTEN = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 åœæ­¢è¿è¡Œ(模å¼23) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_Stop(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->M23CR_f.CTEN = FALSE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 é‡è½½å€¼è®¾ç½®(模å¼23) + ** + ** + ** \param [in] u16Data 16bitsé‡è½½å€¼ + ** \param [in] bArrBufEn ARRé‡è½½ç¼“存使能TRUE/ç¦æ­¢FALSE + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_ARRSet(uint16_t u16Data, boolean_t bArrBufEn) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->ARR_f.ARR = u16Data; + M0P_TIM3_MODE23->M23CR_f.BUFPEN = bArrBufEn; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 16ä½è®¡æ•°å™¨åˆå€¼è®¾ç½®(模å¼23) + ** + ** + ** \param [in] u16Data 16ä½åˆå€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_Cnt16Set(uint16_t u16Data) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->CNT_f.CNT = u16Data; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 16ä½è®¡æ•°å€¼èŽ·å–(模å¼23) + ** + ** + ** \param [in] none + ** + ** \retval 16bits计数值 + *****************************************************************************/ +uint16_t Tim3_M23_Cnt16Get(void) +{ + uint16_t u16CntData = 0; + + u16CntData = M0P_TIM3_MODE23->CNT_f.CNT; + + return u16CntData; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 比较æ•èŽ·å¯„存器CCRxA/CCRxB设置(模å¼23) + ** + ** + ** \param [in] enCCRSel CCRxA/CCRxB设定 + ** \param [in] u16Data CCRxA/CCRxB 16ä½åˆå§‹å€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_CCR_Set(en_tim3_m23_ccrx_t enCCRSel, uint16_t u16Data) +{ + en_result_t enResult = Ok; + + if(Tim3CCR0A == enCCRSel) + { + M0P_TIM3_MODE23->CCR0A_f.CCR0A = u16Data; + } + else if(Tim3CCR0B == enCCRSel) + { + M0P_TIM3_MODE23->CCR0B_f.CCR0B = u16Data; + } + else if(Tim3CCR1A == enCCRSel) + { + M0P_TIM3_MODE23->CCR1A_f.CCR1A = u16Data; + } + else if(Tim3CCR1B == enCCRSel) + { + M0P_TIM3_MODE23->CCR1B_f.CCR1B = u16Data; + } + else if(Tim3CCR2A == enCCRSel) + { + M0P_TIM3_MODE23->CCR2A_f.CCR2A = u16Data; + } + else if(Tim3CCR2B == enCCRSel) + { + M0P_TIM3_MODE23->CCR2B_f.CCR2B = u16Data; + } + else + { + enResult = Error; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 比较æ•èŽ·å¯„存器CCRxA/CCRxB读å–(模å¼23) + ** + ** + ** \param [in] enCCRSel CCRxA/CCRxB设定 + ** + ** \retval 16bitsCCRxA/CCRxBæ•èŽ·å€¼ + *****************************************************************************/ +uint16_t Tim3_M23_CCR_Get(en_tim3_m23_ccrx_t enCCRSel) +{ + uint16_t u16Data = 0; + + if(Tim3CCR0A == enCCRSel) + { + u16Data = M0P_TIM3_MODE23->CCR0A_f.CCR0A; + } + else if(Tim3CCR0B == enCCRSel) + { + u16Data = M0P_TIM3_MODE23->CCR0B_f.CCR0B; + } + else if(Tim3CCR1A == enCCRSel) + { + u16Data = M0P_TIM3_MODE23->CCR1A_f.CCR1A; + } + else if(Tim3CCR1B == enCCRSel) + { + u16Data = M0P_TIM3_MODE23->CCR1B_f.CCR1B; + } + else if(Tim3CCR2A == enCCRSel) + { + u16Data = M0P_TIM3_MODE23->CCR2A_f.CCR2A; + } + else if(Tim3CCR2B == enCCRSel) + { + u16Data = M0P_TIM3_MODE23->CCR2B_f.CCR2B; + } + else + { + u16Data = 0; + } + + return u16Data; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 PWM互补输出模å¼ä¸‹ï¼ŒGATE功能选择(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_GateFuncSel(stc_tim3_m23_gate_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->M23CR_f.CSG = pstcConfig->enGateFuncSel; + M0P_TIM3_MODE23->M23CR_f.CRG = pstcConfig->bGateRiseCap; + M0P_TIM3_MODE23->M23CR_f.CFG = pstcConfig->bGateFallCap; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 主从模å¼é…ç½®(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_MasterSlave_Set(stc_tim3_m23_master_slave_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->MSCR_f.MSM = pstcConfig->enMasterSlaveSel; + M0P_TIM3_MODE23->MSCR_f.MMS = pstcConfig->enMasterSrc; + M0P_TIM3_MODE23->MSCR_f.SMS = pstcConfig->enSlaveModeSel; + M0P_TIM3_MODE23->MSCR_f.TS = pstcConfig->enTsSel; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 CHxA/CHxB比较通é“控制(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** \param [in] enTim3Chx Timer3通é“(Tim3CH0, Tim3CH1, Tim3CH2) + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_PortOutput_Config(en_tim3_channel_t enTim3Chx, stc_tim3_m23_compare_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + switch (enTim3Chx) + { + case Tim3CH0: + M0P_TIM3_MODE23->CRCH0_f.CSA = 0; + M0P_TIM3_MODE23->FLTR_f.OCMA0_FLTA0 = pstcConfig->enCHxACmpCtrl; + M0P_TIM3_MODE23->FLTR_f.CCPA0 = pstcConfig->enCHxAPolarity; + M0P_TIM3_MODE23->CRCH0_f.BUFEA = pstcConfig->bCHxACmpBufEn; + M0P_TIM3_MODE23->M23CR_f.CIS = pstcConfig->enCHxACmpIntSel; + + M0P_TIM3_MODE23->CRCH0_f.CSB = 0; + M0P_TIM3_MODE23->FLTR_f.OCMB0_FLTB0 = pstcConfig->enCHxBCmpCtrl; + M0P_TIM3_MODE23->FLTR_f.CCPB0 = pstcConfig->enCHxBPolarity; + M0P_TIM3_MODE23->CRCH0_f.BUFEB = pstcConfig->bCHxBCmpBufEn; + M0P_TIM3_MODE23->CRCH0_f.CISB = pstcConfig->enCHxBCmpIntSel; + break; + case Tim3CH1: + M0P_TIM3_MODE23->CRCH1_f.CSA = 0; + M0P_TIM3_MODE23->FLTR_f.OCMA1_FLTA1 = pstcConfig->enCHxACmpCtrl; + M0P_TIM3_MODE23->FLTR_f.CCPA1 = pstcConfig->enCHxAPolarity; + M0P_TIM3_MODE23->CRCH1_f.BUFEA = pstcConfig->bCHxACmpBufEn; + M0P_TIM3_MODE23->M23CR_f.CIS = pstcConfig->enCHxACmpIntSel; + + M0P_TIM3_MODE23->CRCH1_f.CSB = 0; + M0P_TIM3_MODE23->FLTR_f.OCMB1_FLTB1 = pstcConfig->enCHxBCmpCtrl; + M0P_TIM3_MODE23->FLTR_f.CCPB1 = pstcConfig->enCHxBPolarity; + M0P_TIM3_MODE23->CRCH1_f.BUFEB = pstcConfig->bCHxBCmpBufEn; + M0P_TIM3_MODE23->CRCH1_f.CISB = pstcConfig->enCHxBCmpIntSel; + break; + case Tim3CH2: + M0P_TIM3_MODE23->CRCH2_f.CSA = 0; + M0P_TIM3_MODE23->FLTR_f.OCMA2_FLTA2 = pstcConfig->enCHxACmpCtrl; + M0P_TIM3_MODE23->FLTR_f.CCPA2 = pstcConfig->enCHxAPolarity; + M0P_TIM3_MODE23->CRCH2_f.BUFEA = pstcConfig->bCHxACmpBufEn; + M0P_TIM3_MODE23->M23CR_f.CIS = pstcConfig->enCHxACmpIntSel; + + M0P_TIM3_MODE23->CRCH2_f.CSB = 0; + M0P_TIM3_MODE23->FLTR_f.OCMB2_FLTB2 = pstcConfig->enCHxBCmpCtrl; + M0P_TIM3_MODE23->FLTR_f.CCPB2 = pstcConfig->enCHxBPolarity; + M0P_TIM3_MODE23->CRCH2_f.BUFEB = pstcConfig->bCHxBCmpBufEn; + M0P_TIM3_MODE23->CRCH2_f.CISB = pstcConfig->enCHxBCmpIntSel; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 CHxA/CHxB输入控制(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** \param [in] enTim3Chx Timer3通é“(Tim3CH0, Tim3CH1, Tim3CH2) + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_PortInput_Config(en_tim3_channel_t enTim3Chx, stc_tim3_m23_input_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + switch (enTim3Chx) + { + case Tim3CH0: + M0P_TIM3_MODE23->CRCH0_f.CSA = 1; + M0P_TIM3_MODE23->CRCH0_f.CFA_CRA_BKSA = pstcConfig->enCHxACapSel; + M0P_TIM3_MODE23->FLTR_f.OCMA0_FLTA0 = pstcConfig->enCHxAInFlt; + M0P_TIM3_MODE23->FLTR_f.CCPA0 = pstcConfig->enCHxAPolarity; + + M0P_TIM3_MODE23->CRCH0_f.CSB = 1; + M0P_TIM3_MODE23->CRCH0_f.CFB_CRB_BKSB = pstcConfig->enCHxBCapSel; + M0P_TIM3_MODE23->FLTR_f.OCMB0_FLTB0 = pstcConfig->enCHxBInFlt; + M0P_TIM3_MODE23->FLTR_f.CCPB0 = pstcConfig->enCHxBPolarity; + break; + case Tim3CH1: + M0P_TIM3_MODE23->CRCH1_f.CSA = 1; + M0P_TIM3_MODE23->CRCH1_f.CFA_CRA_BKSA = pstcConfig->enCHxACapSel; + M0P_TIM3_MODE23->FLTR_f.OCMA1_FLTA1 = pstcConfig->enCHxAInFlt; + M0P_TIM3_MODE23->FLTR_f.CCPA1 = pstcConfig->enCHxAPolarity; + + M0P_TIM3_MODE23->CRCH1_f.CSB = 1; + M0P_TIM3_MODE23->CRCH1_f.CFB_CRB_BKSB = pstcConfig->enCHxBCapSel; + M0P_TIM3_MODE23->FLTR_f.OCMB1_FLTB1 = pstcConfig->enCHxBInFlt; + M0P_TIM3_MODE23->FLTR_f.CCPB1 = pstcConfig->enCHxBPolarity; + break; + case Tim3CH2: + M0P_TIM3_MODE23->CRCH2_f.CSA = 1; + M0P_TIM3_MODE23->CRCH2_f.CFA_CRA_BKSA = pstcConfig->enCHxACapSel; + M0P_TIM3_MODE23->FLTR_f.OCMA2_FLTA2 = pstcConfig->enCHxAInFlt; + M0P_TIM3_MODE23->FLTR_f.CCPA2 = pstcConfig->enCHxAPolarity; + + M0P_TIM3_MODE23->CRCH2_f.CSB = 1; + M0P_TIM3_MODE23->CRCH2_f.CFB_CRB_BKSB = pstcConfig->enCHxBCapSel; + M0P_TIM3_MODE23->FLTR_f.OCMB2_FLTB2 = pstcConfig->enCHxBInFlt; + M0P_TIM3_MODE23->FLTR_f.CCPB2 = pstcConfig->enCHxBPolarity; + break; + default: + enResult = Error; + break; + } + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 ERT输入控制(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_ETRInput_Config(stc_tim3_m23_etr_input_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->FLTR_f.ETP = pstcConfig->enETRPolarity; + M0P_TIM3_MODE23->FLTR_f.FLTET = pstcConfig->enETRFlt; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 刹车BK输入控制(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_BrakeInput_Config(stc_tim3_m23_bk_input_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->DTR_f.BKE = pstcConfig->bEnBrake; + M0P_TIM3_MODE23->DTR_f.VC0E = pstcConfig->bEnVC0Brake; + M0P_TIM3_MODE23->DTR_f.VC1E = pstcConfig->bEnVC1Brake; + M0P_TIM3_MODE23->DTR_f.SAFEEN = pstcConfig->bEnSafetyBk; + M0P_TIM3_MODE23->DTR_f.BKSEL = pstcConfig->bEnBKSync; + M0P_TIM3_MODE23->CRCH0_f.CFA_CRA_BKSA = pstcConfig->enBkCH0AStat; + M0P_TIM3_MODE23->CRCH0_f.CFB_CRB_BKSB = pstcConfig->enBkCH0BStat; + M0P_TIM3_MODE23->CRCH1_f.CFA_CRA_BKSA = pstcConfig->enBkCH1AStat; + M0P_TIM3_MODE23->CRCH1_f.CFB_CRB_BKSB = pstcConfig->enBkCH1BStat; + M0P_TIM3_MODE23->CRCH2_f.CFA_CRA_BKSA = pstcConfig->enBkCH2AStat; + M0P_TIM3_MODE23->CRCH2_f.CFB_CRB_BKSB = pstcConfig->enBkCH2BStat; + M0P_TIM3_MODE23->FLTR_f.BKP = pstcConfig->enBrakePolarity; + M0P_TIM3_MODE23->FLTR_f.FLTBK = pstcConfig->enBrakeFlt; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 触å‘ADC控制(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_TrigADC_Config(stc_tim3_m23_adc_trig_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->ADTR_f.ADTE = pstcConfig->bEnTrigADC; + M0P_TIM3_MODE23->ADTR_f.UEVE = pstcConfig->bEnUevTrigADC; + M0P_TIM3_MODE23->ADTR_f.CMA0E = pstcConfig->bEnCH0ACmpTrigADC; + M0P_TIM3_MODE23->ADTR_f.CMB0E = pstcConfig->bEnCH0BCmpTrigADC; + M0P_TIM3_MODE23->ADTR_f.CMA1E = pstcConfig->bEnCH1ACmpTrigADC; + M0P_TIM3_MODE23->ADTR_f.CMB1E = pstcConfig->bEnCH1BCmpTrigADC; + M0P_TIM3_MODE23->ADTR_f.CMA2E = pstcConfig->bEnCH2ACmpTrigADC; + M0P_TIM3_MODE23->ADTR_f.CMB2E = pstcConfig->bEnCH2BCmpTrigADC; + return enResult; +} + +/** + ***************************************************************************** +** \brief Base Timer3 死区功能(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_DT_Config(stc_tim3_m23_dt_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->DTR_f.DTEN = pstcConfig->bEnDeadTime; + M0P_TIM3_MODE23->DTR_f.DTR = pstcConfig->u8DeadTimeValue; + + return enResult; +} + +/** + ***************************************************************************** +** \brief Base Timer3 é‡å¤å‘¨æœŸè®¾ç½®(模å¼23) + ** + ** + ** \param [in] u8ValidPeriod é‡å¤å‘¨æœŸå€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_SetValidPeriod(uint8_t u8ValidPeriod) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->RCR_f.RCR = u8ValidPeriod; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 OCREF清除功能(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_OCRefClr(stc_tim3_m23_OCREF_Clr_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->M23CR_f.OCCS = pstcConfig->enOCRefClrSrcSel; + M0P_TIM3_MODE23->M23CR_f.OCCE = pstcConfig->bVCClrEn; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 使能DMA传输(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_EnDMA(stc_tim3_m23_trig_dma_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->M23CR_f.UDE = pstcConfig->bUevTrigDMA; + M0P_TIM3_MODE23->M23CR_f.TDE = pstcConfig->bTITrigDMA; + M0P_TIM3_MODE23->CRCH0_f.CDEA = pstcConfig->bCmpA0TrigDMA; + M0P_TIM3_MODE23->CRCH0_f.CDEB = pstcConfig->bCmpB0TrigDMA; + M0P_TIM3_MODE23->CRCH1_f.CDEA = pstcConfig->bCmpA1TrigDMA; + M0P_TIM3_MODE23->CRCH1_f.CDEB = pstcConfig->bCmpB1TrigDMA; + M0P_TIM3_MODE23->CRCH2_f.CDEA = pstcConfig->bCmpA2TrigDMA; + M0P_TIM3_MODE23->CRCH2_f.CDEB = pstcConfig->bCmpB2TrigDMA; + M0P_TIM3_MODE23->MSCR_f.CCDS = pstcConfig->enCmpUevTrigDMA; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 æ•èŽ·æ¯”较A软件触å‘(模å¼23) + ** + ** + ** \param [in] enTim3Chx Timer3通é“(Tim3CH0, Tim3CH1, Tim3CH2) + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_EnSwTrigCapCmpA(en_tim3_channel_t enTim3Chx) +{ + en_result_t enResult = Ok; + if(Tim3CH0 == enTim3Chx) + { + M0P_TIM3_MODE23->CRCH0_f.CCGA = TRUE; + } + else if(Tim3CH1 == enTim3Chx) + { + M0P_TIM3_MODE23->CRCH1_f.CCGA = TRUE; + } + else if(Tim3CH2 == enTim3Chx) + { + M0P_TIM3_MODE23->CRCH2_f.CCGA = TRUE; + } + else + { + enResult = Error; + } + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 æ•èŽ·æ¯”较B软件触å‘(模å¼23) + ** + ** + ** \param [in] enTim3Chx Timer3通é“(Tim3CH0, Tim3CH1, Tim3CH2) + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_EnSwTrigCapCmpB(en_tim3_channel_t enTim3Chx) +{ + en_result_t enResult = Ok; + if(Tim3CH0 == enTim3Chx) + { + M0P_TIM3_MODE23->CRCH0_f.CCGB = TRUE; + } + else if(Tim3CH1 == enTim3Chx) + { + M0P_TIM3_MODE23->CRCH1_f.CCGB = TRUE; + } + else if(Tim3CH2 == enTim3Chx) + { + M0P_TIM3_MODE23->CRCH2_f.CCGB = TRUE; + } + else + { + enResult = Error; + } + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 软件更新使能(模å¼23) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_EnSwUev(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->M23CR_f.UG = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 软件触å‘使能(模å¼23) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_EnSwTrig(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->M23CR_f.TG = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 软件刹车使能(模å¼23) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_EnSwBk(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->M23CR_f.BG = TRUE; + + return enResult; +} + +//@} // Tim3Group + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/trim.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/trim.c new file mode 100644 index 0000000000..413a8fc248 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/trim.c @@ -0,0 +1,348 @@ +/****************************************************************************** +*Copyright(C)2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file trim.c + ** + ** Common API of trim. + ** @link trimGroup Some description @endlink + ** + ** - 2017-05-16 + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "trim.h" +/** + ******************************************************************************* + ** \addtogroup TrimGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +#define IS_VALID_TRIMINT(x) (TrimStop == (x) ||\ + TrimCalCntOf == (x) ||\ + TrimXTLFault == (x) ||\ + TrimXTHFault == (x) ||\ + TrimPLLFault == (x)) + + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static func_ptr_t pfnTrimCallback = NULL; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ***************************************************************************** + ** \brief Trimä¸­æ–­æ ‡å¿—èŽ·å– + ** + ** + ** \param [in] enIntType 中断类型（RefStopã€CalCntOfã€XTAL32KFaultã€XTAL32MFault） + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +boolean_t Trim_GetIntFlag(en_trim_inttype_t enIntType) +{ + boolean_t bRetVal = FALSE; + + ASSERT(IS_VALID_TRIMINT(enIntType)); + + switch (enIntType) + { + case TrimStop: + bRetVal = M0P_CLK_TRIM->IFR_f.STOP ? TRUE : FALSE; + break; + case TrimCalCntOf: + bRetVal = M0P_CLK_TRIM->IFR_f.CALCNT_OF ? TRUE : FALSE; + break; + case TrimXTLFault: + bRetVal = M0P_CLK_TRIM->IFR_f.XTL_FAULT ? TRUE : FALSE; + break; + case TrimXTHFault: + bRetVal = M0P_CLK_TRIM->IFR_f.XTH_FAULT ? TRUE : FALSE; + break; + case TrimPLLFault: + bRetVal = M0P_CLK_TRIM->IFR_f.PLL_FAULT ? TRUE : FALSE; + break; + default: + bRetVal = FALSE; + break; + } + + return bRetVal; +} + +/** + ***************************************************************************** + ** \brief Trim中断标志清除 + ** + ** + ** \param [in] enIntType 中断类型（RefStopã€CalCntOfã€XTAL32KFaultã€XTAL32MFault） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Trim_ClearIntFlag(en_trim_inttype_t enIntType) +{ + en_result_t enResult = Error; + + ASSERT(IS_VALID_TRIMINT(enIntType)); + + switch (enIntType) + { + case TrimStop: + M0P_CLK_TRIM->CR_f.TRIM_START = FALSE; + enResult = Ok; + break; + case TrimCalCntOf: + M0P_CLK_TRIM->CR_f.TRIM_START = FALSE; + enResult = Ok; + break; + case TrimXTLFault: + M0P_CLK_TRIM->ICLR_f.XTL_FAULT_CLR = FALSE; + enResult = Ok; + break; + case TrimXTHFault: + M0P_CLK_TRIM->ICLR_f.XTH_FAULT_CLR = FALSE; + enResult = Ok; + break; + case TrimPLLFault: + M0P_CLK_TRIM->ICLR_f.PLL_FAULT_CLR = FALSE; + enResult = Ok; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Trim中断æœåŠ¡å‡½æ•° + ** + ** + ** \param [in] u8Param == 0 + ** + ** \retval NULL + *****************************************************************************/ +void ClkTrim_IRQHandler(uint8_t u8Param) +{ + if(NULL != pfnTrimCallback) + { + pfnTrimCallback(); + } +} + +/** + ***************************************************************************** + ** \brief Trim中断使能 + ** + ** + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Trim_EnableIrq (void) +{ + en_result_t enResult = Error; + + M0P_CLK_TRIM->CR_f.IE = TRUE; + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Trim中断ç¦æ­¢ + ** + ** + ** + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Trim_DisableIrq(void) +{ + en_result_t enResult = Error; + + M0P_CLK_TRIM->CR_f.IE = FALSE; + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Trimåˆå§‹åŒ–é…ç½® + ** + ** + ** \param [in] pstcConfig Trimé…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Trim_Init(stc_trim_config_t* pstcConfig) +{ + en_result_t enResult = Error; + + M0P_CLK_TRIM->CR_f.MON_EN = pstcConfig->enMON; + + if (TrimCalPLL == pstcConfig->enCALCLK) + { + M0P_CLK_TRIM->CR_f.CALCLK_SEL2 = TRUE; + M0P_CLK_TRIM->CR_f.CALCLK_SEL = pstcConfig->enCALCLK; + } + else + { + M0P_CLK_TRIM->CR_f.CALCLK_SEL2 = FALSE; + M0P_CLK_TRIM->CR_f.CALCLK_SEL = pstcConfig->enCALCLK; + } + + M0P_CLK_TRIM->CR_f.REFCLK_SEL = pstcConfig->enREFCLK; + + M0P_CLK_TRIM->REFCON_f.RCNTVAL = pstcConfig->u32RefCon; + if(TrimMonEnable == pstcConfig->enMON) + { + M0P_CLK_TRIM->CALCON_f.CCNTVAL = pstcConfig->u32CalCon; + } + + + pfnTrimCallback = pstcConfig->pfnTrimCb; + + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Trim校准/监测å¯åŠ¨è¿è¡Œ + ** + ** + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Trim_Run(void) +{ + en_result_t enResult = Error; + + M0P_CLK_TRIM->CR_f.TRIM_START = TRUE; + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Trim校准/监测åœæ­¢ + ** + ** + ** + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Trim_Stop(void) +{ + en_result_t enResult = Error; + + M0P_CLK_TRIM->CR_f.TRIM_START = FALSE; + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Trimå‚è€ƒè®¡æ•°å™¨è®¡æ•°å€¼èŽ·å– + ** + ** + ** \retval u32Data å‚考计数器计数值 + *****************************************************************************/ +uint32_t Trim_RefCntGet(void) +{ + uint32_t u32Data = 0; + + u32Data = M0P_CLK_TRIM->REFCNT_f.REFCNT; + + return u32Data; +} + +/** + ***************************************************************************** + ** \brief Trimæ ¡å‡†è®¡æ•°å™¨è®¡æ•°å€¼èŽ·å– + ** + ** + ** + ** + ** \retval u32Data 校准计数器计数值 + *****************************************************************************/ +uint32_t Trim_CalCntGet(void) +{ + uint32_t u32Data = 0; + + u32Data = M0P_CLK_TRIM->CALCNT_f.CALCNT; + + return u32Data; +} + +//@} // TrimGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/uart.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/uart.c new file mode 100644 index 0000000000..f17a7ccc61 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/uart.c @@ -0,0 +1,910 @@ +/************************************************************************************* +* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file uart.c + ** + ** UART function driver API. + ** @link SampleGroup Some description @endlink + ** + ** - 2017-05-17 1.0 CJ First version for Device Driver Library of Module. + ** + ******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "uart.h" +/** + ****************************************************************************** + ** \addtogroup UartGroup + ******************************************************************************/ +//@{ +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +#define IS_VALID_CH(x) ((UARTCH0 == (x)) ||\ + (UARTCH1 == (x))) + +#define IS_VALID_IRQSEL(x) ((UartTxIrq == (x)) ||\ + (UartRxIrq == (x)) ||\ + (UartFEIrq == (x)) ||\ + (UartCtsIrq == (x))||\ + (UartPEIrq == (x)) ||\ + (UartTxEIrq == (x))) + +#define IS_VALID_MODE(x) ((UartMode0==(x))||\ + (UartMode1==(x))||\ + (UartMode2==(x))||\ + (UartMode3==(x))) + +#define IS_VALID_STATUS(x) ((UartCts == (x))||\ + (UartRC == (x))||\ + (UartTC == (x))||\ + (UartPE == (x))||\ + (UartCtsIf == (x))||\ + (UartTxe == (x))||\ + (UartFE == (x))) +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ +static stc_uart_instance_data_t* UartGetInternDataPtr(uint8_t u8Idx); +static void UartInitNvic(uint8_t u8Idx); +static void UartDeInitNvic(uint8_t u8Idx); +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ +static stc_uart_instance_data_t m_astcUartInstanceDataLut[] = +{ + { + UARTCH0, + M0P_UART0, /* pstcInstance */ + {NULL,NULL,NULL,NULL,NULL}, + }, + { + UARTCH1, + M0P_UART1, /* pstcInstance */ + {NULL,NULL,NULL,NULL,NULL}, + }, +}; +/** + ****************************************************************************** + ** \brief UART0/1é€šé“ ç›¸å…³åœ°å€èŽ·å– + ** + ** \param [in] u8Idx通é“å· + ** + ** \retval 通é“对应的地å€ç»“æž„ + ** + ******************************************************************************/ +static stc_uart_instance_data_t* UartGetInternDataPtr(uint8_t u8Idx) +{ + stc_uart_instance_data_t* pstcData = NULL; + uint8_t u8i = 0; + for (u8i = 0; u8i < ARRAY_SZ(m_astcUartInstanceDataLut); u8i++) + { + if (u8Idx == m_astcUartInstanceDataLut[u8i].u32Idx) + { + pstcData = &m_astcUartInstanceDataLut[u8i]; + break; + } + } + + return (pstcData); +} +/** + ****************************************************************************** + ** \brief UART通信中断使能函数设置 + ** + ** \param [in] u8Idx通é“å·ï¼ŒenIrqSelå‘é€or接收中断使能 + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t Uart_EnableIrq(uint8_t u8Idx, + en_uart_irq_sel_t enIrqSel) +{ + stc_uart_instance_data_t* pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + ASSERT(IS_VALID_IRQSEL(enIrqSel)); + pstcData = UartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + switch(enIrqSel) + { + case UartTxIrq: + pstcData->pstcInstance->SCON_f.TCIE = 1u; + break; + case UartRxIrq: + pstcData->pstcInstance->SCON_f.RCIE = 1u; + break; + case UartFEIrq: + pstcData->pstcInstance->SCON_f.FEIE = 1u; + break; + case UartCtsIrq: + pstcData->pstcInstance->SCON_f.CTSIE = 1u; + break; + case UartPEIrq: + pstcData->pstcInstance->SCON_f.PEIE = 1u; + break; + case UartTxEIrq: + pstcData->pstcInstance->SCON_f.TXEIE = 1u; + break; + default: + return (ErrorInvalidParameter); + } + return Ok; +} +/** + ****************************************************************************** + ** \brief UART通信中断ç¦æ­¢å‡½æ•°è®¾ç½® + ** + ** \param [in] u8Idx通é“å·ï¼ŒenIrqSelå‘é€or接收中断ç¦æ­¢ + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t Uart_DisableIrq(uint8_t u8Idx, + en_uart_irq_sel_t enIrqSel) +{ + stc_uart_instance_data_t *pstcData = NULL; + + ASSERT(IS_VALID_CH(u8Idx)); + ASSERT(IS_VALID_IRQSEL(enIrqSel)); + + pstcData = UartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + switch(enIrqSel) + { + case UartTxIrq: + pstcData->pstcInstance->SCON_f.TCIE = 0u; + break; + case UartRxIrq: + pstcData->pstcInstance->SCON_f.RCIE = 0u; + break; + case UartFEIrq: + pstcData->pstcInstance->SCON_f.FEIE = 0u; + break; + case UartCtsIrq: + pstcData->pstcInstance->SCON_f.CTSIE = 0u; + break; + case UartPEIrq: + pstcData->pstcInstance->SCON_f.PEIE = 0u; + break; + case UartTxEIrq: + pstcData->pstcInstance->SCON_f.TXEIE = 0u; + break; + default: + return (ErrorInvalidParameter); + } + + return Ok; +} +/** + ****************************************************************************** + ** \brief UART通é“4ç§æ¨¡å¼é…ç½® + ** + ** \param [in] u8Idx通é“å·ï¼Œmode哪ç§æ¨¡å¼ + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t Uart_SetMode(uint8_t u8Idx,en_uart_mode_t enMode) +{ + stc_uart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + ASSERT(IS_VALID_MODE(enMode)); + pstcData = UartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + pstcData->pstcInstance->SCON_f.SM = enMode; + return Ok; +} +/** + ****************************************************************************** + ** \brief UART通é“多主机模å¼é…ç½® + ** + ** \param [in] u8Idx通é“å·ï¼ŒstcMultiConfig多主机模å¼ç»“æž„ + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t Uart_SetMultiMode(uint8_t u8Idx,stc_uart_multimode_t* pstcMultiConfig) +{ + stc_uart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = UartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + if(NULL != pstcMultiConfig) + { + pstcData->pstcInstance->SCON_f.ADRDET = pstcMultiConfig->enMulti_mode; + if(pstcMultiConfig->enMulti_mode == UartMulti) + { + pstcData->pstcInstance->SADDR = pstcMultiConfig->u8SlaveAddr; + pstcData->pstcInstance->SADEN = pstcMultiConfig->u8SaddEn; + } + } + return Ok; +} +/** + ****************************************************************************** + ** \brief UART通é“多主机模å¼å‘é€æ•°æ®/地å€å¸§æˆ–者奇å¶æ ¡éªŒé…ç½®TB8 + ** + ** \param [in] u8Idx通é“å·ï¼Œtb8æ•°æ®or地å€å¸§æˆ–者奇å¶æ ¡éªŒ + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t Uart_SetMMDOrCk(uint8_t u8Idx,en_uart_mmdorck_t enTb8) +{ + stc_uart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = UartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + pstcData->pstcInstance->SCON_f.B8CONT = enTb8; + return Ok; +} +/** + ****************************************************************************** + ** \brief 获å–RB8数值 + ** + ** \param [in] u8Idx通é“å· + ** + ** \retval RB8 + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +boolean_t Uart_GetRb8(uint8_t u8Idx) +{ + stc_uart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = UartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + return (pstcData->pstcInstance->SBUF_f.DATA8); +} +/** + ****************************************************************************** + ** \brief UART通é“多主机模å¼ä»Žæœºåœ°å€é…置函数 + ** + ** \param [in] u8Idx通é“å·ï¼Œaddråœ°å€ + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t Uart_SetSaddr(uint8_t u8Idx,uint8_t u8Addr) +{ + stc_uart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = UartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + pstcData->pstcInstance->SADDR = u8Addr; + return Ok; +} +/** + ****************************************************************************** + ** \brief UART通é“多主机模å¼ä»ŽæœºæŽ©ç é…置函数 + ** + ** \param [in] u8Idx通é“å·ï¼Œaddren地å€æŽ©ç  + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t Uart_SetSaddrEn(uint8_t u8Idx,uint8_t u8Addren) +{ + stc_uart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = UartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + pstcData->pstcInstance->SADEN = u8Addren; + return Ok; +} +/** + ****************************************************************************** + ** \brief UART通é“åœæ­¢ä½é•¿åº¦è®¾ç½® + ** + ** \param [in] u8Idx通é“å·ï¼Œu8Lenåœæ­¢ä½é•¿åº¦ + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t Uart_SetStopBit(uint8_t u8Idx,uint8_t u8Len) +{ + stc_uart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = UartGetInternDataPtr(u8Idx); + switch(u8Len) + { + case Uart1bit: + case Uart15bit: + case Uart2bit: + pstcData->pstcInstance->SCON_f.STOPBIT = u8Len; + break; + default: + return ErrorInvalidParameter; + } + return Ok; +} +/** + ****************************************************************************** + ** \brief UART采样频率é…ç½® + ** + ** \param [in] u8Idx通é“å·ï¼Œu8Div采样频率 + ** + ** \retval OKé…ç½®æˆåŠŸ + ******************************************************************************/ +en_result_t Uart_SetClkDiv(uint8_t u8Idx,en_uart_clkdiv_t enClkDiv) +{ + stc_uart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = UartGetInternDataPtr(u8Idx); + pstcData->pstcInstance->SCON_f.OVER = enClkDiv; + return Ok; +} +/** + ****************************************************************************** + ** \brief UART通é“波特率é…置值计算 + ** + ** \param [in] u8Idx通é“å·ï¼ŒpstcBaud波特率， + ** + ** \retval 定时器é…置值 + ** \retval 0,获å–值失败,u16Scnt波特率设置值 + ******************************************************************************/ +uint16_t Uart_CalScnt(uint8_t u8Idx,stc_uart_baud_t *pstcBaud) +{ + stc_uart_instance_data_t *pstcData = NULL; + uint16_t u16Scnt = 0; + uint8_t u8Over = 0; + ASSERT(IS_VALID_CH(u8Idx)); + + pstcData = UartGetInternDataPtr(u8Idx); + u8Over = pstcData->pstcInstance->SCON_f.OVER; + if(UartMode0 == pstcBaud->enRunMode) + { + return 0;//test + } + if((UartMode1 == pstcBaud->enRunMode)||(UartMode3 == pstcBaud->enRunMode)) + { + if(0 == u8Over) + { + u8Over = 16; + } + else + { + u8Over = 8; + } + + u16Scnt = pstcBaud->u32Pclk/(pstcBaud->u32Baud*u8Over); + } + else + { + if(0 == u8Over) + { + u8Over = 32; + } + else + { + u8Over = 16; + } + u16Scnt = pstcBaud->u32Pclk/u8Over; + } + return u16Scnt; +} +/** + ****************************************************************************** + ** \brief UART通é“波特率é…ç½® + ** + ** \param [in] u8Idx通é“å·ï¼Œu16Scnt波特率设置 + ** + ** \retval 定时器é…置值 + ** \retval 0,获å–值失败 + ******************************************************************************/ +en_result_t Uart_SetBaud(uint8_t u8Idx,uint16_t u16Scnt) +{ + stc_uart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = UartGetInternDataPtr(u8Idx); + pstcData->pstcInstance->SCNT = u16Scnt; + return Ok; +} + +/** + ****************************************************************************** + ** \brief UART通é“æ³¢ç‰¹çŽ‡èŽ·å– + ** + ** \param [in] u8Idx通é“å·,u8Modeå·¥ä½œæ¨¡å¼ + ** + ** \retval 波特率 + ******************************************************************************/ +uint32_t Uart_GetBaud(uint8_t u8Idx,uint8_t u8Mode,uint32_t u32Pclk) +{ + stc_uart_instance_data_t *pstcData = NULL; + uint32_t u32Baud = 0; + uint8_t u8Over = 0; + uint16_t u16Scnt = 0; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = UartGetInternDataPtr(u8Idx); + u16Scnt = pstcData->pstcInstance->SCNT; + + switch(u8Mode) + { + case UartMode0: + u32Baud = u32Pclk/12; + break; + case UartMode1: + case UartMode3: + if(0 == pstcData->pstcInstance->SCON_f.OVER) + { + u8Over = 16; + } + else + { + u8Over = 8; + } + u32Baud = u32Pclk/(u8Over*u16Scnt); + break; + case UartMode2: + if(0 == pstcData->pstcInstance->SCON_f.OVER) + { + u8Over = 32; + } + else + { + u8Over = 16; + } + u32Baud = u32Pclk/u8Over; + break; + default : + return 0;//test + } + return u32Baud; +} +/** + ****************************************************************************** + ** \brief UART通é“å‘é€æˆ–接收等功能使能设置 + ** + ** \param [in] u8Idx通é“å·ï¼ŒenFunc功能 + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t Uart_EnableFunc(uint8_t u8Idx, en_uart_func_t enFunc) +{ + stc_uart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = UartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + switch(enFunc) + { + case UartTx: + case UartRx: + pstcData->pstcInstance->SCON_f.REN = 1u; + break; + case UartDmaTx: + pstcData->pstcInstance->SCON_f.DMATXEN = 1u; + break; + case UartDmaRx: + pstcData->pstcInstance->SCON_f.DMARXEN = 1u; + break; + case UartCtsRts: + pstcData->pstcInstance->SCON_f.CTSEN = 1u; + pstcData->pstcInstance->SCON_f.RTSEN = 1u; + break; + default: + return ErrorInvalidParameter; + } + return Ok; +} +/** + ****************************************************************************** + ** \brief UART通é“å‘é€æˆ–接收等功能ç¦æ­¢è®¾ç½® + ** + ** \param [in] u8Idx通é“å·ï¼ŒenFunc功能 + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t Uart_DisableFunc(uint8_t u8Idx, en_uart_func_t enFunc) +{ + stc_uart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = UartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + switch(enFunc) + { + case UartTx: + case UartRx: + pstcData->pstcInstance->SCON_f.REN = 0u; + break; + case UartDmaTx: + pstcData->pstcInstance->SCON_f.DMATXEN = 0u; + break; + case UartDmaRx: + pstcData->pstcInstance->SCON_f.DMARXEN = 0u; + break; + case UartCtsRts: + pstcData->pstcInstance->SCON_f.CTSEN = 0u; + pstcData->pstcInstance->SCON_f.RTSEN = 0u; + break; + default: + return ErrorInvalidParameter; + } + return Ok; +} +/** + ****************************************************************************** + ** \brief UART通é“通信状æ€èŽ·å– + ** + ** \param [in] u8Idx通é“å· + ** + ** \retval 状æ€å€¼ + ******************************************************************************/ +uint8_t Uart_GetIsr(uint8_t u8Idx) +{ + stc_uart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = UartGetInternDataPtr(u8Idx); + return (pstcData->pstcInstance->ISR); +} +/** + ****************************************************************************** + ** \brief UART通é“通信状æ€èŽ·å– + ** + ** \param [in] u8Idx通é“å·ï¼ŒenStatus获å–å“ªä¸ªçŠ¶æ€ + ** + ** \retval 状æ€å€¼ + **\retval ErrorInvalidParameter获å–失败 + ******************************************************************************/ +boolean_t Uart_GetStatus(uint8_t u8Idx,en_uart_status_t enStatus) +{ + boolean_t bStatus=FALSE; + stc_uart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + ASSERT(IS_VALID_STATUS(enStatus)); + pstcData = UartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter;//4，用户åªéœ€åˆ¤æ–­0或1 + } + switch(enStatus) + { + case UartCts: + bStatus = (pstcData->pstcInstance->ISR_f.CTS == 1) ? TRUE : FALSE; + break; + case UartRC: + bStatus = (pstcData->pstcInstance->ISR_f.RC == 1) ? TRUE : FALSE; + break; + case UartTC: + bStatus = (pstcData->pstcInstance->ISR_f.TC == 1) ? TRUE : FALSE; + break; + case UartPE: + bStatus = (pstcData->pstcInstance->ISR_f.PE == 1) ? TRUE : FALSE; + break; + case UartFE: + bStatus = (pstcData->pstcInstance->ISR_f.FE == 1) ? TRUE : FALSE; + break; + case UartCtsIf: + bStatus = (pstcData->pstcInstance->ISR_f.CTSIF == 1) ? TRUE : FALSE; + break; + case UartTxe: + bStatus = (pstcData->pstcInstance->ISR_f.TXE == 1) ? TRUE : FALSE; + break; + default: + break; + } + return bStatus; +} +/** + ****************************************************************************** + ** \brief UART通é“通信状æ€æ¸…除 + ** + ** \param [in] u8Idx通é“å· + ** + ** \retval OK + ******************************************************************************/ +en_result_t Uart_ClrIsr(uint8_t u8Idx) +{ + stc_uart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = UartGetInternDataPtr(u8Idx); + pstcData->pstcInstance->ICR = 0u; + return Ok; +} +/** + ****************************************************************************** + ** \brief UART通é“通信状æ€æ¸…除 + ** + ** \param [in] u8Idx通é“å·ï¼ŒenStatusæ¸…é™¤å“ªä¸ªçŠ¶æ€ + ** + ** \retval 状æ€å€¼ + **\retval ErrorInvalidParameter清除失败 + ******************************************************************************/ +en_result_t Uart_ClrStatus(uint8_t u8Idx,en_uart_status_t enStatus) +{ + stc_uart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + ASSERT(IS_VALID_STATUS(enStatus)); + pstcData = UartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + switch(enStatus) + { + case UartCts: + pstcData->pstcInstance->ICR_f.CTSIFCF = 0; + break; + case UartRC: + pstcData->pstcInstance->ICR_f.RCCF = 0; + break; + case UartTC: + pstcData->pstcInstance->ICR_f.TCCF = 0; + break; + case UartPE: + pstcData->pstcInstance->ICR_f.PECF = 0; + break; + case UartFE: + pstcData->pstcInstance->ICR_f.FECF = 0; + break; + default: + break; + } + return Ok; +} +/** + ****************************************************************************** + ** \brief UART通é“å‘é€æ•°æ®å‡½æ•°,查询方å¼è°ƒç”¨æ­¤å‡½æ•°ï¼Œä¸­æ–­æ–¹å¼å‘é€ä¸é€‚用 + ** + ** \param [in] u8Idx通é“å·ï¼ŒDataå‘é€æ•°æ® + ** + ** \retval Okå‘é€æˆåŠŸ + **\retval ErrorInvalidParameterå‘é€å¤±è´¥ + ******************************************************************************/ +en_result_t Uart_SendData(uint8_t u8Idx, uint8_t u8Data) +{ + stc_uart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = UartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + while(FALSE == Uart_GetStatus(u8Idx, UartTxe)) + {} + pstcData->pstcInstance->SBUF_f.DATA = u8Data; + return Ok; +} +/** + ****************************************************************************** + ** \brief UART通é“接收数æ®å‡½æ•° + ** + ** \param [in] u8Idx通é“å· + ** + ** \retval æŽ¥æ”¶æ•°æ® + **\retval ErrorInvalidParameter接收失败 + ******************************************************************************/ +int Uart_ReceiveData(uint8_t u8Idx) +{ + stc_uart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = UartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return -1; + } + return (pstcData->pstcInstance->SBUF_f.DATA); +} +/** + ****************************************************************************** + ** \brief UART通é“中断处ç†å‡½æ•° + ** + ** \param [in] u8Param通é“å· + ** + ** \retval æ—  + ** + ******************************************************************************/ +void Uart_IRQHandler(uint8_t u8Param) +{ + stc_uart_instance_data_t *pstcData = NULL; + pstcData = UartGetInternDataPtr(u8Param); + if (NULL == pstcData) + { + return; + } + if(1 == pstcData->pstcInstance->ISR_f.FE) + { + Uart_ClrStatus(u8Param,UartFE); + if(NULL != pstcData->stcUartInternIrqCb.pfnRxFEIrqCb) + { + pstcData->stcUartInternIrqCb.pfnRxFEIrqCb(); + } + return;//帧出错则ä¸è¿›è¡ŒåŽç»­æ•°æ®å¤„ç† + } + if(1 == pstcData->pstcInstance->ISR_f.PE) + { + Uart_ClrStatus(u8Param,UartPE); + if(NULL != pstcData->stcUartInternIrqCb.pfnPEIrqCb) + { + pstcData->stcUartInternIrqCb.pfnPEIrqCb(); + } + return;//若奇å¶æ ¡éªŒå‡ºé”™åˆ™ä¸è¿›è¡ŒåŽç»­æ•°æ®å¤„ç† + } + if(1 == pstcData->pstcInstance->ISR_f.CTSIF) + { + Uart_ClrStatus(u8Param,UartCts); + if(NULL != pstcData->stcUartInternIrqCb.pfnCtsIrqCb) + { + pstcData->stcUartInternIrqCb.pfnCtsIrqCb(); + } + } + if(1 == pstcData->pstcInstance->ISR_f.RC) + { + Uart_ClrStatus(u8Param,UartRC); + if(NULL != pstcData->stcUartInternIrqCb.pfnRxIrqCb) + { + pstcData->stcUartInternIrqCb.pfnRxIrqCb(); + } + } + if(1 == pstcData->pstcInstance->ISR_f.TC) + { + Uart_ClrStatus(u8Param,UartTC); + if(NULL != pstcData->stcUartInternIrqCb.pfnTxIrqCb) + { + pstcData->stcUartInternIrqCb.pfnTxIrqCb(); + } + } +} +/** + ****************************************************************************** + ** \brief UART通é“使能内核NVIC中断 + ** + ** \param [in] u8Idx通é“å· + ** + ** \retval æ—  + ** + ******************************************************************************/ +static void UartInitNvic(uint8_t u8Idx) +{ + IRQn_Type enIrqIndex; + + ASSERT(IS_VALID_CH(u8Idx));; + enIrqIndex = (IRQn_Type)(UART0_IRQn + u8Idx); + NVIC_ClearPendingIRQ(enIrqIndex); + NVIC_SetPriority(enIrqIndex,IrqLevel3); + NVIC_EnableIRQ(enIrqIndex); + +} +/** + ****************************************************************************** + ** \brief UART通é“ç¦æ­¢å†…æ ¸NVIC中断 + ** + ** \param [in] u8Idx通é“å· + ** + ** \retval æ—  + ** + ******************************************************************************/ +static void UartDeInitNvic(uint8_t u8Idx) +{ + IRQn_Type enIrqIndex; + + ASSERT(IS_VALID_CH(u8Idx)); + enIrqIndex = (IRQn_Type)(UART0_IRQn + u8Idx); + NVIC_ClearPendingIRQ(enIrqIndex); + NVIC_SetPriority(enIrqIndex,IrqLevel3); + NVIC_DisableIRQ(enIrqIndex); + +} +/** + ****************************************************************************** + ** \brief UART通é“åˆå§‹åŒ–函数 + ** + ** \param [in] u8Idx通é“å·ï¼ŒpstcConfigåˆå§‹åŒ–结构体 + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t Uart_Init(uint8_t u8Idx, + stc_uart_config_t* pstcConfig) +{ + en_result_t enRet = Error; + stc_uart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = UartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + if(NULL == pstcConfig) + { + return ErrorInvalidParameter; + } + enRet = Uart_SetMode(u8Idx,pstcConfig->enRunMode); + enRet = Uart_SetStopBit(u8Idx,pstcConfig->enStopBit); + if(NULL != pstcConfig->pstcMultiMode) + { + enRet = Uart_SetMultiMode(u8Idx,pstcConfig->pstcMultiMode); + } + if(NULL != pstcConfig->pstcIrqCb) + { + pstcData->stcUartInternIrqCb.pfnRxFEIrqCb = pstcConfig->pstcIrqCb->pfnRxFEIrqCb; + pstcData->stcUartInternIrqCb.pfnRxIrqCb = pstcConfig->pstcIrqCb->pfnRxIrqCb; + pstcData->stcUartInternIrqCb.pfnTxIrqCb = pstcConfig->pstcIrqCb->pfnTxIrqCb; + pstcData->stcUartInternIrqCb.pfnCtsIrqCb = pstcConfig->pstcIrqCb->pfnCtsIrqCb; + pstcData->stcUartInternIrqCb.pfnPEIrqCb = pstcConfig->pstcIrqCb->pfnPEIrqCb; + } + if(pstcConfig->bTouchNvic == TRUE) + { + UartInitNvic(u8Idx); + } + else + { + UartDeInitNvic(u8Idx); + } + enRet = Ok; + return enRet; +} +//@} // UartGroup diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/vc.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/vc.c new file mode 100644 index 0000000000..fbb14ed4a6 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/vc.c @@ -0,0 +1,674 @@ +/****************************************************************************** +* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file vc.c + ** + ** voltage comparator driver API. + ** @link VC Group Some description @endlink + ** + ** - 2017-06-28 Alex First Version + ** + ******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "vc.h" + +/** + ****************************************************************************** + ** \addtogroup VcGroup + ******************************************************************************/ +//@{ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define IS_VALID_CHANNEL(x) ( VcChannel0==(x) || VcChannel1 == (x)) +#define IS_VALID_STAT(x) ( VcCmpResult==(x) || VcIntrResult == (x)) +#define IS_VALID_DIV(x) ( (x) <= 64u ) + +#define IS_VALID_INPUT_P(x) ( (x) <= VcInPCh15 ) + +#define IS_VALID_INPUT_N(x) ( (x) <= AiLdo ) + +#define IS_VALID_DLY(x) ( (VcDelay30mv == (x)) ||\ + (VcDelay20mv == (x)) ||\ + (VcDelay10mv == (x)) ||\ + (VcDelayoff == (x)) ) + +#define IS_VALID_BIAS(x) ( (VcBias300na == (x)) ||\ + (VcBias1200na == (x)) ||\ + (VcBias10ua == (x)) ||\ + (VcBias20ua == (x)) ) + +#define IS_VALID_FILTER(x) ( (x) <= VcFilter28800us ) + + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +static en_result_t VcEnableIrq(en_vc_channel_t enChannel, boolean_t bFlag); +static void VcEnableNvic(IRQn_Type enIrqn); +static void VcDisableNvic(IRQn_Type enIrqn); + +/****************************************************************************** + * Local variable definitions ('static') + ******************************************************************************/ +static func_ptr_t pfnVc0IrqCb = NULL; +static func_ptr_t pfnVc1IrqCb = NULL; + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + *****************************************************************************/ + +/** + * \brief + * 指定VC通é“中断使能/除能 + * + * \param [in] enChannel VC通é“å· + * \param [in] bFlag 使能/除能标志 + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +static en_result_t VcEnableIrq(en_vc_channel_t enChannel, boolean_t bFlag) +{ + if (VcChannel0 == enChannel) + { + if (bFlag) + { + VcEnableNvic(VC0_IRQn); + M0P_VC->VC0_CR_f.IE = 1u; + } + else + { + M0P_VC->VC0_CR_f.IE = 0u; + VcDisableNvic(VC0_IRQn); + } + } + else if (VcChannel1 == enChannel) + { + if (bFlag) + { + VcEnableNvic(VC1_IRQn); + M0P_VC->VC1_CR_f.IE = 1u; + } + else + { + M0P_VC->VC1_CR_f.IE = 0u; + VcDisableNvic(VC1_IRQn); + } + } + else + { + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + * \brief + * 使能NVIC中VC中断 + * + * \param [in] enIrqn ä¸­æ–­å· + * + * \retval æ—  + */ +static void VcEnableNvic(IRQn_Type enIrqn) +{ + NVIC_ClearPendingIRQ(enIrqn); + NVIC_EnableIRQ(enIrqn); + NVIC_SetPriority(enIrqn, IrqLevel3); +} + +/** + * \brief + * 除能NVIC中VC中断 + * + * \param [in] enIrqn ä¸­æ–­å· + * + * \retval æ—  + */ +static void VcDisableNvic(IRQn_Type enIrqn) +{ + NVIC_ClearPendingIRQ(enIrqn); + NVIC_DisableIRQ(enIrqn); + NVIC_SetPriority(enIrqn, IrqLevel3); +} + +/** + * \brief + * VC中断æœåŠ¡ç¨‹åº + * + * \param [in] u8Param VC通é“å· + * + * \retval æ—  + */ +void Vc_IRQHandler(uint8_t u8Param) +{ + if (0 == u8Param) + { + if (TRUE == M0P_VC->IFR_f.VC0_INTF) + { + if (NULL != pfnVc0IrqCb) + { + pfnVc0IrqCb(); + } + M0P_VC->IFR_f.VC0_INTF = 0; + } + } + else if (1 == u8Param) + { + if (TRUE == M0P_VC->IFR_f.VC1_INTF) + { + if (NULL != pfnVc1IrqCb) + { + pfnVc1IrqCb(); + } + M0P_VC->IFR_f.VC1_INTF = 0; + } + } + else + { + ; // just return + } +} + +/** + * \brief + * é…ç½®VC中断触å‘æ–¹å¼ + * + * \param [in] enChannel VC通é“å· + * \param [in] enSel 中断触å‘æ–¹å¼é€‰æ‹© + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Vc_ConfigIrq(en_vc_channel_t enChannel, en_vc_irq_sel_t enSel) +{ + stc_vc_vc0_cr_field_t *stcVcnCr; + en_result_t enRet = Ok; + + if (VcChannel0 == enChannel) + { + stcVcnCr = (stc_vc_vc0_cr_field_t*)&M0P_VC->VC0_CR_f; + } + else if (VcChannel1 == enChannel) + { + stcVcnCr = (stc_vc_vc0_cr_field_t*)&M0P_VC->VC1_CR_f; + } + else + { + return ErrorInvalidParameter; + } + + switch (enSel) + { + case VcIrqRise: + stcVcnCr->RISING = 1u; + break; + case VcIrqFall: + stcVcnCr->FALLING = 1u; + break; + case VcIrqHigh: + stcVcnCr->LEVEL = 1u; + break; + + default: + enRet= ErrorInvalidParameter; + break; + } + + return enRet; +} + +/** + * \brief + * 获å–VCçŠ¶æ€ + * + * \param [in] enChannel VC通é“å· + * \param [in] enStat VC状æ€ç±»åž‹ + * + * \retval boolean_t TRUE: 状æ€ä¸ºé«˜ + * \retval boolean_t FALSE: 状æ€ä¸ºä½Ž + */ +boolean_t Vc_GetStat(en_vc_channel_t enChannel, en_vc_stat_t enStat) +{ + boolean_t bFlag = FALSE; + + ASSERT( IS_VALID_CHANNEL(enChannel) ); + ASSERT( IS_VALID_STAT(enStat) ); + + if (VcChannel0 == enChannel) + { + switch (enStat) + { + case VcCmpResult: + bFlag = M0P_VC->IFR_f.VC0_FILTER; + break; + case VcIntrResult: + bFlag = M0P_VC->IFR_f.VC0_INTF; + break; + default: + break; + } + } + else + { + switch (enStat) + { + case VcCmpResult: + bFlag = M0P_VC->IFR_f.VC1_FILTER; + break; + case VcIntrResult: + bFlag = M0P_VC->IFR_f.VC1_INTF; + break; + default: + break; + } + } + + return bFlag; +} + +/** + * \brief + * 清除VC中断标志 + * + * \param [in] enChannel VC通é“å· + * + * \retval æ—  + */ +void Vc_ClearIrq(en_vc_channel_t enChannel) +{ + ASSERT( IS_VALID_CHANNEL(enChannel) ); + + if (VcChannel0 == enChannel) + { + M0P_VC->IFR_f.VC0_INTF = 0u; + } + else + { + M0P_VC->IFR_f.VC1_INTF = 0u; + } +} + +/** + * \brief + * 指定VC通é“中断使能 + * + * \param [in] enChannel VC通é“å· + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Vc_EnableIrq(en_vc_channel_t enChannel) +{ + return VcEnableIrq(enChannel, TRUE); +} + +/** + * \brief + * 指定VC通é“中断除能 + * + * \param [in] enChannel VC通é“å· + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Vc_DisableIrq(en_vc_channel_t enChannel) +{ + return VcEnableIrq(enChannel, FALSE); +} + +/** + * \brief + * VC模å—åˆå§‹åŒ– + * + * \param [in] pstcGeneralConfig VC模å—é…置指针 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Vc_DACInit(stc_vc_dac_config_t *pstcDacConfig) +{ + if (NULL == pstcDacConfig) + { + return ErrorInvalidParameter; + } + + M0P_VC->CR_f.DIV_EN = pstcDacConfig->bDivEn; + M0P_VC->CR_f.REF2P5_SEL = pstcDacConfig->enDivVref; + + if (pstcDacConfig->u8DivVal < 0x40) + { + M0P_VC->CR_f.DIV = pstcDacConfig->u8DivVal; + } + else + { + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + * \brief + * VC模å—deinit + * + * \param æ—  + * + * \retval æ—  + */ +void Vc_DACDeInit(void) +{ + M0P_VC->CR_f.DIV_EN = 0u; + M0P_VC->CR_f.DIV = 0x20u; + M0P_VC->CR_f.REF2P5_SEL = 0u; +} + +/** + * \brief + * VC通é“åˆå§‹åŒ– + * + * \param [in] enChannel VC通é“å· + * \param [in] pstcChannelConfig VC通é“é…置指针 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Vc_ChannelInit(en_vc_channel_t enChannel, + stc_vc_channel_config_t *pstcChannelConfig) +{ + //en_result_t enRet = Ok; + + ASSERT(NULL != pstcChannelConfig); + ASSERT(IS_VALID_INPUT_P(pstcChannelConfig->enVcInPin_P)); + ASSERT(IS_VALID_INPUT_N(pstcChannelConfig->enVcInPin_N)); + ASSERT(IS_VALID_DLY(pstcChannelConfig->enVcCmpDly)); + ASSERT(IS_VALID_BIAS(pstcChannelConfig->enVcBiasCurrent)); + ASSERT(IS_VALID_FILTER(pstcChannelConfig->enVcFilterTime)); + + if (VcChannel0 == enChannel) + { + M0P_VC->CR_f.VC0_HYS_SEL = pstcChannelConfig->enVcCmpDly; + M0P_VC->CR_f.VC0_BIAS_SEL = pstcChannelConfig->enVcBiasCurrent; + M0P_VC->VC0_CR_f.DEBOUNCE_TIME = pstcChannelConfig->enVcFilterTime; + M0P_VC->VC0_CR_f.P_SEL = pstcChannelConfig->enVcInPin_P; + M0P_VC->VC0_CR_f.N_SEL = pstcChannelConfig->enVcInPin_N; + M0P_VC->VC0_OUT_CFG = 1<enVcOutConfig; + + switch(pstcChannelConfig->enVcIrqSel) + { + case VcIrqRise: + M0P_VC->VC0_CR_f.RISING = 1u; + break; + case VcIrqFall: + M0P_VC->VC0_CR_f.FALLING = 1u; + break; + case VcIrqHigh: + M0P_VC->VC0_CR_f.LEVEL = 1u; + break; + default: + M0P_VC->VC0_CR_f.LEVEL = 0u; + M0P_VC->VC0_CR_f.RISING = 0u; + M0P_VC->VC0_CR_f.FALLING = 0u; + break; + } + + pfnVc0IrqCb = pstcChannelConfig->pfnAnalogCmpCb; + } + else if (VcChannel1 == enChannel) + { + M0P_VC->CR_f.VC1_HYS_SEL = pstcChannelConfig->enVcCmpDly; + M0P_VC->CR_f.VC1_BIAS_SEL = pstcChannelConfig->enVcBiasCurrent; + M0P_VC->VC1_CR_f.DEBOUNCE_TIME = pstcChannelConfig->enVcFilterTime; + M0P_VC->VC1_CR_f.P_SEL = pstcChannelConfig->enVcInPin_P; + M0P_VC->VC1_CR_f.N_SEL = pstcChannelConfig->enVcInPin_N; + M0P_VC->VC1_OUT_CFG = 1<enVcOutConfig; + + switch(pstcChannelConfig->enVcIrqSel) + { + case VcIrqRise: + M0P_VC->VC1_CR_f.RISING = 1u; + break; + case VcIrqFall: + M0P_VC->VC1_CR_f.FALLING = 1u; + break; + case VcIrqHigh: + M0P_VC->VC1_CR_f.LEVEL = 1u; + break; + default: + M0P_VC->VC1_CR_f.LEVEL = 0u; + M0P_VC->VC1_CR_f.RISING = 0u; + M0P_VC->VC1_CR_f.FALLING = 0u; + break; + } + + pfnVc1IrqCb = pstcChannelConfig->pfnAnalogCmpCb; + } + else + { + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + * \brief + * VC通é“Deinit + * + * \param [in] enChannel VC通é“å· + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Vc_ChannelDeInit(en_vc_channel_t enChannel) +{ + if (VcChannel0 == enChannel) + { + M0P_VC->VC0_CR_f.EN = 0u; + M0P_VC->CR_f.VC0_HYS_SEL = 0; + M0P_VC->CR_f.VC0_BIAS_SEL = 0; + M0P_VC->VC0_CR_f.DEBOUNCE_TIME = 0; + M0P_VC->VC0_CR_f.P_SEL = 0; + M0P_VC->VC0_CR_f.N_SEL = 0; + M0P_VC->VC0_OUT_CFG = 0; + M0P_VC->VC0_CR_f.LEVEL = 0u; + M0P_VC->VC0_CR_f.RISING = 0u; + M0P_VC->VC0_CR_f.FALLING = 0u; + pfnVc0IrqCb = NULL; + M0P_VC->VC0_CR_f.IE = 0u; + VcDisableNvic(VC0_IRQn); + } + else if (VcChannel1 == enChannel) + { + M0P_VC->VC1_CR_f.EN = 0u; + M0P_VC->CR_f.VC1_HYS_SEL = 0; + M0P_VC->CR_f.VC1_BIAS_SEL = 0; + M0P_VC->VC1_CR_f.DEBOUNCE_TIME = 0; + M0P_VC->VC1_CR_f.P_SEL = 0; + M0P_VC->VC1_CR_f.N_SEL = 0; + M0P_VC->VC1_OUT_CFG = 0; + M0P_VC->VC1_CR_f.LEVEL = 0u; + M0P_VC->VC1_CR_f.RISING = 0u; + M0P_VC->VC1_CR_f.FALLING = 0u; + pfnVc1IrqCb = NULL; + M0P_VC->VC1_CR_f.IE = 0u; + VcDisableNvic(VC1_IRQn); + } + else + { + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + * \brief + * VC通é“使能 + * + * \param [in] enChannel VC通é“å· + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Vc_EnableChannel(en_vc_channel_t enChannel) +{ + if (VcChannel0 == enChannel) + { + M0P_VC->VC0_CR_f.EN = 1u; + } + else if (VcChannel1 == enChannel) + { + M0P_VC->VC1_CR_f.EN = 1u; + } + else + { + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + * \brief + * VC通é“除能 + * + * \param [in] enChannel VC通é“å· + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Vc_DisableChannel(en_vc_channel_t enChannel) +{ + if (VcChannel0 == enChannel) + { + M0P_VC->VC0_CR_f.EN = 0u; + } + else if (VcChannel1 == enChannel) + { + M0P_VC->VC1_CR_f.EN = 0u; + } + else + { + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + * \brief + * VC输出滤波使能 + * + * \param [in] enChannel VC通é“å· + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Vc_EnableFilter(en_vc_channel_t enChannel) +{ + if (VcChannel0 == enChannel) + { + M0P_VC->VC0_CR_f.FLTEN = 1u; + } + else if (VcChannel1 == enChannel) + { + M0P_VC->VC1_CR_f.FLTEN = 1u; + } + else + { + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + * \brief + * VC输出滤波除能 + * + * \param [in] enChannel VC通é“å· + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Vc_DisableFilter(en_vc_channel_t enChannel) +{ + if (VcChannel0 == enChannel) + { + M0P_VC->VC0_CR_f.FLTEN = 0u; + } + else if (VcChannel1 == enChannel) + { + M0P_VC->VC1_CR_f.FLTEN = 0u; + } + else + { + return ErrorInvalidParameter; + } + + return Ok; +} + +//@} // VcGroup + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/wdt.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/wdt.c new file mode 100644 index 0000000000..0a3ea826dc --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/wdt.c @@ -0,0 +1,184 @@ +/************************************************************************************* +* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file wdt.c + ** + ** WDT function driver API. + ** @link WdtGroup Some description @endlink + ** + ** - 2017-05-17 1.0 CJ First version for Device Driver Library of Module. + ** + ******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "wdt.h" + +/** + ****************************************************************************** + ** \defgroup WdtGroup + ** + ******************************************************************************/ +//@{ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ +static func_ptr_t pfnWdtCallback = NULL; +/** + ****************************************************************************** + ** \brief WDT溢出时间设置函数 + ** + ** \param [in] u8LoadValue 溢出时间 + ** + ** \retval æ—  + ** + ******************************************************************************/ +void Wdt_WriteWdtLoad(uint8_t u8LoadValue) +{ + M0P_WDT->CON_f.WOV = u8LoadValue; +} +/** + ****************************************************************************** + ** \brief WDTåˆå§‹åŒ–函数 + ** + ** \param [in] stcConfig åˆå§‹åŒ–结构 + ** + ** \retval Ok + ** + ******************************************************************************/ +en_result_t Wdt_Init(stc_wdt_config_t* pstcConfig) +{ + en_result_t enRet = Error; + ASSERT(NULL != pstcConfig); + Wdt_WriteWdtLoad(pstcConfig->u8LoadValue); + pfnWdtCallback = pstcConfig->pfnWdtIrqCb; + M0P_WDT->CON_f.WINT_EN = pstcConfig->enResetEnable; + if(pstcConfig->enResetEnable) + { + EnableNvic(WDT_IRQn,IrqLevel3,TRUE); + } + enRet = Ok; + return enRet; +} +/** + ****************************************************************************** + ** \brief WDTå¤ä½åŠå¯åŠ¨å‡½æ•° + ** + ** \param [in] æ—  + ** + ** \retval Ok + ** + ******************************************************************************/ +en_result_t Wdt_Start(void) +{ + en_result_t enRet = Error; + M0P_WDT->RST = 0x1E; + M0P_WDT->RST = 0xE1; + enRet = Ok; + return enRet; +} +/** + ****************************************************************************** + ** \brief WDTå¤ä½åŠå¯åŠ¨å‡½æ•° + ** + ** \param [in] æ—  + ** + ** \retval Ok + ** + ******************************************************************************/ +void Wdt_Feed(void) +{ + M0P_WDT->RST = 0x1E; + M0P_WDT->RST = 0xE1; +} +/** + ****************************************************************************** + ** \brief WDT读å–当å‰è®¡æ•°å€¼å‡½æ•° + ** + ** \param [in] æ—  + ** + ** \retval 计数值 + ** + ******************************************************************************/ +uint8_t Wdt_ReadWdtValue(void) +{ + uint8_t u8Count; + u8Count = M0P_WDT->CON_f.WCNTL; + return u8Count; +} +/** + ****************************************************************************** + ** \brief WDT读å–当å‰è¿è¡ŒçŠ¶æ€ + ** + ** \param [in] æ—  + ** + ** \retval 状æ€å€¼ + ** + ******************************************************************************/ +uint8_t Wdt_ReadwdtStatus(void) +{ + return M0P_WDT->CON_f.WDTR; +} +/** + ****************************************************************************** + ** \brief WDT中断处ç†å‡½æ•° + ** + ** \param [in] æ—  + ** + ** \retval æ—  + ** + ******************************************************************************/ +void Wdt_IRQHandler(void) +{ + if(M0P_WDT->CON_f.WDINT) + { + Wdt_Start();//clr wdt 标记 + if(NULL != pfnWdtCallback) + { + pfnWdtCallback(); + } + } +} + +//@} // WdtGroup diff --git a/bsp/hc32l136/Libraries/LICENSE b/bsp/hc32l136/Libraries/LICENSE new file mode 100644 index 0000000000..72823826b8 --- /dev/null +++ b/bsp/hc32l136/Libraries/LICENSE @@ -0,0 +1,29 @@ +BSD 3-Clause License + +Copyright (c) 2020, Huada Semiconductor Co., Ltd ("HDSC") +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +* Neither the name of the copyright holder nor the names of its + contributors may be used to endorse or promote products derived from + this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/bsp/hc32l136/Libraries/SConscript b/bsp/hc32l136/Libraries/SConscript new file mode 100644 index 0000000000..f8e856e883 --- /dev/null +++ b/bsp/hc32l136/Libraries/SConscript @@ -0,0 +1,48 @@ +# RT-Thread building script for bridge + +import rtconfig +Import('RTT_ROOT') +from building import * + +# get current directory +cwd = GetCurrentDir() + +# The set of source files associated with this SConscript file. +src = Split(""" +HC32L136_StdPeriph_Driver/src/adc.c +HC32L136_StdPeriph_Driver/src/gpio.c +HC32L136_StdPeriph_Driver/src/uart.c +HC32L136_StdPeriph_Driver/src/lpuart.c +HC32L136_StdPeriph_Driver/src/rtc.c +HC32L136_StdPeriph_Driver/src/sysctrl.c +HC32L136_StdPeriph_Driver/src/timer3.c +HC32L136_StdPeriph_Driver/src/trim.c +HC32L136_StdPeriph_Driver/src/flash.c +HC32L136_StdPeriph_Driver/src/ddl.c +CMSIS/Device/HDSC/HC32L136/Source/system_hc32l13x.c +CMSIS/Device/HDSC/HC32L136/Source/interrupts_hc32l136.c +""") + +#src += Glob('HC32F4A0_StdPeriph_Driver/src/*.c') + +if GetDepend(['RT_USING_WDT']): + src += ['HC32L136_StdPeriph_Driver/src/wdt.c'] + +#add for startup script +if rtconfig.CROSS_TOOL == 'gcc': + src = src + ['CMSIS/Device/HDSC/HC32L136/Source/GCC/startup_hc32l136.S'] +elif rtconfig.CROSS_TOOL == 'keil': + src = src + ['CMSIS/Device/HDSC/HC32L136/Source/ARM/startup_hc32l136.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src = src + ['CMSIS/Device/HDSC/HC32L136/Source/IAR/startup_hc32l136.s'] + +#add headfile script +path = [cwd + '/CMSIS/Include', + cwd + '/CMSIS/Device/HDSC/HC32L136/Include', + cwd + '/HC32L136_StdPeriph_Driver/inc'] + +CPPDEFINES = ['USE_DDL_DRIVER', rtconfig.MCU_TYPE, '__DEBUG'] + +group = DefineGroup('HC32_StdPeriph', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hc32l136/README.md b/bsp/hc32l136/README.md new file mode 100644 index 0000000000..5367aacbad --- /dev/null +++ b/bsp/hc32l136/README.md @@ -0,0 +1,100 @@ +# HDSC HC32LFx3x-STK-V2.0 å¼€å‘æ¿ BSP 说明 + +## 简介 + +本文档为åŽå¤§åŠå¯¼ä½“为 HC32LFx3x-STK-V2.0 å¼€å‘æ¿æ供的 BSP (æ¿çº§æ”¯æŒåŒ…) 说明。 + +主è¦å†…容如下： + +- å¼€å‘æ¿èµ„æºä»‹ç» +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开å‘者å¯ä»¥å¿«é€Ÿåœ°ä¸Šæ‰‹è¯¥ BSP，将 RT-Thread è¿è¡Œåœ¨å¼€å‘æ¿ä¸Šã€‚在进阶使用指å—章节，将会介ç»æ›´å¤šé«˜çº§åŠŸèƒ½ï¼Œå¸®åŠ©å¼€å‘者利用 RT-Thread 驱动更多æ¿è½½èµ„æºã€‚ + +## å¼€å‘æ¿ä»‹ç» + +HC32LFx3x-STK-V2.0 是 HDSC 官方推出的开å‘æ¿ï¼Œæ­è½½ HC32L136 芯片，基于 ARM Cortex-M0 内核，最高主频 48 MHz，具有丰富的æ¿è½½èµ„æºã€‚ + +å¼€å‘æ¿å¤–观如下图所示： + +![board](figures/board.png) + +HC32LFx3x-STK-V2.0 å¼€å‘æ¿å¸¸ç”¨ **æ¿è½½èµ„æº** 如下： + +- MCU：HC32L136，主频 48MHz，64KB FLASH ，8KB RAM +- 常用外设 +- 常用接å£ï¼š +- 调试接å£ï¼šæ¿è½½DAP调试器ã€æ ‡å‡† JTAG/SWD。 + +## å¤–è®¾æ”¯æŒ + +本 BSP ç›®å‰å¯¹å¤–设的支æŒæƒ…况如下： + +| **片上外设** | **支æŒæƒ…况** | **备注** | +| :------------ | :-----------: | :-----------------------------------: | +| GPIO | æ”¯æŒ | PA0, PA1... PI15 ---> PIN: 0, 1...63 | +| UART | æ”¯æŒ | UART0~1 | +| LED | æ”¯æŒ | LED | + + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，éµå¾ªç®€å•çš„步骤å³å¯å°† RT-Thread æ“作系统è¿è¡Œåœ¨è¯¥å¼€å‘æ¿ä¸Šï¼Œçœ‹åˆ°å®žéªŒæ•ˆæžœ 。 + +- 进阶使用 + + 本章节是为需è¦åœ¨ RT-Thread æ“作系统上使用更多开å‘æ¿èµ„æºçš„å¼€å‘者准备的。通过使用 ENV 工具对 BSP 进行é…置，å¯ä»¥å¼€å¯æ›´å¤šæ¿è½½èµ„æºï¼Œå®žçŽ°æ›´å¤šé«˜çº§åŠŸèƒ½ã€‚ + + +### 快速上手 + +本 BSP 为开å‘者æä¾› MDK4ã€MDK5ã€IAR工程，暂ä¸æ”¯æŒGCCå¼€å‘环境。下é¢ä»¥ MDK5 å¼€å‘环境为例，介ç»å¦‚何将系统è¿è¡Œèµ·æ¥ã€‚ + +#### 硬件连接 + + + +#### 编译下载 + +åŒå‡» project.uvprojx 文件，打开 MDK5 工程，编译并下载程åºåˆ°å¼€å‘æ¿ã€‚ + +> 工程默认é…置使用 J-LINK 下载程åºï¼Œç‚¹å‡»ä¸‹è½½æŒ‰é’®å³å¯ä¸‹è½½ç¨‹åºåˆ°å¼€å‘æ¿ã€‚ + +#### è¿è¡Œç»“æžœ + +下载程åºæˆåŠŸä¹‹åŽï¼Œç³»ç»Ÿä¼šè‡ªåŠ¨è¿è¡Œï¼Œè§‚察开å‘æ¿ä¸Š LED çš„è¿è¡Œæ•ˆæžœï¼Œç»¿è‰²ä¼šå‘¨æœŸæ€§é—ªçƒã€‚ + +连接PA2ã€PA3串å£ï¼Œåœ¨ç»ˆç«¯å·¥å…·é‡Œæ‰“开相应的串å£ï¼Œå¤ä½è®¾å¤‡åŽï¼Œå¯ä»¥çœ‹åˆ° RT-Thread 的输出信æ¯: + +``` + \ | / +- RT - Thread Operating System + / | \ 4.0.3 build Aug 20 2021 + 2006 - 2021 Copyright by rt-thread team +msh > +``` + +### 进阶使用 + +æ­¤ BSP 默认åªå¼€å¯äº† GPIO å’Œ ä¸²å£ 1 的功能，更多高级功能需è¦åˆ©ç”¨ env 工具对 BSP 进行é…置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令é…置工程，é…置好之åŽä¿å­˜é€€å‡ºã€‚ + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk4/mdk5/iar` 命令é‡æ–°ç”Ÿæˆå·¥ç¨‹ã€‚ + +## 注æ„事项 + +## è”ç³»äººä¿¡æ¯ + +维护人: + +- [Ching], 邮箱：<515892376@qq.com> \ No newline at end of file diff --git a/bsp/hc32l136/SConscript b/bsp/hc32l136/SConscript new file mode 100644 index 0000000000..24bb4646ab --- /dev/null +++ b/bsp/hc32l136/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/hc32l136/SConstruct b/bsp/hc32l136/SConstruct new file mode 100644 index 0000000000..ae37ec6a48 --- /dev/null +++ b/bsp/hc32l136/SConstruct @@ -0,0 +1,45 @@ +import os +import sys +import rtconfig + +print "############sconstruct##############" +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') + +print "RTT_ROOT: " + RTT_ROOT + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'hc32L136.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +print "######################env:" +print env +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/hc32l136/applications/SConscript b/bsp/hc32l136/applications/SConscript new file mode 100644 index 0000000000..6f66f7ab73 --- /dev/null +++ b/bsp/hc32l136/applications/SConscript @@ -0,0 +1,12 @@ +import rtconfig +from building import * + +cwd = GetCurrentDir() +CPPPATH = [cwd, str(Dir('#'))] +src = Split(""" +main.c +""") + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/hc32l136/applications/main.c b/bsp/hc32l136/applications/main.c new file mode 100644 index 0000000000..8f772f8f20 --- /dev/null +++ b/bsp/hc32l136/applications/main.c @@ -0,0 +1,90 @@ +/* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-30 CDT first version + */ + + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "board.h" + +#include +#include + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/* defined the LED pin: PC9 */ +#define LED_PIN GET_PIN(D, 5) +#define KEY_PIN GET_PIN(B, 9) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + uint8_t flag; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +void key_handler(void *param) +{ + flag = ~flag; +} + +/** + ******************************************************************************* + ** \brief Main function of GPIO output + ** + ** \param None + ** + ** \retval int32_t Return value, if needed + ** + ******************************************************************************/ +int32_t main(void) +{ + //rt_kprintf("Os is Start!!! \n"); + rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT); + rt_pin_attach_irq(KEY_PIN, PIN_IRQ_MODE_FALLING, key_handler, RT_NULL); + rt_pin_irq_enable(KEY_PIN, PIN_IRQ_ENABLE); + + while(1) + { + if (flag == 0) + { + rt_pin_write(LED_PIN, PIN_HIGH); + rt_thread_delay(500); + rt_pin_write(LED_PIN, PIN_LOW); + rt_thread_delay(500); + } + else + { + rt_pin_write(LED_PIN, PIN_HIGH); + rt_thread_delay(2000); + rt_pin_write(LED_PIN, PIN_LOW); + rt_thread_delay(2000); + } + } +} + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l136/board/Kconfig b/bsp/hc32l136/board/Kconfig new file mode 100644 index 0000000000..35ecfe181b --- /dev/null +++ b/bsp/hc32l136/board/Kconfig @@ -0,0 +1,57 @@ +menu "Hardware Drivers Config" + +config MCU_HC32L136 + bool + select ARCH_ARM_CORTEX_M0 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "Onboard Peripheral Drivers" + +endmenu + +menu "On-chip Peripheral Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART0 + bool "Enable UART0" + default n + + config BSP_USING_UART1 + bool "Enable UART1" + default y + endif + + menuconfig BSP_USING_I2C1 + bool "Enable I2C1 BUS (software simulation)" + default y + select RT_USING_I2C + select RT_USING_I2C_BITOPS + select RT_USING_PIN + if BSP_USING_I2C1 + config BSP_I2C1_SCL_PIN + int "i2c1 scl pin number" + range 1 176 + default 51 + config BSP_I2C1_SDA_PIN + int "I2C1 sda pin number" + range 1 176 + default 90 + endif + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/hc32l136/board/SConscript b/bsp/hc32l136/board/SConscript new file mode 100644 index 0000000000..589332a741 --- /dev/null +++ b/bsp/hc32l136/board/SConscript @@ -0,0 +1,14 @@ +from building import * + +cwd = GetCurrentDir() + +CPPPATH = [cwd] + +# add general drivers +src = Split(''' +board.c +''') + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/hc32l136/board/board.c b/bsp/hc32l136/board/board.c new file mode 100644 index 0000000000..198a1c2fa8 --- /dev/null +++ b/bsp/hc32l136/board/board.c @@ -0,0 +1,101 @@ + /* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-30 CDT first version + */ + + + +#include +#include + +#include "board.h" + +/** + * @addtogroup HC32 + */ + +/*@{*/ + +/** + * @brief BSP clock initialize. + * Set board system clock 24Mhz + * @param None + * @retval None + */ +void rt_hw_board_clock_init(void) +{ + Sysctrl_SetRCHTrim(SysctrlRchFreq24MHz); + Sysctrl_ClkSourceEnable(SysctrlClkRCH, TRUE); +} + +/******************************************************************************* + * Function Name : SysTick_Configuration + * Description : Configures the SysTick for OS tick. + * Input : None + * Output : None + * Return : None + *******************************************************************************/ +void SysTick_Configuration(void) +{ + SystemCoreClockUpdate(); + SysTick_Config(SystemCoreClock/RT_TICK_PER_SECOND); +} + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/** + * This function will initialize HC32 board. + */ +void rt_hw_board_init() +{ + /* Configure the System clock */ + rt_hw_board_clock_init(); + + /* Configure the SysTick */ + SysTick_Configuration(); + +#ifdef RT_USING_HEAP + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif +} + +void rt_hw_us_delay(rt_uint32_t us) +{ + uint32_t start, now, delta, reload, us_tick; + start = SysTick->VAL; + reload = SysTick->LOAD; + us_tick = SystemCoreClock / 1000000UL; + + do{ + now = SysTick->VAL; + delta = start > now ? start - now : reload + start - now; + } + while(delta < us_tick * us); +} +/*@}*/ diff --git a/bsp/hc32l136/board/board.h b/bsp/hc32l136/board/board.h new file mode 100644 index 0000000000..bae1d85f4c --- /dev/null +++ b/bsp/hc32l136/board/board.h @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-30 CDT first version + * 2021-01-18 CDT MOdify SRAM_SIZE + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include "ddl.h" +#include "gpio.h" +#include "drv_gpio.h" + +/* board configuration */ +#define SRAM_BASE 0x20000000 +#define SRAM_SIZE 0x2000 +#define SRAM_END (SRAM_BASE + SRAM_SIZE) + +/* High speed sram. */ +#ifdef __CC_ARM +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="CSTACK" +#define HEAP_BEGIN (__segment_end("CSTACK")) +#else +extern int __bss_end; +#define HEAP_BEGIN (&__bss_end) +#endif + +#ifdef __ICCARM__ +// Use *.icf ram symbal, to avoid hardcode. +#define HEAP_END SRAM_END +#else +#define HEAP_END SRAM_END +#endif + +void rt_hw_board_init(void); +void rt_hw_us_delay(rt_uint32_t us); + +#endif + +// <<< Use Configuration Wizard in Context Menu >>> diff --git a/bsp/hc32l136/board/linker_scripts/link.icf b/bsp/hc32l136/board/linker_scripts/link.icf new file mode 100644 index 0000000000..719e8b673c --- /dev/null +++ b/bsp/hc32l136/board/linker_scripts/link.icf @@ -0,0 +1,28 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0000FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x0400; +define symbol __ICFEDIT_size_heap__ = 0x0100; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file diff --git a/bsp/hc32l136/board/linker_scripts/link.lds b/bsp/hc32l136/board/linker_scripts/link.lds new file mode 100644 index 0000000000..af109a6da6 --- /dev/null +++ b/bsp/hc32l136/board/linker_scripts/link.lds @@ -0,0 +1,203 @@ + /** + ******************************************************************************* + * @file hc32f4a0_flash.lds + * @brief Linker script for HC32F4A0 Device with 2MByte FLASH, 512KByte RAM. + @verbatim + Change Logs: + Date Author Notes + 2020-09-15 Chengy First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/* Use contiguous memory regions for simple. */ +MEMORY +{ + FLASH (rx): ORIGIN = 0x00000000, LENGTH = 2M + OTP (rx): ORIGIN = 0x03000000, LENGTH = 6876 + RAM (rwx): ORIGIN = 0x1FFE0000, LENGTH = 512K + RAMB (rwx): ORIGIN = 0x200F0000, LENGTH = 4K +} + +ENTRY(Reset_Handler) + +SECTIONS +{ + .vectors : + { + . = ALIGN(4); + KEEP(*(.vectors)) + . = ALIGN(4); + } >FLASH + + .icg_sec 0x00000400 : + { + KEEP(*(.icg_sec)) + } >FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text*) + *(.glue_7) + *(.glue_7t) + *(.eh_frame) + + KEEP(*(.init)) + KEEP(*(.fini)) + . = ALIGN(4); + } >FLASH + + .rodata : + { + . = ALIGN(4); + *(.rodata) + *(.rodata*) + . = ALIGN(4); + } >FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >FLASH + __exidx_end = .; + + .preinit_array : + { + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + __etext = ALIGN(4); + + .otp_sec : + { + KEEP(*(.otp_sec)) + } >OTP + + .otp_lock_sec 0x03001800 : + { + KEEP(*(.otp_lock_sec)) + } >OTP + + .data : AT (__etext) + { + . = ALIGN(4); + __data_start__ = .; + *(vtable) + *(.data) + *(.data*) + . = ALIGN(4); + *(.ramfunc) + *(.ramfunc*) + . = ALIGN(4); + __data_end__ = .; + } >RAM + + __etext_ramb = __etext + ALIGN (SIZEOF(.data), 4); + .ramb_data : AT (__etext_ramb) + { + . = ALIGN(4); + __data_start_ramb__ = .; + *(.ramb_data) + *(.ramb_data*) + . = ALIGN(4); + __data_end_ramb__ = .; + } >RAMB + + .bss : + { + . = ALIGN(4); + _sbss = .; + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + __bss_end__ = _ebss; + } >RAM + + .ramb_bss : + { + . = ALIGN(4); + __bss_start_ramb__ = .; + *(.ramb_bss) + *(.ramb_bss*) + . = ALIGN(4); + __bss_end_ramb__ = .; + } >RAMB + + .heap_stack (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + PROVIDE(_end = .); + *(.heap*) + . = ALIGN(8); + __HeapLimit = .; + + __StackLimit = .; + *(.stack*) + . = ALIGN(8); + __StackTop = .; + } >RAM + + /DISCARD/ : + { + libc.a (*) + libm.a (*) + libgcc.a (*) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } + + PROVIDE(_stack = __StackTop); + PROVIDE(_Min_Heap_Size = __HeapLimit - __HeapBase); + PROVIDE(_Min_Stack_Size = __StackTop - __StackLimit); + + __RamEnd = ORIGIN(RAM) + LENGTH(RAM); + ASSERT(__StackTop <= __RamEnd, "region RAM overflowed with stack") +} diff --git a/bsp/hc32l136/board/linker_scripts/link.sct b/bsp/hc32l136/board/linker_scripts/link.sct new file mode 100644 index 0000000000..7cc97595b0 --- /dev/null +++ b/bsp/hc32l136/board/linker_scripts/link.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x10000 { ; load region size_region + ER_IROM1 0x00000000 0x10000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x2000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/hc32l136/drivers/SConscript b/bsp/hc32l136/drivers/SConscript new file mode 100644 index 0000000000..f37a9f6386 --- /dev/null +++ b/bsp/hc32l136/drivers/SConscript @@ -0,0 +1,22 @@ +from building import * + +cwd = GetCurrentDir() + +# add the general drivers. +src = Split(""" + +""") + +if GetDepend(['RT_USING_PIN']): + src += ['drv_gpio.c'] + +if GetDepend(['RT_USING_SERIAL']): + src += ['drv_usart.c'] + +if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']): + src += ['drv_soft_i2c.c'] + +CPPPATH = [cwd] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/hc32l136/drivers/drv_dma.h b/bsp/hc32l136/drivers/drv_dma.h new file mode 100644 index 0000000000..15b455b289 --- /dev/null +++ b/bsp/hc32l136/drivers/drv_dma.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-30 CDT first version + */ + +#ifndef __DRV_DMA_H__ +#define __DRV_DMA_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include +#include "ddl.h" +#include "drv_irq.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct dma_config { + //M0_DMA_TypeDef *Instance; + rt_uint32_t channel; + + //en_event_src_t trigger_evt_src; + + struct hc32_irq_config irq_config; +}; + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_DMA_H__ */ + diff --git a/bsp/hc32l136/drivers/drv_gpio.c b/bsp/hc32l136/drivers/drv_gpio.c new file mode 100644 index 0000000000..4473aad21a --- /dev/null +++ b/bsp/hc32l136/drivers/drv_gpio.c @@ -0,0 +1,449 @@ +/* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-8-19 pjq first version + */ + +#include +#include "rthw.h" + +#ifdef RT_USING_PIN +#include "gpio.h" +#include "drv_gpio.h" +#include "interrupts_hc32l136.h" + +#define GPIO_PIN_INDEX(pin) ((uint8_t)((pin) & 0x0F)) +#define GPIO_PORT(pin) ((uint8_t)(((pin) >> 4) * 0x40u)) +#define GPIO_PIN(pin) ((uint16_t)(GPIO_PIN_INDEX(pin))) + +#define PIN_NUM(port, pin) (((((port) / 0x40u) << 4) | ((pin) & 0x0F))) +#define PIN_MAX_NUM ((GpioPortD / 0x40u * 16) + (GpioPin15 + 1)) + +struct rt_pin_irq_hdr pin_irq_hdr_tab[] = +{ + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + +}; + +static void pin_irq_handler(en_gpio_port_t port, en_gpio_pin_t pin) +{ + rt_int32_t irqindex = -1; + + irqindex = PIN_NUM(port, pin); + if (pin_irq_hdr_tab[irqindex].hdr) + { + pin_irq_hdr_tab[irqindex].hdr(pin_irq_hdr_tab[irqindex].args); + } +} + +void Gpio_IRQHandler(uint8_t u8Param) +{ + en_gpio_pin_t i; + en_gpio_port_t enPort; + + enPort = (en_gpio_port_t)(GpioPortA + (GpioPortB - GpioPortA) * u8Param); + rt_interrupt_enter(); + for (i=GpioPin0; i<=GpioPin15; i++) + { + if(TRUE == Gpio_GetIrqStatus(enPort, i)) + { + Gpio_ClearIrq(enPort, i); + pin_irq_handler(enPort, i); + } + + } + rt_interrupt_leave(); +} + +//void PORTA_IRQHandler(void) +//{ +// en_gpio_pin_t i; +// +// rt_interrupt_enter(); +// for (i=GpioPin0; i<=GpioPin15; i++) +// { +// if(TRUE == Gpio_GetIrqStatus(GpioPortA, i)) +// { +// Gpio_ClearIrq(GpioPortA, i); +// pin_irq_handler(GpioPortA, i); +// } + +// } +// rt_interrupt_leave(); +//} + +//void PORTB_IRQHandler(void) +//{ +// en_gpio_pin_t i; +// +// rt_interrupt_enter(); +// for (i=GpioPin0; i<=GpioPin15; i++) +// { +// if(TRUE == Gpio_GetIrqStatus(GpioPortB, i)) +// { +// Gpio_ClearIrq(GpioPortB, i); +// pin_irq_handler(GpioPortB, i); +// } + +// } +// rt_interrupt_leave(); +//} + +//void PORTC_IRQHandler(void) +//{ +// en_gpio_pin_t i; +// +// rt_interrupt_enter(); +// for (i=GpioPin0; i<=GpioPin15; i++) +// { +// if(TRUE == Gpio_GetIrqStatus(GpioPortC, i)) +// { +// Gpio_ClearIrq(GpioPortC, i); +// pin_irq_handler(GpioPortC, i); +// } + +// } +// rt_interrupt_leave(); +//} + +//void PORTD_IRQHandler(void) +//{ +// en_gpio_pin_t i; +// +// rt_interrupt_enter(); +// for (i=GpioPin0; i<=GpioPin15; i++) +// { +// if(TRUE == Gpio_GetIrqStatus(GpioPortD, i)) +// { +// Gpio_ClearIrq(GpioPortD, i); +// pin_irq_handler(GpioPortD, i); +// } + +// } +// rt_interrupt_leave(); +//} + +static void hc32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +{ + uint8_t gpio_port; + uint16_t gpio_pin; + + if (pin < PIN_MAX_NUM) + { + gpio_port = GPIO_PORT(pin); + gpio_pin = GPIO_PIN(pin); + if (PIN_LOW == value) + { + Gpio_WriteOutputIO((en_gpio_port_t)gpio_port, (en_gpio_pin_t)gpio_pin, FALSE); + } + else + { + Gpio_WriteOutputIO((en_gpio_port_t)gpio_port, (en_gpio_pin_t)gpio_pin, TRUE); + } + } +} + +static int hc32_pin_read(rt_device_t dev, rt_base_t pin) +{ + uint8_t gpio_port; + uint16_t gpio_pin; + int value = PIN_LOW; + + if (pin < PIN_MAX_NUM) + { + gpio_port = GPIO_PORT(pin); + gpio_pin = GPIO_PIN(pin); + if (FALSE == Gpio_GetInputIO((en_gpio_port_t)gpio_port, (en_gpio_pin_t)gpio_pin)) + { + value = PIN_LOW; + } + else + { + value = PIN_HIGH; + } + } + + return value; +} + +static void hc32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +{ + uint8_t gpio_port; + uint16_t gpio_pin; + stc_gpio_config_t pstcGpioCfg; + + memset(&pstcGpioCfg, 0, sizeof(pstcGpioCfg)); + if (pin >= PIN_MAX_NUM) + { + return; + } + + switch (mode) + { + case PIN_MODE_OUTPUT: + pstcGpioCfg.enDir = GpioDirOut; + pstcGpioCfg.enDrv = GpioDrvL; + pstcGpioCfg.enCtrlMode = GpioAHB; + break; + case PIN_MODE_INPUT: + pstcGpioCfg.enDir = GpioDirIn; + pstcGpioCfg.enDrv = GpioDrvL; + pstcGpioCfg.enPuPd = GpioPu; + pstcGpioCfg.enOD = GpioOdDisable; + pstcGpioCfg.enCtrlMode = GpioAHB; + break; + case PIN_MODE_INPUT_PULLUP: + pstcGpioCfg.enDir = GpioDirIn; + pstcGpioCfg.enDrv = GpioDrvL; + pstcGpioCfg.enPuPd = GpioPu; + pstcGpioCfg.enOD = GpioOdDisable; + pstcGpioCfg.enCtrlMode = GpioAHB; + break; + case PIN_MODE_INPUT_PULLDOWN: + pstcGpioCfg.enDir = GpioDirIn; + pstcGpioCfg.enDrv = GpioDrvL; + pstcGpioCfg.enPuPd = GpioPd; + pstcGpioCfg.enOD = GpioOdDisable; + pstcGpioCfg.enCtrlMode = GpioAHB; + break; + case PIN_MODE_OUTPUT_OD: + pstcGpioCfg.enDir = GpioDirOut; + pstcGpioCfg.enDrv = GpioDrvL; + pstcGpioCfg.enOD = GpioOdEnable; + pstcGpioCfg.enCtrlMode = GpioAHB; + break; + default: + break; + } + gpio_port = GPIO_PORT(pin); + gpio_pin = GPIO_PIN(pin); + Gpio_Init((en_gpio_port_t)gpio_port, (en_gpio_pin_t)gpio_pin, &pstcGpioCfg); +} + +static rt_err_t hc32_pin_attach_irq(struct rt_device *device, rt_int32_t pin, + rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + rt_base_t level; + rt_int32_t irqindex = -1; + + if (pin >= PIN_MAX_NUM) + { + return -RT_ENOSYS; + } + + irqindex = pin; + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == pin && + pin_irq_hdr_tab[irqindex].hdr == hdr && + pin_irq_hdr_tab[irqindex].mode == mode && + pin_irq_hdr_tab[irqindex].args == args) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + if (pin_irq_hdr_tab[irqindex].pin != -1) + { + rt_hw_interrupt_enable(level); + return RT_EBUSY; + } + pin_irq_hdr_tab[irqindex].pin = pin; + pin_irq_hdr_tab[irqindex].hdr = hdr; + pin_irq_hdr_tab[irqindex].mode = mode; + pin_irq_hdr_tab[irqindex].args = args; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t hc32_pin_detach_irq(struct rt_device *device, rt_int32_t pin) +{ + rt_base_t level; + rt_int32_t irqindex = -1; + + if (pin >= PIN_MAX_NUM) + { + return -RT_ENOSYS; + } + + irqindex = pin; + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + pin_irq_hdr_tab[irqindex].pin = -1; + pin_irq_hdr_tab[irqindex].hdr = RT_NULL; + pin_irq_hdr_tab[irqindex].mode = 0; + pin_irq_hdr_tab[irqindex].args = RT_NULL; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t hc32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled) +{ + rt_base_t level; + en_gpio_port_t gpio_port; + en_gpio_pin_t gpio_pin; + rt_int32_t irqindex; + stc_gpio_config_t pstcGpioCfg; + + if ((pin >= PIN_MAX_NUM) || ((PIN_IRQ_ENABLE != enabled) && (PIN_IRQ_DISABLE != enabled))) + { + return -RT_ENOSYS; + } + + irqindex = pin; + gpio_port = (en_gpio_port_t)GPIO_PORT(pin); + gpio_pin = (en_gpio_pin_t)GPIO_PIN(pin); + if (enabled == PIN_IRQ_ENABLE) + { + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_ENOSYS; + } + + /* Exint config */ + pstcGpioCfg.enDir = GpioDirIn; + pstcGpioCfg.enDrv = GpioDrvL; + pstcGpioCfg.enPuPd = GpioPu; + pstcGpioCfg.enOD = GpioOdDisable; + pstcGpioCfg.enCtrlMode = GpioAHB; + Gpio_Init(gpio_port, gpio_pin, &pstcGpioCfg); + Gpio_ClearIrq(gpio_port, gpio_pin); + + switch (pin_irq_hdr_tab[irqindex].mode) + { + case PIN_IRQ_MODE_RISING: + Gpio_EnableIrq(gpio_port, gpio_pin, GpioIrqRising); + break; + case PIN_IRQ_MODE_FALLING: + Gpio_EnableIrq(gpio_port, gpio_pin, GpioIrqFalling); + break; + case PIN_IRQ_MODE_HIGH_LEVEL: + Gpio_EnableIrq(gpio_port, gpio_pin, GpioIrqHigh); + break; + case PIN_IRQ_MODE_LOW_LEVEL: + Gpio_EnableIrq(gpio_port, gpio_pin, GpioIrqLow); + break; + } + EnableNvic((IRQn_Type)(pin / 16), IrqLevel3, TRUE); + + rt_hw_interrupt_enable(level); + } + else + { + level = rt_hw_interrupt_disable(); + switch (pin_irq_hdr_tab[irqindex].mode) + { + case PIN_IRQ_MODE_RISING: + Gpio_DisableIrq(gpio_port, gpio_pin, GpioIrqRising); + break; + case PIN_IRQ_MODE_FALLING: + Gpio_DisableIrq(gpio_port, gpio_pin, GpioIrqFalling); + break; + case PIN_IRQ_MODE_RISING_FALLING: + + break; + case PIN_IRQ_MODE_LOW_LEVEL: + Gpio_DisableIrq(gpio_port, gpio_pin, GpioIrqLow); + break; + } + rt_hw_interrupt_enable(level); + } + + return RT_EOK; +} + +static const struct rt_pin_ops pin_ops = +{ + hc32_pin_mode, + hc32_pin_write, + hc32_pin_read, + hc32_pin_attach_irq, + hc32_pin_detach_irq, + hc32_pin_irq_enable, +}; + +int rt_hw_pin_init(void) +{ + Sysctrl_SetPeripheralGate(SysctrlPeripheralGpio, TRUE); + + return rt_device_pin_register("pin", &pin_ops, RT_NULL); +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + +#endif /* RT_USING_PIN */ diff --git a/bsp/hc32l136/drivers/drv_gpio.h b/bsp/hc32l136/drivers/drv_gpio.h new file mode 100644 index 0000000000..bc91b8393e --- /dev/null +++ b/bsp/hc32l136/drivers/drv_gpio.h @@ -0,0 +1,151 @@ +/* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-30 CDT first version + */ + +#ifndef __DRV_GPIO_H__ +#define __DRV_GPIO_H__ + +#include + +#ifdef RT_USING_PIN + +#define __HC_PORT(port) GpioPort##port +#define GET_PIN(PORT, PIN) (((rt_uint16_t)__HC_PORT(PORT) / 0x40 * 16) + PIN) + +#ifndef EXINT0_IRQ_CONFIG +#define EXINT0_IRQ_CONFIG \ + { \ + .irq = EXINT0_INT_IRQn, \ + .irq_prio = EXINT0_INT_PRIO, \ + } +#endif /* EXINT1_IRQ_CONFIG */ + +#ifndef EXINT1_IRQ_CONFIG +#define EXINT1_IRQ_CONFIG \ + { \ + .irq = EXINT1_INT_IRQn, \ + .irq_prio = EXINT1_INT_PRIO, \ + } +#endif /* EXINT1_IRQ_CONFIG */ + +#ifndef EXINT2_IRQ_CONFIG +#define EXINT2_IRQ_CONFIG \ + { \ + .irq = EXINT2_INT_IRQn, \ + .irq_prio = EXINT2_INT_PRIO, \ + } +#endif /* EXINT2_IRQ_CONFIG */ + +#ifndef EXINT3_IRQ_CONFIG +#define EXINT3_IRQ_CONFIG \ + { \ + .irq = EXINT3_INT_IRQn, \ + .irq_prio = EXINT3_INT_PRIO, \ + } +#endif /* EXINT3_IRQ_CONFIG */ + +#ifndef EXINT4_IRQ_CONFIG +#define EXINT4_IRQ_CONFIG \ + { \ + .irq = EXINT4_INT_IRQn, \ + .irq_prio = EXINT4_INT_PRIO, \ + } +#endif /* EXINT4_IRQ_CONFIG */ + +#ifndef EXINT5_IRQ_CONFIG +#define EXINT5_IRQ_CONFIG \ + { \ + .irq = EXINT5_INT_IRQn, \ + .irq_prio = EXINT5_INT_PRIO, \ + } +#endif /* EXINT5_IRQ_CONFIG */ + +#ifndef EXINT6_IRQ_CONFIG +#define EXINT6_IRQ_CONFIG \ + { \ + .irq = EXINT6_INT_IRQn, \ + .irq_prio = EXINT6_INT_PRIO, \ + } +#endif /* EXINT6_IRQ_CONFIG */ + +#ifndef EXINT7_IRQ_CONFIG +#define EXINT7_IRQ_CONFIG \ + { \ + .irq = EXINT7_INT_IRQn, \ + .irq_prio = EXINT7_INT_PRIO, \ + } +#endif /* EXINT7_IRQ_CONFIG */ + +#ifndef EXINT8_IRQ_CONFIG +#define EXINT8_IRQ_CONFIG \ + { \ + .irq = EXINT8_INT_IRQn, \ + .irq_prio = EXINT8_INT_PRIO, \ + } +#endif /* EXINT8_IRQ_CONFIG */ + +#ifndef EXINT9_IRQ_CONFIG +#define EXINT9_IRQ_CONFIG \ + { \ + .irq = EXINT9_INT_IRQn, \ + .irq_prio = EXINT9_INT_PRIO, \ + } +#endif /* EXINT9_IRQ_CONFIG */ + +#ifndef EXINT10_IRQ_CONFIG +#define EXINT10_IRQ_CONFIG \ + { \ + .irq = EXINT10_INT_IRQn, \ + .irq_prio = EXINT10_INT_PRIO, \ + } +#endif /* EXINT10_IRQ_CONFIG */ + +#ifndef EXINT11_IRQ_CONFIG +#define EXINT11_IRQ_CONFIG \ + { \ + .irq = EXINT11_INT_IRQn, \ + .irq_prio = EXINT11_INT_PRIO, \ + } +#endif /* EXINT11_IRQ_CONFIG */ + +#ifndef EXINT12_IRQ_CONFIG +#define EXINT12_IRQ_CONFIG \ + { \ + .irq = EXINT12_INT_IRQn, \ + .irq_prio = EXINT12_INT_PRIO, \ + } +#endif /* EXINT12_IRQ_CONFIG */ + +#ifndef EXINT13_IRQ_CONFIG +#define EXINT13_IRQ_CONFIG \ + { \ + .irq = EXINT13_INT_IRQn, \ + .irq_prio = EXINT13_INT_PRIO, \ + } +#endif /* EXINT13_IRQ_CONFIG */ + +#ifndef EXINT14_IRQ_CONFIG +#define EXINT14_IRQ_CONFIG \ + { \ + .irq = EXINT14_INT_IRQn, \ + .irq_prio = EXINT14_INT_PRIO, \ + } +#endif /* EXINT14_IRQ_CONFIG */ + +#ifndef EXINT15_IRQ_CONFIG +#define EXINT15_IRQ_CONFIG \ + { \ + .irq = EXINT15_INT_IRQn, \ + .irq_prio = EXINT15_INT_PRIO, \ + } +#endif /* EXINT15_IRQ_CONFIG */ + +#endif + +#endif /* __DRV_GPIO_H__ */ diff --git a/bsp/hc32l136/drivers/drv_soft_i2c.c b/bsp/hc32l136/drivers/drv_soft_i2c.c new file mode 100644 index 0000000000..4ee69b8de2 --- /dev/null +++ b/bsp/hc32l136/drivers/drv_soft_i2c.c @@ -0,0 +1,207 @@ +/* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-30 CDT first version + * 2021-01-18 CDT modify i2c gpio init + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "drv_soft_i2c.h" +#include "board.h" + +#if defined RT_USING_I2C + +#if !defined(BSP_USING_I2C1) && !defined(BSP_USING_I2C2) && \ + !defined(BSP_USING_I2C3) && !defined(BSP_USING_I2C4) && \ + !defined(BSP_USING_I2C5) && !defined(BSP_USING_I2C6) +#error "Please define at least one BSP_USING_I2Cx" +#endif + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +static const struct hc32_soft_i2c_config soft_i2c_config[] = +{ +#ifdef BSP_USING_I2C1 + I2C1_BUS_CONFIG, +#endif +#ifdef BSP_USING_I2C2 + I2C2_BUS_CONFIG, +#endif +#ifdef BSP_USING_I2C3 + I2C3_BUS_CONFIG, +#endif +#ifdef BSP_USING_I2C4 + I2C4_BUS_CONFIG, +#endif +#ifdef BSP_USING_I2C5 + I2C5_BUS_CONFIG, +#endif +#ifdef BSP_USING_I2C6 + I2C6_BUS_CONFIG, +#endif +}; + +static struct hc32_i2c i2c_obj[sizeof(soft_i2c_config) / sizeof(soft_i2c_config[0])]; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * This function initializes the i2c pin. + * + * @param Hc32 i2c dirver class. + */ +static void hc32_i2c_gpio_init(struct hc32_i2c *i2c) +{ + struct hc32_soft_i2c_config* cfg = (struct hc32_soft_i2c_config*)i2c->ops.data; + + rt_pin_mode(cfg->scl_pin, PIN_MODE_OUTPUT_OD); + rt_pin_mode(cfg->sda_pin, PIN_MODE_OUTPUT_OD); + + rt_pin_write(cfg->scl_pin, PIN_HIGH); + rt_pin_write(cfg->sda_pin, PIN_HIGH); +} + +/** + * This function sets the sda pin. + * + * @param Hc32 config class. + * @param The sda pin state. + */ +static void hc32_set_sda(void *data, rt_int32_t state) +{ + struct hc32_soft_i2c_config* cfg = (struct hc32_soft_i2c_config*)data; + + if (state) + rt_pin_write(cfg->sda_pin, PIN_HIGH); + else + rt_pin_write(cfg->sda_pin, PIN_LOW); +} + +/** + * This function sets the scl pin. + * + * @param Hc32 config class. + * @param The scl pin state. + */ +static void hc32_set_scl(void *data, rt_int32_t state) +{ + struct hc32_soft_i2c_config* cfg = (struct hc32_soft_i2c_config*)data; + + if (state) + rt_pin_write(cfg->scl_pin, PIN_HIGH); + else + rt_pin_write(cfg->scl_pin, PIN_LOW); +} + +/** + * This function gets the sda pin state. + * + * @param The sda pin state. + */ +static rt_int32_t hc32_get_sda(void *data) +{ + struct hc32_soft_i2c_config* cfg = (struct hc32_soft_i2c_config*)data; + + return rt_pin_read(cfg->sda_pin); +} + +/** + * This function gets the scl pin state. + * + * @param The scl pin state. + */ +static rt_int32_t hc32_get_scl(void *data) +{ + struct hc32_soft_i2c_config* cfg = (struct hc32_soft_i2c_config*)data; + + return rt_pin_read(cfg->scl_pin); +} + +static void hc32_udelay(rt_uint32_t us) +{ + rt_hw_us_delay(us); +} + +static const struct rt_i2c_bit_ops hc32_bit_ops = +{ + .data = RT_NULL, + .set_sda = hc32_set_sda, + .set_scl = hc32_set_scl, + .get_sda = hc32_get_sda, + .get_scl = hc32_get_scl, + .udelay = hc32_udelay, + .delay_us = 1, + .timeout = 100 +}; + +static rt_err_t hc32_i2c_bus_unlock(const struct hc32_soft_i2c_config *cfg) +{ + rt_uint32_t i = 0; + + if (PIN_LOW == rt_pin_read(cfg->sda_pin)) + { + while (i++ < 9) + { + rt_pin_write(cfg->scl_pin, PIN_HIGH); + //HC32_udelay(100); + rt_pin_write(cfg->scl_pin, PIN_LOW); + //hc32_udelay(100); + } + } + if(PIN_LOW == rt_pin_read(cfg->sda_pin)) + return RT_ERROR; + + return RT_EOK; +} + +/* I2C initialization function */ +int hc32_hw_i2c_init(void) +{ + rt_size_t obj_num = sizeof(i2c_obj) / sizeof(struct hc32_i2c); + rt_err_t result; + + for (int i = 0; i < obj_num; i++) + { + i2c_obj[i].ops = hc32_bit_ops; + i2c_obj[i].ops.data = (void*)&soft_i2c_config[i]; + i2c_obj[i].i2c1_bus.priv = &i2c_obj[i].ops; + hc32_i2c_gpio_init(&i2c_obj[i]); + result = rt_i2c_bit_add_bus(&i2c_obj[i].i2c1_bus, soft_i2c_config[i].bus_name); + RT_ASSERT(result == RT_EOK); + hc32_i2c_bus_unlock(&soft_i2c_config[i]); + } + + return RT_EOK; +} +INIT_BOARD_EXPORT(hc32_hw_i2c_init); + +#endif /* RT_USING_I2C */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l136/drivers/drv_soft_i2c.h b/bsp/hc32l136/drivers/drv_soft_i2c.h new file mode 100644 index 0000000000..64dec1184b --- /dev/null +++ b/bsp/hc32l136/drivers/drv_soft_i2c.h @@ -0,0 +1,128 @@ +/* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-30 CDT first version + */ + + +#ifndef __DRV_I2C_H__ +#define __DRV_I2C_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include +#include "hc32_ddl.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +struct hc32_soft_i2c_config +{ + rt_uint16_t scl_pin; + rt_uint16_t sda_pin; + const char *bus_name; +}; + +#ifdef BSP_USING_I2C1 +#define I2C1_BUS_CONFIG \ + { \ + .scl_pin = BSP_I2C1_SCL_PIN, \ + .sda_pin = BSP_I2C1_SDA_PIN, \ + .bus_name = "i2c1", \ + } +#endif + +#ifdef BSP_USING_I2C2 +#define I2C2_BUS_CONFIG \ + { \ + .scl = BSP_I2C2_SCL_PIN, \ + .sda = BSP_I2C2_SDA_PIN, \ + .bus_name = "i2c2", \ + } +#endif + +#ifdef BSP_USING_I2C3 +#define I2C3_BUS_CONFIG \ + { \ + .scl = BSP_I2C3_SCL_PIN, \ + .sda = BSP_I2C3_SDA_PIN, \ + .bus_name = "i2c3", \ + } +#endif + +#ifdef BSP_USING_I2C4 +#define I2C4_BUS_CONFIG \ + { \ + .scl = BSP_I2C4_SCL_PIN, \ + .sda = BSP_I2C4_SDA_PIN, \ + .bus_name = "i2c4", \ + } +#endif + +#ifdef BSP_USING_I2C5 +#define I2C5_BUS_CONFIG \ + { \ + .scl = BSP_I2C5_SCL_PIN, \ + .sda = BSP_I2C5_SDA_PIN, \ + .bus_name = "i2c5", \ + } +#endif + +#ifdef BSP_USING_I2C6 +#define I2C6_BUS_CONFIG \ + { \ + .scl = BSP_I2C6_SCL_PIN, \ + .sda = BSP_I2C6_SDA_PIN, \ + .bus_name = "i2c6", \ + } +#endif + +/** + ******************************************************************************* + ** \brief Open parameters. + ******************************************************************************* + */ +struct hc32_i2c_config +{ + rt_uint8_t scl; + rt_uint8_t sda; + const char *bus_name; +}; + +struct hc32_i2c +{ + struct rt_i2c_bit_ops ops; + struct rt_i2c_bus_device i2c1_bus; +}; + + +typedef struct hc32_i2c_instance +{ + rt_uint32_t id; + void *handle; + stc_i2c_init_t init; +} hc32_i2c_instance_t; + + +int hc32_hw_i2c_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_I2C_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l136/drivers/drv_usart.c b/bsp/hc32l136/drivers/drv_usart.c new file mode 100644 index 0000000000..535191af03 --- /dev/null +++ b/bsp/hc32l136/drivers/drv_usart.c @@ -0,0 +1,627 @@ +/* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-30 CDT first version + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include +#include +#include "gpio.h" +#include "uart.h" +#include "drv_usart.h" + +#ifdef RT_USING_SERIAL + +#if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) +#error "Please define at least one BSP_USING_UARTx" +/* UART instance can be selected at menuconfig -> Hardware Drivers Config -> On-chip Peripheral Drivers -> Enable UART */ +#endif + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ +/* HC32 config Rx timeout */ +struct hc32_uart_rxto +{ + //M4_TMR0_TypeDef *TMR0_Instance; + rt_uint32_t channel; + + rt_size_t timeout_bits; +}; + +/* HC32 UART index */ +struct uart_index +{ + rt_uint8_t index; + rt_uint8_t idx; + //M0P_UART_TypeDef *Instance; +}; + +/* HC32 UART irq handler */ +struct uart_irq_handler +{ + void (*tx_irq_handler)(void); + void (*rxerr_irq_handler)(void); + void (*rx_irq_handler)(void); + void (*cts_irq_handler)(void); + void (*pei_irq_handler)(void); +// void (*dma_rx_irq_handler)(void); +}; + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +#ifdef RT_SERIAL_USING_DMA +static void hc32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag); +#endif + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +enum +{ +#ifdef BSP_USING_UART0 + UART0_INDEX, +#endif +#ifdef BSP_USING_UART1 + UART1_INDEX, +#endif + UART_INDEX_MAX, +}; + +static const struct uart_index uart_map[] = +{ +#ifdef BSP_USING_UART0 + {UART0_INDEX, UARTCH0}, +#endif +#ifdef BSP_USING_UART1 + {UART1_INDEX, UARTCH1}, +#endif +}; + +static struct hc32_uart_config uart_config[] = +{ +#ifdef BSP_USING_UART0 + { \ + .name = "uart0", \ + .idx = UARTCH0, \ + }, +#endif +#ifdef BSP_USING_UART1 + { \ + .name = "uart1", \ + .idx = UARTCH1, \ + } +#endif +}; + +#ifdef BSP_USING_UART0 +static int uart0_rx_flag; +#endif +#ifdef BSP_USING_UART1 +static int uart1_rx_flag; +#endif +static struct hc32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0}; +static const struct uart_irq_handler uart_irq_handlers[sizeof(uart_obj) / sizeof(uart_obj[0])]; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +//static uint32_t hc32_get_uart_index(M0P_UART_TypeDef *Instance) +static uint32_t hc32_get_uart_index(uint8_t idx) +{ + uint32_t index = UART_INDEX_MAX; + + for (uint8_t i = 0U; i < ARRAY_SZ(uart_map); i++) + { + if (uart_map[i].idx == idx) + { + index = uart_map[i].index; + RT_ASSERT(index < UART_INDEX_MAX) + break; + } + } + + return index; +} + +#if defined(BSP_USING_UART0) +void uart0_gpioinit(void) +{ + stc_gpio_config_t stcGpioCfg; + DDL_ZERO_STRUCT(stcGpioCfg); + stcGpioCfg.enDir = GpioDirOut; + Gpio_Init(GpioPortA,GpioPin9,&stcGpioCfg); + Gpio_SetAfMode(GpioPortA,GpioPin9,GpioAf1);//TX + stcGpioCfg.enDir = GpioDirIn; + Gpio_Init(GpioPortA,GpioPin10,&stcGpioCfg); + Gpio_SetAfMode(GpioPortA,GpioPin10,GpioAf1);//RX +} +#endif + +#if defined(BSP_USING_UART1) +void uart1_gpioinit(void) +{ + stc_gpio_config_t stcGpioCfg; + + DDL_ZERO_STRUCT(stcGpioCfg); + stcGpioCfg.enDir = GpioDirOut; + Gpio_Init(GpioPortA,GpioPin2,&stcGpioCfg); + Gpio_SetAfMode(GpioPortA,GpioPin2,GpioAf1);//TX + stcGpioCfg.enDir = GpioDirIn; + Gpio_Init(GpioPortA,GpioPin3,&stcGpioCfg); + Gpio_SetAfMode(GpioPortA,GpioPin3,GpioAf1);//RX +} +#endif + +static rt_err_t hc32_configure(struct rt_serial_device *serial, + struct serial_configure *cfg) +{ + struct hc32_uart *uart; + uint16_t u16Scnt = 0; + stc_uart_config_t stcConfig; + stc_uart_irq_cb_t stcUartIrqCb; + stc_uart_multimode_t stcMulti; + stc_uart_baud_t stcBaud; + uint8_t index; + en_uart_mmdorck_t enTb8; + + DDL_ZERO_STRUCT(stcConfig); + DDL_ZERO_STRUCT(stcUartIrqCb); + DDL_ZERO_STRUCT(stcMulti); + DDL_ZERO_STRUCT(stcBaud); + + RT_ASSERT(RT_NULL != cfg); + RT_ASSERT(RT_NULL != serial); + + uart = rt_container_of(serial, struct hc32_uart, serial); +#if defined(BSP_USING_UART0) + if (uart->config->idx == UARTCH0) + { + uart0_gpioinit(); + } +#endif + +#if defined(BSP_USING_UART1) + if (uart->config->idx == UARTCH1) + { + uart1_gpioinit(); + } +#endif + + /* Configure USART initialization structure */ + index = hc32_get_uart_index(uart->config->idx); + stcUartIrqCb.pfnRxIrqCb = uart_irq_handlers[index].rx_irq_handler; + stcUartIrqCb.pfnTxIrqCb = uart_irq_handlers[index].tx_irq_handler; + stcUartIrqCb.pfnRxFEIrqCb = uart_irq_handlers[index].rxerr_irq_handler; + stcUartIrqCb.pfnPEIrqCb = uart_irq_handlers[index].pei_irq_handler; + stcUartIrqCb.pfnCtsIrqCb = uart_irq_handlers[index].cts_irq_handler; + stcConfig.pstcIrqCb = &stcUartIrqCb; + stcConfig.bTouchNvic = TRUE; + + stcConfig.enRunMode = UartMode3;//ģʽ3 + stcMulti.enMulti_mode = UartNormal;//Õý³£¹¤×÷ģʽ + + if(BIT_ORDER_LSB == cfg->bit_order) + { + + } + else + { + + } + + switch(cfg->stop_bits) + { + case STOP_BITS_1: + stcConfig.enStopBit = Uart1bit; + break; + case STOP_BITS_2: + stcConfig.enStopBit = Uart2bit; + break; + default: + break; + } + + switch(cfg->parity) + { + case PARITY_NONE: + enTb8 = UartDataOrAddr; + break; + case PARITY_EVEN: + enTb8 = UartEven; + break; + case PARITY_ODD: + enTb8 = UartOdd; + break; + default: + enTb8 = UartDataOrAddr; + break; + } + + switch(cfg->data_bits) + { + case DATA_BITS_8: + break; + default: + return -RT_ERROR; + } + + Uart_SetMMDOrCk(uart->config->idx, enTb8); + stcConfig.pstcMultiMode = &stcMulti; + Uart_Init(uart->config->idx, &stcConfig); + + Uart_SetClkDiv(uart->config->idx, Uart8Or16Div); + stcBaud.u32Pclk = Sysctrl_GetPClkFreq(); + stcBaud.enRunMode = UartMode3; + stcBaud.u32Baud = cfg->baud_rate; + u16Scnt = Uart_CalScnt(uart->config->idx, &stcBaud); + Uart_SetBaud(uart->config->idx, u16Scnt); + + Uart_ClrStatus(uart->config->idx, UartTC); + Uart_ClrStatus(uart->config->idx, UartRC); + Uart_DisableIrq(uart->config->idx, UartTxIrq); + Uart_DisableIrq(uart->config->idx, UartRxIrq); + Uart_EnableFunc(uart->config->idx, UartRx); + + return RT_EOK; +} + +static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct hc32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + uart = rt_container_of(serial, struct hc32_uart, serial); + + switch (cmd) + { + /* disable interrupt */ + case RT_DEVICE_CTRL_CLR_INT: + Uart_DisableIrq(uart->config->idx, UartRxIrq); + break; + + /* enable interrupt */ + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + Uart_ClrStatus(uart->config->idx, UartRC); + Uart_EnableIrq(uart->config->idx, UartRxIrq); + break; + + case RT_DEVICE_CTRL_CLOSE: + break; + } + + return RT_EOK; +} + +static int hc32_putc(struct rt_serial_device *serial, char c) +{ + struct hc32_uart *uart; + + RT_ASSERT(RT_NULL != serial); + + uart = rt_container_of(serial, struct hc32_uart, serial); + + if(serial->parent.open_flag & RT_DEVICE_FLAG_INT_TX) + { + if (Uart_GetStatus(uart->config->idx, UartTC) == FALSE) + { + return -1; + } + } + Uart_SendData(uart->config->idx, c); + + return 1; +} + +static int hc32_getc(struct rt_serial_device *serial) +{ + int ch= -1; + struct hc32_uart *uart; + + RT_ASSERT(RT_NULL != serial); + + uart = rt_container_of(serial, struct hc32_uart, serial); + +#if defined(BSP_USING_UART0) + if (uart->config->idx == UARTCH0) + { + if (serial->parent.open_flag & RT_DEVICE_FLAG_INT_RX) + { + if (uart0_rx_flag) + { + ch = Uart_ReceiveData(uart->config->idx); + uart0_rx_flag = 0; + } + } + else + { + if(Uart_GetStatus(uart->config->idx, UartRC)) + { + Uart_ClrStatus(uart->config->idx, UartRC); + ch = Uart_ReceiveData(uart->config->idx); + } + } + } +#endif +#if defined(BSP_USING_UART1) + if (uart->config->idx == UARTCH1) + { + if (serial->parent.open_flag & RT_DEVICE_FLAG_INT_RX) + { + if (uart1_rx_flag) + { + ch = Uart_ReceiveData(uart->config->idx); + uart1_rx_flag = 0; + } + } + else + { + if(Uart_GetStatus(uart->config->idx, UartRC)) + { + Uart_ClrStatus(uart->config->idx, UartRC); + ch = Uart_ReceiveData(uart->config->idx); + } + } + } +#endif + + return ch; +} + +static rt_size_t hc32_dma_transmit(struct rt_serial_device *serial, + rt_uint8_t *buf, + rt_size_t size, + int direction) +{ + + return 0; +} + +static void hc32_uart_rx_irq_handler(struct hc32_uart *uart) +{ + RT_ASSERT(RT_NULL != uart); + + rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_RX_IND); +} + +static void hc32_uart_tx_irq_handler(struct hc32_uart *uart) +{ + RT_ASSERT(RT_NULL != uart); + + if (uart->serial.parent.open_flag & RT_DEVICE_FLAG_INT_TX) + { + rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_TX_DONE); + } +} + +static void hc32_uart_rxerr_irq_handler(struct hc32_uart *uart) +{ + RT_ASSERT(RT_NULL != uart); +} + +static void hc32_uart_cts_irq_handler(struct hc32_uart *uart) +{ + RT_ASSERT(RT_NULL != uart); +} + +static void hc32_uart_pei_irq_handler(struct hc32_uart *uart) +{ + RT_ASSERT(RT_NULL != uart); +} + +#ifdef RT_SERIAL_USING_DMA +static void hc32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag) +{ + +} +#endif + +#if defined(BSP_USING_UART0) +static void hc32_uart0_rx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart0_rx_flag = 1; + hc32_uart_rx_irq_handler(&uart_obj[UART0_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart0_tx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_tx_irq_handler(&uart_obj[UART0_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart0_rxerr_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rxerr_irq_handler(&uart_obj[UART0_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart0_cts_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_cts_irq_handler(&uart_obj[UART0_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart0_pei_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_pei_irq_handler(&uart_obj[UART0_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +#endif /* BSP_USING_UART0 */ + +#if defined(BSP_USING_UART1) +static void hc32_uart1_tx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_tx_irq_handler(&uart_obj[UART1_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart1_rxerr_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rxerr_irq_handler(&uart_obj[UART1_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart1_rx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart1_rx_flag = 1; + hc32_uart_rx_irq_handler(&uart_obj[UART1_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart1_cts_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_cts_irq_handler(&uart_obj[UART1_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart1_pei_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_pei_irq_handler(&uart_obj[UART1_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART1 */ + +static const struct uart_irq_handler uart_irq_handlers[] = +{ +#ifdef BSP_USING_UART0 + { hc32_uart0_tx_irq_handler, hc32_uart0_rxerr_irq_handler, hc32_uart0_rx_irq_handler, + hc32_uart0_cts_irq_handler, hc32_uart0_pei_irq_handler + }, +#endif +#ifdef BSP_USING_UART1 + { hc32_uart1_tx_irq_handler, hc32_uart1_rxerr_irq_handler, hc32_uart1_rx_irq_handler, + hc32_uart1_cts_irq_handler, hc32_uart1_pei_irq_handler + }, +#endif +}; + +static void hc32_uart_get_dma_config(void) +{ + +} + +static const struct rt_uart_ops hc32_uart_ops = +{ + .configure = hc32_configure, + .control = hc32_control, + .putc = hc32_putc, + .getc = hc32_getc, + .dma_transmit = hc32_dma_transmit +}; + +int hc32_hw_uart_init(void) +{ + rt_err_t result = RT_EOK; + rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct hc32_uart); + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + + hc32_uart_get_dma_config(); + + Sysctrl_SetPeripheralGate(SysctrlPeripheralGpio,TRUE); + //Sysctrl_SetPeripheralGate(SysctrlPeripheralDma,TRUE); +#ifdef BSP_USING_UART0 + Sysctrl_SetPeripheralGate(SysctrlPeripheralUart0,TRUE); +#endif +#ifdef BSP_USING_UART1 + Sysctrl_SetPeripheralGate(SysctrlPeripheralUart1,TRUE); +#endif + + for (int i = 0; i < obj_num; i++) + { + /* init UART object */ + uart_obj[i].serial.ops = &hc32_uart_ops; + uart_obj[i].serial.config = config; + uart_obj[i].config = &uart_config[i]; + + /* register UART device */ + result = rt_hw_serial_register(&uart_obj[i].serial, + uart_obj[i].config->name, + (RT_DEVICE_FLAG_RDWR | + RT_DEVICE_FLAG_INT_RX | + RT_DEVICE_FLAG_INT_TX | + uart_obj[i].uart_dma_flag), + &uart_obj[i]); + RT_ASSERT(result == RT_EOK); + } + + return result; +} + +INIT_BOARD_EXPORT(hc32_hw_uart_init); + +#endif /* RT_USING_SERIAL */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l136/drivers/drv_usart.h b/bsp/hc32l136/drivers/drv_usart.h new file mode 100644 index 0000000000..a7dd69a0ad --- /dev/null +++ b/bsp/hc32l136/drivers/drv_usart.h @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-30 CDT first version + */ + + +#ifndef __DRV_USART_H__ +#define __DRV_USART_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include +#include "rtdevice.h" + +#include "ddl.h" +#include "uart.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/* HC32 config uart class */ +struct hc32_uart_config +{ + const char *name; + rt_uint8_t idx; + rt_uint16_t uart_dma_flag; + struct rt_serial_device serial; +}; + +/* stm32 uart dirver class */ +struct hc32_uart +{ + struct hc32_uart_config *config; +#ifdef RT_SERIAL_USING_DMA + +#endif + rt_uint16_t uart_dma_flag; + struct rt_serial_device serial; +}; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +int rt_hw_uart_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_USART_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l136/figures/board.png b/bsp/hc32l136/figures/board.png new file mode 100644 index 0000000000000000000000000000000000000000..b5b5b368d10a1e439e4d35605f444b7b432b8757 GIT binary patch literal 322618 zcmY&zUu4d> z^5?$`!{?Qz>XW(&roDd;Y!?-Ml_yUcQ;6>DasIst09qD4Po9v%{^wu}c~&|-dGc7M zt)^lEvN^o>1z7*;-ie#IMXHbKT`9b28E|TJ(ruz^rE9g*eLFTb_DTI+j5zJ$o2_TG zr8y(+Svke-v@nFv@!#8yAlbEqxX_c3b=#w#haZb%{g3p9)Vium6VV#mBN;@^&5GCK zV;KiwP`zw|=k`2f;2cq^2MCl{&*gt3kA0$8GylTx{u4ojiH`LGbHQQPL#*G5P(|M! zPYq|4LLrZLB0WO~w}z?uZPVTF>qwdBDLGjbaxcnlQCxpPQr6U6dh!D2okvIb{Q7!?GPz-DaIdaRX$c9KB z@KZk@C3%e#I?Q+t^UN&^$p#=fyCCc5=4ICN@-tuLW z?!+j*u8kEuR0Vp8l;{Le*vu!T{uTz)lCfppCT@AX9>Gnul8FTGM{8BmztoxI6Mq(y zW;_EqUsCzHkfdxY6*IOZwmC1N7J7yq-;oKOYRAv{TpWanqma(GXPGFzo#iK_5-=%l zLRP1-HSGF1sYZ1U>N|^TA{?*NDTd%%caoc4XMNH$K^LaX)!-iWhV; zh5a}*n;FCTo zmxjkfex_~^>Cl8tZ{zD70BV!}Q0a>MvY@Be*9EXYqMqOBjpHI>JBTw#OK02VO=IS< z)}Qg#A8E==JzPD()CCub-Xfkv3v!%Kf+oGMbY{91cGnL zSP%%<5c=lCQ9kgT{HiA~Jn!lVIblZDen-Qi)Rm$+i&fWoyDP?`7z*|@zhv~dtrb-2 zfU<2_ z_05yE)di`x2ZqqQ8^X|lV45EJj^v_mMJzT!RhkQ9kKdl#cf`F+bN$hFfRrK72 zhdrE;p=XpH>F3fJY48;YV-TN|Fn7AVq<4~GLjIJ6?Nq2=%#mh(L|xyj;5o*mlQj%u zoLwuYxA6QqEWDSj`KJ)L`({f!CqTf0cp*|udWX1I0Lm?s3!3U zcnOd=hedl&F!!#kc(l1l^$E0-9vN?;rrtmWnsGdGegeiABCT8U7qG8>{S{w==e{D^ z=_i!tH91)cg!eoCF=~;yZy4Q;a@3)WVIx?2{^Ge$ZgytRN#@$)cJZhiUcFl5&=OVU74xiyC!Ru|u$J(~!XO zXz+SYx$!G43D-x&u-}lf*S*6QD+`GgVpMgX!-iJ#P?-G8wv2&SZQ(mcbLWPq2pwxU zTs+yR9wN7HrL%9=ZT#X&Xn!$E{_C`3->cu`q;2aSf9Ij(8SWR(bL4U+M@tZn>RTRj zjD1aw1MCq3uk;6ZvMro{-BxgfEx|;nT@d4M`a^#p-8G~id^&PFJE6_muGOYMSTb% zfr=kc6mnOov~^>qXOH7iDyY=a>!9cF> z-kGNJ7%%mei049vg%4CcoJCF#aP6IJJl=>9XDINw)2V#8mDZ7~Y!Nf@(<>?Vr)Ri% zT3Sd`7PCh1gH%X;VNnN|RIhf`uXAo#3nM?Cocb+9XW2r)SuJVrz3L}u`ABHm5cxfD z)T3tURC4}f0F}tc^`vpRby!QQ;y|(jD>B1hsn6{=EM~Qc1$v9uV~4XvOq#C%Ik@tq zTJgu%r_u@w2!1(Wc#iJ4R`TW1Tlm))K2Sbv87gfQJ)SB&?1`)+M6maY9?yx6?(gLK zTLdF@_o(v|c>cz*xN75>?X z2(K{3dY+BxJHeTrDK4nH`{voM&N9VoD517D&B{zb?Vq0wjyOZ?o~ap0k|6F(m`LN3 z6CCg>Q-T$Tq^=mtHUR4cea)B?5XxKo^o-J*q98Y!*pZ^-)tQ)5Ga-x2YS#oy8(k2> z@vtv)Oapsphm*61&^VA&)q4b__;&08Vf`AjO^IJUAWJf?sAPQ8N0<1VR9 zgVs12V1LN;7ULF;yU2s`r&z#T-o=&HoU`-bN}(}+Qel)CR|9qg;xGYy?}DWI*gIGZ z1Ua{uRO1oUukd$7S)@9i`XKY{>Z>98FGe*Mdf%9lRK&hIs(9i9^G1;8k}RXFSSqr6 zVB(pzVCKi|mgzSQ3ESR!{D;{tlktVRPW&sJprV(c?mmsSm~AiHX!$I0Y4t3qSQR#@ zydfl(qdWmY_Zqvk-(mB`1#+BBu|)1?N>O)5x!tp5AZ~e>l09zu4AQ)Ib~&=<)ul z@$c5hw!kX^U}AktT@3jo3mX`_&6)3*0oF}bff_leMjP^7%x`}C9V!6vJJ*7#G?NQ^lckh2K3UQWRkao`-|e zuU)1)feIx8G3YPHkPu5Ugh|4AiAFH`A4s_E;{`pI{#*d))xT8xjq_H<`_16+6C@DXpg{ z6dkFr_HtPv*cT()v9oP~7*A{0O5ma`4hp~+9cl2+iMf7*_7PZL_R;2> zFMiqRp-mSlmVi`o<;TzD0z6+qV_b!1uB`djt^WE|rMk81GzE@0%uYtGGVZX%hPaQB zZ-S+294+``x4Z}{@MRZgOL(~Gmf;LG*auUp<_8R7ymidqOLNWZD1;H*s1zY}Cmn9g zjZp-(MuWN(R5)TMW03>`mTcqIBGO{t-aBn%lO*%7&uK^)cFDnAtoQ+wZA@~O<1;1Q z$hFs{d&}Db9jQNg!t&! zs#t!YnkZD%ja@T&Qt)B>{+95$XaNtx_Tl`w{f*GWX;wYK?;_N_NSLzmf~xe6FRUCy zz(imIfetj3K5rh)DM`o;4>Ofwz4P4ooz$r{=fW-|j2l4zq0ReVain7bg;>WM(vuy` zj|O~s>BD2hOkg^c@71<@`*{X!_xQnmtp!V4`y@7wUp7i&RU@e3!}V!MooL-aN;L7|MS8wCKZqc2ec1DbdSj&n=C zvA+kr!x|SK_6-g}o=SI340~G3?LD&CWpCh{IiqyDe^pG}UvN~47!+tOpiSG(5DHmj zR#}UeLF*`U^lgM0XZK{3T#c(rgh7hk^Qd5~A4a1^> z7VS@2nPu_n%{y2khoi}S78ZkRR+||`dM;$oZ=80Y|0XyQnfm#jikZcl*1E>gTj1%} z&+y$}M2ihx0>l=3mG$+|G@pf36CKpR?8(Y5=HAMy_+^u#?O~|>=d29J)tlPI3xpVm zcS@gI@~o{EzzedB$wI7T(N51SL~OTc9I}rs56xExxfcB<41&J;(h|JNDDAcX;^szH ztoc2KqI~bj8;WB$D`xj}S^LQz3nLAZwHvrk@aZ2H^QK^#mcJl^gn4(Ke$ay~rbGm4 z!d>0r1LGyDQuJ!)dcW+0kWBzm!O0W|6V4Bh|FCt@q}NC8x(vDQY)>rk>>eRpcx&Eb z&l`+P5QCt8a2PQo87SUNB}Aw*o*;PfP9~O*ky`~pM(gA25(QPv5w5lA@9ufj7;>lO z8VQ3G(dHMd^?%NvMG|;r%egc-0wc2J6yG@sUUxX>fjkVQj=Wx%gk(qTy&!nJ%ko71gEnC|Gg9a?*04dto;w!xRZf6d)1~zboFS-o$F%n1jzRBy z?+auq6vL|R1i$ELHO1tmq=N$|1v6E&{_?-Qo|kf;ddTHC9mFh>>8py zV4$c-3w~CeVsA;@!0?m{8;=TPxXnDjCy-GkCJ?i{(4&I1F}hZI5YP3EzQV?*bo^FP zYBN*&o!cQhMl0MQHRwyTnDVp?`7Ep{7iV^94M+p(NzG~l%ir`oJ4OpE7g;h|*-YzW zmfrqN%Ko7N_7}OzNht#lA_g3_pM(=9`g06M<+`bDt=eL4G-OM6Mb-M%N*Zd2H79I` zf;$*AWtH(T`8yrRD<*AT`thXDvn2IS0f~5DKyT3;exr>;zir}G4cj&k0w$Rjq zh*%WcGvd*#dNt%Ou43Yz!QSDDV>Rj_;w{#fGASGucG>U?OK5jeNAUO2!#i}(+KE6a2I*@wq0&)1~xz?{SyLKFWLZbft zak&QI8H=>KDJ-sTLb8c6ozbRmrzkjPco-iH#-+MULj%@nhwB-+opxiX0z!>(yE>2Q za0ynf`y#qLjYa8vyx{%Zpo5VB5e7J&b<)&V@qGCZdhW6Kn7 z76sGBGC_+sbu014N;Hv{ooRTv3 zOD`KW^;39l3h7C92B75onNu`R#L+F%kj#GQk{O?XQ2D(%{=7Sg;PruR%$rJz?W|(bGfoeXKgiCaO*>vaD^3eLAne#-557RlB_`^Z#P(#(<+V7v zk5@O4jKw4=zo=sQ4yxZ4{aEd`efjE_W3*^9P3R5o;nF=z=*_-xXt15@+WlT*_<8xh zZUMoJ+<%!L4z0(nNuKP7trR6hO4tL{Q;$F#4;%%6pl!LGt7iBT{h(dma|}Efc2|>Z z!%=ezYB%q=5%i1N+gn_;9Yl~^_%kkY+ZkZ67o*Vkp{NtvAYc@KnqZNPxJ84uA7tvj%3xo?z16YIUaMWK44)L&{#abW4`=)->XHi{oD zzXUZQpR8u15~RAJTnibWGmFbxSgK9yhX$>0?U=39ME#*W9hg`N3rJ}5!F$&#b!%T4 z*XpX1(`wJssxSrjja-5mMb%b@<72sqtd^s2_Mz|+sH%zS+{W+m+t^_qy#NmnZD#XS ztN7QnBE^kmEP+rNP5~-~pCQtL4}?sdB=YZw4jo;MSES=PH4Qm<7s3-0xxSY1I9x1^ zgOa}Z$5x8=z38GA@axiFxS}iwl&9RSN&iH7B8)Kk(+)pQ;_VT8Qmfg0bRH*?qa4wIO#vHl75x#VCB4+k_zIJ^mUGvoG^g;4; zMaM`Gc=Abcj)ZqNQp=k#hZKoSM$7o!JwOgRYnmHKl?Tsw71hkxx&guS=l?D+XLkemhyNA+oBTIt{@}esA`w0A&_N~M|;qSI2I^S{@BX5=NBJX((5W_hM zi(wkd@}$+Vvh(wJ-)z7%B=(4yRnYn0N%U^1q1WZ;XmCT3Cg`02voX=(r$G4UrP!`D z?nR$NYT@;;*c2tD*ypr$8_pd@|M&s(X_YYpE_tBDFuT)H=+)bmhkcAuD`>kwYoqs2 zP(un|3`vBWuHE&!7JI+|Y4GE15Bz4FQQ8+FpBx%MBLS;M1B9Ii?C>wKx2&xB*EV3M zM+@ulm4O6luN(Q~{Eo;Ur|fgU-Cnl_T~|#Yh5)wI5dv|wju;$YZVUX&a#_@cRpbO! z$KCpR0gEG>E05qtM+|iZ-b+s8cMiM#OeQ0>1#?c0%S89;A4T|>5J>*Krl?zMPY{su z*npN*OM9PUKCKJInWq4TVgKZ0_Oc7ax@7H%55Y@@>vr_QAfz)SYZ@U#uT(#0q_!C> zYJ4uO^kpYy=>!`pp{aROScl#Qtqq*$`jh8djN*l)dmotgwVStZeLM`fweGqY%mevc zdAP4P6M3Sf9GKsQW36WVtRq$I2<}+oTx@h?^y_J)a$E4|eT%(1!W<+jr)7v|_L7Z; zvp)2RXBe7-Co9PwP(oG;yI%}Df1x9r1?8zBZV}T5kV@K}ESWWU+-ne@14}x7fW4#? z!H;TthIs;djy7zUM+qn4P^=&<4U}`Jp$A{$KKjrqv--8xMTX__rmPHQh177%AQ~ zu;cIaw+OhnGOt2MUOh+3ntLrTD6Q%8E+?ZJ?6C1}*(KSZ1}Q4wTYF#~0)@aIo~x{k zeZ1~0>ulD3ZzkFt=NazeEn!-}o_I_!bKKLB%*vXR>mQb;Xd*lb-eZ1eC#w&&eLyom zoLt!=MS4QO>-T!n4``CLyE{I4Z&^EAQJf)6)fb+Tq6IG!0xU|a+9ml)DUj8E4v&B2 zL|cR-X;^2)+XfU9P~(|q_NK7Rx>@18QJDlfAEiIA{kbf76#zyvOcl0m+f8i zCrRkLO_D>o5F(<5BWNVh%g48?;vS$yZxm&LdG2d|y##3k9S7xiUI=y2dYYyBYQ2wn z8CYLMzNl`(QQW|K%p?tg^xSb8ScUcmbrFyPLov0N+iWE026?y`$2s%7F83GECnAsZ zn!;-_#m-DV9AA4Haay|keK=g<%x1|#^`WuLR~CP6b{^vm%|FD792XzdZ*=eOI}*fB zacs^K!%JUQ0Jcx{?=FiT7}sQgEJWh2_N=2lIM#K(CM1UhBM6$esJ=c<>40m(?)&S> z#hXhN>9Yq*%@fa2*I~J)*emuD~Cl?@V46Q*|9NB=NGG*unX(1t3UScVZKr}0rv{Q zUITs-Lx2>$C**gu)TcR$_MKWSC_^RQh<9eLj-M9oaF10lQxt>Ks;f6Vv z%hnvnPVJa?vJuJjf>;RFUCP_we(k#ZUAz&r#lR#JhW8Lh(WBO>T7j_n?na&-dp_dmIi zB17G1;vozm?>xU!jk7|S9dTZH<;18z^W$K%#wS`p^MEQ^zhQ`z-cVrrh`G0~N%{~l zHDyAD6DCYG&iC8(%e!zn>Jy1!F<JrHqhD0%=ntg8*?H9|hjD9v~A8=v^Ap}d+ z_d?yF0``oiBoK3Yr|;zRzg{+MUz)y>Y$iIgxCbQGM(L-fk^Q0Uc-awyt$6pT^O}v9 zFFgp6Jx_FeD12cV`B4qS9S!i;Ig0w|s^tFsW_H-5x?fVZ%e0Mae#Uu*Kbi)W?c3nU z-6x!rEEfPqF&a&IPjUtO1i|~7NU>8xfZX}*N}XJhpLcfD{P*)^!*K@f!E~KsBBk0H zX$uleU-ND9Zz>tI4|7%%z&B<16Mw;m&sGD7nVkgfb-rkCL4|$k4EXQ6T&(ej4^+U7 z%ny4PUE7v(Y9F)u5A?XeER+?gC?clmS?^f@W}b=p5jYn3gvMXUn4=Vc>5_h4Xrdhy|{m#x?J$6ebd=9jvD z%C<`ha6waSf)!fm9{%-hE{zp-O04_~(wf0f7oB2F=QRB%D z!uL=ixX?~1ag~)>!+3^k^|=5O_^77x>Dac+WN~S8{MWXE7a?!Y6gvjY>|Fo2u5^S_ z_igSl^*n_2mOW%w()<1Ea^mgAh4p zgCl9CM8}4*=NUgjj=t`N7A!G9^uDau>G-$Lf8 zBXl%#WpK>yvDxJ@s|7oB6wg;F@zCLiP%B0Ed;)n0wXE{?TPkIr>=p{m%rQIwrQ6x5 zft}tzvXB{DMQL>UV^a-D#D1y@MdW2LKn{i2qMOEcu_imi$5fq7zV(JHmbK6F*U<|% zVq(fZFCWmB!`Dj>B-jyVdHaRGe(MKRrW?bDih)2&v5mledDdp}4AcUwAl(ByJILiD zT@eOPWDa&ac5j#hm?G*v{${(MD1^ zjyt4V-jmTZyQWM@ri0XjKmw(+b)Rac2E?>7eYZLHi3`eCc$E}zS;Mz@@C=^2riX5& zk_M+n^4n`)339sEa#oAUNwfN;X@JTlPC5v9W#zZ#@rC!&fg2|u_kvv@4c^qBCwu4x z=~sDQ{LLQdDac5kNTw-~AvzUXmZA~~bcSY<`#GuWu*qsF^LnIaU>r=n8Y{oe z-^z$t2Yu~}OP)x!6Bd z-^?yYk-A&q!gCQ5RyQWLC|!sdkbQf|v^OoI!y;5;ar)zA@_W;!cieq3P4OFk!1LcC zADMYMd#W1&dkj{JVGRDlMT0Q6ij%+NKIn%D=R3f0{Qp&?PCM&SqhwMie;3REk892= zJz+%4Yd3T@GQpyhB?i~n_KM8>#jduZ7|VC+`^>-F_rO@J+ZcfzMI{F4s;qm0`L1YS zVLEt^tLA$a`PbKgFPzPj`Qf_T99x6=Gk9V}WO}Vr;K{wWtmxQA7B~SR-Kheb|u^n*@NP5=4 z;`D*k6D(BF#C)}vI$gHLS&(O>&-?m`i>$aNeRHmnCVD!9%FizlGv>oi8?N-ss_bdD zu(5_IQ-5tMDjSR^AmL*^sA$0?aO?u4w<^(nbEu5xGC1J&zaW4Wd*~z{ zF|3N20NBP_OIB_vnW2e`YEE%Oh*iURwp90KISDFuNh70$vu?j56w=EbA=!S?8m7HD z3-4*)sG?`dS+Gfp9S1_jcto9_BwG_t8uEz84!@aL&-Iv#2T+RsLHXO$Xzr5dN{V&0 zyq7)4FI0LwlALa?IzGX%X0-WS{>r9R!G3f2FSF{_%BH``FP%3MtBy3*jyRKzk+*dm zhr6jSN9d>=qzk!{tCa~uN1_B>pJ(r~15zS+`PL0h^=KGhUL%0NSHC|{wgHPy4II99QLNvkwuI;-WQ3+X5h>*0tBFxjwI=QCGy{s`hVq_m?#(DqNh|q{$}4n!)wq z@u+Pq+g#8+^n2RdMet|$wcB1MY4EU{SPgJ@^LR@8y_CHN0OM)D6Q`sQS)W$`;B)~N zN5iA}VZNNxmrcz%hJ)U2leruc271=@^lRU=5>c|fxDQ2v0>+lslys8=$9SI)R+-*2 zM}=c!_Jz6MNs<8DS9O^SIshRp$o(DH;<#b-%O{gcpO+!6Fxi?68Xg;w;ypS`=!HeY z)%X`sS2!k)Ssox#vdKV3tD@3XA}DS24k&$7-fJHbk@3QY7r{IJ<58KsYTFX?cl?u< zcV(mTS2LLz$_I4xc5nJayz_AWG?4H^^BbPc)d=V>NXmA2m_Ac0cQy@2zy1D+fE$12 zC|Vb=oxs@^c!Tdzq>u>7GKA;7wcQ9Z1-L-ZN&l18hCTAVhU@FStts{JzL4pU?x9Gm zw!OCqWzBt#(f}V`y8@-U&1@-5vJlSG{UERVHOJ3pChQ!7*!6#x;;K`+HJvChKJg#t zBv*aFR&V)zmnRXfg=xfUoXj-|s_|rjT}Z8|J#VeGA&(WY4a4&kS_<#@f$Map^7%U( z8U2x%^bbEqMS5FsOM_O8NEP%r#ikz`X}TFr&B6JFZttuq6-fngtM5rEsAYanOf=;7 z_h*~Ba;uA3sq{C@Kun=&0g9v(T&o}-vUzIS5?)zc+nV)wvMf){P%y|E;f3YpyD zOBhqZMWhb6XOuz4lwaQ*~y-r0A^uXeUKtFb<^4EV59Sd3|~cBXEWyd1o9|9Z`s`s-jEWuP47&2HcxOtK?& z+&@%WZA?|Andr!Ml|JCO&Bi;7uW;4VP)QJ!=M?LhD3FmGE(U@66kX z+V}}95?e1r(s7~pU-@Qwsck2|!BmpApApA(>~7;Jse`{_VsmR}fHnDz?EZs+0e1+tt0TfS;#SxpXRBZLM#H33Dnd$F}n4)~eP4$dlU&l-hP1nZV$3u%h_ zU4hAh&~J_qz+S(Km0UY3nJ~-Hf|QHh%@z6ofagf*8P=Z8WKR}rNr|(y&gi7hwJ0}S zx8Lo^ksKZOHx1Z+(WCHBt>nem*3#EoLhj2a&zP7C;F1dz9xQdzUR$`iw4O1qbp)6$ zuz(fVu9wo=qJFx62b}Dd%ZT)f1%>7RxPUp=gP44r>36UXef6L=5bVqugsw->h#yAsG8zF6c_JJ* zgh)*%y|sSbxFCTORN&y1Pd0gWl!k`R(+;)OzZSNa9)g^O-o9r7==APPXruGVE?yT- zOCu@A?s4E?-zO8DgK#eU;9hRh+k*7QNikA9izB88Q0|W3Y~d|ZB6yEJp;WkWg?3by z8=3l2K3Ps}Bi@Y3U8s&wOR(aCc`2uk7+!gAg^J&n2t>3s^G>vB zqE<=*JP?Zq&@+F7eiaCL{)Jt)TU&<jom)=M8`^SJ@Mcj(*CSr_`UkaZIchD~WLfaRkdw}2ExJ7bC!Y9lCm@XXR6JDIb8F+o?V2d2Ah1GDmEZR_mpoq<{ZbXn|1JGboz;m@!y?(6%UEjcIK z+59G#1Z_F=e8jh8x1PlI~j@3Y!!4uUQJVcia)ju zqDrbOhu%OF;_VXi*>GM5AX1{xNxdSgiQibpAmr7%hY-Yu0 zWamfEFTu&oI$>vIv!0?1OyfRpu{f`cxAPLMvH*u4mSA+A|=i>t6pyTTt=t zfQ6tG5wk}(+It#zbK*p^-H?IMs-#h{md?zqPCYI|f>>lsb=q^=&c}vcl17R%%!5xS zc*A&uI{Yd(sIj%PXy*cxFrdp}Z5>&vI}I;NRJ}6)9MJy-`l~3cC#!+K;A%(dPLujk z;oQd@SV|R&mG?9yZWBKWoO^T?6)MG%vEU% zshaqnBHv&czRO0a5(&b`1zMx=_35%y?3zX*h^CR`c0c(SV5Ow-I7nstPZ<*>1Dx8U zcWU#QRR@rs=-gwwfeX-?6<@y?l%aSxg77KAy|{;PSH{%s^u z^AdSDJqftj+-dVckh82xOJU9QME%DGNv+q@9<6y*zj0Zs+oqXa7w|U(^vg{CYf3um z2hFc1U!erj44Uwqxx_VY5d_)esqNGssqi10T!|@(NcgmFc9s#&TY8i9cJdZ_$A*lY z)TS7Cjx6}%ED@A2Atd<%?>4z`AnKOP$kI+NLXk?&Hk5JM_Lhk>6c;og)mzYf(L1ZU z5`xC}?74pG0Od5wu?@ev3D@AgRds@im-gKNn{ZmK zPuj~cT{y#Al9UF)8jd>_1vFvOT*k1rVc&aO5yjh0HrCHMfaJ`FE?Mc@GGu?;nRLh@ ze$%VpsafBKTE>?f0){#PCzD_oJx(jw2nF@)*aTV+`(L}NPTahue3Rh{o$DIMyRwUD zC#XUP2B}IwrTbxjw1|lP{r;O_Jwx?S8@vPh@b~{2VN~>_9~+l* z(NnR-b3HD9-m8b}=+Y(6oH#oyQnLMC0=t5--#RWT%E;F_3TA!@Vy?IT)wyX37Y;74(pOMbvB zA;^6fb(?x-U!0vy95%OIE@UwMK;|s{@WC4 zY3!$cYjX6CoTF3ADA(RM+MUC1LyR!t=02OHMBaT3T_<6c7op^oX5nQX_+ z_wjD#WH6}6@jZw7&w|RNpZb1%`n!1czvB=;d zg*h~4EIrIS?u0Uyw9i#clnA{B6?m|Vb>i&_B{V?D)>BgQdwC%#ju*+T1cUC2Co0FE z{*3%RFp_Rz;Qkr)PiXnjb&uc$T_Go@BpNBdV}7zPs|Ncza2_HB$lpwbr#TCFogE2v zJx)VFS1?24wUrbZ;8*eX$PibeZD)xuH9pvR_$fYS_3-glKSy5n+MTF*N$I!a>8>=I zUk0CY^n4@H6v-d_mEdx+)@|4joqBFK68$rHTcDdhxq|^jQLex0*yeXYnp`9oy~^61 zLX+p$%g;wInTFG#Ul~ylJkBjkAh&k^Wc}gj3cUdh=(?Wf-KDcmwmAEQ2GoT!A7|-< zgrQA@C%;Z!qaXakdcU37Zv0HS;^^sk{j(5}%0?PXw(&)fdfpc~Qj3S)KR5;)ol30r zh@@JXkR7BlEe$2T?0T{!yI9~aL@BoD6-pMP#9vo`>c);PKaJQ6mt36mXnUGZyZ z#28r_CywW}BGEYlu_INHG%3ykoL;nC#a;l)GQ<0l;yMGC9T5lPp{HP4-Xy@d5L0H7n9gDAk!DNN$W-7bQ$NMZQ zC3mi~Rs4yz#@W(PW}aQ3lgI>1#dC!VnWNAEe6qTtKIAg(|JfWtb+UROhdj%2u4Iqa ze(J3D?=M{TDkL?#sLnQmDC-6Z+877nxeA1>H5j0;{(V^u7xNh$rCqcIujSy(nnUDo zaO=+{LF6%od!M_BCUWi@Cg~j>MCWhl8)sgUJ@%8LGYxv5H)3L(X!MuSu!*zdVaQ_L zy{bl}YdBBcJ7;mcSPjosQ}~oFo|>JC``CazmLj4C!iXp|CAw;J0BIgjP#1*%_(8n; z`a3yQdSW>01-QbDov)N$aZev#OIY3c;EA|5VQTrLO7dEGDqL%fC^6brk0qGEIS0VT z*7&3>>7&+sMW5XZHaRIWBB(ElP&?ekNiz7;Gcl!aO!nH*!@p{kT|cp8NJtEe@V|WT zB;KW(j$p~aNm&f;c#ZWc@eN=7#|T9^vND=Ec|T#R5Ez2x6JhJFeA^Hmf+8c~eF%FK z;fV3_R3vG~aKBmy{MtBs($}V|)dM@$OilQ%{gLUVSYQzD)Z84T5^aJ8_rnClAwz=E zQpbB;!+Kz~iZ9>3lQH6>(;5fx=eYYg&GCvBDbYM8lwSu>B>L)B!MINi1P2&Be?lfA zjK@-vAujHO@&PF!NS%N?dC)|Hs*MMRjNbbvV zeXwyct+cv#Xbc!7tyylO_{glVct3K`X1N&q*Wd(&FJkhX{wE#hx>D^x%_7ejyIyUn zxfp@4nv*5J;_4%gX}vjQzbdfn;gT10HbaEcb&3XW6>KW3a|Mu87i83!>by&)lwJ^U zc{biPgg^6q2)n!pAz83@?^f||Q1<`tpzONMt=AI(!n(qrk!!7Y92o6H6nnn*m~C{j z3MqQQS3$(BATTZ4%q)a_OOdw_b9X~w;%mV6q6~kF8M$lSL|>48Ao?SiDzIF#q$x~j z<@pjkb=43>VvoF&??U9pe*p_iJCni0-gIAC5Qcbh4nD0_b$*HW>9mTX;0@*@`URM$ zj8jmNo*i)#o1h;l%t48uFpkw3M>NWzr}QI(%mrDejI(JORI=6C`K0s7Zt%h6mBrZV zeAcFFmK5Hj3}28Bk(>?sD~8HOe3;M@a;4pKI}SYcON~R&67u!jeQc*?&8m?0Db{f>AEp2)k!oop zn`o>D_vZ;d><1MDiX<+aHsvn`)Vo+d)SQU}`KdTTS6Qcn1Gwufny;l$n;M+U`*Eq3mb3|Dq{*)vWs)T$0{Z)_ z{$jP&r!Kz0l)|8xZmg-{;*7t=-;{_M?B^7hDY#N3N#nP`-%%hYPEj`kVMC!X3M%Gk z6v{|#7l^N`Wv|YKqnH+F-g`!pGQ-Zn!;q7c6RSVV{!I93+@3{jtiF0|a@bItiD~Zd z)a(*SV@Ah^ByzCOp1UY|zz4WN~k?<5@=C!nwY*upc?5xQPiP_Ss zCPMo(S?ocsKDlRaWX^F+?9?d5#l5GXIy#yQ(%!EU8en2f%gmnw9(C=wkIN`SFM;W% z9hT;rCNQ27o1dQYE{gR@k9fLS^{|oVJahJgD6+8S2pRF`W?1syoiNi(7kNg4zHKi! zeI?8Acw@Ju(2*^=3V9AJ|2-CTaEGzd8R+_Nc?9pj%OiVP^|MdD4w2PQXV~ zZ}U*YuF)?M*xOHMGRj*WXWkZV^cnWR;;LIwXG-_9UEMpJOiErXO81wOySvPT#mEZO z%w!MjA9zNlJfdv@r*|asH`hheo!caf6_V4;qzDtR1eXRj z%>3o*ZxmE{N}tSjBqCl&b_>SF9ynW!5kwEEb8?BX7!zPhu|Vudl6W^M3Cy5eTsCl; zs9vpjQ6fsa6Z7I}tL^r2GJUCK zc(QlsSc<~2e@dIHipAIwaOM-NfFfU{UC9e7#w^sl(%9mnF!zme5Ygne)+l`oTMh48DFXWhWMH%!;rtj_$jJt*lO#LHz ze8Hswp5~3QTb_af&&gS#DAHIkUO|f+kfkf#6;USOQr4(34*#0#kL={T=BfIX)4^q0oHB9V z--sn07A#U%v<6w;AwxXO&7f~Cv$h{+b40CS|LpPFXyhd3OdgnDCGbkzK9ESaIvd zBkF$qt5i~1g)?N3-}i?xh1~8vr(S2{L??a`x}vnvmqO>p^b7Dkf7LB-1G3h?@$cM% zv88ni_L0)}ny36YWm@7-IcnRm<8p8nl@p9C=fdNc-hDQi=d5VJmf;3A<3z{uQmg&K z2IyJhIy@Jr7}_#dWsf>Y0&-XklMUw%qGD@K9AeDgq!XVl zY-g1?+hx_9(tpU*KlAtN))r^p@~B@^exYq|le%jUuHxNHc2Qwo%GezT7mDdslMg=@ zD_X{+#WM5amj&+E?M;=*gVAkYr%js5;JC7y8iAS`6%}=fQyl@2h#NZG({$8A-o{e+ zSTj^H#U;GBjV=dAW0O*ne$Z<3wD9xn?01LX5xA-~jo%sH=+`C&87-_u>zJC4FytA{ zEG0iQ5~x;Fa=)45tE<~xzRORMo22@O^JYrNRH95!A2up(nu?#6$PXQ5)vXP`tG@(=Xj6b zU;MSPUDx$J&rhA_Fs1F`RY4eXFt`-R#ar;_Pznm zrR-CV27>(7esBbQj!Ay5@jFc}uVLfcNR4f0BuU?|wUP{oM%@v9wIkn=AF}mVKRd=Oaxi~ed z0xVKUH7TBn0#K=~$c`~fLJrzIf8SG-I2p;zLEZKnn6WXkr zq-+uNasx_%)3Pk~6mnr6_^S7zDCtdYE%io3(mwdW)2{7h<(rr5*AH`uu z-hy!-JsK@D#(N|faCd$epo0I3eR?AM>NO%a4T{bR{}k#oIz6s^Tbu;Hf^PYofts_6 zxCf7+YX7k7ajKO0B3fm!r#yOV>rO^q$=Ei4-58h_>Z+Dvo4;U2sU6FOdihcm<<4W*#oVp_rNWWZPCRm4i-IKmR=m`Q|Qsw%j?nXRDmT`Q=Y6Q(nX7 z%-7@hZ^Q4UJN>2l_`@kSMw`WJY-tEN0~I-JPkEH&5KJ4XFY+It%<*p=i}z_{DePLo zHPVdWC=G76%O1OUH8@x4%q5%mVboY`9m!gksyWh_svdJGaRB_*4@=k`0txu1L!!uG8+S(LIQje|;Jr z=lYr=JyqMlLs_5_e@_C63d2}x(VOePk>xX4n7iaOez#rTRgVm4%&l)@kSwY*YId}C zO2=LUp-Rw-&Wbx>p&7!Yj-F1aiL5Y`6-pE+truZ(&niw^d)5|w%ajQ1i4qjle+7OZ z61*o1kqZsyl;GXM28QzpeqK zaPOJJQa#q|+t`=CarI9z9EpmcPF9zgn<&38e-wM-87)3HF)z3`45)Mwzj4QdnY!n* z6J?P$A?T`fwP*OEkmuh|_NQuO{-OI9)KY-|xjtg;iwI@8JRX1e*#YtCCx_#ONuX$9 zd{z*^`HtkzpFcfSfBy0AIbHntbM2pNww@m|`ac8z203>AWhc9+3q@#bo^*;YpY8|z z{=xfK$uImc=F{Kr(zd6o-i;>kfu60~gYryE)Ew{Sni*!AtO5-K65QR$fMYi9ZeOiE z*iSdMcj=T|T*9xf2JgcNnnV26KwtFoFMhr>JiW_L3w7dRM0-D5AMxiC{xsF-wT*jU zNQ(aypPZbT2bUbz3;B#MElvvtvg*)dwNys|kHX2q#jYr#Z=%;_zHlC$^{_{M=jySF zDADA#TEsb8e=KRM>*mVZ-Rg`z5H*Z4P@nAhHK}4)F!6BPF(RP6^XwC}_#nF7d%|FK zdX`(NuRbk;cK@eC!wOYLEw%Z5nb z7>L@Dc_q`}z^5VYN8IxO1=yIRqTZNlE>_KzjyuvP`qh}p(AZD+w6^1?6v8YyscDWr zw!fN>^rV6K|RzqJ)LW| z#OuiA2o?EHX~!6I$9+tUKAJSocz~FD$-2$hCS1+;kebrgDO!Hh^6TDU1-@g5K8I@@ zk<+lJ2?!&O53SYt&b6!GsLjMPMP&~vJcNh`Ax*NRFQ80naXh^I!9e^6}U z;9TlS5**i6&N5Ga#H%)%>r^r%GEXs<3|xM`Ree=0?cA9p-S-o~()zOF*Ws~+m! z#o80oI{}~m@Ng=9(}sbiqCMtAz_hiV0WMBTeoRp?Ht7;KIfb(y=}1`Q#a zo_ZoOPdmpFllF3(i78YK2rbZ{Or0NrF_?Y5EuZ5pF%A6%V)o=yxXU26LTR8>2`Wn4 zl2G5e_--(jtgjten96iPX)pt}#BWWJ0{FQj-BsERb+z@l+#v4Z^)jK_7RiPw)|0O( zU5zZp8H^YVT`9~cP>^!t@=W#>#SW#7@g7EoTL+X&L4SoqG~#YdX- zOE7sxsqlm*l|s|}9FRCF%gx;%Gv3e3ORD#iUm$6W{~fD=aPs8S?0?u@r>WAU%Z|pV z=AuXc0Q})kGnC499%x221HNj7Q}?4}zq;DzQqhR>I4A!7&1cHOi-GjvtyT!U>+CH;yLythy7TKPz>^BxV*{d3iTu4zg$arkEy;RL_%?Tdd+!>5;osrqT!=(Ba%qqWYokBRutn}jyHVRq$>KNVy)+R5;npda1MLuZTa#x6vfEG3aQWSRNx(( z-O`p(P47$-&$%Lxib5=QR@c9RVY|6cmPywWFN%3z(IJpdM95Z%LzFeJjImb-RK9Don)-msbpi?A2EENSIPG#c4Al2NX%eX za4V#t)gPvR5o@N36(x2XxuNFidLq`gY|JAEkVSD41eNqV_}D>HMvfv^Z|+JKk;iCsd&*Yi+Gjf z2v^kr&}Dn<2_174hZtVdI-PM{ZuVAseTa;-Jo~t(@Vi62es4B$8pM$ zFb&1tAN=10s9ZU%Zq=MHChjV3R)oBw&-y|+_TI6@Bw#Gx_siz_#qr6HKDp|BO?Tee@5H-tGdsahU@Nix!ThwTQ>C&ptso_uHT>k8ue zG6TM=eE45dABH$e>@K5w9E!SqMaV%TuG=sbL4ez&HCbER=>v+-uL!$&ln6UZ3i>_2 zJ%rtfUy^#m_QUR`ahg5W=~^^e9>HP%e$_-%e||`%{PvrQNqXncDf_Q=lP9N=c6%ZM zgG00*KP8V$DtQ0NDe3x$cFTozsc&^IT@m^DD}^8@Npd~T_eze>oplf?+O z?tOD#`D28d=?gxmu_~>rqLA!G?Qzv>-ETkS!s?Bgv)Fg^#WXTbJ9^toJ%E^radf4A zSe688`TlcnB!&hW=tRkZ$&E9bm#fE%>V)YN!z0o!4o4myVPMWO6Aot{Y4OA-URWqxg5$Bot=fYQWNvb(g{-E+|ezs04(x@WhXH(KJ;eK2F z{x_C|H(Ia*Zs)R8P;4G0rp=GJX{l z>Sky(eiiz4G`w>AE?-KlsnVFwl(E8Ih7QHueZkjAlW=c+!E})6yJXnY7W=#mDWB16 z3RI;8M8$Bzi)j;lAUj+{?U%qH9%KaCoTKzV5|_!!A<=`pjeM1yq4hvDSceo`e9>G>hZEosZQj(t0 zsJYy&{Go}Qzpp&RXzosL_2UI{MFt=gW;>)s*$}`bC;qtxxL~8yS_y z7G>*UPr3cHjTovQY1sy_Il39SvN;pIt@TP|2^|!766tD4^mnB8%a%KQx(QZ;99(rf zpL2mvSCzVh%W16(C_Q`*~b4b|X62@7$ZKuLluAfRcEIk*l z>1qnsz57*4!ma0_?tL6L!f`SF112&Jyy*I{oLms1VB1kiJoJJS1X_qKrreRP|Jp2e zRFKhWA^u*;IiCHy^W3-UstkK{fQ4UM)Yz4oKg?QD9)0A zlq<#CWT8n`W6 zWRnjNoE&eiodl-qJKHhlq&bdu?%4h)c;J~k%rqzSo^3C~irLI&rUPW{?=EWMp%Q1R zk#Zt39O8~Zzo`0XI{8u$m}5sj*1Y-IGe%xEO+{OV)hEKyY=m?0b!Ni@S)7mK-LZFK zhU@px->}-O)btm=T9>|Cn;wj=~E!C&>n&KZ$N85Ruu)(>P((GhtGa{mQ=_?n% zpWfhZZ-Y%h{_zFTT+z`orcZ+?cKeo}*Hr!ZdXzVIk}-4s>zB>{b!M5-BHodgf4I}? z{$b$>MFUKTG1tLqL79_@V(yau{(K&IQ-9jTDm%q|$3>?8YldY;^yBY>0#x5bE`LWUKfXMpM z(GXJd#@3{6P4z^_SMkDqVbr=k46c6EeTS#!&ZK*w7@oFJ`x z$XZv&p>245jb@EzbS>i{X$%3{E3h>4KR_i|{ynlEVPK`kc=Mr&_~DD*(4C@A z$6O;odl_~$*j#s6Lr~lKupOs)x7d)aIE4z^oG(?h-oTJI(~)g1?fY&^vD0yk>OqW1 z-Wzkrg7m?C=2qv4oHv=~!$z7GCfJFr8v|zyRx{anw)D-eVk_oT`#@;zqMwz8*rRDH zm>I#mB`f8{>|D@{Z0wbEnmQCcZ3mW&%@M zb~~yV5(5XYeFE;4rw9@7VKW<2n3p6k<&Y8=y5mhV6bE8isiGT@Yr5mB#>fm7heyID zIeM(ZC3$s(DZ~P_yqxZ5hMY2koq8QzMGc15l?PgTcxn{G+=kMLQ5PS7S@nG1=J)#~ zlSupVR#Skl#-iWR$iB%M^p6P~{$6MDB_DcyVtxjObK^G!m zjJ@o>HiC}6XUG>R(}pB+UWt8H!vX3;ryOv~w56Ixc+!sAoLyTp?ayo1b9$=wH1j+V z7adJtd?NsQ7X|9cJn@Q*#cRbswf$j+Q3W`klIu)Xs*e2rtTH)6 zT9=b}&9wi;YLXFtx$|iwsR`h;OhBHNxip9Gk$YEbNklK%Ly;*?ip@wsyJ2pWUHW=} zP(LSr|A6umna(xZtj_yVO%Ek9__pk>8K%CV|40ZljXjw0j3BYU?tE43D1Y9})z0#h z4VS|S+)JGFP^{7oHxAW6Z!1CiX513 zQ?&@+3L#jL*`Ol4+)Wh4e}*%(oL^oQgJOQJZ!#fnH>}=nFXUNflad+0fv7%mb(sta zaRsx9t#G1YB}2+l3|zEno-u9xIROe;fzw=ZF{~)wSSPqfbY=ch!Hj%2!?tH#V@mbr zP!-3UA!-Jj&oARgdG=*fv7%i!%0*PBBIBF6rF%a;pKkc!juVebd`K6! z`kYppss8>op8dMyMo-H5CEGeJ4cnXIMh z^;jj;bY`%nS2jJjot-y<>CqHi2=(^-z(_1kp3-k%Je-vbD9y>r)e_N^==nJy4I_3l zO;_y&S-GcIj(C`9PMLc%6ysmGUZEmFIiBK%T732l-LfSup}otFt9VB0Lp)%gEK>i- z>(fM7^CuN>EEV**@dsJk+REHpFTqS1B#CRW#1{$V@^m}pIT4amzDK*VR!h1WRH~FN zD{T?6d^}s<$Uc$>)7dtZ&JlW0x)V;1{V2jv|Ot8z?xi{IBhT&xlCcMoIL zc296U{zjqkm(PR!%;M9+EvKh)jxnK$J``=edoR?wA2(&TQ9pL={C#K*vxdIBO8D}U zs`3rx+zP{{=}5lpqE2!jyCl9 zz;`>?=o+|&z837Bd`*)p`th&a_m0LuBRYiS6_2BAFGt8OEAODg26C;AoKG!IObebT z=Myg~>~l*FEZhc(K~YZ&K;`h37Y{!8LVQvL-+%e4AupPX~VN<&Z~TobxXuB$pHl(1IY3mKf%9~SWQQ%aXE zNG`_RE)EmhS`6P8%>G5`iM9Aq@xznAR9Gh*&OwWnWsQorT$}hC!yfnlCgV4lk?CJv zjjR4d-Z9JM&5>FseZ78I)X)_FgWPY3h6*j6D)%z;)w6<$PBRFJEDt#P*IM_)n>=6P>`3i!48{x*c6e$dz+^)85`Lpdz zWfExXFP^NSd|$Wy|WmJf9;E6>8Uhi?|{Qk>68q7#0~`vHcNk=8Dao)+}OKOI_(woJu*2 zwJJ26d$gY+%6lu%kP|4={P2z`uSV=-)$Pq6og^Lqe5c@X(nvV=Mn?Q^sU0@|vfv;* z{I5X3mvRbRSZIeZ>pyZm-j|;n$w=iwdN2T+)1E9|L`FZK|~6# zi@4g`eYjm<5I;`?aq_v#o9J#Zw>yCQ$R>3P2RjRl=DpJ_SE>E@A>rlyUpb0Bda2*83C4V08x_+~xwEZtI& zbhnx)G)B(-Ocq6a{+9}@Fs5QKCT4jhPJzp5-4g^y{+kXbUY-nnNQG{$x7BJH`6g6=y7S~+vbB-I8P&Hv zBQi9t5vh>-IHbISIW|>p0k%3nd-Fa<@%#?OxF0mkyBtYhzdva$Wff9=fxXI$fLhtG z!Xtw%J`_LO+^5M_Vz-iOxNy`DCnM*tXrv!mi=jdX^fghTKYCrwWnYcG2;^dvS=Vnq-V$Wg$-=)AQe55o4%v*9gD|B1zQ-X8k6z)Myd@C_|0U-;yRUjuRlecCtF}@h8 z*|+51aD8*aUXo}DS6~y30MZfXvHwfRAV-cRBfxK9FUgCh!N31KGLoi&U)2UuLjf5T zFm!+;0;8QDOj4Q{NfxYCW8P-_#D~JdxFd6I%A$Op*_mkpE%{KKF#t$VRa(g)bTNNP z6;~s4p}3k83MLynvu#3)~7J(!datH7@NsQo_(4v`BKnN)$tg65edSl zCb1$BcNY%Ilg&uB1bNoNu#T9xSRoxs9LM0BE)9o~xh)6dch=(XkkAFm?PiNrv_55# zk71ai0Mig9d<)&b@C-(XNxpj9^_vvEX58K{+wb>$bRBV0tQU?h5? z_`vVHBC)z-&UN`+B5giNqv>ISel&@7)bIwYtG)TVTjpSHtD#%wV%lkSqHu1Vq$YM} z^*+Rb*S=hl<6>%xXIN;?A=c-~S2@{>Jh&!H23E`9qX%dXQuo;?!&00Q;?u=2CGOJaOLxu`lU+wfb6Ynw7CeJCs;j0VC2n7TcU#o47cOSWf@z2x( zmXvNkCR-qk6-cStEkXf_Z%Kf23d&EzQAmA?`#ycbnk9yE0j1PA>ZU0L6c!eO!jl(s z8gODNW9bVl`tP8FFq|9JC-bY2Sycq_lPOxh(}Z&~?MSl_28iH!h3 zv&*9c*}sqY2MU6fj7#tuQ)8Uc$Ac;=kg<2FXGE14&R zahFFtmRzCnCMoh!FY+p;QFkkJ=Lq$ngya_v=xLxUi5GHxKGNKY_JHrSj_)PVy6)G* zIBH->_iF13es6uN(>Q4A``?ONi%$d>%!$lYAWvpH--&~*NHRR+8~UL{*K@u%X0F#% zxQ2HRotexfUAw$|kC{@$otioiQsiyzr5qGDQc1D)#qxNp`iI@h0Vrp3CD+bd26O@| zqrTYwU2u0ELwL6Gl=EO{Y#@uRJpdxa#}b$d)xg-jC5QOaX96lYFu#~9(ZQ$cei#5c z7DAkt*|PP5v=X2llq>6IBQ)JP*CS5&Jb{@+=a^Jz1aY;2rr6vmX)N|mt|d&tc#NpE(i)(=nj${>LQzZ{D~c+Q(5rkQgy?MFmUL1%rml z%`Ea0VpgGhj7iiyu?!)V_3nx?s`PP5GbtLcbTiM48xh+bVyQIl5tx79>e3Wtn^v+?I*V6swx zSr9sNk!v6F+$U4mfGizgI-L(U&k5t;L#27zJG3RDmCb02XB)CqQ(kaD%vTYtmUvb6`(5-7%YauAL4*$Gax&)7&=*Jh@khVZr_%qNT6n`KBG$-!^zm;NRfTaC z1q!h~rnYgUoPWHH$UmIMxnCt*BXtw-d2*neD9V59+CAJOlNsnQ#MhI z)YlK~7wezz$MoK=&^jOQE}ydj##Ckl(47(1Bp6|^WD!OaT1gBIK~10-9|KfP049?= zj*_f)fVq~bWg3guJBpqj^{D$SK2lJHZ6q;vz$%MqK|W(o%$y8O_}X^1Cp6}g1&<}2 z_Wv?~7n&oWkJe&i7q*}ZFeAUtUQG)UtT0HIBTyk64qNzPv6`8l$|~rFb6elrCw?K-ZXFO_#vBpZvYeyZ3QD z_X}Nj=1AkL(mlwnubFpepad)#r3UF>^h?#6b!Q-{Jd1`;ux@mG&k0 zeg9sg+#_h#Vx_MbZ8dPGc}K70Ii`}V+UNk`{3x^I!`r=@Ls!xGk0mm_=S-<9s2;S}zW&w?kz>sY?b9!PTSW7Ggy~ zEU~Hfl)4dBEn(+kI%L%%`4iOUo+SYDI*g4F-<#|$pFpT*QYSce@!V4_&Sxza6JaA> z;a{U=NhH>!Ja?LY?tQA@jg2D=NA^S2)#R9mMbc4qx!@ zI#fFQK6?Ak^e;s}JovDp=IU1tRT+(X=8_wDx<^qZ;t+L~LbBjNX}$0q2r?Y%Emp>H-u-^lOZe58|2B%Jf4-~t{k<09S!1&?dJ_3p zeU;6B@KcZa@?8F^8eY!R-Y2y_G*z>xQk*5f5JR-EWzIHePtNa|4noUK3xMAwZ4}I< zUWDMmSL^S_^TzvquRz#X6R?=;YEn;9fJ!3G;5<_R&&<0SV?J;J$cVjmWe!8ALvtlhosq6k9-&DyavNyvo1?@Tn!3_NTxS6X@zNnwjKaGanqlU&rq z4nRZ7atVT4Yfgqgk2uI=Mzaxq1bso4o-1Xg_j#h9|BkuP`}x?95)H!-eM0(Bf>w={ z@}Nc9t%}F*lkL&IWJqj;(kvj_GJXFp?AMuH@qul9WJW;tOl#`Nyxun>dzk%VG1_Bg zUVIFf-cV$0=gTqSK!eR+8X00C9yl$=5DWLl7zlvXc7$EuxYM-#9_4KaSc{{*|M|Iz zEwSI##~2wsXx-+$CfSr2xvz_Fyr>;DaU2$u#w~ZN=60urt0?BO*~0Q z*dIO~$Jd<^p5&GJAA0_`8@7Z3cT9nMeo44QET8(G&`B~KZ20XZ`G3d`M$00X4pOya0PQL@GAhv0niF%c6tGcScM21$DR_c6zHzI<1AtmBx( zbCigwdEVpA(a`r>wy8(2SA%dl4+ItBT3kBKOmc}9`hD2 zlkQQ3lFxvfTgfV2VgEqRqR<=?Waaku2`F-?-J;ugo``eZUuc5wnA_kh&DKN=TFPfp zSXIG?exVe|_>hW1p%GsH#!B;^UD^&MAUM19j!Zcr3fem-uuWPh5{@LNH?(&%1{q3B z0?cSj8GY$nCGIjNQ%MNd3-kGsr!k+AW<1!`HW3VE@uSp2^{Hw@_YxDe8SY?(mlmiyd$E>f%az^ZU&aTm6vo>I>DxGk+bq;l_W=0=nuH8Bd?`wgyslanz`h|0C=!;AuD-r)jvr4(`zau?UA`*_x zT;8TUgtqo5oQS2eMuWq^1!8$$5}h`sMey+78U?X%ICe>TQD`RV@j~wNw4*BHsqr zxu-H%%*Rdbvkq5Q4ou^UX0kyFA}|lE=|Jek&h2djlX@uUfNwm8918in=hAI%g5+fJ zp>IvZ3s7gk1LvtYi;O~0^?k#tZor!D2MWnm}FO~eqj=4j@4t?sxoDWlRfEr>)<| zDABU^HX$egWTk{W z-|bt@DZvdzpI=1frLW7lUJp%$#{bt4PW`%+oD5zPY2@R>9D6&u65(fJdfc4&IMPI1GnZ5T9xkvQQwa*@fz8on!SLvGJSe{r? zET5pnG3w-omY1T~x>`azq9R2RJ6m^w-YR`995wBPA!Iy`p+}@NAlxqZmWd{d%ooOL zBz0@{q7oc$wD3)rm5=2TGi^#h3kjHhh_NpyN5t8Gjy#Ak^do+pLd8c`x(X9CRw979 zQ{Bu(y7zhg}#^;7SnT=iG{Q}7V3!IF;YNGJZ(A4bkA!?RaDAw`gDo~ zhK3FNCL?|)A*$yyOJOPgYaOqTPviR9_6(Gq&j%Ebe70MfX9rs}FY=Kvq=~s# zS+he!VNGy@r8S|sp=SqL3iuRi3Qb$%H5aapJfmnQkXu|^g&s~mzQ|y--LpvLP6l)w z^?dgX*&&GmW^d^CdZ=H}?V%mEXiA*q@}E)XWqsC~b7Y$1=Q?Xkaa{yj7aTmgvnRg_9N^4;%>N)7f2+j0+ANzlHAU^$dX7lsM zhJtFQ*XNIUK{rSK&{y?I31znyM-sjND07{%4kQsF#_YI$USP^Bw1h|DduE5l(Web_@ywYL|vG|g}|f=Ae{ z>Xj~H#E4NP1Qd5sKm~5K=mtO`a*vd>;F;01UL#(3HkMmJ2-(Cpy}8<7OAUhtObrIe zU;>p$$1xU~?Mz$6l#5(qN)5v&N(F<^mI2|OMH2*zilICK00lsWDgu8|fG^UkjhN8l zd)9V7drrWsL`($eb>zsi_bt(fBiT|9@^pEzfFr2b>K^F6C--DnbKzF&J2n?I#d}>( zcrVc@rNK1(uH(YP&oWt@3yZ$*=lOt)>~Pq;V}-D4YtQbIp?v~ok8+*Dg4pNKoCixz zTU{w9c{~XA|p{9ya*I+{+W67K~ItAY*~kqY9Zd=$s&GFUK_q%Kr9ljJPwd)bLgxqV4mD~E1c^#Ap8+#wcm?CzD zfaS=UmN-rS^7{%gM2?jrZ(a#%k`;d^RC25JJ70`re*|~#8v13;)BdVdT&`*xlItZV zffxtvoLe}mJfT>cj+E=>DhW>X1yGY=}F z$rV2=1irW8Z|h*YT5vKjD3!Z7PkbTnYM-rzXv5_z(r2$FdcWEiXURxyvFH&9LID;R zyb$(JtxXF0owFpQS74Ecy1qv@1g%F$cQx^Bb_g1^rb`@RRW!lreMfSj~V9d_tTkyzl$oYo~lFC;nVjxZ)Y_5f{W+>fMB}0^-I;*AL$7K^x zEuW-&S0-QG(Jq1I5VdADDW2?!fwyh1rn0^o3749Wu=tb0Aw11L9YVeb#=UYOa)OJ^ zdIInZBqw$m+TI-L{%?LaMy%<5TfPzdCU8c91NP7_P+YYjF+MirJgtnGhX_efYes)) zI^dx+|Hm^S|Dt8ukHd<}m0>VvQ_iHk`r*zuV?kHH89sFc(qA_4j8%MOJDHw}LjNxU z6^Flk6|i2@%~sOi;ubE<6&&U2&_;9nS)$jGfUS2v^0C!f{WG}*O*kdwA}DYhOldth zuNY=K5Ze7nw*GFOpo}E%55gF$uGIj48x1Lt+LmsA%`qP`zB$A z;VU${wB@;cIXh;w2m$}A2!y@%X@t*##D(txK|7RVL0JFrt|+7@{6)F~85^kxmaK3n zio?95!%|L1nAM7*p2NWNuf3y&c_|Svv!%LcAvTkoMD`Ri9~$p`_B$ifUB`7ScAxM@ z0grDF<+AO#e??w|U)9aRcyn&~sz9#R+dBx}0^?-WLa}xWlQpGNqR86A=#orLs4+G8 za1VTFxylT_#U?qHPZ;3cr4vVd?hayJzmeN;wS83GgW9NLx%c!=6Bcv?Jurz#x^gTwb@eu#ra)IQGF z3_xiGWQU;0@K!J9>DPqHZB7N2i~|x}0L=B^q|pn?eM!PY0VUI?&E9#ULso7kf>vr^ z!brDPn-%8(5mad-uZ>))h^%78=yUoO?yh^(q6)^SKgfISU(T0ScbbpmkO2zM#hNtD z-0HqS++L$N7u-I4iN_EOIb?-ZV?_OtgyR887JKT~mkUvCz#(9HfvGurb z;5s=^m4Saa!P^HikMC48dKYuY?HA3*a(j6rvz;k^Eq4(-5q-qy-AXn89myGU5J4&b z`6wO_%uiSXpl8Q8%tvyh)_yWq{zHvM&hI(OflE4|LB*sP#pC*Z=;`Rx_SUcRzl4ZU z`S6x$XI(!8hNU&1Lq@cUI1xnASRkLj{X^tuvjhz4Y#!!AX-$yRJ&K4d_=ICKRS9a- zAaoMfkJ;Nm5T0}xJO9Y=Xm2%!+P+`mbYN5J{4ngdbxjx{0?;Z(jUoX@vD zRYr8#jsUEQ;gqiSi-q1vn5=l8;Kw|tA0roPWH`X>eGlO~F&Brk8}vnV-H5KY#Dq6J zgw9=qg(XjzO9?F8cc;}D{@g!UJo=3T9-OyPtBeaF904-4{`a3VWYK?5{x7Ux27Ag& zyGCAqRv^P|_6Y}09VDc^w3LGt!dG)t+>$Lu6UUswvkcsbf<;dy$S$N}Ywr*%_`fP(BA%C|chu2ind| z*Pt1o5K1brC-Wl>Cm(6+0NH{0xt9dDM``@l03}2_bcK8{+g>j@mGx1ET{^|wMdEIk z2-wFb-cnvl0Ho_aPqCq_Z9pZe3xMQUUxi}k`CNhh^Vdd%Lqn3$^79TtR`LtWp#!|Q z!+G7v_Hn-OI#i|zWAKu&GFnj!VI-080_td#VPx+m&zQ_uZIoDbPck7>C?NBRk+2z> zRG!2-0TXNCHvQ75j~qgq&H+*Y8QUkI+j_14h^>=WXX-y$_C{VA+=Cb)BWoxhSm?Us zcG@Xf#kC}-w1gRiUeaAY`U4Y9lgc1{ZlWyWzXU> z@6NCToV&T?1Vz^npY1aMl4Sf>c;x z;Cw#GYp}&|`v$3J&6p_;)`X^KgBAz}$&?mp-;zCmV508Azs*q72m_^hcVqzUZ1 zTeF?l>Rnc@Mt4t`kdHXqmDU8f+Rv#GBy$!px8TW~gtVW_8;*vj(d+>hBZNhCJ1?0L z>P6b`Q~8P>1lo^Xh)sWBsFXRC2_%q}1vB{LY9qs&M6r#6dGfrL$a8}de9D84a3fe` z8c6Ns@lkZj|FQB3R*m~EY2n!wolCRMJ;=h8FEJ#a)-V=+H4u1VsA%Z@M%9%-Nj=Q+ zumk5nSB`@0Dl}6e3xrJEiBcf-qs59^>T)(sM-;NqM>niE7%d3NnI(`<^xV9-NzZ92 z4S!cBD^ZRrP^Y4HxZ3 z0aA6m5E!rl_3qv3Y9C@|;_0jZ z#n$%+&wq_6ovhF3e(DP$%X_q@8So1ckBPYoR%SKD{KxaddO6F1{RxMpPox5db$-FG zS(1Q>R`7cMh@)O4TPqJ?j8I&ERt>ZrV->7zECz9V^_}NO)|fRe%(G$58ed91ZOeah z_(KX6c0W?o?q~ph$FJoXsCAEb;k<_sPUs5vXJQ@iE}JVfhEWkPhk$XcQRK$H3fYIU zZ7Y%S`xS{5!aBl>1hE)r$)T#7d-Zk)EWFsaGZ*j_HNuEq_4omR8Y5DfT1hc&znLpV z2!kMot28EY)rx$ElT5Y~rwv+=)5^3;g+Ti*&DYzSeB(5q z-Y`2(6M&;rN)E(i@0q_qyD|Kk_v3m9k<9E?tCdlo4FW2nrHjEia{g|U#l3z|^DSWJ`59w1m3axT?YS?=D$|f{ zYPy?4z7_3k+z;$vESBXnB*7Ar4Z3gtQ@RQz_&qx%Jmmv@)|q|k&D{u?VLumtLt3df zf6h)RMfjhkR0hWP@p^ZB>!F%JDQK*iU>J+Mup}Wrwc|70voLX^uGaUsICqKv|1ovm z;cUlU|2IPI9kce16{}`z?^sFfQ88<^D2k%Qrgo56MG0anrK+}CrHEFkqV{Sjy0q%| zz3=DwUDxA}{O6MR=5x;bywB^L5451W+9sPY6U~O)9{4oIOG>IU%X4ZyrwocQ(2Cv_ zN0sP-p3i(6Yc6{3K2=U0lqo$NP!=84#P!U>$&Gid`NFJe^Ch)qE>}hI8;gb0PR`sg zce(3`hi>^R4B3tBfK}lt7N{BnQjsp*&sJ0vF#mIMd=3Aoo8d$-bwqx>A9vBSweAgWi!?u*$6D zv^Idb6$0oWQ z`%YRtmz_4m3+R?m+L6{jUIp7h=Hmz#<{UUYRkSOiz6gFhKG%EsHYtIuDO$+9IF?Jr z?9ssfELUCE2YlGxg9jc`0IHpCiDfWCKzW^^V3yc2i;xAUeT77&ISjOYeOWS?ikCw7UbPSa#jE%x0p}uW@w?Z9l*FokIFxrRlaC=tY*g8z!%UOb_G3 z;2O?~RK)rMRWq#Xt^1r^a^(a6y~X1b&U>{#<>YuA_wRUMYH8r_=YD$P)xWiP|HXf@ z-)m#|*Nd`Ohb)g@#ot?vWMy27yf!SFId0yRbn7Ya#fYINQ}RW(cl!Q^VFg^F zeM{l={JTnp#>9S>e=v#o1M%m45o=O>Meb(Iyidr-eyM*LwGpanW!~ofG%h9O9V@-_ zds+`8%lS%AIkYCzzL!AVa07>D#ZdEfWXJgfY{k_4J;?McN5vMe`z^f;!Y3F~6FfDK z=WAggKH)*ti8~^s5CJew+c7(-fom%IrPKixg4FK|@u&HA*}NA>5~XHr|ARHFc%jZ2 z-Igue{wTO6ue#t(GqPHF-%q=s<2(aWkxpf8mO}WByG4BSr?ey1GJaQ40G!GKDgLuC zAo;R5dz7sy-mUJyKsyJv%#{A+SxnnzO=iUAtKp!> z(#bCRGM{{(q3gkA`}w5Cp+Hh6vH|S2V7TS*ncX`P_17+=Z~KJ>tA>h;0%m2qs`#tnnZuA z6^-PTWr!zuTf2yj{AwVw&R1e+HbMq(d&7-dP`vpp5?g$0*c%Oa6Dtj>R)Ooe<4QUS z`=90?(c{U0_>1AHwsfhFmfzX$?LFW{0Aub?1~4ofgwnb=oB7a6vblKCH&5BD47_t3 zZ|wU)mA7%9>ba^di#YkW5u5g##kyS+Lj zvE}NKOm=U1BPsF!RWjFZ@m{@3gRg?K2DQVkb`-Uo!jNlY%=c#X zZs(+7J$c<(-Df{ICJ(l8OAEn@Skd#ChM4Qlw`%i;+1NblJwbW4H zxs9KY6hPmJ1GREh;3R_#mF#aguN^m!7io zw#S`fRj_9FLwc2aYlarPAm>T( zb^CrkTLVO^q%)<{Cj7&$3_JuXd!y$5_OpPuKT6c0;ZWF+T<1?}{YO8wuE_DdLf?9B zQ_3EsGlPqo+zwbquYLaz!nS~Xif>}3=JGXuD`bB^PhN916?~}P=8aGhR8KW;p|5}2 z;`S9BWF?>+^Sr>VpEE!T|X`uUpq{O%fn z_y*&f^k5l!+wCl*%k4Q+$g?_asiG_;JJJT53Nvgcl|7f)qnZJ85(yT8VoCwr3cyb{ z-uwb!{j$E|`doHlCC>f@4xQ31%EyzplvOTzMQ*!%Y@HBQVQma_{<{8x))?p_1nb?q zb)Zgb?Wl*nh`<&{66dYg6yvIjNfV`wN7?_l1w5L&#$($&z;n!(>=Zz8Bs7YnF@BO% zZ&Ny||HJzl!MTo$5I&)2d3prD_*}Y5`=`UTyZQzZ*Zdl%XcY8i$a?4;)YliuzP8#Q z$ItJgd{sLGcy<3S2hN}HktS5enNtV-vD|rst4IPKti8GTukV*r-If)u{rAZozB~ZbC@sy6 zhHp`BVzRH!vW)g)OQOybtA(ZZfKLuKD|K?pycivx? zkSNy{VDGBD^{y6q#%qp6Nq#-!@-bC0>14)=$y@3_ST>GOVl6diKMCM2v~B`WfQkSw zX$9qv#Vhy$D!rJ%NOox%!;*tYTY-4?z( zGKb?)EOt}IYj=C>g4+`P=%*Hgot7*E<#-{R$+1I3>G5uk+;36AHY_x4nO&D=!{U+Z{W{S9%Dp zm~sr^pq(wx#xe{IEX6+3AN# zM_A+C3MzzYAB}L{-y|u&@;Rsr@W_;mBY<`hFat|0mjtkXb2DoDP8}0R*G0_ep&UEO zyXqI##4Z4tEq;i3U})abld2@{7gFwBk!74OQ?xHjQA%bW96*>TjGI4I@|~_0GBGQM z==sjhSId}jahW^mQQ1yuRE6RkiC+*V`OQkdX##5G3bv`|dicl++UojLjFbfzGxWYF zRawr*2KsqZw$RZ>qq8}ai12T&CeqV=8@B#0VKI2G zPJ@$^ABnf)wBQN~zaKazA7lk5CgXwJsrr28boiiV3fPBhw9ag2h@HooKJwMoc&9U0 zFxepgP0WZu`fdyOP&e@=$N8MKKL#N+9N|$zN+rz&(6Fh1v4M7aRU_=G=A$j{MASVa0O&chZX)8WbJ9?Z*Q2Mze zhiF3|t;N*`&gg!q!{tz-TKLhH?&Patu>Qvoed9Zn*F7eoD(d_NdLHA=&DKzvdPyT+ zFTt{XO_=olV9&I${mU1OPOiMK-~p8%u*pT7ayVTs?~@ySESftXTrn_Q(Ue23vZtb z6*odW;?NF&D7Ss5xI+QnC}-Xc;wve2*P2q)<~vp!G6Rqdw+SKw1)9E;g%7Og6Y&y8 zq&6ZX$~s7q-Kn$do}#F@MZl5Yk_vti58Opv5f0}KT`z=!Q~d~qo6onZ+AG;y`&Mc2 zOObG2&f5Dfnd9RyR+!Hp)O7oH#PO!biD_e^OQ^6nE1qmY?X-NK6?^M)r5GTArA!ZM zq`t%l(wtEvN|c(PI=54HuVlX9YT9$^WvI2hK9YIg=t=y(Wp?xby?w1q>(g-dn)BG^ zwNU&60OUG^hFcCbgpjQUI-%@TO@d^To8}ho`I*HnbFeg0OtHaa{#XUlOE*+Njw_4Z zAT#Fj{xF+JcyGaGS5!rK&K6(UM}zlw_#FZ<8 z5-;@5u4mf;>vtCkAmH=>j#WK~Aa4+bjoH1sY=H8*xL$(r!c#CPI48^WHsQR81y2Tq zLYl_M%5i?P(XqeNs1RS2In4{Lz{Zf-$v@SJ08T^{5LAaMCIWrvRoZtK#?+a?!F6I- zKNb?d%XDs4nVN0t5151+Q2G3ANSjzZp|MD8*^#RN=*p1*+{{}uZK>l5Q^jU&WE?~x zem+z)zE%`gqh=@K#TF_mrvGFJv#a2a6aZ6iDc9L{o^{Ja)&A^ zO=j(ly^GsS0h<-Bzk1sj_rO&7$emkW%Hmend($+%FK}oXFrpS$O|QV>3+)sJj??pf zd?9!4!>?2U^AFizHc$5Jhr8>Q&sgwU5Ft->N*Agyl4?;v6shJQrP6={m)D;c(>xU zxs1H$;g}m86|L={PI@p^2F<_*m>jT{pPv(R86@ohU0Q>Ckojf`pjd&b9Qtk^a8phE zvjC_ODQ>%X1qSAA{i~AZEg|_TOcg8{NbZF`|oeIwrJ5ovodNL#um!)Bsp{1aMvlC1o(a)Fc>jW}5v)5M9?JKLY9@4)L zkeOya%bMfMtKpab8*uSSs)xbR;tL&xl@UXeNm=^=P4}R6S zCK-yGFPA)}PNDlSJ?G%mSM)QBD{T#6kz1Vs>WQ+^xOF+zsVct0QCET+B4RDl6N`U*eO>=wcpNRZ&W zLWU=s_whQA16P<{5xN1e?iHC;E+yhVqWMQA++<3{^xXqsq;pCP8(v3h^p-)>PsNPf z?+^=v0mXM>2AvQKmPLTfffWW&FU4UmEaFT*Oh}0+VC#a%Pe7Re?232~%teGLNvZ%h z9ILS|&{?_>L?WH#+LSKSt6{wH4n|g!jmFD+E2h4yUySW6kQa#27n1@t7o<3hj+^O3 z-FJx0E`-8RcW?* z+|nIhoE1=ntbUQr{h;)bpVo+D>UlBDN|4Xc)NTc!3-G0!gGAv9Om-* z-vQBIX~52mdo7>84NrC7zv7l%?TLTkmdIbHo=<3nYB}EYLL~$qW+C6UurKQ5r zH*en1IRP(kq;a^VK<}d)oj8X=2k+OqI-~7YFa!M2KN3Bvj4Nk0s_zLf*`x(irkd&sTka zkY|1#Wf7D{eH10(I(4`X^))$8=HeD zF0efOAeb>WJtoEXvQahrZ8oY{4>~P^^=7Nqe&XimdoQDcYWa4IVwmmg;pv;#6_v`M zfmjMhZpYT(Lu<}!o;n3?>W>8vMEgF~+Q&@%noyqw&?1=bfDxEAz>+sndU;yo6V%G_yv#C z$J~Rsbb;;9E|m4qkv~Ae+%B+fkD)?X-2baZirBwINNO6ShP)AI+8#sc=lmG%s4CNM zm9E9cPe8=eh6k?G<~iIpmCd)A5pp|?S}jkxzm!V@71i$TUz>o67Myq}9Km>~s;aYf z##wYAuiYJQJo&yhh)gUGaAe1qvU^x->e;EA{Un$6BJ#_f{TspZ4>FfRYkgl)A=>l? z2G~ANY$#=%N!2OlIdR259+Ifu71dk(K=MB82UVu1-Rg?PqMy>rO<{SLVP-^1@za_< zijpq=1P3c%wlR_njtjEH#7_zo+;0&mGPSzA=LYFUm@2{mSy4IoEGmZ9>YXNo5#!PD zi>D7Ka9>B8R`s@E4^Q^qC;hux7=&643&5@!y8&O^f}sw(INzY)n~xPfqHGm5?V#Y4 z2L@QkXr5W-zChh`R@lc%ZFu?x3BuqY>}+h%CV>ZaP?XYH-u7XaiI&HRZ^t~P=b@&% zR7tMQZJB`ujqz(ZHAyO(aAE9wkG~jhSgC9L{@-~@bUhWEZ`CX3A3JQ+jy9dCfTDrQ zYN>+?$&BCdfNsRhKaY)5Fm|G@k^z|~*Q=76B>K`8aqQ zW`YpxH#apyd2q3_A&$;mFmESLa!fK$(-`);$A4eR8r{WEz=pfBpRv{+3RyyP?lask{?6qT( zM_W6r(FZipkO2DEu*QKz-)#`_D!S$TCd_2$0Za>cK&F(EX3p$qw~~ERg0jztMTD)} zpDTBJQm5YVQ%TQCxbv5D+Y{C>HuUo>?XX>Ug& z$#|%sYO--@@wrK#Kke8forKMUeT~&?HkuAO_bshrMjy5p@jMv3 zadxnN#Dd;GV8F`y#P9TY2Yd|UzQH_d#qQ=PM)ys@*vsb_a*=m--oPp{gq+Bp{AD{I zLNWOKdU|YuRj$&IP^1Vl!LNeD9=-fL4Mb!d?xjP7ByDofT_sDv23|b zKA^OZ8B2PIPq8RVtga(v|1CU$`!TH4SE8-X0-=6-s~bT^2npc8{ALZ558Q$|naEg) zrOhBk8?Dvf@XS+rTsb$2V!yU$B-W4*F37N&-sK8{NhJA)3JoFV*AKQ6)|nnDbz(dg zy18LkxQr^%_r5;`^|J_{@BNMO6_VNoBXUFhdeH4IfwUGdCJZktsBO}Y=3GX2GeNrhA^ms^{w`!yTJeZO^}SJ&!oWi!)iL~C6ud!HZa*7XX>64 zB5lF8@tvPBDg9$=Ge&gfY4vG)oQHt7O){15%v(XXcG`lZCl#?l?H{Zsch1`FYo)a* zCNSHV8IhVJQrES%)3m{;iC_wslyvW&WHvjRML3O(FQ3b8U{_>{@H17)C4+tFbESkA zP0D|DhpblSlNa*5yL*hNhIlF4{6o zOWPMWFnLeI9Xt8Zj_R)M%riQgzbn3OyucdcO0oL*SgZPV7~}C;0`1t(&C_qMy2E}z zzq+bt0@>-u|H)39DZoa=d@Y7p8V)&Tm}R-Xo6b#Xn%6@ep*N7M%O=89)t{^^uakC0 z#J=xvikQLpoYCZG3;iysZL-R`6Ytlr=!GRDtLS9LL+X>#?or-|9CIu3qIwgEt~|=6 zpeUl-yAT_`d5hN?rxtX6lJFu)S>YL6K3tbo%+h~giz^I!tCm!8N7-%pdPpsZDESNm z#Z{>JCL=d%bA`(s(}TB+xvHfdg3|R~32BdFT_h7QE|MCSSq4RrozBeZDpl4p&C&%B zIfj?gXq2~1e7nZrf+YR2>o=-t8J!3}_3JCWZr*n(jKrNt@%dCh-gv-07=GXNSI&Fi9bdpQXYR$(}L2U7pZ6xp+@u26~69QP% zcZR;t&q#gIWd3V&pw9qM@Qe$Zp7%KlFQ zsP00Y$?VsuQ1H6x?~OkXz?{{$=0Cdv?^@oZyTx>S`q^u3sdi>>!EFE?6C5~SNxR(B zh$K;Y%QyN;s`lH-4xnJ7I1~3ts4e+#gID81%iJd4;`qMo$5+=`$JIORU$1-JMcs_d z6*n6(Lru;AMo^@6J%&5o%#ERD$D(UA2oSTWwMT{aFtawO?&H?2UG0zGxg+pD)Si*(dOL_&S&~Tr{B`Xq;?8eR5Sed zf0WI_$y^jWGh3K|!X5qi3 zidk43emBfxn2d+sm^1RARhw!9b1KFUsJ(KG+pp%LBc5J?h}4>IG?D~NXFZJ|JqTtz z|4Zw+Tm_idXGwK9yM~R9<{LBUmy0{tqW?S}la!E0H{VP_n|#fp7!eLWj-O_XZ&ep-xrS<_iMU}Nd59rjY=Fw-2OWNDXDFacSSg3=cMZgBt32uQI_5 z5_Ix`qMHd;P^u`nYkeA<3Ve_mB$G}-N~8_h0YwhsmkQijjzS`hw1GwYid8T(sG$_t zij@<;Z&9ihnd26fT3R29eQ+{|jpzSwedfWp^D2^ErTLs{=KKTBRo^yju-=anX6jA- z6K1pV()iO*qwDv?T&w+*`gRF20!_bZ>s4R9P&_i%xgLHe<_c6D^&y$f{h^h@^AgIT zd0G8#AHq>79V=PDmk%Zj1Mh~XhiNG(4WSC}^?R2^3gxP#=oUg-#g12UL!OO!T8r&tej|Eze*F z&KdF&E(xQqzJvyDJ*+N^eu7kAa55wDj8F(zs(IfbT9v#$$&wNg=?)XECx}`zsr(ay zanT8}QP}@TIP*w>3?btDA33J}`7A`zrFA=wKI5S1fE?yk3896|xzOatOUSJ9Y%7st zZeJU>+K!%KMU8(EQ*$1GkLSAM2@_^x}BAF z9xE9J|Fu#N^S#OVdp^wHSXajeb5iPSi-HU;JpLye$jr`{i9YbFW?vZmq|Bg5g})CD zw05;h*E4!Mtbtpp_2?l%B-a5jmtbJbJj58-AqC_ zQW2(0h0px-q3hl?Sr%j9SV6(bk=M%h|2NsqJ#82g|M2zv`^Mxp?S}^&BIt3PBiJ&| zdXBDcw2PL>Ml_C)KO#4Bq7jjFTx^)?{=ihIh`_dFp&ck#yG#ep^D`zd9X4%M5#jxq zd5QAkfD9lfWSB2*wT=7UG0^c+bN*CHji-dlzcVtA;d9hDn>D<9Z{r+3n0Y!PY)yxp zc>-!MTNr2xL2^Wx{Sj~`s{j#M4L1)r~=%D>$TWc-LmpWS=%6Ob`xd4 zRB2xrk&PhX*UOzxddDoW@nF|Bw?QPhc(jaM&^#>N%9DD%`bz|V@0&KO2Wnp$gphTX zD}_Y&%hEC5r8Boz$BE||Z*e+~qkbaFqg6d>49e4?m)!8Zd$R2Nzqc%C^W5%wFqrXZ z80!jI&96LOXb z*G2^F5go$eLmOvlf6Y&*=*hNSY+SwcFa2NC`~P~>yf4=Vkf3MM6{8m;_t*V}OjV!6 z)}6L<+Np>d>nyXR^w{?N$gG!WOc(ayPFvYP+B3mq8Urb?h0mW0y=tdz=946Y`HVYN zDfM&uyj?R4vSr1%Jd-cgdTB@kMoqR=-FtU$0C@p_NGYj@#Fz%jhaG~@nr}W1YKulZ z53kKvoMF<2=-RO3hiG}I>d=Z`Fg^1Z&)Ed;9totvrDu-7q!+gbF`{I-qUdK%R&?F&h}BD15JI%oW;x!Ws{uwP{9RsAksC zlH`t!`IQi-t_XAey7UvamVAj@a&6MJOPTLGMxHjy=={p$#J}*eHlC(8Fmxq*(>Pt1 zzbi1%(Oqv6SO4+>H{Ms(17D?VdYV21Lw1qH|J5S<>cL?a)E#*)H3+5Fl4+a+ke%tn}k}uIhHl7(L!oF zig0t*v`~AH_EDSMgUYU#{X5U^TvIU(R@?4hn+cv=w6@+S^#zd8lT%*NGax z^PWYb$A<}qKy5ui14}h9?{Bcccu^HCjKUtg7(3?fo->NLG^m%Gg8owFBpS1rUFK{I ziDHCjap9ke{pH4g@_0rOH#yYdFRk`A*x?TA*D_NSL>)m%pt51FjikKCtAi=?rH${z z`J9F4nu!8F*wXKygz4el_7e;^0m)uLchkC88l5GIMmmp8Re6#MmAu{Vj$P%rH}*Z% zYebz>iR^^Rv&xCB@^uAUN;ptMSb+y2vyE7LqX3nuJx51sAZ`zUkmv=2-MGmy7h!YLRVU`^vEp-rp;1is~8e04{# zNUWV)-}WW+ICuC@(7!EGQhe9jvw&3{>_5fC|DKVYW57x2XyM1-#dWqyl+qU7mhH>~`EbUE>wBOj@z*D1TL5(MeaSYR?#cvBEU zbP1h|d@>xFCH^_;NlT@3&8&Xy69ovT~_0@aHRzZib?tKIOb9D_b zL^l$h#g*7=0lUw|oYzjmJUZp<`ds?(X6l6?aKJ)S>C7oh_XNBKfw+fsW*3ye9H!Ke zz_`RG!zOkzKE^m_|L0^@{kkqy@~d1j9w4$`z{^R*q-&qHLfCNz*5k6U?=U6e?&*4MZ$CT*sC#>g^|e{aB4bnc|EGp)SoT$zAdw_BavOF+6KIw_zbvom@04epHgpeZ zwBJ+c$!4c7SS!HtBFW@j#h2zjkADOug;#=HnBLx%K!-#3m&z5ncdbzoHn0S1 zKMfd*f9{&5X++uj@6A8Knf;vi_d$Fv`=gsB3E8jd{-+|-$FBCxCu9^o{Pu1zrWF_| zMXhq~ZCi-?EK_@-B_F-Sc!2-G>2!d(QIj;$UW*f9Y;q@@d>&*FQbQ2zJV~7z`*(tj zZaSu?<)KD$;=k5I>1Xt#O?Z_FovngCgqC|G2*sEMm2Uy7*E>RiB3TmVC5q11feax_ zLr0jvo7Su}ARyuy)G5Fs6|5IIDI1XU+tT%jnhrL6q%KfD8>B4jLIcI@Z!p73sIYW! zTh@4tsL~2(Ci}Q(a#az`3z5sP$oJ4Gy_-Ym%_@}`1=G=yT_aDNn$)$9Gr3aFGT2M^ z;?x(4_U!UVi(_3k%<%|HzniO5Y$L`jM)@tufjS2hUru$)ntwOLH~6+YFQDhzuA9B# zC^ASJlWpdBtD`E%qW7};dH>lQ zwhorx^sJu`m=pFv#Cn<^Ama6N*IpB-Xv#kB+IAd`4qSXvuZQ3D&fAUS!cz|S1(EMV zGK^j)bsUDSqeqpw(&K(1L;xhY8qxLE`=J&?IGYax%0Fs_kJ$8V^L7 zn&b6L62K?ftc@j+JREM7eL2Sn1(!*Z+px(^=^~NW`W13k>K8KGHKxJt4sq!h%Ekx@ znWWmrkw3LZ>G}^wrmCukGt=gA_)9`n@)J>7c(N|nV0^sedqz`A@r=qL*~g1#KZGJ8 zd6H>cIO0WgjT5t51N%8)(sN)$o>B^A=X zRTiRa7Xouv$?zbVzkWW$(hWR#ldy5ZA&cAO%sFK6d?v{Qj%DcUKn?s?{S839e4_H# zrawMlFQLL8!KO{c{?Xvmgp2}R=k!LT6uO2fosaMFTK9x@s6E%HO- zA+@3gy8a#mMswbc$0Zdr>FvkHLxDZm-ya--Sq9;!d6%l`263m=!iB2TX}4ET9$h02 z{TzO|u_atzt?d<*4s4>vt;$hC2E#-KqZ31ITd1twk3qM8d0=mxTq4R7_32eq)>k4j z=+(xgQB--S2Gp}(EHg;JHgI6?j9}3DuwJ6%@Y5>(9-$5c0YGtE+?O6gveyZ9>#N2_ zKf)Bqk>7AwpU|~rPj3G{(Ofj`6MSn?@}-PfxQ0V&`j|{P`IA}+(z?urr3(8!%xst^ z^#}h@k{z1anK)1{cP2eUiDD&06bjEsz(m>4{{Duc_z6{De z#<9SDm+uQ7tlWBa^VdycJl}s^jf87O)p9-kp>WO}mwq2{H6k3nFT%NHnPPbLRQ|8v z3EEcb0r`LNB3D?P#VKZpU}D-F&fD7E2;AjB&|1UtMWIL3Ykg?NzpwW;%QUD6WEBpG zI5V!sOOnr6!Qr3C(WsHjU|s;@OJ=Pd4J-9dJ7Fo4TpRn#iI0?a6xX#_v0z8@*LsQW zT>5EMuMtwd$7*4A6ry{jzpbdT6VV<%69X6x&S>6WJ(J!#3a5c z)?QlK(BDmtieT++@TP)x8vE;e2Z}R%`IyjGE<6O4)A9k1$5PqU{PV@0-el};a*m*0=qs`v6as#dJOw8$}Z4VX&#YO!Zo}Q zcZ@rzY?id^_5r?BoA{Fv;n>%hm3?W`w-W4elT6^_5>s)3Z!w7dR#`0;;j#%QZRqyH z8qI~N4X#&o$i4>`{#XV5k4B~`p^*-~w;>E?>41N`Jp20RT7+%}8=gLpe_fJxe$A2n zv*eBQ(jEKjd2Al8a)if~%g1o8I%z@k-$w(t_+-7iAVaon38|!`6&qpgCl{O{y2T=| zb<5vCTkI`^>EoN#=|Cr9=KY*sv&6&sM}fbKgNj>N z-?s0pRa6U^#`)UDYQ71CRo-(a)3AIXg0U5N=`Bqr!ZpwFNlHyv{ub}9?3w{g^77To z?H^jenoP~)l&B;->O8i{4@LYbpBJy?A<^TxEHH3Hatjr55>a!N9hXee`i6%*e=Dl` zU6|WipG$Z2PAatIr{S^SO8RwGKVj6(kU>BRnF){s5e4} z(?`M6TMZX!U;p@Q^+R$b=mFo(w1KM!kMj7t*48%G()t%Ql_W&`bLoz7uiQgSk0s^7 z!V(y(ls`C;Jv2VERWP&Tg>7dA4(RT+w4bI1Ii{7rKjYxcr9#dQ?tOb!4s|yIZ=JE6>2D5~Lw{4#a5A)2P@C=6ja%_4aYHgB{N3-gW^& z_QTyxW)Bp*{I;T|+1_9K=yK`R6cQx*j${~BI#;_$B{`fY0g|_VU=sZ$@z9(_gR7MN z*bXSC&X3$YSz$7P({Ap*q#AM$L<;SMnxa7~nw!-48EpL)`UBRp^i{+)YVi5hdO2g{ z6Vt)8^t(t%NbTP$O0>8h;(caFIicF2*a*7qB!K!NO;eM=1WgpL$Yx>>dXF8={uJ^yYt~2w)`2w2r?KmE}t8kS&XXO_SiK zm2AU$eHbyx(X2!=pxW7&GA%DX2nuPWIf4s+tmK=cltKII8-kV5TS2$tBk;` z#Osr1)xXg_ueU0J`|WkkwO-C=qb`DrMOXR3yad%ZQotthuyl9TNnL>VxZc8g-KM|$ z+f~bmfR{GZSl?(ej|@hGlz&omriHFLf;l@#q_+jA1#7hRcDqWyWtrN|PnWoTz(;+z zU@N(y`dNa3k#sdz6lN!cVjJWLM~yyeE}5czTQYxR=(oJ~AHhkMw@z`AWycS(@Sa|E z8gMAxM(4(%nCsaZ+SfW#L?J}i$|{cxVJ5tX;~aiZq_2P1X)JS?oPC?d`{ZS0feRBC zU&bn}N-kW3-H$I4geZ>|Ns=J9;asL~e8_0NRO!Op3{Wb4^;Ol(tMBf+*=aJf?@t>y z1&)=!(xC8(YI+1THZDSgun+!6lbjsQfmgaC`Ba)u#s)1>6F+XYjt3;0Uk2RafF&9V zy_nMvDWe7e7s$T&hhIxX2DEpB!06r$9UA#BAY%Bq(Q{q3b_&1T=~=o4*3x}o)~uo9 zrkf`Z4Y*&ZF2ZZ*7KDRqyK|w{hUP8q6eMCMC9KrRUR7VVA~+ms>ZN7nFmKuXEx?ts zP8z0mZ-p&Z(@=e3>Zc(EHcJqjB`J`@VrA01qHK6Uw?8(6#8AN;f&f#{;mG39@s>6` z5%{gqu^coX9idW`v^{@e(9~7uu)B0SKn3=NlFh3hgJdRI69d* z>U6JLz@JkZwQo!)8V!jA8SLMpMtf};n+f}_9YsYxTphdC<}V|-4z>-7B$H;mhEQ8o zSsWc3*_g1reij-0sa<>fEP4%BfkjPD>82z)`+8-vRd0l`KDx$t>V-{LBpCQivgYVx z4_IMedT%lzkZA0RSfUZTTVbITUP@g^Nra4}Wktu32&y|B8~k&7S)hk_#e*eKbWt6u z+S1%jy!S=Zo+B&8%aAsY;Mkf{Dmi>k8IO!ETlYBF1E4wH|H_xMF}vWi9SY}H(JV!> zPuSfKik+`rP5J^iF4CKY6ncXU5Ft1`iWd#j{b&*hWe7}01>Jl+9?6}gM5Vysiw+J_ zd|cNC-3iN6=cKR^6su);wO?ajzs;bBmSjAGysRA-ZezoFbxJf5;>((ZLqkIW)%zO<6})(&|y z;8_v!_j7q&sHz>P4myuOfKv;1<8OLC*Xftb3WEt=!*h@d8$O+*a)a*(;kgfd7Lgs72#;d2K zqmZs`7KY4GY^u_9l-&yLPrri`rS+DdW-U{7G2T7n!-r-a8IH~*QX%?$AaVINM%qoe z4Buku5OW2wbi^agWg`b}m^2*)0Kw7EyfJi+r5)_ZDXmxZmeddwQKc(tmWPe8!k$s# zf$VrigC`BM+FGQVBthPgL1V-PBq>w`D^P*~RCw?D%pvG;Jo!Tq7HC?b)c>P8|EHIh zVYC>u`-9@#>6a&&24wVz&-(1O;pO@tmZe*SHEkRq9D23*#H^JvnI5dM) zUYLSmS^lkR;dc}I=kx9%wGJY#<K_df7s{asNIab7@~;%rn@^X1aD({@HmIiB*p*b6U80yhVJM4_sqX6fsUg;=U$I} z-T6ZJ+IJb;ojcPyfgY3xCC@<09qkI%A2I30uh|xqYv-a&RjMm{ZWUk*=^sMWYS_~A zDQp(R<`n8>(+XLsvB4k^T!yqW{*)VT<(i**N&sPON2+>-__p66vyiU&`epQ!;x-Gl zR=?TE%%xAKo*L7Mg%E7Mf!e7&Ig)d!LPnWEsv)snpc^{KLX6W;bAbRP-KT>+g=$iU z*2uz_v)xp}{4gZ_g|wOlT6l4EQvBz{$CD_F`!Q7!S4rFQTN0bTC7hld!8lG+Vq4)4 ze)2#&{IT>VL$vo=IbpeXN9TKMNgTZi5tL)o$T zeQ}ZU=0Nm`P;$CD->qG)>6J7SX5^<4y;pRI*sn#XVv+8>^XupcUv9c-`U-zPI)4=v zP>q++^9loOoRSlf{uxG-={igDGrK=ItD1a%TYw7*Syi4rC7^rmffxSzRan5+IaE$Q zW{Z3Wy#}u-Q|8eW3lQT4a&r6(yX<{gDEDdXrcJf`1M}+dZVl zC(MLa{7>)U%PXnw2S0@_n#%@9&30P@Hy7=Fw&PvtV?;fM1RC51t2Eg2a$0eh)woIR1&3=yb+%jgv1O9!ecxU z73+n_Xb(h2dLSa2(y=~>q59&I0ufHjF%+lfMnMwghVXbVgvPofG{%kU^hN}28%Em( zN4O#=%n6c6R|H3r(;{)*5pmM>(Fs&%qOTCgrvwPc5gzY}usC-?oQ_HILsYysmGeVv zlD|-Ybb>D(2b~9jNEXfh$}S#uKy|uE`|skR%guNz^eZBULx1BfB6HiK!t7jShs0 zmO6CJ%wg+F*SMez@g;5WlcZr5!E~mAI|3!4ICJ$niW(=t)glT3mN5vnj76A5971i9 z5MrB*FzRrI+NBDLa?V7wOBSM?vk>8!K}sj3QC=EiUDFWe5`%UEc1=nZ%0i1#UEYcP zyQQCC<6+)GnEvyGL6{DZ@Z??}Zr?sf&Xiz!;VibV{|YNDeX+%_1mWQgunX^idtei6 z!IJH&TU;z7li|lm+P-s!+ZL z^o`Yod`%q%l03Ba6rrWdY3Z_twmj4{hm$y#hpNVKIyPw@uh-I5gu0fTAT`ZlB#JfU zprJKf*p{WGOJ#NCsr+#07$`#5Pzh=}L!qqo1=RGZyy0-@S*gR)$q<@`iqO&t%pySgW1`XPe4%Mx1sz&8ip+WVi z>CwKaP7MPEsFOIYO7*JKIjYbxt7r|QZKU<+7%M@`P=S5}x;7T-v=6#&RF^i@si7wi zBMVKE7UgTefR00pj?0j)wV^p(N7_c;RF&4L(Xu*~(}0PUHq344_o3L*-T)SMda!mh zfRzKMb>ZS=30o&)O6$Yel72U9`n{;EiM5VYl;(Y!_NPs)G+|+*4J+E#jMAo-v=5S* z75(0nXYXtbdlzHaQ2kc4FOF>;4dLi&23JoDc=_AGKiCVuuUa4utNGx7mJ4?2_@O(k8hdw3Cm>z# zJv0c@f1)r5(*Y8`eRvJGZxKwd^x(>cbJ)H1D|}_{ij86UaLKHPN@@$Vk{h6zQVpHt z8tA3e!GNTjPz~LUh)&Cdk+n6sQ)7Z3fy0;@Q*&xa38Lm!2EwEyV-s37 z)g_RcP@W+*q=wX}8c;cEv@P`CFPmB#Qp0NkOIuTt3Cyf1pXx9nICD93Ya`01hTPVO z(uT0Mr*d}2LRprDjS)4*C z>}lB+4lY*k@NuHX+XX&>uGDb5QQ8rneh$=tdyr%Fgtx>Qu70-g33G#ID3yzFM{vA9 ze8Sz~AI|Gt;2%Pbewa4`BgjD}ha)a6N>FfA0K#J>h)M`XOmYZp~6kJm>ap3W&Qk&YvQM-8ZaMhtBei>%xvWU_LSg#555UxY>k zkc+0}v@G~YqT%Ed0k6bdcqW#?)+GYdHC!-L$pOCJ{y2aA2|61lV3w*q)~dOnkUEL6 z*3n3{PC=SQ0upTF5oeo-1iK_8*e4^IoM@6`D#fWta!5s@eF{>XGLcLQ^~^wXYz>zA z#o(l(HKrtFVbAXEznaZ^x333}2H(v);KLwH2S{L;-nnxgSFfDG^^51Rd*vo*ocI5_w&-F?G=vw2u1{T@#mL&e9#2G-oZQEnJWJtF~j|>K$0NX&>gT z-G%w9w_x^$-S~RxRvdE;!(;;=WTfPymwNomG~EcM5d_nGD0&f015@EmFpWyjLQ+l+ z3M&ecnw5-{ENYO_VyIycrA9b{8gpu3V*;rWmrx@fgRs~jYWS&fCxueJ6a-W*J_zA) zfrzFCK9(Bm#Ple{QhqcwuHHdz_KY!EF6Q~59|6Dq{KO*qxbAn^_MfUUDR0VNcX z1etKEo5lMHBXJqtzkjF~%*Y}0c3fw8Yyd)|31D;#kqHvvSfZ08RMrnhmYN8O_MvqI zr&w=;p->AA%WzNdyxr8%l5tr#d2%gAqbtV_3%0@p7GE zaRf-JD?Hv8!Lh!O#L)H}lL9I29Z7JG@rF;72mE5Zr0Gyk_!7|l!o8@zKtbWLeEk9i zfQH8SLlWT)2_0(?)e#s?>Hd1d2&kd)bS>!GhSK?Q98BjdAy5ZJ`@%ocOE}(0I@VC? z9E2rOy~%VPNW9GJV$unisi6pD!1MKp3!!ToOmV0H(cs7cA&=9M1k$L4F#3I>5kqkj zK|F>!0I`&gCkQh%6X;qb5y+F%A}MBYMk6gN2I*O`1kHG4=O-brC>8ld87MBxMnQ2V zib}I+IUULA{01bxw_1tn#%B6Gqv7Ho1J8s4_@>vw-ZL6Av|TY>#Swl!-Z+2b4%$1% zO987D3Tvl4$orK;+qV{`fz{9sqjXpeG$a*J4=RUNNENh0t7*9$nnJn`n!)wZk~Ba& zvH_Cv`KV2-#1UmDOiE0}&OO_3;nYFlr455H{pSgTFdZO4aHcoU;_~IwxO(Y4wk}(X zbtYce6`_I0^r8{@>ug7WENURTtM|oZ`&Se#289P(k2m)yll)bWH6qJSFj50)$ zGfmFUKtpE(N@`1yUsZs-s$682r6apM9XTAArcr)2itF-GR7v1vQJLKGEaaA^qogt$ zB~=-ysLw-bT^@>RczrgCNQIRI>#S%PTk9Z?>dL2bg*BO^EELvK<4VgVb-A?fTqI^w zIU8N%m1m-?t^k$wMO0@IifLb^HF+o@6;xy)H8&o5W*X9cbAB!FGZzI_S%QkHb5PNc zkK*bqnA+(gvoL{w6}%Bg&54V@?Lr=UuDPWjcD$gR#mQA3^(moya!DyHjF z)>tU0q&{DWOX(c>yz^;a1+-m0mCvU-vdU9wTe|L*1S8s40p;aZ&^kId7N@gHQ;|mJ zl~$OD^dfS7CCQYROutnkGK=GpoD(G|C6@qK6pzZ*B4L}@4C)AxOHIy*LsEJik~7KK zrN>j}gPdgbRgO^HGhIpBDTV>yqVFuC$*!Rdw|KAk#Dne3RUV?>ZnqPI6uy#j@; zlTbBkHgX%sprm6ws=BA3x@!i?I%gxJekx3(o8VWy05vJ~IH=}@F$o#ixpS-VJyTg{ zI{0YJzz>5k9U$Qu!SwE(3%J~O8kY&Co0hD?24fF=6G`A(y#aS#yhc=Z8S2MO!i@)y zu;+Ooj7V8f}PPR zXsM{gWoo3BYP!J8J`BpR_6&Ss-f*@e}x3ye1a`I;Jgy*3{X0cU{g>*5UornKoP)dNd&{pG6E9; zDWfz6ISf&PaSj1JtAxrC$n&Z5P)xASFQa-$1=Pu?B*>Q2@s?FkM}m}JPS=gMBhcj$ zT=NKe*$hCcKcggtj*%Q%KlJmdgTcyU$41ATMV*yQ0%&$sD)MMOtB`@5fb{@g;3%9U-#~~c6|5-PBd zU^*fp3%j;&5u7Q*^uwbugD@TFVGyPRBs{%;1$S3zuP?sS9?-m0;=W z^?2~?B{gbAXd5>Pw;w%0bz>9OY*>%$x31&Ht=pLYQzK4}tePNJS1PE89BXcA4mEz{gz{66T9`r&W)^ZvN%?6=&5S4a5`mcH zCkV9)DFPLy_ZwHD;; zAzik2wuYUH4P3mPVDDiE8_KhFvx0-C?fclt+aC7rws590J`yi#?>ts52CasFVmqkdsX< zV8~Kug*rVs^tX~KGdOBv!TZC=L&m*~X6imzmF-y}O zGnHK7?e2#&*Y2UKdn%?--U6*aSh>a{D82$$A3VdfS+g-_{0!WG`U+<+-@=;BJJ30L zGC}q61H` z`u|f0!$1v#FdZP_@!dXLzutpOFag1lkubNnp~lJ{c3#x* zdb`5e%as~mf{&Xctet3`ofQGh8WzqrFtRm=k);XrjP#*zZVYWhUFZsvnDk&^q6a&I zoFhTbpQmriL)5GPaI3aB?A7x!S>z_9vvBZDDO=1rsw< zm|9xE%-Rx`_O`I1I_&7Y>_yReS=(E|#nXkr8H%*5G=hq&P?s|ue?X8IoZYxy0;K^Oabe>X~SQ-h}hx3fg^hvy)>oKNtG9hQj^%)As zq-R9GiJ^}0d*~VK&^6K*j?;?D8qu;D9f!HKx$wKG8)!j`@^p=LVQfyvY-R*+e=pe5 zx$BtfL6eSMm-es2lhrKEU}9?xLn{j*Hnp>cv5h&*=x@W?#U559N4jqALB4{5VnPv- z9E(J9!1*=hsBCFOK}8u-v$E0B-iebv=P-B8R|rn2g1Kb?W^1}&j*=t%J^gU@+5@z; zPsIccSIpNAqE1jE{A0_|ckd~VpX|YvYj?5l&4vd~S1>N1< zc>LrAM$cOfpMp;4M%2Ttcp^GdYOs%B+8vjHT|2hoQqSS{Fuim6^x!?ye}XUw(*Y75 z-@S~hS5D!=#gn*rp%=?%EhLz_U{_ibsz*%2`TH-h_vi&|CqQmLb{0K1?&Bi$us82M zh+QXovHkcdJpTSiY(IPqU+p=J+t0p7&xJcUe)9oFGMM>_UrR3V3F^XAp#kZUwn zEnkPptG>b1RogIc{SF+YMrZ9;TTxzBg|y6EM8_u+C>@2y(b$%NMqssdCWt!P!^X)$ zNIST=!q&+hmQHRYS1Rv9jj;o{Id4QKr64IS9l7~=C@v{LO>H@9>&j8zP>IH-YEliF z+uG33+Jc&fdQ{ifqp7_Ot)2C#Z74%yOD*aftI^a_kA~((v~;wiuBj1?RKBgN6OGLc zXlSgVdTPFVLT>Gnuzv}Rg%hh&OCC6 zvE(!Z;Ns_rkmztK6OXvq80_4&9T{1v@bvbCwSxme+6HR622j${gQ~6}RCNrXsHqDj zO?}EUfHFy4&xF<)(>f!l8<|1d%!)c*jxe=%p-z|wYyyJe9uWhN&}eu`B9UKKi?P(1 zo49Zxa%x5(P?CgYCLUO+?~de{I9#~#6fJGjFkaIGb991W?h*&@*iu}5`T~nqtiB^EAS zjoAy9V9M-ym^fo5Cd`-u704?tL{)tm z%Blz|1ec=X926F2BRwM>zJC6QAPA(SrBP#_NO@@}Cy*4-`aFU~K~XlcveMz|;sQyq z1TnF(2oDQG62YUCfRta5M<7V2V<52PWWvwa6B3C(V&fta5gi8qKwlIW<{>*X4Jj#! zNKA@DLVOHDLV^)VE`2t zadF6{ePz=*XXjGc>?E|d*CQ-Ekl>X{9gHGm6ZBHk2zsQf%mifTBq2F1jzpj%rKYB$ zwx$jxCB?L_RAE2q>B#~pQ%DI^CXx1ET3$k(hc@bHG$Nm1$YnFqsWX!vkIejZWaOnI zuP}!?AGMe~c`|h}MxnO8n(9hIL2d@}>G%o@GEiEQN1)C_S#=p&$8@1%;%HY2^arRSiAYd#L)}dmQK*Ic7wi405ohpVc`{qs?JGRws{Y>ezOy6w{FM$jk~dO z^){Rg&%nvB9Blb&JI>vHgS4zRjMwtQOdVesI7cF>W*jcPc#FwPmSXO@E!5e3f?H4D zVdIWNn6_vQdhb3%j@~e`<~RSuW5d>OU~T7!^sF3A zoirI^$^DHT(TRzpx-ezzNP<=x^z}?(VrmCFM|XJm`eEL}1z5j+9oDT{jWtV_VeP^t zSTt`DLV_cpr*8rib8DDc*Qz{=YzdYxSxj1js@hr@7#j;RF*iq6ZZ39g{+jBea@1K^Le6OE+y!WB zZik_v2|PT!VPj)Y0Lr4e)?yWPCYF8qB^J+LfCV#WW8#EKFtV@~j*pMi+baNTSFOd0 zrHim&;T+6o&7FlAlPAK0+?kF(IXP_|*g3gS{z5EX_$B7k@z0t!2eaqS7Os~AIei^n zBdDlp!PLSMW5^-TpF0<`sADs2#&k@bJ{>b>&VZ+fCp2|+F=^tZ&5J>9nuu z(=c@!Ybs_;nTqg02@LcNpsJ+_Z7P?alaKk+XJgKkiI`2tHEYr&%$hbGu`#i*add%; zmoM$tnw)7e=FOXjg>;^Cr_R948M82b#%we;v|`+pnHWpQKYspV%vib>vzKkatmUK? z8!&I>7R+C<6<@B}f`zL#W7e{Dn7U{+M$KA=%Fe0CsT&Kwv|4DpM8nW4QFs%Vl_U%9 z;RNpLG01M6joOL{*y#|Duia8m(=r|j)ze|(ltwW1!))CEn0Tcjs9-F*mhC`V%Q(0s zm7;a-dUVWOg%Pt?W9s_dC>S>n#-XXGpSBe1kKRCX=VGWwHbFh234s+e(VkX?9onAg zq`&uXw(@LV9_BrSTjvhr?v;~xe0vb413e7Fbby2h_b%b?wO(Agb`Ga6ox_5u3$WJA z3p?|=V3k}Cwd5}7C$vE~sR7!FZO|Zq8s&CCJ+&1|ac$JgZh|fWRX?~4dZES84K0Fp zR2{*z7VaUnSYs4`4$C-L1{7nGnFK3zo#5x33H_iVSaV}U4cPdu85r3%1k@bM!! z`bMC#v<|W4C^BN=kQPlYh@crA6pk241fl}N;9}zlM{5Vzn%Th1*&9*8F(}F|g{!?Q z+#Osop?frK6NQD-X5!g{N4Rt83a<6^;3nz8r3?6K%__JNpuB8dkQf|}tmqh=KXx2% zpFYD6PoCq|t$XGk~^czm&kbQY7^ z+F`D#1$S#}xR{z@<(xTq_V6~|J%5Dn?%l$Z%NOwY!g7 zckkoJSFiE*`3pR|aT_l#UB}*a8{tU6b+@#Fi^~ZdSH%wX~$)%Lym;?!tF>@8Shr%jb_C)A>Kev)lKO z9v%UIdplTaYe7QJeAnvLczXE?o?O3$Z|~AIy!Qa#(luJRBvEcqbylKONydiHP)%MKX1;+Uid~DV7_()%soqCw2 zgNO>KMAkz+ydD8%Q!pa420L}U&=Q%39b2~GQqNHVrZ>+X!kxYoPFN?mAiQ!6VymXYHl`9LQH5|V znE>^K4rs*I!#1fF-YHcG%C3hbw-I_lxo|5R3(v56a=8J*OYa>6OEB3q90!$*u~f|m zV~zYU$4e4ID62*#yfBU9inL6xY(LvDm-~^E53nSJe!Qb*ykWC>}Q(N8(l!sk#NX zs+w@Sx(OFjaxhC-53>~XvBk;*`&|QYv%CQ}>)LRurd66Qsl&beYHYXl!c;j8EYq{X zCL4G36;|U$V>gv;$DOJc+%BrYo!l}U@C?GVAOaI?OP_S=qI z1$DTcTZ{c(VVE*Z9cxV-u|VAzXQR_`v!(?%nmTZ!p&i$0zc;fha3(YXGvqa}NZk;# z6*TGmV{o&yR$8u}>Z@wT&B7X-q3vfY=wQC8A*NBiyIcctE3X1K$-P~#ZK9aYsiYQH z>3HTS>tL~#F`c(2Hd;F2W(FN2LFPsaolols;oNT&)L^Nu6_#k33;SQDXNH?;dALLS zzS-D;>n&Y$oOE8L^;l+Ljg{J_m_1Adi&b>d7nO{Ad1bg+LD!Fuk;_#y;VWl9tTVL2 zJgRR#sV6WJ_c9A{x1bca%WH9~j((TQM(p$q!D3BwEKo7TGF@|=2#%)TfXd{R(*A33 ztD>IHy9LL>lCebBhOVDE7HU~zzLpJUsF-7xx+Ui8*khHcAJ$t+u*%pA%k>;o}d#R^|)yI_ThKe}zFS-sck+rb)PlgNq4ZDS9!ZErS`r+jS%PJVgRKqT*n*JX$ z;1XMeu>2O-CDuSCv=pkL6$qjKr>P}v*sbk_wun@0|N3j3J$?XJPV-9}4v{lGG3ZSH z3Bn*u2T1s}Gd+*F6X#%~i5K?fcf&rh66VR(n7M8T4xKrNOV=J^-{CVTZtX(p#Kka5 zsDpJzJxaQ#;K=FoICAm~?mvBriC=C+QpXI$XN|^svmlIgiiaWf$Wy2xnn;b@3bjzo z)AGd>Lq9Aq_rd{59B!nSP=gnQHD>NO87oC--7w9d>Ey^%S% zlw5+H-cgvVZHsx@4p?O9hUKO{*lZt)IqKA~Dw<-UhBX12>Mm;`IJQzl+>BeL4Y)y| zIpQCQwZ_f_KV8g{H^52*8=OhX5dd+kyouB(#PYht7wRs1m49u);J!OL3Op^ zdKtm2tPyvp?Cs)O>~WJ|fuaHC4Aa6=Eeq`N4yW}5aMGQ!R@^RW!QJ9!+IKYODI1XM z(Z_Ov7H@Z(kE@~)*9j;$slGdZMR40Np98$JLBt0*M)>4b{Nh;ksByFz-t#5YF{F ztAF3u@+z^$lt4peW(?P+-_Q|Pl5>PQuF)}GqYlXp0_3ftIs&pQW)9Q9JUK0VW9x}C zQ7LqubwZt7MmW~udVKBZhdD~Rm@TJ?gYFXaL?q!J)pv)^n_+vslCEWGGqyTN2=s=S zGL*^%M&oK$G1XU1*SJAA-<$Ls-Yjjw<>XR)Lmj9Ku?09u5ZmP)hYe1lSY;D{L*zP7 z6TB`YRnp%{IZj7rW1DL<=4d-%fq^#`8U$djo*!oGdtsiDFXk9fZ0t)NJ3lP4499x6 z1bk^5g>l-{Inwk(o?!&!Ju@KZT?u{HB8=CizXwfEr02DuZp3^{oc$%%Y*>daJ9c5t z^3AYIs3cex!!@fJ#a#rFoY_Hyc*&Y48b1#@rbTarMkajBOf$ z%8VTBT)PolR&79HL?U9t5>Y^|Xw8Dn5JwzJ`$&Fihc8`Z-@8j{EJ2)E~Gl{=`zkKpd52}s|y*5gXgVf0+SK%kh8H6|W7npum+?vYrqZY?&h zUxEw02XLeB1P&hFj9Fif$C#O;(KK-c=B!$TO`BKZ@$HLv`tUl=P(3r}FGg1DL^%7G zV7Y-GMwmuJKe!f}A&tWK9n}MCpyE{w6_0#^YBFj@PQ=PhUt!$TnHW8BGDc6Hib-=8 zpsc9_#SI-OsBT1a_gIV?KMjRd4Jc@6Mow)rf(fFQ-XXB?35Bs&Fu4Xl7`ghu#Kjv1 z1Qjb652WQ3Vb!XQShIQq*3-GHTCoT#md!(5eYG%?*WD`s9=<_v^YKGLaWN)Ln1J!) zXkQ~nV03pErc9j--vD1~guUVB=?!0h2@+D$FnQW!Oqe(l<0o`s9L2Nd&q6H0B#MCQ z?c6Gn{0xX~0(7>nqb7z9T|z{S@aaVg2da%WdNT00ui(%yh3 z`aQZwj6!-QHSS^2@b(WvcyuhK!>CLvT3hPSMP)jh8`06)fx^Oa`1yyxfzI1EFcgyD zAdDT+fe~$u=xVP=TWcNK+FDRrS^+OVe|Y%@!o$NCt}d=rj6LSdk;2#y$yM#m55Es!RYaGQCQQ7$gB#u zM5e930x8@;hWV0uZ%``le6?M?t)i-J6y6` z;F{MC_p&a;k6HxF_$CZ@$bf=g6Vv9SEOW@qJ8{SoIZOV zZ(lsd)$_-2;^+ZPo3jv2qbH-Vq7ExpuE4{4)Hx!Txp~c(*tlgAa%!59P}YH*`pKAI z)`?vjK4=O~!NxUfaqa})FFlGo7fz5fJxegX-2b0C7zS$i2f&o<=*d&S&v$_&bs&9B zfBs zv2V``Y~Q*JTeq#oqsM*t%TJH+=eKw8`2Jbkzjpy!cI`uI?I^hT6=Rj5KSr3vKrg5Y zYLa>=2h~F*pbClvQ+dxqsCp(Ny`dZXdoN(ghK-oDWEmE$T7&tk)?qHGl^Uz@1lFbz zqp_46Yi&EhYu-66(}SSk0xutTxbRCB+?-)*V+~CM zL#Sx+%OK3*;^Bp&;(XLq7o)YQ91TsCsIIGqv#Te32+Z0#h6J<-goQ_V&4kBy zY@O^8pAw6_{4|snWgkCm)nTyi0 zB4K8%y{i*kJ-whsj#E=p1Ia0IsH~)OsVf)Cl$4bsIXwfe9t1r)Mpa#H;UyF~w687# zYG*eAmjKvF9fY##8iIT@{DT6asH_MRGb8GFc+&B>A|Q~UXln;^a`e^?_DD!eqTeA7 zrWU4fa<)fkNB|-uB#4NTAUrAQPiwguKF1nAtc%)5HdfhAdmCn!7^X$^#lUUeLDlhnkfS)NK8rZWjn8Ykw%&20_^_ z1WFF!P6-8~FPsqll)BEw4 zKRv@w&oAQor5(6`-+eaVy@G>x5(x)GC*T2>EDYi|On3x;UhVu+R%zRlbpgPX&BV;`(fC%;4|u z0b3hOs3@snh`ciX^^-5~yU)JBa5Xi2A~zIThB|O`wn2DU0Nh<1ph%s7&xa}C-#(%G zKBHs%Vi<-{IV(#e1O_@&=fMXKPG*o-lE;wY3bfx(@%zt);@|%GIph_U2!Mvg1{!NSrM;o+f(jgN<^r6uH)RPaZ-CcmTo@jn0M zkAH-jl^Ja9EfE{O;2~(r;iWyum5IFb&OZwTMlK zf}bP+hUOOd!_eV$9$(=1pL`BmYg-&Yco6q*-@x(12QXvG6mt3#P}A6n;p#@zd9uMU zV|&OMIY8dX8Hz@(P&Dy?vN?g&${(r(QDrM%sM-*qZ6r{&4~2?j1QZ-2AxE*YBSFr&Xb* zWi(c|7YBAO!O8tAaQ4V*T)nUtw=V6*l~bGW1Fiez)fN2w z<^k5PT8nk%jo72+iiXextY5tf=LMJ^mcsPPSvQOKxPrg^&_}w8zr4AQ@9v(&r4#FL<;+I< z$KQ#ICpKf>_LUehZW0U~L*QVaffc$wXg7?2j#nvEeXF75Ukk-Ra;E-eP@p^of~uTX z7L>hHq3)STP9X!TF7X&{6#_YnK**DZS^DD(Qy&a9@WfDk4}7lYj?XCmqqYnFsO5+u zdiEHiYlBZT%<(CKb%>5NK36rt7s`hCOhFI78=?Vu4I|jOc_T199FmA|SlSVY=8un zHX#+_4Kea~~*a&~>F_`q$4D@P9s2!vFbX z7)&g!$(eh@!_yVM9k9omHQp-_jlCMuyt~x{d&Pa&=ZNtapcT{p{%Zr z&xWc}=RuKhk!L|UyoEWOvB+;2x!H59M&UB%gCpqj8_=QAc?b;QB^SpX)EBbmi;rO0~ zxO`$YzP-K^KYx1yKYVuKvi<`X%aN_VLe0To@{`S*#{QXA~0rl^c{>u+H@h5Vm_pW|}~@IizEVO(Nv%5;4Rs9z$&ju-0)HZW#+XE0T2-hFAna(N+SBfF!s? zXF=N~2)gd!unkUvo>L&SZM@(Xk_k(EX4b7pyi%fE&5%jkehR+?t@r7L+KDUm?r#1=r%q|&2 zoH8Nrl20mxf?Fv;wGhKy^D*2l4~pbW1(-VKV2qY8!PK4Hx;w&RlCWp@HXPWt97lF9 zB`wC$UGwqnjh*=S=O;<0@bjx4{POlZe)+zSI;SUb_xc_@xpxNpcJ9Wu`flt~cR^!l z6v1?r0Mi@2M{(=iG2Fe}L(X&%rUO0v17J#4bW$+zZ~cvW*err;|Ej_84-0p0ox|UT z4iT>TTX#3C$So5-!Pb*fjN4~V;>?L%_|x~-2&UHvrWBJHrhj9w{@90~U!2789kZ}w z)i`QImSgYs)xt~bb=^W?Z=H-)8g6LOmq6R22ucApPzh*+R!}okLmHqOR1MWYsg(RH z$fc4~74D@LVYo*jhPdQnC`pdQLv8ZTITYtW&M6CWjK~yX= zYN#nzHlcE+7^ZFkISmVZqC}9Syx*%DQys?mRLPjilIvA9!%%f|DCpP|A9INW{!Sv^oztW4HMdj9-WT?J|{?jCWty16n{bI z;T4<+Npv=b(lHI8W8sd+?^UU8iiZx@$M01PFjT{o0A7KJv=R)Z>o`Q-n2yDi>M+F@ za&&D7yq^)Mb&Z@*Ufqr4)Dp;X{qod#5YLs){R_J0*6v}5%__&lg{zQVHx~LXu^49L z2RYLq47VVlo0G$|r0ZZ4iZASAF_b!9O13f7=?aEpNIJ&NT!O8;j$qsFqu8+H5Eic8 zj=ZL^unecaBUkF2Inm#cb0$GE2lB2(kaI1ixCDysrQ}ellSeU2!K(~PUeww1sf3|J z21aUnV~(mTOwGLz5uc7NTbASSH;Zt3|0;a5b~4T!ScHFnd7N|te|mKW|NiD2{`~F& z{__20>VRIx%SWg1;_($6+P5D&n!2!8-5GVkF<7&TVA^wBxM#{Qy1!2_eROjWrvH24 z7vSf=^{4;$!ao3}gW>;+aPQ6qd><;o?X}C$bLl+BwT;7iLwB4Z2;Dh<8dokHAs2cB zfBTu>$?lZ&A3xuarhmMQzffawSe%EtQ^2Vt%Ra)8M#$z)VxbDoWMHFo!x34HGTwCcB~9j zPP=83gH3_DTLOI2YY|sH2BzdZEF_lXBsvbqHc>Jns)eH z!xmqt*$5h<-k;BDHCqCt9XVMCitPz5_86jJCv5wPh9y2HhdWfw48zqdFkIadikj90 zG;0hc2+I+mhp7^TWh6&sIbV(-F0X0f6CD zDhu*jRIi#fhN}`(sXS|_vbhj{LECB=yTCU*1Il_1_=15&Q2#=mV%pzOHB*9^i2yQv zD{r_3CD8epQ@)7+OF4ClRe8M$L7vN+L(9e+<{sqMsGcF*Nf7dBU;W}d-j9ZbC%JuJ zItI#9pfXBSFP*2nnh}Pp7~>CA|G%gkW0-*>RINPdT3b=4!;-GEHPvlHz&9iCnhN@a zIx=d8E-<&3(6!)Bjurl>VuerW`VTkq#20#Q_*BOgLyUbOXC8oI79kjBMXu613PWvT zgprCN_AyYj3xPVpRGFNml6@LfEW+SHzx|$L7qNQ778I0}Bdf3&MU_>UKKD!PJkpEC z$xC1zQ4B?w4054aWFhgY}Zm+uIs-<`x?-kj|R=|usie}318A6}fpkFW3H z!0x@+*3g0dny#po#9$>k@N=h*;(G59+&!=z@A9+pZ0Dx_|J1?o4-Mzm0p+2Q22?_b7^%O`Q^O0V$JhOw<RZV>xXd3WWODqMc>R3Qs&l<{F7Esl; zqO=V(^lYJ_Z%cVr1V%F`lhait0IO20Ms+BVgY%#UG&(t#))7dx2v$ZmNG+-*$k;=P z$_yvq@wO^d2TPH*9Zs;+F>^&qUM+OZ-3X2hJ0o(01WEuELF&FuQw*nibKa@odE)G>vkwlP$+&8cp4s+-CZNEOs9VdgG@OIVWNuH|^2w2rsux`)yJI37v> zHunmHOGK&wZACg4W$H+%Xwx}r+tK;hK~c?-T&6uNo#S91l1TuiP6_1=)o`XXU3Yay z0;?lFRk0^{I>5m<9ij2H_*|LRs}VdkJfUP3ieV<9_@izBxz89VSSLZjHXXz1Z)vzq zGUWMD6^Be=rtN3W+4#gI9mAY5Fw`j*O3o<+dw*=-c^oU2uZOjjHCozQFmv8);R`_a z4t6N7X~dpW*HG9t6M7N?sz)B=37*5rfe!a9p}#Te%z5_%l;Fuyp}$*Ya;3v5Pv4ed z>V;XVZZNj=frXZxIk|7yH^zd2;>t? zyH828|ChobOb1AK{OBrfU+KZczB4#>_B2K`j1XXYDyc|->8%@Q$d%s4-({SssK0%G z34eZhT7c=nuV&)l_Qe8BJI76ec|bhesj*wl!@PPy&~h&lfXOh`3}}KfJJVo-YA~fG z1Xf8Sl!ByyWiePqDfm?oh)DtL4$3f`q(D;gEP#er7QwUy@paQ+pI8H%gc<~tjD&4` z1x!P85nSAb;g*5;REvPgkkoO*=eq9rLYF{E@eq9va#CI-Paz&k8lp$eNGQW{70M6M z^@Kb@SI^WLt(~JVe#%sgnK%g}#*Rbxn6Vf!ZahYgpGf)BF@;|~KW!$)PM(H#a_LR& zBhb<@5^b#Zk?80gN%^BOb^ct;U$z7t-JNJ@Z5BQWH*4Vn)VH>wvWhR zP;FBSD(ae0-PnflQ)i;8z6C`UHOMV3M`C6+l1Pc^nTShDMRZ&uGV+S3t`0~dqYxYw zjnJ4F#3ZF4E;$1+3F!!lNPvHE4B|3#QC!ym&%h8`jzDl&3_>E~5F8l`Nkk0%g2UnA zCqZ~>Itpn24jz7RCb{`a;N>4h>*8VN7z8yH3njk`Icyaw7ZQ++(^oGlt~DS2uDh43R+rP zVC&$Fxy#mL^wlK+rdv0Cg-umW z*r(x&Hs4TOj)=hDK9xdL)L*nUfyBf?{ZDD!xc-*!&R|%$W4bxx#E0|uyFVBwS)|quU@YQte-})u?Y+LmnrXH?2 z0!&-^o+-gpIj9z@flbg1Y$lizI76DD658^sSd{?FlDgG?1(9RrNlU@CP~c}&1F3PN zJXPOP==c@DE3*v=jWgk#-U6${I(X%G3-3TRi!4H5VK?NhLhzY3L6aKkp`&JNY?pwV1{u$o>@EmV`c!8&s_vqPuJbr#3-#&kc7cU><U(krPoLhy zQ%XO5c8}`6i{~#N;`w(EXx(kxzfYYc{vy!bKHRu@2{&%^;m*AqctqvD{q8aC=Ls#} z#?|XrarN3oT)NzgOMPc?>B?DLzte}i_pehOH)#87xN`M8&YwSp-itjrb@n7qojHLs zXHVfgZFlkJ74+S@g=1TGpv%A&Gv%zXMArkG9K$g~!3wkFZ7_4VEoP8ook^OZXeVeI z%4sEKcGiIy%Vy>n?W@-3fhNdTG(r-6Q%ZHZzsEj{mY6W42 zmIQOO{4rJE7x7lnP~{gZ*e77Ztkvkba1{;I@i^Oa8um6e7{ZSreL4(DN&MZ_T$EF1 zaJ5L`WxoM$n)Q2M*_sisaFbELR4Q4RJ|Ng{z?za898$K!x1W9S zD~Jy2AEeOG{+91I!k_K~RW^WmlW_a=e=E>Y4Tgabgio+tJ3}x%Bfzw!q6Hfb+;KXo z5ce;hLEpur`0JnU;?F-{#a~%JUB!R=%#)F>;_q+H;g=_eaOLI75O5Q1kgL$%+fhHy+!rDdsOm5N;}J6aV9 z&jMz+)(CJ_;n~3c#n25Tm}a*lzG)WhlN(`~P=}z3iR4hLVH!a&EgA`V>qvacFxByZ z0yVzF_5Denkkj`jH|kF?m5@R(%*+qNO+7H2ocVAgAADgHKoBL6>iZE;{h?s!hM=$n zynOWn?+BRRzkP&vZyw;y+b4MY?kV2AdrYD{iofUOw*=O=k7?awiXY*vkmj<_@s8m5 z!w*mK{SQy5E{5h4yyo?-zCq6784j6!uAVyn6Kjuc_SYw*=*PR0rwZ_q2b~_irivnnZBrH~73I(7z>M zzhTj_zx)1$aICCX)B*U8VEy8|dlcU%&_ALM#S_YZhUf2IW z*@a_*oFyg^TqnrcU_1eJ@(^oGmb1o0d238iw!tI~drVca#S|4gj3c0o*KolE9WPAN z^uu%w0wuw8s+KpVYI|d{whyKdOsA^*3F{|O-b8&joRBlaI4v)zI21s|E&($aZ9-4) z1uR;+h@gKQ4vscZP?U$9k|IJw!qL?>0yTBbxcBlk{EIpXra4d!AQ#HeBw&gFWwASD z4fm^rs&^$6y~?3&PcWr@&rx-OiIp#$2&Rjd&BgAo=V8-|@z}9;ES}%qiGP1_41a%p z7Jq+r5r2Dq5r2Ps0e^dU9)Epz89zR!PAL7ht5&SW+LAi#S93+3Pbf}i<>1dsO22CS z|J~IIsIMQ?|CAOj>TmgE!;ip$eZX5vULxn}H~xQh^6MZ>2S~Vk`#f%4IgRrdPvc0> zNwikB5=`CDL(cTU<+C_?Xe<8m?{@^4{^h4D_#4IlK|uZc4}C&o@%q+I^z503-5aK0 z*T(tSv3WVl8e3rK69pHiOsvv$Lz`hRbUg{C5&|IsQ$47KK-n*Xs7gpZ!IdFOfF;<9 zl7f{a+*c)cO3qf4N+36WMbMKJ!6&y9i7j(s6;}s~_*#V3PJ>-?9n7Oj5L!MC%C=z` zqU!<$J!dHDQ%sGp0>yHAE|53yf&w{H1>+zLH=(qN2ULtbD4$?!7(g)rmR#vD0;>XD zm!R+jg4j!f;4}P05c`oD#dqJcyOcUiDJ&U~QhiVGd&hYMN=^$RD83`-`j+Zoz59Wn z+Yi8Z0(1$e?;a93X&Zv02*~dVnD1!&H&ov%0wqKAE!R)^ZyCx|j^j53bk_B=(3QSCmU|~ZbpEw1XX*rlSdm&EUxKEv} zQYicJEc0rDDg9mflKeh6QXb}I4JWs%Mle;-Gu!7)v>G%;mZ?4B*m8DR9`qkh)(|>sQ%T++~N5D1?$SMH#Kkr}hzY_*wIzYnh zn`d#e?-b6SKY@MpkK9nwfDHs2p3VFC>UnJ0yaX?v^x!Y-N`K^MOt0ZT$d&$$8igMo z9mT~%i*RVmRBT&4kzl$IySA=Ibz3L2-9q3yPa3EVT890HfnWW;2aAU3N6k!h44mxbu`5}3J!V7RU$l#M*#5Rd?`urx#_mmnm*6iVb= z6&a=k)u9Aac>-`?Xq*7k9|(v)6KsAac>O?NeD&rjxy481+Mbeg{g#~DLxRv_g6&g+ z?zi}n!1a@mCV&x~o>Td!ub-2?BUk#G!1SB|^)0zb1{ZBl0A%;e`}v->|DM50^@-qS zSPFn;FtgKS2g_jo@jHUs3lhceUXpVpH_Psm>ivQ0XPB~^{hs2V==cSgz9X2vyHE8I zglQkIX#HzC&Np0G z;xlb`4Au4!CV73KV-H0`S11{KL&q)x%4VTZw~oUQ!$1r(mOz_esqT~jtMC$(x6MXX z>l~D|e+ieUI%v3LLCHNE!<~{~Cdo%=b~nQEMk6+@3k!4u(XQ(O4Z9R5JEp)gxB!RF zTqR)6$JnuBv0=kH%$z+FTffITfm2c?3@aWKXowtL&Glw&>MIESBH1SFbLBD5^mk-6`bjXOQ*5-=pi)HKldg> z51dIZ#+!$?(Rc9(dXBHdy&Jpn=IKfN%x`n~_B8Ha+>TSb<_RFZe|a13_U*=jZ&ndZ z*P^_s1zN7bu(M6>ALeD47W|hml{!-%)+MJZX(hFh`(&3&>EJd2rn0V7>P%}0rp3?+ zD27W)E8-jG!#1%ACNWj;DH;u@^d=aG6(F#%6RzP|Sh@8ePG7o#lNYbx_=P^4IClZ( zuiwUwgC~$v-h_ngGHl#=2nSD`#mO_5asJAER5wo~H|x<4Q-6Y~D*{5|2$bKwhv`oO ze4RkcrBU@i27qM&r2Y zXdFKc!D-o;y>=ru?%9Qf>(=4ROgxd2lIk1_$KU0PlQQ)if2`@uIP2`g5AiNm{=;?{+o zIDcd{cB~mk{}_1H)- zJsF>mcaQGiFMoQ0M|Y3no3Ex}?^iRZp_quZ^V_g|MgunSGj)C2gz5i(es>L*&+Nta z&8tw}*aA%#32dwrWt?dN6l7sau`Ep0LYoMvB0Sssf!YdHiiIIyNj-@lrRf*DQ{OV^ z29^>`+Yr|<4>k#nFpjQ-ci|{um{)*lK_|j8YH;@Y6YSV`6nhRI$MpFNasTN<>^*!C zGv+TKuwKHkvzO3!`!+Sgr?77QI;>v10b6$-#!yX1$Qk%!2s>0g7x+nH@azS-ydPiS z=O3lc^v9pS!#Z+63W~Z=RkMJKiYbDE!|{fI^$S7j-$}o`C8&}!4xg*S4lMnKKj6$)xr)L8q%!8HUiNqHDCZW^xNdqfWL9l`H80rVch zl!siOqUUTcCQYA-u;>JM`i4PG(;Uj0mT(M+MMP>oRCG+>6BvrHh-j3Q7GdqWRe1H1 zT<@D#`0?#)a>1`~>)t)AShEoY<&E$Sj)#_>HMI3@psi;E17in7$K{}F>?9mIaSV^> z+VTC?pXi)^e)C9h-fz$LV5gxIs^m>!??W&xXu}^hy)jh72Se2C&@o{SE?vKene&&R z_u^ITKXd{;=lU>p`h4m%T*9WWwqxh+z4+?uEm-j7LbSBCqoKJSv56V*4T`4Yk3nu> zDV1A?`lf2kUa$ZgSAK=Pju9A1?pDLOlwg_%HP=Mg1tz1aegqEgKZ4`OPf*9;IL@5u z#rbn*F=x>-xI|_`Hy{TZLFG^mtfs%q1}Fs8K_ReGc;1;O9P#td95YZwm@0boJ5vFs zE-<(8M|wdmR<2%zE4@4L*Y9tU`@DfmN7rM;%w{Z})PRliMq}&pvDmSCEcR@gga=o5 z*d^y1WoUQ`uVW1W#V4n}3+>Fu-l<;VN@^Y=G!VA~?>**F(FH_X8L#iOxe zb{DoSpN1cvoWswr&f~||mvHC$G3?#30cCYU^Vg-uE`OyX+cRWK4x$@MUiLhF;2mbIeZr!?#D>ts9W7HIUq3(cT`T-bX7z8BlDoR08Wyud#OHb_`Rrf|9xmR0+VL;c@t$9OEzK`~;Yilaqp#T$g zZPY~Qn0r7@!;;EbKvmZQYC2ZJ^Q}(4Q3y-Ofx3YeRP;=ss%H!}EhCs)TH)b?JLD{1 z5}03MBS9>)xB){HEHO;Q4#WAmQC%A->sUik!$PP_kW}l=vu za2=~wtjGR?hp}MEmpFT|7hAS{g?qQ|kxN^RWvf>rzqlBS7p=t7MXNA=+(hizw;Np} zItj){v0=$t9CeGwD1#tqx#dFHB^rsghPXV>vD!--N5ZTX5sT zcKrD4BK}Stp}W^Fqq=DQ1=ObMh6)1%}r%8Cf4CVto^Nyf<&dvM|MQC#cYg#+7{VCTj;*s*a2wr`w; zuh-4N+QrkcZ|gD~*|QAC4z5Dav8~wm&1MwWv_aD?99GsT1XFim0+Nnz36w(#f&@l> z)>MJqrcy8ilAUQYR6}_(5;;|hl|ove$oEc3D*Z9vOH~Xc&;-_zcrp?-cD}_h3afx~ zS_`5YX2UL{4aTuG@XQ|xw{!w)P&VSK#=to&8QXX4#hp91v109NoIQIHSFhf{-Mja3 z?AQrZRn_3ag^SpCct395et>Vj*^N`Zr!jZQddTbXBQk;b+#mq*Mji-=h`}p@(Dww> zAAfv|pMUz6oatMv+q{z;rY#h-JfWoJjPU4WTK^h9zaw}0JrDOj5{7(#{+?YW!89ZR zwjuejk`&?#Jx?g;xx>;m0=6Du&^2?0zL_gj3<+j>1XEo%DCxNo;A~-NC%4n&7fgq2@^{vnA^I+&NBdxJ`&**bfZUg^}FrI z1k}gEecHDd&tspFJF4Za;1OE}v+#WUPS01kC#r58gxs1goV$Dro3`%3)^84=YxHF5 z*xW{GWgU9^$f=$@N!M^QHf-2Lot;Zqy)8#bx!^f$-=Wth_6C&5&WT&gTkE*M7F#RV8gD@Q+;SRy{E;-Y_tLJc_ zrw2uawODKFhXoFyXy|Ci)P=LLc=k9fUpx*g7mvl4bGk69s}gPP)o5<6Lu+Fd#*V1M z+-YrCGH)E#EMI`a>Q<<`M#9P_6{`p?ZHA%bOiKxp^-^alX@(*>QRR?UK`Nnb1kqLj zqDqujBq>M;sDT9008s=|e{vA)BKWz}z-lP^5KO}>;hfrxi29kZA*dRYGxa2A$}@Z| z2v)I`qY+zJN1cV+m^5i3PLqS$vSkMzK74}NbLL^^u02@3Vik2N?o#7^2@@vGz^PNc z*tKsjHt#rsVLI*v1PO*1heD2F8WoQhZ(jTgra%AkJ-*s`5W{)Ku%RCm4LlGQla6=q zUJFB@KmR}={o#QyB>b~5gZCXg!;+xu6az(z5Dd|Ff`4cVcJ4cY14oWy_ul>3wfg|Z zPoE7*TqcGKlXtwx8N1^%b!$XsRG@L}94MRe%OuE^>iY;o(CWqxsA=uOne&(M=I!_7 zp5M|jyu^<`y~DF-kI9K&CP=MCM`t%~-gg&Lzz)XVDe#P`zz{V@4A-)RrkNFD zGg7g1^$PUT^*VLtG>%h8>-5EoIDFz5jvn4EIPIU_J;G1?I1gQm*XPe-ub~@i6s%z% zoCgh$1pGnY7wUGgP%;lh^~kyCd-w_?r+uDK11mn_AhBgb(4_C55TJ&O}Z597#zy#&AY)X|uWOAlYu-wyo^ z29!h9zl{FI2%sc!h*y*xxmIFZqsZM$@Grar>=OpPtP5TBBVWlLsJr*aW?ZCZ$B zvqoap#12fK(1qC(M_}G$0{_e|e6wyE_J2JW$M>$oi9_Gut6hibc*`(3s~)@6-BIit zM=)K2p5q5`^DH~l67@!qYDh<;7X}a^@JUTr?dE=T1jZ zOa|24qG3ibU7_QRc9RI`Q4e1^l$~f3_52&57)HH+e%XCUBh*Oztf?~J7Zo0r;h|k} zq=B?d5asvzD*HE(XqlX;3O{$s_qx0a1(-UeHX*8Uwg6L;xH|ZijDuf(H!MT*k=i&J z{z>_`eftqsuU>`aYgXd!orgGk{vvwMUqEX|7rE~%xOVdvdM;eRy!p%MJlEjLjhpBg zH4|EN9n|d;p=_534ZAReC1>K>SL`mI>gXX_(3$sk|3-9i!lxScRcRei&-tFMU>4&lNtADR}hqB{{`6v@f1mBz+|2 z9l6LKet1Ff|Blvi{`c6t$h}1!sMd|6w~?hqdZjZ4LQ@j25x9nb$}*av!Uh^DA`0p-aM3G8Uho~ z6olq9!PF-K-ic-8UW?(ATmeJBB)BD2z#$?ZdbWPpw4EUN)z|bpt-|!Vv#Ik!9S%b) z>NwcL)X@WD#!n_!x|E#eCLG^)1bb~mF-9*CdQR!E3ChHo>n|{W@k*TPIZF=rGLE0@ z!P?E+aQ4zQ965Rvr;i`S*PAzD-@!xJapD?u0*j#(SSi4iJ81kd1`(p-tX{c*DyaI< zvUfFf95XRe+ZXdyy~vpc!OkfNZ>c+y-cFsmUZL9`Muf0!uKBAhda*?FAW z%o|lSo8YcvaTAypmd+=ppda_|KjZA#GXno8nwwi`xp|BGkDrj=rK?oFo29b7!A$|^ zsWVq7$nQ?;?RzX-zFnPXs_T}8mU|BR?g=Cp^x*AB0g?*S7k`K8u}kIX3k-Dq)6w-x zqEo+70-8VgqL%Ug$eUVdfsM_IVZ$E9I9zeihX!z*7Q3 z$o-X(zkkSnMNKXC-b%2E2vMSuSOp4@ z({oRi?p+83h!eAJP?r;O-a)7UB_;&)ns!Idb$QhYlQN|KXEl_9((6 zAQscWSX@G4S-U|%x_3Xj4;^CTs)bfNQmA6RfGX;GqW4cO=XhoTdDezR9b`^E1uLN;WA|FXv zGm0L8o+wk>;67@z@;VdwJnm`OJ4Lc{>vo#U&vW7E0R|QI$4bC&;1GbJtuLlFu9S`* z#<|mbxO!1O^R|s-_ZotEXd#Y?LzvrR3}?;4D2f%BZrCm`t>9imrNFeDSGQ_-`}iA7 zzxMPEre8^Ve7}*$w`#d@r;*dOHS`!Tnw=i8%<##?F{3X&IRn_Vb34zT-{sMr7LFd= zM|PJ!c#D!S5*20}nM&!Tu{4yQ;aZshwYHjGMH30>F%{pyZtS*5VXAW)Hli{O)h66Y z0@VqkLPz45SweX4iNy3BPfVY2gmx{(CAmMbeI|=dA|QV#3H>JHk}9B$9-^vLotV++ z#*D-?Mu4mInPv>Zx6=p`OBdqOZ9L9tr6ly8PI%V|xF!@)FmfRY-G&G(?~|O7ft8aZ zD^{%I>C4wFUAY=pPj9;S?#uOCcc`pwB044+7iSMPZrR12W0x>=jm5w_7d_w37<*@s zn%|3eqD+@r5aa;<-kz$usHuEjil{hFWN|HRv$-||kiH)5}N z{qX}U)~;p9n5k-CVouk7EMC5X-~RTC!0(HqROXfbA+S~gL;Uf_NBRveMbA1E9h)eu zLh=deE--ZxnA%36Z6A)Vz|`6!LY)rt^DjRO;FP(kuTdf}DM1&M={vvv{+2())@|N} zhG`&19+?>V2}m8n@QO;6XK<5$`{TU;R8gKURn_@h*#iEX^I!SzqYjIzmSexjvCoPs zeJ0=kIlq4r)hcTBbIWzkIfgLS$OE6?3?kEd6P(bA;KTylLXwHf?16ux(wy9%==>o> zoT48?TIE;$#iN zI;IbX5xp^19J%-r;;;>s{UPW_D1jV?VHj76R#*uJQR1|TLuVc?iZ!|vYdJr|I+G2? zDa1r|qj=;juGh43X#YOSPo5Uldy<4aDXSh?n0h4R9+bfJ*)wQquI9o0Rt}!Iz`*It zF^cJdd)g=_O4+|?5=Du?bqVJ1Rr2CaJ#U}f`tzUqEq$%&8%)2F^yGe% zC{uyy?K)1@RMEBXNDetCv&5qipVYww=Z#|Bri1F-zSWzyvhCn;x|GhqyW0fJVg?YI zJCw4@CaN!7X2ar@oI6)e(WrUE4p~TWa3MRb(wOd&h;!@^tOTH@$)#8(kHjf?IK!uI zohdnV#m&dT)0q4b#*h1t+&~G;2<++&lNS;%)&L>G53taEFd3!|1K&_Q}TN9=A9Cr zPYEUXl+PcYiRygIsmoU|^NYvGKTi}_7u@2z(zA3TB~xZIV%kDVr!8Xi^!bdLF^lbo zj`GXzztVW;Ay;oa;%a>>t#@wo>6Z^;ii%WVsx%=BtQ4UB@iPaGox;#A1OvNBtiyA~ zffz2zF9BVL7<5G8>e)x3YaJq$cM7AY&ZWGzj_0qGd8Ka!sPE-|qDqzK-akIkd$6c{ zw-otag`%QU@lEQ=a&aDh6-D~H(ii$kKrRse{n=su>xyms*PQkO(?fDjKF>dy0{g#x z67~C0oP_EcPT2)8-o%|{%eGU0{Q*Z$U!vvq15RJMLf!RNF4xpkA>Z}bIeFeqw>f(L zGUuzVGjj4GCeK^Vv$r3qZ)jxlxJis2IZB3FrQJQ zMsq_H`g-eStCF#XVt?2kcMcT7V?)%P4t(!j~Y z4H7GwjD12c{Bnko(03XM{il#Hcpgp#6VZ+>5tHXE<;W;@5ZVdDv54-^Y+F&LmXV~S zcW2W4#nhBvp{22$%SU(f=^+^pkx zmB6&$D7FYR=6U7fnbI4ljQ-4Bx1Yruc1k5Yn*JlEkY7BR;LfA5jqi(XNG?TVW-@X1 z0{ZqXW^%~{1{RK_N1s{bduDOKJcWh!iA06=Bv2|epQs`NqXv+WTukMqS{lkK8PUBb z4QI~qQB=uK&8^%%dy$_Sn)r0Hm6zA5xL1FVl!U&7go#oP?u%DY54=M=;V-HxGqMK- z$^95C3N|;jKOV_F2osn_OU39cpD(Lu4p!cA^yxpGT>{D@=gzTw`8x6nyRme|S}v4T zuw(ZDvhq69T`KAgyS8!U>^YXK*@C~QZpVN`j672?^eezfz?0RrzbI2tdB2G=RR-WF zD)P6VId$nWRsvJAkj@wcb;mF;AG6>rEJSfx1m|PyD=N@CS?&=-(dfzi^6&qZ33HZW z8<>QJYapd##|ofDQL4?cUtp?&^fyt1q9&U}Ih#3$p>G$8LsT9Corj_A7>&MdxPUYQ z9i=(iCRTtNiLPZJ#`b~abRVpaNIrf33a?(h7RCFC7au?48<&qoKpuKt+33q}ZR;OT zdBb%9xd8X0K>VYC^s}hc872JJBfI(E<9^`3_g>2%@BRareioR1c*E8fxP)6bZm?t9ChBS%m@|JV+x8sf@v|3H zRbJ)v$&*x8ToomEo!>=KKYMbA$4_qa{=*9zYRWi!{4mRxEay>G6U|Y%Of?F`!nu>W z?yYf$h77<&oT3SfcW_Z0wM%smslD}t8iD?d1#7rm)hZ6x zU8?GCak}z0nS&RI(>4U%=#l8e4OY7#bmGV17*@8cRY8ndlhH7@H_&`sFjlw~*0pnM`m{^^4lAJ|NT8@%dTQApVKr*pev4p zQBY^hLkdL+i3N93`wGp2axo1^W#H&3eEQ?x88>qYrtVQ#yN57zWU0VZiTV5G-oO3! zLO`O#{(YswwE6Zej2->exWe|4`Gof@MOTz+U}O%K?x7es1Pf@D@P`UuBha=A5k+1| zQkM~ET6&U@-GhCn%D8&_DR!c4b-Xgr_sK)oBb|t}uDtk3K>k??FDUT-B;V~rE&n#L zGykny9{-2kf8qZO7|g#tQTj-q{f{tJmFZjFU#sP$tshe?eJCjG&)uibS+I61GgoXP zIj+RwAsuPG}#&xP}+X}wX;<44y; z{lDPB?FL@GxXb4c&$)WxD6gMAV&jI*+$^i7Ie@^*bajaRR*ZSzhB zjF^pkd_QcX2VfD=7i$5uMMMeiqJT#_rm^2VkPC*soH6m|ynQ4W4FkDi9?o&uKWG-h z0V$scWdD$PDElmYW!sm-@|q)Z?66rB$4p~5rffS!vehP@%#?1dT)UozYvM%wIRNRY zIJnR6H~;xh{g%Gg^bMw8NqTa>mB%+5xqh>WLs!Zv6qv4#&*zMNEL)_K*km8WHk%lB zT1BzfGMYUWG3+sqWUtsxyQnY6Eu!U`FsV>{c=m%EEjpeYvk>^1cyZLoljT-{jB<`< zs9ORxM6Nr6OH$0O1^1W3s?ZnwI5eLOFwlnQr z1d;<9)yAp7<2Fck+u=`U6KMnAXm@44;y@1=+S-2aEEK>hfPUq8L& zLtO)>?ED#}=SY|CB{V&GM?~RZ41CkD4$Ppe=?PnomvOATnb^#3v_5>v(lzV3(sYk0 zOE)rWrKs1};xt@u@TYz zuJ1VV#;u}j(NY3qhv6SP62Hjdct%O(9W@yD$YMMq2jL$-6u-FP_=ObV8#V~vkUq>lPAL3HF zGr!w#j+;g>&?B0-;S1z@OvWy*fTV$Q&~}KUy{H#0=NL?-V%PUbM9(7?9hW3@oD$G; zOF`2)0YmpBjJz|{X&uHMal~eH<>AZsbR9eqJBh`^3`TAr=dtL`Kh8%(BhfSSl)N$=XdUU%!=wE7o!L!UcK#A6zQ0W7nZ` z>^^XuqbE=E>DQ0yC}DLuHKlo1g{c7U_n&EKy@iou5IVMzSPM+U3QGu2DB!1epLp~B z4b3;3*|~Q=V<*laE-42i8!v1k3h+uR;s*OI3v2gS#%Uds_&PFw&cFC z1w0Xuse_&rNUAUuh$~?IA557F^97{8etN3rAAfnw-#)+PXHj+MMU{>)br;8F4%^RN zC$w-Bh5?1>39z$=EFipaDEZ>l1gG_7+wp7U^&QL5x!cGeHXoPhLJnT2;qIfSY}vY% z`3o1aV$E8{PMJZ`hzSfGGnuK=XEA^NJhpD#!mfP>xLwo4dB0Q|+Bs0C<-C$LlW?}1MX<#@j4hIHH}~U8U=q#ZP&CK(pdl=e=D1E=^@^q;QtlI$Kubg_ z$K-qLH1cJKX(ZcBTL;S4`rEtAQYtfDon$qcBgHh*{1g0*7zJI%PDj`NdK`Hq%gD z$^E(t9*H`Ae4~bE_nQ9vr+!OcYx)M$uOvOX+rs_U8m?cj<8XN`q5a2`JZTN#BUWIV zF&5*Di5R9&z$9%9rYWVE{ApHM<1o*Z3L$AYdMSf35wJ!Db>@hu)DrJ(a-@QJ^7BWY zfB2n;&tI}>{}GN{tl;3KDrT(S!pt?>IC=33XD?o&qT&i~UOwY?^K}Lf8p1xQC@U(e zC@-(%im2sd0@*d2w{x}b7MH5UYHo72<`!kuH`M#>KUKl1u`@Yo9zn5Z99bh56Vz)A z4l(&;j#!A6z){yb3zLxU==tP}TFOOJ_T7?;(Q(Vf&@UesfwWm*p$Z(Us6IHybSE~e z7f;`QV(`R;gcJ-XJgv_P5{pTJ6}RY&AGaz;pmcvi6l2~8kLRBLQZI#IEy#73u* z5EW0)ygb&4s$DZ<4iowpvt#KpI>kq`e(p5t&K{y{&sO3+T=BKGC&WF3P@e=sgK`Ls z=uCJ_7a}4uNlQp)Zb>PJ3wlsy70LoB>(&Va3GOx(gUBLv9<**uscOooU;`yum)Ms@ z8b+(3GWFv|W0Et5urV93${mYa{$Q4G*h=HIYVL?SeOO;E%Cv?T55B?lYfs-``jw=| z_pYljZE30D;FW5^izbpfeG}oM)?k!10fWp*=m}7bGR9+^HWtIwF&Ky^Z6f;yY0C0w zBhXDBhLL#O5g}bTWEICiuUsNJjbPK>eN37@n?1X>Gj!Ns<}aAb!o>^m4+_A`$A?bc zdNO17OjfU1#=SeOoEK=095Ip;Cr+?bD!Jm~!Sv|SlTP_Lc)7YTWAY5vt=Y`7rE6Ha zW-IHZ!rij(5HH{U!u~mnIBgO@u}3V)qKrcOj>j=NkKD1#un-kul~{y+a1V663+dpP zLPysuEJAvs?UId#b0$WC-7pfR)pBFbX{Ue5P*I7 z__M%H0o@nieg5NTj-D?=(<)f*l}txbrwN5U`T6(v>WV6#et#*D{IaClFTZ@?{ily= zU<*BmaC99bF?0x~k5ufRfBk^Ez_)r|We%&T(qDg8gDeaiJq>*;e>FIRy8tq0$VA3Z zU#J4~)!XO1di{b|uU_!-rLz4>U1{d=>zACZYQQh4E1E8e=y-|}^~@BdC_ok1>5EgL z<(`g-dnS3kM)CH8DC3Xv-XEU|OhtkIBH;Wd`|a}=kp6Qs?*}EI!zWRuElr%Z3FMqX z5PJ+`*=iBOX0sqRiGtf;63lv0iW`kXWj~ztqU_d*t+xml)fdJF(-7GYV!c^_Z2Pg< z#FMRJn@xS#XyV64^FTJ3$!kqQL=^_GLyqmX4B@b$A1&=&X#U=YlluOI$+KCvqm1)a zO;k2Mw+WoHUr2 zo-;9u?2lpWFbv|q1Q{_=0*}Ox_%qnZC{d^4lqQZ>Lu49dl@dC7J(dDh_ktlTUbBg& znrqyv{ZpB?UK5ypYv%ph(>IuYCF$|q>pZwwOKWRA`^%~Xrjy8?x|!JFYp@hpnx{^} zRLn?GsF@Qm%$R_F`nWIKX_K%@67`xk3d@A?#0K@?s6_%pymLtGIhJkv_A|V64B;U` zm|EFjVrh-1uRk{S4p>-OV`6H7jh!_?!9F-TS>xvFNMd3FyLRm)Jv|L8D@!aaEb#F3 z!O6t~V^eFam7wkBu2?ww;b7}dRzVk@Jblf+nX@=2mG2OjP?85sB6-MUTt%4_NG0ee z6;(vBg6D;qFz z2twC7NR7j59hOO0VSg@^H}YCw`ux>X6{IRmUp?dbi^sfp@kq`++8(KQk?2nPnL#*T^x8c**0KYMH=vIX>GWf;sZq*%py< zT_UsO{3d;0P8)=f>lR9L(?iZyR#QB73dQ4R&}ZaC2929S$(U($>sN%8gFO~DR_Ge& zqot=!bX*jJhZi%fw1lX*NRm>cF*esl&sZA`eJy^})kM$45GQwcEF2th_w{AuAaF0MPh8@gQ31Pd0l()^!Z!%&6>$MV>jkU zr_puzG`fzNPEcY7{UbRv~ z;NOWKom0_uPb56GD-T}0BdyyIGzFCU?(t;i_vQ2FkAH{hr%%uMC@|e|>>~xFk!V?kVH285=h8W}+jXAi{g z^Zex_p1yp=y%+Dv>ODprhdA^^nQFPDVc?Z5-&GW;U%ogENpy6}6J_2LLvbo*tlr0C zQRB*j;)+WBXHx@I2uRzSc-1Cf0qmzwFKK@85c}XHEIlGc#Z9H<`a_m3UPpRT4#_bo z3>`R>bLY!BRK0_DoY4aA-PpF%q_HzG8#iujPHY=Z(%6lyX2QmH8rzMHiEZ9F=X`gq z@BRz3_PlHF2fxRs?bmPvRJ!+p>CU>rMtvF|V4eMev1eGAp#H~s`m_7MS~pWFl*?K* ziiJoH`~68+Ss(`UtANRo-j57NI%a4eW1IwuT6{a6224- z3S=DYp8ZPq_J8bZxj6pnkn*`oz$l6wyTV6>Y}B^A4DbNiNJHUtf!($;#3(P8}N2jJd{)EbQPj7q2QRuF;T!Eh({C^?{=RB?-nkn>(iTxzZ95J!{+^Uh^T z7FSM(LW&w}^iF%yiZ`Msx#-?&>)1~j8B_4#&#EpF5NL2|Ro4_~9`%PF*4EZlC0D8N z`vgZl`!Cyu!|5xTTeODSWLtfGvdf#BK_f;X0$w`O90NqexIF|k95;6s^>h)h+h23? zsjB8gU&rRXPeq-Bq7`|yJFQU`c*&jGD&t^E#+I2hIi1mms^$}B%P@*StUHfSx^X$} zg9mRVwfIuYlN?BB@uV^SoR{&F2OGP*zdaZShXvIbKe*}y?g+S_>r2Pepw(0yyF2lX zyDVRNiw@hQO%F?A5)=!*8b2TH3Tm`6-WMNf5<$Ht5leoiDiVY*H0ADefun~u2DAIb zW)CLspAdCBA=PVE(*ol4+c(jYy$%xiZL^FS^A{EeN<8_^OY!faFQ|&=A`V__iTc> zfl)s_iHonipDk1ruAB>r!;4;Bb(ZdXIzB$F+itwx#_+OTjJ#6^V3h`7mv-T$|J(Hb z;ctwrlN0XzHi+XB$=O`jK*ui_?N2St z)gWkUY7x__dhk1&zg@tT5ge;af}Y?&6r zM6(`W?FZqz2^6f%Pm_y1`kMLPuj)TSiqLAE6Vv5G_s_SPkr!0CZAo13I>Iaj-Q2iq z>YM+rF2c|e_?BUk6=SDruf2CtciP~hQGjL5Q)95zhv|I zhtXAUl&O8UVACCdQK{K)j1}^`%Y>^~bosN7?wVFr66jp^Y#^@MR=AxU(N!u%^VQcQ z%`|ApaWArN&V8z98W1}^`8I#)Etdx(E z+{wM(e#6;_4)*=HDqC_5c)yH1%-*nSEy-t+)9w?-k%(t@%T}9D92kVQHy}{?Ygos2 zVZD{edaRKA+mjh<`RP>HGqQoaZ<_rMt9Vc1s}=T*ri1BK8`-I#cjSJSNBy^^5LLmk z2c#kG`7Drc`6q4^`*2ujAPT>GSycT#+E1i}SeR=L)QeED@lU9KpCfcx`x!t?&d?F& zf*7v1s&GSW$@LfWQc=<|JC`#sg*7QHol{=|SvNn(Vw*2^4oL=cB}$fBtOeuZChb-l zQp(gU*`16zZVp(!uyYZA|~ZQ(Xz7}c7sin-S;N20iASGV<+g~>chV*D<#how_^8}@{Jd7gN14yp#f zcX=Yni*_y6OQ|iA+A`4vwX>X`JE#Wy7J?7`wp=HzoXuODosmIOWi-DQ^V9(8?wF@&qHRJDWjqeh<;@2;j*R5GPihU*1xu& z-R2PzLcp}pbuy!I{7bv0B5*kIXYc(Z|F(X9e~gE&K=#3OBAdmzg7E}U!U3EG`7krv#&kV z-=6`i4`lcYgg-&9G4#VuoC0@vc+X77$=Jn?8mC1+WOUfKO7b>wQf85CRcfEBAW0BB zf!?b)afd>{)TUn6N$HRvKu5ln&>>7I=cFI0^ zY^Y2nGNydB7b;mFhjX;%w!?8=Sgs88L08$~a%dEQ{VU^}F2oK?BE~v;K0~-A5`lSf z^6pMhB1Be*6^AP?=rnI<0&PEO|J*ml`xWB;9T`;BMambTo*PtpIyLpUThFO|gyzmN z0V~;mwKe0)38;fDoTF!DP2DV|CKI$VwzeKP=C-}My4t;ca)U1BAk{d)5%`8 z<%{18`0e{a6_+E}R};D0qQ2SR^2Ee(6Jc?^<38W80am?3^P>VBLT2j`Y{++Tmv%4M zC)|+=+OBA6a1M%W2_$_{jJg&Z#pI1`Y)tFG z&PBY(UumMfzdSup*m_+)R`GofU#hhfRdg|k=g+DcCsrCSRn-2CJ|JvMiK69@U)*#+ zqVSPa{NHM8=e?EyW+#0y4NP;W~$=^4+dc$-DjfkW~uwn$EVWdfW~#Ro1#b(lf?16IG{^ z5+0f1QOTw{!J>(4-t4-pBZp6J(woAH>W)T+AFm|*{)72omMxr?{d@9p@YDqyC9;B1 zDf^pZWRCAEpHlBtiI6D_MtHjZ;+L zXLch0p|3)Pbu+anJxsJ1z_jmmzUT#xBj1#=`TLYF3~z3a47}g;Qdx{7)|mM?IteE-|3WPie-NnNDDS(DSz^m*jY(EHj z-$!-QO(p@HxX?LrAW)`Yov)V6lC`=B7A80eLH@=~eodr4XiWS6irS$~pWa6!jPO9! zWu=|c-xLaac4>~RiH<4jA|epo+})@D{lm`pFq_Ih9iPKHY%)X#!bMQ2!re|bCNtFCyRFm>=N)aw5 zWu(+lFKtqiX?$ha|IUAY0*=hrF1JKbr5PV|k!( zdO1>4%5KjO`=;OGhV=kj4heY{`ECZSc|S)Ty-b?qXo#O4#%ljY>!YcUfMb%((A0VZ zewv-oH57S;WC(=)Lyok5z3XH+i1=lH3p#275_sR7bgQxZvBqWeMH~qSjm3Iedp{<> z7Y(Y+_$8fql1Iw5iQU9zWizvZm#4Z_yMPq?JWz$`bh5>qKlOHEt95FTd?_5)27>#< zk)jdba8dl|*J#_18hpX~_a~f9r^W$AE9+v`@zG3t zhqLv43y#{dN_vx;Oi?8QKKH1<*c1G;I@Q02XF@bXmeiwv{hWGvHHQ!sQ73(v)+?14 z=s!`Bm+M;Gl*x3*t#xqnvXvJW^l29(emLHlw0a{`sUttHZ}Vo`CKA^2$=Bjbh{Kbe}0M zTV!b7J377FG&WN?t2_PZCY9Y}Mc;zWK-^uPMUj^T?gz!=K8CsQ0@zO#)IcAlqeFat zqwM#5M>e%Ds9#!T@!n=XuHBK!FRuyky;8Lpsb3A;OD3*-KO4%EG+{dV%{b9+di^Hi z?=!J)%k2dVA=vf;XcaR@2V+U-8Hf~K?nR>n?CH9TL`a$)Xg>32jE0f85%ItX2Q^B6 zb-a}{IBun@vjKBBYy|$jMnj1FWf}M}QH>j)6CSEZB^w%2YU4lN<;uMTTVjfp67C4b zu7m@vGfVK>oGNzd5#p)h3*50u>5Xp3gA89aR*@CS06}F)&(CeDRc^HnoGLHpcW7?v z>5NJ_s^_?Bqxq(z&Qh_AU|hB23TQQDHm#9P$POgylvWjJ_HXnZOjwYR3!fOma9Fqq^4Z_h*V5o2d0CgKIdW5o;C9m ztLOR*t)L?yq{#wN70>>cm3&m9_H@)Qsx3>s3s=IVVmI)A#J-yfG#?ME*9OJ^ExM8P zNH!?B?o~c*pB=9~)>F`H%Sl?`Ewk$ydLQGi+zd>uK!9YP#dWEWL9W#WYXMHtcw>tu z7e_(SB?LjA3x0-$m!~Apj<0G4F}xVXS(m-oM>YNtuWxGXQJoKN%GIxM{8=B(d)62$ z#Z8Ennjk49MTRr$O3#b3Wi~^YEv{M{IbnW!S`7VbHJd@p^fa~pV$b}ay{MeVoWy-z zwei35KRbvGPOmQ1meuQ&ZBFb0hB}Az)ONzN5mSe~6`pxV%#%R|`hg0;C=B$(li|vu zH__PLnz*^x#$qa2qx!STa;(N0sRC-!7mPPt3tthS=ZtVm8DSEW%Q#2BehFHk2<*@} zd)PF8dB}UpO0NqzqUiR=lzNHocn44f1PmxUl3(tr0P;i-TlNg6@-}zQ{}3BOYKaei z)Ia>Drl1F=eg(e2brMtVq-}1D35$;SGJsR2zO;5+_&&vmj#+wryfBF{x|%ICD(z>J zepF6|r(Aq~P|vIid|4F~d3}$GHy!nSVMe}9Q@-|JxVVnN=oSWte7f6ZyP&VI@1JD~ zhO_mocLzgp*4IMrDG-m9)4_ael=H7!x!=`yi>en`~uC zS#;Mn2nEm`2co8utDK7H(0T-6B@sk~xP-4GD9?D^aOkWf)V&|_Ymzectq6yor}mNp zu0cJ*F%{g3W}a-)Q#=V5sOyhfXs!*nQr4O2ND6qCirJ9E-P&5qXW4crtD_dgsFbzS z!mzJAvPxN=ssc1v6E;wfXlrjzNXZ$De(@|N1LP7j8F|DJPQBw0c;6nv&4DLNw(o`E zQ{(o>i;;7?A0y%FB{M|4MrQ9;Gny>`it&axyiTmCWqsc=Ysl(vv6jHN9KKJwna4IQ z4<(#$@N*xe|KFk3q<)ZUZQ$aqy`Q#T>tCJ9ZU{d7^~ATQ)bquiD-2pa>ok$i46Tp5 z8MkEqv$piZfQn1n&!D9*w?op&dcT!PhsGrinacAoY9fVNJadvPm1mku*(T3Lyq+I- zDF`nuDN^uwpk>YTWxm%?Xf$ zUmJ61&jgP#Q?um^G*GCM)cAm>QkIIgsQQ1|3G!Fr29q|5e%^}oA<3PIzxP~8g3&1% z+eMFr!;_ZG*@Mc2hnaGNjcnKyB(7@}S*3Yf1f@lYe(yivIK9)_xS7gcr?!v6h`LYjJzJJZw9IHiNCUI}D$(trjaI^n4u zB$c1UBEtsal`?LosHxNDu`E+UtRoW5$Ohf8oUSS{y1Z}2=JzQc#3q@sy5ll`DyF+StIr#qtlosgCA}@ zS2+CX<^bT*Z}m)owk@X!fSgWHh&w9TnX5H8IWkNSK9d#cux)_dYfvsmD$-_EatAYg zpv5~&r*#+iXg%Cyhjg+f<76qYDQJYr!-OC)s8$2ld!>q$_mXOL*~q|$wM3pmfLP!v zqzWc*flJCLBhSu0Bq#_fHTA#-P}LQLPv$O=U$BZr=DdWfmg$~CYcK%04ICfZZXIv` z4Bx>O5ajTgXE#Jrh`&9T=`>(R)59n=pz=k}0j?Cr>bE}xb?v4lZFo{4RIQl}UfZj0 z`v0xXl#ctiUIgxMOz%e@{8F60G;>ljOc-jQi3QNAEUxWJ^^MgKdd2}wbxD1FKK`Ep zG;>CKZdCmusIV@WlE4MTiR&ye$reTrX>cYiR_>uJ#tqrSA}onf??Wd3g4#z}23z0K zOE}u3GjCk@>cVG=-A6g34Ih^|5pDTk)uA#~w-8-Z)7ZDZDns_e%&xEmT|`w{nsJ&` zM?hU;5G|IQRHz{hi&}m@u@l)YMNAf1L6I4*5}(%V@i8$qL;kxYs_Y2SwFt1)qcP~$ z65k|=@2p}UG_VA7{IAqgi_CV~2FXJMx%Oy)dc3N>n$LFfQclfl@0VNR5TJtPj<0eL zO)YP#ih&beNw0`K-*c|@Zvyl!u=0nJQeG|Lvpe>k`Zv36Ohf-?-i^RljpQAKfG5}G z28=>_QN&k~h|Jf=CjybccgjmYIuLC2hlctVo6CeuP;Q-5GijQBt&w_?ZGaX&{0IH0 zM(d_;P);FZigxEUxsBPER%xhQ`km&B+?(q=V8DBR>40Y;{eI^MNKy|wX)*8@u$;kI zLxHlQ11zJGO#vHrA=>#}1}~7q8CIk#)zxwT21P-XLCs_@K(ssM!FzzjJKmFG|M3OG z@0ET?Dkbpo*6=i^beo{V`$Ju1%#~Gx+w?doxXhEv+FO|4?UWP}p0GHI!n^j3JJ{;o z)vs`{7`~L%Zj&@QNQ@2A1G8b3lB&@tiwy}A**C*-8K}*;C`v2}YXtP+-sMqPS?c6O=ASww2mykXZpFLLgH>l6ciQ{ z*`rCmysgav!UW^~8Q+&Ez%AmlZSnX$4?T32%&E>2?8p>9?Ehkt;zVDKlEoRNaV(W! z3^50!zlKYjChIEf)ub$0#Pl-!futf9zZ>aIyn$@Uc{R%XK~vp#83A|y{YtxiC{aH+ zASz@L>-cWrcCAbQ;vGlsv7W z+amklzapQ2o02i>Mb0tf1FVb$bNO6<+v9sUTInF&gkhyV#0jQBp28oc4nQZ_<7jV5 z%MRp0(>wuG7OgkVZ?rGSpKbRW)+;(URS~*W#bU##HJb!R1a{1VK*+OYnxj zov71KNb{oNscPMKx!o1PmuA!Z5>_zI$oOHog0$uPCWo{GOH%H zb5mthRJj1FVVULwoBF&{Yg?Rr3U|3d>%V-ZGlpv0LQreUN@~`81ox(YPpph`>(d?) zFNMhV#$4K(&+Sh=<$iL}?a6ve)2W45(CMb%ZTi3P_<7gnJdxdvn?<37oA_Me?d{!? zweFAL_V`>^iSy#yq-K$X#Z6xj`dV8-rpq}T@7~JEbyst4hsD6ZB0}#H4*La>16JLE zd7>LWcO|5q?mRW{7+=6K)y)B$+1((^DW6Bs$k@XuKuLP;Gn(QMmw>>R*%^K;G%bz? zE-oR?!^6zrCYj71+(c+;W~i?&NA%vl?Ot4Gk|S;XKnD_;f}Yz_?YdY5f+|Dv{mj_p zxGX8zBZamHR*)Ll0TvF<#N0eIHa10IOHoT1hQ(jyH}pbGrMhON{@>1*W(Zj(Y(?DE z>bBUA@#_L$_V4lpl%SwqM~9G3qYFcGHShI%zwD&$BcRL|3EzbOiw8x#ij$*)X_zS{ z0NbB~COhBRjv=hJZzekNBleVJFxr(CQkq}E#Fnle(tX!cVtC7FJVjBUfc$M20scM} zap28N@9yXSW^vnmOM=?}G(ykOYMu+oeVdv=HSCC1+Qt9HWlZW^N0ALk-rGom{IzpS ztBN8I1(4JBHoW#R`uU4_pPk>>;|`T8e;hREe0j5{mK~w!Z=D;;VE5*%%AGtUwk>k3 ztcV-e_*C{uLnQ}t;Biaqs$;Tm@2`xnldo)OKK)+;ZlCR$#$9+>V z*A~i0q}5J9wRZ$Su;jXhx$1FNcxAyP)hDmhY|pm8gUYPi9?5^=S@$N6^1PFM_=0P? zmGogQ@<)r4wo8`qsdzNtSLv)Is$?v&_ZJjCocRDdmgRrAb2tMwTZs|HUt5w&Rf{ut zCpNO8_wjZPPfb@k8Wl1-!#I+_92S4o3yXm4yu5w={onGfig|8qkiW-D=Ag4;g;xi% ziT4H1&$P)^M9kV0CMy?bi5ZPnh4Q(Eg~0S z9O%sbTy+%Bg>tcl1IsZaG1jk$s72vXDZ}?psDi7rq{@9K zgV3hplfs$8@O`XEtdJG%{v&XgKx-6#$Ym^+d{yHI!P!Ru9b;Jj5$8sqtqIeR6F2++FaXBoO6UVXh-0OR%p>lC~e~eEy zl5p?IM(?S?ggg$!I2J4gpu0%FsS{E@tq^;4x;0lBlRVn5Hwwj@)3T=+iKO>oWT!{8}_%s45c?)be>k54}labjk<$$ z#&|ic4&ckI+D-B23CQSFMwW{Ut9Bw!gvb?Nyu^_Qr+XQrf<*vuRf#_%#T^_;$w|x`niv(t|FvzN)4baBa3oX}F^$S&m~a_+i9v zIqd)hWQlyFHRG`>-_)EHNq+=!MlE(%5F?GUby6Jp%Ooy%@{PE}x@rrk==gs-QWqCD z^%_A6XK!VbmWRYTV9@`x= zOT!F9h!bHqiJN$Fyugf!eS$Ou=)qC1p04TITp(wxJAmTsW)z?|^?z%2FP_J({za)_ zAo$cX0ZGZcZPHSkt%Z{K=(Gq zDB|y5%TYh6(2g+`F{bQ}Cd2M$$Nr&Lv(>``L0&M01~M=zd5P*;yzGoLDHXK2b`kQl zT=dDV`zgr=ZR34(Q$#{8xHQy5H(N6#jQj2Doev576^l-Px*}m@rr2$JZQ#-Kg5AGW z5hG8Em`Ai79L+WgwmQ|uz_j0U_-^ZaFzXKYN+6V4+5N7pi-SQ>W_S7fjaGrEub^*8 zr`etDfxO%FWfBso}F8^!1II&4@D2i`!3-zrCx zyfnL84QUV0N5&w)98~Jk1EMH4392{c?+| zag-C>X+(wB_(#7>RY}!CMDf9B+I{OAh()(pNs5@?A4^zfyl|*x0ebG75Z3pGgz>+QBtuub7Z6gtM z?VpZSNTX~->d2SDde+RfN^hG}nnGrga2>a|n{R1z$i4US7OYrDOl`tH%sMO!Nl2zO zf~y?mV#ZJ=aL3eNjc_Se$QdZf%*WvkX|7lh19Qa{F?_7LY#VmbVY#>U zm}H)3qX5*E0dZ2DZ}*4{yS#_W=D-ZynqyZeX~Sd!Q3l~`b3UhBcuHb1&WLm+H^%NR zA5jApmx$Li^i&b~HDB#cnHN-&M!$_Tfi{{V0QOjk$#M$(oA~~N|0cyl%Nt{9EK;Ej z=*&k$phP{Uhv>M1k8ROnzA0d*`>1GgC40LPxU@C}L4r;o2XI4-6sE z;Vzx6p)^dXkn*s=(3HX6PxWA}V?CsAXOZ%%fu}n!Nc6BE+os6T^(l816kdnLS-&&v z=(MSAA8#VOAth&2zw(r&Lri7Z~%vvG#w$()_Te~rvpB1xcQ zJyQopHFkxf9#^ry1ZO_ z<11%PUa6JvyImo_g)5qj9N<*0x#q%Uq1SnxVEsE49*B^wPiJ@Mk%`YKP_E^}Ve&-g zbEtJ$B!Z7K>d&2XKNT=gR;@;|YAFuT85rabMnchaYVCq*?!g?K&>5aV(OPbLsS%hM zWMU77p__DieWhU}ajemxBu-5p3C)z|sTP&gg7FP1tLWiMVA{DfcR!AWU}{AV`LA<8 z3}^1K{fPjzEH|=jmg0`(iW@1kci6I~Ap9mJp6k^mAlNuGiGHyO@tfR}n)EF((UCtx zMOB=nbm+`?wZ5!)+isxsbU03E4A#8oTcivV*X{to@k3E=7mg zpt$)*3LpL$zejCm9mp3|r;cDXTUDPEfm4}iLQkvjENt{Y4Ws1$TKEsic)+T~?|Mc< zh4#K0>Es>SlNEWQb>EYhm!wvY)HqXcz^rqWDU!9NI5gKY#bYVzhzjvJB4c|RB;JoZ zyyrPx!`vmtlec-_s^5280v_A7og5IUSq zLkRt4>Au@g$E9sS!J~svJ3AkbC;gf9_8TxINU%MdO50+u7agpvN$gd>Nh22LTk$eR zv$;<=M7;Z{X;rG?N%Mt1mE@^L>{IL7bU61xP$kzDuu}uGV&ZkljHLX)cKl7p{CGka zMU;Efm~2=&>+8StrmgW#Yeo zTXQ#~8{vfc+I;B{lymk5JHd9Fp1Fl8fcX?_^qj8#xVLcYF8{3Dx91tJH&(&8RFl&x zt|3OIelydp%$O>JF9J;_Zpl+0MfP9L?1~Pp_Qx7%D!eWaSOg`vjU4PWG*;p|!&`5* zkYpyacem>a#&fz8-ooQ+AEupe6)KnNElb7NvB;ohk2qr#))nX&uSDNNFLfU; zU8ThhHq7zh!r4@of0rjIwiSzPtWcI=&>Ou?=g}xnS0!K7{gzx;@<~HWOa9E(-3=Gf zw+)A!e02Ta$?4gAC_KZ3@|3>mO95~mahQP3aB!Dyir@R0bn%#EpTD8beU(+$anthY z*nKVF@#n7@U*7R_Nwft-m4SJ&a8Un2ZS7`sA zC#mxQ?h>Pg`5#nu)j|p)Q!6`KxrxMXE8|H%XC zjpJ@?55ZsXnE=D$ZH2)uPc-?go>o=Zl&_iFj_lp?I8!VI`H&a;JPy~lI`E_PtU;j89CG7FU@tY9|Pu_2#Og*w)SI-cmDBKJI3^mc-Ms1ukY z%@hv}*`kf4Z(k&Z3++EP*ii<6#48H5#YRMBVdbng!eh#!>afZwSIbhIrNUWS7UO za&={81VKT;wY4>M6buaT$a?!Jfn{0m=kzi8ML8m3Gp@y{lSSNvcI43dK*?{NBUj|bCiYY7OFX}o0ilpmW zo6idWSBY_zH(pVd@RxvzZaSxK@kOdo(%%{F<8{lbN87zsX(5QSoXgNvT39oAXw~JR z=qzOY;$Ksk62kouK`KO+RZ7mB-4b!bI>Rh`DCq+>wQ*cGojk?UZhhK0-BzyYp=0MG zl#qZ+E`tYyAv1)rM;mh(~Xz~-(L=<460zGF# z3qEjO7|(Ns88Wpw5cdTlM1?Ev>5fq=>6e*LU2%Glw)I5C`j**r^aZJDRINm|7G z9<6cqGHk{;>0w&Z9RIFhrqwhdvnIV-*+1?o2J8J*kg`%0&HZhdE!`$$Z9as@!06^f zv!6+IxY9$5Ubf5}V$6r`W0)1d<10v{MjC%NQq&IDi*ee*sl0^ zYY3~s%MKZ)Sb&LXP48nj-&NvTw6$I$mQA8 z{6tyR#?y{0BtnrMcYyq>qyoB!k{ImI-&<62{9ic9w5k!k@UnZp^hdK{p-rZMBw z_#`f5p(kXor>TLDtvjERv5IJG{Xd*1wH93)YlG?=c}IvjaagJq-c9o&;`E5yCS@A{ zXo;J2$@jF04ZLVz1ZQOY>SZbKH+yD-;2F-Fo^SKVt@3wvo9@Ybm3}sv4u~}bPWPs8 zs}H0D8^S--(yCm}4>jP^`JELubD`ruF&-Zy#VQu%{n9*^42c$NAcd@ z;e)PnrgyB5G)i~%-64-Pqht4=bfc~o15jA6w8|U zK)>)#g0}{j?esbcF?cDs6ohAP6vU?3P+Xg}Sv8uSZf}W>Ga+802~OjpBOvfeH+iWE z0=F-gn!h=e1+?5e!T~|!zwh4F%1TSF_U@)`8OSI52poy{1Be$dge{h|RmNEsi9~Jj z!4>61-0s8#t3$@@#tF9k$P1b?O-Y3Oj3Xjmss-?~>b*&3mpkPEiZM+sWhHK@dzUNk*IcB7XsJ&v|ZA-6j+ zC%hV)co7Lrf~_(KxYV-Cwfc}_a*|6OlgS>krsTh$VX!?s!bz);0`@(oDv4KT7iA7r z^MO`t{#tI6g&3=Z#ck8q-PF8iv`TcHM$!0KAR+T4LdMa=-ao$bGfsePV5R8I684LM zf%Ab|BfI*1X`J0jL{dq0sXAH1o_kyzYYU%m1aNn97^}!@)+Z|(Mn=^UXEI}eq zavCNbZjfRst?C#*8+6Ilug1+ce1Sv*VE<=2J$R6L_TxB|JDQyjN-TlVsU4p^?CRw? z6e(hzN39f8rA<F?!Jj;n zJjr?=c+g~%R~DCx9{AP;6Zj;i$0*6`;FC9#E3V5C{{B4@!k17ox5ra96f#{;jTQ2`O}``Iy*aw6hKzxv zW8{ede9wh80w2el$OND69=dCt=kPZ=KYB(rY`s3Na7gxiXf|toF+>C3$0O@4TVD>b z2&(kA2UeTaqvdQ{z2!GbQlo6S=Xto**8NC;=D8Ne6kH)bML26j(fOnY)vIG8bC&$R z&-CpNb|&CBv`6n{Y@8j5%yMSW{x_Mg`hLww%H%;8F;=40;?Ek7+ysg!~vwTSPx z4QkL%f+Lj$JfIj_LcxXBWKmV}g~VP3ol-xMr@LV^H~>)PDRpPmQ48_tv|?`TCXp=IvHdYQGhFV)MYSko3IpTW#mr9$a~sJxK5={PPe=+Rhy>=(Mai*& z)|S0Sf`m5)zV`3WKwrqJv{7vhw^|YT5%G~}Wy2Tktex$nh>ENfKF>D3RXt+|yB}q> zk$ip!&~t1zd1PccP9E1iy&Iw1eKMDl$w%jto%Db^OP2z^l+PJo+{uGljnL7t)@!5B zLlxa9n5p`YVopQt?L^0^UyQLg^s;A7oyE;Xy%A0NG)*%2QNfjB3Pugts|O&?W+wT0JCpN zj4+a66`n&XUFx=v(t&dD7lQW}=XtJ7lYfTH2DOoN%IB^{O)+A9ur2UD5I!JGa3=@n zOtM@#H3$?X&}jS-WU$sAm?UprDCuE`T{`*b+g)ZFWuqZ|qdVLv;6wYmH1p$vn|XS+ zp?{rCA?IARyk~wmirtw#I7KWJ&kuay}|V(EgwHBpy%=ee8%>f2&`1q(*p}Y&%UYs8F;ZX2dO#j6o>9@LNAIl?1C1O}C+y>cYd{>B8qg19-Fn^0# zjv?nxeGh?mdLGrl794TCRmLejFd;~1SUvI@aO<7q#e-Qjw)6kxggPbD$AM1v;^jt$ z&F+MsE=X&-^{cXK7D%a-&iO}rkwa5qvYmE>|7o3+dIm?T@&Yra${$m=3F>gTDb65a zjR_I$o^IKy<)?$0im&bPj@4o!J8KX_tzbiWc42|;`L6oq9dSum>BTQo$oH?L(z=`ekNolKJ|^zS!e)tKf9K% z!i1XFIFSQ7tukm_x9*p%hE~g}dT&uG8@vA%gof(>-|EqNx6ahrN#i`%0>JwY|J5hP z>~*jcHMc%2AW2J2yA829rVAF?OfXhg0n8yUdoG$%dJY_BGWcqE#YLLbwuQeKx)U6b zT_0!Gp~ucZ1UH_;8=Zk8hZG&By4a{L-jJb3Xkr5z2P_PZj}yAOss#u8%T9fx5~K^2 zO&a2Gd}nsgRM2Y?bEMGf=vc2&74KcIs`*aWfQYddF-b;LA~UU$W*C??7TYXC*lnl-)F8~PEjMV%VxQl* z!1JuZFk!l7*Jmy*R>NOYsWJgdtTMj$+ihz%{X6EU6#S{_{jh(Fs1E1r34nA;2ZvYn z$*4pl5!=)wqvMocxPsxvG+jZ3L}@ibm6EMXKGNkdZXTyAkg*23bbuo~%OZ((jWK>a z`KEalAC5BlCa^!^vryoBg!8VP_sczh5^e1MU6$o|Cbx#cn(x6l1SWPHM>JP*d0xU> zsoR<@gK<%Bu^?wC6gYbD=Re?1m&;+1(W+eV@Kp#T)zH7BmyfrGm-B=5u#E;_djvnJ z&qxqn9(Sgv<@)qj?0i1QY&ST-E@LjqA9`Moyr3hOJ3jj5{_1#v$>VH|cJeD)w5C0H zy3B=D!w@X)O-(nY<#J^MDJvc?cf7D$R{g8{(9ik7BTt$6vsRCo_WX#j?e}YIPGqYm zF=PZ;`-NtUFc~E6f~<5@RmGOI?#lPh!7pj~@Ed$tws%V=Yf){|fAEmB$%n$0XBJht z#&2$=+?`KfrKyRPlO9?{zeLe^_9Ql^A6iyW#t%xhumMyTDy6)u!GYv3v3zAvQkioG z{GqfI_h}0M20OcZ^sbCz)5JB@*=2Qh#wKf^WM}Iy)tOU^b_a~)nA@tG3y8F{S?q9` zxslU&*S0DNEc7V7!_>G ztC1C$x_cV#AleS#f7(ut-d)2+>AtQj8IG0%rOEV{(TmO9ks;+%0iU=i5{za4E5>$Z zBT(f#xn+f}wf}QaQJM`ynk!!HA3NcID7XsV>y}gGl(_BW_&iya5v#@w&)!NR?WNZI z5+=sEugO8BD#hN5)7nPHHV`j!`{4Z1ygYdD!REtS$sw#DZ%wVfB>UdmtsgFGPz5MQtP-1uqK z9hF3PH1t>EJfCEp?<5t^#nMy+67Yy7%KhMPs6qxuI9a>Y%pcvc4yhZ4)0N0qR^bJ1 zX{`&spT+dz{^5M%ry=|SpqQB=d4AsmJ{YNe4a16j%T4mNjycA-Z=8Rc9TRfWiq9>< zmd~;FlqkL{(A&0;digfRMR?+lpO(Y)!tBCisjaz3i>Nqrr3El{&%`5LVQf<$I|$@+qsrPKsD5Fyxaa6 zx)@UDD4$yr>E;cI2+XfGS*yF)m}1|=;p4gr+_-p#=J*p5@6WS2Y6_w~Kc$UUKxVM8 z5>_rdK`fi@Tw-d04+$?Xb|v&CzNPft^PPyS z=;#%j!k+nlbq%GI8p5y&_vSg1h3WAs+2 zaKZEX|D)oyxwc2PFP^}G?qUo&b1%uM`P~0RmQ;%*q-=&X`eIx@HygD)9FrMDmtgAg zB^PO(c-( z^1c^$iimo!_sqVA$SLmrN<^^52Gn|9?@T|rK+V96R&(#1kxWF)9zmS7-N{{E zvpsiUAILz+=RS2T<+`(EeCIU9MmM*c)^=Jldk5Z_cpk30p-UTKu*Pf*t7={!EO+NW zI>>gA?M#WKDdI-PWteXubJwUx+CBZPIRMB}bJ?pnfAPM3k23>q62LMAxlkGlrI)&+hM-! zY?hPzOZO}tFPCw}@>+F)o3h6a!se?ZW9fWwn1qS6jJ^zuHYeK6-YA0i=LI#s7?7fy z{D%p^%8^{$cg!isrX{l(fFU(UrJb9>W?pEc=eS`$Qb(iykGpQSM+~Zie$ACYyTJ;N zh4-98Z*-;c89y$kHJ?X|0E2D+Hd0NWOeDw$47pp9P=l*+NHcmcRxJEV7(gaJQ@a>w zQ}NTa(;>rULGgKXT|4;Qu&xINKh^NG*%UkISyS z>+95veLOn0WVL0ttd%U~ z|HIQ+u(cJf>$XrF3Z=MH+}*usaS85H+}*7dx8lJ)K=9)3(Bdw^-QE3WpMB2FPsp>@ znsa{heaBdI-=QG#BrbWHH)~bWS6TtyY9lFR|3N@fNJCO!EgNgc$Q%eog@_EUqX*U&0^aZqfeezs?QOH%@ zCSW&bsB|QCy*~VCgK@SSWq`yC*k>=2WY|FT1Pa&}l*(WT`T5TV-OFVG>`6XdUfpUq zb}_$IO;?nw8%EKSpO!8u#irO$;bcc=QliW08#3C)C|1_EW1EAm`!P;$oUSpphUaXg zX{cT2W|N+3v6i~t@$tZf&Cc6A<@1i1IHvJsDTqmyEYJ+2=MmBdjFg1;#R0sIcQ&-^ zg<&~7OweG=pF=O~6vZmO-t>X8OF^}?w!R6yhn^fpZ-VRUwu8@}Sh`e^P5Mku)cA8i zkB;_ZQJy*0&wN+3R&>lnnQiRE5Cbv7*3>oN@?#XmZQr0Uu^=J_sc?YwJ!!W0*SPNi z4!GxQ9R*tF4t`HBb*&FKX0Jwiy1!cJ&D>%T1@h16t$2;($f(sGupesA}6a=fwPsik;d$2esZ~h!_?Q= zwLqzb0`}yEwY{Ds-U{u8xKGQTfSGBz>TlGujUojymsFjcs5^)wY;ytiPo^Xl;#QU$ zP##MrU*IDHf`!GXUVB!OC9Bi-thxdD)Xk$U#ie4ovsFC&Q~rq1N=i#sEvLIJ9G)t} z5wVY`4$T8qv2fmMf%i^HEt4eDs*PTzc(jV5h zFyCqZf+HI_Sj^`*Oy@FC`@B!j5hnelt*3{Hhc^^ENTWGetg`>PHyC+FHo?X1yob`` zR8Vqz3~|T(lo5TLf>hLJJX?m9K*$ERyzy-3Y(`7p)@FBVS=lYOIi?hovGy-%S+CpR zmelOL{+`nI9P4m>LxvWVgFW|Ow9F|FkY}Df;8DP|6-hzLTg3Y=A%7ch(t7a+uKnVK z@Z&YD2Qy9n@n_uA#eqt#YC2Nh^z>^ym*-th-SbsT)u|8TL_Sx3W11lPZ{z3drqjun ze9dj!TZhGAST~<8)DhjRY;DV~OakdR$4xU{&zNxuhj2USgX|`sA%-n}mN=2YzEK~z5kCc& z1Oqq>n0xsP$bOd8lCA4WT^1^0Lo^E-iOr^*BDE?DU5N?71BJWzvGOV?X<*$0BO&n| zi4Sq(XOcsb<&-Jg+Z4_=C7N%c*)DVVgYcpJiEX7r zDZqi@0BCu>mDEzrCCf)YxOQ5-YNb$q0oGl%_9o^B6y$LMXCCN9v^7hrYrzK98j1;IyalJu0(&oc<`oP8YS_f!TFlgW+(n39ng2Zs zU5fXpTnk_rSfG;PQX162>?E;FYy}URztS})S95dYYRYh|p`eMSS)e;36C4ou)sHdFPSbTlQrOL`!!p| z7oX2_?m{@cxy~Ca+&m<$e+NJoaR!w;2gL&8hNZivtBP^iWqUbvDK^L7t0r`NkS_c6 zNJZ4rjO*NQ`={nm*Tn)~LfVU5jw15ajTwYuJ0-JJ8&jg>WBIN{)2CN#O-<<*@J)=1 zB*k3zj0EuWifzMWjM?y549)#4aCe~*H07~xGRrY>gK;;Eq>574{)s3)oTk%4!(hEq z`%anjHwm4t*HSuAiC1`u%GyOWPBBE2jGXP}zxQxI@_ zA~EF|Be_mbDiQDIomz(PZBbC&zw0g!cm{nk5Z7+>CW30Y$=T}|4SYUPicshJhsV_^ zVml}q(xQ`y(A&IpmaaiXbUQWgi?WU9kfG3|68@>mh!JT+h4JB{_V&2H4{m6c2G-TA zVmLsXqs%;8yNIfMkwLlKj$~R1Xt<8g&i)9nqzP@GqVT2o!xzXcsaI*}D%sgF4OD2D zLl}nLycNDINT%oL)I`0Rff8nl@g#~?%H{kvzFUmzjT?A(V&uH_*Ej>{vN=MYGCj3x z?5KGqD{P^};9 zIbp&i?2)dxpDD{^5al4pPU9>Qam*RYzdQnL+vfQ9aqx=@8<3q5gVVB4^$UVhFKq`| zIf$ublqb?!1ljF~BS^Xo8bwSGjg2OYa}e=*e2(I{{XJaXq5G}jn>u^(l?|s<3Iixe zUA4^U=SF5hiKW3Y%W% zAS$SAq*_Q^jCW_Tf*oulh2=XjJ8iazb|T4r#-}xu#Vo^)GTKA!&vqv}fdAmW|DA7>zh-$}PbbO851|E#4)Mnq|?v!oPv1 zq45ym^L~i(j*#;l&!Dr^4zEr(nczBMMG9IjQ0V*Qj0JQaPDq znFf-_nX^@kWSQ}-^VpVPCY*o(%|8zcNI^gM$1&s zbW89}iZmE>@@|DGjmXIxXV5&FVyn2w7n)~&5|!S8hZDQ71l1@BKjBPG`XzB%vN~Vg zNcmvUX@2}k%2l_L|SXO1Ufc1vj-FobITc(aV)6Qhj@6*UlH*oW@e7O&J)>vS1g>TPu{-P+{8_nvhqWR z3O4rUXFOwaI)Sl*=u?X>TA!M0WoC~b!8CWo9o@sXzRk~9!UNY$UjVIyGdKCoJ7_9pe>D^W(0HNi&5^x%Wg2Fcx< zcPQEA@Z(hVk;9xnvd0`&k7v)s6aF$E6}vG*G$x*k{!kVXuh-Af-<#W;Gr+ad+4l=M zsn!X-AF_&(CW@2Z`3+HFEG24K#oo{sP$CDd_0Q7G&!2$Q?V=b|5EvUA*Auz|))N9> zl``L_$0Iy4EchP7RlF+`64D8>cy9_UW#r4a3?6%gJ{T;2kCFVU>pKJ;REMRO;ps}B zY4iQs#+<_;3NDdS;eqj{=A*gmXUhAqU-Z@t!ZSHYW5fwW)5V>7u_BO>36AazqMTTa z=R^>B$nd@@^#5|I565sNl2I_~#{6-L>lVj+FFsfi31L3?fI!g1iekg{zGtita1yQN zcC8Xbs{-ggc!B?I4}C7Jmumw>_Cei%;PRwO6jSr{u>lxQOLnc@7g2I>XE?Ax(f~eh zxG}nIWyIi&d5>wq<7_^*n=d$5k1ZqBkU=5V03OIwz$B${>}6?kj6EXKXFRAIX11LY zS7t;CS_^%dQxapC$m{s>yN4f!`CeT>;Gb<4;88WW*cR*z z(i&5>io)5zj{?m1@7Eh8@&m0g}F*z8UW#H6qA z+Te1=n|v(^WmC>`8wLXY|4`emYCEj^MpuGa0zOc+4*mVtc$x(`ApFS}|FZ5+P zpT8+H$his}4RfD$LSf?hbS$aY(jso>Rw1BHB9hZy_CypzJ@tZGTQovkm?La7MS!S4 z#)Apb3c<&71=T|DMe5r=mKIS^j{#iKz=J12WTz1>$!OseHaYZ3m5>?v9Q=ce;E6PA z_I6NXt&gdQHp6fUpFb2UOHFKHO@f|2TY5i7;_u&M<`4J-CaP4czPEVz44>Vfee24v z{Fl{>3;32PMCd19EODMh%T>)yZ1LFPi*j7Z%$EnIaJ6Iv^|N;bV9HU}L}8A081BCS z$dC5u#c-rfj`D%9x>_#Ru5)am0hrEk(j}XC*^$M1eDf?OK;OUjP4T@`{2BhzUt_p2 zhK4x}4D8yorC>=`rl-DWKn&HrWfrIeq8Jw3WVZx^&*D>~2tVOOgv}TRmF=AFXzQ(6 zoHE0MLEq{*FL9`khm3Zc9@kcs;~uAb{zl&+oYixBY|BvMaWS_aSnXBm3Swz>^16#D zFC-|P#_~BBD{H+w5fWBy@8Jy^H84M{3uIgy1+Z;(MO@!j2ii~Ei@xNcdvS7di|YYC zGFPHAu;Fk+_L>_S66?z}29l?C(OHxh`PxiP_D5?H3a!6bu_7z){j_G&fuRRRC7EEU z2IY7%NN**lhu`%J{h`%l-zt*2?dAisf@(w9B9G#Aevpk)H+?7h<+@;fWyFXB#AWyY z$B|)E?!BnelLQhqdD_V2_&%jz<(f%4EfsdQK|}}W#m3shnc<3*Z6Wwe%c-0tnuqY`CCWq2&w1; zlhe`+ZoGbe`tYD(Vo`$zN4eTvMqGf7d+4ffV>v*`)Rgkg@E<+s!@$alWVTXazWHB_ z(@zi4rEzf(O};0%@?ke8KVm#MP_|UM4MAI>30YLW8MgFUWIg9SCj5>vBES(s{9R@(!c$>O6Bl!0io}kwXAC zgvVz4NQld%I|}7N@w-1UA!3l344y18>2}5}{^HBRnWGB=?2SM<~!T_a9rEntXt5p0`I>p$!E1__e5BiJGsOdcd6nRD)zBs8oybQ zgv6O4kgRe_g@W?F9vMj>6C5Ne$T%Bvkzh@_%k_72!~64FP)z)tWX3UzcY73`p0(f2 z3ND{^WZ2&UCba4AXNGnvHxl+Oc5CPu&|soIzACJ2v)x2UX<7eFUFqgTCuyQn?d{PX zK3@T>2b)QcyP-yaz<*$>^XLQ!1uyXIZQrJQVgeskPOfakLG56EJBjdq&CD5`KVq0sy{5;;jW9*S-18)v3Gl z7(*vAv_7~jb~(6OQ?y;tA`*ibLsNQ$OG@@AqA2f`&!Z`!2W<*{9Ij00IK!v26JL6$tw#hDbUpRMRpkcx-DIKKOGFd!mLYi44RfP z7@-MIn_I%scW z`#nRRkLQY{;^UvG`-uTA1>(`)Yxv>!J$wZvt#rR+Pd-H^%+2Kv)==)-pl_>ILT{>BVukyURdC?TT@F!h%eci_jeEq7$5AADYI%F zij=?2s%-n$Qx1)pX({)GU=Vjr|4m?=BNlScX^>GaEB~c_wmyPmYs4UkEyE{8ZUizY4j;~uB7rP43DQlmFqBI0_VqQk zw~tPUW;aIXQ?B=`IB1x&T~xD5eDUgB7hvwPTECwMgy^(-2tH5f@73tL zUbqo(?p5#X4A|NUxuw1pmatolyPz9150*t)gemGus=pa$ZTS@LXG;hMmxg_4P)tA4 z?*DCmFhEc!_S3F!%4zJ|I%DSFW|j&_O~_J#WE!i{c#G>kKhv<=*-Oi4hG=+Rjd3st z^{l`K`rU83wT2%0lwl4<8E1Ih!9o}V$@axATDTunp0rnYx#Q61ZPpL~yii!FHS8Nl z{Ir2;w_!ohJDg1>{jfU!83lums@|%vN8uiX+rw^MdgRvPDD$ZK`2yYZdb#vNk}G$fafgOyrvtA_)TK;g-PNX;vNsV`1PQ4l*vlCk)`tI?g7S90)MZl*`d zo*}hX93zPMeVjwB@guVQnVfC_S)!}Y=Y(lwMkoS7tu-NiRc2UCS=_X4ip!;Unm?lE zmmgF1Pb&E)XW@C4MJOcA|smu1G z;x;Y7`fOxY>GfdV7tNW!qXt!uf~t8|@7o8$mhK5qU4)9(K{p7XERZi3CbaU}E93ThnMXoq;LYCn^mkLfy#~0eds$ zGNRz4qjWYOu02hUgJXio@M<8P8Wwz!(USy@O8qAhwWo^YP6l{llCxTC1prLc}zdmb;^Cg_fmdW!wEN^1!9%&uIx0 zbFCIt>jB@q+(@@UEE_R&PUhgzyiKfw>2lyPFWF4Tk1r1Y{MkN-=BvNx;wHcbQ?Un^ zm=m|`eam9I7@A5BO`e3x_|%8l;Eoieg8mj z3;=bPj&;0S?P+u_h?XnE7ugR%$d5~d=Kp1g1!DaCD1`hQMYww%3mW%#Q96{-cvgFF zA6mz$fh0fg`p=4}!{pFjuAMN)XVY#S*6bKIsfWi0U6G9li1BR!?ov?1&=)(a!iTm*iw$v8|sQdWx%Xw z!<_vz+fHr4V|+*^6e(4kaWyOe8rQEFd@%Uq!l|L5c(UvZy$|09xL2l>ai*&1_=hwQ z-8nt!*d)Rn?^;Zm-)#! zbM;3$VGc!p8BpG)~e3!aDkI_nUq zGhS1er!G-FhVBV)h_o96@KPEUbZV^y_p7<<0^VhZt3@}Qba3|JE(DbgHe9ytajTXF z8&VPVQ_kyd`=!JY6}q`x;qKC@V~px!1~cSHp~#0OBo#;hj^Uft{z#z~ugiCrm)-eF z2Dp?{qnYVnT<@W|GI2X4^neFmN5>oz{;NRmv3FWum%ECmrwMp?Au#v}quRP|2nXlA z?~T%#ZCUKiVVdez#1WTe=dHu{z0W=BwHow4B^|}!L&acga|zB63)Zjp8G9FOm{Bw7a@WsW@gb)QM=cZPk~y4Mi4`kx~ippNKA5%42oEa2vhN+;=hz* zV&Y1TW^G*^Fk3^7Lr592$&{>qhyFmsFE|Fp_A-3Fs90MMr`kV}d&j)#U2fbY?j&qA zPCp(Yv0U{lSR23CemrQC3j6krwZ*54_+q-^vFu;g<>GUhh}=1^vLSs2qKI)znY-60 zZp$1a-DFK4nv#vls)F+4RH4}UZwriw_d(d8alM{Vf@>hJBW9cDxkl z?+N^j=gcjp!yf0I!hDP=zkXXPii(tkQ3p1tr@sEwO2k9TvTihEoW`57wL@Y~| zTJLL3A1nN+E!?4j-H{gEwV;sh8$l9O9MC(Y=Yv0|9$HLn@d>_}C2d?}sh6^|6|`Nm ziZpCxC>0Ezm>7T|bM$0N1{qhPA6PM#6VbnxwA!fnajG_YXAiKq`J~f}z^JW-0MnO4 zBOcTp8rF6PPfJF1Yl&RXsh|Z;`R%ci6Jht1#h5Dnstze=LQNkF(P4cGz_i>P+dj>& zZHY0&V#{VW2lHKnL4m9>`T7Q=e((+$czsv*ZEzrY-#Z(Bm(RHloSED0Iy|@tw6ZFF z6wP!wd4Cx(Qs<+;+vyE`-xPU&Z9AXccHE!XkKZtMe_m~N7FzFkKCgbHW;}jRHTCz~ z9bPxOJ~^0rzsTTu=H}PwI9u;8Q&(7ebM)~63%m(ah_Aj2b0i}2I$U_1=^LIvZtoY~ z{`XxO({n$HSc`(*GEV3!Kn=a>JR`Y=457&m60&FfiQak`Ggn)m5*|Owo(f0KwZ%EV zzHvUK#F+GjF$;O!rV@GPu(im0vH%}0>~?)Dlya5)Z8<4r(EG;!$)0kmGdTLHY76*~ zOwOH?<0R*Rg>Z1dH`!1==|-8lQ|o?4HDk;B1%XKC*BC>+^9^h!v=wz=Dj}kALClJ~tc+HUjG(7^&pDHT zKye;Ds2rW{i>u-{`9nN+IZ5S4cZ0+^eZ4y<(}3HDh5m^BBR=l%V8`#Vz6 ziO?epZbKIXGfrmSs_3oqedyY|@@2>pI-&sTKwPy0u2c2ywHxi=JGd3Coa0N}-vb!R zGo0@+N(vK%-@*1ho-Rr=-Dtv;)Cb|gtu;ThOO;UR9a~$C_J9oLiuArV{MdDMNgUQT z5sg96fwNo?rg>FaWO@Rh3oeyq1Vv?~d4M+BC#8J-^*_-PLrOE+m0Tktma{LXK=|El zvUS;HH`F$CeF~al&i!g0r~QA7jc1~NAH1)yiV?y8L!s#8gKmjpjg zp7c<6X20xZZJE5d?4fjuXx(qSGQ?f4Cc_5IlyP8;0-(3&1xWCw)N{NWJ zpAF@5nq#h$wo~NZMx+h#TwEhlzueYLz0{bB=8AglcYdOAdJf6VM96-RdF|kvf4`c^ zz2f!u7HacUZVOife;N|S8&b+HoHt5NvmG)b5v?+~W(~a6@@w;AS0)pAnetQ_zBGV; z+8X?H`XuV*^HzSHBjR;Y=pVRRJhD6yu+S;wv@vm}bvGtQue<~4;`+BLQgr`yHBe_pH;ckH z*QTa%$q>O4q+a$5A&U>bL64$!gN1!GrW% z1duCMt%|NE!@#9r46uo~?(~0^+d9pL8i{eL{rkc`t^DpSk-qw-p+TL- znzKI~%aK~O8lJ0%hDfr7Zy(juLn{&Bs#kgM0Du8!Hwoc+BWQ{&5i;4gbJkqS1ukEf z=Fh154^hq`%Nie*2+$&1N$oXBTL*v*`XB6Jn5wzlCUcSwf^02j$Y+-@~z{MvET|MErDt2z~MlHJ?Eai^OHDopWq)QPk zBtja6(?)EUpxT-m!|lr>j$gGSX{uVzA$Z`7`?J`l;hTY|xR)83Tlj}AzP)SzU9zuv zCrg`~FFhdS_X3nhnzEOztv2wfh*1S;Kbb=A)kJN`!<*a3ALZUq>t~?j@~W!vW*t+&Uc zSEIO4?Fins6U`r~s~$DZh)u20C1 zm@0uwZB32uw~h9YMqMqG=jVS(>xS2LwPxH6U;{Gjo4dOAX)4e6-)rGF7bY!qGbk*w zd#BWFu?HeiyR^f=z@n^+98Tv^f>3r_{LKzp4)bekX%>+nfrP)zXy)k!reb;q#fub7BH4i|4vi`^(3RB(wvpgYbrqPdttkxnKneaudp3lj4;jFa zdc#Jj3&QL=7?rroFR6ZBn4XwFX(sKM&#Nl&B<__!*p+{uk@U~&0S<+$?{@YY>V19i zV(9+N-$MSz;DXj(0Taww*zj&42&#$_qd6F&AYmRTW~=|2NWfuQKsSS_)_iWVJ*cRV z!4(<&5z%FDlmO=B;OR~+IGvDm=7T!?m}k#Di%K9IfQlTCy}A0RS)M z?*B1pu3>n#^JxOywcp0}=>jhg+>LIU-va}Q;pT+XmX(#&1-9?0eg8x%1nm9!&FyS0 zDJVig6%>53Fkm&;jsTMv8ptw#rLWFiJ#0}W~o>@9B zV`|d~L;&p1>IorC;DgVEb}!P84}?suEYK($y?t~1-#F(TAma~*b){|hzdnYKJ6(-x zfF|@6Rx4>^GKG?so6i33W7`)O@092c*_URPJ_xmXy4g-*LKpj7MAK37E&7c+-*&V%G-?`ix+#M zj3C7JQ466KT5>Tqk?r~I`ls57{C$L2+6noELTHWZb~khw$h!6pZgm}mdf1MEm24>Oa&H`aa#jRD&!oo3M^dp8U**o+hkzM%GWj zTG5WDTU-HxR>xhM1Mgw4S|(uf`45%vQDru}mW~35uRP3(%O&6_oRhb;e}|{uHhMaJ zca8wH0CkNQMtafNx9Wj1bvd2Na+|}j>lFVwo4Ms%&+?N0yg)Did4V>*;b1tXxK_3% z8giy>rE7_=Oaemki95qK>g10DS-kpA-5{R--b zp+dB9nr2TCPqS*hB~m;sWThu%M@}+AI}65q2$$ZVM;U`?&IWY@992Hsm(FW!t{fqb zm5VFFXyUk`fLN;H{!GLTDl$V0Pw=AlMHJ-xlcU24c|f>f1{;E$nZ%L7&#m09-MZ?B zC40ui?OQeXioL{HKV`gVG(l_`gc7yx@mQhB5h8qmS#?*x#MX!mxdEOc?$rDi{4cFD z{j7+LFvSKcRdhAz+VD--=8!O@D%mXVe$3r;s-bHqB*%D}?+76~o_Azyz=HffplDzx z-OLi~3=A3})J2b1+EY*J0IQ@i@Py!m;wOR<=12~v5wqn zu>L0Q2WOHGqf13K_xN3KLdyVvVPYieshW?Hm!peeJjXBFfQazq^Mz{p+m*1mWVXlQ zitI*LLW|l#wupa5R1}Jwyga|>9hxPJzQxl^te2n+ib5egNOdu~?gv(Kc(GW6j+oH0 z=xg%&+YMI0btIMqF~Ew!sop87r&lKk4ASQuvN=vQ#Z{`+78o?%t=M`PMD~L3hBbm( z#?3&LCJ#F)w^M1vg^^09qebcEP<9R`<=_}OYnP}+nz3|z?nrO3o+QcLz~IJM&>D5t zk#Gz^z)^a?vADee0WViYB(?oAVNscA`TDYCp355a6M~8l4GMdY4DMwg$bi9GR~aF& z6~G3&@a|WFaY+_TEEjTo7sD{WiMxVB{<0$&AM=a3|-;$ zUn&1Gu4mnUK9*Cx2?_8tY@ z_T-~swVc_MEAbF(|J%Jf=8%Wm`j(gRA_yUTOs(1D)f>@gjq2TnN5G?ph1r6}PK($^KkwI8k5|V(bq%(L=PPCQ<|doO|~ss}?^u&P zjzF}k;3-`{U1e5J`pF9R3=%ecVy?Nv6Vv{&RVItxz8Rh4m?DLSLK{FmGO-(aBUdWy zWwpp-Os=0rk1`XQwzlBr85xC5QB>jy6N>=c)JQL;Z3iz;XQb{9rS1CO0sPe%aiQd; zYW!P_T+~{v47VT2KH5TgLgxShLLh?UUVLz|P58NBj zG|d5A5hO8%K947;o)qK&m7yXf7B{7#_7td7!sQG@qsHHrqNpi^kXV)R6kFyc)ZL|B zu)h0#A;tXe=SPQ(j43G%hlzaFzz^0*sjskX+KV1*}z^GM4#m=s3%WF>`y7&tj zOS|z0`;5gHEf)`>Otz@6Jq5mbME^lba6=%G9jvagqsP8Jrz4HPugRI;L6uQmwn%;B z)M$G9PGcDYaK_u%(pbKtC&C465jq*-RyI+f+EPu8*s47qdz&v88MA>{@x``TFGg2J z1V49tj4EP87J)x&-O-BE?Rcjijq}so&Dea7$y<4yw}9D*+mLdeVTMss7(WW{?LrF+ z=k}9_14>jvZW{$os57`^R^5h&%l0mPp0wJ6?GH}gQU3{i9+2L;IbCBK85i$@p^ez$FP!e(E)-F z3yA!L|8|iAV__dMSHV%2n7OP+|Ekjr_HRoAKh0P^hhN>tVt)|v)k}FkUkbznRil&c zoWHyriN1H4oWnNcH&xikYYe@qmTco~{pMM$)@z!-3+(VXC9C!}`;;B=#(7u5_L{x( zF6y~PwzAr=jdJwqxigbHx+I>gtK*JU(PaVS(Et1WxyD>yedABk8QjlVqKS=#aA4-A ztt9Tx3pc^|8PVp@MgijHbioJz=*Jy&vH}fLmt_j(-;=gE@-7B&)eQ zyY^2l{py)Ym|(JdC@T9zrbAe(HrEbg0$V{SU2oSzO>f+$Ct!9H@tKdt>^v!kMJzc^ z1~xX99d;V-M2Le8F5(EA8jR`?8``agw}N1Mj;0D`u0c&O``S{_>awfN=oah}C#Hcn zkK(HeGFbV-Z?3g&VY5p)6r#6D{97_0R~+JbB3VA)f{lx-LN#Bfho_kC<6GV+XLO~1 z>UA}x{1_W5Y_QA!@ZdeUHW_2|dQ&1amu|gXDRv~SRmbg)n`*}?z_w~N0xxfy3aof| z*^c+NzWX6&%9P!4lT5UFcvOj9a`fv)1_&nYV*vVlHM7>%=KuQjVBJGJ>-3x4NVTXy z``F}2qFl35rz=1h6_4e|dZ)h{P|Mc76!HFid$wgnA+u>SmLt}*NaRb1CE+}bz4cLw zc%UHan=DFN;9D8a0vbJ^chOXx7a=cM*H&+XoLspBXW){qgZg^D{P{Qi@{X~AD}mIi z^>8J6Usjx-HSjzETeDsu)BTi~Y-I*q(#u6JTH|e;=oDYLdD6|r=Apm*TisrRCX_>! ztBG*!?7*8TH`~1)OkX4E9rw+vSUKiu?)jF>+F~rSK#K|5*oudf8JfjNj>>BI+QHsG zk+@5L2O9|xmMp82%PNcKQ^84oB^l&gp$td$=|9WLv7qEJFRw?aWSeQ+sI~v$HY($CxGbws3~gPe0lm_^0=~=0i+m$KDMZjHsb_QX3MpF zjbDI!I2^tMgf;_Z{$AzDX$5jd9mo(Bj2YdWob>*6ofk>D_4o(q)Y9v6LrC<7ZYNXk z{+&s|h{?_XW9WS*d41ybK0J)>Sw8u&ZTL(%AKduvmJ5!0HBg8FX$Io+oDAJ#<-H{p z@5Yb61D+9+4()FpLSCO@GhX*6M7ACKdLMkX7Mk|U?ae zl4yN?@5rhSJA4tKm02zk5aHH;$3REd^*tIHNn1}YdVl@DjiLkpy<@8UH!Z~pdRJ>f zKamngkl+(8x1{g-uGrLZH>E^xPZLw8+o}UZ6zfwHKt;wp6y*p_!SLpFy%R zP7&gIXem%pRXKee>4V^ZrWOS0OXzOm&7{`fg&@lwM|E`1<0ni1kf!ZbyRNxa!k(iR z!wG`?+Of{IVG6l|tFS(Jb+NWY+OG(r*8fl_zPa>Zv4xp9JnKE8)9wZzj!v@o+v~`7 zp~7^y2$?VoyY%ICZc+Lpq9o?)_WNUUVHKNdW!KWTp zADe*?W|w+K=cU4VQE}?+cRPxBn1m_wSbKN0yuY|=R_OF)BVsHvPHbH-R1*j~Q()wX z?)E=M>w}v^e19E1GTtLQ#(yKm8T!4~99q0hv=A25-`L-HA}8*Ek+^&da$h&8KQL7I z;lb;-<%*+R7b0mIGtGcg!F~vqw|$ARtY)$vlaY|;lbAP#%~U7;wf?BFHgn_Cm}kc8mJv* zTeo+;>~(_Ul?dA_fACpVK~RlHiDniAk@wi-X*VI{1uLE1DylE9tJ!!exKg_DsmXC;4%t+3y+o*>N^u+8rtFh}1d%i8P@_IK9J! zRk`yK-j>I%;PUBq>y`+< z$R`Pgmlw~zv=><0w^ZxOx$J2-NioG_$YI2IG0P{$eaFQ_f$wOf90LnTibj;iV+}5g z98~-S6!vTJsQh_p4{=&$|B2NR1?)2B9;%*WbB2gld?Kw_ZB3h7jyJoKrC<@x1?wrd z=zAp1xG0st3}khvNKY#kRU6;8ET8|zNxx*hAGVf%=fo9gBnyWP(6 z(`v!0LRe$2I;dMP3|$yux>APq>RJ$>uKstj09K&UR(_$%0A4@X(b(okap`47{LVl< z`_#%n&YXp6`IQ<2kU>LWV9)Gr*G%5Rr|dw+5uz|RJ*O#nUaR-ndJHQP$=M>>m;CFN zRZ;Q3^Qd?#8lJ2JAX{YyFJFInQ4taa1uR@a&abf2V%{FpZ!kGADe#O-OcMk6M}MgX!%WoJ<=% zY3R2`g&tpQt5URF&ZadW?nk}C|H!U!ne!{asj+$<0KUMfR%szn^a%Dj0NT!|P#8o9}2#SFT8pPkKKz z5sg;hl$T)vZH8|Qm%75rDn!?Xe+8;&G>KxCFx8-nc2x*Wy?6sf1O*aB{lF-%(l33# zSKq%PFz7vw5|luKPLkBmY zaaAQrpy-7~O4`T9J&Mn*7Ob863LE)ZwYDeYODqm|xi|(GZ0NpXG)6q*4>TrbKdy8k8g}DnLQ=C~KvEr^e2dOCFp?9u&SC$XgRoamOZjfadS|9>N)wRFm0i(& zykE-V%4$s@ZrPiowgUyE!ZMyJ8f(A$&_A3WPbg^Ya`WXkL+MdH*lAa?xtY%<$jzBM zQX--IPcbS`)Dxi&q)a11qZS=h1hN4?qNqefM zwsjgj1Sh)Qs0~m`5=DOq-FH1h*%+ski@J%^>N}*uT zOJ@IM(jC4nAKu{=X%%64(*G*(*;?z;`hlr-fs1t zJ4Z;<{_*W`gS|#*#rX5fm?JgJqh z*T#=SgDPnKV+wWtPry360~pwWL5fP}5d~Yi@wb>k?a%d+=T^IyRrQ0pH}{-Fq+g2_ z3AA=rd^XP<7A@}T>^y}+C74}2j{srooE_`aIriH=v6-JYkP7V-RLD0uh{GV9S^{%3gA_*ZJZUB zxSgy;*J)MPnV*Xg$Bb93Hpk*scjl`F2^3lJwV@MlK2=&m(5UD0D{GMc4Y0R!?;o8- zWwgpHoJn|f`ipvgtSem(OdgsD91ObTl%j^8X_QcQadqXUhO~J)KHVHjctkU`x{WOO zoPpO5&r6Jtz5z>wCjzbj4nzjXE{-aoDqSKQUPrxvd#zah4ZGfn5dx#y#&p^K2R*I9<%7%a^-rJFm)S3c`gs%=0JSM%&c(Et(u< z#S>ikVdt+V>mgUzVu>46~cbkTb3M^#z9(-LQXt3b8Jbj&?%7=xQgN#SikF`I#P$(vG3wXA4ao&Qh)4 zHMgd7H&hGsa>JomJ3-WEe)`Zb@Ki$@|2Tke?=-xXvu%GLYtSihyIGxr=SE`{L4(4H z&eqI_Yh6HE)PMy?w#+yZEXva59qXoURHTga|nSGO1^!pQa{XNr3a7Vm`MQpA>j8uz_#2N#i3p1>~ZD?B5PuOSEhxn2!h`{+E|* z=h6wK(T)4@t#<#D0mu0lz8`BdGAVxCEuvj3*V3W$_L~c9E@#S256g#XYy3^Aj$!wk z;ebGa`n`$FpUJS}3*}n>4=_Q`zW-?dKmG?WRp9*RPe0Ypc^k1vl;7{8qO^U=ej(1D zibC|K*D6zOuqtqb3f7>u|6Dci>#bXPy?Zx*FJ+QC_V(I09gzOHapSk2rA&2tQpwQZ{bi#i?tRbm`uo>$P|J{MFBSE$Z~TV+>DcE#dNo3zXMZQZlRnXE#^e zJzNEf&NxZIr8;&fs5&|uwa!IqGVlgd`xQ`Ck4iN(MiplDlZfl;VQO;3(bbcmTG(l0 zPW?k;sII)r#JoJNI0SI2*I+W!THzfWkDE&Xo3|XGysU=G$~x9<*uvJGdpUOMoYpf_ zRYM*=ahe@__H*LQc@4N{MQ!VYnqw2#0^8uWqQufze^3g&i`Phu&*IhY{nWb0vVG!I zo;>}A>C4vQ7aGULO}kmQZk;x?q`bUbi+r?P)Lli@4aQF#gRdyTb}qJDv3I1sD8mIh zJEn^IY-h6MTX{KO=}fee0zM?fiv_MWd~RvY0x8@l3QRYJg^}cGVyaCee$mW^X`-g4 zn2nV9`Uo7oNJ)w%t9b&+aS(Fl?gA_)ujCBUz~2d}b*VL3f| zcHzW{6Ljd%fuf=!Ezrc4EnC>RV=F7xt|K8M9~XTvdu^jAHiY5knTp9h6Qfraw%#pq z^l5`hfY`TSGGDy@6@vzhBt@Q6tvFVt@_Z|!zi1NI2 z?IylaE#;%&y-Gby8))9e6epizs&XKAJdBX*_M;MP(c&!?B!QICelxAX+FP>wW){c z$L{=o?2jWLJwLaWU*(1KPsR{_H*6N)OFsR6{uF*Sq<~+pJNKii+ZP9>^V?t@|6+*a z*OQm>-RhlidA7dLPoGyEg=;H@H|`M#l-$X;m_Z$`{{p_0hM)bRLO! z>q7c2+|8Yz|BmI`53*?eR_?$4o_QO0ai-=WC#4X%@$_rvuiek9@;j7!r}JXbTJ{K_ zs_xyPxMV11H+NB=Zg_Zk;qK*uPH%&)y_GgR#v~rU8YpikN>nWyRO!1=HJR(DYSSAX z1gK6LOh2(!QEJTihsR05TEj^39IqOKIM}HldNnl0Ig~EFhH62@CrqBhhAn$3tGUPg z4i)Okc2!$6tKMka2Ud@kzlxG#6|CRyYQ?V$+c`91sf% zj^)wjt&}^4GpS=|Dl6`?X4gR+oV-NgWe^t^rv*Le(xnUS+O?DQRN8lJD~hvz9H}<^ zMXkTF`XMmxc!_x`^Hy!7uEfTLk)9YzQEUXoty&Nk>Wi1RsCXY|5pMBQk8OC zsm%m|s8Xd0rg4$M1d8&Ci>grK1a}Au_R~5bMMZ~cp$}EC`vnUY zaOlt>rcRy8O6L)wdQBb*6?!fd`|V~!}qHRRJ4R2PBoBbUMj{Z`w^&UTf$< zt{|%NT0;#<42D(B`Tg$_h`nn>O^o_dkkLT6pkJzko=tU*RS*S zw?AjK{EmB19x;B(T*gnIOYNg)bm}{Ttq0CK~S;L6!H=B{GPtdk_0U3QKFmCNp68lafvEL*L z=WZi;;8a{wx-+oDK+d~muqLZBLkdSxBL&CM;iGW&3KVtfjkCKa9==}KI9Ow66h$C~ zlo}#qBMMZ3R9Qpe)u0;Qt>(2CWnpP;OJfTgJ`$K(2u!_#Be^bx?gCLImrWt8Z_yPO zuOxJS>2&Nrj@A3lGJ4iB+VvUAxvB^B9yOH(TlTZ-M7b7_JSd?J zOB7}4?c*Yf(u26za8a7kB*sOOATSM3FpUW(GQ^LV@IaE}c(9)bp@E*n#RQNPA4c=! zXhKxvr8gjb*9Hyl$F*zMwD!`;lP5D}$`q{w(uMP9I3(&TGq)G62GwR7!(3}GcGv`R z$u5wc`f&ExhOo;J%obA^`#r*`O3&q}i$9go8B`_ZQPaF5<)S?665CM|pT}{xXlhgP zD35E&e#bDXQ$-c~C34Oyk&3hql&7}hp1mJaMF9tf#>oG5heM~Yb6phcLK73-Kg4{duaZ^1_EbXze(FstM zqh_TkO?!J4ajPDn4b2J4RGw21Rkb2&TPaf20ja(-oC{7)jtn0@oHM7-utyYfnNJd{ zN~WL>&qVK^#QyUYoV)duUSp2npE_suxd{}-%5v8mxAf9|+4bzDU(`d9F~e_vCND!{|L zRk}YfDfv;jzy|wf*|N9QwBL#Y_@^;?-?i_iPv;->dj6?dvmcpizx_>C*4ruCzBqpT zUtO!Lp=a?ALx*bH4b{9VtYO1Be`)#v)AuAjyj8`$Iw=6ED`-7tCLV1^5!r7c4w=I- zWR1p{IRZnv8ZTFfebPV-DFd)e9VEvK(PbCNdS9$F2V+VbOngu#$4sdV6>q(B_X5gp zK4Q?YF#^*_T)jeYa`zF?dD2w1McG?oCxw-Ygk+;4%?L=XZ7k~5s1#(Xy-I_un5r69 z(_b~UXvW8%HsPaBoAFl`c6?^xfM-Y~H!5y2zI{8+>4WKE?TOAQPMcrT&M%E-QdsLl z(y;Q5!%GTs3!gX~!d1tYG_iDSywlJJWJ^JqB>--TZ9uLTZ`V33k0$<^I0UyvA0|L8 zp2oNt>sa1xAmyHkY?`r@akJLayvsmroq|ZtXsrz|Q6c$Mm8nvwYO?M8P93!NIUheS zQRc2%+v%T!sisc7T}9zW5)tlCXoweSDbWHzH`3GM@%MMv0x?9ZU<^^A1c>^KjR?lq z!}cnB<&GM!@;$ad>U7TZJ+E(+DtJwpJKO0aVR1M~Xx zW%UCV6prTQwMw2gpqE3M>ZMIDRBPUltabGo7>g7X(j#ZmL2k)?{uTi*fc(p4%Jyh#bjJ&FMCL0fT03#WTAf-KVUh z=j2tybuFRWq>bcHT!(kNVjNNi(n=iD7KQULwi=E@?nwOP`OR6mlG?g*9tupK-M-G} z{}0U?qhjg4+jIBN*`H2x_UG)2)2H7Cw*Qap&nevhuT8;I0kvUUjXTw*XM5+IzchV- z>3fnM+^XbW?F}wemy$DP3a;%&5m&SdL(5^JN{3?39)><+1hyHY1*$_a2}G^ai_y!{ zAzPrDK1g6%gfV3Z$-yl+Aut{68BLd-!>FpcOTUq$1f&Ug2E^g!8;pymyB1DRRoR+c zoy3foUDYJuW?WreaB*|eIwGkKNvcg%wWBJM()eX(T!aG&K*b1A#Y;>YPE&T+bA+0s= z+W57=KCB%U{yEqLt7*mRmo~mxSO>SGsaG<3-`3>WhjP{-m>_dBc5)v}p9DhV+q3W3 zG4}7@&-LrqxqJ66mEwJ?Hq?9f?rOtM)T}Y}@pk_>Wtvik4N$G`6yr=th!2_R@#JJD z5FO+6~OuvrY83Gb|O05kJO|{LIT`LPK+QvKAfniAT8pN0+N0txyrn}lzC|?OSSQ;r5Ylm#>A@MP+L>Y^~xH$_aB3sJl6xZk<7RB zV~4FD<8@IudbX5jl7VGF9!=d+$n93h#%+68w|)z2)^BCex{b_Vx10GJ4#@f*R&3b8 z%BAbc$ZRiw9Lwz0`xrQGF?K%bH1_?{#cXmGRqBAHrG+?bZ^8)*Je4|C09B^8RrA6h%@Su7Vc@1&)VY<+Xr3zKpYa}{fHlcA#pJFiG$E34;JUN7-Mz`_8CKQ z%qYT;Jpz5JQFyl<$c*L7<(;|C<6C7szjZ@k`c7n^5B7hp{iW#xOy86A;Et+RD&s;` zsVLJac(xlx+JI?zH1C3IN*7$3_d%a31wv*C`eYT^r8joz1=yz##6Gzv#`qo>n)k;P z)0LC}6%i(Z0)c7o0VUkLRZIU718{ct$JH}XKV89VRE$`NKgA zK(1!zPylUcLsjZjDN}>VUary6#LBK7rq%|USsQWj_2-(Xo=KvtE;t0y$3{&a9*(tV z0>+?pQJLu&BXhA1$Pz`WmYD+AECFg3cEJKs*>9;L@C4@y7zDf_ZDrXC`|$P}Q1!CE zsc#$XLtCNqZbc_iy{GNN2z5@z+P5WkazDLGGSSIt+Vo|8`}Wm>A0#Iy3)KAS+_|%; z86N@JA62NbhCucWa8q%0)zBC}QKH$IiR9*_&^$Ggq@-}7qXY5qFcTc?D}W6aPzDno z>Pu*_4_+RQTAON6ke3|yCMG6CKF>u|sesqtLxX8bVwgZ$AndDp@d~s(<+BB*Dl$`W zaIiL2T-&y7wZQxes;U!G@7}!_R6K%~?FQg(2UA7 z)g=iZ?RGHQ$FZt0Z zc~9$YF57CU&QTraoLy8kdng{B{;XKJnp3CFQWO-+X+s#wWVISF51E^i% z5bTnQw52|Ih^SGq<^>o9qNc22TI_4bj6(ETCFoj|;E~%;V7iRTs%t!|E7f57@&io& zpRm6)eSqnElJ2VrNOk30swyXM%w#f$&0*iA8aD1f#fqKBnYsBGFRqx9NYCe0f`RCJ`MPES#s zF1UG0VP>=vvqdk3mC;d0c!UpOVZKC$2NM|;swq>|F-eU-RbW+Bqb5fK2D2Hxqbtqq zjC^b*Ftya<85ly@jcTTK%;$_=?leOq6MZBDD@uU=;rl9Hk{Ajiu- zrA#wYB8iC<2#Zqn^=X(VRn3v=DNyxf;>3yCv}|Li;^ywj z>a{C5b@Bv*y@NTck0Q|_K=M`!)?O*-qq|~=>xnM57xqbm#Niw)aP5vmTsMq~Jur(i z>X;&y+zT&xr<^j2(205G_Gi}0m2YAC@^%?tJgnjM^ILD;)DP)>O&?(To}_#C%DGot z&c*T@^%o5MAiR2C-ZGIID>UOc|Zfm2)PoZk_98wYfDHrmhxgIUz4z|qCk zOkl7lCr<34y5ce$rI1>(bO8lLgS4K$3Z|;6H&_7T7vQ7C<~6yvWAEt3M;3aTHWM}L z;lq_nrK}oUz*T)Px2Mi!M9CPc@4sOBoHbZGhA@BiHZ~l&jAKM5No{&^`g$#Eb|1$( zEP>NkD%p9m3@g8M0jVg>(7d-*yb7xJ!EI?O5VZ--#m=`a?Hv<1WgkI=YnrH1QM$hA zm_0LyYo0|;PL9@-H$OjLYcuup^V7zjDroumG|V+xuS}IGh&EL9s+hzIrmDI&F<$k& zb;RG#Nz|Vg!`Vnre*}HJX+j zL26PM!2(|e(*~f|D^qp90Ij`LeRuV}RZmsb8L3;hu5{}&kg&Mc^)R)IVxEPsR?R!n zAqJgeb9rXj+Ptqee$839eiuhhpJD%@L!3Nynz7@?)3$vNGIR22*Rd-bHm+yHn30^l zc##de4hu|sU>zwijp~Y5S{F9%yTHCpd%2O4&(4t6;y^{?5|Bu@VdLr4ZwwCp$>_af z=upGkOkZ%IbYgS-FQC zSsyrdA)60gV8`)mj9hsX$5zAeY%_>CYt~R(SH_cDWqf|8oL7%(`TFSxn7;4n15DqO zboZ_(shTp*mkCTqj3Z;vSgzDP=6dyQ3P+Bm{N7`ZmDN!^c{Z>% zkTd1A96ETEUHgx6?tB%wesNqh#&fP<3_ZH`Vdv&`Y}&ev5K)hIR(9xY>U&9=olH2n zx@t4TL`4U(Yu7qXo!HOxDdV+Jf)gi?(|Y=Gs;HwRGm9$@a<4Y|cnM(l9zV;zgXaZu?YRBuDOHbN;T4lXZrA=)+`Pxp^Veve znZup?kJup&ft7b6y6`+rk*ca*1yt1zW-Hs)VO_8YRIy~+)6prBGx|tET@tmjawKyW;DCDZ)V)s zF`Pelj?Fs{5Rlpli?DobBRXS>YQfEiU$SxGat?V$^I*_4#*UhdS3oout73&izL(nY&;yH}5{6Yrlb9zgWYeUPGwyiQ)9TrJTKR6-&JfpIDm&sAfKCVuQPf zw+2(4&JHKZd&&V(!(&vfhpU?-*)7u9vu8VBfBlNx+qdBD=8TuC6Ru_hCV{WXXs@;9 z+t^tXAJH&ZgzI8W`KL3tZT?-g7X#p>P{ig8*c|uj~ZFcWJMz>K5FlG(XV)H7P*4-@Uaovr2WhyZJ_5)1c`}6^( z?@79I=LR=xZg8&h2D!sVlht2fT6>S@-~Pa{D^={jP)(oFb458E;^q^9?5%q&5(Saa zx)-O*?{M_^88#m{!okzm$O(+*vQr#YW2VzFzZcg_uQOpp0j{1N+MJ{cq^h@M{or`B zHqDw+W(o+ZeM+@krKKm6*RJ*3o|LK`t3GIh8loU-)o9itAbqTQ^L}cJhkuyB;2s6( zX`FZPD-U;Y7H_W9_e|XlsqZJ(}dq zTw3L}rcb}VbnGO`RKAa|zn>NjDLgz}Q-bx-tcR&8&{f=FwQNv}%KUsi3G}Ovp&J$I zhrf?A0V?#LT&I+6Vp1&0De>AeEIddHZx|zGpY25U~EP%qbAPb`SY*o(t98$PMzn~SKo8)dJO|cP3PtpKcn}saTJc3 z!t*bG&g<`fN!jiDl*_xc_V8uGx{by+ZvgY^x&Cb5bBMiC_*r_yU>DYwrv5GKK`QW6 zODq2tScc})OqLG*?P=#2%Q=T=foYruQ`>+x1jV*u?dCl!T)dd=J9cpVi4R`Tsa2~y++mVZvd@=X-J?SNwHD1Zqb|w)zL^ygP@$F91m6a zt7=|#9|h#ds9*tUfGmTwVKx4ua3e$g$<9b5Gd)IN8cd+T)W_?`FjXK`Lt*aUzpusP zy?XVkHbJ=BzICULs=N0YG<-H5jw+mBBnz$l1g3tBcZfmnlA*!W(o>#`Um8>AuVlxr z9SkiPC`xpsI2LW>KXu2^(Nn%x9FwO`W8CDatlPAe4cian8QVcrscJ9niEU6i*Xtf~ z`}z%T#J1*eau>ov6WF+Z4_mix<@4vy8BjEo8={~WEL(=Fw-0MJZ4!0*NZ@^eEv-6I z;}_3~`ExjV<|=M};n+BOYe4-}VCw4TiLI@js8c;^+CQ_Sq24(&=`cFg=Q}l%ky#X| zmzNt(a@@heRttu2ZLMaOQOy&2t!-6ruwnd!5ga+Ni@C80RC&d5cgGR-pDbnC%w=Tf z=2KgDm&1pT@$A{>%vrRYnwQ_uW7t@_4ld!ItnWBkB9;=-!wrxEi4PE=-jwuu}u=1*Rq^cY&!6 zYbyb(n=jWy0nF&qg-fPjN+-;gf<6RmDdZBeyNLtv1)Fy6W6`Sh+<);U?R)gsoPd+p zDu_;O&7tF$xpwOjeyJTredb^rmWO4KsLhy8no8A2w4$*b6ws${e@2fPM?v9G+O%yaN-~K4{rhXm)Yn(FmwE_HT{K1B0Mdq~ zf~B9~iA4c0oU~5jr(mf5me`}hVLs+(GS5)qpv ziu4r+j+~(M@)eGrI>Y?MD>!rEDz09BT(791S^&Iv*CBc~wdYn)Do>6b;pFM7^8fqN z)WMC9t&DuqMCCO-I-NLT_5x773JWMIRplv1d+ZFh*h*egdCz33?}(&8+mHwAYewpw zK;`tP?a5QdbN1wMX2&E`>KaSms4To9TVQJtM`QXz?mhmJa~E&${rA6Q)23}ac=ej8 z3l}qM$#NdNc%?Nn6pxwCz@o9-{qFDRHhU{R9r`m*l<94OX@fHT{7D^OzP$bBP5qGG z*Yp9V?@79IuatYLH*ZBXEr(4apzA0G%-%w`>DzH>J05*z2{Aop(rfxQa*7rZ-$jm3 zUBi%RtLQsvDTOmP5ZIxZxUS=wQZ$XTE@=#KiXf*`fhe2Dj4Up|NeXQRQw0$P)P{np z0i)ga5#;u9I$96g`At8D5@&f4I9RJQxIG8`(tny z(0MnfWtZVB-F}*Z!)MZc&;&Lgyu_x17g@0J0Q)Xh$o~0kJ8+dnTaVId)S|bF)EwVc z3i|e#;<^Ydv#|-3g5N71NAFD9+6Qt*z!K&hgQaht9B+-SV+e=Ekyx~NIV)GKCz=SckWcL1m7rA^&A?U1qD+z)=?>Ub=+4#=kFun6btlq)2ew@8>l*_ zz^P1C6RYZRwNF`n=Os7!40$$c5^yiMkEcM>!&SiQil2|823TLUU#?dH8&n&vr>BS3 zi&rU872N*f#fx0HaDhjU9&zvfZ4RC~OW&gD__@b(;H@(CXOvAiR)!=RJ11l5no2}U zF87{1Z$n$EyeRurK2;MnsHO=O0cqMa$>%3ev8QWa%DtMiY|tbOYKWA394D{d z=3>orIt?7p?dLym^g<=OPhO((;TM!Yc*XLqhdEdIh>N#g$@aHwxo{u<&g1ZCqpEq= z@uh(J@8rMvgE(J*@b}^G1AGy0?1TNkWNP-B|3dlz)AuCZeNf5+@rEyzSCd^l8K=CV z`1cTXmpxom>2Qph!*FOm6o<4T^v#FVk2y^hU?uk!>xnV0CpNNQmpGVczif^}gX-N>3v-ElC4`s+LsnXz=M~t}>8u{zIcp52v$YFWj?q~8w!kSg2SZRM(OClsZQcu~kR0OM z4#7D(7uUF!xJS0fDBsyGAPuXqT&=CtF1(#)jtSi~u%y7a%!}>T zK1?>nWAB`frAN9r8S;DurWdYWVeHspRai&L1gizCSC>G0bsFA~+$BoZeIMPU%QUa$8z-Ex<3P z1>vcA^e&!?zpOXac@hyC&+_EfoD#?{9x#AC`%Yo$;KD~12L8`ywtV!NH3^9+qQX5S zuh|RW>!E39Z-uqNMzaQ(DsZZfZ+4O=Z6puc$$o>QgI0s06szjIq?G*HwHr8f>=X-< zTXNAcj?SSia8ThVT@xvqw1VE_R^gvDkWq^d(rx5YyfgaJe#CNG7B0jkr60a6is?Ll zHQmN8!>dJsIIKl@y(=-*O0IJl10;B?_GPSJ=tOipZK2)`uQUz+3 z4|QE^Tr~X#4ra&h18mxPn9JuYICbGF)wOq-+Pyoc3?cNi_r~mK_Z6n*E4_8&atz!L<>TO=&fK;8m@#VwV<$}K^7RT%pS#NFG1Iwp zwVYmk2WXwJ+ys^$s@JZcr#4%T`pqu#TRq&Iw5rzzKsKmMZ&@lpsX)P~b z-sa(>o7}y3n*#^-v2p!Yu3j(Y^$$NVap6X6qVutgRUMJ?@sa$q&MA`Fju|)x=V24l z7261Lc!FDF<(I){ZV8yeRaB(rm_jnO;WBmxZ`xZJIb!R>g8qHkymLS8J9Vc;+s>q9 zwkA>>n%vf{2@Ma{B5A1}yjJ4OHM4B2IdxjtN^#)cZKqfJ8yq{e?jZY20@`j}JJY9c zUv}-=&(Wjj>FXZJ34J6{cHTHhzHxBP!W<&sH@YYK_yO39>EipNPb$QiT7WL0KlTao zt|XRVlURT`y$DnGNc0&)3CQlt5`pyNUEBC>+z5U)VFW*)I)-0PACJ)cgZ;l`8#cTt zUH^0G15DqOq+oit`ntfhjI5y(aBE$t1+n+a>WN2scg)E>q#zi8jX=~swHLai9$Ew> zhqQqh6MEqq+fy5mZi?lE21xAt>mqzOj9Vn})VtmIu&KLqHb`Qog zC>j6sF8HN)LKoeNu-1c#YCRCAh*re3EyOXVgMczi0NWq$`1Uviq~p`P3nl@oYjSs* z1hhmSlaIB33k+d7>^X9YvU~TqB|zAkn@62r3tES_z%H^gHt{_%M0CVjl!=XJb1YpV z@Qq5xBQOqIgC`C~SDIPr(3_ob_7L?c(DU?l*Jg;()TpN`z5>oag{g8L8ro6ch2p!W z_Pu+&;rc&!ZiBr&=IbqL%}tc4J7#BZtR392)O+F-Ac`_R7tfe1++qY`ZW*|k64-AS z%Ulb8w%htK*&K_tYYKL1_>fx*(p&dn_tCv9S~i!54{EttbBS-ie8BxXrM!4n%d_Wq zc=YI&DA$n;D;lA7&U*Fz&zQVu6L!(^3}d@uAExGg&18dP40D|_aSCjMRX`VQ_>6r> zKDMEG*af$wu}7i?R0jdCqx=UR-m&!5`*768pB06Llvdv1z>!nzIB-G>VYp(|dS*ZaUaj(?%4ZEt3o2i#?S^W2)j3H8Z`iqOt2l+{xq0UnhYz2j zuV*yJjZsAFyu~TY!Qj;rQ&bND=|F4+mUhW1ru9(lQi|n$DaO9JESrlXnlcIpaYS7- zN3{g|tlkLMo48e1$>ZAVJilGa%g2>``TXXaH}yk$U(*Mez9;GKtt;HFyvl{L zGFlXkqwUz`T&R7*`SRNwx>(7YgO`c#G6GleoV!e1LjIVA*b88T+7Dyu`Xlr%o=JA! zF)ZG8iqq?NQ0f^^v1>FPdlXZCvz&pw`e1Su1tuU>Fjb}?sUWIMK~yPFRh6dHs8Xfs zoCZ~@3O1#>R7_hnxwDtAKei4ge$vF6CQYqy^Y@{&>;_Xhx8sUaFsB9%W!~b|jF`QY zjLv;<6tE?CETC)gES$o#iO%UmZr`!Qw(dr1``+{!F^wT(=P-2ALPE0p;FQoApB6(f z#B{+`oCHH~wg7xE>vrzu_WiqjDeB>hQ#@%taiV-XiL&Y}5blg!Y!B?CyK7+y9sJX9 z4osBq7LC!xSD@-d|AHcHjSe__x#1=1P|YBtVCm_hdfC>86>NZ^f~j&kl)Y^aeRE8i zf}wgQYN@u>wd$OA&r|!}J*NSrJ}L^5cYX9D6QFC@t5xs*okKH+15erM4{$k5QsX7b7SEgE&pW;QLO10OhI(Abmh2hAR9-FV*jDD z7@fSZF}U-YrGX~RY{g+wfi65WRjS%SRePv{sRE`ll^<39YsjA}AF8FQF;T}&X1#V? z{TFJS@Ae&=*}vx?eLX@rWr!fj@ijTa@6}rhr8aFs-YH>E}Ur-Z{GJkeSqnElJ4BR!p-u_ zToRb(6pkiGpmX!d*Ob-VVZw|B+_?XOU6*TV(SH;-UwzMox+nN$_GHx3UA+9|@7Zu0hH8hz40?&u9e$Je=TLicZse1N`P5Y1Y;KjGh-Etg< z$hNqp4ZyF(P#mK>VGhh@^vGE(Sh1RQ8`n`fatybFvgw}Gg6Nh#@lEbXTxM^)Qbmyn z6s&zRa0|;OHK#MdQHcaaCShlCBQ!Pmd3Rfx0Oyq221Aed z5Z?pmoDrDQRW*KptV25sK-zJ{(41AqIQAJr7;P7dZ%k(lq89ajd1Q4O!Z}f!W2a50 z@4x~^j~~ylF%u~oF@chilNdd2GUF#tX7KP~%wM*iJI`Npvg|eyEeGKc)t$(81zf6m zLG`sdsx$j=s>MKJliOqTX+h!4P2}_*hh1nop0TZ%vwSzpHymcj_<6X5Hy7af(?jRR z30q&*6&G>n=vgdn9r@J4#K%n>_@t4Q{7w&1r1cP0`B1fuDs`%yxdum0nR?#pnKd{w z>N#rpP^>=0r5f*S$I>NpIIwd&J9_k^LI8Ssv@F-?+ocsz>BcT#cz!5&rFlXfVC0!L;-ZOso0o#fRR! z?|b?H)AuCZzIBaT6<4@eT1xA}kz@><$km%KxKLWlkdYIqc=(bnC$2Dj`a+(6@eTK% zy(YKUaN6`9!IkPe?A)`Ty#9kIo;aKNqQ1&JBH7%s3)AN;pzgsnRxVk9M}Yf}+NPAp zuL?0$V5tIZ{f5VAI-9l0!Hte?0#hB0n&@y-5s)fx zGPzv`uIfWM*r7Ke0ihf|eV#KHuF4jzlwu09v*0$Eh<{IC1(cdyk%@bML`e>dl12#gpHwCrvCG6Ap`I=4p0t>PR>ga%WuC>8mrJ@$U>3C`%w(XtxORo>=;K;rE68Y0pY|S0XSG(41;DEsC{?M6Bo4JJW z*f!jJ_Kkq)9JYR;%$6!heEw@piC&za7_LwlJy zYpV9lRo+w})tVqwFJ3pf#=)ALR%skNypy`?7dcy4NS#MG`^QgU-Oe36d-_P;qZ{0o zytZ`HUT#1Biu2d1x%=XCHtsq?^}R1RD-OfG=U;K)#A#M;-9<{z63i_J5ZrMvi{B{I zCu(wVRYm@&@`Ez{Uywe)^gT(p?_Q;@@;c|sssyHE1g7J;BI>j5*;i~mafww2&Wkb_ z!;V9zsi?k5sVLT2E4C1o)sd6eYuS6?C}|x#v*Xw~9-qHPnP)Nuj()W1)Q9D3SJJOX zK8|iq*b4~s_DT&{2@D-D2^iJvB?=0~!wQ%>ZKAfEH-8rW2lUo}p@6EuprD|@>Yz7> zst}->-T0`99gUmXWA^al>e(AiY1@tqdVe0ySt5nvX|^3YL+d<&`hw+b+joT82QTQ{ zX9$sr8C<+k!n|Dz%W;ETqv}X4FiA2T(YdvLWPM=1P&Rv)>bq4bmE@RQs z)g-62;?t%MSUb3CvzJ`IepQrs9=C2+)4X{ybvLVN(IS&4Pacqz9M9c*H%U%O;6~Y1 zQSK>Rxq6XKojZt<+^xmVJ#q2``S~5$w{I^aM~-CCqD8VC!P>QJm^5i3qeqWo^X5(3 zEH-P_tkGtK*|=#VZ8~-kMX$%(FN_ZP`3xLfM7M#3bR9UH*4;;7AJh`t@b(zOT9Z9s z6deo3F-Vl>MaLA@=t9_UAIVs2U;IR|djzz{)iYZhnhb*C^N3FCL~KfXk_4n4{>{;w zV)616rEZSL+dUEA@Rs<6w!$YcN3O}jEi@N*+2`REOIc|RM`tbMs5zEfgQhcK@NoKw zb9d!p6}N6Z#5*#A3+2^Jo4W=(V*rOvUuMFLxy+q4pV|qtxMT=q-OwV=p1XmAlOK(3 zRme$4K56VAa10Q~MJdwy@RaVJ&X}F_7{%f6ki6NsV>|Zm-N~)mDke-Eqrp_=w}v)T zl@IG{RBQ>0@T2s`S?<-8v#ni6s$C^)b3b4otWsa@$%G@aWozT;ZW zJ*pmj&WWovwCL22^Obkmx$hV&_a3JF!52*G)}Jfp7`AulPpfvlDXplact9_lTwHKA zt64bgF`7jo7;Hs7*oxW_1x}>|lyX(7p`nwK+BQf*Xz!rL2P$Ri!N*PQ zXwpnngHIsU*KaaAzcc3rrhD^yV|Mn(-ZLC~vk%)2oMhjzQ`~&?j5S+#;1L+Y)v8+N ztXW4!$KK3cy$frDH{&MFH~ag1nzb7F7wQQbv(bwDpL*mB@B>o)Gh!pcm4vj-3T zQuy-nWsV&`!?I=b8M| zc!?G~U(J!KmMXSx_wL=bY1E2~iy1Ox2n7WNTHpnBj+z#3`t<2qsKA-CW|5MWO;amp zJ{46T7#t*uYyqn_ZeiW#9n4?68cR`ipV_(K=pMk_b!*wMdoQQA9iUbKxY!iPZo6>K zHSuSqKy`sWf;j@%`3~_ca!O>GYa%P0Vp--G$y}ERX6nP4CFd_xGr`#SGs`-d`L+=( zR6+A~(af@sX09%bRibq7_b%Z@{}P^fCa^ZV1v&9)oVi}kk;7+r`s@q359%-fTMb1c zr($dL5ygL6R9^+xuU4?JWe2V~g|SwY;*MQMF}nw2Z3>`~l?$JUI(2jRm%L<;odDHd z0IFg>8&vcogANZ-_HnVIp4;V;m8m8a@X~5aR9;jyDXMlrsah=$%05poCl)TA$@&$G znU|16omU)>_n%_@o)dKI+MhKWH*xTC8J=E|q7 zwwjcdx!N3fpy-7V$5!1Vf! zDq0O5N1vHndG_^hx$^KAg!Gt!IcF#{wx8w6ul|vFn~$?>=V|V~{u}n5DdXPPzv5c$ zGfvh$=WNvrzN&g4$~28FZTr!&YZ0}#9#Gg%!Ocy;>4u}KE^{?Xfo6k^os|Yor8*T% z8#;qD^rTd#3Nxh)>fvgq!PLRvh+dTGCl>Zt**W1A9z*%HTIO}@&UH}>Yy+_M zilKeaVN^f_9*!Q|#>-o0*|~fKdzKDi z>yqI-sJlQ#`4vWw9mVCVmpFdvB$H>%!Z#?Kh}cwYZS-{P*pcvv5CLM&+j&n_;Q3+0 zhH0IH6cE)ss4BLvqobpC+$;`B*REZ)HcxfEI!~!oH7BV$FEB7r8`ByS6Qj*qqvj}8 z<3SZR!8oqaeP?1DMsoxshEjy!JDi$|?{a<5Gv zPWq>FF*Jv(5jot5Zb?O44&~9=RK&LATxf<|8_ar9uSY!6xSczYGYM@t9FWe~_%`(G zF7T|o#hk^Sw|^hIb|1se z-`r|qr7Ca_f1>1wI=HPntcIvK?YG-%TR z8qIo^tyse0J-b+xmQJZWmo6cxIEG|Oe)M72zM~wuSVm@-zML(qrApp`+K12RKVl3g zO3S(P@=IzTJfr8pA#B-sfU-wFC%*4wg7OElY|}<+s!MtFMwx!Dg%kYHX8OLT4={aC z(!Kj-+^@R9)$3(s4H%18+u?K?xrDTVb1`I%K$lj8Pn)46^pY38O)-8g29er*49T5` zli0O{te#_u=r{u3w0`u;?#@}qWQI6LklSS_*K6)Fpl@Hy9=@1dyfC}E;N)(Wf=snn z)mP!FLhN0TDpLhqgQ>zywO^_BKBX?KZS^#`zIQyi5$_A+PgeAcg9%)N@!Y+O2? zO^ZgbX3((7@e|2>Yd3kx-oT+NMw<}k!XjQl> zdXZA6YSx#@lP7Djb~kR^r~vdp3%|{&x_b3$ZC04=+jr1s&~Tbr$$#M#Kt)xhz-O_1GYXB@k-I})bGb{eBF_$1@tmV%>0 z0-nC{96NG`jjLC&WcC~uPM^unwQE^EYaXxeJz?35*({tgl?Bu1GJB#Z_(e-aah^pd zO4rU5LeK8SJihsYgF8+U9FU5SsJ&&Yc5wUU*W~u-r-iO8t9{7GiL+R-Wj~Q=xlCTN z9=%^QX75l=6pZ7#e82L|8`->NANG!ZqD=ky%+{Sxn;OI^Ghu0^V5-!n>P0RNoKZPu z;-D#*s=OxaO0g;j@7-ZrDt~Gabux>Srsm=`v2x8i4(#5?nUXP-d!;ddz$9&0m2YGl z0q9+-U;e>I0v2F!|az%NJ>jO_836Ryq*;Kgmc99bm-8D+S*%m>)MlwifU1x{bX4w`#VrqSEs>L1=24n zD$)YfD^+{s$Pr3PN?5*pIkRWaX03vntgC?btJkchzksKirME!AmmB5fY}~ws1q&B( z^3Zn9?ODXenSIzit3R6-jH06KB#Rd=;My*Msr;uK<8m?kX7Q;x0|$9#O+-=J8k2GH zjbfz$yY$K#wr^a`fn7Vebn-OQ$4%kMoyY9ov4_(~$0M&a3JguF+6@N88=aL3UEwjGH>^I~*aB?NRB%!sLuDn2afJ7@nQRV^YzNnitfE5KJG8 zE@cpQ$%C*-8K{|k@(}D(`e97$flX?Ebg})23uq-U&1Q&u4DEV~GQIblUPFfA6c~kj zKp1Ym{y2#`wHFm?u(y(e%L=oj>R|N8VKNQFVH(yIR9#%u^jE5l)Pj#2H{;``)_h`X zz{<`MgS$ZCMjewo<#WLpOc#Nv$tzL{+jRVrI-n10Nl7HfB(V*1R5+`9Kvn@jWVtVPuMHK%6B zJ~nUK#lEA5xpe9T8R=O#xcK1U>Vw|JlX(l4a_9B~s&C!q$f?t8-n9>-YXFuyPx<|x zoIQJmwQJUJMHFSxkfB_?a*a`=M)TsuOM&B19^8MRDbl-l?lEZ4VA+01$*|!(ee#R~ zIlrp1hQWgiIe-2VbLPzD{Dt$ZTD6LUqD2tqKl0ur)&c_GHV7Kx9!K;;6-DdfYj1Rqo($J*4ReOLe!}m z9-|YW+G=x?T8dMr%vzi|HB?3gbWr0^RV_(_Q>Qt3_Bx#0J+=Jn84$wWqo>%m=NJQA zBLw1cMCyYvg|?xIw>TMb-7uyMz#+8&hm>I$Qb(ds9fL#Ka2zs*VV_=%LwX4g0#L{7 z67154W0yS~zxIP!wRJ0ZZdHmhE$7*tGOe2TL!0UQpZ@QH=|BBJ?9KXz^j}JMZwpMT zFLAN_2C0K5;G9=Lc;^yr>NTh29+;D)a7gHgvp~lbFX~RV9pbxSi0O6VJ6i%0(1>Cs%l->i1aPbQlW$K5shnJ`~Cma+^9n@fX1yg$soX#$e z0!?SFeM-SpS%XSYA@|e}4-0E+KDCsB(Z*h2Y7~WKz~t^nxhT`gqSh`r_%p!46`$ZZ zQJ*<9&+9E}A&Srzor!7N7jt+Ed{ep-kk%7}6y&~%o$!|5rWA#5QYTDNdALUBYvBcT zF>M999k}3T3?c%&2@CeqCNlT( z^CBrZg|3~uiyBqVoy*oY$6sm9@ywTIDO$7i+!3aJ)FI$`WMs;evM)4vzzFQ28TxPU$TcQI$-Tn?W&&PoC2 zW+{+2Y}mk#?K{}BPlY&~#U)i0Ja{k{uUsXiWd{LG0H4~p;T_;Fs&y$_ckN;L=+R7? zI1YbLcWfFp#@^DFK_d!TywFe1T_d)by}S2Pdi4eeMa_5Y*`I=O^KcbM$4-D~;}(li zU~TY-Mdu!kPX04nw+QUqBe8N0rI}+87LEY|RDXQqatKMy$0a;R3o_y29Yml->`Q;MO$uPRBO3H+pe2?Nr#nl;Pr# zj>6QuL<_yC7bnz^s>biCSl5L(XUe(&)}f^+)AmDt1k=Yiuk-wV)rV@{{{`v)4w&BC z2cxFK(Hi*MH~T)M|5AD&FuhxSSzua5#^CYfj$gw0+s`?1;|_bzRI%ekDI;bs;lPC| zww)+r-QjEW89k3Sy@&Ilbq6X2mN0bMQlhiEvw7+gO5M^q(Q_E1M~vs@y+`!z)fX2x zADlcqaCCDOW$L7bXHz{X)!dQ_nktaJi|lum0!uAbwQd7Ul`?f#V<}aesl5X_las*I zK~ttpEaY16ASxLt{Olm{n zq(yRk3myB7phMr`Oj@v>;qu)x^9RwYyC{k9*4QWHVUEsb{oZ3#l-98C& zo4Mu~%3llI&K*A`P&~%v<2#u@aS#i}b!FPvo*dY>T9oHOR$LEXex#Onq4OuF?Av1XDubSb3eB2KTXl->8#y)h#@1UaNxvMI`t}I@3BjCA26K# z$1l^h-!KlJxlY?I{W*8NjxK$Na`4nu3dc;Bf_OhY2aRO>^d)reRmi}i@yuMXhVfGu zv1sKsddsn`dry&^(}PCVfi$-9qD9*dTq~>M@Ub&2T(X=a$BvPj(j3bswpe{?PjGMq zyk~MU;qL8) zUvLPAPn~A{wp|Q$59NX}f=rK4yv0$o@JYcgx`#NKeZ>Y~5@_lZ3o$2j!z-f?Zq0jQ zju!_tt{<*x1M$h~FL3RPKD&T`cA`wT)Wh`2opPSsD&@t4YQA}S=gph?A-%8Ze;%f< z1f-IAsr&t#9UszvCq24d!99WLg|c!o2aKUb;bhA1J>m4F8}u(2Ma9iWoWEAa!czSm0%cb&KjvPM8{U=|tdfR^1?L5S(t5r;2 zw1(;jFIm2E7o|5JQv2|8%5FcFW1Dr&!GZrv^@k-XN z-^{n0wrdkn|K0P4?Ax`Cn%WDLpWMvaDZN=gp$*F>b)xdhb}paW#r93h*|}u{k00G- z#`LLFme--vdCXLJZ;)D_?x#@@VQ3jZZ>*Y`v54mhC3ak$B7ZuoUIy z5z|IgToOLf9Wi^hASk9Aj$SSC4())+I}^8%7C8E)V`&VhiCqw%TKNf}TH!3}F(jrP zjvmQGr*y$a0M^tdQlJvdxeH}X7e{IOjQX*?b7xJWd155t{+{@Gd*bTnO7YM^Y@IiY z@~}j9rKB@?yeQatOR;l{=C9-)jjTiD_XyzZ?P!}3#Ntr`($P808qo>8r3DsNHhB7a zGkWA0h71}&n>_iQb|!Hs0%>ZF!^$a!*7<{Z@a#2bB+nf=dyV}kFEVS%8f|Rw-s2ZI zajA^9oqE!}&k%7kE{a{FUAID-*n44X<;1M`EG+`k*~N=kvwjzit(^s=CVnca^y4Nf z_OlAwV61n>)XXt@d#r3Nus2B_l>BFw{HEZk@?JyiVzpjBw%Jz8qt32s9$h02W&=C+ z?qSRJU7Q&rj)th|>K*$ye!haSi#Fhz(3zA@!jy>(l?GJR)g%-1hI!1R4j|HCl-1I&tn&>^sN zHk|+b&HjHUO_}oN=brmtZhtEU-S2(8__en;&ukrdZs)*nef{{gmp5M<&HQaZAir|= zkYxa08BDyiwdZ&Kf&3vTSOe+1_D^;?KG%6tRanA|N#i(v>JUp8&LBA@PSk)UdXt?f zQxgU$q;#S<4F)}K9(sEBYs2_S1x%SXMvFkB!V0QRNe!Jq)L1|lS4Zpxz6z!~H95GA zo<@!B1T6lPmEB}?>sDMb1hKbWPcqV5bG7O=Ygccg?$#5AkDWn6^Hy9fzs>DOpR@ni zIh=e0IVno>&hsybOim-KT|W0-d`{>7qcDWGMIYMZ^aQv?kQLv7FppF`bfK7=c@XRokB2}u&^;b!T_FChu{g;xK$dEst3Cv8$4Gpf zV`UkSmt!1W0wZ6SM7&+%@N|j7$2A6Tr%22KXG1ejd`uB|*azchj>OF_5MOfy&UU^y zHSr`PD4x%2Z&G#U68o30;JbS@{OZnC&MlwJ;Tgpoo;sY;t&90(O(~BL?B|v^5M|<| zOddam3zav~`^NJVQwX2PeLu2s!&WcKv{gI{#&l=-gdR*A(;L0co@Ul|M8(92DxJ*O z(Iw=z&Bfa2BFa=?YKq6sIi3Jfq+fsk3kD1+AUZLP2hU$KbKx?ceDMu&shP}Ox{6!( z9&-QTQ~HV1Hg3{fu9V%y=n_QxoK8GnxtU|O-ke*qn04#-2uz*oVJeFBqtDd*rCy>i zRS*UT^hSfg(V`?2lt8D4z%*K{qOLhhg`+xY&JG33 zeE9Z1Xf*BF^IsMIAMF2o`=`J93BT&lg|jD*QC5AO6-(x5p#W7Ise|4MM^z|^60mnr zRlO?In~ptu)^Yy)LH6$1#G19s89byv7H_7=Qf*dRfO4HRwl*rJsuYSQS5X}fH2PHT z;p)ScD^-kc(}v525FXE7!Pd?1m26Pky?KaI=Pcd4wpM^5`*Y}>qxnh{gDZR^LE zQCZv#N#|)y3!Vk1aNj+YM{a)Ha}VG}a1u{t-$TD7?)oM2B(fzp1DbO`IGf{^J{)xj z$Wgy4xA~|XuDhex%!?HYN8_i)+kjLftXdEi-1#q+8!X44b$J zJ5kMg?^IFONxYQ*W$W&Jtk}4pn~z^JeEf8teEwSCno2^teE!SVJbw0y$k^sY$7OQ+ z{+G1v(3hioj`48WI(Z&`oR~Y0b!&EGVdo)=-${e%$4zX-5%bYH9_btepl_NLOrlC% z+#LxH3!qcyb{smmhX?m=v3BiBtqos+w4no%Nt{3zSA)RVk}loy*}HEywdLiU>0d~# zb0qUR^=9+lW0c>1M0S1;YVO?Ui?6<6$=WTU)GQKolqSMlstIj`` zCt2{~KY;1w%YT0Ex&P(%)%X#7J$5(`hmT@Kd={%yTk&GjbgG7qX0&T46Fj5X*RnIe zT)31IZSuI*s~_LZTg-#8qV(T|=x2@jGPe!a9K(6NVhbymu3&`}OvOb5wd!3J!ANyB za&%Tzymr{x+2CMrg`1m+goH?1<)o9HoyxG1Lh{S{&k1eb7TbVKtV7yk;olOU#CAOS>U+9%8;GNKG^1xP z;Lf3w>}s3O<=z9R9X5u&IUQJ+ki}@DC*z!a81L-M90Ag{v{vlO$mK-4Zfs0xP1&$% zO!SK2aHj#hUbBq{vzG8;)fQf^*u<;VTY0%;Eh`c;IMcg;i$liJt(h}}1Q46DI`d-I zGOi6Q;oj5*e7Rv4pD$j+>&2@%-=~nOF*A9wcs;i!%wS1;D+bv4(@$)WA(TEgK@6}D zqpxicgY*%yKbS)2DEiuYG1)(wyVK@TUNoEoxw*WWJ(C9`hjO)B9v3=hak70HH;eo7 zc)}BN;qw z9QPkRr$guN6pxw2-A6B}x%q&!%r@k-?m}htW6oWw=IpTxRLoq&Ww$6QHg0C^>fPu} z0W{IM@v)_zPXwlBM|UmamI@T2Iu)73IkVSUXdT-kB7$g>+k&~Xr*Y!w0amV9qN!13 zD(`9Ynd;T>EK#+RZ&l3XJ9ln!x4MP{-TQJ&et+rmZA@Rjg|wFWjF>Q;2lBnuP^KFd zbu3=JnYt&h$ZXe@8B5ks^XPL1jhaksyB@6Cb%-0!z9+qC20{6QS+#vTcW+kmLSXvk zJ%Q=NTE70!0qMO@|HCkq^k4(TcZZdOVTdTy550N+Tj}2IG9J`k>OvLn&E!oCn|hR_l~><^F3%EZR=H;stz_oXI~5M5}Z28PIDqch6Q) z>fM6Ng_9^AI+E(Ucj?uuhp0zaOwP_)TvP>AH8jT7&RUkXI6Irf^LG%qT4QZpKN+(E zsVejoOto-sQi!RLZVoz83j$M}(S?sJ3|Ly2arX@sKdF+b`CYhT3KzJ{!rddBrUqY9 zGurX^)h}4QVXrore$T0^6it{#<%2Ica;}_<<@bnbp39)&leqKz8(hM(FhvMZL)u~C zlZ9hg7FTcHXV>oIjGeNS-Pfwvbo4YGMWL$ce8NOCW?!vV59TGO6P;6jT;sM z`mUl-Hm}~m-i^E1z5OV27Hq*J@aW!m3_t(nZy7YCn6nqIa`|dGt=n|q)VYg1d-jqi zQV>^H-lwUB3r(!ONKMb@$-^%gURc8Zo%<*+uclL%o}%Ut@YPp8=gQSeMva}!CHeoh z?>mRJISN~sWbE8Buy#(v+9?g4d#3D5$IdlF;ME+XcXM356F7hN2FDH_Wy!2*Ts*pm z<2zTfVnzW=C--6A#ScjpL`-NwA zVf&#oY}~q?maVeL%udtB(9W7SpV~XOWjUSp9a<6?;KPFX^O-esA-fKor->nuCgxDW z;#=_b_kYd6f>BtR{INFr(r4gszI^>XdF{Kf>);6vp14R=-DA4SdqIfmdGA$i9m zf)i)1aa6wR&b>!@`SlMhUb~gMpMS&1X>&QGVprdN!rd>vrq_tcOj)#s+OK~{&Zwn? ziYd1*k zI~Mo6p~Ur{j9-UQ*f%f4m{x*o#t0%ijwG^uG2Yn&(ZzH{7u$;=QLRYN?u$OI8|J8P zw1~*%lsTP|Zqan^I)H0+cj(@$4+eK{9Nau`baBR63M@7IhE87}eMUu|QDaEe6j^E( zly`?GsHNI=6a}F=Ea~i|KvcbWt)!5A15@vyNUE#vGpR#97xkfxRWW(>el#`(6Bw1v z_<8GTH((6o7H-B6kSqm%SJLte=rdv_k(r$__$1&i(Cj>TvKHLk9Nh_Ba2__kS?B}O zNbcB&H9L=T^~NJsY&=eEPG9VUTVUy%K~s+unz|%nElXSXL~NYGa1b@`<{M5}WIQ=7 za|sKK5@qd+og8!YOCd)-`}<$~j>Ob#j-9$F_pKpEly3R$2W%5S?mu{(%BuT(+}Oxx zwq8Ufw&vmEFUZVj!GZmUq@X@ccuYLyb@#Nk-vUu^nXU4uxbv9RJI>I=F_ETj*)$fj z@W{Z@GecWyChN_->-X8ZBr%|9DwC$qXNWjHeftljckgaQgn1Ji=}ksTIDNZyVAjM5 z3>{cVN%1&_h!UT>Vl$D=JMoEK1RvW*^NB+&PT@H$T)&ro1;q>=T0~LFFfBUNoP|p{ zeDXA-$B$+B$Rdh|6*7MOWLB--$&$4PXkrZJQ*nUO+Vm3$RWM`zdT{_ku`~sV8lA(1 ztF;_Fevx@Aw%`?#M3+9pIefN)(^qcNu}2Y&?L6@Hj^@_9wOnwFqw z207;B>L~xEf!%xevvKW4E{>T>g?n>GWcR{3sx3ir?Ww%;72A&7piALY>c03JHXgac z`Xkpkck>k|DxWfV@-lW`xXGDYUvl;SH!Rp!hHr;41hy|^LdNqd6LR;GCnu^u8kt$QFw85O+>Vr1eSlQ4-i-2S)g{2W&8x@e1nkBCz$zMi(Kl4R3{Qa5h#x$yj?OV(Sr2 zOnM$u=C9yfX(gpMZ&EIH^Y$ZlA3jHN%g*?Qr_!=rPff8zCuOi@_aPoU`%;7A^ragy zdjzp%*FmaoKH#TK#xus(c&Sdz^C5)T3h?$F) zvtrG9GO{vBOo*dJtCl3CBoPxG%f?MxSi5B#sX+~ok#$D} z)i-UWN}Vd0YGa_?oiVwXF}phB>Fdjp6Q@|eZZpGzV>oY&CrKZUE~Je(ROv*tC?K$9 zG0x2g5Zqw|0d0yfB=jb*?I^ruzcH~7u4#ja?lO*u4kIx&AA&KvgrK|v)`+sc^QM~j z15E$-qz^ECPtr|!Y46outyiY~Cg7M`glp~y0q6kq^5Pp)2WeonP9KJCY9YGhB5ad} z2}lLD2?H@i52RU~05)bIaVngkDAOS>akR|q$EAwf^b=L%92A8)AXs4GfzhNFbzmuq z)CRqy4hJ!NldWb3Cwp83oJtL7ia=DX>dmV{^eNTaw3$Hk(`J0!#EM2XCai57F}Qeg zqpX&(?b>lkA42!0228FYgl2ZZ?4K;kvJkz1w2@;JP27_4O6rDlbbEndI`$zgu?xx; zxTIl@%*VoCAR3U1KByJeZizStW@2Rs!ATUYDIgv@&nP)R73at-a=RBXd-)cYZ`i|x zDT_%;%4Of)6HJ>rkD{WH^y)X5L4_sEnlYcj1tYjzS}Q8;5~nYe@$&UAh>lHT^X9!A zKYmG^2RB>=?skR%wr)Q{S@~@~{nU`L#;!*4<^znpISmS8%)L4*LZ9_Z~bUx9b3!IY(jXkxCO+QMsNi zvGLE9&q}13gCARW9_E@j5_j%CA9<=H19hWk2Zrz>M@S++yUZY_rx>1 zuYhx)09Djze0Piq{jg6d#xA}uM%i|Z>5fHwFYID_5apZ9QO8sUy2Q}3{UENE)iHR` zV1ZHuj=p{v-CYF&0#kc|si;vkJi%U@!9$Jx)1f!ks{&P^X@!_51GVnv;f&6~77H62 zEu7#d&1^N*(bPhZgR`5!w3_j4+j7A^hytSrnK_+si%J*e))8Ys3ZIBl{mc|jGf_d_ z@%i|rbi&3X0jJOmOu;D_0#k5{Y%Pj4jbJIf!_wQ+WzY!L?>xq&>5G{;e-&%C?Bn>Q za+Yq~$*Qe;n73>-Tlef?)3)tw*}9vVGZymr$>*Fod4{W(uTWWC!?!>CfhW(N3T&rR zdFKH|<7aT~)>F0|I6*>M3sG=)xpV&+87=dPjBi7J_d;$z{G9ubU(!6i6(u9ba^T2u z`HY=J#wKw1_$kV&>PXLOi_YjzuYuz@c&3cn$FHfl_llL<&WIDx91AxAoku30xupp_ zMVWet!j|nON||~liaJ$_wS@q-IaaPw3>rP1^QCnH5EDts84MpimZ>u)isHY_gS$^j zO=%@gzzrtOTPun-9t)ogn)@VK&UT^HO1Nw&p`2nC3l!D42z zWhPl>%aUc8nVFfHnNc#y7Bkv1Q##X$l~q}__dd|~cHh2lkF}i6z0d7F{j2-Oad|$^ zc;;FwLZOHiGsZi<31bH5VDgHl<-rSE@k;wNHw??-&WVlJSY{jbB_pLR0fd=vzoy?qpn}ddc_M6W8z@ z+#+)1I9q_4g4Qn<7nfj0+qeo$eYn1U9S8TH!A6v77i(9(u(0PVQTShe*;QcLMPO>7 zcJrzei)_r)qzyL8EOTjViV{`qLl^IdAqM5SCVL&uZmzfo1gYr+OK+92bKeohI0SQ3 zlxeue7f0WoSjv6X%5OoNSd2~L6bU@1U>83LgB%+YCt*yHI$6$BCu67N;ef*%A7Xs6-JL~yYlz3~KAk$o^k^=I}tQD7d) zjCblz_J9H^8`>xsE6{cKLg(ZpD$*X4qXC^Vu|w3r`&pA(fv7UmR~eg9CMf+!_M;E$ zOqB)n%084Dy&h|wfi6}${%m2VCT-9;I#XBI!s=nesWgSsID0wguiWNDNu>aN6klpR zNbNV8-ovNSO@Qhf+mAWx_R~ABn5gu=95{Q8QUS@Wnohb4L{F5I)AIZkufF?%uiyQ^ z&%gYG8>M%7{p}BI-L;Rqm9;c?bkfk=%)vwZ*uHI(sLSiDT(y=TzW@5;i|l56PHUXxpAjb6l^W!)isPA zSHzPSuepBn4i~T9;Ml3N96ENA69Vwl=PyuNR*%sw5{+{-G1>WqXXIn+m5HT$Cgut( z1(aP~Gga&2lJVPdhFnjfi-&;JyBFrJY1p_YGJ48F6{bNU(exiMlvC#}uzUY*wrt%( zQ)4>=2aMu&c@t9>Z4pHpBT!DoLg1k&Tx-8<%-xf4mY_t*i`yZpG$kcN+SMbj-zt~j zN5fH3tPcgsu>$IxK11o3TZD~cgsNz}NbMQXgZ{%OF>pjN{f3VxGN~UnqL?iW{y6(5 zU@0ox+A)xBcAj{IBoY{tfyTv;t|kuxd?T3Q8pJh?4_DW&WB1PEbhC1lfXklG%nW?~ zl_h3omKcpjX?HpmrV1pL%@&lQ1{-OI%F-((`;oG?RN1WlKPPNZf;;8d!N~z9cXu@d z(ycr9*mK|rGvt3O8IbZKByf`eP3NDi&L6Og9VM!>2yI*e#<+2~#t$XD-(-Ay6k(q@ z5`Fv#98x7nO_b+|IyI&h5j1c-`;Ln;?P%iVgZkfL`qRr#F#XueCzyUD<#9(14_oeW zv$8^9I){{Ti>PXOB1*N69=W3gsBN6S+eDhcr{&dm+-mH^D|HAnHl5(X5C6)(vp3L* z3d|ZkgBLYT)O#f`-XVbAxf28+9Tbcij$WC`t4uy}b`Ynfq-j$&`&K||i-V&;)TG5x zAnWXGQk|LN*c6y5j!dcD+?~{IuK&ZXnq1V$CCUcZcFwNU*SD~Ez(6XEA)M@+ zM|RJFoGHC8(7A!e-jnNP0;q;3SeyJAIdK8s{QZAp>+WOfddKH)zhmi|jm%xL9)o8L z>HWuW>e5Z#{qQ$VpSsMs3s<;&{RVsYA7tXBDWZbwX=tox?W!fLTQ-k9Ti3FB)nbZ@ z3u$hy=hlt0Tt2;rYv=b=(`t&jQ2!az!DZR_`3Hsfc`D~uv8d0QnqBxbL4Gz-Y zls2X$ZSe8+_&o!XGG3~*KL;lhPA^glN zZwZ$APF&8G^VI|-4Z|fNkNp?#Quq8vn!f%kb2c4e(XMlxs(nnrpjlWaPQZ{hp5TFn z95{KB&h|!u>3=BGzr6gE0qK8U{twvS2mUBHQkLjh_lLLt>n-c}1k;bCJn5(wnBJvS z6jf^eERsgg<$gnlI*Df1nk}@x`wJTmUu4pPwLE$GH4k3AWYC0pBoCax^~x6ZA3sAt zdLIs5y3d2lH)wK;qR8Y$k3r)&Uvi6?Q^w=&>59EckG;JCCyDTtoV<2+TB&VtQnJg4 z+374X8Epv+^2JG@`au;a&P*9IRW@bT8I(1qPS`5x1O=vFb<<#Q^`N1lm1Tp5a8DON z$;b(0W%X4zkKVQW0Nul5X@C5T7hnHO|Dgp0L?lb#(7=gvSIIA)!kh1Z;M(mn2_72A z8ay7oIB<`k2-a`e!Pv1y^d2~veaDV7dHPJ2u2{|0Yb6{M)pp_d9y)7o@ucw{hYoDP zFVKUH8<+8y?>ea~J4r>!L2B=x;oiL)0z)snLetgmdNNj?Y3i|sJm1!@2Xi@S*mR%SHY_zS4r z67h-1qN?Em(`L+}xuu;w`wmjq{E%)o4osLhhws1tg@?~x$!oUp<6r+yV&)Lc>>|`% zXIw>ne*eqg89lBL|Bwh?z5S8G;^_<0`* zrdDPYO<{(kH*JB*{9IMdmMsVAqGUhnrW2TICE&8a$Hzw$sj@~{0yzEq4e9MAh|?== z&&@&2e&i&oRLRS$v_A!?NZm?uZ`5FK&~g64MK)~M%7Lu@)SE&W78J&+ z)mwS~-7h3bFju~1H~&=vrK6Eaz;xV9l19#=Wp3?;yP2;A0a$v1gEdvrK!11RV`Z%o+Y{0C`!s3*?;6T z(^hYz@##<8*tUljk0^E}_feCzw?2Esh0{j~2=c*BqaK^)~5U2V}ix(ER7 zF*7ThySBbOTDqQn`;IYZ*;>53{Fps&5tlAsr=qfvMWT)p(sDR^rGyGm(J9$IS+r_3 zp)qj+w}Ui2eZ#8ldpLdd26ro}y0f_)n%vuAA~TUHb@d&UIx_U>3Xb{FV`GhxMM7H`^WN^B!-${eknBuCZy$Hd0d3sH&`G>f{+}a{R%$!`ZlHJI79(VUB#3;^L|FA2^h< z>Q)^6lSFZfd8YG)V~je}*jiv`q7?a~7;%@|0Or*EX_ht$Y^;4^vT9#pCDSFtTty8d1B}%1mI-OuBfa zV9glDeDr8qJD(Dp zJ_viCOzZ=C;2My?^RK_<;eMyQqDnn{+(^$%A~ijZ^o)2iGLzMGf(mdyjGZb=vs9QGtceZ}6X?*n~iTTU1 zPML}>Z6YB9CU8)c^&?THuOHO&_F;o4Qwcm?Km6^N`lWqh{?{s>VEU1i z&bAubniQB;k~C%(Y2y}C-u{v^_Zo3Z7>Z-uSo%+1Md!CabFHj~vif#$yqydd1z6Gg zj3ejoFm(D#HXpl5?WGdxy<<4tYcwl1?4+TyMx4$LG|C!LYb&$@N0Uhur`7^n8%ykL zt#B}EIk;~N^|hs(IJS+GCk`=qP(L(Ewwm9}PJyY`T3~96#^ivt(UE@Z%6Teh8T~2FABvr$7hN60>E;?k>X0I)E?my44V&1$ zV+Ri&bn@)k8@~PKdv*xOQ<5{OD6eALv?*-cwq4Zj7E!kq{N*oy<;3w*a(z03hYaUl zMLRL+Blye|MHeqopWf+ob4tcPX0Uuu4b-%>v2@)QYFeLg_{=pf->hQS;d5-*ew;HG ztGRTmj{f5&W9^fGe{63azW$4-#a?La>`6?_;K-3v+`nHTaGgYb%R@#^Scrv7oCE}^ zn7L;PNPE#${;!#T7F`9X_5n%U76{%dt0puup7YmlaqVWMC_^pVcOIg;rje(jCR;l? zxm(kMcen&h&avu5Fc<$QzWM$qR;}Aca?VJSdW;~u&v4owJd^K2!1D7iOqn}hVETx0 z6Q>Xs8!zhaA$w1pqWX3@XG9H_83QTXxr^=Fk78x#$`@7+{Mo|DSLR9*doQeQrTs{I zQ+A9|k~gRc91L1frOph^>&K3rYpAU)VePtQDmaxcUS;x;g=JTDGMq9ANtuN{dgLG~ z?_cL-dmHD6j-^pxdT01pp1QdI4$)8c|0nzEtKYoV|F!%Ig}LzRf6dH2^2t7xkD)wh zt)#uFj8ah`$@y~`FlReAAAHZ@`ws~iFbhYCoX4*}$IT}{uxQ_T=5IeiN#k>l->BhM z`&+Kmz9yw$Dej3QII`&=FQXgPOBGFCKTC-O6VpqHAiQw z!QNb9rq-m8tRk2!MsGCF5Zj$ORMlb5f#BXAo$GN0TLV<{`UPg+t8%jf2E zWb-6W?3l^$K^b)U>NA||wQN}}FkLy8t;yi^rf7W!l9UBp`~x7?h%B!FQ_n0+%hPt8m$&;se^X6;$j1@e7{6tjWBnAx{ zssi8O7KyoY44;WART42+yQX4p2Kpzq)j)Hgq&o4JY0m+!D;>u##5>)5<) zCo4DZz}YVjEBgq{O(8_5_T$};|6uv5-Pq{EurY=(W#&p=zxkOFqa|o-c)-!KS48=q z<;2^RO5Mj) zfv7TjTrs@>($&L>#H1+Z&6~oC<#XuSGhLnZrr3vZdu2J7{r01haEKt|T8B>dK$|{t46b>oF@kkqmkEkN|^wD^v7NAYc#}GT300Rd@34iM43%N=irJ?0BA5NYe<#xQY#F0wqnXysRq5BC|6OSdby^kP$ff+ zQtL#GDyEFLYP3oQ8#~Nw?D)!B&u3Q3I#UylUOrS*)UtTsKy{sIq0S9UtvhBep=1sk zM`Vwo^d2zr+&0Z$38P19otN6!1{y~|%W@qOUQKoxUWqRt= zSw@Z;&hX*GIDPsw|MqYH#@)Mj1-yS{=ImKy_w2>R%eRS39jGoP>E;wIu#QIK8mDGp zx^laW73EqsSdIlQo+T5E!1u@S?e_*m98Y#2(CBv6*8RZjv)(3`56HCx3VmC1a;? z&oPwBg9q5M?GRn0U3_k(WI!_Tg}~G#?N5Q|2bk&wj>ja`7K>7i$ zj`sFwwRTuoY5Bs;md}*kKrECDNcOn+_^UHe=lAc=U4iLH3rDo}!T6@+s=0Qf`i#RV zC{q+r7?#FRQMI91*mcL!DF(;TURe2wn)6D;DZDq%ff<}BspDSrV{X;8Qr7f{?FY|s zR}@!y^K;sszvJB161MH!!Qn#(Shs2kt5+^&*1Q>nMTN0%?>5>SZ*lj=VQyVJ%FXL% zxN-d=sTnz3z1NDhM;!JMIk*QW;O-ktUfwYN`q#g3;o>>9ySGPnAG&q5!r9qP?u9bb z*~FebyZH6jzjFTkS)M$3#N7FFC8*F6Cu*}slwV2B1Cr!3I`|}`cMT`C=MWW|8@KNv zAUu}3w#Q7FvxMBy#iaKdLihL-0>hG-w{#U}ub1Ey5Qo7l1&vD-*3R9rat^`TDI5#u z2&^S2va%QD>JpEwTLM;|DFV)n_v=f&!~~{YebTTB=phO>9rw_FWamz1$EgxVOj(9s zi~!Ri5}&Xf{3Cm!a|^@h9Z5p3QS#a`nA^u=>5_n%V+7soyUTevT7i?bD0nN^FnK@0 z>ibbt{g-0h^O_s^qMJa| z=%j*F>Ecz^Gb^f8BllO?22fcRqbN{iEMMs*QSwA9?NBjg+|<*{6$cjwj7|=i93AoW z^rf`qE_)>K7~>F1i9VKajUTqbIdadE@Q%r4g?l8weD)Ere$zE*PcJ`j7_%8#GcnSS);6HGsn@~Ewn z#|`&Hafvb=y%O$6$xkD_SgF~g=`}JpN{YFkdl^@Yu5!pi^cn1IjIe)m3;>+V9}3sEj{3ca?- zW=}T`cUf-Nfe&rPMZNngC83}V+8;+S@hK4eH|rj8;3?s9=G7g_FEa$Pf<-Bl z*J#Qv;P*F`-#gjN=$gt-HSyn^kS?QGnDKyrsz1A{rB$`f5|gv2IQKDTzM$O>@~iU(aJTR91-W0LU!PtHRmPJK(OzQj7CwXQaoM5 z<<$Qh&2GxpiY3Ho;UOBE6>t1Eiyw29*rsP++`ILRK#;x-@YkdGQGRYjYiyFn;kbd6 z70CWLg(FC^rE};&?nTI#m^5j9eSr|kSl}q%7XUI*G!m#l;(V@N2`{KDV_06fus|u9 z;yckl82=-S*FT}dW{y8iD+l`5QkXiH%9!61lOr53J-EX|Dl5_c?CmL)Ae#M_WhRL) zhb)d7xJN9G>W<6cU;j6wI03^}NNpCU)c^!Z;3Wm?zJ2LvCy#W!h>8*J)5z*t_)CR( zQLY8Byh)~}vd?RvWJ7UXX?;f3l5f|Xh9!E*niFglkdQ(Bc$)lheIY+v^2AhUHM_ix%= z6Mn_msaB5}jw~kQ!APGdzL0a$GrWbeE+Fn5<}opTIplE4Kv{j3^v9*B-Gb6fY>teQ z9=9qsss%D%)%PKU-{? zWzlf?2@={GENJE8fQEJDLdb7gh6w-ia}Z#LX}fWLuKrDnEPV#A6ePV$+`7Re(Zl z@jMz%w@|9?#{5fSeJzYtfO3DI{slAYC+Ep8zYqPYUeE|FhZsj@^AIXi-hT`6vkH*; zV&&q|CmZ~e3l^?6HKqQu*ZVi0xU;?yZXtXM;19(kC8FvacaTMVuPa2y)Ai8~+@6+A zP#KL6`oneTQW1l2Cas9giJM&_6}%e!cUwDwWOY+F@n$Lr(ONj&Z$W-$R@(O4EMtrW?9uQDECeovL^q znaBA6*V0iVG6B2yKy|TQXGY|`{dBIKiVZ}eLClst{K5;p7dyBy|BX+Q>T8LBM0Y}_ zW>#u;gZ2}^s>1d;OaA0(E-dtB%-tMw|Mh~C0uXcK2~A&h@9SU<%&nGpW0{33^DD1( zG(OJjn_CLIHamt^$m;5?w{0CcWBao_&gJrA!vh4R*1d1hSTJb=V?z#|Z{p0AKG<6b zJA)UfP(+oOs?dqQ6E_9%qyb9Gfri|`0{DwQP0;mH*qu08Uesm6$9Ray~V6WeKi=bVf=rX(!H&HpR=DY-;G}2e5cCLY&Gb0M@I`K z)Ajh{sp4|#oHkH>q<$zFXfOby(plYkT@OK~lVj>;CB+Ta@4OFZ8`35w_^l2pte)E{ zFG!PAr0QxHMb8KXTtOi~MP|PPJCBQ{@eB?;@HA4q7J^~N=cd&&)yduVQdxe*sQ;Jd z-WUm=2iRkJxPJ+%mqdRoK7G{c^1=Evxd7$beS<6#Q3<ly)BIcx~|S(8<$fseKJ%G_(cin&JZe!y7wtN+^E)hl*+LY;`V zWd)?i*zSW&12mPS-g@`-9c-hDehOzWdNy*zJG|7TYTg0T1*3?i*Jrud zL+&qKJE1pLNmM~6Tok`Z*b&qbN=3<3N@n>?#xXT%CM~IvEoppyfP%c+CsiXb|%kdX=_hTE^tjRy$$NL@2c(8VY$nH(fyfBwdQdlyxLCs8%6xP=#q7JEm^uV1S zeS{%}yKyM0j-RqKfu83twh@G>g zzRoa!_FhEqObDL{IY4I2*85>6CL@%pbn|;k?Q&nGqkn!)d*T6%;xWTiWx3<-x#Hg) z>_36oWr|=EO4WO#I@_%ZD(an5BkXYq;5yVaSlBp_-;p?Fqx)K#AkJP`C>WqHv{H+l z;@>?3M;)fPJhGAK*{-BBu->8YkVOl|EBUXX0`rikFgVsS34n}jC14wGshsKg3di8! zaGfa-36n`jVk+mIy4x=fYCMG%jF-k_)Ey*IE)+D_K$pXwnpmElm!BKISW`<)ZxRZS zd@ppg_IpX0*Y&8AHjq5_dAPeFqo>UoOp@#R)|r?!pP0En&kYE3{&*qqeorp4e57RO z&nbIC*AwW1jR`mTcejks?;6U~^x<2Mj3JIYW|`sC(}eZ|*F-JNpXRaur!*?bbko)7 zn|^u*DRhPKeCS;YFHY;PeAGW?KeEzmJt_knh=#Brl!toU(35Ew=CQ%BQ{}GLZOs;$ zFLieJl)O1TWR0GLBJt%-LeDAnXcjZ`V?h*jt*Y9aqeHfj-2M-=13*lt%00nkRZCT4 zmr}P$3y-rkSu8rV08I6YUNvdUqwV9k!p258l@RGT1;>z>45Al5;?lr7QCblSfVT3JAE=nEFR-|Z!S=Pi0GVdG4(f=H_1H@ae3tt9J_yhrBqGpjeh#Wc?;A@|!4 zwxs{A?LtiRY-^sy3R@{~{AO^5t!?%?T323C%X5oAuICem>GQ#mM@=P;#fNx9fbvfo zm#W%^_E@Fua-%C1A~Iiu+=#{08U?!-Im?Ei82%?eZ>9}S3fE8JGNAI8V_Kxq@p ztmTCZzsH)LCUo_eK4(8A*vQ1!JcW4#sS^h_2(3i40}slNA-O`2=a=8VRkhWpM(Uhs z(bJG{hko_bsBwB+U7RbPZFoY!$KYM`uuN!o#fw*RUT+Q2@mzwsLS^TE!GfVe21zOD zU;0>y@!&t{-RbAon9vT7jIG{ZZ`wuSa`{THixWDSxUr`0td~59g3Py+=IJ3^)lU!B ziP#PygH9R>x#HJX zEP8^@k$!wF4Hl#P2lCWrVj7tB{vYVE1OrF$1K7M}L==m)(#*3J9z2iutU29b3M}>y zdM#&5poD$8Q9PCuW7FaIOs>ecH`sz-@NN3qVVMC4mNgs3qZRH5guGdEb9Txd$I%3; zBT78E-1eA!kYDuW^R+rDjgOPULmSXyT;VWHQZB43SeyRrG3K(139FL{v4PY*fAuF@&H*fq z?rO#_l5E{8lc#%U5faj5WmusVO$;yuI^D^E_d*an#gky`tWd8mRK-8aM*Cd~;Nz4gaLr?;kr6z^ws>BotBA=OBG4OxvYb>qvs*bO9vOfY-HWCC`a!dX zf%SD*Lqksph;HlzzQCn6sb;|AKw1jxu1cZ0$LkLcTen_4OEqKgrW7F}qOka$M0J*} zjQO_`k2m3LDT7fsH5du$SnoXkwJA18jQnn(7J#cdB(m7zndg3Ew)QKc%jXpdrq;@> zhbIjlp$Y;}Caf-8fqxnTV|vOaoTTN5Zz2K5{Az^9i@sVHuM#)NN{w8(we2E+%=XFO z@r<14lcq-$>^>q~)emio$r9`kPc|*SzeE36*U%7uQpwfU?uJpx=A%NMmv)9WxUdnj z#9{<#PPgFdcdep;iOw>~^#_8A3HlUYYbk*FwnWZC%z-f*nXuk=)A^1t{@37RK~H(e ze&u4F$2;`Fq~Rc^vQ;NIz4Wi>SPsoeF^4x%7o&LzAnx*@gEORR$?P{wFC**F7;uR~ ziKR$ZYDvUtzd6vJnXJVvUS6T59IGJGU3UvAsublnTmeQF$o0yAnuEIQk^mNT6$YdI zW_Z)G1fug{4+AQ}D5_#YRerM(7hKva3PN9&~ z7ec!W%_?>d`@a3REcv&rA}=WlRg4i+6r(L=@nKRy^w(muSq4Ah_il#%NKtiZng2Dx zE*AaaRkLmd0ZQlk+8DXAC^Fh!)s@q*&Q^J2 zd4sWxojt(* znJr6vuYkhN9r|wzUnW}>8{=WU-ST_M21~3&sZmC@iMP!u(7yG%a;>X&hZ&1{^8VZc z2dkMHiD{Ij>)(dt^hT_DyJawHcw=lblk53(^D}uM3_0GAIfaBw(p9>LC|eei3bbLe z)&_gF+L_wW>G^d0ddcm5$81ewU8VImX1UVS_#7w9(v9gS>dOvZx`LGsQ32p!8*LUD zrd_fo|9xJ&1GL>;cP)(~P8+#K2O}@+=zg}$=3PX+sHV4jJLhma@}UZqr~NjAErLY> zRUnDGzV@%qV~m)aG>qu;hD!onVUUFz3g$2Szn9pZ?bF(FN3^`RC$0mKzJlbdD&~Z) zoRt?;{zQbVaqOBAOWhu{ma`-R@1a9^LacI-DH9f`xH%5ti6Vt;!d}8>Kl4 zYtQ~&F1aZfLW3d@kF!eX*))t9V1d#u`trUpX=^=?=o-a%)O4_fm(2f<^5yP)vgcc8 zJMkYP>r44YP14WiXBt}%!eYxfk}j`nG*gSJKAH+H0ZF<1o_EAf#mxaB>oOnYjzdQE zPEU?w)oCh4$;vbP6;smfc2#bV3sl7wT{ZKU`vDyTA;-P-O2y2OfV2M{`~^K}*#W;A z&4nmdeYskk%=VSHjPpeu=Tz#IB$m(%Z+NY`M_Q^&p}moFObO8X;Bp0(o+DtqXh=7` z{TWiT!a&LYfbvm)hsGn;0{-UM7K zpMw_wy*6*iI-n)~5B4pe9EN)y_{~vqu&-2QBThd(n=eAdG>K$YZ!ywM=8Conb7G85 z3m@JR#exawSM{m?G@&^h1J?<5#%7T~tx;F1e&w~iwqVq&%zNLTk~8R#%*qv>=2C?! zldmhA+wAbJe%tu=6Kgue!1N$dw<}2mEtSn{*hiUImf}gPfLB_UD5%cRa3a}$`pswT zG&}<%O$QQI?)}vSD{Hb%yHdOH`3qO=+E%J=F~kfrqveB<=%s(v)YfQl&z|h}eQ@ zy;tm6!Bs*5Bl#XJ)nUQqtzTXz*Ke{p(q~LJhs9*)C%*5_2(I49Xaernp&uRXbd7*l zIC8cbsQt3tDbBGM)%H?QJ*t(|c_ya}p{8&KZADY57E_a8H+ItB@Km7>EQ^{IGB^)n z30OPMZ0dZO;Etvs?<5X4mjj>TKo_A_iX%RsZRk=N+O!r6JkO$a1AMM@IG|F+<7Hyr z1@Qvo`t#Tpm2h(J_*V4jGKOw3VgyaZ1p$Fv8iI#SFtkvBqC_Z4{=D`D|-X5SAKLC9@Nhg}q7*6N8&o(itUXd_N zR^}_EvgL4Fyq6i~Ziafa=!DaqGntbtwrrImE7#dBja#Idk^{}T|I^{ZNzD^d^&+x`pW9^&V|jOQN!@iq=fQYGHcy9Wo+tzlSw{vt(`MLTwvzqPrXH!LXI4Lz_swd#bEyu_6t*q{;3 zZ;D7UnKFPo#Zfdlf|(er4~5Ri6r7brqCm_#-Mkye&ks)-2ff41&+|)sL7!hqIo;ar zw?9${;}MdDspLVYc&E?TheTyH<%j27n=B?1UN^&2W+Q{ePh!P4XX{MSNw@c_NJ^B` zH}FwLulc4)DT}*%7!&Pu6kYGnnmd5F_(l1BxDZYN^}LQjM0H#7eB6PT zEmS_SoI-McDWC)dhP{!HZ=xiN|ENEz>!E2levJMS@joD=(NY&;8`T44z%}NF5 z&#1L{>^>`~yW@5?vejb2jpobgqFfVP5mF7X+?oC%2 zPSpBCG)_A0UnDanMkOrXSwd-nY|fKE*=`$zo#}8v6w@H1aThm4J7#vA{2TY3G8ymL*+G$?X4}gPCnpnNx=>T@($sH7TeRBe^o6%pF zp2dv!@gs}V()lg+NhyK6pX3k?k`bz)J}P&1+)qN^ZS>C`zJ>R94RgbeqI{InOWX`` zZ$FrBpT~kcFH&&XMUm49zOrwk*Y!m$y-s8H&9I~%4a4rtDbW#+FXO_;dp(kh%E!GX zm6-adfMCD_y(Xh!p82OgZuTyBHdjiJ-|NiW%%>LsR9j}CFsCHpN|rj@N7-g$?ee`2+Dq275W%^n8Z7> z0&i-Y>9_%}h1cKv7pO3GpWhU2{P_Le!hy)VZEn}7lamb5*y-R3WE?(ay&92tx1RU- zpu$pCZ;%ZkzxO~t$Ej7o{qK9e$41jlfq2<*znG zJWBGtpI@t3zLlCFoXdM%N*{&18c}S`haw2$v3{rf^w)wx7RO?NwtrHx`?DHh!W+c{5}C z5BV3hpmOSen?@DXvvqxm^DHJ%CABLy&o5xMlF`fgc*~}LdF~ic=RZM+K*nKXm~XAR zf>e1fkkK^w3p-I~TfGe?RyPDl%=ydp^U`o^AE!c=elY&{?gE6G{Tg@qEmVmI=C zswAs~Q3jh6>0_ns2#6pmqzs#C(@0OuFFonIA!&ek_R0~xdTH?)Vd0Ec<;nIpF`+;; zmZ9zCrIqQSiQuUYotyU16d_$4a2Sg)h-7YoGoA=Mhe)8rv+%u`Sxj$zWp5VDv%0YODrQI@{IZ3y znAuPP-Qut^R#Xr{pT-h0fJUWsj5~B(zl$y8kMKBFb9-@)=Kp+*_jR9#l{G=D-2-;L zkiXsKi8~d|XC{L?uq9#jY_(NC>6jk8#hCzwgtd9K5*9k5lGF>}WE)O6C|j8qFD}{;v=H7Tg22H zVtLt`r^3r840=Ldvs6d9>%DRmm><6bHoeh3R^t6_b2ibQu!G-_s z?_;al(!%x(UGv3c2?y<34DDnSNI-gRU@16Tz_55lUV_|$w0NNtbT${Va%|> z_;p+Ac!Bh4hJdv{&seA6OWLEOKtz2|T9Ht5@ncJ7kB#3Zg5zfz_~t8KjtJ)WWSC`%qrcidzj$CQ%C0V?_g=fvUL zhtxC!O)RY!n>){6=hJGiLVERdG~a$}kH%(;ZCo6mZuhj@jr~SWQS5ZRhQn#E zHE>6>>wWXY6O~$(XXU~YW1o%R=@eUH$rL_2E)eSOurD#=Jv@LHz0a!sf-jiiDV@lxPxciBXc>cTFnz@NRY zb}NV%soq&MzP}qbI|!y$NF^hJC;xD(eUVr4@Pn!YIk@p$H_fWPB}dDSX|=FYW=4eQ zVtTK9sfpt4?z|_?^duPmM-yFp7vx)Vz2z$VE#PA;xVGo)cXKoA1LOJBFfJV(JUwKV zhR)YRN0HUAhmtR9IF+ADrvztCPM$z2Zd6C*Gm1xAis|Kk>QZ3`Ytr!gyA&fiX{xkH z5)15?qj>CHxV=uMVU}iW0L8h5$=8x3(rB7pmLha;&=mT0526W2wQf8|ZZMA&B(>^2 zH#1TR)7<5!2IQK`c>0)4JC-#3?@B+nZ*JmHS5Z+`Y@nX)DJawNe@iX}3quZz0tXK7 zXem*N71jaL>ZkCutGUV>A4!SeRb=<3jLWC5Llgi0!#d^08g1by-S6vIV+2BhsDlzr zXk?5VO zvWlBLdJ?8?qxFFxHtP#k8{Qn%jfW(F{Zu#zCrAX}Q}d8}0)O}DAT4;f6HBL7uHzWO z$pgNi%nQyHlaYd@ny3ciY&s2JqiS=sBKcIS8ypaopN!6FHAqS;E58t}zmdlX2j^%P z$U*okz3qOw%dBqH`#WcicI(WIj|o#nrb8$4HV33!6sAcVBPa5iI9xqxAMe8r3tQt9 zra$5t9q^aC)BW&LojyhkObQa5uar|N24?_skP;Y}@##5ZXXS|_QjwPD4dQZiIl{($ z=E*4%Pl-3bFl}@k$?~9D^oJsyeqZ#KqR+M zd9--tL!Hk!i-w~hs7jpgyEJZeA4|G1s@VFU%MzO@nwATJ$aYgt!Nr$rNn6biI|oTF zSq9$hgga3j#yX5L9TRKw2Y>IB?1Wm)(i$Oki!0g)JVA21ryplH`1jaZS*-Wy-4M&O|3|&K-G!0b!=> z&fg+&T8*f7F)zrCj}X|UO_?9k#0LNDY#OcfR)#_R1IqmSZQ<{AYn^@k|BWr@=kraR z8cI6aiaLD|Cc_ikHhyGS7fJEU0pTmf_qUq?#Rbphfv)(onimCKyACH? zn@u9wRFi^LDg($OHG<0fMw4q=d_Igy{BoP}0o;?5$Z7OWWz%6!U6PC+gd%DSElv-2 z+6I2NvFY%s%;Lf`&vz8f_YC*~&MD&K3)f}0P)t1^zg1H~v$dX%yt#i(?pyr0BQu&? zkR>dMB8LTkuA@#IVaAN|d;t`a$sSBuTz6^Tjf@QEam1tN_AhSwN$UEs6~n~dw&wa9 z4L2|xbwe9tq=hvL@3XNHG+LrNyKKsU&UJt*{(dxzJ~Ok7Ut|}VdzzdJEH6>^kZ1<0 zGIN@ud+0aY@ZkA8tM1pe3*h&DRdZb&q~I?#q=cNNI=L)ryfq_Ly~=#qritX|%0+<+ z{q+lyrOeO~wU7)akuR;@djM)gwB4r>x7wCDOi`aaK<{gz#6f(nP(mKDAsi4RJ~I=T z!GNb-X92TNqdc+f1-H1A4<594mb#f9`uyew?|%1wpgP@Qsi%j^su@n`o7B5#cFX}x zF5+XG1J#aK=Ar3M6=vt^Rf|^_(HA83ZBKGppjEvLRl=tF_VA{XyluUn&lRI-GbU!} zxXK*-Bx*%Wz3vA#+p3yG+clZ~zUNTTE!>`*E9!OV42yhypMRByjC>);N5)KpR&Kmx zUwtGP=%-0ya{G82T>{V+Lg|Y|?uL??3eal0#6iFkOM-Bt3 zup2qIH|v|_$(tkDDO7Gc(#3=qPMjDtWjSoxVWKJYUxCjgh9I z&hZBiTdbXXp6>?i9MP8byA>@_$mu(E3@DQP?1TI*scbOY`zZ7t0~M80sqIGCBxJn) zFuC_|(U;%l?AvI=RH}Nbb%Z@`mdRYQ`kQrt^4Bq^$iy5ZtLEvXN;jV7EWkye61nre zFwORSM23neXF^v5tl+o!NM4zob5bJE=4Cb#l_#ZgVMA6Q_5`K*f2g1j4I^riM737NMonHJIV zIh-D1h+>2QF%r_aIZN-zhIu__X2g;skUY*x#^C8eA5`rk)O=ma#s$5UgYatyS zm*e4K?q_nv!s6XXwuqaBpt-uD_v?ABoPI;j^{mD1+5X}jr)PuJIwMjxx8fmJ0EMnv zx9Fubt(+p=*d13|1sIL|Vh!K&{|Ol@D|FV@^oije850FigR$A--s5D-ImkGIrr`dB z+MT6y9|cYJtsmLt7gK2*zL+qIdih-)=?2|lN*i;ap;@l9j1=*9nlw_N)Nd?MVM$By zhqq{*C)bZ$l(?u)GJ~8NYCww4Tg&8p*pXrS)%Dk!NS$|Pi{e;wn#|Csg1QB2X*_(f z>hvd3F5M38qj350qQYHRv_#diA3zP(mNXP^Q)#J7Q9V0KN3cKPn`A7RuG&M$q2cXI z=U-;uJ1=~_H*eaY{v0+*FJ)~7{b6bwG38D7=&k4$KB~KT{6$G84XVQyfP2u%uF0S#epP4^{C*mg#=?n)hUW zWoYg?S`LGk05E1CsNl67Z-Y3fET5x2=ENmcF)@J-UuOto_&Nt4mc1Jc4~Infkdg4Z zxQiZ5{#IwE@dJm`1zH%-5`AimzX7VV_q;D$)~`MJj`x5Dx>T{tfO<{PR2$^TCa*Fs z_5cYTn&Bhf#O@tEBRBUPi}<*Ml+ZZK+)FdS%+18@@uqDLGEI)y0Z#g2;L}qYwZzNVDQEN z?8V-|_m)l5h7b0F1yd3h_csR9*7Ye7Hj6t>cUWxU?L41_6yK4M^Vi4y$NQ`G&5^Vw zI8_kjPuD20bo3Rp7d9|D5pP`l4W5QUd^p%@&syxK1;jjK#6O6`BmW|6vpUC8roKrD$*ON`Rwl+15 zFxayFAz4P>wFn1Ub@$+FVNHfK6;jpn&DzShms&YTT_N92cC1(9G(2=BalY;mGPUq69r1VD0+k;8j z7bIK-qet>A0W@uEge`Aj^w0C#Pn3esXbluhQC}5sX7fF?9!-N)?_yHD8d?2Sp}~8T zWFjjmX7Jl{V>4T>E>0Z>kIa`+(aQNUX*_f(o2Gv?2%K#IZd6Rnz|PKZIXMbXPi>Vn zP|5UCm?`=JThW0b6?vusUIJmJ@@^{BH+XFO%!k%nanDwOT6&>V%%` zS70LzMw&kp^ZPM)75ze5{i6DeJr)v6%bPI{ZsDcyTl@JkxzXR(X;|^T*?2ebGx@7g*fs0LPa(YwXgzCzY2Z|qvo#jR`n_!Nv+wYQ+T&uwV&rmJLhnx(|J522(KAe{=h0f! zHTF?6&-(|KXU9*`54Im8h*1_P8E*D<3BJ$Mb011#<~Kg}t&s#i%R(t|5Ue?RP1M7; ziVrS*5tylo?Yelx1kT5%rL6HV{N^Na?qVbHO)D_v|2`vI_M@%5+U{W@l+mP`%5x2kl4!-;#ndiTAo&>Y=|oUBw}?P~kTt_07c z(kY&cKS)kCxe|Gk!t#cZC+4r&{uQNQ1m`F52bj;mt0?4vll3IX@cKCQVlmCEVAwsC zU-@`-xshoMEyQTc-`@C6tP5F^!WiVn@d788EFkZ$wF0)d{$I*BLtz^HA9)O0|09i; z#qNn1lQCm*!*3Ob#ifk*>#-r)Oi;soV#~KYIz5uA(`nJq1mXeF~ zo2VAF;ElfE^8<{`DKEEMakT6sZh3s*ZEVxjDTe%7nO({5Jn~viGH`0MczfP(B&P)$ zC^$5TnA<;OyXZyA>{ob(ecKj9WYBbT`+tC}p8uaQTMTFIR+JV;v<{VZ8o>^uDf}UC zgR(H1STCRRo711QWAG;ejf;Q-`^%HBTm;lnkw-XT45tk?$Yk^@jUJa6I9C9+ZXXUV z475)88;rKY@AkXCMAa$FsG|1$R2V`1hmB=RJ6AY_%#CF!N7oJa&CGjlDfB zk&5ZsZigP1R265wlc~L3REyJu9J!xNy$sC1$T8LiQ_G4Er_0TdbE5m$aHo!ebPXID5M5QhKSly@>^05vaN?8I7gir+rFIb{YDj6)92t;6|`H zllMpxzhCNxtL_Qk`3uxL%ZeYS2X#9t-reZn<{BLNHq<-G`}|ecKl;M)+}&)Lk|CqS zqd`ex9qh9epBB~-@3Hm==cL_lP`Ii)Q5uK+YwnVP*`E9`2W{rl*WDuy56<;QiLJyk zvkKgC0X`Uvl1I}7@B<8M04v~pJ84u@rUZ8WXFfE%_ZnB}`|bfAc4dS7u;>IhQGK;_ zSEY1SCUnmG)dP=D4gxbf$+}kSh=m&HGRlrC5Kjs zsRy387w~U-j`OV0;n*hKh3H5`j~#tGOL-=W`S;ULlr_G zf-!x4+@JxmDFN{nikFpN;*!r1L@CqyUT@#79>%<$Ez!@EX0&+a2n1aAUnvI?pe){r zn<3Z1@)oCyH)%?YIMao><*xMlKWLnUMZbo?3X3)_F7CV;hD_@nkM6f;w1dXSEAy6f zf$<(PP3P~AWUm%MiY-+@>XX43P00O8?ch=}Tzh9k=2GhFB# zQxaub1W6iEF!xffTTk=sO;7+`-t2m2^wpNrAIEeK5^1c6JhK=7u1^4JL>kf@DfO>( zA4>_-$`(RbLYNU&Rz$!FGr!5JijAp~amV=ZFOiKXL2lSYTZoWm1HE}~SJzv?i~0FR zuU!iZ2JL~T(c3w4OaY&V6c4lB;R6A=WEL-R?~V@M?LD)&)KotIkBy=t%JRgxBo^Od zIxXdrv9z8<-bT$@1z}oh`n;dQ9Tt-o!(P9nudv0Fn)p_?KD62`3lpboQq=UeJS&a*4TKZ56qJQAILQ7mGFi@ZbzKs>E2FL6TL!mh%@=$Q&~9nAim1uu*g> za96@856=(w-VjSj`nP1qGA&VG-Kr4Z0hvJ;6HE{^FVS*K}) zH)~4n4kZ7nrpXNwsn-g>VZ$o6F~0+@2!7E88rg}BLPokGjpK)=yF$eN{^GIxQa`PN zUmnt+MnUN6`88COdA?fF>*@wihe$v(b%EdOF6jU!uH43^cz@f}Mu)Hb!dG4&NXPS; z@mKIY=cJB3B?H3gN&!us_lvzSv<9Jb8x+OP8OpB^>QaPmsz>$@v(=8ROQK;dSkxRL z@4@QH@UUmchT&{T>I-%X5A$W)eGUyx-P(FUF&|T^{ zr3UX%N(xG1#)c)$_Tliw?pGy|gwg2Xw1_Ls2S=N`0Q-wmV4Y9 zG~RBHW!USryGN<(w$?e#^IA-3k5y^I(% z&L=?{_PJxOf^)ole0ppAb1`2S^=Y<;Dm|-o|K`Rs#;;9_|0ujwPn6Yavn)v649$kj z>6kl)m_9yAC<&+OE2G|M8nqg9OP?jz$_~|kF{}DVl|Pju_S1nyv&Qi77>u==P5xhM z0g1wTK%Y@_jjG;>#GyM9hs6=b^uWPlDGB2ahfg+1j_^Gai_PeU^#zNGguxNcU}p~% zMltX5NV|YqVheR8QCT~reII+gAP^E7aTF_gdSrU$x$XI7_hdVG!>p9DRr7(R`Q5&x zhSj5(UR`M}aA%|mLf##-Hc*`fs_ua@yLTS?FR@T?KiN}ag2uEAFx60Jo8ZS!eR;Os zU9>hwtcjaIZq!7;j6ge;gW!6E+=)mMK3#LAA-4y}pZpPfa75ab#S3V3{3En-BTk@Y zqiWj6l-Vo72V?&P_jkAIcjO#D`I)`rr;*QVc(@_M2|8x4m`fwOYr+-kI5GLe;?#GOTjf?-T?5Iokub zG}P2vmjUnTu2e|%7Rx^|s=yWP#>@Rs=&`uK%;PBTd{|1YFNT{hNw0I$WT_JRHnUJBH5ITY`R{&??~bi34}3)@-f%l`l>Y^nq56 z0Y4)Go9k;rFd%9H&G&XfzJ#u?N_x9Db#SLKBuz}XLSJp>gx|=$Sdb@vXwlj z{tDgOLY?{c`9%1O{BejuF3D;|*qa|EmpjN>iB(~v{%D=FZDCR;^w@)q0XJ2N{o;l| z`igC&f6yI|$)Rd)&1}99wTyN*0eXhmr2ikuz9T`hW4toZ3y=r=@VkbcyFfRLJ%a+&Rvlm5~ECx9@ zYPU!Jw(+uU{_0mE7j2o9-|!4Pg_@A>K=VHxP?Y_uUy9`7g))iE<#8m#M0R7~O^J_0 z3|>q~DWAviV!fBY;;$%F;=M(b8x6y-k~WdeO0rZ9Xr5vU0># zBx1RrF5K!}fr3h-+jvnRE`u){sfM{-+r|sT8Nf(a{(!`S^4szs;STGrVC-~a0 zCWB62rE4+RudLd6JbxxOG=%na`MGb%LowzyaANKz=-c}{MmJr^7IRnP;MU^6MB(V? z6*Hvs(=>%alfd@m01{zS(^b(e&irF#oAWVhrUt_yXx{ZquQ81*6RQ#M{u4y7IvM1r z+YYErk}vQW*VVm_k}WFfPNrJ~Ioo|YDBv%RHaEg7wb&2>7U7i^8TbCRi&hzSMi&B+ z;fo$BBWOU8v>p#J#GJ*oYlj3`Y7G?j%cAzcZ#i#QWT(hk!$*m~LPZf`Nx*qVjN6OQ zVOipnL>bLbHF~jfyq_<5C>)2`%)hF-VAYxhcPz}wfQ%da(?hFwBXmZe>8JRDy8T1{ zY$W1xrNdHl;bw2Hu+Q|rrGt6Gx?Jbm!%sL#S^(7!e{cmO{w_QlVy^bmwIv%tuAjAt zkr8u{NYCF^IyzgndBHF0)}E2&<7P?xT@TRsF&@}W5bEa89m+U{_r2>(fq~)F7t(;$ z7IP*5OkBYjM`Xw>7MtskLc#9Kw5!xtcustag^q#f%tmFwRrCW#!O@#+Ea~xV39CzI z1pPL|R5^3itMsKvmu5veV&^CJpku_GCXSni>Xg=O8R#Mpf3Ih-^AGT!=av7gtf2dz zaFLE~gkDFgzwBA>uc7Gi`|BMZXYdOQay!$Qm^O5y@u4y0q|Qj;;^x&wZGh?S#{k4Q z4cJ3koPQ71X*qRRLzC31>(S^DBivq}FthtR-}whN9J5dwgqnChElB?Vv2+d$k%ny> z-i@2vY-~0ryUn(3+tyZ_U6XCw-fFY0&75q0^S(A{Se z_wOVXqSo(2dCeaG=e&`s6Nz!xSc>faIx_q=(r zfr-WG58N5F40uQmXUb{xT(q8R@VR~((rIuBWA*>Xob&LvSfCXrB%3Prg?WM?SQMQ3 z`wiyhdqK=1I=?)SQIaMUHOUsB&pX{CkTG-UY_3gC94q9NRrX3>U6V8uV~PyV^4k2) zi2rw2tejfC`BQEjvScbpqPuI`qO?ZE0-jVQ`9xExVh;h~dHZ9%*TwYmVcV#~_L&xI zGFzr!QmLd7%S9JIx-gq_FUi}*`wC}j{Qfi@;pw7}<>El0*lCVW-U21hZw=xU44rYC zGsUCAm}hok<&=m{Cb3{&9-b&N-;uuok$E~H1AS0(?^b*oEo@BwKegd`b}O)5V=TR{oW#L}rwD$#mqT@TZ(KQgs5jc<-s8d5 zuvxp4Q(3^u%HI$WI|Nx_uD9Bj+K)=(Wesv^vZb7canRbQMXfm;B|||;fYl0bX9i_S z)6O5_6e-FY9Q^wWF|0g2pZMJKEm1t#k>K4P${?$at8(2$!%HU{$Z4GluiLy-humgA zu%Z3`SG!x)X4ZVuG9e~%(6P_~o-k<++j~2it;q{5GdHI?>JIC|XJlVzla~2BZxV?= zUr_YBUvna4G*GuI1vO4HG}~{#grFx;yTt5gPIhXx+p;{KjgKO z`yuT$yoV4fg)7KP4LLmp*0Pj~wkdvUZrUvThb=cfS$-^SFoiDQJcT-}RZXsm>Y<=& zS~BRL>H{IS#PrADF;O=8=^cqwI=^VBd?Bb0HzS+uZ-aB5!lf_<7S`40)Ak2Gth>GW zUIr$g&kb<3;Noa9>sdd2O7joPI>`XTM%yu#L}fiMCqY4(n{>f2U0A35j;hy?%1%0U zs%$w;BwD9pJ?fZVL3zrEb@y)Bb@V}oACAWPfs={{9v_+Ijbz>yLzwlEqx}iQP=|{I zzEFq_TTBkzf;XkpG`|Wm#@K`gM~?Dm%l=RC--)gBuq?Ah!N)$GE9}0DaKN+!iu{;LwKInWc5Wa3kk7 z!0X}1M#z8@O3XiXF{Ev=kqTze#KhsnyYwNGzPxeUMhLe|o7tJ%Xa~|czb7(&H@;p~ z_S3{fpT?XxB24)9@KLqDgH0suJ9GcB2%Ze52i4nK*A-eG53P&|qV{4kZuivG!yIx9 zj#%+lyGLA%&2mGlhC#($5aJ_}*=tZ?*XyB#(s8X6A?x?;qW;N@$3>d2)qnslM*77viObmMWcrA^2FbUZ8Kl~2} zA-x_DcJc%cu`(x$JKd7m_ywunEa9S~h-hm(@$J#FKiF9H|H@xZJ7VvnTW+?gbzE;RzMkiGUF7P5Q2Y%DnSeT<3Yf{36{SpUudb+VUnp`URHGkD&}o!6P=qMj`#orQmEkX0zNN4L*IEh>h1RM^n1N&n6sx{ zmC~TcfG4m(>#jE9tt9M_k-7PQGLwgZ4ME39e^Q$0ah%~_SwDwO_mfW2Rr<1azY7OL5lFp|?A~uiaQs52K}F#dM9XG*HsqB)(z*OMeZ4_3a8lrOwLz>n4I817os0k+%nH=`KD3)&IE)RJU{ zka2sS@;Q(dssdX|ikyU1H*z2)%DTNWPiY$4?DmF0lj|!Kk*oa--w?9HsZ}8LChxeo zI|@xVmDf_|as-;#p-YGZE1E>q(qG#44nQUPuQOPL&_#^$v0TS7z`F;C8`_qt?Y{{@ z?QHE7%I&X+M|9d{K37?pa&d6yEbxA&OwLh9H&6E-7?avVc?r;bUbn#vK94gGr}$x0 z>k)q12|O%POw2JDK>aTFkRw8d0%?5D*Rmjo+yLd0PsIPW%?fOhx8`)G2$k%+;SUq^ z>w;h7ww%hJk$U_n^A&K0%P2ZM-&;Qif>e%HJZ>Nqw%=0_JkHwnUjxTmPs@F-u^Bh) zkDRP1Fp(o!H^(2UdBGNGYO%erJ@jKL66K|I?L1C6a!|5X=aS|9(h6@RE9yM8Pv)A| zcS3Y2YwbuLEzwnXIW_d%8H_q@8+Oa+SYI={(%5uu?K7#re@j|Q5(=I~D`a=hrEvqB zhcN+#up!|whv0>4W~((@tXfSf!}pxAm+-6($0Ro&WX0DzXc735M$_S+)&<_PEcT3r z;tKt97{VIiUtAyjHBSiZXK7E6FfDB90#hC|gEp0NhhDxApExqO*a+iw#KUgPPkW{kyP$dtu)HbD$8OFb^VX49{L&sKxg z9xLe1mYSW(N^IF2z8Ku3PskFgCekA6y#apl2JxfVq((uo<@lfbo{MY`E*F&P9u75D ze1wc5M@>KO)2~M`#qw)h9(lCA(Tyk1)TWCg{AfRK0TZ%*#7d{=&M9GBHR(5vZPR+y z^J0z{O8B=#X6TaL6@JLqe?&KH{LCH0M&Qu2UrT?Q3??a!Z-f&++km)A1ZIw*jo9Gj z@t;g?&I->EvoOXTg&+M6qm-t1NhHtYp8-Kkn{xIZDNhNDn`2O%tacOH$Q8!9?+-55 z`sCZzv52YTp$`=eYMRQ!qastx5(n4=W%X4dJsBz$1gd(TAHr%SoSgRNk3o$kVg|cEZPI~%Ds6RZ2 z?v&B)4-n>@_S==Fpd0qAF+#CoKd5K85V*g%<2cWZcsT(wm-Q-A#L9nT3y)4P9H;a; zbIf#FW}cdoQr0==Z(bS%^f2P3wOKow!b=CEpwi1DM28{9nrwE^}LN=PMPY z@CE)?yE(C~ENL!JWDT;qympbw?n<~nvQBTOmQ2zh*xh*Y}$$9YTrRstARV01IhLOqRHa&Ne=Ph+`+`?(@51jF~3hK z>v-h$*si5wAGB=3yywY!zAaTzWKQJwagS0yi%ZwisH&QPGM46PeY{f3r*wRs8zUK0 zjS6j!Jx*4|!_(H{W{abBvVCQB5#xU`JjCeRz2{xXD%ZGJa(;S~3sV3pI2s2mU3UHv zPztMu95H4jxpw`wU!j1;-kuZ@dnUyxf}@uOQP2K7Gr9CTB?hK?SX_;>hUfx<$b&$S zaKC#sQf0}+#ue>;SI*Fqua@?-9P>9r3v&G9_pt1~u{CZWZb3^d+@H-iv3rWgqWgbZ zcv&K&El%H$2uFWOsXX5==dL!{fA4IqJp`Q{MdRv#+uP{43>E5n78PgmRg}MdSh!V9 z4_N$m>7_3=_vFn0VvX1?HBHfD=1M(C_ZyYfB~4vfFAvDp>uY7U)&(uiF&&4n;B7`_ zt<9fmYJe2X7}Z5Kr$>GEN4nE8JIlR85d4KIyQ55CaZ!2~P40=jTOp8-621yN3Thp< zY1h#oWl*wumDi^XICb_lfi*(BjAQiv#__#fGxRY3al$m&jzj|yyu4Ad1ffOOicuv3 zsJovYm?M)S>4;gsk6ZP-Kz28Ru!R%%E%0%yuL?r&u;%t}&ni0C-5R1SXZD-*U_NUh z+RuR!mvaO820YQXviWapHKlhu8!)&|oig$TuxdQ8s<~4-i!%wwgAs8`S!3r;W;Ce< zJSj~w@XX;hOwqv#x*@d{c zx#5(ID3?_`s(jBmJ}BEx#i!p#9M~M&yFyaawv|>N5(lv_8a{1lnEXFDmvSlxXnfGt znxt?5Bk1hTJQfaH`#XarU|-4}I89Xf9|I*R)p`xTQWbdk&Gt@f&+#uXkg^^Xp8`^O z%=BED(ohyBrW>fYLCwZ8_A>voX%yP>hlKI>q&NZN=rttId7KeZ9|OuMT~VoLJ^37- zU&BKw_Dkxg;uB!^o*fv&WJ5Kk!i0SBZ!5crV~M%mk$%0^fr3T~BRWG~@oQ}Zky=hI zwOUYl@lw&i-E^wE=Gt%8$%&$#p3ts3#W7c5L{7l(ftx|GNG8 zjs}Rq$&y{AtxW(#k}Xhrt|A8++pw{Sa0@H}PN)=ih-fn}W+tFw-SIx0cyZCCZv<}u zs4=Sz=2jJ>j*;PCF*4LVam*dCLk)}qnP@u1N+p?KnGfP29#v0++b%!`J=aai8+D&| z{%n!s(Vsw{j>JzeQ&%Yu687Hgu&P{DebeNm;km+Dts^8m3sm3AX*^?HS0DdCZO1AJ zF$hL~UA-@FI}7w`63R@;jEzth9BMEnG$Ck)RBzr$fl931V1 zgocK8{N5Tq>{gkNvTA~0#MkLzZrlNwwUnd~0c61R+)>piYdl8gZYpL%E2DvZf-o9# zgu(#$i)%=*8l;bm2E}Aw$hPCrqybq|C)EzpUYdi>MTG3w74dxHH% zzNOwf%RKH0V{JANRnAzMP2L_^GlHxIQ_aN8E~Yqz+VpFU_~kDTM>d5E4Hew1sh>6h zK~8K2ZRE3y+~0G7Uu}7PLo?N?b!n^3pW`7ePTp04-kwh`rxV;gevcWLG8SNX;>9{A zA|X#!@{{MweBIq5t*ow4pQTBCIijL#azG1^4iwB-95=7`djE-hu{zPN zBGKl(gAx8Cw|!X}7?CMFH*PtwflFbJ4h8FR*}f^1t=(om?Jos3Q-c-I5!0Vtqm3=l z+HiDRqdmdE*0oLW=BLhJrgw6=cTGviQvaRapdOgI1VbsGNHV7`MPeM$pQmDUdTbb{ zZxP2md#bWNM6fuj(GbKiyH^!4ex@8CI!A;|B&;Ltzp?MQaL`vr92(M z#)qX+@-5}^_Z9RSd_iEVKC#}!M0iFV^J#9FHOgl(EOZgoqP;DvN{ozm#aj6$D>v(V zkVSIJmQXY1p9=vK_ghvMGBKjg@gSBl9+6Js&Ye-W%{5e`HmAXO)CcJQ`hZC$5xEu@ zQ|J&U(3Qbspl5++h5rXxN1=yNUs7z8Aq)vLk`Wrk#KCTMRLIuiNXIvo^-t z#JM=5=n@y3%7bS!Ze?4OU(pdA8Ogg4iB?%nU)Y=<2|L-$=eIHtvcz*rdpWnHI$9VD z!^3;J_%OSnC@*(!$7mox^JQxsWOLN!bt;(VSLl7805y`}HWWM|M0-Bczo!Cd+f5&gB%MI`d8R4? zFez?vDA8Vzff)}JFdcm7FZXBUZ!4xIxxgo93LBAxNu zPdcH4V3^VG$6C`Um+3xw5^oNg*Cw`|obT;FLBkgstHF`~)ynLu*_$F8yHxZ5~e{D}0x(S~e^^iC_L`K5EyzsX`x9TCYpLr~-o z7MTrLN(4t!$-;=Z96>iP>S0Lup^YBj7%#SPWX0XICSJR`#zaw-JbTkCuoe&{BjMGu zGKx=+w-oS{F!G=cTu+8`d)UB3GO*^$-FI~n{&R-e=>`ddf?Saibvs)iaMq+Gk)JyE z_=zYhQm%M*FwL8j*xp)Jx6yZ7?I{-&)SN1<@`di66emlh9xKK45I3kgskU!1L_|WY zKbvPPum8Oct#n;&HABWErnwph0lGvRU7d&OZ2;X z|BO8gj%ae+1G+FfAXqRLe173@(3Visf_t>j+FjYgwAB+#0%c;WxWBSygV_1}6%|zU zaPJpe%cwiYn#ZZy0$vlpG$!BZq_z29*#lR_Z>u0SvgeYm){6bJzN+cy&Mp1v}d?bdCb!GuSTGUpB(!N zZ#yA4!Jkih9$_ezT)TS6lx7+bcdV5f;>L%j`;-I%;70OHm0#mX>FZHwy2bbQ(|%RU z;N!7E~3u|(R{-Y6A$Z6--uCv;QiSAi%{>L%K_N7IrQj9CYt>=|O>T{~(icA7!oUT5 zk6y*DU^1HWGL!jOk!UA`{69Ey4!wwoN|4OI9{&iq<1k90#SbHnfUA`D*Mrxw_(2+X zj=m=1yJXD)1Co4+&Q556qG&W=EQS3sxwMSKt*+sVdN9x<4!VR11L%Kx`2W(vVv%G? z9~p{bi1{ojnbFMNq$TW2&yUGR-7aQ_tRA?9Ra22l+sgHDglMX(#DZB}jfj&N71D`XWBGb0EtR~)Oj%>TFZHc{fm>p(-V>6yl{l{k z#PW(vbU>`d{{idxF)h35bzo-7D$wr)F>l(@9=i7rS6aR|s6d)v1|LZ?BDe)r!q(g< zti2f8Tzv_sb#`oCJu)#YDrw6zJ#I~nAZ?U0tgz(*3?!2d#FNoTGwtXoo?T>5v42Q_ z(m{}I?!RkrMIExA4jn)8V*IDwVhJOGY_|vEoYrjegd6Q<1u{1Ta?T&Rs2)kw7?9iX zht;q5M|JCP%s%ABXfSDWHTkgfE=?G37Qor+amM-aE<4KV9~}o(pKo+XgJL%+TKsOE z%QYgr^{C?Pj4r2|304{t-a9$V01>VBnk6}xD;;6k>q|YYAe+@5wGVZDi`S(TdOfa? zNt?7rqi3{3Iobl|R^m$R$$cpcvT0E{zxR6;+R6$pmrlItf3}poR4$XKVjgj>^n)-) z2N@LB{K(Y?4)h25hy)x7wO}*boR69+r=U7#4l!53Z@NctS~lCad5X1Uzdp2_Fnj88 zUnXJj(*&T|<<3j7e5ojCMoOXWaACVmn|s#Q^j+d(WieKe`XMC-N^tD(2JP?3`9h68 zbjg@0c`?ZE_*5-**mp(laB%Gi1+-v!8CcjzWxw?m>X*1vX-Up|xV$op1!i+i1RGJ; z-~6)!L_E&)lyzj64|THe>1~V86a1`p|2X`|%yy^Rh|I^#Hvh`l^@HkU^%j@rhIFY+ zHjHe4TSix@pr*)=#m1oT;&pd?#6Ka(8Gw3qRW_vy-syXguDKn=oW; zZQ|Rf8#C+80b)o`mDvr+%MZU<9JvDN?NVEn^KJ-F2VyV~urgLQD+5CR;2B;O z)2FvYB}&}k&(u~Z6NBs9tgH-nPz6NiS_RLrxTxY0&hXDTlDWhNE3dm?Hyh3?o3+;} z?#TBn&S2v3*r#{h`p;XGfPcJBa|f{>x-$6G|4@dd4XrP5LnRam(i}GaEN`R8e6`YO zw08w?su)?D8_9Db(1H0HPhFWv2H!RY(HcGdTf^3S;3lv&J32%wPe&)}JE`ZXJK7?p z-6B3wfRS_OW>#_iTM1Dbj8}I~yqQZ3hj*iXU0$!h`bA(8<5MPzl*D}by%@vo_*Vto z;T2$G_lg2=+zvdR?}-EU-d6q2H+z23QE{kfIRl4p5ZF|8OX^SYkc?A2rj_*EgEC$V zB*$xKwLLORPUp7I%$2I`+&oS!X-f;Q1yCs3tQ~qJBwTRqVx0A2iJMYobjp=20tD?V zckbuiw**f1wOqgydA9Fq<3oz=3 z+tuXo26r${=a&ojX0xi%C~!*yV0Eh6;QTUk_Ye26SdOs6F`EQVF*dhT%xw?y<3$Ii zh!Zm0`NbH{qap(*l{cf~L`D_3wbhYM_Bt&YxYuW4F8*O_95f}1pY{b>5AT|LKp z<3CvrArH36MpcG%@QJ6-RxW@eabRN-B%}Nk7dQ9L0Z2|vt{Do4w@rmF$vT|5C7QmV zs3IL!A;+b*AUGzo#rbA|`{QQ0SEY8U$Ua5rjyt=yr?{Xdy%mhEn6DWGTMt7IJw8cH z29(j9quRV)r@+|=dg^~StwhWaT9#fnDk>>EJ-@Pe&9^D3Pwy=YIyYW?eO$|7^?Al4 z;tPGqGWB^5Nw2N}wAT1m+!uvBJMYEl^_itJn!%X#hS*rUgVqi$vm zJtcK;ew|&{CBiUGfsZ1MPE?6-pxXy6wZOI4IRYaJs~Jx?J_XyXw|}93HKz0Na^|@% zJ=BHD>EX^_zt?MGCLc0FCd$ISpKS|c`Y?Gbb8Pa}b18rT>HYTUvG?<*i3+5J!bL&x z1! z1*M8f+9{LaU-=U`T+!Sre@YHnJk}hWb6A|}G;0Xr3@`Q*3M3@}0dty56EufcsT6E* zMY&O|o2?cIOu24~{*P!Lv<{7iTWIbS_l2UD5=z@FcZ}M7=jVKD*_#0*Md!YSc_8?9O-8k?b4so_7XFWj9p<5JYKIvB&iz+>W8Opglfh zTaz~hRjlqG^~>1yCArWOY%KSc^emR&FRhI}g8$(f3swQtRLjx+(!8dW?=#i~{BUm6YpMz=YG1YG{9V-lCgoObLHA_!vXTOV3NCM_mwTXKF zJ#z}O_$->k#Na60Hfm(GdxpHb96Cu5kG1NcG}s*3U#M@F8hjE#2Zsj5j$Ol=f%(r$xMN|{0j%>z<~3$dD-acQHls-2R8vm2 z?!Fe?yOFi?3U45Gm-e zeT9J5eyPs-U4BZJ?&#l;^UntH>*BIT6lT9#Swd!R9+hp?k-aJP!|9yA2T>AU&mBqJ zjg;T<&p;Y->;BhQ3(HawxV#?`QQRZ9?egWRk7qx z2M0#q!J%o?v&u`OG{M9Tw}=)GU0QRLL{uUH<;dl9+Jx$9{zN8UAhZhXs1s4t zf$wuyLX{q?yb%3#HXsWVLA>6w# zSM9#t?>}VIn1U((M2iAuCf)YYI#M#~4A!JQh*6E&o;`6dz$~}Os^2O6@@Xzw4j|(# zozCm!-hj*No$>K(&C>H4yCEtyo~sIo7F3>itp8uk@h9JZ$C5W!!bpVG2bV@XUZhr` zQDwewVe2Tpl)f_<=X+tSMvJ8S?>F0AZtpEzLF=x*?_^ZcW9`cG;#OvWM`D2^TPt>u zhJ(rl+W0MdrxsU01oaX;4AKc%T>|y?oxU0EY|n09GJB@<4;YH0^6tUcPZQNHW#j(@$NSf;_^B#^wM^pOd%F?vW@(H%lXCd7_^gO*7 z=8Rg?+jEVoup1f4V8<_led=PJ&8HH_1@Axt9mP4fd&K-}tTP#N#LJG#w`j@1C7IDF z^r$V0Z!*k?yLrlnpN%Qq9+1i9{lCa>&l(+}kA^oWX-Nohv=sJP)Rk#+N5WUR}AE zECFe{{^pKB!xC$Y&NdYz?v@VG(ewsHRgAr|sp_d=9w*nA(`PP)Z&t#uwsZwn(+$`A zfS}YT3CDuuR90G@SjR1pOg~G&=LN-y23*LMo(iEHm5Cmtq}47{`tTN6i}41hn+>aT zZQcm}v(h?c!w!c%)rYa|+N?~v0N!+H^w$PQW5JTRQRBlEf(P#6Y@`{hY!|{8dI5Nm`kZThOLRj7GQchQli-^s}AcZ)(R^C{1M4WPfsVEAEi3U zQgOSe?sz;~e}6r}m2p?!ydZkNeBE=7W*J%Y0cjHO<~$Ea0_#ogd4@H~JgH}%CERnC zeq7~}zI;x9;4)2#%Ms$c6Yrnj`@B`xQ9#Uj=ykdr9=g>C_)9w(`P6{xW4H_ubIvVx z+`r>kgh)>3f;R(B%n~j3Yx@^W(Zc^4#+!{N+t@?TJ)*{d8T`24f6B^2)jK6*B$dur zev{NsT&C?qqEHmVL;F6IlG&=&X^a&9y5z(_l3@0Z*ZzKt1p7#6bh%YqW~q6#Zp@Q<7U~wF2HwLiB*E>AQ!(ra*T-N#2oW<)E7cZ5VBu@`eGe_AW zuQ^fy*{T(A%t42uSJ>c%h08B7&lUjdvP@K%cZuQL8DloM(X0zMZ6W@XhP@kKv)c@= z`TZqcJwCP+e$xDIs0t}ngHUL{v5##AgqGJ)G{E|s_P6P2Q$%tz!yIh`3cuGP)Q)*0 zZU{9(lJ()D3`My|J^)Ht4-nt^XuzCbk#Y8QwTiKP2&*hi$JKBkxcZG6URAA+X{@sR z6p)x$@iAf0nS^WOj;65|Q#7ZYI-x(Ay}>xqTxy6U+mE9b#z+Zk;}|S7_dz9@QhsQ@ zNGg@yZ!1h??hb9aXDKt*d9_*0n}sO7tDoE7<$3jM6mZ1s`3EC|lAe^L9_=y^Vy$gX z@*V*bIIL)eJg|*9Hd$%SHD+fni$9bSMfG%%xx8O=V2n`5>MewRc`6>k8ng3}5!1zZ zF-5#r%IvWu`th-@K%cWZ@f7APjyz!odh?ehRvHR}9)u2)leMlvMMX9_i~LTXz7;1Y z69xz{Mmobn#B^H?)iUvBb}>c4ih|eUaU-HsW|$3In#g8}jY^ZRcY4;w^WEHtVKf{9 zYPn8QANb3@eSTe($)D}g>uzL?sklYF6qS8Sz$jfU8>&0&E0{AUA zQ&H%7H-5gk*>Cv%O=_p(wu#<3?3k=tzr)l&6zcjjYYnnEKv2LOR_$&5OG5?7VfA|gG7Ae{%vVU>WU^Q#d}*$5DTqw^w! z$c+S?hlwZB`UCgLhetrewxnSC`Y}nb*MO=~cFQmO&emKmCd3LS%iv$27=vh4V{&wH zU!@Jm4UIaCPsuJ(Gqonj!)r0DFH`hazbl}>Q>QX`$m} zKg>nnKXhDBSvR8UtbI8{`wywa(AFu13ysG($|0Phg#Yjt`~(Z8Xqah(mg=so3>vah z3aw$FgDO^P-lt*-Sad*MESvqoh*Z*3;OrYykda+bRNTN=S$4QNq>}|NzvJu0xx}b5 zG}mn7d2{b^&h3@b_s886_F#T3ML5!-twff0eZUD;-060Wok*~YA<`dlxi)9-jI;JP zoI>Aj18dVXiT(mx<1|)(5ZwGzi5`-}E3)C-v3QPPTmOX9I}UFdVd3cwbRuN>+(tcg z2|^~2xd?I{>_JzbszE>C&H%sQC3`5pT5&2Rr&Oh{7nmN!f`+El_JD%A}-l_1vEs!oJ9)|Ry)sV+qCzZG6`b@-wOBx_hHf^d^%9fdt?M|W+1HCdE!|MW3` z?7oL0Px%g9AllB8ojTD8=CEynGDaMazYle-xsY&?{Bg9ezqQ&G!;b&BLrQWF#@rnz zv#KRwKp8fco9joZ$EsQi7t1c5g$Ej9`@P)d>9|qhoxLRG2WxOE1hBUWtXa zxJrKPCW2vLx_uWQot2qpl(fxf*YR`Nk36kAqRxylQkP?HZ|H7Hd-CQ-)r|v@6IO2; zwOvAJ+Lmdx6`u0ty<7;?&8dE~+bY4A;!zspWlGSnS3EFujV z(q^b&7RZilWBL7Mg_d3^o9kj7V!pYAc|wZ6j@)A~Suuj5242P2VxnH}xALHuEzJZQ z1;SI~Yo{gmu{wta7tc=I*G31s%G!Yg@&uSVVrYKF8`m6(dOt%hmqrsAL^61 zeH%`jt8HcJZnyYAfO?)lYmVJ`SfiIyqmT>gxM;q;K5KG%ArC;UuhVCe>#JjN*>wN8 zCU=-vLvPG&CXl-;(yn3h{CoB)>3VHCcRV!2zh(f8b&KgwCUfMoKlJr95R0QCmFX-! zIX2j_0IPFqcVYqQ^%j0BHVQ{>>TuzMUEiUW(%0Y63o-hV?r{m^L+&J`HT+@8jG8JP zJNWwjY$9b36BnMp0hkoitW~Hco^T^w+QaEJoG^wlH2oOq;k~>;Jxh*L+GuU{P6(CI zB|H*kF!LOjMyED)My#t)k-JYoS>;q!uKrYy8*7e2`^^IZ+3dc`G=qFnp{W42R2Mp#Qd)}+KT;)2UPl;mX#+-!!-NJmwA{7m zEdVA;W$jmc5w49EpkR;#;|TpoPF}n3WJ)rdu6_e3Y^UhoXF7xbnZ@^hS4=@R{>(#%nHbr zE8rwAqFI{pm;Th4h7~!DB@BO);E@X{aXeX4>u{|e!o(FZw8T*_RUsiaWUUasEl`%@ zkqZ(Z`IVTK8_O$6^EGMdPbDoI_@|s)F4v-zl2_VF{8^oXol65e&GLNZInmZB?QbF{ ziH~}~fcaffA68VDCcT2SnTp<{UJapd;%FjQHjt_rp_N?D-Xbdy#Tvs%MN1u3eMnw% zmUN9>_Y#)8LzqLxEH`UjPD4#gPDYpXyG#-)h903@F)nf>*2CFv}u}vglQm=dwNxiasiN9J^Z_zL_%ov`+%jTB~B&!@k)qumn4y2q zJ?R?#P0eY@OiTuEZ+FTU(Z<%R$}O_WQ@iK|R@?c>2Xtx7)_2U+vK0-bTcAphH~9eA zi+?0P2SlXgG_9SIsnNVxQ%<&Hs`pyW?R{kmtLHCKpGzii#HugKu7Nxv)=w zS-tPKe|bCvQesr`YANZ#)!waUt#m*Px1zf4 z3MMkDsS=-C(T25$fBurm>R*W?C1(bvp-Wp!y|1`Bmg6W`OM~0GE)dHJ`&WUisnCZ; z9u|>k)=>_kIjUncf5=PfeJ+WX>@>Gow^V739R!K*oCO4UFuS(Jg)E`4B)<6JXLz~a z{D3{5-MA14>|DN>t=BLZ`LW<(y`i?qh`QDttZi42A4N++uT z&dkKthm7H{*Zpz|S!XpDf-8K*1Q~^!b6p!R2w$zXRj>;NkQ~SG^mcb zCRXLr(z@Kt#L5!R2^-P|+M)`f&>A`W;Wk3808Bg6V?gP;8WV^?AOfWpmv9eLZxx*q zB+#E|C&<+{@9%>W(Is^*0rX$F7uH$1trVz)RkH+2@Jy7M&QH2o%#ixBW@GX;a*~%N zaZfoTPJ8w=F)^z78<(+o2|JK}@N^T#{MC8gVLQjzXVnD z7ogqYj$e&*suq~d)HSijJI}QCG*^)l-lv*ElLVs-EsII~BC@J7*EQ@K& zo?_jKN*kL@NB!&1f~@^^z*rXUtrcR-UKUwYMUguc)*@=wX2{cjChiU!Uk^$*5HH10F89B-lSwrPxwh3Q!=aH9|wr}0N>C5 zbk<(L>M8PWPxnj>g<2;u!!@@JU3eIU-HkmDKEGE6bc>0DxA!C6uJ^#@?T*Y-3C=g58?oZigPrN!N@1I8(ZzpgfoxJ`9cYW;DN#7MCGp+ zIs+|!Wn~K%?DXR7rRBxSUuoOgIFPUWHuM=dD&%N|l86LDzM}}D8+c|ymwe#Kb}l0B zzoe|o)|BlV8S=pT+?gd<>-#+=H=niM2##ro4f`%vWAB+WnGG%Z5eNi?kR8?3`#&1l zt&B-&>C4%SY<@tjm}1uDW7MwrLMTU`Z207rrCcM{IQ$^_TMcb@b#*?0W4wWWR-5u7#7YSqNxTG(J5NKax26+o0xAH-Mn}@6}(|B=3 zu8`$R-2dXV_byuzaA@~=XH>6y)cK4cb6g7a|IIf^w{v$<%$0BA{^gd6O5}Dr-Qd+o zO^0YPTP84p_d^JO4lLE~9lZyoGnYYIYT|Rez0>g>QjZN@K7ZqgCJA~T0@oo5gG9ug&+bul+q`lm zrVYT3FyYiH-SO$(Pm#v9m=oexTP@0<%pA5Z?eeRXGH}Vz?Y}?<5dS{ z4XB?;>B^(fMa%-!i8YJ-?e}*SGO0CB0PCsdJAw;-KdRV157m1d$-NaCKJe)QS(1WF z@ry4ref9|C2zr|4FPbjI?KZTm2tw+!O-UhL%B3r)u58k#dgy;fE<0z=dq!?M-=fld zW+Z#R4wivH$_%Bh2N5JU-xW~JbsYFqsO4E#|ytaG;GWbmS zxSup_uH3&wx3HW(4=628(pX7{rsH(k>o@s$e+TYRiJ9s4IE53!qFf*Em>im6y7c2s z7wYk@w(Ze%5%z2Mg)#Agny!@x>w_KJRbh*;sN~A!pjFh61x1CF6XI0+V9dTJkZNl! zY%NDABSn29UErS!5iZ|nf$jGj6h?5N zzW z(-x<3wVJs>F}gjDF)z`wL{KG89(NeXM0}HpNW7NTM8kqI(#`Nsl9Ety`u?R_+V;4F zPG*B~e<*%Il|#6x6M#9XvPQLL6}{~!cW|*!_W}pNWjIAPk2-{>g9dm< zV}YUkZlEk)T2XTcT1~jXOuwU1D9D$A5vc&+>ShbO)bfShk6LJ6`UctICY_G4nU&iX zeDT;7s_zFi>$j_9(n422OdIL_q1E0BL?Wunq@v@$e{t{vC8CaPRSLk zjdy48hNE%B)ukwUF39;dt(uS-hmWV04ZR1_g^h(6U)tbp>$9(9s)tk6!^tYeYw}?) z{hxUaB7ST;-9R{GirY+|f6`2|k<~&jvfmfz1{`c}hllauVGO&_L{092wHBG2RWy~m zUEHzr2&r}6dqfb%%CoD3RtF4bLpsgAzy3LvDFz>=s-rlaV<-wHOF%E6%*HL?%>OM@ z1ht}E%7%zQK$i#?$cBjJgEJ>EwO~ST;yT}?jbhq*KK@#_>o$2WTs~_4jvavmMABW5 z=o6Q7HNE{A%3h$$>k67Adq#P`iwm%L4N}4IIGx<|2rzpt*ZJjPpC_{UjZv@jFK2;t zZ@_(g?zX`G@+I-@NU28&vEToWCjMTJ3P5*!!MHZY`}1DMIGIQNgst+}nYpj3OLG6N zIRzVC-`zVF7OoXZ?p{U&fvw(jez0*nQ>~wQ?kl$Hu{r&ON^Wwo)G*6&`(xP>u4hY_ zNqwqftjd_F%3p~yrd5j{h`-puF_n>2Y-Lx}moWxF8$qf^2`B$T&h9VkSEW&bRuT03 z!tN%g%jFZ=vA}i_Aq`B8SNN&T8*Nm+fJihT7^wsEVj!EkZQwf@Bf<2Sk*4&qk96aE zbDQbCJZ*!_suBEArczQl{!H##kjTj*bMjh0*~y#-GhyfAOuh^XZO22NOs#dZ@Pi^+Ij}3CbxU2{+5#~V2{PZf$wMl#F^D|9jUT> zQExHm-m)08YtTY;;NYWhWB!cCq3V`24U3zZJUSH7_~dj(B)^1m)YnGS#2%J}2mBci zh;2TEGJh(z?k5&Ni5x-85?6IbzNWDfl?YEtN)@$|=Mh`I-Y*eLNW+qImxc<(Woa7! zT_U4I8`6==QdNS!I8=^NJfcXgo{USiPNAHdDeC1!&(CWyQ_2%=pOT(@Af^Ju6IXJE z5|i4&82_LpH(2j7O++gk9cTJM&j_pViJ=W``tN&|%voIvPRK1AFvs0A@l;lrI6+47 zr%$xhL0jUBO?JX=ROjvPt3i|bBPl?=k&jKw$NW>Lzo{-uzWdbk9;6T;-pI3$yr|9p z!pVMpJ`1Ui;rcIst%rhltqpG1-0d_n&;Vo<{$Dbksejjh(;FD`?C+ z^+G+nEy|pECPMeQfn)i%f`hE*-Abx|17BW^beLid#4NZyjXHM20$)9O0^NVUc&zrN zKQk)Cu6`|Z#kPQxb~${qSc7(8pY6g0JUzj5_`M$h9oODr|C7|2aI-h(zb4dD(N+5# z@@RfXJW_(R?s`227%WW>DJag#G1Iy@*?;f4JdS%jdSN~bye4*?KiO&gur;69;j*zO zm>`e%SA(HjaC7$)nyhhW9;SZ#b-cseTx0DQB;`~8BuJJB9o*caYzgf9j}#iiqGMqp zd&u^0BD15YI7i!0h>kai0HyS!@`@D8|12MhNNAYx2Ii6`?4GMSiVD_Y)O6SqZe#_P zOdIFt$%k=m&upG!(mVm~A?__0fA>2HRbyZ~6L}YF?64QGh95u@05TP$-oW*MpGMGO z@g5E7(fd{;K({%V9M5q#j9Rak=Xy1v+^@x)c%6B*o3+%#>8}jwyZ?;HeEoS>MlFZK za^fORvXb|*4GN>rRK0DsIv9@bNGPqWzD>Kz0kr|)Xu$zsd6h$I#j>S+jx0F+|RW3g`xJd!8hNPdi8n2?eyIu*n|D6bU{)KEgHiLw-?w% zc6b_N3?)h-mehj>bMfv1WRw^x(OLa(-{F5xsrJ&+#2aagg7{z|sV?T`Ok!f256?*0 zJLr_^>a8dTWcc_h;^HWm$gszQUgAAiPGMA$bxac7K=`~v?O-#uLC$-$!NM52Db`?= zi%-n?N|H!S`DaLaiA{76x9eJdMV;1=0(_RL%Ll@Q$Y&FkQ)M}*AoKoG`6<2eqpO{a z<)W@Y%pY3738ob4C0RM7d;V zOZ2V~UH8{WQ$~$?A60>kTe(X1%Dm#JHiJy(6XpAkIu&5Xtg7ftmG-?&UVw{y)=UIv ziqr9?Et$xB4r7BMyG_1d;3MibPc~KU2%7+x^44@rDU@#j89&8$L~^{o0w+V`ME++$ zS%YR7K0mN5oUIr6Obg}vs^m@7+N;Mc{s&!fM#x z?|UwH_zN!6DTCz~Ob%gSmqo%6DJ|GkyDELW7W0_hpTdSUGk1K-OJ@8QahpEh1r~x6 zn(%YFynU(gC6kRj!0c1mG~Xhrxfo*d@7g{_jt?xPM~kq+hCL^D3@P7N9-@%%NJ)wakeyZZlKZ}VsOWb6>Wfs zWwZdXWiT3U#gsAn%vDCr8D33@Nlo9!EYm98p1O0*M+aAGGdwAqlxxmVoIHFB2#tg% z5*7O_&d6yo`isjeh3A=&@z^|c^z+QEy5`wbgnX^^ArMpsSdJ$6YtJ-uD4hNAv3yrl zv|ImGpq@1nbC6M7SbDj{RYcnTTH?cXUiI}aRrr}JhstX>vQtGH+d>V-hb6#1X^z1 zxqeE0pXfsZxZX~wl<~X7jE3s)335-F40=_pHg_$+&XB`{JN&LgjM{y>&esDY$DaT9 z=6#Is>2-a;vv9s%u)O2Vw}jEJ!vSyG_1R9UhaDHaPklDL?Jv5k2ijA#NSe#h-;dwj zb%OsE-pizNeze{Dz|kFvz}ENaRwZBI+^7C*wd+M^J6u7jcSa?wQdG4|T?(M)G%Mi6 zcPrWV6s3zo1I<&Y+Ln&bPOQ){MFB6R0ddjfxUY$nypGE=IJn{Ef3e_Nc7QQSgad-= zVH{X=6Ax&UJBTt5Nc9**88(xQM$9*Cqk|r#QuE{JXHuFkOv^A&FC!h}9K|V|Vf*}G zc2=3g_}R@cx388tzLthR^(rFLTC&kmBqD>d4={5ix2z1QBBm7zVLV8l3cC4;@^oWsdNCQ%NXhxAMjo0f+T?H`TY;+Xu;xFwbgQS`Y{xC= z5zzNkPRj;lF`VIIub8#NmF`aihb_oSW4)o1Jd*`M?_Z_ zMuOO;vwCF}ellSbTF2i$!S^3*_fd7QgiZypM_)xbJie^;9|fDYMd3~nmZ=PyNQm>y zkZeZJB5*8y9+m_W*yeNYHt6$ErLq~2L{>e0vwR+?p(qI-qqo-~)f)8ze%iK|Q*?ut zxe`qr6{6e8Giicb-xq`1XZd}#`M@PsP4B4Yjnj52qxYWKlB4TRsN4LVb?mlai z@WVyW5sL@pS{J$z$JM>EmF-F#d;`QD!_GJw3U3W8U_9JrLZ$dsg|~;z+y7sRFHLRm zem$UBI9~(bCp|VUp>-QFvEfQV#1VC)pkZ<;mBvdLK#xGhreL-`^!_iO>x$5NSzW*M z*R~fT=P3(D5n^XSsWG!gr)^j$4M0P~Y#3Z37IWxIP)EZPb^F?)nu!62sNuTz5Zp`+vVS2wjE=5A5HDLjrR^w#FW?HxBFKS7P_1|h301M? zBHE$!7lP2{vKmY!JHnr+(;r5PzJ5u=QTD8PM|8&mTj`VNW`5~Bz|k9xWdcDnmhn7e zdos;}p4dK8Sy6Q^6FGYLewxW8<4sg@;aqPYPQMecB~OUyQdzn=&b|rS^@3%SGe7Ld zPjO%aZ(JCPDX$~A3!Gp36!L$Y!2l~3gYB1H;xgf2wm)MN1;nkePKA~ zZ<=_e!#?Efj{1P?6`9?oYh$|ll*y2V2nWVI(J&CqcLS=WyQkA zUTpJiNIJ%jM$_08PW+iBqFuB59={$=-GMCg_ALvcXE%@&*7fouRIg+pizso+;wviH z?ci1;nNz)bx9L|Q(bQ`(Nhg)L%h=Hnz&SQ?SwavwHolT z#2_?LpFcdU-rotN_1R!0ETsN5f}x}}$p)D1vKD=+&6pf;o zr}Yjc=lLh53Vc6CMD-k94eZsLR1vdfynYiqtAn}r0Az&D|F!F5LY%)X%wv;*EBRT> zQErNj`)B5Px_=~-Rmk1%(011~8~UU{=Nfop0&C7+xe^;Zc=Sz1It)f~-?JYpQN=oU zDg^(Qc2Gn5`CpD?6RI-;?q`B;vV{d{vR0U?72^3X*K!|6K{8^rYx)6$X9%|5&U=U* z>w!Z-)VAI}Td?Z}Z6k;7%ica$u*5Vfdt38kD*(42I&d~6k#YH+He8F+7%rdezcb02 zm@deBOk{U?4|)187>265nQkY^2?4y5ROhlAYuzc~6rze1!wVElVMj7D{_$ARJmZa8 zJ)h{D7&as%K4V-yT%wY#bWHHB2TTkb>`zjA^kwPC2$x{#sqya>#*TXQ*-V_Y3km9( z$}q{{5?~2LaM&ZGH5q2nxvI0Tol&V~Bj0d`xhj)DSsbk@i+vcyijN{d2{XTJzqNkZ zW1e=ek?ZN>IXy|Ew2ux+?{I1JqGO~)~ zu(C2H=sj$3W?(`)V>y{KmgyrR$nSyR1%>r^Z(r^ujbI!M4E=m zeH#vVy;&mWdKSH(FflqFgGcUjosW)~!J`JlLkbOzj|aH4EUV@{Yr!{VTP#`k>($Q&p19b(2DK|znj|{f{iT%pq6AQ9j3F7`8Wx~6of1zlgu|6j z16xl4LqQ|r)hga5IRgTFSg5PhY1w{h#74;r3EEpYKTu}bXi;xGE=Z+I+$2D{UY4`V{ zDjOPhZhN&@*WIQ4%3!?GVGj%if4s^l|26N^tuXB9$!dy%1|SobraDspBO2-N)ARP& zM30+T-`~dvT-|jk^hZs;Y4sS8?GpAfh$8|WZ`0a6^V&ZIA}qu zq9)H9XWQrA!cc-UOtWHpv#ykhm^zcIEK zXLeG^0#|~D_0M}+QyIFWDwtK#gSlEWhmQ~wVJ-_ZOtO6ay9?BTlicl4M+K?}wTutx z=)wDfUL00y$Q4AXaupUIMwe;WxWi|*r84IYb>XQHfWdsi3|Sx_E69(MwM5AM4N5UJ zXiHx%{rMaE-1PdooTOyP-8dI3Yh2C#c$LYkKnkwgj+(KMKPpoE(x0FoWn_{KrIbZJ z@Yc97lDPAq)h5F_e+Fs0B5pDfg;F;Bo}4y;W?DIav{QPlHfWJ%AeMHPFn+50SwaUy zm@$GD?|sl681>Wb_)YkTW{kGL@>5ua(B>ty(A?z;CpM=Atd#G+{|Fp6Y8$S# zuJO9N;a>N@XKcu6w^%%4)^ECxH}H+Uxb8b%ao)e$-l}8LX^bvyIA=5N6kXYzY7G7f zpJS=?JD|8s9hm8(0xARXo(E=7=`%C|C~1b&x)!vOeue!gPp*vUI3V$Q5-27VN-B^U zXRpeS3=>NyIb4j}9a(UFdJ^_HSsZz%W1L~wSRiHK^SOgHA_a`3w1q9Y-oTdDpP7!` z*_SQ0M#ynmVN#@fRVknYlCHJ4FIfTj!{*6EbP-<`mt0EO(`%5WS`WVUu$bXI&*E5Afm&^sCGHHm=hE!jS&sXI-ENhkC?;sGmA+)p z#++uo;dChT#xJKIbV0|HoSIJUx6m$l4~+E6nfYzyo!vx|J&>r#A2-dSA2qg<>9N|F zsXu!APv4<;*BMZtKJUJ7>4xrUhT51)w;ttlp(g6HH_N}~e~k*%Jn7DvjDchf`8{vH z@7z4>8LMUHspIG-$$*4y!S7f<3S zYxgV)+QJBSJfY}0aTz`Rdt3o#k*UBL4PSE{XvoUr;y(#1f`kq=toXRWI>Wg~KW_f$ z+yml%Y3|NKgBwFbLlcd(yMqTN7XO-XPV}WW;zQZ1)qy6Lcjg(ZO5=eD*Q|tU&(lp? zXQA_&(@unW@@A>;kDpZ`{)gNyFazf=vd>`ef04wJ>FCtOg+XMuz$V7`R7c6=w~MFt z&Kt}?-}|3|e$Zc?`mb5==b>xR;py`|Ar)Ip3DM}1KW)?X7NMEd=-%dWhs)8G0SmyZ zw@=S=vEG&y@czUb@N$ZQSH7&6yVP~{tWjaqGH|Zt=)_7FmYY&xb@@|Dzr{5*;PuJO z9UMXOta>PTA#Sa_Pg$fCzxUg?DNGVoO*JJ(@z^>GzU#wn4wWCpRoB+Jv~75 z_5jOdnn9<(DmYQXwB&fb7qlFwQ|(3gPWL^1;>N=gy@5<X!`4`;pAJ9`3P`_7P?ePl z?btK)^76L%pwV@q2ezBpJlq!}c2t!%4Dfm?PIrVoSShbu8IWMoZ;n;n2G=+Z>9P!R zuMi0(R7$u!`p+uPhk$EFvpa)UPz-sMHy-oYUwE8h;-1kLQaV(O`jg2d(!a}_NApKa z#lrXVVOgXP()kJ%l(8%R4Rr>2Qm)6Q_jwk8uTC%M{dir_0kJxREt@soI)GofJJ%)E zWLb1)-QZ$H%_cK%AaB-l{uV17|x z-pH_3-F&gP3@9e$3fXDJ3Lu=rs@-h(OQ&{Sn$BhgXH_ABIZ$koe}7E4sNZs*C6!qZ znVWV%~2v|}(?#_U>dr+~QhTe>aKJe{a z0$Exz?fKir@p-^@&`a1bq7rr8wK2L;^MGgI3xJ?*i!sYWDJ?Q=lcl7{ zsz=>ny?Kb2_5Awv*cWyt?B#XU_3d)CXs8QtcLVjK$oX79;j!kdV_Nv+KGCB_obbil z%SiFRTq3oo7+H*+jogq5BreCb@4W?UovgaYJGQ^&4XA|zC9dX$JG>jh$I?Y_Hv!?WI zI0reN3t*Ye@HM}Gl({?E|9AF!f;BK~?_zq(VT#F3fJ@L@e@pzY#hr5>eTbWcuXAF1 z|3b-xcg-MhD7j(1+HRSh*kuLw4E68FlNt#EZXQ^4ELRlSeR^ss2=p@bxkebH~SDd}OYkT1j_p;`4*` zgyUQk4nU-J49|agJSP!y&)gZd{27HfS!GEeSbvU3{rnRmW~TGk8z3W@9QeHL7;V&q z@98_oZp{Zn9el{{#=+~TzkQ5<|Awt-bitaN^nWcVj_WIXb0fYh&7QfTB~jtW(}VTf z3r%lNwAC$93t4k<)gp;r7h78GPe&v%x7%JX2c(tjuft2(NQC?WcyR#_!7`PB+h-MU zD|qe?+b_u{i&dGZT9wF(&(@?KNgVDitMG_Vww*5@CNYN9HS}#>!}eA&6y`=P=V22| z^U!GgqVd{qxUbU3V;k0TMe;4t$@uy;E6lp_2Sa`pK=;?yMo7<1V4It|a7c~Yg z2jM+N)gQkj7H_a`>--nA8YRTphXdvadXF3oh8PDIz}i3tbun%s4)I{??_O!5wRK>{ z4!hNiiH?_q4!<}4UwwVBhAls8WB#SWDzL(om|OqTkWRYYwQ{hwzFCcdB* zLV?{Pt1;uND8Xv)TaPug%zkfMrc4^;jhn|(lF$FngyODDx1xQGlcRKtgYqw@}RPhEB3G!MVz8JRY2DxDBvJr zR{N;fr{mO;9RmM|O-Ll^r=Ns}EZ3!;EUbY(Cph=_!g!?%20qHw{d|gYZ!CkEjdUP; zgXC^PyKA!Pn9u78Pi7p-AAI^!Uj`rqt!h`f2;c8MqUF~7gxa5WyX%Pk?q?kR+)w%C zgo}*n2&6?1jeTO%MsJU`yh^)nSOWc@H-r@dZJhttCOgImQapFr9yiDUvr?3<^Tn>b zHV{=PKXgA+zvhy4Us!j>8yAE#!GmF!{skGSv2ECCV|} z_JmdtF4D5v05t7sOcq|oN52o+)Ij4u}0^Fyx?Dx zWf;7Qf89Tm_5M}g6ToGJZvL5x=$=#fb(}B5s_MkQNTjF%Eaw2p7MPj60gRXAjh}vX z-f#w4|K_o74AUZJKGDC=F*ukn;OzPXQ+=i&`jv@8#ML}UGs7aI$t6Vuo!O6f=aVG{GzV$ z&sT{poy z*n)xEIXvlIpiB(Dz*}_M3BzPFh}rty35YnW#V;mGtI~D%h`GWbaPU@;m8->npZ@+l zO4w`omiXTL>4f-fu!>B?YosS^U4GGP;I`<>;3N!Mo0zkZ?mkcO70%^vuZD5>c?^FA z>Mw(1@0V3pMeSBh1wZPVQ_LmK=iH&gQJwbeHheM;n==StJ$-G0d8fZ%VK$baCqhEY zThN!;iV4$>STNZDS~!-ICP$nNgwg{gHpA{wKRu%)tY!?k57ZOeh&t@Bie!Ee;T_Qk z2!;F$|AvK?FQ=q1o8ha``B?)|PaIA9GZxJe7gad1r(=!NnNWpF*6`d9CZ9sBt--Ug zNkU?;ryf?tWS0iFZ9|?jk$z2QFS6E`lni840-iuLC=oBz-HUH;?daa(W2>kC_UOZ4P8S`xaRvdyXf=;N4nlyt(R zFO4vbL*YWNyBm2!R>+a%&t=|k)2%<0$54?OY`?azI!WJ<4fXx->+i>ztUCTsVbC<# z`GhE*pa1a_a{qUph&s_(^Si|1v3#^VEm3>xHG9JPyu8xcV8inQ4NIT4N*<9(EvsII z%A}Hr2~hP7C;YUnC|rvtDVT>ohPZ<3i1atX3+0ql;iUbBQ;uZ)ry9P*GzOI7=!X{+ zAMTifksma6e^k9tvu+Xj+vk+Myyz&p#FqFEK;3i4ueD?Ys#8-L5C`VST6f~x@mlU& z|H~%CnfwG(`v-+m9wRj!jq&>IOzZDNRA20+h=Z&dD_Osv&gl|sZg1Kr+~PIglMOb< zv^XR5ZMY2>qlI?^*b+7alyj`KE?37|aB$rzd79F~3x%rm#kVsvuSJPOt-+@Npk<%P>cF_+N?VHr{%7x ztd$s7Ls(XR1e6a{kze-wBVnPkcIj$e=yi2g< zV;osZQ|I#8Hdfz!XL^+YXq$Fw=WV%;7+SSGY9`I{Pg-Y;Er9VmGOZWCaH{*WvWs}u z&$_MNvFM5YGUluT*VMnR17zZ6Gwh9DL0NpeZ&5XSYE>TDOEsTRP;kN_o62NqAQFZF zWqub5F&N2E1Z-SfaNnK=n1rA8d_H3vAL}SiaFE`DB8!-}vc|Fxkqni@F$8DoUj_8} zefc_!SY!LaRZ)J_2($+fy`_}^>ZpLrS{zIevF06zmTIH;4_P;)JjT^+&)uQ_z zvf1_ZR25%3{i0;s;Wiy23t=wppqtYjZSrT|`_#!>!2xY?131f1$n0nst=xDd<8Y$AJk{@Wy zkBa&7w>GW&zG?MW+}FQ4)yJ%sK=&W&?G|M!hK8wavFe&dM`73>;Au@z@GrIm(V6vyk^6KQvWEBn8KNx|+*9)vA>^v(sM@LWm)$5LXI z8oj8Cf}hx4dg65yybN)haKUd{f0|EW2rXZl zpE*c)l{I8nN$faTj!m5ls_Y?m%*0lSA_W?U?0DKftIg}uE)(pCr0aVZf^X>2g)nr(P>Pl~k?YkOxMW|C3;?ur~#Tc+2O=>W){`?EK2M)3^AjsK`{3WuV>O;&Lq%&7%7xmxFSC zU&8c~EMeb_U#=;f6rgC-H-seGyUuuk;v2p@9}42+4PJ)%^9ZhTjvfBwjwt^yf>N?#K0s7HrOo z35o!JHX0eO92n$-Y-f^tKMWuMH8jus1zNv(tJ3@VGsPs@%tjfug-s1IQ#4{m7!SK^ zKNnhYK>Hf3yV0zEn*7}N;TvJ-2y%{J%|ypAE5M**hxf=7E7>EOptiN!(D9wke)pEY zTxylh;;5iznET)1S}C~^slXpJ#_E;=?tkUlObkU@aI7?ES^GZPajT#RH-a+ z;xmAfmI3sH`QvIXQFUZPLBAtj`g#Vf%5NnlL6i0VR;s@Y=+D)eN5+#hG}Y8p#oW{w z0*RtmS?YktziSQn*qUq{SyI*|8d{bjQ%-U4H0C!7n<$eL1T6 z^=*hz8BeoH>OaGQk)0kI_-SVxb~s0S>)BZOEP}p(ku&R(neCRxO!nvxf(IM;b|d5s zsP$AsZjEvd8Q1?0IHngD4^VU{m zee4F8%p{;+Yh0!8N&hrL{J^w02E4|NO3-IF+C?z|(&(9R+)w{vL6H_hjsrZ+I(GF%SEdA!b*34eYFK<|XDm`>N--6Um*fORlQ$B&xeiDdqgjMe<8N!-j^Tk5HLOZI$$f zbyV*JUWjs1($A7yRnb!LK1U{jh+Q$_^hwz#G%#XNqZ&6f-EG#I5vJs*t<)G|X{0I~ zsKIKO-6exMy|FtJI!|Uaxpa-X*nvdW4rM5FNhENx8h$wlLo@q)0gUtZVCP;hf!l+D zaV6iy^r;kl>(i!ce_}+{C>qru`CCFM3nF`1J5^|z^@r&Eq`A)&tg5rQBd-tBJs53W zH23N_wL8v_NL!yfGf!;Zv?$xRsQl>TU-DzZPPB4@e@LMrTwx^n4XZj0dnBxXuR-xs zZ=cWqx0_SC=T$@}2otH%nctwzzP$UO$xR%^n%i(^!%w>y#yP2EEKBz$)@4co45U7qz;nxCVa;Y z+m!TKTtfp!dpm@wj_Z^``zX2{J`8cX2#h4`qh90sY$+W}0zt6-))Dv}R#SN56up4Y z&9K(iXt*cr-urR~tpNLq&sL>?DxVbm($y%Ltn1phnKV)VlO_nvU83^@VRf#=rb$- zQOhf_@31r8(BXRU1n1y?tz}uZ*aLnY;P>99FgTK_IsHfNu;SbG)>G7%88Ccjwy)i^ z4bKf)<+q;zQ}9I%=fq?Ie6z$PGCqEE#l|5EU8Oc`S3lErqtq}#)}HeMa4X2DI#(2b zQ2j)63q=$CN^aDXh(L(yA{vK6p`vjl2SvAV*G z_t`is#n!M%cBg5+J1LJ@SgrOYC-yuuTe6|G#>H+nABLA ziwVeXcBFx+?wr~vmD0Gnx}C|0)AN1W*tMGM#)BLvw7aYcsNRZfeR_C6mNd^!P0baR z%8rVh+zE@btHj^$`m$dE6r-Vv(|sEBzq`5Wo*7WMdXOgzii^~@;Iw_doGFPlp|L+a zrHoWMi!mIROP4b)<5$$gJrTd7w@lh!1exJhR;+G+S4PN;W{20CzSK-a@6|NJaVN@{ z`Gr}N%Hg%;W+S6)=BgihH)spB&$R;Nu@ljj zH?!jJ8Defo&Z5h6YJxswue~+{EME&;DZLGdtuvYx?IqB8%5RNulb&bKRuE`yLZ@L+%i1 zv40E3I|@PFREKRVq2uWB_-r13*^@3PX-8G|qGdIwWQvALYCP=H2E zl^&`ZT3olA>4v4L0{2{wj{LtSR98JAnYlK9{Pf9qzKqcCvTvV?y5BbW+(_g(YCdWK zh?7ZV1rZ?kUz8W6zj%2W(Zs<^9d3$vx=gqwGqTB!5t2-|p^2PT*r(4GMgX_#;!t6b z!_5i%IByI(^Ej-^>AQsfnCL640xl-#_Vzq{jb$=oLJ?N}0$KP{G%7PL)t0I;Y={v2 zO*qzHebm@7XghZ*ovNcutF!K3IqauotuB=>^pn?E?%;q0)D1uQ;^8LMF8XK&g3z6* zJBop;JJk<&zwM=lhWtIBN;hzAM7(bj%)5k<8Js#wE}y*XVdp0& zKl`YAZXeF+kzl4dun%CFE90i&{fRmb;jc>Qu7LA?o?#{7cTTAz#<-HWCOA!h~kDV|YJ~NP!Yzn(-ip%cs z(s{_QGtBx(PH%<|D=D1W8}!XNN5e}#cv0po(J-e?6$b+FekAPejm%HE0;?Z}ag@-M z#KoXeQm}_6OpBkbcZ@{#DKrTLFx>yF_G&vPS;+C5sGeKqb2;RpJr~(L$PSCn>4?V< zd`*@}b%gdSnvn&(a*ptx>>Qs5?*DsaB*EXmnf82_R((}G8kpFF>VwPp7>|#0aOJ$` ztm`7UX#qCSG~)lV>X}*%UQg|pD>SS0>3WcC>|3#mwXqm zPdTid{o$=4S3;JMlhI4^;lulloTQjKk_COkSays-00 zs&qoiyMF7MRaaqmN%>3R{s@oJ#jnoV9Vxd>b%}4(qC2Da3N^*CH3%Ql( z#v{2?x6|_ z^mfEk^DtPmmY6erpZm-UT195qZyZZm#?&KF_c>A=*Wzf`!qRx#sooJF+6>kIlLkxLZ|zq82LG$|Lnjp& zhx3frgmJ`4Zty#$856q2YdxiSc#_#PLG9Z3^c#iy8&DMmT(0XcM;x?g^met*WdSiJ z+CZQEQDD3TQDUs((UtAGiX6|MRfGz&_|MZd$%txoH`66~XefoS8ZdEjYhM(Ev5_z= zm+!Jivs&W&Ml?A+yIevsNXKv#*d}HKUXXzpDscdlBl3d;*9-g${`Zg^SP0&`*0_ql z<{b?9Ncartz<;pP_z5QC=-#-=5LZBz9|h$v`Bg)wI!+l%3+=NjLh*B@57RqR7T{z; zt0==q7-3IfF%|G)v^+Um2$z9q!Mlhu}t z*IZKqki{J#MkEOPketnKagdak&h5 zLqbx{GJPL%&1$-ic8=n4c|Pu_x}4O}Jbj9M#>k!GvVmnaeCa&&OPsr1lCk z?P>AivYzd)b>m$Q)7Ww+we8mlD<<>#mAS_J8tryVM%DtoekL;9-Z1g$qVS*1$BB}Jl40s;v^aL-Xok<&hB5Of*xpFDJ4-cYE!-2Y&) zv{FAzis4iMbM7q>RJ*)9IoFw!>${u52in+`czgGUHqU+H0D zv!B?shzgHRam6a8kB5va@r2QNjO{e92P<+ll%F$7xzQF@$_xJDq|7fdy+1?*o2>l zsUkeyhKR7R;)Q+)3hC9h_u||J4O}Lr;O_`ZiTW*4S-7-aCJy41KN0@Yyg<#(^aVi< zVRSQ}VQj*o->6Yv;|arn^{QOddM=+x&TjxSxg~bBfT2y;D!b{ErmBfezYQBHn;QX*DxXamIKx|F46Wqr zNHNT%t|%fq!dyxo8nex9Fnu26mPl4fz%Bp7EuNqeWRsmCBR)5~AJc5HV{NQUl_%S6yAbXp93{@2@qsf#KDJ%;F zLz?CWCiFyiCugBICbd|UNC-W2G7T~;2ga-C0grJA<~%LrRT;vI{cHpgH0lgXPBF&1 zP@2i>f$>}!bMaWHBKd{oJkH-Gn=;Gi0VWWfau=r7Ue$|~WA!8TlBSEn&uC!H#kil= z=H^ry$=O~W+dR)R!~g6eDJE~o$6CQ@%I3)nmj{_0?4GX_FEcId1B)E?YwwC<#%CFo zd@kFBiTIUUm5bg>Pl5=2LN8}pPjT79L2yNnK3z1*I*I(X#+b{VWL-NS`<8e1TvCsBgrm7q~zz`EQt7p~r^8iqW`2Kp6=RJL@#l<{?g%~Yx1r?o~2{Ut%D zxx{QcpUa}zWr*XgdH=K4>LZC!d+@FdtIORPXN8F0NV7jJA9L(J5r69b`dbX{@_o%? zC-U0sor<#}>-E;L5mYt(oQa;hJ)0Q_DmKCE=|g^jpLx&tuK{^1O0YG+B^xR3oWo+w z16F`%^GGNno&^|=8&yW2V7#nKb)P{of~k#?>6{XSM=a*^j(~HQsbpFi(O8X`fH@Zn zWZ~wbiK?h8X!76ZLFAvw3rH(Y`A`x)=Vo3m1@cBAd6n!cj{VZEO+piGDi7T( z%OR1Ac}b-lH9J6W=IZgY!n$!;+X4fIH_^~o;t8!Vl#mGoCz@wB0e6zk5 zeEzQdJlB)hMkbI0^4!>}C(SU`xGpA=G=O*}7(f^g*J^ZaGj1<#p!mo4cp#YO!z9=b z$cD>?81@T!vYTs?9(XQ-%T!Ba2FNZxN>Nr|P&6&1b3(9Iapbm><}PQnlDVC?Pj^rz zl|lPMfBx_H)|R-Re=B^oG+MKv&BvEg+ z;^dCBo)+i(SZh!}Rck&xn4Oee(&I~;1e`*Hq47cVsdl0d8}ApL7Fq__>5Sk8!a677 zUAX=$phH#to1zPif@iMr%wZ;zfor(N>9gzn@BZD}mVb|Pa$m8lFKfbV#He+>36Z}^ zxWNV&M)Sj`{8o+7ezMs5izi$iT1KJD{{Y6OcH}lVe)* z`~~u@_`Xnkbb+>aA~5ifojL@`91iD?@_O450ko;IwM|s63vHyH=RhTaz#uB_&Y~Ok z!b+pny|EcvAuqSgLtD?y^*@-lEmLXo(xxm#K_$j%JReup*>EHbXL7+4_L8ZblBfk> zMuKpDSGL6}+$=P@d=|FUqqprw?_+`B%#6N*xc>EBEWQVM3nqwqQnYg4O7ieL6G|5i zTb+)(?o7t20}VGdOu+}y{rz8J48q*wv)^(4hO12zOZ_IwJ~(lJg%c;>H^D+e&!I7} z+Ha-Ke(V3J2xI*af@>U0x6>G>Q~E>ek^cg9L;^qOz35PalRYe)!yR$kw)Ugs%fUjW z=5Ze}K7IjO!MEeLSJuF(yUV~L|LaBklkeLjhd-!jZb?TwgCy7vn7m3pps=7u;Z0aP z-3%>pndU69;gj22b1lLnqT4qr*s3P6GyqEV+EDo46y5EIwUGMkiIMwO-d3wxKO~a&NOcXrBifG^l(|_Qih@8#V z=h2(KLTcqhexl=_zVBeY*LH42-RSjs)8ZC>Z^31XEWdmmk3h+Mxt+?>{%d(*khJ$a zeipsHUQ1Y8m`XfQO-$Ag(GahJ&-kqozEBy|Ddmk6o{x@|2l*ol_)^@L##N`Xrr--!(w{BcPA4uoZx#~fuOGz)qbX`#K5c4HA|G*R1~{7cwo(gW zhusx5pnyFQ!1wUrT%YSVEm<`{iAae1GVe5y;cm3s z&Yq+&wGtgrQahU_3E;Mq;HJ*F{bz3jYZJQdPwg1D^J4II#w%yvX*|F`c z*tTsa9j%VDV%xUSosMlM9ox2TJKa0)`+fhv_emYBqZ*^usCw>u&UwwgpHqtp3EN6E zEj?nZ+{TRse=d}-zkiS6fr3>)AIOv>I;(s*-9(MnxUue@tUtr46 zV!^G#SNRHxVYDJFXC!4#TtTj{w%brxMrX39mRg_0rGFHMjo}_{F^n|d+73SGCa<;u z87}#oG0+%}hv=;r!dl{Gy@3^5CFQ@kd&z!%MT6rQw5!q4&;q7@4E%84wfQP15IPA} zt0T@UcXwuDSY|Z23Oa>2<>{k<@=1g@A1JDuLGR`A6te#V=Odm38cH{fX70z=mlJW4 z4r-`?r#l-B+QI%B^UjQC@_P#SHY9_2&Frl#R=%OhJFbG|Q29nqIhZ)=B=&HmW}mw? zIB)y)?W_M-ZbH?yzzUHX9&eHu_eI3!Y3H~{y;<%P&tlXf|7{u(88>LovRA(fkL+sG zFc1;~HO2+L=IsMWt10#3jA3Y@jR(BDvHRWG!i3_0=2E5JTa8xa&On$P-x;tR)8cyc z$XT%1vBv%tdB7bd9X+Ebh3(Sf#Ws0B#m!k(T0m^Y_2csUr}jK-eRZecDE!wD@Kp^s z=JGV;3#Enhs-9VX`s)iB8zH92qIvcJsgTO{IBwOK!ikpO>4ytle42R4b4+jf!-S5g zB760ZGXX;yfCfOPN?*cLHb7p;hM0f}@PbiX@oDe^Z<2c27kwK?n`lvujWyaoT{vi`368H(vtL__29T;P0TNUNPr_zA z%~kMf2S>^?^m4Oc)%+wB2)?^T8X25Vl=HC0^Tg_cSETFd$Br!FO`7>a#@KI=A$UQI zp5hS-dxm|swS5$`JGNJ6>N;z)0dMKsT`wl9x{)`cnD-uv4G+>?c4iXy&5z90XUlR{ zoq-LOo79$*x}iZ3^U7eX;lC)TcSs23YO=Os2nE#^ zbl^T=7n~p0h){@x24{AEXL7kSA^#rQwL=yK#+wYB&^hH?9^f3QZ?hyk5-invoSMcF z^7qy5Qs_3@0@4>d`u480ARV^|wbVZOD?N?2MszsT^I7}NDa zsYY}Xv!w)Tpwqrhf_YucIj5p&P%@$!K0`KBi}@|uwIGgkEdkXE>4~@0T$)fbcAS^^26iOP=?>r zs&Qjcd?~N7@PC}Oi|ajNWe;Ac#No<6xP(+K>hs+Sg5+;p5H&v8ZxCdPVi^LtrZ5FA z=y>|)S8MOl*pHdXxoZNFOQuw|8*swojSIv}0voRv(#2_}oF5;M?H3oEg(zbgyiwjL?yjo9Q-r2@c2QQ}dSughr>&&1?)@yxy;nsxZ(4 zfY06iNOr`%vt~4<7YmtrU2l#DC-A)CreB!t@sP;mOkQsko8_94?H$nq%XsyLW`_Ip zYT#BqRZKQV8eT&&q9YKlHGRI?kQ4D>4X4In`ierjjDVMzS--M}Bdv`6$ob#}9^{s_ z(sB)Uxvq(hl{(ROpZs{O4nWrHpy~xlL^cSV1#=!J+jMM3=!sGFb2=z+% zXyO%d!|yJ^fgr2#{Zm_Y*ICQn>};-T!l)tpdd{iw@pwK8kH><6*SADv#^M`BgO}56 z?sz5^f7{aybP4n3@k#0*!|AA5L;+TTnyyMVRhPdmt zo|c`_^zUV5-F7#M;KP<9kUAc_D+&emRN!P}Xf zG`Jbmlo2&>I-%V|$RvXGBZ}SHLAV;acyKZ!I^3p4QDeeLeM`nAw4O2P(V`!&f^h7i z$j0OK;0p%tcjMppF#Lb{wd>knhZAm(hX~Zo@>hr znnGKFjB^;A!k`n(UhX`JuNQ##yB)6?gXtf#VBIS*Es4WgQrc+AE5@|&)Tq>2g_PZI zsxi^fw$VY(I(te$UkNV#0%zST=BV+s0n@-aQ*D^>P2NhRDGNIflx#D^6-@mv>$B;S zWSIs0xyAcoZ{`GcK=mEUULsR0_>shf=xQVO;VEF4e{UXQe(?>=2l}oX-L!z#$8^ms zf~jwwX>4Jclx5M3HM@ycMy}{TD~FI>|FF}7`lrs9H=3jBtyrpRr2La+4=MK^3bCK~ zY9Z1;MK*F}&wDu5po$SS=4W^@@W{vP&Z`BH${oxvLPn8@_~RC{-S&ZTJ;Vt;Gph5R zj-OZzztwnbqbRv~gB?}XN~ZEHJ_c@mTyMZERqy`(MNetDj+rO!S<@tVvEC-LKyTJN)or#NJ!edJOIs<1t%w4T;c^juyNzj+XQDiSCqf=h*9ci%y*- z;yq5y_m7me3FGcK{rG$kBfEOX_BO8}M=b8}&Jk-C8e2R zl{htq_ChAO8L-y6h6mmZINt>l*vzJ8G1(CCiq8<0+@$o1Hxym{i3fGyT5?@jG-2Qx zFxuwJbC@rwE9MYbN;~E0)j4b>*>#KVtvYaebffh#m4a4|*=9 zeY6vvYTySb{R!(aLM?;8xgyCqEtbuuFfFnKan0UDT*@GCHK^G8J8I|C#}k7jJqVOuesGRcX~l5cO` zp!aOanzQKouvfBZ;0#SxExKT(uKk)39Hu33(xOXB%?)K%^T%A8$k6gf)B;OISfu=- zD|&GCWxkBHHp0;X>d^k~>KX=7lCCGWn&@FjYYLnsCU2>*Pod+SScz^NEdYIC9(>&;_80KCi*V<#qRE$g=A+Si!o+Qml~C zKNZsU5c|GI6&Q>j35MUYL9;4q94tYG^Eh2WT=KaWO$T^Q8MFs33P)@~!Z@GpVI4&j zY<9Z~%X8bBg&jPzwObh*_Kz|w>vV!B&YLgyUdkAd2zU*zRDaU`rQ86u<@|Zoz+4yb zA)JNyG#ygX?b)QM;dMG9|0>(-`4QiD5tr)YZiUO6BimqkbN9;5r1i9?q~`sm;aUiE z1&B+>@9xa*8+7``Cyfy+WOk&4D;qnv|CH$1_K%J-JB*{KT=h%Hl;^(V>pnERU%XHY zn_N{o9tu5pAQ*0}w4UN=IK{}6^3uY}^js_~awq3(qp*@qEu?axq^i~!1G37pUdqJS zD~oA(?-dFRNMd8q#A&DSc#MMTg*qdkK&^Wea*?UW_~=?vI_6ZjWlfY8&on|6sJFab zqa)Sd6?DK$AlT^?PU)>(2$?`!Rg&URdE#{~1d0li5RFK%_Nak zo3wrW$Yw`pO`X^o0PRAWq>FQ}OFz%ti=9WGBtC)WSJIEO}Pt(hkCX^IjNPi^%~o_Aez` z`$}hGGGd&GAj8Ora~X+F4VBx=K|VA>eNo34#v)V1I9vG$Fcy|d8TOXa5inhP#3VUp z8TyvAZ3GKLaB%ccsG$@zOl>i%l3pk%;JzEs3}v!J)0W=_9ZM&8&FMo>VHr30CVBrv zV(?{9<7fP31YJ8Osy9cKgsbP<3J5CX>m#4Mq`xA*bM{r5drtJRZY(ta#41pfP{#1A zy5WuFr$**I?E39I2B-ns**|`R3s8`JdBytH)dyCcR7Oh0FjwA zrZ;8eFQ)kU;3NPnDt{yam~l5?Eyz+S9OgsKcz2*cgr@j&U< z{u~2dl$x{E8eKeg6?4fOkbf=o-S)cMr^ytM4qa`BG1umN!8lH%aJ+TPjznK$y4E9= zm%}IR_X8K$Y`cH(rg&l08q%Qe#!{gg_r53_C4uLV*^tt(?$!W&m5Zxf9~nhnr`oor zS4Y%k^#o6bi90yWJZHpb%~Z;?YioR_Tt5Qr5A~WU5G@QWf8o^G|K$8IBXw}tu$W4) zwc2^oZN8)I%q|P7(X!<703$_Ssm}ZKFi)J5b0^05 z?)aCJXRBe;s{nyl?h#_Bqo;BF9RzU~C`eHghe?3Y&1NXB$ou9+I+S!pLQc?9GhNAK z(j+yIn&1Mj5~svAn8%S|kWSx03HV!6NWNRKnUPg@?E34cbz09Q`8?!3FncG=I>1k& zY{;>dJ^OKLclhk!F`kQ&gB-#9qyas~(BHKh0)ysUCQy)#! zlBDXWT`VZ-v||jMr^E#{H$K z_~KqVoVKh@P;4@O5zlD@wsaAg!3G1z0vm--6hQWygzwcbUn>|;Mv|8DH)GC%0KA+5 z$fA|XU4(7pLt@J+SU338!=%zg<@q|+FPj}UPHQq3rXZ1O zV}_QRS-`-_Ub`$Gw*ogi}?jF5b1%3JChSm2kXB*SPly0f~zaz{~BS&2u@ zBXK@;z0M-XrRa|S4}W^UvuDm~g2ws66bL+JEa4-0|K8jCw=mA zXl@&pcF+EUQ(j~eKTb~nc;{6C{`wfG-I2d8rDN1$L*8yWHA9RT=zb)sC!II`x`7Ei zX`=np0bgX0zW*m>UtlcZK6&2=ZhY5OmD!%A$t<5L?KpJNAa-=uPfp+H*!?h*H_-vX z=Jn_a(O%#q5Hj5!baTP!M%*EzrV2gIeYy9V?M^s4v2^up6P{?K1LwmgyzYY%Q z@_dGtPS(^^R?rpx*1@4prec`46sfrzY8z8-61fo_`iqw_mfke6QlA!OC8*X1TN<;L zg)&@Hbd@pD#)$D5_=^!|#Jwr!ddl>B0^{JXOp=Vjj{qcWs6uvTo^;+jgX8F6Zt2XF z3TUz-Qws(7b1~DfGanAA;L?gxbRY-=MfK;@9J(G2MK-Of_bkh#ZRq5kFRqko@s)jY zoolX)M?5;?T4!X7vi?veea7FrE1^HW?=gSA_R;@~9=|r)o;7(pxfM*i-Vir+MaB}B zo@a4JHzXKR-KffARE4D@f<@C@!;#iwM!FSbrG6et*uWxD&1_ClYBlBGiAkM?;FUL} zdAKFIjbs?s4x|y&&~Fu?Cf81DgBbkg(?50tXA>{&p)Vi_@{$`o!bxO~Qo9R1mhDcv zwm!wsqkWZp3_aSTAiYD8A7&R&Y##5Sp_FHYjZZKTFeedGqkD^#dqj{;ceNsXoU_5Y z!OvBH(x(gnEdH#Br=1(h#1Fz?fgUn(l=$U7_zT12>|=02O;-f--;-`MTUEW(E;?;F zd#OmACgrhlkanv{<& zMqpMKI)oZ)&rWgRhhl*a{S~Vp84|l5p5+~|j&=>yE;4ksp}-NszKS_$ZU(jg8I)m) z08AoFfp0gVj*5MDX5Yjgck%wFZf?B)P#5!vXwkM&V|AobOt3NG9LBC(?HY99kQ1NX zR*h+im_hS0*8T8xcs%|d#Y2?*Aj+70sWptvDiy~%ia)8~EucP`sK5nPCqNmP`YVzV zMd=$D6*~>7>{B+=F%Cn1awbX67?d+^_FOcyHN2A%IwRt=WgK0Y>@M`e6TY~`qB=pY_~YIs<1Uo1=q#i$Zqn-!b;`l^*;tp%x2m}{&?c3hUXaJJH*Dv8iop9pI7wc zv`f>4`Y*O>Tg=evSFYP0#xT2BRYfSJvN^W#oHa6KPAW+bKY|Wd!c`uxyq3M)?F7{LZpH5=$ z7FCI_@Yhb@D|=v~ANVs0Y#D?C0wQ2vQSt^~})F zLK{QNsCsroFgi={O}!`>!0Tr8tIxtx?j7d`rI*4fs|Nb1B@&1yvq~53kmUB#Dd%c| z*F13U6ETvaj3!$UzuhpZj_W$*V1nx-`Johv?L&EunnFkdzjZ^1$p6^LA8SkwC{6_= zF2!l+y#r^cSzwt}Ii+}&opspScRavfUCy!L(T$7%NHPVjB68@2*#8uP>pGP?zZ z&5j)$$Tvi59XWP$P>!%+qsn9UHal)qlOjQI1oMEEm#s?2otq&IGag&GQvG5N{a!cb z?hME03+89N5NSQ1&W% zJU4bzSXW4T7l<%qj+*odYsv<@dlTQg$E*~>gS}ONiM;p0Bffu&DoZW1;G`?boRu}q zUg?SH&i6cb^(?%f%;?@!YbFi7Ce>iUR+e{5H5_h~y8KJnAE zhi6X$PdZW!6{m zLn%TTb1)`ynpGU15%gE$E+Az!hIjQ1AnqaL@SH;*#Mx0L8E6N})F!;{$1vAcr^ioM zk+<{Z=a)lu*usBo|J@1}dfj(>x}^{AVO| z5htAn2z;7J^VPpg1J#gz70{>ZAu|u+&jwe<4)BjTyje^!R?WM~)^q$6+)PoG3Fy zYu<&x8>m}Z#FjLvmGoLk6h-wXW<)LuCvkc48=vJCIQ@p6h|D5?Lcq3QejcEj3hKp< z2+t2??ow?02KUATy$2z9ZKC>M4VMrwZcKAmCKvbLFbP}+W%`#$a&`Fo#cY@S?hVFwPqC;Rq+Q`U&UufWZBb5A0I z{8=3UySL!MpY)>Ev!$2Y!Nb~(?Z2_t2sP@ONl{N}Ok7;+Lx|3+1GzT+N8&^wf%61R0IEgh}31*XHOR|mSodl*j zHLjdPF745IKu0b&W+P%6`JqMjv#O72hI6=-Ek{hm2S#?#PS(a))?gi>Z@k@9_A*wm zDXymxzn&guzG&O=4Vh^2Arx`7)rO!0@f+#ti zvA}IY0^tp%KXY4L;M0iGwThxmowF^s{KP=fjQh^CSdWxZJMx`?i zO@cv&w3r*pRH?bD4f=~DRwTraaKY}Jo&$1-q$0M-X;J}zDE%6oz$IA*g)^Lj=CulR z0EDcz0eRgj-hgHCUW$MnBe+N8+dQKAgWTnSMI;q^UY?wWC4Na~R}+FqCauP{W1zW2 z9_^f%m|6psa+nBXl^$}> zpgBoapc(ezUYf6@rTI==?9lM9Co^nZ>0JU^FeJ4=p-f8F;GDm^j&$d`d3*!w?y;_7Y!4$c8i3OCA^Q&GM3u|1=#gv?`fDeZ+xaqwr zh%2P9c@P^nGTvajj#=O8{J9MRPH~EwvVj79&^Ho`(>hjWSUd-YIXN|;)RAp14Lwmm z=8x?)+Rt`%FPT-Vl2`_<={2k?>M9Ash9ogM@72B9Caes%-b@|3X>L4Y)y3)?xcYIq zk?V!bn+r7vNl*F=KDGAW=}rg7D8pDpiXHa3r?VUpjbjK&{Le$F>lo6O#$RCZ(JKLw zzXXuDJe7%U(ZE{oYw9@S)&ARg*j4WjFq`=N-`5isl`Bo*+RP;X@pSb5H!Jrw9SVL; zhyD8{s5;&Uw1&V5;K7?=jP9Rc(0TJ5ivz3RuyR2s2+Ffb9NuP|B)C*fUCKR2Hx~qK z!hlX-HlZiws6vxA$n$u$V;$5sl`9>{REwivHU5bk4j{+>mm$$v1hE)O`8(YwY{iKY zbhxs2$0{`xapojXMZl|UZ~Ndskka*g4nO`Fe$uA}U zP0K1?N{cjV78QXW(8e0p%6qgs3!%^x;u0Q#kMyl*uQ0W@a?-9G zQAw0$OqL`IaFZa%NxL`gUQ8tL2m#*$Mq#v|Q{JNp#*|uaq>-am=;g2KW{F{3zN+;> z0hI>t0ZV1GY>gDxPg*{skGYaAm3=YHWUUc!5`*!G!^{$!Zig9T@edok9!ws2)vC&Q z&nmW{2_Sn8sN6$r0ZGmeT`-p~&_=2Mq+ZhNSsVIBIityf^#WhnNr>)Y^LpT(8_1P3 zJZ_Go2~dh)z^>_`Y}?X!5G_z63iSD&;3I{RXGu_;fE%a)Zrm;rI?m}8eZPZ&2KciM zmE;FuDVUF#qpuHfdl%m;e-%zvuW}`yM#!BwEotXR#$tPTNpWm4bbx{lBqNqLZ(dRz zFWjSucCx2>SAV}t-G2)Yi#Cn1tiDj+ynYv=CcM48VT(>CrGGg|uWEYC{sJ$4mxYp9 zMVLCH_<3Hvc|LuZ*UYMa$h&eIA3gL9BVIg*luFC`PDjwbJxUU>=0I3 z9l|n9wXrC;>1m2~Lr!pLK}Q^9(q!6)sQiFHx$uo#!X!|BD z_Ei;z;RiCDp>i1{6=W zE1Subm;SK@m&siEKB7!os-2rGHYcGuC~v{+8KjYi6qsL$%7A5|!N`*KIsPPMAE;{r zMbr8DB}Jx+$UgQxB43l<*f1RbEWjFs!=<1yPATP64K7%6Dd6%IM>ynxpj4%`%Ym4G z7B}M?6X)dJ81egklV-Q*ZNTiF_0mBI zDvB2HK*vzy2&vsxjBU^3i`uA$3iV2Ql(B@@3nLHFn{v5fZ%d<3y_|Ncph5HDIbFIV(UNTi{j@c#lTfCgx6iHdqmB2ZR^(!mHh> z2kJky#}=d|{p&{`@eVg)w2AkSA3r(oXR8`T^jJK3ugZ2!!N|#1wEWu=?OiO zjz=r|ehHl+t{}xhz5q@Z; z*+3UH%7&l}PdK)h9h=R1R4NRxJ+fnQ{)2`TfXfw%?EQ2vWm29}1~c!D`eNAo|6oyM zgTEl0ixVAZD|qCvF~e)FNJ~>@Ea~xmDgsF2e(XaVqNc96P6RU+C__JoQj3v#GDuAn zFUWQ-sCO;`>FQd1t|A>wnLm;Szjc_&RAOW4MT$oAQG&%@1vn^3`_YtBq2N7dt+d6YdFO7h(;d7U<6!KIBf zw-u;0K-J?xsGA`wJO zH`dGY?8p$4%!T)XXpmey+{H2|&J6cQA+E+8&8O~>p9ecbPf#TAFCvE)`%Cxol@f2( z@u{4}h1%#YxDy~MIDsl2>#VxDOfgdVM?GFmIuqhLq6NZ3wsCFlS zmwTLuco%z|By(ISfD)ynhl08&A;qBWdQU({tbUdk`iP6yL3Lg#Fn1LzQnjau8sSEh zemRwPno_!2J%|x@kPqK_jhelV9>6z_GF?Yfh7}ofvn&LWb6Xvaa9c zLalg1t(Z{tvQ|#FVZePLX9myE09ZL{2tRhggvQuMPrrtzNpG#I=%EtCTMVIY&~#CO zuU~MGYL-QgP$!XUlIo*H*HDhPg0`%g)6c}C=8b63fmq2Og|Uhbw5D10r{cou5hYag zl`}>v`>eHm7);X){{1s;ChjrB)rz|P*n|9CfwExRW8-r;k;M`7{P_w!qnYFWFMYYj zSJM7E|Ni+)1wZ-!l5yOgk9$nYc^ekzb;%(vB#{l{Iu}?JbfkIR8~Sj6n06pIRy19Q>69HDH0aW^$#-g4suuYD#`@W@OM#W+Zkj66k$fSZ zre<|!n!$Z-pXyy>XzQ0(TkGA?{taLt_tTG2!(O)$Y1WsHejh_}WkM z1xI3V-_jrp@UPvQJZ#~VT&i`h_n1Utl=#h-z-E&21aoN>ZI>9pF<33!ub>>u<5IOO zBUmz%55rLkXoeh7lq!hU!k&g{h`H+bx6o5}^uaCRaG%nUbdH8M*O=L$NL>cWDi6E< zW5fKkZ-gTR<9e5JbzC;8Bo}Eke{D!kj{vrem?=r%QXA5quzJ z>JfbU=N#d5V#~{P2@#!Tpq^9$tv&YgCp+Cck#JKnu&YG0M?u0J&3;w93O{LP)RYW- z+&zx~7DKdC*{o$aZ-vBn7eyBl!6icHl=;S$Jf0x6p+ck+i>@Un^7S8{=2i)xrJ(7s zfjj`Ug(~wo5`4W-nbeay!(mfR^Mm|Ju?1mSvAuuZb#erU(Tv%}OxmNlr!`>aR|6+xh->L4e(~9d`^Mg8K!xDB0(SRyYat<>cu^%cdAUi~wR~S6z zgjbp5jfK#KUZbvrFqAioV#<*@dDm1`Y08@Di*jC2f z1Ymu6vN#oUBa-)*&|7V&t*N9$h^eBqF&ml6gRuuh1NBHYBMXCsF8DnIPZ70})aO#2Tk=_d z>@ix0#~i!`xe_9dA9WiFb^G2z>@s}agJaH2zvAiL0CS>cGq7jz}r`GFv z%oO*7#%vT1gQz0Mmnf?v3^DnE^1CUT6KO+u`t&X2PG23FeR!+WR=WOL8ke3n1s4pe zX`^c)XU70geae1xK_@AK?rQ9g%Tt&@uzbJ#)PB9KyMW4*MZCGM3QRw2tmWVlB%@AOZXNp( zyZ<7-mc!Oi`(#JkdP9xdpX=yvO@~iZwT-fsdGiG_i*LvUA%>EVP-)0iKV4|6_o#Cu z|2aJUg{&;6+zXK4lR+ zoyc^i&KY$U`ezL2ar1iH@c#F__1t;fRCW9+q* zED1PpU2+n11u!&$1rt_C;xS?r|EM6=9jMTu96oYFJ%X3acxE0f@W)GoEL1ITwvbPg zvL15*a3$L4BGvSec{45Pvfttv%8fIDisK#bPraXCKl(drzP||~d|jeK(!a0yz2Hvm zDNKe>VrD4eWFV+4R^zZD6kCvk%2?-F;&Q_xi`fDzcouQ3tcKGNB;;AnqZG}GpsU?d z6C3q{W@PkE#bvQ#j)j4YQf#hKOx$-^Qsg0OBva=V-=amg$$BmseE zmTuVGD^kv60Mt-{s7200;TnT%niw`=tS>p}Wq;cIg z7!na?cZFp2?!UTR<24^+-!}wHmnq5|mAuC_@H4m0HR<^Mb3^adeB%*VwZCIQ^eAbm&cHz@zOg8ej<(FF4f3m+)q(xT>{p*>vN&x< z%ZxUH{sU)0ZO!41yY?ehvlkO@*z9{?vc>*ra+=-Un^jJgPEUNx^|6Z<6Nx0s?qw^Z zy*puv+oG42?T_6+AL`{Rp}m_(=MC={E|RpV8KLX@7x93GGMANX$lmR45L z3#ThGYie_r5Z~`9!7b-B6t!gMIneZE%;tOodU!qYvFZJHIBa1?n<%wjH`R_A51via zDxYXmVaf=z$IeqH4)w4{=MVAO3nyH7)3%pL+gctFDy5^?i42E|H`hI%Pl@~o3(%Eb4i0yZ;DL;^=Sl_iEt>H2A2Hl znJZ=Bies1$u*NTW;>W6$Gomq}GS(l~p3`HjQ6-2(R6xd5kbHws=e#O^66J)Onk|gO zGKd{0vPL*d>E_Y!1r@;TadnvWvv^kV7(xb?slMQX3Lr)TdOfHM*+JHviwt_1#w~GQ z5o$eXpAF#*Rmle2-y9a$nVyF+695`tQ#^{Hbao#DJn>;{cJm2LHEA4c{1m~=lnDX9 z`A3RD$WAMnV{%f~ksEbs90J6}}nuG&vPRevbsGf|zwrBN=+6zv;Hw68tbR z`8boSA?oR}L#M4gkU^UyYW{JrwW+nG2+;X?RT46QJlrQ3I69xkF654XEw{BNIo{^_ zj)$_xv?;ik(c(yzwp2|h>=&5LO+3>HV)u5xHhaohwcTnD{&Jq$n0--^@=b=9at(z1 zQ=zdI6&Nyy?`eel_$d?DvZU+{TKk7MtqEEvE><^1hXc)Y^i~>7{+eEG`^xRNQ-8&? zClWEFbyrtHB3paORwXB@E05QzhBY*51~hUSGQByX(>U)=Zk^q(1bSjTkz2!&hQ|~E z5&t5J#+TLFYNe`QbLMi?s*9BlmI72agj~}ghm{(B+Vdh$X6v?r5IK=2H@t38O4Ou& z`ehx)96{4DVrI0RQGMP@|FeV3wG>ZyB<*+j;G(|gsgMd~^W22<3N5jtSM^+)&TkHfZZN^j&Pg}wL zXV~BxrIoFGvNvbSAp2z79;Ul0plLD(O}Z@t#XnFgTzJuS`>K2h}+eNF^)oHeTc z9gtpSyR9PB81=3-qYZ8~2ydcPcl`C7yY=4=I5(5=!ABW|57A~*?s7ygA#Z!OS=N)| z#fYC0q2S1&Z5D*I|xQ~M2V3E(0@N7mhRiJ%@goXw|Imw3M}rfgA|uOs&ifb zju16|Xr!#(QJGh;@wqXs7w9_mqzb>#0gAc=keUdM6^zy)g~Si5KS{L~-YfU~*a67KAWYQ}agg^j?$s1eNr%8IAsUAIlLLX`4h|g)PkGM?c zOs1q8T}Rvv7QKtmytq=NZ7S$e&9ktoLo+?Z2BJ>;{F4Y#r0WmL{e({WmR->$2mR9$ zp1f()-9NA}38Df_n^zTD>%K5E7oVjzp@K+duO7P$> z7!E$gpqRwv59}Is4r_7tTP` z2z8sIo-1sWOZ&r$+8(8hV(Pg%8_0L}%4HYFXBb|4pI^S~%k|#p^vx}c4OLBfOOKqD z#=3)17KpFD*G6lcZgF^`u7?`ffE=aC0$xUAzWlc=Xgx2`BO$idRN?op2R~$H&`w5L zX4gmMfffiU<#@OnzTx*5@9OVuiZ=7{-(=;C^prl%XwoZ(73u&lh1rWxHKD*}NZ<${ zlS;)qzPyNYqxC(3j6#alY|3=&-+{c8dEDN>YIICyg0kW!zR>5M&0SO!RO43_&<)Sj z6*wVw_}a=^pJbr-YfNa0LiYG4@OqaRv$wt2%}OVy;Cn2XHa-gSIX*$o=|ed7wOKqSFN-Ey}@dkEUn6*KXZIJQ&)HL z@I4;xIzOt&5Uqr1+w3aIV#3&9+7+~{?kwj~UTM3%NctaOh?SucYb0iz?$8ZiA#K-O3pTyOL<2x&|(a! z5_WQFqs%E`%(EQ1OLGID4!w{*w>d{xa>U2KZ;xaBtJkGDCBJA?!%tXm1Ny5s`Vh(j ztIqivT*%`|L_hm^_BVbQ@4?bNn3r9=jO*YZb+;S$HIJH@*w`BNUhsO00C`f5+a z;VC22#UW&aZrAug@dn-P`q=gO{Dy8{eqhbUPg5f*Z+;Y~r!%auLJK$%=JEH7{e@R~ zOyykBrPkSvR^M!7fiK%>{fQw8u~6?~_VWQ> z=7!Hph@CeID^OJMt2K*~fjd4{-_7xP_x->^aaYO>l(B;< zwMJE|%I4MucjN=#*WSr8stUZf=t7$H53owdRNx<{mxXL3D9~dZ9=k+P0DOf&e#@^k z{8OP($lpF3celSyor6V%F5d2EohM)*`-6=D+kbRym|0`*@%4(Obm5;5e|D&Szws0Z z!?9xFRMe_+Iut31X3)flmoP-Tgt2N_s0%6&Dq9+SM`ii^GQs&m&UgO9EcVBNjThH0 zB;gY!EK5P0?iCO~Y&rR5(Eb=Pjx*)-bRv|u@n_=C-#5fOfsV1izEzF3216yHx%;*b zG=sH8ZA#9${A*g)Yh4zc-Yr#!JyTMkastklcHlVv8aGpkg&pAhtfEX`;5n3CFoQb_ z`8=)GQ=N#vxe61uGY;|C?e=2SGf#+bI_?R})_^zNb=n7pr92z+|=E(q|85 zmrw|8`sDjWW%cerWOU~rUs&!+ak_LLoPXej=9p~uW42uO>++XbuD0kUuP>LV960UI zJFHv|+x<_1?}NI{^(FhYZU)P>fk#hd$bhuKYOh;W9mq@jTxzGyVtCbAI=5Gh}#XhYQ|0 zm)-aGt>1-DB;$JTCMfTyKsQ-rjN?knz98&9X9jo~W*YA!Iju{c$;<_$%lp4Gv#E9W z%PQSYIQQH{yTKzK0RQA%)aKEzZKHxXO%?ffYlczh=2`zGOH-hIpRXDb(|&q_%4~Ju zJgd#GqpzlLBIw4kDtc*aVcTjh(NVb~=_q~0+}KMKP(|?34;4*>QNyZUwZJ-p6z1S2 zjEsNhEWW!c#z9sGFJ%|}r2hFm56Q>wFCVXp;N>TuupbZJ+~B9$EK6XP#(}|YCY*SF zo33YA$p5wj%FgIt9-j+qcKq3CGlYDdVuw*3>W)XCk&DxU$61rL+TUig2PS7s$_Yz? ztXhm<&bA?&ksvvR=+#&j1Ip+2WI8O+*zg3A3tzXv)dP#q)-IC*xup0|%pM8zvj*1} zCvC3M$12OQ1ibD-4A=Eq{cb7!zYzB?Zx!x58+Dms7S41GxRV$qQ$Xw*Xis*BAxi9t zu@bK<%(Mw+Gu_3nK{t2u%;Fv@2T`ZR6uiRvxZZS>P>ZqpXSE#Re&^|jcg>W=#Z!zt zFf~QD!^3Q$YtsRHr6fZCQhw1T>)M}6 zSJ)BmidykdDhz;3;Ek*rB64aY0{6s#3l95BrLtdd$T#v3J*j5L2f z9+>9?S&x_uS&zSRimHP)kpKtEN^?M*wc6YXeGnycXQQeC5c(<884jTPS&+TVbdN>;3^TnQ#7mP*I3Rpin1qPuS7b$i$2vhBpPL)F-M`_e3% zEA5=yoiYiDq(Jh0i-3(sFIj7Gk#s3i6s1uyQrqafr1<`~)ZI;`# z**~7cPZ#+{jKIzjewyHXd^LHwzI5Dd?Pq7P`#$VYzsDK&sh=MKmUGJ9b{T-ym{r8F zs>!i@UpJw2DAiE*z4_l36rkVRpYS zPc>g~F4E0_v9M;-TK@xGxKErn6`QTRy0kU)x9jrb1IPI8|!I*L!eW%wA z$6u}~cD=_Ai=8m}_X~2v(<6Rb_%+8kpMTsHR1Ewo9n+A-`mF36#pMpoM%@}5Wk-^3 z5y{zrh)}|nF_ojg9UY~lEJ4f8P}m3vlo+D=etc0?#dLs;I~A~thomq~%IgaSDIJGa zlC3lskr?t!5|dhi!$q9u5eCg_B12DC){n=-6B{Vbe((kvahfk7V~&*O7N@hyzk9JO zt|P&ynh25@exmUb`6hb%2_F$TOv6Dat;|g5BjAV(PtL-Xr^1VapDogwf*c=5Lv9Zy zItzJ=tVj)-`Ee!q8M7-Mtz)@633Cqju`nhI-?oB8i%mP#%ltcN1#~}>-IA6p+ut<( zZYB*JvtD9psE+l7SO6M<>vhlNdp+ztJ9JZd@m?+b8NdDWhfEFRuJ;g5ENEQ#Fa4pP z`*pLW@Xlzd<=&X-ee?eS5JB(0QrGRizKY+Jdw!F@^z6ysdiCOOz5h}4?fYu$(4nr{ zs4IMY0xD`@-T<&Gh2M7NzoOy4IZVZoPIZFhHSk$8*yO+RU&#M%c<=EIo;#6|*6C6zV^FTo&GU>R17aYPv=BBO9AC&xx| z&Pd|Uw4Cn(Y4@0^a;M(~Qv>xVjJQ#~plpnT({W80EiN<}_qZ&q0|#LjG6YlaM23zj zzB`P^7uXh+IntXKE%y4`?z#$E9Z{1@sp?^t@8bJcp|3`HHlg{eRvb6 zI$A`{oIKFXu|16(-nmwsWCOdzY3^>XXKQl}8ye=ZwtfzOP!*b7i-0?xr{8H5QeLnQ4j5cLg@l>3O$ z7N`HGUVX4|awa4`fnX`)6DHS-OCTaKiGgXE_=U$|XzqloM<}Px-eq`74)vy^aJhjKkD8cg>K zOnuU)3P{T^8z62oPTZ(CQjkv;5{?KjZ1$;~d+yhJ9^I+19*(PXpbxAMEqQFxofFV{20-+gqyHzHtHD zn-;P|w7qEoyIQN*-CE6_O^f8UOE|ElhK?<@9NfNwKXpw&db(&9cP}31+1;~z_|6S} z{G-SG?8k5O%b&f^z8#H}7mZ`l!eVY+J;1+y`H%+}c2h4dc}ngWPMCx6&xfG3&B0WPs#`5=HrK%jU75hCj78hZ%nLgaPjhy zJbOF?q-;ny=8{&|3=~l77#Q3cwcMrTnLJ5qDCPJL9o7#=V&J9oRP!1lsNJ{iD)|h#)-8Gi%^gKpRnoCT2 zA@QS2m{75dlB$&~S+kitnd7w2`&V**7jHdc^PWSrA2`81iSMmg$JY|S+qRpF^)2k4 zzk>FPIu?#8Cog#%jdNBpCwn@1DU+BqIFFJMr4$Sj$>?m z4%t!T$c!8#=f-L2jIgnc3>iau@MzKlN0AOT|>p`!I=#4A3;X&P-Z5jalLj4Uu|jOC!06&^DXQ7 z#kLLnV&^7)xvLGXTzR$i^PhLsMqS}YH=wpmKzc!-+LiYThyVUCy}1r15Kz@Ovjm{?*Qb4|R=rw{MsF7|7>L~$4-3IyAMA#HRIRz_WZ)kjNjSY z@fUX&er;>XzgQUaFXl#_vglmoUg>eHKkJtjvA(vL<`q-fP+P#dC6idcG@o@#^Vm=` znWox8nwN%d#nwUo6hFbIkPk#Nm=RolOmMXj?mA4KXq|#nj3I12ZFWuKM)Rmohqi=qWNVHI*_(^pkR?@_Aa>J78#Rih+W+#Oj(o zdiJKbj;>Z#Pu^eO!~_#dEA%8*_n}_fM^B$O1kSy5bi{p{V`O2WNnKOLhGypSS~HBq zVfzI}aNzK1vIeDdYj8H_!iREV?Kh-=T@;oOaT?AmvfPo|V=pZ9Nq zLwNkoN1ARuevhN)u5sw-IXVuXrDo+O7OvdP@-0VMw*3@2OE(doGml9t_K@Gu!N569 z1Q*s5I%O3xpFO+Fmv7(Vi??s^#rqHV`s2r4mDTqp{1LwV>U%XT_um|*zkzXv(C{8y zt$;TN!RO!6#3?FzQQ5xMtE~?QhSRdVi1t;}IJmi*jRMe3%M01QW~!FnyrP&^0c=}c zA&pfNXrA>SLX^yN5&+vwsInCt8-aXmB*UuJXS8q(bDS{6>*?#6~FuC zR~+55nTG1Av^7+4cxxl`rPhtaOBY~bF`uYa+>!(BCzWuslU5WM4(N)qD2?&kk zHHMPb6VU4Qqpwb1diU#tkpNL&>mu$+h(*ZG@qbF?s@QU3qQae*NgvN6Pl?E3eb- zEGOsGYt+5y=*czZSjDPLA1SY$m-{l5Yv~JY4JECkEBB_WBllp0w>ZrGhfgrSd^T$zy!*^d6r)z0K!Ouk-oy>l#dd{L#a% z%IbA^RfE(}|DA(0Yud-a_>Hi&1oC%&cT4BiEh*Rjz1B~v=kj^gOg>vMhX>_zs0vDA zsz(B4ZXy?vbAQSl`%~hO@Q<>O|4x;5#l^O`YDLNkyfW-jR~Z)?}k}iI?zD-@?v(bp2pF(O4`JMYR7A*v#+Uw4dPh$ zH&@WUvXp~zz8j`DW{je-b^>kn1#Fjd+g6m&P%(<-Gc#B=Ba4QGQ+WTuH9mju85Ko2 zY+hZ>vAwNS%qZc^nNvhXMd9w^$c9C;*i<>6i{(=^m<}}Kz-4jw*!&V{QtIC%5~m#+-4E=l#cs2!8!?EiIV25ZjCeIE<{qA-xjI)HxbR6KI(%1n|M4xJJi5$-yH_}P>M}vu<(MQ+!7#2^o58CeUV>qG5rz?^ z7=(+$x+Wbdg-pR9NKGV~jA3xWH|dZ9?N~oBAN?Saiq#mYnsg*m>2IW#6U>wR&SeGF z1SG>CxmIAIXd(r5yI8*W0^TWO$*Wq&vTetS%9u<{dJb#bwsPT2hq%o-G}V^SvaE#7 zb>cn+j{Dcmy}KQad8g&PTs$fO+3|5H?oj$dg!zWMR;p0hKS_-SA@zP$igma}+xMt+tThxYdNI5;|D zWo0dnQ{bngoU3xMo$%F_vI?4(0_RTXnrm=Wuh$o-DnM$I@(PkRwl+99J7Mo&uena; zV)YeFb>tr8{nfqbiGwwl>)6SA+t}L5^%Su6MF;XH8V9l9^@!Q}2mOuRA5ByO;`jZd$=_cONcJ4Ms(v&>w+ojGeenA38M{!?m*D_coK>1uo@)!{v98Sc5Y z*o|Inmh}uWc8R#h2~Vdf%*+t6&#h* zRB-J~TS&f=xun%B|IQCE}g{2+I+UHF6Z37IvSVc3NUju;O=c!vw1tm zOmEK`$2tM&>dNtSw9KbzalSxQU^;UY_0vYOxHOIVrQ_MyP|MjPdzn@^mh$|uEM8pA z>ZVqF0z=51G(iLHj)s+-Ei2}#!1PF26_Ii2^fGW{NLDUQZ9A|qv%%EFN+4w{utem5zwUy>3O~s)q7%G6i>|_;86$sUN1wiF~yTPnn zt8%4%UMg#0VS%-^fLtJ{!BnoL+^jmUx`n&%MO{a8&r(*;P|i!9slYTmBAR0-E)W$Q zN29qjM|_jXOqHO}B8TYn_Fmq%D&R8CkM`Gv_a8W2PTJxxwep zq(Slg8b5mX7GHjFx9gYsJqUmPV^^X($np1JnSj?YeMLeyOds99#*s5u1g2^a(?X2I znW|?ohT5U%(msF0@M=rte(!X)=IY4m$FM->iNC(v?|Bi zG*<&_Q*8k|B>(8v#ag;?Nj^K*&fv)AN*WhU66LbFzL>omD_+3#?kqK4nnT0qbPoibZZcGHECMK2`7@BI`v_{4z8Xy(0RQGH*JQe)9VcHEf z!9utAMG%X=y2t6sgxL zDF}DNRCPhC_f_uJ)Z7efak9#psys7mOX3F%=IEJggoY+kXY9lVi*VfBlW>fmh+lds ziIW#HW_CTrbL+Tu_bI=usL(#||A>pzK-#VU_>ceiJE;EKzx|ru{O%82zyA(rZ@ov$ zfosfJy^lE?j#9SvFhk~SBzblVgDSVB*#^`u)lOmk;>m1ZHC+HX zg$>ntG*-#=1k5|7%nO*#&SBl6JesBak+w>9%4-{Djbi2WEP-hzOUg2sI%W`+B{{UN zTE^&+!zeB(qkPU{`kJ}o6P!T$$T4J(%3#{$LUxQF%VleSHjgX8)iZ*=#*Sp=%Y7d? zOJZsU#%9(S8kuR%)WFaPCl_bJBEnxlQ%QkL9V^Urhs zbC|vi)t~?T7yRbm|G=$B?{VVVQ(8N&v#k9zbJibb#)jhzn!b+2=^N-jtA*hFdIAd? z@R_s{=j>V>MpSDsRWo?4#FeTA?losRXwHjqPx~SBG@z<(UIoz3aZlAn+nIg=(5`%& zLGxdLR5?_oZkTqCt$rhmWC3yVRB^oRF0R&z?i*oVhZ>QR9|6-`WmLMNciCKZJs{5!lQfFIDY=R22YI+9PZ~PjBQW$yB`|R)b1J5?e10M87v#~pcnX_qN(87SY*|)HyJ%Bg zk*3Y{C0eYY+A5&jR9`MCV`EJb>laO?c~JpPRg>9RmCwe?d@bEr{mpFNbCc6(Sdc@T zxLtLf9jm5kFkN0glDesx%+DXn)T{x_%Ns>m&S*wwWH4cpxEA{$dYXD*WaW-;Kq&L7 zDp^z4z`2S!T(W^TM?>`c_KaWw8e!OFIMc=?5)Zy-?8(G#a>M}EO%)~s9G z*$pdF@KRmA3Wf@33Wf@VK7PKGl$GM^>#IRiLA2Y2c6a-#{Fs;+>gwtko;KpeHP!W$ zJMHeyRb|y{0s{jH3JTKPu5z_1R@XG_n#|M<)1-mP_y-2y?BYUS0kWZmH3_MiY}|Pg zKfi%2H}ay z^;i5>V0!c6+Z?<4n3j&qY&>|AIcpD5y7B;{s<$$5W;6X~G!tIfK**HU8ce;$t-x`F zdMswXHj7umRCV*(stvmZo@$|c1=H>Y?>omuJDq5^3+)DJH(b^E*y1*Ab+B(hI=gcc zleTkA=L}!vPBn)r$A*c;;)L@UGqZ||S1$6wv%7ry>=s|WeSyl&%RvfA3870@MVePOx^zFVbByP~E>08@@DF+6~oChuS%I zs`fU0vCnBx4*CHT(DNIEp6_V%eX=Dzl0M$4m;|N}J0ycy(~78=l1=T5@vNCQi4B#L zX<8)EtSO~Uz}h6vv$du`lrNHWo#d~WDlW5>4NHnxTUEe%foJn#0qeqi)-IT&Nx}2? zT`=v)N@B&VF|1iA?;&cKJDS?*=`1N7#^T~3OdlP~#32zBj?Ex0CXV2UWQ-jndDGCF zUZ&m{T6@sg+D`q-RqSlv!_(F4xn>>A!_}JziWy8Vb5HbKB5;q-z%_Chde-jrGBBgJ zjy`Vg9%N;YqNKEx-U73p>iN=sy7>9~Gbt|*6Eh3?DA%alkD!o17A%}cWK<+Qd-f9b z#?ICrJ39yM@s>UU-JX4V6CE4H+V!iMHD|iy>(WyJRRF4~!VA=tv)icLK;j347^@i6leMQ2D zkFN3L;Y}Xgzs~84SBM@p1B?Cw)7TPmisDQKoN6|%q2@$8A=(`)m@0t2tZt}w$KC0_ z1FOW^m}-~0f!YaIwK|eOT7ar2Ak_<2t0M_e11F;IHx>f{s)6q)3?c`TouE1Dn@0M4JtY60YGah_`gpsN=auxjBH z>gP@tDR@q1g~YY9CTOac^4%~!keS4?=~=9pBM_aDK~>2R78a#4D>sqi>_{>aeHfAu zLQ+yPCbpjRvGCoFm`B2Zfs7tKio}EjEG%s_ z!0GArBf#I2QKQlc2=c|)#E@CDW)dA8MM8W6Zk}F*goZL8DN&qhI29Gs$)3I}KBrH5y6e$3XB_lJFaq1ps&!o7dh~SVQxu;w#Ep3U4 zjwUufiv9x!VB-;hfpa*9ZUZpzNWsi0i5k-Yt((``bs)yUgX4wZHshPI)K@Ubr|~+x3gM&20#k9P z_wQZd%;n3(jh%%>!v7eiM!`j0=}wp`II1pQrI*3^GDy|AmychDX*W#3kbbV4W^o++ftUrlEQ%OjOq+nbc6NV3JT3QBE%gQ-@;wVLVag=?D+%qdj1f7aio@(7K|Ay z_xRxlWXo$~#Krmr`p`c)o~=8#5*8WB;+kb_*}j9qqA8p{eV)kh81g6OGjzxx(z4TW z4~<1voVKoe68!|G7S1Wung_GqJQ7#;6oKhjETZ!8&6rJm?n1Il7jXUVQ~vVBSN!ev z?QiLpraxZ0%9EB>es$(7f4Y8ye?51eU!J|p{Y`t=HfsrcD%a9p*+^Z<66WO0qhRDz zaz>OgcHjhBYTB5bR>JtyQnCk@F*IrdLn6mBEP8^LPK_AL&~V8MoxotZw}AnpNcPXx z)SXW9>ym#K$$^=q1j)I;ERv*gm*k(Rl}ia6t!Yrum`;U^m9nE46x^9saY}F&0|L_+ z7B++XFCq~ADGxxTnl4X#}<)zqEIr4^~8$U4i<_9Kzyk+L6In%ey zd~pj;Vg2sIEZMMy4cm@zb5%1}?IZYj&rwF_&!DeW0B@KD(#t-I-nQZNF!g41?sRtU zKE#;OV`yt@Va=M=R8}ow=Yb<^+P0g#$%TxcIDxBIF0o*G8BtzN%qYlWTWcMa^UEnI zR*NGv3cQCgXWl|`a|@V1ZyuMLD%aTDc0Rr!2mM&ey z?|%1dR;{XMvV1O8OR88@TSNQKofw)~5EvHCq=I6m6i?;i<=ez23??Q%iRG);uxwo; zZjl4g_w0{>&rtNdh6zjuQ)?DXlXV>afg>;t9gBJ7B>c1Hl00PzvsY~5$f=9`{tth6 zF*f?mnCYKIf8sBHQIExl{`gmZ^P4~L%U}JDk3Rne&p-VIi`VXC;kvyn+;ocB%_kXJ z(L~7PIzo$95mUB~h~fr3##LjVUWwhXMc59Rr_JP5kH)CjQk#S%dC7CN@lN%4i<(UI z@-9g#t!+UVTZWU?b8(&96u$gAl{Si-rj4V2-EK4m(wrno6Us!PGD?Tkau4jx*8s zPDjr(T`KM&7`a4}Q#6x<2M_U+AAd%NwD2cor7|Gg4=+12#tlzp^pL^Ch6i)?!Wq^z ztYF`c9Slhx$dN-wnK69^`}Q87&Pu!J-h}l=v+ReypMC<0>9+*t&`L-+RW6##NML4x)Bu4sB}}vUf)dwM(lgDlTDIdNwoXFQTw)8uJz|;OwcR z%$re2)5-<3E-R8fz1uGY28>)bJJ@6?N`5GW8+#DS68!m=?V(VE7*7V z3~8fsSX#f1-TRMIIAu1c&fh0{(sV36f*4s)#`x)ragLGi$7cv;ej_pUNf($75txRu z(K;4yzf?@aMx*wsbr@JgYH1w}JC1Sr<^uuv@4o}4f8sy*BY*j;0_xxRt$_6NFMr9` zzx+M--uaTtPd;bv>YdD8yN|g|$C$SMDC6t)5RzYqPfjg?c`J#U*@R8@e5}(JVmGuJ zn^d*p(VQ1RRWP+u%Locc)dZq$C@Mg9Z#Vb?rZL|QQ&nEQPL=6a_e7=cNlZ!>iRyXN z5^M+LFtvImw>6mFc?qWX1g3Yt-!T22g#Th^`W;iJ|L*ud35A6)dh~1k5A<(?68P7F ziTq0Rlf*@;;K8A#f|MvkpHs3+33rlYS3kG%Z&=Yh%m`|u%r6zIo$J{~-A zb`Ux8+|5;vy?EyC&QIgwc;DZjujAr*$JdW9W8yfWtH)g@XRcUU@yy$Y&mvgv3?us(-jZwfvx%Xfbu@h~qcL|*B0G0Ja~C%lrafeh zEyYRheNN>X*0l(<7OfT+x|xlw2Uyd*pP+zKBSCp9a2vZ6 z+w}Q(4?BY7!?-Qyi$7fYek0SfH!GYZNW{%9SdZcF9!WYTjQhfZqwz>5Er$ z@5VJgc%)!@moJ`*p55g~?+94me+|=DJ^UBL^xFf}-#-3Nf~o0?itx2w>;F`P^qmEe zK>|f_n*zq3=27%8i{veH0jq#h!SyXuaikUjylEN28x|1))i609uElSPD|SE%q$yHpgy8zeQ#-9+^V1iuy@OAVg(8Zr%#{m2+ zy%>`)ocfXq=4a(n6rao({{XW5{23b&Ow;OR5ni;#F=Hq+-$FB*OJ++n^D4y(W7XssVBiZM($JI-!_Ou z{{aNr2N3QO&X9-^B!{HpDCgWQ1MzW)!pA8AFZ%>M>_oQxMTz*?hfr(b#746a90G?5 zY%?$q&A=fsm!aZJr`K%c^o48u{ttiBK>Ak=ph|z$mJ|HnA=WhHN; zsi(Y;yQDkSWa_~NV>eCBW}fVE31*Xp18o+zw3*w|YGT7C(O!EeZbXK2J2I3wsk5PD$mRl%X7QaOczX(QGlZ zW4(?U>%{r`Sc=oMjnv#_Z@UB&}o@E3q8gsPWGzE$(R@ zA$jUJ4s&_k00HMUakR&c1K2NsK4KY0he;3}rooyH2x#|Pgt5;eSQN;9`A+s)__E(B zfDXBrg97$rmO-4h4dJYH5NFK2IVqpfaWgND%6E5C@=ngNyW7c6(K9s`(_A}0L zTyT%&fpyFomS%z zY<&jPFLVN?(G#&BP)OXwN@~R2o<4h(KmAc)`e%XYU;ilj6My;Z-}tvb{Dq(W`cHiP zli!FN{gPeBZqt6`Hgi_*p{#B@)orJlvGy zctxj%RbZVu3+t2_SPYn|fmFq&38ezLPVi}6yb7wyRmRIX)rA{dDsWV5Ru>5<6-+y& zHqbW}_u4Hpaj0q^VC}q$qXnwsQq^@kVJgnI3#Q%9^uetg0@Is(B0&B8@y*vT{T_w? zZ@~0*_@9P%pIqYEz3V)9aDx*!u9BQL2aA|VSV!e!6P$yU-#9D+#$)b34s*Y;n2A(c z#g@KfvGS2vWF=`!pD|c?cS_}1c#Rf~!dzl=Pl-ilp4oCds;g`k=H8hSXUcIF)_$Yp zy|Qrd$i&ub4Elk&==e>-K(1}zoBcwDQqI^Xjp38#vH8duHg$B+w*LT4JNDDGZ6D2B zcd&i;PL7{A!j2v7Y-w+yam@3>!RoetnW#L1Wl^=`j!>MwJ zp+ew4Lts9`I+|%#F-#YCJ>9^UGCfabnfS~5cv7bCO1Ysk0kf+7ykU0zw&Q?{3{pkf5f(v_r--CVNugD(FrPBPcvfL8v5rgC3{{gX|u(VPF+Vt z?otBARN*(a8qZPHc#T<%%kX(P4w-|4$Zqf~foHh}QS-!dER&{ny3%+7V@#);G>Ms} zIZd;;8KS8gK+WRCg~pV;0IFf6a;U|UClFR$y%MW)+WD??%E79!Rs~e$P!*)rsz_!D zQohTXc6al>|F9FLUpx_a+6B|EK6udeOMM+))$m^n({E3m{;sLiufzXVc<<>|p54Ex z!Stg1phu3IL7C?;mO7d{WNR4$eOKp;=u^GrxN!Kb_b*e_nEwxNy zsl@VuAX-W z`aYRjY#^1eh3^n{9J$2x$4_b8+)B&V?KHP-rLnn*#-=8kTU*$=eJd+ht)#x8j_upF zu&up~ZQBH{JGQcY&mOk!+9S~2$Cm99@9JRBfg|iYbc|j5k8<(aJ*LiD$n3c_jGZ){ zys6cUFPX=r(h8<7T7h+7JpBZeIu7DAZNkKDhSA49l0E{|zT!}I#DO{n3}SWL0oHFl ztf^77Ve3(5&0WjTv~eURCb6t$F=NN1abVvr=FXYUq={omPK>8^Nfko|r;wGIj<=Tw zRh0|y^Yvl<+EsXax-qX}9?lNVtXz^I&}0$I2I~aY+a|ElDxPMG zI8m$?H<`!E`8YOoX`_lIZ@s8dNy;@^#?WXLC$Uoew+zYu2-E%PtBgmy(t_mSH1D(Q)_$Ej#xTnVOD)y+4L_K@7|)qJO$LXqQNOTScNH zpwY7qW5n1}-u>ij*0=3rUHc){Z#lw-9mg0yYY{`U$CKPYg{kGUm|i@U-8*+PXLbcO zOKTZ5YBZ-#o+58jK4qm-2@8#6vosVE;sC!+6UwfEoMx`Q#Q~2~59y`xZZb z|MeDZuX=b5(^n*XBrtvY=qe8$-s0-D+e{i$%2sh1brys0bIZcnYbWUpaN57E0$0+RFv$1o{#?fswjviT3CR56e!NFq;c5*E{w@gj;?y4(S&U>jc z894i7;3{s@Rh*}%IGS1JksLLNl(baB0U7l38;726hE&c&F!maRq4z*+{Q9%=;7JzO zHwa84u(WZ+$k<%lMMdqb;^^#zUw}WZ?rz$aWIcQL(iVbOJF2+4x#8;mGFcG0x$ z0OxPs=gR%3L=PU{ImyT}l3wQijGk1^2cLdLNL(7Oq3O6qX5$&1fw@~aa~C%-d2$J} zXU?IdsFYp1c2QVZ$mY$P1*W4oe*8EiM~-Co?%fO-GKBNz&y$>-%#$ZiNJ>iLz4zWD zGBT2f4<8Z}8^ebme?)?uKYQh-z|;d%hftyhjv*#xB#8q4KR7vSFjbmv=t3Xsc=}j| zqhskOj`;wUE7npaTD+ewtsz$kgfa;(&yZxSm|j4i+*ViG2i`ItmVzQ|Z)6yBL<7F~d;f@in@HC!4b;#`dd zxW)>q0%IcuWO1-6Hi{PKs>;Xb;m|*uxwQ@4zjd_>rZ)tpH~8_hn|$^B24BB>yX%+w zI=rgkHB4WT&<)f34{mbh>MbUXEu+Ogj`_CY{`_*#Q`@WsPeC`Nhq{S9 z19bHTgvLhN7GR#A;WnFNl;B}Lq)xIVpr zQQ8)MrV$eb+Bq1>|CgzPpFq$cEEhwOf?+ohO$D|pR*>wL%2Uu)Ahn1u!a_i75IjME zIq3yVyUUr1BmFLzD)(wAQV=y1;HvaDFdfCL#ml*S^D^%}x~{?W3xVlZPbGeSov+@# z)%8n#9bVP&8m6yE`0%M(=w89}7T2!bA%9#so9rW~bQpq7@OX5>@&u&$7zRqk5Fize zzf>|JBR{D`{G%lkmwRPhh&&ECCOJIVER)`?Skp8o(*xTE)apOi@oSj*^ zcnMZk)+}69M;|?Vc@Gcznkcz*u}7c3gQ-%3t_?=cF&NnS(Y|dj4B6#3<90F2kXz8F~<91dx?a;Jt(;k+u-ORAe0wzzdVR-&RT#_c? znKlzY)txIY)NRmIyar4rv!I&F`WDLPFK1#&6&bm+C|yv`S3%r^@e^L8!b| zU}}?4g2RAv4Aphiu0~xT?uN06a-jlKlZYa@mH<_bO*D{B#z15!F4sVTSse>Z%@XpZ z0Wpd>OIC32<`v!%n11;9I-jcz!k=8{M`|m!cW-w6QeTHxHN1xDD-u3Go(Ts%4FMU z_L)WD;W9`ZO*%%Nnb`UbV*7#PG_`J`skx2%#e?Iq-RiGUdp&} z%$L6j3ID7swjZGWay>Bf$Ks=WRLcOE^L;|DahY~kwFdz`v(lhy;Lu?R}VHZ~V~HJdzgB4(k|h?4Jp z^0X?RzW)Im+BR|L$vYgsAn&z(CpVveKvv;Gj6Kwt>_|}>2A*l!YFGwd85nqHNP|uw z>n{yE|M3FW@!Bd{#sWfP0i=oiZ<~fq`cI|KD;Y|81Npx+rEmqP~PFUQwp}Mm-;%qs^K+EUy<;^(`!6?bd3j(ZgcJCJqjjFW3ycZ3+xApYaA!8 zv=AfzA`Aiw&<_%*2IisXpQClt>iJ6L%5Q&%{1={D!C+~myVn;bnSc^B?dE6&rxqd$cQJ?~hKafP^z6}_?95DULHUe~k;KL) zNm*;6;!?Q%;1PQdA7EX}2HyMRM~s_1lb$9%yk+7qF4UdisAPtY%%PXQ3;j%d>0{uA zo{1|a=C+I@^h)AZDmE-H<$F%8lrO{xIj-d;^Or2$0Tv4`!g9lG=w-5;4 zxVu9m!QCYg+&#E^kj5cEV6?(Xhxw`b7q5fNagn`)jEx=EgNkv9%J4Kbg{Lb^7oiGdTL?vy+bGXBD_| zifgw(!_})J|;%> zuE#waBRNBNJc|`X94D72Bq`MI3J|v@<_TTUfed{IZXCghvpm6o|6WOx>j}~XiO$yA zfO_2+wZKn+w@cK-y89VW|L(u!F}H&w)%7HtD{p&nvdvn)!7CfbQgF?r0OCsL&qG+8 z&wMwOYVk6{TKCUN+(({Kor|77f-z3QVJ5HQYC9UC?BgWLVSc1&PlV{dM;<@3k5=gR zy{2l>;xObGU18wNGX8x{q_@x*sSajmE7ctcDrs19yya6Hzrxaxte#+lw+-=ALPSe` zAndxfrfzz?)s?{+EiiNb28o{xrRhZawKppGnc3>{qX0*%s;au?=W&dUjjfGO1RxNy zwN}eg6$J$Z@3wYO%Av9K@35$hx_udEr#tpL%*ADH?&(|w(&D69fSv*5?6~%Z<|N?A zQL%c%_I)>Xb3*`-SHyb8WLd1GTdy=+4yo(2uz5n;;t!w5@l`&Ak-Hf12>+CZ6+_Ez z`1CmD13pYyHa4`T-n{7^Uq<;Os6cN`Z}05dz1oe(WXoATTzA-#IrYOTbvNG}#z; zN0_!qy$J;3_xHB4w7%sI;^_*x$TO!vpZID1l^$lKtjYGj){J=C%&qwGgFfH%290sU zW00BM{r8DH8WH!nv)|Dz_YEZZKmsXFHhHN!0X>5Mo#eVe4~q8bO%Yt_WTC5Q*1$+xZ4>Rwml((T@^C8Ole7thtd$2OY74zcZ!rc?N@$#lzqQ% zH0d3gkQ_KbSx0!PR5g;W#CUpDYt=XyU?c*!gS^k;X~=-y7ZwOdS#^N1IH8`s zD5(Ays;Oi07B-%=zAlV?CL}A*+NqeHpO}bkW@dJHeBAD95wqR~o5Vu^bawVIwy>cm ztLvU$2RkY$3D$Mhk$CU2BZ0m5w2*Nb@(Z1KV3d{cSZM<^_r!rI2|fRc#Ygou-JpPpLf zUl}l1JbC7QHMBPUR-ODi45r@6r0bt)WM-_wTWB2Q6w?FhTp|jRExx>szOsYHQ)*%% zX|b9M0|egt3u-c29OK`Tk-fq(B*{HVWh+ZY`BGZ6)cvFn8?4Ok# zIlcVh4feiMRjupMz#8sTr+FDhx^ayY^XDHk*` z(ZuE%pE~5~lO~GE^kiu!>47WknN-znhgQ;6xRX*na2%GAc+X|Se>6vCgDVz>R@qb2 zhXz9*etZTGPZ6|HvcDG_iP~4ntQl9+D)^}=7`#EZ6DSTCVsPURJXWd9&f9;~ciz5> z|L2NK)-i-msynrMWImw}(Ls*?huwXhGPU@szkmKl2r>Ic4DEm|0lL2gKM@vLIr$?g zzN8eV)Ia;+n_w+mzDf!nbp17NeR-FJ2=3-lBbJ~p-afcYz4e_ zZt&8g(};0M%S@Cg3Lj)%0X=x^#5RzEe=7%56hXL#Mq`w2xlKf@lOGTQ(## zi6(sBIw8iz_e^&(Njtwv-;@9kpMD6Ggc<1F5ZPE+iF-uWp_qGD#*~V1 z_i2&xP?pNzv2#>9pKIpd117t-ab0<7ulr-U;264p4Jo+r^<8cV)R+Y9zNJ%`_` z_tq`!k|$&~6Z2h&k_fy+a0&JGI2y={)+$;ixzT+ow7yz{-n727MYZwyiQMz^NvZS< z`RVy7yD5lPWBKHU_uD4AcDN5MFP#DsQKTcamjG1opRXXTMzJYTfgL@GOgH%6 znRaJ{-}B|>MJmTPB_*F@!g^P=2)<8q;j_BXN8mE;PxnQPRumh}Jx4jTNn5QrgWf{M zA?90Y`=vNG>t%(hQ34d=fT480h1XhI&9%V_@s`64pfeM5gEfx65-Y zn^d%e(0PT=orl9PjuA0if`CoH(HV=BW9oBx0JCdY0a%a7et@}5yD7&WGic_3+2UB| znhuB607$NR?X&b$gQv@e-m;11wCBuIUUchBD5D?q^&gv)9&~X|mX?PUlVapUXk2Flc(;;I5f@AnKT0-*QXvPGoYxnJV+e!L@fz~)x%jaUEzYuuY z+NKDKKb7nV5Bi&L)$XXZ(M~xg5x-;HjJnNK^8rc?ZpGfNDb(=OU!4}0w8_PH2&uTM zKDq~GgeWMjfQbWbTw{fIYkN!1&55W-(#+7vFeI&ob1JUNYH?EHtyt~$c5QIM^`O!a zVAJ1qTN9PtuqrE9K>5tmJGCH?nmONf$Q8Iv!10A&mf9(j0Z`+JwQvwx)r8-s(omjR z&Lv0eadMlR+^GD`_!}yisvn{s*N(ygpM$r5sV@2Oq_WPjvUQDcev!mg;HbOEGn8W; zORHyY$_82N&7`nZ6L(0Rlz+3r0hRvd?PRu4yj4gOQ&1*#VhFIq2*JT3 z8nLqgL}I!&Sj^yfdA-`ZxXc(>+L{NnMFoADgr)Nj5~e-rB^FSpwMklq}u zhQhGAROwE-;zGK4ok+LZ>Ym7cvaq>(Jx_<2GLL#L<;CEXiOG)m`GRDyI%i5x#$(@yM!K#xNfTGN+&gY*yM3*r%f9AO~ zS*!WUC-i6E&5<<|dR>xf2W0%4Vfa)F(RB^sIfeHhb z23)^d5?AQW-KC4^STlSu8tL%sBP=S|(yXG)oZfra@yv9)D>CSgEsQlompSV!O^dss zBPuw&iask<_^g)MN=HDSY(*Zjc>`wg#*A>D+Z{a-$}IFQugwI|G7G z+>%VI;sXNy4X4|O-@lw0bNULXRo#-t52UiEHF~|X5JPWzd*1&|M9SwGgFXG2qTBLQ8@DM7eun(kiBKN>r#?Hg^lDMOe{nc!E2}uPimiRYdM@vt zpc+hJ`vxA$Y+$~xd?!Jn+!1^7G7YAEjwMCBG^dU#{v8j5i*|^N2y_nM&BtXCCdj8v za?s+m6+p8$hLke+zciFzW_GIh-F}0D2+$sU`!@%W&XeMh|3;d4Cv2`?yHx#-oEbOT zrLO{wmP=tYO<3`M-+^Q=DJ|>|WLBGK8pAHcbVOLWz0L_ddo#2UP&&W6k*%N;?Z57o z)LQfUnrqO@Z+DNDmN9cAA#IGx(7KP{PW;h|aI8*nG~0(({)QR8+Rz%RRF24>l3CB!Bn*iY9#M3h)@!4v%w~1g{bi!B9gKAr*ObS0K42S;$EYLsV&IaGangnz*GlWdIEgO(Xo9>RNLbdApb-0w(cyn?-4Xzl^c8ZnRvq zlF!vVImJF;F&Wn zNS4c+0p^e{D!$c%z0_h&!eRI`cvl{5ZHg@?OI20H63}1FY^5t0!_S+hsZ#^mwy5E9 zxc=ws+~Iq}Rzk=*)x7uVgyU@IbxcyH*_rgiSJ8sYYHu}2_VrlbXDH)$^5f+Zf96_K zZ?30#qvH+R!36Qv=+fWTm-QFuCEE7)XLFs7J0eHwx^a89w$hiG0Ukerq_31{8A3hB z5{&xI{n6Gf;*fEeEo^u=XjB&va@>c!SZ9j-V6$qz7R)fJUyn#k4OKJ(cy=?HUSSvQ zOqJJ%I_AVofGyotxoe&6zh1(7G?7iuKiWgZPM94vVmFj_hAWXfl7o$v0Yj@O`xPD& zs8v-RW2i-|jniZk{E%G6K7o%CmdqpMQ~RqInt+H+Cb@4w%9~n@ebSerx83H6`?T5a zrH9V=`+0XtRlxJ!WAs)P{lE1+4f>t81j!ex*=z*~V@TlnHNY4)XkY3(0AII*FVd@j z=PRqg2QFEHBPxkNX?&5&tM5?SyAgG$R@5VmCe|^ zB!6xZT%=jh-Th6IeB9-%8TIf;BYtJYpI?H6>)w6~)zQ}auQl9s1ARbWTyR)#krq-f z5C-6M+c!LhYrbJOYSnsJW-e}Pj1b4~9YsH-e7+#HJ~0dGeFT_|)0$pRk~cOY11USQ ziWqpPIPg*zw|9>vrA+?#8^`Ah17g?r-hKlFGD-mm~bAlg+WbylPfZt76iR% z%OqfEcVqpr#P)mx%l!yjA&NM|usjqZ8AIVJcx78#+tXdv%1VwI0|Ja=>hamEP&+}t z(mMF*b4ES5@nrI424z+lAn>lLikX^%{)>YBax}C#6Q{YgQDPHxae^|y+0ivoLWcP7 zHI-sYLSEOcpx8YL^Rf)kyLa!U&y1zPg*a&MCWYM*iXHi&+R6ut?jX{z@6^7w6f|(o zFjiWq-{t@P_aH+N6^AJidx@)}YDY>=?g*mHpqY<1;hkJd<==@)h|^=a!D{EJ#@x#K z_ts7WDWsMu#_jo#<)YO)A_7;z;r37%>R8h3lPR>Hs% z8$x5%u{>6rT3r>9Rc6(0uukltj=?Tb|H-7)SQtOX;9z4+SF&IW{s+e9Z|H)a*}8QY zISee4<$;VG7D8vi5NddNr;5Ug*cPD$>s*W3yGwM5%ehjX!7{4KcVqj~WxNvq!j4Au z?{LaP>MSUyGP0%AWUAA+v9$P~fr+y0Vdu-t-ePC1VH_X zeeb#dZ3doZ2nm1}PF+rxdfaCm!W*4zKh$Z1AbuM8=}ac}Ytk6=e=7AW6F)odV8?$h zCCpoy`>Eu;i%PN<7$WbfIzw|Q_$9<~3GiE4SzldV&(04y+dIzTr~=qHBsPS)y8JIg ze;g-OWEYwK?VQyyu%rMuV}f`Pf&4t28}&#z$#Q}4(ko#szGc+1Qb@tmEL`2;(o>iyQtu#5f;;<(#zM2K&Y~U_*2F@y(+0~mW_HMD#Q--^ zhIukF2(1Kj;b0#-Aj_8W%3eB>G`YtQ2BB^bikOHP(7-a&>C1^N5-PL{=E0TeMQb0;7w8?WnxBg$I^Nb4z}vn6^0s{YU*nm%Lir7lkhQIU z&a(mZ6A<9CLRJh1wv3tf*_OF`>(AX0{As`g<^54LO+gwZYK5j|c+A~St^pU*&1Mj* z!V?C1kq$b>^N(u_>6|6v|5k@q9#DVT8t^w4d_EU;dy5K36y4j~UsG+!US@rk$~tyr z+OKC1mfr?$)GF?Pzd|e3wP{AGR9c>}+B4K|X?TWIHRePQ@69Ess$s@*#jjh^PqM^j zn(1*piT$VJhNJE*udNJX;?i2GFAMsbf`7R3Jh`B?T9j}`{V5Zq&&X&46B3hQvV5Ad zi>vUp;CDz>{AUuBCq26{QtfNEl9_=2aIc!eRiGp(7FW9M@ee!SYSoI48jvX`T1%b>G zhCp^Okm3XS-Yl{|OszV^h_`p$qZ*``nBHZjZJo1yeNl;Y>Hzy~*nKKWOMt4weRx4~ z3YYhdokfC}!6rt8;~~I$Nl^RZ9gjEopE+T8xmQ2Dd=*z<-WE|xlfnN7Zdj#NUf=B>W*ifEjNV8+DS}yp6fJqS{kOyF-6l-^LwD_*zE#P7Zci&o?jQ z(9npFH%EhNtd_k&@A#&NT&O|=++pqV(8>j{)*|r=w*amBbMw37I_M2l`oi+Q(Jlnp z1^~T||6WTv+0)4$?|N_lJwFPe;9r60p<4{ldmHOn;L(VX>O}56Hcd8!vdgF1w>GV8 zTmn61lT8~-@J!<@tTKzL3bVodhngL}dG>Z~KpzG}FYfT*cu&^G8iu{O|t}nbGT4&cgA6y^q@y?77F5rpyO8X7zw4T-WMZZgbCRYlJe(D3)&J=90UPcW&G zQ2}bgFc4_7;tFF-L-TqliKUrJe#o_z8MEEhg?)7;tT+=fKE#VisUfXHrQ>!!ri56- z_7|&m=qvQ4k7g~d`4g2D)jG%dSL$rmdqU7HCyvKU_58|}iQZ=E^$JWpMjlpY$R#=n z0vbANbE-1teiK+&S>-!Pe5bk>z81uZjuXYhL=IaxI&rnZ zfxTC&*+BO$_|GCt&0Z}A%L->!GvDEq*l!v;saT56 za~h?eROQ52!tt1*rl;t2XJ!#+cp)?l0^T_)3jU_$|L0|KQ}-#o7)F1{`E+-`#yd)r zE}kZr4T+!IfS#iZvJ?)W?=AbjiN;{vuJwjB=Z9iUx#EUwW05Bs5_u@)6rWG|)Q`8C zTKX3SV5*^wFVaeyO*M(9LKp1=@A9@enZGVBD{1KT2Pe7QI-jL1t^^0bZ*M<8$pn$g zGuaaauZz}6Qav}JBt6LFXBi{O8>V2Xms4B137F~8K>I`8x~Rw`40ESa+2>nt$9usV zjmiDycCo{?z_-w8yb0aRvnSws=B6|_naP5Y9JhNoa#X9ZHCULRn^lc8w7>e4goRRI zZx6>?U$3m9CoxoO#9?h=ZoDF3T|JdXm9s682>q1fdmFM1^prh4$DEj)W!^o&X1187 zEV@+xh3S8KdJ14=?OGI5SZ!|NQs#Vp<*$WY5|!%|1029>6RGVes&jY0jmXbubP&{C zwM9hQ5V75xc(;$Yv-$6ht@1)3Gi4itjZNnEp_;OePH!s|4U>W80fC&t44DTgD4Z2F zw;-`ob#|t?20_T1(Hj=rMxW@I=(ug*2^!)a`6XTQiU(EfZ(&8PVhtB~KZF-iQtK4G z*_ks#^jBgiWyYL~Mytt;A=-w7%d`0}3tM8(K#aroEn>aR%4iTBZsXe{zGy#ISPwQx zR(+)jU;%^x!MBJlqWMCpFNM8+~ea#WeI&9dhw-4iev-QsA;fpw>ghvZJaHWJYl> zGFO?IdQhXIF||nJ!b1eMw0L4`@a~M;tL_=K%&m!+a%)2s@o>blctC6J6katBnAVu- zmcY*(xH2IE;qqL?9$<^nnXVx@X5Eh2g)LRo|Bf)OdjrqsZxMX052!#+O$0?#{?Eu+ z%!jbRgm58)w+kv zxavgE0hKqmQ|Uzxd2321yR;wzWT2|6ZBt`ASWX+jW=GMG#ZUbFzK96))Q~VZP4+Xb zR0$t$`V4%5Tx)MvL$VKY=1sAw^P5tI&Tmb}vzmLK zQCAwDH~EEx)4qrIx3 z7@Jk^5SNlt#1S?)-2df6h||lfFU6%x#ZM(4l5m}+KwJA8pD_|y%+K#j2o(2$QBMBlkpee0LILc=qeV?pJbT~3 zsHCMSEKV72s}0lpdiw=orKfczu~@@ojr*n^vo{X99rl*kh`9=Rb24t`biF?4AcpjE z^PEB8ZCA9qhIMdQCb!6)xZ|;J;T3{S-Cu7bw6a_oR2O`sSwTw&XQ{?=>DUj|SG9gu zys*IU97Gf+;`T|8NFJ{$&ri8qd0?@Zz}^9?v8Z-7n<>*t#yHt+4;pIKpHh?j055Ju%*22g=3N zA5Si}v^6WV{%61@1Y;|kAp>FbJ8LU8+)%+D!rU6cQBRp=-Ki~tlmbXyd;NM5LAh<=0fkCUB!Zhlg=oNE#& zFM7<|Rcf?DrPJa8)wmI}(yG@KpZ#d6Q4b4<#z9~eqBB2?8y%FMDblY>x}P^2Ctex{ zC(bNZnm~`$iO;Iy)Tpc;Jx86SsA~=_C#e}B#9)B}Cq-%BNs%EkD>>%NAY~7S(Ym#_QYdi( z)CtM^>Dvzh8476wmVoylrOb{so0EA7d%B+4uE0mzG~tAt^{H?%#fuQu&@*5iNB|8lA<>{!v!mTuzU$ z1L&tayIpUq&0fKz-j|VS$qM#cyHMvkf<5Yj9x)FaK7+V|&%W%xldkR*d`81=IGL-F z#TTf81?r(yntT)-Z6)@w9B&T|Z9j<%)zx+Qr#=;XL2wn_(-F5$0 zLC+XSc0X8$v;UIZYp{0y=^NZ^KsIuOpqKqIPlRx3*>) zQuH-N$FA8SeQ6-f14dR$B^sCZuZxf3MhB#RDar@+=9WhSaLS2ly6u)ZE-)}Kt*zcg zdd-o=pOdU zRJZS#tP~-z_MuSHM~z}=6i$n7PP*Ndw~+-EZ61w(zBG?tJ@%m)FJ!_HC5L-X+~Zi% zj^JmJOn?j#Z)0xF=WC64(46gdd!=2RiKq;vk~)9HHo$V&hNT^o3#l@e7jW?@7f1!? z$(g9Qpe<<{4-F0)^z_#S2Eto<#-_@MibQ#Pyl`!wT=++nWWdWn91F=Yfeu=5r3~8_i+f$`Ma}Lzp`HD>Bth zxNm)D17SvcZ^n`7nz20b(J8D;f@SFe*f(6QjhWA{4mc6UYl=L7W$6gH*lkG$%*G5i zBH>h`2fzQ!CSgMLFnB-=GQn-_B>|B21g%aj6 zMY%k{+)3_dViAaHcgQq=n4x6xvwG$ed^2U-DSfF*FtXweJfq`2HOsg=j)Mjf4gS8d+YVv%0^rKoxAlT6r5+IU)A;YSDVsJ+^Ww zkHv+v&SbK)a}G>S#&%|Zu}rQox#-H((De9QGP5*xQiz+~L;*LWH!L2$Gnro0h%^?2 zq~Z*lE%OFjj0ENx|JIigPFO`Or1lPt22q@N>?bW(%Hx+*tyb%^IuA`aZ1}^?6B^-) z9us7V({(%B142NY9sc3mH9sr2K)`GYn{Se_)PETV8U#rYEew=%Zsxt)0T; z_P!!m>01;3p1+BQ7gVRf73^Yzr?~_H)O0FxQ`Zq?CPD{B?E~fH#$bOK&X#G24@~{l zSbB`hJsI@r`E+{sTI~Wi6Yn6resR2BP8KcI?nVy1(Xz5CR zFfz_(7OA|%y4avEaOeCWoBSI(XaH4;x{q`G_1}289-N%>`wB9LQ;Tw5(9;tB1G2vdf#(%#1v&qrJS`HSHC<3wMYZM%n7bzTYl zF&bpd7u-PQK4Am5|F-}-=<=1@R-d=)hBw*G?tzxm77I zbVbq@X4jYd@xR;5Tz7xKA30G6=zrpFsSa+4Fo_kebHcOL~Yi>{2W^z?`Z6dmuY8iW0W^#X(7ws&{Q zVo!-kA-gBVIkWTBVmJaG;bl}c>=G}?q}EXsK39{E^lyz!RnZwk=%u-Nve6?5eg<)8 zAYw;PN>PIrNB(Q8#jZGdU09PQz!q|!P>bo*2nrRctNJ--T}Fj-m(UMnIQ8XY9r#SjmcYPH|Fn)cX;n?bVK|~rV;A5Am zK&pHETm`X8@ftiI#Kg}3;CsYlTz502rg+=%J8Ceux$=A>+Y|LBe*f)Xi}vwvCMFAK z_j-3*+U7HmE&}&6P!wVh0+~%Sks*8|^()T$q`I9wi=k%2JJQRIDu$Ld8XtuKQs0n2 zYtEoV!%vQjJ6oTy!LtXuo(1PLCb6rIcX1-4<2+uVav35|c5l*$PxdBy|>i$e^k z2r(HLhtIJkC!>0zACR~RMA0<`xu}Q!QJ1#F&MOXuj0#jrJb%91{<;0md+!24+=;pn z^9>W*7v?+eU!4Xp4bi5?c+B>9nsVWDJ8CE?PfYDde%AvU{`^{F#$>SW|9v#G#TQkM zuvQ%2Y$CJgG`wjvy+cfBR~9|uviy8a3d*9EYsL;pl#9n&6=^YJ#_H|>m7kwqs!=7f zGPt5urf&7`lSODnmIr-5CMT!5HC>%;k4jNXggOLE8%G=JqrC<=OKOSu_7&=#txUUb z@iY#FkR{O4;!`h`iNOwmtl(3$Co++zHtb9fWV%HXUf{sw zyYJ#jq7!d#2i@qjy7`r@G&t<_v!iA4_4JSNHo4spL*;tejt9VLWnd0Ib5jrT!&P~2 z7&7WN4Ij;zH#r_ar7gSK?LKmsuX>`t#H!r##UCB4KQ%^JO40bbC~!POlEyse!Iq>8 zUkSvVS6SI$BDsy9;Fi5#b&T2wbGYAA}Ji~B8UD}H3dmF zFkS85H{n8hE#BP)eB8EPU}p5&(OCmJ*^o0|fh@h@<-o7FD{~C#%Y~>V?crM=DBult z$CD|6AH(3U2pH5}$ zT`bo&AvDtBA<1L>QH?mQN{YyY9AkWD3Ry=mCKb?Nu2@w}OzanCEIs`wJ4j1|0Eu1> zuF~?U)0T>;C`@Y2IL{Ia0h^BVx%wMB+w@%Co~!c(ZPAs|U1?E99h_e#NiAEs;c8(V z3JF{2^)x85U#o{-*iM*;Zf1p%Qi_4_B)zp)+~PTjMMF` zJpFlSS5fjWPs!lt)ouw}k2yx;VcRsXNoDb>lKu54YP!HibU*Tf{my#9uSPf2w3F!UvvoSy0^}mbFe#66a)w6^F35i8)m4UQ5SeS}?P(l7L zazTF>v2w&?2O`N#c|O&7y6hO5BWJEz_ea=(99S>XKJ?jd-aj}Mhh91`eM)OmK6%C^ z6feVY0pma36t$5D_uB6DEiU|SHw2zPPw>6j%Mkk_Vbb8e_q-hR4Dk}n(E4JN6vevd zAuh4FiB@^?|AB+-EdYB?96|*R*$mq!h z8`84I9I6g7yDi%3P|Ow1z#G*LqEch$0Hmeak8%yaM?${-4t@ihCfTXTg1pd0ZJaN< z`OtAlQidCURjMR$z@rrsCuL|vJT6EG(HsU{)vAlmkCfq`NhIa7B>9Wx;#iYJkBLHr zdkVI;_smLHDl-#~^sWfG)EKRjFBvYf!p7o#N zE60Ii1G_{AItBSKX&)$W^Ue3T!Syms>0FK^2+`@CW4sTaUuyvF-BMyfZsb&>gqrxw zAWmEOaebbcfr(6v$NLRBKKXPOgla^=@ zXyg$5b0dYgt>0bfD=dWW2e~zLWH0PT3==BKdV0UNWTVmhqwZBXep`&A-E*`ad~CR$ zKXf&kvwmHv%Gn72;`$Mcmy~ptX>pOZ$t?Ye7Qf}2*Tf^&ge-O|wKL&_Y$ApR{=ad< zH-N#YPGm+Cbl7)gGE}BO$!($2;+2q>2CXX^zgujmyBZr$x#QaiJ&@1k*2gCx&Ff4< z=cqxat>2{gGT}Qq0?E$>)G5JTv+bcG3Hp@w&o6abg=D@*Ff|4!L!Ig0wJYt$I7W4< z;kPW{e$eTMZ&%giTt{{;Hpv41JZS;bTE4K-CL3BkK~wJGh?KboNE|@dMH>`PwL9BP znE4ec<=~|9xjS7fB4Q$fISnS^46(W(Pg$J7Fd9^8`b;2{)VzvDHH@Qh9Fm#Zm*GvN zuG6+6q3@2_{&L5eL7EYqn|o;$mEPvWdacjU2dNd??>7sJ%`X7748Dl+5QVDz@~;>N zQYb_$ns&8<_SclB>n#Y#IBEv7peZ~7uSNrQc6N>0Utcr%J%g>;SE}5OBs8S`4a($M zm~hRcC}aD#zsX@y+8|1u3L*vN?*M#W>8)1UwHx*9et1*4P#@+6R%B7XzP4?iZ=u+d zx;DneJ2C&-I=A{_gy~J~(Y6GGvC@H{T-A%_;xcc-@g;&dThUH{1_-N+>*`usq!$!) zvu`N$6Ol?G4dG&vs2DH5XBmVNM*~GsAjHO&`&G_63&YRwIBbz+%qs>an+Taf+r8v9v20EpO2K0iqYsCo||MOYfZruJX)8jzR#Km*ihh#&tO}RG$ucOKL_a$DV>DAm9cDdH)qhL$eVLU5(j!YX)qMvQ}a zdEwc@`)vM2ASC86Z7Q&8Y5&27SA;h4gMG`1KvIQn2z5n!ZvuBjmD?S>lYpB)1kNkG zO%T-Gg<17mftZm~KgW%e3YZ$oeX}25olbu1dA?W$<9UB7?Cs4zU#b~`UDD8%>T8=T z?N>&glKI!5SWbeJpLa*WFV`F+Qjb|`guXWvLJBnh5Ec^~=#n<~?aB^lXh87yhyI+G ziS^QBGTXCc@?|u8MhHT?wK?D8&KHDNmfzXeivuOl6e;5u`AACMbTa;}L0)b3`q^TP z8~%(-&e`xe=(}4nbMJ9@S z=O+*9zSt*6L2~qV@=Dk*zo4H*cNHeD=zPl>+$-Y(>%aTl>J>rHE(E3B)<{|JclHN; z`Zb)-#!7j1_;&MZB;4eZ_DQiCl6686Q7cHAkIb~3ss8AIRv!73pSizjtyTc}olT@E zuJA}B`zbnD7^AI!jIYbmr?}2-U#Sh_6R)*v%ea6yywIXOhNawGw1@Z7hSh+ zaoQi(__3xifhe#NQ3&N%zslDy|L{R5cAI@Sgl;|^*y!i_k_cU~i56{CSR*L*QeydFw&P*u!yD2}pEfcF+tX2@9W=vMd(>*Xjc!R6A~Cncz?jR##Y1QX|Ldp%zYMz*z9!WfR^J^7C1~S|mPSmLP z`ktg_8&pS&q6Rx7unc=k&ZS8xeZ_6woq5jSDD6MYO|;^2CJ7Xw>IZ_L+9Gh-BybJI zDq30y`S|$*yCloY87F_{`!}G%w`I@6B?rh0MsAzBX+2AGo9%Q-dI8Jre8nv3PHQl| zNiIzR&E1E`0r;#3B4yKtZ^4l7NF53VKT{bFvgflNvC~xLLU69-oy(}cQdA#ZlHov- zYT-sR7W)lSrM0l2RXKrw@N-mQ*-{_@^ijMs?@tvDWQ>O&qk4{?WL-FNyk>-fn(Z(M zj85dvgGA7Ts$Oo0Y&PO{JMU5?cw%21#`D7^G7XGm4nS#Vnp0IHf^-c;)xcsdd(s~* zF{98g#yAr8m_P8#>sNWMIH)e;XiaN`5)CcI?G=o_EH}?EXBMnlqpc+}BP)Ke0`^)V z%9hsXc6cnEi&EBmtQ(lD&W)bqj9Ub|X-uQh9=+9ZAeMzV^tng!GOy;00jSR^3xESZTr^DRB_MvRceGZdZe4L zpLJ3H&!-3+b#e+?48*XoZl1hTH$TJSv9| zR|uDf1G-*SPW;ByLWLvo`G#HNiq|6DkSQNRlj!NvlfF1+#3@@OFWsVL78lyWK@H*+ zWrq!0`i{rz%}A?W-q{LQ11aTYp+Xt&&NEEG&r!Q_ejIs$WXTL}1uP}vH7}Cd&|2O+D}()%}%mXCST20_o?oy>dDW%RK&oJ88Yp^(LIUu)E@d!`&2G-^z# z$6WbEiOGYrR6SzEw`34^&1l_eT!URj8RNxRLZ}+W`0()4%-5m~}VWPolTIj+` z$ixa3hfy=|Hzy*v+z^k(ML2-sGnHm+C5pPf%lARR8GK>iN?e}?ww2G4(BLjQ9#-MN#~ zw$Ph!*HmB}R;EaK|K(P${fQaE{{b&S(7tZp>cF$-&oQ4W3^tl@^f9EOkBMQQP9V)B zpyoo%&6G~jaP~{VlP|tQVipywjxJ;-NVU#Tks{Y<^#nafIB|0~eGf{dBjj=ds8S^u zt4r?x7v1Wq2Is}PI_aFIe)5m+f!s@d1E1AVVDQvam<3B+=>4kD!~P~+lSRPb%;*whdqZ*V%Ye}RLF0k_fUm}3o9_Ed?w0gPQ|>1 zb1{3t0*o9z8PjL4#E`LbkTqy522H7iYwSRR2mz2sRMY2n@S^v_Q0xY!y&D0G0ZOqg zDNS1fnJp_#*9-zDDNh2Ty;~X_+*07+%xl&rQ>BDJ%|4S|W071u4)aJgSFGBB*qqU3 zr~2+Gu%h!=vGVFL3{dNCh}w~&b)frjzbh{g&MOJocB@)5NO@(UEMdxx1EsU03A17) zcyd0${t~7=p=tqVPvhSow~nwPwfKte2~!D=g7-*6VDdmLT3dsxqEbv-u?ao}7~;gfLw`XkI=wiQR4T5y$M zSiNZzat0P5F*P0GQL&J!HIS&C1emfvUIr=q=H)?161f~2gBDS75vZaa_?7 z4TrC95d3_DF=zICQl;C4(Y%Kb9me978_`!Cj=ls78-@odQlYS>0^L@Z0&B+zxCEr) zvu}Te{)0zBu6KpX8*!){cQ?R)Ka5 zQUOv~-2;W_d!ovQ0|C#0z$tc(hg(E0JR`E<9g~lu@rxmKi9%f7aGY$ui8{K^ezMCq z9w9tqD6Cu(2&N1}b{UyR-*=9netA)G5gijdN5jDs4SQ3RP!Y2>BoSa4oCH)4^E-0j zXQSsauRz4B4DmB|TMuwr%mUMQLHa|JuBC63;mP~_8|BynRNm(4V@X95QG2)v`%W}r z(T;i;(uct>XDI5A95uuAZYzP5tp#5YOxbBe?>y5FKlH-%0|^$G-nn^2aM`xBd=d8P z!m(7J1w&8~+*3wi-0bz3xM&B)%&S3A>PRfy)PSi=_Cg!lAF(B~;h!=R6XtKCT6Zm0 zZQ6##%a>!?^cjeVj3$LdO3Pq?e^8*%wCn8ZB7l^g-b*D?Xf$dhCdHv*VI^+dyazYW zSb`}x^M=6PF_Kh90x45-lbxLhuS+?AVp2q&CGVJ>M==$IMRc4BH*Zn{?&+8?cO_nZ z^*xSKVf^azH)uS48lQjh4R-H2gmafKV(-x-INf|7I`<@$jF^sNq_`JVEy2-aC$M5= zH6~7)BG|O))3I^WM(o+U3!Pneu&{CwsyFNv7RKg9s6_;H5f!%Fd}(7ygS94BP^~Tj zDfsNm?**q31;s;2>5o8eVJVW*^9hOp2oDK`iJ)pSxx?Mn3vMo+2=ou3G*^U$M8ZIz z4UG(khAJUZvC(kSX%HP7N2=8c@o`B6TMhab41i3kKw3&VbOh|A^a4noJm3?OLY1LZ zEUn&zHmW$R-@F4}fzgmV`JiaXSloN|DR!`b<)-s^@%fk7uw@%gpFNK!&z|A(<;!^d z=n+nzIfcUw^c|f)gQ-)eV(*@MtX#1M3+6At)*ZXCVC5z#J;UG>5QCD*l_;6C7#jZ! zi0Pd3hAaPD3h^7!cV~{s&3MMaDj+u*B zV%D-XC||Z2fr+IM8IuH8hk{b&Rt|0^CPmEGVVGK=%ElEVR;E2+YB7eWxhdDIJ}oe{ zfU_q+8L*Z#HeN{IB`gQ4YWAVE^C70tcc)7k4BzY_0!+Ej^dE-_FHAp>@F~Ic>75pIlHIv`2g_$KMx8c9ST#l$Oa)Q!ASnF`A!Xm9J_CdS6>|R) zNO&GyKrtKw2SH57q&_*2dnF=m;22?K==jOy@C^uoolHh*%t=tC+*j(P)j%W>o7XlK zi{Rwsi1@^K%vnIn^!5{iX#z$`yl_%R%1#~$8&e{|l$An0!ID)etI%Qro;}UheIOaZ zmhyT?A>_E`(VA_nCShjLGUcUYmn`<^=^wE4Lcjrc=0+q?mt7z)ppb$I*#qT4x*%VJW7X-#j7vB!NzU1Sh{)x zUcdPktJbU+DiOzzpTLf7+flc7FZR^cVZ+v~*mGbXeJ?9;ud@SfSDLYS;UfA@W?|X- z8f>dSf&-_T(0>0Z?mYP%gUe>YD>NP6Q91C6%|*%7Wl;DLpctfFAtG3Df2jadf?P(? zFr2-76>Tm zKC=?)#1i<^`#OC5xB%1VcX(P%%R4arvKOWweCUPg2NHe^rU$fvSfhCpc-JQOnj zQi#bU{=DEZFMK={BHux<_bY*|FTu>G#9WXNP}RY?@J%R!!6zElVig?ZGRUrn#BdY^+Gl9%`syqhst&a7x8mg6VIt@5n_`Hm?aTE%=m_;=vQ=aN+80v~@j0 z?U7cf2&RL^%tGCP!>HSL01YQkVcfV0Sh{Ql<}X}~>9gjcYS~IOw_U?zQmGTB&A{Td zy9lPqq|S#x;nR-__jrOS71a6&Sd-c4eZ*Nu_Dr!x2beQaJ}BD!D%tI$s1v zrPKH7jbc)EPR;>H%PobL@+Ie&5jf&7X~AY(zTSlsjc0L&pmgT!MVvi<6?11Vq0e^) zo%bJLz~G^Xh)>3y&Igz>btWcHo{AmYcVPS08q{pwMv8n6GI&Z&@n9@kR3WUKb6{^B z7R+4;H+O#|<@Cp@E!%O2p!MR_m$-EGIx3e|Q)T5M4xKoQx)Y7){OlWK4w(&GBPl|z z6p?y=t4xi_C>%Nw=bNwL@UfFPc=ROhK7EaZ?7{F1O+v%PW}Lm!f-@H`;Wjgp%)Pbar)M z)f^tp8-OKRQbv9R%AjEc(IF7|5m5aG(Kahlf+s=Lft0F)&p_CD4Im@HaSh&^n`6@j z2j$jM4V;Wd$kcMENR_6T>@I8XXtEy2jXc*G^l^`-H z7vrWcz^;QQv3vt5wc|~gy<$5gZpoy8)8XVxU~`RvL>~%Ak7$TY5s-OilKRPkDxiRr zSwA>ZtPU!q{d`E>Q(&))fW0;ZQWH;AiGbWKMu_$PX;8YyLgpL=8^=JX+~b6NjvfiH zQ3t_2EDK_N5R|TTzQ!MZF$8joeIxrpqzi{@Xn%;D6QJ`;!{L(`aPaU6{OVV~!k1ru zi9h}M?=f%ABHZb?kJg)auw>O*R4!YM>m82?ID_Hp>V?UZCS&cIYAmi=g5Z!ys_f|K z9XTOAJp=O>%pJ7Mc{}F~ym<*kpC)|B};pgWIlR*n-6VK&! zC-onN0RsjKtMPfAzhmH{z6lgJ~3jP^Y!owgn5 z_r~Dl-VA|Vf`k{wjn0_GP+0#3C+I0U2S<(q%%+ z>N9W{sZxgNAOWCa0<46adC44niV2`4RIqT&aHTZg5-MzR;Xp7@7`&i!<^eYD!D)06NW++oDWxuU1JBsJ#HwpK?U%L z9Rla@QhLrTvUIq|lwxAl7Obp2gta^OVQhIN0V^C5Qy8Q!k%-P2g~eNrVEOh#*ie5S zQT--RdNND_SvcL?g$Xk%F=pai)EzmEsidGvr>ul671SbUQeq}nVWff#85EQ05@6*R ziN36m2n<$^A?V{63@ddAftdaLh6>xCD1*p?DPM?SeN-U?+-PCxw7zt#uPR8`?@M_k z1g5@90=g-U?w5qV1m60F^Qhgu53N^Q(0utKK7H{Vl@-g-a_tVPx9r5;qo+}S;ykK1 z?}y1F6iTHYxw*MmyS^H8=gxv!qlJw~25SciLCPPq=gq?G`EwD)1Iwh22#-!gH})9CZW!5RBl|mEv2qF4Rjq4X_4>4bUMvTG0O_BCMpp$qWN8j0}y;W&2u7@pp_floWk4jX=e={0=QJ2mEm z54|w`K*G}}xAE*=J09G-j=OhnW7W(G?9~Qhkv0Pwf}>r)Py*>-f~Z-UnvJ*FecvDg z=U^&e%qH>~N>i7o|w3`wwdPBAy(xe{zm8L%;=!;a3eF{Z;xpAKt77Fh;tP3chkXTvX{ zh*VJ?O#X?a8e@btJsn)r;pk6bjvEfo1OjpbeSTL`m)aNvMC9YmH^0G@=`*l$?Ro-A zJKAn{qUOM90wWdJ#xz)I32vH1!PptTjZ-YF)pTvgD1u}d0h3^XU*UYN5m^gU` zcGc9Ne)k?6KX?=aiiV+Tr4OULpRi!pWTBoq`D z!PUzTUj9KyN=m}CX_GK_&P?Rz=8)?1!TidlIMQ$ySDLTk+=XU>=W(1obq@6hkKD~4jyYnBB|XeGv=e?;VT40r(@{& z>9|VYuL|;)`MplGHN`!9>2oPj)(NQ zPNVbj=NLU>1;n0IA)*Q#+Yb8N^h5Q|!)WWg zi>3>0XuRXFDlVvnxRcs?f~)pbcO3I&JviLoZA}kig2cCrqo$ z7YfQ$fGMd?TfZTsHcLsB4i=hw*~AQ2P9tzSc++t*krd+xf z6=I}-g}x~^?iXdRIj(v5Sd)Uj1YBF^9N5#o9Vt_uGGXsZ3c@XqwrQW6f8F|lz2(@E z>UAI!vwC&Tg^h_IOXu==d_9>@8XWy%2~>JmJGw#X5o`8r#MgJD=OBQKy(zC712P`g z%1HQz8mCf z8-QomA|8Gr1QMMGsWTra-3iDVALJAaLuKU( zj2kx&3oGYg@#0FV>@32HHS4i(@iI)DI1v-ZkHyUClQ3n{I82{00|$piqmdgJ+a+TVft2`_QLdo54|w`K!OFP z_X(z5U3a=+YF4IBUd6B>INJLR62K|;C6JPtA<8f%g~pI2;7a_5QUSwp3FQ8{h{zoY zy?+#Re!=jLj>q)M#b~2-6<{bLSUM04?Rj#(09D>*nDS!N1p-WMg(hG+ z&Mxi9Y}qB9OO`NQg8T4zq^Zm|6UHzq@U=dq%HyE*BZW)Qv*+v6bsX3OlS>)_oSoVy z5^xh>^3B5iPrt#6jhoSM;XG>V_7F_kQG1{XV)iS{>zp!pb!-G?9V=5dhH0FjP;G^& zGz?ZVL^-xrN7Hk}Q695`<(RFnQ#3vz0RN1X>&FaReLTT6g3==?jeyH)+{CU83A74l zcB0 zn>Gh$FJH!kM-TAi@e`aUsG4hpT{97L*=3#;<* z(sc|~-cHL%#)|4{y#DfAY_B^88NpORik?>sa?k}}?&50P?&v~ZRvs=~X~X^_N72yK zgq`)rF?!}w$h>m|i1uvW6_Y9z`}Gq{;!l+0y6p$|`k z!aE4spa`tmTaRO{H*vbX13QnM!j=O^aHjnh&b8jav2z!2{mDy&=8Pm@7Qm6NJ4F*s zFpYtS3oC+Rxb5kuh@AlPalA6q*IE$1gL6g91 zLrT1?#k=Nr?Z4K9RN%pe320L0Ghp(lqRUnqdsmiGH{ z-y}iKN|OXDrzEI6vr)0`5RP5Bi^i)R7(IPH&XQ7VxO5+`LHVRa36#1x0fM~lX&-{5 z6;%`jBPD60iGwZYAqC2PsC`snLTsZU7!qKuNwM0}{n!||pQyqKnjwOH!uj+u6tj=u zD11U-wz0re9}fSJ1QaBPW8?H}Y@3;a&9icl80wFV^mMrRhQP@?3|ik9IH-Lvv}_jY z51+=|`IVS8cQz_27h&4Wxj0X7sXx+)k)tPI!jy6h89g5T2MN+S0mTwj5TbT0NzIlQ%LIKpy=;?&7wczUk|FYb1)7Q@Pv>Q<4RKqW29Ev7xKEh7e-30`10Z3w>put+v@tkDg`KBI62zo_rS7DP-HQom`2@*yf<>Az)qqFr+L#E2 z1|E@_-QB!PO4K!9$ZPM)s0F+NYU5T2YdU5{VB}RvgyvlVl2q86vI(#$q*l`* z_9O*M3X1Q;^J}@UjFoL4Z4xQcI8wy1f^&N-%Fhc}yG4&dLh(XG7EXuKHybI%*7Y z%f|Wbw9)vOz-mo#AF6=Za1%27vDJj4V$o{s+qwel%ll#LtaO5DE=Cq-V*8F7$c>(m zx`x8RB^(agFoYx)W7D3KSh}tji>tR#yaOxN6WDeg#)>ty7&B!t%BC;H$Z3l(WO5aj zZaszM0dpa8HM{fUrf_yX&oQs=)0dP!JFT~+cf=l$tf^vS=S-Cv?$_4E5Xhr(^vor? z{vMnqm^Pd^g<4X;^A<10^G{!*zJ5RU*43h=h{RWLk z)v6jKlA7c`c^i=!N+(CCG%8`G9ZR1ntJ47k3ovW;Of;NsLShC%P#p{jy+5%rL1-@4 z`ek9njJ2rRbR0$FmZ5OWVw5l0h066ukXk$o3U0m)7(ifTkaE8%gOtszOfBk^n|)=Z zSS=={d{T-ftWqhD!Z!<^F?pE1Y7=yk`B2mUB)s2noIZ67&q$3jOkZ~W0Mj>JJUylt zrvEqXrwF|;{XoL=C+&D~zZH+}U&sBfF07iq7`wEQSfo#dlV837QK=UVLg7~om+&H#jGQPaG`Gk!D1Fi)C&elA9w?aDg9;jo6{I+o z9{r&twJ9f)`3{7{XCRzB2V%No9FD2e;OCk~Fr{+{g!V3lg4(nu6)N(`6@b^5Alg@- zMnL2NE%|V8FNA~V0N8sJ39*RG!Grca2a%OfWuTbiBB}@wWCiCBd~5&}_=N-j1}~{t zXTAr6G?VT@1*B&I0U!gP=y-{>1X6ztQ&Od*f^E6U*p&)Zx|WQdll}5?zaYFq%xgt}wbe67&A??<`Y{h! zBJ1l!0M^nuWIs~`(sP9qe0d}=!fRoE-}rNX`RLJKr2l%;CcL5F-uvkm`zb;%Oh1tDf|M!4^dZ5t>wXuO&0LJV zPLbFpiAD}7umo*7($(om)MX-`U>2{>M4~Yp35F~rI%gumB@0PZSf&V;hO*dVoL;m6 zwUerlZiq#aE*WVuW`!lF&{&G&2n0!HFpvtib?HxqF`ri=+~1z(A-ZN0@VH4f z5w<*Pm%hu7PaZ%Ph`w~p+L4Ys1<^VF z1YkdWLV5eB{0Y1P0xbDhA3FAt%nKjOeFZ4n5@cvHPfTj`rgXsEnZ@Nz(I%Y-hK;s&WpvYtdN2kGB;S8xE z2==66c>t9?t9qW}%gyWrO&fNlNG3R+C$kb_0xU0&M&Fk(dYT~r2|Zt5dTy;(80wFo z#M!2^XlgiygL`-2?CBF2SX_)t7n*Uh;UxC&+l>SJcVYL=?YMFC8rE*!gbUX@;1!uf zK+Qr-dOn7ZnTnC)r=nuX5@?JXs7aNYOa{2SyAn|KP^lDHvZM+tSFXZ|Q)dO=(hj+_4sWMkY6~Yoo1IY+}3Ie1mkRTX9mAoDx75VVg82Vk%w%C_rv+;VY z5{~H@n?;@STBcI=gyfY2g=Y$UV+*ip?`PJ5~`0q+3ezS7rJI5Gy|7d;a1$!<6%|{dVb6A?=&y=C^5lKaT&^$_n3|J^K!H*?zrlopAh5nVI;SDixM= z%lUs@R`#Qnh@T?#!t?_PpLWCa{=If|+`EganNEaLX8h>&9p_YoaNC5-w?z(5$CCbWXF5&ez7` z3deNb+iMc6*sf|ba8nhHMpXvf2%t8kU|IF>s9hdRB=IB_Y04pxW)Ua}tX>vyvicm;x`<09pEH!@^lKTxsYQb=17L7(y z-cUrR6(Kk#hg4*LL?jGASX@4WVluE`=_*vrUx*X+2hn)!IF6F7T(KVW7F0v3@`9b% z8N2tK#LoH?7(Q`6J`sBp#2KcZ=p)u+S@l+&K642-@7#mh=!Q{~W}$4_5=iJ>+EYb` zmqFvfM0PwExZ8wsC+}1?zkehaSdJrk~K2*7|)rG-U>4ubyd@QZ3!r{HO zXsF+TjjIpwjcq$NA}KQ$L&qA35_<0lC_It`Ckhgtiselp z6LdNPYLl~KB!&R6D}(pyadxP7^we2Gw(kH1qmSd zb4m){JbU)TF@oY>En0*xUcGuJ|M!Ov3;F-;lTYv^Dg570pN`+no{itES%ZJ{^?eH# zi!m@Q=YG}I^)~&t%a-Bi1l68-f6V@N(4e>H|EsO7kj84-lGfAy#nJJdbN`%{_7{09 z$9}bayKw(sZ{GYijXw*=4AcJ>6NA5xj(!KIzuLC#ZQieM-TI4betY@y+q9ncQv`Z~ z-tZxWmru-nruVzrapztq=FC}&uz)NS>vK_{%R;^`4gGYf=x4|z%RxU|kz&oGV|?9w0%HLwSGF8J z-x!N5Ln>^kP_pK}P*bKbI+sW3@&F=hx)1k-3eF-3qz(j72hUQ9$-GM`y;OjxEdf*j zsQ}fUFr|WzJu11R!oek(z>q*nD*?JNQX<}2kh6P0_e}KBClE;ENJWNYc=h;)DcM!Kb?qO?9Eq3hMhr0bouzTNO?5aD2u7{su>8g!bvT6gW zH*6!@j`@qLaqad4Y}~RNHQNs0_=!u{uz3$=&ac9y_UqWYyN*D01Q*X-z~Mv3v3m6; zQfQaq;S&kD(gj_2pWs$!7pcBIuySyNjogP6vj?oiTC8Lz`K{M*|Na96hKA$T-G{hy z|26bp$-)|=_HLxUJ?Q)6wLyhxFRV;6g%Qs@sEhlhZB2Pp3CX}GT)_|qVMW7Q9R@3@ zJM2Unj2k`zrwF92r}kjm+C{Lpv4&JE!H6LPaHM_<&Ys$dGpG09@ZsHvPtAskK&m9g zD|gOLtx2Bk|N9NA+P z0a5N<1UXfz6!be&c=v7!)gCQ@0R2LjQuG+{Vh;`Sz9Zl{q4}9e{oH|pRiAP zf6I!zhe9Tlcw+zn>>f!(K~()I0zGYS_z=QpPulVL;SD?{WqR-KZA@Oc2Fl=KCu3*REg3wq1Mi{MBph-d&3a5AWg^zxE9@$Julf$@{d@#@Q8;P9~qeEs#;_|xD05#N6IJ<29c z!^3AU38wq;i*LWfi>D89x9c`Rdmmb^UPowXEJR`jYIp9&&6{^HX3SLBijA-*klHE< zbW$A#m5xNm?Jm?GI0B8%4Qn>+!p3d&aC8oa+A{`9Pxg}=N$)ES4x~nTIWz}u>Lrk} z2P$FdHA>?q-aaaVs4fyVq|n(3g|*BBVz~x6DG}JUVgl+{jKJc_1SES~*x8CPpkEs5 zHqFPe-HUK=&vG2zzX`c{`4G|ju%qj--(!g}nw}*Bu0ApF4~~OpKnT>%&QR)&g0Eh+ zvk#n{-4PfbfmN&5V)D$nF#1PB;h6-PR~|%O1UoVYD|;wXQYA|1OG=do6b100B2t$G zODQSN_W>#Pp=Y6e1}XcB=8@<^b8mM(OI~|Yz+$?lgj9S$JXJi0jzU;ke?$(P3QhcA z#PuJAvu94@amO{h=rlWRcNJrtQdbkV}<}d%lUuo-~XNKS*)kBWl;TFpFTqR-j-Y~oVgjcb zn%&zBRoa#W(0&gSah^bqhrVO7;E@y$raWWFk_eaCzuG5E9ok zEZck#ufP2zu6K6gX4gGDc=ZO(RM>I>tu#hJ=NUzXw=d)_AutA~LFt_inJ_4c3S#$E zQnoP=xy3+BO5To?8vAv%(?>$23x=adjNntZuQ1>!7{)+SXL1*Oq%cC_5{8)U0l4${ z8J>UoDSl3{`|Cga4lk(C+_GaA?mvEtQ>RYi@soS_-S2;m&%bz$@;USH{N)$ey|*4W zZ`{VK*RSy9H{W2=)Y*9P`difQ*@wG#JMlTCe@)k$K6}0Z)7tI3@$AuKJiJGr@zyo0 z->^Y|X+S^(BvO^&%;4*9zC&gfRRp92Q+h^wr3v;jEn;Jn@$Bgf%$rjInL-P9&rrCy z1!F+zIBec|7^`dc2}`A|-+2Q5vGlzfN$HbnG&hm+0^Ygcg}H@+N2E+`^|55}1k*q` zsNFDd@E{ashhTGMF}BXlL)D}L1bDl_jbNA^9e~aAhoYvUl#UO>`lVA48$;hM_ZREp zA>z^Iu2Gmgdj-~Ss>9}*z1Y5cAF>Ju5KKLwHuyp390V7yFf3oQ1@#9HW8c9e*m2+l zat2SM3QasD9w}tWkh&*Q#emEsfk2xKnRf>LuJXu8fpT{ML)QY)o-ieNir7Cj_rX&h z5y9AUyeCX~0d#-__CpT8JW=PbgWW9N}m zI+Y-qCX9Z~DxHWai>k47^G+OSyo}7^v53qZjNrH|tlzN@HT#cY;FuZcEAvAiMF4!_ z2EZ7a47Gm*H2$eD1t((Z`pww6ua3ZZ3XLZlP_wNTLr0Cp;uY1Xq}uhKJ+(M?{1CS9 z*oKs}Osv~fgPF7DqNZjWcJ8Xhj-9oLPf8;-yB}o}CZlHSR_xuo8#{OJL0Wb{Y}&RH z@rqLPrEosYr+197sk3BkcpP&&H8QR@zs&J{98J+yjf zEMK+)>2&WAqsAjAw-^e!5f?AEVg1G$oIG%2Rw8rXR_Cp>pv>&8`}ZACZntRYS04VKEj=DnwFT1PU@zkss}gbyIS&eo6|~ zPtQj6+#yJe4S{!166`eLLPaIL{|M}^Z=h${frIr&F=y_40f-(Hlmc7xV@% z`fg^R{aQPYpE!=$6_q%4_9}GVF$hd9z_@uUP&RuB22YrUvE_?UR=x~|piGE7Gt6N0 zBw%{>BNh9uIgqlo_okRCcIJiZ38bt*yCKTP`RqJNt$XJ|OqGk+oS~RpQH8?M(-2ua z4XT)8#N>~_g>y}2W!iBCFFP*3ZRTZ|e*L(|=-bz?%|LT^7YhB~E?z98|9bs;VP6>Z zW68^dfh^nIW>J0rLo60R`G-l9g#CZdxQ~_lR^Lzm2Y-KIkdI~m5C0CV8Kw+fAtw9d zz=8Oip+kiVz?&Y=_to9I_-_#r!a3g`I`qynTZ{)CS+4tieZ4TC$+FLC(_)r1OCR#z z3>)?~?S1>Jg$sq4`;a;B?-nc&_PI~ka^IgK(9`sW4pfW%inD4=~CuA)!WfRkRjuB%aBRI=>1sYbR-DZKQERfVH zJIHtMkG=*jfb)bw8$1${N6A`q|EL9s6pJWkmxdNq%0T@wnEv2H_&u-^OtrqrxYqeh zSh3^DlgFs7-Hooh572z26*sPv^84&_96fRZZEZIx&uKjV^fj(rzl)lEjTkev0+-r5 z(DCFcuHL+f6Q|GO%%wJ*zI+w?s4%#Cy$y#NPvCU(RoJOK(O2#d2Ynng0h!PQr&7V1 z02@-g2A?2InlT-7=FP_JS+g)=WEqqi6Ldy5IHXiKOueIyg3*%b{sS&SD4(r;pO3r@@dntdBYm4T(uN& z2?+!k7lehyVf2^@bX^TX!y}>5n&9N*3bm6nZ5yDX`>E6#xVgGex)T;uF2VHj1#r?h zqoea7#*UjvFyDnsEthfU!4nJ~H;>dJ!_++Alou_qz|_u}o4(DCaNx)pVRasM z1Gr$tTGSssj)sOtJbU~EqeqTJN@@~9g8dNg>xLMA4@A-S;L>88Za9J8{nf8AZ1_+- zc>0_w8->_;r~yaLT*B!qZFunF6&lW7#EpB8F|%r;(3j5BqS!>9^m*PhR-C+&k$EXV zGfY{T3ZSKQOUy8}_sW6DH66uc=VDCxTm&TKKp#^Cb?hL-7L3HD3+M3o4lluW1)tuz z^wt9s!}Ob;Fy+F%8w9MXzP)rw7&!BXi4%pizw6ge*#Bcu5&qH3OBezB_FMw7r7x0= zN6j+aEc*;-&c}UOPl&%KfeXEizI##wztct4w*Y(2pJC=3*W=#j3GqIuC|= z`^-Izn_he7`%`xIJNxh3JLiA?IexiomyrHreWu(r%-a^2@?fUkX5QZLzZ@(ueb@u0 z$_N4#!!&?kO6I^#w>`|BVJSfM$6(3|*4(^n0V?;S%Ke8xCiI<}`%k6p-#4I?pvvo{ zvdSC?E9X2xovH#$p$Hf#jIecZ=YbvF&9h|ORLg*r()DF@Z|=9{zEXQHf+g}| zUU!w(U$wxLjX}%al$=AdaqH15v~rW_=WlTS;#E9-_6p6-ZFuzPFqZx@ zwp>TUsne)hu@Z+)p2pfOJ4lsXz{96cgk|f_T{w>mRES-@-ioKsAK>7Tz1VYrKy&>X z?3B*vBlU-^I)OlvN}neMcBTY~ox@j2Vfk((Q@Y7M-tzSgJ%2DbcK)0@#bh5G$0B%GJV3FjA>P7y&D#G?_v{N>mDa zdwWzaUWVzj&CR`+==-PQ7sn2>(%yg}V@9EFe;wvd8;0ugd~BMVg)J2Y zSYJ5^Wy5pP(taCGZV`}ZJh853JN8lD{dIeBqpcP5X3xOzVFOW^6NREA9~38gVn9YP z=FA*LfL@8`Pwr!E*)Vk7>%{nplhNLB4+Dpe#DLPFXuov_N9cVwo;yz!p=QY3(;#st zg~`7`5Bfar=GGE6VOwavWrfNk%DI`BKuSvWeVE#Fzq(g0L@wzVF?|Ud+iqb0nO00$ zQxA0T$QxA(Oe!5oMgU$K6n|XhJ@+7`Hb?WW4|D(^r z1EAi&?>B92KbqHKe?4~WTeGCSe+>&vS(UT${LR|6!eApyeug*?-m>g-vo8bnrwDY% z-tZv=p_%u=4Lssz-j16BOl6^ix?wt!z{x;0D^fNAn%(fUK$K&Ks(IUNJ)tTllMn#e zr0gu8K}y>)N@u8w2y#|j0Fw$(1W|ebkHjT4>dABTSb>(l15*a1091-C+ZKpg`bBvm zb3qAHY&qAGhntJJ5A)We&vCo!G4>xifrH1-c=7^Q+dFZx z=`vn^{uL%opNZwGSEKIWA*|l836EcVikqExagS8dsk7&?d*5C>dioH@8jhj0{T5o< z?!r#y32Rj-Z1hR6Hl_y%m|F1G6@r=Oea7(LFuH0 zj1)*%SSZ%5TaDa2QpS26fl>{hfN&&d<-tlKA@DlFo&f70lhS?IWRNSx^eiHRwG=iY z2^KD0g$dIa!B*;uK_jPQ|4~v?FTcgnb1m3^u^r25Pm}t}5a!?tiwHQ=whMh$_C`fe z{TWY(F~z{%ITjzOg6aE+f*~Xa14hgsg?JkK8_r?Pwta|5Elc`x@bQ3?cRVLYs;}=Rw33; z&BDr=h1j*F5(n$H;_0JKg7+lc?RtQ*$T%w<}f%`#fKj`(}Cj9|8m4Ifsp>*zhs7f6?iLQM&&S5b!qb z$IPNEEoOn~|B4BffkfhLDLdjKx*zQHRrMPms*smh>aj;QI&#`I+c*IBL$vTV&j%a;2a3YP;R#6 zCD%xi68vNYUnv36qAV?->}h;mi|VuhQ-C!Oa-!IBt|bqHTJN8P&ZnQFksw%8yBj0N zPD5OJ4lcJ{!^KOaIv+j24JxpB&`Qg-8@SNig4=gHslaW=!K24j=&^> zY9M{eu#^Y!<@Mbp)-0Q zBr*Zkq;~B@YJ#R3BC55^WD=;9q)th}N>z>!Db=u(I|*K`G78J!pbmoE6b|q3Y*ekS z!>pCH2*?-;-_+3pJgwM+lv_5esM26ZpH&z{#_k_w;jq?66Kvz~GgSyF*93^%lcDfV zLs0rKMD-gDuY`e6(*BI)J2AatIks-wfSo(mVdw6x*tV+%^H)@3$B7oG{L>&Zg<`_& zN~~DFj^14vMvNMY`Ew`Y^obgrKeQBkmK5W_(gE19q!cIWmf*yZZD?$)rwY*&oVs)s z(dqrMV$&X+YwN<%vu!wV@-l(?5lp>hS6so`c8fIb?(Q1g9fE740fIXO53Y^7y9aGT zkl>ckxD(txxVw|L_ukJL<9u5`pvJ1IyRK`_$tH1zHcouDi&=N6xI+>W+11rS-RM~b6EPVnYU^}7f=~ZV=cZ(k+|Ktu2J{2L% zzRz!bdT?`-dDSN%aA_qOB>&gR75GLP%xlrV+FpXLE#XW;-%k+ofl8uZP#-Mg_E4K_ zbEIu;IfN6OEuy>BVjPx`_wC>Op#0K4PN%7a&*l9FVfN1*E3=z!0|cW<>s^1tYok-> zKJxINt9vUKgS7+YL?@v#umVo?4Y@*+2j=Ll;xpn2*2_8!0gTfI5e_!=y0PRo9)jSnC+dl7~>ywT@Q-2emR)NZTL! zyfct~Fz&TA4T^gknzT6C@H4(>i+e+Q*c})Q0}<~t*&%5*3Eb;dx4Jv)ws*JkJGCaX7= z1C4F8q02#_rPeg&YFB<++izh+d&vC!)xOG*2P-a%y?3ib*6m`OZq8{ll0ju+)O+HX zfLN`^`O9y3mw$F}6>MN2#%Vv|l1hGZes0WGGFMyYi>8RQj(K>&D9J)uv97ap{bCLg zt2fu5gXxbl=b6Y6`lP38z=-L^-j1L6Mq1XPY#65vqod-55+2BMvDD1ucw1FUp^Bs! z8QMH^D}2m%?XG13B1u86?h|37*+`q0=EPi95_)wTVF@P>7B_>kWi=0$EAjl%%ETB< z2cAMCxGCv8#AJf!19Ml6T%}GtnUndE`?8|bdin`r1buEz?!=fniGw-0^D6z%t%ye-nIzpKGC>2RAZ^f!470_%Im-Qug zPn&D7!ur=$D2q4vR4?D98wN-96Up`cKkS%rF?8Y$+r5YPC&I>_rpiyx2L3BWX=xFU zn_)*qc(~z@F7k=^7L?*IL$3kmc?lFs28ei{3JZ`pJ|+IMJ^MYj_xRbj{ZcHG(Js!7 zssW)ZGgMJb>ifaXPw3RPuu3ohd3&HwPpoZ`v*%WVWtJswLHZ-t9wU$&3^aE@?`tB< zM^}pkmw(EVUeW%M+X`h$b$^i7Hh{lFI&^b75QYi-x(}CikP!>e5BQ{myoWZ?L?@b*v9OFbTNdHyY1xglV*ykba7{H)wQVfOxR{dVAM5 zP`t{I_08t-5UH5V4};JR?(QvanjhufW%D=+?6X((ti?tUtB*d|EUG+)TlGjEVL9e7 zfo)w3VhV85@}snNZE0!BVFcX04I0LznIsKFpJr??WvPaw0?N>FU*T5Cc8)ygdvl4{ zD!;Iq01DE*O>G-z5fQ8Bl4BsbcI;^{mWAwa8L?9A-)`8fg7A^PDHDW8Bx)H{CHBZv zYU)(=*@>cNtSIUn^=Y0FCSq)GFa0eDX?Er|Fh?K4RRa(TN0yAT5RWwlwPlME3&ss? zDa!{NE2~3hY2dFcG&x0P``iS@@hM1Bd<@bf6v7a{SxTXZASLxtKA-BA)qkIZ1?h@B zmjd?`xWBON9_HZIXYZh^i8*z-o6Y}_B1x`y4-5LQTVj{?svA*s!r6F zbDP!ajkYSbIlB`(Wg+(AF3>x`DOg=Ckcld9Z{y#}`o-w|!+QNI6vH|QU*(gWZe29N zLkvEUVsV~q5lY$$j1q>;SGch0ou zXjHL!X;xe4j2#>+rLhQozA%e~Vl=LKoG7w8?BF3y_}5aP3a+8_1gRB_(ZWkU_&F!c zAe+6>!1A5*rBG^zp+x+S7ja)|oTUD}fnSm{S|yI-k>lSb%L?BVN6OINlyQL-7N$V( zuYq2CV&~&M-x9I9bcO3{{zt>!uf&N~`;I*H6TUv17Wso)HjO=*Z&$Hzh}5+{0-%{l zT55Y_T6ad;FMm|a(20|h9|L>8+_&{8*RB5ntU6Yc0FgEZ1ysP%p@4JIFM!5 ztwr-YI@Vhc!8Wb=L}Q2^H?-JbW!8WpGtHtb8wtE;-VJ^)5;`?2AqZoOGvdS5j;?># zD2M}iX>3|UR*09bl=%T-ITFP0TFYEd^u+rtXHE$lB+sgOg}^ zjZLoqxSOsGlgkGYIy;PFR50bkWzK7Yq@TxGvYL{AJ2>zs*O|FH^q|s-m~B2J>1chJ z6;G;qo2J3|Nbp(TMH&7B-;`@p$eabCnW34(^0_^ns!~pD)iDbg5BW z3rbomRNvw#_2tlZXiK`w67|}0iNe5pz2edQ$0_)5HoRImF(9TJQ8#uZo^UZG)uOt0 zv@AJFnZtfyl+K6c`LpcJYnqlOA@A33dwXAhO196=3wuxXYgXfw--v4hFxianVFsQa zJFRS=@|}+wtzVdkh#;1@Si{dOaO=(g+Z_ZzM;Kz~9f?s7PzXUDa)oR-7^RoNb5yvj`R6U260AARyJWw- zXNpXIyN%u1FLjiG*>2029-t9hPPwcj;$~txzmN_}^0nuK7ae3$ z1ov(gD=|jze@i0MB~{FcRcx>~=H0>*L^dBO#Yy9*m~Pj`$q-J25knk70GvV^HF>I0 zg&Fpu$0#G_-tn;WJ|X@)1j^ATN-3&x%Y1vGqiumv%8^aUS6Cb&PP|Otj-Dh>ddwe5 z7r?=3qRN>Rh_96-cN50LPL;b*ECRGk5V&&$+EmI#^Py<6?v~J--O=a{OL+Ru=lvSh zG!TvKNi23aBc>Ocwq?Sn8Uxu&#%_Gh|3mZ~qmBQJt@-6ProMa>ZpdMX{*=b2w)G~Y zbO}w_9wr~zP~EdIc5)G0=gyOg4t99}8!3&GR36l+gok7c*PLPjpHo<oM!lSJ{%HJI3a-Ug4$S@FhTwmzH~yr89`2GA$(6P0A@Lt6 zezww$b+==szK|@Bz*C(pGqL#CAD4(Nv%^^K`j!*k4QU=oD|cCpt=@1vA)65*p`O+~ zd=Zf@n0=253*)*Rb;l}P=q*eX!s=A~YuhOH5{!nyU!sEeSNATro$fRfsI6qKyIlSRww3A_P7xT#x-SCj`=N^s4V} zu4w8}j*6VBkmWzml`^|oa4|->Y6sSh3OtH%)LloyW8AGggr3e}#1~$u5$a2R! zp~Kpw3&8eO(E@4F`Za-mvU?KD89ruwq4q-M8Nve=_@8alMR58kc8{K|)ZKc8=?-(` z4?)~OD$uq%#B-e*ou&=l>bJ8d4;Sm?kS0HS@H1 zEBXY{MM?oERZVBa@>}#@s}lwl${wFZu0Sv&_2p9)x{SzNpIPq1q6;^3)yBp~2hiSX z1(bsomyOa@=yguNj^bms)8M;n6YJEbxVk5WrYWH71gzo1wsVHhIdka@x;APBA?z)- z$@ffS12QJ5)CXY>jb9Nwc%G$d_@uwwMmBm2@o_>lJ0qoK7d@}HA|Q0s7MtU1tQO-T z{mJqfCGO}~lp%j};1%l7 z)76YZCPclrx31!db$=mNZv`oGklIEbeTfAB2QqDxEfGLefgVSdCvjcWVCq#zYRP?` z_1Z9RNz5vyoRuZ!AFRXPmsk|qO?#)>O3Wti9Q*b*o)hdAUpK(Ej=XviT2smWXs~^) zL#kIMvyyb1^WIW@OmTqaB$g2Q68_Y9mv8H+wcd4&Q715alV3Pkn(q6Ien52oga;-4 z{CCJCZXUhSj|Z$wqFn342Ud(~dch8d#Um#ZW~V9>z#LD^>MeZ|%fSL`6ybu7scAmI z&us)#lf%U+mf$9{B-zSQ)~{}|BCwFG_jz3@VVPkV!{1@GWW^HJK*Y>!q}qp#JJ51&9>HL zsC|Jk&etBc1F0BDUPX)W6@iM}Z}CL$3k;Cl zbo8m#TX)qSU$}*@K=%XRW^&+1qQggo&$P9~rPCIu(rnB8prNmp^v>BbZtM7RZd_+k zC2CYLgg{sQJ1skYxo;Ude|0|-*Sd8q1k~iD>+`~%SBG9}`jJWRlI~e{svj*LKJvq@ z=zbB~W1@pGVQdq0e4Va{lgi~&J;XcvjxwY$3Ij)Vb^>=5vqpjXz`TM5QQ)D1q)iXS z!UWWyGDb(Dozz`}_Voas{=hsDYjy}9G8;+RE{m@kQEC5h9B?DEmUHWxzMa-`8jsWnP_~uqoCzRs)N(gFCsFpIrG^` zcqn?E8g`Vt@yn_|vFKqww7&^hRX;eB@PvCw;@|1HVw@|2qJHSqpwu*klpHAbnHun-bkrcj#&s(r-TM<{_ z))^nZdbl0V5#&4CL#799PQ|~H<<`ppD|V;7j%X#$+Ey@T2_X`{7v;IW4CzC+6Q;*R z(pOVHFaF`cWXXMsqYpI-zqeoRC3@a_J9N*3!6_Y9MG#Q#>y+5PB!el&lYf8wjQ{;# znQ3fDvL`*`=x+pB2`U+??=W)o@;1aM8xzNj6@BOG@Sj(=MvOkqCmbI)7ZY;hK{R?K zE6vbUgmwj79yEomJkwWF?E_AEC_R=~z=l;mW1{Eq=Mk}h1AAl=WfYF}F1ODkGdc-3 zX*oU?nYf-JnRpPcd{SOCj^&W$V>XZShrTMedi;vxTe)5gr>6y!fThD$vRxMF;X_3g<-QL$q|E#sey^+v6`ymuRpN;lVQ#%5?RFL7%<3ja)jM-o^i0SaWdMHq{V z$5RFKn3rOLG9@;hL1(BS@RHPV#wi{JtnP%`U=XpeIpw)za0J8mMe~gv>nej5RJ5$L zAJv2TfW4> zi6J;C!KC8kyZNc@$E&Jheju1`=1@p93iH)=Ey0?OuV7p9OVk2$G|olH9Px`9tzI_Gq1cv99=fS zUJiN`%IS!DK?cn|=1{X-WDH#|uMrtd2AYp*sOy92S5&>}d43$#O-!1?nNN37IIOnloBiXRH2TgCvhlLB3BP!EYZo5YD--}gz!$F38RUp{}( zX8+~gYlr^_K^1EL9Q|IuX8XLg@mcl93i{VMMRSWbHsQf z6_mnLU$;%0nBN{hsIusKEW-vKus7)TWjfBAEZyHScUsYonlSR-c0RxZ$oESf>|=lp zu^b!V^k{|2`&py=6J0FHj7TKTEzyuf7&E{$neH8__XPOgsWX7N;WtXtL-OcgI)WO* z`*+!hAId6!=449*q~wpBsEmZSEFF=SM#yQl`IuOXN33*&RGLIs>+i6^{Ex%Z;Yp_- zlO5wVNsNmtKnBXb&}eaSMW6!IQ|KL)k$%mlR<-VrO{TcF%qoLS4z3sYc~FGDq=nG8 zK%69zSkr|pk%&&N=U8U84y5r?iK-JpNdU~1h>w(X5ra zn_p{y^rh%$8r_u|uw;RTq`G2V(;t4rm-q{$LPFwm9UVBE2zl># zYx8R+kd4Ibn>T7r&d-7Wm+XqpP9dipRJAp{$wrMSUj*exBW=fGIZe{te#{XIm!Q(e9*-+}pecTjPd`;~0;rkSr*fvU z6Fb-=d$9&I#G5$|sVtKyHoKdG8RLr&BBo1icMSTJs_CC(K3-^nc|R2GD`M+l%gr-B zpWCk*(pEm$VLAGvq&raLGZ!r!q9$y}t)?fbo>xJb1TY`NuVbv0Ve8R#bAT8uIlWpc z*bCSJEWgtbE2r`yaKN8D-AwqCq1Y#IG`!)`r?`mCti+v4_WIMdsh7%v#tmD9$X<#N z){OB51{J#n?@Q|FR22BNVRorA6zz5m%y`(ND&uw(xwFMY8J4q`jV?w~R z-@}A|-wREG?(1{x+|faq>L!#j^?_>h=)Lkj5{v)8tvBe(ecb**S?Vj;$L#?4TS7M; z#6AUf*)GwHaC~=V{c)P%^r1FMmN6Ky*sEB^&S(ThXhyCj2!s9BHdeiCdUJ+ zKyLA}7-hn{u3ugr`IALG5>dfH@NaMv2E)&(f0bihL z%GY-_x8()s#IS7uDq3FJ#zW$EDo6F8{Q0Zt!{72RqHvvSTPUIkAJi)7GFs8t7B4~) z#;F93821^YruVPq}rAX1qthppoo_a#lv%6zp%CVw~pnx}I`96ZO!T9NV zUL33CK1_%}jTz#Mf*yo;0}Gg?DaTl5?))*LzGHN>`FnD9E~}8P-Ip%|Tad5@`&mZg zc6WrB7$u+QTjA@Qmt82{eW~LsnX*b$@!6o-BVsr$J1eG<_i0bd=hb?rJ<@n$ear|J z+>Rb6bQaU7$Iw}`It`h!B|QCRrD07uY`O7TEQDm@H1qNUi8D_zQ+E5{%yvYaxr>H)%zHzY*gqvS5o-n1kbptJFiv8<=< zXq=vfFD2Gms|^WLnNE!sp3|lFNY_SsL%G|pv^2EYwVS{&YsZ#k;9W#UtWF+djtLEl zw$cd;lN>+`f%&V>yNC=^USwjX*0kKOF|#F@qD=? zjw4yHlz-~I$k3tDMjS*i+@II)`+kQ`OiZw!t6$AHzRLgmW^T~w22X$c>j#);UcXF= z%1c#^D_nq0F z+R2-d5=-MyV+b4_tLlBio@En2eUBt)ggf#IOf8EGK-hhhnD{Lv#*FX9^Lbl4qi_0t z%uD~+h+@lVt;$sKSqc6sGk}o^bP^p7F`xp5kWxdH;;;B2Yy`Co5vB6*!Ux*lx69^b z%H7Lu$iaW;t8md70E$R409v@p(GjKLI!#fT^Fu|4XjE5G)?$iNlu;l}Qkb0Tl+t1r z-l=a9HCxGnHd!||c@BDvv24USA?V2FHp4H4l`h#1_m6@`{q_-khYzGA6uL3FTVm%z zxpzxSCi^FdloEcCn_g=};{WJht8J(z3nh|TCiVY3}O#p6!}!G!zE{@ z#?Cut?czf`&m#8@vx+#_qx3$1PAD#>{=2tle!kYul@ni8We^eq6Fgohj%GO+ADNZK zM5vitY6x#jB>4B?A}TH`?~i8%&eKQuk_Xg?abZMd6WVbG0$lAxm|4OvJTq2emy9uU zd>Uj*xVg1w@ox3}{b;j>r{Pn}7&^|^(A8Q+ci4$6(3f6Qw+7FOM0J|tZ;{hY2KM;? ztSu~Sqod)Ez*faLlypVbs|7P=vm#_0#-!^=bGMQjNR1ATrW;WhSo3g^lsTbmB7s4y zLS62OuN-E=MSDV(an`KQ-G5#xx?VfA{I94yYEl;P#twf}Zcg zzKCL(pPusniQJ=cd9-RW5l*u8ZYyfig{H&izN!BX@+^HRf;OM#pl4DndIPiPL-B0o zK4`L|Z(B;LnWhm>j1+_D^^P?lE=9nMaI!^mDCfS?pvzoxg(@Io=BKYgOAuAXxM|E; zlt$@(4|mN*69GyL7({DkIdD`q4Ked1MD=Y>(_`K;&{|o+c@57{v65kDT4JHlO*dte z3e7uw4EU884Xd=ZE0(D4K#a_6*o}!A0VO`td?4H3>fz!)NMrd6#pd&g{JcCZQ zq)GlMtSK=j{v>3Y*7_9CK8oVbg!gTS_wZ8z^lhi!>5LHsW`d<7cYDo9&rih1iN4g>%frDXi9Lm7xJ(+0NI$nf$wx*C6rq(nZ&NO! z(Vd0?+Jt# z_Z)9e+P-VbtXV4k=8D@SPq$Z-1nK5;*xwOx5B3eAv^Iqqctiq!Jt*qHD%Q_^?QN&YtN9*!Xu)=7@h+PYHw3j^qeSUA(nI7(J4a80{N8_*4u{ zK83ArNTcQe;~wQA!MSD~Byryt`;_;?ezAI05@C^nuzsC`DQ8w`0C2>eC#(kI$ zz9hb-;wEuixabYrRckvZ4AnnrEpa-PGyeU68o334b7Kw_LWU^4arx~yg@+IHP0Ye; zHQ;1(`LegnIrUc`>t-t`d!FSsFSVKD3E<8xelbXZ4)ry=Z4mbL$051=-^2G7GC4no zmycC*S?==zf81y`e!*k?zE4N@0pqliC`&~8jQow{Vfwf`37VdVuh_L33-lqv_>E zM5X?Eo7g-4kqsM{fT?C}XZHZ*H?<2O3W1t~4grlw*G%C|09s$&k5k%Bi3SetD3@mA674=RDv7DrB9+_E z0fBrS`t((bql$W6Er3XJKbbA@6$f)pFgbNS!6VD4{`WS%jSh!`#{sX8{4HL-$feBY zLYd|Zwx*uE@7hp4L0-F2k5n?Ur|{nVeQp|-MH)Y zOCtvvn=%rJDeUSqoi5AQ05o9CTFf}qZ@{ICYYat2MRCfQk~wZuc$|diZ{)5dc|gkEmy!90pin2In$wCtK*vNQ#Eo^XH1LNpz1VEr)A+X^>=bfY5w~Jz zP`##sUcT80#jtv<5IWEOMc^TzVonGoat!{w! zm;*O769%Q}N6%NAvYd9sg+qAnO^l;8Av>9fMvIdIp^lL7xk<*`$G+YEhq%7(LENRZnhCR@Tr{*@;!y{55OwuJQ4n>tmr<{cl*YqftVsreFVF6*kL?*!JHv&v*)J68vS4xg4T@<*O7g1k%#Hzr3vL=7?Q8&h$F$nMG%qn__xbUY^NxxzkT1EE-f~6 zTz#yhca%ow_#;rW@P*p?`{-y1L?YRYc`&kH zX`(6`5vW{FK7yU%1V!3B1P9jO!~qnSM5GE(iTR6^;Rsu9UG$>4+!>DI5<)-TK+ETkpB--qgI_b9;@t#Imk9{ge`cEvJ+NMy^TRuGdBAGu+2Q zGWSCVlgVN~lUka8FCUGdB~}}CMNjcdtHuoJ)@F9{OxM^8O~JD~U5;G1326w^nQk?<6sdLhPsutlPZK~I z@*W+J`q98AxmfY!{!C^z2l2FKJ^ZZ9sx>ury~7^Q!TYQ)v*3kh8bAl4_RH8xJvZzB z%i`gBIm|8QdyTyr_>Vv6D$jKLPs6TIaC-r(0!y#Qs>5=Lq%Qri(^mk+{q_lQh{SFC zOLag=x?fiW_{R^-z4o}I7&a-cX(az2{7B~hyDVm&(}{lKmL38 zFLJIYuwsg8jgL(mWdBtCMWzT$>&|Bdp@Y70(3s)-d?gk&*@=&O^|zJYpT)A!Fezui zN_>BU%H*YGV7?ajW>oq|fBt5M9v#wHgyob0WWFWM7F*wzVcdIHWBtp{W$oIKqj1a$ zF>%QMTy?2!&pZ(Tt>l-N$&{fA-=1^2-rtAF{J@>7Mkpi{avy(~Cc}_{LMY9DW$qD^ zu@MUd5l;50b)oD0!pz%S-XG74vu4Y*eCwD%MoEZBFh(L%z~Tu8nZrn=y!03zDHP3< z-LvvU5b08j(J;>2e~AuLEP|u*MOJ5%<(4~FLue-HFA{p{)7u7_mkw?l8lgG!6%C!K z*t%Uj69hb6)4bmfZEjiZn)g@s)3UJP#E_sUPAT^tYRO*hoiL?W;+Y0};hA=Ig-w}k z3^kG9;Sk^@Hr>)gy=t_%Ev*+zAeY~PVUuL~Zk>DN&iqAv>ttWrT+hY!b=m1Y5``f9 zr~MhvJKsY59YXw<2&1=f9dJ^rfIOq1DdI%$j;4ZxTaftYQ4G*;C1Z0Ns$#|tXTKTB zilnFGdng;*mDEdy3VspgI%AtDP8vp80CMQcp>sWjo2}He!;yc=cpu{8&tq6$yLCKQ z;SXDY)2_Bs0$a$h>Ip1>c$&+-&(wbln^IvN794uZaAmMIaXtRI&>;dCeI<6vr$w&X zK6Iqb#x?c^4%p#{e%Z3|52V$N9JjGn1~v1-&gaY@b#gWD>W2BTPuXZy0F%&#{07ah zIw%aZwWC6GP z{_p4)gjXcdl|b}a@bd3;;J9fcUUgN8W-?EPk=f`;*7HxKGKh|l72Pja+EE+MNER-X z_C6c);WA~R7bfc9OL}z9yoCIn1}>kEbRx|#eN3vM(?fXo4hpf|N+13DwvO4QRAnM6 zqG4<<%v9tZ(n?sg`$i67!_dHLL~tqDXok)^dqKcag#)+Q?}{ZLW2o7B7R^u4S)N`B z2w{;*MPk+pbyPv%W1~y~VsuA|qEpslYe}D&*&zZXz64 z>qvC8zSd6_{Lcegx=`0dXVfK)DRz|v=7$~@WhII(PHs&Xc=*h?Wp4Q(QV4RIj}JqT zQ7@%oK3U0eeWQirHeciF3VM=iyDw0&{o|WcyXi+VagdjsQV8!TDk!&fIIYa3*1$X6 zNj-3Z69Pr4S*&Jq=!7l-es3W&e|27J{wJhfXb;(r^2ga0cuAefn1P+XZiliASSTk|W}A7J$tUeDXxHtAo5#h+o_{CmyKmAwmul$2$9o}^3nXJNge5laS*u)CG% zS|#e5`|XJ>W%(%2+bJnf!2>6cB2LR@M`)Zr2_w_A=Q}E)&JU^GWj4ExVKz{H->fI~6%z`Nh+G=V+vu)1VNac6?|L}QLN4q@igcV*vinX)?kpBFve$U% zu@N50sl==lRF*_-EL)(H`w=A)Ce~2ZQIi_8mIaf^Xh~+CP?_aW%!e#5A>p zk>HW;!sI63u7UX?{*+{`=RMVTM&Y{Qxw$UXU!+KMuBA>>knmLBs4Yx;p*}pWy)TIq znKE2zVFiwar@q*!G5FOU-i;ryxy3kC;I^zzCBnDG4{1LKQY2~x? ze3w7eX|T}atGp>I<=B*1$uLO#J8vDnkc4TySS#suC8w15hhNH=Nhd^$AnLuiyZ61w z(&LOK8xFVlK7k=SqKAPC{T!Ai8Qfe?Gr)`k-Zs-fpd%=r*Qq~W4@PHA6U<)=Ft>sc zZE(>gAZXH&O8w^P?F}jEi_#SH1VEO_ME-FR2Zqrs5>xAo;5bc`2EKtn+=1!{{fY9x z1V+0qS@TOY5M)(_xC-hKlv0jAD6G~}bZ~vX1!JdOQ}9`F5nQrW)iVv4Yp`Y&PMh>o z=8)qQC5J~PQPK!VAU<43_8iZja9LdIG%XMGf} zc2|k64)3i&$GTm9E7BQ7{*TWS+NZ1SBzK(x+xr>2ZQegZPw7RB$fl?L2rDtqq~Fd- z#kzyZK2WYhW@`mJKT9TcF6J_C+OPdyiH_3O*q%;kw3BG1a{NBVZFk8fr#(=rix-QI zgqNO3d3lc}tz`}i?RP7}b->_3+m7iT!Q5+c`xYD-e_Hah1n8=O#n%4^1Iu7L!^+HMHhThuE zim#2ea99)ycW6`b_z0lv-XerDG3yuwLysc=DNZ{7Jg9Dyvu!mDjIF%Es|oS8B!PgL?*{@(7P-Ohr%N4bAObT zE#OU(PTBAW(Yhz&KrM2x*v^3Do?Hx;2rKyUN&Z`tC;kkNdxOK7&FK#pDJus~&y7&z zI1R|$@{MMv?FVVyFi@||oYQKoWkLcoEM)Cu8(lB5+q$g1B?3dB58P-n40jfjbcL}k`CyYFHCfH)skJEoFv4m397 zIf;Q$#|`xk!c8JXRpiaXqvugmCV`>Je>BB{-*Jhi_;>$aF|Peuj>g2LKPo~YTi*HgVba1Ojad8Cw2@8mLO zn>k2rhu{!@62MGjN}|i=l>PlG^Y?(rd_DJ0$h|Byec$9%)CV`Og`#JqQD4c;q-Wvt z(AFU#ieshb(uvGg*(IJ?hu*$)Ml!zDU&5{N0h{L_B5FQXOa%>r63<6Fh%a294tP2Z zRTp(MokBQz&t3W8h_g%)r5as5vdVCm{x+lv) zwLpSomoc%#b`u1iwb}Bq#6v_U1-)pP_N;GGy+xrz1`?4j-IHjtpP~P5fmp4x?^*vpee`DFdW?&NWwzH=<5ZCu23QGAl_8Wa+{Pqk6I&6aSdcmb zuL3wgAA?TBvwlB2)-0PuRW&&UyvP0St-soHbw`m|Zff^YqW&ZkqT?^u3*{mX78}Uf z5PtJJp%e>v;{SP#M90BFRg~gq)aZsMuyERw{t2z*1|@Qk4coFJ!?G{2plxn})u(>B z(OVK)caMwYwdFRu^|6DeExtvS-l%U_`t=Vvu}C7Rg7*NqiVe9UO4Fnr&dUMI?sbRy zAx2Jh0fybE6T$mjT=rk8R$0hxbi9hf?_LWr-z$7xTeZI9yAy<=>mhZ@q5IFBu6HY6 zRC7egP$M$&PpP}!U)jPV6n6H;1ebn&`Cw?|Vllfn+_7X5d;|bW97Y113|jF8>jZFK)zP;6 zXM#|toHbSJ17ujQrxQHN^p1$78{ba3K?lMhPO!eneKrA8!K_m8DgEBEr;li^#^SUW zdaEj^PU`I(B{Boqvs?uU;P0T2 zRYx`|3o^0=vYtPw4;u4g&cBsuyx7J|h*nV#i~1n=&yiYJ7)OetL{n6YAvVjp)Swik z%0QHR*YI$yD(^~4CTgqs=jqgX%+4JWn=y~yDPzl3;-krJGgS~XVI-)H za18x4ip>uiX#4kju~t8#l-Q0hRY$%&bnbOah*oA)D1Q%3`<-Rjk_s&D3ih=k=0D@pn)F#in>C zLr9Z;PSE53P9g6HNmp-qQIAh~NIq|S9!{d3xX(~+9Ptzj1*4Dy_KSBPpDQ-YEUuzB zZ!)wSjrIE(-d#RDO(tG;eZ*$X?-ucnsqWj&tP9k{4%=E76gyz#uuYzc9H>doqdbU* zY-?`XXPw`+6gf}UvOBN8S(-gJLIc_k|8%o`c#Kw8FEnnXmk@?g`N!`>pknHCG}L5B zn>MGlTTY0dr3PXVLKOL@$Zp(7AV}HW6Ml5_2MXM27Cqr|c=d$#lF`x#Ya?m+NZdE= z&G5qn{-j)eug4;s4TL`ABE(1%S7<$kSi>J6-7e6GM4UrWk+}o&g(pD)WbREE8#=v zTEL{F)hW$@|3}(eMYZ)tZ-b>2DK5o5xI>`06WpypaR^r2U5ZmQK?4+uLraSmcMlY| z;uf6ZuEX#DeRDBu&0Ne(E^=;8vd+8Sv-k6Cd7qtr_#$lL0NN?G+HGA5RhS!HN9szI zzE!kqXG|8zlUjr!+bwnA&v8>r*$(qA6<(m}zbzOkbAZDjfNcpQ=^*0f@rKyFpg?{CH5Puha|KHZ=?&P4Ye zyTN#wLDgprH>l0NBxUF3V(E#isY(xZNU=y@Yu83I6Jk9!(=@ zS#11zwTH)}%Q8^l1{0vQ@LS_qb|J2%OQBLDzyt7DbX*EOUkBxSDsMh=J$Fhfj>iq| zuA2D=skR^jHa9iyH>QG-c|sMZPs>GF7iGtV1E{kb%GYo93K2oLwERF~KAXzUj%bb0 zXbnZ>2VguOl*6zqW^#qZJUI_4I3K?} zzcn65E^(H%$AjS*ML3&{bEI+5$Xg-#Lme+SEA=-D%Z|orV%rtdUV|c^nmXK^I0Ux`hh*%8P{obtv@l9dxsuv6hu}xy% z>{39}5)BiQ+D*SCDRA~baF$NoXGh*34*W>PJ*d>l4Z9JEeA_=KdOHR}l9okwTs5Bo zcQ5`o_FRuAXx>{j=SLKGTDp|V9BFAngitwI^vSO;-<#~tz1_OIUVv~0J} z{JZ=I{EZebbAzu6k25x17oW(|9ha1Vf0al@f<-=**;}5k6y8{NV;R4MgQcU(pl9w9 z^T%H)Le8FOd64)+`^0(1{a~oN~ zpyg(LBY~Mgb}@n|8>c&?qB7uC!XM`$7tE!iI4i?91+O|5q&8{}Nl3a+?2)`r=#S3B z={l6dbURvNebeqP%>tqKah@6=a|v9I;aSGtI*(VJ!nervMt2Vxw1!O}{MfV&XO*n? zuct9glU#b1uTWo$QPU1?(#0yE2d{^I+et*fsA2{(&a=H;FnJi-eCz3zWC5?i*1Y>h zVtSPq)6^DaaTz5pcb8nXLdHXn{l6hHBzf4`ia2)i8~2P97QW|n z>L&a>JDX{zd$uVS6At`|1o^?!&!V2UIi^kQ2eWBk(iH31M--#~Y?Um>C`wX_RBB}{ zN8`s%VnP)?nPK+V79L7AcjAz}*B8`sHB;qAyx=>3#|g2p8^QI#FF5kfj;}Hxli$c# zQ|xy_;TJC5i{1RKBPzWb!frRb%w(StEPg{6URYVp+ zy-t+@9m1e6j|ra}tiXp`hKqam*Z2sAK;@P&=FxuJRhIR0w<+Fua7rEyRXCEFT5o41 zbN*ON?5?=uYk%Cl7|1GTZ|B77Iv>ZCh8C~i_z1^%ADg^AF0PC-%}&|?)lY)>xzUt^C@?cUGNWzPQN^9{M; zBn}iKXj8HgemVUUc>2#6i(EAPp`MS|{Ll67WidfB4onI-rgUT82?pwQcPKI~q$Q4s zWDa_bgC9JS5lz8)@xA{{t<1;IRRYD<*e~cRA0twqqaPIt+2KRaGshHxLavmMGds@% zQA%-1iZ4fbI1Dmr4`@wWdMy`{ozHRT7j4(iKARWg`Ld+^c6iJ>{$nQon~Bskm#B{& zpT;!q)~Ar3 zJduN*l!?~`BwZ87@55V;-RHWdCY%Pb0&k9Chz17Bhd>g5yOM$eS}Hj|Sfj%Zs74Z7HLC^HY|J2vyOgVwM0to*!kRZ$4n%&= z8+aCo^_3?Z{H^xn*o}|J_d++2HyAZ4@g7HZK(&j9V0APznyfaB*C7{JG75{%H`D0+ zW|5*87)MuRL3K7GL_o;vTSO40kt1C*%t|WiB+#D4gN+=O)NgAR-)$?akpFyAy{l0( z`I)}o>gMM7r0;JzDX*Id)5ymNB(PzJh1GZle|k_fbPkJ3!&HIc_L3w1(V11AZKNv` zb{rOb8Cz<~!?n6c2N>4y_V9&=u;amwxf}m$L@KYc7g8AT* znGEYI&VxG;o>RKU2YifZ9V-PJ1x0B9HmH*%z{?sE%n7HojDcdAgE=@Z@_iD%uLXr} zIur%w98Lr?{~o_|DGT5%Hskg&2Swpm2Sz5{2POswJtzFju1{8-jvJgNqLbi4_q~0i zkFDMXx_*;8k1q_Z0Pfz(LccC}yiT(&;-4xC!}hFQkGShTB7VJ8fq%0>2Pvm|5T{(b zyP;OMKkma$srCK$DM1r36*D)Aei0m&#-3r`8LE}JTqyZ)r`EZVn^$;kTNvxuk2ety zs-%0deTj6{fo}tAl@md0`k+wyiJ#AkK#gY!nK91bo{^BhdA+ZI8X)1_&HTpa36__6 zKCknxm|@I*zexP@av3NN--p@+(Vyb`J!m~w!jbx1wYTYGRPPJtN)FkN^ZxE}5C#=GnhkO@C+BC759hvg`%x%ZV?`m9B2lT-m zWarBmsyQvM7vJM{4h&PxyU~G)bW5NfMQ4Vr!>Z3uJg_IV8y7c`PjP&jCONU+3sfI; zlcS&yp1pE%o!4o&rvB{_E%$tljpC8D+3dMuUQvZ9gp`z2NW3u+79KMxP(; zdJg&> zGBIUXfF0kY3}?9Ao_QI!xf5m!IQKvJoxAQv)AIoN`-@eg8hs~{RTIqZd?6eySUoEG z`CjId(+xj+J|hRf&+mjnjwna-I$j|MA@5QcccVPUHJZEPqauFqaFI$Kw@QrWw1n!| zj;*I22?IlNBP3vRJHKAdN(7Um;nEDOAV*ibwx>vk^3b>XM3IJ7P}6IlJ0$(Wck-VfIi$rKGB-X6^h|4lImS>1o5o+Fm1 zW2?Si@r(Lm(8YiKLC#prDkj;j_C(o_^;h0YQ9zr7%XEBzQJaPfx|)Zn&5gwk5%HQR z<87P>jE{Hiy8*_sH`>VTAI@YqdK};!Ew>>%u&ao3Rt>*y20kp^dR>x{>_)?l{8O;1jJ5jfSlv`x=0XNO>RYl2mce*= z3wbPzDXZi>W$IFhVuqR(BwIecw6B1Nk^Gib>*U%$Ol7CeZRUiZVC9BhkddIN+=W4U zyOxkX`72&zMK39O0#|1Q*h1s*4}_Q|q5^>qW|RZ)LBurXVl#S&OL6|T`B6n=jM7Q` z$#bN~Aah$+Ou|->4`cxn$S6k8^8#M&Xi$c>kK(!pyV4lCLBMV3&R=yWLyMWleZy04 zNS7M@-_BL$hL3#BRtzKzD;hK}0!7m@GLb4xbj6hV#C*Y!(Z=#i)|ou8R%CbNF5m(r;{Vp+&TYFQhPB6qGPHX;~J||Ab|+(r1vod|pwYJg;q11|HQn{;sPDppT%t-|_q4)_}=7k?$G2|dI<$s8Jl zO5lc?@`pcjaB30$x-!?m9k2yfesg%o znTgQvUh+lU`6r)%s*Y76TCd~_GAMvMoN}k$*dUbKHML}J!0R@Ad=Q9WBViDaI|9WI zz@Pcj=FpCg{kF46iLi-+d)(q`*XdQ0k%aqH2)?wo#Z~eWN?e2^DDyg2cdzD1TmmFm z<1ARi6_krJcP%}Kd)k95Nek%4g&@Rnj#odA9ArrE^h!kBh%2zf3VzN-c=#oc?ZgTq zt;AdgM7G`zLmGT=wN1qpJVTia;3Cy@-1sUI4&Y8qf?R~CUy5(6;8QN5n#6F2aYL~; zW$RSB65h(us^m+{wTnU^+XhkJS7s}(gjIJz&kIkHMu1xBFmJ9*)n}%MQn9o*M4!k% zsl+PA>73-z5T4f4B1vxb7xJ^G5Ax&4fxgLsa%ygPIWgqQAq*@0{Yk9&EQ-OhVHL7P zBnQW9t6?FkaNl{@adLKsOtPeiLQ9|nlI-)3wPLwefMCwjR z4?GdQmT#^zHVR{$?bBiXMs$$ z_sl2HVynfcICO}reY#TNfC5c{+3L#8b!af@!ZTl>3~(H`B`EYoVHMB9yGv5iHxIoL z^Xalna!@Q5S8~m{^|TVV+5EmF0lX-^^y)_AkmFmM1{Kpz62$*B3_US$)|^e6o69nm zaw;sh!0w3+pmWv~lt&Li7sxdlBRuV*X2_-g`~?!j2We%>9pwK!m>LB()M0@9V}#5x zLeG@8okH(CR zg7sTW6sZ_g#t74`s0LL*Z!G~c8+C&=(kS=zaLqWyRB-a8;=2<0d|F1zTe!stAcR&GMOWYv)o^chBOVa( zZZSZS^qR`uOT8y=a54`3>q4@y(!}X>e@`|dnS;A~hfMH&TOf|;^ql!b!Ex26KFU^r zOvy7H_IZhRA@DcjVm)J65QtjTH6-@bwGlaF;h#$Q;LO}t$BfnioZmB=SvT)>=eW8O zhD%THn%;Mtra1WtC;v%TylkRZR$?L-Fn?FWO+kMGqhcPDdJ$BC{1N!u14*$fN@6dF zk+OP#`!EnB&`I;v3qjr9%l~C(h`tBp4bnSJd`h*mqe~g&OH*Ws1RohEhf|5DVbIsS zWtK^x4NJi3%QX?5__`9%bRW%t`41lJx%~%b&|!hi@BL$QTmqYNp%!yd;AhXm%y6~; zj5~)}JE=-Ko7M82UZ#*e<@h{_;h0Sx7mVfE*wu*LY4#KhXo1JrG+ru zRU)SQI&aoGa+n0=C$r}#lR z99;Ulxcr72uI`|st!a`P|GgUwm}byLFm9GomKzjnrBi8ulp>T63WfaiS#bpR+aFbP z3+Yl^wEP($=Ac>@+Id?E{7-cFJVb~jhHOq+GA<$)r0Z6OMlYpVBgNdpbKPG4DNa?! zF!i@|HH>GfIJEeRV5M3OHZ?XwfF)qPq#}*q7|t;0a0U;ghOj#Q*-gc)k+>!Y*u(F1 zyBUgx_v+kMt|fvOI`9hMMp|c4Hr3LK%n9I+btLY%8hy|6-Y9Mi;juV@Q7klB`Ox^O z;kWaN0y(OfV>z;aJR+2s$Q6qzUcO{&2uh{dUss=x z{<6RwbZ!!mucTa48&Mcqg3RX=@|9#P{tcqGpX)jR4Sj%ypnC2pLr;NDRxu;KGy}dH z6Fw`Gjuuq0z#Y)77_=E3#siq@W6M#k-CGVClvdHX0VHs!#GS~0WPoTR9H8^jor=$5 zOd46Cx92-A*?kG-`8_mJ$zYD{(R=C!XJaPAE54gXQMctC>M`ogt+-O(_3d~+#4S99 z*`l-aY4@xvV0ZbN{zbzD)k;1Dg)@OlF%d`R^{whD;+%=Vj~P0aPJWsd_YNRTUXG|O zO*s_iJ{0~!QX!o?D-CX5p@m(F@vCae<>KD9BQ=~%O}FEPEKqDzQ)um~pq-^-!TOhr za?xS(s6@>3)L%;?{GmIo$z-<}^AiNH?LKWtl-p%xC?x`JTcld@6_aVI<82`DksGGm z9H0}UsiUQrtXz~OQ>0uw19raC;exQ^fAafqD5{l3Bnw^)R4!yl8B7Pc$)_?*(kr$? zhBCozd;EiE{T%uWkvZ~mDvVS;YK-Un0AV_kB4`wA8ox4s8B2<+(zt4-x2OWNoIj2+ zj8pL~BSFcSO7BOhQU;@~u+~IE;gQT@lZjh~9!_88m~kapea}15hcS|DEovnMg$8i- z<`rUrN_M#_M5^wQ93KO&+#Tx~<7+37O1hg!6Z?u_Ktln38y7hE;>$o21Y^8z``F$09uDButF5v7_GgnTqjsG5$?=VoKRPJzp&7@TBOZUwBqj^@d1pr>?$^K(Rh;>aNFDjnk_ zjgppxafZLUF8U;)70+f1>kTuN^G_pv&x0r2i~T8NzHQZ>zr1GBc9x;jnY2ZqTl%zA zTQ@Ux^fyfxhF%QSb(wFu0 zEW9m=G*pz0$K#|I?aiPv{+hiqZir_9xCPM$28<-6tuQ4ID=V3Nk}FZeXIs`G3(@}{ zZnsm41(@=jPA%Q+u(mH_Pf@kcaPh*2IJ%L4|1zm{Ne?5aeo_!AK248Fds6sqt&8YO zQCur|A%AW3AK0cRE9_F=%VXj5876_NtU>+OFt7=mdDfmgz5+s}CEZ?N>0KYFU6NpL zlH*bVuuU`76KmcBw<72FU>w#d9MpvpkrYMb^CZ~(F2Yx#FJRD0RV^X9nu^XiQv)@y^@)b!wgAlb`7hk**tlH-G9WrVNms zESr@6JEc^3ca=s#z%(ia%jcc!3Bpt8lPU#ic7ckdK?O*l0{-3QnbS=Z z$RlzZ@el;Oh{+>QV4m6=2oX)hq#g8@Q%}0QgczgfI;)suY204GFGp^OAzP6tu0p{& z{T-1a&{rdHvV|GWbN@|Y40pV3K=Rb$I;0@r8n?=I6br#1hYy2t2xXx|(1l@x+?)~w zpC|;^kp0i2jxM6EpFs_|&%GV~58;kKL`|W8B*nS#_Abs-jv-_RDiR&Iw-Shk{BuOW zPyvs~n?4A)R? zY0sNLXHAIfQF@q9FhATK&L7>X&*hgVrcHCE=(o-M1`nnktDRrZJjJt@J9N|1{ZbQK zm)tUBU>}iDGbD!C5ku?+;Hq%3*nOz#Luo3=kO{&D;evd^hE0Cc{`tg9^-O2Tp0F=- zmWc|t`4OVZFz+Y^;Y<+H-R@J`VteavL1>n`)7wT!fFuZSWF?4k-9yo?6NQ0mVJ?j< zaDXA_*D+c$PW+0%aqB)ZsQvJc-8(2phP=brgvU?lPPtvUR$wsklkHz(-G0be@=;R5 zfOo-mF4-sB2f_`nj1#L0P-jySod%uu2yMcC$ZIhOj~^;qrKy6JBMZE)JI3I3GBKfI zks?qQ*B^pEBK39sc``C)jn}ksVdFjI2R9KXoFRPI&p@&!@mS~0U1R6!B7SAAWCSjL zc^=7#jFYg1e~Rik<9tbJwz#p0;~K&h_ZQCf`t3Ba1gOg8!IXAkm2e&LsBI;ysR1IM z4dG{VI(EbMqyG1r8KTnCxtA)DZgW^SYz*YyBQ9-wRl}m{AAXpsms_6%V*?_f-~4#pc+DR(~qkEWh%E#VN3GyCMN2kB!^kQqCs1gr)#`RVAtM4}y& z4q!YTSR4Y&ADdIoE7elTD|AmAO7%w8_i#^>BQQ+wG{IMm{HO%f_2*6DK=iTEoM{*9 z%mZP%TZ~5PW9!=a?lp|_><~NF*c!)$Vh(tq3a~Is&i=zxE2v^5Tsg%>7(45qHe}Ks zAKzU|o@MAliC)x^{X4;?R{9gcO!S9BixKx231-;v4OLluOggxp!C^!>e|fO$h5pIt zFsThJ9?WUxP=--vZ9%aZ*#$_QlQ^2#U66xv={N?FPhA4>N$xPJ8R(VczZqtB6#W2x z1gv`c=ca?B?Js!Y`@op^T@-!RCB54A7+k*uA%crz3VhIp#mkAW>j0+t_DWHLT{EFT zv$eEGlgXIq{H`&=%BV#7>e}~nL8h6iKo2fV=GCv>*;8E3N0fr%jkK#OS&t+|DldOw}r1d z359-Tmw#HCCZo=8FN&&w112FtxGmJlCK))m-K?qPtpt?3YYT77v)b8KGiZ=O`H{}q zHB^jQ9ehcUx!f2-dFFSv3DCsTkYJDPj!=Y)-BRkBUU13E!9fKVIU;_>nKu|Og4Fp^ z_d>U$h}zsz;BtJ8VE$mpc~)y~40k{3j7LU3u8RG|5$MS=?E2{wxL`ub z3yXF40*AM1{K(J3(%=`ROAJQ^Wi^LF042cqAq$XZM0`%WwZ`#7dS5-$6jYTB4D+PV zjy&`u*Ii(QsNakwLZpsSZYo=7;7~>q>ogmbd>cdknCp-DT`AW^BsRrz0Lc`a#`Q90 zL%l;bui;S6z|g((VI}Wlz=&0S&c^$^ zo93X|7=p`27 z5a&OHJcCQi&2A}KG1XBv)d896kP}4!pfki!mKdgPrlj*iWG&U9hD^nC zX6U1S^7T)K)pJe=GpuARrXIAsCeB55I1|2xZC4_3~Y8DAr}AOPoL zPWpN*cW9Rj;Iioe^nhl1If)H&_Dc!03?zI?zwn${^+d)Rj3vOZ@2bf}x+P5nF!!22 z`G5qv1I2WeFq?WcecIt)G9{G|aM?(t5~FgYYAGj*N`|034n7w|FwMgche&J$x@Vie zSdvt1S)7-U`^?zQI#{q6M+?LTZAaWH<~30&W!KX?^>7tclvY!)9(dEkR8#ggf8Imt zHeV6=K>sqrnEr_pOB>9}@9;G))Uc&v-Kv|hu(MbK*% zW=MWB(cX7Nke)97tP2AqN?f^2Yzw4Zm}yGM)aI*dT2k|)fsrIqsVGY}x024#<_!9t z<<3T=X0D9h;}HiuZqPtQ=Fp&IiS2j%-e~aQ0~fHVoIG{}YEY|0Zj{^<^{Y}nOjUo1 zHFgFZB+}t8>KDxHCw{Ab-~(`4Rxfg)J!b$alG#=;AN*uKmIZhqe=U_xuT1Ixc(?F% zkZBRFPj?W+i`_J!ULeFpYRGV~-CU()lS^}r!AO0@f_>`H>cf?%Y7I!my}b-!AahXw zE7R~jt^AK8|B0$5Brjq%}w9UaF&|%oILkfnu;M9EjB7+jc=&FrCiKL^s-kq ze^N1YuPDD}aAt&<66=14DsB`pismVA^~3oyo)V&MeqQ)BOZah+==$phLw}ho5f707 zyN2GdJyQ}1k{I`^SgVh%PL9dcg6}eI%0PeJVfGdRMCTOK1JQuzBI=s@f6}u!*zX)? zq^|0h2esy;Mv1Wz&J&0hq=6O71TT)z(Xi%i@P#U5@n2AIea2h4o2BCeK_E{g`6eTZoJr{WATu@CU z31wL*i?Sq;`@X1IXCeCbj9kyqk$wzvDeyhTtD(?!)BB+jraChX_Z|e+{G<^~xt!kh zZYT^5aDFK^N)HuCISHOA!6weQbXR3dvL=%`hD*m%fbdm$niO~1q~W9GevN9nLA6+D z4rYnT3aCsC=qQTVy8C6mS2Nq6&BZl5u*I^zhB>e*dfCT&Qv7|ea{g;iu&Um z3sq9J1f!FjSl%{##t$`|hDis-9D6t~>HBxKhrH+WkfNl8lCm;IkvZO#_8|7J2dz~i zs}hWijFU}1qQiL8*Q zsLGr#2{tyi^Ku5anQ{jI`o>1s!$aUNe7}=5q^FMOM_E^S?n;=_gQARqg!) z<7>LCG;RA*s*wi(0-ik%dhZD$p}Bq67yAFNshHIwMw6x^PpkfUm-3;GflcluI(^AL42s`fcHb$+}&nDa=A#-$lmv)^Pe8W8P)A2Zxawdy{RLN+@&?^q*d*D5ZETe1j>KN}C1-L{TV3Y! z=g&*JA4=Pw?i|!*D$P3jdt(Wk{1x)s=q~)&>dJLW1%7Do`(N(&S%+POYSlX){;eLF zh4huEWs^4u+D|e(j6FZ#UQ@rjy-ZC@YqADTG!QvEJ1;fA98Bu8u&`KqsJ0qtL{^36 zkd0UX^+HEys-^*w8(j54Qxt7?foRL-Fk-pEI)i9BnvnRTYnH z@Ba6Pnwnb3ZR3q#$n}xQQ5j7B)2C0Hqug=y3W?@px#9^)9rs6~zp5c-{Up~%%bP0! zryG4sn??=JZc`FLcl<_4Q5D%0d|luL$_1~xJ`%H59l;yRe+$2NCyR$ghsVB(4p
  • VL>v#P~Q+&SOt6ipM{+4&i{={6RNMzaS>X+ z7B-&;W!Qybvt0+#_`c6=7UO4YO`ob0%}NBnX4#fpye{%On6+4}cS;bwf-H=ECRT~@^S`T1QBa>N7DjpWCi;9TuOerF6(*cAOEQb7CQ1S&oQ zI!V=ac?QznyfZrV^RD*~p`>{<^?;Qub^R>;>2p4m_=ojuxs~&FuH&gsocW+8E%G6) zfwN`&BkBkb3un^Ft>yjIzXa$J2MCJ2G{!|c2iT+gyCHAfT-mbAHnutKfj5K)v0713zJWksBHo* zv)U%(evqoYfP++N8Y{j{4xI9Wv=tkN(efKiHI_0(wYtKEB+#pqP!Fn4(91Fmm)?3- z>idmia`H5N9+T`}HadsZAiK|q`%$VgvskpcBHv!Eq-LwZWpz8T-&#~sJcM!V>G8g4 z>&0ax95}ADk}WrTIRvVva-Akv|Dl$IH07Uv#b=t@9*Ix}{lCOwzJmmdNpfwWSUav6BZYTPOWbYlkqUE4oB z>iO)iWsy%_hRG6-5opO4eO&W?y&Cc>Lj2l{o?#7zdft!TD64o#wnfugwEA#tyCzNy zY|`@XZdJ579%KB^pNiA>H8=Y|DjVr9y1QkLj=3+`EWR9CGN`Dihy~tMRevtj=O5~L z+DwvkW->GMl+RSX&DYOpsG#8te zCnov7%FE%81G-m2babB=qjw+r;z*jFtA}z^P{i{N_V(Z}dQ@-b%`ELAqM~G2-npMY z-e2$JmgYew-uy4z6W`Z@WJDpR#dPa;v5Ds1(S1E!+mq9+JSL!^SZt&pUM(M7TFNnE zIR#U$Z!1^7Qb2P5I3r_)queLllFBtu5wu(oDqGFVf^x=PzFw(Es|Mx^t zs?yP_D+~pbnBzZ=NK9>(&qmPECtz50^E+(DkC@{o9IlHL9M^r%{zw}?iuV7+A2ADS zyY|Jx|2Of8oR~NF%I#WhTiv0sl?*51U3?tIx=VZ!~8cdJ`y!tHjD8AlVUB1p6}gQQSjXn8(8+ zcoIC(a5Ac0)Ap$03~bknWa^^@1KCD7vX3ib$hUmK#Q))W@cIm3c=6THvhC)l-~q?G zBY_`~J=@o5?QPYXV<;1HBMmw!yP@X`%oc%DSlioz7M_-ZSmJSzb*ndNpL?nf%ic!J zajo~N>m3T5$*Av;4`-dS_n7Uh{@f`@MH|nQq)LfyPja3b>*+{vL-K7fBtfGvp&~Wz zK;7iKui9QiM#Qq?J-Z6Zw@DHW1f6NVbB;|pXHrIGl$GK zZuOX0zj0;8xUek?_HM>qBX((`f_()hO~pD34eoBgyM=5iFa7wX5LPH`tUXwxP1m01 z^aXgf*!H&-z1fgTY{9k;<39u~J0Sd!>ip;oP-WOLNrlV5UcIx zm-WiwpHZb(;9`aQ-!S`u@J?(p?$M~3G_=7j0V>Q#);y~uv@{ShU^IRphCUd2IcSTQ z)%b0LWabfQtd$kP9yu8uA#lyD^%^VVQaVoy?Ia8*Sp%;a!)@Yw)z@P#8N_T?=7BMD zPz4J%y0{S1L5^}V((%vcyjWft z(j)EhV*04-1zWyS?F6#CFShbcHj?>E*WLu*yVO0395P8_=4`lb#G7z9UYP-8SsKTU z?2GcCf06VA#6=VRH}`Lzx-sv@x|ISRQm4sJUtNCZ&UM-%p|dj8@_-vCzQ-t9#@ov9T%ffwY0O5OM8o+2NoLyD?4A>CKYkgL zIEvnrK=$4jin@yPqlSO@NE^vj01Tq-@Md2XcOZHbPF1|RWAaJmtkD8_F}{`Hf%Fu8 z&Sg1rvuhGb(8dcKUb<3Vap)alV%E$Ej<^pVN@p((=2s1d{?H}0B;nVDBA zpoIN`t@#ldu4ha?0=>|ijRviM{W~<%E$L6v(xJhfVq`cF{})}8N(^-R*P@>zU%3+X z)AMq++w`aY=BuTj@|6i|Q1zPj`z(}k?{fu^o`5>%!kZ*o>_1D?5tJsdmjQOg%VFuW zoPXz6y7hX_$N8Gk0s;d5nk(K7-C%!c|H(}IE-Or43V=8%nB5x<9 zHD_j`Ar54dm16@t`~EyUr*GzrZdLY!6R6~Ir$IX0E~57tswLnL#t77(6K0mRa8}Ym z@It>2$t}Ayk9a1cy#tj1mODaUyMeXK;?j+oF_Y;hhV0i|Tm7PqKJ|`@#pM*>kh0D2 zKui1&moAzeVdU@91Ne&QM<(j${?7pi>%$ULGRjGdC2~)&f&CW}LyfR$Ph(atjBpp- zz835+ENI@@QC4R#TIXm>p5V7s8TP_q$0p%A1S1E%EJN&$deko_8RShRSWxuhgQAAd zOE!!>bso7}OT(yh5_arkx_^VBofy2bTnr&(Ij z&NnK}7$^U@f?gtt9w}S)?SFOhZ|8$^2T;nmOk=+;H1iOwbUWSCzWee6vSk~=D2`?^ zU!L9Q6ih`@S1&y^9&R!+tcm_4vRaed5!sPT(CkGP{~~8-@i)0W(+TgM&-#0~_5K1+ zBU`T*vJ)l$l}s(>%UmV5i#mQnB9gVI_1Yyr9slYP?#g@Ns)Z+Uei|Dknuhw289HtR zssM)wdTE4qc}&cj3GPOWm;AwM8`tZSPbzL3C?ROaV>_Ia-H&cw3-5B$N~ZPlqYUb% z@v7hR^1vps2`_q@xRz%5bi6o(h{s0w-u+*Id0@3;G%lHl@H%^GS}HXyblU9por+u| zQu-h9={oUM-%|g4A-t^eEN7tj?dM8i(?HW1Wm7^jQ?>aa z{US6pAN@a;10MPhxW~*-dj5aV3(TbdxP?L0w^RMk)+Jc|G+6)dDMavGRB;WKb*td` zyZpv)G1u*-F5!pf&n0R1pgoy&S}=>q~*u9VHFrYF#0}NW3wg-vE1Z9LJY*io@`c(P0GaU zJsU9mWrAJge%KF#+7+DgiRyo=Qep#`vt!yuZ4f6tUb zI^aLbF!~~i{!zO=mQ&=L{XP=-R@3-q#@)Jie`gi##mCxJp7f#|jl;z8OjZuQjFC_P zl6}m3x9iw+N+U@_gyd>;c5?fd^p2qGMf-vI0(!{!2{Jz-7q_bo+~%`dAio*sbBWrT zE|=f$0@o-7HQi+O-eS0mRe4;Y8V8X_@T|M#)YSL2Iq16$_Y=?BrsjJNngLr=g=o6f z99;JjkuI=C@;h7s0-|?4Gl3K~qmpq}9>m?W?KuIqre~br+O=bZ?z;MlV*=bsQ&0-O zSzMx`cp3(A$^5Ce{CwvWv7LhACXIN8cOGj-gB+f{YybdKe77%+z6k{jeP|B zQAjo2ANJGz?e%jWUoHMZlyYbB?K`%6)-%J1uWdF}IWwi+39Z+bTlGV~(GS8IUw=pJ zIxMap@EFHMb~#eYFzWb6H@vF{D&WY$FUt3^I6{>{1pR^|=FY){@{$!j>OW01$(!*q z3X2pfF8$D(eiNx&eWZut_~={_WCS<9GV&o=5-UguP*S6?zC1rhdf`NMCcXf$uShp@ z%PR~0^up)+$Lgu3M>_hCX?uj$7hkPjvu7o&7{o~Q)LF2Os19JSGBQv3`?};rn9y-f z_BEj1*!;nsd`N!jusiKurexdHGe2^UrQuf$$9D+D{zzTMpfJYk{oy2onoW?wxDOK7 z9^>bnM6!3MI_Rmd0c=A{ zya_8;=&dDEiE+FOL@5TZ$%|)O#HTJKbb|cn>}?b}B@J(zR>^zV-e94m%nYF;RTI@1 zB0%nAXUmB9{@ZJzRr1AX+|B|D`;icr6_Ha^h|5M}e*dRK!TieaR6bRIlL;aXOyf?c zO~QnpdFvBDzMh&c@d-Sr#1voDB;`5?mng(pi@Y#bPi5^*q<_$y3S7eZvbK~7tlnpwgfT{MeTzSeSSFkAc_{q$=&JJ{$f5fe*8ccI2D+2!v zGq19WZdoLIsQb8MME0gb;*?AMZ4Wux#CG9(SiPP`St!9DuC>HR{CK@dxyFZIGwNTH zGwgqy%$VHeqNdPkRs+7L$r?u$gs~X&H6zc-TJhKwqi7ErdA#sJL!BJka4+Qc?!=ZP zx2kIBevULYa}xC` zkOgl2XhA@xwz+m&<_=8uVhLPFZg@ZKZ(1~ic~aHy^Erx@N{mI#YpHrrXw2_~%~F5= z6*qi*IQS0^saVC_;Fvj@q9~O%J6<14e>-jGJz)gB=U^bAUDkAN%hu1qUM`QbSd~}N z`sWfuFC%(r_JrIGKfvJ7tA;~O{d92-w)nnf1Fj7z$Tcs)>;gu*`E(0NNk6O`>i07tb1VIfmu{p*pAufr8#U-Ki!kW4H>=>tg(u>K zn}0Q#(mMfyfsC~q071KiCxUD>^)4wk9jyfu$5q?7R#j%Z_?veQPKXvi_<2R})7F1g z18+=?)P#Zixs6a5eGV0;MId+CvNPqA(`>i(@@wNk=;5dTgSfX~i>uwTMMEICd(hyn z32wm&6z=W>cXxLQ?j8v4?uEO%dvJFMxfT8PzNfoSpT6gL?jL}vwQ8+7=CC)17Jpc7 zV+_z!*pyT~n_b9N&tlBRKp}72ePoBEj4-y*{j9oo+iDU9>0d)LDwJuR{bQKaVy|AgIc_&K4-&ZayPZ8P;Ec=!nOYJdy z*YjkaoCCJ;ac)aUzx}EC%(A-FRp20?hr^C^XjpzX*rIE9EA%KQ!|^~U$Y4;}2?n9E zH)&P$HCt>-TT}xjeA|XkgAr*oRUZ8VXPg^c#iShZ)Sw%6k_%IEtYO4gt>JOk1yW}v zzVDbnAj?vKa#+Ek1k<_)7{p7|)9Y^PuwBtychG;G1rK_6lJovSCe9XnjovFXG|ku_ za;2kY1IM|`B_HC3i*?;~h+c~qr_ z0;Joof%A2)2&_k~u(!~-8cjEW@8b2Q6%{3#qFe@iW^PWi?-?Z?lD6BQd*@r^@Ij}8 zcII7vw0_8EGx+k!G;?1kxrr6N4Ay4lJuXy4Ch=7*3Z?_fC&+&P=9D=hC$2cBrB7Ds z0RTQh+LKkR;s9WOF-Gq4A!9G1ChUsn2Ic3ak}&VWMY%L*Am_Lz!rfsD_N(l<3cxs& zDbkh_W6D!2xOfOu}(!X9$$=zmw>88@r zcFvgAU$YKlxsab-MvKX+{+K&7`%#F-;OlkUD?6*_L(^2*SZIplbL3%U;_f-HTSNA)NR{90uQN%&Z1pQ%huXyCFI*M_N#zVG_}h zpCH{cq*Ky>6J>c~v+UThfgcvJNSmTIDcwgV!eiQ~x!p9$z zussprh1PvtVAYhzg!Tjegf=|=ps*n(uoxeZZWHC9*N~1X^a0bM|UYG}tO5xNQ z%{N`a~!Pau|iyyUNqoZVyRmAR(X=HHrnZUAm0F#0-A@THvt-&1ux+miONa; zOBCO4a$4ulp;h6TFc^_^Zbl;R7)1z5IH-yC$^k-YJt->Uh@UnNX*aS9V zNrg%IUE3eq5!-j4$8&}kp3nM#p!;%+kwG~Jr;KFT;Uw6UbGuDqZNbsRi&SbMpLXc& zH%Mc>J*&^o$tk|Yr?;%ar2@eTYb4E9rEVo=LFE{%pgpOTh$&KfNKc4gQI zie!}i=N+R9xYpMu$esRuHiL_pw`H0=bhzp&nX-YCL|z}jDMy2>r*Jfy^k47@+U+r< z1&>5NTeGYMCSQ(i&Zh-11~YtJO-XczD=0@Njx^&~C0^-6rg=aL8vKBUjlbldha0g@ zf}5RBkI34@$=KkD(EIU5cLWI4k2bftU&%7g+yEcTQ$22#4+)^heQ(yoKQDmWnls7(fE28t$j5O=r+=b`c*pU?@Ct1AW_T5go789Xl2?X#%m}u zTt6Hz-;aj5dHKwIJy~D1Kr^;lfX7c9t|MD8_xdFBztXjt-5b}(JiqaMfO2NgCw28o zgK`$)up)IjyE?un(7yfS)k`7bA_6J?fv5bMCy+^#V#D0{F+In92^|Y!BRhabuXXyo z^ues9v{aZ5E3bihM_nTpVOP4qxdz!+6*CydzEfWr$=TJ_cEj~M>q)aK5otBfbu!R- z!xAz6oSM<8z8eY0;AMCoIiEIybh8--eYE%MqKyVZH2cLVj zi{NHKdU9aVwOoGt1V~0b0N2f8#u5CAO_D9ko#*W8$SdNg9r1V?K3e*Q1ySa>4IR^# zDxH0c9G*5*W*7S zs1ukme>r7_0 zN8)q6VMl!fRjjxmaoI6Jlueqo_`2z(0%xQF&r8Rf-n(K|Nzr?I>$9H#A24h3{wTyn z#x6D-K{0U;ArpS_{ku0SLtvwUgDP2u1hX z6rtxb?%_-)rgcg*S;S~U@-_K2=YO<0n$&kzIqE7wSY(vZhLudk3+^$5u5E^y!i5~? z_!#A%5FgxcFCS%CVNNbDFO~n@qEstp%vnJye}~~lXRo5`%;Y%fKK&d2Z*Cf8WRRcN zOcrK={9j39?~H*BgNOG`j>X_rX!Fl!&A&iy%K-#bnkEaX<}2{Z0TEk*YP!XQeObUE z7b5jXIvooO$xYr-(*t0tSwT1D#XCR6bxrd{KmdtIAdvIuJil3<%6~{1sO0EbLyu7Q zV0LD*CTT5=;2%5kdiYKRqn?1PLnO=q9M|6&o$_^m3wI}2{f%^YH%p(*h9`XJ5M5ST zPT1q_()mhBY=g%MJguI(3D4j((VpdmhNnV)uBgtGu*XqKZa99vXN)CFB&0#pKEGko z3(da5jUuZ{`ZiWWH5;5(SKO+y(zT?>!5Zp*^j`YUZFAiBJIt-SA@)NvcX}f{F)*`4 zcST@nws={+192ttTfq^6buj>$a6onKys<2_%{Sbnk{R!SDSr55gEu_h7`Yv;_?Wn) zXdWzYM69@Z=Uiu62%;@&$>nX#u44x6g}i8aJiyuDZ}g1To>dG9)|xt27YI$)YZ~Dm zPOdk-5aJ8Z^{1!%y6gvZDAR8QRmGtU2XBJb@P7!&)*CZ@9oCLW;hYCkC((MTOSDb_ z58l$17t0<}`AT!sObzXv+<9&QNrVN-;!{C~Si1VI+4kkoF=fu&{80=wH*=iw<{pN?4@F?(IlW(Oztqev@ zH33>>)OTP?%fDP2Yh=rWN4hAbbeA@(T2COQYC;v_P>vh+13g z`_X5asI1(sH!2_J>=j$NnUiBc;e6a05wDOD@-I5$V98bAHg10~^UV^2X{!ikC=5zs!m{=%l7Zd`*lvo8Q7@r7Z1mSm=RaE;`lig2c5R z5g9-*U)+c+!q!i#HnE9DKHl9ipccs(Q}oEws1KHoan(ABe_t&*CK{6j`R)nTi$3>$ba|@hKkiJU{`}`|3oVJ;kf#+ z0fo#WSjeP-+lqQrSOSMyyqFo|FO6>WWMnUvzl}vLE-j#^M~s>~QgJXOSs_ku$!%=< zp_sW<{B0d%H_m8hR(ai~6sN48LjE$xlnBW3;`RN@opUN~=)jUPB*$jR3K2&#>zlnZ z9e7@V0f1npbup^4C@MA6^Y0c#x{V5@iH*Wkr^avyo;rX&GgfgqC7pfVQY*OYbQ=_? zq7OLD4Nv_b`4ST=0LT_v(&ca|ZXjM5)`qyV`m&_PTr}U@>rU{8tod$(l3v_Pp zQ%-6&LQsg}eA7ArSK8Sw$rMWL`$(5-=nzPvJS*c1bs22VMbtEL9gu2qil1TB-)MAS81L>5?a zA%mZ`ix9|w*hgM?exISihtY@q`3*Rpt?JNjB0LCvePS!*PC>`B(fjFiAhLgvxPh<< zp^&1}dg0JY!#K?m)Tb~^M|sQEyBmMN?zn+UpU&qu#n#&Rp!^tKt`*btwDuZX7`tHpx#D3$q_;G85l-oM9TQ3!`%Dbg3h^;p0mg|rNvKtUxh}bH0C-~XP z;=~V|u>;DWY`RkhYvP$dK7vjn|3P@FJLlB*OMDOz`G8CJ0q(AjiasJBsFlnTN4ulY zu6{ik=6-QvK8w^IHS#aCz3)pd=Et?6Yv`>36!U?;Owdmyx)tI%S z8}4i|ZNSA5$Gif#LmKL`M%@ z2$H0>r?i|(&xU46-`@1c=K2*~OH-AJ+Vec(WCw*v-i@-2i7tUR;R_f{?L#J zI=yEwGj7i(Y{y==3dOIi=JbRej)Hvq*3uXathZdt!&teaZd`GWt&sTOENffuW=(i3 zTY%i6s*D85D}L#I;CS1cz<`x`50VxWbSxY4DCjp>f;z6JLY zO|+l8lz7{QRn#9vsVD|vU$P)%}qbaEt1eAN_ zW8|Q;OLy2&lzifpk!*&BVav+OtZR7!7plidnp(koZw{({T1G}PJ~~{KBmD3x)SPwq zjAgNS@`j@=)|;3u(Yo2di6q3}&ZW{Fg|?~9ESyb+ z4pOfYPZ~483#@HgIAT(KuyLS*y_nL;YC)dMT=py7VI5ZU0#BH`vR>>*+}QshHu^{= zy4J|3QUcrjl`Y!}EAnU))j&JNuhEEul8TDo#1J>PaaaAlM;@|Gg!VSwWGh0&-WE{B zb{X0=rMTi?&!a*0xVPZ;%VvW#L1^bl#d+8*qhKFY<7Z=G7qD^lM);=kt>{htV2p1; zf;*pK!Xqs@CnH48qH$q@Z!Q#9ipRTJhRk!QqPI#LataVu0IFqKUxtgx; zVBIv;mAg-6zj6$YFj-|F?;yaia~k4Y(JC;RUZ`@ne6elu)QCf z1221iC02p4`N5T%;7BgOMu-bsxu#@jQ%{IzvQr4?Y|IlX;<*WKJe(OhAh;%4zyEcE zK^aUn{ps+BBMG0H+lD^l2tTY$vrSnn|DJQ}Y~>sC^lVI^#7ANyzLND_iE=>4Uf5M| zE7-tolt3R98VkSly0sZgg0_1I_*=}*bzUB|df*0=z76#UcpIq~c=+jA*T?8-4qhR1 zN~x7k_5%7&${tw+k?Imbre;A8q@wdJ#D}v`ohPzy=tptE;=7dBB_5+-6a@@vt2Xy( z%tT(7QA&2kCx92mSeQnok-lcA+9j)jbo4n8^xBiY$8+O0_M7z%e!IoA8JuYV-4F;3 zEvZ2&dUMUsE(JvtMN*D|)!|LB2gpW;3jxp}X)ld%F$IRsS)Ouj zWz~(MMhM}~T5U9NyAb5m3WsJ`RlYr&&MSm{+TIN{R-?~R(8wU~P;TO#I9K&jSH}VzH}#R7T^GfYh2TPIBOlhpUL%v3ee@LtTao@)o5#GU-t9yD zxcjHhfm+VR*Y$LStd7Tv+Ug+_aPVhh5A!D(uZQuvP&_>d5@5D;Tf`A8ZI9mv8K`B4 zooG6&9j_7#n8#7YZzZ1UmReBB0YJy&Sh8Ip;2`UBqxoj@c}MPR5IW+MkA2pb;e_U( zn0jEx1|0feU^bpQzWw+^4IyDOewXW^R(eSXS%mpfO?N4275OR&0wL932@3KH==!!X zPZJm!aWT1+G2sEOZMqim9w_DnTpsB6*4m=rQrR}dtJ{`1?+E39ATNk@MXR4#Z$2Xv zJJ<@zfeNb^RZYp(eRbdL0du?w7Pb7oek2aNg{-fmPS|4K!L~N)FZK0ci?E}g9K~wo zMyH~aIXyUelBaTgx<2VvWs+MFhC=_MHh)6skh(?3{3u|O3l2mkBS)672Q!{nn4LM- z!di}FX7M7m)g$VZtV^Ut6p<$%plPsG`lhGj!_e%RruQ8hVPQreKM-`qd^@3p=kr%R z&@wmxYfsBRosv-uNC|{bTeE)ww6%}}UD%&;Nxoe&kb{1MZz;7FzZFH-#VL^ON3=;k`;!)=f9Fo0&6m?s}Tm zDtX%FGUmJNv6J@l4}942tzw3M`ljQt0Ppiep{8CwG#| z({kGol{gLe1%6YTZ#R0`1P7@PbgAlUkHum6A)pWt27(3QH-^0_QT7Z6_N6tr1mP2I znURFt7fD=v(kT>S_JM8TXhC*+LbKLZ#&Q}3^e7iwZ625qy$snaYPqU-jDdnzQ1ZKB zWFbxKj?r9=AXKp0BGk(rTIWL&#hlcxbg?ZaY`R0 zm4%9)OVWveuJO;sXQJw3iK-EG6g$?g1QfrbGNDMBp;$XFVP^3mu%jC-;*@jfU4;`R5`Ra8jY}>{`Q|g8e|vLQm?3K<})8RVb)d6g`6^t zL|5_N9JF_?AcTc{Hx%8$s;VVExq9MYs@7A;izAlQc_EDi zsZRDO_Pdux-TM;AG-CQMCww!?yJ2@#O9_b?bNqg$deTw|aiR8~DlT+Je>arm8@u)L zOg(h}m=ftfiVMk{Dei8;LC5w33pAl^odc?e>@9zvhw>w*tS7cY z!h*gi)3pShe2mCGJ}2W#b_7Hbug%foE1j|@t7+;u+uic4JgO)%`UXG9Yxt-vrDIdy z5wOXpMBXlm_?IL#tnGL?=9EBub}Y~}=%3o)WGEBRvL&`%tNXt69W;2Td7(EZ-=Z33 zJK0#zXaF*qU!(O#0Q+^nO{C*N(>7th;TRVni%CP|cd29|#<}&wnKwQ0gIjBSspaXZ zY4jVMKFKnJloiVVb7kfI{|#T&Z)^5%`KR5iOHMVAc~$)}R7OK)+CJBuV-<1%_$+C5 zdtV|bXU)Ecz4~(rIa}td;4uxAnLb)Qj}N|q5jtU*N8c(3`?E?tWgtkD`Y}V&wM0T8 z5v=gt^&2ubPCT&~~6TE^V^D6Dw6e45{UbCu-z#<}poOQLcG8x9b^{dapO_ zVih!5Hdo+-eNXVEQtFT?bla*>4KrNS=vIdUA6WwviT%Vb-2v-biPMUcce z)w60176f4!iKV*w`rr~(JT%O;jm?mnkZD_x#F)y7IdAw7AP3=Wz76oqt66rHT(jx8 zNFsfSI6}_I@Hfb?!Ca!if(%pCy?r9TI_`|t)bKr$uw$H~g#zUiDND`qW_L7yd8-;k zVwFgy#vrIY-1M_E;Bs(}wfq2HRZml3Dn)j$=E^j?cI=k2jn)Go2uTXy@d6D+CEv6- z!caIC>D5PL8R#d4T`p&}OJLBDUw6G%#NF=q=t)UjOllr$T_L*QbCO#&y(&i=aH*7R-8>k_jM#NUoeC}~; zW$9qkx3p%)`U=r8F#)5tCIwWzO?0-XeLW;i@%|?C;XMyty{D4_Ht#_!p6+F6i8>*4 zv#3u4yA^~2qP7piF(0|TIrr2r|2Cbdg5@tW`IIf~a3FLV-ZhIoPP;yWT`oRp6kcpC zZ%73H{}m1M9()4)G-{tTuaqEISsOj6q;1FUvoR-!${y_pzFD-AFeoBnkQX?Xpo2fI z#;3OxRG*<(?V-|Dk-x18|0yNJ!Ml&H2Y|lM&pgEQDP+wz_U(q$Vc{0K`}d@2>dG>{`-n$m;uCr z8UViU3FhfwDP6MX3fy2{+4^EU+xG;GVQ;F&Ww$vsUSudr%0@`peW8gknQr54I(2NG2O!riH z^#LRmT=sQu$&j!MN_J<>#Mnc~np?2!WD#zQD0A;@L+2;sDW zBskLYn_|c#p_f14uGDX$Cg@=ss1{@{t?b(KNikj+TB;n5;|7EZGN=h5_%R#1|U6KFnB+Nb^ZC&#~50Yv$#ULVp78_EfamAt@Ou6JWop{0Ygo% z8a|Pk>x;8THS>j+`InunL)!_ont}kfu<#t;k~0HjNF)X7xCeZf%reBlLp8IFmjbi zMQv*omnnOeK^G@n(3fvJV>0|Ij;1A-S=%Gw z)RwYL_J~?jl>LP+(^cHYAuyfFHlGlr(Fa2d|2VD>*Da99<$p!sjoZ%-WE0~3w@W55 zlVuOjEUM?bUfv8yrbp%YQZyK*1~yfx%$pxa(W_@hbIXSdoT@Y4o^&WSuuxe~X$LdJ zTM?y0=Me#+57dx02(g1Z-aG9bb3`E%oGSOO28fT9%^y6SxJ^^IZMu}Cz3agUu3ZVq z_5~Hv=kYWSA^-4s)IYX={AKM}*gV1d0X$ew&kbu{{<&!tf&X2C^53&xblkry0eZDx zC4j8ZUX1^pSlIu|x$zArK`k!6)>EP_aPuWPTYI7OTcOv{!Bj=U=}!^CI91358B5OU z@5Np8NadE=3mJ0J{ys2#Ap3HGhx!aa%l*u%8mv-8qVge-q(<4oZy{H-Vn#c>2TQJB z$!Cz}l4-6gd^qHjj@>K7{gFPN!YVbtdq~9br3$DzRn%No()6CYiLWS2cRo1Cxo@#j zHPj*{W+8u4i4TVnRm5c?9}2s7f5*a(E$RC2g#TKW4XCP`3hf z)|G^;?4lI>7Vb_8SdOd+fMC_^7mYZdvYH{Go|Yc{<$gP&Ibvr?IoDfmK47oC^J~19 z#7>__==#@`);@md;oq2+0ZJ=}HDsE@?Pk*WEB@D#Y^migg%OR9%L{ioUc^a&Uj+_X zE1hUN>*tZO*o|Fa_xLSyTx+Z}tF= z@zmt|hDZ7Rx?gM=MkAP5&wW&-!!&AAKI_7DX*>NDfpV;^nD<5%@7~*k7g}**b<{uP zdqpZ2T_z1DY2cz;GWRLPufP>8Ujy}4l>guHMbna!7<8_fXmbZ-!edg!5K=zwYL>L& zETLcPBT1E*Z%OI5uZFcRB~31D0niYyob>~d-4GW^q>b_yh3=M&b;B$*^qtI;=jfo1 z17uXKu?c`1&X*5V=J;tkWkvpZOXm?ohBV&F~%f#pHPg661+`j z^!QI!k_N6Ldx#oH5x}f?OtI{+0svuLHvKv>B+^2_BR#A0Ui6(MW=burFEBFZ9Mtv4 z{ue1ZZp@I#e574Htj1((J$-*XG?uN0vs5OdzG8Gtvy84LV0KId%~re_+QnM1Voom~ zNiAV6>m*>}3q_!M9CT52S>Z6z)2k`{xvL{YHV)l){RK$0KN%$-cl*@sa7jMMJat1U zAC%P`prLGwkjCo7zt*btG?~lH;u)Uu;G9JN8a{8zlTsp^nNDbLf(V&1wS#LK4${t5 zH-=x~lDUXILaP-)Rrxd%l-vLPW@|n>SkGob_Z_P}%c+CCNp;)&whtL>(w7g4^$dS_ zKYl$j?s^187ypgD%>^ohTego}7s5W_IFKR=uulTgGu3a9fgv$ES&r!Za?-5mcDJ1Dm$IMB>k7X(k%AWBjuKn+|*%@ zuUqeVi_!pXjH zKD@tIz5Z+!66m}jRKnsJJVhO5vl`Sq`9;#Xo=OTB0=7lu{)pMubkKmT68Q=3ZRLX} zW|0}L43&9P3Kkg~qckH}kR-j{T<^6EpQ%rWJ8^@!(@|eyx1igy!d!c@KQJ7suJ6U04uA>nat7juv5$#uKw6hhO$ghs~^E!#U5D- zCT}tW1?n^t6m9?Y6WUYR zn8~6f!4H@@{`^_)u3iu8cY8?0R5!*JYIQMzl;q3Uf3TZmBw1kidRQ9 zeguamGzCtM|#%A8cx!?=51%-gX)15Gk3}_DGj6j zlwnKxpKXDrMeWuD`=RZ{OR$LBagS)^!sDbbGZwQVz{gsO8YPo1u5l#U$fayc%z&W- z(X-*tCezrm%c{dFRt#*`Y%-T(`06FaGW&)v!Rv{Mb(rK3jJBF{XDixWAfSdfJy)Ic z<9-+*vHzAOja9 zX}Og#;{oji=)~Ll>{!j-W})Po*-5U+7uPq>FTBGztniWlu!%F;gjA~N$S3h>eSH&k zdqJzRcRep$E+`ASv%0SsK4Y=L9+O;(?95ybOG78=GB=wa3iTfSr1(7Bx8m zvU4RGW-w7FsAVdA9jlTfIEkIe5jAx9BzT0Dlj8V$CT`|YylRzJ~+xzZpKo#?XSJFW#C|0-w$ z1uv4VJhO8a2(w!xu41|gf#qhV!W)qQPdxg|uoi#li$Mg`VTPbq5~{Wh9+FX*>=?L8 znZR!#!13d!q5C9&C7aAk>Bl|=yVQFXnAJyWJWndtrxZ`}Gcydde*hgm_Iu^zRCC@W zrYWFj5`fZJd|)-x-pC(ERWn24Z&1Zh#;fB$HnK~$RZ!InYeEx8<38&*<%>&94=N3# zXFYKx#)!uj{y+qc$hc#0aAN+l73zZqn^g|&TZ^b);a&$aP!QS<>uTk&hk=J$eygvb zFe+$21}MV`3i+ak0LX%6F>Ns<9wfcBhRzjeeq}vo9w~hOemW&*AuXjM6?5#hY&eIz zI@RP@@2tbr?CW_XHR?wj_e(@>mz+q+PUt<_B?M`LoJqSOuT_qzUx|x+tyNbDe0)eCC)cyN61hAx4ZW@3>>fkq!ZtcQ zj-faT$=8RM1G*tx=n34W)1+627Kf)%|rP$Vk4 zLFH4_Iu=%?#xLqnT7;o?{M@Ym|CNlEy-D0wKUKn*C?wH=SFD$ zNgBj7zf=vxc5#Z@6e!RzqW+gmLznKKS5zc=M#CN$D}9rH1M4#sHPR_-4;4F;4!6J6 zTBouyKGw@26k9!VrL{2u2MciO07>P`oNdTm81nUs0pX*?27&`oI^-m22<81q54&0Y zDHq%ii6*t+3J^S%y|f~W-BzSr}|}YQMP|^A5-Gk~3d5yqM{ssgzg866sWL zupsmou))6&u+-_w@v|1EBs2RkOZRhH_4L;+267Z}GB$c5boQZ0t~CCKv+54Ct1#cK zu=aSU6P-N9i(|$&ZIoHy#b`?F#OQF-lS!1b7fAu&~rKs?E_*s`NI|9~lZ7U|j}6`aPDOsza+#KMlGCF#HRu{dXqye>koF zuW-7ctgLVxymTKjx{cFHF%XxHjZ}GOb4Fj62ZpVTB_Kql$E)~jR?nxxM7IKXhcQql0y$=zmxvc9t z8=Uy!t+m}6it|oT*LoJwYFu1)OA+E`Aaxx2HVI!l)ns^E-;vpVzjRg4GY78qam2e; zTDHCx7lAl7()GPKlksYqo`Qjo=VvL9bsDgVk)(pmV=1=i7`vT{cHmd;JnIMA-Vo|U z8K1vw0_hd8Mf+#X1AflL92*Eu8>Sor6Wtsg?ivE&T*f7Y2LrCZR4j(fuV#)>NXYMK z{{nus!1d@ygz6dIZK$b6jaRR2PDw^BVt}u)nlX2t4~9S+pS*I0^6y+bq8(j!>Ye%` zeLj6pesj|9M@yX@2)Ju*=$smY)0%WH<3n3Jv5V%t3DkD~kUMUIWFdIvu*cIcB-zHR zps;dQSBH6xASr_OHQ*EN)vIAvTK|MCvpdn9oVsCxR6fjgx2*;vP*r-|M(8A|h6#?a zhCnTXQhPfNYxm*LxMxnOt8Xbu{g&!mwy@u^P{z`aPrHAI-VY0X$dnYkM>~y3p;kxb zHC)!Wl65S@{5WPa4CuB6h^;;wv9>DwrIAeF$_oBTS?_$-J#vhD^-EQoiQv#s;&aHd z#B1Fx`xirqK`gOah6Oys!;X3v8v5)>2U~%)99Pn10T)-AuVKwbfiykeN=|GBq2*7aq7uUM=Vl(1r z{F3AzBAgHW@3LpP5dwE^KZb4p{k?aYwpE~^`=j{!N`3>jBWDzMF-dRh z9cpN_$>@ye0OCgY>enoe*gP_5bZ#yj$&Q+E>i2UYlR8D*FHEIVij{wQhSz5qwDg|J z{^fV03|G%1cviWnPuxM>U5s9(7l8=2~Xi`vO)AQ`XDt7MFkxL=Hp;wC) zhKb)JsgBjK{I)}N$ohg_jy;+4&9?}w43|FQn+JEmY=p2MI~rn?JE>-VkBE$t&3i>3 znn=sHBG@0q*0kh%OU$B!->vyObmr4|HCk#B%WqY@U|(qNn3;j;YyVC_k*0AzEdZr9 zC!jWfCk#D~_X-0lc|e#lI7CP(8DZ8V@71YMh%0#KSXp1lo5mAESyDvDW2AJ2ef?g- ze`F?Q=bdtUCaWUO;np-8aYGcTHp-`-uK?Mtmm@2zF((=}Fj{-Y0@(Oa&33)c31pRW zf<A0WnTQIPFW(cQ@Kh|m6Qm$jH=G=Zst4%@1|p8ClA(Hpell)DGeb)0*c??%Yu^YF zSWur9?ohCxl4{YxZ}B4kOGS|cP?XUNsmXDM7A;K`_|F_6$?svr00q%mPvOR zI~;G8aOIUp#h#wGf_c1{EhofIPj9d>0LM(HxDko|_=zST=Epd``~Frg~fC=4Mhh%w0JdJ6@)#r7A;{!iyLCc)1V3myKg@|Qz^*WrBF z|8bkvzb~9R2>-rS?j*`Z92k*|1k0o;dmFK#n~RBlvP#+3>ZZ%iO?mr_{6_}%M#RWy zz})GX>zkpUo6p zO1!0UdB2v&`%{`_n17$I-hLAGvAuUM;;_=Z)jc2UHkb0*#}FQx6)N@Q_}~?4`4Jbw zDR;o$?MnA;XP@RSU0t48**HB0Qfj&{8mrWj$_RB8{lMkoY4M#jn~dyxQCbbgPr&P8EJ-T6QdN?xqrYH2TMUy{caPyT>)F zYFe}30k-!Xe-{l{kIrbOwmZ59y~Y@hv37OsrJ!`fs5R^!6fJHn3y58pz^^1!!&RW$B* zHH5js1@#^NH^^_S+(HE3E^-W1GFn6Wn{EbUh<}l{!;r84(ie4b<&cO6t#6X7VS%-; zk*V8*Zg(|>O}RWGEi9^kH5K$H>=gP;VUig`)yJ9g(efCVu+_tP&sRRRU0 zgy^SGzk;kc-sKfrC;A#3_FxR5!6pZS?8!LJJOSA!9zv`}0dm3SsY5k*w@Px!ZNh=a zuhN=KL)G)KvTKd-;oY4t8cp4vDkPz$t*o4<&Z>f*UDUS+6D1>fl;|dfv%DC~7?S;0 z61LwiEdWoV@d3Bxy#zsNvweZ3Kbsm(9Y>VfIya&Pvrgio!h>8J2$tniEaD7jsi7gc z92=USPhtNkE&FX(|ME?mN!>>$k1_;>-Yz+{5V<}2i}CzVvvj(aRtKhc3j!Dt-G2O0^&vV zLnomrwc%Zr#TD}PgY-*RC6iK8Vj4p6(H^XsM?ykHqLU1Iof7r$^xl4c$K_1fyTX&I zV?PF~R9~lmLk@-RoYpamhNV8;n^(h%3f3BSB%_P- z9lWJr@xU8vDf6u~lVnba6*@IMd$EGE$CMcZ z)u(U;unLG@{ChEgF&MTYUQU09nts5X zx6lSEd`b@ZsqKCatFc=u0yJMU0flb?^dO4+DNb69abGUBuuH(_>~em?ycW{cPLuBh z+@I;m4!2Wj^!qItPM(Yf&tw5wAH#-!XZnSHW%@(Z8tw9P@ID$-dAy1*&XyFgI857D z=flJOj!?rrkQ!o2j8UsDA098f1;HV!l1w{vr+RxFfO3M?Ut2(6gwoMZ8B0} zaYVvU%`#-=QFGnSyZ>D)DnpIZhK7(^dg(7B0DO$4A;)=7+Js8Jttw9Nul(Eak0J+> zur+ld@XGPJ5$TBB;kXi}TAC$MP)D5fj``74mK#Ga*|=pXJ>k4~$m|c9u|dt+T@^$g zOiOPtzn`x{@_*loQ0~bYd<}KOO9~q+hlaRyUDU95gTwj-v5U3|ag$pVZ`Bo&-ir8q zGZfJu7|@T%2pk0Ks@PY8zBt7Bq+bo=2jRh}f9lZCyGy(>1}))+(9KEIx~Lq!nG`gR zN7hlZRmZr(>1|-W$XH#|t*MWY<`8pgPL^CaiM|{vEgX6(1yFeo9|BO|1-~~nh1Igi z^hE&GGE<5PDEPw|4YxxoXc>M`ioYODP0jF(4|u5bkz0#Q)nO;w48OQ za((WmqO%?ZIMHDAQe}Ns`@<>B*S4VleF~aEPeK2fhzS&fbv&?nWKr*PZ!bwTz-Rzb zPTfB(2b1uhu&OW1=h#1PLF*uzYW2`By{W5 z3^r)j#-P|IYrW<;W3PlLF6Rqq)qFuMrfReRcg`qz@r}lh5J;Yt1&#$C0;=@-GVUcL ztO_Hx!*##-;m>gX?-zXjSCC}9^LO{B@spxXGL_#sRM&r5;`tvH1$d7xRVd^(EtEnD zQ;yQSuTI5h{Y=u&7EvM z`*d~BP|_8e@^%iK^6w}DUf19|m6kNvh?Sn~>-y@D6AY|D)Gs0qwM_{(H9$%&9xyuJ zK}QixRCI(~tLtK}=|R^d{A9vS``U4(?}KB~b={Ygv)wM4Q~nCkEdk1jQEyW1<~g?{ zO6qALzm5iysvIu|$13&CSDxUtNT{(uq8eZE^>G4%yR}>c$KABzt*83Xn*BBDycC%!Db!D|%N$S{c>*FwU3z*YUH&q4SD`?708H>3)2>Z$rN9BgJWw6P*o9qwkRHnwn!RWfQ&?W7s=6xqwdUt9d^Xq}i;nw))O z@;^a?i!5GbNa|cB`$#5K9Qh_WZXPZ|lIHSW56(9x>iW@+=)_Yd`VJ^4gi+2oOj0U5 zhFE*v3~^0YZ=4%Ye59v+4Wq-AizLbZ?K!Z z{A#7q+sj+5+cWU4ApkIBW0eQUCpMVZ>L@JEZ!mO4Q8Swbb_7v;DX!~7TJk@;y4eks zy1e;`HQwPur6HcQiedRY0~^{5P#x75*R#{{j|dik_TNp9Z2C$@*FIpZzs0!+U9|AMw!*vPPgX16Ff93D~pi}sdzH$HZRqs zRjgN9*=9cK7t6nfeX`o>jx0pJS__!#!C+LD1=@^6u$$?FKh{7hKrVH0RL0xo8y+Cr z*E=f*%Tc$~FzSt?7refIci3c6>rRRBWumyA=yuh=_%g`svitym`Urq* zS_B8gCZ?XVx9 zu=Lu@W_AFbD-l0HU6;m$3RJ53zt95b>UW1!+3JZvY*usZK!p9U1xS9e%eUQ&imqqk z#r_53h(R@)GUU{PF~zKL5c(D0ZJ;~d!z*g$-j|?364fjHGwDynXc+>zj$<;)5Z+2i zEVInM$yDVXBKfapz0l6955b{~!0`LIXiGcP2Y$t~1s($NApbMyy6({D+-yTMVMHi3 zl0SLgef`%C{RmBwiiGV!uOL19x251NuGLFtUmq zqHIA;OLf?VmFNAmW^|d~S}DDw2brOHS~reABV51DE^yBY?CHy}!6IHbRqpxV`oYQr zkz0xucyK7KYlY0}>(xPM zRV+iaYTGZpU+;(e<$cd{&-4DD-;36QZ5(u?53SHY1(nvXOZiu+`@ahL=ixA4cE$P? zFzfCnd`-K&E3KKA;Q58d{ZEDbt6z#W3f?|6rGLRVUPfXr**7Hl`Bf;dL1=0~S7Z-# zJ4CigRFOzT6Al;slw#H=PS`}cANDZ4u?@QW1EBe*(q8Qv8)|x(*`Xbe`L1u*vcFC+ zCJjJeB~n9L`G|ry^+Qv^E*9>-BXiaVS4121rp$RXsJc&B_75wN{T{}&Zp$d@#q*+U zS#RG+6H(h=eLuF;=48*gABp#8cupnhRh%>3DL-53GCG2T`iF&Mg5N=sp1f)$C5WeJ zl$yV7eYSgP?G$wRH%lk#9^;sKMcg<~sWz@dTMrPmPY(O=H_+Gd=}=a^PfQbk?-^kU z4WAy8l^~`62xyFq(>Hktx+_)h$x{_83!07VVP2s^)oz}MR0@v@($XBB&(|nfG3Ct>c6>kT+1{}I~^;!-r^Ln+M_?#xODe}NfnOouy zeM{d4!>`#3qg=Gxma80{Y^?sozE&Q`)kM>NPv0(u8@pHAI);XFi1aWlOgNgsI$d-I{B>uL=Q&;E*=Z`PAZmFfb=kM0+wJ7)u%E<%WZ( zHCX+$umng|+XpmK*~FsuBgd#--?W8!FC3J_P>aP^lT2gf)CfTu8<{T|1vuq|d}4jn zkpA-2;m2NfPq#V;!*6&73i-esK@CiXGl+1$F$B{hy&Hj`H4n-dPc_l}(S_3&kgkmo z;tD9(#0)dj$umxw!Idrc732E+<+zPa}C z-+@J|&{7U|V$NIn-tDfIlxKnWm6a0>GC|Eu*c=Io+MF=NBgZkL3x;aFO}#D5BSY*S zlH<0YT`UCJvJ>lWY}kpCBms@lFVD%dFZL^Sb%B#pp%vj__UV$9F5l=6RAjIRSozu< ziPDiek&L4%6$_O0oKrt-VURp3Qzz)bc<@cnAiwLh%}9e#O95X}U)}Xl4y4Tt@zXnt zOKDueu^EQJcs--e4|(d*q3z~3ZC1^h6yp7N$;4^Qxb5GZ?1KtOvTfcSX{jzr%~p8X z&EqFGCIm%(>8cSpMy}7EJ*O8l;gk+BvvG_@I^0SrUap4GPpTT02pe9huvct5aGdwS zNLjOUZ>$OSr~_Lqlllg$Ttcn`KN; zka&F&y8NVx17Xl8VtZZ2j@ajMDo>_$%k|-CW1P@klLdVCrCGO*q>H@HO~@`R5?ARr zyyuaX{G@LQgW-TmYYDb_OHC|Z;m9#$fUePpeD)-_#Fp9Z2`;X(%ndtg^o2D@>w(#H z=3)CDOb?Vc0W5d6mM?Zmd39!7li5PE-z(=Yl3jZ(0dd)l<3Mju;mA0vJfGJc#fTlI zbn;w__W_*Z6Z6a&f1U4d(BamCbaX=p>koakFAZ(uOIhnT#(Y-!5ohR~X+C>kA4%*L zf~M#uBIuhAZP(m3vG0BV$;8&e*r)##imCNOsAqvVUMT@hZeWa!~_Q!sI>0FJy1_ly|-8k1JuDYw5oJnKZ#{s#DmX1z1j3FyFcMu6O zIzB|}W`NGE5D0Sl6PQUah2h$YxSD4FT^Zp(@s76%&d&PW2<22i`R%m^2x6b+Ds_d* z+Xy{xjnEZTB@!q<2ch=Ob)FLJ?5*((K8>FeU?F^8@lRM+O4@y8Tsso8B#4X9%ij5c zoCho6ZcLVdqh<1&vKQ8$=G3r%Y?FH>A}ar6OITa&oQ(q87IPWp4_>_}`CtLgUv%&M zQ`V2YMl}r(X4pAT7M`%wIeP&=K-zuVVd5%imF*@MIF(*tD*N{R^zdQ39Zu3$+3hHj zt}6;JU;fmh*;Erq2D`;x&n%&iCIe?s$x4UVbMhcl4X ziGDP!r!OUP{bRB1Elk8~rg|Rm=PNlOFLE3mcDzgWNiuk}Shau6%>jschSvgIZj%OB zV1)sD4ftbIZu6Oc>i|?z%>#fXodH6L|M#_3;d8+1b@6onX1_|n`g7F!m{q9-CjKwr CAKuFV literal 0 HcmV?d00001 diff --git a/bsp/hc32l136/project.ewp b/bsp/hc32l136/project.ewp new file mode 100644 index 0000000000..1ed9cb8f20 --- /dev/null +++ b/bsp/hc32l136/project.ewp @@ -0,0 +1,2157 @@ + + + + 2 + + Release + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 18 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + Debug + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 18 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + Applications + + $PROJ_DIR$\applications\main.c + + + + CPU + + $PROJ_DIR$\..\..\libcpu\arm\common\backtrace.c + + + $PROJ_DIR$\..\..\libcpu\arm\cortex-m0\context_iar.S + + + $PROJ_DIR$\..\..\libcpu\arm\cortex-m0\cpuport.c + + + $PROJ_DIR$\..\..\libcpu\arm\common\div0.c + + + $PROJ_DIR$\..\..\libcpu\arm\common\showmem.c + + + + DeviceDrivers + + $PROJ_DIR$\..\..\components\drivers\src\completion.c + + + $PROJ_DIR$\..\..\components\drivers\src\dataqueue.c + + + $PROJ_DIR$\..\..\components\drivers\misc\pin.c + + + $PROJ_DIR$\..\..\components\drivers\src\pipe.c + + + $PROJ_DIR$\..\..\components\drivers\src\ringblk_buf.c + + + $PROJ_DIR$\..\..\components\drivers\src\ringbuffer.c + + + $PROJ_DIR$\..\..\components\drivers\serial\serial.c + + + $PROJ_DIR$\..\..\components\drivers\src\waitqueue.c + + + $PROJ_DIR$\..\..\components\drivers\src\workqueue.c + + + + Drivers + + $PROJ_DIR$\board\board.c + + + $PROJ_DIR$\drivers\drv_gpio.c + + + $PROJ_DIR$\drivers\drv_usart.c + + + + finsh + + $PROJ_DIR$\..\..\components\finsh\cmd.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_compiler.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_error.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_heap.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_init.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_node.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_ops.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_parser.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_token.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_var.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_vm.c + + + $PROJ_DIR$\..\..\components\finsh\msh.c + + + $PROJ_DIR$\..\..\components\finsh\shell.c + + + + HC32_StdPeriph + + $PROJ_DIR$\Libraries\HC32L136_StdPeriph_Driver\src\adc.c + + + $PROJ_DIR$\Libraries\HC32L136_StdPeriph_Driver\src\ddl.c + + + $PROJ_DIR$\Libraries\HC32L136_StdPeriph_Driver\src\flash.c + + + $PROJ_DIR$\Libraries\HC32L136_StdPeriph_Driver\src\gpio.c + + + $PROJ_DIR$\Libraries\CMSIS\Device\HDSC\HC32L136\Source\interrupts_hc32l136.c + + + $PROJ_DIR$\Libraries\HC32L136_StdPeriph_Driver\src\lpuart.c + + + $PROJ_DIR$\Libraries\HC32L136_StdPeriph_Driver\src\rtc.c + + + $PROJ_DIR$\Libraries\CMSIS\Device\HDSC\HC32L136\Source\IAR\startup_hc32l136.s + + + $PROJ_DIR$\Libraries\HC32L136_StdPeriph_Driver\src\sysctrl.c + + + $PROJ_DIR$\Libraries\CMSIS\Device\HDSC\HC32L136\Source\system_hc32l13x.c + + + $PROJ_DIR$\Libraries\HC32L136_StdPeriph_Driver\src\timer3.c + + + $PROJ_DIR$\Libraries\HC32L136_StdPeriph_Driver\src\trim.c + + + $PROJ_DIR$\Libraries\HC32L136_StdPeriph_Driver\src\uart.c + + + + Kernel + + $PROJ_DIR$\..\..\src\clock.c + + + $PROJ_DIR$\..\..\src\components.c + + + $PROJ_DIR$\..\..\src\device.c + + + $PROJ_DIR$\..\..\src\idle.c + + + $PROJ_DIR$\..\..\src\ipc.c + + + $PROJ_DIR$\..\..\src\irq.c + + + $PROJ_DIR$\..\..\src\kservice.c + + + $PROJ_DIR$\..\..\src\mem.c + + + $PROJ_DIR$\..\..\src\mempool.c + + + $PROJ_DIR$\..\..\src\object.c + + + $PROJ_DIR$\..\..\src\scheduler.c + + + $PROJ_DIR$\..\..\src\thread.c + + + $PROJ_DIR$\..\..\src\timer.c + + + + + diff --git a/bsp/hc32l136/project.eww b/bsp/hc32l136/project.eww new file mode 100644 index 0000000000..c2cb02eb1e --- /dev/null +++ b/bsp/hc32l136/project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\project.ewp + + + + + diff --git a/bsp/hc32l136/project.uvoptx b/bsp/hc32l136/project.uvoptx new file mode 100644 index 0000000000..f6c199ff22 --- /dev/null +++ b/bsp/hc32l136/project.uvoptx @@ -0,0 +1,924 @@ + + + + 1.0 + +
    ### uVision Project, (C) Keil Software
    + + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + UL2CM3 + -U -O206 -S0 -C0 -P00 -N00("") -D00(00000000) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashHC32L136_64K.FLM -FS00 -FL010000 -FP0($$Device:HC32L136K8TA$Flash\FlashHC32L136_64K.FLM) + + + 0 + JL2CM3 + -U4294967295 -O78 -S4 -ZTIFSpeedSel2000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST2 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC2000 -FN0 + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 1000000 + + + + + + Applications + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + applications\main.c + main.c + 0 + 0 + + + + + CPU + 0 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + ..\..\libcpu\arm\common\backtrace.c + backtrace.c + 0 + 0 + + + 2 + 3 + 1 + 0 + 0 + 0 + ..\..\libcpu\arm\common\div0.c + div0.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\..\libcpu\arm\common\showmem.c + showmem.c + 0 + 0 + + + 2 + 5 + 2 + 0 + 0 + 0 + ..\..\libcpu\arm\cortex-m0\context_rvds.S + context_rvds.S + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\libcpu\arm\cortex-m0\cpuport.c + cpuport.c + 0 + 0 + + + + + DeviceDrivers + 0 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\components\drivers\misc\pin.c + pin.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\components\drivers\serial\serial.c + serial.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\dataqueue.c + dataqueue.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\ringblk_buf.c + ringblk_buf.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\waitqueue.c + waitqueue.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\completion.c + completion.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\pipe.c + pipe.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\ringbuffer.c + ringbuffer.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\workqueue.c + workqueue.c + 0 + 0 + + + + + Drivers + 0 + 0 + 0 + 0 + + 4 + 16 + 1 + 1 + 0 + 0 + board\board.c + board.c + 0 + 0 + + + 4 + 17 + 1 + 0 + 0 + 0 + drivers\drv_gpio.c + drv_gpio.c + 0 + 0 + + + 4 + 18 + 1 + 0 + 0 + 0 + drivers\drv_usart.c + drv_usart.c + 0 + 0 + + + + + finsh + 0 + 0 + 0 + 0 + + 5 + 19 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_node.c + finsh_node.c + 0 + 0 + + + 5 + 20 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_parser.c + finsh_parser.c + 0 + 0 + + + 5 + 21 + 1 + 0 + 0 + 0 + ..\..\components\finsh\cmd.c + cmd.c + 0 + 0 + + + 5 + 22 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_vm.c + finsh_vm.c + 0 + 0 + + + 5 + 23 + 1 + 0 + 0 + 0 + ..\..\components\finsh\msh.c + msh.c + 0 + 0 + + + 5 + 24 + 1 + 0 + 0 + 0 + ..\..\components\finsh\shell.c + shell.c + 0 + 0 + + + 5 + 25 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_var.c + finsh_var.c + 0 + 0 + + + 5 + 26 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_compiler.c + finsh_compiler.c + 0 + 0 + + + 5 + 27 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_heap.c + finsh_heap.c + 0 + 0 + + + 5 + 28 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_ops.c + finsh_ops.c + 0 + 0 + + + 5 + 29 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_error.c + finsh_error.c + 0 + 0 + + + 5 + 30 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_token.c + finsh_token.c + 0 + 0 + + + 5 + 31 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_init.c + finsh_init.c + 0 + 0 + + + + + HC32_StdPeriph + 0 + 0 + 0 + 0 + + 6 + 32 + 2 + 0 + 0 + 0 + Libraries\CMSIS\Device\HDSC\HC32L136\Source\ARM\startup_hc32l136.s + startup_hc32l136.s + 0 + 0 + + + 6 + 33 + 1 + 0 + 0 + 0 + Libraries\HC32L136_StdPeriph_Driver\src\trim.c + trim.c + 0 + 0 + + + 6 + 34 + 1 + 0 + 0 + 0 + Libraries\CMSIS\Device\HDSC\HC32L136\Source\system_hc32l13x.c + system_hc32l13x.c + 0 + 0 + + + 6 + 35 + 1 + 0 + 0 + 0 + Libraries\CMSIS\Device\HDSC\HC32L136\Source\interrupts_hc32l136.c + interrupts_hc32l136.c + 0 + 0 + + + 6 + 36 + 1 + 0 + 0 + 0 + Libraries\HC32L136_StdPeriph_Driver\src\uart.c + uart.c + 0 + 0 + + + 6 + 37 + 1 + 0 + 0 + 0 + Libraries\HC32L136_StdPeriph_Driver\src\sysctrl.c + sysctrl.c + 0 + 0 + + + 6 + 38 + 1 + 0 + 0 + 0 + Libraries\HC32L136_StdPeriph_Driver\src\gpio.c + gpio.c + 0 + 0 + + + 6 + 39 + 1 + 0 + 0 + 0 + Libraries\HC32L136_StdPeriph_Driver\src\ddl.c + ddl.c + 0 + 0 + + + 6 + 40 + 1 + 0 + 0 + 0 + Libraries\HC32L136_StdPeriph_Driver\src\timer3.c + timer3.c + 0 + 0 + + + 6 + 41 + 1 + 0 + 0 + 0 + Libraries\HC32L136_StdPeriph_Driver\src\flash.c + flash.c + 0 + 0 + + + 6 + 42 + 1 + 0 + 0 + 0 + Libraries\HC32L136_StdPeriph_Driver\src\lpuart.c + lpuart.c + 0 + 0 + + + 6 + 43 + 1 + 0 + 0 + 0 + Libraries\HC32L136_StdPeriph_Driver\src\rtc.c + rtc.c + 0 + 0 + + + 6 + 44 + 1 + 0 + 0 + 0 + Libraries\HC32L136_StdPeriph_Driver\src\adc.c + adc.c + 0 + 0 + + + + + Kernel + 0 + 0 + 0 + 0 + + 7 + 45 + 1 + 0 + 0 + 0 + ..\..\src\mem.c + mem.c + 0 + 0 + + + 7 + 46 + 1 + 0 + 0 + 0 + ..\..\src\ipc.c + ipc.c + 0 + 0 + + + 7 + 47 + 1 + 0 + 0 + 0 + ..\..\src\thread.c + thread.c + 0 + 0 + + + 7 + 48 + 1 + 0 + 0 + 0 + ..\..\src\clock.c + clock.c + 0 + 0 + + + 7 + 49 + 1 + 0 + 0 + 0 + ..\..\src\mempool.c + mempool.c + 0 + 0 + + + 7 + 50 + 1 + 0 + 0 + 0 + ..\..\src\timer.c + timer.c + 0 + 0 + + + 7 + 51 + 1 + 0 + 0 + 0 + ..\..\src\scheduler.c + scheduler.c + 0 + 0 + + + 7 + 52 + 1 + 0 + 0 + 0 + ..\..\src\idle.c + idle.c + 0 + 0 + + + 7 + 53 + 1 + 0 + 0 + 0 + ..\..\src\kservice.c + kservice.c + 0 + 0 + + + 7 + 54 + 1 + 0 + 0 + 0 + ..\..\src\components.c + components.c + 0 + 0 + + + 7 + 55 + 1 + 0 + 0 + 0 + ..\..\src\irq.c + irq.c + 0 + 0 + + + 7 + 56 + 1 + 0 + 0 + 0 + ..\..\src\object.c + object.c + 0 + 0 + + + 7 + 57 + 1 + 0 + 0 + 0 + ..\..\src\device.c + device.c + 0 + 0 + + + +     diff --git a/bsp/hc32l136/project.uvprojx b/bsp/hc32l136/project.uvprojx new file mode 100644 index 0000000000..9c6754cc94 --- /dev/null +++ b/bsp/hc32l136/project.uvprojx @@ -0,0 +1,713 @@ + + + + 2.1 + +
    ### uVision Project, (C) Keil Software
    + + + + rt-thread + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + HC32L136K8TA + HDSC + HDSC.HC32L136.1.0.0 + https://raw.githubusercontent.com/hdscmcu/pack/master/ + IRAM(0x20000000,0x2000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashHC32L136_64K -FS00 -FL010000 -FP0($$Device:HC32L136K8TA$Flash\FlashHC32L136_64K.FLM)) + 0 + $$Device:HC32L136K8TA$Device\Include\HC32L136K8TA.h + + + + + + + + + + $$Device:HC32L136K8TA$SVD\HC32L136K8TA.sfr + 1 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rtthread + 1 + 0 + 0 + 1 + 0 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + --diag_suppress=186,66 + USE_DDL_DRIVER, __DEBUG, __RTTHREAD__, HC32L136 + + applications;.;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m0;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;board;drivers;..\..\components\finsh;Libraries\CMSIS\Include;Libraries\CMSIS\Device\HDSC\HC32L136\Include;Libraries\HC32L136_StdPeriph_Driver\inc;.;..\..\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + CPU + + + backtrace.c + 1 + ..\..\libcpu\arm\common\backtrace.c + + + div0.c + 1 + ..\..\libcpu\arm\common\div0.c + + + showmem.c + 1 + ..\..\libcpu\arm\common\showmem.c + + + context_rvds.S + 2 + ..\..\libcpu\arm\cortex-m0\context_rvds.S + + + cpuport.c + 1 + ..\..\libcpu\arm\cortex-m0\cpuport.c + + + + + DeviceDrivers + + + pin.c + 1 + ..\..\components\drivers\misc\pin.c + + + serial.c + 1 + ..\..\components\drivers\serial\serial.c + + + dataqueue.c + 1 + ..\..\components\drivers\src\dataqueue.c + + + ringblk_buf.c + 1 + ..\..\components\drivers\src\ringblk_buf.c + + + waitqueue.c + 1 + ..\..\components\drivers\src\waitqueue.c + + + completion.c + 1 + ..\..\components\drivers\src\completion.c + + + pipe.c + 1 + ..\..\components\drivers\src\pipe.c + + + ringbuffer.c + 1 + ..\..\components\drivers\src\ringbuffer.c + + + workqueue.c + 1 + ..\..\components\drivers\src\workqueue.c + + + + + Drivers + + + board.c + 1 + board\board.c + + + drv_gpio.c + 1 + drivers\drv_gpio.c + + + drv_usart.c + 1 + drivers\drv_usart.c + + + + + finsh + + + finsh_node.c + 1 + ..\..\components\finsh\finsh_node.c + + + finsh_parser.c + 1 + ..\..\components\finsh\finsh_parser.c + + + cmd.c + 1 + ..\..\components\finsh\cmd.c + + + finsh_vm.c + 1 + ..\..\components\finsh\finsh_vm.c + + + msh.c + 1 + ..\..\components\finsh\msh.c + + + shell.c + 1 + ..\..\components\finsh\shell.c + + + finsh_var.c + 1 + ..\..\components\finsh\finsh_var.c + + + finsh_compiler.c + 1 + ..\..\components\finsh\finsh_compiler.c + + + finsh_heap.c + 1 + ..\..\components\finsh\finsh_heap.c + + + finsh_ops.c + 1 + ..\..\components\finsh\finsh_ops.c + + + finsh_error.c + 1 + ..\..\components\finsh\finsh_error.c + + + finsh_token.c + 1 + ..\..\components\finsh\finsh_token.c + + + finsh_init.c + 1 + ..\..\components\finsh\finsh_init.c + + + + + HC32_StdPeriph + + + startup_hc32l136.s + 2 + Libraries\CMSIS\Device\HDSC\HC32L136\Source\ARM\startup_hc32l136.s + + + trim.c + 1 + Libraries\HC32L136_StdPeriph_Driver\src\trim.c + + + system_hc32l13x.c + 1 + Libraries\CMSIS\Device\HDSC\HC32L136\Source\system_hc32l13x.c + + + interrupts_hc32l136.c + 1 + Libraries\CMSIS\Device\HDSC\HC32L136\Source\interrupts_hc32l136.c + + + uart.c + 1 + Libraries\HC32L136_StdPeriph_Driver\src\uart.c + + + sysctrl.c + 1 + Libraries\HC32L136_StdPeriph_Driver\src\sysctrl.c + + + gpio.c + 1 + Libraries\HC32L136_StdPeriph_Driver\src\gpio.c + + + ddl.c + 1 + Libraries\HC32L136_StdPeriph_Driver\src\ddl.c + + + timer3.c + 1 + Libraries\HC32L136_StdPeriph_Driver\src\timer3.c + + + flash.c + 1 + Libraries\HC32L136_StdPeriph_Driver\src\flash.c + + + lpuart.c + 1 + Libraries\HC32L136_StdPeriph_Driver\src\lpuart.c + + + rtc.c + 1 + Libraries\HC32L136_StdPeriph_Driver\src\rtc.c + + + adc.c + 1 + Libraries\HC32L136_StdPeriph_Driver\src\adc.c + + + + + Kernel + + + mem.c + 1 + ..\..\src\mem.c + + + ipc.c + 1 + ..\..\src\ipc.c + + + thread.c + 1 + ..\..\src\thread.c + + + clock.c + 1 + ..\..\src\clock.c + + + mempool.c + 1 + ..\..\src\mempool.c + + + timer.c + 1 + ..\..\src\timer.c + + + scheduler.c + 1 + ..\..\src\scheduler.c + + + idle.c + 1 + ..\..\src\idle.c + + + kservice.c + 1 + ..\..\src\kservice.c + + + components.c + 1 + ..\..\src\components.c + + + irq.c + 1 + ..\..\src\irq.c + + + object.c + 1 + ..\..\src\object.c + + + device.c + 1 + ..\..\src\device.c + + + + + + + + + + + + + +     diff --git a/bsp/hc32l136/rtconfig.h b/bsp/hc32l136/rtconfig.h new file mode 100644 index 0000000000..68c2c571d6 --- /dev/null +++ b/bsp/hc32l136/rtconfig.h @@ -0,0 +1,180 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Project Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +//#define RT_USING_TIMER_SOFT +//#define RT_TIMER_THREAD_PRIO 4 +//#define RT_TIMER_THREAD_STACK_SIZE 512 + +/* kservice optimization */ + +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x40003 +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M0 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 512 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 512 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using USB */ + + +/* POSIX layer and C standard library */ + + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + + +/* AI packages */ + + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Hardware Drivers Config */ + +#define MCU_HC32L136 + +/* Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART1 + +/* Board extended module Drivers */ + + +#endif diff --git a/bsp/hc32l136/rtconfig.py b/bsp/hc32l136/rtconfig.py new file mode 100644 index 0000000000..4556c8a87e --- /dev/null +++ b/bsp/hc32l136/rtconfig.py @@ -0,0 +1,132 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m0' +CROSS_TOOL='iar' + +print "############rtconfig##############" + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +print "CROSS_TOOL: " + CROSS_TOOL + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'E:/Program Files/CodeSourcery/Sourcery G++ Lite/bin' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'D:\03_software\Program Files\Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'D:\03_software\Program Files\IAR Systems\Embedded Workbench 7.5' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' +MCU_TYPE = 'HC32L136' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m0 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -g -Wall -DHC32F4A0 -D__DEBUG -DUSE_DDL_DRIVER -D__ASSEMBLY__ -D__FPU_USED' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu=cortex-m0.fp' + CFLAGS = DEVICE + ' --apcs=interwork -DUSE_DDL_DRIVER -DHC32F4A0 -D__DEBUG' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter "board/linker_scripts/link.sct"' + + CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' + + EXEC_PATH += '/arm/bin40/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = ' -D __DEBUG' + ' -D USE_DDL_DRIVER' + ' -D HC32F4A0' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M0' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' -Ol' + CFLAGS += ' --use_c++_inline' + + AFLAGS = '' + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M0' + AFLAGS += ' --fpu None' + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --redirect _Printf=_PrintfTiny' + LFLAGS += ' --redirect _Scanf=_ScanfSmall' + LFLAGS += ' --entry __iar_program_start' + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = '' diff --git a/bsp/hc32l136/template.ewp b/bsp/hc32l136/template.ewp new file mode 100644 index 0000000000..4e56df1965 --- /dev/null +++ b/bsp/hc32l136/template.ewp @@ -0,0 +1,1933 @@ + + + + 2 + + Release + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 18 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + Debug + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 18 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + + diff --git a/bsp/hc32l136/template.eww b/bsp/hc32l136/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/hc32l136/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/hc32l136/template.uvoptx b/bsp/hc32l136/template.uvoptx new file mode 100644 index 0000000000..53cd00988b --- /dev/null +++ b/bsp/hc32l136/template.uvoptx @@ -0,0 +1,184 @@ + + + + 1.0 + +
    ### uVision Project, (C) Keil Software
    + + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + UL2CM3 + -U -O206 -S0 -C0 -P00 -N00("") -D00(00000000) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashHC32L136_64K.FLM -FS00 -FL010000 -FP0($$Device:HC32L136K8TA$Flash\FlashHC32L136_64K.FLM) + + + 0 + JL2CM3 + -U4294967295 -O78 -S4 -ZTIFSpeedSel2000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST2 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC2000 -FN0 + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 1000000 + + + + +     diff --git a/bsp/hc32l136/template.uvprojx b/bsp/hc32l136/template.uvprojx new file mode 100644 index 0000000000..c40f7d0bf7 --- /dev/null +++ b/bsp/hc32l136/template.uvprojx @@ -0,0 +1,391 @@ + + + + 2.1 + +
    ### uVision Project, (C) Keil Software
    + + + + rt-thread + 0x4 + ARM-ADS + 5060020::V5.06 (build 20)::ARMCC + 0 + + + HC32L136K8TA + HDSC + HDSC.HC32L136.1.0.0 + https://raw.githubusercontent.com/hdscmcu/pack/master/ + IRAM(0x20000000,0x2000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashHC32L136_64K -FS00 -FL010000 -FP0($$Device:HC32L136K8TA$Flash\FlashHC32L136_64K.FLM)) + 0 + $$Device:HC32L136K8TA$Device\Include\HC32L136K8TA.h + + + + + + + + + + $$Device:HC32L136K8TA$SVD\HC32L136K8TA.sfr + 1 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rtthread + 1 + 0 + 0 + 1 + 0 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + --diag_suppress=186,66 + __DEBUG,HC32F4A0,USE_DDL_DRIVER + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + --keep=*Handler + + + + + + + + + + + + + + +     From fa6a9ec7dac39b905effdd4905ad437d9c0001fb Mon Sep 17 00:00:00 2001 From: jacycle <515892376@qq.com> Date: Mon, 23 Aug 2021 10:35:49 +0800 Subject: [PATCH 02/29] =?UTF-8?q?1.=E4=BF=AE=E5=A4=8D=E7=BC=BA=E9=99=B7?= =?UTF-8?q?=E6=89=AB=E6=8F=8F=E7=9A=84=E9=97=AE=E9=A2=98?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../HC32L136_StdPeriph_Driver/inc/ddl.h | 1 - .../HC32L136_StdPeriph_Driver/src/ddl.c | 59 +------------------ .../HC32L136_StdPeriph_Driver/src/dmac.c | 2 +- 3 files changed, 4 insertions(+), 58 deletions(-) diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/ddl.h b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/ddl.h index 0979209c91..6b60df1c71 100644 --- a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/ddl.h +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/ddl.h @@ -59,7 +59,6 @@ #include "hc32l136.h" #include "system_hc32l136.h" #include "sysctrl.h" -//#include "gpio.h" /* C binding of definitions if building with C++ compiler */ #ifdef __cplusplus diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/ddl.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/ddl.c index dbca2ea4b1..13d1e25040 100644 --- a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/ddl.c +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/ddl.c @@ -88,11 +88,6 @@ //#define __CC_ARM #endif - - - - - uint32_t Log2(uint32_t u32Val) { uint32_t u32V1 = 0; @@ -146,62 +141,14 @@ void DDL_WAIT_LOOP_HOOK(void) *****************************************************************************/ void Debug_UartInit(void) { -#ifdef __DEBUG - //uint32_t u32Pclk1 = 0; - //volatile uint32_t u32ReloadVal = 0; - // - //// UART0_TXD/P35, 19200bps - //M0P_GPIO->P3ADS_f.P35 = 0; - //M0P_GPIO->P35_SEL_f.SEL = 3; - //M0P_GPIO->P3DIR_f.P35 = 0; - // - //u32Pclk1 = Sysctrl_GetPClkFreq(); - //u32ReloadVal = 65536 - u32Pclk1 * 2 / 19200 / 32; - // - //M0P_BT0->CR_f.CT = 0; - //M0P_BT0->CR_f.MD = 1; - //M0P_BT0->CR_f.TOG_EN = 1; - //M0P_BT0->ARR = u32ReloadVal; - //M0P_BT0->CNT = u32ReloadVal; - //M0P_BT0->CR_f.TR = 1; - // - //M0P_UART0->SCON_f.DBAUD = 1; - //M0P_UART0->SCON_f.SM01 = 1; -#endif + } void Debug_Output(uint8_t u8Data) { - //M0P_UART0->SCON_f.REN = 0; - //M0P_UART0->SBUF = u8Data; - // - //while (TRUE != M0P_UART0->ISR_f.TI) - //{ - // ; - //} - //M0P_UART0->ICR_f.TICLR = 0; + } -//#ifdef __DEBUG -///** -// ****************************************************************************** -// ** \brief Re-target putchar function -// ******************************************************************************/ -//int fputc(int ch, FILE *f) -//{ - -// if (((uint8_t)ch) == '\n') -// { -// Debug_Output('\r'); -// } -// Debug_Output(ch); - -// return ch; -//} -//#endif - - - extern void Debug_UartInit(void); extern void Debug_Output(uint8_t u8Data); @@ -209,7 +156,7 @@ extern void Debug_Output(uint8_t u8Data); #pragma import(__use_no_semihosting) void _sys_exit(int x) { - x = x; + (void)x; } struct __FILE { diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/dmac.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/dmac.c index 8c95fea752..be82e4bf4c 100644 --- a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/dmac.c +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/dmac.c @@ -268,7 +268,7 @@ en_result_t Dma_InitChannel(en_dma_channel_t enCh, stc_dma_config_t* pstcConfig) /* Check for channel and NULL pointer */ if ((!IS_VALID_CH(enCh)) || - (NULL == pstcConfig)) + (pstcConfig == NULL)) { return ErrorInvalidParameter; } From d316f09175f8430b8f9e6cf4ed2fdb388ef919cf Mon Sep 17 00:00:00 2001 From: jacycle <515892376@qq.com> Date: Mon, 23 Aug 2021 10:50:22 +0800 Subject: [PATCH 03/29] =?UTF-8?q?1.=E4=BF=AE=E5=A4=8D=E6=89=AB=E6=8F=8F?= =?UTF-8?q?=E9=97=AE=E9=A2=98?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/dmac.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/dmac.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/dmac.c index be82e4bf4c..048d35e12b 100644 --- a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/dmac.c +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/dmac.c @@ -267,8 +267,8 @@ en_result_t Dma_InitChannel(en_dma_channel_t enCh, stc_dma_config_t* pstcConfig) ASSERT(IS_VALID_ADDR_MODE(pstcConfig->enDstAddrMode)); /* Check for channel and NULL pointer */ - if ((!IS_VALID_CH(enCh)) || - (pstcConfig == NULL)) + if ((pstcConfig == NULL) || + (!IS_VALID_CH(enCh))) { return ErrorInvalidParameter; } From 83636c461f5389e4407d156d6fefa4b75b3ca505 Mon Sep 17 00:00:00 2001 From: jacycle <515892376@qq.com> Date: Mon, 23 Aug 2021 14:58:40 +0800 Subject: [PATCH 04/29] =?UTF-8?q?1.=E5=86=8D=E6=AC=A1=E4=BF=AE=E5=A4=8D?= =?UTF-8?q?=E6=89=AB=E6=8F=8F=E9=97=AE=E9=A2=98?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/dmac.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/dmac.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/dmac.c index 048d35e12b..1003e61def 100644 --- a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/dmac.c +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/dmac.c @@ -267,8 +267,7 @@ en_result_t Dma_InitChannel(en_dma_channel_t enCh, stc_dma_config_t* pstcConfig) ASSERT(IS_VALID_ADDR_MODE(pstcConfig->enDstAddrMode)); /* Check for channel and NULL pointer */ - if ((pstcConfig == NULL) || - (!IS_VALID_CH(enCh))) + if (!IS_VALID_CH(enCh)) { return ErrorInvalidParameter; } From 1f24348464a572fc184f029e6420fcf0f12727fb Mon Sep 17 00:00:00 2001 From: Dozingfiretruck <1473454180@qq.com> Date: Tue, 24 Aug 2021 13:40:58 +0800 Subject: [PATCH 05/29] fix:Unable to enter the menuconfig menu after executing scons -- dist Compilation failure for enabling DFS after using SDIO --- bsp/at32/at32f403a-start/board/Kconfig | 1 + bsp/at32/tools/sdk_dist.py | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/bsp/at32/at32f403a-start/board/Kconfig b/bsp/at32/at32f403a-start/board/Kconfig index 9816ab4729..f434d04b7c 100644 --- a/bsp/at32/at32f403a-start/board/Kconfig +++ b/bsp/at32/at32f403a-start/board/Kconfig @@ -172,6 +172,7 @@ menu "On-chip Peripheral Drivers" bool "Enable SDIO" default n select RT_USING_SDIO + select RT_USING_DFS if BSP_USING_SDIO config BSP_USING_SDIO1 bool "Enable SDIO1" diff --git a/bsp/at32/tools/sdk_dist.py b/bsp/at32/tools/sdk_dist.py index 4c36c9b6e3..e3db1e519a 100644 --- a/bsp/at32/tools/sdk_dist.py +++ b/bsp/at32/tools/sdk_dist.py @@ -4,6 +4,24 @@ import shutil cwd_path = os.getcwd() sys.path.append(os.path.join(os.path.dirname(cwd_path), 'rt-thread', 'tools')) +def bsp_update_kconfig_library(dist_dir): + # change RTT_ROOT in Kconfig + if not os.path.isfile(os.path.join(dist_dir, 'Kconfig')): + return + + with open(os.path.join(dist_dir, 'Kconfig'), 'r') as f: + data = f.readlines() + with open(os.path.join(dist_dir, 'Kconfig'), 'w') as f: + found = 0 + for line in data: + if line.find('RTT_ROOT') != -1: + found = 1 + if line.find('../Libraries') != -1 and found: + position = line.find('../Libraries') + line = line[0:position] + 'Libraries/Kconfig"\n' + found = 0 + f.write(line) + # BSP dist function def dist_do_building(BSP_ROOT, dist_dir): from mkdist import bsp_copy_files @@ -18,3 +36,4 @@ def dist_do_building(BSP_ROOT, dist_dir): print("=> copy bsp drivers") bsp_copy_files(os.path.join(library_path, 'rt_drivers'), os.path.join(library_dir, 'rt_drivers')) shutil.copyfile(os.path.join(library_path, 'Kconfig'), os.path.join(library_dir, 'Kconfig')) + bsp_update_kconfig_library(dist_dir) \ No newline at end of file From 00373d5e23e02f8e0de07e2713e6898933c0705b Mon Sep 17 00:00:00 2001 From: Dozingfiretruck <1473454180@qq.com> Date: Tue, 24 Aug 2021 13:49:55 +0800 Subject: [PATCH 06/29] ATLINK is used by default --- bsp/at32/at32f403a-start/template.uvopt | 30 +++++++++++++++++++---- bsp/at32/at32f403a-start/template.uvoptx | 12 ++++++--- bsp/at32/at32f403a-start/template.uvproj | 28 ++++++++++++++++----- bsp/at32/at32f403a-start/template.uvprojx | 14 +++++++---- 4 files changed, 65 insertions(+), 19 deletions(-) diff --git a/bsp/at32/at32f403a-start/template.uvopt b/bsp/at32/at32f403a-start/template.uvopt index 33eee51f0d..98f84ef5ce 100644 --- a/bsp/at32/at32f403a-start/template.uvopt +++ b/bsp/at32/at32f403a-start/template.uvopt @@ -10,9 +10,10 @@ *.s*; *.src; *.a* *.obj *.lib - *.txt; *.h; *.inc + *.txt; *.h; *.inc; *.md *.plm *.cpp + 0 @@ -31,6 +32,7 @@ 1 1 0 + 0 1 @@ -96,10 +98,12 @@ 0 1 1 - 0 0 0 - 6 + 1 + 0 + 0 + 3 @@ -110,9 +114,14 @@ - Segger\JL2CM3.dll + BIN\CMSIS_AGDI.dll + + 0 + CMSIS_AGDI + -X"AT-Link-EZ-CMSIS-DAP" -U9BE164220040B56D0117B002 -O78 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0AT32F403A_1024 -FS08000000 -FL0100000 + 0 JL2CM3 @@ -151,11 +160,22 @@ 0 0 0 - 1 + 0 0 + 0 + 0 + 0 + + + + + + + + diff --git a/bsp/at32/at32f403a-start/template.uvoptx b/bsp/at32/at32f403a-start/template.uvoptx index 769c7372f0..88ac49dacd 100644 --- a/bsp/at32/at32f403a-start/template.uvoptx +++ b/bsp/at32/at32f403a-start/template.uvoptx @@ -10,7 +10,7 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc + *.txt; *.h; *.inc; *.md *.plm *.cpp 0 @@ -101,7 +101,9 @@ 0 0 1 - 6 + 0 + 0 + 3 @@ -112,7 +114,7 @@ - Segger\JL2CM3.dll + BIN\CMSIS_AGDI.dll @@ -170,6 +172,10 @@ + + + + diff --git a/bsp/at32/at32f403a-start/template.uvproj b/bsp/at32/at32f403a-start/template.uvproj index 7f6d829aff..eeb9d55126 100644 --- a/bsp/at32/at32f403a-start/template.uvproj +++ b/bsp/at32/at32f403a-start/template.uvproj @@ -10,6 +10,7 @@ rt-thread 0x4 ARM-ADS + 0 AT32F403AVGT7 @@ -72,6 +73,8 @@ 0 0 + 0 + 0 1 @@ -80,6 +83,8 @@ 0 0 + 0 + 0 0 @@ -141,10 +146,9 @@ 1 0 1 - 0 0 - 6 + 3 @@ -158,7 +162,7 @@ - Segger\JL2CM3.dll + BIN\CMSIS_AGDI.dll @@ -168,11 +172,11 @@ 0 1 1 - 4096 + 4099 1 - BIN\UL2CM3.DLL - + BIN\CMSIS_AGDI.dll + "" () @@ -218,12 +222,15 @@ 0 0 2 + 0 + 0 0 0 8 0 0 0 + 0 3 3 0 @@ -357,7 +364,15 @@ 0 0 1 + 0 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 @@ -375,6 +390,7 @@ 0 0 0 + 1 diff --git a/bsp/at32/at32f403a-start/template.uvprojx b/bsp/at32/at32f403a-start/template.uvprojx index 9f3a44663d..3809082825 100644 --- a/bsp/at32/at32f403a-start/template.uvprojx +++ b/bsp/at32/at32f403a-start/template.uvprojx @@ -11,11 +11,12 @@ 0x4 ARM-ADS 5060750::V5.06 update 6 (build 750)::ARMCC + 0 AT32F403AVGT7 ArteryTek - Keil.AT32F4xx_DFP.1.3.1 + Keil.AT32F4xx_DFP.1.3.2 IRAM(0x20000000,0x38000) IROM(0x08000000,0x100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -132,11 +133,11 @@ 0 1 1 - 4096 + 4099 1 - BIN\UL2CM3.DLL - + BIN\CMSIS_AGDI.dll + "" () @@ -182,6 +183,8 @@ 0 0 2 + 0 + 0 0 0 8 @@ -322,6 +325,7 @@ 0 0 1 + 0 0 1 1 @@ -347,7 +351,7 @@ 0 0 0 - 0 + 4 From 6ea9a4b3b5880b369319241e846f45896748c8d0 Mon Sep 17 00:00:00 2001 From: Dozingfiretruck <1473454180@qq.com> Date: Wed, 25 Aug 2021 10:11:31 +0800 Subject: [PATCH 07/29] implement RTC framework V2.0 --- bsp/at32/Libraries/rt_drivers/drv_rtc.c | 121 ++++++++++-------------- 1 file changed, 50 insertions(+), 71 deletions(-) diff --git a/bsp/at32/Libraries/rt_drivers/drv_rtc.c b/bsp/at32/Libraries/rt_drivers/drv_rtc.c index d943123e88..9eba173741 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_rtc.c +++ b/bsp/at32/Libraries/rt_drivers/drv_rtc.c @@ -4,12 +4,14 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2020-05-19 shelton first version + * Date Author Notes + * 2020-05-19 shelton first version + * 2021-08-125 Dozingfiretruck implement RTC framework V2.0 */ #include "board.h" #include +#include #include #ifdef BSP_USING_RTC @@ -24,8 +26,6 @@ #define BKUP_REG_DATA 0xA5A5 -static struct rt_device rtc; - static time_t get_rtc_timestamp(void) { #ifdef SOC_SERIES_AT32F415 @@ -93,25 +93,7 @@ static rt_err_t set_rtc_time_stamp(time_t time_stamp) return RT_EOK; } -static void rt_rtc_init(void) -{ -#if defined (SOC_SERIES_AT32F415) - RCC_APB1PeriphClockCmd(RCC_APB1PERIPH_PWR, ENABLE); -#else - RCC_APB1PeriphClockCmd(RCC_APB1PERIPH_PWR | RCC_APB1PERIPH_BKP, ENABLE); -#endif - -#ifdef BSP_RTC_USING_LSI - RCC_LSICmd(ENABLE); - while(RCC_GetFlagStatus(RCC_FLAG_LSISTBL) == RESET); -#else - PWR_BackupAccessCtrl(ENABLE); - RCC_LSEConfig(RCC_LSE_ENABLE); - while(RCC_GetFlagStatus(RCC_FLAG_LSESTBL) == RESET); -#endif /* BSP_RTC_USING_LSI */ -} - -static rt_err_t rt_rtc_config(struct rt_device *dev) +static rt_err_t rt_rtc_config(void) { #if defined (SOC_SERIES_AT32F415) ERTC_InitType ERTC_InitStructure; @@ -166,73 +148,70 @@ static rt_err_t rt_rtc_config(struct rt_device *dev) return RT_EOK; } -static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args) +static rt_err_t at32_rtc_init(void) +{ +#if defined (SOC_SERIES_AT32F415) + RCC_APB1PeriphClockCmd(RCC_APB1PERIPH_PWR, ENABLE); +#else + RCC_APB1PeriphClockCmd(RCC_APB1PERIPH_PWR | RCC_APB1PERIPH_BKP, ENABLE); +#endif + +#ifdef BSP_RTC_USING_LSI + RCC_LSICmd(ENABLE); + while(RCC_GetFlagStatus(RCC_FLAG_LSISTBL) == RESET); +#else + PWR_BackupAccessCtrl(ENABLE); + RCC_LSEConfig(RCC_LSE_ENABLE); + while(RCC_GetFlagStatus(RCC_FLAG_LSESTBL) == RESET); +#endif /* BSP_RTC_USING_LSI */ + if (rt_rtc_config() != RT_EOK) + { + LOG_E("rtc init failed."); + return -RT_ERROR; + } + + return RT_EOK; +} + +static rt_err_t at32_rtc_get_secs(void *args) +{ + *(rt_uint32_t *)args = get_rtc_timestamp(); + LOG_D("RTC: get rtc_time %x\n", *(rt_uint32_t *)args); + + return RT_EOK; +} + +static rt_err_t at32_rtc_set_secs(void *args) { rt_err_t result = RT_EOK; - RT_ASSERT(dev != RT_NULL); - switch (cmd) - { - case RT_DEVICE_CTRL_RTC_GET_TIME: - *(rt_uint32_t *)args = get_rtc_timestamp(); - LOG_D("RTC: get rtc_time %x\n", *(rt_uint32_t *)args); - break; - case RT_DEVICE_CTRL_RTC_SET_TIME: - if (set_rtc_time_stamp(*(rt_uint32_t *)args)) - { - result = -RT_ERROR; - } - LOG_D("RTC: set rtc_time %x\n", *(rt_uint32_t *)args); - break; + if (set_rtc_time_stamp(*(rt_uint32_t *)args)) + { + result = -RT_ERROR; } + LOG_D("RTC: set rtc_time %x\n", *(rt_uint32_t *)args); return result; } -#ifdef RT_USING_DEVICE_OPS -const static struct rt_device_ops rtc_ops = +static const struct rt_rtc_ops at32_rtc_ops = { + at32_rtc_init, + at32_rtc_get_secs, + at32_rtc_set_secs, RT_NULL, RT_NULL, RT_NULL, RT_NULL, - RT_NULL, - rt_rtc_control }; -#endif -static rt_err_t rt_hw_rtc_register(rt_device_t device, const char *name, rt_uint32_t flag) -{ - RT_ASSERT(device != RT_NULL); - - rt_rtc_init(); - if (rt_rtc_config(device) != RT_EOK) - { - return -RT_ERROR; - } -#ifdef RT_USING_DEVICE_OPS - device->ops = &rtc_ops; -#else - device->init = RT_NULL; - device->open = RT_NULL; - device->close = RT_NULL; - device->read = RT_NULL; - device->write = RT_NULL; - device->control = rt_rtc_control; -#endif - device->type = RT_Device_Class_RTC; - device->rx_indicate = RT_NULL; - device->tx_complete = RT_NULL; - device->user_data = RT_NULL; - - /* register a character device */ - return rt_device_register(device, name, flag); -} +static rt_rtc_dev_t at32_rtc_dev; int rt_hw_rtc_init(void) { rt_err_t result; - result = rt_hw_rtc_register(&rtc, "rtc", RT_DEVICE_FLAG_RDWR); + at32_rtc_dev.ops = &at32_rtc_ops; + result = rt_hw_rtc_register(&at32_rtc_dev, "rtc", RT_DEVICE_FLAG_RDWR,RT_NULL); if (result != RT_EOK) { LOG_E("rtc register err code: %d", result); From 3ac58b8577b61b7c1384fd38d84a828db009c518 Mon Sep 17 00:00:00 2001 From: abbcc Date: Thu, 2 Sep 2021 09:55:07 +0800 Subject: [PATCH 08/29] =?UTF-8?q?=E6=B7=BB=E5=8A=A0=20APM32F103ZE=20MINI?= =?UTF-8?q?=20=E6=9D=BF=20bsp?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/apm32/apm32f103xe-minibroard/.config | 375 + bsp/apm32/apm32f103xe-minibroard/.gitignore | 42 + bsp/apm32/apm32f103xe-minibroard/Kconfig | 22 + bsp/apm32/apm32f103xe-minibroard/README.md | 84 + bsp/apm32/apm32f103xe-minibroard/SConscript | 15 + bsp/apm32/apm32f103xe-minibroard/SConstruct | 60 + .../applications/SConscript | 11 + .../applications/main.c | 30 + .../apm32f103xe-minibroard/board/Kconfig | 32 + .../apm32f103xe-minibroard/board/SConscript | 24 + .../apm32f103xe-minibroard/board/board.c | 45 + .../apm32f103xe-minibroard/board/board.h | 60 + .../board/linker_scripts/link.sct | 17 + .../figures/APM32F103ZE.png | Bin 0 -> 553130 bytes .../apm32f103xe-minibroard/project.uvprojx | 638 ++ bsp/apm32/apm32f103xe-minibroard/rtconfig.h | 177 + bsp/apm32/apm32f103xe-minibroard/rtconfig.py | 150 + .../apm32f103xe-minibroard/template.uvprojx | 396 ++ .../inc/apm32f10x_adc.h | 332 + .../inc/apm32f10x_bakpr.h | 135 + .../inc/apm32f10x_can.h | 337 + .../inc/apm32f10x_crc.h | 52 + .../inc/apm32f10x_dac.h | 181 + .../inc/apm32f10x_dbgmcu.h | 83 + .../inc/apm32f10x_dma.h | 290 + .../inc/apm32f10x_dmc.h | 351 + .../inc/apm32f10x_eint.h | 119 + .../inc/apm32f10x_emmc.h | 355 + .../inc/apm32f10x_fmc.h | 251 + .../inc/apm32f10x_gpio.h | 247 + .../inc/apm32f10x_i2c.h | 334 + .../inc/apm32f10x_iwdt.h | 108 + .../inc/apm32f10x_misc.h | 100 + .../inc/apm32f10x_pmu.h | 97 + .../inc/apm32f10x_qspi.h | 337 + .../inc/apm32f10x_rcm.h | 365 + .../inc/apm32f10x_rtc.h | 85 + .../inc/apm32f10x_sci2c.h | 311 + .../inc/apm32f10x_sdio.h | 418 ++ .../inc/apm32f10x_spi.h | 319 + .../inc/apm32f10x_tmr.h | 659 ++ .../inc/apm32f10x_usart.h | 296 + .../inc/apm32f10x_usb.h | 582 ++ .../inc/apm32f10x_wwdt.h | 78 + .../src/apm32f10x_adc.c | 1058 +++ .../src/apm32f10x_bakpr.c | 234 + .../src/apm32f10x_can.c | 1110 +++ .../src/apm32f10x_crc.c | 112 + .../src/apm32f10x_dac.c | 393 ++ .../src/apm32f10x_dbgmcu.c | 132 + .../src/apm32f10x_dma.c | 546 ++ .../src/apm32f10x_dmc.c | 409 ++ .../src/apm32f10x_eint.c | 176 + .../src/apm32f10x_emmc.c | 735 ++ .../src/apm32f10x_fmc.c | 753 ++ .../src/apm32f10x_gpio.c | 531 ++ .../src/apm32f10x_i2c.c | 1013 +++ .../src/apm32f10x_iwdt.c | 135 + .../src/apm32f10x_misc.c | 207 + .../src/apm32f10x_pmu.c | 249 + .../src/apm32f10x_qspi.c | 594 ++ .../src/apm32f10x_rcm.c | 1078 +++ .../src/apm32f10x_rtc.c | 221 + .../src/apm32f10x_sci2c.c | 898 +++ .../src/apm32f10x_sdio.c | 730 ++ .../src/apm32f10x_spi.c | 598 ++ .../src/apm32f10x_tmr.c | 2133 ++++++ .../src/apm32f10x_usart.c | 816 +++ .../src/apm32f10x_usb.c | 378 + .../src/apm32f10x_wwdt.c | 145 + .../CMSIS/Include/cmsis_armcc.h | 894 +++ .../CMSIS/Include/cmsis_armclang.h | 1444 ++++ .../CMSIS/Include/cmsis_armclang_ltm.h | 1891 +++++ .../CMSIS/Include/cmsis_compiler.h | 283 + .../CMSIS/Include/cmsis_version.h | 39 + .../CMSIS/Include/core_cm3.h | 1937 ++++++ .../Geehy/APM32F10x/Include/apm32f10x.h | 6158 +++++++++++++++++ .../APM32F10x/Include/system_apm32f10x.h | 29 + .../Source/ARM/startup_apm32f10x_hd.s | 354 + .../Source/ARM/startup_apm32f10x_md.s | 301 + .../Geehy/APM32F10x/Source/system_apm32f10x.c | 557 ++ .../libraries/APM32F10x_Library/SConscript | 25 + bsp/apm32/libraries/Drivers/Kconfig | 0 bsp/apm32/libraries/Drivers/SConscript | 27 + bsp/apm32/libraries/Drivers/drv_common.c | 125 + bsp/apm32/libraries/Drivers/drv_common.h | 38 + bsp/apm32/libraries/Drivers/drv_gpio.c | 573 ++ bsp/apm32/libraries/Drivers/drv_gpio.h | 38 + bsp/apm32/libraries/Drivers/drv_usart.c | 292 + bsp/apm32/libraries/Drivers/drv_usart.h | 22 + bsp/apm32/libraries/Kconfig | 8 + 91 files changed, 39419 insertions(+) create mode 100644 bsp/apm32/apm32f103xe-minibroard/.config create mode 100644 bsp/apm32/apm32f103xe-minibroard/.gitignore create mode 100644 bsp/apm32/apm32f103xe-minibroard/Kconfig create mode 100644 bsp/apm32/apm32f103xe-minibroard/README.md create mode 100644 bsp/apm32/apm32f103xe-minibroard/SConscript create mode 100644 bsp/apm32/apm32f103xe-minibroard/SConstruct create mode 100644 bsp/apm32/apm32f103xe-minibroard/applications/SConscript create mode 100644 bsp/apm32/apm32f103xe-minibroard/applications/main.c create mode 100644 bsp/apm32/apm32f103xe-minibroard/board/Kconfig create mode 100644 bsp/apm32/apm32f103xe-minibroard/board/SConscript create mode 100644 bsp/apm32/apm32f103xe-minibroard/board/board.c create mode 100644 bsp/apm32/apm32f103xe-minibroard/board/board.h create mode 100644 bsp/apm32/apm32f103xe-minibroard/board/linker_scripts/link.sct create mode 100644 bsp/apm32/apm32f103xe-minibroard/figures/APM32F103ZE.png create mode 100644 bsp/apm32/apm32f103xe-minibroard/project.uvprojx create mode 100644 bsp/apm32/apm32f103xe-minibroard/rtconfig.h create mode 100644 bsp/apm32/apm32f103xe-minibroard/rtconfig.py create mode 100644 bsp/apm32/apm32f103xe-minibroard/template.uvprojx create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_adc.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_bakpr.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_can.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_crc.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dac.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dbgmcu.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dma.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dmc.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_eint.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_emmc.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_fmc.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_gpio.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_i2c.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_iwdt.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_misc.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_pmu.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_qspi.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_rcm.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_rtc.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_sci2c.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_sdio.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_spi.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_tmr.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_usart.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_usb.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_wwdt.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_adc.c create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_bakpr.c create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_can.c create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_crc.c create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dac.c create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dbgmcu.c create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dma.c create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dmc.c create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_eint.c create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_emmc.c create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_fmc.c create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_gpio.c create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_i2c.c create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_iwdt.c create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_misc.c create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_pmu.c create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_qspi.c create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_rcm.c create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_rtc.c create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_sci2c.c create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_sdio.c create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_spi.c create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_tmr.c create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_usart.c create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_usb.c create mode 100644 bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_wwdt.c create mode 100644 bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_armcc.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_armclang.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_armclang_ltm.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_compiler.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_version.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/core_cm3.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Include/apm32f10x.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Include/system_apm32f10x.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/ARM/startup_apm32f10x_hd.s create mode 100644 bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/ARM/startup_apm32f10x_md.s create mode 100644 bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/system_apm32f10x.c create mode 100644 bsp/apm32/libraries/APM32F10x_Library/SConscript create mode 100644 bsp/apm32/libraries/Drivers/Kconfig create mode 100644 bsp/apm32/libraries/Drivers/SConscript create mode 100644 bsp/apm32/libraries/Drivers/drv_common.c create mode 100644 bsp/apm32/libraries/Drivers/drv_common.h create mode 100644 bsp/apm32/libraries/Drivers/drv_gpio.c create mode 100644 bsp/apm32/libraries/Drivers/drv_gpio.h create mode 100644 bsp/apm32/libraries/Drivers/drv_usart.c create mode 100644 bsp/apm32/libraries/Drivers/drv_usart.h create mode 100644 bsp/apm32/libraries/Kconfig diff --git a/bsp/apm32/apm32f103xe-minibroard/.config b/bsp/apm32/apm32f103xe-minibroard/.config new file mode 100644 index 0000000000..495e6cd0d4 --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/.config @@ -0,0 +1,375 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x40001 +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M3=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +CONFIG_FINSH_USING_MSH_ONLY=y +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +# CONFIG_RT_USING_DFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_MTD is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set + +# +# Using WiFi +# +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +# CONFIG_RT_USING_LIBC is not set +# CONFIG_RT_USING_PTHREADS is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# Modbus master and slave stack +# +# CONFIG_RT_USING_MODBUS is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_LWP is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOTKIT is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ADBD is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set + +# +# peripheral libraries and drivers +# + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +CONFIG_SOC_FAMILY_STM32=y +CONFIG_SOC_SERIES_STM32F1=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_STM32F103ZE=y + +# +# Onboard Peripheral Drivers +# +# CONFIG_BSP_USING_SDCARD is not set +# CONFIG_BSP_USING_SPI_FLASH is not set +# CONFIG_BSP_USING_EEPROM is not set + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART1=y +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_I2C2 is not set +# CONFIG_BSP_USING_ON_CHIP_FLASH is not set +# CONFIG_BSP_USING_SDIO is not set + +# +# Board extended module Drivers +# diff --git a/bsp/apm32/apm32f103xe-minibroard/.gitignore b/bsp/apm32/apm32f103xe-minibroard/.gitignore new file mode 100644 index 0000000000..7221bde019 --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/.gitignore @@ -0,0 +1,42 @@ +*.pyc +*.map +*.dblite +*.elf +*.bin +*.hex +*.axf +*.exe +*.pdb +*.idb +*.ilk +*.old +build +Debug +documentation/html +packages/ +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +.DS_Stor* +.config 3 +.config 4 +.config 5 +Midea-X1 +*.uimg +GPATH +GRTAGS +GTAGS +.vscode +JLinkLog.txt +JLinkSettings.ini +DebugConfig/ +RTE/ +settings/ +*.uvguix* +cconfig.h diff --git a/bsp/apm32/apm32f103xe-minibroard/Kconfig b/bsp/apm32/apm32f103xe-minibroard/Kconfig new file mode 100644 index 0000000000..7a400db91f --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/Kconfig @@ -0,0 +1,22 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "../libraries/Kconfig" +source "board/Kconfig" + diff --git a/bsp/apm32/apm32f103xe-minibroard/README.md b/bsp/apm32/apm32f103xe-minibroard/README.md new file mode 100644 index 0000000000..b27871a2eb --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/README.md @@ -0,0 +1,84 @@ +# APM32F103ZE MINI BOARD BSP 说明 + +## 简介 + +本文档为 APM32F103ZE MINI å¼€å‘æ¿ï¼ˆMINI BOARD）的 BSP (æ¿çº§æ”¯æŒåŒ…) 说明。 + +主è¦å†…容如下： + +- å¼€å‘æ¿èµ„æºä»‹ç» +- BSP 快速上手 + +通过阅读快速上手章节开å‘者å¯ä»¥å¿«é€Ÿåœ°ä¸Šæ‰‹è¯¥ BSP，将 RT-Thread è¿è¡Œåœ¨å¼€å‘æ¿ä¸Šã€‚ + +## å¼€å‘æ¿ä»‹ç» + +APM32F103ZE MINI BOARD，采用标准JTAG/SWD调试接å£ï¼Œå¼•å‡ºäº†å…¨éƒ¨çš„IO。开å‘æ¿å¤–观如下图所示： + +![board](figures/APM32F103ZE.png) + + + +该开å‘æ¿å¸¸ç”¨ **æ¿è½½èµ„æº** 如下： + +- MCU：STM32F103C8T6，主频 96MHz，512KB FLASH ，128KB RAM +- 外部 RAM：无 +- 外部 FLASH：无 +- 常用外设 + - LED：2个，（黄色，PE5/PE6） + - 按键：2个，K1（兼具唤醒功能，PA0），K2（PC13） +- 常用接å£ï¼šRS232转串å£ã€ã€USB SLAVE +- 调试接å£ï¼šæ ‡å‡† JTAG/SWD + + + +## å¤–è®¾æ”¯æŒ + +本 BSP ç›®å‰å¯¹å¤–设的支æŒæƒ…况如下： + +| **æ¿è½½å¤–设** | **支æŒæƒ…况** | **备注** | +| :----------- | :----------: | :------------------------------------ | +| RS232è½¬ä¸²å£ | æ”¯æŒ | 使用 UART1/ UART2(通过跳线选择) | +| **片上外设** | **支æŒæƒ…况** | **备注** | +| GPIO | æ”¯æŒ | PA0, PA1... PG15 ---> PIN: 0, 1...143 | +| UART | æ”¯æŒ | UART1/2 | + +## 使用说明 + +本章节是为刚接触 RT-Thread 的新手准备的使用说明，éµå¾ªç®€å•çš„步骤å³å¯å°† RT-Thread æ“作系统è¿è¡Œåœ¨è¯¥å¼€å‘æ¿ä¸Šï¼Œçœ‹åˆ°å®žéªŒæ•ˆæžœ 。 + + +### 快速上手 + +本 BSP 为开å‘者æä¾›MDK5 工程。下é¢ä»¥ MDK5 å¼€å‘环境为例，介ç»å¦‚何将系统è¿è¡Œèµ·æ¥ã€‚ + +#### 硬件连接 + +使用数æ®çº¿è¿žæŽ¥å¼€å‘æ¿åˆ° PC，打开电æºå¼€å…³ã€‚ + +#### 编译下载 + +åŒå‡» project.uvprojx 文件，打开 MDK5 工程，编译并下载程åºåˆ°å¼€å‘æ¿ã€‚ + +> 工程默认é…置使用 J-Link 仿真器下载程åºï¼Œåœ¨é€šè¿‡ J-Link 连接开å‘æ¿çš„基础上，点击下载按钮å³å¯ä¸‹è½½ç¨‹åºåˆ°å¼€å‘æ¿ + +#### è¿è¡Œç»“æžœ + +下载程åºæˆåŠŸä¹‹åŽï¼Œç³»ç»Ÿä¼šè‡ªåŠ¨è¿è¡Œï¼ŒLED é—ªçƒ + +连接开å‘æ¿å¯¹åº”串å£åˆ° PC , 在终端工具里打开相应的串å£ï¼ˆ115200-8-1-N），å¤ä½è®¾å¤‡åŽï¼Œå¯ä»¥çœ‹åˆ° RT-Thread 的输出信æ¯: + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.4 build Aug 20 2021 + 2006 - 2021 Copyright by rt-thread team +msh > +``` +## 注æ„事项 + +- å¯åœ¨æžæµ·å®˜æ–¹ç½‘站进行所需资料下载，如pack安装包和MINIå¼€å‘æ¿åŽŸç†å›¾ç­‰ï¼ˆwww.geehy.com）; + +## è”ç³»äººä¿¡æ¯ + +- \ No newline at end of file diff --git a/bsp/apm32/apm32f103xe-minibroard/SConscript b/bsp/apm32/apm32f103xe-minibroard/SConscript new file mode 100644 index 0000000000..20f7689c53 --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/apm32/apm32f103xe-minibroard/SConstruct b/bsp/apm32/apm32f103xe-minibroard/SConstruct new file mode 100644 index 0000000000..c253622173 --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/SConstruct @@ -0,0 +1,60 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +apm32_library = 'APM32F10x_Library' +rtconfig.BSP_LIBRARY_TYPE = apm32_library + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, apm32_library, 'SConscript'))) + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'Drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/apm32/apm32f103xe-minibroard/applications/SConscript b/bsp/apm32/apm32f103xe-minibroard/applications/SConscript new file mode 100644 index 0000000000..ca2395451a --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/apm32/apm32f103xe-minibroard/applications/main.c b/bsp/apm32/apm32f103xe-minibroard/applications/main.c new file mode 100644 index 0000000000..64250f9010 --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/applications/main.c @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 Abbcc first version + */ + +#include +#include +#include + +/* defined the LED0 pin: PC0 */ +#define LED2_PIN GET_PIN(E, 6) + +int main(void) +{ + /* set LED0 pin mode to output */ + rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT); + + while (1) + { + rt_pin_write(LED2_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED2_PIN, PIN_LOW); + rt_thread_mdelay(500); + } +} diff --git a/bsp/apm32/apm32f103xe-minibroard/board/Kconfig b/bsp/apm32/apm32f103xe-minibroard/board/Kconfig new file mode 100644 index 0000000000..3a7d4e1312 --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/board/Kconfig @@ -0,0 +1,32 @@ +menu "Hardware Drivers Config" + +config SOC_APM32F103ZE + bool + select SOC_SERIES_APM32F1 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "On-chip Peripheral Drivers" + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART1 + bool "Enable UART1" + default y + + endif + + source "../libraries/HAL_Drivers/Kconfig" + +endmenu + +endmenu diff --git a/bsp/apm32/apm32f103xe-minibroard/board/SConscript b/bsp/apm32/apm32f103xe-minibroard/board/SConscript new file mode 100644 index 0000000000..f453b68f6a --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/board/SConscript @@ -0,0 +1,24 @@ +import os +import rtconfig +from building import * + +Import('SDK_LIB') + +cwd = GetCurrentDir() + +# add general drivers +src = Split(''' +board.c +''') + +path = [cwd] + +startup_path_prefix = SDK_LIB + +if rtconfig.CROSS_TOOL == 'keil': + src += [startup_path_prefix + '/APM32F10x_Library/Device/Geehy/APM32F10x/Source/ARM/startup_apm32f10x_hd.s'] + +# You can select chips from the list above +CPPDEFINES = ['APM32F103xE'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) +Return('group') diff --git a/bsp/apm32/apm32f103xe-minibroard/board/board.c b/bsp/apm32/apm32f103xe-minibroard/board/board.c new file mode 100644 index 0000000000..bec2c01cde --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/board/board.c @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 Abbcc first version + */ + +#include "board.h" + +void apm32_usart_init(void) +{ + GPIO_Config_T GPIO_ConfigStruct; + +#ifdef BSP_USING_UART1 + RCM_EnableAPB2PeriphClock((RCM_APB2_PERIPH_T)(RCM_APB2_PERIPH_GPIOA | RCM_APB2_PERIPH_USART1)); + + GPIO_ConfigStruct.mode = GPIO_MODE_AF_PP; + GPIO_ConfigStruct.pin = GPIO_PIN_9; + GPIO_ConfigStruct.speed = GPIO_SPEED_50MHz; + GPIO_Config(GPIOA, &GPIO_ConfigStruct); + + GPIO_ConfigStruct.mode = GPIO_MODE_IN_PU; + GPIO_ConfigStruct.pin = GPIO_PIN_10; + GPIO_ConfigStruct.speed = GPIO_SPEED_50MHz; + GPIO_Config(GPIOA, &GPIO_ConfigStruct); +#endif + +#ifdef BSP_USING_UART2 + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOA); + RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_USART2); + + GPIO_ConfigStruct.mode = GPIO_MODE_AF_PP; + GPIO_ConfigStruct.pin = GPIO_PIN_2; + GPIO_ConfigStruct.speed = GPIO_SPEED_50MHz; + GPIO_Config(GPIOA, &GPIO_ConfigStruct); + + GPIO_ConfigStruct.mode = GPIO_MODE_IN_PU; + GPIO_ConfigStruct.pin = GPIO_PIN_3; + GPIO_ConfigStruct.speed = GPIO_SPEED_50MHz; + GPIO_Config(GPIOA, &GPIO_ConfigStruct); +#endif +} diff --git a/bsp/apm32/apm32f103xe-minibroard/board/board.h b/bsp/apm32/apm32f103xe-minibroard/board/board.h new file mode 100644 index 0000000000..da63a21995 --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/board/board.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 Abbcc first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include + +#include "apm32f10x_gpio.h" +#include "apm32f10x_rcm.h" +#include "apm32f10x_misc.h" +#include "apm32f10x_rcm.h" +#include "apm32f10x_eint.h" +#include "apm32f10x_usart.h" + +#include "drv_common.h" +#include "drv_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define APM32_FLASH_START_ADRESS ((uint32_t)0x08000000) +#define APM32_FLASH_SIZE (512 * 1024) +#define APM32_FLASH_END_ADDRESS ((uint32_t)(APM32_FLASH_START_ADRESS + APM32_FLASH_SIZE)) + +/* Internal SRAM memory size[Kbytes] <6-128>, Default: 128 */ +#define APM32_SRAM_SIZE 128 +#define APM32_SRAM_END (0x20000000 + APM32_SRAM_SIZE * 1024) + +#if defined(__CC_ARM) || defined(__CLANG_ARM) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="CSTACK" +#define HEAP_BEGIN (__segment_end("CSTACK")) +#else +extern int __bss_end; +#define HEAP_BEGIN ((void *)&__bss_end) +#endif + +#define HEAP_END APM32_SRAM_END + +void SystemClock_Config(void); + +void apm32_usart_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __BOARD_H__ */ diff --git a/bsp/apm32/apm32f103xe-minibroard/board/linker_scripts/link.sct b/bsp/apm32/apm32f103xe-minibroard/board/linker_scripts/link.sct new file mode 100644 index 0000000000..5f21bc4aa3 --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/board/linker_scripts/link.sct @@ -0,0 +1,17 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x00080000 { ; load region size_region + ER_IROM1 0x08000000 0x00080000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + RW_IRAM1 0x20000000 0x00020000 { ; RW data + .ANY (+RW +ZI) + } +} + + diff --git a/bsp/apm32/apm32f103xe-minibroard/figures/APM32F103ZE.png b/bsp/apm32/apm32f103xe-minibroard/figures/APM32F103ZE.png new file mode 100644 index 0000000000000000000000000000000000000000..de26f5f42292303b29541459bcec05d2e1426055 GIT binary patch literal 553130 zcmV(_K-9m9P)Px#1ZP1_K>z@;j|==^1poj532;bRa{vGmbN~PnbOGLGA9w%&011W?4?Vtl9`1bW)|gpYRsMXwYoAkD_dU>Bm37YAYp-dqz4zMtoIII1e>gsxpPxTH zJ)Jub^Yb2{Q(Kf28#V)wJ}IlnN$3l6y|{3~|LMuREa&L|BcXS-kbi-ao^uvp|FkAN z4(Da7)!4ECK0m+E`H+fJPcwd$;OWU}GuE8sP&GLd90(PhVmLM|l*L1=v&_5}JR(x9 zmQu_ob0@mgcm=cpu?)16Q0^dKiqIJwHVA*h2x4`}9s(ya6zl16cz{+LZ-gq%ole!S zEHqkYcgO6>iLL9s=|xJh%%{c#pt!KGFi=)Esa7Y>pU~3N#rcK70>NmiI6|DB9G4(^ zs2$LJKzHykR$Eubv27zoWd_{WJhsOXCZK{f@FKu)_{22=p z0cvM(mGwoSWP5XEtBAmi9?p(8PSh4xRS??}#B`WTpn{1%u&I^Pj9H=6?C4TO6=nbx zRQW5kR&kXie7INP(T6+WU+= zv&;#Zh+;~%RJK_37~!r5@rZ#jz=h+JIbO)fpeA3WtK(BLJ}(TV-%m+%Cr6|zt1xsz zJ_7O8)RzUo#^Uzz$%!xXV&x*O#t0B=6fg7M1uH@DzqZ8c2^+ zk*KO}O&r3Uj#fbjxL59!&VrInRU0IcRu_KEKocqc4!{*GajIr(JCqYIL($0-9S^#aGQSl-cgwk*Tu87V+BNKfpwwe^DMGX=1b}7D z)hOe?5kILDc+7R+F}6>-@~L_X5)>IesrHkUPe2Q3ryqV_Rf^`KM88c-gHzibJ+<{* zRy(3Z(nkSRg&Kcmk4!=)lQXe~2>Fp!D&qzkY0*WCvfATvK{m%)g&mMdjOzq8UL zSb3S$SxJ)`ILxqSE;LpCii>gMn6w$;Dq<+67wj@OUE}ot%UF%qNg z#mLKU(MxaXj>YhmOgJS`CpeNL>42_*ouY9lULYw|5vHrG?zF7z8YufQ86(a>g2lSB z7@7$v`$6?aka5G7kaDDw2kVuEy;@OI2o4e?RWe6s>2Llu1%g%9p8@=cl{mUfTpSUl zlb$08K!%~9CPf3Ds*5=1#dKNFjQWTN>jlf@_WsOrzO3ijq%N%3w`YCv5D z;V~%UnT=4YXA2Tjkr+K4801FoiB^{?TV2Gna0D^KdMfIyy_CvC;Rw(4g2jLv%-$$R za7z3&m0@n=P8}5Ik1wykfEvKzJR1)MYMYS_%#=W6XeB^GC_NFiT10I}sVeCy+5qrg zNwq|zPC{RKRtub&anF$=+RWO%PBN!*As8Mib;Zd;q5D5)riW%loeDRR8Pfr(9L=Ag zp95-V;T)wn{&WZvCN$JVok4RZ3J$p#%9*g)yTwAuL={zG&!zo*wpTFoqKf!Ii9j1< zO}%1y`PVkK*`>12RZ1nrDgxLK9U((Y&qO$dsrInA6hZ?iIiJzw?-oC5(O|nWPJ9Kd z@~yq_aDtHLSkz#P7oez3m^(IB3Q}clDv)d0K8#=lPXy)N7RTYo0r9s&9DaS1!&c%3Tf!kpaUVACF6j^cmV1YC{C4n2)7)m zC_g#p)l~*-c!O?$VXp;^7{tjkL6+VP z&0{I7VyUOhF@!TXUwXU64b{ar=1vGE@?|6YT z4|}A6vOP3f2YnfxrMB1#O^q-smpw(wMeHSKz?xE2Sft!5u$rGH^mbspP8s9-sS4d2GETmU3OOO3< zQ{Ba_s??usUd=Xo$37DQ;8@Qbm9fg^mwlRV6m;o{|Ey=810_NMiZirnZsR_9!aHT?39~TUp`ah#n9jtp;;&f zAYz>!itP+U8E!NU9_On8sickZvGF&BU2O`17MzZuH+&|^cEt5iJZe>Hc#GmeD5Se| zDSrNQl5oaoDXM@X0bpkw6{bLps3FHfipHsk0?3SzP~;3AgO+|2z{B34mS-UhQFKm^ z#hwzKIeY>LOTz+8$Bv1!lM_O02UK-d+r7>~*$pqygbJq@^tVO%oQDMzIza)nsv-6| zXBlQ8%BZTB<&cWMy(DxlB=9nHvLb@+)x354lP8#(UJeY|A~G8-ch1auRaFJie6FZo zcm$o9nfpS|O!d*p@e#Qu=Gji-fo~aQg@8eO9a6h&v6w5cDtny12+Sfix+s_HwA-B# zG8*wOgTYH1TGV)~iUal6$pXD*csSa)+OeFcryRjJ)+hj$semOeKnRyWu`K|C!+?2R z1?a$xDusAKDFztzB-QX4KuvIy}rtT z`(>LD5eHcTNVq-P+vS1(y#}RuB@4k}8$pnpqRS}iWtcN|?F89ohfo}daCnA3GFQr^ zmxxO1)SwcdG@$espsDeusvvmN69{ppcc3(C2Vn!m%R?;odAZjxi&P=FU_}RsgRc~F z41}%ymsHwyCYuH|n5ECanYzB7R-q=xHvZ3`%I9rhC5H~E>ltReZA6)?Xu&Q|NhFHS z6oyY_yowYF&vCD>LR5$zH57fuM}bml=%KHN74?0&*T4(qolq~E-soG?(P6`p+yV3K zw3f*lj+B`s06k=ddesh|Y{7J8R6Cz67>Xc)B+agBCNvGY$N(}iF}wk*@5$%dDhPfi zu1-mD1Kav2bLiF-TTsSC#i$W&R)`LiZo3y+kZ|@_&9=0V)G}77&+M)c6Cej14Aiz8 zW=Xykkce8P;;xu36G9h?Sd`S9fp1!66^XTE&p}H796Qs#gl;aKsZ~&Dln|XB9UW#h zC*Q@qJ=mi{e;0*|R^pq?$!TMwP z)hvOc?Pserelw%EK0~>|%H0`Nvqz07+Ge>kh z0-R(9iZhg$J}=t?#Ae!hxr8bPvFNhy*(2`YQeJu%+0@Mf?!;mfn}w+MELT%#;Lb9b zJasm3y(-}x9j+!GsA9tkI>D~|si5^b3um^3*;4S%m+Gg2;J!E)J#kUr%vnbMJjPPk;dJLk(SIbwHixU&^4<+3_yP8rhH2fg|7E$e|0k)i>o1G8O?6FI|jhM*3d?oCqCR?!O}X;|j+s7V3AtwyM) zhBk{B>k3$+Zi|2zO?|j#@eZ0Bjjj(JDL{`_ZtX?H!^X>EhkO!xJqDcD44cz74eQKX zmqs=w)fQIW(w{y7_CnVqDh^X|&KQh*A*w!C(}O0Q^{Vt#xgcm&dcsAglha%ay{gXp zDpv*kk@Iwhc2L94V+2o7+-g1n2zL6TB~WUfX?-Zc@X3+59<|z zT~*$K*Iu9$e>$L<+F5h{H;d4l|Itqzq(u3dOM-aq7G;hCFH=G4Y9MroRog>P;phfk zNRBTPNJl5Y$+TC60C>~Yd7`FRL#+^oj7VQBKZ~70{>h0HdD;Ge=9}Q@A~{P1g3KxU zGL(8aJw91n9H8I$!$V>X1NI%+r>A93pWeWL9Y4%mb zfC~U`LBZ&(U_m^J+D4Gl9}6kmsXi0f z2A0ydXCnISx!p`iKR2Kpu3k|=3Z#hCL^aaGYtX2Hgd(*CjkN_KuO<=a zD?Eav#@4g6#8>IgatBa-uk8Fv0NtZL2yS?ql{3L+38toy!xME|_)Jc4t9iKC^3LH5n>` zx(cFt!WMH5U2;0Q7J1G4DiN6BA-rpAD=W(@9~1ic-x7nK^RsSg&(nIbyL3Ud4_k^z~_4oNlqRoP*%0XKiOeeqJ4^ zvDHgRMT=V4@+$s1mP@mE6P*FZbn4}(n22^n2p}94kMgD`r=CAxgU*-d=EoB!)MLyD zpO-uX=%soVVmeWbP>J`P9AY9i;(+|&EE|uhg9vjGqv|+EOQ8W29(MzC4f_NXXE8XA zJKemB*sJ24AgR9)tE%!7>Zu`iC+=~)2B+;XR+36>)7eAWs<6y@D-Q1`^rIt_(1&J% zHx|xTF#V3p;RHSkA!a|M!m<*I^57=X=qTgmU`?t%1A_Oe>R5<)g!M>WW@3nykpNN~ zK`2>3L{1S*6a}_ARuMpJ(~ymSC}&2S#pZL<3{YFkM9CJhdKO!CTei4miXe>0NusJ# z)ntoDO-)rn2@n_h7lCdZ2w;e?H#d7GX-Y(#))giykDO3!gZEOXGElKcDLWhZ>;6Eq zQM7bw=izxUSk<6rp@6{Vls?y_FM*;4XP~Eis(#?SNNH=th%~#8NmGPR?>hSVdLRuC zT`bjMKa=BFmOs_C5{wQ{#nMqas1XyGRZ?mngX)w#btB9MsUw_ zlVnpgG1$rux`2wqN6ne&r$OH<87IwbFO`m&0W9%1V-DzT1)t&P!Y7Jm_|HoQdI$bA zsM<72<%w00qJYjw zq?Et%cFG(SklgnmXAi2&CJky+Qktq2rB-WE*+bF$+R!?nRFcILLP6o`GR@(MY}n*% z+mozIs)yS8mWCLb)z?5$giJS9n|F|cQohx(5cJb%@+?-#vqdi`XNnchCWR&~GypeP zJyc+xHw0q>cgm47!ixsXl~iG z2l_nzbgBi}W1@Fnl4uzYP}ZfaOccAClK2$p=t`CT($GUs?2AA#Tl8=a6iv*iGu9ob zv*#{`K(A-UW-Asuf@gU6dz}BGh~g5b9@lO00%oqMk2r^Da}t_D7~^LROm*R1^osAS zNU35H>7vcePmUl8jc^{$Yd8Z)RRv2U1?w0a9q+wxDw@#HusNri=1vlwWh}}&aO~yW z)hau~`55vT4nna_{Ov)K&Yqj**U=*AsSq|RQD}XV%qT?^w+2(h2#ohCDRv&|&bG9MkQDSxt#Y~au z0uczgah7~(H&B#ktoLjw_BA~vwW(6HBZ8EugoFpAGbK_yg+Q6PYB>izvDnP#Mx!F0 zO=VLr6!So%BB`<#QFpiw@6LgY3J~_HoakG2thEGCL@l){Q8iZ~;L#Z;1`G1XfB6A? z>Xw;qrc@mm4NQqs6vTFGdxTTlL_Be}qT2gOyocE;N}xT;K%V89 z)kHCtsvQjnEQYCvPFlpZDtd|tbUJ0Ast4&&TllOS^-u?;O0ocLWKx0TF260N?K%lh zr@xPbr|w^wSnX>I*vT>yAgRP&n{};mKSl!@h1y7Jf+NGCqc=n%DnpPdl{B^wi-S_m zHuws_F%aDay=-xGeBtEyN&jY{SM>=tywIrT;xAElpyLdM$aFU-PlgKvxCt>edK^tP zD{Q;aG{T%aT+x_AZ?_QCrluH#;?xbW^0o1Bke!qB4X8RQiz^!9bt#96ywKMv8DL5-XjH_DmTToAJ=7Xfqn{D&nf?X*LCV@NVj{z3~8be?KO^ct$ITX zsbGY3A;k{|R?dPVq06i!`8STaoU0d4iW6veaNPt*bVH-29%O{lwX{L;6!Ec`d@A%j z`ZI&;PSD4c)HDIktCnAS$#o-;l92)nkt64%xW@3OL9w52SxbUNt11abQoIK=w_5M` zarVE9Wn-m(7(vxEADD3rxDZ1D`se{+KNAFcVu49k{Q^vn_s6F~@1g)=a-Grf7}Q7u zVSI528?^GHMyEodbk>84c-L54@Y97>@6+u#8>_h;v20TZo2kok%=?%mOFH#svi)7@w=1Cq0r&86qic(`& zRH&T`dCXD+?R8GXC7~#N5tzjb!qb$4R(;=`Dst%Ls-hJFQtB~cBI!g*rK&tPUJjkg ze-Xe|Q*oBLGcA;3J!RHmklyVc`k3_1%pxsLpU&R2sQ_{;C}J-T^yH#dk`;kc$Sik3 zSJ#j7e-VTSCWK}$)|@2GWXc6$2>BE7I+^EsochLItqN*4b+bS~zPB^OCiHE2j4tRW zq&8LBez0~j1XTw8LC_u1>B%79k!NO9K>JojZKi{SFJde zmu2aeq6C7qmbkq4&3$rQRM~8Gg^^;0EoV#ZEK9J;01TB%6tP?o1BKRI2$BxYDp*}f zvAGcV^t~Rn%63Z6K(SnpH{~F0gosAMW0?rO40W11_sRjiDJ1ovkw`RpfT>eh5Vdmp zSW!4rR=liBYIftElzKH#OW0dQ6iTaFiH(BraU#@e*(hhg)?W#Re!e&ZC8(xct_~8n z+`@Ionkus@R40GO51_4X0YM3o`k9WKfg=8CwH@?Tvdy^K=p}mApcH$3z3>dciXQ7q zN}k{#rKY4%(ib~KvBH5SUb3CGq6qSytCF4`nx*toeH=gv&)H&h!CZPpBsSrC&$g_! z_{^$3lR6wvQB>u|b}pboDjj*8@u3)-f(XE0#`0hMo>MN~Go79OqFYuxRY1vPxvs5M zUsIr9E#}HcM`^LHZ@~E`Bm-JqRfVT##UYsf)aU&H^67EDJQXw_d#@qD@FmIm9al1+ zwXh3|{O&v8G$%KJ#RCk}(kOUF%GS9^T6XG}Qa#r@dEzx>IYQ$=u0J{P;zRZdojvUp zz4az~5kIQ4u&_8-tT}3+7UtJhmKPU?i-Tdk^-;=kKm0`yObUShY0=ycXVnSCt>vJt z*eV<5SnG8*&dLxu=xJcqt_=+6l|>JfY8MBwW1v<#Tt!5ij}&x1%9T)94p$>as(*tE zpwjwO+LcYexI#v)r&Ks>S5ammO6=2!ox9V0rZbKDBtWi!mp`H87~7zQbl^>17>H&6 z5DN_9N_Du~N)iP@U^~-M`T<<)(8nQFsT1Rr|3RVMI z9D6#zPL?FwAbd3hi*UvZp+_3bcmSL?U=cJ;PTM{6FAuf7=&aOPr4e+|?&6pVIbds| z6v-uBts=2#Wz*@)L0{DrrGjS{5R~NQiJjpw;~ebtbUdEy?e0F<-ahif-qVBeL2Ws` zCyS8#z?f<3{I^6oBc2I-oNOAac$k}JNzL#umy)%65fyk=okuO0{;CU97?9JVU*dH# z7!2|mP4_Ida~%zbk@o5)-0qzQ3&X6l3*K=bEe%MmgT>)sVRd7k&epn(cQkqR$_*Fw1( z=)})tai(83tgTt9c{%k~k&w(krN5L|o2K<_4H{eR=*^o&2EaPQfliQd0zK?5b!P%S zoHtPx&VVXN&~UN(-uf94>TFvK4D?J|{@TVC2t&7==_*iFva3HQAKJ~+I4_wLTlqw#ob zwNu4SEqPP3*;_K(-7DrhTN|iDK)Jg}+a8aUZ~muVkRD$?#jCU%6Oh=hLdS6Oph}8A z|1wuTrI6&}&ldOzseDL38TfQ@evzKte)#CYgYBjD&E<{twbivJE??N(SS8!8t*vfu zZLEw|*zM}S^ICP<){*AkInYl0*B21qF$*>Rw|8ZVKnyCEp~zx}hqBQxsX!K0MT2KR z6>@Z3i72GABnud;a~{e8)k8FRD03ayFLq2hrUs7SK#%wIf}-dN!m;p4=sh{_l4>Yc zH-S`bAw^NCa87As!^c#bhMWbRCqQ?vhVfCuEVV^TES2w-a#m5gfw*_o&9rc)xr3R8 z$k{pU2npJtSc=l&rN5&TbH`TnhNlwBthh)gR8X}AO>KzE&JgA5NV6jUBcW?xscZnz zS!C60x1Iqt&}(V$8A??_Pvrb~l0ENb8L+l@1*DEjOFN5SPG=P*4tt1}I?6d4K&%uo z7}ywj8_iNT6eJXN6W4p1`G=?Pi&(e}d!5AN^p?T*I> zM@JL5>bkP+Jz+X#yQCwtyU|i;ZVf<}r!xmMuL6Z|gxG@>IKo`w(4eN(SxdoDD=E1q z3=QDUE`f%midL1N(Hl&sr~CUydxuA3_t$e<8*A6DUD@2+94*Z+uM9Wb(QXdi2m{U{ z#rV%73ZMF$LP;6Xr##4HMnh=GCamsk9ViP(K zv%16HpiEE;B2QJMc?@Qb(n4?gTLaIaG|v)0N$J{q22h|$&O0M%Y~umxi*^6-Q=#Vx z!~D4+j4gT1R2OL#*l)>fB*XoBkAJ&z%Wr9oem7bCki@{s#J zH3Xz|DYcG0P}Jol$4bEv!K-!_%CXV|BlstBsNj#QHmFNic(M$z^2|+DgIJ8Z|FKB4 z=NE^gx%t7t;nCsI=@CoA>FM&y@@TZYx;DJHwX(9jyuP-1@#2LjFGqxWa3xzP^oLTK zL7HkP#-YhnqHMR)IPlk6T8o1JHc#d=Gc!QW2$|in?MRs0tyssIXX67;bWtnfc&zwn zy)=g$9{)N(e>mZYL%rvc8d9pNSjSn)tO(E-Vd4B(EdZsqvDN9HWB`f?%yI&sPt{s)vO%2H5G##R-WI|EB1LEvI8%tSPlssel@uGr@gT#np!O9lWge>^h7`h+5=_K%NGAVi>GLZtp}6;tS%h`d;aS_rL%g6Euy z6%-aq(!$>>0ZP0Rj)UM)4xhx3dj^}?ru^LGXmb13$G30YW*fV-xNu=>{djtEI36Dg z(w3l}bIZEb~JQKKB+KQ+ms+Fod5 zu7N4624x}xXY(9x37X?n-^y5e`WAJZ>hz=@o6@Qx+M9zV=O~FX{-Z%{oTUf4p^`$l zat3P*J)DVjZ7h)aao)$FoR8^pz+$h5D;|*9)L9IlgkFSWokM;MPHW>-kwz&)5y38C zEi%#{mu`Wf@5?_UN|(h-CuoR!!SW$qo%vSuz6Cw8hibj5th6vISZ2Dkm{UUB>+JRQ zCjJEgGwe0!XW4C46v_~Vy|!L|LDA28gr&|Ep0f>y93_1Vs#wf5i^XH5add)37kb>O z6&^u4E(R}wf(RsdR;0E%EC7Qp6fsCZ#pOgDs#p~kW(6BqYjNhpq5NyLmUDI8L8&@} zUQwFT4A~!@`ZOeGdH44Z?%ut(v$J=QPh~6&hVz3#?JQF7egx>H$yZFCD)z*JPZqJx z9II5=Pqt{|)jWp{%Jg`W`>IeZ!af`>4F-!O!711L(F`5au})s)tR_o1YalrxZWpwu z&&?lAj*g~BtdCbNZfvd(7Z;|>qlMwp5UGRx>3DL)z}nf_0f8L_*+`aG9J-;9#h?(A zR|dlj=v_K8gTlKAMh}HBO5sn&sD&UjE;tXiFAq`-NI^Xv6 z1ww%>0@3P!(VcX2#xplJJ&^)(?3=oB`s=wF#tE%EHA*QvHN1H9w|p`#aAb!;3KITTw1Cr?!a;LZzGRH3j|)rw;0z(^Ue z_G)1GC?MK5$U-!8t{!Y^fmyX@N?N554a&+Z(uiI2o4SmuA|QKi3KatfN2h1&_V@QD zlgT05yp#DyyZa9xZ4U-YnZq*amFR%fRt8%+I(nF;6kb3v-|aL2$ri#l*^W;plcVu; zdIW=g#Ris%lPkySGaN`&)fTkQGP!C(Cqc-7)9LZicrrag+u4LKm||mmw7va^ggY4@ zE{_JQt3w*bqGDb@IcD2_aCiu(a!HFp>Q5^u)EtL24oYd(5u!n{5vfdX6kcoz;jBxx zV@lq_mSPJrwGdMkDRQWbFVKi*NI3$B6u(8tU&S~v^YXIR1Z_G_s&)GY zdzndh`kXHr8H|G?EInQMJv!z5q+Mjo+fc+MW*^XvSOEn8D_R_>D((W%s_GzlU67~I zfX3Na&x@q8Az~3v)8rI-A|PL2rbKvK*x@at0Io1JzN)p{AQL9Ctv6Gfd3*LsjKU#L zB#Mt?>Vnjm&c&uKP+l6%LVN36=jmUY&AI4Q8FQSOvAns91HO*4sJNwv1QZ zlM1I$+Te&Wd`K3NB6dUqnv5B8cnWoQ1_jh7{SAjW1S~7Kg({pZB5_hvOp{kIBxHBewI7yo{{0 zAeszPc}(zv#X=HmW~iQMFso7O8%XreIUGgtS(g$Pphwz}3p7fQVxVy$wN{IEsyOFZ zP<5?>h0H=)6ZOqRMX!emQpZV>}!j&Cl*rBS!oRYF-#qP*1+P& zv{j%*EH+Oagl>NT?h!!FXCJ%jbe^o2U!x&!vU{EPat5M3>f~Zfx1XnUFYFm4dm^_l z8Szm2R|Bm#&(Esj5wsTnB02#><%kbe+b2GbeHVnG1RM19PsKk8eQk&EKP#AWVNg{;`p^L1=u-9 zGL8o60tM7&q9!iX>^2m2ur!AH=a_Ms(2IvAl)E&Y43{b1+Q2_}Ew<4gL00ei8Xrx+ zn=_i70O$X)G;j~3LsPgSIfwCMN*X=zj(uX7|;_2C7R zEXO0ZnnwrbJ5{^4U0fWZk%-E#7mKtH0s&%^i?-%LT!~A-3Aqx8E#r{~AzVR7+VI#M z77Cb=Jvp6>$4~|fgZ1^5&wu{2&p!L)@$peUV6otD-r5c}=Vo_Edfp5wZFHS09|GHOTC1;IpBYdtrDzbsggQ_Q&qJE;8itC1d91F zqz8&o)2yUkWL619I4O)%w71Am=PdmhX&Eu{V&b3s%!pjezpXY4i;U4N4o zl9ZJZ59Uod0Oo1&QWxgr=LS}!#S9TUAak>U$+Yh5S;z}0H)fAbUEu+c_KH^b6S#rr z)&)SSRIdtyc+__8Nl}A{MW&QjXBPFXXK-(p6D4HT)l8gO1ft}u2sf?v{)`*{lx49d z(?;d>Y9B_RN*jn)CK6w$TPM zIX?RM!w>G?yZh0{ckbWaUR_@L>l6G;MVTm?vza^D}Dq4QX4q=5^qU`8LKCQ z1&KNufQ@7cfgCEY8O+fTo4T|x&o-HaN=j6aI3NKttmeE^_M1zHOphmUq79u%?q*f? zwg@aOEpde3bUZ)LhMH`RLLJRY091(e$90i-EUvAMZrr@SG#cH#|LFe1$%h~B3>Ky@ zJbMKl__(sZ@yxSN*TcC5DC@E6Du)~U-@}95-Mxno??2kznH)_Ab0-%zH?oSDd-o3x zN&3W%SYZ@bSJ&5WJb7bnea%hua49!N?dfiiXoyyvnM=CtM#VWOw&JYF6a<%?D#8f{ zt=)K`*o?LT=|&?WLXQ+w@slS0G=N8k&YV97Ws;2%_(FGoqeKcX=qVsT5euUG%o%Wz z`s;w^aQviTA<%mb>gopbY}I2BqAX!-oEcBji)W#AQ{j?vg4qSl~ zJ*797LN=)wV*lBRR;(0=jdMwsmKIyDB~Y^rfJI|Ek}%c2)>uT>d8iQRTQL`r|9Ien zk+ITArV%v(qMmvtwd?M9GI_AQbN~K*uIYz^d9LuuZZvFTWBu;E2e%&_gefZ(WckkWVUK%d^+)JNb zUtj*<{g3zd_Ap(52$`!FBqu^(b83pr2LPZa`D%bF5TuSzd~Ac_U|~qwBt?RIytioG;|`W+dGyI_l-Lwc?Wytvz!QuXzO*zNEDlM{IcID#2S&cj z8Dq5nUPt->zWNHA;zJy)7PvNll32jwTiFrZhjh+SrK-GpQ6dJ>_Z~73!k8V2bt!{o zM0F4ivI1}zdk2w{LBTzQODLq(&Jbfr&}3IzNI_I7Nkt`DE}$iZtWRMc{LR1lUj&Z| z5t~xN9jymxoHUy#^pqL9g=L{=j#aJy5Rs&)g20)_oD=9O!7!d4-FxuhwKv{)`A>fQ z$}6wG_wIWS?mb|?dU&wU73!sn7j|}b?myUJGfO0x-dvw+Ih4~{wgPvQadN(F!W^DT=M4z zf)uWZ^WjctaI+_6b~BjJNruK$a;iyIT)I&>@iSedXYK)3rx@Es>j1i~X%K}1cpVFRVzs>} zJ>J7C&*Kc(ffCf@<1uV7HucS3cm7ncV`m)(deJ}4pIPWBv&=>OBr^aT^g1@ujK$y{ zP$s2%tJ;&=qLWoI28H&EG)_l&-MwNon^u(VDhoKPp_K&c&Wh=*AgJZVaIzXJXVSCt+;0J4OQ!&wD~#!xDNFybx$02lHfef;qsf9JbD_>&*syZ;dV zi_0r)Ul)gq%d4x?lZCh5dhdge?wrgmEDcAC!{y=9GS{XfUn``~hYz;jXW#YiJMX;x z&W9g;G@VZHil(uZ^JVDMQAteXgLX-Oa$>sh&couuqPey5R~_-MFM3;)?PfBpdtKjZ z;-ZvBrIWoa;7tH$jQox?5&l!=WjGjlkdkw~#lWUuVPV8I_HZ#Dl9-;5ShIs*-YGMO zQv){X04s-ij8j|!*fV0VN`>@-&^b{WX_qiyOA zCzHDm?oTEYn*?;-EndJpm?>eMV+Nz}IP(lh*O~(7*k*N~mz^yZ{z=MX0I{df;xTI` z0&I0AkPg+%pM?yNh6V~RP-Avz4G;AAEWO7aeKT-Yq&BbKzBgJw0nqznA-zk5RLWxT z;kdIzeW1SFOfs#`daSaH9BA?{B;+0L0r1k^8wqxn;w{9D20^KHl(#){d0OhN0zyYi zqdN2hRGH#48ECxz*(b`mQz#Y18n74wM`WuQ3k{fUkJT1bk$*RyG`Z_U0QQz}3t%!n z&Hwn5jZkDGUIxOZ+VGy~Ye0oSW$GL^#YC92*Xd~2fOZljUbxB;?&C+hJMVw+A@g== zd6_*JIVPj;^uhMSM~`;gqAmC&Y4TN46^muwspm?WI&#PM_9HgGAAj`m+wZ*h`s;5V z9v&v4ISjjl=P7V>yf9dt9#4l$s3d_58BVyG=Id)6E1lJ`a$HrR3KHoL_hE!k@rQv# z40GCR+r&FPg##)#E6J2(OVVN?Ff{Ceoix*_(RMInYI-!Ca8bgQ`03oy$tf=rv3tsF zieaBj#(APaKrNIqH<=!dClg%S+S>G~wF93hxPR~dy?b|YsGpp1qw_5hm`sii4iA== zMqS%&m$x(qi{9;I6uVX#NEWja2W$cC3k%+s&iu@?6KdPp-J>i|vvUS;dN5{4owPYx ze#Eyr_E7Xl$rVZ}I*2Fdpow(a3Mu?CB<)bVJBAvFTuTk%60@6JU(0KTx@hqO27y-u z8)*hYe%vLrX31<&L?G7Wtj;asC#39;KKhvQ^khPQI~tGo_8yUfXnf5O63X)O3JIlY z#`?VPI{|9(IRT8S(Gj3oQsfD{*h1U_I0PJWq;#asHyxC_s#20Y=2SSI8r)1%n^s*^ zqH4m`&?3CKeZ+w>WV) zp4`6u@%HvZnnV7?7(f-)9LjMaI6=s_BU(u! zi!M9!bF_=?F533@4_F0Ca{+>NjKv~%c*a`Q_Q!IvKjIEhRgXdOJO+<3&+~VX+uJz>Bq8OP_-RTGg=_g zfD7dV086_@kvaV4JF{t+5t%=6T(msPzmio$p-5+^$~K%^H3tOIr7=bmy z&4k6O){OO*oGxCEN;{Vz!lrg0`l;16Es$248pMq=!NT=79(ROd6RE0-RiiadL08;| zgs-$#rAHHk?Xp5fc}l=T3txggN{943t+r9><$tMZRnEygJ-{xBIShrC zxKVXU^MQg|A!rvFaL9blr7}g>vWYWufun(z>})^!_~YBgKx@rkUVD4H_wU_lPJ~8s zm>!djrf36)h6CVa+q9ODaN?zaU6wKo_B#P}n=McgSvPt3p@pLJA~}YFA9fG_85+nS z4xlns-sJT0vfKuB$8Oc!g6YjPueM}o6FSC>kD1;?mj!C*4Pquhm`}--gZ;yUyZ7#= zzvpRtcA!TD+F6qpQDGEN%r-S%lbDZ=*nl3XB8mR=c*6dgwxN7T{*BG}LZzXgJ2)at z*QIH34l6zxBuc(dcVq1g!WL3_5kGpKR@D&I$q}M`Py#)-K*{h1J!ouHO7jkhp?~{ zpfcSIB{Q^ATC4rj1Tz>#KH*Ot3*ew%ZIzKyB#bdsfrdHNj2Q?KZXKW}#saDm4HC}? zl^WkbqcS{2Xtn?+oR#6NiZb5;Q;}EUJ)6+P%^>L#UCO9F&lWIzGiqUAs?gHj8WNx6 zX-J*o1HR__P^41MOGf@-!<%pwNITa7g$Rbbp*?E_RIF=BMY)1owFNR1qg~Qw9;xZz zV0=_JPEuFxAzwhCUA#yry^>@nKMrep4d500>K4p>5AHo=KNnZsH4EezE@Ij7j=h-> zX&>5$8F97d`W*xbGB2V~a;v~>l94v0K`~U@QZ;KYt;mtBs7q``Qchk_6I)*Zu9L)b z84jRb8o~xPPJ{;nAht;I^hp5QY&wmiifZ1D18564{!y3fR)L5e9*%c*cj2ENPxf|q zd{hJ0>2VF1EKwKu-!`f|F zW8aN_lkF@ZRnW>l7~i0I6R_CeoJb*>cpRv*s~j?)tn46mWOMkb%vo6H4y-L&SX1&4 z3Fk$zodY>+b%YIZXrJbWp_=ipOh91Zbz``oYU2)lw!yBuX}6JPT!rh^QfWcpbcc<|3_NhmuW7YR-5BsR19{$$dPa+yNvwOj_3}Ux4Y7#Ibw!FMT?ri&35)!I&Zx>+9nO3`iXh|z& z&IT1F-Q;+#=*r2GqmzDl_wv$UWr?lkz{H0i3kzn>Zs3$~cT^4HtU^bJhrGgP*Rhjj zgPX?Tl__;;X^Eb4ee%ZZ1bQOvr|O)M8CFzbO0@}WS^U$$;lgV8Dr}RoSBYu9q3e4U|``-8Tw`J-ri?5XsAR&AK=+*H|R;I`=iJDFc4II51bH zE>uWUx32UeDQ#(({4sAz)qvN+c{1wV_EkI zU(E!7wuWJrr|^Ql6|>HR`Oq(wknMa%kg|Er%IgP{G`H9c}J2WUx=jT^9)-GPWz}5^ysy2P73|Vm#7Fout`{cD6 z+#Jnu010T|9@w-tQT=sVG!}2$WfJ$Li5MW`(V&SEH2Diq8Lo+isI%Uv*Cs&))`8E$yt0^xpf+k&tG}X|}kp|el_?Jw` zt8OJ_%CyL6pqViD6)`2Dm{2*(&!HwfcsWowNEP}Q2lJPh{sA-y*?3vfHMYVMb7jct z7I?0ZNA1>>$R=OIlM4V$>#)heck2QdRZj z>bC*|OkT$0g?ZnpX`5W1u>fIV={Lfmx9zZci zW^jFA>(!4DUbqC%)i%u;&H}SAolYm?F^Y?IK94@)i9gI36FQfM5W@m&sYjX*a?uDw z08jn`D)E#c)Z}V-2fb$KPM&yI#X=r~;{ViIbk}(G7#5l)nkxM&Y9>`71!ydRrl&*# zWp38VIu=r3!4Rj`<5?ar1n3#%6S`J-u$GfoUQs)X%kQM@N`X>Xg7{Vdhjc9zyO?a0 zeaYL=oxC76D_ewmMGUYG_v5(vwNz$+m0gR*FlnnoOueGjVm@IcOB|h^ z@bdatiBg{D#yLv~w+<<%Nk9Xs1f>vdCeh3zCiBn>OZC@mWQL}w3`96N&;s$O&?+0X zoO4GaSkz}~SduvaavmyA#vwCe#V`@^)KmdMEGiU=Ab+@vUR9p3oVd53TaPb_lqESS zQfR>_)U#4;(8w8=GLv2QJBW!28xweSbve0*>v1!yw*vgd{Iu`J2 z?$mp;RJcHcv7epr4{G{g&&5u2Fc=LNZ(O?uKdzL0+ZC%pfb0a+GF2pLwWz_dEikXAR1C97E6U)pABQwwTkN6)!rXHW{M5et;TqWB*d=;Y3kGl+M+d!0z9 ziYjn3PYB=zscfn_b&d(0h#+H|CFe|s(POLYpy&aKDGH4g&KzAG#X|>52g8O#UleL- zq()rAj5P%sIG&o%nIeJgwB)K|>Bxyg>xonb5g3B*;Z);1g{L75U?5Mj!qEsOSr?4;C7$3$kYeY53v=H?>rc|h*PK9By>&26}m3v2A!4&l&2OI z*2)<}1BronQ518HC8;1uJLPMt&!CD{bMUdDoEk~M0dr73fMkF(dI;enr1|;v^;NUj z-27;11VXh`FLhydMdU~hVv+;&F$lZZ@p!_<7AG-9c356oy12QrJYvmbi&qgb53=dx ztd~Hd#+hV_vZBGnD-G5CAZm2ZSufEhm|8hQFyHCh@eyl5QQZxCdjTo=5o50mO*F$; zMUf^0a+*vIZPD~-ckhvV$y6-fKTbwYjAmQKYT`yV zt9W|Nv1)8PTh$OWu!m*WPsNahXmJ3|sGDPT&xU2?gH{WeTHOEU1~i7?WwEHehxXaHNn(wHOH@Pft{B?ZMJ*dF&ko>_etnB?B2BLmcJM!Uvk zCU2={AEp42VRqNZ?Ngc)qma^E9)mTC%x9*nq;FM@j!w3!yW=c$gvN;o@dV*WRj*CK z#;F=!%sdLSCcqn8Sc2I?#Z=|F*Z@aiCsK6fKqa4R0#H>|tJ=)I;wcDi&h0@x*qx0J z&bLlYht;N$IRk-)5OGUR%4L@;f!#V0hzkjd6?yCke;^T zMRv82P0q&AY3UJAyk{b^-_p(8b}<()woF_$m-GQ2nPqKl%}0plP7lXpu6(&(UK)Ar zZ2Q%jj?6pU$5X#0+nTY&HMbiB;oaO4A~7)>8WQ{2OcWDP&- zRS|D}7DFNd*Z>sTV6W%>d=zxIr)~kgABvyeYj8IXn_0As!31}dK7G{q%HbDGxaN;{Y-B_!GML8`3jyY#&~StIIywli=6ZM;??Gp|^n=p5QC zbWqCmFs??XiE}J^Pn>}?NN*ih@!fFgF(gl62{ZvKLX^)I_-a+%vD8^BHxPP5GDc)8 z3h+rv0Xmvsvj8+ztq{QP!i~Q@5Op1c+lf9`#;Jm;m3t;>A}x_(7i^1xLO2$4FAkcF z0k}&r9r-F82H0A9tz$tcqC0~3^vbiEubwJ~9{QrL#Q_|~JgSSR26hq|y^(HERfLfQ z8oy=k=t7SaPy-DlBii^lZ>uhS>)0&_O+^9ljwZ}d3_?F>oB_Q>lYgv5b8%4F)YVZL zUgSO6*NukIf!2Thu|urm;HyYMFkVpQBGTKm!ELOmgB=r=SZ|KmlFDcZWFtS4CWFuA zhN*AnF!z^6!?m>)g2jZdIq%zC?)KQXx{oD`9vz(=9UbSwu(MT0@qiO37qZlOu=Z z+U3=?<>eI`3v>3HJ{S-?*gZNuoz{jJlGAF@*pEglgW(bhv$~0;h0KJ%aNran#DY&> z5CHnE45TzvMqr>|VOwCZ;stc+GhgW-_NDIe{~V-^{yS@vm6+y8qP1&aA-o<)LI zEwPa0y)4EdrmQDtBgpjukfhEwHI5YBS5+$DPg`h$uYCFh`+ zX698v98XTh_l~iU297SXY!&R@)H{sgR}evBz>Y|eJCKPZic=6zHPgYt*)_JRGF%mL z2xKqpb{KMMu$|p;+dC^e9zytHu4+99t4 zu@mzIHJ(I$TA5MO4-0t$h4;ro8qO&_P$b&mcn`(cbkK%Xhm=Y^Tnr)XQJXWMG2v{Q!HHdTFMYlzaT>4I6H;c_Y< zgE?E4#ug3gVRk0)r2dWk_3Uq|gSU^PHZ- z5y!Kt0&;gEo$F94L(Ku8im4H*s)&VfY|ROrRWXTX=*ZGXsq?Q?^-w$@kgak^JL5DN zD4y_w)bSiZnc=M3WLQ#CYI+fcU1_AaI|d6#Z&tu%3zJo?r%K*#^aUYufUAxtDRMDT zZcwskU^jJdG8cO`=b#W$7QkXFvpwyia+U#@Ew)6^;B@ex{muVUv1))Ca*X{B z3`UNcDVB5UXCQ(y6w({6Vvm6K^MnHkBn~~kySqyQ<-(o`-%D|!zP`4a?((gC80kFc zi?YU?Av7Eg$+u*S;czjzV?6MkF`V}{;^u|T+ysbECcwEz4<7FC@3Ze)T^&uQ)4iRY zgTsTvL$Wqg2nlzeaDw0&O7Ml`g)@?pLfJ4@Gux5>2L08Iv(P(I9Q;?h#y#yP(b8yT zbuwDqyZRfn>@@i&S7A)U9ChJzax}>|T;+BIJ*qDAS)6hgU!G_H%W9t6+1c6KKiEGw z5IOJzTx204!D2L8SspDfkq7tpA06!P?Cw3<+uPaSh4Inu?)La#|8RfzbpH6_<;}}i zFS5}mu#3atXa!hZUh%!gEGJ3*UPBNNXEG^$v^?D0Tz}%~6GOj=+!Tygu(*R?9vNQ8 zYdV(-PnL`zuZ+lq%Jf4c5`6j1ragiemmO84*q9tH4(2ajx`ZmPu3VzgV}EdD_rxA*I-PR$IzI9%`bh=*dpn1Rhs7{xaUKj3nZr^%v|A7yM4Tsao;o92rg$o;O>c~gwky9>?nW*!5bO|S2 zb#1F)qr5-BmHvPRP*S6pAX)!2USTr?vLVKWp}%pEP^|EE^VGd$LnC z?$xPU4U4xn)WGi0UZ=K;e}*O$Zxr|#qfY~56=26|igzi}5RNUdE)7YC`62|Y>7rlY z?Y^HaG<>81)DC=-U~YaX&tqjLjst9YS(dPfEi4=#d1FDtx@RE#>_zSyT)TSZ+rRit zTD!gd@ZezY&38VeqgGZ|H!f_s_?^IoGc{U*&_?5CgYDN2h#njjOMvPGpA$rzmJn4n zB(pO`;^QQiW{9Gq{lS%5=*B+=H79Q%-PG{Dswh<`dS463nqon?J_VrHEFh$_;%Q^4 zpf}T@GfE0^e1%DYKm?l6LLkD1381Hhs{!VxE<(nKA`BI-1XU;zAysT{ie41z6p8X8 zQY;(D3fRR+tV%(fTD2t}VC=ki@r)dFMySC|5gkz}z!88n7=_s>M%$hE}3MSGD zsv4ASh-sxUxX41Ray6BCmAefpDo+MlT!4swrM>UIStttsr~-!#LQAp*#b<6Q45-dd zd(mAwi*wchl+rj0Rh1-&w;B3QXo?;IX8zG+a{vCl+jnoRuP+Uk7w_JAaJWBV=80T$}X~1tq0I{ zGB}-bfex!#H4UaGrjsL7oqAW)jE2Lwg$NGW*-4R{7Y9pVl%|uhZLMqflM`f*AWe@< z&rW!<_V8%z4M*CAk=(BJX$MpdmzGF!h%614NOp&Z2e!|jIpCU_tT4?lwu5*b&dot&6OMB+%p2!O>)l zw$X4jolIB)u!8odpL**0wTtU(!^>B%Jb1LvFn;pJ^&3w<$qstKBx@5L9(dHoRgF$i zsTnDjJW!V-C!9=&_fi?Ciuh*=NY_Nf+Ngx6p%m@mK&DiPU0KAwh0Ho|elCIc7H8?7 zgkpOPLUUwrLfql(h?PZDzWeJ#fVB?Cq5j{rnQI7WN!s-1<# zmK!_mlP{qF)I!I6Bf>l*61C-V(+NEwRblx{x$6o<8tV{Hv;9-d1%+vhiA~$1p(Sqn z*4i`fE=uKv^VmYIvvO6fxMY=Jzlh*fr$;F?VW@G6aVka4%>-NoztbrwN0Cz_2x@zD z;1>W^pH&mn14x#xFgEZ4r?67pYn!!X2Sl4hZwtg*c%rtdk~GaM+uM)ce*5jCqob== zFWq@~|D%s@;koZ+9Z%Wt7%89Am^(b!o8-O$vlk7E?#|p{Rgr;qcyK_2*DqbVb@%pg zuw0AHBXYsc&Nlm3@7wxa-F_GN60_}e@bJNdY2L#j zE0Le3M`T0dO9SV*I^Nse86O^E8gt}*--=>$dh9RFY;0a&ndG9JDwE*&5Iq~4TcC&I zF-e{z>l40f8-55PKjlE$qEQQr1Ef}#y$_2Rkzr@;O$i&3ztLxSGe zy0Emk@Jqk&jjw$5=TM2DMrlSGY0)u-N>d2~8=7~7jKbN73|pHXj|1`m;sNvknzPgx*|Ov{phx8CAikXKd_!xlp_CxBa_>eaM^)>M)4~62 zr*xw+&j55~5}%@Au5c$p2gT4Ii&Dj604Y4`H4_id7=Yq03L}U9cDhwM>}s)2@};8( zS)iauXLK^GqSIysXp@pA(Q^Plm0oeBvD7zFgWT9F+Hh7nk(7hlW5Htwg%?|67BSk{ z%*-%oS><+mrM}b_1OKHMMh*;?W0;}DxPI8urj272qtdeKxjZ_bY3H~1{pMCJC47+j z*6L34w!o{!S?CoZ+aFO?+BhN}wDACRTdFRUhi*=u`~@g7^Lqtm0KgZag| zslQe|=ROV#B=*68jH9*eO4+P&{elLg_9Y}xr)bI znw)sDTZb^uip7zPnKUZE;Coms67?xzQ;dUvV{T=0m5`Z}9SLcMD}3S%U?a*2P7QRd z)IKZwN}sOtLIGp=869dGED!hgb|#014C&#(pv^B1mRHs`Ha78zMjq_#5!==Ejg5`1 zD_1xF@~{2s*4jFLIffD|<1E?+RUy!8Xcn=csvuXf0Af!8A;}h-a|tZd26~q-oI}Nl zC@t|XU~Qq+rIrR;P$7_*G?4ks69WRsN|iS1zo7+)Fbks2gi?K<4NOUQkW#sVMR;0> zazX8V4q|SWYpq6YAsh?m*hjShVmaTKVMqO0YosH>u@HFpmnA_1l!~50BqhF)HYtNH zkeaG0ElS3$)*)g;WR<2fvde6x$xV0T4XR zVRTtyt8V`vn^Frpt=TgB4=Dsg7M-!JE0i*g^OqtVp+qWTga7<*{+FJGVlt+6K)vL~ zZ#kt;hw{FT)ji$TRkSB^1Tx6x4h|1~@bXVTzWe9^d+d@<*aoo`J399JdKf)JGQpzv zI9*Fj5iZ-K0cqHkb#YCTG*~LWn9~ah$5+cR!+z-ZH(_P-|rr5Gg4bYyJlk+dyhFS9`}g zSCy%M6HD{2*aVY<&Wjekna?Y^-cs*h2jIOei}YFN3{dn|n**Vk6@Lt<>Y>~&yb#Le z48`7P^Rv@Qu?A1FZ38On6(I8#5=w})uFT3M82s^!cm`pY*lCr5GH6w0k}aR2 zoeAq*D@bACuQ8V^u@+@fiYgdVQ;?a2Han<}>S}TpXBHN6J0NxV*CO1+qCe+tsYJq!M>pIzu{u=$?In9o+Hh$=Gj0^o|=N z%&h8kr`fRiu9;Vsx`n!g2}sGr?!^ftEt~$!^%|!!>W5z`L{-b^OZo076NXV_-YKi< z(r#xIxNMN?z|dCuH-?5~Zp_gL$mbuQv$u(gXgapK-bRrSIJT?f(%jisk@(|}{X+W{SZ2?Trm zV-hD-EQb?+&SuOGdWr&kN6ZMf8=Qt2h4Xm>fo_{lvKF<@TUlPafA;}NMCO2zH>lMu zJ<^H*j_G6Et6E#vA#!v`@!(Ir7(l)dx8s_gj4!Tu=BFoAElf}6eX%n6$_Sw2II0zi zbi1=s{L=wjoqGix`3$PaF^-!$@Re(`?k8JP>ZE} zoE*~RtX9aCGU?WjCk(B(=bH81a(oA#MuD zP$GA*Kg$nm9jcCu-aR1ILumux=g8o#lp2a2)TS8R#_}om%nMMv-L6!FgLU&I}NRzP{$qxs#mBs~of5#hJKK6Hg80SOJD$ zsAF+fv5>HI2uG?y0gN?%v9{3>IFX~7*Hw^1%R9X48-)lH(}OXGBHQD-Ow5U})4MEk zj3yD4&j7@J(gH=Pqp5@q4$WmKCAY>e!jl==QIzjm)B_Q;NgDI7y>vTHQKv+#cnaT) zj&ez_2}9hFp?55R(cZ2DEjUNbge~=rq1WBl&H~CEE?uSJ%~nWyh&Wxrq&D3ZDGOZ_ zqLX8~DjCCws{v-onMUDiP$K0R_+y?o+@g;ez*d~)Wl#b8*}KVDu13UQft8HG?j&GP zRjI2e^ItmM4|Yrn2URzNpd4~c(jPVAB}favP#_)(RWJV8%NAsYZWx7N>c>6F#$#PHFX^ut) zpunTra??*hjE^RV$48Smn&Cn3nkSW!l2(+rfJ_Fo*w3J{$xXg+*D0CBpagnyfmIong*S#k;ayd8sRM|qZ9~~hwQjTn z86g%cZ;$S64~Ej9ni@5i_olRj4?@i&uInqbz7MaZj!`igIF;gA`>jYT6Yn=gJm5 zVZ-q@VDv7rf`zHih%PM}1L4Kaz{Oaj>O{R{m58?XwWFW`N{xq?N-8^tZSa5k8-KHL zMk+z9S33xb_O&5&NOP`hfXDPoqgx7+ss={Yn2;3SdGDip_wJ8|L(<-q`Oj`4DFYrq zzqvRhMkKmwB!F4ti8A9*vE>TSX%9PFM!1t1$OUdxiE+mt2k5Bmo_uhreUN_zS*AUe z&;i?)2@rNC3@%vf8#x2J7w&FDYG}G3C>vY_m~LB3kHx^TG871OT}uC@bs8?Verr!X z|8dA}lQD>cBPCvS|5t{{GN|BJGypxr4KuNLeC%8Q`EGUQo_}Gra2{8()63{qW|^>tFoB3v6klscA6tsU_M% zuV_NShoB9r7~a-Wie$_;-+uS+{GI>z+S(eIAv8gsM@v2-=iR5%rRAmNmC@$b#iilU zkj~AGM#IJ7kOaHVknqt6Hs1aKB}+d%7$Ih8&XXa&VSpi zr$BEKvNCx%2}_t&L$tw}DoA!8wtQRU#6fs6-$pgIGIDLGcbp6qMMfa0P9K(F*f*0U>o!{>PW(a!Ju!S~*J_dT?+r$i$c=CB?45dOko zw8Z?F9PB%v5%hxz8Pds&D7UxDUh95#YCg#yZ_|y~jQKp*#M}`et1#ICRpWyLlDM-G zlgUIL6yv2@3026pqDEP%Y|tIF=8D>!1DZAN{Sr^}>pwa{`)0g*LkIxN#!_zQyc@$>)5{UaS!7>+2PK^eiur7@Ji1Alm908c?{rysQb9 zI%eyft@Z{N+pFpHaJ)}8zjW~ut2-L-fnmmCGgw?AHna?wZ13*v8mzem+CjYWe43l}xP#B`Z}fNY zXlIuqVcFl?+rz~CfM%Bic+O16^TYjpI?T6Rv+HqipPo#(W+kMHi}OcZGR}>?BacCI z@zT=rDccdEH#fh&wt;dr2>#;8>7siMGTo5S8TkZES9?uytjmoX+p=Y(Lz7 zxUe!>U0vUK@PMI-1~wyXEV73>V&6eeyJl<7aRmcjO^^Jzr<-J)AvG+_F{YUStYo-= z-ws(*yq(HuGhh354f+`<D4TiwEd68B={ z&}^llM2Km+gmN4}7i~rW8cl}5sFCH}v@I<%Cli(@Z$5+6&h9q+4JVPaB` zp{9cZv>gE%sCGb_u%HuqMi|FZNT-KG7KhU`UzHnKh%_{YNzelyu^_H~GR92+LtR^J zDCz2a0};W9^2x&dkS!bI3eknd1yVVqRQ-f)!JF5JN4YzX!^1;zag7o3|kwUL~d?d%=TCGOT_0rFykC!!VT!dgJ5UXwq%nyo24F24=NwUAP z;+m)P01<#G)2RAcqI>UtbE-EUsHIm3irk2WHL~ng&Co1{6e1xM+K!J7OkrS#Fz3Rp zoI!xX(OboWBHCv`FzE=hXan@ip0E}Gq4wA>EU=jmws(K`k6wQFgZJ4TtgQNjG1sqN z8!atyY4GOTZw%N4Tz=y2N4F04_X!q*iJr*VI#^m>9u9`PyE{i@fw;s7W`;Auu0C-M zw!?!%=m%Us?CsG`k~Q|Ig-0ied?I)>Ii!SBu6|tNxt}!X43v!KRob(9O$y)Z#ZTQd%b6NtBfM=RsWAy+yy1Pvv7 zxVH<3+ZI2{zBU$wX0Vy{osc`{8xVE zU%Ghdf*BwK#!z*GijK=!Yn}pBQS2D9(MWBh%+0Zd`EUN)fAA0g!9QGDUSiY}B|3p! z*pPr`C7^$CiSBSD8|R_#v-))nUT45SuN@t+^KeNv3;2Qc26iqDg^vQNoNh=tBba(8 z$Jt0`y`(y;QttfBWy?Hp?@Xtor1o!d*vt+;z!^@2pi@)C>{6?NCYyP-Y<8{}WaiNE z0SF=}aWK%E!=(zO{?G^6%Nth{E2)Q6p#L0k9uFNq6znYrGbj9H?dLipL2_XZVw^#2 zJ7$t7QEbU_ycNZ@WGB{aTk7Wuj)_k)o<<_&6Ygx-kGY0+oTGMSbrV@Xe{|}F0t3e# zcg7n^qR&^YY-%{28`_iXsV8&8!DxNm!F+sDMAmZFhSPbH{%~V`la9m$4f^`mzx3;W z}{JDFwPO4_E z+504-t|+z99bm6#19u9iTobjgtsw}3191Q0&hP)x%ex2Ul#_=KA8xF!5plY2Z+Dm0 zjE|2lUA}t%_TByceKIU#h{44AytlivG#ssMY}~(lhdIC~#5HP3M(dlK8ylM#Iyg9B zU(7CmJd4G2~0lJ_0&q{02Y{qbZ>>LEa=B`=bj znWD=pt2>Xj(c_kc0iIvFPF`DNSnMY=5*a56)6NO(J{lq%?mY6fUPkT2Uty_m;+Vl? zpgZGe>O<)2bp+C?1awQG!Kt zM*+OqBex<1W<@UjXb4SHLq1DJ6)Fos3EJs3#0ecZTH(h%mA5N#uB>TPZMx@|mbpNl zU*FhdnYniP#-I7Kzwp`TpZ%x5^ZUQ_OW*j?mtH&^(V z0s=t>8nP@c9J4wT9CfmN<67L0OV{VHN#ABG`qy}x0x~sVWq=&}sc6y#n+8)4-Qfog zb0^m>Mnm4AV*n6VIt)6t;UqVY=iNp^#s@|?V_cS`9^2v%$mwZ@jfu6I3_v-ieQ7Ck z5`{I{D{dU&fzC0Skg|3(KRh0feRGM6d)CZk6C^MJKAc{C&YvH(}aljCL%6Z)mhX=x(It%%&d-wmzKlx|V(}lzF;m04m>lVmg>pP^L0Yu~3!!m|6Ks33u z$+zq=(3a+h7$$|$0q*S7uL*j(?iJd{bG~&0C9dTDHtL%%n5zSsYiHpIga;f*YuM(%BH#ndfH6m{ zPp#=QbVQ1QusKBHA%FqYfiRTeVRLQl+>R5Haya9$g5t4CVziwzhD>Lf8n*t_#Rh^8 zID3&e&$f4UwEma>>aTtMt6%=D-}>DfPhR=8U;EX=Lvv8+EC4T8IW|(Dc&e(9kfj%e zp8EU$=(m33AN@moV8Gz|{kwM$5B7)wq0z}iOqU!O#GY#cf0t7t{lZlt%cmL8mZ~4M z5h>@$faVjks(Hj;Jfo@fBiFBvI`fxD_hJyTbF}Qv4l76<&v7YWcla#TNtV)Nkn&%f zve&XoCgGBTL1E}%pzo*N6SA)z&zV#D7XJ|(xIQ|-kkoB58d~WDhYDBjTu3`rbicd# zTSno4AGK+Xjn&BU@#?_Kl<~=wr00GPUiS$t{VgzZohyi{2RAhBO*tRRoX*qhj$weD zXUnwXMgcEagV3YJKs5oA#c##*7#X5Sr$Ff@qfN$#8gHo7sDq7^zObYYP3hqri#nUG z&DD(!#1HllzV(f-{hNQ~UtL*R3O`MOY@nP0I6$x46tks`B$x>kYzc;mO#%K5p+K2R z*znVcWd?QNOiEPF9^q0^5THjM2lO{=2I8(&WmpGvw^09jAa3E8o#JS;wEbx3M?d_N z`*-h8#uFAwdc-R{2Y}wP^U@+izrF;ETsbkFIo3{0sjI8&TF#Z7p(4Ty3!|lFKSt|Y z!PTz28!Lr+F5k<~Plh zjp1Q@!1RzH2up+E64KTgB%8p|`179~F0MF4%)++DaADDzraul9N3BQx5#mS>hJZ83 zqMR2xB@GsqP{exZ9dRatUZo4c%60u2KL45LpS*eF{=NGje)!=xzVQ{Dp+o6$fWF{} zZxE{Yie5kwD4xbiy`2J@1Tnwxqo2I;_B(IcuXw`j8cz<7yhX)zt0{<=!;*YD@0V+4 zIx=gia)i2LG3#Lkgd@$uh8H^+Wd3E>;^!1hIgVEl9a$J0wU1}0!I8vr>XnK6;wjrx zvaDX1?3e~lSx2!3QSQUTWOx2RA+U1{qHILH)is&;W1!IwkRqwVR2`jZIE>O399S@B zMsvI8MU{qP8aPH@wHAb`xM`(tJiy^*$Rna$Q&wpDuAs)~V<#`7#84yJ^n_z45S?rv z$bj;Om58|;DTbmZ&UPQ-M!VAht^kx&fngL07fXwd5L7^fLszY%kGU+HqKKBWH69L^ z*-`nd2v&|xo_YGI7eDv3qn)@I{?39%oXZZ<8nE$}0py5EmF}8$GaC94sK5S~>#iqx zg@uD_1Es-#_BZ|uPNmd?#K!@R#SL_^s1POG(MhrFGG;5e7Ee(D1JRN!U<(P><;$0T z_@f`+yZ3-tkbxlTTb5sEZ0#{^sG9;)R1(l|f%#7~+;HJAE|phG`t7bK)Z37(jaanW zj2R{iX+q;S!#1A0C%!Zy3)D};EDe{)3GNpbhd4V=1|zHClIqC0oU#|Tw79rD@{6c- z8V~b>*di>OQ45OhbUa$X{cUsFL+*kiQI_GTU}==naCLQ!H6!}vP`gp^mR$0QnU98G zi-XB_$kogOR!~kz8DjF|VLapIz`^xoJ22zGu$HINH2NH7=##TWNkL9@D%?1x**H^U z%8!L=0SVZ>J|LQoJ328JlF_U_+h`z0&pr3djT<-i_V#}Ev)8`<^)KNkbJ|ALV9~6F zZtOG&@hrnq1f>wV0FGzh`Th^ydg~2(j%JWScJ}w{N5{ytFt{1?(!l9T9uLK=MlC~! z5k>!^T!akcyX0`1oy=CSGhOFSCX^V_Tu7nCd~Il;;L{OXVdemr!%5r_IZn`ICS{Y! z1fL^!`fZm;<@fWCOmEWJ_vst$Qkx$^MhPiDZ+rRk!ZtQT8V`X&j6zNOyx1kODM1Qx z?Be7E@jR?bkx)fcS-Pb(*twF-S@>mOi2-#~+Fn^rtCVwDQ{6<_aRoj9qS-5;&iZfx1A%F$XJ69+vZBlKF>5{mL)N#&t z7a2m#VXUmKt*Ui#z%upJlh?oSx#w(M{0F)K2(Z6v|*GL6{p;gHddW>(-&|;D{ zDKx+w08;*gP+Msnx?fpPnI?lzO=Q@`MRFf(7&XTv*PsA4>h+89W%@yjdq5Qmq-Rl- zM4t>C5yXm0Xjsc}P=xTK$<}48J0b~;CL(CPSxoTg`Vk*9Ua4%(FU-42BqJkbT+>pj zNWm1ce%Z8goI0%nrJ*u21+6QLH{~ZRRCTdaxkaW8ZDdxUD(RbuEGN_X+hA!Gxt}B3 z@MqXmJav;Mz4pdiFa6vL7cXv|kQ_2x;}QSS>`t^^)RiF;3V$B;u!uq?yq_kRd-;by zdE@mrXd~Xy^*g(}-rFILW<|l2mCZX4iw@S(O+x`PCk?6)<$0DPjnE@$G};u2a#T6o zIh!PP9r4m>ZALw3iwyqMPRX}nj;Rj3J>?B9s%RIEfcKE#3)CW>_NuC{EwF*Uvz}1{ zumNWZg)e!LMl?N~toGZNbWe*wrl@*2mi~%wwjgCu$6NwJC)~c1VJaaGM2Rp=^0C6K z8O5wNRPbU5lwq`~DTpR>VMGy!uo8=TayCXG!(lMvo^^4Qa9K=`xJc17U%E$d>1k#u zE6v8*26GBM2YY+#tIMDH%+uq^_#n@0?;mF9W-v0jH!NK<4?#{vf?t#A% z!jj`K(>wE8{E70cI#Sa#d?w{(5?FFxr2|vS8(+3EKr=Y@#X>5$j~x+ClN$v{5L)}Q zy0o}ZE>)~H)FKh)47HP^!^6qn{k#A8jdwrPDZM()n=|GRw0K36>vtrM77U_Qc<+5N z5?Q-~X!@tqBs5#$#gRkKhYEAqlT;Fa{xy60Wsn51R6sy4&Wdj(+ZumkXwco zPxtluiy)w!QgX3bzp!;-=g~v28WZ6R!TFVywQqjwn@?W920KgaH^2Gim6hS-Xzaa5 zBb^Du4Ac$wWb;Qy#GJKLh*4tRt`LbyJj|cbF~Yy|yMOTNYp<~)QiWq5fA|raxe~9; zX4u2b3k4i;zdR?#=>prxR$n(xPA8Kw6#8wBYnP=wA;4bGCj|1~cGji1X6S5V-k;={ zw`9GCi=Lhb1h#}wFp}wdD1hxx6N&;ec=1C4z^hobXsBY-&ty5Bn}S9^RUD~85TvA< zI0393k2;N>v=U(y)p+O(L08;w5OuU8L-Ugu*)5;c&Ly6ad}Kdn7jKTW08iBGiF}z; zGNl;BhJdRZoMgaIunT;^!v}$^%vgzwu9AdG&2vEQeU>?FRZLLyBSMM4Fo)GlJ&5Rvj)Z z&iOnh0dkO&tg*pZL=+ti9WK#*$8mB<(Konlmv88!C*P{&P>!wEUPL&Oo|i|f zj4k5;N8GRzGCq)^T@J5|LdBb(Z72g()rYRCK;UKya;DgcOQwzXmV$B;J^VzLrqQn2 zk-?93mUq??d?AmQPLmvVQ5A(`@KTOQZV2cDM^vGfW4V-u=(&2Oz*E6@&=dk7SQ@}N zIx6$t8d8vI{;MR>vqc$mbQZQOMoLOR-|}eA+Q!Dsr=EG|&DRh1_trPI4)-2S4i6YK zN90-b`96CsFlaNoWs2d5Yi*fE4}D+Cae!(D23^h|8!a!7Mt&)KJoFyO-P`x@{P6IA zB29PLB+fv!j$^qRi;h$hZ-t#inVjxaB)BJT+kAeGmLi1)^k?j;1S?fU4?vM)vyy!W zPQu{uLknpx`(?nbF|^uFrV9!X1fY~}9OL!b@GG{mu3F;2PL{5SD(D5pgCIy9OSbBe z5(!w9H;1up5xeFSrE2KPY$me-1(ZNxfR9Tu5G9g__(P$pDh?^AA{NsMtXQN1N`)>f z%V2zX7{0Tysxuf-higN6!3pKY3PUr2qO-gpCCRR=UEaLBzHtHZTzH;7dbFKKkA0YL zIP|_6@@S@#DKZ|9$y?4cG8nsKzX;V-dotO3?y2kl*02B1UV7;zlyh|$-?U{zh_~J6 zFepj^ZNgayCfV{HU9^Qm&(|TJEF#IP^%hgl2A`fB9F9M_b?2?O-+u7m{&+lbrm?Q( zCQb(H^w6)eUKkEWTyF30?b0w>`|+K72M26Cz1V~k?KF)p%HGXn4I4*x;8+^vmC27G}AAo-@($?Yc>4y%bmp5AguTs z%A_y%)`5iH$G1plkN>#d9x(iY)Gu_({LV(RwMYLchR0PWgO-s=(Fp`06qJ*Di!?y#x9m^! zt)^NB()(1j4>u(>&)W?cK7A%}268`0jt*pti-|Y2#AB`0p7T=tN6nN!p++`(`yth| z)^`@pS56OH!viE*xM!*3-$>L@@oE26NY;1SlYjSfvg7c?)aXw?ja=JYZb^oaxP=*K zDKn;V@>fqpzkf@u4`$&aR^Hv*jFozJ)=*B)P$*>=howcM`xX;uRPj4ABft#`Tm{lO z?5Gz^+i6?#r=nwk$u1OEPWWYoKWkI=hJ`*!*Nr3#1r%r8im8y&7p1<{PSbqm(+9-I zp73}zV&nW!L6+MT4akcZ)9dSIen*5}Fz(VIUz|A>{(ch55#4jnX zASNeZpqUb%+Im%Sel^_UO_xK)q6*0PYgeD(J=_OMnzeq5vW&ZER*Cb5tf8Nfy zRs9x=cxM**U{v8DJvaMcO4wcDJFdTOwK#GghVk`eK6TY&&`A72QjuYhqGGoHws7>} z%f3-R`Ibx)Lv05Cxo+E<#_gS$t{pMCjuK@)#MSW6*pd<#W6-JkP6lIRAP<$~H*WWG zuse;m9=TFN2r?Z%^na(lMkdP^-@`rVnIC?J92G2UZmOCw8ug)Rs(@wLbxkdR8GWw& zcs1|7Nz#9BBbOhB^7eCHRezsqGF>+=440vMuR!s(^yz$&o;Tr#Wp(PGgYypMMV{tfh8Fn!qbXq3Niw=Ga#t^G>7A_4VgrL#NTLS2c1X?AhMzcVrcGB_(&DPuQ(1 z^Y7$v_R&BeYB6*c-a(<_3}x5g*J){T2xXB z>OxxYcWw>r-F+H(?u3S;LBVIGw1^;d7aX^|jO%JFZuW=1vsSdUQpR6c5nK@0GqaJ5 zADzXS^t|soSctWs+>LVLf2Kvgz1MYTE_R*bib^LtMyE;lnYUs^@Q$4#1dXF5z@XSR z-0?{G_#e=bo$}o4rmJ}*G4d>^uF!m_GB8{JMF5sOs5MKmz5?o@kRyYBrtv) zZNvPZ>^$mtq`9PV{N%~ZHn#CliaVQqGt@h8(oW-f(GwMvR!+4dz7 zPNz-DKWgpYWoy+%BPWVow@I`!$>7~RDRh5?o&U+Y@i!|`2q*AfDY@-{cs^P-8ucBu z)VkjTbN+R^Vn1HE5qZ1VqnOW&h*}D{GmzV1=0gP)?~MNLW??<*6c|h6n=~R@%E=`m z{b0S${hRIUK~R!)_X1IQVj&5P@dD{i948$3$0fbB(&_aBx1WXOlFU+6CME2Zs!+w_ zj^!o4w8s!j{mUd&q)-E;_M0|EZRM?GuZ-2X*I^8ia5gnPv%VhQ!)Ye<8M306S-fyB z4u^1B-4x~*O|NYH!j?0#LP$-AWT4eG|Dw;bnV;z%JfBF`nYVlVU)DYa>m9cI%a?C? zKi##Il%z8Gm!6g`0rodY<55=0491#SVN0MFMxd)zoRL+)x)2Dzdo+S9H3L`_I#sbu z5>_oWwE>6ylven?QTTCZEHkd(z!Hl`huo|pJGu^|*4O!bPZ%Z~b6ZZKH?;WW;keusV=ue zpZ@9mWbMYfIQQJaK_91FOKt2#XLYJw?=ikFJwOs`X+N1J#Wq*ae|kEw@eiYN0soew zoKlf!_4OjB zQTgIrP2p09jxv;9tXJBW?&BktfGJ}5op$5Cv*@~-{}hzB#?G0DI5@g)EaiLtc!n7} z{&}B7J|iblkqjW|3AC4}<+l1Wr!3|D^8a!bE%g|S_1X9;s;bC(TDj@E4SFTU7mcj| zaav4Hj`sS=Ev8AmkY|3*&i0!F^s~PqsKa{H3S1i`8U08a7caPugXd5(l}TO$jU`R* zx^@DmO0Yj+6n83Nd$ftd#lUDzLm#p|o0NR}qC_y=mH~E`#v6zVqW->_%HYd#{Mv3{ za`(V4|IKF!_4JA_Dh6cCDp6t3({Z;5e`+(outQ zDz|JF_cUb}WeYvXy3eJ>H@%W6^L(dZ0$e#RyY8&h3v%#pR^&{&i4l&|6?)IKoytqY zKuLm>)=s|Amf7A)^TgigZqR?_CDqx8-eY94_`Q6>l$o$qD88zz_&YpQ*;+{-x?}Rg zhKi?4AC190K;5xU({1Xm%ly|A^Mpk#fpN>YWt%3RCjYH_waY$Tn5T?3-c}3u@@2Jb z?05CBj;$z^_Mm}zOI20XknpqM+<>iOOylmL1Yy;Kpmy1jSUK=bEk<4h#{emNkWg*` zzaAuExQbPKQ->4?P<)lr!+XP=Z0odOd!AYpVw{xiCAHq&inw zRnySe8iLvD5dvGneQ^U{V6m`+L#~5^1MBqfr5p8nRuEh%8u5QW^25rYwcVCB@Y)^j zyR5noD7fg>|MP~#>DD~U&0>#pj;U{F+yd;ESVCNlef_u&QCP~_bKY<&^n|q|jVebx zZA&E*%t6Bv1%QZv4j@aPrqP`vf!3KjZ@#C;4z6z-%&qVG{>r)#WxD>-Jsj=IcBA&<2)P2LzVdw(9;Wgpho=<_jy=3bh9anw59az)k6 zJd^5K4-@q0upV)>(}k9>YN%>zm0~f_5*aj5y*PJL2*zE^9xcNGIcMVc$~V@>^xKEz zw7#52=8e82D0Jgj5IblgkHkrrj{ty5w$e&`w3c*tdNp z5qF{(i8WE44aT;|?(X>%~^xo5uakj*@v1WXYx9X$HgT!tYnEcftF2J5JY{ltoMW#GB^GX1Qh> zckS#0cCFWFA=^=!hxW{Nqbn@KLmAUO0#)}zsyyrgDclW~NTiU}O+AcfZtJ8#RGnspz9)2dcTES*&`U&&njRQ!>5ib?4~ zu9|@e!>Py#B~Z(aj{oD@GlBH7Zs!VFyPsAz zJ7rf5Sf`rKO#*JQz9MX!4AIBvMt<7oCPNN6@>kA?r_Bw*@3x)J5{e8|ea?W2LARm1 zfRlW{&J~X|v9Q7?;0vJJ*PA7c;uVw@@0xlz4Wea6UU}<*VLOYE@O?tB> zeh21L&bbbek4Y9Q|4p1j31(1isuAKcXs(cko9exTt=nOYi&1XC<-%}L`O^RtoYoRE zUjlTam)@QOa+7v_pBx^UShjj&6e(a!eIs7doG8@6HUD4QU*gpx71KX9T@}GA4JS)p z2Ib{ftz#=kM_5!_f)|Y;YOhR`MjL^}5AsvDDeY}|%bwbVM5?NR{+9kdI5JT6N5Ma~ zntQsr<+ygZF17e)I2@u}4NiY~P~YbnIVT-1dz>g1qv@bmzx|j!^z)A}hjTkU<$}RH zb(`P^|Ajr^`(u2<7u&`CZrbbFBafSixQ0e=2ib32uf7y9J!ObC8+nyiP}dtuXJRs3 z-$cbTaZHXrTEbren&x4TqF*gjUe9=qSInC|q*Vg0GuRN)C#gCTAtRR^wI3jpWEL;Nx0+ z@9=D;sR46nb-mS$YB`(90>Z|EX6-+*9OYJ-N6%STD4PZWoil(o40GX*qtJC|=hKQ@ zfiVHla-aS!+U=czX%TZ%m4(X={mgDBnD?S=Q<}3TmN{=$-0E6BJ45g|wYMGZB*e|QS=RsYFK zS}5)fE#HWVH6``Hga0zVtgnCUboV5r3uu;3B*v9Tv1DJ6uo{HlYsvs^^HO z*e$@tYkl4k9E@?XYVchj*e`Fx8-(op;dc^R2`Ae1xIj<8Nbdp?4(#Xear*y#=OVqD z(6a*U8=hpdQ>8}&H&V!TMv;VNqxV@c8wfqIZFRlo*oL`avbw%GGgxjo?L3p0uvm~x zE&r?HwZ4_A$CfVPZn?C;isG!;RlX2%EG*dE6oQ59k%^2<>%kz%#v*siMZ~frMUNlj z;~|03Kog*jo^bD$>&tgs#MFKd4U6797my;_j@IcB9&*ddu&5^bm6%NYh5D!Lsv3*f zUDpQ`jtrrePzJi<_oxpT-Pg~rSVGSea>O2euuW?H@oJYsQ?*#hj_7;g?z7}2WQXO= z2~s2Tpaw1Db4m01S%IIM(;w$o{emI?@AX4qv` z72WA&1X$!CWky@C8n<&>Lk=5@z#&I6qwte7KPq28U&gI?Skq&_=Sib2I@(CvP@#O4K$pzzkr+YgH zEaGMp48^(_m^b6QxNywn2XvD{^wYGDXmz_Ayn~xs{7+#wQG}9F6)gW?FBk4)upzU2 z)&u-6iB5lV_=S*{QT+^InQ&1K!TcI+!EBL(+s^1>cX(%08@Axj4z7``Nbj3j{Ha9S zx!0&F;b0havyE5`sHq-$*12`%ZS$SdKY{enqe>Qpp~d3}J+Tr?!33NVC;(T=6M8(5 z{2h}}-Eyb>B#Eu09CAT9sv2}SvW!I#@S}Saq)p-buQ70b&rk$n(ZoU#X9V43%7q7P zjzppVFD7OA%>Nd#<`7!xsQb{Bmv);eo-hQ%^vW1m%$qM>4%h~bdLv!!+NU=|WklL@m{KD6Xt&7yN1?kIU|27$H_@Pv z3E(;=#;u@RgD|J`i0htm<-i&!>WIXFwE5fr>FZ|u`*Xh0yRp!CgFYjY;QnLp6>9us z+ll-a)5N3Da^O5)(o!~{mVqX`!=G0S+77l=%t>owO;r|Y3())dRhV^Xx`w4 zq334M;~>PM61TH>(gfpH)QV2t$qAKpMIu9deEcOXn)C@RVdvu9*vWC#Xek*;LT z@cmeq^m_b_MDT9UsAY3aWnE)kKWD~c=K$wj4?jPM+r=*l=m}t7yxZsq4mt4}ZM&e! zDqPe^u`VqKtDbbHj^F2V4XKfBYpgsys2)8!j7I^nlP9P2?rihNWq+>(ZD+JIDUzPN zi7TVnhca&5)!~pXH%+*-HcK9vsHXmNck}JVjp)no4h*4{P*bA7lUGw(6Av|6|I4J5 z?u8Fnvv+(#{6&o&uGiJ`-R{@oTcx98r=|I9-kHd?OEYQmH_@h%^yLS^e$VlZZ&sF; zJPO$6g!n?$ueGg>*9Tss?tj7f<4qK2{5(#~CR`-72<+K#bz}zq$a8f*DK9^p25az5 zrMx}$-o??8;72%CLP3sszLc9Uh4Gx-fhA~lZ8oFpKsP(;S|IhC>lFD63NENWrCGeR zX(lx#=i*9tC(9z4U7Glp&?cyJo+r}4ylUQcmh{sd(X%scSG$(O0`QP%&nMDb_OdPC zb?;K4yrX9u2PuWDFbjIHfUW*nODJlS3pZt%Uo@e%wC1Vuc@hXa83jRs4jP77Sh(pz zwcPB9fM)~;AuleRS1z=WPO@mGkj+Jj;7h?_>@os-RI~pc_wk}9tUj<%`^`kxaF&6q zyW3LJ#c@LGnKYF*jqmQG*_i0nOJqmKFhH!+gZn< zSv^-^j!ybkyf9A`9g`rv^gxFJ^s*X(TLw01IkYP`t1~>aT(!ePSK7ty6Z~yMmfFV7 zU&W=AFB!YHW^RMuNNWE+t=o4BvH91U?i2bnp?MZ;j=ccZ60OH;j@tY`3vkmBn7Gtm zwW&P4w3oiw111WUn+wYFSN%X7%{=g->ZBZn93$ayILY<)cH7BjXuLTYN+z64l}>ip-7K(y!C=tya7GDp(;#HE z0d!Nu$~x(W9Ey?$0b7>q9=*X5k*jdhlCO&t%5M^qJhvGob|rhSaOAXrxkjl(2$GVi zPQ3M^7f1^U|CKsk8_Q(rf7B1}?@&U8G}P^(@8S=NK*$f@z5@r#g$ zG+i8~QJ{zh{%5ign^m&oL;3dVeA4vn_qhKoErty)yvTo>tV+eL$Z}VAU?TrhUVgmh z>+q-V+3T`ec#oCf)fSrRg#{V$)bu}IdE^`7EmKcF9Pg#Zf+G1CsE%;U9G)W1vm2hW z`Aix0gM%emW=sGxZufB&X*z{`nUxT^Rq)yZ76tDTWuuNXf;F5{T0wW`i*kiV(#tJd z0uOid6MXBr3Q1Q8J0pG}$0^HjAZ9}~aJNUo^>69X;eljKypVrGLv_&A!hSjOa>FTj zy*K3wgU52MqOzGf^^2&io;~4)-ItBldB-d=a-L$Wu|yW(aBZ9VTX3DEsH+RYr~XZU zkSwZZeYtmogF*253r~raXuIN1l5q z`k_1E2pk-N-7P6^11u|swCoJaVY}c(*9P`|c zASD&ID@`s0f7>^6k(TS;yV-izhZUMyT3zEO8+umP0Ok(H)u!ws4WQ>jXm^NmW|n)Y zn8ku=voEHz+Q4%2zXNOKl@(;CyPdwV203NQ$v8Qxjo^qss83H%2jQ!`IgF$8@D4u&W0tR z7?IgB&`0c1pNI<^ll)9tx^DD7&;ZZ%Rlx#}owAUTB>Wx2luT(5TAO&4SuVorrkNk- zOPW4?FHfo0D@zMM!yAR|g@!LCC)So~v*i8IwB~&AFLmxx(Um1R>lD@^c^}qPWx~Gi z{5gTig!}Ovs-WJmsV^G@QNpVu=bfm?O7|E)f<)u8ik|d$ps&dm_jaj>N?= zHuPUxF-J;ZIQDvEWF%*?9@d2K-rAa384(ZSH|BB&*$D-pkq~wTg*oUoKo$txFGy&} zy;LD${8Lk;Ovda4Iii_MY@Kgq%J9~myd$7p2&#J3G74=#9gd4?MiNJ4PcRWF-cjXw zVVT0K#|YAnF#9|Cf2eJR>*l0OTgfTXI5!U=wZZpr=W@7&d~uO$sR_NXh>Gi@@0DlN zfltk+wIu1#N;)MJ3IP=cbeBj!1a?(!_G0tvizoYn60nn@Ak#q?p|g+|rE(ulQ1o<* z`II5Ug5uO$T*?ap4e&utWtD$UFKN6Ny3*^uc zdt)2m1F30|wyT*;z7F|jti@m&!^kx6nxqX_B&ITmvl|&f>Zt(*;-<+(#(0X*{uP{INzQ_5th&n{ureY(ZM68Pb2kox8>1Wz=DPpo%kNaM14pUBd zps@$X4Y^I;sgJkDyRaSsw7sY!Yr?9MY&U@tMi{ap3=*zKL(U6OKyDULX3~X%+LOy& z@PgfMwS=8jYg?bq-K<$5ZEQUXvHi!KO~`zehRY4K&{A;&wAZ_b@(86RSjc*ogxlZi z#XMO_lG-?Z$Y6tT3-MsUF$}*Am9a0rbk7^!`CT0HBATr|?EzBjD*<+M@Ge;taF83I zx5A%p*VoD6+n}hnW-nC7>A(k{i+=y1FCXo_Fat9KaV16#-7O*Z``4S4=@PDAwMr%_ z;F4wRecZj&Vb?1`s2dCvGuoxo8nSnNQ9C`p5Q!-CT90AVi!A^EvgUde$BP8rd*o5; zLb?8HS9Yf>ec<5ZaX5Mf^IhcWkN6-nAfnpUU1|gP@9#;_yVW_@csbi&9OX1?r|h2Y zv6AdtBStxrlFYJh7j(EjzE3kk75Mw=-bemH@3Orq; z2EX-WcaVnDC}f(>5*@ckm1uTnJv%ngMMQ;*L{oInv#3@>k>MF`IG2jbmHf+ zrn=T6nRg*5;ecHtu3r3{kWx&*DL1D@tG|s;MuzmL_$RZ>F_^UI>w6|KCK80D#LbT#5F(0k{<%kI4-H`CX?D9x+PfuoRW&hl)X>TesembAVo;#eMs(4H8LB6x3;QE#{ z(WDXfhbzP!O{C#vsquHjLjLsTdJ8<39q}*3H=P>0N?|2g+bL)t&ZLR`B z+@P9AWxFWIQu@`#@L5~SNutU6%d>A5{7M27B`C;!M+6pWdgvWE;L4r=*+x)5EUS`v zM?NgT_*1CMUs_%@XX~S$goait*JC@+IoY>CF3FGFg1QcZ!WjfO^j>P$S~(jpE;eG| z@MYvp813}%Xt{WK(qE?SsG^kqxIrearB*c1JsHFY*La0|j2X$YGJcY4)}7B+Z$@4a zvFl~9{1b7c>>o`#cg`XqUWHo5ZAk>%9{C@yEOJ3MOC;R?mNrICiA)aj&=Vadt*(gw zGvZME>-ucR+9!V0a3ZmS)afRs&C#xYe6YL)zjd_I@hdi66?-!YBiwjF&!Z%uXeE&G zvhf*qCQ%{R_HoNcpZ)99xYB6`Q+KS%-^i}iaVHnZMd!@SjrBiGmaO;5q8})b$POeP ze_7v#(*xRZj-vzBv!S@u$6P}j3%*b=%Al2?4eZzCuxU}WM~9iLGzkCo>1MQQtM|z@ ziqPTr6|0PmeUglipiDm-t~$!@7c0>di6Rf8?Ak!l>SH4pEqXbiH$WkJMiLOKJ$nT1whg65$yko;nP1S z)=ZV;x}&z-dqOEiyhl=W&|7vf4JyZ54zf!F(7Odfm=>y z!h_J3*m;AHZRph@^oFesBLs{$D)hCgk= zihaXgA$5J(JzJH3QtTLvwEs&oeCwDPorC6HL|=4&#+ZWi|Ej`B#vgEf{q2xA7c}0- zEGZ)x(-7?p^_KYs}G9|DesNIU$v-( z_R`rAc|6%J=ol0k)Eite=%W@%{5%MYKR;CcWN96%&R-zH^PKGCn}a(SzT_vY2ABO6 z;>2QiR7ndbDGGE9MgLYj5lD0fY#|giy2jP4r-x#9{5A6y&ilfwLbDz3<Tja-LwbD;d7g*W$0PUIFJLdN~^nsS%Yd=SRrNMu&=2GZVfKGZL^n@!-RlskVvkSO_= z%K9@)!_B)71)R0!+!>55;m%f*4?kB`PBRbx8bb>)VSy#{S@G!C}eJ`c5?G6R8QdxD-FKQ~X zG7DiccA}<74kr0G&Nc>DTL$M`Nm+NPNRm!Gw@LA*+AmVnAB1(i;^-LrSq{H~UE!M4 z+}&ZTmXHE*W%J1I$7$&{a{Cykf`s@CiWt+GI?iaSz5XyNv4e3sm;J1VfcD>paa`fPBPPu+J|V5YUKGUS2mCEeKJ3-7U9LQe&Fhu z@%OwLnv`!lUOR&xj}oqi>sL(8O>88ox5x&)ibl;>8Uk%D>^yhSW@2Sv^TrTdh9eLw zJQXnrSl(KiFBn^~icP+u+Q4;DR4LoVkX zL0*_sd%*=P7_k!K|IcA_B_{}k2lfa4=yfw%PR?Pj((-b5H}i(;?pnJ2%ZdBrMYrvQ z&c(fo6}~sO9WIMh?F0UpU?%;&bplH<_wDM2TQc|DP_GmwKRZqR4(ns-JpYrQr6aB3 zMDxwGUN5G$2d0u4DE*2%T-t4wl*-+{zgK+}*_&;};LvKv^HDnezMIM7e=_uaKku1U z&dWV5RM5zA_iC>l>>8^&o5xarjc;xB z0*V#NzDZ0J`Y3n{Kw(bPTlHrgj$Q}_8I@Z!d3<#73yKn<7tfKeo5{ru0h#b@=wr8yV@7{)i589$)mAQ3mFZFweTlqW5*(QnOd&!wJ` z+1Buh85?xPf64do;IPX4+JF}b3oR@veB;HQJ@tci$V}zp(ls}39)bAvQPws=W6EuDO7#y%B< z2a66wkpEM&M=m{$Vd2u-IhThxSHYI-`=2tkcIZxrgit(4*^|}DvsLOUQ)cIMpK?;&|E*#!I=WUcie z${Cgm3)d6rPHF{2Ydz)51_)CooF9lPGPUbqfiDyH|fE_Pd>3I3-C%dN%ymu#V>xf=OZH4 zQpEHpSP8_y&nFzy(#YB{2!dhR3nn;P8sukhdwyO!_|>j@#QJa|1wbJ&O!eXx-C*yG zlpEODB)NWh#|=DaMc7Ad1l%kwYvqqG9!#I@xAmUHkE|>#%mB9KK`3}_0J3wXgEJit zBE*6S=UxVIES?+;C)^U*0^GAHflslcmA{RP*P#d45j$Q0NEQ)@R`4GcmE|S#`MJ5^ z{T#GT6|?E`lC{TG{)BP~>MXf#c1F;c>~}mFui9Y7%r4J%eU!NC^9kna)U$h!9Ech4 zsV}?S;{qq>Cy*)a8Sf|jh%Hp|7R*`oVs2@MJrbZLoX!aZWD{xpp{So1Q}cQ!b!0R< z!vx807j6H!ynI5=Yhx`GJNVT)S+G`7*&taZ1h_AaZ_kC4ij|MO+s^`Eyvu5U@kQtW zL@0~k)+%Z9tA$ahi;w;8pcTFm9CEfV4_0kF^VlYbp67_nibL^wR;yn&doP4wfv3fB zwUn*`vvM=40NxDfS9YxdRT{dD5RSv;IKr@0Z%_pZ?tt+5PGib|(~}sA2gZ+i4xQ<2 zf3O@5koVt_jWm?D5v{w|*qPM%+b(DaD;7gl_4}!^a~DTq*0av^dg2({<0ivu^~Z^5 zXtY5b{!gd8jHm!UgDs$oj<+%9_p>*#ijdTo^z`Z(*$Q?Tbd>7HTbv(0{s*ffTYVxo z-mCxAU4rZR&#((37dt6%*wus2U|ZHWO~kLCT#uPYFC-SVMr0GG)L}m!n9-sT0)j&- zep%$?{4%{>bHOP^z4RXvmcCqPU|p46L_0R!^yhZiu^q2>Bw#;g6i>%)oK<&Fhj;2P z9*WjYHj+T4YqJFRhz*>W$jr}3_{xuFu?HDtr&1c9ouWg=F=T-&%p>(Eoema%S{j-Jgf0eQJa^JSw%aAEfLkI2erWAnZpeZK`E>gE;*g$%$R zFG!?dlRQe>kMn>#&cRqGU{v|+yfi@-KVZ~aQTZBe$MF@H^ybIgLQ1B}kNN-X&fK&` z7=QAAiXb_DpCK#>6Jil{-^ia*LIeBL1DcOBLe2B{^Y~Ac#Y*TzdT|P;4o|38yAq^_5_v68J3Y4CV9b7#*}E`sl*>e)_w1I!Q}XlG^Y406hWjZLvGU>> ztT!6QrPd>ftWO<6GbMk?a7VoFjZTtFs~BhUm3t;sMBmHc%%7RzIYRI6E!f3Gy-M_2 zgJmftaPJTP1Y!z?jnKmV=54r+ix{ji~6`SMcp7H?z;;_BL|=DZq) zJBHIDY~S_N57*YlP1hpF5>iM)>Yif-X~K<2Mjc`et*w6-N=5BbU4Jp2ue-BWjTLCC zus}K2NZ+ly=tcfI7@v@)ckH<$-lb;ESvFUc56|=M8`{5araU3~?Z|v!MxIom(gfeDAlga(BwBX= z);gD4bYG3_PRHAZ5Q6 zGt6SBK}O$$O$>_K7^{J*BOXvi4qwC#PftH4)|1KRa?my7?}(LQqFsB!n^$0Oi4g}P z0Cf1hZ*e&%$(#>N+)uAF4A5Yz^dWBIDTw9rp3t%jtF1lQVbUr<4h#T}J;J+BNdo_fG)OU*iI=moi8iv0L=ykSVYKz=)jJkwe@qX{~;%To<96QrdKU8zVInC6{-bG$9EVps)Abq z;3oWDkjCg#fMR{6od5OpZE(qu7?qKP%EkOBomE&k!}OD*VXND}-+O}sYp_mOI=Paz z$^gt-L=h~6Hym}<*;C?VO@LzV&R=!`G4BH%M;qe>N@Cl`pU9#y&6pzrGF@8eo-L|Z37x=!~pN#^SVZ{EVj1&L$m z9^fAt9*b?QZ*&vg)%+wbZe$~1{k$O>lT$rb;+VK)9C};#0hT*Gr1vSmO}MLJX>0#= zUx}gq3u_}&(LV1Y!+9EqWv`vzl<(YU=KMPj{mpoW#iTNHnXp047eQP4gFo5oUw=h4 zMJ4*l#={(no^VXcm$;M+SvA?>)_~yRl%OLf!T~G@pW(OyIh)4%sRAg147+3idp)h+ zr4?pA%iK+}76^a5>VC)AK>0HwiWb#!F$1J1gY3vw&;1Bj2^mjDRR}D>4PIEzMrnEL z>@r;dR=VUu?KwE|Xr0}b+7*^&i&JTt7@F~I(D z<~ix6WQCq|oMs{>WOLynrQnf8(onU2kv~H8ku=1~& zovWH6ZAAvzXB$M>lOK4Iv#PVdc6UGZ%S_izcJlNh9V0c0?-(29C`U%odySxl>u&14 zOka22U5NK;AkTcTJDVZ%QckWumvFGn;#g;Gf1At&a(7Y4_?3$*yyJ1;$#!c?Rg>ji z7PiQ6D5zME{*JDyyNU|t)Tr$xN(%Dfvu(U}<#nJ{MA^Xe@L9tdp%*)unJ*l)Q*Rcm zuHR*1*SYX_{>)Ety|n7`qe}WyW(8fF-_G?(@~Kk{|EI+NBGXkey2K!!nhElG>z3+D zK#d;?8FHyYMX|RHgIvxx*B^ykxL5)9d8zvDMQr_Y#WI;Xbh}UUcBB+YWDZn*|NSv~ zJJEm2b3}|J5aSPl#MQxZBTC^tNiqowlPMR|0Q{KfTq$YX8jLHRu6>NU-e;iJ`14fu z$}@OezN~%Wz0A;gGuk@qZQgoOc#vP6fq~Zg$$1ed1as^$L^_XH<`AVqfw^vuqdJ1-~^un;3!-J7MqiyYXdtYW0$|&qmkaQC13)X_0 zBPjXj5xlj%L&*I;{Xw^;(po`lM#{1#QU$(t4+p9_qq^9!hUfiDwN|3UR1ebWCuK9* zUvDx>4Y{6Hao_3PU@?#7PoLN%;nK1CR~ zt=F;aAdxRdlF!=a+PvwMRQ$T6gddTzo|6-$q_o&f3vktx5V#Z+{$y|O|4q+zXL_s0 z`mRtVZe|~ZJxKs)X#vNVF5nk5LTvlz;fwTtp~pz_tNjON=H`5kqL<>(iEn`%`6v57c}w^IF&{Yb7b?UfW7?#obJZk}=8pTQ4m&wSN|pa&@<8 z^2hA;&ItGwe~tOYldihYX2xd5)ac582Ee$E*lKU&+UB59+2(FEb@JeC-`(`GzizH& zVE0n6oW ztDqKLu`lZQF0`MPE-oz%S4@9@{@0)pEbzLqlrnuxUA{xBUb;vyDnv^5&N7vPw7C;5 zCW}XR?dqFPBu%Ht%mc1l*=H7_vh7<#US84zD*tZ(_`<^)>oPKS+p{yed(Zp5Z^uXv zX8|P{G;L&Y_&BexF~dY(ecPn+2kY?5A+@bnT4k=DOdRb}?~L=4$#fOm8sw6b)pU`x zyi-Ye0aBp}b>i{N6dNRGW1UVRYU(!3$DZJds@4FEXAxCU(~N_E-cl`#dl=H;yyNy~+<7s$GsJsjTuW>A;wJjwN(P7t(o;<~D|tF!o>(xdN4%C(%5Wq<3B~S)NvP30A?MH$Sdz9kFvUHgki5o z3Bas$wNxtvUJ2gncg!UWZChS1Y`V;XRk0gwco*nNf0jYwBh)QgRs7Y=VsjAI)k(*( zAa#>gH5lx-P51Hl&rg0-I$sruyb2TY>0lqSJbir>li3E0fkXO|etxW+Rz4lj17mFs}bgEH*sQCG3gU&B^ zt8}{b;=&IRY|-gq7h-jBHt;Dt<&G5R`#>N2!+{;N)R8$H!o5qsy8NGSYD}YS?$LY{RJ(RZUq$ z-Nb`z0%h|#RKHQ=<;LakAwRnikehl;I{3$JuQjt>zu0!UMca1f3p~HiR{{nX^pOwh zlT)6R`xXpDJy6U<#HP^58S(n1&3G!a~__n#sN&L#XX5y*Tj7_GwLdtZnYV8?4c{gX!gYi8G-HnZdKU$v9VL!s-8 z=?I%{O>fhqFWE03E4qK1&7<3$I*0ftGn5AkxKuBYO0!b8Y~%F&qOUWvh_3fOf5djV z>!7!{{rvncFMW?;VxxfM?Nz6&4VO*P_qjrC@Q@La}yTTvvaT6vXusp&6ve{ zRn-i(kWCjW0I=P&YQQ12fnA=#(F!2ruG~v^RavlPcB^oWWy#Y`Jp(DV2Puu z4L;k$Xap2R(4GxyH}QRoZd!(Ts^&}%oo{4^YdzuSNz}N{VwciEYU|aJVV#9N*#Ar~ zN9HQo%B)XA{F(oo7qhcx?k+`+7rGzQf@<6I*1N>QGjkyyX3I=#Jxl*s1fj-}1=+39A6#i1g7bgmcnR(ryRb{q`umbNr<^A`85LovDZWZVvbez0B?9ked5%cvtLqCj)vG zL64mhT0zV%%he~szGsK6Rh2%?Qgspi!O$X>I1ku<7yD8aWV@u^&7?YUgdOxTawqog+7s802DXbwIo`rPvx}CH$;XQGs(m_d=3HBI<$YrVUt zBX@{Qozxtohi$rFvtVaGl`-(zyq(BRPS*eDKXBW@SaQ8{bu5-Ve#`6e)=x8ESAqA# z4rjY>9ee|Q-9H><6mb%E4ML9F;pi7}aUJ$oJ{!lOB%>e|mB$vshNq3nV?hhaa0?1M z|I@4at|$q{=gj<-S#BfbHf-OxBSRkXj5q6Tm-BHk~)C_#k+&B&H$X*ONYboZLP2{wK;zyK+`LcA3(Q$6H1+tkd`33rh4Fix^Ui zQ|J~Y?UCrwi~aIU`XF5IK^tHE46b{NskiWx-oC+1xJRmPfHFA@x|W26;;+yQ68FZW2-gncY)d0aO7o!WD|XLH4md_No0wuvCz zAg@!Xu0B6Q<{s6tmA6$rX4SWs5eRZ(a9>xA$=o4Q-uV_1Ej;trz0HBZSgx(4Uuk*H z!bQZM*Qn9@O2^0NHu`AU`{JEa*DaOXB6mYO9tZ8r_k4YI%i!{8@pQnf>|o!eN6?xm zIk93WAck#={o{_<$_M^~`8wy?`u?MUDK*+JIWz;zPdY!FiyJ*;3|?UjrhFPHrA3*O zT$M!C*B~6H|2A3=}O!ug{)4Pn``L){YEKTpk*!`$PmTrB=)*6A2Hq za&M@&e;I}Dp7DYjPZl;N%5` zm{kHO2nh0GO;rZ2l~}`;P&i5~>rR=?Wpf!o#bSwUHd83*t>?_&eZ~ zyg<~7rA%t3udny$ku#TvM=@*@gjnYi(BvfqqdYP)d0}Ys#K|+LF<@NN30a0!4MT}i2g11Sy- zT^t#kJ#_TcLMDfUmFC+GK-HlV{;#Ob3FTVL;lqa~r)EcnM^ROuy;&Siax9niA!NXo zN=2fRQzuT(&SlS@AD)|^w_dGpksx9j322fph|HnW5#o4o$8PIgERQyq* zvQgeFua(bFP0l>^^z--K`>Ww$LgVI2;|qRPQ}xiGS}L^wS%VkOA3J(-e0+Lze9E@B zDLH7uU@@WjCfF)*EF>e7jhi=4&&&^9z9fEXmfsW(X_Xw=;AzVB%IN6m+BK_SFYXw( zQ!EygjazCegVVMc=%@3q(M4+SH~51-t#dviP+0$81{$BXZa|jr01hyKRLSP^mxqR?CMO{Xw<4EUuLElDzCF2o z{`iUGm0A-qNJnd;t2423b$?rHe0q8&m(9kKaUAZ{)cn}w9A4Gy^Op~g6jr9o+(v00=5jfSU^`6!ix zGJH^x{D4&;g9aF*7&RQP$lI@DrWR_KP915BkO5W&kWnqd?H`WAbtfR!sd(>j0CNY& zuDkz@pn#eV?8`Ose+TeBkFlzxRo!pRLxk?tyo}in(N?nl|~`z}hrEI`QP=Pv3k0gY%i9UjQ{( zTmnmv3?T>!n#ZT+kDtBx+`;38qBe&Spklc`uMbpF7!hK-^y=`)Sy#XoSb~!hB(JbnN-(UU>SsgM^&05$=IL+(oq-JaQI6gjm@P)%yUAZ$F zi@`QW#Zq#oCg_Ic0#ZY^UDX96qmf*Gse~9*u?%NcfVR8Z;LQ)yj(oNyso8ac~ENy}IE_w;m$cR_zNk;rFKlVd}Oo;U>=;}<5zM$eo)-PzgA;G?+1sLiAo z(y2LcpaNE>LKCglEzH$v$q658;*%X(5}9V(jiji>*dlA!%#>3y98o+MtNwpm(E)nq zR77I1H@&K!_(#+R9!g>a`dd>pp;LoJbAdB4ag9P}jg;xAeYLu!BOq4UmD79)fu+h; z?);XgM=pA`^5u<1qlg0y*3_0DgK-K! zZVaJY96Ny_(@eb-s;)auOj>anA`%iTf}<_K-JKipPFG-(oH81vQOktODI7FH@JaB?^IQvam#t)hfCQC~u3Wx1+14 zt<~m9a>P#0>B#veJ!DlZ&>#?vmRmfjT!{hJ_C(skvCTh7)GwAwnaqMO6zm>YGq8SZ zC>)bNHMFTrlDCzKX}SZs*jhLkj>n=H7mm-&TwjIIQVBw}1O_;}%NNc~O-|F=Q3_0s z0K_P0q{@1uOVJbX_pe;rw``^64W=`6ZDEzzOf|eAO;9~-ERk&O?&%BZt3O<9@YZGM zmumK`s)qK~w)T$BZrQSpj*Cf^;TQ>OnCVAjk-lZiIyyUByiJGz!>4mp!WoXi78AnZ zD6B@m$y1Dm*gCIJ1yg>UtC9ZHtG+0(;dF+n8``ROrKB?H z^MixLbLTFP>C=IF(|L=biO&14zGicp{ZCWkpVu++ef4h$@3PB%L{FQu_Zv$X=y+&n!qtv5T_ z2BuE5y1jFDW+J^XThhDNnq!HMi-W_hNo|mhL}M#fu7Wn?in?foH~LXQdXW{{m;-rI z50j5bBX7z_avW%ADnWr=LenU*tP+LPfg-2ejyW8;q_$2qt%P6wbAFYf%WF4qjAs6; zC9TYWg(p@=xjK`UXcf!+1%E(RE47olfeZ~fRY#V{yAtw(X(c)ud^*Qda!w7}+BS79 zMNuva6uJsSDDvZ5jr-(-LB`Nflc%N0N9b5fv_|UH(%j4#^KmS^yQjOer#BYs2nHfO zy{j^F8Go&%tE~;_v}S;fg~ElIbg3Xv@~y@|I?@QPor&|6azWHtV9w;m4P$jI#NHAO z`esX_i(w$y))DXrmMvf2)zw+8=yiXRifN`3ghE}*gFJ~63)5s7oB|gmRJlDYo6Tm@ z+UFn#$|a7jFFI0>EzO}YQ%(t8mxPrZG#JWxf|$05NU6XQy`@u{lXQ_pZMj9cT}sd+ zy2T|0gJGu|i{+XaGuSKililZSk-Dn*)QL5Wj>>IB%q1`a2V1d8O~Mo-iBtc-;*okOErBtXCYmB?%Bf+{OaLn zo_XfXnbYSl3|_c!@#M+V$4{J?nwdcipsK#Wu-RWPHErFz@v5t~o;h>r%&D_=eRzc- z9CvS)YY9c-XvXIX&ajG>Gb8{vzJE>9XiD99z}E>mIMUkbnMuRFTC(#Dvc@X4kLwT6D@ejl>`0h zbo%JwV>JTJYAIVRUA#P+E0maF`@F$26A*iW)~c1OqLFZu-h){$SL<{0b2Bs39=+Ju zTd9}B@o=TiT*hCn>ZO*r36#mUq1G7s9R5a#I3#B2YvdB1iY$?FWK)fD3#k+!$N)^& zg|YDvgLZUL88Rh%5hDwK8IxrZ&Z`4kK!9v0*d;ycCw-L%)H-9s45=hc^h@LjD8ow4 z9eNyHhPu|Hl0(K_A^|{>lTMe+SKt~Hg*n=3t8qw*%QQ-Fbf$!Zg9a!(jxw4a__>Cc zST@j~P0fr94>L#e1-*R(-J7>=sJGN7CdWsIF74U7Pn*(o7fNqh35P<2S_H!84y#BB zHUbtN5Z`GFml&x%Hz45HLRiCy4D%Xknd4mKY z`Fs|?ffAGodEGd&g$TuZ=E3c*T%%vahAYyaf@SlSkVB}byY#xdOG4Uc8r159`jrY@ zV}2pZI=={hzfbqcEdQ5hl(Afu$7w$fcSz2#jK4o(59r=u2w zcVr1Z)HlN+@vDUN8>5RkL;-B^#A69l49zc53a`(vKtrt4>IY0PdI{C_j0s?+qUZ)d zuuJ)Km}9{#Nju84egbY(04&T05pXUPE8`P0mo86?3{UYlH#dj2p+bU22Vw#fplaW; zp4)G~u~@48;D`5QvpK|}p+>xfPx^6uwv7JBi$0k%pnz2O{DIy0dRaXs2f$@q9>ib= zT`Dih2@I$Fo;ZH0P}C?FizW8#-hTYVnfbZ-7Ow_aD&cleqf}~sd~)otW`_r!6maMZz2)fv17~XH7lNZ_Q2rzi&zLqqs^qPo7eRA zbo6%j&(6*1YtI!ls4$c84)j<;r7%D1@zAfin+c9dXnr>Rj)TZ2jnxW$eVd*9KWj<{qU?T!BAeK_z#p zx`sKR$cwZ^nc`>Q11d=&hL+b_q~4o}8k0;jgrmq&LpN*)Fog)Hv!iw2?p?lsClZOD zJaS6%U6?<5=-|P_2PP&*j~zX7=Q{LGFYKqJsbCB+MsBC*=OL z7z!KgRbdiF7Joxc(bCiu&=!c0o*q%Blp`T6o&twLFroiN2^qAK9y0+;ye*gTEPBa{ z-grQ0sYsAHJCH?~5d(HKMdhdrCIG=Hk=InCR?VB&ceK!%c%rQ-GJX>1Ato8PVa~uq z21=k>H8tr(hZ{iv)sP%rKnZwKPve8VDMo=ajzV~7wj7N{gTWw8U>`uBl)R48UX5Ya zX^Zhziwulxu~^KmHf6HeGpA2NJD@bsdQee4r^h9fEgVav(+f~7_RC}?1$_$5>!Evn z5yW^7m-J7mW%;t@Z-2*YyL*z~_{QC5PMr&d!l>w8y|**w7EMX2XVQXDRF{LetpGuz zE*1XUK3R8k$rZZf3iuDHmM2rwtVY^jKY8*jGkt(gPfu^%wr17pfx`!nK|IjKS?e8} z%2#WXQ?r9-2G5>7d+OxbQ>V_4j*e%t1-)I@0ztr96TReR)v6VHuh=m=Gk@>B4@Bc} zbV6{LC${)|ySj_H?5UGSCq^f8nLI`^HaU0U(kKH_i_aenN0|FzNqhF~N@ogFQ&UJR znMg349eDADN<{|RX-*bNYY$zECj;MglMeIMKj<}XH}G*8k}=4!MclC~8u#QFt<>yB zaT$qguAWZpI==>78e>T?%`;c5C70C5!0LxK@|bp;hmHUM7%pj?(-18P{FkRz-aM>g z3b{pt?T~6D8d{kOIl5<=Aeal8Ogf*-B24TVljAy-ZH>|;ny3RXB&l^%y}PUZ$}9F# zjD1I=@n|GAHa0dho5>e_=Prz$K67bmDjf-hd-{?+U7cExg)c3hU?_a~^5rw9&o$fo z!WAh6f`wdmc6NHx<}LV=qlXXs{XU$5qXIm^WQmzd3NBEO1pL^(eftY9JfF*_H*eln zF4j(+I3e`R8)8%_DvdOi@OUB6!J#eY2|2h4JQ_*`f8}ko@lTuBmFGWxL<^WW8C7!# zh`nBqUf8C0rWh;bWjGRWXlSyvUDzpORuG3DtZAXc{`k+qVq2nG^BSNAlKEW5^{Za( z;ZeGS#Yh?0z(Wuy5xx!u0vm(Vh%Wh0edu+j0a$rAd$R!v4wJ!=0+CkYo>4(nI_0Xt zmts(tib7I!X{Q0~t~WQyQ{y*fDsuWT%?Q_l3iNJl@uKjUl7mKb2%#$V1j`~*5TqMl zAfS8s#Gdd}1DM6Faz}zKGOYn#ESYT6ijj4OH#BNw2J)xJRrY`$QRLMe*WfNb*s%lJ7@&(9%#bLe6k5Fkd1Y+D^T!Q$|Wu)@>i-@IwlJKp}f zHLJV7^Sxg_^29U5CHP{D?3ydDh=rrHGB5%{SH?{s7#Jz44F!tZEW}c=U2qxF%L`os zh%2%)ej72=Vi9a@nV-u(^zhSb*RFWe8(*upy2t~FPI}UBwK?d)x}%s|wWe>h`GX<9 zKZsqq?)0{n7Jnoh?(gs0v1@B66!^tGzbq8XZ5=&GlhA^xr?{_MrEvB{C)2?pI* zG7(RZQurP1}o+e*QrCQQ# z$HoHvGY>1GESa)OW26ffl91J0-?5VZ#6P)a`335{G(pj0nlIa&-IQNQirr?7h8>!!tC*$0+R`M|94Km%T%P|_(@`oXi5SW9 z&h9ckh@qFPd3-Bt90k|P)ev~v^d|JQ7`JKbmfmIkJ^d?)^d_bzQt8y}{M_J$Q%^j6 z-`SHV1EF9b;0xNr;|z7}i3DB_#|I<;FmD$<`V)BLhNyRham1228WHAdwZ4?UV*kDy zUh#@xI2Z|sCMU<3=_lfGr_$gCc?JzgO*Ce{ig&Q)2n7$KNhl>4CtS0R+zn5-q;fLU zboQZM)w>iNXl5)b7icAlNpwOhVe3L*=bG)h{uA3d5@@bMlJ1^WnF0e!ku|C)#)>B< z6vuFL{G|eXb9U<10p%i*uLcag!qp$tbFTq=fDOdx7vy!+77NfT+GDbMNS1yHUo@)ObW?1yH+zvl zPw04ja1d7u;l$>2EgywMjh|R6Q8WCGCz8TSim7qP;3zemmn{k@W65QlUChnREG*2z z2*iryx8m0jnY7ulrWqvBa)if}ie@y|`U5gB zzzo`f?(VLY1Iw?yZvV37J@?=D(7AKx5Dwu3Vv%dJq1fy9ZQQnD+wSc46l)l9mn4mTOvQ4%4b*CZn+A&V}^O+iLWOE459oQEFGQp~d$ zX-WvjohljWt`r9It5fh{&_jaMa#eNEf3Awj^0U$pPF0^7Po;$LVG$Q5$QxUOneU+N4u0m4-omDO?h^JhltrbL=8f`kLjsq2?Z zn(9g+8@5EDyJ}#}12X-qRtP`kM=JG1IMN!4wzjoJV!^TDq4Vd?T^hPLJ2yxClhY#w zO>n(Endt56@OhgPu>{RAO>Jnbdzf%zrHryf&@uqMLr-_NMI^~cH^S95C(Pd!Dvk&*^I#7&4bf(kpa90frzxV}tl$+gJ23J_iR7hEa=A5XdqGXC_VBWeh0& z*~>8~g3mZG0P#n-fZ(VPEhZ7T?jF^lBJHIN(9BiG7EP`#))gkg1>S2_mnnkw`O?td zUxW8ZB-^5RskZi5JQ0b-!_jywo{T42DFknzqLHDnLdDjO&eqlrt|pVJOkY?Tg9MRg zE=TB}N-xYKWm_A`frg@cS*li1NH|2JMf)X)#6?w2Tg0eg$O}yxHJWI~TS1{1T%pem z4&bA%Q6ZYs>;Vdv+l;aF|_ zllI_U0PobE`Wx4+dFxy5+`VV-iq&gc+q#0GnBN!nc|#nNtz9T`Yg@>H?na}Ff z5@oKX%b3zM@@P9ysA&Ea{FUJWi4Q-)VXJ^O8jqCR8-P+aF`o!Ze{PNy=p$#m+70seUYQ`h6L~Cqd zMK=ycO0DRx>hU%I;%E1!i`6=e&?-n%GSR+&|E}rzX=(+0-uBiw?Vow-d8RUPl&iA` ztzj@fNxhvs;*EA;ZbIQol|i*08>S-wbfJ?U`4rkfd(*2RKxhfkMWk129rtD z1R_oWg?q1Lhv zH7ToK6O-ob_)X4ei+E)VZR3{?3lpn{T>i)5g`S23GX- z_4W4jwzs$TbanOj_io*`dHc4_S6s34)?4=O+_5$k^xyZ(C;s)T-yR;FAPj&L^4vnR z+3#!FzjqgtCjc5t#3c7?I#lPJ6AXtWz2Y>J$2pn%H(EK8cP*DnRA|#t8)P(|h`w^Q zR4M1n<)8fcmm{O2a9&%}Xj1q1z0I$M$8l`EG~_N!k#@~a0P)bK8k>0ulOr&2yk7}}m_UAJ-Nt8d;{%H;tF zG>ji4|KRujcr2AgP#_R$@%481fAlxscX8uIdYH zO%;vrHn34D`jr7Gn?mv{j)-vRCNaH@L}GA2H$J>ROnP|elCf0H37iR_nC|3r8A3nY z78D^DW43_1j_6M~*g~6nuq2#Xyx59-ko8Mt=aTR@=%IY5xoM$WtHBeDLU7G3+BQ;q zBGe7e4hN7rvDy-J$Nhk zFIS|Q4UUms$j5baLK{egz6FCcUq~&`kZPPdg&{*@LAIezYNS^MTKrhnO=?J{8g+y# zn7dINLX2DsV<<6d!PsoT(PSNx2}EbmV}pAWtGq?u z_oNk<5GY4NCAucYrgPJ9ll{yk%W?cZa9NkDcjZME?2g zH3*gZ#Y-bcj~qL6==9jwH0Uv_fh-Z#4DwpbO2k4R{lL4I_w_-58rnbUiiwpZ)S(?o zSkltW9}>wrHY_H00^Un`l8H>)2`B*@x7)dYfCk%;JI}W-$@HSTY?pnWWdDqCu_z!>l zvx5f@Gtx4A(gj?^4dc=4m72W;La(6PykV6a0~J1-U>Md=__G_-* zD-Tr3$D)B)EXrv9#FLNLoBY9WxTm*2o6DCfB_dgGQ%fe5%I6Ev3BgWmj^vj!rEW1S z|AZ2C8duE~HmYzYrXdF7xV;>Nafyc3P8HPfCE(7F=v;QF*}b|}Md=p3xN1^U6GtOs zrFNhzM4+4IY6WQLXiN(wQ|8ZRA+EW~3?QI2a|r5V^awSZ%i>R&B(`;Q(gp5Mz?$_g zdJ=j{E8xq3DK|sv?QVbND{drqpeD)$OIq7nj~zX6_~>C|pwOdSL8&*bUAcDk%C4?n z410QJJ{nD29=d$s;7NHJq1}W_1tua<)Ng)ynjQ(MRHuu*eVZg6lt6>F$QO&C2t?rFh zE<9A=ABpL!*LoSD-Wf<8w2|p8qmf1=Ye;|yK=D?uaE#K{JvvMmlq(3t-D;gtwg=(# z?3O!8khUZ#DoC%i62UydGK7N`Lh71rdc&)dg%HT6ISv+jkr!mc1i)y_maZtl44O#d z&CM8&xF@%zn^eRB*-RRy(Ie#z4qHo*r7!y9Pe6>PTyoBxn)+{v3$$yfiX}%2iK}n` zJ#;53H`;(oLRUF;YUY?g2DXS^W18HY1`x@VL~+nET!QUHsj;~3X~PPA05}>I>ycVC z7LCQ)+Pjb)!-EZiM5FS1mo8p<{`u#gdH(sQpMCN4sWUUvGZ!viK6`%f;Nc@b{>gp! z|LT$Z?tAd~@zeQyF%a<5zeGWTCq!A*I;`=wH1FNBGZEK2|47CX*}F!1v0A*7ncIC7 zU1(|YeEPGWqn_1PB14;(XI!2n%V^A}oB=dx4`j7={P-z+RdpcLIS-yV5>h(Uv}br6Wou* zn}fkXOPvS;c?3{{r=NPdT=QTnealuT1~23jtw|IFk5DQUD)zl-qd;kiaQ-U;ClqRk zaShg(E=n=Xz3H2oDiwP%5{g zAx-2AaN=w;~`2lA-2$;nbSTgg8apq^J@55?sBmr^<6#LV)(p9&nzUoum-I zLl_G@!&yj?q)B9&>b{oBl~?Se12LwlDO1RWB9UjFeCovM0%cnnpQ-QYec#_JcQi;(BZjc9YNCpj47%@c3;IgJETyo{qBqLB_ ztT;(wCYvrGzHkIE7&a9|kyVysvQa^oolYXr)OuTCZ>TC2!$ZF zE(LAs>g)+ed^@+SlTu5qp*g1LW$|Jgj5L(j`^3g&J$CM{aa%oH0Rl zP2_#40=F=thOXE~Yt>X0tB#a_DYqpCQ_#Rg-KkvpCG-ppj0D7%@Nq{qw8XhNJJlz- zLYF5o8Zp|J@&!~6Lxt0&VxhaIAM2f&p1?c^>j?S`?8_i{+=#)bp1X4Y{$Ril6oEUoZiVptP#uADNq zPGdDY(T9`{M%%?L8 znbbUkUut1ir|AWKJ_C20&n?W)f}L)N<#YLLhT*xW?=ad%+M-@NAd#6TV6dWNG>Ukc zNq}ytWix0zeGz_kbaoR(o0n7^3f4@h2u)0s+5&-Z0&_QYmcz4g!g*>E+{5J?S1G|8 zYMY7+y@4-A*v(C)iF}- zs5u|P#ePnlJd?@gT725WOu5#rwCW6x7+IiJPqR%dU=DFt%9yoC5`4h5lznwq|1|DMyQjtviuF_JR{03-C!!{8c; zcsl~v!zF z?B>jz%>&B$JeM-U#AL(}zOXQx&*juDIO$ohY9@^no0*!L;AdidgtkPH3~#!RPxC@f zFTcvCGpU7KCIvLS-qhq6J!)cvsI=iouUU|D%%l+$JqdG5;Gn@rH{x{1vTOk_g(OoS zi5@isHwsH~XLT@#s9-n(K(Muq1X@g>9z9acng|4Wp_$Ke$`~L&o7dh0dM5*0^az|b zA&44U_zA%E0pLL@Ys5mhy$R!YnbJ>C}0PeWRtDwe7f<8xyp^Ru(5db5lf zO9RV9BGJ*_hWu!B@W8W2j~-_9B8+ux2U+@JSVKAJF`Z5e2a1dgv<$Te9sGN9y&0Zi z9yoWOkLfyyXcf{{z8wu9Ow+nPMTCTMIo%_YCshI9!j6)H4j*qFQi+$H$pNN*BDEgv)VIJ8qbOLfIw1T zin0Wdw1kXM(AcZZA1<%DbwV~zFc9`bg9ZDVOo|Nm##K$en0A?yEu)LpQj{tbXz_4C zE=j;h?#FRP3$^C0q;o<;Z;fgu9KbB*=Vy?)w%Te+MHhimxd~c~tIa3?R*QdO9t?V> zQi2WU#sjUJ@gok(Z#JS=J8L9PtfZ#PHh~oY=W+>7VT^n)23lK4%}z~@%*{+rPK+=c znwy!P93P&V7~wcGJv}?kVQPMMW^Q&ewJ6=tW$$@8bMZf=(Njz9cJ zIyGnhG?T>z&d)5Q=JcqT?hWdOE-p{DpU+~huoTxIJnMKmO_^+ID$TLErDh*2*9ZjB z@R=A$_?s$7Uuvr$H!U!YkO)(eB1TQd z^pT1U_*^k>VCw6V%L|-k=!}dtKn*le6FOGNQH5FslNBjs_1cPbl| zC=%FVP5uBJ6wiPG!Zb&mx83pTWy|{&dbRihvZwd+<*(;V?igfETs?0?)*ttRjEgI+>0qVD2V-QlOE&4be8i}DP@Han21Og&jfwBo2 z$rz;$fog1#a>}x7KR-yRJLsrt?nd=Ov8a2M8q#Wt$i2kxm3+}Y1OjUbOiHCtI10mw zEF7vpmy%Q}pd~|<$~EXvD@!yKjbeg(DoIt;za@iU(80EWbCVfi22Ns%xIVhWIl>JK z;A}3Q*B&7NGVY*Ylra1N2R8x-80F{@XQ4l>oan(;b2xH2#MmM>eqe%-na z8`|31`d2Jpxq5Xp9@TPwQxnqCTe-Zx`3!8BqdN?nu!^3M5^~R^(+Eb0+Uig&1_IiI zV3DytH|rQo9myNPLvkG@7s-@U0g#de31R6U?yJI>Xbh0}s3SNAgd}iMT#s z2%MgteDQ@BeBQ{zk32S?NAp{iKHZ=uw6B+Bk z-7{PD1Vj4z$i(;rv6=DG;f&iQnkdpr&KI%xv=s&r=&c}$M#o~pSmiAY(VI<-{08l+ zX*j!ND5wXGY%aRwXn0wD1~-_ZhUlTgMsC`;Kz$8E70pSlXSp+zXJh*jRj6)G#wO{o z$#5WXs$@QgUsos?rXrTF;<2H?_$%%UA+VEcv0Hou@Y$4kq$Ofn@3t`BXl!n7@9OUCS=OpA6Lz+DcXju5hoTX{nkUk$o3iOFVJko! zx?+ee2ZFx}Q5Tty04^obX5EuP-82rWM1LxTD1*g8cMHMC;P8ik1hUr`A{Zn?Oazif zj=Y0fNZ@4cjtNl2UB!+ZxJqbvT@y#unb(qcZBqvb9EZhdK)3Wg4uD!Gy>(pTj|>kBGXtPPa>*8Qr2WR>pcb?ojn6< z*5Y?C3$6T`pe@lv4urOL7fqL}mDJK;ikV`dB}&ADS`C1m-F;o%{qY!x$v?WQj`3xw zkTwgt5>lhBol@DlXe2Jd5JtF=-jf|@ZB2G`c6wTxG>7HS?)$@lVA!4n35OYhWE*mP zkgFLIENk!RXlo}9UJmP+;hS>SY@B1z@&N?_;k3{NBmv(+2)gMVys;S+8$p7)p4Tw% zM+XdUM8qaQ@x(}|OX^0KZcf*lXr>2P>}H)&({P<6tFIZpZ1Axs%*B^+;}OnX`~d6OX|Yv8j`}&4%BuNALj_@OV}w% zODYdP_{bOj=5G!jJmw2VhDXOHr)IDanlUIrmV>PDOs^fXWCWqa3-fdR%a`rBa@X2T ztJiH>-`&&I-q}?z*WniIQ!)Xxcef|n+A%Bo<20o3BE~pI-x!$H6JJ3S{{!P3=FSXA z!k#~Bni-Q30Y-zFsUxeqUN0_XS?8Xwopu%S7*YI>WdRP%?#Mid%ED{fg zqqs20W?~VGCu#2Y1(vT^)7si$iY>aNiHb!QJ&xfc@#rZ7Q&Te;F_S`z7O8;h6$&}x zeB9cmjq7&r-ld>4qDLj%EPx}f9CrzBmi577Ab^8OvIQzSyL+h*{F$lA(V@#s5W;co zpQ8)dMQns{WS%BCS~0c(7Em-1(}cWf6h@}uR*@RB7ZigsFcdwch8k(t!J<}JiK)HI zkX$tC5-q8uNt*6_zLcy<1E3}BPF4-OCglwDu$cQ|ua^1lsIU5!>4Acy9hy!_e^yO3woTx2zUhGV}{FwIDYtn35 z(V7bB)O>1gCY#C=85DCR!mv_K%W?oE7@!iZbiYFHNph=5ioMkut16cegQjF|h|{Z{ z9J6&mev+gkiW+u{8Ke~nN-}yyX5+JwcH30s*@kcfAU7bK@kgkkmh%?}G+Be7nI(W2Chclc2SOAk z8}lgx2e0)?(yv2MSOseJKp}~jl{lVeq9yxpD znWN7;N#RH<0j*RIM%EX3VlbbY}9%ot+vyTxM8e7N2c;&4_xph3d4 z)Dq>Wu5eLfo277dQJr2|6W5zYD18#hFJF*`XiGTrt{G6>u!s{CB4rnWgmh5O_*y?VFxl!{{V5OTGHBBA# zFgJ)QFtVCLUIMG+ zXLhdYmh8+fH`*(`RJK^pu9yd{RS_%~!PR&r5m6gy(ZoS8MKVfNWbOYu@J3!pE;T`? zMKguwt1PrI=a|iAa=9$ZU`uI;uRK3DRW20LGn2Xb>CD_z5lb!>(m6C+@}q--cE%JD zHp4os#|p&rN|h*uUr=R?HC3MHW|n(0_HLY8n7J-Wz9(pVzYB7!BWPqHDk zTEXTqE?J;1iFOmLpD2$m$l(RTp%~Ge#HGoEb!Y0TK}eD9~8z zMnRK;G+)jR|43C$ej}l1GLdXev=RzNW7^yewKOrha8?2QtH+c`XbEjioFzQHYF!&w z#XpNYQvd+}^hrcPR7i8LkVc$>H0g{$o8mwysPDZ;V+;(?LLFfM(NZBXMQqf&M#ULm zf+1i{zvO*LKo;%{i&}$H97L#k`SS3I^yI|E^wh-cwC+dQW`m1U6JvV9 zAfyk?fhvEXlqOu7omrTfogN>Z92?GRgf8k1)`)IfEzHg3b9uk1izpWxIqKcG_+@4r zOfoP`aj>}s1r`zZHVp8W_KG#8NTx6*aA`H3!Pu!nHMLqsk*HHmOQ?XfMd~L*gc+`~ zs|jN`Gf!n(2@FhwGq7Fk5jz{sdnu`_mnY6#fi-Z+`ax!SnJhh&E6tUvM|%O3kOT+8 zv8c*5Y4pEHt@FH`3R9u$)Ls8oM|5dAAXU~aeXZHW5^cm~>(;GDIq;jwwnU*&=<4X) zy=&LDZQItbUDemq)!p5P55>u@T)T3`%H^G1ozZB*=OtDSgO<50EnpF1IHHK56ww$y z@Likxe6e1xGD}gcr~n1_mc#(*pxtVB&cKq|qQQh_&Gib7v%v&eH3q}EC`U($ zzU_{IHB$GSHrQ$dvIaHFJ*Dx2JD@CN(#kDimtzbm{!L3v;Qod|fC4F<=9HxPygL z!mO8mz@P58CWOReX@xu1KQ_kjyI4~W5KzfPt0Y4W4RR3b#w583c}cx! zH48_P4l`)KFK7!>R3Yk@*V7$BWCf?p!%89=<|QT)2kM|sRC8c$T_GQfCfabUUELjB zJ-AxX2uGu>?VTN6aAHLymSEz_bSj-*zzxy~R-v)lmW=2^PKQ|7K3kwUu9qQ5kCwMo z>&*6hdU{r`0OUX$zgfF(<5u9)8`v>}jwjoKwifJEP5PsKhYBsdftMcY6(xF?E^})5 zt^I0r8i~eNt=%xNdR-#f&LyT3h~GwNq%H!*4(X9LP1DkxnkE6*G7xa%p>ULL4H|9e zipu(gEsioCOLlbj7mAhEw%$UnsQnIEF`RyFy~x+z(G9j}W2#DSOQD<1Jx3Me8Sr4o<^O0^dwk2BIq#%pYt{l0! zBhchjR^UE5CFN16TAF~ZgrbIrwY+>0*BER9;SkX~7+7^BAs~}gO zN)iLY(9I1a4PU9*s~JB+nM)?(p+I zFrLfImC6`uxRBQih!d^JTrNFy>HHht^p=if=U2bN;ukP~&f)p{))_dv<8mz|kXq>3Z``{b}S-we6<(nHp z0~HH%SzKi*(Bfe@Mt_;;2mGO2Mo;BxIR#Y_#|0L(Vb)H-NFlP*sqNF?5~o~3z+#(y z3Iq+$=kpknY{YFXP!!_BXW8UTJ9D80AWc>6?S~@9C43N(Ce?rj5X!+0Gc%#G_V%9_FCT->Cv9Mo}$57jcDh5a=W9ge`ub zi}&eE&*DKBnuQ3~ZrCzEJ3Tf!1a8y^FobXw$-rN%(t|^gOQ~hkISW03pmz_Mvuj58 zuywQ?)KITNzTDZ_ooG#@Q*#UUolU$voJX{ULJk_Kgx{eMD8z2ypvO(MZrH3{`C3Jg zGhqzDM}hf{-TUX}X2B4NNcpwwuC*hV5yH|aeo2%n2gA8ahVF#oqJ23IBP>%oQSgxu zy>DRIGSO@rXwyH1P@IzNHdmc7l7^hpra4>G-9sE3=cZI7!J4!xGIf1{gR9{B0=gR6scRdJ zM4=xYqGl)(E#``oBbTqe@hbShU@zxet(`vpBH=Ac*4*R``GWOwDHI7Ok{x(hbgf)! zna?bYk6m6!r6bX{HJdhLQ8QDMjGSCe&(Eb(Oib(nCkWSjh{=c@a*kj^saP&{lLu?c z5S3K}Lp^iBHMpZ#Oc9SrGQqhitvs@l&P5S$Xe+C;LB)s_>#d4nBnok|02E3T89XHK zI7T&&E<+z=jOQ|SSE7!!N@y{=eZ!7o7+t~St7SYzI2>KJVil27dSRC7+vLP}I+abf zcF@t>+%(PtznQb|gga=aXE+43upA8d65-_J$Vec7TdBckI_>J|i$?>OFC1UFdgILW zR6L%z;ij7j#x4!bKJxIR1ZLW(Q7+A&S0s=S&ch3OCPXYoV}`a5+U!gpGKk^s(|1;wrjY79Rc5b7Q> z7W`J}j%sqqFhP$Zlv?Vt5x1WMjac$$NES*pT9}h{+QK#E&9tQ$=$QFdGiB{hs(}>-OqwVJWL^Lfwp2EE%t45e6v=9ZQlps+m3A)U@&ePy6WD24 zQd(eM7Mk=D!%F1`Kltg;(6}~9P+6$kt{ro!w4$wb-=t03u7-8uZa0W-I|mg&bHtfC z1Y96MTfM!_@25vj%`c=T$3}hLCI-u7qAiw)xA>ZJ>2x%f?CkBE9375_qg|by(MWjN z%KoPwf8^r%Q6B+FDGM8lWyKC_H*JNIR4Uck)0asv%uO@p%`kodU(Q4b8cIwnjC{DY zggEmBieQ-3hiP@Ggl3?%QV6|`#mk7MsV&6O+N4KQHMeL~`~(P^r1gzdxd8^3(vnwwrR zu&O^8^v=)EKt(*-nvoRZzDpH5(^h=KQV4^v_< zk{uWrxapQxKlQ{js#NQoLcbNr-9H0a}+IAd-o+J06~6est9ICGy&jVJ@!f) z?J0GEo^g{CfIAywFcpoqa*tOioVWm>@Lzf1Fddo(|=V|Kd?IVEC&My$4wRLm_ z!r}hzj*S~Pg*1)zjSLTe>+9dDRP~qd_QcW{e=|f{bp}1>}nhIlc0VQ`{51;ns=b0ZS9| zMSZOv^=s^o#9RVi#rRkPKsyM3{fvt?e3v@F10W>H#Igoo?ci;wsnF7 z6G`ZW&kR3^29l^|s)+*XG#-z)w{}d7j5O8rn>MWO=;&mCu2xEV5IhuGziwSmZ_nu1 zu&2cri^NZzIrsIie2uxWRISD1k3_n9mZ6g+yIw)d|2mdP zmYcLUnIs-+s6ds?&6?e++-?bSl?x!|bX2v?khrvV-Rc`(amzRU?Q3~GNvX*byu`0E zi^bic_KX+s3N#4paS-rRTp~mPicRsHIN+ETXI&TA3>Jja+7hSVA7D%c&mi)c}dC33V6d7PJU$qpf<=s7AO4!=Xt;kpT$D z&hEBP{r>Mg{J=v$|LMJQzRjM1UmsQ>1d>{6&EF{--D#4Gsp2>31p~hA_E%nY_5RQQ z>Hni}yow7W^cEo~3c|xH<%?Oz`Wj-e7hM`>K^vdd91O`K`dlIDhF7K+5kl!pTRqu!AuCK^SP`dT?;sj25+nR=u!ENfXwC4JaH(oO~HvOf4`7$J9IA8@R18!tk0!fZiE%+(!>h=b} z8PCxb7{=^CooN-oT&5*!3QbLsXygO$d-uu}#0qk=jz4fnf97_P6Xzs4lDpwdk*xRu zN9aq~=*L1!mvJSG)pD{L#pP5GU7=JilnD*1-~H~7M#rbIYC(~J=@qrG8xCeCR*rt@ zAAL#1nws>E4Ra`56GoN*&PD4~UGqy#rhB-WLM{X3a4eoprza=I7!nzNtHnGXSgdNQ zm2q=kZ%^NfHLC|YJK7m|BN5;H%=F;k=-k}=*yI!ruh!&4*4uaOV^B_K(rs<+XxQN3 zIR;2!UX>*$60HoUus9Zr&(CXxD4kA$F}}Wk`AWDrIW>;d30V63mc?TswDrRI^Ry0! z<9JVoZm5`=9PeJ%KRq=LQB0+=rJ>7%iMG~FTXw*iv9XaHQ?2~>jS-|}!ceCE_~^iQg3!+YPd0Sm{@ zXiP8?CXmo$=9LOA3}+p*twpGNv6wHH3VL>YVq#%o0Ux2=GbJp+-`d_aH8E-y1xxJS zbd&5HmyVNN(Z3ST%#05OTgt1~u0g3^fz3bPz+Pl8+7hlkNbc?(af~T6(5NWX~1R4AS zg}P*?(90#*rAxXQC~exaXV>fQe8X41_(fZZX$l2nfuMF-%4(aN{d!4L6M75;aPa$> zO55DR!*ryGT@Wb2E8viUOY{tA>_hgXhk}TtLY`)?`DJe+kyM}BNUta2xr(09S1!lA zo45(Gt3>xvd*>-?AS-KdQX9;nQtsR14fz9F*<*xea$}znL%uY||H=lmheaa_BgE=8 z%eQXcbo%tAGiL__0XewVwzhOC4K3~M9WyiY*rx&oq1PM;C{7Or1Bpbexy9Sv)f({n zPMyEt^9Gt~`WQ?k9G;tB$mR3VNHiD<%%$c*Ue=v2nXeXcm_6=3nTYurbG!;3p@nPM zBVHjG2tbm?00toy8@le-9vUWK1#f;FCy^PRgn_VLxbDv$thpd^DR%5k7}Q{$y*C5{`Ae5>L#{ zOlzsk9~c|G49hz@d!{GHWAWssZQGe_A`k5R@}&!BPaU6{oI%0bJG&>whIMPfLSsZj zuz-Of7QFoSZF?rhMhm&rKwsyw<$c|~J#DQ?QZ74(hxIixhmE$k_nsd-`^SI$>5Id2 z8k4IvFMcE#Z13zru8O;>6=ohN;`wtY?)tU6I+Csb=YRi2EFLd6Ybqmkkt#|zrQDoK z|5Zpbqmn*Jqs_7ztWjw)XlYkh^3VUzUom0GWwb_wN+_nV_yv$~s9M#{URl0PMHMRv zL9NgMi~@8Ub|Dn}3ra#?^oYe^Xkbnqxm=-S!8P~^2jRo;oXKQlU3&4G;tb%LCgWBD zIFWo#y9T9H3X=s{6JD)~U>gcKDz#ckafqPOJrEEL9*oM7a3q_}!#TZGP9O29YZF1h zr|(pI$oLDGqrO{3pH&Ql;mFAJ_=1Y8(+ep^5Zt@%oq>+>*ysodc)b4kg$0N$mhv-m zlc|My`h*`esp{cX`KNLf(O1HDtBD~JtI9v0D?lPkk^o=owafu4R0aWt2gSJ zN@%(n4u?P!Mu9`I>_;S2O(t65gS|~yOfWx2ea)mv0Hd#lv$E+X6A8_Fa7{R6tpRGL z4;QHb_vJX1)3WVHKK$M_t5yO4ASyEz)ZPxm$MjJuN~cgnw{A^VeRBboh6LC0e!00y&!tP3vCL+#PsGVJXnhkX&Z!CqDW=$Aw8>_;O1bM!5*2l1 z<M$;x@bj^^sX$^l*4FM)xjs3c&f4<`+qUh6fFlQ=FXnQ3#@_g-!M|S5`X{}U%^0$ULMjrB1by11Ak-2h<&U2oKQ>u<-hDB|c0^@9NSjjb3&Uk0%);(H?XO z3nLmJzGISvsUcgig`fHC0s_(}|IkR=y)Ub5);Ax)p9M%#jooAa<%Absi8c

    S@Rdp-?shD zxpQYtoi;5T4nFi5x$Mb)N+PKNp~% z?M@(HRv{r%j{hm3Z&#f{qD_w3Tz=QC{dy6D*Vo$Cykz0RL?VGePMtCZ+mHR*w0_Na zp~NKg>(v6wMKMh7{lt8XNd2>U(JXe3q>X>4qqeb)SQ&pXc_^7Z%kz^tLc z0VW0EaD)l?V1FOs08HnHVz;+YUZ9S1(<*?2mu=-I2pb(F9{`I5_H(xdfqX z-|w_Si)Ae2cZig0da8?rKW@@grfQ{q6GhaNS(0s5qJEjcMr5q7oWET|X!xr_^L$px z7$!~wR2eFYF>IQ~d376C0diHfKM)9qV`vB++(;J$W5dQ^D1iJjfab@-*yF46TzJvSK%hFEK-DwEA>jxUtLmqoeU*Ub;)^dh zbl_m;iQ`0wXFx0aa0e9-k|CZ2?f6)7@4KKd*wGUwP8>UW_|)lc+`-8co#&i$-tD)&E0Z4Ex_!%daiWlk zSLCyc7tQ~~9e2!_IUVDBy1ScD;ni1P@9P`t>l^It8u-pPzO!KI{B$z?;NKn&>kUN# zy-M6>x%lie+66YExzII)6>ZoP6XFh3Gr}R%7*l#M%cWb=%&#$p7-f{xF%A=BlH-UZ zo@>WkK}$OPYzRE49;AgwvC8M{d-YX_$t?GRi!MO-_w3vY z5GX7oszdvVC}B8QG8*F(Y@rcg?e|yJ)i)#(dU_bJ0MrCkM=(t!n5a#}qS0hB<@W($ zF_THvFhy=?Xl$(a_y|P$pb~!L$dOKZ#mqrfU%;>TBzP*9ESMkkY0=yX`~OY!Pa<>X znl!ik$%D5NonbEDQfUVh$+f2tHZZ?)UWwT~6TEmjecuC*B$L|NgQdIfs>`QLX`{m4 zJ^Q-4duB|ZdGyG>^Oi5oWpb~q-*Tk08`sFl9(x)`>qJF;r%A53RJ`fhOCzyBwlKbT z-%-MtKrk>g(3ei@>FNI7(*PHWM6zi$fy&Srf{qRk%$hxW@?^$o%cj!z{^H*HXoKHV zHFx2>{@&q(2M#V>dG@TClYzbKWY^A}J7&+FH+$v`WMSX_18ZJ;wZ5qd*>xXK6M|60 zP$o!*VVH79EK10L6bb_{&`C70no=_C3x&vWB*Mf5p3;?^r`8-OF561HlI6{wYCH=l zH7*CZAR!8C#RU#ZmCm%j3aNB;h|wd>ag!+N4Yh$FkEW@n&PLfLTn zdZ}r3RVb*psS-l~lb#U7P15zUp88^+R`l_CLG3kc#m)-rV%xpTENws5dP| zyHjV)U;Kj~{dl5OsH?97M$7(EC2|A7A*l;nATF zeCVHJ4YfXRB$*fmTEc~DPcWTM2AD3}7E8%h`4MtEC z3oA{@=d~=LHwFX<=<>OYh%B`dl@tR?z@Qcm5*q5>zw>!?XcjhzUuT}H;1}~6j9?Fu z(NuDbAw*}794r}R24VBsBgG(23@clYjuwbvrOudUzrH}DbvZ`Vx|tS1w5yj>BruPS zwuv2}hQm?j{~1mDB>#wO(Ozdv!m@D$exWH}LPZ1>}dzK6r%bI)FUl-V;X+VY8EB8seItaznrPTtUHZVg zZ>=jY@*?|XJ4u%gWtTxVJhB67S&6l_F_o-pMWHl7p>k&XUAbMF01c!7+S{_S4j9?7 zMEZAsx-Xs5dvmcYh(0Lgve|etp=}~nRZADlxa^Yild1H&Eqe|g=)@}kif|?rwnr@J zoZiAg|J$#*tR@=DPE>E-b+B)sKbcBal$gRQ5)6d`$BrBpjQDU(a7Ol8m)g{dyOIlDu#F@u?ozU-qsXJYZV z43ajG$v(QS9JL*rt*!dulnjF6E^$O)DRB=in#9UY-+Bl zt3Q79*wJIBbA{Zuzx|B|AH09vo9iPH-D3eqhdT*iwDCjnl%Dd0h(Lu!1uS6h3; zRtIG2M)XY^zDBwMAmRO!d z$P}^!=AZt|r{nR|L-+lyzPWk9k`<#PL!(0jb&XA!xpZ=j-WftscP<}}1V8bw?^&^A zL9tZ*-(UY>S63IqF_6HZ&+6(tu0!_*$7f8R@}qCx6$?kYdiuZi-JgzSvsD;Pn`KfT z=*x%@4VjD+;77xOic0%_EdXw`8>*;PG_pTz8s#jR62UR_wgrRd;GbzyLTO6%8!$e z#A>iOa=&LR6bKcH6KmJL`RL=%KKI{~?E$X0G*SGHV^b7UYd!>K<`#aeiwy@dd8e5ARi{9Gow zhf4z2c584gTc}*Oe#b9<^}FBw@xI^u`7hu9*-sz%>)#8dYOfzO1vUxNNZIMj6F7L_ z)YcvQx9#7%|HO$cd-gu@)MJN_9+;@il*W^E>GK7dpV9>Va4Krh>h1USO)bP$hzN#; z5=T!U(`3uSKw~$FpgE?yZRghx_}62l@vFh6V@5x=#UK z8R#A9KGECXjUZKwjU1^3ch~lzQ9ZPh&1Dg;YOQ+^!%YN(p)Y^o3%B3)&Trg( zx39YD=l^r>U0?iSwO*1UHwdB4!fFu{ZW#`mO3)VDhzx)h8R{~-l(DpDz72cOhkJ?{ z6|s_JVkpRoJ`#N0T5ylU!dB>mS*JG{A?>EnL%OIp)FTWd+>^he64bX<2n;v>IME7d zL7$V+h}dsEc#XruUI)AuX6ABPbQLxg$YH5zY>*IN>-pU(ZGO@U1K>{RMj4=+u);jm zh1Y1VR;6Um^}+!Io}fo@k0e(vL}pvTi^W2;0vP37ybNa*rYhLcQwfm>9acdT^NT(L zqHs76iEs>sQRN!ZK~Z*P&{Nsk(n9~ltjCWX>hJC1YE6A3AQ3Z-jE)rYn*8D0LV6oc z)!4{TU*GU6udlaHz(E($Qc0nAReeKq+vMprbq$cbzkh^ie`Ih3TVy*KEs!x?gX{dD zn^X;C?Q1|8dsLNV3P^HhP!eLNO2%PRcDqE*jIkw3Aqj%R4=TCj8n~l%u4b~tHjETo zMi#!x_*pm1vbEP5f#OnirQT-HGdQ$$&;ES}4=1(dtuQh?02{G?jOw$4#&sFMzT5iaD*Ew?b)@PUoaG6d`*1t;ep`r(7?e1JBEk*VIe#rb{-oW zMzDmhLF#k^KG8iua+=GhD=Ohfequt8HiCh1QB`#`vLJ1;0j5GU6uK70lntl}oUEeR zWjcX1Mh=(C#5MBBmg0UWq$a(*)uF4xAXcbSPTi5QL}BZXksasM%&zLl=o*%gR4^-y z(W1T*HR+6NghlGa;>Y;#7;#yun9PpnDg#w@jdhV&%pVQod#I>dGM8dmEL7t~CG~1I zpC0A+c`KQx$3i}zK37#5PXz)M)22@@`lEU%a&A(TUZ zGT=#MYTP64(~S{~4Yja+l%TP86G^&-UC<&zR_g|!!d3F=WE@&xoDfF@8+isJ!Y!nZ zRz$220y1hz*Pc740&{;zluKimtC-$P25b~tVHnrT5Nvaq|$`k zUVH^NF|z>RAc#+LG|3b1T7%%T0H~06%`4CB+PX0m3O6)1 z6L@FR*xBKMzMhfc!LiZd_-On$e|-20cYWvHU;e(kyBoih$!6T$^*D$4DAdPhHBFjS zSsncTkAL~||NZN4{`g=vTksKDpkquN8E|$n(Mj$eBY$!TPD9crp)Uc3N zy84E(wiP*4|Iv$*(3C0pM~S0OIroqM^lVqgnZ#S35_P4q1c4%7{l#SK9ZcQ|k0$5o zOs2c*I5-nb*4Eack*O3Ri@y4WS0TR0n0cjN=JiYl(cTlCM>ni{eR!zf9}L&j)dd2< z#MlVLMQRDXAVr~=!#~PrFz7fxgnt4vtw|ZS1WHZlX$`;=^%Sk^W-$P3&EFz%gI&lV zf^?^8i`Gm<2SgJgb|^a{O5cbYptrrXUai$u6C5vrw3vYEOIj(1B={R;%H))0(gWfK zedrnSq*MWk&A$J^5t{16451~+LOtmN+)>ARNkZADSnp<=B==;9d+zwp&;IXke*evT zzW2Ys{Ppkt_?NfecoUsK2d*MMica*to{IEnA~8JNeWG)quREQJ+nkB%Zt3&?^~LXg z=X<~T^>6?5=Re1EMk67Z z=?p7G5LKDIDnP(xa%Ruw5^$kT)s+Q($6y>(3e1H(0j`4y)$INsY(fL8@;QtMEMPFq zO*WZ|6Td{l(MY(4>Ut(K=xc7B)Bqeo|Ql6-?gHtHLu0*+}l zhx?#8!E01Pu0Ro@{$vC9C${7D&!OGz8RqE=_$I zt$;RWXx#a?Nb+Fv&xkb9-6}F%FXq#kB&wQBC(w0xr-kGaM=^_mIHvTeb4}A|j(ZM- zA}2Zz_jI3ZY-$cg!gyQ^E@2iZkgzl3Ro-N-Kv2vjNNViEKuMdlK<4pHYH7Uu(hIA7 z6a6D2uWj9YYIq1kAmy$01epASGqJh(QDj)^2L~%P52FWYLKwzXnL0>hSh@an=}a(6 zG7Boxq9XX}O8EojisQ_7jUINXtRzl)BxI5Ur}$LRMQoO*lF6ScPbjuxT8qAL$pE36 z&{O=&^aN0_wnQa1DTeg)KV|x?y2hqrsi230bt?{`QUGM&fh1EpJ?P~oDMYL?ys1Pw zo$-1?l@*BTIP?mKBcVWKq6ET{4AY!4c9J~XGDU}|Gum6yT`S#Q;1V{`M-Tyw3ZalV zu+i;>GF5aZDvv(^3p&Ioi?$Y%I0}&Tr#va1VB*BcW-%Gg(acqOtFoR`mmPFbfW0?_ za=~e?g>Ff2Wn@Y%xvn5DS$7JhLCT@&27uyRLw#xXwXc5lYhS(Vr5B#tuwlc?FTe8a zGtVA8cnGzniS>)ns&XtE`_!jD`Q7h+=Z8Q2@h3j@DFQuNz=?{0H}u?7PyP1Szo@IN zzhu=#%a$!!zGM+&e*GKYc=WNy{&fFeL!n5qq*ZvrJt&F2{=pA_@Yv%IKl$VnFFyCu zj49Jbhx>&^RaH8jOpT2tG|p2{=WXffkE8@W@zTbP-S>vu&0ZOWF5lN-PM&C8%0n?helEff;dg{5ejqS z>AwDf?twvY0aFdEr?m9~jnR?hhBvqMobH9V0I+A@eh7;(bkiWf7M+>S>n@6v!fBN% zE5^~oS7NU1-{KSr!axuMQm4#2XqC?)oyeFPR#tMVkdra|!D^g&C?cf=S&gG`mEQEa ztnv%awWG_ecVnpN1dD@7g$V8?TlhTN*M)>s62rpZob4DR7REBm;N{7yCUDRYl;{(3 z1;f!mFif{%kX*QX&ms6RzDP%(TI}%Yt2RDi#0j275w6uI23O>(2Eqs4 zd>#-mUAbIZ(YapQps(q`B|29mVK0EkWdayeheeC#&zd!zAj++5AZ2(7MKFb8b*YF~ zXLh4y5lb{I6W`-yUI1(eAsTBeH9Mi@VC}HfB}*!@M3y2wR?7*ORfM>y!vDXj^6qFA zW|tOOgQJ3$w|5o8w^L9TH1*+V6&bO)$8?YTH8D7 z8yfMJ9yw36&$bT0QKl+dE|gUh#tLNwNFWe4Q^m|NFk|N2nRDi}ceM5Q_ifp_1)qiv zC`he>ZHTkp!v^>e%b16P%c*ioZ{W;-@_P7A5aXJ(b|_e-{ICi9v|LLP{7A4_3RPA8 za!o@{HVaz~Nyro8$m5By@+<;c4$IL$}=dMiveyIHom>Kx|<3<5zgX&@Vt z3?>%uLCyeEiLPRWP`11R%&ybDd-okYa_I1}qn(Ei9y)MfFJVeDIVL|=DAqUDWYSqW zpF4ln55E1aL}sL>Hr6qDGA0S4R!wN>Y;0t-s84&wPIR3-e!Mdj^zGQW?{~lb?cmrj z9&mWL7xuTbG__Bj9IJ_)wQvFC+_Pu@zJ0qvDUr#XbIz(A+qZ(s$NudTpZ(08Ai975 z0q~{7;o(q2b_sQ00gA`$)euCAG*i?fXcZcgM;i#FZhzOikbsBo`}?`8&Tnt;i0G}C zK_bk-z7ghu_91B57X$;d?)CUV6Y>x>rITswTa*Yp5-U}B28KpQ5(%utBM<)VmfPOJ z6!Njho(#w8GTG$g5C0820v(g-ff}LPH(#9XTRUTh3CUnZ@$NiYuKDm@i!VL=aoY5NB}(L3j` z2iS6=RBS3B1w&C7MWj)GDxuK<=&f$v9V47V~Hsqi8ORDM=^C7A{&`-#lq}XfzNCHMO)ZU2z_C z*PhwDJ~UZVR~rn5LV-{$RvV5H(uN3WHO=%>Jq&_?QCr{S?#XjDID~ti7#mG6ho%!K z19*5^_zK$q7VhP9xxC$@14=Ur@{0k&>AQ}KJ`}i?c5L4{oK9G1Co`HaWcX1F*kC9>2nWm1onooj zGN~O8KQz$CYyu9!r_td-x*Hi8N~e;HVvv;qWke++92zs5)GL1Vv?5X)tErF0Y9K*l zV{=<;+oVZN@zK#uo8D}wZ)j<1^ap&IoSs>r3I0c6BEwZxHaEA%VzF#0$y8A*gA6BA zRw={gXvQgO;Iz$qrJkj5Q%q zY*ZFzu*X`LlZ-UA93*Bj5fOJ?1hnR^z9<9(jYU?h`ji8ZoC#%B9=*TJ8$|Ox)s>fB za`|UIbLXRv{+-Fj2i|}C_rLR_#~yn;o{Z0&J@umVFZ{#r|5#Js6pcm+20M?Pdi%{c zFIcqT^y$tIfBd6MS1jr7?(tStAMHHIOmy3hEvqiRsH3CxtZ@l{IYmOd2blsI#KlHbUz}hj_*(pH} z*k*k&2SguMG~ucAR!vA|WUzEqdicKgyblsQ_=msdGl@Mrc5GVv#=+e?W3|ylB8Bw< zSw|}_WUz7 za~76baVr7_V9Qd8IHVxZBMzm13@+M4gv)qzLewYon3G5oMH0+X83U?m zw`~BxlB+kro(e5uMvDddA!gCj4TYR`k5r5^56ERxP@G^!^D;d&thXs)Ua)`)8O_II zE=7484>f#@Z-3j_ z=d7GJZ{A>kf5>0;j+<{>z52qlSFRjOB!)-&S6_Ug&ll_)=tcABh1qY60ouqsiXh{`$t+Yp=QT z^3@kN)YoER-~P7iR;@aF?!1}FRICFwX)X1=mF`_JHOLm8c`jZKw zS|uAz>C9LV)8l8hV15_{aJ3j5D=99P3Md#>H5QEqJ^pvU`}Uvw^n3j7z4u2eS1!Y& z{nwqJ|JQ&1a6X-zGiT77iDK1=vuT_l&Y(eOLRLhHKB31gJQlqQ_Ga*hH- zfwPQ_t{d~HqoGZL#V|`YilmDivR}{~i)lu#P?0Y%weWiD>KcXydkHfFfuP<(r}sDM zkwHj`j^xutpC=ft35UXgs_KboeT6SvsHkGXmSK*#Xvspa-;>Q08yXsihX+I92#9$q zDkI@&Dw*g$(dnxw`Kv3(3%Rz|=FzcXsM63_4+RUQ4E4YHt-I&Vp0|0+R!B@tVKU@! z1fBB4+0b=Sk|-`NsL)mtv{*Y%sDj2%oj&;!pZoOeMe}P~8e6B&2-LS8?dlo#R}YNz z|Nj2_e*U}P{m*ZHbMNne|BFBV{?C7X@aV~bU;g6P-}}aQo__jCJ;IiWcl8ej8fw}n zw@vA2Yj2?6AfBGo66w^N5P@T|FW((#dwN%ik}*R6Gt zS{R5d(23b0*$K2B^+E(>Gs|m3f`Q(Vd-r}8+#oZPNF+*S3LzzMf;s93FVpFCHkS?f zz4dkV`}gkuZTR4Sm=d;g>l>R!rdq1FVvb6EMP>vB1>n8^Yy)6g|q`Os4=w5ByVBkujGrtF%Sn zFp*SL;?%X}D519-)?_$x$#rOA>h`_s?a?H))N-mIq>#2+!*=^0B*g`0hH5L}tS~*% zxE`OUwl<2@oG4U2_V-5y1_p6U6D8eUVP=gKg#y}jA5RPyOGyY$1P3?#K8PgES4^$D zgjMa6I&jWt)9K#sY%Yc5hN3m&72}#!R8{9PrOHxOsi0d%&CN}hTzc{B*;Bv&?eCwx zeCZ3XzQo)Ote~laBDq+S)VO}q$`|us2x{o_;Lun!7X8eBee!GH zxa(Wr{n|J0x%)fc`|hXj{O=Ea|AP=gAg>k%v?*GW->67!i2~3{^$iRR&0XF>Q$PiFp7FN23aZb@cPBEaB0qx19 z8m0~ZNCulOE2h^mX)y$8B=iLrnuAoeS794mJrGyTL!-dDfz&98i8$Bx~JvBG_S{L62D_3Ocb#DP8g*Sx&u&X51c zcklUjtTu+Cp_u>kqkBL0u}?R(5M_*i@ckb^_B2todmy5n7MGAj&3OTXi2`v4;zQNCrCx+oB<_5fCE~gvqwsi+_0&&KYSSoJN`Y)D^Q}v1Hn5$2&U@?tk&=$GT2-4i62E3=J|5X6zicHl4y;j0_LPM@QmgBdK&Mola%b7>UtT zBF;4!7Y^&;cyyztrXdiBJp24>`}XaFh6fKH>+S7}#Ui`*?Ca?0m^*ilZsO!Km?>b# zgcD}?z2XS-2varaXM*em!_=9)aJ599TDq6-O5Zw)Qc_g1%Il9MuIiG^2>&%n$>2l^ z1&r!%e)pGDx`1A_x3%7S>-CAT#K`c_jy-#7W6^7_z9N%JG5qemho?@PcKrCsHLtH5 z9UjZu*FAyMMy*7ufRvm^YvF{bl1K{tLCtfifYH&G0%&AGCA5Y>%m5DT-8o~%j1_0E zJp1g$yS8or<mvko*^(d8N0zd&c}3*IaY$ zdvAL;;tj!mBLapmDrfg_Q7IsUvOtPF8Ju!uoQfi5sDz6x9f)Fz!UCwM zh-l{8HALK)uuN*5+;!rpf+kC@6&Y8}mEetOsK*LR1ln?ht{NT=U6Fr-IMz8Kkb(;} z*Uf7(WObmbwxnQvu~6t(X;M@D1s9(03kD7!J+y7pn~Rn#+rDFKRki<|Rm*<)(_h^6 z#V-wY_YyE~-nyYws?KCI*(8iDmC|ROwXh}U#KPf5G8 zMQY}NNRhw%q_XC!gyaN1SQfaS&!dg{h7D?ucfu+YmFEjGNN~ha38m7SX~lRprwkMj zzw|vuc|1)GbY~f>plw5NlwiQxVnHVKFm(lfuA;WJJ)2FT`N42xY-9*)g+0O#MWQvy z#AvLhUaOeN_@uU}!`k9qAQpocD1rDjKH<}&OxRO-Z~-WVLl) z0l9JPmNL0*aJEnYY#39FH5p`E8?Y4l=JhTDoB!t0DWnY(DH}#;m(%CGWbbWitZg3d zDKf3t<}s0>aCB^B5K=frLo@<*mkjCv5(J0Tz*#8d@aq;_Ym*u9`@DWcYMeL<1+hs| zHIoZj2J9iQ%R+$>{XlAGh0FgGywJZG0R8DuifkfDk}FE4XV0ARr~7{Y``T>Zz@*2}i>H{X-8w{Oq{8(JD$L6mF~!zW1H) zP`D1)gb{pXW+sIzM-G-41!TS2S6W%V@uh2Agu#W4$(Y-@ow!|mF= z$GrY{Lqq+N#b@3Bz~5hc^^HPt;^v#)e)!-))UskC(APKg%B!!vxnW}_t?$9n4;|7C zpkX%~8k-phDM2Lh(9DX$(Qr*e?ZPEXnwpz?PInIv4B(l88x*~o-+O4~+2>SyCoaG0syTD# zJp1&sYhQU4wPbXmB{~tZ8kK~wY$By##~HHXEUeK%Yy6@EdHyJ;#9z_JGMGi;7iPtj z8_h_n&QQP{A05uwJ#y zh<|~k!c*a4`kT#W2K)QAyt!%L{ynGrday7jPo2~T7LTW8QuFP%zN@{Xd__Egt#=3Gxb{?w7f$CfTze(7ab*48$iI(h2Ci!NHUcyVXvk&ccj z7hik{YCJqN46N8JP$M`3CvYJS1$t3_d_wM)Yi|)8q&-#MfUjELqOB&ZhGv9crp!`l z+Bk;7IWs+&Gu^Y&o>{-Ivbqvqt3?mGtwufctSZytP%NgK8&!G@wkrF4GApGLHkTL{ zQ_d;&3^&gljR;W;vgiz`7zE+K;?W#$Cv$0c_GpeBGz%-nlflALjr!t`O^>MIc2j6$ z7L#6Y3n%j}`>L2o1*%NYYR|z4zItCkOnRC;*{h zCevaMFVTVK)Zk8@|3cCN6zJ_T%EOXsne&TRU%qbr`U86pAmeSVlPB(>WE3OW9 zGq}@{a9Ho{P1(z~0h}bqhpd!s4q8$Og~EZLFPM=?sM<$;9x2`EzSSfn2E&&lN`X zY;GDa9`Fa_BV%c;!Z4ZBA|q|nnY2%<+aYYnl*yA9EnTvB$=vOmH{JJ_2No_|J~q@h zG&F)Esc)_YmEP06;ZUf)zCM{8oji4Vp^)CUXFux9(1w=mm(jr4R!Xs2a@dptEk^_h zqLGJdRwlKFc~(J|(Y1FZqG18biRN1VcP5*PTvtn?HZ#PozUzUm-pZ4KJ!Gg!o9O%<*&arR2(3kbwD*WTRN(6DFEo;7c*ff)-IE;@90 z|0S1QlT0QqzUaL3&OZC$zx{Rcv{_rXY|JM{tBNVqh-fIAFHZQw4UKJc<}C1gD|!Zd zBa!F}&%AK+ZMS!wI9L~`jwlw)RC=n$1GRygmg6UT>KogR9Nyj5G5Lwdo+Q5c$&Y`& zam)JiR-U_d{rYot?|4j~$*6A%ha%gz?f%l2zfkF`hQIipY{ni*@)N`AW<9+2`9h+& zzQ`+5345G6ny(p-(8Ww+m3;b;lqVStVk1NSx+@ZiCPqj6!Js1MTsBtMKp03o%S4#-rslSRzSH!NaF8&I;uEZt z`4XWWmyr-elpvNc#<-)6O_b=ay6tA6HRECjWeW8eF5<5>(>&2fE(5c?oSHn)3HBXS z^&GQy-4;DQZF16VUBQ|>3Z8(vKX8Mc?sUcxIY*MUQRK7z-8g5 zzL5hW&VnF1U@hO~*UB$+!x+&Af{s70&^8V2!_soO%_ad40s|)<8i&Y;#3Bo%FlWOV ziGd&sFi`HtOcaW-SX~;Ag0HH=jOSb1+kHN7#duXNU+C&O(cIhyg_%{*yfhAThd=u1 zj|Rfg#~yl&=@|jp*ys=);yW=%*-WOOZ>f23M7pgCz7v|8;vKV@tX3JIl(bLQO#ILy zRS}n2-#lq_2$8PGjAXQfZ6ZL_1x>VfI3V)ca+b_Dy`vGJH!)Ec_5Itwyg$TTQy-8A z3Sozcg0rN{^x7p6#+=PR_Q|>nQeen!h8F|t+UvjNNRnI31W-$zwf=}8Y~Q|9-|MOz zPsUUG_Z(p?qS0(7x$nRMx>~jB?D?~&&z?2?$g$33D(lfRx7sZSs^|?pB0WsUT3Z`$ zxc0JnGp95)HXJ>1s<*cfQTmBoN~fTR z-Ih@si4jzRhSppw2_hUbj**wKv6} zRLr)3S~s0-vw?hOZ#wm7I; zj))eql5X&8uB6Bgq;*NEZKT6O*j9WfXk}y5 zBu`~^Z8WBjjiC4j2&%5qReYD5M4*q6Xj&D`7S8qgePw8tNu6mO8J;YO(3) zcTS%wDETn86BXEEJP*jC_Q6nuKD9EN&xT{Q0H%GljD$6}bp}a}iJr3>=r$vg@%t6S z5)4CUjJiY$i!XiGXTi#14~TBp4Gm36VFR-qI3Q6q!^Mb_Q%S5UQ)cq1%XUeXNUH6m zngh}C_;@Cpfs2I#eq8Z+I+KkPRgR6tQwfZv6h4`t2lE7SLl<9mY47Qt&6_vXH8xF| zF`I5F^xCt|3bpLPVyH)xXe@U7yKel@`);4q+}t}blFjA_R2dnhu) z*I#?-`R6Q}Jh}bYsctR1fi(fU$A@$YQmM8Kr66}gI8hM|`&TYsN)#gr(^bZlB1`=2 z#N}P0M9G?~y(L{>qIgElNh%?gX{0%hh)cqtNQ}9JIi_^H=neRNp+L32dV;t?!88s| zhAfp%jmF1_zzJBT{?*ll3>s3qzf?g+rm~W_b>G1w8@BJ+wBx{N9FNN6R|2BVbpMxrqkWn^gZ*x^I{eSO##>y25Ar^*+o@Op}srAoiID(ElZkccXR{!+!b zj{wOWzA;>)Kyn#FR9=oB9OQ(IMiYc4FA0W3X0EDHY* z^%Md__P1C8f;4dDR8U86F$It8KHW@jdi64Z*#eCY2Cz;P`BGWCDdiU>;B+L#B2zKJ z6ycq>-1fkq{`{$rf9!o9dT-DFN7jD;XjWAD|8RFdIX_S5G(9=z%tVGLL2?iT5fkPJ zqU)-luDhejutr~Ba1ok-cS!v|k_;i*JC`rYsTdpr_(<@slahWb&!DtD#c|DH+avLkuD?2buM z&dbnXKWO1DBvaYcXbPK-s*jfnrCe%Uk3u4l72!xY8jbk90d&Lf_Y#G)Hn%o5wOoGr zm9@2rTW`Iox~BSHzJ5P7Pqv?W+ocy%8!R>H*iLm&HdgDs*9=6K2(#tVmM@1i_K=Hq zRuMv`nMjk`Oit9S2}aJ8D9o58B$_x~dMZ1W%BC|=qg*IvQ|a!`Gb4ljM-J>89O$E0 zhbwR(pU)+S2a7pUUX!Te@-akJ-(^KDRSTNQJ`yZr_&^g2OL)I=)1~1s@jKYjuM??g zx0aI!6S*RIqb3skmt098Y-+(d!k~{iA4Zhj#Kb}h#$L!}kQGJ>9Be3}fQ6+OyO*VH zRS1dZBp0?AueJ~jMF37sQPK>kZq_+#^i@@Q8=0%Bsj+qX%(=L(PzE}KD3%vD0BGbn zLS>&GOf?f<%o8P;s5ug=yY^Zou-Ass3kDF}7$9Wl6pn)u^uZCgHI@Meooilavk_EG~$Ob~IN0Njsc|AEQn;hX6o}a&d`IT>5KY#8t z7_ARi8Gi6fQ;u95x^+lsUX-3<2bii!(~YGjaY~|}B^&od;uMGzU#q1CiJ7jfcQeQ; zP(wXB#>H#|)g=1-H`&C=kiA9iD=OdIxhrQoa!M$MtgeL4aXTQ;*{+^Fd-rbNzH@kZ zR4;0?l`LEgg-L{FiU$QWpD!OgbbQa=qo+^nnMiCdN}^YdSm#c!%&@*7LQsW~9UdA! zbNVP|2wx)@2(3781)=DH{fBV`gdav%L5v8*naBYIIUq(dGm%_{`p)Q0B_uptr(6TK za_J6a5F{nlkp751T$Oa`8fVm}sSLpw96|Ezp*LuzYmzJhq1@pcMb3!KuXR8;ww1#~ z1<@bqG6E81XstpyZeTB`iE5P64U$bBGXNk}wo3v#j{D=j@S=-wR1Y6HcGvqqym!a$ zRC4%|i!S@^?|=W!TW{;{?RxW#*RQzp>ZhN0I#C_3tE=<6s>X98O#W_9VBF=aaE12l z-M@3!uC9*GU^pDFsekUtr^6xNn1v=Y7O_tXj9qu!biX@z;imIfEMGEf`qZG$KR7UqC1cc(XuOQnq-W2bvvS$W zw$@40rcCMU>cP=lziz{f>C>wd2_`{(T*nfm1330(#*C>`rcSA@O$5E6ygnE)UMLo| zL|fE*xN$r4gYBf`bdAoGQ6x^?QTk%4~90bFFV2O5LW(JY`;%jLmN!A-^}c58~# z8ZpkYGaT3m3V5c7jN}lNv1g^qMZJ@|${r0jlUm`t4KAO}I5Gf_{lO5Gi`ZOy^DJF+ z6=;|c?5l-+W??HUgTZj?Vl3TI@MgnzE~wn3(bldNe=up0!(&FU0g4>}3>o>D zrZj3S>x>u(1oj`JvGTl?>15`>fddHn>61si9$!;yTPPaMWi!l|nRH5@Mab#PvY_AC zTmu^0ckJK3W4G)j^sp}~GQl7x@UgbOQIlL%)$}P-1_#rxy|JgGt5@@k=16U)Lm)v8 z%O+H8SfC;jRJo#&z>-Dt8I>XUuRI9(<7K!r=pG_K$5{ST4~mT zZqyfzkQ=GJ>Q2y7)|&zwG@~2S$F;enH&pAQ>9Ngw09AG4902HoBuvKi!DqYlR-FkN zf()l5E%R}S-W}o74k3mGZv>fnK{m=>?V*7Pgv6F;mi8B1dhtJf{)=P9ic-FC`@7z? zeC5iIeDH%e-FU-KfA;f7{`6pHSNjit@{jOG{byYDAI z{hy!z1(T{&MZ_Zq_Zsz1^AN$nDx9@!O$$vaIG&o2o)79Pmfji#c+trCjgMewV zwW;y9e|%_4TQgk5O5btEd-m_%Gig#=I2PTzb6YfCT~l9owyP5Z6AlMmUeCyA3Z0I| z6Qvxstc>GkCP^%mqhpW8Vv8Mbh!VIVYPvky5Rgq*xxKP8s$Qi#T}8dj5FWbh#XTq+ ziUkq0h+#Hbs{~pP!OrW0n0UJ~OyjzT&RpxppT+am=VZo-(Nu0bz;H+bqEG-Q)O=n- zaQQ&RB9fwgvNHX+@XiO>#^?p_1T;zz1i*@=e&Y7~m@;WGcmA>kOIC8}#E~P8nlRx(WVg#7j(elASby(uDmhYc zzKLfF4&nf>t!bDsW6I>olV5o5MR)}9bGBSAy{@d#>W^(}17{6TxaqwJoH06|%U@F+ zzVqF;VCD71i1b)i%Z6sw2Hm%e4N7h0`G4_CUlI)rBGfQ1RLL4sTc=J1k~~*jRk?TC zJY?oly9>7M*oCPDB9#rgIfMqru^LLEgOH*Lu|X&j5vQxFMurCE5?e#74)Mh|2O*Dm zBOJIOiE&j10zm?VfdM`42FavX_I0)kF23ma(Zf4;?h1v&^aTcB$bZelm?reqLK_D! zVB$?X87s6OK<&_pS36ELpaE&764) zAA9Wa7hc+Y?0Cna6Q?@Q4xTyPb=g(deDsr_S+jn9Yg_ZwDU&C)O}qZ)Ti0K7`ExJ5 za=hbg?@0e}Hj^usyutA=e&t`Ty!^^Vi?!nbUXf+&yddtef9? z%c;{R2M7B;^~ujv*VOLZ{zidmZhWl1p_!k2E(;{Ihur=Y8~}AKA8T z`|_15zV+?@eER8seC=!BxclzUv^Gx~>K~jtcg}Yo`04anZA_r+)}4>>efgyqiuv-D zS6=h2|M*TQ80zWmeP#2D5WcgsvsfZp8vpgre=#tU>g(^A+FCz-a`W;fi|5XpGk?L{ zrArodcXx!s(e^VZ&UAJjIdtOkE3W+7zkcne8*hxoP;74*3;Dq{p%WtA6kWRBo;>h;Wh>pmfDJKfl78uN?T&Miu*}W4Iqp!?Dqx&^jOe~y0Mbl zn^j%kq%MkuY-&`72>~OH;K#3zk|4*RUDCdYsz{=SBTAykQC3MVkIx=qutyS*`XYIG zml8a**7?IK(T)O{RDL)yF|Q!*kA$Ky7r~Wco9a=KOIjk~pJH=8rvL&p^f2>ikFz#B z0o1L#Wb~;u4N%GDvg=0gK; z`Ms`X%NOI|(4|>Xt8*@Ks_|P}5-JEx*OzR$fCLht!+*q)Kk>fqDHE*+6hx}Q*&D&7|i9fgT39d9flLgymfRkjF;Jo zJWXMwcwrKfsJxzb+)S<)2-1^=mR4wA+YC%oXjvt}B0l2`K zj9v-huv|hTKU9bUm2=QT$~hZ%S7C8wZb3&@Yr?QHM949bcL)RsD8tdtAv1#%rJO6G zfoh#QnxR+TXrjM!^f|{=QP1W8S!&d&jC^Zi;Hpzipya|5JFB${Re}jNu*xuE#_KOHShV1yAOCn?Z}+{s7-B^nF=?Xd^v%vti?Z+&&%!sUk!>>cVo zTO08<*GJnLYwPMFQ)f=8sPZ2?aB^h0uf5}VQ|r{Lueo-|&NpDh+6^1eTeJF9`|&$( zzkTu2WgFJ6*}DDBEw8+S)Z;WE)KY9sOS;>Ds;pkQa^t$SuWWvP)rytd-+XiZ#*G`+ zt$qBlznwa9s;RYU+T^x9dv-2cw&K8%BR5}vHG({6%Cthh{LC}YW>X{UHmtk$?N{b< z>D7yuo<4Ir8i^b@co>zNG-XOK91DlTi{{U{{+eqdQP+%FZL?-iS+HQ{#TQ@Lkfd70fySBPEK6}=5%xRNvw$N z@hZR_kKYeJRxCen|DGLrd#^JRz??C`MBVR_&A`7yXfa`Muqbm-P_)6Y^?Z~^{!3Z= z2dH1xZfI!=e8;mDQS8xJf_K@Tf}W1W_k{JBZbUl}icqtp*ixG@9BI#{lGs+smA%jl z(WNQjE3Lo^2NoHjcb_kyZEA$mdcMF}_tw$@&YC8C(6v=^(BvPgLIzBv39_>kI$pVA zW5%oD*ryDEAa`CL?$)HjB@$7o-m+Hd(&HXrHm0X4Je8iR3g;o?D!gd`F+$TLxiknq zzWI{nOA|E>!y~CsC{kTpKYiBxU?_~Ug%gTV4o72=NHiP@b2Su-1p*=H?DsR(27TIa zriU7W_DVCYI8V5op5w=~*eFL*%l##3=D5DgLDyPx(Svy;@lh7nRL@=M4u=9OmM_K( zODjzmHTHAKlvK$%6*(Bsm%jXEPAJs0Y?sJ5)%dSo%(vo-)1{R9T)DGPHlHuW} zbh@^-e%-oFbLTIBi+w#^$OG^k+bZB@%hZKYLpDpdViYA&hXO7MH!za~2wNd3ztL7V zII$y_XsJ`qt(C!7fz418bs3bdlFYUWpaFmuR+Fhsv7Yh_U)z!dlM3LVnLr{gFNu7G zHnVF>4c!1v=&92&CYX3E@#CNU)a|X9I(7Qe6>B!0e_?A&dv~uoZ~gXd zTjwucPIPtg1sf+tU27IETsD8+qIq+!y7^sm=g%M0Z3a&%pPw;j7K-`B&;QdaFTb(v z%`Ja<2vUt&^O&ja#8(kHi zZ+`V_&prLrmDgPR^ixkA*uQ_t;-&NE%{hMZ;M}Sv_!7ec1b?GfR#A0Fi#Iq`F!XCHDMbzNTb#}Jl#co zoMuvD>fGs;I)q(=@?ESIEEo{|wuCAJycx=4b*VAi?f|1QrArg=8*#0KHE?lw-+3)S{LPIcy5_4^h5PTd* z3BR^@=-y>n`-$_IYEwalkLV9tGm=bqp6zXHYPjmED=)h6{HCUQ266ROS1bmnd2{iO zXHA>7X2r6F^Jg+C^z`+Eg@SGKvI9Q%>Xpl7;RFe}nx^Zs{Tchj~1`mKLmuy}Da9{c(?zW%|Fe6Uc+tXaSAZCAeS zu8+R|y?4DI@N^7hKv~bWP(ZSsu!exq$|49occlU9ezdC6wFO6#JNfxkmayrfU5DGs zKy88$I z#=b}-md>J#h44Za%X4vnbV!We(?7_Jv~?hBuGpy@yN`x<-}Cuze*4@1`Tc+Y(a(OkcI}EoM~~FiH0WzZ z#d0V>?^-T|+|{)WspN2Sc&M1m9X`0FHsO z8a7g*x5?-sPAn|&F`SUZXs!n(0E_zxtzZXY$yKz0np&>SW~fb%_#BaFHE58Rn&U;f zs-O%Ubx|nChzKi$KMgqjn&U$oae#9uFlY${B8DdEDc|%^P!9m9a6l zB#6|RoI_29Bmt(J|0*I$H>(gt`r-=p)y}R$4CaECw${&l`qP(PdeI%X-}>b*-*>~! z@3`~5w_ShJwfEik#S1RF_^uCq=w0u=?bG*scIu2dv|`f5l*9e;3N2ZPEX-_12fS#c z6BMHH8u{{4B2z29`Ao`+hh(RO5%N)R%XGs~Z(9o@1KnqPcWmGF=Ju^imoGSfy_Rrm7EeG%tH0BNS_<6B4ia`Ifpp;X?C zfpg9BB;A_U?*u6=ajGM~BC@q4QNflkQGjeF&0q*pd>(gQO*J#mp1pe;o9oWsv~KFu zwz;#XE?c&szNvBH!o{f8Q2z+z2WOlXnlRIH42850Msub(q@ILsMHR6IRy7n3d-Y(C zJ{akGwS5JiL{yLRpR!|#8K46izG&64Fy5{c-nIWwkAZGH5S zhko?q@269#KmYN!8l*`K5Huq7s*y??Y@a#hBxk%#$dW=wvSjNV0+`K%l#Yan>arC4 zaaH6rj}pdXXOV|-2OQyP($u092F1+=fcV2nb^`HF2XaD(&pALommt1t|;}8Ea7OKW` z$>qlLg-lM~hbvX8bcbpJ@fLR=QQ-;<4yHOz_xE*n(KT`d!wc!`c%i~IuJ>+u1Ne~< zLRXxXR3?33-_G9dP6*iE-to&{{`%g}{?pZ0yloFI=bH84^_kDyLsW6kJ@*a`554fh z3j|_DXWdc&ZP9bQf*5=I_U*s_{hxZe`tJMkSJJs+rOW&4-~Il~nfAXt`p0M_{JGD5 z?&!fI@p$6p7hm}FM?Uyp4}9-GzWbj)`|TeH+9BtYk3V|#<(L20w;%Zae|-Ok5Bww? zib6V9rK`1h(hJZ1{RiLq=C(I?zWK(s!-tNXK6UzR=h+h{PVe1!;OW0V^_74A%0s{T zeIijkGCcB$Pks#d$nExh;qzZSwEy7q&pbVU{(@(p+x*Z&e}3uZSGTAtb{_aQ^xfF8)sWl}Q1a$@z=1NDR0Abb~zj&2|W z*6Y_>@R1*L^c?@G0)c^*Mvd!TFW79K_H{XbS_YBM>Q4)?S_7Hz2EYxe!*NC$ zo#2o9S`u+HI>|QBov->24v)U_+H1S^?|1vX=vL3!zSAc=28M^mm<$WK?%rDn)GX_+igMNj0*$=a`=GC zaD|eAmCzlbWY%X&aT-tghHEIAc$SIsFtecuBjy#^b|-@Ys{D)WGRy? zeE%muO=XK-gu&&y_~MPTW=-!O?2p7^Tej?IsIHkaZ!&Cs?uFOq%$ZT&Q1j43kDNMw z8g&I4qm|8ZDUKc)9->4uUS)-|YlPlml3rgwR!&q`*VNTzGZ}&<1Z#Lm?>d9|oo7xi zTsVK)^jV9S%sX}Rv1e5D*4+^sV$+3 zoDM)pM#)58X=1J;Ibccj!38I8)>AQ<7QhS*QCvhX;!5)?lWJQdjBbQ}l0x-pek)fk zR>AS$vNj1-z^s)@(6*b+$Oa>e0+fpl)*qD$ZQm9KsKnkz5Nq(;_m zxU{LEvH#S8a5$3BVxq@g@#>+W%${vKQrY3}Jn-MRcc1yxz0+n*Mm_p_2kM%dv~#~) z>h0~SuC7lehjY1nAQ%zOwrGRH!W@aVKyGa<%@+udBxB`5Fc>C;_j-e)!^vVfJMOBy z}db# z|NP?F7oH}t=sMH!KmYY32q*(r#*UQz0q+Mtes`j}HW>7;-*Eo>-uJ$p+qZ*>pMKM+ z>e|{;K07)(QrpnV{1J)9Q2taVg`~==GO<-wX=`XjRVq2c5Qh4CF1q~M(x3v_SF?R?l~;{Ga?tFXC{NUpIhTVt`YzsR63 z5W>`Apy>hy;Ziu3AmhZ&W(>V~dy`f$6a})h6(C3*Fz{Ur0lLEUlR>DQz5UWTdtU*8 zw%H~(NFu4~U1}ncMD;+AepMgwGlu|BQeFcfLAB%vC)hdyj}@#exu?%;`Np@t)zR6R zPG#QQ`bu+S^NLlgPn|y9+|u&&)6XnixUe{0tWMPb;WvL^K19+-h6nEX!skNK@Sh%f zm?l2I7u+)0bVE}se?6UN=^FovnIICW9vK`=XGfqbNt8!2t6b4&6l`<3T%x9~p|Ld& zUD8Q!l^Y>xYimAv>UcUkdgBe(ZQ1hr^l6i;HZwXjggr^6l9@~@5YYaFuFm#l z%a*iGn!I4a?Do^AzV#p9{rD$75s&$P`Lmzpvc)OWXMFLC|Frp~=i=4Xb7s%G=QE%A z%)S5o*T?>_`Nhp1x4srmFJ%m*Elt=QC^VoB^keuEBZ#GkGA)&F)W z0IBeB1YfEvRRN+fQIA#n$j`XX<0~y%vT$T%c=wJyO-+*n;i_B)!#7gpF1yNOK5zK@ zKmX~hIdgh@y0Mn`eCjhtj~&5CGd19t5QyISp7-B$<4wubC?uLTdFtU~C%j&Fh0FcG zcfbAO(@zA$QD!|b!7Sc#$DKFddK>6XZfpF(cfa$8-~S1}rI5!y`itY`Y(9(9GDhe? zedvM$GYXhU2_y8HOXxEH12%v^e-4SDZ!8vDxOfp3htR$znpnJi+2C;J=@Vy;A3WL7 z)z#hKtICQQFi@F|7n~mn2XpCEu{^$a_ijkDa^-4_IdSCB;PB4vZzBJ&kA9$Kz#m$( zW}PqO4TnO5LxWph-7;RGS6C4gWzs26FsNn4Y`(6csrT#|CI(o5ilRO6$W~6#G*>Jf z@9*wtYHsU3+g@GQFgnzaO4rmi;*n{sQ!j+|74tbbsoPnKWALOfW%@d=n}OTMWdp&m z@VAvsbDgwd%Vu!Z72hi=3HM<-F@(KJCTrp$$5r$_usc|Hjvl?S~%x<3RranL?rL^>~_E+CU6n3R2^5Ga%F) z`jMb0XrEEUZ1b7zDdrty$EY$WGItNE?v6l10T3!|AB*bwKXW#bI)vf z$IVy&{=r8Mo;W@+?b(ePUqw}Oef<6Jxt(~$#ziL%1tt=Cr;xk`U#T}J%E&?iiex$L zAIa=X#as5*y08mevaPau)%rv#C3CqS{o>cjbe^cwS5a~8HCJ%`=Rf~-z#qNh%1ak5 znD^5k|Dv|Oe);m{uf6u_fx`!U{xCeD55;o#E9!(xC63G8+-iN2Ts zg&skLg+jvAbXYdR$SP}VBpcIL4={7`JwZ=}6Lc3TRcI0o1oDDu^n^PC2@-T|wMll- z%B25NV|8bXS;jr{xBa%SX6G}6{K87v6I4j%6^c@W5zs8nHi1N_jU_svi z#2G~X(8f|2D-{ZY2@`NnPbc#uk*-ZzbfmYPiEdy}B_cz6qE1{?MKeNQ+m$p}DZXBf zVYG($ZX`CF$$s-&-+sr<*ApQHf*}YwJUmn#kG=lJw%cyIrE$`<(b1tS(}3+I!Zgr6 z5{eJ@^*|+mP`Cb>u;BtUqJr0BWHelWkA3Xx>cH*Aa*d1*HnmQnYh)}EOW+OQ9)fv3 zlZnLQ!~MPfP#6f=bP{h6q}|LDnC^-S?0zYmL-3fH;0T6^K}X}&m;k!L*u~;CnY6yv zOmoPgu@wt0yG;)+*gMA0{2(7z50zBnmw+2{Gu5bojfT1Su!t#I0ESv6z@nCP`#uo1 z-35Abr&Prp=+;}fkOjO`GjrqFR1#3M6nc6icwTceGq=_a<Rb<@%Im%Ie8L8l+Wkx{=z*NyNCby zNPk~17PC;44&sy&%8ZT<^M~*tNYO}?e&82o7qoB-q@;SzLUSRgI0_PrSGP=_hFoRR zG##d9IOtuweoe?9Etbai?A|xfH?VZY;$3_9S7;w-yMWaHZoaK zT}7IVdN%Hf3}kfS*^{-wE7?k}lw72M*0Ko`m&i!(?G%D4n9G-BX64Bi(%Jk^fBBnK zrl8Lemd9FKTMMP^i4&(7*z~DWs>WO=Pn}q}U>^E->~v>$S5IZ-#6lGH*(nN5ipA6-)=ef9!R1wwQAe^-S#7+udXL$kg#4JuOLTy>^>kW$jV z89Y|UaNF|*R8n4F(&ZGQsSES?Ccp}a)CQnVAz&!is)BU@KpTe~7D87Tz(t?iqr2?X zln*E>X}^R-0}yI0PuTVhVZ1c|l!}clQ<9^@T*?))xTsoM6=BM#CDsHHXCQLWY+(*_ z>I@iUG!{j&^2pG0G#O(gU91vH_8Jr}lrctGqIJI?`3eNWdX_gi^5Y->AQBIc4ksIG z8okA@|4px znMAajsTv%8p-^9ccf6(!mlMSfMPk`ZDu_+5sK{kA;Ye(Bc+mC~y7XF7<_6gu&CS~5 zJ`N?l70eKb0!*^^sBOI9vR&I>8yOj4gpo*GpObMGKp~HPAraw$AXsWJDS%nIR0VcM zB1Qqm3<~t=3yMjY@k6z9wj!GqCpl$4qu6l7SS>=*r1( zgvpxHDO6)s(Luik%l<1lwg3N;gp(fzARDA87zxm}Dkj#02ag;*dK@PiE!uzJ(4j+z zm#wXl-rn?YCcl=N&gMTQRS;Ar=k=x4ili zCZ(7!LT-RVh*53x7MU0fHrgKuz^ab+Q~USquzACIC|mKq)~)OY6wr%$xse55x-T?N zP$s5p_0H(89|hoKaNgBQ59(;CUVnI|$REC~P1jTtZ6?U7rgW#g(Mf`8c8$DLT4f@Z z{hp(#BvR|nCjYjoh3d;w&I**^~IMKfKl`TgPA3l2Ic(I7WSGr1-<9f@8 z-pxkzgQ391qo?HXAYI^`$`sO#raZluQ)JShg@*X4n?Jf!q|jTNs5Frno@xcTI0L$D z2iO{OnR@l&F{3Ia#zAoifu{wO!^Wb|#0>}c?K*GWg}`Bq{8N3K`N~Xmpz3iKabaDR zWp|Zc7S4D;6Y_a|%q!BSdtG6CeIszZ6pBZEp`iFy zDpX0p0;8D>rrPBVj6)m{v+r*7c6FXUaWohV*EKXJ;&GhTy1F_|DPCV9QO%SL&beIH zT~)bk@!VT)diy_p_LI|ECvg?aieyg^Un1gPwPao*9%i!g`@>Z7 z1iTfv$28Cj9nl37anl_`eyq}qU{6?8jTN3+-YFn|?vlfBlQEfB1L35J2ImSUh&utr zGLEd!$OMN!j~;rVf}Flef^fgv@6$x5@Ii0zWMXtDV&PaMR2@%veSYR`z0X3Aipq%t zbq64E8R3=RuTUso7~8#j52^)mlKQ}^Za}MJAtnn8$s#x!*-U?5_o?HD^?fkC`CC&x zGLNi)9HgW&sg2#i(3mkgD%WVS7IFzqNVNK5ln8m@swmrvaKcfRE7;HKu|My25sP>UE21SE(nn!AA&VH~_97 zREp#Pgvj|^;nrL4xbUJ2=gyunckb*}Yu9VRpt54?Yp?hA^e1Yfu|%-BsSb(i@9jEq z`jp2P#8uXvjL{L@UDmgV#t2rhN_o9bMGsI(P-QcLFZPfa8c0JZ@e*9TZu}hG0tGDz z8&*c2>;oQ4{y!wXqhE$L|F#s%Dz_lcv3$bXMp6M}Xo2nQJ{^Y@WbBFB6oSIF7U0UXY7ln?{n!A41otE#L=*s-ws zx-CdL>tN!Zebzx7rN{yuAjs9V`=uHS69WS1#$`s-%X#PZzIs!PrbFb3yvOAk86MI~ z2ywXF&;Vu&yd=|J4}KF6#AQL&D+)*&F{pA0>&e);q^7P&D2!PIs(p>RQeT}z^S%1? zj?W)pYQ*|`gFyxoux~&xKp2xrr%oK*pGu7;YHNLdA_sj3mt-4zwSPdY&*o>fO}h2w zD>rUfIcLrsqG1bpg$@2)Fc2gMlG-(29e&TduD$cN>*mg#LqmtFreJys36(cTAB!iE zF}WbG*wS268BLpG&RsIyaq<&MjHWRJoj7$aPyCQ^3YGo;CKbwut+3?;^V;Z`QoX^< ze3r@z)CEaIf?#i)G$Q{!cnsbTHWvI?Rn;zm!Em= zmHqoq?B93v#L-g&Jp+UN0~IL2I3nbM%P@@aEyQ0abhh)%@uP>37%|Vn0i+NnYEWjC zWS5vLk&!CB;5An+;4h#{cw};cEHQj2CAl|g5GY#~AaRuwuA^8`lm>vMvg(*$tV^mU zP--BkcF)mKBmD^pRgiwlg#iL`?wB~WFcKrj5@qpAb0!(;a8zW970~lJ@&$}#>Prkh zXAlj4?1gZnfPY*zKT*~Y+eMuTr_$h4*};rD6e34L%9iICn$u7#3E(H|sknm+0BZsvMt4GmO!VIYu|o)tS(sKdUKa)5;0tKpEY#;LHL1Ihd%vTG#2b*&>^Uek4IvOSaq#p8VF7igGIHBK3v6!Fd`rThYW}b zb8YEIw8b69;!Mn zJm1&b6^>%4BjB7&j*g5B^Os5{p-y3}*q>haOwO5axJ~lW!m`fl)<>|HQxR!>h?JRGGnlMGo@$)f$4!hnuVLN+uQ2X>6hp@xmzAr1s~bW?e7 zcJel9SGc}>pT3OX(9!v|zyCcymz~IqMPn62Akupy9JyUP_hhnJ1Oh4o7jzI?@Iqn; zR|bcYXWBas9XZk7-YNEsjp-F+V`B(910Eh6(8JeNmC5ADnbRFurRmBJTt5TSd? zlJ2$Xo0`?N^@uyJ{@_3#BSBWsT4wcC=dFSsn_trIONhdlQ9XLcu!?e69J&OU(SzZb zeH9NWhj?Ti5^1FLYcF0g!l^Pt64m%GeUX(R?=;s{wQ`KI3sn;Ul4eBJ0~xLxa3zNs zZ=G@hg3!PUbqS&Z+4=>%O|VuCo?=Ucnk~j5a5QwlptjVYYqg>cSfPse3C?P)&{K1P z(afX1$U`V9(5GA*tHP=EDOxB^pgNIgCQN_>1lui$Sy4NTrl+i3C)FlL zhB2PqeLau=<=N4ErqZXc0b)r+A?pRth2B91z%YycfGlz`+scp$V?s_U6AYzBhp~ES z4uS;M4+cxVZGFu z$p%7-9f4)S5ACw5>$zhTNy zH{RUy>g#*@`ugbvjC6$RT5k3cMz>CCUAJz-jvYHwqnX1;+V>qiK9Wp|hNveJA{#|@ z+$qo@X#gmgRy!&xW3kY(MGLgp;UwKC5w9msIk$w6NE9^q3W5>lB+V@(r~pPqN=$i3 z>gp|uD61cxs9gU60$L!V6*+US@b43eT3X_k2ZEYH5t_c9{-MD^d{(NPK-%p{gxfxV zNF4)(s&ZDP7oKUp*TiltvtEUsID{DoU@oW6-7uYdJ$eNv#+OJ(5>qbYo+EyyM z6oUkq251g`&KT9RIjtP|;b7A>T}XcD1?49w<%-x0p&cShKGaz5p5q}Ri>l6l$|XsT znS&SrrzYhhn#ml{oIfj{;DnXSh^uHq;zjwlP~}fZ%IPyn(VIzyFbx?gxhiedv`Ix& zbjfBp#$7f=vlJo#$7oHN24aZl2EU&F(Nl-86U`KhArpkcSb&i!vxY6X(rRhJ2u{ES zG6E~JD3h(OFu10iMxsg}03B@2zM9TB#5ZYSnB=is8l3qJS}TEJGSgH>>GB)at$+BT z2iKps7SY_dcMoy5$Lj&az(5}sHq8v2NkYZKc%eM5n3|Ns7+FZmDD+Y#re1w*7iTLY zY02nIBnr%Jb%>t3I?oIb_N7y!cx=WOMde(PP>T`T(8}l>et|F)M%guXtukrPoS35F z=*`IpkQ2g~PRQ2Kzv6qZB426(JQ$5QzzM2EK(jc|hpaLp6}?SNa<(&UEW6EExklB z5Q5^&230E7D{rLDe%*moEhu51EwH3nibTc-ll0|jh8q+FttBD|L_6NM-UVxAAf)5rBm%^G?h{X63I)Hwn=Eq#HJ_%rVM?maKmjawV_Tn=a?@^ zU1Ok=;OsdcOUde>CAh*wsu)&IoD1}04eab((z*RZp!Ie{#~(HoqGUp13_7J)z&yb~ zE{7;c9WhJh|6>P{R}{Rysin4|DWA*s_jRM$a8FtRAADM+wqL*Ua0KnMWDD4SVC6Gu zCfRtRIvR~rEgDZOSh8Zx`c3rBY!Qi7`vc*MDmR^{vqYRFsDy%~MhA%)fLY9Eh6j2_ z2K&JjKBKzO{oH892FIRfvuXNr$|ZOc>Zh>L#LheySwMaI*eC(@IFPrw!3YmMC`LM= z7CG5!GpXvyu}2bL+m@?5?Zi>wTQ6p34J`F3;0SuifkR~x+N`z%%?S_14MlC%8wNtA zP)aiaipyADMo3JU*G*MYXaZW=Urry2CqyXbGsIoQfE-w3O(L2_ zF!Iu2XI%8F*R$!_QwPIR**FGU6}c(H+OJx(dgaPx>o#m`YnzOb zP=P!*S_ z%2Ua-TORkh{IN(P6bb_e5@M6of?l=IF*YzTFlE}@`HNRfYMVN3=KK|_H`dlSc6D{& zzt`2&)F!GMYwIUXn$l3$&`{S{*VvM%t*x%Ej>X~t42L73U?>`i#^VXh1^haE@JRdV z&QQot%V;cO#&OY2L?idA4N)c#tJuEptu-g)+=#it&c5XJ; z_2n;r*{Q=7l{%M5ax!!V-R)e7B1tHk!-+Z7oH5Dl+_jsDMB40jd0my^V5q5~E)?+f z^mgIhHq_Tln>r<%OD9LOC|Jv+$sCi(Q9KUaBt;t$d?0BVSHTRZps9|OJLrnHGB+A2 zd40{gSPX@uNCxzYVQ#DAwY70PmRB~vGJD?K8*jRP-G()Fb+v~N>`Wx0x4!fC%PzYd z>h*SaUUB*5x8HvIjF~gHzwvqnlOf7tLvuPpM4XKIuo@);REgE``vM}6d4)1$)OFrB z$Ym$g(fzRruNkF)cocCIK$Isv;pTTKl5?*OzBp>;IW5P)JR@t?K|>+IPcojBvsvNgXHyTxOp zgTfe#LIl*BtGaVE$f%*mH*DAwW2dp9qyduAFw0|b=Y8+LGhfUv zUAD5ezUjs1o~Hw}x}~{(@#1-g-54?Ut{wY(di&6HXCU-}FwiN8Q5k%&Ss)+-DpD() zNAnqwrk1y&H!O(Hhk>SR=6QTy3<`M!0EZDPNqt&V6L$~C7;4CJ5p&pd$N(@bKo$a) z_?6M5O<8ZB04;^^V`FFAPqs8qI@^AlU`>3{Jtf;>EQc?UNhPU_dF6=rO%{=G8774+ zIxn}>*e8dhrFCjLodOwq9zmaZ4g^Ek2^m;8Sk$IEpI@Ioqd`8CVs-=$%{{&VCKa3! zD(d4k27(cEHebjQMeE^IbNA!{OUkQp!$JvkF-#q8oQ z6g0Qd<^Uz9d2(bh?DcHgbkUT_lcrCdR?MYl&X{)jWtYvJI|rFQapZ7QYyI0UyM&nG z?$1*VE#A1=<`jDccScd7$$`1Gcj|@1ckX(AEuhsH{#7S!{iE^|znpsxm z5^M@ZTG5$8t{`Xl2#{{u_MOiAWEsKgmCJ6r{;CD@=d4`5B%jaJ)z;p2>n-ya&YwGX z{?X${^7&kSbMs(dFW#;!1=4IVO;cr5L?1nQQbFKk7}{zMh+1N7Acb)T2ibHD_WXb5$J2Ky>W1$@4D-5giL2U zI(F^dOQ36`n;5t=D25z~MDY~Nfx;;>VkkV6CnaRy8N^`tCS(-qOtuwRy1zU@ELkFr z>l}Qs!1B%+Uw*}vutwhxiNs%jb=#TKXBfXT8sTr#749BqxUS@VfgnZ`O>+jv z(7pbN@412uc)&v4GO~y6ASw1kdT6VzauSOL+;)Zqe<|nGh~dV%Ior%_DB`#=k$?jU zwY72!N@3SF7Osl9zTMh5c|L^aL^qs-GI`%sq;xINC9C%1_#1cQOAOzu(MDD zo17JS%+^3(7o*FjlQ`^*!mpS9=}`;fHs&IW&-H8wW5MkZkKoAo7(Oi1iP=njtlmO$ zKN%Wo&w?zz-VHAalnm(JAg6R^wn8FDA=gk5Y8v&#U&p(!B==4~(g^)fQ8HlMk;86t zb19pfJ9p;S|NR@W>e%`XYulZFr zWiCdZ%IQ=R`SSX_g+igDy#wcZ(flRMmf!sPS0DI~Z-49Gz8;Ci+a^zvZ4O7kUGA#F zd3pGvqLPMeHbsd6LpOUZy0oZVl7T?Z+1 zin2kRY8e5X_21@6`awhOhtZ3^s2@HKyretBO(F{bgGRSbzj*y}Khy#R08fhwz(jnO z$0{xZLDEJ=E&DQQO#m>R(KzI*qGlAyP)lMkL*O8x)Iu=%}d_65~bpRHw4~ zHY+LB5~BJjncx_bq73A6jIW6tG^7J)h_!~=j2Z+<44%W)S6+P_@jh_om6x9X+&%YB zpE);|DO`WkI~FWmUMQB+sceR@siJb(vISrL`oDt)xB=XOz(DfZwAZJ_Pzte7Se8Io zZxo_mkk>t{swzrEJy<}rYb2!tXF`mBHWOgiC}98sE?sqqECJPETu_5*HFq;rwx>->f^aYVrC?LmBM%kPj8AO1{S2P72(>5u`6#x@sD+8o5 zq5}Q^4`Pn(R>W8VAGYL{zUYH4klOJg0RjZALU_HD6ml5_NgAtWXos6xx&>Fe%O}6v zmUnO!(QASNPU%Qus_6$lyHQ(&li5Kty&!SaB}p=KIV`q63@hL;?x-;8tjoIFQCn5z zO{GTq`g+fHcV}{ip`l?Sl2fNU`v-9$8)DHI)6A(8C;PfPU3wLVHpz^P3~Qat_R?t) zMth1};aGKTLt`WogI+$L41(xnmJdmg>mZ8iwjNd(gkhd0v`7@zG9Ts(h3e|s^H#6L ztsfW|2nGFXR;{Y7u12Df!*DRXQlG(}Bt|$IE4i+MLeN&)BVjQ1O8`&-hxN{>^Q(kL znU-2@C#lqIu#;%U(G*05oJk=Jmb#Jh=nAw(x3#uHSCti!aQOTUn`&z628a3>;lX`} z+E2DW^5=)Uy1K5o;tDtg3k6N)1J7kF=na%I_D!c!c`RQT%jU{CJ$CJ=4FpY%4&|~b z@BlvyWH=fl!ynpq^2CwBfnIb2JmlHw0VH>Ib!^F!Wp8fXzJ1%SLZO&S4rg+?zQMk+ zV)>b8p8KDl{%F%h7q8o}A(txvUjqPZ8#_nR@bG{hPS?Oiu5k<0P(+NfjaD6_6^#!s4TloP(T3L=0qv(hVr;ShErz?1@u0RllDdD6^G9jui(w$!$o zJCpn=kYxeyRyT4u(&Q%(>_0VD-! zZ3bZO(OX5l(kpvPQWjH=n^vWPrs10qyZwIDYs@}OO+wgZx#ST`PeEKg8%j1D8VTEp zqi#sxnKSJ%v*GYjoyDhfuT zQ>M*sZl2_fO%GF{`gm&k`cY1*6$+bf=%yBG3JSiU9?P~t3lSTT>=*nMLv30Wm(4p? z6_CSArGc>4j6s%2j;v9a1Qlib&gCT?BZC9b4a!HV4K?^eu|ZvLbT|t-Ow0m@TCN#fuhGf zz>L($>C>mT zw6=jPPQ0!Cdd$Uf!Oas#5B2t(ZEru_e)3o$n;jh)9vvFYW%RBbu!6l=ocxiYk->gU zb2^h@X3>^-rX2g?waFRu#Fx@aF{63x@xLBFezaIB?Ap1fy|ZKXtf}oCUH|=~Uv1sG zZRYf8VwtobJrHm6&P#TrN6taN5+F;|(3vIZ<%H=nm$Ze!*0FlzVcJKe#$FI8nnt%V+w{; z?v_kLlo;bg#%2vmLW~mRkE4ie8p{vYt&&k%%n$=;DSIg&MdE4~C87pQ6)7Px**K?M zLc$4xosOvlaYSA4(+wY4Ftj9{$V2r%s-B z;aP;j#p2lae(=4A|MBSKk3ae!|MIVybiwU%r;;P_L@lGHckpxu3>*xE?2A8$zz`r~ zR(uv6ORUh;Od3MdTuPLmDQ5~KW-0I6ZLj!%iU7gOd5A*K9!^eN|i{Ea2?M)*4 z>O}SY`Ew%S$Y^?G_S`AA-+t4gMRPN@-ohvyLx5!}7W7z(ETIHe+;V=zGUwF9!?6QK zm&1r6X&WmaX^Tsx`egEYnK*l+bQxT(HS4#x9?yklf&-OQ&VFd^U}kA z`b##CH&cu!!kf-tzjD>mmbRwno`3$yC!QS|9D&$eBI)53CfIT*8jaH#Oag*X(dQ2U zJXTXzGi%Pga3qdBO{GTV0=PZdERJbb{+FwYz<e-u&XriA2qrGwsJu zcLpMnR4U!oeRl2obxRg6{_Eq9|KqX0Pn$k{#i|v5e&pfjo_${PxriZhNb^mvNV@xG z}J+&`cWGA6mqb60XvatB3^WQUJq2l?6lpw7&wH zJ1U_Pt#lwkBoRjI`dTqCl+>v$fK1GSLQ(zF!VHJr7h(Eb*6w=QCXGPm-U4wn*%qyA zbPh7))w?r=NU^nQ>~&Y2JaO{xfB$Pod;9_>n9+h4ujST2{o=GrUoc=x;3Z#e(r zi!a=`ald-ViYE{iV@bbF0};$o7|>&K=-F2<;S zWvRs)E>Tn6NYRC%Falsz70&0a@4WNO=~JoU;UIn@C7Cob3_Fl;Y$zc%^aN%w6meeG zOc(xOh`9lCfnSV)Fh9~PtZhs127|B}hg5p0)dq>QKNNvAS_zO7s|^rdd(N0@g>s3B zu+r_y6?58>Wzh-t$Y4SZO|+Ud&2(arhet>JzCc}FLv>9e5)%iQ~r!UcpKx%jwVUF5p2|R>Cah?Oq}x2hJu55^Bwh6BbNP zlJiK0T!CPak>v7u+_g+PTP#;$sLyuw|KlJ3ICSuEB3?f@n0n=vt)ru|S9Db|R!M{q zjs#XOTZ#w4^Z{`s(3(UijI5MIy-EZPKa)lw1WM?PT_Y6;y&b!23FJs1ZU4uK3czu^ zJf15Rvsg$ytx@{*uYcFqk9Q3dk^euKiy|C zA?26AjY;PzvG66BPNv|nc9anXd%Uqkv{kQ$s!HJ)r%<0^{0~{QipmT+!zAqSG`F-( zYMWXck9TyQ-gy4nvz;e?`2GLJy-%f+K79lXO1RMnOd;IQ!%pj6H>3Z_#gbO`>| z0LdU5=SFPh1)gevR6Z)#@J{&BI9-y^C|R) zxd$^M#T&0clVJfEIpPkxy?TjwUUV*MW0IBvVT7|PidAyUmZ@J&9(tgNVw@?rE5Jxs zoVRGx1sg*izi$6&5dhIEz53c4FTebXxm|WEzoN1*ZhO>>q72+;Z}1~T)oi4gpbD2q zUirATbK$0?2Kz(7NG3H3@;1nmWcfGBi-C z(nb-G8XoM$iDP15P?31eP+vE!1}j{<^7E&>za2DLrGOfe%kE@5$yW$fCxMNUevR6@%cMQDFEE%z`KsRnAfAYt=pqQYF}(8y9b2aV~9 zkQF>=45vT!*-!QK4Q<`JHIvE4;-o!SyY+oGp!zeo_XgdR9%Vry-yzw3^7%E)5A z&1)bzgLD$e*r?@OFtLBHKx6FbwaoGND%{&!G*iqx9`g4 z^Ta3EKmws&um?JoDqY1~F%a~}qERGxaBu{ue!o7m0pcLxC?U|xg`&shYiz3b`&>0O ziKWYz&0n;zA zeVjw9gc2`Y7K~n&(4tuI1p~IOiGs@vXfP%y=nSk98q9uDRE=IE)gZA=vPY`Q@P#QE zbL%iaI;b{T_+#~`r8RC*O$RwIPL^^LSa>aqrtY+Qd#=8Lf!zRsD7wb5%}l5tE%YcR zrE4&hWZNo-BMoY7k1&WTWCcWeZx@t=mcwwfG8D>OT1VEeRw1lAeTosDSXOta7!{oZ zfvi4452{vfevcmUl0-6Y#~al)BX1Q#0MYEDj!fXDbDC<*C8WI~6i=00MS7PgjcLP> zGYo_Q3aFO#$ka(hUK^7&_ zLE9b*RL|w9CNe7C)GCTcZd-+TfrzbLyZ+Pn-2Ksye(084ZocG_OBw#5eLJyW&;8%BX8h2z*}SsLd~33x(!k9}gm9{f>d z?H-}GoaR5dCh8ELai**ZC*4T|jsB7#&G=NXte_W>ib`2&88ggRu^>~cb#UhF3Oy2S zp`t*c=NJ}TA|Xs}tbE}m7au-!aL2YctE+1pnkETP5l8pN!Ogj=rX%&W;sgc8VzCf% zL7}tGKoUVPzy#2?ufrb*4E6OuD_YShoM6~m$`Y%@Ejtx_(3P_4SP_qfmn~i>`+IJK zJmn7Xw=!0!Qzy1@efhpG(-KNJmr0@uQZAFBJe2ysNn|m%$ZkuK1IjYuHDHFnXD>-EP+0INsQhxa^7x=FFSn zCN6Qi&a}7p_4S3r@q8|q8XZMaNMHl%dSpRg?hJLdpFFaE&*;#w*B{t${(3^c7hik< zS)>}+PYg;1MeJr+bWM&9ol$XB*> z!<3vF=49YIs^ANT-F|;0QKR`r>(zR;O+E-ynC3z4oX1W$BLx>D$e7#XClV6nD=MmM z>(P2l67jGJFawgah9#7VkdR>D0FNy$I6BApF#E-ly#W??Sg#@iO9VvDTXJ;phMRBv zumAeqlKFG0Yr-`((J7N#uDs%Mera73wD(31rd5)ceWDdDnidJs0b z+L~t1n;Ub#Yh$u(Y)U_gL zts^T_QQ`IKQ7$Stf7VE*P%?p9Q5P6qI0y~2E}@xQC7N6DG(G+x<-UL)7J~D}P3L!Y z^={v`HDAazG&NHRgFyGt0OZxwwt{FZ#lpoGZn*rywbxwvw%vOVr&6Mxqj4Ys0+_av zo^I%CZK}WYqVq1?xX$Zxb#!)#O(xIOCsCgSNysCV5)le3Dq_*l(!~p~ynmL-TnQ2L%CG0r?Yc- za1iwXGBqKSzWp1HM5D3(-tJ?E_d{zi(z|xFIxa%XHpyU#uS{IfUBs0%2w%F^z(q<~ zD-GvdIZQoATb)vmO9ErAr79Rj^=GnW6(uurA5Eb7p|b6QqLS=8A`kgQpL3v{JkX#W zM{v-o8Ylr!ft%?%1e7AH6UTR;AH5I{+k}RQiMXqlXee6Sst zQe*j1kGm3esTivYh4o||KA+!PHBO8o3tzSmg!oEhB?Vp;rCctVO^;NT3Wzws6vTSCj_f(Ck&Icgyu?P_nNU9c zI5O{4a`vv#9M#K}3b@U_a2Nmxja*lKuF+G->3LIRm1(0S7q);fV1X&Y>jw=zB4>9C zG4}vN#a$kF?qNnmzK{?HF`AfFSK>@+#RZi}K@3NUly)OnLJGkWiI@8T{l-fKmnt-0 zxU3tp1$*aVUKIphdPQ@2WSSMc>E!4uFFw`X)e#QIkXR7T7xE*?(NX?JhOs`#M?-D& z{B^5ip%CON=p8p=oK~>yv4uz^9twmB!-MY99XDTn$;M^#rcaiFi0J&AFow>coYBBI zr|=w+;if}>$ABm~87p)WHL#I7cYW#0Uvi2?Cd)uPs+-N6X!BM}G9;V&gpOo`Tt(%s z-FuVF80XM(Dx2}wGIMu-&w-=Ic5L6-)!C!)P4Du_a6J~U4n-n(siI_&sLd4&1P&fK zcI;S3U;l7lS9dCvf%ACf-;)L8iB_dt_(;2iE7)i|puj&H7b+ef>Lk?$Qzr zUeq~sp)UYDLBqa%*&K%bogfPJxl9E$70Qwrm?69^Fo0&tTbdXVm7$F3ijy#EAjS+$ z9vrxgY$1qLVBo~LR2H2aN7w;i)|2`aPIPR^IW_p|T1d;MQ&NVjl(3oRb!KBLAggN}T-YH~eV$Oh#SQGpKnm7`#5z-u4 zC>5@~;ig+|fB&0rynOq6KfGr3>fYY7U;X-j9NPWH4ez*ZpiPioY&vi`_1os@673g*WPr?%{RVd|L&dl{PUNOA3eDC{EM!*;_ZhI?Y;L)|90lo z;Th9stzCP5S9j-seDC|+T_;zq+jQr<-}~Z=FWvU;_n&P)HGAGdt{yzF_X8jN#86*X zQ%mc`mtKBw|GwMq{J_X?|Am)a_R)`ieAn*R|LMN3rqjbdU-06$U3%!y-aFoVS3aAm zYizpix|V^inZ zuD4zB_T$G6-u;CyHq=$azb}2|Uv|B@<+eNDH+gd7U~lhdKL3@2`}SRZ<4uc~F6is( zx%>0?oj!GvOnmmMasIdX8gjDMDpPm{sFc_x1k8~v|NzGQ0jRH#L4X`6wQ0p_j-fc|D^W> zX=znnZCQ)vT3f&l<#TYC5F7uGJdhDeTz(7_np()~))$vRn+Xel0%uS{X768?{Mhz8 znoFtmX{a&+hRzi7S=23HZ>vE;v_>eKHL+sApCn&!^e!exrDPriM3P7)6`7hzs6o_h zhpY&^Q3--dsa&X1+1U-IKcag2Wj-rpv-*0%rI++{^&L5U$QKM^Z~J=B#uL?(r_KcW z$ncOojH^XbbOg{*X0SkL`_BFQ4;@QqGGLB<0Sn+!EgFfoG&R*%S2K+)U9{-T@zZ;c zo;iNztWX3~>e0ZoLj|Vtj@EF_*yGXA%4Lh0YUH5E2cwp%se)+@M_mAbydA87HRcq1 zK!&O^NV46gWB(@^t#p7sRH4Kw36xrCf1hFVR%fbZ_MUh&S4s|N;JcV1GRvq^69CW? z6seC-+t)w%(4YVIk0+i#b@KF3Z!djn%|&aA0_(6Aj*!pgvi3xsJ+xC*83=`H>+2C3 zN@(Tv1YDIKO_$m@t3^EPPdiU|Qqp=Lm$y@|H^rgIk|Y zDn$aJYc9X!yu~Y~Pi~n$WpXSLn>x8U77xst(biN~*HTlvYT4q(hKA~BxTU4W9jKf- zrL8Uzud9vXw0eA=)vK1(R@XH(*0#1Z*48vFTR1l!@vYl*{tY)>-`LnPecFtGCr}*? z*49?HPHDUSUAN4dJ$uEP4ez}5mgeS$TW`H_?yQ*?Y`Wl%+ismPb;j+t-MVtcnz}^8 zl$MrQAW&bOC}&2NFJ64h4ew~Kt;MLXT)AS|vQ-~=?|bJ=UvS4A@44oZOD^4T!Taub z&%$~0KmL)A+<5H`4T*;7Q>KQaktx%fYih%@=FYkMo=?qRxS+MQZT8Hz`r63MsnbIK zz|5I#v!={wsc&3=-ty+!`kB*bO=)R@<%{RfAYjDLgGksf2m~qT%$qY-fzRvx@ehCW z*GKuzpoorI@p95kkj z_mW^Dx36hxnuMR7C-*zyYyw0vRDHOO?B9GVPjOCNbHPfvtR719j1 zR+}{j{-|dU7HP(yW36v!n(*Nw1!8`G*dHJ?jp&0@e&W#pSL`V9Gbxozj;Gbw(%d>} ziWI&|_hTTJ#MG3RSjX-(7Dk2!i^bB*n|FQnU%&sOU;OrLPp^?v&JzT8tWPeNTC!}; zjkjErOpkr#U%vm{pZ?*cS6`PCBnBB(rC|J#m4a}J5#`5)_oCZbQeIOLDT-BBI@j=j z6HXIQDRq?Apo)V+*(uPeC8x1f7FZ`^dHr|#li%i;1q@fE8y(koY0PPbJ$glfJwHwZ zS&)i~cy%pS719h1_A&TiI67_m>}4y~%$&QRwzfVR#nTVswEBs3yxst_u`vl|(_JQ$ zg2{=RTBfp4D3YkIo4s_&%JVnqeLns`zK|QIuUtMenj9G#h2qFWCOtAb+@I0&V6wT+ zJ{Th(SSvJ^j8e~@qLBe|ETjBX^hyh?|7M*;y~Q)2@X<+r!NhC+!%v^o~AfkE+Tth%Og{=9{a zjZJY`&PHC!Z3`JwDlO}@~WT}pY8X6lH zFI_@?yn6))+L$5oK}qCOjH;*_8BW1DBsZ1MW%T}RJr~D7s`2uyQidf1Wa=3!9nVgt*+kZhULz;*`T*{UbHPA0c2p)?? zg5i)!u?Jg@k;1CcoW7(2T1L}CJoJ!^34aW-U&3usv+7h;6^i=KIo6h%)aR1WwgpsV z!d0cUH6bCJE5yLhLCc27ugZ~g2TxT{2f!&HPRY@c97>u=XLG51VI-9rMv@Ul`lWt8 zpG7CDa1~0DRe%f)4JB$4O-(IRrp{_)BYHI56Z5x`K z6Ag9Vc%rtkwWhwVw!SeEjghb_iRzkYJmIQzA3b!uuV=^~bmhlO$y_#@%jg|px;ucg zsHF)UL;Nh8hw=;soX{oyEw!At}=lgQY>m2^p0DRFFrrMEI_WFqr_8vJjD zF*~QGq0)U?60|A?)m1mNSig4Z+BGX?PM-k=t&=9rTQGm>v}p{3DR{~>9GBVXQF3$$ zE2x;LvJzu)_`u#HhxQK-4lpvu%z+62Nu0`aH635W*_M!%OfZDTO9>c=9#$6Q!y=sO(oQeuGP=G`w z8qyl9%$BK~d0mBi$kLYT&rO~(yXGU9pCHkqSa{fvY8Z=*=z5(XCm4EN2DFfr2aUmX z=6~$0o}QFJca{!x6JKMZf!$2=`22u!kR+*3jD)6YNerqqajMQ-7`)+;5wv0Qv}pqa zgKe#CLxY2(sdP(g^QlvZDkWqhPnjGmL5*|-7Z4=hMKxuAs>mNAWiM3+basiWHL?O=kfIq4L3G5GRuae zv0y0NJJ5^hWina6FAxZNIy<|VrwgTAUvGCJkr)|C`h1aWK9^1>A@)de7`4jf3NWXx zu0E4Z+qacVlruC~F?q_&WHJ*BgYdUC

    dOp zZr|Y%rOeG^V?&cuWB7WHJrzO-Bo4z{o2}ES%^4ZV#7M_;dY6+G<7}nEp27%6BD?lp z+11^X%jWa>%Ao_#&CJMP;pCe2>juxA?Ck2=vGeMtW?(iCj|`qTdJI}10pPG5L#8GS zv>R|GaQ68;V1*LGE{fzFgmFdDBUn~zp>Q0Z2$NwT*5_2EqqB=x2d0pR5NVFB^O9dW z<&ybLxnS*cWE24{vryT#ZMEbGhv^8YG)JZ%`Ov%9u3cLx%UL<#@IoW7z?nGhXk!Li zR!1XC2$<{UY866?zb0Lm+^I$z)JgtT2^tyB3gu$HQ2xn}e>OHYt~I1)27f0o`aq=? z=lDDT9_HYzUnwS`a^$^9_6N~uP zEbHq^1|tDaBpCE*+^yo2y%3Jy@%xBp7^`z-&l3kuoW3-Sb$7J))T&L>F@z$%+b6WBr*9j9&%j3ilpHhGq7tBa?WTlw@^|;HXz%P89loeo(_S^Pe&f2$ zo3~;>3`H=Ic$Ar*_Ou0qs3}udqD~smr7{ov^4{UgmmvhOx;u)4_V^$eDAI>Y#U30K z!h{%P7%{KE>4w+7_DprI6P<0-M7~K*iW9+UEV3*mAiIpzz!H>z5KV|O0MDpIL(1toYV;$+ zxgl$?Eu%J4AVkFsNpWF4c4k9Vo5ew1w#7!36b7?8>SSQ|^Js{0Ojsd#p#w7khKFtw?U@S^OD_UY6)s3I}Z?u|~>c<+IZ>K49 z3+>XQ9^)%xX{lUnX~J2fbqjy@PhVWWe#6kvWo;4FDt0B7h{q!F(aXbyYwjrJF zp00Ik)_nEL|1vW<7mS3H$<|yp_0f-g_-A)N{LlaLPXy!EIVb@_^Jv4(MjA6@XS9@P zB+wTebWev9pM9c<$nkf6|94jpto_DU|0|M+E?eERci*lb|Lne=o-RH7Q!Fwt@7S@i zRLCB9=I|}I-aIvx`}@ED2kZd8b#-;T=l${SM0y?{`(&q9lrFI zx4d~io%-<)e=<5Y#@q(+(YsKBMq4~38A=kBWN0jPm@n!E0#%{Q%ka&tkirs;T$9mR z1^l*UOj!im7Ne)6f6p@FwC5_m%QzuW)&dvj0HPqY@i{ z!hvIFUpRK=)Zp0R(}S0Wr<%M$NX8ke&z9!4_D(WBf6#qMneK%O^E>&ZD#`_RI513# z!PD8IQALQV$1=nLydp?oLefULMiS8qWNPuj2!tq(ic-~ty3$lABJ!))i|$=&kgSy! zjc3$klrjRf7laC+#wCF?u$C9?)YB#LO0`^NGQw1?)H?tf7aC%)Bst(Iv|S=(--qtx zFBA^b0L*jx$Y3OArpsUh39bnl!UaYeKOVVO%V%>Qd;W85Ix{(&BU+hFmF80AvFVx9 z=LZiTJ25epF4RI3^M&Dw`Fy^pNZ9A??pn{KU}{gXb@7*tq_{a|h0!8-#C=snAKX;J?N&*eRU2gjmUlLQg4Q*nida zcmM2X$Bvx1aQ58j*wpEhXHuz!&D*y9->-k;#K}{|Qf+oVH9kHwIy|v#S^wAn?W+oa z3Y9{x>E!VvZOM+uANb|O*cekqVj^ZRM7)UNf%_inTQShrzcLsIWz*@68`hsbbN=}Q z2OQZXa6l~`a~xOo3&GAGHQa@BG-5Tw5p}ZZ6rM2<@Dty@`n9jZNV+@QhK7bWY}&xU z(AT@Hlv~)ac4a&oFJ^0zXf&TMJ@@FR1dcvUnT?fbX0U z(s5LCTLE+mpjt*La*<}pxTG;2ujh&@cDJ{+13;iG6sD@OR$Yab0BAlIp;{eNBPHN2 zC08P1421nEsfGTL1PjBn^(iSUN!DQg#!zka*{HghAREJXg+!?g@syM-et}>b$+jC@ z<4k*Koa-STWZr5HNRcB@N~Lmhi#HgK>ctx!J(2dVL{DF`XPGw|XF3s2c7)@tfpE;@ z?#tB(IV+HanU9QI%IC7$c4RvM@ie$vGSP4>;13d4YjA2NnDFRkmF_$?RpntZFQyf~ zCOs6S8{wcLPRI#^EI7-si}uxcc{c_0a?$h-IU<~qsj7X{T!K$TG)ya?5$^`oVyq<~ z0-yS>RmH|LbtJ}{@T5IJmcfhPQoEPh!ZlYJc2SulaW^(2O^}3yhb|lZY$iQ5sRtSL zCe~a=cNgs=%&G~)>dbXYQYMW_K3L=l`m*_~UVGEhR03FYrO8u`wMKjTdpo*12Uc%b zyR{O#skH3il1@~Iia0TWXHb94t6tT)z;k$jh5DYSfbqn`SUqFzfPK|>o z6GxYzfnUuoeWm_jQLTU97+QJ^W9popa@ z>R(#2P+n}bnFPvME>$jHINLw4;)YvqyZVM3uejz0e9x(~r_rlhZoBRJo36j<6*mm@ z_c940M9?^HV}^qS7%UN3;OQ)eUIi5mu}8`-UAj0qF|~2ax?g|)yWaG+*S+&yZ|`5Z zYIZ&|HZi_z#fsOy;k9?Z`E_r6^BXqp*fg^+H92|l%B!!x;pUree)V;?-hRj2e7aiq zU3cTHue{}!n_qFwYi_%xtFwE4W+9uIyXofZufK8cO*dcpmbc#-2uFv9FQU%QXMqL| z*3fV)5K8E3z%Nfnt!DUPuuAm+S8yGem0E?6Z>X|G_2 z#%7FMRg*e=u*&Me>0YBRmD!2sk3Rc3P_}ChKc&Xy#pK#Ziw#8*KNz1j8`LU?4<5;8 z^I$_GYB)GFK{Xv5@nR8(z**9Di}K`#1ko-TW+XbmFDMMD)rhJBfdC$W`c$b9)7m2+ zEb;oeqzCLA4Rqn?Z)k?~!>NwC^_eRa@=T3qrYE!6w7yfMCsMo;hXpAv zNfLx|Hsjz-j1VAuKM0tso^ay_W@<15CEbYoX_Ph$+iN(u>Vkw)`od<{`UVyPgG1+thH(kmv zEX-@;z3wCxTRC`Tefcj`V&t)rW?d!D0QXl!qjegDY+TF z5%11*DpDHSY=ts2%8(26&CN^#(6LP{TC^Nk=%h=c7w7jW7cgcI_DMnD<2dA7t(w|c zWy`!`>@)MF`Ym;bN(p zXzlprJ-?WqnbTYcG^8&ME672OrNQdX^on^E6^g~|z`&~Msi|fCD}3ITTqZN0T9}$! zC>G22-}|dVzIkZq!uj(TPMtb==Ip7dsrhH0eFm>KIX-;$%(+v?k5p@(Cm(;Bx!~x< zi8c@}89{7NlDA12tpLACyEc779aahU14pHGw39Z22 zq%4w+I%_C+vLoR5{QhlQH+Ocn%de2EBcM>5R*qfP(17R$O^fF~-4)yu-9ih5 z7;*BF?nt6lFc_f%B^8C|qQ^R@WA0QCEnHUkrchM+CHJncpMej(i1U>2XNKyU5IO;(xNid;WEyE)eDHsgp^I04LaWK`8h}~BRpiK;TK`-La=LT@H zxFjypJ-xsj^faJ{*~RUEU*8U?YIT61So)8GwzhRZUsYRGD&4)ys4z1N8KGs*bY5U~hZ3>;hn_|ny-Ixe|9WD=O`#)EEgK$1_+8ldvIOGoetFpHub#3)3v z>Q`$B0?c*zhMC9{nyu0bMsT&OyU#eUHx|*N-dsC;@R{kU$!tE4!+P=gLqnIwo_pr; z!Lw(x>FoH(_<`pS9651jbY|hFKm5_Tv*%$EJ%}Wmx;ae*RSsp(6XFP=~W;%7`z~NP^R-_g(&mDNd>-C^ME40Hu@X!DFrIjm}-~7r~ z?A)~j+4{YKW5;iFQJ)@A9xf-Rvc+mZR$ zXiC;xgHEstW~fXmJ&a(gpjM7vgJ!HiF*F(qI0)?7y|bgEP3?L3k`b)`PjZ+5ibisa z1`=Fd7cvYz53bGgOkgqizU9k_vu38J6=zv+C3XrB#9;CEkfmHnGXnrYA#8CSiG=3n zXe@z|yHoriGt+XloGaw;upR9^U|uO{X$Q(D9 z^K)9(&_1V1saP%*n7mhQ(+~7%*N!5urlyrER`>NSgGN2`T*~228HyyTI=WuKY@6#X zx-TKw%aWPVX(?V$UEuS){y?x)B#_TR82*$BPzO%{(AU2L--(~X#Y7^Bc)V3Fi1PVj zu|#KQk4B8GEkQ`%Wx!~rVHlj%T}yjvu@qy?b{K=p%-4vW%Pc7SS-GJ?W&clR-^T&PoJC^n~26^ zE7z{-Uop_y);c~ub@IfCSTxzYyr+M~@)fJrG3mT`c5vv@V0&kGYe(Dif&RW_{d02* zmq*5{^(wT23q5lb1I_h2jv6xZK8hiXjf=?I{#J2EM$8;&^Oh|)z4B%P)pZ*;wzhUX z_R!Nnfvd1;GqW}e(LGxAAao7XAd0s*)Q%(&86+xhlZnE;uoDSVyFb~oHiQrdd5Ng zlt!rzEmc8v?PQT6(Y_d=b1H)uOjQzbE&;G!+qZXDTU(Om4G=OM0d?~sVbE~Ux}b6X zv!DGOMT%-9)<$wwUyir+s907tz-w51PE<#NoWdW7ZCswoBw7wa&FgH&$ zGC2mOExwj~F@u7_AEbmL!8p`3;0xNQ1nEJP1(8W>zyxtq!RLv^lZ8Bll+pd5KSbbD zE|#|M+|K2vp2EqxO*s-2$$(2+ocf};oVuf~^3MewR$n5vBZ&%7Ev-f1j0B9oiYc(O zicJ=4ic+bIbv1k9@ixD$SmRW@oCCLB^(oBv1ww&nB%0K#T-y@KM5PK><=@dULD8$z z^`JX$+0*0+hj4j`Wh)2b$#8lhbMe9jcoz%D`j+>0clV$?6XR3!vkTH`cp`7snB}-+ zbnDbnw`ADVZMMe_23D@>=xSx)W_EJ=)TwkT4TxkSwqy4$q!f=OPo6k7Gc(6grmtVr8jVipN@Cc>WNcuB*FeK0%l(Ay^W+WO@srplzy!5_}M}Lz86?sA-A0BMXxq z9K|M7+PiBioZp+2!34h^89!>yjc_ z?OST9pFVX?PS$!6(U7X?1O2rS`_c!s!9hoZywn9HD67j*NOH7U0)Yl$ZUr_P3!gu8 za$2gkGp82BuX8eC9Ep{($TPI`ZaNwW|zV2^Z1ta=8fgxckYexo01LceE*J8EGM*^%HSaA6PmK;krcXPABMS=)IBPs0P@og$kfK_4!Z-@(a2xKPm@xO}mYgBXl}fuvwh^ur1WiYMBD zkJm%^f^RqFs)Ww@tafxLhQdEz)P&V{00=$CO? zNWze*mQKx0O^i)Xjm?aYEKKWd%q!P!oS&awvu-sL)u*0(Qg^@_E&f}ABGki4mPFo; zh*t_jcXrfOW*=OmdkCTmBL_yJOSYh-demW<5{gVZs#jfm{Ttu*<{dkCY}vf2kV*CR zbhjo#ZShENXM3_W8IQ$Yf9D(D@P^mlc;k(mw`@Lg*$e#jG!HD?fb8}Hl0~uHa0aqJ2^TI6K&^~5)FlqC;&(JCdfk87B0Bd zFbzV3T5VwU>b{=dd^QsdMuvw+XQroc7oFYRkyu#INaPC>6Vu}pW8K~TYgVs0dHh9m zC||6OjgEyp-hqLY{y-=-JLUD(W~Ne;6B8>2Rz+g|qCTTrVMw@e>5|>gdD$Z#;;8A8 zc3Yd@wO~*ozJ2A>c`DM9{Yn7MEzD~#T^_w~ap=U!Q=?;(;aD6Mq#Sn@2!^qw;gPYS z;fa%{&s`oGZT1C;Aw{)rha!D#EI}1@JJ_d1QbsyB?AL0Qk6DCC-Pq?u4?^^5*nsU4 zCQ1!L?5Z_!2vd#!T!SJaaC`(M(25`}G!r0QB0MMIRRy~-uJb<-@bB5at-UpAI!8N6 zkV=-5M$!eK$I@K>3epH7%kxcB(51)-cKuH%eQGvd~%EZwWcm3$wT_ z`GUm(6H}q2R?$bj)T&yUo1ev*mGW}LbO$`iPs6<)0L7x<9>`$l2qT*%j!8ooUR^ww z$Yld$3Ym-|dyOJ>{4Kti2-*b5=u*XRf()F|=&7(w>(P{h5J!ib@HAoQD18=}@ZGuW zf{vLK$Y43dybE(PX+quEsdQFfQB5r{w9IBx3pfQtrs!28gcfb--LH4h#ORh;@WR5} zmMxo@&OiFd!+Kl?eSKM?UtvPePB~0lV85>E$bSt^I=Wc4l^d9?GT$R;*y)Ddd?P%y;&z zICcCOlMaFgBf;=r#NBxAY(asMNstTbgXsnF>BdbPE5(do?^Z4^WHQ5-F8I9u+wOSP zo?YAfx;s}4ET5R1Jbm)Ss?{4dZ&$$PG7L|N7V6(%BYY(cd$$eC4wT4i)q+1?J24UKm5k@fpON&ZB`Q5c5h>5@Vy0 z(9jlRJGL1J1j6>6F3@K9L^-KRL&kn+K`_x+4DFY<)-%KArlq%Hrg3A@wC&a)-AI5(&Ze_)^!Z;}WMJEv!^c-ru=Dm(+tTaFOt;)D|@J!D6_^V;>4I^EHgFZx-qQwz5p>g36@ z3(Q>58!B-%^3O1+|u@KL5t2#!;Ozf5B25XVVJ4i&{G z+PzR950mg@@DCm@;lIRviQl77cU0^#Csk5a{@eJ43%A91%9-GE@anCax-+0cs%i-c zr)hq+S)NO!NJWm6KW+Qh@}Q(Ah_JWC?T(ff2p)C(A?<7x(>&;nhA3KcB!M}C0zTcr zOBW$(2IaMtYe7K)gk(s@pxv56#wd`+%l{AzYM2&Qu45@5K?Nhc)>wrX)~HTBaF`K7 zv`C(c&GGCC80j8I&9p$3HA2t~e+~xGNTO7#3}3#8Z{L5-Rl$HCCmRguVKCur$pETf zA#9*2bQRpGD-pJqQK>5EBL9T4>KGpzQmk9aN2B3Yt5;Xcwb|Kpxn6Qp3_K*K-;1`2i4 z9Flv)2*4^=8QdnG((|}&t*u?1-8bHJ;}ut4v3l+5HEY*SPEXOay}fh$jty(qt%}DY zk!WOUVgjM9Sl)m0E3WJ6YVYmq#S4#I9>y%T?AYADtXKE<{K3>hhOjUa^(K<>7M~{= zjApYrT!!Btnw^~y4-whogHlj!*on8&E(Nn%Dsj?xd9E(b5(9ASxqbVX1uN$mZm1scx`dV8a8cQ)7{mjsi(jL#4K9B2Elp}V1>fX zGJc#afXo;GD!63K%obJLkz|SZkP6s8C5naktJhARIFm}JZSg@iCSC}R{IPJb-j_f* z_%7Kcv!KOfY_orqxe8|3kx+R5zMaFDFAZL}M4?+P#bRj=WLVGSz2U^#*141r8PZF%`GiBs`@+LXxhvchx$FrFv6=ao74W-)Rg~V*VA>^N3{> zi>q`Zw4BQBDa`bbZ}#0W8=T8TR)14bm_YDsM3s+;#&eKj|+K@7sChWxt)6Clvl-Jf2V zr{7Ac@`_t-$fOHB%h$EHMOUrtZB4Wd4Gq!`RS$+Dt!*8}YE!ba3s!go{%4+gc4TA- zxi$I~Q*;b@>aTmR;AZtCq$mM#d+`=`|4af9#_lxpe75wOp(< zd5)bp>1pxz_V(U!`|YPs9!gyL9EXj|&aOqN%)~@M-biQ&#p;mESE{Cj!rTun zqKU;lTH6fCW;=~6EOZXuU)_SiI|IGqR?!(a)Hb=^n~ zf09hyUVA95Ab}b3h2LtcmTE&8;PiZalZNfME~;A`m2l!m zH=YTF%DHSxYGlhdToGeU8e*)fT7h{<+y|q#@@g%!7uOaCGui5*kYIy(IeRw2_)Mw6 z;z$146^buft5sW|35Y(>fO~fCRbEeS6E6vWwH$y_sU|$8XBq&pl+Vx4Ojb)JS_vjH zqHDdMR6{*J8s0iI)Im!N?$RF&>3t-&=LuGG;G*%ztBAmmw}{Cv_r^%Z!5{GZebH#t zuWwYlVGqu0WU~4imz;)31scQ(mYplvB}*@H=_Os{0GvjBivz$`PEiDOz_vBbnkPn6Z(^0qtM+mew;xVxu^;bz~Sy=&GEy!!Un$6DLr$A!y7p-5!o z=FP9X^~PuvwG4%v7y45s62Vn>Ox;e4hrHadwoTdJj&df9Fx5Pj-l5SVNX)#9NGs*K-o*WSgU z7oQ7dP}Qg@rJ{nd#cp3y2ZiSpIsnD&5H~{w%Fz_ckvZz*DpP?jG@%3{|6N~{S^_9c zmxgcw%#;XY70J51s|HL}w&YmqN~ngEl-K$I@P&_A0cCEMrrLCa8B3AD4?B9v2U2el zsL?k8bnN-`r$1AtkctghswzB|sxBs2%^wwv56WwkRK0fS z(9u+C!T2tyR+pnd0fb&%6Y}opl2ubuJxg5Ws7vP1#YJ1D!2mKr&A#9Xj`r-?IXF0Y z>Cy->5#=HVF2E3s+=5MeZVIuLL7$e`kEEkagK`HPj3nu1jfc&8O+;OO)&kq0Pp=xq zCGa2MfHt=q6k^(}DyF;H90LI`jZgAo!dUK4?l&0J+d4Gra)LgI1M*v-A*LAPDFbb6 z&&Zdbq!Nnk#R7^PL9{ z9JnwzI5ISP;^^6PXU-EFFb6;M;^Fbh>9d1_XHK6Sx_sfP{a5_zfk%c%#&jD;j8NPs z_DbStg)!C`o@{OF?^}^sSg1D@Uw!+l2hU!5?6JodQn~4=x%=+Fzf>vg+q?IL7Y{%D z@S{T`qvNAf4?J*RDCF6^Y0Eu7|HTW>y)ZsLdHndfXP$m)*PflTvvbcr^X%MgW^`oy zR}b79i$^zY-ulc_&tJT7u~aA?KXNoRKljR8Z++_N0|#Ds0oH-Qq7WLQFiIOw6;nav zn>sn<5u&Qvq|HjiYii)H0YyAiEaW9}4ZeONStNrNG0x#z0j0`~b*+Z*oB^69NTW!L zN6F9C#8^~E3MO3z4e~BoT_w5%2Aap*w{fj;wMmpTG{|tqrexrvS39fKPh*mS`3f=f zDhRAnF7Dg2tF1L@w|+1-J_%pc-g-tDuDJuX2t!Ab>w+Vfmbx>K-Kb9?fEGC}x(PBr z_R$YK^xy-JJ^6fCAH{RB(W0N~D>9SYQ$sU#h@+^fPAnj#sEIgjq%uw|t|ie*4K>7x zl}wBUv#yt@R&-}fAu9SoJtlqBhjP;-p=M()^H#%LL86dHiAJ$qdMD_mXvE ztbpk>0XVTTdREX^mFzhM^AZ>)^iY#Jpv2Ij(O#SRr4hj45)eSrI`mcRdVIri1E0ZB z)Y;2xchX{n284UUe`SKSn-fFEv&`M|20W5(MPTHas+l|oRDfLZVsJLqYxTd2w}7m!MM{wwCG`uS5k`jpr(L$?U%>elk$`J+jzA zzK5cbj%+&p;(^C;bID{|E|>RInv(J4rXAaY3Gb@a18;lF+duKq-+J!Z=jtARv)%F* z8X9q%>ZRN_zx}T#PM&}6*%yQ1kXYB$bn7c$(b^h+@ZrZJ;V6>y`@F5m#LYKd|E_m` z@W`=~@WJVlqlo140@)%kPS{{FZt3jm%w)6|g-J!Ftd&j1U%e16n=iVTLsjcR zraj@%CqDHDk3R8aB%)WfNx99A%tt8$V&niw24tNdH1DZk7W+cDl+)CXdd>yi){HO` zO{eCaZZL;*%LRJVQ&wo=IsiD=a zYo*B0ZWKym<@+G2U>*Q1b(KNSbw@_;$K#~MgPzdbXqPPmoe62JTKvd|-n(k$3TO0G zATe-bBxC^P+ydc<0Z|;(Tqu@dr*6#aeJJu!4nK}Aktfl;J?-7N#ZIPF(ko?gvfuj8 z?~PCBozSA)=)r6p1RJSD1IfWz%89U8=5ysVY88dRV4_J%Q@L0K6so}Jpr8`v(~Gs_o`kA!5)(l{ z3kYb5*He}h?ft|hZO#=)8-a?Yyf(~REBqu5LAq5df{GlGo-EMowPYsM_pm8ViFqSnL($ROAf z_IUzX#Gsc_>l5ihQZO}4de+p_VgXJ7o`_rHUo?%H<+Mtl2huLS;2fBMT)$BtDh`R%)}?C9+3@9iq( zOF#JDPo8@EF^|61rPs4L%LPF((Y&oF6|Kg5{W^ov#ueCWl_fe&98Aek8x%|{bKz)O zZ`8zOn!}M;A+LDFy$6}vrcrVf8WoJ4f@5-bFtJrd49aM4C{=`k!fku3)@o8!Wp*kj z>Kw5#(*eO7pj4WDaB8YjmbXzTq2S846PS|}94+cuEN?N5G@J`|R%iZ&Bz zA3k!dx2LaIEN9bs%qg2mx3(vV5pc2)1671`UY|FWP9a-JwdTTG4~XI&wbjmS1H&Yo zL_nyxhB$pW4kd_0LWxAQSSmS3St=2%>mBa^hb}M#Ra(nQwP=wDrwqR3N)Z@@3G|4a zJE@2$DwtO)6!F5YEkHClLT{MhAr$1SR%uEtEQCXWL?SsgISpdAMnUCjESbzGrNiL} z&Iru$P%t{^i$HAI-q6el1Q1ZwtG=X!x<5&e41G}5}Ny+F?N!{9kpaVPq3w*lN0 z#HY&`m7dP5!hMg=5BYFXDn)(7vp7ExNE$VRxwpB3sI$q|IPJaO2mqwv_Ie*g!03e| zh{hAl&C3=1u%cyig|cyY2sRCz%C$-{b=zxi``thM!&G{{x4U~jmHv}Yf9}AuPyhaB z{$%r(&BG&?H*VPS)RWKt$!9*N^_F1c#nMKUU|=zrHW`=+J^XL6&-rnU0lB%Q^v_@Y zYFB6H@W?nN-}%;m-1C#WBheVM;7|O{r|$Z-w_h9_zW3)3y!th-{M}D|dfldhfB4(K z0q000{Hq6_{Mbi7(vfWY*ROwdVtQuF<~5Z{(~-j`KmVD}b@z7s?LYrhGLgtj!LtAL zUw8lXM?VV2!_cM4QzKeZlt6|A!Xyxe!>9q55Gw;Sm=kA!wks?a^VES$iDbJ42R?r= zgp;*6w;qip%le{aQz#V4X4CMRRt_xVA~s5fLQ1T6Icu2UIAdbh?8IFqd=*+Wgohw$ zh5QE(S3#$iEQ3;tw;ajCVMHm$(y49gaOAkkL0dbJ?&0+8Gr$l*IsJI?GflPkzvrDB z)~_v>6q?|cbtEXZg$;?*EDLWFz%NPj&B@Y-?kn+Qoe4Wju1hOcg1JQoXnX2h&Zkn< zr!eZ(?|k=1qhk|rLg1AQJ9D*0wUwF6chG?IKOn32BJV8jSh@;dlrI&Fo$ZM$ue!qS zY3tLT$WMlg^$-matJ;Pkxj4lUdUFkd2oq(qe?}Dsy-Fk+#rmu(ZPLeQ1@TYeD1KQV zoG+GwA^YBErItyjVGcoAYGK}af12P;$lE_#tiZ=>x@T71cuqzk339=Mgu_v^3I`27 z`r?S*>+Od$DU49o)2^@%Rg=i&2L+QdyX~O(77v9rW-}QIamV>QQ+_jUZ!=Oa6=52R z17hZD?3MzUX++UG!1MtK5~lzx*k}3!f#BTCTsocBHrslQh}EXLP@`9!Qh|nuTyiv( zgccY}j$UhCPU%rK!QZPD53QVt54MGinvgHq;jMgxLUN<%9=+p3l-CF^(-qUCc(Bte zdn#-A@dtua(_`su1;+v?CHP5%FSjT=M-#Lw(UbvJgDvW%oaSEk51gH{+1+IEu&9^1 zAsrFr^Aa1XEfs7EB*hZ@5G@024ZZOPBHMOt4FKmFar z^yKMN$FIHidYXRpV;^T26Y@3*00=yEDk%!&3gpLI>dj1s89PL9b4w;Y_L?`mZu#$i^76!kukxS6<{U7|`{`-Hia^&jy8vDTee-jMveA^rDddEBB(a2lh z@%9UY;B-6Kl}50e(}uXPrmzI?>lhd z*f;<0e|Up#TBA`G#AJd}aydZ}`LYu5GSSPUkx+Zn8r8)0cXV{F7+8Je@Qd0l%M>cB zH?AcTiR*8?<)H_Eg=0ko2p@MYD2w)ve*{EBWHySst8k2~=#NHlvw9j5SfOlG5D)E+ zGe5)@i$VrP$g~7Dx{8iagHW0-EDmPU zS^nUA?^?HRHA)V-Ml|#zEiKPD1*3g{(2qfgz6td#l2!1mK*LBS30+Gxcc*e58sza# zIx^t%moF9Z6yN*a-9y8}nzjRfaVInIoU~kX{yVWy*f5X9UK}gc7N=|mLlWAHZkGfh zg+iuK$U}yf+VCW%l%fjXqZm{*rJWWmLl=Nbr2=Tsvsl(3Uz1E4Q`0c9NC!`2`%B0d zi#d%=FGCq*AeWp&k3=kA(g=ryRc*MJzRHnzV5J;{;WhX3eKKHuKn@!$jZceM6=^WXn9ozC9=+S@<%hrcs3HIvI0zV@}RJ@C-upl7(F zG`g8sE;9|1w?#yZd=2JHQ4L+_@-RH-uD;>AEn9X!{nT^eP_VPJ>$zv2oEW{F&t*UI z(T{G~w)3lB{K~uE|E~Ul-aq=o&lk&;n_qqXu3ft`sm#+)KRbAS^M`-(XV1QH;JN2s_~`pTc<;RrJo&_v%{~R8#wC)hN~9T+ zB|tN093ZkG?=FEb;Rpha#uA0R9&E|wvic-MC<1$+ORl0+%B1F3u3kqRGdeQT+S-nC z&d<$oGzd1bN)+_i98?Mu=W>-Ir%uk^!3$}EjV4}!5LP3Uq+RynG{cf8jD`-faahFA z2XM%Xs-|XUY1DQOSA<&Rr})fP3Cz|68FTVB)mS4#O0y!Y2OY*_1JNUJZ+ zCMIwOLJUwW3UPYLj2bP zA07sL9taEQJTJjF5F{TbyFN4rE>EE0}|qp?UV&R;Z<2!*2{6N@L9X;Mzr zNHp&9O!4?rp=F}6cz_`f#HmAGpMRt^;dKnibU`7rE#hJ_s-uQ+{=k!BnsZHW4_xd$ z5=-dyxHN3*fGxgY$Oq2Rm_Hl|0zVR@p&xQ!R50kXjcQQKshu0L2O zeIXcyC^9G-<1-l_e;VMM1HnL|t<8Fm372?+DFQ6_BcA{kTVdi2o8!r3G#q@BG2cG!`ao@7#s}CPO#F!ymE%bAP0e%W6Vz|k}3T-Y~=qZ!d~?7#p12lron#qa#~$78Yh zg-e%T`KnuvA3HHQHuAQ&zj^)o^@ImUj~!dHX2VlYJsFI6-}L6YuD|X^*qctJh!;;B zJ4P%5GS2QGlMMKPt20Ir1!pnxWeEvlH$)!tjF}XAj8;uePG&RNWLtYtl4@#i@0_2X zh3?VO;b=5=+ikBM8681?ZQ=+YoS)@a-SEp)49`rV_0_;c!i7P4bY9-p!d^saSaGgV zvyrH5UPNH6p+*SG;UpQG#Cr%#h<-7C<2Wj47>7mTHFM_G~)377^3>hQlO zRRq3b7V4R~w%s8B#XT#6 z!~fe~nMp2O@F;AoH`eS0qi!$mtkA8Nam6AM7&E6R6K?A5v<>Zd_;?uN>MeK}{sKtN zqao0y%k~(qULXL5ZW-4U$ao_;G2}YZY`DXVF{7|Cm05Gyp0kH8MsE;-niAy%6E3T;18LRC09X$8&n>!Fn~=QX}FD)|vzLmO!l~*yIVd zcmp*pKQSKBP>@mE#%rkb2MHQr=~iej+JIOs3BVbBGg{^PM&#Ak-0+4syycG9yz%;* zUirE=y!o}SebXyn{n`ziwkKM0j;jN83BQZ++G6x8L!a*S_wK+it&&zgup*b^rC(Tz%aQ zcyhFW#vr3e6a^=vBbW(i!&K};N952<7%DRLr;ZBHG0n9!!_Zr7w4z=*efCnWP(5?z z;*(E4vvuqCT(Vt1WZ*kC|NuUlW5Mo40 zwzgA(MuR7_??{AU-uEBh{HEXEa@}=%bNQ6hB`CV<*M9xPiDUHg2cP|&L_9V(yU^Yi zJACx`*Z%bzS6{uqzqhNH&vy0n?!W5#!$(eS*s$(B?|oNiXGbwtTD59DWARUZ@`Iai zxaLi7xr0%d7{>99WSBsxk`Q(#=0-BdNsAMOf!?UoLadsapMgc|)@`Vi?dykr|M=+e z+|2Z=Zhcj6PnRsXsfm~-om%+zxBh+A%9VR|?@px`06-UR;E{|P6JlaanUD2rNPvbp zE)#PN-Qg;hu8FL?ka5*eT|`?l*H6R4;*ljM&;mC+JD2DbPeBG|k{nT>pbl;LR2{uQ zPUR|-ve+t$XhD(Wa)3|b$K|Ohq1mZblPlI+xX4;0s{|~UQEesXR$L!qG8s#nvX?8m zXMOtAxrKC^+H?;V*5gYQa&(~VsFs4aSWXf|uDWYVx@eVOLPm_GYe%kCbl8az`fY$> zU9USc5pF8XTEV+CsZ3n#TdK&}!hg zG{|cvjzs17Y&RuNpGZL>^mxdG!!eK~a&@y027eTl$WHcx;@FY}T~J>#vv1r24I=~z zVXAK<68eQXC1kLe-k)r3gYC@MfIwVK+)aq6C#-O9em#E$Xa!34x*W$=K@&W=AqtEl z{m_Ha*O)_58zdC7iBe;!sw#M6fTAX<%f)EO{|A5cnQN}vy>t7<{rmRp-MwSa?rr<_ z@VAqB#n8|&)5CYa`<-uk~2D=*qo&KKaQH?AyC_-@YBYcW&OdZ~OlJyY}thdE*UNKl|*{I6g>s zymvAZQ4Kt;L{v(%C^3{pA2wpKr(~$gGRO*7JWVa7QvQ}(U&Xw8VD+*Oe&~bCmiNEq z&2RqU5AW{k?z!#u+bg=AlYj8RhnXq?*e#48IM{CMinz*3I1)d9{&cBaeenJV|K%V5 z`Jo3M&g&Vk?Dn0z6RquE`IoO;bM1ALlhY4A_@II=Th@1fQqY<_ z5w^3llWRAw?d@Ftt#5p1=iV)|)6@6-{1^Cm28io#x+#;*fAc@Tb>-FjN~QXJ_dK?c znY-Z?H$M5~Q$s_S2!0=Z`0-2UFK^qqC6P#c??1n{Y0Jjh+4*Old~t4W^6Kla8a#dB zi3cCM@|r6SJb(Dmp~E$T3gZk+6FzpLyk+1eybT4z-ewPii-aP?b*KyzEW8g?psq91 zQ-lmOgra1!^;NgM?#SVTXV0C*wE+=jmW9=uGU@q?mo74_BPMx33;TeNx|*cqDLJ@s zl_a)ULV_lC(@a7VF$_foL1%;dhQDdJnhAp4FtAg4AbHCrDX$8f=oI(_E6s!^AjbR` z(0E>{kM&|fhXNl!XzMS*R8xKHru7U|y4*;BmzlT|+HnqO8%ia>#;Xo#X~Z``FC{zY zpSz?}trHjzbcaRJV*S{$Qws|Vj4~z^B}j1@IHeyu3K0jzlB=^+0vxzWmU7^@T2@D` z$Qy7qk>Tr96mW?jd4C%QDFrDCxoUNc(N*0cQf-R|X{`{_?v2=xAaL%oP?3sDT5_^7 zq=vIYt6;F%hN{vX87d1Wm2hZbTm_;6LYqiqT3tPT9OB6~=2Pi~Ip&g`J^d6ijfzC$ zL@0qkprf<1r?S#33+1}CK*4~;-w70f)clS1X0}FH0qSJH^+QC^2 z5tGDOXn_pWLVR2LC&#L5D&*X*a!N-UxDwtZ^)!Xl4_rJyI5cuGl89Y>&2=NAdeuNCv+%?dPdc*~!sZLW#*|+QW=K0dguz_l z0P3Z-&i32yxMT0`?aNm5uU)(Hhd=ny!2>Ta+?Gn^LMivU*T3%Q@#82*f8W4&zWu#; zBJ{>L+_7Qfx>zF8)zR^v|MwfAXxoZa%dfa%@1=`Fv3O)*K6n2;zeLCPTye#^wd>QV z?B=bTAARJ>Qzwpj{qk{ONY^0Y^5U!v6OYr})4ifK))5Lt5{Wj38@y6SPfsWmZj-)s z$FwZg>TM>xkRRKBhE?+eJU zAR6NW)`XLjMA1*(Cv+j15X1MGh;_|ax40mQAGHTPoKGO5LXkrgk2Vo0V3Kd8705VB z6>Tt4ZnEfDv8@vaezn^QqDD@@bsbf`I#N0K9P3@gsg?x?~ib_l{s#()3 zLfkezwUkCkzRx^Wp z}M-Jcj^IvY; zzU%F8e^aSk^7{yLY!a$%hThS!sXzPt=O?D8h`*>$Loi2cO}r2$(K&{5%{;4;eo-Vh zMS_7~X)I}}>BBp4$-`N_$){Zawa@>>|GxJ6tA77~{n7JJz2Fac0^a6N{^9T4a?4H6 z95~S4+1c0E`}sfq)9-)xJFV@BcfI$6zwsL%$Y+ax`}hC&-gp1n>a_#^_T{gA<%?fo zs(9P$?)Za0{GCER`}~1}x4r6?-}=qpJ9PNux4!$YZEeXnyylHN_w4w>7yjmb?|;uT z&mQsngTlZPBch{8$T`)!IPhO2V9@a8wZ@sB?J>0B-wkH)_Lz3+bI zpT0Vmn)s)$es%4-b&+T|pUM5sCx7q2!NZYA94p~ZdS~lw!rCMP@)(37J2Iy3*m^EI zzjN=dfBDLn$0sIMuU!81Z~Vts{^{Q+hd?Cw#V>vF>TCARFJx-v`j@}*umACl|NDUt zy!&Gx{jks1Jhzbk%%}hC!1K@dE$jWKfBs@1G#eW-{8ghI=VGN@Nd&Q-CQ?Zb~>#ld)cH14*lD2SVa)r}p&u-tgDH7I` z2=IhJ#HXjiYN=HATi^T93kMIVaZ~dZSL}Pkov;7D|M6c$`tTpB331@xl~-Qzn%Cai z-PHjjPMo@!E995=^ndwZ{(W+KxLC;Ioroy$Dq6W;9391aJ;W$`6yLOjO|fzur~_Nz z8Zi$27zMiKjs!IHTg)@fZTMFF67WHujJm5=OHH~vYL^^%pc7$*dYhDL)+R9&h~dU;;MtixW`D8ihZQh|O= zZ&WO>^5Zs)I0liHAgknMg;axDJ25Sj-_uq3HG$H2;A*N+E$yn^e0+HlO^euaS}GT3 zrYD%32ka}#VxPu2DR9=Dlq&OIrOp0;rs0?_w!;h_4r&ERvk8rs)X^H`*>w8!i4z!fUtcHQZP)IdZ+qvR z{R7?U%v?IX(7&wvjyrC-^2#kcwr^u{Pv@w@mTl{Ayy*)3ELg)LIDGlyxr-Mrwh_s; z#iphw&!0a#Hayhb+3}V;-|(*YyldsE{M`hmU7cvwL@K+PZaz zo*Dpa{xss~hP%nm=razxQ zG$ImjO|*40H4cVC(5=N&SR_qT<$OM?J!;0B=4M}eN7svo4uJE0_ucocZ+^GMAJ$u& zJ>Gln{dr51_X~gf_ZKfs;$dN?G+YcdD{?AioK+duoFPe<>5M8rffuWI!^XD&}I(`1%{_R^Zf!GdA%%*fOL>iWeD&Q{q`+7HR z8rZRO_4e&+R`j=ST0gLV-^Tvl_RfyjhKd;JTz$>LjU~mC!jtkrvYN%c`ks>J6w;K9^jN6gKj9jjJzJv1W|~6vtr_<>Up| z&_pFv&-@z2bW4?`+AgEkFUyczUhOTp5;8Au!V%UiT{RvGzB?7p>PWhXfvESza@Dhh zFvzR0xdq-$jgP`h{A?ta2!Xh2+09!v_w+7TI-n;pN-wm_QG7Gx z9kGg`%xzf(Jb+XMGEs3ysLWqw#%ehV7ftfN7LBx)E9Dz+zVUtUf7iR-_0IQy`2E|q zZ^`Deb8~Y<_a}~>$YzQ@Pq1EXo}Eq)Um5|}6}xsuLZQQlj?c_2_yYRyOg5W6cI*UV z85tV+;QKx}G<1Q%_6MpsT06Z5~74SOGX_^#g;^mNFq{(vhN0 zPmXbF=r@vL44Vci+BHp+wG|4C%D66h(OQ!pX0&^!I62@82OEcsBP~$c*51Xe*{9ua z;!iQ3P0i2m-Meqq>J_{8ZU4J3{X=J0XR%QB2P1EJ)7zPze(1v=d&RBSrsn71G+;Ch z)-!KHmQ!M6E3Y9G!(V$vHArY*U<;1>(MKLT_`-{4PMyB)nj50w0P{2aFX~Ozp3WX{ zd-ZL%y#E6q$fYuRukU<%WOQun){XCb-(9Ksk?E=Nd@+CBwO1F*`S<_Ed#}CW+Dtw* zmzqr`6Khtl@%aOv{Jl?h_jcpm9DQ;=Ha6u#1-&#u7GT#)Dnh+gew&-!DHHF^4M8(Q>Cd^WE?0L3e~cRT!g0gq13(p zCMGnJkk$~mriXOI69}}ftTNtMA&11MOY#`%+8C+pYNx8IU^z>Uu@sw?sX*s8q}e&A z>cV~$=K+$#k{w$2(hi`$go>r5yvw}ov{BQbItcEPg{{^RzjB|NLxC2P0uAMhp{^3G z43st3z(XF54QR68;#;|D{rU}?23D>m*aX|H+jgy7wK^0E_Ax(Sw+^m#boIRNz3=$s zCqDAYPki)KpZe{-{$2$>_Bbps6Uo@Ex8Cyc-}?ARKKlOO|ASB6@~T(rowF|`VUf$E z8#1uTwO=3LgaY04_j?J2VjvZcgfLw^K`xUbn#M%8Z{N3m^RDi`HR)XOJKz3(KG#IN z3_Jay;M%q8Hm+Y^%ojU5+qQ4t!8}wX8F`XzvnLpcwzn^9ZR@{u@xt8vtk>)7?(Wa$ z>t{|4hQmpOAV#)$Mn)&WtB66uIf}$2@t5$xGRkY-MMe%rC5;2##jRp zo)iGdal&75D6Np{i@7pDlaQ&%#=+x`f`Fev7yRf5=%e|&QKlOO;1?|l5@pZv{_|K2Bl^Qk8u zl2~f_*{Owp{<|;z`;X^MTeEwN*``TB&^xE5BbLVUCyz@10c-LKbjZaNY z&(HqGhd%h8_x$=>-}0v4{hbd#^6;-Bk=DU;m;PU_-UGm{qq_g!eZ6n5TJ_##%a(0f z?l$fQV*|z=Q%nyegg~fCAOS*vUkCvLN$Aahaqp6wEX$T9S-r1TtL^>m>t*-<`JQgOLW0B$*>qe!=BqE`+LZRsuhq%K*#>|g7x-~h|Z)zbv;C{STaTdWj| zf=aEYNdR&$k^?kI`pQ+AhMh8ii4&C-2~a;X;WIpm|=wK>!^wH7l7OWqEK ztI_G1LVLrCz*BFju~RyvmS6Ri=dBD(HCtLZfvLN5+ZB-Fl#UFbXt4IKxP9SBUwA4@ zkcI*RkWR}TD4Mw)v4DQnUj8saBFnd2c?CZ7&O2}U@JHXj>EaFVd+(he``G=lK z@%InB_~Pca_Ev%v>``Oc=;m6*Ogj{5K1RnSC@jJ(OVec(5slHpu2ETdaq~0y@ps*R z(`P>S*LU7`*Ok{_H|6zy_j~{G^ixj-!wQqvtX&n2geH?2&-By<7hM2?(j9y20_iSB zuy)Ow6)TplJZserH{aCK+%h(v`qnr8^#|YoL3i&-U%;)GPEQAY&u)3<%U}H5wpX?W zgZhxQD}dsp_V}%?5=Tv@rczP~Ib_aLErQCJ9nqJ%amEDC3H({vQ&sd#djkG!HiOkY z_UI#j|Jl!e>5E_d!*3tV;VCqo4B@&hz`ddR2{tTOEx>eXvW)Iz4+%M|mo* z``ED`pC_7#;CubLZ$dBVLf7?YrbCQ_5ea8Gf88>n*MV#OoInG>a=e!Gh!!Q<8VeeX zOw>lNH*^A$exQmJG1Rg#jldKlW3D{-_wP(lnH^zp>^*mxJk7hu;hupc8 z!ya%?9-vMYeAQFYa0mh8;PudpLQ4?z`2vA(yf$9n6mMt_MB>%HAd`PdmhSoeZ~yq+ z?|kpu|N5P;{^Qr5d}?zrR^ttZv-&#FRI%*K7k!~%z29Hk-#6aX)i*RW*?qbXl88L~ zfp995OQv(lOn!7Msc=!!;1BmMo07h1L0|V3!f6->PvSKSMPUVD@0)veJ^J_)&pr3J zR>!J!@h}vP9XxdS(Wjn!@ue;BGm%Ja+O!FXlc`K&ea*@hD}uog+?&5(Awu2!+_vGN zF;kMEzH@ZWDf!PNTa-a#JijN};_Yi>E zFp|CBguV>!hNn<}W`?0uP;sMK1A$XF4Q&-F@KQrrVMiRd+)a=Kga$4v6nba)MX^eU zg)|Xy(4M^e$kBsy=FX|FZ+h{im%F+<&%fY;L?X81jqR6RvMC-2q>`ELuKq}@4oFyd zqOSI=_3O^raJJ7=Rg#c99z;t zws-+-g(J>DBb7V1@BGhieYdZ7puMBv#+xqr>%V^AXFvDXSi<2$ouP0d9FEPK+mTA8 zc5HtW8(+O<`K&qZK!(gtFqR^X4ZWd+ZM$ zKW@(l$cxuAY`68%+wMJ=^+$7Bx03XeAn|9dKg1bu!N(bP*l&@M`F=LZ7icEHzweWu{M)gK@#*Q}yt#9hFJHX-%{_bGJRFUL&p+>M_(uA;WYMBx zzBJH3pmiHD8qvje?mqhe{@;)Faq4KCv4nzfK;24cojkECcDDm4FsbKq8A(AwUbW&5 z>_m|+GlIfiv;sMC+NrBf0E?K|TPpjsyen9SfNOwQ-9GeASHtFl-E~sbjYgVxRX8ga z>83As<&;o=T)NJh4GGGhy{-HwdR}o%41)Q)RM+R?D5CwvHtA!@i+#c3!~uR*CPTUn4in0lF5-mKFvfa zt@8P1&uPE$>Z>s1Tp=UBtu-2lq_#*%a@DYUY!qH-*@=QwtX@$fXPO<}X^fa9%Pwx#P7RBO?=7-+H`{ zf(xw?OB<@HwrqKR#~VA)v0S0>FaP|t-~IYm4Na}lXk4qYC>rxPEUKEq6GY;*ct9D4 zW@BT%ZN)T4fw2gAILPAKj5E~%r`XV#vxq}ok$}9O;7A;LVx2DVslI_6U`|~_>-hLY zFc3K1-8(om+SF9H@uG{vk(zLzt?r1E0*81~8v6^tWcIon! zEsYJyROYG2pALqCK+fm#OlWpTHhwV-Z_V1}_T=dh0`y~(=KOVJ_DM5HlSbLiKXt=&M+7R&uyt=gjw;6|W9Cg&*3J>VI z`o=^e4&m4;Ok-dw36(ZP#6Y{f#%@_>Mc@ z{f^t-b@SVAc>CKfyWyq_Z+^$y-f_!qZ@clP_uYHfJ$JnG?%UsS-(B~%wY3>I5n8sp z$FL7{O12}5fDsU@XV^@&v<5BeF>fSg0^|h#MK@zmq@iR|$^#4(YAFG-afjlb9Rfj_ zgwNM?@;G{H`Gh|bjo?v;02!W$!Dmlk!czGi*@*O9yo%Rw0_m(+z9bqB@7;TB_pZbF ze0j;@Ic+V?df5`bMxUq%U?BN?epY)c`Q=}I;zNJ``M>+nN8Yz=`AWnsWJ%%SA)>Zh zvLry6n0|z?EJ`nv0|7Ah`GeF#uNGX1MKEB?EFm6HaDqzIREq%Oju=WgL$z?C($+~d zv}3E?nWI=<^NiyPMgD}nnJ`6Xz{RXYRwJC%SYRBU8j5q)`u`NG6anh$8W?Q-f&=yT z2gEXAn)wchH}nM16^&7?Nx}YfqZ&N3bphv+gtoS#jX+p4{~0VPcD}L$E8M=o&TJ`X z+Sq{9{`o9}YfjP|3k#I(+h70w_x>v!iC=Nmm2Z3d4HL;R=2DtPqOqRtQ@LC&7zoxk zG&MD~6-z`6L}xiqbpW^K3k8znW2Hjr!2Ug5r%y*CF~Sf_U8OIKCd^#`YcV^u!en|n zlg@yS!lh71_gYDGBsiLKiDNFk;>w$Edsiw~dST0ppZ&zgKK0R$KKs`@O4FfN<-lc$m36yChB62UK^LstSKf^(YlrN)-qGE#@H!l z8kVS^f2w%@`|iE({yXlz^^OnRecN5P+;Go3-}c@+-gV#Yw|@No`|h~)x|?r( z%iG^|A1+|*_ z_`=i_S~RO;UR`}_ELKkxPu@_IsI@bdB0)=}QVDr7g9ahcn9Gr|d1?}oYp=h4{({BP zL=9d6uEIl9I^Yj#f;G*y)dsDPg8~h_)uqcXyA;z~x^&Uymv1C?uC0x)Ub!;h3lTbi zYF&LD-g7cJzH-HaTW`7Ynyb%y>kSv(cI!3qNGLU_FVk2ABePNvsvAR@F`Y8HcvX*t zP;@M{G}mU11?oXa(~{jV0D*cA+mdN%G@1_>E2ai2?hrUeh?{-@#SE(_>%c=I)>)5S zN!}JnY;+1;jDGrQ@}oxhSiLYKaMU-xkeFJCBs;6(IPMDgSz|C0at=XM*a)85w`c#v zWCrF|n##5-SR!Z5d;H;QX>C)ALS`EVAZ%%@j+LDXiUMQ6D6YX@?pGRUE~(fX!?{zY zEtR5X`mH8ZDVK61qa)8e^K?3uX>Dsc*?F7{EIFR+Io+L1rvCJYUzN+g4HsPS(hJXx zjEz0@_(KB&g9K%r$2&Vu91r-yqr+p}C%bgeb)u=M5#DcmX&buB5D+1n6|q)uL;eyd zvqJUsg%_P)Uthm-=k9b$Uv&+K6PI0iX?uGUS^X7PUUk{!S8Uz-3PKA<6PZl5yYJ+s zmt8hGH2UW5{ny-ZMMp0cP?z}}s8jje0et=e$zIp>|XzNxwX z@WG>B{Oso^CPy)njhim|%-??|6d`B#pMUzn^F zG%(UOtK(xI{m9A{D|)(z4({KV$)y3TcQzRp#1Mf|(RkvLw3G-7C(cyw4|uM;^77HK z(eAEOsZ=^w%w-FO)MR>OWbE{*Q~mwJ#P3AaxombKl^W8E4@L;mx4pK#^TY|fgH&CH z4$d~CFs74_QLWjxN{@BJ2O(e>&p$j=S!>-RJjo%xYNgurOH z=bqKjQ0pREIx4dgg0dc)q7*C|4$=fzRC(eH&{|=h8BZNVh~QET0(_TnZ9xEG>W>ZZ z_v}45Ihpp@bIfWdv!uAN6jrG~FBa=Wzx?u!ZLe>A@x_y!UHkX!V`pL_7mn9m zd+k+$P#_$O%$c`j`?gochQ@OFayFf1;vJnxu03llZn3>%)&&=A?CtG&b?Yl3-H*aJ zLfc_P0X=YF3qP3cm#tW~c`k{^bM)Aeum9s$9{bayyLP{^eD&Ivrk0-5 zr+d4Hn%g=yoVPxah`sQ_3ln3C($}n8Gkf-|HS5+cS+e4}r=E-?Vy*2>=bgU+lYD9G z)`{_PECwzk0x)#)L^}GRprs~jvoRw8s?PA=X@q8K3jy@2j##;PjYdvSXD3F3!9a2% zwSVt{lbxMM4;_B`@h4v2zUzVC{NYzW{YAj97f3$)$8b? zLa*70>VtH#DB=HOk37=TJAh^5P@KB~Nv}r__*+rL1C15BB+QEW(9Et2l|TLIzg@F> z*-I}zckQ*;bj+DuRW2-EJP*#l^2)1PeIokN^FE6503%OSF(yg{vfm$k&pmg|o85f; z_=%dD_}aBA4(>np)Dw@>i}{Si;OukOUVPD}!GWJ(pXRjj^*tv60U*CxfHlE+w+Egrg`v*s>rhUtnFT42Sjo|&KKRw^u z(~E1i08UQQB?|gSv6~;@D+e|iIK>pb6!V6XI7uD(M>dx&xqG%OP|&gxKWd;O7m4Dv zDRgl_BtCg>j`gsafSSqh%YQKP>h%s)XRTS@P){}kE;_G^WHd5iJ5Ur5wu@(iDJKgE zDaee`iHe#1zbqCCNUGW)Akh6SdST1{{fEYqljs5GG_1qPz@T4F)#z?`GOQdd77vDM zq`5*=)4)dM&*36Vpp#WQL)R?Cz9qh-0|Kaae}SuY(N=w|o>ugtMo(-o4eHLSpq7F> zdUHEjyyfy?=BIoxoX*pRZA|v{31^L=zBlt?;E;c(}lBU zx6PeDZ{51H=P#On`BhhL*swl1p5C_g8F;jTy^_hcQ!XG9h*0Q@v$Sv zhXx1y_EfklcmSkt3L%-O2B9hgr9z&I;)JHw#zyxCzuiCj>PiGk#-usr-??Mg^IJB* zuzB-KTb_URsV5KY+rM|u-qYQug5j`ca&)7r>iE$kZ|>Z+XZOz2-93?LLU$_zc*+|H zBn}@uxaH}mU)lEBv16S?rKGe%v8rl3Iq}9DJNE6_bKv0qgNG01^7%k0B=b->3P?jw z{KjUSrl{!93Zl33nm;t*8)5pdcu+mmNt!0ZzzUHYkeeGCFTe6FFTb?4sdd)!H7g$Y z^)J@0J$EuSPVkb>X7GQ*gM%-%|ja3KAA4w=q>W%09xglddID| zG&VKV)yKU75BX4COlY%f5X*JKk>}2 z-FxY-*jJ9s-L0k1!E3(Z5%7EZ2gbTO2M-?Df6-;ZBk zw5P9o!+GbdTE1xhg86T``qG!2ja%4~6^>kXnV%o3|>?#aKZn ziIsl-P$-|zu35RPwWZmDNv2PR;#as?F_y_+dwlkI3x_lBE}-x;Q)u-6+u^+Pup&_@ znLCibm6M&AP^`|dMm&wxQ65$p8W1+(oZy&(=-AjK$7uu5WCjW2g%#^tDQ+J=%SsGo z*hGzM=882`OIKVQ5T%FfjCmmqhX8~~mbL^#*7@e{H(q}61yb@I+qdH%t9*FODPsO| zxiDQU9zMMP#TT}`_UdcfUVeG7e-PPYmT=?Da8sTthQVw5>?2A>w~u6y6gQb1!KnD# zy>r(OzW0OIw!iB01{xb13GtqL=5Zp;p3|oeA33o7l~=bsv!$!|WM5z3%UfTptx3$8 zy=2QX&$hLEBe8IKsyda*Mnch-Uwm$$w|Ahwf8PB0$;tHp{MV0q zx=**Yx1GD;{E=bGP%seK_vZfYQ(eR((i+Dh&FIFFN`;*<{WD33x3J1&C(na8IN`Xh zUZ^s(=|Z#`*p;D>C+G`=Bf7&S5Q@~)i35Sk2SQL1++Z73dv@62s@mTK=* zeQQ%gYjdn7(c0S9(%Ke_N6@NbzK9o#CF&A2b@4<^eFLtqC5-#gtN2knA{1T3kb;8+ zPC_?LyQ?Mm%1X{;$l3QO6}Kw>(K4buBZT5vlx@f+ym~N;LovbQ86N7t=;BK+z3R%h zTzgery!Ma3{o^&)U)R@r`pA(ZH{W_&U48uz{_}f1{r#Yn&*^n*W)n)QLBO~p_Bl)p zH-=V<8uCuR{p~lC>igu{rjh2z=y*Dnotz{c&*iiER4ScHrN)!V(Xp|yiR9?$*x=Ck zw(Z+TM@GbNshMJJW-Mqnw;fa%F2huE$w+dq8eNB`oYPaq!rR{dHdF{|vPCG7m#fs(o_U=1z z{P;&c_Tga2moMe#&YAuCYde1Nv!9PlB#GOXEnOH-M7O>A3MluS9(myR4;G6#q99}p z6_%arUJ-t9ohCTl=b%*@v087CL8jE3>gvJ|jTJM^d~=tAibD?E(7vcu3h(>@N6v)N zE1!K&j|Ng|B}IBLMCvak0)hf(pu?1Pt5-BPHQG!@(PDv|x=vf<;z}jHrGclqpl_CF zna7r@#MU!KI9QwwF^!mjX^&_H%z{v%a;CrnU0SWw(-%cJO}h)xQ?p|3GV0fi~FytMJp4dHf5)zh_gjrf9mK3B-+s8WipdQREuw`WL%c<)6Yj>oJoyM7po_elf_~h z_Y?^FQ|Tm}*Nr#9kl0lykUodQ(QGzFq=bSo_l1I?becI2ONKf<$c;n-Ax@)Maw4EF z{+KHj@(SOyryF|}GDyz|h@@3U8e0`=)eEY`2VWJDEEQfqsm zaBEDxFuYi*scT^RDV0h%Vz1T~Mq{y>+C)4Q@ZNX-`{VJ%$mqzd_6{VF$)tL^`@Z*` zZ~MbBSq#zuRR;I!PB?u=b9$=l;M6xUWqZw*mEEJ<5|AiM`oX_W9d3hVYk4X->_nq!JXT$k;#Dj-U1fl_` z&t_7=a0GKeB>>K#z@&gR`?vxWi&|{L=kdpUqSQ6pDo$g8>ccMB|Ccm7vOwed(p zO)Z**xeN@9m8QM5jnP0rw>B5c<#f6TE#u=O4B9bk&cwv%@W@bYO>K2mfMgI43vDn^ zd}GS?2SGsV+9p#egWFLOEVBiB$8$~?EjB%v!vRh(7|h#e+odE57;H^|MrQjsJ>B1F zA6$W5=7^(?L!E;4}vTb;3fh z1stPuvPDru5uW-n6xmX&-W;B;8R#7`1!kzCzW2qv#9aF8-~91Z{~)ly8M!z&Ic!*sBK5L_g?d-xKvB;Q{c*B#0*0h(;LfsD13NS! zu_GnnkQi7=|#kC<_W|>S*^mLs7ijY?zN#E+4y2jS_Ik@5EWQxY}5pa*lf|R+c zDwiTv^rVvd2A8NdkAtEZ-QXxM#PLkAL$eL&f)mhF_LOi`h)HORz1Ge(skF2sB2$V=K#sydEyXsBK(v&Fj-^ z+ucP4_^CHJXdwvx5G4^F!ZA5+NX%u@g}h?MNHhlV98wQ_j8R!R4o`6k{E#M)135LI zMl7q?Jg!huVxN#4GYn4`KK;4BO=YvAqe)r1Pt2i_I-&j5)3_6-08^#1-CVBgKpemc}|;nYHPGjsk6Z&b|Q^5A(S+G71J`1buX+9x~u2Q$1%jjVY;-i-aeN zg&?a6x`G~`K4pz)n1dNT945#RXDHG!IZfSJ1y`Y+cKB8fIm_ta#vx=g{5o&~&+Q_q%Rfy>dA-wP4!U;uOJ{Tqv%+(AHvab%6OVuN!zZMM@`}tD7k_6;38R zO_zG8Vv6|HoGcSwIakcl?dQMzUH|YHbEhqoiASzGJ1&?JCY6^|S;#4_h+(oOw9p7c z^%=#DMNu;=t_E0e8iEO&J$gDxiJ``rDYS7l4q>+P6&0zt2@06}YSqT@(?o5k>WDV* zL$!wd8Bngfgy$v(vkKRdF3DWXH{Iv&oAy=@e;~UPR^7WmdnR1Ufh} z)Q>cW`v(0UUpy8p`vTY-09#vUMMC;Yb~c-z7#j)2VnkczX?<-s8cSp|>0(J)13SXU z7==a<=YS%(f)!Xwn1-`qOOev(&1y1VRifQ}z{#N&^VA-@0pAO6VuKRPr#1Z$X=h&brR=yYIgTI1%3wQFnY z^>`L>?zAToj!#z;(BvCx8{6C3PoCJ7&E$RlV4|iDA^Sbm$;pXGZR_~hSeAU;8>9;% zJN^ZUA@y_ z%Rcl=A;k!IsQZ3klh+&ac>~2#&hjL*)Lx*cNXmwg(PH^}9*ll85R;`-3bH)dqt{(f zagU{HPRx?BfXSHLD6;{A82FW~uiYjSD8`ql9 z!d?nN2k5t(k?jK(4usL=f^(EE$qFfDpUH5paQjOj90i?1YK3G_C+EDhWFiZ%ZlZTN%;V#JG=}x8~+TZ zxOh5I^t_7qi(mL6XRLvW`*mBI&s3|JHCBcyPMlsV&>D#YWVIkTG9u35SM?DZF%w|?oOj+IO2FI_aZy{UdyOWo{__FOJE zI5HAX)IxAPUQ=7&kR`%Rj^*$*rnqpN7)YvMR667-4qJ-$g^##|COQJCm-$#dHb75o z2q#V(vay=ly2hr~LO$Qn*qqmA9f&pTwiS^j9#()GKcUX2w`CVDx_G0<6T0sDn?m8> zBY%1%ozB=?uG=%ElDe@;mo{zmDcBVX;|Qwhn@gw02m3Oq32dOYCbDe#{7bI5bp3hf zELpa2{`@&hmo8hlVD_9j9l>yLcwlIxuRB{T4zNv6*47gXGm(+lg%sCj(l|;mlc*|I ztzC1G;t3(DWP*7ZQ=k^aIEAw|r>x+JfL491z4&8sB|Kv~;g>dIxM`yqv&S#HMZN{v zh)dW)L7z1QgodZ7QwD&kml&b5$i-V73{;mF zS5seK(^OwqUsn^0MyRi?iN|A+fY0~LGcODb4xzvTB1?ffyeHH+HzAr~uXfDu`#ipI zAY3RG7#buLyLi0eU`Q`<$5yL6;b25>-G(H+)++#(gbAdf;bF4ul%WYe@ij z+LGNYd*I-aiOETZ1ctbxS=~?qtS!~MeXFlvAQE9mrIlJ^p6qazqG4tVhi*%E=Zc-T z5iVAY9tTq=7+)jWl){m;-N?36FjF|VmgYUgXsZws{|C+tzu0k%raxOI2KI8f48atU zl*GgI&6r}`wC-H6XJFXov+1F}?$+k!bI)BrtF2+)ym@nH&ueLGO((}j`iDmP`_dDW z`BXMJI#E64t!b#;x9g38!O_CB-eeq!#7I=}cj=TC3X1yNtTfN?l6{lvf}N4>Bw8H^ zh6%Mqp#?ZJVkR_pL8N|VCz6hM3+L&=PAC%o$X|Wzt#7;O`0*1rz3pv{jSaircs&pb zi_7ra)z|tyjwFP}* zsw4$s7`71ec+%-qZ|CuJDm~b9`qa^b$7^r) zbRO!MH~ZM3gQq%Aq$iW%SggLGmB>Y!DYateuX>#L?-9)r;>Fg z4rQwezMzk#^QW-0sw$wY-e*hkeket8nHmH`UM&_GZYF^ zkH-Ya<4-=GE9y=oeO4ou&GLWcZ-`ntw=O(GhJ)z&q{qOk@& zU(?DAT2otFTVL1E+)`VI7q4pvn->1HwYSe|X=$r#XaseFhC)f-Pje&)chfg&6iR!l zLy;&G4_KoYPM~UP3u|ntbQQ>iv+OvPLxb3H^{|USJEaCFiEC;5I;1^?9X+_^Oj3$0 z$qJ}Um}3oO<}KjXM`}+klQ$xX#o{QV>p~;(*c`WfyY-h~1--H+Kz{}@augOwiZiPR z&Se{HKfwZ#<%*>XTAP~)<~2BtteIdsW3eJ~v@f%%ytLcdA6sm+(%gEU*`XBefi(*R z$Qw$<(o|00qc8pTH-GFtb=n&YF*njoQ=irin&JPVxZ%zqKyme|5n@_l zz*tpLBDBG<;ey^MObz>L0B}!rU1KvY5-mieeJ77ij1H|?y_$Gs_p7f?jE=88|GfE& z7ytH`zsTfEgOBUmERzP|oUY8<_g@@jUl z8B$RO=8Iw~rklH9?gu~qp`%9*&6~UQ$guNq6b#$*BIWJ5D zU^=jzaP5VexH-61HDZ&=)Fg<}&1;o{!+$v<^ROzoQ(Ym1 z^JoFb2Bs7y#y2NR0e`l1(N(l?n563NcinW(S!?tptAGg#V8s(N8sX+>^y+2bK1Om* z)_EqWiNriZtI3Zo03=!wo_omD=97`o^IVO)^F;g>-{ zZ%dMvqtEOBNB8y6u2L!P<6@~d9izCB`R|aj>53G_mW4S-d-2G4b_PA*u%oI)7KXrU!bnvrZ_{YV|<{vw7X!}c><8_Gz%UA#Dk56=+=o%j#qGd1~TeNikd+xbs z&Yad{CjW_#ejpmJYigZ6XTg#{Allb^dVG91lg<){AzsqQPk!QqUcc@|e{hS;KB>P|K0EY=2yS2sc+DES-bA@M?Q2VM1UpGT`Feg&6$sJp6>2uvP~o! z^7&%NyaiLqtsrP^2{$Kv;XNL~#b7_zvsWnPnn=-35B@uHZV`)D}G^i>U)kf_x zEM}>E=8pHg_lm2o))EUudc4e_NGD*g{^QRV@b&i&{_1DH_^ZG9tN9CO|K@=QPaHdb z_q})K@_AzRU;ONszyIxT@dX-@z#^B6MQfT{+r7SNe<(0*@6Sg=2to)_X;Y>;;z*3`PTy2rcCs(ZFB`RVEfZdHmq;&>)xr#$2il4g3F} z|M}_g;J}t=pQMfTk@h1&VCvQtxpg$UK;C0XlD>FY$QRS8$@4C_;M@x?|KjJrq~~bO zLBKf1H9NG+07SG{1T-3A4(%D;kRNn5==k8Q#TiV-Zw=Y;a|K#x#22904C{LA0<%0UWopQIy ziLvzf;MwP%1K?aPLt;KLHUUB%9kaGP^9)HLZ3?Awa$;mwTRW3hzBJu?y05meH5yMO zY8wi=Ju5?UO}L6(5O$=K<5Q){j@f#9x5pni*?F4ai5U+9F*A_FZ4y$IrqUxr!`Vz~ z{rYnr{nKNmY2DRim`XHgmYc$5HFmGn+uw03dhq|g_03Qy*4@>8>eMM;FzA}QXv@f> z0u9j$Cq8F#Y$BD;c!NaAWMnR%svaF1nm2zzGBtkqc<1gtdq+k_0M1+rThX~hZKE3w zg-)mSg1g!C<{dtCWMZPwdE(SXS6%t|pB_#@Zh8V2(BIS5*w`A2MkX_bEt{V|a_Cql zpRaFf4u>QDfW9n(CKe0%vGEZy;-d%lqLwCZyVhjko=}$?l|V&`n8PnV!s1%JIgg?{ z_vtuQF8tl!e)iSC1HQnsPe1MV8?m}NSJvCSqVbx#nrJ*8i6(S+R4g8j z#)H8~ePe5FLrYCvQ%!9nr(!h?we>Bv_07~E^jK{}ytcl!zNxXLJzm=wit0=6VZADh z2`i+vf?$Y57$fdE-C4}%5u+$G^@A;pe$mAjKlJ-Q?AZQl&*`o=_w4HLAM82ZbMU~y z6P?G89^Ri!rDL^C1c;}5dQ<7#)O4WQ8=9)}p6u#GhD(>N-Lhpfh9Dm&fMT3^SY=Bt zOu^&SH@0YDA(x}2f;OF{nIcMxbGX!i6>!+68T+P3?xLdPBO4@s*TR*WJ5#cZMA0rS ztqZ%_5qyiu&@}6=q8$XPf#g+b$@GA#n`X;X6zroFcw}KFr|cqAX`==O0FFpF`l@ti zg=hg34WQTO!{O?6)zHl;>&Rf7@Rv)4wX2r4wKNmDNVzn5YvDqO8a_sf<_}O}NA)>< zyHT#Ltkq?CP)7i*DYT=;v4$Oe{tP1^fGILvrsJ z7vmB5Vs7?81(|?jt+f`){HOYACKfhmho`CH_YL zG}TbAKwFazTbsUAfay9qP;Lj-m@%7x^y!(<)mL40<>i;8Ch7)joS(BT<{r&%bPPB9$D;PNqP#kWDqU&EB!~<>scQv(G>8(MKNf`2tL{`QlVV zOIv+oT_KzHd8QXEUfw!;9@v59V1GXb+uzqaF*ce?O~ey*x^>FunKi4a=Ts+F9F8~O zUCCQh$x(;6A}`(SQb=c#bLV&b?ce>w$M1h1*@gw7BFnx!CpJ6jBJ|mF=6>OyzV!HG zkDNX=7zxLa&*M)#ghO}deO~9$#4FSl&Uvf!D2HHqbYX3}Si;5NLG;>{QXYv65B2F| zl1SZCibUh|Ay2`5EM9#Uy$BA8u&Squpty$-E_9^#)baX;*5Q#sVkG&$QjRfW z(b(E^FRu3a`un?yg`1jM=FVS?A|%Jha(TTmYhrx#efPgVn@WHFv!9N{VzM0JYFeat zRu{DhQzSmZ3iLrz^59VLM2;I!1wmRiEtUTJXaD`3fBpLF+g{VHAi*$cL$RdiO5!!O z!Ehiwsc*yqJsOY9p1)}8%g=|x5fI3vlb`C&Q9U}21%hq81U7bg9`fg}h zry@`gFdVIL=x`R_tk!%n)xy(NqBcbI>2%T=G7V&sc2(JB=xS_U1tvHnWtwsIbivAm z9TBKM=nDjBkk4hp;iz+_G-hTZQlX_1bd=fN>Szu`QIsJquc=iP-OM8giiYFgaM{4r zpqBMYV&?0sr+v|y+EO8R_q%R5Yt>32tFTuSg4~$QO8?kF`w_I)M|wh67$FSgOZaif zfjWhK3iPnGX3|Ml4;Xfx`(dIWd_aSwJ<=T^qc#=h;@2wBgoZ?=iwtfQwUoP4V^`n> zhiYua?XaPd4%pBJ%IK?89fTcO@zD>!CUgxc(C4)Zu?A(V|pK;|t>V+mWkS@k(Sh#n6R*7T%J4*fU|>8unIURMBcq8rxifpYvfm%_`UA^XosGLE zrFVn)KktI`7}`_?4vWV$gFRpcsOhPK z-d$mD*^ts0AV7u*$!Z#Ww3@1lg<^znq{(P*#9!3a6T#Jx`GO7Z0M7e-VSg}|FIA0=jU`7$1J!})LYYWz-onML?d>&nwZ#6k z)F(u}iiViq%)?@(lAX<+cIgkyT~uWXgM@Xvb6Jn^C>KT(G#C2WFX}ssT1Jn@6K%8R zUVr0F_uhB+`|rQ&-~Rn;|Mc}Qefgh0_wE1qw;%ra2lu@9y_Z~Z#k~1*?z#8AJMOw; z>CzR^aAS3qUBcGfhEGTQ)qZ7)#3e=kq>)&$qwQpInXhBnB$MzjN(y8>s=`n=tfM^z$GL)6dIWfze!go?5XWCh(S zx&ndr78Ti|f!$q8jr7~Dt1&1A{E)Kq9imrB9#E(Npzz^OMYIZGJD4#ZqtJ?-t29*~ zVPVyF2t?O^W)^aF1T5-?_FA#_^a70vH-$*0JvJ@WsZ%2>)CnQG^+XA;H0CcsRSNrH zDMOLWg%xBo2wm|<4i3f63j)m2pRE!UrRea^&PZd_012^Gnqb8-krwO&oKp@CcuiMh z%FJ(Gq&jErf@8;zOjie*nir-gGw3Q3q8WX}3Z~ZSs&Y1`RJ3Zkkk5?_kDTf}$>5xk zpnSw2p-?1BzK3lwm^7@anrMi0RauVLJ25sw!$2S`6w3sO!AK-#kCV#}Bg4ac_v}b#CQ7ArA)k@`dWy(czK=0vU>absueYGL5|#=0 z2M79x1_pXgogN<@FXT&sV2rS|uC|dt%n%bl4M|;laD~VPXi`QgC^oEH3#17!rNRN} z633nZF0wpTHI*;qYU^s=|DpTtz3<&Oz4dy(*SBNq);&Al=sn%DPwps?|*Y_xVQgw_wZn^*E7}EbMlpKFLj;j3RHXQ>KmD= zai!sKSnk|-qA}0`U8>SmL0PCp{R91{Gnow1golhRn?eOGO8p$SG4>8FUADhQ7d)CI-nNsK=m|=ZWu8HjF$tF z065~mNTOgqZm~zzR@A~0A~&=HFP*anLPSLebV8WupQ~46j!Rnov=$=IoidPis7HzA zyOo#y#ki8TDMy87D-MEm)_ksor2eWYpKj;S!j4oQ=k?Cp?s?z)Kl+~ceY~NmmEql> zD)hCEjFL(wPj#Jm^`)1(Pj>0ULU<;8$z(DT(_2vh6^YmI7YK*l1q4%}Vm6x|=;?X> zsmJYTnh-T{$)AR~ozYC?X}qR9Hjmb!)(8V5olGaK0h5f(E8+B}&`cAq?PX#eiy#5jBg z1`!J0&@N)=LN9*DH(jm2sVag@Bt|^QJdw%d_P@F7#IZv#7FcA3p+Gb@nIqc6j-ZQ< zMwU<)+V1f}`?D1$&M=$mmZ>VJP;*jMxhHAh)HLB)v7n2($??HrfeCWFuV>)R9j~Rw z##1AsCk`GM>+kbT7f&5NdT7s^rBaT-vs^ArP3Q2-2ro4D<05OUxp&%IW zeB>kVUA1Bvngh*1W-@DNYF@B-WwC$@Dd(rND;6(LO+v^psuzz0FTdo{%P!t{(FGS= zxM9O(n>N1XvWw4IwIt@R4*P=3mMj|`KAlVFQj@94$)v(-Ne*Mg)f!iYjTQ_U2o_}s zFw&C}zHHE~w#ggFtiVyWUoi^WNdIO+u9>YP4u>mSdg>bpTavMkLU{IT;46U~ZhFRGh3xSB*Oo1j?CX*UeQ@=)?5P z$Y8{H;0PWlPGL$nq!fvFm>KZ#Vz$I!oM#9SsTLhpn6Idv0jaT&h#@YF?XYqZg5fDG zbkdC3)l>d|7_vi4a{&US8j=F0dc`*mpxOX|;uOM0RB@GVM{}w5t#rZf5Wf|2lamua z|F0kZ`!~M+hd=yoY;=stSE~dPj8p(nI1Kb}Y;1UZWH6l^DHPJhsa(ETNM+N>^n`8- zF&Bn+^Ln&eM@PLL3~WnE=b4++lc}BCUpn1+%f6}{=M&Laojd>scZ1JHvo*lnm-AT*W=Lv#tJg3@Tp)xB(*SQs1*+ch5`C&wqZ zZQFXsJ$H0<9ozQGOGs0mNBSc2;S#e1Apj153Naj(*iE>`QpL99j~RVxl37Z}gFU;ac&t70uDL=5kTD8Au&WQxuqM zzBdA@^nNUeDisRM0hx3b2M1QrGBhwWJUq7R_3aH!HP^rW`pd4q;-bqgy5gG4-*wMB z@B7G|>&{*^HZqn7M1uiuD5N%!)=m!GOOu5lch@@sMZv!Z~NHKD)W0o&o)yDyGT9 zhYo%3JO75j5I(8|0t%dUO-XkHF~=G?cpSyy@^nPz7F`+|Dh_>PzM2^R6dl-(l&;62Vel zAE(Kp67r`o)7CQqOUfZeI=?Sw^D7tSlvxK>1=Ub%n3~R8Jp-FoBN`nFicTXzK~iTU z|4bJhnjfkRMsY61U{zXBTptSi!sO4D=&5`J`MB6*)(AVy+%%4pnIX z7X#Uj4pmpuHR8&t3IyA6G`e0ooM|JvRqzgK3}=lZjjlxlp<{Up#nuey9wuQ@9 zEn9W=g2gN5EnFUp)pmCt>pgV>AE(cr)HWpQ8v~(8JW(Hu*VS-XQ`gws2F+=LkmNY2 z_{8W~Dmh8YgGoaLgmYGS;$DeK3ChV8wJ%l{3i)6#(Ad!2(J>dQGnwSN_2>FSA&kUv z1Iol1vmY2s7vq~g@F|$UP#Z0P0>@cTGMyY8JPp(0iFi1I+Q-B3n)MqtU3AeExK~^n z8Xh36_WL+hQ`Zy-$H$TrOg*>?CLhVepc3QHU%D((8;{o2L~3J!aG<8XZr0qnZEdqI zzxJPM)ilTF9A9gOWgR^wpQ`QT4kTQ0zHsx1ed1Yj1 z#8agwO@~K@Mn?xvcb|+!!k%e;+%V*4Q>>mYv@|u&@96MOm%LRTvc|FD?(HwVxNG~i z>Z&4kZC=B}6f!h4AkJG%3YL&l`7<>m7-H_j(^i3o9%q1=TGY}<&ZTo83B!dh(ByCl zT0NC#}kevwr+jiABsNw@I!qA{pVkNMKYD`KDocTlnZ%^)9Hcf ziNWfLq3X%e^4MTGIoxyX!2Vq?GAn@3o3Fn_d^nNH9_~Eui-zRg&$vRRi>Ba0$@pjm zenq zc!To*()l6w#FF}1uUwRjN6(@(ocmanegE5E(Hecn&ve34Iq1vF3 z#%jY|IGAfP2*3bmNmajc(hA{aI1X{w%lVgzIZ+gu8YDZ?82kvZ6&(vVo#RlTjAe|5 z`=mlW+{KhPUSQJyTExwyv^*qj?uS&lYH(J-4NGR!hq)JSK2t3CO&Vjl}RNjc%Sn4Rmui(=2(h-%lVY zjhvpYt#9g>v!K0Wt`>m&p4syj&R(z-_@l%9_+^wb7{mkWx&%`?E=JD)CF3S4cp z6S+)^zicLjLsuROtELEMD~Ug&!2qC%LdS@z>apR$u9KZRwrzjriDz3{+vm-l4?QMn zF%gcMK56dMffeEb_5rB;S1VH_E&!b>p|pAkA~!KU0=7sK%MWNJ%Qt7<{N&^$=o{LK zOM-zAkYkDH?74HjRX*i$`FwsdnMbIlLmV9$sHv$XQtmo& z)PfsDzX2^5$|9tK7SDsd9ZN*~7t>W^tMC;qP?P{|kl_!6{_w!B`Um=^z11Wh`SHGn zy6E!d3nqFFj-5JE7#+%w4CY6By_w|6U9atb_4)clVydc;Ob#KlUAy0S>dA+F!JytQ zG(8T* z8n`xW-J!MyheADMvjsZ{;GDKrXi9@Kf}w~On-Bl8IFu-K0hqH!_F)v=tWwxk8W`TL z3ji6Kat2ju)bUI&?JFqeG(nCBA4(I_4ZCr@R4%`^ee3a~#}c(MMr7bvEbgoJg@R!^ zj*SfV^_*gd#-VT&#|m2tg{>=5=SUU%&pmxpU`q%x#O;=>e@s zG}hGC(J^O!U40{7h!9opQmLAnJ$HU{dj~mCa%`A{5wb<6`6(bP>@McXjEIeq02~EX zv7*|;*mx%LK5&O7@MQ84BWyy1YLEoV#Q6AkzxmCVUwomr_cV!`KcKZLvBEgx7-AYI z6%<`!T7{E@>^M-gITVRaBqs>!;gkth9>H;v|5(N-QR2wZ8H0h4a40H=>-QvT;>#8< zs0~-QH^yf-H*_>NwKdi@*VjZNesaHPC`x9aR51{QYCs1=5oQ$Z2|DT;>T$^BT%P1- z<(joOy!F=0uDF`ORyw1xO+!roITRmE>S(=E6k`IFa$tZDg|YjxXF3s0WK!cjecdhf zO<{aZvOhO)BHeo=*WWXI{OG`mBUQPK&s*p|xpTO?x7ttk;`4_iO8T|t>m}h3!ggVP`H|gQpwF&Y(Tr%!M|8$Tiu?`~aDWP!VIvt8HJH|A zaSrux{Z!%m-~D>;=-3Z`{n+Qe_5JVv>=&bB`Xr2l1zh$5UT-3j*!}8`+uru>=U?3) z3kP)zqKY#>JepDg;z|aUpAtpjE_FidIK{Zm1skC{G$gGEIcH5e;uJuP7>?E0q`{U$ zx+KPb{Aw-DkV~&IFPfql!MMXe@D2 zg&*jg`TUGc_&Ot2NITu`nJqQ27oeg`9N~~GrZnxDK79D-@X#n2xMmc$V}JzH0pK4B z0z1#Nage2Kas)c*0Gv6cBHs;e6%WW+XjZi~bH&w*N`RXfaWt?DgvB-s>d6G*twu8a zpqGPi22KS?Wpq6q?eTie*s*hH`7#CSHH%G-z5nT!cf6tIPY_+Mf?oNt)uP0^$ee(Flmt2ZY z9y)M9k+0*uu4YJ@>}vv6tyCStAP@Va0#>jIg!JNx$!u!h;ge54_3XjjuWvf{tdKrH z?uQh}kcakGhZFJd{^w7>{oS7&JbIGg&+F4?-Z>+xr>E;1>sG8;_xdYaaY2dNS}Fl9 z)n-IwW7N`@QH7hK%P9OALF$MaNyc8i`VwtiIJdo{y-f_lrs%K4 z8xJE6xT4$h6zYg|DpUywTy~688^=L6oa2l7+h8iLy>>K7Xa_iFG|9nq9bJtzMm~DL zrc$ewDHSFndeBCrX}~{^$S)gD^%TC5Q4Cq}_e>iKHMFFLePnB6aZ0U9Q{?#U$%)gQ zDg!9$t*aYCSN0u1CwO;CHLeBl9f8%JM;?Cg8(;s*?|=K7SGGPso*eaf!tr>`&9}U5 z-h$aT-FnMA@4Rd2vXw)FedA*zqeBC+NbJb|UE5!N>d@X-4(-{oW9th~{PB04Cp%x> zy6t=a{=={R%QwFAk6-!DcmCtIzkQ(RbWgxn#oxp%szF-2RXk{X&P|JrcqD443x+ConPFm3{0|oFImtS$s zwKu$#+$fhGPfq|eLCd}lkB^O~Gdb*>lwH%ciOliV_8liwV3Sy)rxJbH$rRC-uSyqu zU>U5$7WHgA)~cLcx46J~4BZ9a%mJ}zqPeBxth3J_>hB#RydCV%=TeIn&Odr!|E?W7 zUU>HDU;gipe(<0F_4A+p^wlk!At4kE=hEq1a&oZu6j5!&A4Z}G6wi{)r1VM$zb})? zY`pN2-kww6{>H!j^nd>A%FC}oSl~=?Lgbe&Vk63+yOYH+oidR-0!?KUpLnB*@k}9= z!8;Z36WFkHZ5mS0lLD$ek;-r0{A&MbCQ)DS4+Q1JA(FnD5leOTO@*8;1iGstLY5PD zwUc3}(@=KZ25-O#h39fQLWct4l{WYhtI1BI-NUn9bJ33a|RBqU`vsa+N5aNzE+%ZuZ#j< zK%1k-gmq804JQM2AvVL{VRQK$+mgK$MSP#qGYIU14Zz_!C;_LYt}ani%Y+0dLSxPO zrZWVpAj}UZY$d@_yqeu?Wwk{ zd><_<-L2Sw*3ycDEpwmJ!=@0WxR$K|p#&1IgF~Sgg*bwG1Exh)Y6KA_0IWj>u)2m` zY;9|Q&wJkg>A(Bz-FMy1seB=oOpc6=j$|e?y%1V(5voapWOA%zuXAp1oAvfvZ@cwf zx8M5iyKZ^c9q)YS?YG@_7eV>G@4fwkjTh48h0UA4{FyKOzkmC;)MWbnb2q^ZS+CSd zYy9vN$gn{=Zp_!d-XlKw+AA+tG|Hndb<2{`Cme1nRn8aSe^EE&=V0E*2!4E|s#ps9 z!{p-~?XwG$lii2+9Y3(+@ZRl-M11Sk7f<%~Wu}7ZQn1<^3x;X}!D!Iu9qT!MVCSoQ z-*|Owpg$A{VfKi8pnqUue4J4O0exE#BdD#d+xf;DHI1`IhDXgU=t?X|qZS-F{W1G- z%W$A6yqPFWD-krINR>jMY&M&o#7$u&ktpec%#R@y_{oV)6QSU7avuC6-YnYEm^UaltbAeV?;&sq%p`>WC+Cw!-+v0Otf%g+%?j6I|B@ zSnYkP<& zh)|08Jf|4K;Z|4IR9oK|K%L~WL5XU&dS3Beu23n2-83d%$jQ*%yuB8kXwUx&uEqoq zb8U=0k_jgnqhdldGM-oVwRL@G%3tmqbeF}e3;w`0b~Na;5I6iCM^vxjnP0FHhZmR{ zEQ>N=yN~0t}x|uga7-?No(>v{5q~)$~9o zU0(q#Px;EzUJSskKH2psY{EC~iA5qEvs&!ygq{;8k4{YJ4#e+$=U<|dRCY3v6f(PcytKWjznUYU3t~bx88EqRaeFniCx=X-gMEWbLK6G#%h9r5a0{C zT$u?}SFK&W;{1*0`-7w-iBLF%L>WDs%V4Xzx34@+%sO41?r5#Q=xr0cEMut9C=wqwY$|HZF77i>Y&%$d2{Z0 z?;ZEN|Gs!Up3mz`_mbxHbT|?#T#2u?wjr5JHnp{X_*0+%_^1CdHI_Sk;OK_) zH}2iN?_}2r!f9VHOtv;>(c(qRm)&~XU3b3!V;5X}DW;uGr;(M%=b1>2hhh;tsdPw_ zV%6lttWHW_=ZobCTRP;x<`O@i3u_QFeDBuh93Ik14;-2ZL@Iqzb zq|{5OR_Owb-QKT-rhJ}i+TnbsN@aRm#HytLxJ_R~gNOOyfBwh5y>Eyd!BeiPloqm` zS|da%AWH)&j9~JmDbPfa<_ozn-F}xVTIOut)1-_&(SQlVAVV}H+7l>-y_t|1k=CFC zqWsTR@3t!JsHGG@cFiw!vagxdTlS&3#H=aqYu3RM7^vc@%|WX(DZDNCKs;Nx4`>0g z9V+Bsu{fWe_fWn8?H1)g6iyjF=(2?5Y`r|*a5x%_gc+LYfj>HcjDd$A%*{euWElR` zXhL$UHVS)%o1U+!kgS%#c8#q@#aJR<>68I9n{iB0Q{$1U{#^cV1znJkDjn1c^qKih zdgE5UoK{(1a22}Nlnn?tEUiX(Sj^~fWuxLc8a9>2ZpZDz6pF#42nJ^zr_dkjO|7XG zyWzXd|LU$0#XA*;r}`Ts*q0OyqTyrcQBvMm znw*&2vib3NJd%jTYvMK2#S$!lLUP7nFw)XK>(+PP_MuOF{5>DMXX)xyBSXp7_Swa3 zo+!ub4HpaLiSbk>oyVIjU%mY18*eIR(}VUz4K5g)LR}a)r+W{;z8ZsUs!3da`6ZWL zx~Z+b5tYI=K%40R=c>?GFTj^}qOJOPhTi{A?o_pT%jO4u^YcIa?w7y))z5zRzd!ih zZ+^1t^*4U>y&paO*dwt-&Dhw;=y>1UIg5V%v){C}&a!7a-9ulBi5$Zn&jiqJjiks7 zG?cjw-StegRo&LseAQd7y!QGlXLYpXGAS%c%*4;wgX-a^o_(yXtMBVQ%?xp>=TuMc z>E_nCPe1<54R5<8nJMhvdwBcyU5`HYr{DhSSG#xY*}ZG`vE$v4G<(VND{j1{W6oSG z2Uj;d(mO3TRZ2}xfCW?O^UplJWbxv^{?upgy7N6xJp2&qhW*Mh*)+h2u|zFW24`s* zzSW5wr6QA?f`@30)>2SY=mF=cl0G%%4G41!F3YGpJV4h7&ZkSd0jP{u)J<2F2V`hK z#C!7O@vnUL6VE*Q2jVi+LkzMf0M%C(COw96_yz6a0qyE5yX;WUu5O#QE6KD(qk$pW z+qENd6nt?sobdU=k3Re-T`R9D@dpiF5G+r5v?T6)q1>wVl~E|0rH#xGhpV`X^M6+vK6YF<{XvoSst?p=V)x=QH|Z>sO!=cAkYy#p@DTXU}l({wH@_kM}RAl zuW~N{6Ny^CiropI<}(sPdpk3pG!TR`Ic0UF2`rIU@dx~&h+eQu54^NM>vc{(WfG+l ztn>rRd=UcyCm0GdjlsrTE-N}s+yI2(4q*;Jgnc_?zM;P+Bx>1(7Z#Z7&5G`n{z;W= z&k9U~Ju1}5y$PUNSrg2*Qe10_>;LBhXlqPihtB*WN`yp><7Va5Oh8H>8K_t&9ToFU z4IC)i@n2|FxUcqZNB?IAa;0+4TzRF9!{`4D?cBZ2A^u`1Z(BV`<2q7kX5*{4PB7Fe zb?7{-4uyh)56PZuuD|AEfAxta%U0FY){Tq|o;-1c`ON}mAI2}`HsEBDXn!^}i6O-j zjn8d);l(X4@7VsvsqUWRU0vV*&+n$ndcYjuv>P89KXUlU>pR}qwr%_F-MgAQ=2Zs* zM~@vY*_T?tWHLEHOjO8aiiIqiHl8WH^!$rYJ^EyFyd00!Mos?Ymxo?T^3yMK}^C46aGkTy^CQTVHx*&Dyib+>wo> zrHS3~L9mgU!VF7nMI@f3YC1VSe(FRgksXtKFdU_2f6u9-hdSTfxmWikWtki3M3y6X zjm<6VH*U%ov$=eF&b)b>F1u!YY;f9~>?)BgBV&%Kn*rBci|8Qm~}g^W#>N0L+B zeFJa+%U-f_?b0=Cn`X7Qv~|?iH={vd0hVx`P2WJzKYadERaM1b{PahUKKcjbEOua5 znt#guz1+I368qr7hUNn3S%jh)aN#U zt;h*v0Z#4}jzqOG4jOuWgeoccOVwCm7;$A;&frneo zU_dDt?R2x9TmX6xA3z&Tbpug!TZ!9ooT+5e0_fZqrQ%RHl%O0(jXSEeZWK8MS7~f= z4csI^3+4yNk~~a8uGg8qFci)h_bW9};+nw%Mw5@QLJc6@p*otFT+1^J+&*X7x|V0U zyGl!%M3if6;;hV{Y;7{vOfFtX+S;eFgkkjpQZYj90md4mB*ljM#<7XvwP&4IDC9;) zM`v{`P}1iO_yb`noK2S{45^UM<};J&34J!AYI@)PBM0> zV$Jf+&phj>HpP-Xz#@sMA`Z=`;##%W9}G;UCi;52tDZ>&*WtfZcv{$olSZI z{@R8b3~h33?BwyIBO^mK_4POihyozgVKmY#&y+tBIdJ&kzkdCno_y-@Y9*LH7+j@S z2FUQhTFMH`ZK9RRSqf=#=13{IxTSNBdV3vnX{y?SP%qk{Zy^S)$y6i)!=mwcZ6ul? zHg9Zc4+O*Fk;P?@=GEP1`bv&ci(G*qm@p%oN~b0!lF70DzEj;@M^7FU)d9!_5}-Nz2=8V9Ytk=3PmGGaM}|frq`Pl zOnJ=Z5#U3xycI^Jbu=lF42N*i=>~@|P&-z{T8p2gBplCp0F0+?*6fWJT@FJ)l^UAJ z`mi{=#{hSReeq`!FqzP+Os20IY(&`Df(Cqc?$zcJ{GgU%g^Z3g&mnFg)7ZVrKx6SI zxlJ)YWix3EgSMIUBv=7O?G-mDdT=N?a3x`w)4kNl_;R5}}G{+rITf0h64z0K&6?cjXg^sdZ;dExO%GsF?GhnD;#L5Ba zT8%EMSUp5mhISo6#mVt6(SQ*Mh8lKUaiJKJ)Ya89dG6c$W?fBVu}Dkia6*9~Iz<{=#M62`MUU>!&ldBU zVm4FAkyBy-jg4(V`M_{ImWYPpp@?3w?(+tSW&Gh-p~_SAmdpOB;&c(+5=o{g3|(8- zNW2LFOo1p#U-zl56P?pl{z5T#>cn9%tVz^I0^yoyZ6XqnMB=q|P2pHvum00wv@nMV zF_JuzU7v^aQYkW_E}njRI#tl-*(Eo>{hdpet*mcsOHXEohlazEL{rOb z{9d6rg;fRudgB3}1UwVO>2>wQ?4}Q(O?+q9tfVbObHFX(k?bKWNmp%5^bjfy)-A}e zS@&ZI9&R=0!xIrGmY6s zhPtaSzwG)eFTe82D`T;sY=p$0(83=m6P#5Og847L_@dk2aq~TQyz7!HE)E2}!C<_~ z8}fK$PbhgSf%d)aW z6ObU7p;18_cl{O*J5}G<%xtaK?+{aj!?Xnxa1d6^5RnK&lKMCV2z%|Z+E64KO(bfC zwoDf+AxyzC!bL)8a;cJbm>X3PFEk7|j#D$SBn1uhLV3*p(5I-^QOV0ND+sJqMlAYE z2kWS=6!Rri=o?>#h-+g^MG0-^Ora-R^@4>n1!tx8nCYn_M~;sSkD`|f59lVHS8*NP zz8%SE`5}#Q&^XPGE5NovE4{3SLP{tioadw7opQw;s@|}74Gb;^rUx>lN*iDxOY0|} z>jtWHu^Me*Di(*5>I@L9rP@dlT3TB#*m(ZQlbwm0TG;*Q!+*pR3TF|53QmO)ZoGyG z)7Ym{L2r7xzP>4!Nn6h4scUSht8WTL;zX0xK2I#3AfqHgVMP3w;R`O+oR!q4J)@%| zj4vMOG0-WcobqUDl$;nL)YXEcvK)UX9A#!FC#tQlYiw%h=;(Or(MRxd*pH-QV2z?F zybcFoiI3_&-TmMLzkBidEmKp)O&4GC%#%-g19*Rl7{VnIg?W-U_=rO`y+N<$1Jb%c zNXnB&i@Wrc#h1#K!{C`=Yh`FuVejg^Xd66(I5Q<+S9*6eu%Wdl7u zK(1?QYi#WxO7eyDE-PZy<*UyE^Q|wvIMCONYX$+d7L+onNw6ZMJ^%a*PIaB!y?Zwi zCDxcuCCg@+oR#&6Vp5H2dqq>Ikjof3lDkAL;YiSIbbx1|mo1etXguUuvT**2HRt%^ zjh<+YFJ9+Q)cYcdP@)cgzOwywyhb{m3MXpQsmX$#k+1dzLxj5&Mt~u6<}GZh3*B-1 zJKyono6cFkX6@=#leuE&@y_nfqwqvuwMk`KJKECFTqzcE69vK|$@mRcxL`5>h;1TrZ zM!ckdu(vl63Eus#>n^$YqS{1k?K$U%Y8yO(h$j-Nj)daPP4gBlYn!{Qwx#jxbJq0@ z4j=FA^7*vNgqRVoxf|VaDT@#vQ8)5#TTMXvvLpF8yp~mH$r#O~n|Nw`r=#&%cwu)? zlbjewGl7p!1Vyw6#lVHRc$0m$0DyZ2M_XcrNF)X`30TQm=$p%Fu|-3hyVU#3Z4twH zJwTE{D0KG+vbl`jNn|fXMj>?9E~DC~F8CoE(fu$|SFL(eGOEcE zJcVo)e!FL3RxF)AtF29@QSmU=M?bPNnVJ>oz^@RJc)$3?FXvE~dsUq2?)R8fXigIb3j>u*@#1#VD z?lLRr$s4VyiElJ!Fi?R&1qdERL!nSKkJnb9xJ~zEFkr-d9s$z-Q-~Qd_7cF0U=@nOAeAyMR zy!gVKJ9p|K(aMwQ;*DZh;{$jaleKjWM|k*M96e)bePddmpNiMiYataheLnQNP$oQ| zZfl=Ma8y;yq3S~eJ>h(&_wU=cZ+LisAR?b< zYRTe}$47^SgVqx>$BrI3bm(v_QSY7y&ERA$!JNSsWl$7D@{ySwXE+&IShpp>NymyR zEez=H5iy0PB~Q>>zT@3*U4Qmj!EkKZnsciI;b6QbTvJb89gNqmTzmFZwSUo~MVDTB z!LHX|A0ADD6@;R7vN$W2vsZ08fBk|*^UmFH?yR;JtxuFntu3vuzVK4#$>R(c;NMi? zyp0=Y&zp78h7IA6p9CNpjwYfte|+FKxssL(;YL$!?PZr;vS3czIqT0shFD#5LqmN{ z^wB4t%;d9>$iTGIpD$pmiAtcQ2BqSq7p%Yj`YVwO zd4e#0!GdM`4NW(S2+^Vwh!7#BG4dnYlZqmC>MJ!?bO`GtkV=tO%yg%?2F_+p zYqYxR&M**|qx4f>|-NJLaiI3l6w#Fmqq46>Bgdxiqni9gU<8+NA;p!C~;lkaS?E!*&Ka za;$TBc!d16vgT#Qb%z-cQC*(Gf8f2eLarOxELB${YijYotDvZ(iHf3M8=aG`i-XUW z!Pyc_JAOERna|haw28R_QGf(Wc>yeTm59c8ZrGv(gnNvD*R%>lKmgTIjM5rqay4ILIN-LOwFD*~I$DL_)dFECB(<_T z1o1(jihBa@qTb(HZf$Q*)WnuAU-|O$&u0rI6j3xG_i3NSZK$Fy4H*aW?Xx-_{nH=z z?%e&{(@(wf@=NG8I#A)Vi3T!^mkgri6gQ!%22sMssi{~j5spN0H?mTNJ*YlgNdN)q zqn=geQZ_>_d*bl^t`kQxsT8`Do`fqCWgLo4V=e9Nbq$UAe9G?&w6x5IvFT*eefK+? zp3J5uC&$OqDMGw#zK}zsYwH@9EL|Fngm&$Gjj3y}_Y?@&^iy#GV2sbf{4gg1VT-JF zn^ZtqXXV}rV~SaW5e&)UNcB5!c?Uj`6nx3DRpoLq8Vcj@5M?ABZfl*@)pe?-zIpkI zl`p*XN_TI+2MJbJgELNn|Ba1J2qh8s-*o+T>(-rx6e5u@fjnFp8BgxowX3JM2fhS@ zR0poQ_S(AIXh+*D;xyRotqu&2jlZ#TZzhui`$#0(RG+x)@(X>Q@|?MI#wW%nC)4QT zWGcPog{}R4y(S__2{A&B4z*yajIEqZZd||Of{m9nb`L*5q_Uif;^eXbi|4@fbouNHU-%*esI4*8EvRT; zhQtnawzV-SBGP;;`*ssr)$!w9BO_x_Vm?mL=?)8!4Vg@ZowhxLisPvQV)4M1$;>!y z97)ABsN^TsUD%r#bP8eEo6s20{s|5zL5xmr6oaH?EBD}v?P~MEMzk&NYi3dFqF?`BH>6wQ;R{> z8k5G8(wE7UY0M6w5_L6e&)!g1S2uU=>^HXWm>3=Lg#yr^Y_d84x9E)+85_E?x%5jf zZy6bx7#$y*NKOVqQA?gpGfm^!L6qnTJK`rilpH8hO?*=@5N2E;f)%Lq3kAB4fz=i= zC>H)i-_$CpM48YeS(Jd0QwPBM1#M3&o@UpszetWG<;mG=@TvfIp-O32+uH z%Wm}X9h;)`zN@MFhURy_`?g#*`RvnAsf=N5&@l`^mri`+9m#cAktx66@EkudS_r z@|owmdwUCo%4Y|&naQ`k{pL^o?WeHx-tLok-F0`Vm_@cDW69C6)MP5tJJ_2mlwaHS zDxyQ4VSnJ>d+&`U$W)4>!(%;tgQ;{r5lg(Z_0^G~!Kp%y=roZCe&|CV!J=@iJ-vg& zBNG#o%w(P?o_u0-B1x*F>A_3tjVKk4LDUsjTo;Si4fS@dKWpXk)oa^3=AfmWC%bm; ze)C9Y_u(VQ_wL>|(9<7{MO)fhmn~ij_0MeHg6~~4f8M4`E<4eA1n*<+28JP43vr~W zfEQ!U#N^-HA)-ev>?@wI6ONzkQ`pB3qPo;z4){$sUCo@YteMiw%u}+Ht?3>Ec0I9p zJe{6INUj0FzU|0z<-F`&srXu8vLgt9)T+9?vpZWPn1x4r!-iWB(1NU9%$ZKpmZ1%l zfTIg|b0!Z|Luo_+9L&n3`(`ijLN7^1+w;p7&1-9Ec23q>RkZFe3xa`3u#S0N=QJ9A z4Xx5yAc}HV+%A9wsshd-r|^839)tJ7xW3+iYzW65hy_8&vs7 zHxAX*&_-r$F4gsNMf>i*y3$O&EZihewiOn)M8!E>FP+Bm7#8NH4SD@)xl_6+tcum3Dmc%^GHwkiPK$2PaHk?pWpswfA1g;!W2WG7}w%Au%JfCBWJ)L-&eV8 zimx~Kqbs09O1kYlhi%(V9>*$L3`J&T3xx5r@>aR5zBoNPGDtYq-_u0{T!18KVJxV^ z0C`vb>lXC#S!Ztu1w*G#b&?>$0CY%iF(Kt(&eIiVS{3Zxawx6x`EhWK_`P5>;tPk! zIHu&-gotB^FtUB%h<)zRSf_Rfx>Ur+rPC?UmiN@#^|b<~Z7@Pyj8ns>L}Q6;CS6n4 zSl`&9>ni$IRS5H7D6={#I(ivT)J79Ek!U=YsDb&U1;it83*vMun=Kk}h!rrT&#NT~ zm_+<)MX7hirwQ%gfGJ9Xj3S1wqxVC~uK z<}F^z)skMBLy`R4wk+h5-^ktsE_w1vYVWL7TcY9lr0oxT2|O_%19sj6c6 zhU;(Gc=lO$-*sm=5NvL0j>j90>^s71UG3Bp>Z&T=%dkSTT5Feo!R-uuH(nL_U}8~*?F3fWPCIUZ6cHz z5gBMkamx$M$+zv~_TDjz``3dMh{O3E*0>J0#hTjpRDn5(#}3q^Ocp z)mB?8POQ{WE#;}I(%P5gBLUHa29k*B8}JpEknJhhB&^Yu;%p|H)a`32tN<|iyyjQV zS`TRsilMEvUpG$zL2+<^+(0ku1_*kHsf1%Ol&z=_JK=bAUxC1w^mq>6|Op(%F_c;&{LTH4@tC>+w# znV(>>q>tenw#}^_j5;Uo`mUuK&Tbrn@jkk5^ zrP}bum{md_;0n2P0UJRMHhnu*XhMb}w&ps~;6HOulS<_?4JhW4Wy|9=wN0(F8k^g} zu)eXq89VQoQ`Z2t38XR5(>XNIjR<59_Fu42PP&)Mu!JacOLCL zcA)F{p;9qVjEh?knVxEc}Fow^At&N;r3$i|yVrP*Pjb1=h%LWT-!p zsMAucmarvO5H`h;_Ok<}glg` zM}1@S(q&6lEnSQfjqBODB*U&*y?Wi+bvTl8aq6*09)0uB!3Tcxo6KZ}P&HR92MF9s zxZ}JYSoQmloj8oKfF*y-Mompkkx-up(BiY_(4DpL~d#bOxUD2y?R!SZV| z6Zu?ND(+W&p9=eK$6PLxh4LFDMJJh|)w?d}m}?AlD;(-hWEzkw6zuykMSDR9&`qig zp)f{rv`Yo)3|ZW`(!N3-*TZ~@9|SDT(A7{#5A_7~^<}M7yO{|BG_`_?<}+XjZ8>Q@ zwJ1{E+)QB^6ItK5!(a{FSGUHM>Jt&eWlObAHj?bhH-H#v7< z1xZSHVXT5H*hW~TrzY~m(2qR&S zt1jdCv~M+nX8W`kicIagdgXFwW)s>}u&tn^X;2LT2v;jeQrLk^!iT%w``-O~c9M~! zUB$ejNWB!y>&fH`HMI?Ro0m5~7K+5<@w&Fwj(8%b(bc&cTS6D0w!X2c?{w$>-8+M! z7^XXC(b9&7dMGh$#Ys}J$<+ADmFxO?d$zss{E9WpzVuID`P`>Il}#5v@z`z4l`sH)S~c}zEO98_3NBYqP3N=O zj=3H0{qRS>|Lt$BTzh`|tT|+({*bO>G4BI}DdE>Y`Qh%@U%^WgyEHVnU3%3G&8>vA zet68J6Np3z@RG^ouYUaB{k>zF|1ecV{q-ldn$Ucq1xGCn@QnvWx zpZ(&e|NG;uTV9#dUh};l|2Uqg86FeXYZ38sgS ze&pk)dq%Im=CV*Y@{O;4HI_)ECnuN*P=LmU#{d1<&pcIAk#JyEM;o+|vuAU~|N6m? zfAyD;qc{O~`2aNywH z<;#}hoykdtMkc1p-oN?GmtKGURh#_@Xixy62^5X^tN7^SkN)I;fBv)o{_jgKJOBOf zeQz`tpPZcR=^aj{lq5%EG1|q$;YiSvh(?ffHkbS1kN#)hp}qIq{hpg|x$Pq#_~^j+ zFkzcK4zV$;H^XOEKra}CN{S180ObrBmi~FCTq1yU%I}J`SK&v1!${T;I@CSJ%+j*Mp8lBC+O{HiFsl@lk+atxBfNSt|;jo{q)huuI{py&RM%!kJ<@ml_};^`S|B++I`-k+XzV#I>q)%~&g8LUcXAUViDo{~VOhNn#q z0B9HhS{7q+QdfgN<4;`|imP|+DeeqAMu;xW&77*BWSuH~@rDj9(9jhUI743ntNd3Z zQ$a&P!|(?b>7w9P-SoEW<}X~p`3o-Gw0iC8wP&BTYW12`D_1X^H$N5$wY0X64EF}e z<%`)|A-Q7B+BNIetysBq`HJN$SFfThTd_Qrh=(H4;elZcipidUa@oo?9UZe*tXjQn z`I1G8mdu;CpuM9b6ba!2vFOE1=WpD2;ggR&L3I4icfDitGmnptkM*2BH83)W@N4Q4 z$B!QCJ>3I_j?bVAd4_w%kcYCcP zx4P6ZtG#1ZM?RY_7qT^pL{As4vlNQf);2VwM9ru^J09I8E z%{9xHFYO%~)dOki)SmtOj-BY-vuE$NS6&5=Wh%bb#A}o_E)yPbZGCM z6DNBgeDu-Z{PqvO`~8D2ZP~nI+beHu-~Q^>7q`Cn+|y4y`S|0H|Nc)8{NcerJpI^H zBje*Ft#s-F-T4ZyFr1rUN24!P5s?qXMY-Dr@1;JdkWUQXjRdsU_tL~+Z z&`TiAM8U%s3}fA?ld4K9|TVslu+ZavQ=Nb;YE=wgScx}dPK?Smxl7Aqe@Yn$gop- zM&6YId15X{2>8TP&%XY~&R{s^yd>_8xx`6ehJz~XJD#4|arm(#_z1~pWg@DwImC@_ zZ6rbpRc9c$j;_X{Y$VETqbaL`cE#=DKXsO7R{Q52`oarlVD^bmT_<;zQ!v*}aS%?e zqC8`ZmocZU(rFbDG~S;bV=G;$F~*DQ{3j_6g~EUP_kVry#TO3@3IZIWKMAx^3&W zYOhv8J=MD5v8QOE@Fu{BR^XGBl9QX6ou1?IzlC-qz+|h>{}Rj;~jO0%~Mpo?Q7x6~ypR6(y{l}7mj zdS`wypNAwm!a7Ej4Jh-aL0NJuP5Vv7s8QHR?lGD4ZkGMRa&I0t7#Y= z9a6AqYaPLGBtR_a4~&hE+;i_;L4WXne(+;L+bpZr`5^#^KeB47FEe_6C}&Yrz{uq|TDIUVztFI{oZ2R`uhGf#!W zVT@_zviaZn&Uebi@}YgZ>gwup`NHxQXH``P@4NpaCypG3-at_EM+wm=#PKnMJn_Wi z-}{g6KlSKS9=|`8AB#n5=FV9(Iy96{=__zPzc-eM4fOVrPlWI!)w;<94I>x%zz6QX z?6Rxh|K1NyX46ERW>`+IaeV`dNDg_Np*c*n%EAph;wOW=_yr0R#gBU>36oP6fiu0)^bG0-4I8);Gi~Gy$$r zNio_h+Y%?V)~5oHN|!2`6g7;(h?-g}jAmryCu4S{Tqc`ty5g$qKsBG!-8rZ@^-{+& z67?mM6S&v0krB2e+E{feIYGv1&NRgQoJptZ>Kn$!N3+?K&+DHvZ_&{s`z5ogsu+nm z6R*9(W-^`h2S}PC6B8qd2$%ZYV^4Q<%)S5PA3b&aNZYL0u%v%z_z~0p$o&Q;|@_Er-!IUQw$Wx+B*o?N&~BDjDSl&{mlbE{=pBPe)5@EZ5`sFC8Ec++41_kdiulScTkd|fpAEV zv8Ix#4}9=_O^wap{>HzC!cn`AYMN*xlb`&DFMRH@ORqS1;Go~@j}fLuBTE)7zyAXt z+WP7%%&oQc%{7V8H~#e-iMrT<{Rc;eC)(O(oqN_gpEq#t``&xt$U%vAdis(JFZlY` zztVTQ|J13jS+i$1H#N?mH~+&X_UhKKq` zM~4N+K3BuI&gRb`iQX|5-VDTmM;&<5JQxT$1gZ3gr2nYabhUTxoOwQf^`+;nUA;vJ2(`YIrKOyL@bhZHSVl{ zl*%X_K}`*Tq}MyxcN!cGB|zaC&^a9m?P*+-5>~`qQbfm`tdH)Q6Tw#tA^yxIi7iMS z#MlQVv;#1TBlMs_0c0$Y4C>m5&AkkuE`)?AuFU~psJjJK?IFmDCqg&B^Onmmy(AWk z(Rgek`~SZC{l$xxY~T8PGMU@3@q*QBS7%b$=bnAyc;|^gD2By|@5sR3qk)0~kP$^O z)?5Vns$fVjJwn-`fwS<9L^nM#3fdSh6}okXw8|s`cGwB1C2DIv`-Lwt^qX(Kv1Rjf z*WYlTba3=5}m(JgO^NqXS*zw(O ze~VFI1oY~XS1J9CuYcw0tFKR|GWE6fsjR*5sXTS}?YAB8>_&*S4K0yi)enFCwWjVXLxeLG|Y3(x;5YZ_iv`Na3h>AmTKZLoW<||_|WG+`=v-U zz?9e8K5uxiSDNDq!0b{f_v_#MV#(q~&<@bw|NhY%Zn$>-{MIeczVh%x5C7FCKh7vp zP)on;vWLP2UHi8c*dKiVhfh4cB@&H7nogle`aFju2qz?HnFuU_0ea8|MWq>-nuX$F zm3o^#lE4+5DsoC(G}CZ95a#wd3uN}C>QJlpO4rLU*=BJj!=MGfNF0ga`-CwjNoVpe z^YV3d_23bW*T5O7ahh7(Ga`#sQ-cG&!^49#KrP+43@Vk@g?ZVO->1(w2@}u;qE|1O zMQ3QwP==>_F?j{Ag$oxE%5PY^^t`jyFae2tGhmvP^?ZM4SA9_NT;5fa0o zxn+B!IF$gU&`w;MDdv)Bq6a7;JDblJ^k_Pf?B?Bj_M&`*Ky)PeCIA5c^hrcPR5W99 zVr*0jIQ#<89H)LA99K9?jaouXWrxu{Ep3)U;ot=@i8roKqbuq6DjQI-xL@2C&d>pJ1j_mJ00zJHUab z2GxgZAw2kt==4T?91h3!4~6DWK2c+9okp3CrLopmzt&ROH2sB=+E3xCIZ3LC1OeyJ zm13B-sVhVXV*%lRxw=#+WrNlJg$riC=e~Q6kTZ-Ur@yZ!TM<*9TNj7pL7--J-!qS8z$*DYCUf4&;I)vsN6FwWEi~rU^CS zi4za;5vPG*%Bu?$#bW+n|KGRH-*`Uzfq;L@<`-I9TN;`gM@I*Nvu5Sm{@y-(Yn9(S zG&GdSOyw|V%00d}iIVC~5oCq~i zgQ?5Y)_q^!~DEEvf>Qc$! zIrHXTaN#Co#{7}VrV}-_ufO`*p1pg5@faA#YwB_n<4yH-fCX{J1vUgtjE`q>dBj3> zOWT~`!9LMd?M3qo`N`JS_C$?dLxI$Kx_j1~wf1A5`1EK0=2N31qoIgyVFrwu7u7pfSA-FEq{;i>JFz5RTwt%|@!3co>CVhO^X$de8$&M^`wMpf8FV^fQHvuhdf% zF=+Y>HZ(OwqQT3~KkJ;;EAbPWugngGn4a*IV&P}?kAb8vf?&%9MlnCI+6V!>DB?7` z_6GqvizL|El5CNLPTqF9>X~O=*u8I`R_-h&l{>Kl(hd~pf{Fn#pKF!uJMuU*Be5F{ zU^c@6$lfq-RLDKfARNjgiQLjNQRnZQXXOedHXZlj;s~T8r{BlKI zjOlEF&sLRsbBTsvADa~)HI#U4^E-MVG~g#Zmn~Z-{=;^0S95?opp;bvXi&~F;pZ|b zd=RnT8LXg!L1~X-v86jBA~I3;=TnLr%*%;k{NU=T7dm>4I_|idV7gpY@J(0E?U?)C z_ub_<_y$g6sm+Z(Ki@B`wYiX(7qh{~@ z!FWYqxio+A%2S<3L04Xo=)Ag!E}>1MLw$i@7{-HkC=_OP_WFaf;Eg6Zm zmf4`DHh|RFJgnJ;kVk(7kfUnmA>G)3ko3I@0IIvDc{M|tpeOHYp(`*On_CG}2tnfH zO0{*^ra8ar@yUt)-qYEvUR@-C5hb|E7+5kN2^(E|tDgopiGd6TU4yo>+2LeeEXqUVwm_#@lrxRhLXqK7^LItMjBZKqD$WDSV1Z|K# zXv*Y>9U-W`8bw@`j)A9LIbxp>M?X5P`vE%IXP1kmfIo8L__6aYxbXZA*Q z92lgBxM#T1-abbv4FLu$H0j77%$ZP+UWu`?8O>y7FxbD>qt7&Wn0eF{kttQSrLKm? zrW{e2hhV4bU3c8`*0;R?8$sm0^Z4n$8?S%&owwh&chBDO@s!UO+Piz-wbxzy-uF_o zyGW2XjbkY1r}RA=W_Scz$Y)`mj17GQr5SBx2*)@l>0l@Vm$YZsHYt*u)`95+Id}&> z^o7)?b$fH5>Gbeh(ZWu}36j&vbRjPpmav?Zbgp z2mD&CL^J_EXfo4~wbmr+Y8qM^TH4~Zwb6LOMOc)Q%(&dt+>RilgpRdMb@eT=a7|rp zV;~qrcdCnJy)3Mt8H@QzawM{jguUTVRlrmBP8HRnNb-OuhdkyGpo-5WPrx6GM(V=h zx`01QE*y!}Fee6rB*+DyCm0GO{Jxkkknn}buk|ijua`e9uo8HZb^s3C;3ji`EzRSG z^bHk4pw{WYxHaj5ExOqZ|xZrhs>_%RpTjrbu^bH4@lG!hHFI8P%3BB>0B;L zU#3`igzGd*l0Tu6(fM!wgsmoHIG|PdvH~V*0Rk218~f@f4(WMLbdX-yfG9SiZMGJX z6djt~qNzr(yo$itm}+Uw90n@vxP9AdM}Ap;MQ3dg)!L2a1@TYkTpj-fogKEY#le9| z`kNU-gMop(J4YNEGIoU2p-YvPu2R@{y(CmCe*r}Mr~*B0%0=j!pW#b56aku})-~2J zhQk>MuAXB=COB4Hy=4}{ih|yw^uW@svgVX2Y9x^Qb+F`A9B0uap{l4eVz1P4XPpR5 z3|e)e-tP|~eon$&C=G{W^_aU&yf$gg>ZK&wNap=<$&w!xz1ok632fQ^J_Q zNxo0?sspY~kL)T4C?4LwyPA}_x@yaFkNo+O5`iKp(n=f0X~!|t8C-*NLz z$B!OAajf&3-}qW%OZ)Kn_>Na!d-UNaUU>fH2Y&aPGttU)zUZwEc&dVW`5=DKUMT{$ z4DJRMx3!g{10_AAtk-U#1Ts5guRZWy`G|<}3C;qTE!{*4HPRxE;aIgt4GDR$FODkA z$2;>!rASm}P&PfqZh0)y#9&I1d{Ok$l`rOtmf`YioB}((g!FMHrdrYK)I=!BtY;_`(;$yGlY+%)tfrxKfvSy5#ssIyDJ|)MOGY0O0_l z8H|9<0JgP#))jBLYTGMYjvhK#Dk!7@C9DYzkHl&xM<=R$m`J&*P+q-a`6vGNF_qD%)7QWFeM*abz>Sb1={A;!XYfB*>r^uqVj^whfZ*I#zw#m)82 z#DT|;9Q)(Lzr!e_vG~YPzjUTlO}cQ-hI8>Mc%BCze00aFFO#1TX?v6c6BwDnX{99~ zHd;=}JQR(_ArCJji!-e=4HQ18GaiS%TsDnvI8W!-qp>!rn~Q+Gz@a#c6HJ@fXux0r ztx8)ksLK`jTxe2wr1{%KNrgBpS=zj4w`PI~sR^cpooLn*DxCDyBoZK;sB4JD5^$bs zy-q%v%x5#+U@%rwH<=tC?C*hJoB|*i!VQLGP;dZqNN^b&Gm1si71u;PV*~=>SRziU zgL{sKf-6?7>K^F6WW%}*>(&ygqN@U_c|wj`M|Q}6{BXcN`XKVZV6QsVDvOhNA}seeUUm-!#+FC>+7sjSWXCY z=TgnR>S;U~u>7i|1Xi@q&evMe{%M;Scuq z4^F0Y@tQi!X>wwe99YZqK0h;9I+X;F>1A~^me8jaBN5&D8i|JS(D52_&v|?SDT2Aj1Kh<3}iBS ze<&7B#K*=)QlPd;5~bi=TV;iJ_q(6kIf0pv^C6z(%-gf|0%P13yfY zR5(O@Gh1U6E(vb?b>oCClyZjDn-GT3JQ%`V>7~lCICky}hL{mT3iExdR<612-FJtA z@j|h5;igU9Cr$*=D2z5=sH>^@-Vc9#$)%SqU%u-63pVZBw`**C48wr^N-YUG^`xVQ z1|LZU5n%QvBV+(>Fj?8+OteeArAEY_@(b7pSWA==EC5kmgEOPU=ptJ>P@K||&lCNC z1BnL;a?bj*&pG#8P{^b+tIs*NeRfB3Vlp)`e%9HmFTd)N)vH(f{ZmNyoO9NnbMCsc z&R)0Sy!B_Dwfg3p-?nhxypTUgp4-^iFgP@^cjrz`6*zsS1RJbSE`T;nBNktG)`nSg z=B1M9e6CQFsAKZ|@cr+-^~M`=`CKF%tVzV?FPL}M>a}w_X0KkgX7#Go8#iq{@BH&& z&dBi4MVl@d9vOT2rRR_f#7|92xQw7_+fq=NMuALe?{pROlD!a;dbb8BE~$&LK}++p zA;L7hdr+~SZn}_TVoPf=xnk@xVfLAufe&yRb4U@H=ALZiKifEhkk*-%5hR5p5oQRq zkzkx~G@sQ90G?NQhTo4ZfD~$g?J#gAqjwF11}u%$)(3pv1YX$dOQll4#>eAK7z~V#4bPw5F{fjeI?-9#Ga^!A zFPG&E12)>dTbzdw?-#%DB`PhFQx*Ff){6A1;`J&;4$qvTFjDrZsp;g&?*9G(KNFO> zV27xYfzk_qI>Jh)rcOuM7Zf|qz8MIo^$#E*D~x0!_8-KJ5p3zgmP#i@3Oiszy@8n# zFg9W%0L~8WePC)K%4bN_kAvgTP=}dwh=Wr$y8NB11S|d=p0p%Z0T;P-I|ojNwq|^T z2Jq^}`q2B{|Djo}tt;28TCs9j$K1AjDNFRWXaC;3y@ZgEP1#5|?3Y4C(E!E`hN8rz zmg2<7B~?dDB&=6d1n?kwuU;TjE@WcS=aK41RAXFvVomggoW zvL3&XWHil8TES4dM~uwAEiBq%qF;|lNwUg-8B3-P2_|tVmNeL{-k4rd%)N3(e;kU~ z%GDBeaH`_URJD=>#xEC&x88d5-+kt@bLP%|`z`ORZ*KU+CqI7K<(K#NoPKlH_RB82 z_=58;-23MK<42FxH#A&$;rZ?D%~Mm^=4Os!OBO9^ZfqPF7@kO`j-Na+G&s8Z_187? z!&OruIBA!uro6uCzyJK_KJbAL+<3!vy}bi4<@?|J?%-h0$|Z}(#s<5)Pmc`^daCkQ zT(N0(M~mNIJ$p`jdt39_XP+C7hK7feot>v*(Lh)C>DON0%8XQzixr5PVm8I@%2rq^{jg#+yG_k)>}Y9KZ`9N)x*3I-7oUiE%$hw9s4`W1=}*R<>jN}% zIFd!rLOyRK6h!`$skH8`HWfs#nBHxCS7g=TBQ=#WfVbQS-CJ53KK0>ym(K0j`R2h) zIz4aRY_gL?G_qvzf`-~U=VR#uP^pZ$RI9OtLKUMJ4R-I7m72lA%APtKPpHxGXDT)C zTO_Mu0-(BoaAHUAXLqGJtAreE%~*+cEbqQpE!XaIM+3mJ*na zrnA(XDb`AU-|7urQL5oMCr}2EHW;?6;S3e7zH&-bsIS{mrJXPs6_`}GLn`>=(1>#0 zS&0lg)h*0~pL^~pa&ycD#Fi{scEk18rE@6)K6*DbwU3VsHP+X4pXxbw`~-1v zAQ(MyqVvheAJ60o2kfC2GYRP8?~JAxGZc^T!?EKBTSqU&rXpvka-bJ(yeO4Uj*pGP z5;sEA$V^1E-p`{`$%c3FI+b%NrT2Tqteac;UxC_KAD$zNhopiSe<4jTWWKu?cBL&!2-QyCz&l| zb8Rh63+B%uWE&jpR~9loRa;jxtF0xQD`c|yy1JSZCr|F$^@iQ@EY*c-qf9BelNvZM zx;Tn5L$VPK58iqf4*WR%Tj*cU&|P6fdVKEY|MV=~3bfFpp= zh5ee^+Ib5XpE!D`P|)m4VZ>}MOPo>P&DCL4ku92_X*^NbD}wD9?Sg@Qi4P6W>MOncGq_2a(LaNKK&(Aev1 zXl!b1Y6_vf)!qxwKX3W+B}L88Bh)S|BP|;Q;fWI=X;OZC(BRxgF71U96_IwS87Y zLsQGF_IJGV_H??KOzLZZG$TTtHG2-p`|w~tHiNHVj*_M6PT^u86rfjKU1PqG%iAMQ zz(!9(;YfS?tSjGgWqW%^byZ;AyafvvEe!`q8xzrJoOIRe(}N6i=FGk1(u<#XT{+RE5f}o(j%KhDmyAW&6@Kl$%-&pUTwd}4fLG&7lI{y>A&kuX69rZ|XBsIoyQ@8A1oOIye9 zfA`CM`}Yx=9XWIaSAgcjpjaaQg@5?!+2@{h(IuCx-*A3!PggPtb(nUL8L6$M`SQ11 zz2>a5H(h+mk)wxGlPR!pQn=;TcPwAI>W(|_T6^|cot>Rz&ANbOa>S0LEPs)%f;?kE z^ch-cMsbI3hcVT%B4+Otey6JH&U@~C{k7M+x{f!uv{w5=7hQDWsue3<+4}N}Tb@6A z{n;(8t$qFd?QL!GaIn3-HJ?jOB**dJOrJHi&9D@UZ)t8G933FO-}>V7(^Ewpt7(PM#!pdFs(e)~!FgtE;=CqXQ421;eSTNG#aa)|N_5j*bo? zPB`4y&=Lv+FsWFqE)))Qo$lW8`fIonxN4N?G6s1C%x5UA8OSB*o>_8n=)!V9g0zE^ zy8A^Om1U7&0iWzE7Ox?L)}8Y*Uh#wiShX|nBCn^5TDp*6C!J#zanx{%8ukeiyH9oE z+>mL2#7>LOW%82Rnz}-vpw%-2#YtjSC#jl54cQ!;#y+NQ_jH#)Nxn4{f`o_#vpzl8 z7Mw^Xak3)V=12D*QSUTK#5=d4L)+5bovg4=f;UUF^IG{0 z+e;ikAr_6GE}3-pMCVC$UZ>o%%|x|J#CE%Kn-wwelM~mHn9t0V@z_uC(4UNqs=W1S6^}Iyg760n;PHqp1a?2 z)mzq`efGKy=U;TuCC@(dl%hbNZ`Q0i*IaY?#g|@s?RD4RaMSfSz4b=63m43N_`!!d zPxol;k}+&?0CFmNFGf0+Dw|dzDCR&@mr!DgCcr^7!rzK5$r;mN>C{wXV*}%C-m>}T zx8C%=_ub#$+kfcLL0>?ZM}XrbXmrDNiwC_^S6_SGs+B9RzV61wiOOkt5KN#A zqmT#Q{PwpcY7&3={U3&g2TqX=PUpCrMU}c&+2GfyKYrHR{!`T4+kT_)bNJ2u!0+yS)L=hd*@xyt#89_~mbIzx~cV`}fVBJ15}trc&wVrq=C(+`E7O{^8Myp^@?4 zp25+HWLI||iSnLZyW85^yL)=yd~=^kK(+uyC^NiZI21r}f}&LPO_3m+aH}qyW@|Mn z2)eGmiDso@F_WGoCSczQ)R~y@#`l?9q?lgOON(HflJZy-Oe?kkWJ@zGmj(P1Xe0)P zc)+MEVhYjI01m(kD(%9QUEmD_vl(VnQNe644Q93=c&~31%Ji z`GUiZvkb=;#IO#~P?%#3p%)A(y5|W!zIY^xm0{JjHSsm8SAd%sr?`r?0%lsE8;+=$ zvUlwIEjFisGr-xZzzUqK8=C^k_-Jv(us>4-(p=9>FA_khxOT7-pYBDc6&*P@K0a~a zz#;MrYJ`=!Fp3+6F8pWT9m-Ivl({Lws9>R@W-9VrSd%r7N4CleD28)8jKY>KcC7!- zHDm7DDlAi5*PznOG~>)6jbQzmeRq~$w|}OdBdbR{-Q>(JCugu?5DB5uhTaH%Y`DMc z#Ie`5ZF}*>mo{&C{+VZ=e&*rF9{$bm`}_Mt(Wo(Jn&h`mUs{cULV9vCmnk&0wgtof zU^wLUdzn$S#xy-eFiSE>S_Dqa&#?Q|7q|TEfB*Z*#~*v?`RAT_?zulb_{V3Ted++A z;NJZ`r%x+Ltg3EltiSZ~OP+c5@l)NWy1F{MPoF+;U|%E}-?#7Zk;8|Beu5w^Q^`Au z5;rqCE*c-ei9d^Qsey1Q0DrcOLmj)Yjvzwwn?25pf)+BV`j*BAe*N43{o(ifhx@v_ zyM~5`y}{r#AFu`L!mCXz&Uv}xG{~uj{0VmgS<$s_9&E3Nc8fnDLk}Vl!$;^;A zaTqqd!3}J{+08lU0kT&L>N z!9xe>J3Kyq|NZyx+;MQ**4^8;?LB_{%(4_>DK;91a8@edv$7c5OR+{LBk4 zyta4W;l9Dx3!9(cwr$5tuWdck)srjry#DHocinl%jvc$VZF|Fu=9o7T6QBmsYtL6V zb;+k|1})xtC9^V%mOj|lYCtb?EVbKC3M{vCdd3<<6Eg(Ol9*%N9lKx{oOCKfr74U! zPjaptP?c3xKCj=DP6mtUkRZ$aguaZY8%PADWRl?2wb!aw5x4dg!3zJ1Fgz^oaNp+U zg5j_p{0ano9uL89Jjp?q%Sd3Q5J7k%yKMoASiHa~Yc=*O^Hr;gX zWr< zVT(=_HYyc#7hY-qz!1}^WJ!_1G#NO5SA@a=_!6F2>xz}-cd7}=YNvuwhu(z@NfL8P zAV?~ucEY}gUd94SI;6-}g|@c{y#O{z{}ss8SjCJh|JzY6BucEeA~;TIW1#-ZCH2yT zCXN>yPqL&ejg3Wv5!VuSqy-96p@ zfR_JE%&ex@T)gII|M#OzwydXTAdxINdEzva?9lKS&KLx6PX#Ug^#m=7XH%E%LesA- zK@p>9)10OIqG*8StEKH*6$wX1WCX3;@6orfSFB$4_aFawurhS}ZFh~2jc?z%O}GBo zC0(_b;LOd@1qwaEJ-fGz#D^dF!*9=@@5g)UP8|#AP|}9RrhodEuibdl_0wlg|J*-* z@%XW0r_Y>b@#rb{jt&pNnAX;5Pd)xrBA)*9pC9h->y=|FE!Eq=qtTZ3)_uEocb)G( zc<|7P6GzMJ@dPP`-Sh1TL_G{2y&fO=N_c;x{4R6h^g=3@>lvhpty{J{_x!WTwC-qp z`Nii6+p+WXM83YZ_NH5IzLK=z%9fU<#~*uKJ2O5O#kk@S?&P2T^=s?buU))&NjjZ= z{E0{Vd-_tTltWC~1z)uyorRSehRWDCUWj=2K05%=*}5rlYv5H1+wN7iMMs@9ExuNk-MeQ z>|HauLrw`eROtvbYA69EP0Om#^#WZia-Ryo#VFoH4|MOX4Q)r`^pw*#s2YJpEk}nc z$<NT{~9W^`mM9vk;~gI-UdrM<;h=8ZIy$G@D#qK} zbq?M$e$j0?25}TV&Xn@@D!e6R-tTs1m0{PUmu+iqsPyhYB z?~X>}Wm9WL`okaNmGqG~xMVW-u6Muf?z`WP<}94Qcxa&at6%;S<)&u2)vMNg>$~6G zduZS4WA1-``#TRl_yF+@vlI?N(lU8Lt>SA*Q)P@OnHnL6p^`OI0)G+; zEL}C9Vl8!x6{J|ik9OHjQPwh-&4fdWs!&A$r!)GL16;(3)HO8s_nc#qY~IR~$)y|G zroqqQ!G5!R)BbEu-~WT-UT>~MHy8=d#3T_+K9}LNtz$-|Kjw&I za0utloM>onJ$vTxv>BWRGRgSZsJ`Kbd^Oc+f|M}fu6ap3hg_0y*KU}e=rb*l8Xz?& z(xj?u`eKr)ylK4toFm4=7N=XsmJ2-O7oZfvdGh#ZYMlqL-C-rp=>TT}K|MO;V@lB* zh~y%uO(YXAP}eGSQ+Y))m83n;fI#w^@2;$_X4cB2lK4Wsh0-6CtJOmzy62&*>s&NC zE-XvPlF4*}ARXUPTT@+KUE9#o+}Gdrp0~Z38F8q8ARLO6 zmY1})wbs=(ifnO0)S|~e+XjJP11~2ae=N?F>O+cD7+drsw{c$-SbJl-;vJ`;t>;lV+nVJ|KL)h#bS z_v90Q*|~kk=@Ta~vF>w(as54AeJJmt{fG6W$b^T;sB`A5i`K50H-B#Xw6-~OJEMvG zcr3Yp@6I_3=f3xSA7bs=F}?k^JKprnGf!r9ySt(@(P&#^5QB&qk#XTHL{dY%pazsq zNfVs3t)MWlw2&)lX=}dy_B*1n#JRKQe({U{izl)vyK-VCjZsOgB!E)}uP}#CeeyFy zBO^0A=MMGv{M*;Q#@aNS!X>frp9KF)F2AIwyNgxLQ%^rx$YHAvLfP~g(?9yL4<}Ob zrAwFm?0p}`Q_IFp#ba^%8o#20ffR0 zDWfY8E#h!7X$;*}stPN&Q7tBNT}T!iN~usvF~~(HrujG~rd4bttJiwydysf8yu3dU ztg5by#zys$h+GbLkWQ!Snp!X-j2uR(J5XS~&sXO2=JgzxUHu29n6G6mv0*S=arEH6 z{{Fs!fj(j*5UZ@JEB6M52YRQ?n2qPn<_n`^VJXlUk3>Y55vt3Woa@OFj6(4WH0tgGF+z-U7lakt(gT57$07qAi@*~&;bia!|EEF{jC z6Z5h@fFSK1XYAes;ji1y9B$?crOAwoK{2MjLLhr2={{>;FgRIKHZVA_^|dXpZ`t<7 zmL2;K96odG*vwfo8=IS*R*<9?P{@Cws8ohEC;}rZpIh9MReOjxHaJ;2Mp>qqtdXKN z`qK7RDb>#x3Q>umJKpGxNU?0jLy^w#m{;NU=S ze}B)h6Q}=p-|vP71~*=P-NF6)zxl8Kv~T~eH^1ecZQHi>4-8^sHn&+^V{ZZz7m6Iy zMOiW~Y;laDSSVp%#&V`}f={1s^71RM#Bzecz+HE}Wq4#{+xG3DPy`74iJ@XCqR{>1 z^zwSj@4ox3JNLdZYu3zP{_^LEcxrfH5Izh_$~M%JY7vqgWbuNuB&g-m#@+(qJX8#R}Bvj!4x=V;YQ<8y*qevk~Lo{5oZLVVD|w> z_W~=L0o-L66kw=#d70jFi)W*wsvz9%R3kdZ`)4L5n4Afg>+0*KcXZC0IitRzo~E<} zkYTE)mFeqQ{t8#?~@c%oxHm;dduX0WdxW-v0! z5s6e>zUlJMfAJr$xN=i0mAm@78*jMz)@jqHH@8o_c>NXK=g#4snYj^jDCA$a?jrYw z=0G6y`s=TsJaz&S8XB9fzxmef+qSH^_|l8kUGn?i{5p|H;xD0AM2c&s2}ZHVM^3h~ zW^|QKF|Z6D1y-spU@eQ5Eu1@V?y(cc`}ziU?A)E~}}oxao!)FS+!x?w*0c{z25Nwx(*us%2g0PaZh1mx=1o!2`a4 zzq+Pspnn)HU9^7f#;dN3goBYt4MT*}Ij80hN{*CK;>c%$KCb-4?^;KN50^=upP+oN|)}n0+U(c!d1vJ+^gjR18Lp}vO21&uB~rwX}fCU zWeeub@%cP8wKdFyG?r+M9u8A3T2#x=Dl68N-|L)gu~H+u?1f|y;626Ki-kaYovc!t z|M|knQ)dSHMxoZ@)3=M%S{yKE>c*A?i(bs-9ZV7#w*zZokOC&Fa=rDg)hQd-Z0OoM zI@I4XP6@0?69|8*h?kW^=}$T&n~|oP1W1#Z@Kl_P#`?5qqDWGIT8t_Qt?zg zxo6Mrk&zLP*VooQy?t6|AQ&VR)>}=|X;h@5stQC#MurGl?L7biZGWRa$s~&)c;S=Q z`9=l@3WZEEp6nkOUbcMc?9PtrnhJFAvP&=BwQKwM*hmT7oh;CJ{UsL%g1T)MzZOm8 z4(>Y~2tKpF7^DY9WmtT2}6`7#gS`~v+Y?9Ac zR|UWEAKywQ&U_s-pWcJF%YJ#YH(M?Q#SZ>(>f*4okD(Q(tw zx7>2mt-t^MpB5~f^__2hd;7MX$Bv%r=^fm?cTX~v{=naTVAqZvp0bJWe(!&Y87K3T zet(En*Yue)-gMWSx4iKN4qub6W^VmifMG~kGBTB%mg0rs2H4WTsFtU&#>MvPVM;2c zu}cCZva}&XN4ikJd`}Rn=JcJ=ZBoH-WNc&zR*H9eZD6jcxhp(hEw5{69vjjP_vRD0ReIHNthhM6MOf zawT-H>TnV!L+C78p1dkoBgFc2{i#zir4oZf(* zc>5)JywR3cd4$xKm=KIOq@R0RMGI!LKA@zordE|GKP}WxR0EMhhT{k{64VHxFW>tWX$PfRB8UtBZ=!>k z$Ss2&i;^NCZZ&vtcp!#g4Z@lpeTo&p;Nw9}#(l#0e#R6*d-0GXJ7b78Eo zB+m%Np)LItaVea@qYDt>MpTk+FuS5N!VQCvW`nkQTdVpjCS=^uE;FSE#o;Kij2l|; z9TtGmPq9M2rfvGPO`A5n`s@qKmMxt#Z`RIT+ZlV#+*waN_NdnroXDpV6<*Kl1!D&z?B4Yx7f2J^bfCKmEiLd$w=k z7>mXcFH5CdJ{1i5)~;RcDc9@$^M%}wt=rF@>G%61fnepF`E%a;ckhf;RlNMtb1cS# zp)f80MrLyvDAewl?F_&@7OgM{>QDs`a7-2}kpi9^zlpOb*A?MS8?X7rPk&C}d9JJX z^x5;9+|K5X7J^k`C&py9= z`NBQBb{#!(^7)1uwwiR z?P2EhX)`_LzM+9W4PB;}@X{H2K>=&kV2a=sP0K(HE7`W(h48?&KoS!(I6H2*a#}!g zK9|QkL$qNn4`P_&F~uUB0fT~@hBj{TUtuD{D`3~fXAj`;h(N=wNB6q~IX9H9!tB`!fSWZXX$y2~k=jkP)}V&tSN{GHTA zjjQ;ZQ4C%YVOMKqBwEV|T{#*`M&ilp)o1=d5Dg{_z3;wXjE)RV>*%Pft4r%aL(JGe zYwnyi>sGE>w{pXEo37Y&C2RbD|K@+Jy7*$Wgop+Yn~29kkqStQMWbL*R#JverBf*Y zGHK&g$>0;+))KgbDC`2GWowpy=Lg^W(%0^tw`lq08?V3S`de3Bw0_>gWeb5y z@m(qwbSQL@M2r_E8tw2HSKy-F>=mx4lqAqmy*eZ{IyTzZ*IQTL1j}%)m6duLQmHUpzTSZ-xL@Ye<^z?O)4tLL6IQ!yDS6_4ERgKM+@dQz+KK2!hCsOIe;-zyoUVX*g zZ+qLyHOmWxIN6L|JeHq~#$qf|FTd*YWh)k5cf-|IJnXCW)pnkx0a$4(=!hLQ-XVHJ$oecupC^0bh!4YOLY(BkRENiZlhP5|I^Ci#3(7 z%7H2*V)3AAEZmY~Whek!p_pS>Y1t>&R+zv#f}se0lO+-10d2&y$wDd_*NoyAXS>ki zj4jydu4fbMxg;U1A+&TR%umFkK&IU6xlErU0vpia;pn)6@4ftLU7-LGe$pecBnR6Lz!JymMgMp3S^l29br*i?1HHP_GV zoHOC`-gf(~H{W#QrmL^%oV)C%n{VB|Yx~&Pn5PVN@wH5AUATA!*y=)Usb^q#q}=Bp z80_uq?P2=gwPW}9zVoeDUwotcd>34SumbEcg5imA&L)_tWLhU>bw>)qRn>UCNt^r& z+3dXeOZxh{-~85l=FFMd(J{>*2*s1xQzuXC+O@;y2`KnM%VmacosF2v>T8>uni_7n z>6+@QifnGOxuv7BvUbaBub(+{wyvQuor+z0*@nf7=eD-ib}~1tm3Y;wuerLuwqp6x#Vo{Io7-M`@%g@i zLGh4;D&}=tyAv~b899=xrT{X~W~WkAQ)%&sX5^-ng91gYrWfjB&Voc<6S?4(miv4P zkOfS9r3+rCs-`{`9krQBYJ#H9nms=r8&9QmixSG|Ad)Tj>E2$<2F_!jUY0TTL~p?7 zpFMBknKQ>(f==f2hHsR+uCXPZ%O%nYf~JYQy&~4g)Qx4r++=EzqoWPaBOF!C3K=(n zk7HncGLBe9mSj!?5;YNcnX3r;G&A8nw3lHU8S;!MmMway5#|(|J98y2*5MCmZZHfE zs(siG1~c_=6nW?IK{%aGX-|W(jpt5e(mjnb#eWWpH07QJR_<%kqt6#A{^jWR6U>$Y zie9!Eq7WD}^Ln+Dpp~vRB!R(VS2rp!IPtLtlC<0aWlR#fE{AvUh8h}b3KQA7n(C&; zdgm}1g`?;#&U)f2daZJysg0P@obKS$g3sikr>|fHf35{ZFh{0fw?`qYoITm*QbI4I zExh{bj+bA4)gSabkuW4or+ZN&4akKf$y7)K7TqL+>W*k3U~(5*RjNE7_?Tt)=Ae9!!ig!$yf@G7VQK38U00V|Lia=b*zE0fO7oE`E^(0l~-RocflMK?ZnA5LxUr`w!ZB32ff}P$fL&y1R+e?dtEcB zOwb#ws`TG>=k1Jm;LxeMhL%J7ww^!RRqhQD%GK7^&YL%{wXMF8i>0$AyLTM!I(IA* zsgy_0rl!r9**SY2n57eA3zn`ubZGy!H(so+u5M~>#Va&6)Q=7h1VWMK*3SO^o*g^3 zWcBtek%rcxt59JabuyJFmAI{hHqcInBXKxw3psfWv4{4|N45~uO~X?$7pHWG4Me8+ z1+j}dYIVU!SLYdzmc;(hc<%IxGJK{!ss`ZHytzyI2L@Qyz{{+Cjmlv~e}3hYaJZAD z71edAL<}AVgW;uXFM0jtXSLwBH%jIv3v(ANPo=YcJ?GF&_Z1-^Frq&gD&(^A30hw( zNVX-DW(O4_4*5PpJG_-9OH+Fg&;xst!!L4e?}@fzIegx`SWHoIPg7KfT;^Z7D}|`D$2F>T+T4+2XpWJ zs_v83o&#+yl%#_=Z){SMpzYU@&CxD^k@C3X$;q?ldd{9Xi@AzxHj~rFb+e3;gXT`5 zR^U}?>TaR6bckv-pr+_#i^-}OPK5?s&EUA??`C@mPeyL{5=jiutb+lup-j?>EQ)ZZ zka5Z71=j{DB4^Ev9JL_>5Z8vJ)-)}YojG;(*{7a({k7Lv!k#~O{)OkBJA3-9?uBOd zM5W71e4%hUon%eJypO6@R#&fGcQMffy@^tNelPwaIzCF=IylhFg2+?q0edNd#}f)g z2tOGO1<`E=2-Ut%rxzUt{I!*pYcF0~Q5hT?8w`c@(93vqJeMntCsPwSePt`3&&-%L ziFp~jl}y85bICinVlZ&cUTqgy_I*i%NR#lpV|wu+4`>ukA- zWEc)sK)yJlxkpz>$Vq%Mev2f^q+u#6FOQ9nR#eus&z!Sl)$01jwv#8$oe>6C8cskE9Eh|q1hr4@c{5_N8dnd00YG9Yigf<_QX*zriCXEU`ah~#w?hoCmQ7ch>Wz9tEs7*J$E5<48YAu z4HJ1`M6J+yc8rs}< zquA7->%&Hq9JIDzi>AsnKwhV?jJ8Cwct7hZO*Vn>s~*sj%jyd+YNCw`c&vqv%hS&9 z^|v-L8I;u5RoB(kq7D?=H)@N?EJgZ5()z~K05*sisflsGU3j8}S~^4=V_dQuAzaxt*zT zp>$F&bSo{%m%>Ysr%YCXl6V6Pb$20DdzZ4kM&sC|pxpON@zf07QMuN^iaGmM`D?wQqdm8$bTR z55M*8?|$s#AODYk`PXZ%y)G6T2WmK6QCn3R3HoPrOmA&zsjjUl=zgt&r#uhRZ>}1yJ6F&uipE`Z-49C@BhfBfAD|5_|5PC@bzzg z=M$g*!neNvKULK=r6okCVVI1{Wb^swpMLz%-hHn;xB2nM9t(#f6iY}FgE-6&$Y!u1 zTdqpM3VMK2)y4`Ewm6x|5}5l5^A)d57P6T{Hk)j1YhAQ_Sygo%UIq~f ziiG8zEXnux_eLrzPM^d#N%JsNsK#y)_sCH1jLw;(&gMp?nDe4}HQ)C1aX@jAvBM?n$4A1hPj#P9^uY3Oo z-pR;I7A*eo2R?GgEw?2TL;v`>f2gaj&1baIce)Q`ekKa}NsneSmXboUq=dDw;y101 z%Mo-qQepJylj)L>)^K`Im?$unP8~Y1%UO_c$L-%D{qy4OgP8u@jTyqa#NS9oV~L+o64X zx4rtxUmkgE=ZGL?vqjAYZ)>&C`(D&ZK) z31CCPus-NiTC(Mpmmd1#@3+48`qo!oJAP#UzTI2*Zr^j@z~S+cp;O0CvJ65SYwBum zy7lIb8?UHSxn4zcWn4<$Cra3#$=W!dMU?dXq z+;Z#fzxe4dI%iIAY_0z9AAEn+$~Doku?K$tJK7dZ^GOaunO7e)l;&xk5az5@8d}@C zyU*$jdb62aI@Q$Lkxpl{#U$5^G?Z|-?s^(S<1=9U6qQP5OKyu#VXTy0%UZ%%2-o1{ zr3(GK%bSHkQM%BXMTrOQ%5o&BGzU~VoWf+>a#8uI6(y8s1R_cMd!WY<@`6MuUFfKg=%OD5=gTv_L zU8&)wmVZOHCEic^?K zrw<-G)ZN$p;)}2S`JpGCd;W#}I}iN+m%mNK#|TV`-E+CgY%U$}`@_LdAfT;%zfbeC zMh9kbW_6@!x*$oRr+kWS4dDZ&NSx9|7c0uWP%TMWv@$v}1Pk+deJ=}yQQzqJ2yqJD z@Z^aj_4SQRB&_DBp}UmZXkk!#38oa3n8I6IQ-{MF>+hf5+7Sqai|9>Eg8QREb0y1_yeE2799M5r3$BOi%vkHFtE6jgOx?d-|y-A3A;Z zMTLJ0j{Ss{G=Bk z{ed7c7CEG0B{D`VM7qtO2x;mj(_A)1U}tW@B5M;U&B>UeYF#71DwN3qN~Gz7o?xh% z2?+F4Oefn>!pvz!2J_J=hA9q;d8QlU5^5=|$S8ExRu~z&i5Hf#?mew2jd^9_$6|$+ z)$q(lB4fL*MCG-04OLY&!C;6kGF#`xj3l-|E>J)T4 zl~8wvbZ%=(^GG_K8s23bWb#sb;Vn&-=~8PI^b|B5i|skWK}na;z^2mzs~Z&qLOMj= z1TS&wGQ8kGJ75IIjr;$5{M(G6ku|&11Z6;7rFd36Ew*-fxggS%zjn0C$?Ku)iJR}Z zbJMlguf6QD>uL{r>`Ir>D67CGfr)isx1arwXg>(_3&>9%}X`SrJ4f92IzFI~B8;qs*yty@pv z3?JZDLu13GSFGRs%;r~KdE?-LBZm(j-M(#Welj~Y65I0H>&(xnf@skuk7jM{vl~5} zGMppGsNGX-COI9zx?XEYswzU4~!9Ts{ z-S5HORaP~>_R1?n502NAL@F!mo7+4-zvck#glJsIKz41@J5QfFCWINRv@DZKEnl{Z z`u>4I`XW;u`LFvK!sOIa=BZLVolz=L+I1~izD;<#^~z|Fqf|_%Tly5_8vQgwh|+R% z<=slm~F^5-)&k+fcTjTbj3b(FuK9Hvk9NxokFOue5J%?}){s zbkX%eGbC}O!z#$1@mSTJp_Zk#)dkJF*F+R;RGkL+~TaE1O$0l z{_g$iy`T#!rX#{zzm{N&)qtXsNSahsg_D&8_+OYnyxo0$XU?1{EB6V8oSS-R5Tlk8 z{yURa?Cpn3YITKn3l98&rTAP1V7sZe@y{qyh9G zuYOjl5sSv40{E-#RBh)mEVDN(vX;>0F4w53nBqE;Sd+=!8!5$c&HIy>Zu8kpXUDWz zowG|lC3V%+g#2CSyZd^(4jtY*GCW>Z=F1Y1Mq}mPU|oGnS-Jnz$)l_;BqjM=Nps|jD4Z6fUk;{MhLw}!$k7F$59$!2jJ$drzWJzxE;$?ew9`yR?rNQWK zyeswi0`(15Z@uR&2lwr%si_zp8adb1z5l@8OE1477LA=hckb5P@0{J)(bsc6o6Yw2 z_MSL?JRTdr?asSjdFjPD^JjkQv!8qYmFLf%I&<>GsT0SJjtq_5b?03JeLb;6f~9vT z?3*)p9*fh#;h|_E!3wyyr#F*Md3<(3-25q|nxLgcI!c1jXexn}X;3n$1tf-qWvIrg z5Q_y+Qa4VW|FUFGwiw@$sHH6|A|A7at>_O$Dg%MQK=1jdpM3oJXE*=mmp|Y7+RNR2 zqrd+7FP?q!@mMl00XSV!V3omp5?e_MK&PC**&a)+YiK@q`narFdzZd+BHlTBZf+vo z-_tL7X;Nh934F%9#Vc7}Xd={Zm_+8_gEmq#f((C6A&|xFE}}q{K_LQa$WX$%g4Gv` zMe#u@;TjjQ<>+=WDTQaEU2%y(QE5k&P^DqL9$oLZO<|drGiTuFAHvWfQ+!&XC>RYY z76=oE8w2^gUfdfq817jc@l%-dD-}ivSpI--*7RvO*>Et>&`^i&%SHz0hU6eqMV&^PYC|i>I4hQQ zQ>W4*1oLi|1%iWy>06b6Vc@isGf<%cq>EL6vXQQqYHm;@Gb7#|)zGFysDZyUkV%Mn zY7Uw7WgLe9%><3Cf%~ftS)DS*W%J1l#KOGf__0$jzx3jBn{~zMiN8F){f#$Xdg+yD zG+td>kHQn3jE#=;_xIsJ@`Z_LbR2uZpQ2?K>WQzX z9((NN7vDI2$sK=X2k1t=oqPDiCzM-bMrFr^{ zjstu5wzYTm_xA7FxzpoiN{8RJ70zlgn19x=2n# z8BP)?|L})Cm`tV5p6%)H8;n%e&Ym$d81%L_Pk;8Q&HjLpH}7VPR^w|^W8M4T`~IUx zkJmM{OiX&}8=IQyYG==ye)8n0lgCeAd(Aa-=gdrJ3e#rH_4tB~jji$Vk@Xi}^!S61 zELt-EZEt(q(Idwu`a{tAaQ1qxQkFOX?E;t?1G4MIyjhOOHTc{_+KvUVG)Ho36R;)|+m){l+V(upJnlS;%#hX)dg@mw~|Upf^}>J3BV ziFh;}kLS~=jW3F5onm%}h+@hll!(9Ncwa@3!Zke&k0#`tR}aaadiL(5FgF zZVCXc{iK{u>$*7Z2^^3Y(vN^k2UG*=?`BviZq}e))gj#&D3Tr#wLP(R;pssDET+ zB%T;g?b)$&U|;}Og(=E+6oqSoGkv&_IF1ZQT zLU*}x1mMwrD?u3x8%f2!!Ie#?K*#S7oIQ0M+#t++w_<8cf|7kX1dN4h#_LUamMS7O95VF;Wlhbf$6Vv!2{7ONz9!K6@xIHIftK&*!{ zRACg?T(jxMn{M5>VdLeOU$J!gs>+($Ws8=kGMUX!Jsyw6vY8a?-}v}wDix2%qVlTo zu~b6kKA(4ZppVtAYGR|K!~J8U!!(IU$Hzzd)9K`rmCG-`;)=GG)}hg{TW`DR`s=S= zxM*S1wCUI1aO0kxyM~9y(H=}Q8XsT2V9rD#n~2Af(ddDF2VUO%tTz~5d+DX0`@-jM zxIypj-nVz>*hmzvfpy+4p}=0$OA2S?7=gxzVirY(Sqf{DF*<622_ISM+;;2Dmt4Aj z-s1V!UVnXO=k%2;S6{Q~`XdMTzx>JzOvXS$(eYR?kpr$H6bZfOz3-a0aKW03)-7MQ zeC5hjYcIZ-sPoakJaXpDxl7iszwP#0=PzEo{?f}=u3CM?hE3O9e>2+uzyp75Y-xPU zJ#U>cYu36;E?c$cqUEbrZo2yVHEY&A^x%U`M|a+N$0LvYskcXOp-rZeqhtMdz42f8`#d2i5h8Yk_n$FqZaf~1rxUPUz%2o!uBN`awl0xM0vcz^ zFmgZ>h04mR_V($=jvPei0f0+jhHIZTJr<9S43E+m6l7S&Y1xD@A%2wWq>u)#N@`5G zztT>fhZ zLJuan`ySL(<%W=r$C5#@S4N&apUHq;2CBAf-}BgGk4GX^XbR0-V+}Z!=;-DgMiu$4 zjSNygnmK|JHyoTSnN&nTGXtZRRN1NExKqkOfChA@iHu*o)BcOiR1!SwOU0tPMOi=` zK6KTkLvla>8s`og$G-&*Sh65P^d%<216A>-?Ib#jEk*Y&DmYR{sTz~Da+su($$Z%F z(OtCRFx|(-qse%JhC~53-ge8O1Bc)le2Y|6!iS63UHaz-etqWTi9j&K9NRHtc3)q& z?8*>cv1)BP6CWHL&{b8va5les?Yh-#*MIf%pG(D42)UxFlIfP1x1zEplS@pLdP^qs z>SBM`|M`#qU2QG3lPrYZ*t+k*`|fXSY5V7I{^uhP-1qVe&wb>xp9}aypZ@z#w6@Pk z#Kv<_Qs#DAbzhDsg0QI>k=3HOB+U|I&@*3&GrVkx$3v`r!;ROkTem(K^p*Q`Z(}B& zW@7&HgMZw$YkR;~L0H3jE)Ta#C(8Mj zXHM_D{Y|%3R#t{|_e>$Hr;Br2-q`x$^P8Dg@4Wl2*>h$g?rbhgo6(Wc{=VVg{rYDW zRaHOx^{;VZp7OGceXs{BIDh`!hu-tvWIR5BL7@KLqO zXU?4LAMRD8F{PiVU_(O_aK@u!vLaI|8>FY$TfNuz&hIHYiMBVq%afWY*?)>A&I=77~c}LBu_!GZ~h+dZZDQvJ)kRy$6mx`p94WK7GBe*mSBpU0jBwyu6iY zBY&aFwTE~UIWTfg`=!bTM|o2?@{X-8Lphvva0Eg#i-L2@Pk5L-^|=PZ1lxHK@idm> zP`0$xye;sHl@1O}x4iDNA-E{0vFbsAAJoD!wi49Z#O-QH!%$&iN#3n89L@mO_XV`; zi7c4~5H<<~p4h;<-~ax(^X9PFVbDMz7>ns4+JFAiKPD3yM9%0?I0Hr$772qeu7M|J(bjYHRVTuqzWEV-kwSqSxJY`*qjf`q2-) zml-P%2-P+<;Z0)WQC5So@lk&;Tv=H?HZrI;^m@ISRIH}1p}w(sc(9*YxT3mdY-li* zPQq<%py_J5^iY~ImB>RcM@JkPLsjBeEiO`T=GLihUA8J(!T?0;49YCg%z8a2HFc$dJ;JTadI(+0nPhS_xA|O)<^8LXOPE;y1rM(Q= z($ap}mDl|KH$TRkn5;`PvBak9Z|xrFK62=wr`(67(uHzrL60tyqrpU|mmGx>9mzP;142t{JDmpm`$QMEquV;|i6nG(%CTZf3ixk6-OvbrL4?S{(>`3xRn;ez=f0yAh2g)))J zN%wePqaBwURwU;ujmCaTKyUuq#%FgrugC#B@p9gGDOW$BA3T0JKxoP{P;1C z&#!9wSr-~uKZ9$~Xo}a7X#onn)j-fd37yoRN*Kkg&!!32krPmLjom3ni9{ZaQ>mjB zf>_>mnMH(d#=uviA~*wiLp7kKYmDSLq8yxF7{!i6>%|>jTBw&S?t%_sflNl$j;R%} zVv9DnXduB$jpT5xiL{3*(+Tsg{(zKSw}VK=Z@l{AbDN)fe)ChCpMK(*ryqapk%yjr z;t6}|UEeQq?pRDfS|+fa+g^M6@kd|W{On85zp(kKr(Syg`KOvNyr>98E?vL2A`#uDw)y$OOu2}M&Q#^#u&3tt?e5yk*B5~)lkVlJM7T3@-hsipPn-};X` z-*o%h)vJ~)UA1-VYfMQXB(~cfm+%p2y7fh@(be1P>Z*@_@*_9ieDy`^*0#1!KYZ}8 zalgc`dxguczv<5Redq&g)-1LMsQXP|#H1K^p{BRWeG|ai&VQ%UMkH z(h$Zj2bL4o7L6^f;fktYD3VSl;VLYo!SFyYu8r;}L&jcpI5gBBPsT2Q1cKCzACm|g zEtFh@F;S?fsESlpojP#@O`!p(6mq$la~6z@4h;_umEphaR{SCyi%vLk5_C*JiB)Sb z(Kn82I>i;yK6T=bjE?$}k?gdNly2BuOJT8@gHHlUS73cr?)FKkGDUKQ(kOr$nEZ9X%HPDcfNdU1hAYhk^jQyv41og;R*+Z3Xn*ti=| zGSt}8N&JbBDJ{dX>a?J*miU?9^p!ThwnGc~jlEpe=GN!7gO)Wa-XP z85xTk(<&|;NepJmohkjbK~V{*btYG4n+UARHGn*mb)%*0LUJY0O6cz#vw2&)Hf182 zYA%9BvIOIXD_IB7e~|7=y;S6%ch&7jtXom~yZ zQ1HB=iCnq2JcOSN1pS7)oR4~GD0QbS6s|7w1|~{9L{yVy9+qll9#2ra5F!D9vDk14 zsxpyh{x+f{jcmyTF;qv#jCu1H&zZMiJG7KYrknx{7lBT`8e5AS zv4a2EoD>d~BNVdBEW|AMBt`KiV!^}<%h~|v04Px+%PZGz#^69-TrZGj9pfdKYG`c2 z>8En3crpqUg3NGb1tu%@3!L$arH6e+fvLqftOuxYwIWb1NihT(<*LLj^Ely1rK3+8 zXbCtJ>WK!QUb9Uz3hii0Yi(p_f};XD6AS`4pjU9{)HR_?5whBlD_T1lt5O@_bEKG# zaNQiM5~mhV7uoCj`U5OiDmcXz;zi)FJMxS4)J!_2yAg;X?4EAP0U&~C!_kJ87OiTN zMMvTk-L@>$Bx7SBgTpSGfuxX77{VVx3`ntf^|D6KrdUI3Ecapr+5sS!(^Kr}v~KO9 zrQIYO^6FLJvJr@fR+mHWx&;B$9CnsOH!QjL-mf~H6Vt34=uNdKHl0dE%r%V`#135v zC@mWt8ajEZi(s2#t5<>!j(;;)sjia&KqF8iXq=%M4kqjbsKCjfi@gA%K~1FuioYq` zNHi+OLbk0=bSU}^t|LKkWhS)5*}BajLE{%LlY;}QHF3Jc2voT|jZK;=;fJoYL;%7E zur4|<(wt(sPQp^=Eg)dw8n_~4Z-ts#EF(@B&dlBfYy!f7^gvNGx^|IBMa?icv`~_t zR*8VnkrQf?i7|$^haiQ7jesjI-LT=BGiOg6Jbd)niPMLU9Z%&;*I&MI)|}Z_Uvu5F z&pftd>C$=g7tEP6_b-n=qVH7GMFv~syyg!D?+Qc#t4VE2YbgN%m=8ZPnJnVU=8}b6 zvaH-2jmBSp?e$n}Y+!KczrXk2<>f)W(%vF#AWYG~shGx0Hkr-l)43=A@+iya?c26} z@7w>ud_xuP!wl2AZOe``XU+zL6`%gtM_?eV)RimS2=@B?xl9ICZ>n#Jjt+Y%N3YP# z$;sNfhOzNc*O*8LZlJY*b&P{!+iAesydyKDq-6* zXU%J9ZqI3RE^X2g765N-YMncG!NG%j2=JuLm{>NuV%0^_Sae`u02-hcbP!@~ZM}1W0%V)D)$5e+7JVp&UA0A-D;^zVR~5%sA_ga zcIa7oc|MmX{={%mE%Wl~0#_NF^_Ir62ua#y+YTfkS5($Wj!4tvrK-p%d&Ci6XF@Mq zyJ|5MVv;r0RlpZ@7F&|g0Psdh;11;^Q1u!g^dUv~NJBBB#4gyI&Z)np3mJ;FLt?Zk zUeXQ`;K~LD1`i)TVR$R5m+NuN6#`Rzu4`*)}xPd zZRvEvkb&juZW1y?4T%2Ps*@VHKuCwrF#56qG;_#Mz|FA*p3#7z zU_yO;{gs>6FJHN0<(f4(>ygnxjvKGOYVEq^l{FPu)4EI6E?%bV=EK87r5kH4GKfj~1H4%@cQn~tu>ZQw;FIm169L}EUnmcdK zv}vu-8jr=qQlk|2gXq1bSQp`j?kdr(>7+7mGM8dKLU}fumX_dTjfEl#94tw078W?} zIQT@^SR23s*1|$lP8V>8Qr5W zlS3Bj#Wb^j;f=;K&IT+F!Ddgp&sjOL7d%f(NLV6J%rnn12)w zQiZZr>o5Te{Fu0rum7ND}48UzIehjD-| zWcA@mSfkd~+>)+58x$q5C2tM1U*kASa>S5vM^0&B?R9O+m1zHaLLW3H-k@YcU)L>6 zXp_gf5I4&|awhImCJ5qzsD?orUK-d`fD2N8(7=K;&Ezxe(&j1Cx7~bA9%eH zATalMz2&p#&t0;7Wd>t5-IPL?Oky_E+op#C0jxY2j$j)NjSa)YW3RmW;-V!>rqAqv z4pu144|@Dujf5?_3YZhq;!?VN`YAy z9fJ@Vv}|uO9QJ?h-~Ro-zWsH7AUrxcOuL5qhIha310zEt-}sMzzx1*zySjUi963}` zRTYcJTtE%gl9Tvh&fU0bWJC@`MNuF}1zoz=S-~Z+}`N{0a=qPKk ziEM_^+NRI^*-wA|uV4F*fBlz#e$$+H%RALUGu$Q#unT(zc-9?TBt z(hAMelt~+9gwk3nRH;d=sEQYK#z7+$T|hn`2!;IKK*2t8fy~<5JKJZ>+OhQ&Y!^Ng zyd`4e*Ijq}u@grI26}1lRMffyO0gpN;<^}{av;WzIxqX9(h0>ZE}M7IT|0o z;nuhI^zrKXVPtgK6A}@BO2IxQS%oFxv<_2>gj-x z98AC8Z?YmuAr%HOsiYF9fiDoW;Y2=TIdQx0R;XJY9P(JDG+$8V-1!k(EQX*>I9!#^ zqyhnNLrv{v7p*|mVZpq4v(Xfz(alM)NLRl!gq9}!is3RF{&e9>l*rAHiU=D+i#bc2 zGQ3%yUIk2^Lh`8PxpU_a9yrWAB!#iYh`_W^WV^l;v9zYKgan;nfg-vF0tN4APR2CW z;)W>%@Pr!HjYzt{ED{;VcdO-$a}grj1<<4(Ro0@EWF2#5;vkL1XpSlto=y*J2KGWI zg$_P&%e}tUYu4O$>&-oVUDeg$#>R%ezTSMcaKrUCz4XG%u6QQfuCr&( zoIl;yKm5;M`Qk5s_OtQPu{Xcvt$%vxVP^2s$+FRrXn%M2%g;a4*fRaGM;_G%oLKEd zRcaI7WNmfmO?TY+n?L-5*)SGQojY^p_{n1e#BRY`lLSCl)gvs(U(4V0L9b1tRP5i6D#lWt3+s4u!0PStFp(Ad<* z{AV}#>jFkyLqkJj^Vu^eVYqo@P05QFFCQ8nj7CR+aI)5b z#{7zQe2-hgmz6RgK1QD^p}n9@Xo)}xhG)1~R{<9->VoIh#up)l+ZikJ3PPwwktk#$ z0hoNB5$NC;cXQN|z`-ShE>TugRL}?rw8cR1l@{pfb29dF8Mv#V>0-zzti}=J8=%yq z4?%iteV~Vu{ecj?ViesdhKP%IvX%uy6}WPAr!pK~xnvQ`CdAm#Q0J%wl!8^u(Ard6 zPS$Kj3ZW`B6uZH}xL(W^lX^@Qax9*>#EGt7O|SxjM*uhN)B~CAtP%E!WQjvUUP~Q#+H8eKDO_i0F z!QTt@nEdf?<@AKo8VVR)bxf=V^BI=+XUq_j`T8;eny!M@}9+ zae}Z5ak!zyR=pTO(+qV7w55Irr znWy*c-Bnjphp|2Szyk+%AAbDNXa4Y;2mbWH!@G9vId|L}+Ve*Vj!-FM#u zk390kiIbgic7A$_KJ-gF5YnY z+KW~#pVKid;46RWm6vADne(Q*-#LB8oR-$RizF{TSY}Ml}c!zRhR$VUnzg%v9Vkst7jQ{ahwlJy22CatPEMwE z(rSl;(gh_qBf(Bl2Dv2NCgBN%D|Gu5t4sW<3|0u!j%EU9TBidhXbNMMGBB67GF>(p z>^eU>(3?ue7=`RCfq&UjILOo-W;a}!kTb`K2XO4LN-;1CTAaK%(6Dt z%g7O(2Bu^}Z^&Ut^@VBpT&N~lUek}mJsyj>Ui`zrGntg`*VYZTSaF7y;+5%urZ+p{ zRVk-~v0C~d*)x{SYCxlz(36zqdI?=weudW{j-eR&(aAmx_tc=>mCn zm!ZNjRmh~1$#^_A4)v7VZoM#am@~fPl(khNKZU;%8TGOwRb}>AeS7=#kAM7=AN|O)LYL#Z0XOCQm!i9*O1nn-3&vgjM? zo-E1XaJ$cRCC1|&9UbGt1LMPeb=B2J_wOMt8yXqv9~i8tuFMzGZEcOyIy%NihH>1< zRJN_XZSBRETz&PmmtB4ZN`o5MA`JSJM7d%y-I>kW{p{K9AO7!8jvhZ*D5P$>;ks+C zzI@Xa>u|L^wg zKc=Z3)0T|%2e%;#-6I2C#qlH&n>NL2?QGD}tVj&c7qSZ$FZjsEKE8j?))zKE`Qg9+ z#6|1ZrV`1%p01O}kDNVm=2I6;0<%}J#t z=~U9ErzbsG?XTg;@(>28POFPaBo^s48cmqiz!wUIs%iqk2)gb3Cgrp%W?1mr9BduM zLfcI%UM=BZ=m`*cCUfw@O*_cgFdVfV3l3T!Qv!!v6&N}bzyndMt%g7_5DFX9APdl1 zOn`@ZK(AixiP%a-yHGN>p#&T)+B~^j?)=%4x|TF009OxPBpAr>z;vWBiZ2kL*fn4+ zNGu}UG@9|HUfD*EMC@0D%Tqb>44}hTtx!KuutAw zM4^+oU?J&Tm_kmwRAtPT_(-$|W7sJq^h}fHZ*oQj3Rj}g)R;yCMzncTvlPx3Q0Wv# zoRI#D`5vg(#6-1ysh-JzJRNCC$dyX!Q+wG=&hIU2s;_|{aDxQ%foO)5iV~9M9TK${ z^aN-9m3#GAEyZX}k@pu`m@vqb$Z+cXi8R9^0s$ofUe zV^bZ0*PJ=C@3`Z(nX_kUi8EPPx@f_tKl|x*mt4Hzs*RUjapl-p;>H`V4TpRiHf?O1 z)>>5=*}7$$-_NQ+b6|9I$RG4CU%4U>&=Moa!aEc`xPRa7o!gic<)CzoVjy`hVZf3om;kzjmECN{<>+?Tc&rk z%$zf0cyx4hIDY=jsRaucwzstd8FmqY_H_5`+_p6uO(1&_TVxjWmWCsh7hSyemFJ$D zGiS#7b!%#>>Q0_K#Qavsrt9nKYpbdg$yC17Gk^a4zOFO*LdmWj+iL0>Dk`fJ>8L-% zw4rMePO*yufPq>nikTFUjKS!sHY4$R)Fi|8jaml6Y=FOY+!~gl-{=Ek-UVm9U z5vyxxK7Ha~LlE_hl@^lG*w9!s9jR@2^07z#em(YPFm=T*uV+IFb+uL3-f;a(Pd*z7 z<$a!9T}_zKJm3%K%RQT)d-j@5*Yi@dT2F{% z)3RFYWeQm|4Z5or0L2AtM~!8|`9;gtGHZq-)m>*#;S^;25YkdUfW^rkT;4n8OT4v9CK<0N|b^%zLGY?m2iqeGPF1UORdNx zgGM?JsLcfVoXK*J51%ikvLR@NPSIQs1em8Yl(eHFY9NQmNP+oOP-X{uvaa|0{P0Kq z+YqLnBU7x)(2O|%`63noYFUa`wJY$RZnrX{i|2!Zn(aA=%8KSIPJT5pc#S zBOwscH4=bmprCHpvX>|Y0^#b)+U1Mqq|@oKSgfg`eo7X=cAJ!z_|^3{(Vzw*X=+cF zb7Pz_&!lc;N-j^L9Hh|z4r(+pN!U$~o}RwrM^A$=)(=E6*A$Bc2(_C^00AHwKnS8V zQb`ilYdi8L7%Q7XTL>5u4#MB!L*AWI&WT{aZmeUnq&iYDf6@G$-eMKX=Oycwee*S+ydE>R$$H&Glz3j3_AATqvi{EkA?fdud z-?ejpAQUVs4;i>;Ih1=8*#201L=Iba2kr0sqq7QwmI(hi`YcIdP{f%u$jvi|7=={#t|9y0192K}gyJcW}Nhso9 zbMcxTZ@e*Q?yQcs=5R35(|s0ALxHMm>hWT+M5?!UsJ*3q|NcFdHFdAO{Ibul4;hu1 zIUvp{Xkxm&gE3$Hw4;%Rx3M4s??X#+Rx906>{eP+Q+wNOw{N`W=9_N1tERT*nWr93 zCDQ|gXYRiHwvNu}4fVA|H@lCX80?R3+wzLfryFt5ItM>Hkwa>@y_vJ-kMy5==X>7P z+TPqyU&)Np)i*jY5`E+KR~Ii@G&a9EQHmBuC4)IsA)X(tj^!wY z9Gw&i>Z`BX?f`Qd0hv4wj80^zLN{zUxen)W83t(J!zrWq{V0#V@kRS^z(1?AC8oRa zCK?;;oodCQB}Chu79%y)DzsI?vysz%vT8|z)W(c#N}Pr*h042RsEdQn(P}X>Sr{4` zK5_hvZN6*mOe+`x5SlPr5tJPnL{JdPR7S&^CILxhCK6RxY^7gQGM7>L-vDta>t9jb z#YFh(_4o?eY;|o-I-7p+#TUoNW5*9227Xm_&5JMKT^}DF8aj3I__iHy96NS$pm#7D zjm2WoXmlhJsr=LZe>#7@r?;=SqPl9{f_WFMyLid6g~tx>WrbQ*T{~^Y%$BxRk7l-# zy*sxCf)!}LjV?35g9HK<9$$ck$lzdKt}row!P3`XezCQ=Y1YEd=-6;Nl}Kd@d-k6? zcedM8=5J`Mm^r&679B|>qr|NvBe7%0PGky&wzio|SFUdDXsxMl*tv6O*SWJqtYQMD zYdaW@6;N7LTXp4z4KKa)d^DQgwRP*hJ-d$_J~}uQ%@oRCdFiE-$4|epedjCN-WV7d z$Yiti4K1&|`Z6ww1s!^7J5bI-#5?7k0RD#IB*$3S%;~)hUIl7T1Aicp&87Zy|F2$r z;psEyP98ga`0>I-u_ zTQ*(0X>??`kV}>O{QvnM-+A@**KmsmcI}G|kG$jE?}&s#tOi0M-}BGD_@f{Gh@n}< zLI8viau!NUDl4nT$43-=P2twi*b*HZ#gJ&mqEEAhMny%{L|ili#Z^;6QEE&u>roch zi5mbE%Ir8|4OHh?z`15B(V`nmDFzHRmXPQ>*3Mb8_V3v#G!%k)GP%s+r7OqA zqW!(y6xKF2C8FcN2MA1n@ghNx1z(^{pL8Fw#d_dIJ8H>*FC_>Yj%nd)J7drVdzstR zT|C6(r7flI2|&S}q=nrb0b?|VX&4P@K)qZWRmK|WfnClCfFAzDNk@J~V`<`XB-5B7 zIF&!PyTKq<2tc(!O%m~MuBMyKD(lBhmv#1*O-?XEc z%%iEP2seW(_HjL2a#FD*-l5RQpQ*uQ#4I2lxny&d3zI}4CG;iPSVe%ea2Z!(>s4!L zdP$C>@ln7@bf-``YwwQ55+SZ$HUL>croKqgJLIyNIg1v~o;%x9R({15S9H$kSi5Eo zVd>3x-14tq|JG$!Zo2bLcVBno&7b~_-ZF1cpLWyB!0oTTsiE9gk}V_lDhq~!5+a&bS{4XL z^hL=0M0p^zaOJXaZRL`cD;F$YTwPm@KeZtw$SKi?3B=K@t<9@eudJ-BER=fx^6*oS zKl0q84?X?(!_WQY!DoK)^Isl2eRlS|1>ODUHe7q{cy!chj~*1$m7;PlL5cRx6@nSV zi-N|aIKs>e$%YgPG{IkxF@Yh4@_F;;uUfgHWBSat)>(BmEo&~mVj^Ew6R65$lHFZr zhKBk=k;r60_fC?eZ$cbRlcdU6^XMJE!AwezGh|ZZ=T9HX<}x_h_UUuNq1s@ex-j8Q zD-0<;ckbNS_=wksuP;v}GOP??S9UV*35U@0fLE7ZLE5lV!Wwk}Q=BRdhbzz_*eD7` z2S7x$QACnE5k96rAZeCfz+x+_YcNQ>fT|<`+o2{TGy#ZR3R-3D)~~48P8Dq&%HVo= zI-StP96ga{&ob#&7OlkfLIVP;T;5Y!R#RI~p#he&0c}7smJGzSok0w;x6H$O*^fgj z&F1r|6dsUr@XBP;)s>;Dpg)&NBOZ-NESJ?QJUZtrtZ!_ssIK+eL)${n5MwN1sn6#K z2xQ=1>FC->#+uB`$C;jsI5A2cVX}2$Y(_`SOht?WjINo1 zAO;KJoCAbE;Ukzug(PEp(~O}DVhX>EM=-_B4V;n~j3j7wol0${TnB2vDLHVm7s2?z zuTaR*ol~md92%X^(=p}oxQF5-L0Zy1ok`n;^0GichOAw0DT0k${E=jI)PYnioJz&k zN>rIx|5|+^ccD-$Rk@uSwe*K^8b$t>g@AUlVF(41pL{xIA(ynNY`!eoA0$Fx^pdF}btE;OXeBl0H{Ospv&YUK~ zWs2(?=s9!t^tm%<_U+kTRaGstg%x97z(EKR!=em{WFnPL^>m-tlX1B$g13X-YuMj? zR?nxGe)GFO@cs{c@-vIquWw&4FVa+Vw*PFnrKw@&tgCOh={@iIz(0KU-j@3<6wUk?xt+EXQt%S%#wxl!{iG-J}Sl!y*R#RJ( z&&r7~y@xmKfCwJs>p9|`B9<6|Dywk8Ee0Zna;*j3i?u@Ng)4Rf37 zIkA0a{mG{m_Yh3!Ou_WvkiPMU%YorVePt|b;7EWCf>ZR@(tFpE1^~2%uBC1zG>v5} zaT7qC;=7f#(P%|k)rcZA%~oeRnMz{W6w^2<3J>78?1TRTo2I~*U6PL>orz6k=rk&)q8ENZj9JxgY> z3<^QU2t_kI@o4-XKmF*mTW*e)s$T`;(vF_NF&~=;I&x(a(NN z4DhzQZhz-n?ta^yZ+iBrXIMswl~WO%G(!($IM1S^k)tFfRv=Rx_d+i_RXk#C2!JMs z`ul3@8ka0tdd+p$ti5=BS64SaHXa+#aVmlqf- zU!H}1s5PLn{?N&6=JbiPxnvdubZ3v=`<4rZf)U+j%dj3Sz+z8L>R31y1@QX%hP=Ji z5RC&SevXBtS3%ljD6CgH*~mC#ZT(B}jF*gWn8;~Z-@g*e&={VaSdj@X5YrWW5AMSpAWa^H5VXDrq6CVJHz_%UP@F6H@Xo22e=Jq2q4yG^PiIY7AD2HryG|gqs%Q zW;VDE+=?n3ZotYx<3v0WEAz@*p?KzHG_K4DKf{`!peLkNXrMGOaVx;fJs@CSSd4Xo zwg?ntgbyTh6z4=BoX{?(D@PS&dB%4RNKGWmghj47OhAcA;u{qudY885PI~Ii-;+ci zf`&_xlF%F6-Me7a*EZj2EB{_(qb1jXA8ZUSS;nfzW&v4;M?ouH+{LSqKU9*S z9q)c`I+Mv4O7H!re}=GS%a>nr#bvYSSn|R+oi|Tt#)bbLO-=?z(%`nza{Qynfc~x!`m9#L?-~JFncZ2}y=Rk(QSB zp1$G1;gPZ75r$a4a+x`ZlB$|omeiAz{^5av8*jb!&bPc}#oARDufKeBWbDwv{rRje zL5N4t#y^BXo+2*`n2@JTpY2+{YQ=lr_r8Dl#79q^Ix%PNqE)L`cFvqpU0waiLl2_K zUcL50Pm!5!keu;I=89V{$lCr^8V5-@Ig;A{rZ8wiC{$#}qhK2Pq0@rh`iNlS|; z$l6r_=u^p*#)=hFEQ4WcuLwnMg?iP>C=~VR&171TYF0G8RY%86yRXK<5_}f34ULUe zRdrfh*eGH}Ny$Z*TzTl=USctMUPHi1#p1A{v1oLJpiP@Bdet^<+U{N3ZM~?#Et5;H zzG(euEZ*DGTi?)<%cV1^grh~y&O#8`heMsD;1{2+FopG&khcqWZaB~__T{Kjm6Oai z-2|mZkWOCO2^+1my1`!BJB<~GoRQK*W08Y2fFU?$EV4+7woW?gY=v+VXbeGtdRbBq zp4j~if?{ygz%shC7^3K?Dmg1aMS{W3=^d>t&G@KzJc-Y0Y;J`YXot-aUZ6QVQ72YE zdhu2$luX6}tFP(>g6VX!wz?(~4lG+VHjXUi*`%=I&2jp!5I6- zmy;$*uW?b&sphn!znxHOytP@36ONA20|Ub+j-6)e(5b1HOX^dEB_Jd+#xMF>S820K zIGN&}YeQGH|TqP z%gf7_ulk?=`hGGQyZP2zk00Hi%N6>22aX><+tbtY&Ue52=+XUSqhsg|qhn)t-}BZr z7p-903k1VHuWxL0{MgY$x8HS7TgRMTyLat7d}!PDZJVEcroV4^_S^-@%;@}O%b$Dk zg;!qPx_!s~H(uS=*LC*Fjhn96uxZQdFU8`qqel;)ICAE|{@w3**ZW6?2fMq@!-}S+ zR;Z4%8bZn7gq$srkB`}I?);gHmn{A1kAFNgJUlcwxOUyeG#DKnd*ac@h`o%T{E;-1 z0fe0Vd#N6URJ>PPw{ksYG}7%KcvmJfG|P;Q8jr^x9gC*4OpD%q&pT1q zi`QS=($?nn;|EW7A3HX)p*vF!ac*aI&ef=AXa%Py6@npV`@Y z>cp|3fnk5Cw}H~C+RaZt_L;wk(-E)M(* zW+~xrI+H{kXadSzK3Q5<*OW}eeW6euoy}&v<=#B{DZXh!HkCtdG&kedpbMg99biWz zsgv&B5BNg_nJ$KP%%PGVFvxVBqup@@EaoJ^LbXk~jZO|EP*mQvpU79&RQvtGzTRG^ z{6MA4ocW8+oIVkc>+brZ1k8PduCQcW-D&Pz4?$?IxuvzDrf&bfoeF+MiN;;Dcttdk z92p(OX~xG#R3(o?odxnFBLjYz!NGsi1WhvF#gMGI1?^xDNVUJ*`E4?xCbT-+4|goFM?^JgcM83KMeS#y88#RRFQHpP}|hhS+5Qvj(do3cc{Dy^?LUmVgEHZ(WQ zQH(jOt*xc1s&d|f`SlHTIX$Q0!1JFj>Omhjib{*J*Y3CqU9m~RQKD`_SZL((`I?&A zy1M#!B7V`jbu(voqH{-&9Ud7OfBf;s4(!`AG|<=5(z^Phi&v~($)Y}$On5#1me#g; zi|5RmHFtDuTvw>-no@~WRb`}oT6?YXXj?%uI;-6O}2oE#b&4o3o!ilA8&XzH!Q zO%3%OZ5@LHebMOn;lqb_Zr@hO7nUzyeAyKjkBvtgn`VtBCdbp>#`eyIi{`)g{U2Jf zd}S(?Z<{{9++Q;mPgmD>utr+4WN|Q1-Pbj8bl=INhYnR#*36vQUR4=FT_*B4inKAs zF$hX!@Gu4z?AyH?75>7P@BPnjee>@>@#*^d`bZ?)+T4aQtA&!7hJnB_$7mJ7Qe~YY zNJi)?dINW9TP!K_*jtbhkod21{pbK!;lnq+|Gl67>X*O#!vlA{=}oEBc+l^`o(`Sv z8Ay8;th#FXg0;zLl=U3L88lmb(AlO~8^VhshbsKD=PhrTv1rZOjWgP3;xILccI+pr z>)LWz&%A}pHeP$<#*H_O_4fqyk*ktInf`LbvNpA5a~Z5qM3UqI<-7{{oYYfsLRl_L z+Y%4Ph{!~<*)9J~&$S|@Tn$Re<8o^18qon5hz`??Moz~Z@+2~Lra+A4qzx;MS*3GX zrk_$#B}(8crI<3BNqnHr#s&Jq1?#84jU1S;g229+G@uHp_#niPiK=Zn6EM<4IOd2oIWBN;I`x7qF0xYks6EdwwbFEXKtL~4z+3kkl!D$ z%b0@Z^?;Wk+nlFS;D(5Do)O=v`(qh}SVWjo4mfhc!4MN`z(KGGP6E30&$z4&S=2Lx zTkKjh*IqjV5+G=bnK}igZR`SrBd!^Hah#M~09GmI*fItG~`1n{dktDFiGdMDJ)Gs0h7a;?lVih<}F&t176&;`Y zSep7(vO=lng=7pe-6Ct6L7|>s1`s-AY;_}%u_F!D(Urg^2wS#f={w$f_Z_$2{Qmd7 zaa zXkcJqXmEJR@@3)5$f?sOFTG>~2yDFin$LatORvBF((A9j@!^mD{S7zXu=(jHpL*<} zC!cuqLm&Rwm%n_kztr=??|tX!;loW0EpYbw8*ZC3XAwU1{ORu3UwZNA!JR_`r_;$% zcrCTF4L)P^1Qw7^r=NY|k*6PhZ0pOfo;Z3S5cF48MXIYJvFOmBANbYjBL})pAKSlk zE35QSARG!th+y7$^_ep#4-F4=@87cnjSK|*Cy(vh{`zyh-KYC{PM$q|P#Z$&ls2jS zK4R3-(P1=E(v|SU-@;@8k_QIHzwz(?QD56|{!Gu8Klj<6{_v-7yt3^(-~8s-*oc%E z=}eiBDFbJUj9~DTfOMo5D^iSUieu`9#EX}4$-6cjtr@)v$>jL6Pd)a)eZT+XAMXF$ zr~YB{Q!iJ9>qmx0y`GBk(M;b^BALfqHNil78bJMuU#1k;fB=`2hC-ExPoIq@3z^B% z=EnA*KZF+NvKfZ)d%Q!#W8Ofdv9YzjrmniK!KaVo1+=Wf3i?tB zRpLCbCiK>Q?MR3U{Xr=(!x25vWExoNwN+hpRTV=h5_Gq+F@Ob(!p1PPxyNoBP%GWc zU=nfUC?opC1U^J>dMFy&ph|k)6Z<(vMrU)=^h(B_xvUU2a6flXIkxn=9lljlxe zclGs~pLy=_$DfQuLSSfDB+L!y+buZ>4Z^guu73`D*x`s{6sPmqT$*`VQyi7KY$}sX z7IMU1K3zEWhAYD8UpzjJG=P*$#q-%heO*I39UB@N3WfFd(z=@JaJZtY>zuyrGm(`N z+RA15s&)VN^?yyqM7DiU)o0F} zibbQu1x){`OnT1j1t0mq`wtyF8Vm)Ei{b$P8C2R(T538jE@xv2*g~y85G3YB`%&9q zAdKl^ta4a(xeP_3G1LKtK!z1G)vnNz2Efi_`K(X>=K6y;Plc3^zH*e>hssY7H$kJP zRIfzBZtwroBac7&z~+};Sh#duBosP#=J>n?GjF}+&3E2@tIr$KV`jj@BTN=NHa$&i zZ@mBhKYikp?~BDUEF($^CEeZUZ+X)lh3v%VKJ%$x{qFuPuReG5$jQY^77vdPr4sr6 z{=UzD;Y;s$*E{W%Bqe@gw|EqM8ycH?db)h}`6khk$ z=7pgRhViHQsoZXKElxjZxGa_>qlIV0M;H`SIlUBH(MCpTEu{wHi{d2^aY}BU)bjF% zQh1_KU^w5wI09N;UR_t0N+c5Tm_%R;3k3bn_y7I#&p$QN-^YRl;B@g&g_wYY*gT$W zCS!wWG^XCwYcF2CX6+BY_dS15mu_eujg5c&(_egJ`?g&>x9h4`J`ENM!pn8jDln!Ewc>`Y2@tf(?OGp=!2%D)sgyul*rHUs3jEMZH#4~PvIX15 zC0anQ!O`3;t>eE&*9I24Xa^l; zaXlVpenY2T-51Qvz!Ld}Yc^cFY2&|t{ky|MBbAjEZSAe^de=LC@RQ$;#mB>u2=Ow$ zU+a}J-Dw9v`!WIu13n*)RM@q$$&zfowYlaUZ@OV@EZH+SGJEzkP{MG)L@4TBMB^<< zLKVj-=06J*qGqX)6owzY;{o=GHP&3{x{eG(!pWvHSuGp#IN59(yDgbKcI?z2@Bd36 z9JCdsmh(V|TGvILO}gYk0`0we)5gm#U48P@>7JhMmtTJEj=S!th(x~it#4uGASKP! zTOhT!oy%k-OD8!JnAnyOaFC0ILL5{>PE#N5tz7SH1_w>BUJu^Z%doJ_R&)ji3F)Tm z!X$GA;6<=>0;{y)5D!zFu*mEF0RjYIFIY6UuBIL*F2)nRPE3r)qq}$R@p$xMOCznU zzOj1wvZVw~(f~zRx**ndzKiL1TE`6h7Wx75xIaeOv2#}_QaNYde6JQkk_#!5N#nIJ z3Dn;RWt@pbGWpsoFY9)D*|HwFv4$9{tgOcScb`8Kid2BSbC1Swu~-S>pxXIgGhkGRI8d$N zh`dP|whHCyWQk5We6uF~{kos=+P29gy}GO5+QVk6yt|xKD zx{`23MLZTGW8;W?yeEE8#yf!qqGeilF#p%o)P!)6*=${Xvo=!g#ZSY-0|XOHUj(G6 zH%G#$dGqHrH8$_xdk91J`3N#5J7&!685)53Rn@in_I@%Esi=e@^wlUJU+#5rvF=R> zR)DZ)qNHImCYbsW4{FMwa@eLiG}G9{-6gXkyQ%|XE{N zZdO)&V>fK0q)eR#N(uo4G$EOYWAqj!D0rk0wP18&e8v?Eq-~&D8n&B?a`s|iEm3k= zCQMBX+ElUEuK^TgQuH(#si@Kr=q`lVjAdfAcuG%&*d{4jYZq@+X3fa3xZ_vvNwG&K zNH7zg822>UxPBzZ96Kd67Heouo)VXUso`Kg3a4!;88M3E(;lv-ahAlGab#TrxzX@2#V&hqdlc z{_iIbKl0~_s&FbE|LEU;=KAZeP3lpcvPiJziKM{A4bx2aRg$8=_+)s8LmQ-M~QCv}rTy8|#M#hkDOY z3V;d)Umz3=h9QZ*n^>p{@HLRL66yaj_=9ig%%@NqU5ga*=L6F6%F^41s zDI_rp4IKU?PAQ~BgdlbE^72YLRTzUq601n$_2{I0I>Hr95yj990TVP3tze&gjqzMR z;NF^CqO(WTcIYb6RM=4=tqI;(evNp%Hbs$tZ;sik1=PS?UGps;7 zj_90$rKMY$zT0U}n}M2Lw|P*GV!FXm=6 zkZ_fbzxeHaWAWIAE7zsc>EHb7x8MEG|I|k?0a`K{3|BCQS)pj8&9OSZrjq`-E-OHm*>)%2Ojw2 zM5$H`ih(2~COCo{Jz)W4UCz>yMQXzkl@%3>mdw9o{kl-N^0$9{bZm5(D&&Q$VYW!8 zlla`)nmXi#Z$m+GvP7Y{plMCb^)=xeHm&RJ9UG0u=FV{s*Fd1HRLo9T0U7clhjSdP z=Bu)j@~?d5UQ-?^zh!g@nO|#WJXW1Dl!!f&hU`SVqEAW5(D2xygGVj8QJFQDS9KjV zp7PF}DHj`$#^UkD=2ld2aByIBWE4}tPN0gJgc%iPam4E4(P&DqL5y;mOll8{pbTM0 z$48-V+Vu8&?s?1QSFXR}@=GthY~4i{U-ZW7+Y+&)mS5myN&pT-Fh-E0LWEd`qmb03 zGnGKzN-SWpA|-lZIWkyz7TYD4TNGHlDsG5|xk5^D*JNonlgee%s3zzGuD+oWS!A-Y zX&vn>g&G^1=ggfA(~`-Q$K!VhgE^oUE?wgDmo>K3-+0SyJ>A_fx#%*OIKatP$^-%| znNZRB^XJ3=STu?Y!!o?4UJNHH1J0SZI1x)svQVY5ZGt$0 z8A4b2MWNV8^uWRp62g%RW=dJ60%Y9`Kn#NA`$HjI1Jvp=g+7fXe)4DJ*vj1YJzzfZ zENF|#b}dNqf^oP8^C@u9rkEnH9R5PczSQp~ZC%4HFVnh-xlPK>C`IQ>0%wtJR4AFY z2o|FlIZmkAYzn-bS!Icp!hyHG?X6yaxjz^nGK!5Qo_XpiZ_r=n^?I}kP@0a8mum+c z%Pe{S2i|w|=+XHL=QTFe@7}Wy|B^^1_Uzeu`qU{T2+UL}ttSx*lfVASk1-IRJ?oXu zWG}zsvh!!p4h#(7EH#;cS21+Zr4A+-B0CYz)R)bGFRY^k+F*?YA-U?-Z%Bt%#u@Pk z-=|1LhNVK&Lqa&OSV$fYnCepQ62oycHfY#e0;FK=ep}|?CTr&pKpINLEKr$pF4X7$jg_nAb9WT>1SD^&mUT8$OJf&yw&uL^TOqExBxW*LfD~@p$(4zxnmh$jE|)3toTu^`YS*q=zyA z#(X}GOu{0`u8r?Dr$K^>FJS17BGQtpf<}!mU6CboRK|H**VyVA&2=X^;MC&>!xiC= zfBKWd!-I`2?RUQEO*^)42}dFy`}D`lN((2CpTML|5e17wr~*~X6ehB|tG%R9TVGRO zU&~U_>kUZrm?w)ad-AdkS2i^_#}ni4e%}ZBdb@}MZ@lGpa2V+C^?E`y_~KW;gdbYC zc;RP0`?*)1f9@;)^sk$)y>{)z>z{q%1qRgoYQYG^ee4sTn7d%^Tkd(=hK-xX#zwbp zdEKuM*eG@_E$D7OST=n|=LbLdp#=-(e*W|SxP0Zx%}+mr@9nSWj zX<#TifaNRHwQW9|44fWneIvPWhNsZ-(2H|a=qisVy>b(PIc}o#;- zh18L&g&4<~Y)+)D;`AzV7B57c89rr$7F& zxqaHg`SbSg-TUlQPwB&c;Rqd)(J@*QXVlg-Rzxb^{Fb-g_nY4x*?;7U%P)KNwO91P zh_k2O_nr?w@Q3>#lLhRVlgCV*JzHOY#lAOz`jurenGIKMICb)P-{9Z`;xG#mqZ|$3 zCQT)y6$;79B@jA0d*B2^#pRiH$SN(Vkw}#li+6%)tb<+>EhGtb*G(O2;I;)!KC)-y z33=UQB9Ul|ish`&Zdagy#!kH%#Q_8khK8}HQc0%vOD?%2m!IhE>&N}Dw3jiKmCczu zZ**kj=+PsoOv+>1S!jq86HxG~I9rDag!=s~l2}%1`?jH_dG6dfZB0$t`~><5J}i_m zMVv96nRMU@-o~*9I$0}4f+5_>%BAy1N8>1BO>LD8!eI0UWdftWeZR1hCNJ^JFykEl zz&~?VOfO27-aQh9;y(1dhwr z6;wf!h2ReJx>%jpcV|t0(1&e?10mIz0(#`VK7VCJ)yied7R+DpcYpVuD>hv05BN7-zu_%!y_+Z=hXMpcQ>olr{=pA_ z@|x>!x$)M!zwxdAZER}z$1nf$e}4DB-v7am5~ZSlQf)WSm*r>9ns(#OxBlISKljitUszY&yf@rf%7arI}2$Fp*Rb z?MG|+B_O3C;Ymw#bH}u{nKL`1qoddcLpwp$JpTmWn9 zDnIk-PsPTQr;eYksi--8=*0bhxZfU&6BXpEZ=v}LUAWn*wx?uw}rRJW3`A=Or7Up6O8LUkEpM=T6 zTf!GT@}Ur9Bmt5+%mjmkARg6(JlVXiD~iJys5+TID3B>Zt5GUVF)#vZ$y7t)V=U7V z5=K|Xax|SzDU*zmA*#TE^4}I`3ZhIsCX$J0G8MCHKaQi!`6V@VwR7e#?Cm*AP#Os0 z^dglJy#|jEv#zc&QdPrxA56fZsG$l zqLnq8)(7I87)6nk&Q^+QMaQX`Lk!uEc1CizTkLtJe7=R^`;!efIkvM+7|K?(>vQ% zteD^0T05h2x~IgGN+hsln3&B<`&m{I{dvlLhy;1y#j?4Hqel+4Pn)q~<*NF++U;Am z4)*s)s;bh-Buh)o4!viHit0#ZbtpC#lS8lsn#LmzB+WD=cS5n96*++J-U3 z<%BqClB^gRIooo|EppK8U?6zib=U0Kwsq^Pug_UD|9sc!4}JJ!EExCf+_(LW?JQ~N zfL6iMiHY0|H{Uc_l3BcT*{anmo__Ml^IfOfrZu&jG8DWQ-oiBwd~Sul6~C6}Z#$#6Jy?D)~@%KGP@c?#yU?ChLTUt6_m z^_t4c>T_pL6JKxJvTb;9$Ywin$(VxVC(_u&Wd8QsZ+-mHzs#Dmpu4Bw?`wyXhhdlWS>f{L%mY{MOrU>73Ka6cY4TY~Q}q7xZCWxk3TKfA_oJ z`^=|4aoer8+<4QC-F-dBjvdo#SXw4&2n~~p>8IR;X)4o>*}v`N5RTGX5x1N&d?@NR zJuPT0pu;#7r?qH~F05G_8>HBh|CHlZ$TDN;T)JVGdZsW@Qwz!INscn2uswVBfA^dJ zar)%3Cm;XI{lEL&xzne@kqYKaU6O*;ny1Tw+|zZAc=k8H{N=$t2ebLY!6V0>f97dS ztm}N&_rLp}`E1V1QbVpUKYjZ2`i6#m`}W{mgnYRV?{n#;mz_C%va7pCTQJ3CzKmb< zgU}NCI3_rP7*uOgYutQO2*NbIQJ4^%$qm;##?S&v2sOiZO!0t&y6?Uuy*Y_)C>sy1Lv;3 zcGK!L7mbXJB;pCCkZd}2#fGa;xvukP(Q|(&LQKH;eZ9SqAC1NsHkC}m1bm36tn9k$ zF8$zp?z(L4MK8U!wSQm$60|*9?nxyR`1EWpGtk?$Z`Y2VGiR>9`m*Iq<}F*gpth=J z)5c3`sw%50D?&j(bHKHmuB@)E%x3e$V`C@>j@a+>&YRt?sbR8EU8P$NpdMbi3n>U2 zopS&9bNqJt@K>F1%(krDo@Fh6AzArU&4p$v!r@Ya2_eHsxQg{l)~?1#ZI}~gw648) z$+9)`nw#qedb<ew zw_tW#`?TiP)=(sfv4J|K*sNb|5bnYp^w~f%Z<==$6ar}V#B8S zOBR0S^Pm3myfd-%v+5Oe>U|sfF0^qo4fDwb$Kz{`}d!yLK}D*VZ@Xb0z&f z{Xj#T+ow(Y=C{AUVByk}Cr)9a(P+H6qwNd#elb)TmiLs65$5RjyKp4@)vtZ6y?xp* ze*BZ(?t!(d*B?22fNBw}0EH~}Q1Xvo{^A$Dbnoc!a3+Ex>!6(gy_+Nl;oJ|)Q5_yiu!CO_p!hKyIC{m zzWK&mgSJlxqqQ|w$Tv6DFPJy`sb`+J|GxWA96oaO6<1EMn$w1rd(O%w36TLoO%tJo zoTw(@A>#1*_1Xj~7@V*U>=6X;X(^I%b6zjRNXi(7*W1uC&6cGK!{yB7t65e_sU>%u ztOpI03-j9B^L$=EVltA%WM^HlQdmjI-od^BTm$h}baY%F+{x!RUVRhsRWT$~(hbW! z-910}-uJh>x-DE?*W1_o!n04H^N&69=&yhND`?ebj?+~sp^z6ZZ97%Au8U^+?f}LN z+snOnAC>Td%}nO-L^nC)v$|s+si~!Lk4Z`K2S2uKmoEUI2@X|;W)}6VifU>bp#__r z3RcXk={lv}rdY^kFzG@L(||bp^fE4r^(zDG0=XuJES=NI#Q4ZN-u9kV%hoj2*T3i8 z@496Dr5moi;{53|+g^R?=;6J0zvZ6QYu8NgoQ^U_qodC82wPor75+yLA2@Pg|MoXt z`SU~fpFVvm78~#H>tP{=AIRyBCzknz?!Mlk(UGx%-ef$^syC@?3FE?QQcpBwQ<+pO zT2_d!S-$v^HLEULy<*<1c4mwN2adh`%GQ@(eXX^np|&neBo~d!ry_e;j4KN;pNVcA zOy!hhFERzWf}*R?#O7E;D$$n_E;L6Y_@lLIO#K}^#ahxVtpcc_|5Q?gk(>@rJT_ii-_Y9H z($rWF^9KiqZ@B52^_Q$WdFs@{Mf0Y0PFuZt)&9MEe*Mdz%$d6Yhk4@oai7mVtyok( zCGs2{cU;Moy@+#gzp^+;#Y<%U#=RWrF zFT%7?B=qDXkD@#X7^Zo=rEh)P+i^hu_rw1l8;Q@FGw=M_?!kejV|%;smFezLsGe{j#PuCDW^PaOwfBAMzscMcN@;a|g%u5+i~c;&T69{S6HefwT` z?x`)WzxLwuPx<{}5dbTozpON!jvv^wv+I2K1NZ&<*{7d~MN_~2#m|o%JQ@h<5`owU ztup$OTqfJr+WPmO_{6U5dmjDsqa8D5Jo)&a%k^;=ukoeGUL2Gn*~t>GMdjEk1BrWO zoTcWoWZvG^KK4B>EyYT$19!qE^UO?9yvo zr@Dzpxj`<9*4I@%e$xuucVd(A~_=^l?Ickb9RGCYC@$1|^4dr?hI-Qd7L_xW>aA~+WN z<=#L*ADh80&;ppih%nnz9yod8%wHbg{M6>>2Zx6>9n#3w_)Jm7siiRC@dumg>Tw#U zPM;Ybi5)s}Wcu`Jtt~CB?ale@B+)Sl`2B%7b2`s=_vN&eGEor+5c9YkTC8zm$7IOuZvRJyo@O z2r3>Ow-`bqXDErx_I!~TJPZdy)pZrVfWNY`67-mQ!xa%?vEJ@(kgBh5?C*?>lnj=*K?!VKgip4#X2t=JDp{me2pgXU9fTg~_y@LDhrl zXfHvP7y&JgBcOx;EF-i)%nU>mJ5#mxvs9#V_YX^;&|T$crlW`|cq~hIn|{d@E)ugz zB{P}{C-g;6^emH1bJQabKKn#-=|m`8e(N1~m6rH^^UI&&6Ry4Swih-(xnR+BZEM@KWPE(*wl}8FS&)b(x=$VT z`-8+wUYDnqr;dBdec^C$+v_h@*P`I9{Q3Pp za&bM}J32Jj*WA)}{>%wZ2_BQF1jCJv599l^urp6LGCcIS|7(IKAWb9mkFx_{zWj z`<`8U6S2{w$Bw<_?QcKRb-uQ)exPsoXFvYGk&(evD*oBeeF2a7`YW&R-mx`UQO(3d zs8m^1hoDgyEHM-ekwK+l1}o%TUijehnPBAd@xdP57z+L@g6A%ny<)`*oJ`O8f!+J| z<s$18`d#4jbI z(5Nny?7q zthhi22%2#G0dzl+OlQ)W;Stnph*kDLe;#cTvjgP5j%=ZCj5VIvxy!QHkTn4uv9BUFXj1 z*uEVbpSNf^UJ?VqR=q)@*bol7nxVaZ3=C+P^zdLWa-KG0HhwUbPDLWs-Di)tOq)?% z+kiavyrEyO_lF$foA&9H*JrZnrj}_9jV(j{eVua_RaV#ef@q-b11HX^tga=_>gb#c zZ9abxZB8Yk`CNMG%5|VUW7ga`^OwY;WBS6DPcKr?Rfwuu=we0LIeUI(P35h(-*V@h z?q0j@Vx02vqeqJzW}c8?Yug@C>oE${v6N|Ga?!$hpZMg*Kl8~?z5d#(pZLTlj~qUJ z`qWvU&l3q(rW2{w)`o9==llQjU*Gx7FMoa89kxtCUMxMy-PBvx^$m%;Da!I zS%NVTrBV#3hI}rkG$7FeH-tA_f7zyy;lZ})vpZ(Y3gJXU{`$JQgdX?u4i63B5r|mu zcfoKZolI3#*Rp23`o^0!U3-1!?9Q{NPo`7p-kz?mvnOd&*Vy7^`4g^~zj#Go_qpi! zh%X${ECm+~3qrmtH*DOqdk5>G@^T`2u+W^L$VZMO9T} zOFL57bj`-j8Jz)Nu&b;0d~aVmpN&*hELbqNqoZx{;`yDO(}>U3ty?v-bNYcJ$4;C) z0|Bf%D#GDK^E=1KQ@M#ek*rZ>?;C=0f){yOBlrJJifi20YE@@P6o^R7EI|#X63pR5 z4}DW5|0=%nC#J>XiQT*QmU(q^IBOkn^^{G%_WJABTzgeEoyJ9WcFs6_^vLXavo5-L z^|2#I0^vv@r>z_S5<%_07=W(Z)>u(ihOH3BNN^%d6-b%sFmDh4X3|Vl+R05MlG#k2 zE~rZ)5rg9`Elo{L4ZC;j>Fw=ZxBjvd$B!J?zwhF;>kl6|bo}_?Tkd-Ef~AYsuV2ra zx2LDq{DQVu8Pl{*eiK3%0>My2a4n4#)kZw1iD;sB5lr~QWZpV$20j$@(MuURvjleI zWj$EcF$*ViZ5R}%fOjKosjjJuR8--Znp)cFl1e0fzA#P-tg34o zLg5-F=18~-|ILI9X#5)f4?P|qAFi!!1Xxv7jY2AWu{;KlNX7B&*w}(at73`Rnd8Ss zhkC1O>v1~NLIA-C1VAh%3EK%uV0&Xzo2T4+?$q&)ne!?czOH`y%(+Z67*$J42RI`g zC=FLs!lZ$|^XYW5efk{8XDUvo6Q@rc*2}rRhZ5cLZs4u86kREw3{uAHU*H`0__aE5LxGPpJ9~&8c<>eO?W$QZ1 zL~V8DyWaiIM<0Ij%$d_`)~>`np5FW{wFVAIWs20~ISADB*e*$MsVK*v=Fljax(O6v zV|Y%kIw+?jUeonL%2Iv)BzSaOQ3uLq4Fy&17G0r}`4@GW0!6tRshp%IXf|AZ)BZi% ztE%f4EL=Q)!MszaPom3udw()HHagnhd(PwaGu2gA)u0b!BSUmucll+ROzQ0EQ>;sd z1_l^P-#@OYlO|NNXs$;DNA~Z4nRZ{T2GcAsF#&{uf&L?h4lx5o z8%TG102G!|E8iy!yyzRAnqd;j)Ugw%aO&Zjnp`1|s!Z$Xm^Ei%Hk*Iu=_i4Fg zpL;QtWct+0=T@&?8>y`6?d~5N8?A3@(UVl=rPJD5qvO$2XU^H=nkU>wzX(AXOB0GQ z00e*r(OS2alrZ^bQt`Itwn!*4k)Jqy@_hf`P--%p%4CioJ-uh|!CiX}96EC1@R8%Y z_mVj|Ff^(;%C68>RfZSLnI4U%^OJ?DD&iqcC?2hr#6+h9;wFi?*-oL9lJa}M`cJM7 zG3h8>ku}ohf&(JCt|m;9P1;gF?Iw)JVuubL)!qlaN=gVR!{N}=PrX!ITN?@oUwH9_ zrAwDAUABDLlBLX4M-CswWzd=E3^`<3bO=rn9GD0*rwz8;ph~l(-IGgVXdxmdY6(C~ z0%TUo&CM+h^)=hy*mnNhxvs8r1APO%-F=4-9o(^P$F5y_x_VUj-~+$kx9>nCQYrT1 zcbpQMrN9}+;ap?sL)lYCWz>>$za(<`Lawc&6XlD=#z7zu4EX{9-O2;6^foE~lBG*! zB&W{y^`1xh>Kj@hgl6GL1$qE9{1%|<8yi^w#^SL|O1H3JY~bY&>Eb>Vf&xyBxp%?h z<(L*;mDzQ8sK1_Y2A#I&tcmI6E+_Rm{f4IY%E}r-{&*}lHZm9+8)~01hf$J=7>tsW z)y9ZDROTtKs;ZqidjaG2oI5)-(9eXSt2kvPwe=0DR0_s~i62u*q%>{%OxQd!JTN-c z4@w;~=M*LsHsa7LDypk%n>2qAn76bxx3;#lO#?9oqHL&t>}Nmv;X@DHciEL2_wCuk z+{R3gUvMg9_dk_p?fsS#x2^P7UUbPN>(?z?wuEr|>8GANaqM`xR~KPe%Ojb2i{>p} zwsPI2msM3aJo)4khmIU1?nYW5gZ=_Xepd06uJ+^$+INF$x`R?}Lo>`odbE=e72xO* z+q}M{z|eYr0Z`PU7_tDT%GLoq=|XaWin^QWl0i<^R>@UaMq8OGEh%AYWHE8}%t?Ic z@>Ofma9ym*6^fZInjOoGfQ%)$rB#l=Mgd#Py4aslRNI9pes2@IW1r#S_+ zWNa)P2~D5giNWGYyL$U<(=(?x+m)7OGYaEilr974Gd8J;ib{l;PV34ZGr@|*^WuqY zwvel;j7ZQZl4LEFFem!gAI6emOBE)|ziLkQZ_}jOIC+@LSvTXoy2{~M64z`4VRStD z{~_xy;OjcB^?z8>VLm!y*#a|D?3nGuA%~$!Lv7QfZOV{h(l*eh?QL%u>IbJ?SI$v2;3qGPocrak^)QO`_)22J!0-e6@4(J&g=y)eWN~ z0~o5*%Sx<)7-IljF1hMqwF=Nr3?V2s)6E8)EEp4-U=-A~tZLGXj51g%AyeY74jCHE zK`xL7a_U>BF1M$tbvnmwx;>S6_OXBWb+?~7aj2$lN^N}|3Xw`Aj~&`e7x`RZM zK>}ldAJ#ApdB((1YK>kx{_cRx^tTB(Y!z;Q0FBLM(n@ARVZ9e%%@P?2;8(ohdDY~Q{;qg!%GyvIo-a4M~-)NcIo3r6D496uep^67MY-2??*s|&*vwb)aWM4-7a@c zb$I^l)?`Ybqp7S6(jYoy*9;gmN(YS0#Z0TfZSj;1@z&b1ltd{y8y3?o?pxa`RFWey zMMNVxgW_hsk9{Rv7ujwq5jUcqX+lxP*`iz$0v}U zggK!XwDG!JikW)6UXRbO_}=(iinL9%69VAL1?6V2lf@!~LdVi6&Qi%t$-%0&6Gs#A zxKb9Iy}R?o>n}dG^~EQ5y!OI@w_h3P?Rn*e7Y^*-i=53}!e^kD;q-O2ceEWldHBTs zU2lWSzCf_Aw-bfOE;!5B84DyyrfL@YX`aoX2zzkB`K z^;chg?fiKQ&OYnxTt@3yT8xD%0f!paGJV9S49ekh+Rc|)hll&X0BWLMV1cFQQnjKo z02CT2LxJ*KhaNQ*w%RJFM`VkGVnaNlWxLk?2159!3rx`l3>2A#e3{}4gms23 zAzK+X4-W?h2IA4A%jQ@#XZ~S8ZW~12f5Jk1jkk3S_QQbK3A5a$6=*-XZ|)r^=xn`kWB z+ufBfj%9K=cCj!sCs0AZZnsBCqj@=-ZEK92q9gd`@dvAF8d90`{CTt8E*G6bBt|Oo z%_!(yc5OE!GE9M&AP<$&L`9j zOQ29e%~Os4tdsnOD%4u{sUq9lw(`L=9s;;FUISz7vy&s{dZ0WLPn=iR|&fNKAd`A!M$>p+|OS1T;=h(9K zQ<@Po#D_wa$>=bA+xEtb&pq*v?)Ky3`FwnIIF(E?Ca=#uXTd_eugBw9v~t<}MYDko zlN2kKL2JQcc;)u`ptfoHtYBqmN^?VV>vU4BM0~WjyFHnVle7}jg0`tt0ySTH=32Mc z6{@Vf_^K<;y`wR2&MaFgiLyG&C|Y?D2S(ELrmXAAalK5C8R7zrKIk%o$o!c%sbh@nh(aO`04X z9Sv57SFKsw)KLAmhyMQGrysiVy*G{l(EZ&22s9JG!$;aB+Jo$TCPTOt-_Vn=mxut3G{Niy(kQ< zB3a==Gc#+x+Xg#~_47YK2k3*s>QO@bsS zEzw)Y)sv+#I3cQ;Xw=%ba8r*a&>V%vtXPf!*W3`Zs_JT?l-Xqr(r?Mza{8D}iC=2K z4)(=snq<6s*@pPPoEXFD^5R8Kp46A`Brs%Srp&EE*W#?95?Wy%bx=V@Ksqc4G`_Sr zF`l0gBs*Omb)?7o;16WNsyzJXpk*MI<>2}%m&ZbRY`}$W`tyq!HW}?Hxh@i5v%1j_A-A2vVZ(MWXC6{}go-cms zOCP%Vx`0+raR-C7es35oBS7XK`7ere>6O=oBK}J*x!^}X{9!l{K&#MTLo7YIWMUI# z`H50?tgv$3%5yhgc>M?7_w{?e>8Nm%_n}hO*cl7vLChA5j$C~CB`a60UN~po9d~@` z+8eKf+oe(gl@Epk5@tzrTY810m|M4T&6z8fgY6%>`GZ$nb!DWgGOtrv^b(#Sk(H~~ zUvSCQv*#^noi-Ck3IE2;TLMPY%8L_YdE9VutgJ9bqFymE*3;W{;@F9RzYz{I> zLQYU_v|4S-9t6i$*voNfLPI20qiB0pjHbqL$jxZgf)HOzrsYY5%_CWOQ1k)WkTS|L6*5cP>0SaeGX^Fmk~Ruj6(W|L zZcnJPn*E}A$c!tXm?~W5^#x+F;dD0b)oZBLM6mqhY_PJ5tEfzFK~`>nMogx_V|rA4 zLmohv#Ukz-pG~(0eDwwa|EQxWPX(=d{BxY^N~LT*!-X8e@FV~eDCCPdHnX{GGC7(| z4ws5ax7(S`#)`P@iLz-k=dD_MZgn*dw}Irq9|-sZ!K&)&NOeu5s+!2AvZ}f=QXSUA z$U)Fk`K&-jFBF$oI0gp?63OJAeTPAIhRlCR3hvOmAWbkLfih%e24&;81e`)3=p9pV z4L}s}2KuWBl5)V#7`kANL(&g1TSX9Ap@k2H?nXCEJz=4Rq((IVPq8keIjaeCL=u%^ zsRf!dA)&U2w;@qe;37o&tOSa}9yBnvNKL)NH$v`+13|0GlA%c8;kqIu9mjP97r(@RaIRubH zz1^8;5_Lp5Tu$6RF=iF?B4abD>Ui_j=TXU#p@CE^78@N!1Q3cUoBKHvx(`suk4EYw8+8p(^wb&yU%7yk4AIEIQOkk*zWafwjHjLE+UbDKL|ba zB6u~*W-$<{a0GTUH1mqp_)!1A7eD*C&wT7-pZLfJ-`@7-^jUMpN?N!YYB8-uH2$T} ze)iM1e&kah{mAcr`yiATa|(48n3+ON{279xI|PL)=qUD&^%e`}*#cpo)IqQF3WMnu zB@pNmB1pYNHpNI=B33oCYaK@)EM<@$@JFG;?5MF7e}4d}q(;gNyYUwQJ; z|NeP+WMuA~nU`FA;U9kW+fU#6sZV_P)*ainWzre1$B)>$J5Tj=wjbQRbD+0#-mKQD zfM=k6@C%>1?UNt))GN67JfG8M&W|;sKfo-DF zs5(XQxfu!2W{8ypD4as0+#WA_o5^SOsF*JZR)Vk?V5GVp<4Pr>AQ9KlG0b6LCVt{l zEex*|(;qN=n|zqTy8T7h3cu(}bG~|2!LSg0fXNeMMS?H%R)GuuOk^Me0dmkdn@t;I zC-fext#3GU&Drx7oVj}axh}T{2&QW~%VtQJgg@G`?ijI42g)D;D9Hmo;V_LzY*>@a zRaIHJ>8y=Yr%cgpB~U+`704>daqGPRN*U>O!9>bMpB|Ods%+57h6znHd;uZ@p*zTC z@3ddm5sh5`7@O_RyY7@$a$G+;t-W{an)2?RrPTb-u3VTIQ!z4t(w(@`*ailuRk zOq*5{lSwyQn(xpoVR?Dcx(|4|HHsw|s1PTh z4E|Wh`Oo|@Qk8R=z<_YmnPfIpkvntElH*#v^g{Kpl#PT!GI(6bWxOVdBeqz92xKcB%c6;lzMz;?W$V3MR zcI|wty{Ct;f{-W{9UkoK>g{Oj={PwuIM_O)aoy@On;IGm`ONc=KiAvSJsOMkbe$X> z?xQB-PQ*r2$z(baO^%K(TeM(CYg1QO-%Bq(kIEI@W&bFcAmwMNd~}e`jY?edYRfD{o+*H5oop(-kbVw7W;+i8fyp%JS z`JpKKbmMq+T_hCt*G;Lt`kMFpy}>PSyoN@j%ha)zYxN(S!yeCM&OYz#70b?i`l)9~ zEDhYqoDmkVBgNO`uN^_6e6l$!mqPv~8l@_oDJ9c+LkLAdt>!VffIajuDJZX3pZ^HMFM?2{f|EWWLw+uqX+hl4iCqp zqkY}&_(ggy74yO%LjymkDMMz*==o$Z^jjm-K5+m2{e*LC^UU&oZvjp?+F%yLH=BY*Zet#NW&uXzHN0ekzug$)o{SuHqmxaa_Mz zw1`cPIo&S3P)=~@_i5VHUO}!$V(yGYYF#cpS_4>Px&--DBP=HT&F51qR<3GjZ0_vt z92t(cPMbmWKyW&9#*8CJj>MA5aAg%}Kx{#67>|AW>~3^{xR_xB$0(WZ-c?4ZNo+fJ z?z~7i9Q5lweMtBFyaW(an;U7criPffGFQmf*Va&*_6RQAE*Igf%k5k|XJ$N+MyGr} zH;hGVj3yY&F#j9jTXC88HG#qK@4EXgSgg5NQ}|=TRjC@gmfCSpP^4-)B49LsG-Et5 zo=m3p?LUOL#W(v0Bqp>i{@3Yg!ZJ!s$^N%^>rgGPQaB{Dr}w|KOqh-Ce!NzG7T$7E5}}8=A)p z;}v?EK&vs~@3WbFxlOO+GFFQrW~?gOh8;#7&6vk^1!r~Csw9o(kkY738aLNc6Wo09 z+2b}>xTNs&E9I5epy|ZVul-r%)?^nO}mCLTYaHy~M zKY#ywbaXh8h!sj&v?3WBNhU_lJ#WS3mtWl9J+x}|8CP9<72f69C!gu->(zp==`{J) zcv&fz&CH)O?ISneFx1<(biur9-}jz#&pZFkH{WbKdJGd_U`UooHkF7&035jR{B>*A zt{xs4y6(p7)~{VQ&^PexT@Sz)9XS6>4&qunuI)?hYhewAZ)pf*N z^>uZfogIWWO-=Q?w{P$6>6MZhIFkYyW|C6CO*Y6Dt7|HM{;S`<=bCFSx%7&L#wq{( z$KMYgIEX0GMS3RGz31NVUvbqn>o%Ny$;Fp#e|y``o!jkh6Cg_)kr@9;EA{FD-5@~; zO1C!=rB0f{1_Yo9!e1(*kLGK7CWyu}?$rHEhs}w`gJOh9AO7I=_^N^7RIoDi>@&}BWsy{SEH4yCR2AhU{)E7n zU3^Z!Qyz{quG)0YlTSW|uBWpp3?7q-M@LkdzRetn5e<75-BM=$T1A6E>EeDhgr&t7*%RdvnrQ|*M<^dAmKh+Yd?s9LZci;i}*orn(U-fUxi?W#4) z1781`E017mt$~n802vi$vf?{r#HvqDPru(a0p!%zY&;W zHxeNh&>!iMi3`j06fFp7p344zia25tE3r=1CJ*WwQzWW#{^`c6q$;fd8B3Uq)VI9c z<8(yA)ujo-rQ~RI)a7)qTsm)B%hX(c;f z(y8oQ+xI)%-ZHz=1cEpkcDn58R3n*i4SzyT=VD5udlDl zW{W3Iw)GA4G`BQ2H8$BCwtc&H#p5xL-&b8TrR~@Wr_*a<7g?8OGuE$hg&H`!I2%Z1 zP{!9-(SbY-*iC#DkHwsJSN+tMNM+@}{_@wcGFK`UU9eT#ixX_dNYVRdaLSK))Yl@;GVBSf8eu zY&N&c8JsAT+D{%E?jQcs@BR=BRUbWZ!XNZH>=jhR2r4Q(!~nxXeHh8EcXqaQc5Qoe zUwy+Azu${oN$JS_z&f%AB8xHy4$zxTC;R({fAW(DVfpeimpR-4zo%SJ=aiFmYGM3P zD1>;d7zYbf+~m~fj_|L-M8jUAKd@aHYk$wcr$72pf>Dw>3?rG$dOe|vakR<-vJ}S4 ze)NMMn6<+l4?gg#uJ$%AK~98B#4ls!l@J;wWKxS};L?4(waYbTK5?qP&^lc2Se`T% z4 zO=;v@E|(#v7mmwhM4xd|3Vx(bleCEtL%eonx+DT}apS>oq^QS2OV|$MLWikh*l!0S z3u8rps1j7AmqIQ}YVY+0k)RSIP29_4l{EK-ZpkpUK`~3{&<}rT*|5uQGG|x->gXcH zR+{hxD#{aycuUii4QtMP=bdc}=FIee@D_rwp~1mdU;Ga!d1T+->C>7&aPv*O-`P_n z8WJZf^nM9$&U|PJb3bwHNHP(nxm^|I!BC_)Hl9hR7%~i3YHxSnc>NWX;i@CYj{WEH zCkP{K4re-@#Kh1&!yS~Zd%TdZkNAH2v-_&6DuK^*B1KGg;PBB*DpSbl!HoXi{`KpY zH`G-T-6i7*VlKis0$R95hzLRW5i!|ud)>}V%@nsiZ zcKIb=yXUU@DRtLgf6e!Q_&-f8Q;G$BkR6)e9hBuu7!K0n2tI&K#-wmb-b8gMs%$o? z;&EBFQ&C9dX3t#w{7Y}&amTm!@7XuCrG+@f=BRMU1G?dmxdBt`>Fdi+Omy`QKlIr1 z$2)px!tL?aHZ=MCLAS>Pzz8*p6Ma2>@ z8nhIK(@9cu;T2bm2dn@6&=b+oRDHwLa4>?i@rPlx1Mqg>{mf%+jK%Ku?%1*K;isPM z=pCx5sR6LuULSFjZU{SF9)GC2t1l5t)>byQ9q;_(U;b6Ba0J4Y;8(c1j{FfZGibj* zT-T^~5Quk@$@GgaymsG@eo^7}1j9k6$LS0B888geoelU|R_68k1W%+m=0Oe%VJ)4} zolCRJDFu1uj@W227K;&Zz%=ARHqg>K1IYrOBO}8-J-zMir(h1`V*Co4fEB1RGi3aw zQ8qv;k*a;IVMzNF?MgpQDrV|11n3axkD1pHfD4Qe1wj1f#sC|{4HR8YET)Mf11qNs zb)+f^7j+RwXhq|pSle`EwOL;7_4#MbTjFrK=$z=evbqY<`$Li1#^$Q3ni(_ZJCQ<# z%i{^TT|TYY7VuR#$^zlA9^7#{^_F@_AF!frK$gw`YZRWI&_)hQC#Am{pMXgSYXl%= z7PX9~aq4u&NL9020Wk!y5FCRR87kxoj>qI5dp; zHcguyuANd@Rr&r8eg#}MHjkjme0XeOx}h&H|vUNIEsac)|`pl z`0H=J(b>^<^u)09JPCiw(nVlkZBWB?7wOSH&m+EJio*Hlj=!y8%~D5mlKA z?CKwX&7O*BLRBfWYz9TqL$Xjzbvnacz|nL%@xn7tb#|PZKX2}eGnd1}j?S)A?LCQD z-WY=kf(edf61rDwv8hyMf9=if4?p_Uqfb6Nq7^Ylj~{D0+16gj>1}BS74QYwHU@yI z=rKAtE?(>LAQO<)k$7b`nJe}Gc<(gTq zuEQ=OHPyagkO6ucGD=2VVYgR@Yv;_ISyNM`86&3~9EMANf2h8(1>h#2aN6x|rvpJJ z)9GD1cau+qf>mBmfOe6XlXyEEfeVDEp~_%>Y#d6ghmCwb{jV6LyqvgI`mS$>;5OWD zmls)+vQ^m2s%k4+X3p?nLAG-G_jq+v+U|1dwTSp=IuY}D^Z+AFgNsJ`QhT9<;h_#1 zEC6xnh%UerP}iK)+`^H=`%!d^AHz^sOk80@E||1(Gb936EA-rzxyL0%GI4`&&1~?; zp|!k>2oxZEGA1jd2;;5Hh|@?^QC`?#>fL@!%&{q0ThO zzf>w-7%w>hP=_NC9YNNZL?95x?WOgxcRd5=^#u?CgQ9Uv56rTja^WmJXlhUvDR)2} zx+9)7TteW)kHwPmbm0~Csep9=(N#55UVrVaAAau#WH_00^3dVECypQ5eA#6S7cL~r zZfR}x_=5}qq?4G8AZQbUu@yWPZG^*NoH~OfuXTF>eV5baBy9fPPapWe$3FLipWH8I zNNk#V7H{{r!Ga~r&V1yl7r*`eUwr3>Kkw=q#3#S>(w4^_d*RJ(JJzi` zGZG2!*tx$d62aT(wIjE_6F&K$npD%qlgUK*Px@s%8s`l2WjU6jS+#YD9qGNi9Gg-S zBe2O+I%Fx)_=Jso*@)CSjlmbPIgk>KbJ>V5#%rppuXyh@GiS~k9Ow@OecQM1dhWT` zpMLt~Y%YK0HCN7RVPQ z*?|t>&xG3(m?)Lk)-^&)aT%+uNeT#kQ7%UBf`?6!dOuw0F+n(10~DWgphbeuO!}+GNp#5yM&LNlWyxM zwKQ?hUtOq(+0qtMhikabq{P&gJ;QC&f(AB@Tk;Y3izbEbr4z^Yr!sM}M?AaN@24_A zcI3d0p}zjEQ*G!opo-rmas;VJ(aOslMJj^+@=Y;m50rATE>CY`~|GXU<== zc;3Q==WM><+Uu`B>+DT#S11`D>mN!Er<2)Y_R`DFyXlszFS+d8WGcOA!Q8d0*6iDR zcqAIbIU^Z;M@`d9<`&Up4lz!cYNTPkaiK%#4AkoEX$&=<`Tr?KN|F<*!f8v>CjVH) zIwJU<6e)V8Bf5p4yG*#>cp~w{V^96=H-C8br8l#=!t~j5%AC#(XP>ol)rv@Eq_(ck zXd_rXo-y~1xLzu(7rI>f4w_x-CwY80tbkpux)@h7oF%%I{_~&Qx8t2XEv?g+tz5Qf>7ws^|9e%{wMB+C=~cJVH~Ob(7tO~(7*%LqdM#F(kO3ttx9RJS@dPjik;_-CA^_32^lY3v5s#-5$y6eh zNu}UcE}K@IHAd)NVeX>ZvROUem`TKXJ5HqI(NuKAyj3N&#J3Z)a#bo3MK|ePuBH2= zJ}ns=&7@QLVlJ6ZLIg0EPG%4@<41vUL235W$;7C#JZNQfnN$+{nKGq`0Cr5v@dynW z0US?6hp8!J7#mBc)45ElzppEmCP+=-oJx7EfCG{I%cYZGH)dAIq$?)Iv$Tbm#H-z))0%Zrnh4 zuo9M&j1~(yMi={cIFYN3*_0*G3{`cSi zdG6U~5Fk+}yk)T91)USYB4=>HVaN1R)m553OcRVmhlhs;kRP!uq(masp&K*IaLg!yr2qRp)eez8pq}B#>bIs zu~6)2@9yd9qCQ^j30cfy1n@#7^TIUciP9wN^ zpn>65I0-$*`+M3ux=ywC_MnA;bk3}a1^>tdQpwzKU!T|S9UIF}6iVTsW9pQqiGtn) z%cWDmTq>?-70J#R~WCD zC^pvCq71lnyS^#G;W7Xb_?Fvw%Q85=C+6-^WM(<}qTk%TI%r#4Rq4gD_r zXK%g!{`-Cqw3QRTm{yxSpuIwM4e=8q?pSwgh+KA2Z@B}5rnl`5JRkp_%ujC zH^oq7=#o9FBa6xAoddecPvD{o1-IR~Z_nNbfAi~nu29O2*(>aiKm5oy?*96nU%TV3 zJ8wUA>Ug-SYR}$Xuf6o5L-S9X1^(}O^8f(<^hrcPR0i2;v#0aaJ8!u3cWzV3Am%mms80KMD%JVg#<`OxaN@o3Y}U-tRM-y z`yR8@p>)IiH5JUBwybO3EvJPkc-AZQ683l^p4zi#Uj?y)!aY4yaO~J|Mo4Hu)!v@I zy?gf`J9^~x*Izq&^vKEfQ-pVZpVqeV5X9T<1R{VJp^&74CYsPdeOMqz2c}aFazM8j z?OK?}I8t{sI#Pfon96wB+m2zBjkN`Qo$Bz5M+1 zUY`$MZ+Y$2WIS!xBJCO{MPtLe=;>*_N27_u z`wv2rutN{75ys|8j$2w9&N=VA{X6zm2Hcsf2WJC+a0@k6jcm`F)x3D=f?eCUpLfwk z3s)>_oYMTx)~!Gpoico{j|j%MYW2$1E6*Gmjn7}S;I41oUfa;{#_L-n)wSm1-d;cq zCd`;Uzqz$_;eyurGh6c`L)Tn;^_TCsbH?o1k39SkFpTiQ~sY z;qc1Ut6zKZ#s0nlLJAmX!6*emnjqcUMb=`pyrz+g@#XS={3c%))#19%63y>yo+^D)=}MklC)y~$~n2&ny`2xq3voIii@88c=taywizTOwq*dk-Ajxnuvn zJ^L=d_T~z^6B2`=N>Y%9sjbV`Y@9KB=FHaGg$w3+L-n!I_{0DC_nNaWxZ{HnF95y9)PZAs;_Jzec6 zTR2kN*f=E-Pwd>a9SkSZ&*m~5*X{HaS#LV8kSs@!7O+A?RwYR~i@KjUc`_PHdiS7`Bl&YRW&sEF(sj-~vOV zSX!hFK$cdJoZ*%*R<7KLiXy?8dRCzVnq890D@K!^PLNq-ckkL`zA>b*8IE$oy3jD) zmQJOk(RjX4B7=bz#!g5a2nK3uYi7@$+tuDdYe=jxR-|jjS=4f~xOeHk<%{STu%b8O z|Hdg(;UiKT=Rigg>;?AyDm?PLe)Lbk+6D|GL#4BW(!GwICa)U_tw z6eU^1vPMmTTKZyx24$_r!p#|t#i+{Uyqhj7o2aXAsB37bs;)1$*#lwU@Nm-YaV}f7 zxU0SQSbLk_AD%I5k;m(aMF*!g&79IYt7ZDExwB`WKI0DWv?)`Qqp{;BPi8WuX|op2 zTXaS~pV1=$fk4a5IaRe)KDRSVHdGxU^E!C=cy7#tZh3qmw6SIS+;C;2qQX9N0Bo3ucmCotn_B1i{Qfgnt_}tqbiRTS5-~W<8TpYzxn#M7hZa$v1JzOAE~MdgsKuF(dO2f(`U{Z zn<#l46H}WT;~DyLZQuIF{=>)o;Rb)WvPxl*Uk{~w-Lv$d_(7N3xBQG1Z*Sew*EgWF z#IVjNA)6!zvNThKbW&Fnh#7^Q8U#0Ol(^~fkvSsjX0ClWFAgvO+!{4rq1CIE`i zrJ2Ak!I#>Wdsa=;tJNqqQC-U<)PT-Q<*)@bO>GLJb;_zhF?CGfYz|u2(v7hf-Kpds z_DLV=m$PN^nq$&7OB`|6#w+``QaH?B098UheYvgB#Dg2)yX-?3_M( zzSHHNHhX@U{KZ+maNe|CTep4n%Xf#X!e?E4u`gITf8iMe{R5b;+v^?Z?F2VPo*9u* zSNfFmfH2}lkZbPZ<$b+fz$F#n2S|ken0H>Z&;b#m%j1oX4go-zOeh=yC4OgCHeiHt>7ojaF_nm&x#~>JcE^t0_+e_Mh&hY-`3sj2@Aq_dyS*O9t9F#& zdXSNmXhn}b$lV$-3H>Qln>}{{C$Zk%zJYi`FF3cEN1DlJ0a4w6B&cJ< zx&uOshC!A+n9lX7ZNFyXU9?0m%BuXKU@%NQJtwQr_#i<&bM7>s^kFDaNVJawN8Q=x zAlk;S)u6a=+W$bVIimXsh6$23r!1CPb@;^?2qy^`QP9z7Z2$hF&Weczi{@r?h5n%= z5lpd2I}@d`F|xKf3zvI*ejIr!mFPNoqSEI?mxe~-*{nR_&_EAKwl5H#K6_E?tOa(P zJrZd=aihbKkDuzj|0jPu ze5`xLh7B`j&cj^oHb>*sX>;bE;SYwi_^D<{C#7b%&7if$vsBI$i?MLk2L8;Zjq}v`A%`Q$i2o)_j35m5>z|LQa(?vP-7`hn()&Dm-E!rYYypK(w*8 zZpD&$<}H3LXyEnwK?cZEOl=l>)Ce3}?V2`;jj7X6-{^4IX^_@Hut{u^*2u|f42A(# zF}rGoZ86GHNb7_-q~$aCC;k{%F(*~53N+5IInI`t3eOx`%R@V=VETWTeO6D31I_%G zMH{RHq4I_NiIc~ufb+3XPXgc?LzzNlbF)%{r3;Fgf8Z!RDejM(&rfPW#aJqxq#XoB z1&choBh9hsDHd~}A?<2?AmfLnkfvDmxz?gq9UGPzvQ@`AqXwyIjx!d?#%`~xpHkm2 zmE0tq$pLHg7cOgRp1}}^$&DCL2CZkxf0dC4*rK~3p3wAZt(Uy#>UA5>@puB*HPrwz z$kp?QF0GIo9UTruYGCK=1qZTrO??<&9BIINkbeOm$@? zs9RmvoJ^(*1-%h~zSh(dt?RKNf(6Dzs1yo@1EK0tnSHFx79CAGT_N54i$_t$k&!_< z@LVUN0;oR$@wt0l7yIcxw4Y^oho zO^xe$Nj)V<*JIkOY ztD&iIk@Vb5-{}y>1sQ-Q!41k#$`=3;pFfxw9nPmxPKV3q4FE*>Y?{mP-mo`1GQg#9 zKU`f4mc?SjaGlX;A}JV#W9H5WIjT}U{=qs2=aiq*Yh1#Of-z zp-EXlFqc#4Vc?cOhMB--evDL>%k=tqnrn;vNyam&7$C=KsxwHfVmVRp`h4|`4Qn=@ z+uSmp*osqxR?^(ca7|5ZI9%!R_`FmyUkhc_=D9yT2W}z{vI++-y1#Fvy<;F0taRC& zqRkM4ami=sxfCr$1_PlopVu>^>2w;{;c}08kO?e?<*0@J8Qn3eq+-OOVr}!Qfd8($ z?quvv2BHn>u0XC@f~A=2-w~lKC%RC>=R+tWZ>vMFTP?6NBg~F6SRLWq1av z#x#Q-3A(bl=&EgKY@9MR9*=dkA48l+jvRV(+uJ*K?5(V6Bt+RYye=d`%n5Y=-@2RPs>hpzU z23qhtnoi}Pf99FjUwt(YuJ(sQ9I33T$)&S{1AU9mIJ2^{G7*dJ-Tv0`!^ivjhF*T@ z`Q1BrEIMONz#k+%M@~H*CuJGBgg_^$o<~to7?VTO%PdxS1&RsjFw#+8#q0Ml( z+U|4(f`J9IXTGuJt#mqGUDvRC``gi|;xF+~fscx{E#_OXkNH*t@-jEK@`>~?fo4r4 zJR7GpwXwdwIuLMWvdMftQ!Hf(#PO(rn&5_pEX+1KCJ~u}BPS}s(1mvvQ0k0sLRu9l z^vf~pl!eY5;kcUOj8OxQh+0)J^F^v{uGPG}qFL*i0S+=2qFq!?uN9Qr#_|Oq*6;Nb z12;4_ELpsCYW)<4+p}%!mYut{@7}ZLAOHC4o3C%p<}yvwW^-*g5{^el!%_mC3fwnu8zi>1tDMjniXL%WU5x!T;( z=RonJ6aE?hswra{VK_=w3JSGQt$7RPwoGds9f^l4YtCG=uDYhSG8}GcYCd}GSXXBU zYUyyfO?)rU3W4O!Km-hs?2Ob5wX$eZistFlnp&EwDkJgH;nDaAbpaD1|TbIRh*|Kaaseg5)CqXPl-OCg%5 zsjbr@?Ai1{U+3PPZ*_MKbaeDYqeCq-=CsV51Era4c6g`{yl85fkuMZUXx@17#X|=U zQ*+Obog*UyXRO|cMWN-iN+=NshRf}GS1%l?e(i-P2#`-5Kh@FJF@5IzX|v|z)XXx2 zS*OiDWonDtqwiP0^ZF~J!voMc(AOKTs%mJOhOz>vnPd`hZ=5=vQ|8%#Y=2kh@L-=m zR22wT1}keqm0|ohd63?^$>wIxnV&D@GTGdo?eFyU^gF!X(s*a_t8Z*sa>g3sbo$~f>JpERbhe*-^@Zm^okTL- z+ue>swM-Od$`Vxgg`4I9L-W*Op^zo0sj056t_p10xaP(iZoK&7%^NnXUbAl1^5sj{ zu3LNFIp?oldv+p`=sa~2zo)AVE+bk*h?LPHdPjM5+z1OfqAlu|VuZ&L>sN}+MP?oo zgSI4Y)v*+eqwE{wq&_h+3aj`OO=eT3rSM!xO=bCd1K%<_ZIu`GButsd7ohRlhWe(K zmQ*@5ckVp=#8~-wq^55A?0LF((>&c52*Q(j^A?>vaSU9mudf5c;C92*mgQ^K&zw7V z_Pho0WW2J9Qmap)lu9F#ySaOgYML)iiL1I{Bcmq#hdi7&4h(Q~`vRaOzKcyzm~G$$ zjPv;X;8-dig=EkVf6p+J@hIrbNC=0$eqx0JsXC3Y1Gh{NZBkCgOHbO=f7&(}2md%q zYw!_HR2nR{p|9E~sDdEW1M!-E1?4_}fEumS zTU%S20B;ynTVGun3Q;c-4zx_2GOf7@zexBub!uHW6iQ{1u#o}Q*VlSH?s>CXW3eRK z5Hw!^p#4dlFuEg{`M({FR=<#Or-@{(VksZh%wLEzf6NZlkdY`~;17o&TxmF)Vfk(gfX)`4E?ZyAK{qI75S;!+4hfY?C8lOZSX>YhZc64ATy$0J$za$z!T_0@$~S3 z`cmWcZfr@cp_mP89O_qOhz){cQ7f6zbQ#DVsi}bw>OfVs%mOUl^CL4uBxgHVJkItge?tIo5|Et$;8OuKq5Yhq5yoEbRw6_l#fqT*G#FY zpVH9SOw_4WtpcHRGL81zE9@A9nFqrR+;bN$t8Z+wJDj!kQ`Hg4buO1oB%;Fuk(x%R z;|OZqG;LP>lvX{FqlwFWWmPq90GE(Sr3taaRk*$JOge6Nd7K`7QV|#8bnDguOw$Zk zCN(n9U)#`BK~!dUWV5+B3zjyuP76h<8=I!hU%VV|hfGI?2jR?kX{`Iysr|e6FrupJ zx^yau-GRRlY_Zhhvnf(Gct!8Yx z4i1kDgTh{qeeK$HiCMx>^;c!*`^jY&-rp+c!lXEq98sgCe&JuCYo40`Y2#F&GpWi<;G(hVBkRGlS z!}R`AN81r0nuu5I2FA0+F4Uv%n3ZTnTQpncNvC2QMOy$$!UED`@GKArZ} z>o5UpM|-8*7r*?)8*aSz-1E;N;C8y~pZL@#FS+!hi!Qz}namK9e)@B_&73{`&eCO64;^lVTySW z2M$3imGNHSy+^5-yKzcgV?#qBnJqk3+4~TEpQ= zr=~}&H<8OhMzmg(DCLnJLsMyDyebl|uZfgTRHQPQ%1C7-5+=5HdtC4+7z~Y@r#&=7 zuBTGWa_AMdL_8V_g{MrJT2mY8?e05uvTNPOwF{RnT)b>)bxl=wSLd|ZGq1e*J!h;~ z-apWV&Rli%)e9HR>pay4D-B~9ntU@fFd%5Nw#}$5=r`$@&_VA$a|R`myYvR+)hEgc zFsX&_{Cf4v7YOJv#*$`~5{Z#~E^h(~I}vVG zO+AEXQwfsU%18~DU>NCS3?=gi0`NYkI|O?4Z%Rw6OiL4qMIu^^s8GxjpXhV84o56D zIy}^$&7{C+hCm}JqN+%>o|Q=_F`kS*`rst5goDVjSkTv4F*KXa9g7Z~d;TV3;eq}E zU3yb?Sa98=*Y-mZ%-nb z@puAQFq!L$RU5MLR9D9-;%@k3z*0)DzvlUKq-hxd2N?^-P0$N#bi@Fn)LJ(&RHXI> zp*Y4arx*x;09UDO9fTDafia&+KcN=PJp-wZIVH4p*j%u~sqc?rjpzwz+cJH|;w4K_ zVlsxKM-P%jR#jCG_V*4C54c?(%}pvT9&bN+Bve^VW5~Lvy9*A3AnolZdwM!i6$sG8 zW+t16#RmJk7=XrNUYRkJ=($u_EBL30QjxRxJhC5-V>FP&)u;+y!b^NTK8Aw_5nWz= zLVK)O%A}L10b@k{2*7dA$yl^hDq7Y)xy*@*po{(t*<3N3NcD7d96Nky%a+%MhDS)qlJR&dMRbybkC9;T1J_-C>4lr- z&YJb+JG)YH8=}QL-IeBFEIQhD;^14`whZ+SO>3-)R0gNFHfQpAug7z|t^HJc&qT$< z;zcu~(P%oA9UK@gP8YsVRYEr~5J?l;|pWn56&xFH{7Slp&Q`7n9Z4CI_b7s#Z zqz{Jz7hkYxT64|x>CGdfu|y&{GBT9cmmz3D{*A$7=ja6i=8DA&F1+yU>gt+P?VW4Z zuAVz@*3_vDEiFwRmuJb6Wj>!Tl}bWF^R(%D2F0mwzz{v*e5N)vH8$3@9Xrw8-E-3| zA6U3>0c4(c-uVu<{gO*BCbRMS+*iHl8U}sAx#!l_L}tyJ^U5nP*>xvT!7S!vaX=$A zg>A<2e>>(B9N-X&%^pE0xP(o)%(q%Yp(?@zzdwjwk)X#%qV@`KHkU~fXx9RcL>dHQ zV`T+Hj25?~eL~$di9jMz8q1fNDRlS%MiYQfl(00-d5o3m?wJV{#`T(RDhYy{`@&-& z8*ySHHez==rp=m57@}7*%OMi6ov(H~# z2EXVZ-ky*=7_JP2^aLfsNrU?F7>)x!;`3M1X>?>bos0vU(cwY8kDty8GO8PhpowLS zlTy+K7H3jf#{czi+_meSU46X+c01V|Zl(xdHB$2g42&)0ve&)umUU~_cAYrTI&Ie8 z?QdZ8^$qp7Rj=Dk0#nz}(9+u4*fbS&9qjM%di;KmJC})_xB23MzW%oMb{sLPh{6g0 zY1F*xjlzPd^n~l+R}r5z&1xXhh?Fu8vHal((1UQh47KarV%d6-_?HH>kle@sjk<{TIQu~nXH-bGEP@d zXaUKRuQ!0sq>@p>JMdpK7!x?cG?2=Oe1RaQhfK*pHL2`&qXhWTTsjTEgyMj;dHhif z5ij%~9H0j})$q;4BnKF^#Yq@waYK=ixxGOp6x=YD+7lOEa&bD1>6ZxAPaHoHsth|F z-iC&zuHK%aFPkfvn`k7aTDjCb1*|*a zkYqZV@CTfqy7iXkDNS|NHE(U*J~TQi@2I?d%#Pky=n*|VOqdOCl8y z`2EA9!@)p^q`$AP2UQR0`|okGU`PU|2zgtlO{=S~I&|P*`>9jwHmpT@ef>R6O)Z6D zk(U4G-fwMv{q5t&k9VCswe#)mvlq-Cn<%{U;>++#BQ$J*6%fx3ztCn(Os8~GQ|VF~ z3TDX>bQ-WQVMWUAQARd0G@{AhaeYJc86zlWGJ0V zlcMDd>4Dx(g5p#%7aNJ@^Eh>!K!sf&-f)2%Vs)`pVHYtubS#qu^b3Ww%k9WyVq@dk zU?7l)k7P1Yr%T3=PNsDKrrd^#=Q3$JO(sU5sJUf20kGyTLZODn=3FjCkOU0q!EZ*T z1t;BJpC=p%B&d4vDn$?o`ZfA@xJl{W2AdvP(|5zRaJx@hlhGOHfQeqit*x#m22O5{Y5=?Z$bu3 zg3@o~Xg3SjN>^n7pa(>3$3OeoL^7I)Ci{B2hKC0F`+7!(`iJ`aJ3CGe z^tU%QG-3phyKLDRd-iOttgZ@%{h@HEp`p?3a<;TipErMTPgh$w7$g#CnKotitl6)< z{9MP$QK%DTN;pk0dxN=^(G*Gq#%EeE4iPd0C)Xm(LjxJMh4i+gdDKSUK4grE`} zVH2`kNKCK0;k|{@*uet_|McL4R9LxY_0!M1uzmZ^BZu~p2j21ZZ|>i>_o09N z#a0359l3n=j5C)L${g5#D4ovwd|o3H@)gGF#0-sa*wm-Pz+l3ba6ArZm(Jk3^51>OOv=ec7`4Pd)weOE0}1jg8KpGo7fmIub#& zM~|N*eGLRq_~3%s)B6U7$qxcPL5D#Jd2V>Xu685=O9_P}s(=a=wY;Zlhze88iWG`r zVGX-F4Hp3yJ(Q~FSox1a_=$2W+Z~Sn_78v3vjr&2`1qpv^RBpTvm(@dVgG?6b7nN3 zJbujXtSC)P^z_9}o@&pe(pWpxAU}~L52ru5bi(PZsHzIyU*u`%kU7* zC?Y(Yjmz=Fs1xBNTHDgnvhl35=FOY_+|y6L`pT9&?!3LBzGi4>@Wk=QjLIQuh1!+ zHG6OpOwlZrUYZI5OmGChjPR4UccaWWVTHcoBEW`Gip+hd3+jE;_w4G{mn^Y-iH)j0JVKk>ix)B; z5?dM}O2R&|oROg+r&|lM$PJDu)qpCmS2r6IdW5^&=S9yZ*j98{ZX-ZYut2C{f*p664yezfhx3DQ-BP8~A`BW4zIh4~BTyziEe{{6xGF1zx&@=_key!OVM9ky{C z9nFJR`;HYwe(~~E3#4lYzDu$y5ILK)|7@!-~nh9jfz%&-lrZ`!y>9v~b$P-UK z{=l#Q@RtYwfCsOXVzD@Ktu>DMu2z%pi3(ZqB3qh@IW0vmVN7P zmQhd{0Y}6ib4b=DpfPqaKCUfw8i5R?OmuISKAEy<(>b$dH$VQ+!>_!w|{|D*1!XIdkT70Sy9hT!v2QI&r@Y!VU3y6ov{k zt}gVTk=P15>}FD!#E@UWEt|=e#`9h;AqE*r$$Z0Z!s&G6vbyIxR+32rf*zvsN#&Q@ zpbiptIUVwZx<$#aJ~5I`r=S%WC1CWklih=BWt~A&`=yK~FGa4D6D2|uQi*QM)P`LA( z|GV|&mkQbVRoA@tiNF43-FfHCnb}&%=F~j;1ePgfw^ukdB9s9?QQz1!f6`2BQwRqO=={TDz=g?qsfL~Kn0YEj|_2`NLJH{3apBZlo|+t z;b@$aiy4aM#O;huBjtb@AB1VV+A{4Dy=oDRaU2TnMeH&w)!MYaqjbZol_~Yn(@ZwI zYSji(u{U0S>DEtt>W$Z4>*?+ag(LK($wDyH2+!s6Aue*H1&bHYnmwNwqO-lbr?ZQ$ z09-f{3RhRv)RVP%{XzPLEG<2g&ryM}1M&e@{3+wInbi@2SNQDIGunQPiOP%&7e$6d zokVn4BP-Vei?F8vDOs`>MH1yMr!NpjyE5qn`eWS{Fh(J)pf6-Eb{WrR7@}Degk?A* z_=$Wew_?RAjx;y7tY5e0u_vC|vulq(=%+hI4LKMQ zq#B#TNf!}^MH~Eq+f_9+*yyS=&zwJJPJjQ<&fR;vdiw0h+4>Hy`G6i#Q9M5EV)))L znrwI2^7%|Cx`Lk4SiV>o=o|jiU;jR4JQ%fG8mFGKY5nj2_{RyG z6PYyC*Ijn`d6kt_1ia5a^Yq#cXSKDRA}@deG$zqhHWdDZGw^XJca?7#ng_UV_dz2Um7F>AI zWe&URm2342wkNkvShm!{2d3RaAFvebkVSw%W01b*`!GbFfvdVrUkW5 zujn7=!6o`Kz&%bE>X>L0$c7q|K(WE4NC#T%P6r#X5YdTgjLW=6!7!+XDN5}X?D(_k z47eW%Rh6`mxrm`PXhTP=IGrw_p{b?i%$2L2fBNxaNnOAwMqz0)WJ3(w7QvP;WC$9g zRveb`!(IMo2on|fn6g4Hzi`2#tKWOmZ}0o|)z@BMQyo0M|In(l&T-q&NVdZCxo9)}SeCQ*$zPWX4UvD39z%c2RQPLvP0yZ<5=oi0w z=e5_pFPTg_UG{h^_Jz-W;@FWkn*-#Qs6&w&#*$9OtyfMMv>0ogE3zx%hQ}xL-i^ba z&!mt$8bc((!Av?Xn6wiwYatl3#+$l!c{Kf_DXC1#_!#+FPbh5W8B(wU_Mm~V480Ps z%pk=CROR$G2bH&22ZcVgEP8Z9TuVop8*}Eo9!n}{g;r_xgr1{_C!&UIO*J@O9>Y}h zt3-~6{wCwm58nF0%F3F5{^P%8wz7o_7Y9Qje8Pr}8+Pp2_2$-XNQ|q*8uJl&>7hib zCP*bYDv^v&Fi5x89Sj9GZrJGecn=>vJ}@#GPo>=zF0d6x0^y`$5{m9FlqnlC@1y36 zS&zpxt#!(Em!5avU^^aqdTS#dl}<#eei^JFRmuh*OtFkYMOq?vDE%^HBTm%v1=iL4 z!)Uc<4nQ>FYfdjnDD#CZ{vR41`Q7jTT&mFQGS@IdHHqPg#agtGUOZk;A|Atr175#b zfy_rBhG!N{hDr-ojCrdVl~!{cr=Wbs0@MSfa~wf>Nmnb%hX?z89(TAh@R5(+`t)Ou zJ^9$P9>0_8NKVl?F4Frh#oV~o{F(@c!bEU-ip6}Z25!<9z0$_v>GKloE2q zWSd-qEMW`d0@3ohoSvpO8cbW0R!wVQMM(|-1(i;e6BOq$8rW?)D4K&;#KQcdYl7wS zTw`PFKri8&Vq2%fg%2R;85=Loo;T~(kAJ+Ou|6J+J#haocfPaN;|alR*{Zo?u3?tt z#>R5XmM_2L^2=7PTGiJx{JBqjBA-|E2mO|;p@*RuUWrO$lfbTCLS+|5iA!8ySWQ?z zQLap!;O)KdeZRA!JT=<4X6?GfXy4N1D-$tLfHCS(&|;o;^r?M8n_e-JZ_v8C6J_(} zEuA)J_TIhktXRIjP#kMN+4;fu-w?%g>27SYCS6G6C~dJ|T$&!#C#)k%w1CgT4#Q-z zmGNRc5-YS;kQ|gO_23BA&^p-5HXBO1%%XA5GA$#JP9@o<3x{2bhm9Li2x!K}3vgOX zaXOsoYaoWf z8k+w0_kTY4n_vC>XFu}>BBerJ?K&KU$HPU+;AJ13By>lP))}sxur=*XD5p;`B%zfXApR9qKHjlg=97 zz#l~yvNg+{%fBKr1Wtm*2`BNjd6r6fE?0uHW8-$V3?#uvlkU3%`m{hj2I(^?xWCP)NA84cw0t)@v9i2zf?Qyn!YDAu+Jl@VF>Cy!gjv|{~J z;S{VvKTI7(pqy9CWa0=+9cGT6;3BQ9*d18(@A$ANWwCE?gDr%L{PS@g^Ixr zw$WoioWenq{+YjcHk&P68NtIi?e?zDllykPH8{|Fs_kfBcb7ztZA=u(>=gtf6BT6z zeL!)7tjFo`yZix9z>g&XUcpc$UXk1xnnkV|3OqqCt$`Z$nS09efyhP&+2F^(im;dh zr{E>K7S>pGOf@wtYeO$8CZ^47{lR@d`SfjHx%Cqt|Lo^J*VEle=)py%rU8z!vf1-z z-}I3WS5Z@s+RLa~GUZ zJC=mRd{J=z#h2W7|1Ya+>T4UTzklC-U-kB*uuwr`S!0Px&Qp@AE`|2 zJKz6qAmG*gB_W9xHJ>QYvQbr2{gYoj@PqsA+jP#R-8*-@|GH~(IVr0~H%`}+j~K%# ziwS1#SO8>3CyF=^C#@k+91c$zCZ_vL_61AN=5WTQK%^7})2 zIiejg{8O3qNGvf@8aMayXkFH!C7_{(Bj{(j!=BBi z-g)b-Pk-j~fBok}KfV8#eFJ^ZJ@>RX5TIYh;80a6C8MMC2vukZTBz@0=)OV*9^gxe z%d+XDnI$0L^Pz_zGU^D^J%samhBAdNg9_e22>R2hL?#tiEU&z$j0_J4LtqPyv`&uC zF8RCWoy9X@YPrirm_xv}3w(E*A*{-k?~f^-IiC z^9HgGU21uV*U3Jyn_kQz(x4!>7|MOjP-ef8%&^KL} zLQH3GJ8>xBcR%>2-~Q^sUoKm|=pTRii%B}vm1$1}N$lLdW1^z;$G<=L$G`lwGF1KD zd%q#QCk8Zy+Ay@fp|P>C{(Im0-hcl7*j-<{b8ujI#;jQ+CL(HL3^tN{=vC(N2`or) zOvMCt2E&UbeUX&j42J|>v@FZf?Wx3#x4d`y%$b=~8j!Sx$a(Y6ig3v~Q3HLA%{(`4 zuWy{fe@L;pb(YZ?_$NC@%m|2Kkum|h6M7)a0Llb*?bO7_#6(q-5z&!O|{?W zGmoH~X<(eR?!D%KiAbadi$|Z)L!2vkWO$}!YlIq7DBb#0$gGjre8Dg{W!P0hm{6|T z|BvSLizbr=7Ye!F?simy8YrDq!e|6KrV$&tpq9|Bj5C+733kU<+;BPt^gUJ@)!aLYh$Yso8eel7FO~Uzj zR4WZZlrInh5g8ipToN$v_@G7Qc!XTOtWW@pqz@pCoGbb-&0vp?M4|p#{FcfX;p&K% zIMAI5QZY=M@CaRSircg3q$1t9^(7~uU3WvF z4#0fIn4N`vZZFjj#g#33t?l5;>Znk*bdYcE4^xe0m6NJ@}f(CsT5>?9G%2TQ2(7-@tWhfjD96xcax2K;-1dhQ)i?zD{0Ft_# zU%CCZ`+xD%Z-3{9)22_Ws)~>&QGr3Bp!hAX-;+v3KlY&y-}=E%KKaPAbLTGpA7HD&hwRq8@ z3okfl^ZDnjUAbc2>Q(2Qwc(PBFUqAx>E4YMjcfhpaf9{Lw-i9)m4Ing^Ca=aXd*UZ zJ+4H%0#g%iS?o2V=8!xs(t)KwSeB?ziXm7PZE8&#Ez_Pl2p_wy&5XZWyoHipTSqvR-b+TMJ>~2w=_@XcpwlA z2E(CBy{A}HS6@?Guf56$2Q9dy0{>htLNUDnmyE|Ssg8~w2#|yrH?l+efVa6r#qcmI zdY5rQvyljgg|;>uu*)_CSv8@@x?l4DUl5hpLTlzZS?Xh@`d=q-r~0w%N2kPGbKG!< z7+QeE2E5=mm(B0qvyc4G5`r3*sVIe%ZkoPypMjGo_rw_XQ(M=-c%@~71JpI>sS6pi zq6@Qd4vm0QD(Ly?VHl=}b`BB25cAS1Ro!mq`VH$3A3SjI&>=X2(i;#|N(ecsFEG+* ztjo=&3LB=5?(ImExXv)nI%U)mc596Vp{#67mcZb3m8uw=1Z{QPVv_dxLHlWkGJWQp zj`pr!{_JNjKL6T+MGH5q-}vx<{tfZgS%wK4o0^;MxZ|GPyLLYH%;V>syP1INoo#QS z?oux!6~oc;v(G#G`WtWf@el6%?F08;u=(QE>()Q>qyU>K7p4;3pZ zTF^q-D6mUIBz;qwr_m&4gGOMGk3RfRPhZD(|Mz_yMsCD`kSI3^a|o~40f3BVn5jnjgEFKm-NuQUSe2USGn~>T zr=LlH3=4paq)gi?W7V|{sbr#YYU|XgQ%ZhrJ*yXeM$A^BszNXeOgo4oW10Zhrs)P={d<<`eXx z((*6-?{E^x>#1RBUK#FNE{Bdh9+w?3b0azqx%dP0o6|HXG_pIit{}A)SnCs$RKXdj zhH(;{VP7}jV7qzZ2V^;@>Um&L}wYm^}1uA#1zq?z_~t(rQ&T*h=I4@QZ~*qXnI4 z8OgS`DdvO<+xW`u+xNzmrtyyDDN#9}9o9X)pZ1khk2d@ZGF ziU5%-iQ@F|t;w3zm1$n54Pr7vb6mPkp;L}q8|Hw>(6}K}2hDNAH@0+*H9YHbF_u6> zcT+X{l@p0xjX@bW$H9pD&@~uc}DxGjt72ze=-?+>E$N}`g#ZY2Q^aDuj;`#ha;1Y;+4s@ zwr}6z@wwNoUHk8U{#h(Nox-z?I=bBsP&-^nKIne!)z^0K*h})Lk(!2df4@`+MM6Km z?-$K2t%Lpjt5z>>Y-oJ^u}45>s~vu*N!RcSFLUfzTQ-}2`tis5`vyH8bC1}Fz+#vA zg#d#@*l0!hhO;*fc6ZH~23(FcHa3oo3?-r?%}_XO z&c@d1+SfD)vF-RXk3TUuI{cn%uYURYSE1qH!F`?W9VCDqZO2fU;nCsct5=_Q;pWfX z_Qj#W;ZvvD$TT4bi9nK(nDh+_L2-7i0wkCb%6h0I7)7BCA;5(d0f1|aQQ|jzV-u2S zhY)OPQ;RZL#eAj8NcDIr_m@9ESehs;Ua{=zYp%ZThWEer`qpFuMANhM3P_}5y6s8C zaR0A=TUlHA$xnQI&)z-PU;nJ3e`YZ$m6_b0G!TLB4%cdrP5%WwRTrJskgd8IzYMHR*}|ojb^+K-G(Jn zRlkaJpjYY0X)rS`M<+Bbu5GweR-pwMm2v7EHEd1^OWS~Wg&rCs^Oi~J*+C~Pg-!^@ z4As6QfL~KYm(OO_pM7>XT=mYj?cn@^WlI1Iy=w0d?Ay05mB}txwD{ajXA^h#_4O0Q z%lAVS;UHo#i3{5}3B0$e=Cz813T@L7WLw)-F(cCPcXy%0QY?Ns09B}hbrz;FH2#VU zLK6eHv@pqZw9F1-di4B5==QIDxxcUH$3Og@+vibDQ>f11am)Ht7Ac-9@ZxhX-u!{9 z6NypLW~4?nD8zJXYwFM2v}yf@jc2Y{J+;2+*pVY}p1v(=O-;=z&6+d+L$`k9JKz7| zFMj>okKFpPS6_Znifcw{74g_Me)ETJI<)t|-M8QV)|S`rxc$zSmg#xj&{t=WZmD~u zIuHu_Kl8~?eEu`Heet%hOlz4|Q(c8@4aYQg4Z+MmeD4Q8oi}$uq$;8>?VEc?rYnio z3{%|DU={IMb|nqO(yZ@{;fTq3&2X>{8OFP}2X#<3gJmh}q)B!;YBW+MNBowEBVXJS zO48llR#zFUtqhIy_4xylv5B$|-13nNF4}y-1)C4<-}S9~zZEi{gh3%?@W#8t5{LnS z=#7lmYL-(%Qc(4DSC(cn3{BUW!a)GSQhToDEEdVIxt8J&h7<89FxTC6^1$AGvu4k} z=iB%E^0yCc*s$(zfBj=DHtNvBZPs%?R%<5CaM&V|z}44WIXE!*;~#u)yjW;$o?0yE z>vn{DP(ep12C9V@0#iXiV2i9D^CJ!hh)%aJ7;<~O<^@7M zG6m6Kk3KvzF`m?--THDk6&Q%7R!qU%@_PGD)1ySqWcs;mI-kpAGy3u-|Jcsu()38K zkV%_QzhrYH4eX{fNiIOXT$$wnadIL$Hdgq;mp=2|@80vxZ{PL44_vq5tabN(`<}0S z^^Pxm@$)lg&%ElI_k87!JFdI&CfE%y)) z*Hl)8slW(Vuib!8$ZD2HFCcKa+_6bR=$=lr9CHCcBn&Lsh&-L>jV%-jH?_99yd*5f zZ0&ZhKS5qK&GoL?u;|AO^x;$^u z!jFCWlVCf=8l6Zmfiu4xp|GuC8pE=bjNxN_lA5{1m_3weu29|u)`@={GXBccV9)Re zgQ2|JKwdyB7|JDEg@PB{*m*0Q)`#-}; zpo?mcc13J?Azz5cW3%T>|LM=}`|*$Od+>LEz4w29OejX*7R?rtQW~c=?LWNdMKKAh+{Lhbkfgm9u)vQ9NUaz+@9QoxBf4=qkoxlFcPdnRB&YU@CV%&fQBx!U? zqRo52jvH>g?)I;K@tSL{aS9r#qeeJuluF7&STSqXbYIYM@g>wQJX(JaHWJ zw=~>pfVM5d7>PA}z{@&o9kF_1Ac`5Nh|!scI*7ASR`eHVZ}CJIoA`^kXJDYWkjoKo z>Cq1Jb=Z5p@tw=gyUgu!^bhtw{`h~DrWl}C>*9}GIMGESnt0%WUk(k796Eet)A<** zwRb%6>0++PU+cZO=UU@UMRL)4rbW(c!_i&$NDtk_^2vBKIy{s~XL@^jMxr!c80s6?xqT1nSW_J#r5NZR zIMH^hy`yu%yjg%R_2 zhQ^vpFTOAs@PEu4}AmXsmB;YU%6kMsI2xra-gPp>$+qXb{V9oz_}aRoRX{o;-HR6_*5q!GZq1 zRV!Df<7xcg)z@9s)G}quYp;U^U-{Y>XV0Df*dzY|*%+5mZfS|dAgfIBP6fGQjhs~l zYKj9orz2dXZNsJiyV$g;2Fi6O9oei~yZZcd&uM9DZmg@jVDp95HT7HHe9fr`%VlBa z(u$e0XD?Z@_?72g?(go0X~zy9J$PWhm3U$)R`+P@;-yRN70wTT@I#M2^zh&Q`sbIP ze+fPk!5O?$5N(LGEnd3hj5C&?+5jTyv&Zd5MmP~=cgE#HG8%uym6vV4_=5Mo@9K*$ zzkKfedCxuj+^JJ1oqD%QW0&buwPK>NVamp{H%*_>n#rbj?A){E)h)$|0*Gxui3&nY zoYwW%UpHso+&OdSv`(L~aPh+4p03f+xZKbruPo}sAhB^`%;j{RxB23}u8yWDQ;}p% zedBOHsH885czhvZFJqco%rsb8aT~Suy^9JghT1fHn&omm3B_4m|iC8YV zYu8(&1EUvRv>ALM&~kd*PdxF&V-NlNz}`b`$BysX@y;8szxLp7e=(+;X$T$Rf+|Qs z3V>v3jSU(M1Vf-FoS)#_(HdxnG{MnaCg0fDP*q*`#V>y0Lm&P4-aWff z7(E9ng_PT-56p*-l*N~o32o`irA1Wrh_$)3$jFH1$Ogbuh=d_-ePqQEj}8Ma>Qt^> zpYo>nRDANS1dlI3z?e?OX|sgOEw7-0;e#f=j2hCgbq7cgPLCXe3>{@xUorrxvbilS&9Ovc=dL|-=FEyzRYfW*$0o+k zJ!ch=1c#5G?82=Rk+__ihFmmvR#y+{kzetwiO*!d0thxOy-?APG(r3_;jAgDYV?C2 zV-41xYFU*K3DtBlfeil2pa@&kk*?|KV!Lg;f^d|W`V`Sx$EmULqSxb|HEp`1tkh5) zT)t#(O~gOY*NgF>!3LwX5H*H`W}szur}vD7^Uptb&F0N#SJi|=A-~&c!|jIx0n{+y z@%b34OIph%TunPLRn#jIk-B4ss5PV(OL>Gx5`$k@xn@-^n+k=((`L4gjz(X2{^eY* zU^!+~R_?|WHYggiiP3NahEw#cBUG?{Cpl%oC_^_hj2uuaVwZNbp?YE(?L7VX6DNg^wn#$p5=w7@CVG5_H1$k0F}7@0k7TEOSN|5rcz!dJeiwFeNJ z(E~J&dRSC4o9`bQdi}N6-q`ZmPk;8a-Fx1)Ig}7t%z!}{c6VF<Y}l6#VcC6MOZdbo=QYX3S~AXKx11;kFA_|pEgK#Ot@rXWW(`-UR2Xp3BCT1FBqwe z)OZM%oNj`ruC8vo%YES`7hinoWwU0_UAzA5%dfoFObE!~K$K+<6gC(&lmRQja6~MX zXjBOeq5C19Xt)nrX9IG;LOBUfS}Fqj|}&Z{_XdF|M-VK{PJtB zZP>7}I$WjiHR~w_y%>fMG3}R!DkFE^{jGxs4<(a@S6+VU;~)R{`n6{Po&>Gx&p1ed znjrudK_(dhaHG5V`3ySAuG8g3_XuNQDFuYpOVxUL+T7JHn{YTiK7WugW>bo4@mIc} z*54rCM+e|44I1~R*Ck4zwH4Bu_??18WV!lQG+TMe#Dq=euO%V{Qe0*@W@Z9qK5}Nj zRVW-JCVlCd7r*hfuMPI~V%u+R-S+&`PqrO9_|%h6{rtWkv`%kbuz0!6OnK*X1)?`u zqxn!6!%3wRkOZu=4NIUwPaTg`35Vv+p4s1{XVR%5h1M5#i`iTTy5$ur zoK;ofv(8?A;W-<^K3_Iha5&sAyzu7V|M^fN9*aj4XjdTM_xpTWKA@zRu;>N)amp|O z{upZ#Cp9Wh3Unc3=s5*Tf(62eq;uVb`hl?swkV z|JtkD((z)m z1`9)BrK!UKvC`<4-Z~Wz`8~}93Kyy&POxJbVw&NwRNChc)z(%wHtGYbo!uQvmM(GF z$&QT=G_qj`{r#Pxu?4LaF%Wy=?BXL%uRS|ppdxsjPHr?{kkKXj5 zn?LgLkFQ<728%N%jU3G{t-bu*(>GrAo|~`zz(+rD>xbTV)7`g!1>`m2(*K5bte`MB zFfeV#tZ;SRi!Z!<-w*B^9g5q{jX@exHNvH0p>gVzuYT=o`}gkr@8AA0v$f^NKe?|m zQi<`H-c)FcQ97NT+PcQyJn+Dt-TS`#oo^mIaB%MI1>`4&D-;NuY!hwg7uGO3f=wwf zS)>lD&>*I7Y`_NAx!gWF!U<1ES9O*8)g3(WPN6-AIF4)2>WOj3c)`)wFx4Lb-<5)( z&^~|I?FtPK4Xs$YysNW)%WJP4I&_c_4<;}Q2~sVn5i=HTKz4s$xA7Xh$EDjiFLYxLra-3GdyKtli&{?u{MSXn(aFoks&fc`{FMt2j@BZ}rvo~xY zW_Fdk%?CVal(zJ64yXYMSVbzA{O_axs<7Ms{m;Mk_w}~6v;q?JN6UpmR`>gGt`mfB zK&swk1N6aDa8Pd_==QynQGk7LADjYnxx$*GQ%}U3a!7u9%%qYG4?pDb2GB6V9iS3c z5afEj0Z7YdvvkVPpwqBIMuGjJO43h}Z}HILr z%MQYhqlXVw*fbsV`fG3Q*s-&!rv82JyYZ8s`4Rzj=gCvBkuKmifKIKt+h6|r9e@7&zx2^2bLRjcBA@ek zydWvsWj+Gt8;&Ip9_|<>z!@4zB$Az7eZ#{eE{A(`DD|&@J@eEvTMi#S)z{aLYfESJ zda7kU02gAlbil+>V61jDWWxuFIj6#a8M*DAZ+zq3qm#;FKK5cAv3_aE+GY= zjWVIMSh-fr%;m7R*|X==)zuu_zrXFo$;}sCv~|m?zxw&lMn~csH=P@)irn+{uXgqH zTy)8$Z*SXPVRx)papub}yol4aaMg@!aza+)GH%M6>VhB8&9623No}%zsCb$`mNl|% z@z^wF>I)bruDSM_&i1w^9)0*TpZ(m*)vJbvh8}z5aUh_AxZl*HRTBJ7XP@=RfB*UZ zn?5ji;rs>j<~{W9hsl1h2Q@Fk#(;&|`l|2!@AuZNTNO)0YisJVnH)p5I7xFBVWnbe z-Ntoaz3b~|pL^bU7hZVjJ^sie>1>udoYe}E#*qAh zz-K>u+qP|6KK+@`9^A9%?6c0{_|~m&=y3&$WrjA1+l&{#OZvEG{f5!u!726iPE8jy z4D@!xGTbkw4h{lsAO-L(4`HTOfPzGn;N9tU`x=^CiKA#A3I_W6ANudVK|80z!U;%!^Eojlb>G%goZVJnu#DR@452qbIuBeyw~4w-Gcdx z?*IAEP<%LsOM3U-m$H6f-Q)A>Gh7)xtp&+;2SK*xit|}GuU!CGi*lvlCPx?)Kny35 z0aT3@@^*9E9TZL{6P4Aqia<*xmq)LlWV3q4OOF`qCWc+L;t6Ps8 zKUJD2-?e8SnSjk${aQUnRT2E3L1u}NFD_n)(K;;Bp%B1uvbt3oz{XqnS%$93=Bt& z=9G^{qt871(wlGY*mvM?Dp%|s==1qKQ>HXI-5z5#axyev=EZd@nYgBcl;7t+ajK&< zhRwM7=XU$cZLWL~zX{UFE!oZYmeDyhT7T#_lLn;I>D1up@Z(QDzUSb9K)4QyySq*i z&z@-Odg;YifBCbYp*~&h?Z5o_Pqi48%wf{{b81OYP!7j|> zkTg=WV;0B6EB?s+pu$u_K4oR#`|9-@_w7CWt$V*kxPzKmhRSKI)VeI4$vT~0e88Pw zyJ!CFc>$k~j*V`}R|@&L(q=n#>iCzw__<#`aQ~-1@{up!_W8g4`419~5s8f6+>L>- z?(QxUghHwCpMU=APk(su)mL8EOFQt+q&$W!MmO&AR@61t_9Nsd z>ZDU~x5t-=Yq{uSNA|`OBZTH&zdH~J3=WP`(G&0jKt)c-E#bfB6gh_Ut1@#^s;`mUE{Og{YcpC{M;m5tF%lu2B>TX+c;jnY&ns z9;&b~21AEhyFho(CsL^d($&gjz5pZBqTLf?(b1v2S)3E;fUpGM2n)+I^Lt8~(Q9Sq zXt<^X=vGe-zzpn{ZA~_5ITQ1?T|SpeC$oh@G(M67;-#FN$Ha>h<+iP_zuMh-QWHVr zWqrMa+uwRSpViC*Y}vhg_w&y@*Kx9g=s}Oz+U%seNV30oV036GQeDFlr_zb#5m&f`^wE?0^rhDo^k_EV1FT9}#cG9;IFxKQ%lH^DGzobjT_|YmO5uMchFOiBHB!%X~3t8H9Bd&F*k|G#A8s%|7>uUZMKBSrvqH84h6k5wS>rp{8(3a zr_1XGiledk)~)Y6@z{SyN22Dr2rdv<(@$)4)a`Rs*Hpg!=9?$lPU4ZbzVW(xK+d#k zy1)UFcrIPGjO4GOp(&+6jLbz-RGc+52plN`eO)_u?%1(?*9*@-OME&sGD`A?v@OSG z5jH+i_}&kGboJHOo@_hu!|#3nSHJirhKOmIcFc&BwM^93)UMvJ4(rNgGx2EZMS|aV z-ahS~)hSTL9;UVF{Bt*N-t71LR<2z)wYlZ-#~wd+}j&oo!D&^Z3}9 z!{sOs`rRwntP2LUBx|8i+WPt{(UIX#efqXP{qBJyhYxjib`Wbn`sfoFkWp%pL^oIi zeL)~y>!<-%>8IdcU+WszC)v$f3{+MQjt&Ka;XS+dJpK6NIlYFU)}#s;44$d1j1+$3rn4he)gQX~hSh7<`#heV zJNIg07aTB3i>X`DfO(s|l+*X{i8b{k=olzwCQlI%d7i`R<}BBWF04ivB8lM1*f%Kb zCrHVeHxAf^y&kWZh*bz{<_#Dl-N7FOPS>>q)uc&{Pv9SDfu`t@UKp3TkmP_f9@xrwkPNC#8@WvS+|3vE_YJ-C=C;bJ%A-g3 z;@D7$n(FFYE)S{ze0|+r!$W^RcBX6A|B@; zRVls`2gx6t;Dd0a>o+mp_m~U#ctfR>4P_aIFn7^{`EW7ZrHGA_x5x; z3-=Klbs*1Fo@hVW{)?af;#QUvwT@Z*Sf9>-!&g;koBL zK0PsRRkI3gC>F;$J3DfP>_ZPd^w&TCxw^jQz`ldDPgsE!(V9h_!7_m;s)QR}zwzw8 zo{pA=DPUS%ZR1dHH$z2dO#iCPKl<_pLPUk=2fCe2YdKWX+s5W;V425brVEDp9)02= zTY1_4{@}g}SJ{a+{ny^nH83y|4EScuoa=Phmo8tHNF*-3> z=L;{t@;#{R@BjFl{@%V{{q(2tM9S&)nY-8w6-gKHd<3DPQ1BPO`qh8_@sF*qzC{9i z=hyB$aq{?~g9iXeMURCdu?Xl1NI?-60uAgMkE>TyNz0{|OeqGk7hC{?9K{6Py?=|JteY6ZP+G8VZ_F?O*UpYMX$7= z$pp;Ire}-gX)J7(k`Nxbf`Je`;)tm%&EY?TLw4if2vE|U@K2|PNetgc3! zEmND|Rw9{%^^mCt6UUIF-u1wbfE;6HZCPjr)Eux<54hNuE|}HTJ3yX<+oTg~?3Qm8 zwoKZfVpDU3#yBb%I(?M?RXCvX|FgqT%%;_h>YEC>-sstw?p~KLB7_3+>zO0W2(_z# zYCZpD@X1_Gjqhes;#j~%It3aN^@Rf(diLwIR-zck4x+WFow#4MZ91U+Vi_^E?nqz){Iec%f@EsQxoSd^UA?4aZakuEuNEHK4QjDzk?b`kETR!}e_ucfVTR!r}mRE27 z@P~!N6Uv@cjNdwO{O}iU`}Ai&{i)C0_L+ws`}YkWxG@y0Eote#$$r5Xcsw*P`q2;H zboEu2{rOM7r`HV|)-*M@Vnynb-pvrujFTtZw!HCrI8yc2ws+>voAa&je7B(d5pYvs zaMZ+R4jnjLD2!Lv)Z>>$u%YB#F;NN2YCm!86SsW)nMa<#?DF?K@!XSNyyJ`56?IHe zkJL1LpSbdh%WuBv=1+h6Q@4NhYYXQs>hJBvWRw=kP{mjppY)eTm)L;I*-VC>9X8!e zAe6>Jpv3T&QL|}$v-t`ZI_A~7Ep#QuGGP_4~cyNNsJ?%$lZ| zHm8f6$?pr_`|WRymrvYt?>GEG|5xw$3ihK1vCX|WF<4fwC8;DuwJ7lu5by^g(Lonc zlTR;$vTGDch2cONHKhhB*1KNi#Mg=?&HEI@i2y__IvfZ`GMUWZ{`$9oKXm(-@4WRR zAHVeSE9@>5tXNi|Rm{gG2tNyO2((AP0hI0A-hiOzpM9pMuRjv0q-FS~fLfo{7S}=T zWMULsAwvdah?EOvg#<_fPeDMvAX_YmVB$j|Y?xE2r1^5K+Y8_VLm(`zF%VkRYqfT+ zBJ$OH3NQxdI~}@7C_WjXa0!%H5h%MxO%z4j0V8Rl?ncrh?4Vicw%XweuI5r3p{1sV z#k>iSS{w$BZ53k`1hHe;Qa(SHE3@fQha!P-Ij&7nvxID{4J&ZC6`m*belTEKLAXkc zl}yA^$#^=Iq%xo(HB*Rc7FyJj>e4^;$^T{gSoNG)Gq1Yr5|7&}Mk;=%pFF)mvBroK z)4*MfB$LT%S%=lI zSYpmuyfMY}sDjeT71)VQ0NF7V6>(`*4|5UXEpb9`?26G8B4yogLZkH%U#X|3hfxBN zh?CKZ?`AYAvLM~Z)JTk#id=A!+!gO%$O>G{%TCY(b`Zb=zJ%9wj1}o0DY~9Ov%zi} zfl`=7Ks?T7Ir$=_X#qXthmB2kdOB`ZUxr6?%~7d{(I=pSQ_@Scjqa^$1l1EBU(nnN zoJ2-7Bw!h@uCAIlckY}yv(~I$zHq^ugyIPCz*sETNpW+zRBvBj|4^*Ae`shpDhFWJ zf}mKfp`Cair^~Zu{rdAS+`ReX^FDC%`$wW9{r$ZVXZ0j9Ama`&D~uQ+z(gwGdLGp44@Sj8xqK4xT~R%go# z1)PM^bGoNK87(mh-qfuBq)-b^!&bNi3bV&421>Jfh{_CwPRVt#1$xToivRf2pMHD) z&;RkKKYahY-?BN&OXFk1vE(N{@#%{$y5zRoKHJgL?{WJoCc_Ie3L*lw7!}3_!;RP( zl{z+)7b0BqLW;GZ6Bwl`lxQS+&;sJoDNJ(JI8HP0wOuOLDUh9g~FUElfM zy+8Z;Ptf(d@4B;jdJ}qVBf&C{Fbn4^oVE(r;LuQaPv_5masQX^y#25L{u|`I^3p4$ zKKWb*HbMrVIJu;N-mTM`DVbE9lph)#<~18}HJ?%FGmc3r%)?7y1*ud5p4%0a$gO75 zNexw_H&f&`8_Eg!*3iH*pqZh;3ZfZ?gWVatVtg8}F)}13K;sadB2p7gn;R9XN@W3r zX^>c|kkLnRIH@TGGb4mj%HFs{0TTzc@>V{ZO&1ItYfJ0ij=5bPL|_dKGhec7)!c=P zTbr7owyL_Os-~{8su~W5Dyu@_h|8fD>tQ?cqO#BH3kE}>P?!zyBpr{J@)JEhLpdCL zt}tFGm(Rsv&~L+4p%4d?wO@jq!M&yz8h^3O$92mX(^$l*;e6{_^OcsS!MFo z+R?80F{h>b=C4)n-RrF*rn;K8Hu(qRIA{G%Ko5wCDVo|=Ll(+XkADoix~7g)Wps4- zl~-OwH3Pv)>mfnixpcYMAfxw_!TNllfFf6Gg;4U@@$qaLcMWpY*VHxQjY-NpZqkIY ztX|_Y@4e_ICSYyhAbpz*juVDo3eS}5>0x@UuV$VzHPp$R@X2O?7?0RO6$Woih#E3J zi5Z}W%`|ONOT!)QnQaw_RCBsk{->RI= zW@gQu`S4?p{p}xr{@XwQ`o%AN{*Bk)jE(A3R8*ix3K0i3=CDuP_Jyy0<}+XT(1$)+ z9jW`~UEhq3jvCF7vYS#)K)86>lJEcchu{C<_kaA0AKiJ+H+JlJr!=mmjI1J)FcXN1 zISl4n9lcx3E={6RrRA$vfA_xc{rO*iX>Mux$cI0C^ZP%T%PDZSh^MeYD~eJooHM3R zLmqv-1C3Lf5E=cz(qbuBEM?{A`_#rqv2~FwK13 z%e)HA8H^1wIQs5|uv84Q9>X#|1B{4AM~4P_&^R=ctIk-y?AQ1I`tzUu{I1>mZu-y% zjvZ-tyL}}6g>2Eh{N*YyBiDA7P1v6yfbH*^HGA60w$6`!qPGRXuqG71~XuuHQI)^c1L zP(_6|5JVP)k<`HkktRPb7r_uV1c!PC5{88r4c%YEl#zKA8Ywjqf>k|D<#szgPMZ^X=oYujt9wtJcYA3 z4v?J#jx(7+s4`qt?bC;%%PpXoB*lsMDpz`>$4=yX$cgmsR)u|VVDR9fW0jS98kz)P zVoXnl<+57LTJz~-31eDa2joY-$TXeKD7Q8;#=a=%23Tg)---lpVu|Fh9{2;AX*a35c~L~^x$Ywh zc5!tR)-x~qzpSjXwjL(r(kWtIV?uKK43EC(*HU7m-0~ib%Q|Jv3=oVGu@cFr(h0YR z9^*#S_y_2dG zOrPzX9O-G)P*P*)p;(Njj;_@x6ys2fe_W16atT#+mR)10`~i2=(!_WugvJJt57GBf z{}7_Y&6s(8H7!CR)i!p$?+INs6Tt-GCy{-~lt9a;cx#>WdNw?7c zl<Sdk>%b1h3u?Xm$3Od-FW}CkQd6e3CX<=3 ze)%gWP8_YQsw?DEH@yD?Pe1kF&wc)mk9339S5{Y9PrZf%q_c_h#t|Ts~6vjZ;H8qWAtlpSRjD#v{8PN8( zU;4;rKA+FoYHO;d&zNSnyR^b(sZ>+f(A|FG__6L(K22(gbWkem7CBrqiwkS$W;D_| zj>8|qQL=Kw6}cL?L{plZlnN<>Mrgy1>u zx%+=kojmoIKmKO<%Jtjd-b!bY>e^r^($#)kZ#+t+prFiQbNunIfAM(iFFybLV-G!X z;`j->yTax2QGqte;&6UICu5;I@`h|S<#KtPB){gNZ<1#$7v)jZ0;V{fXhlXb?1ag+ zU8oUZFVv#Jf=rK}ksC`?*o$@v=RDqgfjB!iVIvgb5>TB^xR1O7v!^0ze1B0#2Q$pcNq(3||Iy^c!vvpb` zp6Tiu0PE<>69^EYU3$UBgNKeUm_NI=whCS=+s5@OS}h}NlK_PPDwd+c0VN1`-hH>8 z!;!sHEU@L@r1i;;C^{sRH9R`~gQCGvf$8|(JqNIVx}*hiJ7N|*0`L#^AWAi(`vw|b zx!r;1$>*|T`J6FUgHXn{*?=A$k{$EEmOB&OhBlLp;mj3>n%jn14Z!J+Mn{N%rcG;| z+SJ&FK^;3Dj?`3!LU`UHnLwfB_4}%-!{JCUolfNSUWa|6OlF3=4TnO};Sp)1fg1_~ zLMb#@Gj_VA7js4vui}e%Fua{J9@jj`eM--i9AB0HML+#f?}j2G4iXoHp``^2JtBzlwc%XTX#qIlaD_3 z>dUV@{lrrT_aDR{=~on4%}ly67;b3Li1I8h?A+TbX2rctoLr?pf)y z+TmI`Crx*dCa&GEhH&Fozxc(k?*I9p{`lKWI&X4PHTZ=ue(tLGUY$y$_U_u<-gcs; zwaM-D9^AF#?9CT-w4Z3IYY6yh-a9fpNK-D49yt3)5~ z)D}#N5D5++JG}qdm!7jZ!s&Fry}fH-aHO-NyQ8Bsmmk}|e;=+7xIvuyg=_(-VdJE; zpeM7Cu{CRtXiR)+hRFDI3bqg|k?1J8!==(BHRm)!Lq(&b(P6f#3-kA}J=?Vx+j1Vj=tVlaCAy4_~nPl23i|qsz`* zx_AFRqdc^!kVvb(8i^A?klz4&h*(~|!ZxNap(!fXs2mQ`f>NQ7$>_BmMUdvXF)Lzq zm^m5ZN}^B@R#Am~Pr29U=gL$fPE*onGl_`{vG@ZkfJ>2~yWD^(MKg0;PDhI5%^~y0 z#78=zuYZCST0=~=icVL>_x|^PuD{{xbI(7gx~95uO5Kp^Z3290nk=FOj9S5rMYI^uD==FDkbzjlSo<65)o3~Yx`8ip)i zwxlxbTQGl4GLcKrzRO8-ZkJ=;%xPUcy-iaay&iW-6MZmDf-q92PyU>?B}>`Zz(DT4 z=k7^mQw15Ef=`3T=77rN)nOCN4l*=$ zAq%zPh!|L|7sF+ZVx=tKTq;s^jgU@v{5hby^7AUDRkcG6(42$jz@#uV)2>2>rDf%; z)^uL(N4%gNh%)U6%1OQWh3C}N34`*cy0Tg&W?G!hkKJN!^uRgE&V&+%PRpw);@}c< zL}#pRt0}7*85V;zXI1FQs!WA4yKb;bjVf&2r%o+ewD^7Rf8V0TOWiJKM@L6l878f} zn%(^;uDka7+du#1=bw4%obxufwzmG_NB;|bt2Uh7cH-Fd=H`%4)*Bri##m|E>klzZ z62`1~Ih|o(D!?#N8&MYE=yCg}n5PS@mmLo6-}B6iuh^U(JU)?Qv6w^iNgQMGVK@ik zK&wSO1>&JxSqw5VK0y35XG|?|nqsbT7aXtc&b zB+G{6Z9X|}x)T8?b1)dzBZsNjnX6ZyJb6?PjB2@-;bbC83zz}8ObcjtE|-}YE32ug zTd;6`O>NzC&pjWHC5d4PvC$G~7j~D=afEKbW)q)|!5=G-GzjYy){N_GiAaY!Kr>^^ zrqfjL_=D&UFCeIcbV*Vu-8N2F zu^m5#ji;}(P3ZMx6e3a?c>hiB-}ct_Y%aTc^-4WgQ7ruB_kVcq(MN`ch9}DG-94QP z7A=15<(J?(2v8{G&N}xzT>6Q&lZkke_;#?Tr?;nTXn2UYDmprvh{rH1y3n+VNqSHi zSV1U8%TNvq>%p#6l7qfLsHtgc%hajyczkeh01q^CW-HJi^!s~z2YY(^PMl~va`^bJ zy?Ylgnl~^o+}+)S81Ya(pJ)E;R&cDky2|Z#(IaW36lPp#D>Kk&&A|VUT^heEe6koL zHrn=og=6n-=|>kS3XtkpEiopOq%cH|ljAnj)(sC0?%KO&?aGxamMosu+%jj@^!amV zg#2EI%eMWUZKsYMMP*?ePA;8Hz@TI@0rKJ>Y2Sndv*Vg;Z#whLl`f}!*321G8|#1n;BU^_bk4MvnFilAKr=ElS=pi$ z@N=9oat4DjyQ+XXDr@NL(>sJJG5x=Gp6OvcR$O%IXtkb)$H|$bw!4U(#oTE2& z!Y{o;j77Xv{Qdx$ro&(jt#C>;Ch>(!)vWp(FF&xq?JJ+Z_y6RVtJiMK zk*N_2+Uz}@{l!cPL0^8wrJwlJ#|DS{U2cC#QylufEL~#&Y(NYl8KR8GM$iXL0wW|i zCx0}QTe$@o%?4`eltkMozvdUD zLom%u%fcCo02dglAkP&RCzGjZ)27u_*Bm)=jDjIwa@my^UwJJs_n&|MWopy(;o%{o zI1`8H&YCh;yL=B>|LDk2bY!@vt8?2MTe4c8M3ap}BnZ9TiDZIKydGzDI9Oj3$rrNt zBnF5!<%n{#nOJPJtK-B|PdxnO6Hg5E4~0U(g$ow#+kb4&-UH)hW8um`OLH^I5{o4+ z-h9!>NbK1074JT`q0e+<{sDiWuBMJ7NMY8rskv0FF6_VV>Wee!1i2^N0LG{c zYp@~`3h)uYMUb1$J?n<|UHRT?FI&5A&E`uly6Dmi)^1!iW6m_U&pkngU0#$o)V+8! z^P)*Zr7cq7e2#335o2u0WV*Jte(~ZJ`NCM+@srSZ{f#$%_@f_hYM%c1Lr=W1bsK6B z3RQM?c0cp@)4e@|fshBphg!>qr5u(L8(5@3DmbSz$XTYPRia@!EKo2@ZJ~{Lf%0*L z9iRWGbZ&r+;YW|xx^r_~ZWScoAB+!4rHG;@hTUM@mi zs_7adyeuBG6t;l+wClOITfqh zY#dCLvKucv>kt3>>sRl-cjw;y@4w|k+uwQ%W|*1u@nWI;!3X~|I?`V#j{WVge~-md zk;aBBs0u4hM`W@@!;FvAQa8f=LBen_PV+*!EZH#QC4m)iAov0uaup+hOgKumwRC z3prwcsNw>$d%{nKPRb8wxVDhj8afcF0hqg3usxr_Iq9Jnx7Q01* z;}+RAn_E-571^xbS;xf6&3g(Y6L=9l8J08O4=&~z3v|+{oCIvd!{~Lg{8*__7?(h0 zDkXh?7gf||QQK^YNcc8ZApGW9kH^*7+40DK|9kgWZcimf67lFSe)6LSfBhiQ_l#L{ z|MSm3*4Nk1nYZX&ZS?wlNXFyw>z)H)r@phRJOlpAHNr}UDorbTT=v^O{o(()_p3ko z-o4A_FF<}`sqA&!4QFhQiZW*^k>9%Ijgi6bD=#|ljQKN34FGYZwq?uC|Ni%>Xe@f& zb(giY*6%-XjLuz77vd+Ffwwp)x`2B^Ua7)_uuzJq_CG1zY)?0wtaa`%&1D9!dMgwBD7z{GW%!wV_aU9<4ZnA+* z;@u?PWCM1{Vcs|!M%%FyGqWwpk}PJHMlc%2%Q*A>-cwi3{-3XO)l*$vaQK|6uI>g5 z`Mj{68VS6%_Vq+MHFw@DpSRjmUGn>@W=x-6TVD$V)PmVsUx$rMXdz)V8VQG*8e%Pt z^^=;L(Cr;NcD}KG)AsGVQpt30Pw(#Cd$w=gnM!2g^ohwGb@cTdb%9rk5zkVw-p&x($yI;NQ%Lfk~?Cl*%C*=$?nM{3s-STsnx3#w< z#s~o<1VYF->Jp-HCR1J(Ab^GEq8=oc#_736&JY?(jH>0Ne)w-%CxJ8T=E_|mlzOYg zS|}rSow2->kVkplB>`iFo5D9vb=eFYm3a3cUW>Yu~u*i(mcHe{J3RrZ=ctC=NV2@6jsb1 z2-G(;gCj~S3L5&d5gwvBMW=|Gm2f1ABBTp7HZ-nz_1ROWjvwhfdg$n}gGUa&{Ni&h zO|7~K?yn|9Zf~DdUtgb1+1tSZ9$Lv|Sdi-o13t!XBZw_PoBnVlM=jVcA@>56_617Z ziF~mjdgp*9`v7df%J+i;wsq#LIc;t2aP9cui2T6dAc2JfLn)vJrE@x^t=X-L z=bn46w|6KKsm1mca%pU=7S=r)D3eO$GHHx8;VM!@{cJi>)MnC3G|3wX0aZ4W%x6;o z=?jG+C{avGAEVW+Duttdt^e3MYz|1Z4=fm>IZ-WO!;#ABs!${v2nNwF$p$Rse@UN# z)>Y%0%C$1!5)!CqkJMbdFd>P)j%7lw5k)l7%o_~o8)9Sw{>aNOuX*792Yb5v!l6JU z932|Y^!E2PH8y|d&d-1FpFaX+hKBmI5?mVBV#vfeGn-s4P0y`ulN%dbFd2=_Er`F+ zw1*ZL3)sdhip|aX+y{g;BTvXb&IMp2ssl*vkFWFwL$R7jc*f+`a4;~fqb;8sKixB! zN@asVJdK1c%a-ihclf@)JUlQE zzhw1AA;160C!g{7Ly$b1FNDL9begaNT8Tk)OGd8M-V2vXBn}@uws+6LWGd6&KYFaQ ztG8$H*sx*Ixg&Wg&fwJ(rC^G=ygZB`Ry%!UFrw84@B z14N)_Gk^Low^=o4deLdZsoyUhpMhLljdIpXiJ%WXL z{NabYPB9IYyg`SR=bZ;}_Uzgd3`S?nn@3mCXza4ft{xrJa&|OUXOhg6$eT+Q;$z93 z+jc+k)Jw;@PBQBOAg}}m$X;9D$SkhDz9t$A6CTjp(PN#v_8!@L@X)T^`!ZR*r7V}v zZri$J`;PrbkDnS##t9b)Hb9*j`;4hm;)z64Q$si$M)N^RLLr$!@l6x}S5o7S9OS&K zzoHK*su1l`U1i03{Sm>XD(2BoA>R{6jjkxx%K+TjlFX+74OS+cPjamhuHW z;ZX44zC)Wf@9FCst#51y`u)*ZO(;?`I56aFlZGg_(*nZq=vaT>@Mt_eIH-kMCP0+u zZF-1!+j}bXRvZi~5a5srUYI@9*EPhVk=E9x{{FsgTeo(eIDF*r0l!asTt-Gmw{Cee z9#5d*Qk#m3&dvk7cWfCMNxb>yx-FZx{Oy4Uayc0nAaMy<1RjQ6)X5Qu$O# z6w@C=#O1l_PDw}}g`B!0C1gZL0Mk38nB-0LN zvBSZ^h>}k9&?G=((v~r~#AT3j9g@hH#cu%h-tHDZ{E0J?z}lm zmz*_c#?)A#rmug9i0X~?>;Cn_|8nlRtDbt|(Z0T(rHdD>dt*Iz1iwxkSCq7qP-v$p zA~S!$g{K|Pa(sne#R64*%5L9gE~5RAviMln4@L;V@Wo<1hL z^hI;xS;)c=m}$Vq`*4a_V-O*=Kd4tV(u1bp6D8n;#Z)UXODPS-l}t?hO+;QDHG`9`qOps2D4wZ$asyCYl7p5!pfPvKbM^ zbswHVJ%QHV&?HvMZ^MbQ^G0m&Mp_y&_0-#Dsm7$9Nu1#W_WOT?{4O=Da5KQnG>bUue$2MfxY{7?hOP2O^q!Sd8@qBrcECj z=^Ggyfj%e%2OJdy?;jjHcA~d;a0sR`KZ3Twa2Ut{6sm+Hv8hw1wzsx<{NY^(4sYJR zyJv6&`V_|z*Qz4E)*chrZ4jT2nE~Jy^wPMh+NRp6Qz!Ryb$7J41w#P@!30Ahp+A-t zf6pWdj{K;e_^OogQMK}Aa?(t-gnCr4GEsvJZLBitim+LIaFeG(MG>-M>D9Gw?AX6| z!dHoMK-S#A(4ZR9y0rccFTpN-4xk}irKPKnk$@0DP9xL_ z*+$|~!ji>)9JR{pz%I$<=ovh9Ok!XUrc5qud^{Kk`2Bi#jJPa@VYQnHXac%Ns7uJ< z^M{592O|+?BTWc~-jE_Wvu$IBksAdIi5gUt2;Otw{^ozb_`-`d(Heb7ArNS7Z+`Wq zmw){IA28yx&p(?;B$+=)BXtix_&4w?7K?#Mq@Xw(lFxEEB3Q zzD%tpEP`KegQFFOsJ6cDjH?zMQ^_Q9&A31X6|sQ8P9sE@tCUa=vy#i{TZd+FCvtgx z5|Pk>@i0*NY+84^e1u^7ZkX;3VqrDck5G-#^I0rx0h=4t_kDvZ$?5%DbjX1Gmkmzq zRS!Vo527z2Aj_om0$Dva7tm@077?4v5dZ*#LXKEiSyk%E8K0p5IU%hmOQu%4jLQiF z3I$|GX{8&sCX-~$BpXdcSs7r-m8r3m4keQ8xG6vMpBUHvJd`i2k2v_We#*er5<_I8 zRG3JN#=A}&*|_#a96Vw}h>mT=H{;Bb$z)3Ji%O(YiA*+?&Lx@7Wipu@ey>1mJDN_X zm{vNTGTrxjaWn?U^K1lYl5MF|$JT;Z7xX zzNj9JF~{le>ppsT|KI?j$?0q+3-qRhaD}OoUyxaZ1v4Bjc1^pEpddB06s%7zXd{%a z81Q5m%Sy@!;sekt#{sK_C`i;8i#-2DH0z&MF8@{nYKgBdSR1>lj+8aVSpsc4Q=u!N zn#zsN8p34V*;%zNl>&hfb3nUUA$_y1R2L+vK;u|l!B~b<8lfIeqsG*UWYiJ9;jVO#uy2&n2tV@Quu)z<4 z2qppm)Icl0&BPn{_0#5g2|hx+K5IC^wsfTm!;STsf>{XY8=rBM!el4-ri z-sg=n5odA}3^Lc2m7&UTJcSe%a>bXQf8mEe`2M!dTc3LJ$!(jr;HIlX#IOz;5ggz} zIQyw*gOYJgErhEmSvldXh>(Y96$&RanWWDj*|}}|u-?Ro*i0a)G&ca`5HP-U4zduA z`p^QxN~F#HQh^)>5mN(dloxXOg5F1=FTPlZ`nC$4%5Q}97ITYM^+5!9CVOhTwHTnN zH+2!Q1|d5vD_dBZPR$7@!3L?srq9T~dd_Rx1DzuT6ha6rEaazis#y>X6n-ob<1z}s z3r;!(a+pFT16wX#hCAeIgdYV>uV+O+QFk>P>b+E`Q5q)a-4cp^?zBZH+tXdyTT1QX9#kT&#}z)Mv~&0SeaDmr&==6k}*`Al5$H+Vh4X@R;i&{6zRSYpqMYv?I7wK#I9%S zN?t;y!EuhPzAutV*EKYCbWBA!+;%pk%M7dh4;e#1P4SSBhC!$a$&oWykW40UO|Tgv z+QWr#s~TwlT&nQ{G`T=+!WRbW&60G(Fo%Nx&v3%Z66GAJW3e06gfo1muCO-S0uw-n zE7p^&o@-^4E03b_C@kAhU3E4~R8x(ARMurNRg7_VP$iZCkGudjJ@M*6MsO8*DM5dH z0lnsqQ^4Q|rHhreVxZydV|kbs?O{}pDpbufLsj1_uY*F&QjvCvh^L$w*yI@683Hl} zx{;^6^#XXMJzAR3_<~tI@z0zS7tvuFDx7h9jnzsZFa&y~4eYrj1_S#*=q7xN#ZV}W z269!ejM5m=Z4ECwLI(g*_5nsYl-7s*;Z2!mqtuM9w?z{vVfkV)+nlL!zkK&M{&N2V zU-;4&@A~Rjm!ET9HkT$yar?%EF+^6EbSUOpfeH}KF8?jfJU^$rF@+HT=+QHNDk z7M2wxkc{pkwqp5?F(!q!h$k{PYtGagZ@MNJ2|Fz|(2xW{MNNTf|J0{hGoQCI77A4s zO4#juPS1l#+7;1|v}~*i{uv`f5qwl%)|;+UZgf_Oi5IgP=@{}QIvAx?toCZAs%Boz zRuGs7K=`Ig3_#dYS)~=G3cbw?CB_}NX_#@sOs$f39n#~#Kp!I!P9hK#3T211aRhpi z71hO0CDAOWZ%;B)NW@2h6R2_+W&0o~=D-Yx@DQQ7DvAkk&_*Ze0Zi02GU}@tvQGfiM>YjtfTvBxU-V67}KN~2d4>l#1xh!v== zE~vbkICH|IpWcK7HL97IR28we^vO@Y%{@X2ydImY%R?E76}D?fz`_9DKt4}vqd8*MiW@5oe1lO2PW%3z4&81BzvAS?5mP!zWB@k7d zfJIEQEMSt)XAlTDqWd-zxpB}H540-)9tHybrj{1y!+hqaKm6{)4?TF>J8rt}sw=l{ z+Qfu3f;D%~!T@ENI6!3dk#yr0gp3TNP^-XTh(i(%logsg{>usR7h#u$74K}qA(KRM zUQpabqOoO;Wt6}jtQfM5rL(-^%7PwbO@ofiB2q;Ae2(!HB8H=6a77RbkllO@8BlL_ zCsd|W4|M5uNaS#Z#UbrJ$tVjN}fJ;9h>JLZl{+P5) zz}UWEVQ~gEkb*v9v}h$#$+ya+%3K1uu^!0uj#GIuDp^Y%HQiAU%n<$6ey`qbSgg>V zZnY4Z(08T?*#Gh~ma8OIS<%oWxt&sv9s+0=qydiBriKu#!-s5{4B!CLF=g zBt)VJ9@u z`F!05t*ji2kH+I8HMRAv?NgaPLEczRZDUibNTZ2lKu=Ejf-n!7z(2LMXQ&`IeIjK} z!?XEJVZ4C4J4*pyUmzV4NrhK|9Y!1~b`|;$&=MMP)XdLFlOs zNs8lzM0^a!B96E#XaZ7dQ#-`>io3~A!HuKAOeKi^*0Mz4f7#)Cu z-wf>lmJS&G;h#=1E3z!u1v&v*=%9%OM-u^QuzEnKY#*3OkES4K1R!uCQfNWIp4=DH z#W+f!Cys%z6!d`w{t_r)`#gTV2UY`@2%2PJ=?z;6vYAwzIMU>bjxm+;G{khpd>(5` zC`uDEl*G9N`&H1@mOd-6xpapS@#`T4y#!Vp^39|G;~Kmj74hsMZz`FU`+2qqmI`b z)@z<>v|XU4jvkN(>JpzqBrwv#QZW@Di#N5j&0n%&%B;B;Tz2hQ%g#<^a>K(Tqobp; zu%R$V=0JL5R3sV-hmlF9I9fQ8y7ONzWB_6yMYuMu-~RM7Yk`MY4N;T)R90s7QbQS8 z+)sRTEIu~s)~}tS!E2c#y}qiN5Y5DxMyQum1|l0zmE5UIWGR+%P^LDjL?KQ|FWg06 z&KMS5HJvY?qDc(mI-wPWqLqe|IBQ6}sHj87Hm;sEutXjascUGWPJCn-33D8E&^aiL z>@umMjpjADYq>A-0=KFPUyooxhuYePnX~6LG&V0k@0?q1yS<^I0p(;a13R&+1U-df zhFM0Tl!KJo{bObg$I2|#Y>^Tj$`Bd^Kn0qv&<2+-(S!nbl{QcTP2h|=oVupy7Hz0N zZ4uRKb5PDPgP$eS5bI5q9C^xD#SZoPe-r&Fg3wiiP0*^1^+jjSWJ7!#4yIwL6qsW< ziBFAXR@ovuYJxUuV}UTGGPGuOQCLn?!5B(CPWT~S@v#wi8w7@m#pON~Jy~a9CkvuN ziIB7n($VjDQGy5sEA8XhYD1SsFh<}%t-vjvN@f{AZ&p($g?ug)i8&pML~DuL0A3wJ zI7ML;>j9@K8-eLHwg!NRN&}%FoieAfujx!MkwkOy6P{!;k;x2KPUJp&=jTw~;i1IR zWlL^*_q&G21_lTF3Pr6^NLCd&h-~HzWKjWB0yBYQlN&UobwyYp5)ySV7L9>VT(N%! zY8BQ>Ypi<9fp`StC?_u}DT=pntV;7%B2h(okuzT8FY?)C{8bL4=il?6?uDP-F2Rt(ICi%za4sG+}Fl*p#5 zD#n|do9i2!8IgcK5)ReZ*R{2^$D%QHl}kYa;IywrD7?UcW->|qQd`GV2}PyH=Lu9- zdSL`{nAkEtuGf!^mx#46sv6c91X=itUBQ?@C0XNOG?hx%)zzPS&bb#~c)_fh(`#d~ z<;&+@vij`nuf1x~!i60jZ5Nz(&YW2@0|CWqAR@V_((7v>AVH)sHksjqkmt-q#0^SD z^~>iK)nER~SM1CrK&5KvaytCK&0HQnO9-^iq6~&@&z}8-Gxr1VM~zKQ5Eo~T3Pqze zwY9bSN>4C|#4EH9MH2B5H%$g} ztt%>6|Efm8gsHR?*zrOoQU=sPps7$z_=A7f5S5ioDP`;2X#6L>vu$T6j2hU8Y9i&- zK)|QHK^C2v}Zy^GW@4sIx1C+*VfgZd-k~pc5hp_U}1A}vwI6Wz+jKi8A67lp1K~h`(=8P z4Qxx}y7@y8&^)P?c!vo*!BZxi-2CQ-jT^T4{hqtO`prm9ESpcBJl%ET^uVFRoed3j zt1nu;eaq$>Z+gdXe)FqiCr(VB+SE3wpE3`GG3^U8>-g^dqKz#*4TNhu6p#+5R-xfD6meoiHt$eyyg<0KT3M1_Jy?a3`o z*mfi25GhdyG^dJc7E1WibYk#JcYpN*AAIi>S6*`V*~@bIgXJQW^#q?=2dU|`a*(}0<)EIZ*lWund zJk5ltm{^7J!33F^^%9OYH#UU={#+*6P+QZ~7`^_g)tIPrRxTRo8%!q!Gj9biQ-}A2b zoU?M}?CG}Nq`(|qS9S{FRE-i*Pt}yMcEVT}6hN7^vO3m}7-1cd)Lh?v zn9vS(XJP4+noJVRKCfPjT?fnp>W(p6Qa%D7ywXL|(l`+m?qG(;$WFE$Ks}l+u^^`ztyrQZwkqd_c=dZf(z|Kwc z=Pzt(Y)CM(Dd@9(f=BnsvkE|v61|`=KsiHT1?WAM9Gy0OrWqQ{kSCi>ZP~nO+qPZd zaQKV={iXf;cg~nOr!ZbM8c$AXZI6b6vu4hE{IM4=zU1O}zU!7{=PbG5+MDkA);FtB znIO)7lzxPpurflMR{(Ixi*}SPtWf~HF=hxi?XfV9i(}$%*&SkD@eRgCCGfSQ!~kB% zrdI1|UD!dLSWSI8nW%4U$=TPuv2b8S6f6r%{Gr*c_Bm;x(>5EBC^S1;EelI@X76$Z z04mT4?8Ta5DrpWG;fk7gJds!(mKOuZ{0|wiRai~)F&wxtMx+OSFzmM%$YzppEkQat zbbBNOw=t9MgsvPar{XCQF%u)G0bixVYmbhJ;+Y|E93In9JvpVTNXYqb(V^3?MW&wah!~ zEL-gz&ty{`Uuouy8R>K`91isM4#wkp8~Wl!^PhkIwP-Zr_j)@!yWp^2w?K+5O-=E! zct_i$kd`imh}lV{x7aP@6j*Rkh>A4svP;lHs^bodZPkpVI_l?4Pr9mvV8ICbL{)W( z`G*#6ydd!G^H22jpIW|RX*3o(e&X1(&ph|qtFKOK?%2C$@9EQBj3YasZy#y1PC<7S zwW1Fl(vU(P6NjuAF;)|4YHn(u+Ms?bb5GX znBJJaXeG+$J9PNKgAe^Fok>lbHV3WP^ycO#9(!!p&K)h2T84&({h?rUTeHHQrs z_#qh%S9%j}A{J8WMKnR03o=`>yrO_Ckqf#-0|=uYtQV%ZS7 zM@%&}F(B+zOmX#Hq9Uh2VuezEZ6UPnK^omn(G5;A=opa;E-2s+X$8%mWS2jZPHF8$ zmx5ufdu!oayOq@hbETa$dT9uW49+YN3inRzJxww+IDK;D3?0C_ zs}ryhu$mV9gKqqjrPjS^_zYGJjg!ER*(Jdj6)1t|)jlsXK=-TmBi;t5$AdRWCE^;- zhiy&d3mN8uIB6rHhXEkP@Ziwr|KqdYzWb{`|Ngh{{EvT6rpFNEd@1u^pSj})-~YjD zue|=QcfWhfmhEk=Q$o6XZu1OF@>pU`LD0%#$~OpJpmmF|VzJBx*ZFTu)X21PVxUK@ z@_7ghfRdRr6Efo}JR(rgjGlQL&7hfd-sAzA1jA8=z|>+KAtSRrs7^J3q~|I%EDXVj zkR_O)CL9dt0R$+SwpRkmE{DP~ae=5GowA1N8QYyrC&u)47+?v6qTz51kA;Or>F6^U zj=@&qT)oXe;L2JB!V$0EebW#D^1}%Iv{AiM(TQ=~Bun;MEYs(9!n5Ws3P)oIfLxR% z!=3~&^dvohM8e97k+HFkj;Uv_Tz&lb=`EW!Fps(UmfJt``MV~yO@H{W_doIIYn*)*QstS)nzqv$?8^l&7r|g zyL`shnwYvX%`zq`P}Xx+p4ZVft^0H@_P4&SMlTZ1<=3rUgS8zT7zAz1CKSre%1`N-vU>H^Ljz+ww{O7&u3UM}JKuf#?78z44e9Z?s!EUECj`KZ z>)IL;iugc~63!?&gRJN`u1)o#gJCS{sJ@1F%El#;%WBhF7R6Om59-@3-pPntAJRY) zg~lk^QBDPw>&J*pi3qJ^`VW<53nX^TA{d)I&8-Iwf)L=bR7p!<3S>yIz)lTXa^NiQ zVv{MEJZDQ#Nm!AQ%@Pf9dzy_>U6m9RBd&^ksi)euk{}Rmg^qrKlhbkl;XX-iu0@nE zAVo1r2?y;J(`F-uei&PAi>S1*XdP97)$B?^pU;-GV8zy|JIQkZWX662^*URJU>Z9#XX2_8Tk zE>I{2E0xU+RUjNOBSi3defHk0LT}e`Xh0{j(Yha{C+o0LP%N8HVjKa60_}CRDXKk# zpcfwUqaQ^k*(^XJ{DFX8W(e__@6!)583=}uFpRRjj!O$T{!j$d2shKI1Sr9UP$Y_3 zf$s#vjKmOFbG@U-ulsMn#--di21j=j`I&cw=eq9#ka|6s?lNlKHl0nMI(>{|p2;bt zw!2j_ql4C+>5VfJ2~TTF+wo&3fBUQ7e(pa%)p_J#O-;?ie|zBPKm0-8>8_!H0rVP9 zBleXQ)sV#8iPoJM7hQoMI3WtpID5S`ij>J_qmfugd;NmxZA<3Oc8e`I3I0e~wEZiD z%Y1Y5hL>M`p}W7kf1v-3bsN^NUl&gfd#e3UJ@w*)_djy<$kB<4(z2EFTics@db+W) zjD^x95@V18lp#`Cw@L88iMP`ROD-evFjOU2u9O5o&Ilmk^y9dzGP4C7U6pcj3{f-P z&H@PZ6k<{ec{-1Ez5eQkHLtD@`T`AgH5aa0ar2GW)zpM#7Y#64BNk{&Fc<`Lyk9UJ zUa)Z9wAYKh|AU9lGb6-}&%A{qu?AN2W}f^2#eO<+AzN zv*x4QAO#-AB!`+<0%)8<5u*hb1S+XSfAt^Ah-8$|(z0f}WcYNegc9|pj*RL?B*cpX z(cOBWlsd>AM@XkyGW=#($=OxwfX)f2oWbQ(!#Nq%x+-Q)=$iF3Ddw*=5=gE&p&znE zo)fCN`oJIqDnRT84oM3LL_Mx8S0qA|QdifUw740lFccQlp;Ohx(jgmq(UBJ4)R_^D zX}EPPgQY$pp!SW)cv9;31UwabH&QsF&F9H@9Q6Zd$N{F*U}W8b)%v)CRTQtjfg6kFe))DD43fQnnJ14wjCP$;-;A=>I-|S%fD$=8h|-c05yOgc<7Kq zV3lam!T2~Hgd#45^fGMRgFWEy@g|dTtd;KMg~AltCILN4;L*EmWK4-w3Bt$#1<@#o zQ-U7^hCnDxH9F6xQ(Ec)5-yuP#b4KhKy!& z6iTQA2N?}rBz}Yw#6U<3-b+&o6G|W{*Xh1}dk+o|j^uJxxlHNQiPNV}^dV)zU=8dpZ+g{OOk#*h zp=%M#Ti@7(y}%9FH$Vyb{mDce0Kft=#-ia*ef-1Uyypvde(vKfEt8CZ;;A+U*!v$4 zdK7wSpg%s+ebGe=Kk}j5KJ>o#V$-+p+?Pu0zU$z?=!-ADT2mYCJbvoH!6QJ8N5sz3 z5!y$GipQad(=wAFh7jw`Ap9dq6~J~}YqDH+x}hYc&{bMnk%^H@TtVb%W?BtOcF-h! z+m4+Dy$Vd<;A(EHpE|YU{=YobdF(hdrzHy)G&I!YlBsYoaO~8{c(xR@U0M7i;N=gH z=?M}&kCAO}pVZRQkV>Y8MpJ#g1HC;1=~U+Uv7-kL?(OgECDbR7O(pe43#e{eA)Tyt%_Cmf;%A_;!_@aw1=|0`{ zhhP6DlhxaN5rZ?hiwyj6lsa?C#OEKE&BEIH6Mr0KDR3E8u#Ap&Rn6Sd=^m!WIN>gl zB?H%K;_7e;QC(YCXaEQvDXmM$oIVfn5BC7sAs_DAO5_V^%F&unKwH(*;)`n_JysQx z#w^#Q6W1XJ3O$<2J4vqzbkz<|5Uw&oHYp<_+?X`8Uy}I_bSJ$jvy9QyA9g)M3^DwM2 zi)KtgT>G^(7eS;Y^q?<*@ddUJ#(yIvi}Xea>tkLoKU&OX^iFO%AzsEBVmkTBLsV6UqqP`N2K?1}RkI%$N?#N_Gm>Q|dA%b#ZkhV%Wdm5{$!!+rl8C#PXE@%mvQ3#gT zu3fu--#$hmm>wIAuUorzaB#>AN$|jW5#sSnz84e4(`m#&X>CEw?$3x-p+_M%T zUGzC~)*R%wjsPnhh0qLy<(kw~f9VD1wN2{i9UR)UZBHhh22RE$S`UXJfl!Eg3Nwm@ z=^afUde8d+1)!dPdF_^Md$f#=A+D-8cCvft-h(Gj_v?$eo@!*-k7f1w=FXm#PN!#1 zn-Z{Hv;Yr&;LXVHNOID`(XQ%Heb?Q0yKCiSpmG5rl8F4HjVsoF#8K9jRGP4vKxzAq zUD>=QQ@FKsu5kF!(Xo+H;K2TNo;tPv(9vCc53Jv`WpF6&^Z4o;n`!FS@(~(!QzA5z z{f;NoM-F#x+rIn6iLU9N*HE!f{T zUVo#zuY33I9e7eEKg@;Q4=MD z%HH6rfl*@$08kAqt4;(YRgrmh=O(#WLo;yJg?f{Ru;J{d0)&rCg3t7aBK`nMwHEa> zglp)UaG5LC2mPCgF=u0SD757Q&7Lt>RnV45P3s#aGmZdH|5UXO8LwJ9J<{i2bV)WH zj|5|h#K^3<^ZR;w$BSZsurshkNu!=lI53GW7MoidY8q;X`um$(CJpot9zJ~Z@h4v_ zRqAO7RNNa01wui7zJQ+8B$`9HZDd8+K;rNrgE`3;^f0RtNDo8^B`zA$AZI{Opxe8g zQ;SnjhDjbTyQb>=>Fe zO|hpRfdYHy4`^)xn}WWeD40%!pMG?z7e`=%u*`Z!j#fEEtP{A6@(M3gwrqwPph6vf zu*cS6Ww}C;8i3JConCl|Aj$SI0cVtq?X9F|eJQ)BtKbC;T%uckPyi!EF=%oXiwuxt zzy>18XB2holDJa3qXi{KcFR-Rmrq-|OQsT;R8r*D7Q@o$=;Q4>mD zb?vopu77Rc?mZaU_Q})fr;yDyHZ>0q4aCRv#R@DS^Ws=-T{e|Db^Q3yXyUo&U+L{1 z$PpwkyxxytjOdGCr+Gxb?wFzU47UuDljwvcH{RQI^7P3gt1h?*cwT(*g$msh7QM&O*=R4rSawVs5v)m3Y{U<{_>PU|JjX3J=06v!zOM1w>XzMf);!%s@2rqR(o?< zX7}3B70|xgO0CRhGa$lM?LN{2W94^9(z$I$4qzNHg~Ci<0MpVPgJ$gISpGnWuns3g zR}jN+2YV6@*u+4j&?R{h`=GD%6w_?#0}&((w)c)c)m&dAsRF&B8 zb~HyO$&15pw9z80iFv@Og zDQ_FW#ywS)elPLA9-oC&`V^yPM8-Lh108UL05+tAs6cqxB{Ed|zbK1#PUmEdWZG2K zNGDAeWwjz2wGM-!=k#2q@y?C75g5j1mMSO>GQcA~Y{lGeO*UqUgIb!^RPqe5+V zQ5_;Idl!tjp&K1Gci|7AkYE52bAd9DTHzIf_U;Vrqp=Rln4+AO6@hT%&Gl<0Pnn)b zjdo0%v1ixzS+nP3x%+#2i_D6!gNTkEvtl;qM=!NiG@mC-^ZP@?1AX}Nqel+-0)c0q zeHJkTZ>>>-jhhzPqY#LKG)2S#RFoUoFt}np=n^^+g8-EgPu0`f*b2f}s zQ&V5x*a9#L#l3pNti(~ZF_M~Vnl`8{NYR|5(-h%o+V@r=^|e}VQ+oy^1%u&WFhnlzxcmEfLECDZ9tA{kG_$B3oWuU01XVs(g<)px0M!<>)| z7T`^=$cTPAtp{OWn z*;r0P_#;7Q{4=A2RCQT$y_XLz=tn9u$=IaI zqKXD#Wa~{;&aCcHOh&A-@I$4w8%u9F(h8#DU>W0zbM~|Qjj5ZsC zp(J1jOb0VVV}>C!XJ*lS7?DgWVS5R*XO`X>pFs(A>5#lkv%Zy`O(n*#&iy^7Ok(vM ze3mI4{35o1#d!UykGP;DEq1y8o1v4p@+LcPJ?Le^$q^q8x&#s?m|%;I5Y0I1q5>$@bDdIX zwnCrbe5)T7yJ{wD)O;&(&JoOgCR;F}nAJT^2w^tD?<5$>M*QiPjI$t6M|EuPA#7pr zY%asB0ffart=wy$U^u8J0*zr>B>)sL%%CN~183$i2v$(OYCy`$q>^Jjr%%8J3T;3Q zE4*|&TPB+vY?8uZBS6EW3BJlLxeCgNxMiXP4oBCgqS7;Lc&i~tp==ohQDCW9B|rs1 zq;zLC(gK$2K||@MPVJOJ*)^(3ZWNbku{5 zA)lyk4Y@=wme(b!F(aUfdNE)q#@rheG!g04q1h?@>@Jz8sZbp@2PO5@`W`{RAN%WH z{?yhnL)$z{dA#KA9Xl_&^pd$}%`N2eJ*Q75lUUc`v612a?$cw#gQ0K)1`+C>?mk^p z-?)9-u6uv=t7zlYifSe+p8R;FSS~RWv~E*6qeBLbE)wXd$iN^qXoZwyTgYk~rtw^q zbe-t0l+YX%BM=*?q$hXKPLht*5`plV%XOEjjB?dt(qV;mM1 ziwP^UnIt{n9f24*H_-AB!&PGl*o1u)gX~3IS$n_bX~f#jpUt?2Xkm(V>IFqltx*M$cP6Bm;{{JYE2v3iTGN#kvfArAWX;k*=>t6fICQRuQY*xoQ>9`y?#XyUJtRWClr8o(MUMp*ZU{UG73l27o{@d zmZ1}uI0yUcFMZ|9?wU(R2PZ0av}9RbQnVrqR(VZQQFlfXZeoSWE?pUS(Od+JZlORZ5`|INRw&z0 z-!!SMl$5s;?;f(O7T;euEzm5}$-HPZ)G zkSvOLj*@Ea5LJ=QETp|Ep$12KfKE=O)xruzMC)IG7|JeVJxV97ZnH}=sw{!m~??5Y;KF+eoL#Bu;THMZpfb<9j# zA)bCVj&5R5-vMCdiUAp%?x{>M1mltrfnvBZX)jR2D8b=~17m4rRh&|R%ebe?I~pe@ z?f>+D+_~nZry3fYVBFz@2WbFQ!~H{}gQNXD-HFk${_bw3yXi~@Wn|PT(`Oz%di<+* zeKoBYgjEx`5gS;TY@xJdj(AzL(y81D#E{tPA4nDTu5q6aGXahDPf54+ptA|AQUzf? zf&f``Cy;aTQ%eejm%8yK{tFA;c{grCJDP)CwOZ+m1`t;2VynHVw;I@l7hq)aEXbt? z3q17}K3N*KRR|c}bF`T0YCZ3uI>ve$Vm1^?=yjl)OKI6aZ{YUivuV5cC1jY0P@-Nk zDFCO6s{=Y&d(SMR`E8~G5wNNZ1Sw4h^w@eh8cSzVg9ANq4>g1WQVeSNv;~a;w2Odp zx2HuwDE8CjMh01iO?52*q(UITv|pcPq|hQARnphA0%17dt@dF7aVDSv{_0=W+1|!r zYuV$4;)R!76b#iQlUb-bW7fPm^A{n#Xm?*v59HFjW`M@)X>4wdMD?5nu!^K4dl#Zj zyfk&wxyL&?mgwypO(yk)Y{ys#jB&%TGGIQddu7rJ-AYVpUXVxdDuRI^ASTnPd9!B( zi1*#ITAF2+f*gv3*M6GIo|C?P)+kYUrN z%_YRu>LUn@qD}}Hv8@tmO&pwvgGpP*R7jr~8>O+6aFaz{QpUQbD?sE(3C*y)^g}T+ ziRqOaDV3s;+WLm3P$)8e=A0$VR^76Ow z_%Mje6k2FWdTT_NT!{#6;?9}V2kP5JYC=}Cys{>8KjnrZvdcK*D_RR5nQ67Oi`E4t z2$PjtiRxHoDJrGq&4*@oDKE23(;qnjQ^j%x73-?4FYCk#%u6BWNE>2JulX zEh^Y6lzd*j5rP^vy--HVq$mSh!CARPZM8M>%m@suJ_R0_s!Wv??*lLY;iUnrMNbvc zMvunI>d~>JN)h)2o^}6$J*e=%eC*Rbr;nZNIx(qjDyBOT*HxXX z$dm{F+BZ1*z3+ZER^Qsz-r@Io!(m?_;El!f=wv39@%StZG*BukOMXvvb3S8q^e;^XlE6=f#(1>a<0R#o7Buw0tsE&^l76GvMh`h<)NfikvHHQILlWoYNk&J`% z0MT$hv_YlSgT6(mN0zZ5j`?O`^?b0iKC}W7Y7*6oT1HQaLYYvSqM}PhdlHOnI93Od z8Hg(QOIi@pI=jp~4C|>@9*@3xWv_q4#8Mf{<+m4o6$)8^!@z>=WN3L=*#Y_h`~uF^T&Of!;GR)iF7p@5MaCd3`(qga+T{z=r%mr@ zpVZvc09{9Qd%SAV!ueAtw~Y>s>Gch%RP&?`OhtTjw6$##W_)CL0K$XF>dP)g3%76C z%xq@i;uYz%z7ql1iTIc_utF}JVL%^c&ty_iTk?jF(OZLc%YkYT7r?~0iK=8Wh4sMx zrc=p)*K^55tLDv_v0}xN1@q^}VzI%&fhCLPo`3Gjg=ftP_`O482_aaaPa-9A*<}mo z;a(I3$6{tX71f~m2q!CaZ89ljb*>a)b;*625y0N%Up_PzP z6h<)_`m#Hnx{Uw@td(xmLU;=CM%F_aY)drN_%O&w=hj%XI4J+5giQx*+9+Z|!zGk5 z>$-tKhF0XHB1Ut{IZA}oH@!2Z)dljd90{^kf}gI`kE%J3BJ=9NqXI{mMFk8u8H5Dg zCeF&F64j*&I9t*OSTpBcc_3_02>gE(O7KrKz3aW1e4ZEx7%0zYvUl9^she+k=g{y_ zlV1N;F*MZI)YPyC-QX~GNGG9SX$gx?sg3PuXm2S>aX$uC>46U`|thvudci9x`m782K~N6hfeaj7O0MVmh~ltVS2`&Vrlc{EzH(vf=Qe|Z}!da zxS?Zm>++RLA~m6T^JlMIxwLsweOqg5eO=>u=dKzW9_~5at?o?n)TPa%5hFUIXIU-A z738oDy4W@m`<5Rwkzg=bSKolaWdZ<{nM`KtwCPZ!si{7dO08f2=56nK_vM#e2!PkW z?fM`wOCfW|XFfe|?z~rCc>dzmS6p??)pHljh0vQeY{Et}IzzkUKvHyL6AeR|q)U!C zF0Wb~MH}UGgnPswK(264*6<%hbj=V?vr0%Qg=9#`z?thLC}8&5f?^R}4uD?DzK0qR zS`&PE9cBiKVxSntMO|@Jcp^Z`WJKZYW`gDs%I48Aw*t#RZdRy@_B1U(Xy*{>thWAhO0tWyZR1yOLpzuvM1RO^6ELh6nyclWHuizTHkW7yGnDEL) z=>`DB0biu^=&=``d#=5`$(%Cx**X0{rip_JJj2KWa^X|M~)r8<(79`aKZVX`s61wsq}#Z`>`*gxfXnM z3kyWVU1J~Efr8;87Gu;1@vye$GbAvml30d8Aw)GZR4nD;74rr1U`=>MC`ZVx0c>x8 z`03t?ZDK>Bw`?}e(8Q~7>NO`Nr<}_=chhH(3bhK?QhLVp3S6+i)LIIAH4X-86=Tgkm+=F zWM*Vom7tilus@Is1W|MHp^*QUTW&qw({uRf;iZcgx3y26Gi%njzWKF>9(bU&ZAx$N zscUbzxuKzU{cG!bx=s#_jx;nig~Q>E>)!yvOD?~J2=~DL{Rkah4fYRUe43k@u_Q91 zrm)~B_cx(0tw3541$`;VP+$k34~~aw%`KB=&YJ0|_GPoVMT_P{qW;AT=k@ds1pNL} zC;Ojz`uQqv>AZ8!L5T+kMjw6j8A#R9+O~iHvFb{1eO)af{(`x)bq7oW;&2p^Ow=tI z6;y1I2aXscdzaG;R{{2)F{yStKtd-;qaSF?RkyN5GEu>~7qhwC)}6c2QN)WWWLs-9 zzbBq}igq(*O-Dw$yHCCR%1i6kuHCkE+mWM3u@mW(b`F9z+_k>O^LcFBOX5*xU z#atj12uDJbS|_zn?%-mqrnaTE9Z!qhg7KpxLp3$ASWT>@r5Vz%e`C{%b61A^-Yr|+ zm_B{RK>tuU5}7(}3iF}9?$i5s9qjM#UVhHXJ-hdA*|;faUra*G1VK4^H6=TfLcpfSCa=}7+nkkrU)=Fd1m3G!_hohf&Ht8<;;Z><=KhCpP@ z8Wtts)+eJFYXyl$q%E!wIK*iwq?%w|^}Z6MEhiH!QkR%Jp?x@c6w9hB4533RV?1lJ6{hNejPmqy##hN-YSXAU60J?^Q6)pa z91iOk@CTFG?29kF^z;)??Af<(bS#0r$`*==RC;7|Y{SOa4jnl(d)Az@&RX>EpZW}Q z^l${*;d}m>m&4JzvC()gTRM95#Mx)BeEQiJ6UmGgPUyYblh0%>zI1h0*Kuq|YHTDK zPr!pv(BIh5yzk)dd%k|p!k0# zl|@1dV`x&{xfVH8`7^_pBLug7SIoW2;SU{Rd|(=Cj}3z0^l$sO3Iv{dYSuo3i1cgd z2`shWi*>d-Odc7*4v>REQ@506Yx3IXPMZD#Abm z@_1R8NE|~4nQU5K))2ARhwIBOfGb+UK@(kuAQ_?rs>*=7aMoN&0>CJEI2s^H?ka=o z##wdMwb$Oz(%jV4(7bEcp5vWIsQct&&z#~K zy5Rh=;r?CQcc;>ci!Ql{+4bRr2jcO>(7?dpKyOda>EoTpv`ZqH(0AkQL1e}v?8u}u zLPSX$mPpVCQuE8pg=A`L>uPH1n1oNA+`MebS&?XL%jR8ErnD!MsbifdTHBf?Po7M0 zkw_-??LRhc+T>_7a_ndq{0fBwnM`u&qWOM2lf_I*(7+MInCmhS)@8JW=ScQeq5&GA zn*337YeNgUFWdcwD=T*^)w3G9doFKGB?`tXL!rRi-hS=;dGih*I+V-iW=@~Ibn$s- zEm+zyWqN!pezLQZ@Dt1tEWH7rl+*Kqy4_POc&k07d?DoXb+orHTfY3pn{T+`#%nvK zPOj6Z`H2xGAe45)sR!N8K$?L?;XqYoIIPD6JyjJ`r*vF$@s)da9(eVYm(M%zoZ47; zQcJ^SmtQqB*njNs;p4|TmoHn6@kKuXqo~Divy#F{G782bMHx%}!=v)toQ$h%RM8|_ zSjz#aG5R1m(|rcHeSmW^so>L@Ki$RBJYDK)23>_lWBy1QkYkG>=#I+FIJB@T4G0o+ z5CEbHI_fBdmW|9an_ zW=xq1-HkNjz9R*|BO6f1!h83zJg@V{V2AX;AOObF4GwgJf}u}2aQL}asvxSLsP+Y- z4NaNs_`26N{Nx8e{q(>&YL&v*tTcSf&1?J3-~%_INMslY-65mx<;WmBom`8 z85~g@PDKG>AzK5cR)ui38dFFH3eXG-tB=9xp?mFnbzMnn&6Z&X0hMy|g?YlvP$UZJ zac>Gm3Bzm?0-ORBCK?z-?ZOG_^Ry5(lh%{9pb5M23UrOT%g7=4 zKU_DjZMBS;AgzWI6ZLiV>)+V;jj!DO#sB=T1G^8*ojZHljF$OJru^XEA1_&PZZ4le zo(cWWUwuv{-T%hxFV34auePR+u5|CwXa^j010&J7KY9y)XgxF=6;yy~h8E?Iryz5@r- z*;HF=)2j2AtXRG+%(e&UhYs&4vWBVCAEcB z0A->}WsRbYT%Fb>j0FGy{4OfAj*PaS{P;(Ey1MWC^PjhE*}7@trfpldzxn3oojdp7 zuGI<6?6EpYASgJtRUpd_se z|L~_jJ@~+%HP_ChcWmCWYtMm1BAL_IVssx2 z$Uz6NoJ2U-9bG{|90w`Ae4R*E+cvp`G2uE*z{uh$J=j7&_(M+Nolb4Ff&Q>%&dEtt zZIJ<^T*$i*&uEIE+r+kpLx+K&ULQkO7!y!pbZvOn{w;mZ0J|o-ReSyRjJWIz)h65y z1l{vA6Kk(e)cazhl*sUv^u<;{01`S3m_0>eu~ya!NFyg)JQ*6c*KLu?V@q{#|?BO>eB-@cJvS5uKkreq_$Pc{ktkuB)!S zj-Fn9`Nh8Olgn0|w{zE)x%20J;*L9~&X~D*>(T71rm>v!X zvzhFn!<~M=Z*oU_eO<%eJxABPwmuqRa@SWHI^Ucc-w6|cBeCn z)zO^hNi9<+Pk!QwrxNj8FjTu>!Tj2qV8ukyIkUljz3@@~%DjrKj&Tv;_En9abN15q zw&wcAroplJ@e?Qd2L^|RM*I5)ySlotu!H^mIh=ATg+R#CS8CFo%VioGnwy(i>gsFy z`c7|Hzou!@q*JF(9yo9~7>RbYwe|P+KXm^?-KTm3!NBp(qb;p%k!bXn_ukues+*7i zm;vJ-wm@iNtzqK3f63$)5(*k-hR_f8#Zn}a_kf{Q|7F)q}B`wgseIc(ZnF5fFmr)xU5@t z8qw$m$pkpbd=+>pwj$%ajJ}hqc)7~!%VslPZ(!@zE!(zj8yg-wb)xIZCmu`X@*|1l zMHj59i$y^S6=T4qH zcHIp({^8H}Uv|aiS6_K`>!eA9{Folem2D7~e?}^>xflZ6hvdM>?&kY?E(?;{Mz>rxMFvx*ZBiCaD(o!~3u_lr zb+zt~+0J6S3r8h=%3G{2X+38=pv_X+OF#roMc~Aahr%(yKwp^r*-XOY_Br@N+WeH$ z7lyQsL|^({M0e(V^YBNPr}C|`Nu#e)Y9Z`!!!$;Th=@9PhSV~39%93F}9-M4@Dt{sF0FTMIY z^CArCIp?2)!W=!^i4>vWpo|-CYH14vLnIh2NwaCLzq;bX|MZ^gF28)!d9^_U_oRYxCAU8#nDZeB>naiWA4X-+XiX z_U*enkDVZ1m@qs-;b1A9TC`xE`ZVDXmSz}DIFuZtU9!{4>aW~=m*S7I84wi(EI;Kr zYPCfbU40d*3Qz(!;X0=w!C3pC7lSwyY5MrCzfUBjuaQ%5_ydIv{)`Um18@xH$PuG3u@R)iT?Fb&dD z#Xef$GJ~VH_zVs7&tEVX1N_Fi*H4{1xohXvXtb_4QR+T*a>w@VUVk{7&2HVib??3d zYu2oL?wMy!pY92TBd7!zy#XVS*wEN$0a#DrXw@e^dB?1|vu?TlrkiiMdGqESvHJRJuDj-?7hdc<)g`$yCSM%t?_IEP$uIBy*$=<>z1Lq~i&1oVKv;(b5F`9V0OXBCc9|1c zV0V6i4UOd-IH4qU_$N#43@&2LsaIjUdeB|UJO&PfLnn|0;t(uqCzi*nPm>u>3wj1$ z-i7E?SjfWKQ~5IedS3@ui8Qc})WNt>f_oe%_O++H7#+KbcI2}98Vz!)l34$BmEccQB+`4mr$O*vgvBS4@8NnVT3g&n$mKC;FJ>uG)~EA+rKOq|MjjJ z>dH72^IAP1(aK7SmE)BogM-)v&a$~Qf(Jpmd%AmjdsC@2{Xp+zB88MNsUf@?9v(I& zfkK7Vm#ywO)wONQ7UHuRbLVRrqF5vkF!YbX4TOSBqYc#J$`#9}w0G=3d}7D0eVH^K z8t(#|v>5}f4~8PfE`6eA#nPpCl|#o)Z`k-|t~Ab+U_u*ttGrBQOfL{`0{aTvHVXY~ zYGRee;=H*tb>~(RF7v1v9B8{>%Q#DNc@o0#)?2uw5+rp@b(1I2OJ!74yha_8Ixr$4 zK{;(P(YnE=tvm7s&6rS=iF_fENP&Yqu3! z2=TTiT9HJ^3|_0NnxYIa&>Z4fZ@Q~jvZ=r8maA6R2DaN=GNN_@nK>mxKR7c=4H#9U zBpitmTcGI38Z{lj7GK*chh_#7TQ_Xmzk3gw+}b|*D|dZi#fqhK=FB?xoRuq9hJxPsWxJ29okDxY;)kVEC@Suiw4=)e&+XX< zcorhJYpFq%i%w^wL z^ZLl>5F^&qHNbI;mK3xiZY-{1%sModf*F(>&C_s$yAaFXe1PAZfHm(lgY$T zDw)jZ3n+49Q}g%)IxN#;;l9K`eONC{=-{*w&|aKswnn`7Xxo-Xp-31qxE{SNm*6VK zwH+6HWe%{5MjYZ?xQ{Lm4fQjF)O>JY1R8sHdD(0B?GI`EstAl}9R1dRb zko4275q-~=^P=7%l0Z(RXZif>Deak&k=t&6&%b^AqaIJiym|A!_x&HD_Jmwgi8HGl zNTS0?Jg^Mc_=9}G&D=y$FYM5Rd3t$`i3wDq>+R@#1mFq6sZBUEAyN%-2%4W`c) z*lKMdolIm>ak{6zU$5U*@P#fpVe|O?LRv#rW zU@=sB%uF$LX>C@?msU>q z_O08vDV|BdMfjacrx0f5vSg^>)H;{X5Fi{q*|l!#&f!#ILQbMW+rIcQF#skeVKRnF zfP~uPoJ#qEMdISL^j_r-fchk8P5th!<9&TSp-{NJeKHb|)&rAisH4pWIc?`e zIgznENy|?NjeI_Za8$R*BGLHRu-55ef_7OWj*@Z|Dw!AqPR2GIE0}raCyF^tJN}88 zsLf;a-))XDU9!sHMRD1zQ_Rt_>P48yIw%LiaF-IbLXhB%c^9gQ#+FQsr$I5D#72l4m5NI2Zl z+D2vgqOfzk0@^X_h5JYmb4&=SF{P#GnBIR#o{nfj=M<7e0{y|As~Q(gx)46$Yb7F` zf;a7(*K_nLp?*b)>mY{tOQlCX`?>%A!2AB03fEqH!;gOSKiWrc5g8gDjD)LvK2IQ+ z&LoH#7_uzd6PDzv5B}>#lzZ>PJGW z#Ti{g#VRVNP3>5=WD)29is+^qs^lVKu4Tz@&dd)ViQ`AQCCA(lys)4#YGYoiw zo~xNkC2?hXuvi`v5X) z>43eRQb6JKZSqA@muCVKl7_$`Ybqe6daK-J)Y39mO~N7sBqJhd87V_w8ADC*aEmya|E;5hMJm* zd@(&XR#7NMfop20R;yjG0F>T2e2()RuQn%38#p@(UxGD zF|?5Y(g=MSABm|PQ~}$cFXalke2yRj5}|hvQ%FTD$b6_+$^v0~d&lp8|GVD46My>C zFIrn$F1TRTdv3pNU|?`?C_XSa+}+bZIyCUrZ`|Ye5rSpM-A%ZPs#G%mf%kpz>T9k$ z+Ijp~*XaYtjvqeJMV$QcJO1;H^=m)=sXM;@gS&qI%OCIFy(^X0?pn#4$qMvvq~?HY z;YS`YAiKe)JY0sh#yxQs9&swOZ(9q5__*F9rO?{qL>huPmXQ9K+EWNwh!rrPcx#h% z+m@8g#*h(z(LP+>2U`2fWf7N z9x&E04p1>@SQT(YbLDQekRm$*Y+7huDxLQDno#gf-ve2x{3)zlhUN|RbU zI;KoV>j=a^lZ2UeDCMR!~%>!0K;KhD&Z6M7?EgdsGm7qZ~m72D?%4kkOK6D z2=Ick1Y2mTmQjP@hz6-9Z8sy}9@sGWp*fjyqR=I<4*rPziDb&~T1; zrEny|e@tgcFOmpS-qbXSPB5?Z)ZRX|uC9>)Eml)Md+vgHXD!YZi;1yO#`1dnu~=Qe zA3_TlAHo5HILy)GLrBpVMNWDJt?to-fy0GF27Fvz&|4~Bm3>xDM3QCXv@9GBcRLZe zIi&)!V2yN}izE7h6v>cDNHv72TLU8@N0CTf%dWYM82=Ulku554YDZXF1r5Lc^>07& z*yF$b!|yM>@}eLA?5B@D_QbU}T;I~x`sKU72AvNbJOJzBqr;=|G30wBKIXKDRGO%W zL~8++j=5x`=vAk!?Ng)Cnx@7kPNT7Kz^~DBg<>cYE#z`YI6*We=#$;A(i$J|kX%M& zRTQ6ZE@Vg{IE3Pt*FLRfw#$#DqsTqUhl$%3laLM?H#o>H5e1?2k(+6yuxnO z)<^3a8`>wg5jp+$m;U?f_k8nfU;F0Ho!c7gBiCK`wrYPQSt=bka-y$4-r7Fxnrp7c z28~ak29j75rkF1+U3k{{7hX6N&#l|I`|zp0N>54v`6!I7foT!euN%710qQJ0{z)<&Nsg4n(1RC*Az{n`; zjV%-tJnHsWc@-Y5Az~*KzybycPO+7AONYKd2>Sxx)id&gbCrwJ6AgB^O79aub?6zw zj_VmG`EN$Fbp!YHghI5YzM-j=2$#{3XbfnE7`BjyJz5UdE7Hfc^aRyRHqb{p@p<*a zLqbakf?)z3LU@x#;vpZRMTy=igCC_8gqDGo1y{7hWv9l$5WpZ0xMc!l{-e#2U^rME z@K%6-b;uj^+sAGJ8A#|53g`>)T8Pkd9ALo_NOIX+ePh$iIdj|E+ZQcedBN(dn6?iN z4B%&?k!UPdQ&(5df2=U`u!hFwkQoppnGvxP>Kj_I_n{>oin z5gPWRA8SJ`)9N#}m7_~Y7=@I;7zvnGWmU3u>&{F%3k$i16B6vXA}m2dne5XuO$ePh z;+b?aiaja0W7P%aHf0fwlrq*p;B8~#u@L@1rf0&of0W@rZ?BQZKh z^6u0fEm@T_dAWEaqN_&^Fx;t#`_>&*42@UeIn}K%+@|7X#ix=E@ z)7$qQ*gG;Bk42;PqHuLzf8V2zKZ1ZRT)J@6#*N309iv{gG%YF@}SaIT%OVlOO%q$G`mLFD+lO{ML8AbIFPoFTL;_lz{JW z4Z%M9++}xv^_!Pndg;~IUNdX@%*P*pbk3Yvuf6ihPk!*Dj*jV5r%nCYkG^~Cz>!>j z{M8qpN@P-3Uw!qT{_!6deG5}`fUP%$QjvX;>bW8#}1Oy5qAnBw9`OyXIWTER9`L- zfzM%VXbLWniy^R#DpY{4-CYD}nkfJ8#m~v`RTVW^BhAa{}y-F|>PuAAeEMK`| z+Vq*&tiImUZ5B+tL-qCg<9W#dM$Te5sr zI-Tn4IUNp1hlU0l+p?TzKBuD{5;Z znN0Sg^Uqy$*1Y-i=iv@UhKCy)Yg=2Il1ck^29&gKCiwJxM`6jLd01)?m95fF6Q{yX zi#3FmXitk8!cB}UIg+TOBv2ryD{)6hWs>Zw=u4#ut+ANRMcKA**~xs5@P-I%#nRyLR;@S1ej|)~;P!>*|}{ zbNlT}mo9$CO*gH+Wc8}^&mQRSS+;Wde|_O|S6*|~y!o^D@7oQrow;NP5@V47%MA*4 z92pwCT^)DepDR(4v{|gmHDuAz3XP>R70bN3h9;SECt#*J>Izp#0T-Od)`;>bvf~hd znXeXdo!p$YaAj-jYyc1577 zaM@*73=NNt#uJfnw6>-eBKP+9J@&}sUQgBXvzPDQx$AUy4;Tm~V-olaD{#D@sFu2Q)VENkAtpPTye>*x8AaF z$>O)&^tM?u=FFHe=a$=U&7{(gKlXUIwl)|EVc^6OXrT8O%2L1tX-b)=dQu1;Ig3My z^ThCnQ)(!37mF!DsU*~#V%qekM9b45a&GIedXkkUkS&`|(jk!{b&S=LlVUC_-NK$S zZ>=T_&tXp~k*M4I`lN0JEnfncKNungbjAf^qFCGGWkwBDL}5TkCk!EF$>(7rCDvR| zNP4wbSNnf3&9tLuhRE8dy-0MP!I4X}C9o1nF;~YkB;isy#?&R-RBrT+@{gycti^);=v?DB#o^n_C9@dokYn)^#Y%V2p$n zmPkuypS~ z7EGM#+L@~&r3{4C)0s%kfAz>8Y_@HHIBV|Q+ireGLqpxXd9!bS_q%4yntJoC*DYRp zR!wc>vdb@>zv!$hue!=t?ISRU0iwIXj+6&O%K+N2pX+YTPwy?F7$kAD1PE6-jr z)Ytpu-yT|Z&bc4?$j8&Elt4IRUIEETk5eRfM247=xH=#WQ&k5!;~G+Cp|`S*E)Mic z3(;*u4|T}t32>FTAIOwLW_2hZFL%XX3c-|eC_&fEuoTEzI?;J(+vatBy)|Mtm$`NMsG{Pdmw^*{gfi=mO><0nrPvU)`s{6)JUVb;EDggZ&ZlRJ0q85$X( zd6D4Wo_QCrvJLXZMNj3ao`F**P6qVSkcpw8kwh{{g*Yt}quE@xscuqjeG_vsgRrb- z1|9RMVtqpklUD2q7MPi2Q&Tf@;|*Ik5PqI>-m2T*`<@xoI;j8Q4}bK1x4a`33XB)w zcvT^tnK^y>r59W+7aZpEqm%LZI)MGNZ45@YlcpeLSAjjRp(cC`T%veg65!AAh3vbl=fKN8|Ak ztj*>(xBukFKP6(W!z{d0fmT z^Jr~i1tdD>NT0H>m{-{m+elkk6%0oi$95oSw-)k51caK92YmWB>#XgJ^u|>HrYkCd z5yQ*CYR_3Io7JZlOa}EJhIWRaqFO}8-}yxx1>ahQ6XOv@)C6fW3oU6k`jE_GdsJVS zq^(ft=6BuX_lH0Kxi5a^j{kh|rB}kyP;oqe;RWX}UAZ)s83h)E?cRHT{`=qjcIK?P zGiJ^fgce!rMvk@)1xAL4h6nl~sn6^2`+Q7SQ^^G3hzsgd7-hW|MjJ^GazoHV%qxJT zcvZn*2#Y}gfs|sm!a;p4u{55A>a8u4rcIrSk%0?D5=6mS=DTXA*ETW>AV(j#M)iiq zNVCftt$#A9@nC8kjLc?88Tn965Xpii14t%<0yrW+j@w!)NU; zK=*UVG(^mq6Lz;~np!4xOr92s#v-+~4Nc8Z4O%cbq#qp}V%9J`!sJ38d++W&-Cf;_ zmn@t%t$okFU8lNEo;=?5(4QZ@|GtL;fnYIT?C$P;^ly(n^7lt(%$RAW(&9%;7DQ{- zhSdWrN`R6=W3%+u2&!`Dy}^QHE=WmvYH(&wRa8>YD$;3@--wJ-aRehHsVggUK^9lE zl@sKm_3Xj{ab#q8ptt*E-oCg+b5#3<=brrIpMH1qt?zvO^_O3G{>lA^4nV%;OU{9q z>(;%|Gu$5t_)!SOT2&QLC>>A7M@GAQ`ZY{NWip9T(9i~n{-7eLe6`OTAB$^|qtXjm zxe{ddP?)IlgwytMr1{7`%ul?K0VF_Aa-p>6~EintdoqyV03 zAfN6yVE~+n8p_Us=v2DlqI*d@F*{{?i5<|&U2)M8l44FpG6uPVq2Tf3$CHWpzkc+S zGiJ`Ls`Q*V(X(y)_S@h6J_7im;h~}7k&`D+KJ)Y={r$c54RwqHNQku8-ouwkr;i-m zcjVySJ-fC(^W-BvJ*UUUMw0O{2$)T$FdfPG=;+8`JU&Kz0G%sL3%oPe* z0{r$V9W&?7ojY$~WAh}5yFMaROed4sOa_qx7!v~|>b`g9l6$17%2+QIHR7ry*26f?=p>C-1NIp~N*%^x{&GM&$8 zpMWhwTWrNybKas!ue8)QI2-;tpofsKkk?xR6tWpBnTQZo z5u}=yid@VpP;&FuO7udANf-+OnYCkO6!GT3TlX00gs9UW4APZKv{$h}3G~)ht@6gN zY64hbrE(f4r)7i);s@exg#n>Mv)~%I=;o47H{4`s>~lNt9stp3YJxe+15ymfCCx~v zfKY&yVrnS}0GQlTOW)k&50{WJi4Z4Tbxs$OOt?9pToflzj<(cfDz